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authorValentine Barshak <valentine.barshak@cogentembedded.com>2014-01-08 11:31:25 -0500
committerSimon Horman <horms+renesas@verge.net.au>2014-02-03 20:25:01 -0500
commit64b7f9aca549db8a8bbcf68c911e9bd24efe76f7 (patch)
tree23c57b28af1375011ca2914555aff4408fc2b99c /arch
parentb89dfdfad949798e1624dd2ff494bdb7ac943b04 (diff)
ARM: shmobile: r8a7790: Add SATA clocks
This adds SATA[01] clock support to R8A7790 SoC. Signed-off-by: Valentine Barshak <valentine.barshak@cogentembedded.com> [horms+renesas@verge.net.au: resolved trivial conflicts] Acked-by: Magnus Damm <damm@opensource.se> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/mach-shmobile/clock-r8a7790.c5
1 files changed, 5 insertions, 0 deletions
diff --git a/arch/arm/mach-shmobile/clock-r8a7790.c b/arch/arm/mach-shmobile/clock-r8a7790.c
index b2b232335ceb..f25b43a1fd73 100644
--- a/arch/arm/mach-shmobile/clock-r8a7790.c
+++ b/arch/arm/mach-shmobile/clock-r8a7790.c
@@ -196,6 +196,7 @@ enum {
196 MSTP1009, MSTP1008, MSTP1007, MSTP1006, MSTP1005, 196 MSTP1009, MSTP1008, MSTP1007, MSTP1006, MSTP1005,
197 MSTP931, MSTP930, MSTP929, MSTP928, 197 MSTP931, MSTP930, MSTP929, MSTP928,
198 MSTP917, 198 MSTP917,
199 MSTP815, MSTP814,
199 MSTP813, 200 MSTP813,
200 MSTP811, MSTP810, MSTP809, MSTP808, 201 MSTP811, MSTP810, MSTP809, MSTP808,
201 MSTP726, MSTP725, MSTP724, MSTP723, MSTP722, MSTP721, MSTP720, 202 MSTP726, MSTP725, MSTP724, MSTP723, MSTP722, MSTP721, MSTP720,
@@ -226,6 +227,8 @@ static struct clk mstp_clks[MSTP_NR] = {
226 [MSTP929] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR9, 29, MSTPSR9, 0), /* I2C2 */ 227 [MSTP929] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR9, 29, MSTPSR9, 0), /* I2C2 */
227 [MSTP928] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR9, 28, MSTPSR9, 0), /* I2C3 */ 228 [MSTP928] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR9, 28, MSTPSR9, 0), /* I2C3 */
228 [MSTP917] = SH_CLK_MSTP32_STS(&qspi_clk, SMSTPCR9, 17, MSTPSR9, 0), /* QSPI */ 229 [MSTP917] = SH_CLK_MSTP32_STS(&qspi_clk, SMSTPCR9, 17, MSTPSR9, 0), /* QSPI */
230 [MSTP815] = SH_CLK_MSTP32_STS(&zs_clk, SMSTPCR8, 15, MSTPSR8, 0), /* SATA0 */
231 [MSTP814] = SH_CLK_MSTP32_STS(&zs_clk, SMSTPCR8, 14, MSTPSR8, 0), /* SATA1 */
229 [MSTP813] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR8, 13, MSTPSR8, 0), /* Ether */ 232 [MSTP813] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR8, 13, MSTPSR8, 0), /* Ether */
230 [MSTP811] = SH_CLK_MSTP32_STS(&zg_clk, SMSTPCR8, 11, MSTPSR8, 0), /* VIN0 */ 233 [MSTP811] = SH_CLK_MSTP32_STS(&zg_clk, SMSTPCR8, 11, MSTPSR8, 0), /* VIN0 */
231 [MSTP810] = SH_CLK_MSTP32_STS(&zg_clk, SMSTPCR8, 10, MSTPSR8, 0), /* VIN1 */ 234 [MSTP810] = SH_CLK_MSTP32_STS(&zg_clk, SMSTPCR8, 10, MSTPSR8, 0), /* VIN1 */
@@ -340,6 +343,8 @@ static struct clk_lookup lookups[] = {
340 CLKDEV_DEV_ID("sh_cmt.0", &mstp_clks[MSTP124]), 343 CLKDEV_DEV_ID("sh_cmt.0", &mstp_clks[MSTP124]),
341 CLKDEV_DEV_ID("qspi.0", &mstp_clks[MSTP917]), 344 CLKDEV_DEV_ID("qspi.0", &mstp_clks[MSTP917]),
342 CLKDEV_DEV_ID("renesas_usbhs", &mstp_clks[MSTP704]), 345 CLKDEV_DEV_ID("renesas_usbhs", &mstp_clks[MSTP704]),
346 CLKDEV_DEV_ID("sata-r8a7790.0", &mstp_clks[MSTP815]),
347 CLKDEV_DEV_ID("sata-r8a7790.1", &mstp_clks[MSTP814]),
343 348
344 /* ICK */ 349 /* ICK */
345 CLKDEV_ICK_ID("usbhs", "usb_phy_rcar_gen2", &mstp_clks[MSTP704]), 350 CLKDEV_ICK_ID("usbhs", "usb_phy_rcar_gen2", &mstp_clks[MSTP704]),