Merge tag 'late-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC late changes from Kevin Hilman:
 "These are changes that arrived a little late before the merge window,
  or had dependencies on previous branches.

  Highlights:
   - ux500: misc.  cleanup, fixup I2C devices
   - exynos: DT updates for RTC; PM updates
   - at91: DT updates for NAND; new platforms added to generic defconfig
   - sunxi: DT updates: cubieboard2, pinctrl driver, gated clocks
   - highbank: LPAE fixes, select necessary ARM errata
   - omap: PM fixes and improvements; OMAP5 mailbox support
   - omap: basic support for new DRA7xx SoCs"

* tag 'late-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (60 commits)
  ARM: dts: vexpress: Add CCI node to TC2 device-tree
  ARM: EXYNOS: Skip C1 cpuidle state for exynos5440
  ARM: EXYNOS: always enable PM domains support for EXYNOS4X12
  ARM: highbank: clean-up some unused includes
  ARM: sun7i: Enable the A20 clocks in the DTSI
  ARM: sun6i: Enable clock support in the DTSI
  ARM: sun5i: dt: Use the A10s gates in the DTSI
  ARM: at91: at91_dt_defconfig: enable rm9200 support
  ARM: dts: add ADC device tree node for exynos5420/5250
  ARM: dts: Add RTC DT node to Exynos5420 SoC
  ARM: dts: Update the "status" property of RTC DT node for Exynos5250 SoC
  ARM: dts: Fix the RTC DT node name for Exynos5250
  irqchip: mmp: avoid to include irqs head file
  ARM: mmp: avoid to include head file in mach-mmp
  irqchip: mmp: support irqchip
  irqchip: move mmp irq driver
  ARM: OMAP: AM33xx: clock: Add RNG clock data
  ARM: OMAP: TI81XX: add always-on powerdomain for TI81XX
  ARM: OMAP4: clock: Lock PLLs in the right sequence
  ARM: OMAP: AM33XX: hwmod: Add hwmod data for debugSS
  ...

66 files changed, 6280 insertions, 1383 deletions

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index a00f4c1c7d71..c8a916fcd54b 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -557,6 +557,7 @@ config ARCH_MMP
         select GENERIC_CLOCKEVENTS
         select GPIO_PXA
         select IRQ_DOMAIN
+        select MULTI_IRQ_HANDLER
         select NEED_MACH_GPIO_H
         select PINCTRL
         select PLAT_PXA
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 4e02f1b6c8a2..cc0f1fb61753 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -231,6 +231,7 @@ dtb-$(CONFIG_ARCH_SUNXI) += \
         sun5i-a10s-olinuxino-micro.dtb \
         sun5i-a13-olinuxino.dtb \
         sun6i-a31-colombus.dtb \
+        sun7i-a20-cubieboard2.dtb \
         sun7i-a20-olinuxino-micro.dtb
 dtb-$(CONFIG_ARCH_TEGRA) += tegra20-harmony.dtb \
         tegra20-iris-512.dtb \
diff --git a/arch/arm/boot/dts/exynos5.dtsi b/arch/arm/boot/dts/exynos5.dtsi
index 6afa57d2fecc..074739d39e2d 100644
--- a/arch/arm/boot/dts/exynos5.dtsi
+++ b/arch/arm/boot/dts/exynos5.dtsi
@@ -95,7 +95,7 @@
                 interrupts = <0 54 0>;
         };
 
-        rtc {
+        rtc@101E0000 {
                 compatible = "samsung,s3c6410-rtc";
                 reg = <0x101E0000 0x100>;
                 interrupts = <0 43 0>, <0 44 0>;
diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts b/arch/arm/boot/dts/exynos5250-arndale.dts
index 452d0b04d273..cee55fa33731 100644
--- a/arch/arm/boot/dts/exynos5250-arndale.dts
+++ b/arch/arm/boot/dts/exynos5250-arndale.dts
@@ -538,10 +538,6 @@
                 };
         };
 
-        rtc {
-                status = "okay";
-        };
-
         usb_hub_bus {
                 compatible = "simple-bus";
                 #address-cells = <1>;
diff --git a/arch/arm/boot/dts/exynos5250-snow.dts b/arch/arm/boot/dts/exynos5250-snow.dts
index e79331dba12d..fd711e245e8d 100644
--- a/arch/arm/boot/dts/exynos5250-snow.dts
+++ b/arch/arm/boot/dts/exynos5250-snow.dts
@@ -171,10 +171,6 @@
                 };
         };
 
-        rtc {
-                status = "okay";
-        };
-
         /*
          * On Snow we've got SIP WiFi and so can keep drive strengths low to
          * reduce EMI.
diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi
index f7e2d3493f82..7d7cc777ff7b 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -180,9 +180,10 @@
                 clock-names = "mfc";
         };
 
-        rtc {
+        rtc@101E0000 {
                 clocks = <&clock 337>;
                 clock-names = "rtc";
+                status = "okay";
         };
 
         tmu@10060000 {
@@ -638,4 +639,15 @@
                 clocks = <&clock 133>, <&clock 339>;
                 clock-names = "sclk_fimd", "fimd";
         };
+
+        adc: adc@12D10000 {
+                compatible = "samsung,exynos-adc-v1";
+                reg = <0x12D10000 0x100>, <0x10040718 0x4>;
+                interrupts = <0 106 0>;
+                clocks = <&clock 303>;
+                clock-names = "adc";
+                #io-channel-cells = <1>;
+                io-channel-ranges;
+                status = "disabled";
+        };
 };
diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi
index 5353e32897a4..d537cd704e19 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -180,6 +180,12 @@
                 interrupts = <0 47 0>;
         };
 
+        rtc@101E0000 {
+                clocks = <&clock 317>;
+                clock-names = "rtc";
+                status = "okay";
+        };
+
         serial@12C00000 {
                 clocks = <&clock 257>, <&clock 128>;
                 clock-names = "uart", "clk_uart_baud0";
@@ -218,4 +224,15 @@
                 clocks = <&clock 147>, <&clock 421>;
                 clock-names = "sclk_fimd", "fimd";
         };
+
+        adc: adc@12D10000 {
+                compatible = "samsung,exynos-adc-v2";
+                reg = <0x12D10000 0x100>, <0x10040720 0x4>;
+                interrupts = <0 106 0>;
+                clocks = <&clock 270>;
+                clock-names = "adc";
+                #io-channel-cells = <1>;
+                io-channel-ranges;
+                status = "disabled";
+        };
 };
diff --git a/arch/arm/boot/dts/sama5d3.dtsi b/arch/arm/boot/dts/sama5d3.dtsi
index ff63fbbd18ab..b7f49615120d 100644
--- a/arch/arm/boot/dts/sama5d3.dtsi
+++ b/arch/arm/boot/dts/sama5d3.dtsi
@@ -1034,21 +1034,30 @@
                         compatible = "atmel,at91rm9200-nand";
                         #address-cells = <1>;
                         #size-cells = <1>;
+                        ranges;
                         reg = < 0x60000000 0x01000000   /* EBI CS3 */
                                 0xffffc070 0x00000490   /* SMC PMECC regs */
                                 0xffffc500 0x00000100   /* SMC PMECC Error Location regs */
-                                0x00100000 0x00100000   /* ROM code */
-                                0x70000000 0x10000000   /* NFC Command Registers */
-                                0xffffc000 0x00000070   /* NFC HSMC regs */
-                                0x00200000 0x00100000   /* NFC SRAM banks */
+                                0x00110000 0x00018000   /* ROM code */
                                 >;
                         interrupts = <5 IRQ_TYPE_LEVEL_HIGH 6>;
                         atmel,nand-addr-offset = <21>;
                         atmel,nand-cmd-offset = <22>;
                         pinctrl-names = "default";
                         pinctrl-0 = <&pinctrl_nand0_ale_cle>;
-                        atmel,pmecc-lookup-table-offset = <0x10000 0x18000>;
+                        atmel,pmecc-lookup-table-offset = <0x0 0x8000>;
                         status = "disabled";
+
+                        nfc@70000000 {
+                                compatible = "atmel,sama5d3-nfc";
+                                #address-cells = <1>;
+                                #size-cells = <1>;
+                                reg = <
+                                        0x70000000 0x10000000   /* NFC Command Registers */
+                                        0xffffc000 0x00000070   /* NFC HSMC regs */
+                                        0x00200000 0x00100000   /* NFC SRAM banks */
+                                        >;
+                        };
                 };
         };
 };
diff --git a/arch/arm/boot/dts/sama5d3xcm.dtsi b/arch/arm/boot/dts/sama5d3xcm.dtsi
index 1f8050813a54..31ed9e3bb649 100644
--- a/arch/arm/boot/dts/sama5d3xcm.dtsi
+++ b/arch/arm/boot/dts/sama5d3xcm.dtsi
@@ -47,8 +47,6 @@
                         atmel,has-pmecc;
                         atmel,pmecc-cap = <4>;
                         atmel,pmecc-sector-size = <512>;
-                        atmel,has-nfc;
-                        atmel,use-nfc-sram;
                         nand-on-flash-bbt;
                         status = "okay";
 
diff --git a/arch/arm/boot/dts/sun5i-a10s.dtsi b/arch/arm/boot/dts/sun5i-a10s.dtsi
index ee0ff9ba1bca..3b4a0574f068 100644
--- a/arch/arm/boot/dts/sun5i-a10s.dtsi
+++ b/arch/arm/boot/dts/sun5i-a10s.dtsi
@@ -95,20 +95,16 @@
 
                 ahb_gates: ahb_gates@01c20060 {
                         #clock-cells = <1>;
-                        compatible = "allwinner,sun4i-ahb-gates-clk";
+                        compatible = "allwinner,sun5i-a10s-ahb-gates-clk";
                         reg = <0x01c20060 0x8>;
                         clocks = <&ahb>;
-                        clock-output-names = "ahb_usb0", "ahb_ehci0",
-                                "ahb_ohci0", "ahb_ehci1", "ahb_ohci1", "ahb_ss",
-                                "ahb_dma", "ahb_bist", "ahb_mmc0", "ahb_mmc1",
-                                "ahb_mmc2", "ahb_mmc3", "ahb_ms", "ahb_nand",
-                                "ahb_sdram", "ahb_ace", "ahb_emac", "ahb_ts",
-                                "ahb_spi0", "ahb_spi1", "ahb_spi2", "ahb_spi3",
-                                "ahb_pata", "ahb_sata", "ahb_gps", "ahb_ve",
-                                "ahb_tvd", "ahb_tve0", "ahb_tve1", "ahb_lcd0",
-                                "ahb_lcd1", "ahb_csi0", "ahb_csi1", "ahb_hdmi",
-                                "ahb_de_be0", "ahb_de_be1", "ahb_de_fe0",
-                                "ahb_de_fe1", "ahb_mp", "ahb_mali400";
+                        clock-output-names = "ahb_usbotg", "ahb_ehci", "ahb_ohci",
+                                "ahb_ss", "ahb_dma", "ahb_bist", "ahb_mmc0",
+                                "ahb_mmc1", "ahb_mmc2", "ahb_nand", "ahb_sdram",
+                                "ahb_emac", "ahb_ts", "ahb_spi0", "ahb_spi1",
+                                "ahb_spi2", "ahb_gps", "ahb_stimer", "ahb_ve",
+                                "ahb_tve", "ahb_lcd", "ahb_csi", "ahb_hdmi",
+                                "ahb_de_be", "ahb_de_fe", "ahb_iep", "ahb_mali400";
                 };
 
                 apb0: apb0@01c20054 {
@@ -120,12 +116,11 @@
 
                 apb0_gates: apb0_gates@01c20068 {
                         #clock-cells = <1>;
-                        compatible = "allwinner,sun4i-apb0-gates-clk";
+                        compatible = "allwinner,sun5i-a10s-apb0-gates-clk";
                         reg = <0x01c20068 0x4>;
                         clocks = <&apb0>;
-                        clock-output-names = "apb0_codec", "apb0_spdif",
-                                "apb0_ac97", "apb0_iis", "apb0_pio", "apb0_ir0",
-                                "apb0_ir1", "apb0_keypad";
+                        clock-output-names = "apb0_codec", "apb0_iis", "apb0_pio",
+                                "apb0_ir", "apb0_keypad";
                 };
 
                 /* dummy is pll62 */
@@ -145,15 +140,12 @@
 
                 apb1_gates: apb1_gates@01c2006c {
                         #clock-cells = <1>;
-                        compatible = "allwinner,sun4i-apb1-gates-clk";
+                        compatible = "allwinner,sun5i-a10s-apb1-gates-clk";
                         reg = <0x01c2006c 0x4>;
                         clocks = <&apb1>;
                         clock-output-names = "apb1_i2c0", "apb1_i2c1",
-                                "apb1_i2c2", "apb1_can", "apb1_scr",
-                                "apb1_ps20", "apb1_ps21", "apb1_uart0",
-                                "apb1_uart1", "apb1_uart2", "apb1_uart3",
-                                "apb1_uart4", "apb1_uart5", "apb1_uart6",
-                                "apb1_uart7";
+                                "apb1_i2c2", "apb1_uart0", "apb1_uart1",
+                                "apb1_uart2", "apb1_uart3";
                 };
         };
 
diff --git a/arch/arm/boot/dts/sun6i-a31-colombus.dts b/arch/arm/boot/dts/sun6i-a31-colombus.dts
index 99c4b1847cab..e5adae30899b 100644
--- a/arch/arm/boot/dts/sun6i-a31-colombus.dts
+++ b/arch/arm/boot/dts/sun6i-a31-colombus.dts
@@ -24,6 +24,8 @@
 
         soc@01c00000 {
                 uart0: serial@01c28000 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&uart0_pins_a>;
                         status = "okay";
                 };
         };
diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi
index 4d076ec24885..f244f5f02365 100644
--- a/arch/arm/boot/dts/sun6i-a31.dtsi
+++ b/arch/arm/boot/dts/sun6i-a31.dtsi
@@ -51,13 +51,137 @@
 
         clocks {
                 #address-cells = <1>;
-                #size-cells = <0>;
+                #size-cells = <1>;
+                ranges;
 
-                osc: oscillator {
+                osc24M: osc24M {
                         #clock-cells = <0>;
                         compatible = "fixed-clock";
                         clock-frequency = <24000000>;
                 };
+
+                osc32k: osc32k {
+                        #clock-cells = <0>;
+                        compatible = "fixed-clock";
+                        clock-frequency = <32768>;
+                };
+
+                pll1: pll1@01c20000 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun6i-a31-pll1-clk";
+                        reg = <0x01c20000 0x4>;
+                        clocks = <&osc24M>;
+                };
+
+                /*
+                 * This is a dummy clock, to be used as placeholder on
+                 * other mux clocks when a specific parent clock is not
+                 * yet implemented. It should be dropped when the driver
+                 * is complete.
+                 */
+                pll6: pll6 {
+                        #clock-cells = <0>;
+                        compatible = "fixed-clock";
+                        clock-frequency = <0>;
+                };
+
+                cpu: cpu@01c20050 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-cpu-clk";
+                        reg = <0x01c20050 0x4>;
+
+                        /*
+                         * PLL1 is listed twice here.
+                         * While it looks suspicious, it's actually documented
+                         * that way both in the datasheet and in the code from
+                         * Allwinner.
+                         */
+                        clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>;
+                };
+
+                axi: axi@01c20050 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-axi-clk";
+                        reg = <0x01c20050 0x4>;
+                        clocks = <&cpu>;
+                };
+
+                ahb1_mux: ahb1_mux@01c20054 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun6i-a31-ahb1-mux-clk";
+                        reg = <0x01c20054 0x4>;
+                        clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6>;
+                };
+
+                ahb1: ahb1@01c20054 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-ahb-clk";
+                        reg = <0x01c20054 0x4>;
+                        clocks = <&ahb1_mux>;
+                };
+
+                ahb1_gates: ahb1_gates@01c20060 {
+                        #clock-cells = <1>;
+                        compatible = "allwinner,sun6i-a31-ahb1-gates-clk";
+                        reg = <0x01c20060 0x8>;
+                        clocks = <&ahb1>;
+                        clock-output-names = "ahb1_mipidsi", "ahb1_ss",
+                                        "ahb1_dma", "ahb1_mmc0", "ahb1_mmc1",
+                                        "ahb1_mmc2", "ahb1_mmc3", "ahb1_nand1",
+                                        "ahb1_nand0", "ahb1_sdram",
+                                        "ahb1_gmac", "ahb1_ts", "ahb1_hstimer",
+                                        "ahb1_spi0", "ahb1_spi1", "ahb1_spi2",
+                                        "ahb1_spi3", "ahb1_otg", "ahb1_ehci0",
+                                        "ahb1_ehci1", "ahb1_ohci0",
+                                        "ahb1_ohci1", "ahb1_ohci2", "ahb1_ve",
+                                        "ahb1_lcd0", "ahb1_lcd1", "ahb1_csi",
+                                        "ahb1_hdmi", "ahb1_de0", "ahb1_de1",
+                                        "ahb1_fe0", "ahb1_fe1", "ahb1_mp",
+                                        "ahb1_gpu", "ahb1_deu0", "ahb1_deu1",
+                                        "ahb1_drc0", "ahb1_drc1";
+                };
+
+                apb1: apb1@01c20054 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-apb0-clk";
+                        reg = <0x01c20054 0x4>;
+                        clocks = <&ahb1>;
+                };
+
+                apb1_gates: apb1_gates@01c20060 {
+                        #clock-cells = <1>;
+                        compatible = "allwinner,sun6i-a31-apb1-gates-clk";
+                        reg = <0x01c20068 0x4>;
+                        clocks = <&apb1>;
+                        clock-output-names = "apb1_codec", "apb1_digital_mic",
+                                        "apb1_pio", "apb1_daudio0",
+                                        "apb1_daudio1";
+                };
+
+                apb2_mux: apb2_mux@01c20058 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-apb1-mux-clk";
+                        reg = <0x01c20058 0x4>;
+                        clocks = <&osc32k>, <&osc24M>, <&pll6>, <&pll6>;
+                };
+
+                apb2: apb2@01c20058 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun6i-a31-apb2-div-clk";
+                        reg = <0x01c20058 0x4>;
+                        clocks = <&apb2_mux>;
+                };
+
+                apb2_gates: apb2_gates@01c2006c {
+                        #clock-cells = <1>;
+                        compatible = "allwinner,sun6i-a31-apb2-gates-clk";
+                        reg = <0x01c2006c 0x8>;
+                        clocks = <&apb2>;
+                        clock-output-names = "apb2_i2c0", "apb2_i2c1",
+                                        "apb2_i2c2", "apb2_i2c3", "apb2_uart0",
+                                        "apb2_uart1", "apb2_uart2", "apb2_uart3",
+                                        "apb2_uart4", "apb2_uart5";
+                };
         };
 
         soc@01c00000 {
@@ -66,6 +190,25 @@
                 #size-cells = <1>;
                 ranges;
 
+                pio: pinctrl@01c20800 {
+                        compatible = "allwinner,sun6i-a31-pinctrl";
+                        reg = <0x01c20800 0x400>;
+                        interrupts = <0 11 1>, <0 15 1>, <0 16 1>, <0 17 1>;
+                        clocks = <&apb1_gates 5>;
+                        gpio-controller;
+                        interrupt-controller;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        #gpio-cells = <3>;
+
+                        uart0_pins_a: uart0@0 {
+                                allwinner,pins = "PH20", "PH21";
+                                allwinner,function = "uart0";
+                                allwinner,drive = <0>;
+                                allwinner,pull = <0>;
+                        };
+                };
+
                 timer@01c20c00 {
                         compatible = "allwinner,sun4i-timer";
                         reg = <0x01c20c00 0xa0>;
@@ -74,7 +217,7 @@
                                      <0 20 1>,
                                      <0 21 1>,
                                      <0 22 1>;
-                        clocks = <&osc>;
+                        clocks = <&osc24M>;
                 };
 
                 wdt1: watchdog@01c20ca0 {
@@ -88,7 +231,7 @@
                         interrupts = <0 0 1>;
                         reg-shift = <2>;
                         reg-io-width = <4>;
-                        clocks = <&osc>;
+                        clocks = <&apb2_gates 16>;
                         status = "disabled";
                 };
 
@@ -98,7 +241,7 @@
                         interrupts = <0 1 1>;
                         reg-shift = <2>;
                         reg-io-width = <4>;
-                        clocks = <&osc>;
+                        clocks = <&apb2_gates 17>;
                         status = "disabled";
                 };
 
@@ -108,7 +251,7 @@
                         interrupts = <0 2 1>;
                         reg-shift = <2>;
                         reg-io-width = <4>;
-                        clocks = <&osc>;
+                        clocks = <&apb2_gates 18>;
                         status = "disabled";
                 };
 
@@ -118,7 +261,7 @@
                         interrupts = <0 3 1>;
                         reg-shift = <2>;
                         reg-io-width = <4>;
-                        clocks = <&osc>;
+                        clocks = <&apb2_gates 19>;
                         status = "disabled";
                 };
 
@@ -128,7 +271,7 @@
                         interrupts = <0 4 1>;
                         reg-shift = <2>;
                         reg-io-width = <4>;
-                        clocks = <&osc>;
+                        clocks = <&apb2_gates 20>;
                         status = "disabled";
                 };
 
@@ -138,7 +281,7 @@
                         interrupts = <0 5 1>;
                         reg-shift = <2>;
                         reg-io-width = <4>;
-                        clocks = <&osc>;
+                        clocks = <&apb2_gates 21>;
                         status = "disabled";
                 };
 
diff --git a/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts b/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts
new file mode 100644
index 000000000000..31b76f08b3ad
--- /dev/null
+++ b/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts
@@ -0,0 +1,53 @@
+/*
+ * Copyright 2013 Maxime Ripard
+ *
+ * Maxime Ripard <maxime.ripard@free-electrons.com>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/dts-v1/;
+/include/ "sun7i-a20.dtsi"
+
+/ {
+        model = "Cubietech Cubieboard2";
+        compatible = "cubietech,cubieboard2", "allwinner,sun7i-a20";
+
+        soc@01c00000 {
+                pinctrl@01c20800 {
+                        led_pins_cubieboard2: led_pins@0 {
+                                allwinner,pins = "PH20", "PH21";
+                                allwinner,function = "gpio_out";
+                                allwinner,drive = <0>;
+                                allwinner,pull = <0>;
+                        };
+                };
+
+                uart0: serial@01c28000 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&uart0_pins_a>;
+                        status = "okay";
+                };
+        };
+
+        leds {
+                compatible = "gpio-leds";
+                pinctrl-names = "default";
+                pinctrl-0 = <&led_pins_cubieboard2>;
+
+                blue {
+                        label = "cubieboard2:blue:usr";
+                        gpios = <&pio 7 21 0>;
+                };
+
+                green {
+                        label = "cubieboard2:green:usr";
+                        gpios = <&pio 7 20 0>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts b/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts
index d3395846491c..34a6c02a7c72 100644
--- a/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts
+++ b/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts
@@ -19,16 +19,43 @@
         compatible = "olimex,a20-olinuxino-micro", "allwinner,sun7i-a20";
 
         soc@01c00000 {
+                pinctrl@01c20800 {
+                        led_pins_olinuxino: led_pins@0 {
+                                allwinner,pins = "PH2";
+                                allwinner,function = "gpio_out";
+                                allwinner,drive = <1>;
+                                allwinner,pull = <0>;
+                        };
+                };
+
                 uart0: serial@01c28000 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&uart0_pins_a>;
                         status = "okay";
                 };
 
                 uart6: serial@01c29800 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&uart6_pins_a>;
                         status = "okay";
                 };
 
                 uart7: serial@01c29c00 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&uart7_pins_a>;
                         status = "okay";
                 };
         };
+
+        leds {
+                compatible = "gpio-leds";
+                pinctrl-names = "default";
+                pinctrl-0 = <&led_pins_olinuxino>;
+
+                green {
+                        label = "a20-olinuxino-micro:green:usr";
+                        gpios = <&pio 7 2 0>;
+                        default-state = "on";
+                };
+        };
 };
diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
index 33391517118c..999ff45cb77e 100644
--- a/arch/arm/boot/dts/sun7i-a20.dtsi
+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
@@ -44,7 +44,8 @@
 
                 osc24M: osc24M@01c20050 {
                         #clock-cells = <0>;
-                        compatible = "fixed-clock";
+                        compatible = "allwinner,sun4i-osc-clk";
+                        reg = <0x01c20050 0x4>;
                         clock-frequency = <24000000>;
                 };
 
@@ -53,6 +54,111 @@
                         compatible = "fixed-clock";
                         clock-frequency = <32768>;
                 };
+
+                pll1: pll1@01c20000 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-pll1-clk";
+                        reg = <0x01c20000 0x4>;
+                        clocks = <&osc24M>;
+                };
+
+                /*
+                 * This is a dummy clock, to be used as placeholder on
+                 * other mux clocks when a specific parent clock is not
+                 * yet implemented. It should be dropped when the driver
+                 * is complete.
+                 */
+                pll6: pll6 {
+                        #clock-cells = <0>;
+                        compatible = "fixed-clock";
+                        clock-frequency = <0>;
+                };
+
+                cpu: cpu@01c20054 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-cpu-clk";
+                        reg = <0x01c20054 0x4>;
+                        clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll6>;
+                };
+
+                axi: axi@01c20054 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-axi-clk";
+                        reg = <0x01c20054 0x4>;
+                        clocks = <&cpu>;
+                };
+
+                ahb: ahb@01c20054 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-ahb-clk";
+                        reg = <0x01c20054 0x4>;
+                        clocks = <&axi>;
+                };
+
+                ahb_gates: ahb_gates@01c20060 {
+                        #clock-cells = <1>;
+                        compatible = "allwinner,sun7i-a20-ahb-gates-clk";
+                        reg = <0x01c20060 0x8>;
+                        clocks = <&ahb>;
+                        clock-output-names = "ahb_usb0", "ahb_ehci0",
+                                "ahb_ohci0", "ahb_ehci1", "ahb_ohci1",
+                                "ahb_ss", "ahb_dma", "ahb_bist", "ahb_mmc0",
+                                "ahb_mmc1", "ahb_mmc2", "ahb_mmc3", "ahb_ms",
+                                "ahb_nand", "ahb_sdram", "ahb_ace",
+                                "ahb_emac", "ahb_ts", "ahb_spi0", "ahb_spi1",
+                                "ahb_spi2", "ahb_spi3", "ahb_sata",
+                                "ahb_hstimer", "ahb_ve", "ahb_tvd", "ahb_tve0",
+                                "ahb_tve1", "ahb_lcd0", "ahb_lcd1", "ahb_csi0",
+                                "ahb_csi1", "ahb_hdmi1", "ahb_hdmi0",
+                                "ahb_de_be0", "ahb_de_be1", "ahb_de_fe0",
+                                "ahb_de_fe1", "ahb_gmac", "ahb_mp",
+                                "ahb_mali";
+                };
+
+                apb0: apb0@01c20054 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-apb0-clk";
+                        reg = <0x01c20054 0x4>;
+                        clocks = <&ahb>;
+                };
+
+                apb0_gates: apb0_gates@01c20068 {
+                        #clock-cells = <1>;
+                        compatible = "allwinner,sun7i-a20-apb0-gates-clk";
+                        reg = <0x01c20068 0x4>;
+                        clocks = <&apb0>;
+                        clock-output-names = "apb0_codec", "apb0_spdif",
+                                "apb0_ac97", "apb0_iis0", "apb0_iis1",
+                                "apb0_pio", "apb0_ir0", "apb0_ir1",
+                                "apb0_iis2", "apb0_keypad";
+                };
+
+                apb1_mux: apb1_mux@01c20058 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-apb1-mux-clk";
+                        reg = <0x01c20058 0x4>;
+                        clocks = <&osc24M>, <&pll6>, <&osc32k>;
+                };
+
+                apb1: apb1@01c20058 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-apb1-clk";
+                        reg = <0x01c20058 0x4>;
+                        clocks = <&apb1_mux>;
+                };
+
+                apb1_gates: apb1_gates@01c2006c {
+                        #clock-cells = <1>;
+                        compatible = "allwinner,sun7i-a20-apb1-gates-clk";
+                        reg = <0x01c2006c 0x4>;
+                        clocks = <&apb1>;
+                        clock-output-names = "apb1_i2c0", "apb1_i2c1",
+                                "apb1_i2c2", "apb1_i2c3", "apb1_can",
+                                "apb1_scr", "apb1_ps20", "apb1_ps21",
+                                "apb1_i2c4", "apb1_uart0", "apb1_uart1",
+                                "apb1_uart2", "apb1_uart3", "apb1_uart4",
+                                "apb1_uart5", "apb1_uart6", "apb1_uart7";
+                };
         };
 
         soc@01c00000 {
@@ -61,6 +167,39 @@
                 #size-cells = <1>;
                 ranges;
 
+                pio: pinctrl@01c20800 {
+                        compatible = "allwinner,sun7i-a20-pinctrl";
+                        reg = <0x01c20800 0x400>;
+                        interrupts = <0 28 1>;
+                        clocks = <&apb0_gates 5>;
+                        gpio-controller;
+                        interrupt-controller;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        #gpio-cells = <3>;
+
+                        uart0_pins_a: uart0@0 {
+                                allwinner,pins = "PB22", "PB23";
+                                allwinner,function = "uart0";
+                                allwinner,drive = <0>;
+                                allwinner,pull = <0>;
+                        };
+
+                        uart6_pins_a: uart6@0 {
+                                allwinner,pins = "PI12", "PI13";
+                                allwinner,function = "uart6";
+                                allwinner,drive = <0>;
+                                allwinner,pull = <0>;
+                        };
+
+                        uart7_pins_a: uart7@0 {
+                                allwinner,pins = "PI20", "PI21";
+                                allwinner,function = "uart7";
+                                allwinner,drive = <0>;
+                                allwinner,pull = <0>;
+                        };
+                };
+
                 timer@01c20c00 {
                         compatible = "allwinner,sun4i-timer";
                         reg = <0x01c20c00 0x90>;
@@ -84,7 +223,7 @@
                         interrupts = <0 1 1>;
                         reg-shift = <2>;
                         reg-io-width = <4>;
-                        clocks = <&osc24M>;
+                        clocks = <&apb1_gates 16>;
                         status = "disabled";
                 };
 
@@ -94,7 +233,7 @@
                         interrupts = <0 2 1>;
                         reg-shift = <2>;
                         reg-io-width = <4>;
-                        clocks = <&osc24M>;
+                        clocks = <&apb1_gates 17>;
                         status = "disabled";
                 };
 
@@ -104,7 +243,7 @@
                         interrupts = <0 3 1>;
                         reg-shift = <2>;
                         reg-io-width = <4>;
-                        clocks = <&osc24M>;
+                        clocks = <&apb1_gates 18>;
                         status = "disabled";
                 };
 
@@ -114,7 +253,7 @@
                         interrupts = <0 4 1>;
                         reg-shift = <2>;
                         reg-io-width = <4>;
-                        clocks = <&osc24M>;
+                        clocks = <&apb1_gates 19>;
                         status = "disabled";
                 };
 
@@ -124,7 +263,7 @@
                         interrupts = <0 17 1>;
                         reg-shift = <2>;
                         reg-io-width = <4>;
-                        clocks = <&osc24M>;
+                        clocks = <&apb1_gates 20>;
                         status = "disabled";
                 };
 
@@ -134,7 +273,7 @@
                         interrupts = <0 18 1>;
                         reg-shift = <2>;
                         reg-io-width = <4>;
-                        clocks = <&osc24M>;
+                        clocks = <&apb1_gates 21>;
                         status = "disabled";
                 };
 
@@ -144,7 +283,7 @@
                         interrupts = <0 19 1>;
                         reg-shift = <2>;
                         reg-io-width = <4>;
-                        clocks = <&osc24M>;
+                        clocks = <&apb1_gates 22>;
                         status = "disabled";
                 };
 
@@ -154,7 +293,7 @@
                         interrupts = <0 20 1>;
                         reg-shift = <2>;
                         reg-io-width = <4>;
-                        clocks = <&osc24M>;
+                        clocks = <&apb1_gates 23>;
                         status = "disabled";
                 };
 
diff --git a/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts b/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts
index 759b0cd20013..15f98cbcb75a 100644
--- a/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts
+++ b/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts
@@ -37,30 +37,35 @@
                         device_type = "cpu";
                         compatible = "arm,cortex-a15";
                         reg = <0>;
+                        cci-control-port = <&cci_control1>;
                 };
 
                 cpu1: cpu@1 {
                         device_type = "cpu";
                         compatible = "arm,cortex-a15";
                         reg = <1>;
+                        cci-control-port = <&cci_control1>;
                 };
 
                 cpu2: cpu@2 {
                         device_type = "cpu";
                         compatible = "arm,cortex-a7";
                         reg = <0x100>;
+                        cci-control-port = <&cci_control2>;
                 };
 
                 cpu3: cpu@3 {
                         device_type = "cpu";
                         compatible = "arm,cortex-a7";
                         reg = <0x101>;
+                        cci-control-port = <&cci_control2>;
                 };
 
                 cpu4: cpu@4 {
                         device_type = "cpu";
                         compatible = "arm,cortex-a7";
                         reg = <0x102>;
+                        cci-control-port = <&cci_control2>;
                 };
         };
 
@@ -104,6 +109,26 @@
                 interrupts = <1 9 0xf04>;
         };
 
+        cci@2c090000 {
+                compatible = "arm,cci-400";
+                #address-cells = <1>;
+                #size-cells = <1>;
+                reg = <0 0x2c090000 0 0x1000>;
+                ranges = <0x0 0x0 0x2c090000 0x10000>;
+
+                cci_control1: slave-if@4000 {
+                        compatible = "arm,cci-400-ctrl-if";
+                        interface-type = "ace";
+                        reg = <0x4000 0x1000>;
+                };
+
+                cci_control2: slave-if@5000 {
+                        compatible = "arm,cci-400-ctrl-if";
+                        interface-type = "ace";
+                        reg = <0x5000 0x1000>;
+                };
+        };
+
         memory-controller@7ffd0000 {
                 compatible = "arm,pl354", "arm,primecell";
                 reg = <0 0x7ffd0000 0 0x1000>;
diff --git a/arch/arm/configs/at91_dt_defconfig b/arch/arm/configs/at91_dt_defconfig
index 75fd842d4071..690e89273230 100644
--- a/arch/arm/configs/at91_dt_defconfig
+++ b/arch/arm/configs/at91_dt_defconfig
@@ -14,11 +14,13 @@ CONFIG_MODULE_UNLOAD=y
 # CONFIG_IOSCHED_DEADLINE is not set
 # CONFIG_IOSCHED_CFQ is not set
 CONFIG_ARCH_AT91=y
+CONFIG_SOC_AT91RM9200=y
 CONFIG_SOC_AT91SAM9260=y
 CONFIG_SOC_AT91SAM9263=y
 CONFIG_SOC_AT91SAM9G45=y
 CONFIG_SOC_AT91SAM9X5=y
 CONFIG_SOC_AT91SAM9N12=y
+CONFIG_MACH_AT91RM9200_DT=y
 CONFIG_MACH_AT91SAM9_DT=y
 CONFIG_AT91_PROGRAMMABLE_CLOCKS=y
 CONFIG_AT91_TIMER_HZ=128
@@ -62,6 +64,7 @@ CONFIG_MTD=y
 CONFIG_MTD_CMDLINE_PARTS=y
 CONFIG_MTD_CHAR=y
 CONFIG_MTD_BLOCK=y
+CONFIG_MTD_DATAFLASH=y
 CONFIG_MTD_NAND=y
 CONFIG_MTD_NAND_ATMEL=y
 CONFIG_MTD_UBI=y
@@ -78,7 +81,6 @@ CONFIG_BLK_DEV_SD=y
 CONFIG_SCSI_MULTI_LUN=y
 # CONFIG_SCSI_LOWLEVEL is not set
 CONFIG_NETDEVICES=y
-CONFIG_MII=y
 CONFIG_MACB=y
 # CONFIG_NET_VENDOR_BROADCOM is not set
 # CONFIG_NET_VENDOR_FARADAY is not set
diff --git a/arch/arm/include/asm/mach/arch.h b/arch/arm/include/asm/mach/arch.h
index 69b879ac0289..402a2bc6aa68 100644
--- a/arch/arm/include/asm/mach/arch.h
+++ b/arch/arm/include/asm/mach/arch.h
@@ -35,7 +35,7 @@ struct machine_desc {
         unsigned int            nr_irqs;        /* number of IRQs */
 
 #ifdef CONFIG_ZONE_DMA
-        unsigned long           dma_zone_size;  /* size of DMA-able area */
+        phys_addr_t             dma_zone_size;  /* size of DMA-able area */
 #endif
 
         unsigned int            video_start;    /* start of video RAM   */
diff --git a/arch/arm/include/asm/outercache.h b/arch/arm/include/asm/outercache.h
index 12f71a190422..f94784f0e3a6 100644
--- a/arch/arm/include/asm/outercache.h
+++ b/arch/arm/include/asm/outercache.h
@@ -37,10 +37,10 @@ struct outer_cache_fns {
         void (*resume)(void);
 };
 
-#ifdef CONFIG_OUTER_CACHE
-
 extern struct outer_cache_fns outer_cache;
 
+#ifdef CONFIG_OUTER_CACHE
+
 static inline void outer_inv_range(phys_addr_t start, phys_addr_t end)
 {
         if (outer_cache.inv_range)
diff --git a/arch/arm/mach-at91/include/mach/hardware.h b/arch/arm/mach-at91/include/mach/hardware.h
index a832e0707611..f17aa3150019 100644
--- a/arch/arm/mach-at91/include/mach/hardware.h
+++ b/arch/arm/mach-at91/include/mach/hardware.h
@@ -33,6 +33,7 @@
 #include <mach/at91sam9g45.h>
 #include <mach/at91sam9x5.h>
 #include <mach/at91sam9n12.h>
+#include <mach/sama5d3.h>
 
 /*
  * On all at91 except rm9200 and x40 have the System Controller starts
diff --git a/arch/arm/mach-at91/include/mach/sama5d3.h b/arch/arm/mach-at91/include/mach/sama5d3.h
index 6dc81ee38048..31096a8aaf1d 100644
--- a/arch/arm/mach-at91/include/mach/sama5d3.h
+++ b/arch/arm/mach-at91/include/mach/sama5d3.h
@@ -65,6 +65,14 @@
 #define SAMA5D3_ID_IRQ0         47      /* Advanced Interrupt Controller (IRQ0) */
 
 /*
+ * User Peripheral physical base addresses.
+ */
+#define SAMA5D3_BASE_USART0     0xf001c000
+#define SAMA5D3_BASE_USART1     0xf0020000
+#define SAMA5D3_BASE_USART2     0xf8020000
+#define SAMA5D3_BASE_USART3     0xf8024000
+
+/*
  * Internal Memory
  */
 #define SAMA5D3_SRAM_BASE       0x00300000      /* Internal SRAM base address */
diff --git a/arch/arm/mach-at91/include/mach/uncompress.h b/arch/arm/mach-at91/include/mach/uncompress.h
index 5659f7c72120..4bb644f8e87c 100644
--- a/arch/arm/mach-at91/include/mach/uncompress.h
+++ b/arch/arm/mach-at91/include/mach/uncompress.h
@@ -94,6 +94,15 @@ static const u32 uarts_sam9x5[] = {
         0,
 };
 
+static const u32 uarts_sama5[] = {
+        AT91_BASE_DBGU1,
+        SAMA5D3_BASE_USART0,
+        SAMA5D3_BASE_USART1,
+        SAMA5D3_BASE_USART2,
+        SAMA5D3_BASE_USART3,
+        0,
+};
+
 static inline const u32* decomp_soc_detect(void __iomem *dbgu_base)
 {
         u32 cidr, socid;
@@ -121,8 +130,12 @@ static inline const u32* decomp_soc_detect(void __iomem *dbgu_base)
         case ARCH_ID_AT91SAM9RL64:
                 return uarts_sam9rl;
 
+        case ARCH_ID_AT91SAM9N12:
         case ARCH_ID_AT91SAM9X5:
                 return uarts_sam9x5;
+
+        case ARCH_ID_SAMA5D3:
+                return uarts_sama5;
         }
 
         /* at91sam9g10 */
diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index 5952e68c76c4..56fe819ee10b 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -36,6 +36,7 @@ config CPU_EXYNOS4210
         bool "SAMSUNG EXYNOS4210"
         default y
         depends on ARCH_EXYNOS4
+        select ARCH_HAS_BANDGAP
         select ARM_CPU_SUSPEND if PM
         select PINCTRL_EXYNOS
         select PM_GENERIC_DOMAINS if PM
@@ -49,7 +50,9 @@ config SOC_EXYNOS4212
         bool "SAMSUNG EXYNOS4212"
         default y
         depends on ARCH_EXYNOS4
+        select ARCH_HAS_BANDGAP
         select PINCTRL_EXYNOS
+        select PM_GENERIC_DOMAINS if PM
         select S5P_PM if PM
         select S5P_SLEEP if PM
         select SAMSUNG_DMADEV
@@ -60,7 +63,9 @@ config SOC_EXYNOS4412
         bool "SAMSUNG EXYNOS4412"
         default y
         depends on ARCH_EXYNOS4
+        select ARCH_HAS_BANDGAP
         select PINCTRL_EXYNOS
+        select PM_GENERIC_DOMAINS if PM
         select SAMSUNG_DMADEV
         help
           Enable EXYNOS4412 SoC support
@@ -69,6 +74,7 @@ config SOC_EXYNOS5250
         bool "SAMSUNG EXYNOS5250"
         default y
         depends on ARCH_EXYNOS5
+        select ARCH_HAS_BANDGAP
         select PINCTRL_EXYNOS
         select PM_GENERIC_DOMAINS if PM
         select S5P_PM if PM
@@ -93,6 +99,7 @@ config SOC_EXYNOS5440
         default y
         depends on ARCH_EXYNOS5
         select ARCH_DMA_ADDR_T_64BIT if ARM_LPAE
+        select ARCH_HAS_BANDGAP
         select ARCH_HAS_OPP
         select HAVE_ARM_ARCH_TIMER
         select AUTO_ZRELADDR
diff --git a/arch/arm/mach-exynos/cpuidle.c b/arch/arm/mach-exynos/cpuidle.c
index 225ee8431c72..ac139226d63c 100644
--- a/arch/arm/mach-exynos/cpuidle.c
+++ b/arch/arm/mach-exynos/cpuidle.c
@@ -200,6 +200,9 @@ static int __init exynos4_init_cpuidle(void)
         if (soc_is_exynos5250())
                 exynos5_core_down_clk();
 
+        if (soc_is_exynos5440())
+                exynos4_idle_driver.state_count = 1;
+
         ret = cpuidle_register_driver(&exynos4_idle_driver);
         if (ret) {
                 printk(KERN_ERR "CPUidle failed to register driver\n");
diff --git a/arch/arm/mach-highbank/Kconfig b/arch/arm/mach-highbank/Kconfig
index 6acbdabf6222..8e8437dea3ce 100644
--- a/arch/arm/mach-highbank/Kconfig
+++ b/arch/arm/mach-highbank/Kconfig
@@ -1,9 +1,14 @@
 config ARCH_HIGHBANK
         bool "Calxeda ECX-1000/2000 (Highbank/Midway)" if ARCH_MULTI_V7
+        select ARCH_DMA_ADDR_T_64BIT if ARM_LPAE
         select ARCH_HAS_CPUFREQ
+        select ARCH_HAS_HOLES_MEMORYMODEL
         select ARCH_HAS_OPP
         select ARCH_WANT_OPTIONAL_GPIOLIB
         select ARM_AMBA
+        select ARM_ERRATA_764369
+        select ARM_ERRATA_775420
+        select ARM_ERRATA_798181
         select ARM_GIC
         select ARM_TIMER_SP804
         select CACHE_L2X0
@@ -18,3 +23,4 @@ config ARCH_HIGHBANK
         select PL320_MBOX
         select SPARSE_IRQ
         select USE_OF
+        select ZONE_DMA if ARM_LPAE
diff --git a/arch/arm/mach-highbank/highbank.c b/arch/arm/mach-highbank/highbank.c
index 88815795fe26..8e63ccdb0de3 100644
--- a/arch/arm/mach-highbank/highbank.c
+++ b/arch/arm/mach-highbank/highbank.c
@@ -18,14 +18,11 @@
 #include <linux/clocksource.h>
 #include <linux/dma-mapping.h>
 #include <linux/io.h>
-#include <linux/irq.h>
 #include <linux/irqchip.h>
-#include <linux/irqdomain.h>
 #include <linux/of.h>
 #include <linux/of_irq.h>
 #include <linux/of_platform.h>
 #include <linux/of_address.h>
-#include <linux/smp.h>
 #include <linux/amba/bus.h>
 #include <linux/clk-provider.h>
 
@@ -35,7 +32,6 @@
 #include <asm/hardware/cache-l2x0.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
-#include <asm/mach/time.h>
 
 #include "core.h"
 #include "sysregs.h"
@@ -65,13 +61,11 @@ void highbank_set_cpu_jump(int cpu, void *jump_addr)
                           HB_JUMP_TABLE_PHYS(cpu) + 15);
 }
 
-#ifdef CONFIG_CACHE_L2X0
 static void highbank_l2x0_disable(void)
 {
         /* Disable PL310 L2 Cache controller */
         highbank_smc1(0x102, 0x0);
 }
-#endif
 
 static void __init highbank_init_irq(void)
 {
@@ -80,12 +74,13 @@ static void __init highbank_init_irq(void)
         if (of_find_compatible_node(NULL, NULL, "arm,cortex-a9"))
                 highbank_scu_map_io();
 
-#ifdef CONFIG_CACHE_L2X0
         /* Enable PL310 L2 Cache controller */
-        highbank_smc1(0x102, 0x1);
-        l2x0_of_init(0, ~0UL);
-        outer_cache.disable = highbank_l2x0_disable;
-#endif
+        if (IS_ENABLED(CONFIG_CACHE_L2X0) &&
+            of_find_compatible_node(NULL, NULL, "arm,pl310-cache")) {
+                highbank_smc1(0x102, 0x1);
+                l2x0_of_init(0, ~0UL);
+                outer_cache.disable = highbank_l2x0_disable;
+        }
 }
 
 static void __init highbank_timer_init(void)
@@ -176,6 +171,9 @@ static const char *highbank_match[] __initconst = {
 };
 
 DT_MACHINE_START(HIGHBANK, "Highbank")
+#if defined(CONFIG_ZONE_DMA) && defined(CONFIG_ARM_LPAE)
+        .dma_zone_size  = (4ULL * SZ_1G),
+#endif
         .smp            = smp_ops(highbank_smp_ops),
         .init_irq       = highbank_init_irq,
         .init_time      = highbank_timer_init,
diff --git a/arch/arm/mach-mmp/Makefile b/arch/arm/mach-mmp/Makefile
index 095c155d6fb8..9b702a1dc7b0 100644
--- a/arch/arm/mach-mmp/Makefile
+++ b/arch/arm/mach-mmp/Makefile
@@ -2,7 +2,7 @@
 # Makefile for Marvell's PXA168 processors line
 #
 
-obj-y                           += common.o devices.o time.o irq.o
+obj-y                           += common.o devices.o time.o
 
 # SoC support
 obj-$(CONFIG_CPU_PXA168)        += pxa168.o
diff --git a/arch/arm/mach-mmp/common.h b/arch/arm/mach-mmp/common.h
index 991d7e9877de..cf445bae6d77 100644
--- a/arch/arm/mach-mmp/common.h
+++ b/arch/arm/mach-mmp/common.h
@@ -3,7 +3,6 @@
 
 extern void timer_init(int irq);
 
-extern void __init icu_init_irq(void);
 extern void __init mmp_map_io(void);
 extern void mmp_restart(enum reboot_mode, const char *);
 extern void __init pxa168_clk_init(void);
diff --git a/arch/arm/mach-mmp/include/mach/entry-macro.S b/arch/arm/mach-mmp/include/mach/entry-macro.S
deleted file mode 100644
index bd152e24e6d7..000000000000
--- a/arch/arm/mach-mmp/include/mach/entry-macro.S
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * linux/arch/arm/mach-mmp/include/mach/entry-macro.S
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include <asm/irq.h>
-#include <mach/regs-icu.h>
-
-        .macro  get_irqnr_preamble, base, tmp
-        mrc     p15, 0, \tmp, c0, c0, 0         @ CPUID
-        and     \tmp, \tmp, #0xff00
-        cmp     \tmp, #0x5800
-        ldr     \base, =mmp_icu_base
-        ldr     \base, [\base, #0]
-        addne   \base, \base, #0x10c            @ PJ1 AP INT SEL register
-        addeq   \base, \base, #0x104            @ PJ4 IRQ SEL register
-        .endm
-
-        .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
-        ldr     \tmp, [\base, #0]
-        and     \irqnr, \tmp, #0x3f
-        tst     \tmp, #(1 << 6)
-        .endm
diff --git a/arch/arm/mach-mmp/include/mach/pxa168.h b/arch/arm/mach-mmp/include/mach/pxa168.h
index 459c2d03eb5c..a83ba7cb525d 100644
--- a/arch/arm/mach-mmp/include/mach/pxa168.h
+++ b/arch/arm/mach-mmp/include/mach/pxa168.h
@@ -4,6 +4,7 @@
 #include <linux/reboot.h>
 
 extern void pxa168_timer_init(void);
+extern void __init icu_init_irq(void);
 extern void __init pxa168_init_irq(void);
 extern void pxa168_restart(enum reboot_mode, const char *);
 extern void pxa168_clear_keypad_wakeup(void);
diff --git a/arch/arm/mach-mmp/include/mach/pxa910.h b/arch/arm/mach-mmp/include/mach/pxa910.h
index b914afa1fcdc..92253203f5b4 100644
--- a/arch/arm/mach-mmp/include/mach/pxa910.h
+++ b/arch/arm/mach-mmp/include/mach/pxa910.h
@@ -2,6 +2,7 @@
 #define __ASM_MACH_PXA910_H
 
 extern void pxa910_timer_init(void);
+extern void __init icu_init_irq(void);
 extern void __init pxa910_init_irq(void);
 
 #include <linux/i2c.h>
diff --git a/arch/arm/mach-mmp/irq.c b/arch/arm/mach-mmp/irq.c
deleted file mode 100644
index 3c71246cd994..000000000000
--- a/arch/arm/mach-mmp/irq.c
+++ /dev/null
@@ -1,463 +0,0 @@
-/*
- *  linux/arch/arm/mach-mmp/irq.c
- *
- *  Generic IRQ handling, GPIO IRQ demultiplexing, etc.
- *  Copyright (C) 2008 - 2012 Marvell Technology Group Ltd.
- *
- *  Author:     Bin Yang <bin.yang@marvell.com>
- *              Haojian Zhuang <haojian.zhuang@gmail.com>
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License version 2 as
- *  published by the Free Software Foundation.
- */
-
-#include <linux/module.h>
-#include <linux/init.h>
-#include <linux/irq.h>
-#include <linux/irqdomain.h>
-#include <linux/io.h>
-#include <linux/ioport.h>
-#include <linux/of_address.h>
-#include <linux/of_irq.h>
-
-#include <mach/irqs.h>
-
-#ifdef CONFIG_CPU_MMP2
-#include <mach/pm-mmp2.h>
-#endif
-#ifdef CONFIG_CPU_PXA910
-#include <mach/pm-pxa910.h>
-#endif
-
-#include "common.h"
-
-#define MAX_ICU_NR              16
-
-struct icu_chip_data {
-        int                     nr_irqs;
-        unsigned int            virq_base;
-        unsigned int            cascade_irq;
-        void __iomem            *reg_status;
-        void __iomem            *reg_mask;
-        unsigned int            conf_enable;
-        unsigned int            conf_disable;
-        unsigned int            conf_mask;
-        unsigned int            clr_mfp_irq_base;
-        unsigned int            clr_mfp_hwirq;
-        struct irq_domain       *domain;
-};
-
-struct mmp_intc_conf {
-        unsigned int    conf_enable;
-        unsigned int    conf_disable;
-        unsigned int    conf_mask;
-};
-
-void __iomem *mmp_icu_base;
-static struct icu_chip_data icu_data[MAX_ICU_NR];
-static int max_icu_nr;
-
-extern void mmp2_clear_pmic_int(void);
-
-static void icu_mask_ack_irq(struct irq_data *d)
-{
-        struct irq_domain *domain = d->domain;
-        struct icu_chip_data *data = (struct icu_chip_data *)domain->host_data;
-        int hwirq;
-        u32 r;
-
-        hwirq = d->irq - data->virq_base;
-        if (data == &icu_data[0]) {
-                r = readl_relaxed(mmp_icu_base + (hwirq << 2));
-                r &= ~data->conf_mask;
-                r |= data->conf_disable;
-                writel_relaxed(r, mmp_icu_base + (hwirq << 2));
-        } else {
-#ifdef CONFIG_CPU_MMP2
-                if ((data->virq_base == data->clr_mfp_irq_base)
-                        && (hwirq == data->clr_mfp_hwirq))
-                        mmp2_clear_pmic_int();
-#endif
-                r = readl_relaxed(data->reg_mask) | (1 << hwirq);
-                writel_relaxed(r, data->reg_mask);
-        }
-}
-
-static void icu_mask_irq(struct irq_data *d)
-{
-        struct irq_domain *domain = d->domain;
-        struct icu_chip_data *data = (struct icu_chip_data *)domain->host_data;
-        int hwirq;
-        u32 r;
-
-        hwirq = d->irq - data->virq_base;
-        if (data == &icu_data[0]) {
-                r = readl_relaxed(mmp_icu_base + (hwirq << 2));
-                r &= ~data->conf_mask;
-                r |= data->conf_disable;
-                writel_relaxed(r, mmp_icu_base + (hwirq << 2));
-        } else {
-                r = readl_relaxed(data->reg_mask) | (1 << hwirq);
-                writel_relaxed(r, data->reg_mask);
-        }
-}
-
-static void icu_unmask_irq(struct irq_data *d)
-{
-        struct irq_domain *domain = d->domain;
-        struct icu_chip_data *data = (struct icu_chip_data *)domain->host_data;
-        int hwirq;
-        u32 r;
-
-        hwirq = d->irq - data->virq_base;
-        if (data == &icu_data[0]) {
-                r = readl_relaxed(mmp_icu_base + (hwirq << 2));
-                r &= ~data->conf_mask;
-                r |= data->conf_enable;
-                writel_relaxed(r, mmp_icu_base + (hwirq << 2));
-        } else {
-                r = readl_relaxed(data->reg_mask) & ~(1 << hwirq);
-                writel_relaxed(r, data->reg_mask);
-        }
-}
-
-static struct irq_chip icu_irq_chip = {
-        .name           = "icu_irq",
-        .irq_mask       = icu_mask_irq,
-        .irq_mask_ack   = icu_mask_ack_irq,
-        .irq_unmask     = icu_unmask_irq,
-};
-
-static void icu_mux_irq_demux(unsigned int irq, struct irq_desc *desc)
-{
-        struct irq_domain *domain;
-        struct icu_chip_data *data;
-        int i;
-        unsigned long mask, status, n;
-
-        for (i = 1; i < max_icu_nr; i++) {
-                if (irq == icu_data[i].cascade_irq) {
-                        domain = icu_data[i].domain;
-                        data = (struct icu_chip_data *)domain->host_data;
-                        break;
-                }
-        }
-        if (i >= max_icu_nr) {
-                pr_err("Spurious irq %d in MMP INTC\n", irq);
-                return;
-        }
-
-        mask = readl_relaxed(data->reg_mask);
-        while (1) {
-                status = readl_relaxed(data->reg_status) & ~mask;
-                if (status == 0)
-                        break;
-                for_each_set_bit(n, &status, BITS_PER_LONG) {
-                        generic_handle_irq(icu_data[i].virq_base + n);
-                }
-        }
-}
-
-static int mmp_irq_domain_map(struct irq_domain *d, unsigned int irq,
-                              irq_hw_number_t hw)
-{
-        irq_set_chip_and_handler(irq, &icu_irq_chip, handle_level_irq);
-        set_irq_flags(irq, IRQF_VALID);
-        return 0;
-}
-
-static int mmp_irq_domain_xlate(struct irq_domain *d, struct device_node *node,
-                                const u32 *intspec, unsigned int intsize,
-                                unsigned long *out_hwirq,
-                                unsigned int *out_type)
-{
-        *out_hwirq = intspec[0];
-        return 0;
-}
-
-const struct irq_domain_ops mmp_irq_domain_ops = {
-        .map            = mmp_irq_domain_map,
-        .xlate          = mmp_irq_domain_xlate,
-};
-
-static struct mmp_intc_conf mmp_conf = {
-        .conf_enable    = 0x51,
-        .conf_disable   = 0x0,
-        .conf_mask      = 0x7f,
-};
-
-static struct mmp_intc_conf mmp2_conf = {
-        .conf_enable    = 0x20,
-        .conf_disable   = 0x0,
-        .conf_mask      = 0x7f,
-};
-
-/* MMP (ARMv5) */
-void __init icu_init_irq(void)
-{
-        int irq;
-
-        max_icu_nr = 1;
-        mmp_icu_base = ioremap(0xd4282000, 0x1000);
-        icu_data[0].conf_enable = mmp_conf.conf_enable;
-        icu_data[0].conf_disable = mmp_conf.conf_disable;
-        icu_data[0].conf_mask = mmp_conf.conf_mask;
-        icu_data[0].nr_irqs = 64;
-        icu_data[0].virq_base = 0;
-        icu_data[0].domain = irq_domain_add_legacy(NULL, 64, 0, 0,
-                                                   &irq_domain_simple_ops,
-                                                   &icu_data[0]);
-        for (irq = 0; irq < 64; irq++) {
-                icu_mask_irq(irq_get_irq_data(irq));
-                irq_set_chip_and_handler(irq, &icu_irq_chip, handle_level_irq);
-                set_irq_flags(irq, IRQF_VALID);
-        }
-        irq_set_default_host(icu_data[0].domain);
-#ifdef CONFIG_CPU_PXA910
-        icu_irq_chip.irq_set_wake = pxa910_set_wake;
-#endif
-}
-
-/* MMP2 (ARMv7) */
-void __init mmp2_init_icu(void)
-{
-        int irq;
-
-        max_icu_nr = 8;
-        mmp_icu_base = ioremap(0xd4282000, 0x1000);
-        icu_data[0].conf_enable = mmp2_conf.conf_enable;
-        icu_data[0].conf_disable = mmp2_conf.conf_disable;
-        icu_data[0].conf_mask = mmp2_conf.conf_mask;
-        icu_data[0].nr_irqs = 64;
-        icu_data[0].virq_base = 0;
-        icu_data[0].domain = irq_domain_add_legacy(NULL, 64, 0, 0,
-                                                   &irq_domain_simple_ops,
-                                                   &icu_data[0]);
-        icu_data[1].reg_status = mmp_icu_base + 0x150;
-        icu_data[1].reg_mask = mmp_icu_base + 0x168;
-        icu_data[1].clr_mfp_irq_base = IRQ_MMP2_PMIC_BASE;
-        icu_data[1].clr_mfp_hwirq = IRQ_MMP2_PMIC - IRQ_MMP2_PMIC_BASE;
-        icu_data[1].nr_irqs = 2;
-        icu_data[1].cascade_irq = 4;
-        icu_data[1].virq_base = IRQ_MMP2_PMIC_BASE;
-        icu_data[1].domain = irq_domain_add_legacy(NULL, icu_data[1].nr_irqs,
-                                                   icu_data[1].virq_base, 0,
-                                                   &irq_domain_simple_ops,
-                                                   &icu_data[1]);
-        icu_data[2].reg_status = mmp_icu_base + 0x154;
-        icu_data[2].reg_mask = mmp_icu_base + 0x16c;
-        icu_data[2].nr_irqs = 2;
-        icu_data[2].cascade_irq = 5;
-        icu_data[2].virq_base = IRQ_MMP2_RTC_BASE;
-        icu_data[2].domain = irq_domain_add_legacy(NULL, icu_data[2].nr_irqs,
-                                                   icu_data[2].virq_base, 0,
-                                                   &irq_domain_simple_ops,
-                                                   &icu_data[2]);
-        icu_data[3].reg_status = mmp_icu_base + 0x180;
-        icu_data[3].reg_mask = mmp_icu_base + 0x17c;
-        icu_data[3].nr_irqs = 3;
-        icu_data[3].cascade_irq = 9;
-        icu_data[3].virq_base = IRQ_MMP2_KEYPAD_BASE;
-        icu_data[3].domain = irq_domain_add_legacy(NULL, icu_data[3].nr_irqs,
-                                                   icu_data[3].virq_base, 0,
-                                                   &irq_domain_simple_ops,
-                                                   &icu_data[3]);
-        icu_data[4].reg_status = mmp_icu_base + 0x158;
-        icu_data[4].reg_mask = mmp_icu_base + 0x170;
-        icu_data[4].nr_irqs = 5;
-        icu_data[4].cascade_irq = 17;
-        icu_data[4].virq_base = IRQ_MMP2_TWSI_BASE;
-        icu_data[4].domain = irq_domain_add_legacy(NULL, icu_data[4].nr_irqs,
-                                                   icu_data[4].virq_base, 0,
-                                                   &irq_domain_simple_ops,
-                                                   &icu_data[4]);
-        icu_data[5].reg_status = mmp_icu_base + 0x15c;
-        icu_data[5].reg_mask = mmp_icu_base + 0x174;
-        icu_data[5].nr_irqs = 15;
-        icu_data[5].cascade_irq = 35;
-        icu_data[5].virq_base = IRQ_MMP2_MISC_BASE;
-        icu_data[5].domain = irq_domain_add_legacy(NULL, icu_data[5].nr_irqs,
-                                                   icu_data[5].virq_base, 0,
-                                                   &irq_domain_simple_ops,
-                                                   &icu_data[5]);
-        icu_data[6].reg_status = mmp_icu_base + 0x160;
-        icu_data[6].reg_mask = mmp_icu_base + 0x178;
-        icu_data[6].nr_irqs = 2;
-        icu_data[6].cascade_irq = 51;
-        icu_data[6].virq_base = IRQ_MMP2_MIPI_HSI1_BASE;
-        icu_data[6].domain = irq_domain_add_legacy(NULL, icu_data[6].nr_irqs,
-                                                   icu_data[6].virq_base, 0,
-                                                   &irq_domain_simple_ops,
-                                                   &icu_data[6]);
-        icu_data[7].reg_status = mmp_icu_base + 0x188;
-        icu_data[7].reg_mask = mmp_icu_base + 0x184;
-        icu_data[7].nr_irqs = 2;
-        icu_data[7].cascade_irq = 55;
-        icu_data[7].virq_base = IRQ_MMP2_MIPI_HSI0_BASE;
-        icu_data[7].domain = irq_domain_add_legacy(NULL, icu_data[7].nr_irqs,
-                                                   icu_data[7].virq_base, 0,
-                                                   &irq_domain_simple_ops,
-                                                   &icu_data[7]);
-        for (irq = 0; irq < IRQ_MMP2_MUX_END; irq++) {
-                icu_mask_irq(irq_get_irq_data(irq));
-                switch (irq) {
-                case IRQ_MMP2_PMIC_MUX:
-                case IRQ_MMP2_RTC_MUX:
-                case IRQ_MMP2_KEYPAD_MUX:
-                case IRQ_MMP2_TWSI_MUX:
-                case IRQ_MMP2_MISC_MUX:
-                case IRQ_MMP2_MIPI_HSI1_MUX:
-                case IRQ_MMP2_MIPI_HSI0_MUX:
-                        irq_set_chip(irq, &icu_irq_chip);
-                        irq_set_chained_handler(irq, icu_mux_irq_demux);
-                        break;
-                default:
-                        irq_set_chip_and_handler(irq, &icu_irq_chip,
-                                                 handle_level_irq);
-                        break;
-                }
-                set_irq_flags(irq, IRQF_VALID);
-        }
-        irq_set_default_host(icu_data[0].domain);
-#ifdef CONFIG_CPU_MMP2
-        icu_irq_chip.irq_set_wake = mmp2_set_wake;
-#endif
-}
-
-#ifdef CONFIG_OF
-static const struct of_device_id intc_ids[] __initconst = {
-        { .compatible = "mrvl,mmp-intc", .data = &mmp_conf },
-        { .compatible = "mrvl,mmp2-intc", .data = &mmp2_conf },
-        {}
-};
-
-static const struct of_device_id mmp_mux_irq_match[] __initconst = {
-        { .compatible = "mrvl,mmp2-mux-intc" },
-        {}
-};
-
-int __init mmp2_mux_init(struct device_node *parent)
-{
-        struct device_node *node;
-        const struct of_device_id *of_id;
-        struct resource res;
-        int i, irq_base, ret, irq;
-        u32 nr_irqs, mfp_irq;
-
-        node = parent;
-        max_icu_nr = 1;
-        for (i = 1; i < MAX_ICU_NR; i++) {
-                node = of_find_matching_node(node, mmp_mux_irq_match);
-                if (!node)
-                        break;
-                of_id = of_match_node(&mmp_mux_irq_match[0], node);
-                ret = of_property_read_u32(node, "mrvl,intc-nr-irqs",
-                                           &nr_irqs);
-                if (ret) {
-                        pr_err("Not found mrvl,intc-nr-irqs property\n");
-                        ret = -EINVAL;
-                        goto err;
-                }
-                ret = of_address_to_resource(node, 0, &res);
-                if (ret < 0) {
-                        pr_err("Not found reg property\n");
-                        ret = -EINVAL;
-                        goto err;
-                }
-                icu_data[i].reg_status = mmp_icu_base + res.start;
-                ret = of_address_to_resource(node, 1, &res);
-                if (ret < 0) {
-                        pr_err("Not found reg property\n");
-                        ret = -EINVAL;
-                        goto err;
-                }
-                icu_data[i].reg_mask = mmp_icu_base + res.start;
-                icu_data[i].cascade_irq = irq_of_parse_and_map(node, 0);
-                if (!icu_data[i].cascade_irq) {
-                        ret = -EINVAL;
-                        goto err;
-                }
-
-                irq_base = irq_alloc_descs(-1, 0, nr_irqs, 0);
-                if (irq_base < 0) {
-                        pr_err("Failed to allocate IRQ numbers for mux intc\n");
-                        ret = irq_base;
-                        goto err;
-                }
-                if (!of_property_read_u32(node, "mrvl,clr-mfp-irq",
-                                          &mfp_irq)) {
-                        icu_data[i].clr_mfp_irq_base = irq_base;
-                        icu_data[i].clr_mfp_hwirq = mfp_irq;
-                }
-                irq_set_chained_handler(icu_data[i].cascade_irq,
-                                        icu_mux_irq_demux);
-                icu_data[i].nr_irqs = nr_irqs;
-                icu_data[i].virq_base = irq_base;
-                icu_data[i].domain = irq_domain_add_legacy(node, nr_irqs,
-                                                           irq_base, 0,
-                                                           &mmp_irq_domain_ops,
-                                                           &icu_data[i]);
-                for (irq = irq_base; irq < irq_base + nr_irqs; irq++)
-                        icu_mask_irq(irq_get_irq_data(irq));
-        }
-        max_icu_nr = i;
-        return 0;
-err:
-        of_node_put(node);
-        max_icu_nr = i;
-        return ret;
-}
-
-void __init mmp_dt_irq_init(void)
-{
-        struct device_node *node;
-        const struct of_device_id *of_id;
-        struct mmp_intc_conf *conf;
-        int nr_irqs, irq_base, ret, irq;
-
-        node = of_find_matching_node(NULL, intc_ids);
-        if (!node) {
-                pr_err("Failed to find interrupt controller in arch-mmp\n");
-                return;
-        }
-        of_id = of_match_node(intc_ids, node);
-        conf = of_id->data;
-
-        ret = of_property_read_u32(node, "mrvl,intc-nr-irqs", &nr_irqs);
-        if (ret) {
-                pr_err("Not found mrvl,intc-nr-irqs property\n");
-                return;
-        }
-
-        mmp_icu_base = of_iomap(node, 0);
-        if (!mmp_icu_base) {
-                pr_err("Failed to get interrupt controller register\n");
-                return;
-        }
-
-        irq_base = irq_alloc_descs(-1, 0, nr_irqs - NR_IRQS_LEGACY, 0);
-        if (irq_base < 0) {
-                pr_err("Failed to allocate IRQ numbers\n");
-                goto err;
-        } else if (irq_base != NR_IRQS_LEGACY) {
-                pr_err("ICU's irqbase should be started from 0\n");
-                goto err;
-        }
-        icu_data[0].conf_enable = conf->conf_enable;
-        icu_data[0].conf_disable = conf->conf_disable;
-        icu_data[0].conf_mask = conf->conf_mask;
-        icu_data[0].nr_irqs = nr_irqs;
-        icu_data[0].virq_base = 0;
-        icu_data[0].domain = irq_domain_add_legacy(node, nr_irqs, 0, 0,
-                                                   &mmp_irq_domain_ops,
-                                                   &icu_data[0]);
-        irq_set_default_host(icu_data[0].domain);
-        for (irq = 0; irq < nr_irqs; irq++)
-                icu_mask_irq(irq_get_irq_data(irq));
-        mmp2_mux_init(node);
-        return;
-err:
-        iounmap(mmp_icu_base);
-}
-#endif
diff --git a/arch/arm/mach-mmp/mmp-dt.c b/arch/arm/mach-mmp/mmp-dt.c
index b37915dc4470..cca529ceecb7 100644
--- a/arch/arm/mach-mmp/mmp-dt.c
+++ b/arch/arm/mach-mmp/mmp-dt.c
@@ -9,17 +9,13 @@
  *  publishhed by the Free Software Foundation.
  */
 
-#include <linux/irq.h>
-#include <linux/irqdomain.h>
-#include <linux/of_irq.h>
+#include <linux/irqchip.h>
 #include <linux/of_platform.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
-#include <mach/irqs.h>
 
 #include "common.h"
 
-extern void __init mmp_dt_irq_init(void);
 extern void __init mmp_dt_init_timer(void);
 
 static const struct of_dev_auxdata pxa168_auxdata_lookup[] __initconst = {
@@ -64,7 +60,6 @@ static const char *mmp_dt_board_compat[] __initdata = {
 
 DT_MACHINE_START(PXA168_DT, "Marvell PXA168 (Device Tree Support)")
         .map_io         = mmp_map_io,
-        .init_irq       = mmp_dt_irq_init,
         .init_time      = mmp_dt_init_timer,
         .init_machine   = pxa168_dt_init,
         .dt_compat      = mmp_dt_board_compat,
@@ -72,7 +67,6 @@ MACHINE_END
 
 DT_MACHINE_START(PXA910_DT, "Marvell PXA910 (Device Tree Support)")
         .map_io         = mmp_map_io,
-        .init_irq       = mmp_dt_irq_init,
         .init_time      = mmp_dt_init_timer,
         .init_machine   = pxa910_dt_init,
         .dt_compat      = mmp_dt_board_compat,
diff --git a/arch/arm/mach-mmp/mmp2-dt.c b/arch/arm/mach-mmp/mmp2-dt.c
index 4ac256720f7d..023cb453f157 100644
--- a/arch/arm/mach-mmp/mmp2-dt.c
+++ b/arch/arm/mach-mmp/mmp2-dt.c
@@ -10,18 +10,13 @@
  */
 
 #include <linux/io.h>
-#include <linux/irq.h>
-#include <linux/irqdomain.h>
-#include <linux/of_irq.h>
+#include <linux/irqchip.h>
 #include <linux/of_platform.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
-#include <mach/irqs.h>
-#include <mach/regs-apbc.h>
 
 #include "common.h"
 
-extern void __init mmp_dt_irq_init(void);
 extern void __init mmp_dt_init_timer(void);
 
 static const struct of_dev_auxdata mmp2_auxdata_lookup[] __initconst = {
@@ -49,7 +44,6 @@ static const char *mmp2_dt_board_compat[] __initdata = {
 
 DT_MACHINE_START(MMP2_DT, "Marvell MMP2 (Device Tree Support)")
         .map_io         = mmp_map_io,
-        .init_irq       = mmp_dt_irq_init,
         .init_time      = mmp_dt_init_timer,
         .init_machine   = mmp2_dt_init,
         .dt_compat      = mmp2_dt_board_compat,
diff --git a/arch/arm/mach-mmp/mmp2.c b/arch/arm/mach-mmp/mmp2.c
index c7592f168bbd..a70b5530bd42 100644
--- a/arch/arm/mach-mmp/mmp2.c
+++ b/arch/arm/mach-mmp/mmp2.c
@@ -13,6 +13,8 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/io.h>
+#include <linux/irq.h>
+#include <linux/irqchip/mmp.h>
 #include <linux/platform_device.h>
 
 #include <asm/hardware/cache-tauros2.h>
@@ -26,6 +28,7 @@
 #include <mach/mfp.h>
 #include <mach/devices.h>
 #include <mach/mmp2.h>
+#include <mach/pm-mmp2.h>
 
 #include "common.h"
 
@@ -94,6 +97,9 @@ void mmp2_clear_pmic_int(void)
 void __init mmp2_init_irq(void)
 {
         mmp2_init_icu();
+#ifdef CONFIG_PM
+        icu_irq_chip.irq_set_wake = mmp2_set_wake;
+#endif
 }
 
 static int __init mmp2_init(void)
diff --git a/arch/arm/mach-mmp/pxa910.c b/arch/arm/mach-mmp/pxa910.c
index ce6393acad86..eb57ee196842 100644
--- a/arch/arm/mach-mmp/pxa910.c
+++ b/arch/arm/mach-mmp/pxa910.c
@@ -12,6 +12,8 @@
 #include <linux/init.h>
 #include <linux/list.h>
 #include <linux/io.h>
+#include <linux/irq.h>
+#include <linux/irqchip/mmp.h>
 #include <linux/platform_device.h>
 
 #include <asm/hardware/cache-tauros2.h>
@@ -23,6 +25,8 @@
 #include <mach/dma.h>
 #include <mach/mfp.h>
 #include <mach/devices.h>
+#include <mach/pm-pxa910.h>
+#include <mach/pxa910.h>
 
 #include "common.h"
 
@@ -79,6 +83,9 @@ static struct mfp_addr_map pxa910_mfp_addr_map[] __initdata =
 void __init pxa910_init_irq(void)
 {
         icu_init_irq();
+#ifdef CONFIG_PM
+        icu_irq_chip.irq_set_wake = pxa910_set_wake;
+#endif
 }
 
 static int __init pxa910_init(void)
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index cc36bfe104fe..afb457c3135b 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -63,6 +63,7 @@ obj-$(CONFIG_SOC_AM33XX)		+= am33xx-restart.o
 obj-$(CONFIG_ARCH_OMAP3)                += omap3-restart.o
 obj-$(CONFIG_ARCH_OMAP4)                += omap4-restart.o
 obj-$(CONFIG_SOC_OMAP5)                 += omap4-restart.o
+obj-$(CONFIG_SOC_DRA7XX)                += omap4-restart.o
 
 # Pin multiplexing
 obj-$(CONFIG_SOC_OMAP2420)              += mux2420.o
@@ -148,6 +149,7 @@ obj-$(CONFIG_SOC_AM43XX)		+= $(powerdomain-common)
 obj-$(CONFIG_SOC_OMAP5)                 += $(powerdomain-common)
 obj-$(CONFIG_SOC_OMAP5)                 += powerdomains54xx_data.o
 obj-$(CONFIG_SOC_DRA7XX)                += $(powerdomain-common)
+obj-$(CONFIG_SOC_DRA7XX)                += powerdomains7xx_data.o
 
 # PRCM clockdomain control
 clockdomain-common                      += clockdomain.o
@@ -166,6 +168,7 @@ obj-$(CONFIG_SOC_AM43XX)		+= $(clockdomain-common)
 obj-$(CONFIG_SOC_OMAP5)                 += $(clockdomain-common)
 obj-$(CONFIG_SOC_OMAP5)                 += clockdomains54xx_data.o
 obj-$(CONFIG_SOC_DRA7XX)                += $(clockdomain-common)
+obj-$(CONFIG_SOC_DRA7XX)                += clockdomains7xx_data.o
 
 # Clock framework
 obj-$(CONFIG_ARCH_OMAP2)                += $(clock-common) clock2xxx.o
@@ -209,6 +212,7 @@ obj-$(CONFIG_ARCH_OMAP3)		+= omap_hwmod_3xxx_data.o
 obj-$(CONFIG_SOC_AM33XX)                += omap_hwmod_33xx_data.o
 obj-$(CONFIG_ARCH_OMAP4)                += omap_hwmod_44xx_data.o
 obj-$(CONFIG_SOC_OMAP5)                 += omap_hwmod_54xx_data.o
+obj-$(CONFIG_SOC_DRA7XX)                += omap_hwmod_7xx_data.o
 
 # EMU peripherals
 obj-$(CONFIG_OMAP3_EMU)                 += emu.o
diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c
index b89e55ba2c13..39c78387ddec 100644
--- a/arch/arm/mach-omap2/board-generic.c
+++ b/arch/arm/mach-omap2/board-generic.c
@@ -238,5 +238,6 @@ DT_MACHINE_START(DRA7XX_DT, "Generic DRA7XX (Flattened Device Tree)")
         .init_machine   = omap_generic_init,
         .init_time      = omap5_realtime_timer_init,
         .dt_compat      = dra7xx_boards_compat,
+        .restart        = omap44xx_restart,
 MACHINE_END
 #endif
diff --git a/arch/arm/mach-omap2/cclock33xx_data.c b/arch/arm/mach-omap2/cclock33xx_data.c
index ba6534d7f155..865d30ee812f 100644
--- a/arch/arm/mach-omap2/cclock33xx_data.c
+++ b/arch/arm/mach-omap2/cclock33xx_data.c
@@ -421,6 +421,10 @@ static struct clk aes0_fck;
 DEFINE_STRUCT_CLK_HW_OMAP(aes0_fck, NULL);
 DEFINE_STRUCT_CLK(aes0_fck, dpll_core_ck_parents, clk_ops_null);
 
+static struct clk rng_fck;
+DEFINE_STRUCT_CLK_HW_OMAP(rng_fck, NULL);
+DEFINE_STRUCT_CLK(rng_fck, dpll_core_ck_parents, clk_ops_null);
+
 /*
  * Modules clock nodes
  *
@@ -966,6 +970,7 @@ static struct omap_clk am33xx_clks[] = {
         CLK(NULL,       "smartreflex1_fck",     &smartreflex1_fck),
         CLK(NULL,       "sha0_fck",             &sha0_fck),
         CLK(NULL,       "aes0_fck",             &aes0_fck),
+        CLK(NULL,       "rng_fck",              &rng_fck),
         CLK(NULL,       "timer1_fck",           &timer1_fck),
         CLK(NULL,       "timer2_fck",           &timer2_fck),
         CLK(NULL,       "timer3_fck",           &timer3_fck),
diff --git a/arch/arm/mach-omap2/cclock44xx_data.c b/arch/arm/mach-omap2/cclock44xx_data.c
index 88e37a474334..1d5b5290d2af 100644
--- a/arch/arm/mach-omap2/cclock44xx_data.c
+++ b/arch/arm/mach-omap2/cclock44xx_data.c
@@ -1707,6 +1707,18 @@ int __init omap4xxx_clk_init(void)
         omap2_clk_disable_autoidle_all();
 
         /*
+         * A set rate of ABE DPLL inturn triggers a set rate of USB DPLL
+         * when its in bypass. So always lock USB before ABE DPLL.
+         */
+        /*
+         * Lock USB DPLL on OMAP4 devices so that the L3INIT power
+         * domain can transition to retention state when not in use.
+         */
+        rc = clk_set_rate(&dpll_usb_ck, OMAP4_DPLL_USB_DEFFREQ);
+        if (rc)
+                pr_err("%s: failed to configure USB DPLL!\n", __func__);
+
+        /*
          * On OMAP4460 the ABE DPLL fails to turn on if in idle low-power
          * state when turning the ABE clock domain. Workaround this by
          * locking the ABE DPLL on boot.
@@ -1718,13 +1730,5 @@ int __init omap4xxx_clk_init(void)
         if (rc)
                 pr_err("%s: failed to configure ABE DPLL!\n", __func__);
 
-        /*
-         * Lock USB DPLL on OMAP4 devices so that the L3INIT power
-         * domain can transition to retention state when not in use.
-         */
-        rc = clk_set_rate(&dpll_usb_ck, OMAP4_DPLL_USB_DEFFREQ);
-        if (rc)
-                pr_err("%s: failed to configure USB DPLL!\n", __func__);
-
         return 0;
 }
diff --git a/arch/arm/mach-omap2/clockdomain.h b/arch/arm/mach-omap2/clockdomain.h
index daeecf1b89fa..4b03394fa0c5 100644
--- a/arch/arm/mach-omap2/clockdomain.h
+++ b/arch/arm/mach-omap2/clockdomain.h
@@ -217,6 +217,7 @@ extern void __init omap3xxx_clockdomains_init(void);
 extern void __init am33xx_clockdomains_init(void);
 extern void __init omap44xx_clockdomains_init(void);
 extern void __init omap54xx_clockdomains_init(void);
+extern void __init dra7xx_clockdomains_init(void);
 
 extern void clkdm_add_autodeps(struct clockdomain *clkdm);
 extern void clkdm_del_autodeps(struct clockdomain *clkdm);
diff --git a/arch/arm/mach-omap2/clockdomains7xx_data.c b/arch/arm/mach-omap2/clockdomains7xx_data.c
new file mode 100644
index 000000000000..57d5df0c1fbd
--- /dev/null
+++ b/arch/arm/mach-omap2/clockdomains7xx_data.c
@@ -0,0 +1,740 @@
+/*
+ * DRA7xx Clock domains framework
+ *
+ * Copyright (C) 2009-2013 Texas Instruments, Inc.
+ * Copyright (C) 2009-2011 Nokia Corporation
+ *
+ * Generated by code originally written by:
+ * Abhijit Pagare (abhijitpagare@ti.com)
+ * Benoit Cousson (b-cousson@ti.com)
+ * Paul Walmsley (paul@pwsan.com)
+ *
+ * This file is automatically generated from the OMAP hardware databases.
+ * We respectfully ask that any modifications to this file be coordinated
+ * with the public linux-omap@vger.kernel.org mailing list and the
+ * authors above to ensure that the autogeneration scripts are kept
+ * up-to-date with the file contents.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/io.h>
+
+#include "clockdomain.h"
+#include "cm1_7xx.h"
+#include "cm2_7xx.h"
+
+#include "cm-regbits-7xx.h"
+#include "prm7xx.h"
+#include "prcm44xx.h"
+#include "prcm_mpu7xx.h"
+
+/* Static Dependencies for DRA7xx Clock Domains */
+
+static struct clkdm_dep cam_wkup_sleep_deps[] = {
+        { .clkdm_name = "emif_clkdm" },
+        { NULL },
+};
+
+static struct clkdm_dep dma_wkup_sleep_deps[] = {
+        { .clkdm_name = "dss_clkdm" },
+        { .clkdm_name = "emif_clkdm" },
+        { .clkdm_name = "ipu_clkdm" },
+        { .clkdm_name = "ipu1_clkdm" },
+        { .clkdm_name = "ipu2_clkdm" },
+        { .clkdm_name = "iva_clkdm" },
+        { .clkdm_name = "l3init_clkdm" },
+        { .clkdm_name = "l4cfg_clkdm" },
+        { .clkdm_name = "l4per_clkdm" },
+        { .clkdm_name = "l4per2_clkdm" },
+        { .clkdm_name = "l4per3_clkdm" },
+        { .clkdm_name = "l4sec_clkdm" },
+        { .clkdm_name = "pcie_clkdm" },
+        { .clkdm_name = "wkupaon_clkdm" },
+        { NULL },
+};
+
+static struct clkdm_dep dsp1_wkup_sleep_deps[] = {
+        { .clkdm_name = "atl_clkdm" },
+        { .clkdm_name = "cam_clkdm" },
+        { .clkdm_name = "dsp2_clkdm" },
+        { .clkdm_name = "dss_clkdm" },
+        { .clkdm_name = "emif_clkdm" },
+        { .clkdm_name = "eve1_clkdm" },
+        { .clkdm_name = "eve2_clkdm" },
+        { .clkdm_name = "eve3_clkdm" },
+        { .clkdm_name = "eve4_clkdm" },
+        { .clkdm_name = "gmac_clkdm" },
+        { .clkdm_name = "gpu_clkdm" },
+        { .clkdm_name = "ipu_clkdm" },
+        { .clkdm_name = "ipu1_clkdm" },
+        { .clkdm_name = "ipu2_clkdm" },
+        { .clkdm_name = "iva_clkdm" },
+        { .clkdm_name = "l3init_clkdm" },
+        { .clkdm_name = "l4per_clkdm" },
+        { .clkdm_name = "l4per2_clkdm" },
+        { .clkdm_name = "l4per3_clkdm" },
+        { .clkdm_name = "l4sec_clkdm" },
+        { .clkdm_name = "pcie_clkdm" },
+        { .clkdm_name = "vpe_clkdm" },
+        { .clkdm_name = "wkupaon_clkdm" },
+        { NULL },
+};
+
+static struct clkdm_dep dsp2_wkup_sleep_deps[] = {
+        { .clkdm_name = "atl_clkdm" },
+        { .clkdm_name = "cam_clkdm" },
+        { .clkdm_name = "dsp1_clkdm" },
+        { .clkdm_name = "dss_clkdm" },
+        { .clkdm_name = "emif_clkdm" },
+        { .clkdm_name = "eve1_clkdm" },
+        { .clkdm_name = "eve2_clkdm" },
+        { .clkdm_name = "eve3_clkdm" },
+        { .clkdm_name = "eve4_clkdm" },
+        { .clkdm_name = "gmac_clkdm" },
+        { .clkdm_name = "gpu_clkdm" },
+        { .clkdm_name = "ipu_clkdm" },
+        { .clkdm_name = "ipu1_clkdm" },
+        { .clkdm_name = "ipu2_clkdm" },
+        { .clkdm_name = "iva_clkdm" },
+        { .clkdm_name = "l3init_clkdm" },
+        { .clkdm_name = "l4per_clkdm" },
+        { .clkdm_name = "l4per2_clkdm" },
+        { .clkdm_name = "l4per3_clkdm" },
+        { .clkdm_name = "l4sec_clkdm" },
+        { .clkdm_name = "pcie_clkdm" },
+        { .clkdm_name = "vpe_clkdm" },
+        { .clkdm_name = "wkupaon_clkdm" },
+        { NULL },
+};
+
+static struct clkdm_dep dss_wkup_sleep_deps[] = {
+        { .clkdm_name = "emif_clkdm" },
+        { .clkdm_name = "iva_clkdm" },
+        { NULL },
+};
+
+static struct clkdm_dep eve1_wkup_sleep_deps[] = {
+        { .clkdm_name = "emif_clkdm" },
+        { .clkdm_name = "eve2_clkdm" },
+        { .clkdm_name = "eve3_clkdm" },
+        { .clkdm_name = "eve4_clkdm" },
+        { .clkdm_name = "iva_clkdm" },
+        { NULL },
+};
+
+static struct clkdm_dep eve2_wkup_sleep_deps[] = {
+        { .clkdm_name = "emif_clkdm" },
+        { .clkdm_name = "eve1_clkdm" },
+        { .clkdm_name = "eve3_clkdm" },
+        { .clkdm_name = "eve4_clkdm" },
+        { .clkdm_name = "iva_clkdm" },
+        { NULL },
+};
+
+static struct clkdm_dep eve3_wkup_sleep_deps[] = {
+        { .clkdm_name = "emif_clkdm" },
+        { .clkdm_name = "eve1_clkdm" },
+        { .clkdm_name = "eve2_clkdm" },
+        { .clkdm_name = "eve4_clkdm" },
+        { .clkdm_name = "iva_clkdm" },
+        { NULL },
+};
+
+static struct clkdm_dep eve4_wkup_sleep_deps[] = {
+        { .clkdm_name = "emif_clkdm" },
+        { .clkdm_name = "eve1_clkdm" },
+        { .clkdm_name = "eve2_clkdm" },
+        { .clkdm_name = "eve3_clkdm" },
+        { .clkdm_name = "iva_clkdm" },
+        { NULL },
+};
+
+static struct clkdm_dep gmac_wkup_sleep_deps[] = {
+        { .clkdm_name = "emif_clkdm" },
+        { .clkdm_name = "l4per2_clkdm" },
+        { NULL },
+};
+
+static struct clkdm_dep gpu_wkup_sleep_deps[] = {
+        { .clkdm_name = "emif_clkdm" },
+        { .clkdm_name = "iva_clkdm" },
+        { NULL },
+};
+
+static struct clkdm_dep ipu1_wkup_sleep_deps[] = {
+        { .clkdm_name = "atl_clkdm" },
+        { .clkdm_name = "dsp1_clkdm" },
+        { .clkdm_name = "dsp2_clkdm" },
+        { .clkdm_name = "dss_clkdm" },
+        { .clkdm_name = "emif_clkdm" },
+        { .clkdm_name = "eve1_clkdm" },
+        { .clkdm_name = "eve2_clkdm" },
+        { .clkdm_name = "eve3_clkdm" },
+        { .clkdm_name = "eve4_clkdm" },
+        { .clkdm_name = "gmac_clkdm" },
+        { .clkdm_name = "gpu_clkdm" },
+        { .clkdm_name = "ipu_clkdm" },
+        { .clkdm_name = "ipu2_clkdm" },
+        { .clkdm_name = "iva_clkdm" },
+        { .clkdm_name = "l3init_clkdm" },
+        { .clkdm_name = "l3main1_clkdm" },
+        { .clkdm_name = "l4cfg_clkdm" },
+        { .clkdm_name = "l4per_clkdm" },
+        { .clkdm_name = "l4per2_clkdm" },
+        { .clkdm_name = "l4per3_clkdm" },
+        { .clkdm_name = "l4sec_clkdm" },
+        { .clkdm_name = "pcie_clkdm" },
+        { .clkdm_name = "vpe_clkdm" },
+        { .clkdm_name = "wkupaon_clkdm" },
+        { NULL },
+};
+
+static struct clkdm_dep ipu2_wkup_sleep_deps[] = {
+        { .clkdm_name = "atl_clkdm" },
+        { .clkdm_name = "dsp1_clkdm" },
+        { .clkdm_name = "dsp2_clkdm" },
+        { .clkdm_name = "dss_clkdm" },
+        { .clkdm_name = "emif_clkdm" },
+        { .clkdm_name = "eve1_clkdm" },
+        { .clkdm_name = "eve2_clkdm" },
+        { .clkdm_name = "eve3_clkdm" },
+        { .clkdm_name = "eve4_clkdm" },
+        { .clkdm_name = "gmac_clkdm" },
+        { .clkdm_name = "gpu_clkdm" },
+        { .clkdm_name = "ipu_clkdm" },
+        { .clkdm_name = "ipu1_clkdm" },
+        { .clkdm_name = "iva_clkdm" },
+        { .clkdm_name = "l3init_clkdm" },
+        { .clkdm_name = "l3main1_clkdm" },
+        { .clkdm_name = "l4cfg_clkdm" },
+        { .clkdm_name = "l4per_clkdm" },
+        { .clkdm_name = "l4per2_clkdm" },
+        { .clkdm_name = "l4per3_clkdm" },
+        { .clkdm_name = "l4sec_clkdm" },
+        { .clkdm_name = "pcie_clkdm" },
+        { .clkdm_name = "vpe_clkdm" },
+        { .clkdm_name = "wkupaon_clkdm" },
+        { NULL },
+};
+
+static struct clkdm_dep iva_wkup_sleep_deps[] = {
+        { .clkdm_name = "emif_clkdm" },
+        { NULL },
+};
+
+static struct clkdm_dep l3init_wkup_sleep_deps[] = {
+        { .clkdm_name = "emif_clkdm" },
+        { .clkdm_name = "iva_clkdm" },
+        { .clkdm_name = "l4cfg_clkdm" },
+        { .clkdm_name = "l4per_clkdm" },
+        { .clkdm_name = "l4per3_clkdm" },
+        { .clkdm_name = "l4sec_clkdm" },
+        { .clkdm_name = "wkupaon_clkdm" },
+        { NULL },
+};
+
+static struct clkdm_dep l4per2_wkup_sleep_deps[] = {
+        { .clkdm_name = "dsp1_clkdm" },
+        { .clkdm_name = "dsp2_clkdm" },
+        { .clkdm_name = "ipu1_clkdm" },
+        { .clkdm_name = "ipu2_clkdm" },
+        { NULL },
+};
+
+static struct clkdm_dep l4sec_wkup_sleep_deps[] = {
+        { .clkdm_name = "emif_clkdm" },
+        { .clkdm_name = "l4per_clkdm" },
+        { NULL },
+};
+
+static struct clkdm_dep mpu_wkup_sleep_deps[] = {
+        { .clkdm_name = "cam_clkdm" },
+        { .clkdm_name = "dsp1_clkdm" },
+        { .clkdm_name = "dsp2_clkdm" },
+        { .clkdm_name = "dss_clkdm" },
+        { .clkdm_name = "emif_clkdm" },
+        { .clkdm_name = "eve1_clkdm" },
+        { .clkdm_name = "eve2_clkdm" },
+        { .clkdm_name = "eve3_clkdm" },
+        { .clkdm_name = "eve4_clkdm" },
+        { .clkdm_name = "gmac_clkdm" },
+        { .clkdm_name = "gpu_clkdm" },
+        { .clkdm_name = "ipu_clkdm" },
+        { .clkdm_name = "ipu1_clkdm" },
+        { .clkdm_name = "ipu2_clkdm" },
+        { .clkdm_name = "iva_clkdm" },
+        { .clkdm_name = "l3init_clkdm" },
+        { .clkdm_name = "l3main1_clkdm" },
+        { .clkdm_name = "l4cfg_clkdm" },
+        { .clkdm_name = "l4per_clkdm" },
+        { .clkdm_name = "l4per2_clkdm" },
+        { .clkdm_name = "l4per3_clkdm" },
+        { .clkdm_name = "l4sec_clkdm" },
+        { .clkdm_name = "pcie_clkdm" },
+        { .clkdm_name = "vpe_clkdm" },
+        { .clkdm_name = "wkupaon_clkdm" },
+        { NULL },
+};
+
+static struct clkdm_dep pcie_wkup_sleep_deps[] = {
+        { .clkdm_name = "atl_clkdm" },
+        { .clkdm_name = "cam_clkdm" },
+        { .clkdm_name = "dsp1_clkdm" },
+        { .clkdm_name = "dsp2_clkdm" },
+        { .clkdm_name = "dss_clkdm" },
+        { .clkdm_name = "emif_clkdm" },
+        { .clkdm_name = "eve1_clkdm" },
+        { .clkdm_name = "eve2_clkdm" },
+        { .clkdm_name = "eve3_clkdm" },
+        { .clkdm_name = "eve4_clkdm" },
+        { .clkdm_name = "gmac_clkdm" },
+        { .clkdm_name = "gpu_clkdm" },
+        { .clkdm_name = "ipu_clkdm" },
+        { .clkdm_name = "ipu1_clkdm" },
+        { .clkdm_name = "iva_clkdm" },
+        { .clkdm_name = "l3init_clkdm" },
+        { .clkdm_name = "l4cfg_clkdm" },
+        { .clkdm_name = "l4per_clkdm" },
+        { .clkdm_name = "l4per2_clkdm" },
+        { .clkdm_name = "l4per3_clkdm" },
+        { .clkdm_name = "l4sec_clkdm" },
+        { .clkdm_name = "vpe_clkdm" },
+        { NULL },
+};
+
+static struct clkdm_dep vpe_wkup_sleep_deps[] = {
+        { .clkdm_name = "emif_clkdm" },
+        { .clkdm_name = "l4per3_clkdm" },
+        { NULL },
+};
+
+static struct clockdomain l4per3_7xx_clkdm = {
+        .name             = "l4per3_clkdm",
+        .pwrdm            = { .name = "l4per_pwrdm" },
+        .prcm_partition   = DRA7XX_CM_CORE_PARTITION,
+        .cm_inst          = DRA7XX_CM_CORE_L4PER_INST,
+        .clkdm_offs       = DRA7XX_CM_CORE_L4PER_L4PER3_CDOFFS,
+        .dep_bit          = DRA7XX_L4PER3_STATDEP_SHIFT,
+        .flags            = CLKDM_CAN_HWSUP_SWSUP,
+};
+
+static struct clockdomain l4per2_7xx_clkdm = {
+        .name             = "l4per2_clkdm",
+        .pwrdm            = { .name = "l4per_pwrdm" },
+        .prcm_partition   = DRA7XX_CM_CORE_PARTITION,
+        .cm_inst          = DRA7XX_CM_CORE_L4PER_INST,
+        .clkdm_offs       = DRA7XX_CM_CORE_L4PER_L4PER2_CDOFFS,
+        .dep_bit          = DRA7XX_L4PER2_STATDEP_SHIFT,
+        .wkdep_srcs       = l4per2_wkup_sleep_deps,
+        .sleepdep_srcs    = l4per2_wkup_sleep_deps,
+        .flags            = CLKDM_CAN_HWSUP_SWSUP,
+};
+
+static struct clockdomain mpu0_7xx_clkdm = {
+        .name             = "mpu0_clkdm",
+        .pwrdm            = { .name = "cpu0_pwrdm" },
+        .prcm_partition   = DRA7XX_MPU_PRCM_PARTITION,
+        .cm_inst          = DRA7XX_MPU_PRCM_CM_C0_INST,
+        .clkdm_offs       = DRA7XX_MPU_PRCM_CM_C0_CPU0_CDOFFS,
+        .flags            = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
+};
+
+static struct clockdomain iva_7xx_clkdm = {
+        .name             = "iva_clkdm",
+        .pwrdm            = { .name = "iva_pwrdm" },
+        .prcm_partition   = DRA7XX_CM_CORE_PARTITION,
+        .cm_inst          = DRA7XX_CM_CORE_IVA_INST,
+        .clkdm_offs       = DRA7XX_CM_CORE_IVA_IVA_CDOFFS,
+        .dep_bit          = DRA7XX_IVA_STATDEP_SHIFT,
+        .wkdep_srcs       = iva_wkup_sleep_deps,
+        .sleepdep_srcs    = iva_wkup_sleep_deps,
+        .flags            = CLKDM_CAN_HWSUP_SWSUP,
+};
+
+static struct clockdomain coreaon_7xx_clkdm = {
+        .name             = "coreaon_clkdm",
+        .pwrdm            = { .name = "coreaon_pwrdm" },
+        .prcm_partition   = DRA7XX_CM_CORE_PARTITION,
+        .cm_inst          = DRA7XX_CM_CORE_COREAON_INST,
+        .clkdm_offs       = DRA7XX_CM_CORE_COREAON_COREAON_CDOFFS,
+        .flags            = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
+};
+
+static struct clockdomain ipu1_7xx_clkdm = {
+        .name             = "ipu1_clkdm",
+        .pwrdm            = { .name = "ipu_pwrdm" },
+        .prcm_partition   = DRA7XX_CM_CORE_AON_PARTITION,
+        .cm_inst          = DRA7XX_CM_CORE_AON_IPU_INST,
+        .clkdm_offs       = DRA7XX_CM_CORE_AON_IPU_IPU1_CDOFFS,
+        .dep_bit          = DRA7XX_IPU1_STATDEP_SHIFT,
+        .wkdep_srcs       = ipu1_wkup_sleep_deps,
+        .sleepdep_srcs    = ipu1_wkup_sleep_deps,
+        .flags            = CLKDM_CAN_HWSUP_SWSUP,
+};
+
+static struct clockdomain ipu2_7xx_clkdm = {
+        .name             = "ipu2_clkdm",
+        .pwrdm            = { .name = "core_pwrdm" },
+        .prcm_partition   = DRA7XX_CM_CORE_PARTITION,
+        .cm_inst          = DRA7XX_CM_CORE_CORE_INST,
+        .clkdm_offs       = DRA7XX_CM_CORE_CORE_IPU2_CDOFFS,
+        .dep_bit          = DRA7XX_IPU2_STATDEP_SHIFT,
+        .wkdep_srcs       = ipu2_wkup_sleep_deps,
+        .sleepdep_srcs    = ipu2_wkup_sleep_deps,
+        .flags            = CLKDM_CAN_HWSUP_SWSUP,
+};
+
+static struct clockdomain l3init_7xx_clkdm = {
+        .name             = "l3init_clkdm",
+        .pwrdm            = { .name = "l3init_pwrdm" },
+        .prcm_partition   = DRA7XX_CM_CORE_PARTITION,
+        .cm_inst          = DRA7XX_CM_CORE_L3INIT_INST,
+        .clkdm_offs       = DRA7XX_CM_CORE_L3INIT_L3INIT_CDOFFS,
+        .dep_bit          = DRA7XX_L3INIT_STATDEP_SHIFT,
+        .wkdep_srcs       = l3init_wkup_sleep_deps,
+        .sleepdep_srcs    = l3init_wkup_sleep_deps,
+        .flags            = CLKDM_CAN_HWSUP_SWSUP,
+};
+
+static struct clockdomain l4sec_7xx_clkdm = {
+        .name             = "l4sec_clkdm",
+        .pwrdm            = { .name = "l4per_pwrdm" },
+        .prcm_partition   = DRA7XX_CM_CORE_PARTITION,
+        .cm_inst          = DRA7XX_CM_CORE_L4PER_INST,
+        .clkdm_offs       = DRA7XX_CM_CORE_L4PER_L4SEC_CDOFFS,
+        .dep_bit          = DRA7XX_L4SEC_STATDEP_SHIFT,
+        .wkdep_srcs       = l4sec_wkup_sleep_deps,
+        .sleepdep_srcs    = l4sec_wkup_sleep_deps,
+        .flags            = CLKDM_CAN_HWSUP_SWSUP,
+};
+
+static struct clockdomain l3main1_7xx_clkdm = {
+        .name             = "l3main1_clkdm",
+        .pwrdm            = { .name = "core_pwrdm" },
+        .prcm_partition   = DRA7XX_CM_CORE_PARTITION,
+        .cm_inst          = DRA7XX_CM_CORE_CORE_INST,
+        .clkdm_offs       = DRA7XX_CM_CORE_CORE_L3MAIN1_CDOFFS,
+        .dep_bit          = DRA7XX_L3MAIN1_STATDEP_SHIFT,
+        .flags            = CLKDM_CAN_HWSUP,
+};
+
+static struct clockdomain vpe_7xx_clkdm = {
+        .name             = "vpe_clkdm",
+        .pwrdm            = { .name = "vpe_pwrdm" },
+        .prcm_partition   = DRA7XX_CM_CORE_AON_PARTITION,
+        .cm_inst          = DRA7XX_CM_CORE_AON_VPE_INST,
+        .clkdm_offs       = DRA7XX_CM_CORE_AON_VPE_VPE_CDOFFS,
+        .dep_bit          = DRA7XX_VPE_STATDEP_SHIFT,
+        .wkdep_srcs       = vpe_wkup_sleep_deps,
+        .sleepdep_srcs    = vpe_wkup_sleep_deps,
+        .flags            = CLKDM_CAN_HWSUP_SWSUP,
+};
+
+static struct clockdomain mpu_7xx_clkdm = {
+        .name             = "mpu_clkdm",
+        .pwrdm            = { .name = "mpu_pwrdm" },
+        .prcm_partition   = DRA7XX_CM_CORE_AON_PARTITION,
+        .cm_inst          = DRA7XX_CM_CORE_AON_MPU_INST,
+        .clkdm_offs       = DRA7XX_CM_CORE_AON_MPU_MPU_CDOFFS,
+        .wkdep_srcs       = mpu_wkup_sleep_deps,
+        .sleepdep_srcs    = mpu_wkup_sleep_deps,
+        .flags            = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
+};
+
+static struct clockdomain custefuse_7xx_clkdm = {
+        .name             = "custefuse_clkdm",
+        .pwrdm            = { .name = "custefuse_pwrdm" },
+        .prcm_partition   = DRA7XX_CM_CORE_PARTITION,
+        .cm_inst          = DRA7XX_CM_CORE_CUSTEFUSE_INST,
+        .clkdm_offs       = DRA7XX_CM_CORE_CUSTEFUSE_CUSTEFUSE_CDOFFS,
+        .flags            = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
+};
+
+static struct clockdomain ipu_7xx_clkdm = {
+        .name             = "ipu_clkdm",
+        .pwrdm            = { .name = "ipu_pwrdm" },
+        .prcm_partition   = DRA7XX_CM_CORE_AON_PARTITION,
+        .cm_inst          = DRA7XX_CM_CORE_AON_IPU_INST,
+        .clkdm_offs       = DRA7XX_CM_CORE_AON_IPU_IPU_CDOFFS,
+        .dep_bit          = DRA7XX_IPU_STATDEP_SHIFT,
+        .flags            = CLKDM_CAN_HWSUP_SWSUP,
+};
+
+static struct clockdomain mpu1_7xx_clkdm = {
+        .name             = "mpu1_clkdm",
+        .pwrdm            = { .name = "cpu1_pwrdm" },
+        .prcm_partition   = DRA7XX_MPU_PRCM_PARTITION,
+        .cm_inst          = DRA7XX_MPU_PRCM_CM_C1_INST,
+        .clkdm_offs       = DRA7XX_MPU_PRCM_CM_C1_CPU1_CDOFFS,
+        .flags            = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
+};
+
+static struct clockdomain gmac_7xx_clkdm = {
+        .name             = "gmac_clkdm",
+        .pwrdm            = { .name = "l3init_pwrdm" },
+        .prcm_partition   = DRA7XX_CM_CORE_PARTITION,
+        .cm_inst          = DRA7XX_CM_CORE_L3INIT_INST,
+        .clkdm_offs       = DRA7XX_CM_CORE_L3INIT_GMAC_CDOFFS,
+        .dep_bit          = DRA7XX_GMAC_STATDEP_SHIFT,
+        .wkdep_srcs       = gmac_wkup_sleep_deps,
+        .sleepdep_srcs    = gmac_wkup_sleep_deps,
+        .flags            = CLKDM_CAN_HWSUP_SWSUP,
+};
+
+static struct clockdomain l4cfg_7xx_clkdm = {
+        .name             = "l4cfg_clkdm",
+        .pwrdm            = { .name = "core_pwrdm" },
+        .prcm_partition   = DRA7XX_CM_CORE_PARTITION,
+        .cm_inst          = DRA7XX_CM_CORE_CORE_INST,
+        .clkdm_offs       = DRA7XX_CM_CORE_CORE_L4CFG_CDOFFS,
+        .dep_bit          = DRA7XX_L4CFG_STATDEP_SHIFT,
+        .flags            = CLKDM_CAN_HWSUP,
+};
+
+static struct clockdomain dma_7xx_clkdm = {
+        .name             = "dma_clkdm",
+        .pwrdm            = { .name = "core_pwrdm" },
+        .prcm_partition   = DRA7XX_CM_CORE_PARTITION,
+        .cm_inst          = DRA7XX_CM_CORE_CORE_INST,
+        .clkdm_offs       = DRA7XX_CM_CORE_CORE_DMA_CDOFFS,
+        .wkdep_srcs       = dma_wkup_sleep_deps,
+        .sleepdep_srcs    = dma_wkup_sleep_deps,
+        .flags            = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
+};
+
+static struct clockdomain rtc_7xx_clkdm = {
+        .name             = "rtc_clkdm",
+        .pwrdm            = { .name = "rtc_pwrdm" },
+        .prcm_partition   = DRA7XX_CM_CORE_AON_PARTITION,
+        .cm_inst          = DRA7XX_CM_CORE_AON_RTC_INST,
+        .clkdm_offs       = DRA7XX_CM_CORE_AON_RTC_RTC_CDOFFS,
+        .flags            = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
+};
+
+static struct clockdomain pcie_7xx_clkdm = {
+        .name             = "pcie_clkdm",
+        .pwrdm            = { .name = "l3init_pwrdm" },
+        .prcm_partition   = DRA7XX_CM_CORE_PARTITION,
+        .cm_inst          = DRA7XX_CM_CORE_L3INIT_INST,
+        .clkdm_offs       = DRA7XX_CM_CORE_L3INIT_PCIE_CDOFFS,
+        .dep_bit          = DRA7XX_PCIE_STATDEP_SHIFT,
+        .wkdep_srcs       = pcie_wkup_sleep_deps,
+        .sleepdep_srcs    = pcie_wkup_sleep_deps,
+        .flags            = CLKDM_CAN_HWSUP_SWSUP,
+};
+
+static struct clockdomain atl_7xx_clkdm = {
+        .name             = "atl_clkdm",
+        .pwrdm            = { .name = "core_pwrdm" },
+        .prcm_partition   = DRA7XX_CM_CORE_PARTITION,
+        .cm_inst          = DRA7XX_CM_CORE_CORE_INST,
+        .clkdm_offs       = DRA7XX_CM_CORE_CORE_ATL_CDOFFS,
+        .dep_bit          = DRA7XX_ATL_STATDEP_SHIFT,
+        .flags            = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
+};
+
+static struct clockdomain l3instr_7xx_clkdm = {
+        .name             = "l3instr_clkdm",
+        .pwrdm            = { .name = "core_pwrdm" },
+        .prcm_partition   = DRA7XX_CM_CORE_PARTITION,
+        .cm_inst          = DRA7XX_CM_CORE_CORE_INST,
+        .clkdm_offs       = DRA7XX_CM_CORE_CORE_L3INSTR_CDOFFS,
+};
+
+static struct clockdomain dss_7xx_clkdm = {
+        .name             = "dss_clkdm",
+        .pwrdm            = { .name = "dss_pwrdm" },
+        .prcm_partition   = DRA7XX_CM_CORE_PARTITION,
+        .cm_inst          = DRA7XX_CM_CORE_DSS_INST,
+        .clkdm_offs       = DRA7XX_CM_CORE_DSS_DSS_CDOFFS,
+        .dep_bit          = DRA7XX_DSS_STATDEP_SHIFT,
+        .wkdep_srcs       = dss_wkup_sleep_deps,
+        .sleepdep_srcs    = dss_wkup_sleep_deps,
+        .flags            = CLKDM_CAN_HWSUP_SWSUP,
+};
+
+static struct clockdomain emif_7xx_clkdm = {
+        .name             = "emif_clkdm",
+        .pwrdm            = { .name = "core_pwrdm" },
+        .prcm_partition   = DRA7XX_CM_CORE_PARTITION,
+        .cm_inst          = DRA7XX_CM_CORE_CORE_INST,
+        .clkdm_offs       = DRA7XX_CM_CORE_CORE_EMIF_CDOFFS,
+        .dep_bit          = DRA7XX_EMIF_STATDEP_SHIFT,
+        .flags            = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
+};
+
+static struct clockdomain emu_7xx_clkdm = {
+        .name             = "emu_clkdm",
+        .pwrdm            = { .name = "emu_pwrdm" },
+        .prcm_partition   = DRA7XX_PRM_PARTITION,
+        .cm_inst          = DRA7XX_PRM_EMU_CM_INST,
+        .clkdm_offs       = DRA7XX_PRM_EMU_CM_EMU_CDOFFS,
+        .flags            = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
+};
+
+static struct clockdomain dsp2_7xx_clkdm = {
+        .name             = "dsp2_clkdm",
+        .pwrdm            = { .name = "dsp2_pwrdm" },
+        .prcm_partition   = DRA7XX_CM_CORE_AON_PARTITION,
+        .cm_inst          = DRA7XX_CM_CORE_AON_DSP2_INST,
+        .clkdm_offs       = DRA7XX_CM_CORE_AON_DSP2_DSP2_CDOFFS,
+        .dep_bit          = DRA7XX_DSP2_STATDEP_SHIFT,
+        .wkdep_srcs       = dsp2_wkup_sleep_deps,
+        .sleepdep_srcs    = dsp2_wkup_sleep_deps,
+        .flags            = CLKDM_CAN_HWSUP_SWSUP,
+};
+
+static struct clockdomain dsp1_7xx_clkdm = {
+        .name             = "dsp1_clkdm",
+        .pwrdm            = { .name = "dsp1_pwrdm" },
+        .prcm_partition   = DRA7XX_CM_CORE_AON_PARTITION,
+        .cm_inst          = DRA7XX_CM_CORE_AON_DSP1_INST,
+        .clkdm_offs       = DRA7XX_CM_CORE_AON_DSP1_DSP1_CDOFFS,
+        .dep_bit          = DRA7XX_DSP1_STATDEP_SHIFT,
+        .wkdep_srcs       = dsp1_wkup_sleep_deps,
+        .sleepdep_srcs    = dsp1_wkup_sleep_deps,
+        .flags            = CLKDM_CAN_HWSUP_SWSUP,
+};
+
+static struct clockdomain cam_7xx_clkdm = {
+        .name             = "cam_clkdm",
+        .pwrdm            = { .name = "cam_pwrdm" },
+        .prcm_partition   = DRA7XX_CM_CORE_PARTITION,
+        .cm_inst          = DRA7XX_CM_CORE_CAM_INST,
+        .clkdm_offs       = DRA7XX_CM_CORE_CAM_CAM_CDOFFS,
+        .dep_bit          = DRA7XX_CAM_STATDEP_SHIFT,
+        .wkdep_srcs       = cam_wkup_sleep_deps,
+        .sleepdep_srcs    = cam_wkup_sleep_deps,
+        .flags            = CLKDM_CAN_HWSUP_SWSUP,
+};
+
+static struct clockdomain l4per_7xx_clkdm = {
+        .name             = "l4per_clkdm",
+        .pwrdm            = { .name = "l4per_pwrdm" },
+        .prcm_partition   = DRA7XX_CM_CORE_PARTITION,
+        .cm_inst          = DRA7XX_CM_CORE_L4PER_INST,
+        .clkdm_offs       = DRA7XX_CM_CORE_L4PER_L4PER_CDOFFS,
+        .dep_bit          = DRA7XX_L4PER_STATDEP_SHIFT,
+        .flags            = CLKDM_CAN_HWSUP_SWSUP,
+};
+
+static struct clockdomain gpu_7xx_clkdm = {
+        .name             = "gpu_clkdm",
+        .pwrdm            = { .name = "gpu_pwrdm" },
+        .prcm_partition   = DRA7XX_CM_CORE_PARTITION,
+        .cm_inst          = DRA7XX_CM_CORE_GPU_INST,
+        .clkdm_offs       = DRA7XX_CM_CORE_GPU_GPU_CDOFFS,
+        .dep_bit          = DRA7XX_GPU_STATDEP_SHIFT,
+        .wkdep_srcs       = gpu_wkup_sleep_deps,
+        .sleepdep_srcs    = gpu_wkup_sleep_deps,
+        .flags            = CLKDM_CAN_HWSUP_SWSUP,
+};
+
+static struct clockdomain eve4_7xx_clkdm = {
+        .name             = "eve4_clkdm",
+        .pwrdm            = { .name = "eve4_pwrdm" },
+        .prcm_partition   = DRA7XX_CM_CORE_AON_PARTITION,
+        .cm_inst          = DRA7XX_CM_CORE_AON_EVE4_INST,
+        .clkdm_offs       = DRA7XX_CM_CORE_AON_EVE4_EVE4_CDOFFS,
+        .dep_bit          = DRA7XX_EVE4_STATDEP_SHIFT,
+        .wkdep_srcs       = eve4_wkup_sleep_deps,
+        .sleepdep_srcs    = eve4_wkup_sleep_deps,
+        .flags            = CLKDM_CAN_HWSUP_SWSUP,
+};
+
+static struct clockdomain eve2_7xx_clkdm = {
+        .name             = "eve2_clkdm",
+        .pwrdm            = { .name = "eve2_pwrdm" },
+        .prcm_partition   = DRA7XX_CM_CORE_AON_PARTITION,
+        .cm_inst          = DRA7XX_CM_CORE_AON_EVE2_INST,
+        .clkdm_offs       = DRA7XX_CM_CORE_AON_EVE2_EVE2_CDOFFS,
+        .dep_bit          = DRA7XX_EVE2_STATDEP_SHIFT,
+        .wkdep_srcs       = eve2_wkup_sleep_deps,
+        .sleepdep_srcs    = eve2_wkup_sleep_deps,
+        .flags            = CLKDM_CAN_HWSUP_SWSUP,
+};
+
+static struct clockdomain eve3_7xx_clkdm = {
+        .name             = "eve3_clkdm",
+        .pwrdm            = { .name = "eve3_pwrdm" },
+        .prcm_partition   = DRA7XX_CM_CORE_AON_PARTITION,
+        .cm_inst          = DRA7XX_CM_CORE_AON_EVE3_INST,
+        .clkdm_offs       = DRA7XX_CM_CORE_AON_EVE3_EVE3_CDOFFS,
+        .dep_bit          = DRA7XX_EVE3_STATDEP_SHIFT,
+        .wkdep_srcs       = eve3_wkup_sleep_deps,
+        .sleepdep_srcs    = eve3_wkup_sleep_deps,
+        .flags            = CLKDM_CAN_HWSUP_SWSUP,
+};
+
+static struct clockdomain wkupaon_7xx_clkdm = {
+        .name             = "wkupaon_clkdm",
+        .pwrdm            = { .name = "wkupaon_pwrdm" },
+        .prcm_partition   = DRA7XX_PRM_PARTITION,
+        .cm_inst          = DRA7XX_PRM_WKUPAON_CM_INST,
+        .clkdm_offs       = DRA7XX_PRM_WKUPAON_CM_WKUPAON_CDOFFS,
+        .dep_bit          = DRA7XX_WKUPAON_STATDEP_SHIFT,
+        .flags            = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
+};
+
+static struct clockdomain eve1_7xx_clkdm = {
+        .name             = "eve1_clkdm",
+        .pwrdm            = { .name = "eve1_pwrdm" },
+        .prcm_partition   = DRA7XX_CM_CORE_AON_PARTITION,
+        .cm_inst          = DRA7XX_CM_CORE_AON_EVE1_INST,
+        .clkdm_offs       = DRA7XX_CM_CORE_AON_EVE1_EVE1_CDOFFS,
+        .dep_bit          = DRA7XX_EVE1_STATDEP_SHIFT,
+        .wkdep_srcs       = eve1_wkup_sleep_deps,
+        .sleepdep_srcs    = eve1_wkup_sleep_deps,
+        .flags            = CLKDM_CAN_HWSUP_SWSUP,
+};
+
+/* As clockdomains are added or removed above, this list must also be changed */
+static struct clockdomain *clockdomains_dra7xx[] __initdata = {
+        &l4per3_7xx_clkdm,
+        &l4per2_7xx_clkdm,
+        &mpu0_7xx_clkdm,
+        &iva_7xx_clkdm,
+        &coreaon_7xx_clkdm,
+        &ipu1_7xx_clkdm,
+        &ipu2_7xx_clkdm,
+        &l3init_7xx_clkdm,
+        &l4sec_7xx_clkdm,
+        &l3main1_7xx_clkdm,
+        &vpe_7xx_clkdm,
+        &mpu_7xx_clkdm,
+        &custefuse_7xx_clkdm,
+        &ipu_7xx_clkdm,
+        &mpu1_7xx_clkdm,
+        &gmac_7xx_clkdm,
+        &l4cfg_7xx_clkdm,
+        &dma_7xx_clkdm,
+        &rtc_7xx_clkdm,
+        &pcie_7xx_clkdm,
+        &atl_7xx_clkdm,
+        &l3instr_7xx_clkdm,
+        &dss_7xx_clkdm,
+        &emif_7xx_clkdm,
+        &emu_7xx_clkdm,
+        &dsp2_7xx_clkdm,
+        &dsp1_7xx_clkdm,
+        &cam_7xx_clkdm,
+        &l4per_7xx_clkdm,
+        &gpu_7xx_clkdm,
+        &eve4_7xx_clkdm,
+        &eve2_7xx_clkdm,
+        &eve3_7xx_clkdm,
+        &wkupaon_7xx_clkdm,
+        &eve1_7xx_clkdm,
+        NULL
+};
+
+void __init dra7xx_clockdomains_init(void)
+{
+        clkdm_register_platform_funcs(&omap4_clkdm_operations);
+        clkdm_register_clkdms(clockdomains_dra7xx);
+        clkdm_complete_init();
+}
diff --git a/arch/arm/mach-omap2/cm-regbits-7xx.h b/arch/arm/mach-omap2/cm-regbits-7xx.h
new file mode 100644
index 000000000000..ad8f81ce9b16
--- /dev/null
+++ b/arch/arm/mach-omap2/cm-regbits-7xx.h
@@ -0,0 +1,51 @@
+/*
+ * DRA7xx Clock Management register bits
+ *
+ * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
+ *
+ * Generated by code originally written by:
+ * Paul Walmsley (paul@pwsan.com)
+ * Rajendra Nayak (rnayak@ti.com)
+ * Benoit Cousson (b-cousson@ti.com)
+ *
+ * This file is automatically generated from the OMAP hardware databases.
+ * We respectfully ask that any modifications to this file be coordinated
+ * with the public linux-omap@vger.kernel.org mailing list and the
+ * authors above to ensure that the autogeneration scripts are kept
+ * up-to-date with the file contents.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ARCH_ARM_MACH_OMAP2_CM_REGBITS_7XX_H
+#define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_7XX_H
+
+#define DRA7XX_ATL_STATDEP_SHIFT                                30
+#define DRA7XX_CAM_STATDEP_SHIFT                                9
+#define DRA7XX_DSP1_STATDEP_SHIFT                               1
+#define DRA7XX_DSP2_STATDEP_SHIFT                               18
+#define DRA7XX_DSS_STATDEP_SHIFT                                8
+#define DRA7XX_EMIF_STATDEP_SHIFT                               4
+#define DRA7XX_EVE1_STATDEP_SHIFT                               19
+#define DRA7XX_EVE2_STATDEP_SHIFT                               20
+#define DRA7XX_EVE3_STATDEP_SHIFT                               21
+#define DRA7XX_EVE4_STATDEP_SHIFT                               22
+#define DRA7XX_GMAC_STATDEP_SHIFT                               25
+#define DRA7XX_GPU_STATDEP_SHIFT                                10
+#define DRA7XX_IPU1_STATDEP_SHIFT                               23
+#define DRA7XX_IPU2_STATDEP_SHIFT                               0
+#define DRA7XX_IPU_STATDEP_SHIFT                                24
+#define DRA7XX_IVA_STATDEP_SHIFT                                2
+#define DRA7XX_L3INIT_STATDEP_SHIFT                             7
+#define DRA7XX_L3MAIN1_STATDEP_SHIFT                            5
+#define DRA7XX_L4CFG_STATDEP_SHIFT                              12
+#define DRA7XX_L4PER2_STATDEP_SHIFT                             26
+#define DRA7XX_L4PER3_STATDEP_SHIFT                             27
+#define DRA7XX_L4PER_STATDEP_SHIFT                              13
+#define DRA7XX_L4SEC_STATDEP_SHIFT                              14
+#define DRA7XX_PCIE_STATDEP_SHIFT                               29
+#define DRA7XX_VPE_STATDEP_SHIFT                                28
+#define DRA7XX_WKUPAON_STATDEP_SHIFT                            15
+#endif
diff --git a/arch/arm/mach-omap2/cm1_7xx.h b/arch/arm/mach-omap2/cm1_7xx.h
new file mode 100644
index 000000000000..ca6fa1febaac
--- /dev/null
+++ b/arch/arm/mach-omap2/cm1_7xx.h
@@ -0,0 +1,324 @@
+/*
+ * DRA7xx CM1 instance offset macros
+ *
+ * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
+ *
+ * Generated by code originally written by:
+ * Paul Walmsley (paul@pwsan.com)
+ * Rajendra Nayak (rnayak@ti.com)
+ * Benoit Cousson (b-cousson@ti.com)
+ *
+ * This file is automatically generated from the OMAP hardware databases.
+ * We respectfully ask that any modifications to this file be coordinated
+ * with the public linux-omap@vger.kernel.org mailing list and the
+ * authors above to ensure that the autogeneration scripts are kept
+ * up-to-date with the file contents.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef __ARCH_ARM_MACH_OMAP2_CM1_7XX_H
+#define __ARCH_ARM_MACH_OMAP2_CM1_7XX_H
+
+#include "cm_44xx_54xx.h"
+
+/* CM1 base address */
+#define DRA7XX_CM_CORE_AON_BASE         0x4a005000
+
+#define DRA7XX_CM_CORE_AON_REGADDR(inst, reg)                           \
+        OMAP2_L4_IO_ADDRESS(DRA7XX_CM_CORE_AON_BASE + (inst) + (reg))
+
+/* CM_CORE_AON instances */
+#define DRA7XX_CM_CORE_AON_OCP_SOCKET_INST      0x0000
+#define DRA7XX_CM_CORE_AON_CKGEN_INST           0x0100
+#define DRA7XX_CM_CORE_AON_MPU_INST             0x0300
+#define DRA7XX_CM_CORE_AON_DSP1_INST            0x0400
+#define DRA7XX_CM_CORE_AON_IPU_INST             0x0500
+#define DRA7XX_CM_CORE_AON_DSP2_INST            0x0600
+#define DRA7XX_CM_CORE_AON_EVE1_INST            0x0640
+#define DRA7XX_CM_CORE_AON_EVE2_INST            0x0680
+#define DRA7XX_CM_CORE_AON_EVE3_INST            0x06c0
+#define DRA7XX_CM_CORE_AON_EVE4_INST            0x0700
+#define DRA7XX_CM_CORE_AON_RTC_INST             0x0740
+#define DRA7XX_CM_CORE_AON_VPE_INST             0x0760
+#define DRA7XX_CM_CORE_AON_RESTORE_INST         0x0e00
+#define DRA7XX_CM_CORE_AON_INSTR_INST           0x0f00
+
+/* CM_CORE_AON clockdomain register offsets (from instance start) */
+#define DRA7XX_CM_CORE_AON_MPU_MPU_CDOFFS       0x0000
+#define DRA7XX_CM_CORE_AON_DSP1_DSP1_CDOFFS     0x0000
+#define DRA7XX_CM_CORE_AON_IPU_IPU1_CDOFFS      0x0000
+#define DRA7XX_CM_CORE_AON_IPU_IPU_CDOFFS       0x0040
+#define DRA7XX_CM_CORE_AON_DSP2_DSP2_CDOFFS     0x0000
+#define DRA7XX_CM_CORE_AON_EVE1_EVE1_CDOFFS     0x0000
+#define DRA7XX_CM_CORE_AON_EVE2_EVE2_CDOFFS     0x0000
+#define DRA7XX_CM_CORE_AON_EVE3_EVE3_CDOFFS     0x0000
+#define DRA7XX_CM_CORE_AON_EVE4_EVE4_CDOFFS     0x0000
+#define DRA7XX_CM_CORE_AON_RTC_RTC_CDOFFS       0x0000
+#define DRA7XX_CM_CORE_AON_VPE_VPE_CDOFFS       0x0000
+
+/* CM_CORE_AON */
+
+/* CM_CORE_AON.OCP_SOCKET_CM_CORE_AON register offsets */
+#define DRA7XX_REVISION_CM_CORE_AON_OFFSET              0x0000
+#define DRA7XX_CM_CM_CORE_AON_PROFILING_CLKCTRL_OFFSET  0x0040
+#define DRA7XX_CM_CM_CORE_AON_PROFILING_CLKCTRL         DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_OCP_SOCKET_INST, 0x0040)
+#define DRA7XX_CM_CORE_AON_DEBUG_OUT_OFFSET             0x00ec
+#define DRA7XX_CM_CORE_AON_DEBUG_CFG0_OFFSET            0x00f0
+#define DRA7XX_CM_CORE_AON_DEBUG_CFG1_OFFSET            0x00f4
+#define DRA7XX_CM_CORE_AON_DEBUG_CFG2_OFFSET            0x00f8
+#define DRA7XX_CM_CORE_AON_DEBUG_CFG3_OFFSET            0x00fc
+
+/* CM_CORE_AON.CKGEN_CM_CORE_AON register offsets */
+#define DRA7XX_CM_CLKSEL_CORE_OFFSET                    0x0000
+#define DRA7XX_CM_CLKSEL_CORE                           DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0000)
+#define DRA7XX_CM_CLKSEL_ABE_OFFSET                     0x0008
+#define DRA7XX_CM_CLKSEL_ABE                            DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0008)
+#define DRA7XX_CM_DLL_CTRL_OFFSET                       0x0010
+#define DRA7XX_CM_CLKMODE_DPLL_CORE_OFFSET              0x0020
+#define DRA7XX_CM_CLKMODE_DPLL_CORE                     DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0020)
+#define DRA7XX_CM_IDLEST_DPLL_CORE_OFFSET               0x0024
+#define DRA7XX_CM_IDLEST_DPLL_CORE                      DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0024)
+#define DRA7XX_CM_AUTOIDLE_DPLL_CORE_OFFSET             0x0028
+#define DRA7XX_CM_AUTOIDLE_DPLL_CORE                    DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0028)
+#define DRA7XX_CM_CLKSEL_DPLL_CORE_OFFSET               0x002c
+#define DRA7XX_CM_CLKSEL_DPLL_CORE                      DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x002c)
+#define DRA7XX_CM_DIV_M2_DPLL_CORE_OFFSET               0x0030
+#define DRA7XX_CM_DIV_M2_DPLL_CORE                      DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0030)
+#define DRA7XX_CM_DIV_M3_DPLL_CORE_OFFSET               0x0034
+#define DRA7XX_CM_DIV_M3_DPLL_CORE                      DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0034)
+#define DRA7XX_CM_DIV_H11_DPLL_CORE_OFFSET              0x0038
+#define DRA7XX_CM_DIV_H11_DPLL_CORE                     DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0038)
+#define DRA7XX_CM_DIV_H12_DPLL_CORE_OFFSET              0x003c
+#define DRA7XX_CM_DIV_H12_DPLL_CORE                     DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x003c)
+#define DRA7XX_CM_DIV_H13_DPLL_CORE_OFFSET              0x0040
+#define DRA7XX_CM_DIV_H13_DPLL_CORE                     DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0040)
+#define DRA7XX_CM_DIV_H14_DPLL_CORE_OFFSET              0x0044
+#define DRA7XX_CM_DIV_H14_DPLL_CORE                     DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0044)
+#define DRA7XX_CM_SSC_DELTAMSTEP_DPLL_CORE_OFFSET       0x0048
+#define DRA7XX_CM_SSC_MODFREQDIV_DPLL_CORE_OFFSET       0x004c
+#define DRA7XX_CM_DIV_H21_DPLL_CORE_OFFSET              0x0050
+#define DRA7XX_CM_DIV_H21_DPLL_CORE                     DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0050)
+#define DRA7XX_CM_DIV_H22_DPLL_CORE_OFFSET              0x0054
+#define DRA7XX_CM_DIV_H22_DPLL_CORE                     DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0054)
+#define DRA7XX_CM_DIV_H23_DPLL_CORE_OFFSET              0x0058
+#define DRA7XX_CM_DIV_H23_DPLL_CORE                     DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0058)
+#define DRA7XX_CM_DIV_H24_DPLL_CORE_OFFSET              0x005c
+#define DRA7XX_CM_DIV_H24_DPLL_CORE                     DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x005c)
+#define DRA7XX_CM_CLKMODE_DPLL_MPU_OFFSET               0x0060
+#define DRA7XX_CM_CLKMODE_DPLL_MPU                      DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0060)
+#define DRA7XX_CM_IDLEST_DPLL_MPU_OFFSET                0x0064
+#define DRA7XX_CM_IDLEST_DPLL_MPU                       DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0064)
+#define DRA7XX_CM_AUTOIDLE_DPLL_MPU_OFFSET              0x0068
+#define DRA7XX_CM_AUTOIDLE_DPLL_MPU                     DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0068)
+#define DRA7XX_CM_CLKSEL_DPLL_MPU_OFFSET                0x006c
+#define DRA7XX_CM_CLKSEL_DPLL_MPU                       DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x006c)
+#define DRA7XX_CM_DIV_M2_DPLL_MPU_OFFSET                0x0070
+#define DRA7XX_CM_DIV_M2_DPLL_MPU                       DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0070)
+#define DRA7XX_CM_SSC_DELTAMSTEP_DPLL_MPU_OFFSET        0x0088
+#define DRA7XX_CM_SSC_MODFREQDIV_DPLL_MPU_OFFSET        0x008c
+#define DRA7XX_CM_BYPCLK_DPLL_MPU_OFFSET                0x009c
+#define DRA7XX_CM_BYPCLK_DPLL_MPU                       DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x009c)
+#define DRA7XX_CM_CLKMODE_DPLL_IVA_OFFSET               0x00a0
+#define DRA7XX_CM_CLKMODE_DPLL_IVA                      DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00a0)
+#define DRA7XX_CM_IDLEST_DPLL_IVA_OFFSET                0x00a4
+#define DRA7XX_CM_IDLEST_DPLL_IVA                       DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00a4)
+#define DRA7XX_CM_AUTOIDLE_DPLL_IVA_OFFSET              0x00a8
+#define DRA7XX_CM_AUTOIDLE_DPLL_IVA                     DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00a8)
+#define DRA7XX_CM_CLKSEL_DPLL_IVA_OFFSET                0x00ac
+#define DRA7XX_CM_CLKSEL_DPLL_IVA                       DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00ac)
+#define DRA7XX_CM_DIV_M2_DPLL_IVA_OFFSET                0x00b0
+#define DRA7XX_CM_DIV_M2_DPLL_IVA                       DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00b0)
+#define DRA7XX_CM_DIV_M3_DPLL_IVA_OFFSET                0x00b4
+#define DRA7XX_CM_DIV_M3_DPLL_IVA                       DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00b4)
+#define DRA7XX_CM_SSC_DELTAMSTEP_DPLL_IVA_OFFSET        0x00c8
+#define DRA7XX_CM_SSC_MODFREQDIV_DPLL_IVA_OFFSET        0x00cc
+#define DRA7XX_CM_BYPCLK_DPLL_IVA_OFFSET                0x00dc
+#define DRA7XX_CM_BYPCLK_DPLL_IVA                       DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00dc)
+#define DRA7XX_CM_CLKMODE_DPLL_ABE_OFFSET               0x00e0
+#define DRA7XX_CM_CLKMODE_DPLL_ABE                      DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00e0)
+#define DRA7XX_CM_IDLEST_DPLL_ABE_OFFSET                0x00e4
+#define DRA7XX_CM_IDLEST_DPLL_ABE                       DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00e4)
+#define DRA7XX_CM_AUTOIDLE_DPLL_ABE_OFFSET              0x00e8
+#define DRA7XX_CM_AUTOIDLE_DPLL_ABE                     DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00e8)
+#define DRA7XX_CM_CLKSEL_DPLL_ABE_OFFSET                0x00ec
+#define DRA7XX_CM_CLKSEL_DPLL_ABE                       DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00ec)
+#define DRA7XX_CM_DIV_M2_DPLL_ABE_OFFSET                0x00f0
+#define DRA7XX_CM_DIV_M2_DPLL_ABE                       DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00f0)
+#define DRA7XX_CM_DIV_M3_DPLL_ABE_OFFSET                0x00f4
+#define DRA7XX_CM_DIV_M3_DPLL_ABE                       DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00f4)
+#define DRA7XX_CM_SSC_DELTAMSTEP_DPLL_ABE_OFFSET        0x0108
+#define DRA7XX_CM_SSC_MODFREQDIV_DPLL_ABE_OFFSET        0x010c
+#define DRA7XX_CM_CLKMODE_DPLL_DDR_OFFSET               0x0110
+#define DRA7XX_CM_CLKMODE_DPLL_DDR                      DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0110)
+#define DRA7XX_CM_IDLEST_DPLL_DDR_OFFSET                0x0114
+#define DRA7XX_CM_IDLEST_DPLL_DDR                       DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0114)
+#define DRA7XX_CM_AUTOIDLE_DPLL_DDR_OFFSET              0x0118
+#define DRA7XX_CM_AUTOIDLE_DPLL_DDR                     DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0118)
+#define DRA7XX_CM_CLKSEL_DPLL_DDR_OFFSET                0x011c
+#define DRA7XX_CM_CLKSEL_DPLL_DDR                       DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x011c)
+#define DRA7XX_CM_DIV_M2_DPLL_DDR_OFFSET                0x0120
+#define DRA7XX_CM_DIV_M2_DPLL_DDR                       DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0120)
+#define DRA7XX_CM_DIV_M3_DPLL_DDR_OFFSET                0x0124
+#define DRA7XX_CM_DIV_M3_DPLL_DDR                       DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0124)
+#define DRA7XX_CM_DIV_H11_DPLL_DDR_OFFSET               0x0128
+#define DRA7XX_CM_DIV_H11_DPLL_DDR                      DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0128)
+#define DRA7XX_CM_SSC_DELTAMSTEP_DPLL_DDR_OFFSET        0x012c
+#define DRA7XX_CM_SSC_MODFREQDIV_DPLL_DDR_OFFSET        0x0130
+#define DRA7XX_CM_CLKMODE_DPLL_DSP_OFFSET               0x0134
+#define DRA7XX_CM_CLKMODE_DPLL_DSP                      DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0134)
+#define DRA7XX_CM_IDLEST_DPLL_DSP_OFFSET                0x0138
+#define DRA7XX_CM_IDLEST_DPLL_DSP                       DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0138)
+#define DRA7XX_CM_AUTOIDLE_DPLL_DSP_OFFSET              0x013c
+#define DRA7XX_CM_AUTOIDLE_DPLL_DSP                     DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x013c)
+#define DRA7XX_CM_CLKSEL_DPLL_DSP_OFFSET                0x0140
+#define DRA7XX_CM_CLKSEL_DPLL_DSP                       DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0140)
+#define DRA7XX_CM_DIV_M2_DPLL_DSP_OFFSET                0x0144
+#define DRA7XX_CM_DIV_M2_DPLL_DSP                       DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0144)
+#define DRA7XX_CM_DIV_M3_DPLL_DSP_OFFSET                0x0148
+#define DRA7XX_CM_DIV_M3_DPLL_DSP                       DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0148)
+#define DRA7XX_CM_SSC_DELTAMSTEP_DPLL_DSP_OFFSET        0x014c
+#define DRA7XX_CM_SSC_MODFREQDIV_DPLL_DSP_OFFSET        0x0150
+#define DRA7XX_CM_BYPCLK_DPLL_DSP_OFFSET                0x0154
+#define DRA7XX_CM_BYPCLK_DPLL_DSP                       DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0154)
+#define DRA7XX_CM_SHADOW_FREQ_CONFIG1_OFFSET            0x0160
+#define DRA7XX_CM_SHADOW_FREQ_CONFIG2_OFFSET            0x0164
+#define DRA7XX_CM_DYN_DEP_PRESCAL_OFFSET                0x0170
+#define DRA7XX_CM_RESTORE_ST_OFFSET                     0x0180
+#define DRA7XX_CM_CLKMODE_DPLL_EVE_OFFSET               0x0184
+#define DRA7XX_CM_CLKMODE_DPLL_EVE                      DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0184)
+#define DRA7XX_CM_IDLEST_DPLL_EVE_OFFSET                0x0188
+#define DRA7XX_CM_IDLEST_DPLL_EVE                       DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0188)
+#define DRA7XX_CM_AUTOIDLE_DPLL_EVE_OFFSET              0x018c
+#define DRA7XX_CM_AUTOIDLE_DPLL_EVE                     DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x018c)
+#define DRA7XX_CM_CLKSEL_DPLL_EVE_OFFSET                0x0190
+#define DRA7XX_CM_CLKSEL_DPLL_EVE                       DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0190)
+#define DRA7XX_CM_DIV_M2_DPLL_EVE_OFFSET                0x0194
+#define DRA7XX_CM_DIV_M2_DPLL_EVE                       DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0194)
+#define DRA7XX_CM_DIV_M3_DPLL_EVE_OFFSET                0x0198
+#define DRA7XX_CM_DIV_M3_DPLL_EVE                       DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0198)
+#define DRA7XX_CM_SSC_DELTAMSTEP_DPLL_EVE_OFFSET        0x019c
+#define DRA7XX_CM_SSC_MODFREQDIV_DPLL_EVE_OFFSET        0x01a0
+#define DRA7XX_CM_BYPCLK_DPLL_EVE_OFFSET                0x01a4
+#define DRA7XX_CM_BYPCLK_DPLL_EVE                       DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01a4)
+#define DRA7XX_CM_CLKMODE_DPLL_GMAC_OFFSET              0x01a8
+#define DRA7XX_CM_CLKMODE_DPLL_GMAC                     DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01a8)
+#define DRA7XX_CM_IDLEST_DPLL_GMAC_OFFSET               0x01ac
+#define DRA7XX_CM_IDLEST_DPLL_GMAC                      DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01ac)
+#define DRA7XX_CM_AUTOIDLE_DPLL_GMAC_OFFSET             0x01b0
+#define DRA7XX_CM_AUTOIDLE_DPLL_GMAC                    DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01b0)
+#define DRA7XX_CM_CLKSEL_DPLL_GMAC_OFFSET               0x01b4
+#define DRA7XX_CM_CLKSEL_DPLL_GMAC                      DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01b4)
+#define DRA7XX_CM_DIV_M2_DPLL_GMAC_OFFSET               0x01b8
+#define DRA7XX_CM_DIV_M2_DPLL_GMAC                      DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01b8)
+#define DRA7XX_CM_DIV_M3_DPLL_GMAC_OFFSET               0x01bc
+#define DRA7XX_CM_DIV_M3_DPLL_GMAC                      DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01bc)
+#define DRA7XX_CM_DIV_H11_DPLL_GMAC_OFFSET              0x01c0
+#define DRA7XX_CM_DIV_H11_DPLL_GMAC                     DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01c0)
+#define DRA7XX_CM_DIV_H12_DPLL_GMAC_OFFSET              0x01c4
+#define DRA7XX_CM_DIV_H12_DPLL_GMAC                     DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01c4)
+#define DRA7XX_CM_DIV_H13_DPLL_GMAC_OFFSET              0x01c8
+#define DRA7XX_CM_DIV_H13_DPLL_GMAC                     DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01c8)
+#define DRA7XX_CM_DIV_H14_DPLL_GMAC_OFFSET              0x01cc
+#define DRA7XX_CM_DIV_H14_DPLL_GMAC                     DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01cc)
+#define DRA7XX_CM_SSC_DELTAMSTEP_DPLL_GMAC_OFFSET       0x01d0
+#define DRA7XX_CM_SSC_MODFREQDIV_DPLL_GMAC_OFFSET       0x01d4
+#define DRA7XX_CM_CLKMODE_DPLL_GPU_OFFSET               0x01d8
+#define DRA7XX_CM_CLKMODE_DPLL_GPU                      DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01d8)
+#define DRA7XX_CM_IDLEST_DPLL_GPU_OFFSET                0x01dc
+#define DRA7XX_CM_IDLEST_DPLL_GPU                       DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01dc)
+#define DRA7XX_CM_AUTOIDLE_DPLL_GPU_OFFSET              0x01e0
+#define DRA7XX_CM_AUTOIDLE_DPLL_GPU                     DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01e0)
+#define DRA7XX_CM_CLKSEL_DPLL_GPU_OFFSET                0x01e4
+#define DRA7XX_CM_CLKSEL_DPLL_GPU                       DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01e4)
+#define DRA7XX_CM_DIV_M2_DPLL_GPU_OFFSET                0x01e8
+#define DRA7XX_CM_DIV_M2_DPLL_GPU                       DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01e8)
+#define DRA7XX_CM_DIV_M3_DPLL_GPU_OFFSET                0x01ec
+#define DRA7XX_CM_DIV_M3_DPLL_GPU                       DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01ec)
+#define DRA7XX_CM_SSC_DELTAMSTEP_DPLL_GPU_OFFSET        0x01f0
+#define DRA7XX_CM_SSC_MODFREQDIV_DPLL_GPU_OFFSET        0x01f4
+
+/* CM_CORE_AON.MPU_CM_CORE_AON register offsets */
+#define DRA7XX_CM_MPU_CLKSTCTRL_OFFSET                  0x0000
+#define DRA7XX_CM_MPU_STATICDEP_OFFSET                  0x0004
+#define DRA7XX_CM_MPU_DYNAMICDEP_OFFSET                 0x0008
+#define DRA7XX_CM_MPU_MPU_CLKCTRL_OFFSET                0x0020
+#define DRA7XX_CM_MPU_MPU_CLKCTRL                       DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_MPU_INST, 0x0020)
+#define DRA7XX_CM_MPU_MPU_MPU_DBG_CLKCTRL_OFFSET        0x0028
+#define DRA7XX_CM_MPU_MPU_MPU_DBG_CLKCTRL               DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_MPU_INST, 0x0028)
+
+/* CM_CORE_AON.DSP1_CM_CORE_AON register offsets */
+#define DRA7XX_CM_DSP1_CLKSTCTRL_OFFSET                 0x0000
+#define DRA7XX_CM_DSP1_STATICDEP_OFFSET                 0x0004
+#define DRA7XX_CM_DSP1_DYNAMICDEP_OFFSET                0x0008
+#define DRA7XX_CM_DSP1_DSP1_CLKCTRL_OFFSET              0x0020
+#define DRA7XX_CM_DSP1_DSP1_CLKCTRL                     DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_DSP1_INST, 0x0020)
+
+/* CM_CORE_AON.IPU_CM_CORE_AON register offsets */
+#define DRA7XX_CM_IPU1_CLKSTCTRL_OFFSET                 0x0000
+#define DRA7XX_CM_IPU1_STATICDEP_OFFSET                 0x0004
+#define DRA7XX_CM_IPU1_DYNAMICDEP_OFFSET                0x0008
+#define DRA7XX_CM_IPU1_IPU1_CLKCTRL_OFFSET              0x0020
+#define DRA7XX_CM_IPU1_IPU1_CLKCTRL                     DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_IPU_INST, 0x0020)
+#define DRA7XX_CM_IPU_CLKSTCTRL_OFFSET                  0x0040
+#define DRA7XX_CM_IPU_MCASP1_CLKCTRL_OFFSET             0x0050
+#define DRA7XX_CM_IPU_MCASP1_CLKCTRL                    DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_IPU_INST, 0x0050)
+#define DRA7XX_CM_IPU_TIMER5_CLKCTRL_OFFSET             0x0058
+#define DRA7XX_CM_IPU_TIMER5_CLKCTRL                    DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_IPU_INST, 0x0058)
+#define DRA7XX_CM_IPU_TIMER6_CLKCTRL_OFFSET             0x0060
+#define DRA7XX_CM_IPU_TIMER6_CLKCTRL                    DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_IPU_INST, 0x0060)
+#define DRA7XX_CM_IPU_TIMER7_CLKCTRL_OFFSET             0x0068
+#define DRA7XX_CM_IPU_TIMER7_CLKCTRL                    DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_IPU_INST, 0x0068)
+#define DRA7XX_CM_IPU_TIMER8_CLKCTRL_OFFSET             0x0070
+#define DRA7XX_CM_IPU_TIMER8_CLKCTRL                    DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_IPU_INST, 0x0070)
+#define DRA7XX_CM_IPU_I2C5_CLKCTRL_OFFSET               0x0078
+#define DRA7XX_CM_IPU_I2C5_CLKCTRL                      DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_IPU_INST, 0x0078)
+#define DRA7XX_CM_IPU_UART6_CLKCTRL_OFFSET              0x0080
+#define DRA7XX_CM_IPU_UART6_CLKCTRL                     DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_IPU_INST, 0x0080)
+
+/* CM_CORE_AON.DSP2_CM_CORE_AON register offsets */
+#define DRA7XX_CM_DSP2_CLKSTCTRL_OFFSET                 0x0000
+#define DRA7XX_CM_DSP2_STATICDEP_OFFSET                 0x0004
+#define DRA7XX_CM_DSP2_DYNAMICDEP_OFFSET                0x0008
+#define DRA7XX_CM_DSP2_DSP2_CLKCTRL_OFFSET              0x0020
+#define DRA7XX_CM_DSP2_DSP2_CLKCTRL                     DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_DSP2_INST, 0x0020)
+
+/* CM_CORE_AON.EVE1_CM_CORE_AON register offsets */
+#define DRA7XX_CM_EVE1_CLKSTCTRL_OFFSET                 0x0000
+#define DRA7XX_CM_EVE1_STATICDEP_OFFSET                 0x0004
+#define DRA7XX_CM_EVE1_EVE1_CLKCTRL_OFFSET              0x0020
+#define DRA7XX_CM_EVE1_EVE1_CLKCTRL                     DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_EVE1_INST, 0x0020)
+
+/* CM_CORE_AON.EVE2_CM_CORE_AON register offsets */
+#define DRA7XX_CM_EVE2_CLKSTCTRL_OFFSET                 0x0000
+#define DRA7XX_CM_EVE2_STATICDEP_OFFSET                 0x0004
+#define DRA7XX_CM_EVE2_EVE2_CLKCTRL_OFFSET              0x0020
+#define DRA7XX_CM_EVE2_EVE2_CLKCTRL                     DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_EVE2_INST, 0x0020)
+
+/* CM_CORE_AON.EVE3_CM_CORE_AON register offsets */
+#define DRA7XX_CM_EVE3_CLKSTCTRL_OFFSET                 0x0000
+#define DRA7XX_CM_EVE3_STATICDEP_OFFSET                 0x0004
+#define DRA7XX_CM_EVE3_EVE3_CLKCTRL_OFFSET              0x0020
+#define DRA7XX_CM_EVE3_EVE3_CLKCTRL                     DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_EVE3_INST, 0x0020)
+
+/* CM_CORE_AON.EVE4_CM_CORE_AON register offsets */
+#define DRA7XX_CM_EVE4_CLKSTCTRL_OFFSET                 0x0000
+#define DRA7XX_CM_EVE4_STATICDEP_OFFSET                 0x0004
+#define DRA7XX_CM_EVE4_EVE4_CLKCTRL_OFFSET              0x0020
+#define DRA7XX_CM_EVE4_EVE4_CLKCTRL                     DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_EVE4_INST, 0x0020)
+
+/* CM_CORE_AON.RTC_CM_CORE_AON register offsets */
+#define DRA7XX_CM_RTC_CLKSTCTRL_OFFSET                  0x0000
+#define DRA7XX_CM_RTC_RTCSS_CLKCTRL_OFFSET              0x0004
+#define DRA7XX_CM_RTC_RTCSS_CLKCTRL                     DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_RTC_INST, 0x0004)
+
+/* CM_CORE_AON.VPE_CM_CORE_AON register offsets */
+#define DRA7XX_CM_VPE_CLKSTCTRL_OFFSET                  0x0000
+#define DRA7XX_CM_VPE_VPE_CLKCTRL_OFFSET                0x0004
+#define DRA7XX_CM_VPE_VPE_CLKCTRL                       DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_VPE_INST, 0x0004)
+#define DRA7XX_CM_VPE_STATICDEP_OFFSET                  0x0008
+
+#endif
diff --git a/arch/arm/mach-omap2/cm2_7xx.h b/arch/arm/mach-omap2/cm2_7xx.h
new file mode 100644
index 000000000000..9ad7594e7622
--- /dev/null
+++ b/arch/arm/mach-omap2/cm2_7xx.h
@@ -0,0 +1,513 @@
+/*
+ * DRA7xx CM2 instance offset macros
+ *
+ * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
+ *
+ * Generated by code originally written by:
+ * Paul Walmsley (paul@pwsan.com)
+ * Rajendra Nayak (rnayak@ti.com)
+ * Benoit Cousson (b-cousson@ti.com)
+ *
+ * This file is automatically generated from the OMAP hardware databases.
+ * We respectfully ask that any modifications to this file be coordinated
+ * with the public linux-omap@vger.kernel.org mailing list and the
+ * authors above to ensure that the autogeneration scripts are kept
+ * up-to-date with the file contents.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ARCH_ARM_MACH_OMAP2_CM2_7XX_H
+#define __ARCH_ARM_MACH_OMAP2_CM2_7XX_H
+
+#include "cm_44xx_54xx.h"
+
+/* CM2 base address */
+#define DRA7XX_CM_CORE_BASE             0x4a008000
+
+#define DRA7XX_CM_CORE_REGADDR(inst, reg)                               \
+        OMAP2_L4_IO_ADDRESS(DRA7XX_CM_CORE_BASE + (inst) + (reg))
+
+/* CM_CORE instances */
+#define DRA7XX_CM_CORE_OCP_SOCKET_INST  0x0000
+#define DRA7XX_CM_CORE_CKGEN_INST       0x0104
+#define DRA7XX_CM_CORE_COREAON_INST     0x0600
+#define DRA7XX_CM_CORE_CORE_INST        0x0700
+#define DRA7XX_CM_CORE_IVA_INST         0x0f00
+#define DRA7XX_CM_CORE_CAM_INST         0x1000
+#define DRA7XX_CM_CORE_DSS_INST         0x1100
+#define DRA7XX_CM_CORE_GPU_INST         0x1200
+#define DRA7XX_CM_CORE_L3INIT_INST      0x1300
+#define DRA7XX_CM_CORE_CUSTEFUSE_INST   0x1600
+#define DRA7XX_CM_CORE_L4PER_INST       0x1700
+#define DRA7XX_CM_CORE_RESTORE_INST     0x1e18
+
+/* CM_CORE clockdomain register offsets (from instance start) */
+#define DRA7XX_CM_CORE_COREAON_COREAON_CDOFFS           0x0000
+#define DRA7XX_CM_CORE_CORE_L3MAIN1_CDOFFS              0x0000
+#define DRA7XX_CM_CORE_CORE_IPU2_CDOFFS                 0x0200
+#define DRA7XX_CM_CORE_CORE_DMA_CDOFFS                  0x0300
+#define DRA7XX_CM_CORE_CORE_EMIF_CDOFFS                 0x0400
+#define DRA7XX_CM_CORE_CORE_ATL_CDOFFS                  0x0520
+#define DRA7XX_CM_CORE_CORE_L4CFG_CDOFFS                0x0600
+#define DRA7XX_CM_CORE_CORE_L3INSTR_CDOFFS              0x0700
+#define DRA7XX_CM_CORE_IVA_IVA_CDOFFS                   0x0000
+#define DRA7XX_CM_CORE_CAM_CAM_CDOFFS                   0x0000
+#define DRA7XX_CM_CORE_DSS_DSS_CDOFFS                   0x0000
+#define DRA7XX_CM_CORE_GPU_GPU_CDOFFS                   0x0000
+#define DRA7XX_CM_CORE_L3INIT_L3INIT_CDOFFS             0x0000
+#define DRA7XX_CM_CORE_L3INIT_PCIE_CDOFFS               0x00a0
+#define DRA7XX_CM_CORE_L3INIT_GMAC_CDOFFS               0x00c0
+#define DRA7XX_CM_CORE_CUSTEFUSE_CUSTEFUSE_CDOFFS       0x0000
+#define DRA7XX_CM_CORE_L4PER_L4PER_CDOFFS               0x0000
+#define DRA7XX_CM_CORE_L4PER_L4SEC_CDOFFS               0x0180
+#define DRA7XX_CM_CORE_L4PER_L4PER2_CDOFFS              0x01fc
+#define DRA7XX_CM_CORE_L4PER_L4PER3_CDOFFS              0x0210
+
+/* CM_CORE */
+
+/* CM_CORE.OCP_SOCKET_CM_CORE register offsets */
+#define DRA7XX_REVISION_CM_CORE_OFFSET                          0x0000
+#define DRA7XX_CM_CM_CORE_PROFILING_CLKCTRL_OFFSET              0x0040
+#define DRA7XX_CM_CM_CORE_PROFILING_CLKCTRL                     DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_OCP_SOCKET_INST, 0x0040)
+#define DRA7XX_CM_CORE_DEBUG_CFG_OFFSET                         0x00f0
+
+/* CM_CORE.CKGEN_CM_CORE register offsets */
+#define DRA7XX_CM_CLKSEL_USB_60MHZ_OFFSET                       0x0000
+#define DRA7XX_CM_CLKSEL_USB_60MHZ                              DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0000)
+#define DRA7XX_CM_CLKMODE_DPLL_PER_OFFSET                       0x003c
+#define DRA7XX_CM_CLKMODE_DPLL_PER                              DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x003c)
+#define DRA7XX_CM_IDLEST_DPLL_PER_OFFSET                        0x0040
+#define DRA7XX_CM_IDLEST_DPLL_PER                               DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0040)
+#define DRA7XX_CM_AUTOIDLE_DPLL_PER_OFFSET                      0x0044
+#define DRA7XX_CM_AUTOIDLE_DPLL_PER                             DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0044)
+#define DRA7XX_CM_CLKSEL_DPLL_PER_OFFSET                        0x0048
+#define DRA7XX_CM_CLKSEL_DPLL_PER                               DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0048)
+#define DRA7XX_CM_DIV_M2_DPLL_PER_OFFSET                        0x004c
+#define DRA7XX_CM_DIV_M2_DPLL_PER                               DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x004c)
+#define DRA7XX_CM_DIV_M3_DPLL_PER_OFFSET                        0x0050
+#define DRA7XX_CM_DIV_M3_DPLL_PER                               DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0050)
+#define DRA7XX_CM_DIV_H11_DPLL_PER_OFFSET                       0x0054
+#define DRA7XX_CM_DIV_H11_DPLL_PER                              DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0054)
+#define DRA7XX_CM_DIV_H12_DPLL_PER_OFFSET                       0x0058
+#define DRA7XX_CM_DIV_H12_DPLL_PER                              DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0058)
+#define DRA7XX_CM_DIV_H13_DPLL_PER_OFFSET                       0x005c
+#define DRA7XX_CM_DIV_H13_DPLL_PER                              DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x005c)
+#define DRA7XX_CM_DIV_H14_DPLL_PER_OFFSET                       0x0060
+#define DRA7XX_CM_DIV_H14_DPLL_PER                              DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0060)
+#define DRA7XX_CM_SSC_DELTAMSTEP_DPLL_PER_OFFSET                0x0064
+#define DRA7XX_CM_SSC_MODFREQDIV_DPLL_PER_OFFSET                0x0068
+#define DRA7XX_CM_CLKMODE_DPLL_USB_OFFSET                       0x007c
+#define DRA7XX_CM_CLKMODE_DPLL_USB                              DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x007c)
+#define DRA7XX_CM_IDLEST_DPLL_USB_OFFSET                        0x0080
+#define DRA7XX_CM_IDLEST_DPLL_USB                               DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0080)
+#define DRA7XX_CM_AUTOIDLE_DPLL_USB_OFFSET                      0x0084
+#define DRA7XX_CM_AUTOIDLE_DPLL_USB                             DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0084)
+#define DRA7XX_CM_CLKSEL_DPLL_USB_OFFSET                        0x0088
+#define DRA7XX_CM_CLKSEL_DPLL_USB                               DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0088)
+#define DRA7XX_CM_DIV_M2_DPLL_USB_OFFSET                        0x008c
+#define DRA7XX_CM_DIV_M2_DPLL_USB                               DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x008c)
+#define DRA7XX_CM_SSC_DELTAMSTEP_DPLL_USB_OFFSET                0x00a4
+#define DRA7XX_CM_SSC_MODFREQDIV_DPLL_USB_OFFSET                0x00a8
+#define DRA7XX_CM_CLKDCOLDO_DPLL_USB_OFFSET                     0x00b0
+#define DRA7XX_CM_CLKDCOLDO_DPLL_USB                            DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x00b0)
+#define DRA7XX_CM_CLKMODE_DPLL_PCIE_REF_OFFSET                  0x00fc
+#define DRA7XX_CM_CLKMODE_DPLL_PCIE_REF                         DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x00fc)
+#define DRA7XX_CM_IDLEST_DPLL_PCIE_REF_OFFSET                   0x0100
+#define DRA7XX_CM_IDLEST_DPLL_PCIE_REF                          DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0100)
+#define DRA7XX_CM_AUTOIDLE_DPLL_PCIE_REF_OFFSET                 0x0104
+#define DRA7XX_CM_AUTOIDLE_DPLL_PCIE_REF                        DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0104)
+#define DRA7XX_CM_CLKSEL_DPLL_PCIE_REF_OFFSET                   0x0108
+#define DRA7XX_CM_CLKSEL_DPLL_PCIE_REF                          DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0108)
+#define DRA7XX_CM_DIV_M2_DPLL_PCIE_REF_OFFSET                   0x010c
+#define DRA7XX_CM_DIV_M2_DPLL_PCIE_REF                          DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x010c)
+#define DRA7XX_CM_SSC_DELTAMSTEP_DPLL_PCIE_REF_OFFSET           0x0110
+#define DRA7XX_CM_SSC_MODFREQDIV_DPLL_PCIE_REF_OFFSET           0x0114
+#define DRA7XX_CM_CLKMODE_APLL_PCIE_OFFSET                      0x0118
+#define DRA7XX_CM_CLKMODE_APLL_PCIE                             DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0118)
+#define DRA7XX_CM_IDLEST_APLL_PCIE_OFFSET                       0x011c
+#define DRA7XX_CM_IDLEST_APLL_PCIE                              DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x011c)
+#define DRA7XX_CM_DIV_M2_APLL_PCIE_OFFSET                       0x0120
+#define DRA7XX_CM_DIV_M2_APLL_PCIE                              DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0120)
+#define DRA7XX_CM_CLKVCOLDO_APLL_PCIE_OFFSET                    0x0124
+#define DRA7XX_CM_CLKVCOLDO_APLL_PCIE                           DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0124)
+
+/* CM_CORE.COREAON_CM_CORE register offsets */
+#define DRA7XX_CM_COREAON_CLKSTCTRL_OFFSET                      0x0000
+#define DRA7XX_CM_COREAON_SMARTREFLEX_MPU_CLKCTRL_OFFSET        0x0028
+#define DRA7XX_CM_COREAON_SMARTREFLEX_MPU_CLKCTRL               DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x0028)
+#define DRA7XX_CM_COREAON_SMARTREFLEX_CORE_CLKCTRL_OFFSET       0x0038
+#define DRA7XX_CM_COREAON_SMARTREFLEX_CORE_CLKCTRL              DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x0038)
+#define DRA7XX_CM_COREAON_USB_PHY1_CORE_CLKCTRL_OFFSET          0x0040
+#define DRA7XX_CM_COREAON_USB_PHY1_CORE_CLKCTRL                 DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x0040)
+#define DRA7XX_CM_COREAON_IO_SRCOMP_CLKCTRL_OFFSET              0x0050
+#define DRA7XX_CM_COREAON_IO_SRCOMP_CLKCTRL                     DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x0050)
+#define DRA7XX_CM_COREAON_SMARTREFLEX_GPU_CLKCTRL_OFFSET        0x0058
+#define DRA7XX_CM_COREAON_SMARTREFLEX_GPU_CLKCTRL               DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x0058)
+#define DRA7XX_CM_COREAON_SMARTREFLEX_DSPEVE_CLKCTRL_OFFSET     0x0068
+#define DRA7XX_CM_COREAON_SMARTREFLEX_DSPEVE_CLKCTRL            DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x0068)
+#define DRA7XX_CM_COREAON_SMARTREFLEX_IVAHD_CLKCTRL_OFFSET      0x0078
+#define DRA7XX_CM_COREAON_SMARTREFLEX_IVAHD_CLKCTRL             DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x0078)
+#define DRA7XX_CM_COREAON_USB_PHY2_CORE_CLKCTRL_OFFSET          0x0088
+#define DRA7XX_CM_COREAON_USB_PHY2_CORE_CLKCTRL                 DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x0088)
+#define DRA7XX_CM_COREAON_USB_PHY3_CORE_CLKCTRL_OFFSET          0x0098
+#define DRA7XX_CM_COREAON_USB_PHY3_CORE_CLKCTRL                 DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x0098)
+#define DRA7XX_CM_COREAON_DUMMY_MODULE1_CLKCTRL_OFFSET          0x00a0
+#define DRA7XX_CM_COREAON_DUMMY_MODULE1_CLKCTRL                 DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x00a0)
+#define DRA7XX_CM_COREAON_DUMMY_MODULE2_CLKCTRL_OFFSET          0x00b0
+#define DRA7XX_CM_COREAON_DUMMY_MODULE2_CLKCTRL                 DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x00b0)
+#define DRA7XX_CM_COREAON_DUMMY_MODULE3_CLKCTRL_OFFSET          0x00c0
+#define DRA7XX_CM_COREAON_DUMMY_MODULE3_CLKCTRL                 DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x00c0)
+#define DRA7XX_CM_COREAON_DUMMY_MODULE4_CLKCTRL_OFFSET          0x00d0
+#define DRA7XX_CM_COREAON_DUMMY_MODULE4_CLKCTRL                 DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x00d0)
+
+/* CM_CORE.CORE_CM_CORE register offsets */
+#define DRA7XX_CM_L3MAIN1_CLKSTCTRL_OFFSET                      0x0000
+#define DRA7XX_CM_L3MAIN1_DYNAMICDEP_OFFSET                     0x0008
+#define DRA7XX_CM_L3MAIN1_L3_MAIN_1_CLKCTRL_OFFSET              0x0020
+#define DRA7XX_CM_L3MAIN1_L3_MAIN_1_CLKCTRL                     DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0020)
+#define DRA7XX_CM_L3MAIN1_GPMC_CLKCTRL_OFFSET                   0x0028
+#define DRA7XX_CM_L3MAIN1_GPMC_CLKCTRL                          DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0028)
+#define DRA7XX_CM_L3MAIN1_MMU_EDMA_CLKCTRL_OFFSET               0x0030
+#define DRA7XX_CM_L3MAIN1_MMU_EDMA_CLKCTRL                      DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0030)
+#define DRA7XX_CM_L3MAIN1_OCMC_RAM1_CLKCTRL_OFFSET              0x0050
+#define DRA7XX_CM_L3MAIN1_OCMC_RAM1_CLKCTRL                     DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0050)
+#define DRA7XX_CM_L3MAIN1_OCMC_RAM2_CLKCTRL_OFFSET              0x0058
+#define DRA7XX_CM_L3MAIN1_OCMC_RAM2_CLKCTRL                     DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0058)
+#define DRA7XX_CM_L3MAIN1_OCMC_RAM3_CLKCTRL_OFFSET              0x0060
+#define DRA7XX_CM_L3MAIN1_OCMC_RAM3_CLKCTRL                     DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0060)
+#define DRA7XX_CM_L3MAIN1_OCMC_ROM_CLKCTRL_OFFSET               0x0068
+#define DRA7XX_CM_L3MAIN1_OCMC_ROM_CLKCTRL                      DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0068)
+#define DRA7XX_CM_L3MAIN1_TPCC_CLKCTRL_OFFSET                   0x0070
+#define DRA7XX_CM_L3MAIN1_TPCC_CLKCTRL                          DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0070)
+#define DRA7XX_CM_L3MAIN1_TPTC1_CLKCTRL_OFFSET                  0x0078
+#define DRA7XX_CM_L3MAIN1_TPTC1_CLKCTRL                         DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0078)
+#define DRA7XX_CM_L3MAIN1_TPTC2_CLKCTRL_OFFSET                  0x0080
+#define DRA7XX_CM_L3MAIN1_TPTC2_CLKCTRL                         DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0080)
+#define DRA7XX_CM_L3MAIN1_VCP1_CLKCTRL_OFFSET                   0x0088
+#define DRA7XX_CM_L3MAIN1_VCP1_CLKCTRL                          DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0088)
+#define DRA7XX_CM_L3MAIN1_VCP2_CLKCTRL_OFFSET                   0x0090
+#define DRA7XX_CM_L3MAIN1_VCP2_CLKCTRL                          DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0090)
+#define DRA7XX_CM_L3MAIN1_SPARE_CME_CLKCTRL_OFFSET              0x0098
+#define DRA7XX_CM_L3MAIN1_SPARE_CME_CLKCTRL                     DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0098)
+#define DRA7XX_CM_L3MAIN1_SPARE_HDMI_CLKCTRL_OFFSET             0x00a0
+#define DRA7XX_CM_L3MAIN1_SPARE_HDMI_CLKCTRL                    DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x00a0)
+#define DRA7XX_CM_L3MAIN1_SPARE_ICM_CLKCTRL_OFFSET              0x00a8
+#define DRA7XX_CM_L3MAIN1_SPARE_ICM_CLKCTRL                     DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x00a8)
+#define DRA7XX_CM_L3MAIN1_SPARE_IVA2_CLKCTRL_OFFSET             0x00b0
+#define DRA7XX_CM_L3MAIN1_SPARE_IVA2_CLKCTRL                    DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x00b0)
+#define DRA7XX_CM_L3MAIN1_SPARE_SATA2_CLKCTRL_OFFSET            0x00b8
+#define DRA7XX_CM_L3MAIN1_SPARE_SATA2_CLKCTRL                   DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x00b8)
+#define DRA7XX_CM_L3MAIN1_SPARE_UNKNOWN4_CLKCTRL_OFFSET         0x00c0
+#define DRA7XX_CM_L3MAIN1_SPARE_UNKNOWN4_CLKCTRL                DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x00c0)
+#define DRA7XX_CM_L3MAIN1_SPARE_UNKNOWN5_CLKCTRL_OFFSET         0x00c8
+#define DRA7XX_CM_L3MAIN1_SPARE_UNKNOWN5_CLKCTRL                DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x00c8)
+#define DRA7XX_CM_L3MAIN1_SPARE_UNKNOWN6_CLKCTRL_OFFSET         0x00d0
+#define DRA7XX_CM_L3MAIN1_SPARE_UNKNOWN6_CLKCTRL                DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x00d0)
+#define DRA7XX_CM_L3MAIN1_SPARE_VIDEOPLL1_CLKCTRL_OFFSET        0x00d8
+#define DRA7XX_CM_L3MAIN1_SPARE_VIDEOPLL1_CLKCTRL               DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x00d8)
+#define DRA7XX_CM_L3MAIN1_SPARE_VIDEOPLL2_CLKCTRL_OFFSET        0x00f0
+#define DRA7XX_CM_L3MAIN1_SPARE_VIDEOPLL2_CLKCTRL               DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x00f0)
+#define DRA7XX_CM_L3MAIN1_SPARE_VIDEOPLL3_CLKCTRL_OFFSET        0x00f8
+#define DRA7XX_CM_L3MAIN1_SPARE_VIDEOPLL3_CLKCTRL               DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x00f8)
+#define DRA7XX_CM_IPU2_CLKSTCTRL_OFFSET                         0x0200
+#define DRA7XX_CM_IPU2_STATICDEP_OFFSET                         0x0204
+#define DRA7XX_CM_IPU2_DYNAMICDEP_OFFSET                        0x0208
+#define DRA7XX_CM_IPU2_IPU2_CLKCTRL_OFFSET                      0x0220
+#define DRA7XX_CM_IPU2_IPU2_CLKCTRL                             DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0220)
+#define DRA7XX_CM_DMA_CLKSTCTRL_OFFSET                          0x0300
+#define DRA7XX_CM_DMA_STATICDEP_OFFSET                          0x0304
+#define DRA7XX_CM_DMA_DYNAMICDEP_OFFSET                         0x0308
+#define DRA7XX_CM_DMA_DMA_SYSTEM_CLKCTRL_OFFSET                 0x0320
+#define DRA7XX_CM_DMA_DMA_SYSTEM_CLKCTRL                        DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0320)
+#define DRA7XX_CM_EMIF_CLKSTCTRL_OFFSET                         0x0400
+#define DRA7XX_CM_EMIF_DMM_CLKCTRL_OFFSET                       0x0420
+#define DRA7XX_CM_EMIF_DMM_CLKCTRL                              DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0420)
+#define DRA7XX_CM_EMIF_EMIF_OCP_FW_CLKCTRL_OFFSET               0x0428
+#define DRA7XX_CM_EMIF_EMIF_OCP_FW_CLKCTRL                      DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0428)
+#define DRA7XX_CM_EMIF_EMIF1_CLKCTRL_OFFSET                     0x0430
+#define DRA7XX_CM_EMIF_EMIF1_CLKCTRL                            DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0430)
+#define DRA7XX_CM_EMIF_EMIF2_CLKCTRL_OFFSET                     0x0438
+#define DRA7XX_CM_EMIF_EMIF2_CLKCTRL                            DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0438)
+#define DRA7XX_CM_EMIF_EMIF_DLL_CLKCTRL_OFFSET                  0x0440
+#define DRA7XX_CM_EMIF_EMIF_DLL_CLKCTRL                         DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0440)
+#define DRA7XX_CM_ATL_ATL_CLKCTRL_OFFSET                        0x0500
+#define DRA7XX_CM_ATL_ATL_CLKCTRL                               DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0500)
+#define DRA7XX_CM_ATL_CLKSTCTRL_OFFSET                          0x0520
+#define DRA7XX_CM_L4CFG_CLKSTCTRL_OFFSET                        0x0600
+#define DRA7XX_CM_L4CFG_DYNAMICDEP_OFFSET                       0x0608
+#define DRA7XX_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET                   0x0620
+#define DRA7XX_CM_L4CFG_L4_CFG_CLKCTRL                          DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0620)
+#define DRA7XX_CM_L4CFG_SPINLOCK_CLKCTRL_OFFSET                 0x0628
+#define DRA7XX_CM_L4CFG_SPINLOCK_CLKCTRL                        DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0628)
+#define DRA7XX_CM_L4CFG_MAILBOX1_CLKCTRL_OFFSET                 0x0630
+#define DRA7XX_CM_L4CFG_MAILBOX1_CLKCTRL                        DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0630)
+#define DRA7XX_CM_L4CFG_SAR_ROM_CLKCTRL_OFFSET                  0x0638
+#define DRA7XX_CM_L4CFG_SAR_ROM_CLKCTRL                         DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0638)
+#define DRA7XX_CM_L4CFG_OCP2SCP2_CLKCTRL_OFFSET                 0x0640
+#define DRA7XX_CM_L4CFG_OCP2SCP2_CLKCTRL                        DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0640)
+#define DRA7XX_CM_L4CFG_MAILBOX2_CLKCTRL_OFFSET                 0x0648
+#define DRA7XX_CM_L4CFG_MAILBOX2_CLKCTRL                        DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0648)
+#define DRA7XX_CM_L4CFG_MAILBOX3_CLKCTRL_OFFSET                 0x0650
+#define DRA7XX_CM_L4CFG_MAILBOX3_CLKCTRL                        DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0650)
+#define DRA7XX_CM_L4CFG_MAILBOX4_CLKCTRL_OFFSET                 0x0658
+#define DRA7XX_CM_L4CFG_MAILBOX4_CLKCTRL                        DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0658)
+#define DRA7XX_CM_L4CFG_MAILBOX5_CLKCTRL_OFFSET                 0x0660
+#define DRA7XX_CM_L4CFG_MAILBOX5_CLKCTRL                        DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0660)
+#define DRA7XX_CM_L4CFG_MAILBOX6_CLKCTRL_OFFSET                 0x0668
+#define DRA7XX_CM_L4CFG_MAILBOX6_CLKCTRL                        DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0668)
+#define DRA7XX_CM_L4CFG_MAILBOX7_CLKCTRL_OFFSET                 0x0670
+#define DRA7XX_CM_L4CFG_MAILBOX7_CLKCTRL                        DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0670)
+#define DRA7XX_CM_L4CFG_MAILBOX8_CLKCTRL_OFFSET                 0x0678
+#define DRA7XX_CM_L4CFG_MAILBOX8_CLKCTRL                        DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0678)
+#define DRA7XX_CM_L4CFG_MAILBOX9_CLKCTRL_OFFSET                 0x0680
+#define DRA7XX_CM_L4CFG_MAILBOX9_CLKCTRL                        DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0680)
+#define DRA7XX_CM_L4CFG_MAILBOX10_CLKCTRL_OFFSET                0x0688
+#define DRA7XX_CM_L4CFG_MAILBOX10_CLKCTRL                       DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0688)
+#define DRA7XX_CM_L4CFG_MAILBOX11_CLKCTRL_OFFSET                0x0690
+#define DRA7XX_CM_L4CFG_MAILBOX11_CLKCTRL                       DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0690)
+#define DRA7XX_CM_L4CFG_MAILBOX12_CLKCTRL_OFFSET                0x0698
+#define DRA7XX_CM_L4CFG_MAILBOX12_CLKCTRL                       DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0698)
+#define DRA7XX_CM_L4CFG_MAILBOX13_CLKCTRL_OFFSET                0x06a0
+#define DRA7XX_CM_L4CFG_MAILBOX13_CLKCTRL                       DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x06a0)
+#define DRA7XX_CM_L4CFG_SPARE_SMARTREFLEX_RTC_CLKCTRL_OFFSET    0x06a8
+#define DRA7XX_CM_L4CFG_SPARE_SMARTREFLEX_RTC_CLKCTRL           DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x06a8)
+#define DRA7XX_CM_L4CFG_SPARE_SMARTREFLEX_SDRAM_CLKCTRL_OFFSET  0x06b0
+#define DRA7XX_CM_L4CFG_SPARE_SMARTREFLEX_SDRAM_CLKCTRL         DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x06b0)
+#define DRA7XX_CM_L4CFG_SPARE_SMARTREFLEX_WKUP_CLKCTRL_OFFSET   0x06b8
+#define DRA7XX_CM_L4CFG_SPARE_SMARTREFLEX_WKUP_CLKCTRL          DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x06b8)
+#define DRA7XX_CM_L4CFG_IO_DELAY_BLOCK_CLKCTRL_OFFSET           0x06c0
+#define DRA7XX_CM_L4CFG_IO_DELAY_BLOCK_CLKCTRL                  DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x06c0)
+#define DRA7XX_CM_L3INSTR_CLKSTCTRL_OFFSET                      0x0700
+#define DRA7XX_CM_L3INSTR_L3_MAIN_2_CLKCTRL_OFFSET              0x0720
+#define DRA7XX_CM_L3INSTR_L3_MAIN_2_CLKCTRL                     DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0720)
+#define DRA7XX_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET               0x0728
+#define DRA7XX_CM_L3INSTR_L3_INSTR_CLKCTRL                      DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0728)
+#define DRA7XX_CM_L3INSTR_OCP_WP_NOC_CLKCTRL_OFFSET             0x0740
+#define DRA7XX_CM_L3INSTR_OCP_WP_NOC_CLKCTRL                    DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0740)
+#define DRA7XX_CM_L3INSTR_DLL_AGING_CLKCTRL_OFFSET              0x0748
+#define DRA7XX_CM_L3INSTR_DLL_AGING_CLKCTRL                     DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0748)
+#define DRA7XX_CM_L3INSTR_CTRL_MODULE_BANDGAP_CLKCTRL_OFFSET    0x0750
+#define DRA7XX_CM_L3INSTR_CTRL_MODULE_BANDGAP_CLKCTRL           DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0750)
+
+/* CM_CORE.IVA_CM_CORE register offsets */
+#define DRA7XX_CM_IVA_CLKSTCTRL_OFFSET                          0x0000
+#define DRA7XX_CM_IVA_STATICDEP_OFFSET                          0x0004
+#define DRA7XX_CM_IVA_DYNAMICDEP_OFFSET                         0x0008
+#define DRA7XX_CM_IVA_IVA_CLKCTRL_OFFSET                        0x0020
+#define DRA7XX_CM_IVA_IVA_CLKCTRL                               DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_IVA_INST, 0x0020)
+#define DRA7XX_CM_IVA_SL2_CLKCTRL_OFFSET                        0x0028
+#define DRA7XX_CM_IVA_SL2_CLKCTRL                               DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_IVA_INST, 0x0028)
+
+/* CM_CORE.CAM_CM_CORE register offsets */
+#define DRA7XX_CM_CAM_CLKSTCTRL_OFFSET                          0x0000
+#define DRA7XX_CM_CAM_STATICDEP_OFFSET                          0x0004
+#define DRA7XX_CM_CAM_VIP1_CLKCTRL_OFFSET                       0x0020
+#define DRA7XX_CM_CAM_VIP1_CLKCTRL                              DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CAM_INST, 0x0020)
+#define DRA7XX_CM_CAM_VIP2_CLKCTRL_OFFSET                       0x0028
+#define DRA7XX_CM_CAM_VIP2_CLKCTRL                              DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CAM_INST, 0x0028)
+#define DRA7XX_CM_CAM_VIP3_CLKCTRL_OFFSET                       0x0030
+#define DRA7XX_CM_CAM_VIP3_CLKCTRL                              DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CAM_INST, 0x0030)
+#define DRA7XX_CM_CAM_LVDSRX_CLKCTRL_OFFSET                     0x0038
+#define DRA7XX_CM_CAM_LVDSRX_CLKCTRL                            DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CAM_INST, 0x0038)
+#define DRA7XX_CM_CAM_CSI1_CLKCTRL_OFFSET                       0x0040
+#define DRA7XX_CM_CAM_CSI1_CLKCTRL                              DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CAM_INST, 0x0040)
+#define DRA7XX_CM_CAM_CSI2_CLKCTRL_OFFSET                       0x0048
+#define DRA7XX_CM_CAM_CSI2_CLKCTRL                              DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CAM_INST, 0x0048)
+
+/* CM_CORE.DSS_CM_CORE register offsets */
+#define DRA7XX_CM_DSS_CLKSTCTRL_OFFSET                          0x0000
+#define DRA7XX_CM_DSS_STATICDEP_OFFSET                          0x0004
+#define DRA7XX_CM_DSS_DYNAMICDEP_OFFSET                         0x0008
+#define DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET                        0x0020
+#define DRA7XX_CM_DSS_DSS_CLKCTRL                               DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_DSS_INST, 0x0020)
+#define DRA7XX_CM_DSS_BB2D_CLKCTRL_OFFSET                       0x0030
+#define DRA7XX_CM_DSS_BB2D_CLKCTRL                              DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_DSS_INST, 0x0030)
+#define DRA7XX_CM_DSS_SDVENC_CLKCTRL_OFFSET                     0x003c
+#define DRA7XX_CM_DSS_SDVENC_CLKCTRL                            DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_DSS_INST, 0x003c)
+
+/* CM_CORE.GPU_CM_CORE register offsets */
+#define DRA7XX_CM_GPU_CLKSTCTRL_OFFSET                          0x0000
+#define DRA7XX_CM_GPU_STATICDEP_OFFSET                          0x0004
+#define DRA7XX_CM_GPU_DYNAMICDEP_OFFSET                         0x0008
+#define DRA7XX_CM_GPU_GPU_CLKCTRL_OFFSET                        0x0020
+#define DRA7XX_CM_GPU_GPU_CLKCTRL                               DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_GPU_INST, 0x0020)
+
+/* CM_CORE.L3INIT_CM_CORE register offsets */
+#define DRA7XX_CM_L3INIT_CLKSTCTRL_OFFSET                       0x0000
+#define DRA7XX_CM_L3INIT_STATICDEP_OFFSET                       0x0004
+#define DRA7XX_CM_L3INIT_DYNAMICDEP_OFFSET                      0x0008
+#define DRA7XX_CM_L3INIT_MMC1_CLKCTRL_OFFSET                    0x0028
+#define DRA7XX_CM_L3INIT_MMC1_CLKCTRL                           DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x0028)
+#define DRA7XX_CM_L3INIT_MMC2_CLKCTRL_OFFSET                    0x0030
+#define DRA7XX_CM_L3INIT_MMC2_CLKCTRL                           DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x0030)
+#define DRA7XX_CM_L3INIT_USB_OTG_SS2_CLKCTRL_OFFSET             0x0040
+#define DRA7XX_CM_L3INIT_USB_OTG_SS2_CLKCTRL                    DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x0040)
+#define DRA7XX_CM_L3INIT_USB_OTG_SS3_CLKCTRL_OFFSET             0x0048
+#define DRA7XX_CM_L3INIT_USB_OTG_SS3_CLKCTRL                    DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x0048)
+#define DRA7XX_CM_L3INIT_USB_OTG_SS4_CLKCTRL_OFFSET             0x0050
+#define DRA7XX_CM_L3INIT_USB_OTG_SS4_CLKCTRL                    DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x0050)
+#define DRA7XX_CM_L3INIT_MLB_SS_CLKCTRL_OFFSET                  0x0058
+#define DRA7XX_CM_L3INIT_MLB_SS_CLKCTRL                         DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x0058)
+#define DRA7XX_CM_L3INIT_IEEE1500_2_OCP_CLKCTRL_OFFSET          0x0078
+#define DRA7XX_CM_L3INIT_IEEE1500_2_OCP_CLKCTRL                 DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x0078)
+#define DRA7XX_CM_L3INIT_SATA_CLKCTRL_OFFSET                    0x0088
+#define DRA7XX_CM_L3INIT_SATA_CLKCTRL                           DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x0088)
+#define DRA7XX_CM_PCIE_CLKSTCTRL_OFFSET                         0x00a0
+#define DRA7XX_CM_PCIE_STATICDEP_OFFSET                         0x00a4
+#define DRA7XX_CM_GMAC_CLKSTCTRL_OFFSET                         0x00c0
+#define DRA7XX_CM_GMAC_STATICDEP_OFFSET                         0x00c4
+#define DRA7XX_CM_GMAC_DYNAMICDEP_OFFSET                        0x00c8
+#define DRA7XX_CM_GMAC_GMAC_CLKCTRL_OFFSET                      0x00d0
+#define DRA7XX_CM_GMAC_GMAC_CLKCTRL                             DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x00d0)
+#define DRA7XX_CM_L3INIT_OCP2SCP1_CLKCTRL_OFFSET                0x00e0
+#define DRA7XX_CM_L3INIT_OCP2SCP1_CLKCTRL                       DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x00e0)
+#define DRA7XX_CM_L3INIT_OCP2SCP3_CLKCTRL_OFFSET                0x00e8
+#define DRA7XX_CM_L3INIT_OCP2SCP3_CLKCTRL                       DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x00e8)
+#define DRA7XX_CM_L3INIT_USB_OTG_SS1_CLKCTRL_OFFSET             0x00f0
+#define DRA7XX_CM_L3INIT_USB_OTG_SS1_CLKCTRL                    DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x00f0)
+
+/* CM_CORE.CUSTEFUSE_CM_CORE register offsets */
+#define DRA7XX_CM_CUSTEFUSE_CLKSTCTRL_OFFSET                    0x0000
+#define DRA7XX_CM_CUSTEFUSE_EFUSE_CTRL_CUST_CLKCTRL_OFFSET      0x0020
+#define DRA7XX_CM_CUSTEFUSE_EFUSE_CTRL_CUST_CLKCTRL             DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CUSTEFUSE_INST, 0x0020)
+
+/* CM_CORE.L4PER_CM_CORE register offsets */
+#define DRA7XX_CM_L4PER_CLKSTCTRL_OFFSET                        0x0000
+#define DRA7XX_CM_L4PER_DYNAMICDEP_OFFSET                       0x0008
+#define DRA7XX_CM_L4PER2_L4_PER2_CLKCTRL_OFFSET                 0x000c
+#define DRA7XX_CM_L4PER2_L4_PER2_CLKCTRL                        DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x000c)
+#define DRA7XX_CM_L4PER3_L4_PER3_CLKCTRL_OFFSET                 0x0014
+#define DRA7XX_CM_L4PER3_L4_PER3_CLKCTRL                        DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0014)
+#define DRA7XX_CM_L4PER2_PRUSS1_CLKCTRL_OFFSET                  0x0018
+#define DRA7XX_CM_L4PER2_PRUSS1_CLKCTRL                         DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0018)
+#define DRA7XX_CM_L4PER2_PRUSS2_CLKCTRL_OFFSET                  0x0020
+#define DRA7XX_CM_L4PER2_PRUSS2_CLKCTRL                         DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0020)
+#define DRA7XX_CM_L4PER_TIMER10_CLKCTRL_OFFSET                  0x0028
+#define DRA7XX_CM_L4PER_TIMER10_CLKCTRL                         DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0028)
+#define DRA7XX_CM_L4PER_TIMER11_CLKCTRL_OFFSET                  0x0030
+#define DRA7XX_CM_L4PER_TIMER11_CLKCTRL                         DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0030)
+#define DRA7XX_CM_L4PER_TIMER2_CLKCTRL_OFFSET                   0x0038
+#define DRA7XX_CM_L4PER_TIMER2_CLKCTRL                          DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0038)
+#define DRA7XX_CM_L4PER_TIMER3_CLKCTRL_OFFSET                   0x0040
+#define DRA7XX_CM_L4PER_TIMER3_CLKCTRL                          DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0040)
+#define DRA7XX_CM_L4PER_TIMER4_CLKCTRL_OFFSET                   0x0048
+#define DRA7XX_CM_L4PER_TIMER4_CLKCTRL                          DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0048)
+#define DRA7XX_CM_L4PER_TIMER9_CLKCTRL_OFFSET                   0x0050
+#define DRA7XX_CM_L4PER_TIMER9_CLKCTRL                          DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0050)
+#define DRA7XX_CM_L4PER_ELM_CLKCTRL_OFFSET                      0x0058
+#define DRA7XX_CM_L4PER_ELM_CLKCTRL                             DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0058)
+#define DRA7XX_CM_L4PER_GPIO2_CLKCTRL_OFFSET                    0x0060
+#define DRA7XX_CM_L4PER_GPIO2_CLKCTRL                           DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0060)
+#define DRA7XX_CM_L4PER_GPIO3_CLKCTRL_OFFSET                    0x0068
+#define DRA7XX_CM_L4PER_GPIO3_CLKCTRL                           DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0068)
+#define DRA7XX_CM_L4PER_GPIO4_CLKCTRL_OFFSET                    0x0070
+#define DRA7XX_CM_L4PER_GPIO4_CLKCTRL                           DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0070)
+#define DRA7XX_CM_L4PER_GPIO5_CLKCTRL_OFFSET                    0x0078
+#define DRA7XX_CM_L4PER_GPIO5_CLKCTRL                           DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0078)
+#define DRA7XX_CM_L4PER_GPIO6_CLKCTRL_OFFSET                    0x0080
+#define DRA7XX_CM_L4PER_GPIO6_CLKCTRL                           DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0080)
+#define DRA7XX_CM_L4PER_HDQ1W_CLKCTRL_OFFSET                    0x0088
+#define DRA7XX_CM_L4PER_HDQ1W_CLKCTRL                           DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0088)
+#define DRA7XX_CM_L4PER2_PWMSS2_CLKCTRL_OFFSET                  0x0090
+#define DRA7XX_CM_L4PER2_PWMSS2_CLKCTRL                         DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0090)
+#define DRA7XX_CM_L4PER2_PWMSS3_CLKCTRL_OFFSET                  0x0098
+#define DRA7XX_CM_L4PER2_PWMSS3_CLKCTRL                         DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0098)
+#define DRA7XX_CM_L4PER_I2C1_CLKCTRL_OFFSET                     0x00a0
+#define DRA7XX_CM_L4PER_I2C1_CLKCTRL                            DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x00a0)
+#define DRA7XX_CM_L4PER_I2C2_CLKCTRL_OFFSET                     0x00a8
+#define DRA7XX_CM_L4PER_I2C2_CLKCTRL                            DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x00a8)
+#define DRA7XX_CM_L4PER_I2C3_CLKCTRL_OFFSET                     0x00b0
+#define DRA7XX_CM_L4PER_I2C3_CLKCTRL                            DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x00b0)
+#define DRA7XX_CM_L4PER_I2C4_CLKCTRL_OFFSET                     0x00b8
+#define DRA7XX_CM_L4PER_I2C4_CLKCTRL                            DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x00b8)
+#define DRA7XX_CM_L4PER_L4_PER1_CLKCTRL_OFFSET                  0x00c0
+#define DRA7XX_CM_L4PER_L4_PER1_CLKCTRL                         DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x00c0)
+#define DRA7XX_CM_L4PER2_PWMSS1_CLKCTRL_OFFSET                  0x00c4
+#define DRA7XX_CM_L4PER2_PWMSS1_CLKCTRL                         DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x00c4)
+#define DRA7XX_CM_L4PER3_TIMER13_CLKCTRL_OFFSET                 0x00c8
+#define DRA7XX_CM_L4PER3_TIMER13_CLKCTRL                        DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x00c8)
+#define DRA7XX_CM_L4PER3_TIMER14_CLKCTRL_OFFSET                 0x00d0
+#define DRA7XX_CM_L4PER3_TIMER14_CLKCTRL                        DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x00d0)
+#define DRA7XX_CM_L4PER3_TIMER15_CLKCTRL_OFFSET                 0x00d8
+#define DRA7XX_CM_L4PER3_TIMER15_CLKCTRL                        DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x00d8)
+#define DRA7XX_CM_L4PER_MCSPI1_CLKCTRL_OFFSET                   0x00f0
+#define DRA7XX_CM_L4PER_MCSPI1_CLKCTRL                          DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x00f0)
+#define DRA7XX_CM_L4PER_MCSPI2_CLKCTRL_OFFSET                   0x00f8
+#define DRA7XX_CM_L4PER_MCSPI2_CLKCTRL                          DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x00f8)
+#define DRA7XX_CM_L4PER_MCSPI3_CLKCTRL_OFFSET                   0x0100
+#define DRA7XX_CM_L4PER_MCSPI3_CLKCTRL                          DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0100)
+#define DRA7XX_CM_L4PER_MCSPI4_CLKCTRL_OFFSET                   0x0108
+#define DRA7XX_CM_L4PER_MCSPI4_CLKCTRL                          DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0108)
+#define DRA7XX_CM_L4PER_GPIO7_CLKCTRL_OFFSET                    0x0110
+#define DRA7XX_CM_L4PER_GPIO7_CLKCTRL                           DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0110)
+#define DRA7XX_CM_L4PER_GPIO8_CLKCTRL_OFFSET                    0x0118
+#define DRA7XX_CM_L4PER_GPIO8_CLKCTRL                           DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0118)
+#define DRA7XX_CM_L4PER_MMC3_CLKCTRL_OFFSET                     0x0120
+#define DRA7XX_CM_L4PER_MMC3_CLKCTRL                            DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0120)
+#define DRA7XX_CM_L4PER_MMC4_CLKCTRL_OFFSET                     0x0128
+#define DRA7XX_CM_L4PER_MMC4_CLKCTRL                            DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0128)
+#define DRA7XX_CM_L4PER3_TIMER16_CLKCTRL_OFFSET                 0x0130
+#define DRA7XX_CM_L4PER3_TIMER16_CLKCTRL                        DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0130)
+#define DRA7XX_CM_L4PER2_QSPI_CLKCTRL_OFFSET                    0x0138
+#define DRA7XX_CM_L4PER2_QSPI_CLKCTRL                           DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0138)
+#define DRA7XX_CM_L4PER_UART1_CLKCTRL_OFFSET                    0x0140
+#define DRA7XX_CM_L4PER_UART1_CLKCTRL                           DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0140)
+#define DRA7XX_CM_L4PER_UART2_CLKCTRL_OFFSET                    0x0148
+#define DRA7XX_CM_L4PER_UART2_CLKCTRL                           DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0148)
+#define DRA7XX_CM_L4PER_UART3_CLKCTRL_OFFSET                    0x0150
+#define DRA7XX_CM_L4PER_UART3_CLKCTRL                           DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0150)
+#define DRA7XX_CM_L4PER_UART4_CLKCTRL_OFFSET                    0x0158
+#define DRA7XX_CM_L4PER_UART4_CLKCTRL                           DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0158)
+#define DRA7XX_CM_L4PER2_MCASP2_CLKCTRL_OFFSET                  0x0160
+#define DRA7XX_CM_L4PER2_MCASP2_CLKCTRL                         DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0160)
+#define DRA7XX_CM_L4PER2_MCASP3_CLKCTRL_OFFSET                  0x0168
+#define DRA7XX_CM_L4PER2_MCASP3_CLKCTRL                         DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0168)
+#define DRA7XX_CM_L4PER_UART5_CLKCTRL_OFFSET                    0x0170
+#define DRA7XX_CM_L4PER_UART5_CLKCTRL                           DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0170)
+#define DRA7XX_CM_L4PER2_MCASP5_CLKCTRL_OFFSET                  0x0178
+#define DRA7XX_CM_L4PER2_MCASP5_CLKCTRL                         DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0178)
+#define DRA7XX_CM_L4SEC_CLKSTCTRL_OFFSET                        0x0180
+#define DRA7XX_CM_L4SEC_STATICDEP_OFFSET                        0x0184
+#define DRA7XX_CM_L4SEC_DYNAMICDEP_OFFSET                       0x0188
+#define DRA7XX_CM_L4PER2_MCASP8_CLKCTRL_OFFSET                  0x0190
+#define DRA7XX_CM_L4PER2_MCASP8_CLKCTRL                         DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0190)
+#define DRA7XX_CM_L4PER2_MCASP4_CLKCTRL_OFFSET                  0x0198
+#define DRA7XX_CM_L4PER2_MCASP4_CLKCTRL                         DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0198)
+#define DRA7XX_CM_L4SEC_AES1_CLKCTRL_OFFSET                     0x01a0
+#define DRA7XX_CM_L4SEC_AES1_CLKCTRL                            DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01a0)
+#define DRA7XX_CM_L4SEC_AES2_CLKCTRL_OFFSET                     0x01a8
+#define DRA7XX_CM_L4SEC_AES2_CLKCTRL                            DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01a8)
+#define DRA7XX_CM_L4SEC_DES3DES_CLKCTRL_OFFSET                  0x01b0
+#define DRA7XX_CM_L4SEC_DES3DES_CLKCTRL                         DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01b0)
+#define DRA7XX_CM_L4SEC_FPKA_CLKCTRL_OFFSET                     0x01b8
+#define DRA7XX_CM_L4SEC_FPKA_CLKCTRL                            DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01b8)
+#define DRA7XX_CM_L4SEC_RNG_CLKCTRL_OFFSET                      0x01c0
+#define DRA7XX_CM_L4SEC_RNG_CLKCTRL                             DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01c0)
+#define DRA7XX_CM_L4SEC_SHA2MD51_CLKCTRL_OFFSET                 0x01c8
+#define DRA7XX_CM_L4SEC_SHA2MD51_CLKCTRL                        DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01c8)
+#define DRA7XX_CM_L4PER2_UART7_CLKCTRL_OFFSET                   0x01d0
+#define DRA7XX_CM_L4PER2_UART7_CLKCTRL                          DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01d0)
+#define DRA7XX_CM_L4SEC_DMA_CRYPTO_CLKCTRL_OFFSET               0x01d8
+#define DRA7XX_CM_L4SEC_DMA_CRYPTO_CLKCTRL                      DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01d8)
+#define DRA7XX_CM_L4PER2_UART8_CLKCTRL_OFFSET                   0x01e0
+#define DRA7XX_CM_L4PER2_UART8_CLKCTRL                          DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01e0)
+#define DRA7XX_CM_L4PER2_UART9_CLKCTRL_OFFSET                   0x01e8
+#define DRA7XX_CM_L4PER2_UART9_CLKCTRL                          DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01e8)
+#define DRA7XX_CM_L4PER2_DCAN2_CLKCTRL_OFFSET                   0x01f0
+#define DRA7XX_CM_L4PER2_DCAN2_CLKCTRL                          DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01f0)
+#define DRA7XX_CM_L4SEC_SHA2MD52_CLKCTRL_OFFSET                 0x01f8
+#define DRA7XX_CM_L4SEC_SHA2MD52_CLKCTRL                        DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01f8)
+#define DRA7XX_CM_L4PER2_CLKSTCTRL_OFFSET                       0x01fc
+#define DRA7XX_CM_L4PER2_DYNAMICDEP_OFFSET                      0x0200
+#define DRA7XX_CM_L4PER2_MCASP6_CLKCTRL_OFFSET                  0x0204
+#define DRA7XX_CM_L4PER2_MCASP6_CLKCTRL                         DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0204)
+#define DRA7XX_CM_L4PER2_MCASP7_CLKCTRL_OFFSET                  0x0208
+#define DRA7XX_CM_L4PER2_MCASP7_CLKCTRL                         DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0208)
+#define DRA7XX_CM_L4PER2_STATICDEP_OFFSET                       0x020c
+#define DRA7XX_CM_L4PER3_CLKSTCTRL_OFFSET                       0x0210
+#define DRA7XX_CM_L4PER3_DYNAMICDEP_OFFSET                      0x0214
+
+#endif
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index 3656b8009a1c..ff2113ce4014 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -665,6 +665,11 @@ void __init dra7xx_init_early(void)
         omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE));
         omap_prm_base_init();
         omap_cm_base_init();
+        omap44xx_prm_init();
+        dra7xx_powerdomains_init();
+        dra7xx_clockdomains_init();
+        dra7xx_hwmod_init();
+        omap_hwmod_init_postsetup();
 }
 #endif
 
diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index b4ecd2c7db8e..d9ee0ff094d4 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -1405,7 +1405,9 @@ static void _enable_sysc(struct omap_hwmod *oh)
             (sf & SYSC_HAS_CLOCKACTIVITY))
                 _set_clockactivity(oh, oh->class->sysc->clockact, &v);
 
-        _write_sysconfig(v, oh);
+        /* If the cached value is the same as the new value, skip the write */
+        if (oh->_sysc_cache != v)
+                _write_sysconfig(v, oh);
 
         /*
          * Set the autoidle bit only after setting the smartidle bit
diff --git a/arch/arm/mach-omap2/omap_hwmod.h b/arch/arm/mach-omap2/omap_hwmod.h
index e1482a9b3bc2..d02acf9308d3 100644
--- a/arch/arm/mach-omap2/omap_hwmod.h
+++ b/arch/arm/mach-omap2/omap_hwmod.h
@@ -751,6 +751,7 @@ extern int omap3xxx_hwmod_init(void);
 extern int omap44xx_hwmod_init(void);
 extern int omap54xx_hwmod_init(void);
 extern int am33xx_hwmod_init(void);
+extern int dra7xx_hwmod_init(void);
 
 extern int __init omap_hwmod_register_links(struct omap_hwmod_ocp_if **ois);
 
diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
index eb2f3b93b51c..215894f8910d 100644
--- a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
@@ -325,7 +325,6 @@ static struct omap_hwmod am33xx_adc_tsc_hwmod = {
  *
  *    - cEFUSE (doesn't fall under any ocp_if)
  *    - clkdiv32k
- *    - debugss
  *    - ocp watch point
  */
 #if 0
@@ -369,27 +368,6 @@ static struct omap_hwmod am33xx_clkdiv32k_hwmod = {
         },
 };
 
-/*
- * 'debugss' class
- * debug sub system
- */
-static struct omap_hwmod_class am33xx_debugss_hwmod_class = {
-        .name           = "debugss",
-};
-
-static struct omap_hwmod am33xx_debugss_hwmod = {
-        .name           = "debugss",
-        .class          = &am33xx_debugss_hwmod_class,
-        .clkdm_name     = "l3_aon_clkdm",
-        .main_clk       = "debugss_ick",
-        .prcm           = {
-                .omap4  = {
-                        .clkctrl_offs   = AM33XX_CM_WKUP_DEBUGSS_CLKCTRL_OFFSET,
-                        .modulemode     = MODULEMODE_SWCTRL,
-                },
-        },
-};
-
 /* ocpwp */
 static struct omap_hwmod_class am33xx_ocpwp_hwmod_class = {
         .name           = "ocpwp",
@@ -482,6 +460,34 @@ static struct omap_hwmod am33xx_ocmcram_hwmod = {
         },
 };
 
+/*
+ * 'debugss' class
+ * debug sub system
+ */
+static struct omap_hwmod_opt_clk debugss_opt_clks[] = {
+        { .role = "dbg_sysclk", .clk = "dbg_sysclk_ck" },
+        { .role = "dbg_clka", .clk = "dbg_clka_ck" },
+};
+
+static struct omap_hwmod_class am33xx_debugss_hwmod_class = {
+        .name           = "debugss",
+};
+
+static struct omap_hwmod am33xx_debugss_hwmod = {
+        .name           = "debugss",
+        .class          = &am33xx_debugss_hwmod_class,
+        .clkdm_name     = "l3_aon_clkdm",
+        .main_clk       = "trace_clk_div_ck",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_WKUP_DEBUGSS_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+        .opt_clks       = debugss_opt_clks,
+        .opt_clks_cnt   = ARRAY_SIZE(debugss_opt_clks),
+};
+
 /* 'smartreflex' class */
 static struct omap_hwmod_class am33xx_smartreflex_hwmod_class = {
         .name           = "smartreflex",
@@ -1796,6 +1802,24 @@ static struct omap_hwmod_ocp_if am33xx_l3_main__gfx = {
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
+/* l3_main -> debugss */
+static struct omap_hwmod_addr_space am33xx_debugss_addrs[] = {
+        {
+                .pa_start       = 0x4b000000,
+                .pa_end         = 0x4b000000 + SZ_16M - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l3_main__debugss = {
+        .master         = &am33xx_l3_main_hwmod,
+        .slave          = &am33xx_debugss_hwmod,
+        .clk            = "dpll_core_m4_ck",
+        .addr           = am33xx_debugss_addrs,
+        .user           = OCP_USER_MPU,
+};
+
 /* l4 wkup -> smartreflex0 */
 static struct omap_hwmod_ocp_if am33xx_l4_wkup__smartreflex0 = {
         .master         = &am33xx_l4_wkup_hwmod,
@@ -2470,6 +2494,7 @@ static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = {
         &am33xx_pruss__l3_main,
         &am33xx_wkup_m3__l4_wkup,
         &am33xx_gfx__l3_main,
+        &am33xx_l3_main__debugss,
         &am33xx_l4_wkup__wkup_m3,
         &am33xx_l4_wkup__control,
         &am33xx_l4_wkup__smartreflex0,
diff --git a/arch/arm/mach-omap2/omap_hwmod_54xx_data.c b/arch/arm/mach-omap2/omap_hwmod_54xx_data.c
index b4d04748576b..cde415570e04 100644
--- a/arch/arm/mach-omap2/omap_hwmod_54xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_54xx_data.c
@@ -740,6 +740,39 @@ static struct omap_hwmod omap54xx_kbd_hwmod = {
 };
 
 /*
+ * 'mailbox' class
+ * mailbox module allowing communication between the on-chip processors using a
+ * queued mailbox-interrupt mechanism.
+ */
+
+static struct omap_hwmod_class_sysconfig omap54xx_mailbox_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
+                           SYSC_HAS_SOFTRESET),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+        .sysc_fields    = &omap_hwmod_sysc_type2,
+};
+
+static struct omap_hwmod_class omap54xx_mailbox_hwmod_class = {
+        .name   = "mailbox",
+        .sysc   = &omap54xx_mailbox_sysc,
+};
+
+/* mailbox */
+static struct omap_hwmod omap54xx_mailbox_hwmod = {
+        .name           = "mailbox",
+        .class          = &omap54xx_mailbox_hwmod_class,
+        .clkdm_name     = "l4cfg_clkdm",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP54XX_CM_L4CFG_MAILBOX_CLKCTRL_OFFSET,
+                        .context_offs = OMAP54XX_RM_L4CFG_MAILBOX_CONTEXT_OFFSET,
+                },
+        },
+};
+
+/*
  * 'mcbsp' class
  * multi channel buffered serial port controller
  */
@@ -1807,6 +1840,14 @@ static struct omap_hwmod_ocp_if omap54xx_l4_wkup__kbd = {
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
+/* l4_cfg -> mailbox */
+static struct omap_hwmod_ocp_if omap54xx_l4_cfg__mailbox = {
+        .master         = &omap54xx_l4_cfg_hwmod,
+        .slave          = &omap54xx_mailbox_hwmod,
+        .clk            = "l4_root_clk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
 /* l4_abe -> mcbsp1 */
 static struct omap_hwmod_ocp_if omap54xx_l4_abe__mcbsp1 = {
         .master         = &omap54xx_l4_abe_hwmod,
@@ -2107,6 +2148,7 @@ static struct omap_hwmod_ocp_if *omap54xx_hwmod_ocp_ifs[] __initdata = {
         &omap54xx_l4_per__i2c4,
         &omap54xx_l4_per__i2c5,
         &omap54xx_l4_wkup__kbd,
+        &omap54xx_l4_cfg__mailbox,
         &omap54xx_l4_abe__mcbsp1,
         &omap54xx_l4_abe__mcbsp2,
         &omap54xx_l4_abe__mcbsp3,
diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
new file mode 100644
index 000000000000..db32d5380b11
--- /dev/null
+++ b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
@@ -0,0 +1,2724 @@
+/*
+ * Hardware modules present on the DRA7xx chips
+ *
+ * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
+ *
+ * Paul Walmsley
+ * Benoit Cousson
+ *
+ * This file is automatically generated from the OMAP hardware databases.
+ * We respectfully ask that any modifications to this file be coordinated
+ * with the public linux-omap@vger.kernel.org mailing list and the
+ * authors above to ensure that the autogeneration scripts are kept
+ * up-to-date with the file contents.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/io.h>
+#include <linux/platform_data/gpio-omap.h>
+#include <linux/power/smartreflex.h>
+#include <linux/i2c-omap.h>
+
+#include <linux/omap-dma.h>
+#include <linux/platform_data/spi-omap2-mcspi.h>
+#include <linux/platform_data/asoc-ti-mcbsp.h>
+#include <plat/dmtimer.h>
+
+#include "omap_hwmod.h"
+#include "omap_hwmod_common_data.h"
+#include "cm1_7xx.h"
+#include "cm2_7xx.h"
+#include "prm7xx.h"
+#include "i2c.h"
+#include "mmc.h"
+#include "wd_timer.h"
+
+/* Base offset for all DRA7XX interrupts external to MPUSS */
+#define DRA7XX_IRQ_GIC_START    32
+
+/* Base offset for all DRA7XX dma requests */
+#define DRA7XX_DMA_REQ_START    1
+
+
+/*
+ * IP blocks
+ */
+
+/*
+ * 'l3' class
+ * instance(s): l3_instr, l3_main_1, l3_main_2
+ */
+static struct omap_hwmod_class dra7xx_l3_hwmod_class = {
+        .name   = "l3",
+};
+
+/* l3_instr */
+static struct omap_hwmod dra7xx_l3_instr_hwmod = {
+        .name           = "l3_instr",
+        .class          = &dra7xx_l3_hwmod_class,
+        .clkdm_name     = "l3instr_clkdm",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = DRA7XX_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET,
+                        .context_offs = DRA7XX_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_HWCTRL,
+                },
+        },
+};
+
+/* l3_main_1 */
+static struct omap_hwmod dra7xx_l3_main_1_hwmod = {
+        .name           = "l3_main_1",
+        .class          = &dra7xx_l3_hwmod_class,
+        .clkdm_name     = "l3main1_clkdm",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = DRA7XX_CM_L3MAIN1_L3_MAIN_1_CLKCTRL_OFFSET,
+                        .context_offs = DRA7XX_RM_L3MAIN1_L3_MAIN_1_CONTEXT_OFFSET,
+                },
+        },
+};
+
+/* l3_main_2 */
+static struct omap_hwmod dra7xx_l3_main_2_hwmod = {
+        .name           = "l3_main_2",
+        .class          = &dra7xx_l3_hwmod_class,
+        .clkdm_name     = "l3instr_clkdm",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = DRA7XX_CM_L3INSTR_L3_MAIN_2_CLKCTRL_OFFSET,
+                        .context_offs = DRA7XX_RM_L3INSTR_L3_MAIN_2_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_HWCTRL,
+                },
+        },
+};
+
+/*
+ * 'l4' class
+ * instance(s): l4_cfg, l4_per1, l4_per2, l4_per3, l4_wkup
+ */
+static struct omap_hwmod_class dra7xx_l4_hwmod_class = {
+        .name   = "l4",
+};
+
+/* l4_cfg */
+static struct omap_hwmod dra7xx_l4_cfg_hwmod = {
+        .name           = "l4_cfg",
+        .class          = &dra7xx_l4_hwmod_class,
+        .clkdm_name     = "l4cfg_clkdm",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = DRA7XX_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET,
+                        .context_offs = DRA7XX_RM_L4CFG_L4_CFG_CONTEXT_OFFSET,
+                },
+        },
+};
+
+/* l4_per1 */
+static struct omap_hwmod dra7xx_l4_per1_hwmod = {
+        .name           = "l4_per1",
+        .class          = &dra7xx_l4_hwmod_class,
+        .clkdm_name     = "l4per_clkdm",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = DRA7XX_CM_L4PER_L4_PER1_CLKCTRL_OFFSET,
+                        .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
+                },
+        },
+};
+
+/* l4_per2 */
+static struct omap_hwmod dra7xx_l4_per2_hwmod = {
+        .name           = "l4_per2",
+        .class          = &dra7xx_l4_hwmod_class,
+        .clkdm_name     = "l4per2_clkdm",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = DRA7XX_CM_L4PER2_L4_PER2_CLKCTRL_OFFSET,
+                        .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
+                },
+        },
+};
+
+/* l4_per3 */
+static struct omap_hwmod dra7xx_l4_per3_hwmod = {
+        .name           = "l4_per3",
+        .class          = &dra7xx_l4_hwmod_class,
+        .clkdm_name     = "l4per3_clkdm",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = DRA7XX_CM_L4PER3_L4_PER3_CLKCTRL_OFFSET,
+                        .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
+                },
+        },
+};
+
+/* l4_wkup */
+static struct omap_hwmod dra7xx_l4_wkup_hwmod = {
+        .name           = "l4_wkup",
+        .class          = &dra7xx_l4_hwmod_class,
+        .clkdm_name     = "wkupaon_clkdm",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = DRA7XX_CM_WKUPAON_L4_WKUP_CLKCTRL_OFFSET,
+                        .context_offs = DRA7XX_RM_WKUPAON_L4_WKUP_CONTEXT_OFFSET,
+                },
+        },
+};
+
+/*
+ * 'atl' class
+ *
+ */
+
+static struct omap_hwmod_class dra7xx_atl_hwmod_class = {
+        .name   = "atl",
+};
+
+/* atl */
+static struct omap_hwmod dra7xx_atl_hwmod = {
+        .name           = "atl",
+        .class          = &dra7xx_atl_hwmod_class,
+        .clkdm_name     = "atl_clkdm",
+        .main_clk       = "atl_gfclk_mux",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = DRA7XX_CM_ATL_ATL_CLKCTRL_OFFSET,
+                        .context_offs = DRA7XX_RM_ATL_ATL_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+/*
+ * 'bb2d' class
+ *
+ */
+
+static struct omap_hwmod_class dra7xx_bb2d_hwmod_class = {
+        .name   = "bb2d",
+};
+
+/* bb2d */
+static struct omap_hwmod dra7xx_bb2d_hwmod = {
+        .name           = "bb2d",
+        .class          = &dra7xx_bb2d_hwmod_class,
+        .clkdm_name     = "dss_clkdm",
+        .main_clk       = "dpll_core_h24x2_ck",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = DRA7XX_CM_DSS_BB2D_CLKCTRL_OFFSET,
+                        .context_offs = DRA7XX_RM_DSS_BB2D_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+/*
+ * 'counter' class
+ *
+ */
+
+static struct omap_hwmod_class_sysconfig dra7xx_counter_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        .sysc_flags     = SYSC_HAS_SIDLEMODE,
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+                           SIDLE_SMART_WKUP),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class dra7xx_counter_hwmod_class = {
+        .name   = "counter",
+        .sysc   = &dra7xx_counter_sysc,
+};
+
+/* counter_32k */
+static struct omap_hwmod dra7xx_counter_32k_hwmod = {
+        .name           = "counter_32k",
+        .class          = &dra7xx_counter_hwmod_class,
+        .clkdm_name     = "wkupaon_clkdm",
+        .flags          = HWMOD_SWSUP_SIDLE,
+        .main_clk       = "wkupaon_iclk_mux",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = DRA7XX_CM_WKUPAON_COUNTER_32K_CLKCTRL_OFFSET,
+                        .context_offs = DRA7XX_RM_WKUPAON_COUNTER_32K_CONTEXT_OFFSET,
+                },
+        },
+};
+
+/*
+ * 'ctrl_module' class
+ *
+ */
+
+static struct omap_hwmod_class dra7xx_ctrl_module_hwmod_class = {
+        .name   = "ctrl_module",
+};
+
+/* ctrl_module_wkup */
+static struct omap_hwmod dra7xx_ctrl_module_wkup_hwmod = {
+        .name           = "ctrl_module_wkup",
+        .class          = &dra7xx_ctrl_module_hwmod_class,
+        .clkdm_name     = "wkupaon_clkdm",
+        .prcm = {
+                .omap4 = {
+                        .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
+                },
+        },
+};
+
+/*
+ * 'dcan' class
+ *
+ */
+
+static struct omap_hwmod_class dra7xx_dcan_hwmod_class = {
+        .name   = "dcan",
+};
+
+/* dcan1 */
+static struct omap_hwmod dra7xx_dcan1_hwmod = {
+        .name           = "dcan1",
+        .class          = &dra7xx_dcan_hwmod_class,
+        .clkdm_name     = "wkupaon_clkdm",
+        .main_clk       = "dcan1_sys_clk_mux",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = DRA7XX_CM_WKUPAON_DCAN1_CLKCTRL_OFFSET,
+                        .context_offs = DRA7XX_RM_WKUPAON_DCAN1_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+/* dcan2 */
+static struct omap_hwmod dra7xx_dcan2_hwmod = {
+        .name           = "dcan2",
+        .class          = &dra7xx_dcan_hwmod_class,
+        .clkdm_name     = "l4per2_clkdm",
+        .main_clk       = "sys_clkin1",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = DRA7XX_CM_L4PER2_DCAN2_CLKCTRL_OFFSET,
+                        .context_offs = DRA7XX_RM_L4PER2_DCAN2_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+/*
+ * 'dma' class
+ *
+ */
+
+static struct omap_hwmod_class_sysconfig dra7xx_dma_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x002c,
+        .syss_offs      = 0x0028,
+        .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
+                           SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
+                           SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
+                           SYSS_HAS_RESET_STATUS),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+                           SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
+                           MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class dra7xx_dma_hwmod_class = {
+        .name   = "dma",
+        .sysc   = &dra7xx_dma_sysc,
+};
+
+/* dma dev_attr */
+static struct omap_dma_dev_attr dma_dev_attr = {
+        .dev_caps       = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
+                          IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
+        .lch_count      = 32,
+};
+
+/* dma_system */
+static struct omap_hwmod_irq_info dra7xx_dma_system_irqs[] = {
+        { .name = "0", .irq = 12 + DRA7XX_IRQ_GIC_START },
+        { .name = "1", .irq = 13 + DRA7XX_IRQ_GIC_START },
+        { .name = "2", .irq = 14 + DRA7XX_IRQ_GIC_START },
+        { .name = "3", .irq = 15 + DRA7XX_IRQ_GIC_START },
+        { .irq = -1 }
+};
+
+static struct omap_hwmod dra7xx_dma_system_hwmod = {
+        .name           = "dma_system",
+        .class          = &dra7xx_dma_hwmod_class,
+        .clkdm_name     = "dma_clkdm",
+        .mpu_irqs       = dra7xx_dma_system_irqs,
+        .main_clk       = "l3_iclk_div",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = DRA7XX_CM_DMA_DMA_SYSTEM_CLKCTRL_OFFSET,
+                        .context_offs = DRA7XX_RM_DMA_DMA_SYSTEM_CONTEXT_OFFSET,
+                },
+        },
+        .dev_attr       = &dma_dev_attr,
+};
+
+/*
+ * 'dss' class
+ *
+ */
+
+static struct omap_hwmod_class_sysconfig dra7xx_dss_sysc = {
+        .rev_offs       = 0x0000,
+        .syss_offs      = 0x0014,
+        .sysc_flags     = SYSS_HAS_RESET_STATUS,
+};
+
+static struct omap_hwmod_class dra7xx_dss_hwmod_class = {
+        .name   = "dss",
+        .sysc   = &dra7xx_dss_sysc,
+        .reset  = omap_dss_reset,
+};
+
+/* dss */
+static struct omap_hwmod_dma_info dra7xx_dss_sdma_reqs[] = {
+        { .dma_req = 75 + DRA7XX_DMA_REQ_START },
+        { .dma_req = -1 }
+};
+
+static struct omap_hwmod_opt_clk dss_opt_clks[] = {
+        { .role = "dss_clk", .clk = "dss_dss_clk" },
+        { .role = "hdmi_phy_clk", .clk = "dss_48mhz_clk" },
+        { .role = "32khz_clk", .clk = "dss_32khz_clk" },
+        { .role = "video2_clk", .clk = "dss_video2_clk" },
+        { .role = "video1_clk", .clk = "dss_video1_clk" },
+        { .role = "hdmi_clk", .clk = "dss_hdmi_clk" },
+};
+
+static struct omap_hwmod dra7xx_dss_hwmod = {
+        .name           = "dss_core",
+        .class          = &dra7xx_dss_hwmod_class,
+        .clkdm_name     = "dss_clkdm",
+        .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+        .sdma_reqs      = dra7xx_dss_sdma_reqs,
+        .main_clk       = "dss_dss_clk",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET,
+                        .context_offs = DRA7XX_RM_DSS_DSS_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
+                },
+        },
+        .opt_clks       = dss_opt_clks,
+        .opt_clks_cnt   = ARRAY_SIZE(dss_opt_clks),
+};
+
+/*
+ * 'dispc' class
+ * display controller
+ */
+
+static struct omap_hwmod_class_sysconfig dra7xx_dispc_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        .syss_offs      = 0x0014,
+        .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
+                           SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE |
+                           SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
+                           SYSS_HAS_RESET_STATUS),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+                           MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class dra7xx_dispc_hwmod_class = {
+        .name   = "dispc",
+        .sysc   = &dra7xx_dispc_sysc,
+};
+
+/* dss_dispc */
+/* dss_dispc dev_attr */
+static struct omap_dss_dispc_dev_attr dss_dispc_dev_attr = {
+        .has_framedonetv_irq    = 1,
+        .manager_count          = 4,
+};
+
+static struct omap_hwmod dra7xx_dss_dispc_hwmod = {
+        .name           = "dss_dispc",
+        .class          = &dra7xx_dispc_hwmod_class,
+        .clkdm_name     = "dss_clkdm",
+        .main_clk       = "dss_dss_clk",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET,
+                        .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
+                },
+        },
+        .dev_attr       = &dss_dispc_dev_attr,
+};
+
+/*
+ * 'hdmi' class
+ * hdmi controller
+ */
+
+static struct omap_hwmod_class_sysconfig dra7xx_hdmi_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
+                           SYSC_HAS_SOFTRESET),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+                           SIDLE_SMART_WKUP),
+        .sysc_fields    = &omap_hwmod_sysc_type2,
+};
+
+static struct omap_hwmod_class dra7xx_hdmi_hwmod_class = {
+        .name   = "hdmi",
+        .sysc   = &dra7xx_hdmi_sysc,
+};
+
+/* dss_hdmi */
+
+static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = {
+        { .role = "sys_clk", .clk = "dss_hdmi_clk" },
+};
+
+static struct omap_hwmod dra7xx_dss_hdmi_hwmod = {
+        .name           = "dss_hdmi",
+        .class          = &dra7xx_hdmi_hwmod_class,
+        .clkdm_name     = "dss_clkdm",
+        .main_clk       = "dss_48mhz_clk",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET,
+                        .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
+                },
+        },
+        .opt_clks       = dss_hdmi_opt_clks,
+        .opt_clks_cnt   = ARRAY_SIZE(dss_hdmi_opt_clks),
+};
+
+/*
+ * 'elm' class
+ *
+ */
+
+static struct omap_hwmod_class_sysconfig dra7xx_elm_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        .syss_offs      = 0x0014,
+        .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
+                           SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
+                           SYSS_HAS_RESET_STATUS),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+                           SIDLE_SMART_WKUP),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class dra7xx_elm_hwmod_class = {
+        .name   = "elm",
+        .sysc   = &dra7xx_elm_sysc,
+};
+
+/* elm */
+
+static struct omap_hwmod dra7xx_elm_hwmod = {
+        .name           = "elm",
+        .class          = &dra7xx_elm_hwmod_class,
+        .clkdm_name     = "l4per_clkdm",
+        .main_clk       = "l3_iclk_div",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = DRA7XX_CM_L4PER_ELM_CLKCTRL_OFFSET,
+                        .context_offs = DRA7XX_RM_L4PER_ELM_CONTEXT_OFFSET,
+                },
+        },
+};
+
+/*
+ * 'gpio' class
+ *
+ */
+
+static struct omap_hwmod_class_sysconfig dra7xx_gpio_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        .syss_offs      = 0x0114,
+        .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
+                           SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
+                           SYSS_HAS_RESET_STATUS),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+                           SIDLE_SMART_WKUP),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class dra7xx_gpio_hwmod_class = {
+        .name   = "gpio",
+        .sysc   = &dra7xx_gpio_sysc,
+        .rev    = 2,
+};
+
+/* gpio dev_attr */
+static struct omap_gpio_dev_attr gpio_dev_attr = {
+        .bank_width     = 32,
+        .dbck_flag      = true,
+};
+
+/* gpio1 */
+static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
+        { .role = "dbclk", .clk = "gpio1_dbclk" },
+};
+
+static struct omap_hwmod dra7xx_gpio1_hwmod = {
+        .name           = "gpio1",
+        .class          = &dra7xx_gpio_hwmod_class,
+        .clkdm_name     = "wkupaon_clkdm",
+        .main_clk       = "wkupaon_iclk_mux",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = DRA7XX_CM_WKUPAON_GPIO1_CLKCTRL_OFFSET,
+                        .context_offs = DRA7XX_RM_WKUPAON_GPIO1_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_HWCTRL,
+                },
+        },
+        .opt_clks       = gpio1_opt_clks,
+        .opt_clks_cnt   = ARRAY_SIZE(gpio1_opt_clks),
+        .dev_attr       = &gpio_dev_attr,
+};
+
+/* gpio2 */
+static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
+        { .role = "dbclk", .clk = "gpio2_dbclk" },
+};
+
+static struct omap_hwmod dra7xx_gpio2_hwmod = {
+        .name           = "gpio2",
+        .class          = &dra7xx_gpio_hwmod_class,
+        .clkdm_name     = "l4per_clkdm",
+        .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+        .main_clk       = "l3_iclk_div",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = DRA7XX_CM_L4PER_GPIO2_CLKCTRL_OFFSET,
+                        .context_offs = DRA7XX_RM_L4PER_GPIO2_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_HWCTRL,
+                },
+        },
+        .opt_clks       = gpio2_opt_clks,
+        .opt_clks_cnt   = ARRAY_SIZE(gpio2_opt_clks),
+        .dev_attr       = &gpio_dev_attr,
+};
+
+/* gpio3 */
+static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
+        { .role = "dbclk", .clk = "gpio3_dbclk" },
+};
+
+static struct omap_hwmod dra7xx_gpio3_hwmod = {
+        .name           = "gpio3",
+        .class          = &dra7xx_gpio_hwmod_class,
+        .clkdm_name     = "l4per_clkdm",
+        .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+        .main_clk       = "l3_iclk_div",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = DRA7XX_CM_L4PER_GPIO3_CLKCTRL_OFFSET,
+                        .context_offs = DRA7XX_RM_L4PER_GPIO3_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_HWCTRL,
+                },
+        },
+        .opt_clks       = gpio3_opt_clks,
+        .opt_clks_cnt   = ARRAY_SIZE(gpio3_opt_clks),
+        .dev_attr       = &gpio_dev_attr,
+};
+
+/* gpio4 */
+static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
+        { .role = "dbclk", .clk = "gpio4_dbclk" },
+};
+
+static struct omap_hwmod dra7xx_gpio4_hwmod = {
+        .name           = "gpio4",
+        .class          = &dra7xx_gpio_hwmod_class,
+        .clkdm_name     = "l4per_clkdm",
+        .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+        .main_clk       = "l3_iclk_div",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = DRA7XX_CM_L4PER_GPIO4_CLKCTRL_OFFSET,
+                        .context_offs = DRA7XX_RM_L4PER_GPIO4_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_HWCTRL,
+                },
+        },
+        .opt_clks       = gpio4_opt_clks,
+        .opt_clks_cnt   = ARRAY_SIZE(gpio4_opt_clks),
+        .dev_attr       = &gpio_dev_attr,
+};
+
+/* gpio5 */
+static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
+        { .role = "dbclk", .clk = "gpio5_dbclk" },
+};
+
+static struct omap_hwmod dra7xx_gpio5_hwmod = {
+        .name           = "gpio5",
+        .class          = &dra7xx_gpio_hwmod_class,
+        .clkdm_name     = "l4per_clkdm",
+        .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+        .main_clk       = "l3_iclk_div",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = DRA7XX_CM_L4PER_GPIO5_CLKCTRL_OFFSET,
+                        .context_offs = DRA7XX_RM_L4PER_GPIO5_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_HWCTRL,
+                },
+        },
+        .opt_clks       = gpio5_opt_clks,
+        .opt_clks_cnt   = ARRAY_SIZE(gpio5_opt_clks),
+        .dev_attr       = &gpio_dev_attr,
+};
+
+/* gpio6 */
+static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
+        { .role = "dbclk", .clk = "gpio6_dbclk" },
+};
+
+static struct omap_hwmod dra7xx_gpio6_hwmod = {
+        .name           = "gpio6",
+        .class          = &dra7xx_gpio_hwmod_class,
+        .clkdm_name     = "l4per_clkdm",
+        .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+        .main_clk       = "l3_iclk_div",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = DRA7XX_CM_L4PER_GPIO6_CLKCTRL_OFFSET,
+                        .context_offs = DRA7XX_RM_L4PER_GPIO6_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_HWCTRL,
+                },
+        },
+        .opt_clks       = gpio6_opt_clks,
+        .opt_clks_cnt   = ARRAY_SIZE(gpio6_opt_clks),
+        .dev_attr       = &gpio_dev_attr,
+};
+
+/* gpio7 */
+static struct omap_hwmod_opt_clk gpio7_opt_clks[] = {
+        { .role = "dbclk", .clk = "gpio7_dbclk" },
+};
+
+static struct omap_hwmod dra7xx_gpio7_hwmod = {
+        .name           = "gpio7",
+        .class          = &dra7xx_gpio_hwmod_class,
+        .clkdm_name     = "l4per_clkdm",
+        .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+        .main_clk       = "l3_iclk_div",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = DRA7XX_CM_L4PER_GPIO7_CLKCTRL_OFFSET,
+                        .context_offs = DRA7XX_RM_L4PER_GPIO7_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_HWCTRL,
+                },
+        },
+        .opt_clks       = gpio7_opt_clks,
+        .opt_clks_cnt   = ARRAY_SIZE(gpio7_opt_clks),
+        .dev_attr       = &gpio_dev_attr,
+};
+
+/* gpio8 */
+static struct omap_hwmod_opt_clk gpio8_opt_clks[] = {
+        { .role = "dbclk", .clk = "gpio8_dbclk" },
+};
+
+static struct omap_hwmod dra7xx_gpio8_hwmod = {
+        .name           = "gpio8",
+        .class          = &dra7xx_gpio_hwmod_class,
+        .clkdm_name     = "l4per_clkdm",
+        .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+        .main_clk       = "l3_iclk_div",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = DRA7XX_CM_L4PER_GPIO8_CLKCTRL_OFFSET,
+                        .context_offs = DRA7XX_RM_L4PER_GPIO8_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_HWCTRL,
+                },
+        },
+        .opt_clks       = gpio8_opt_clks,
+        .opt_clks_cnt   = ARRAY_SIZE(gpio8_opt_clks),
+        .dev_attr       = &gpio_dev_attr,
+};
+
+/*
+ * 'gpmc' class
+ *
+ */
+
+static struct omap_hwmod_class_sysconfig dra7xx_gpmc_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        .syss_offs      = 0x0014,
+        .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
+                           SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+                           SIDLE_SMART_WKUP),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class dra7xx_gpmc_hwmod_class = {
+        .name   = "gpmc",
+        .sysc   = &dra7xx_gpmc_sysc,
+};
+
+/* gpmc */
+
+static struct omap_hwmod dra7xx_gpmc_hwmod = {
+        .name           = "gpmc",
+        .class          = &dra7xx_gpmc_hwmod_class,
+        .clkdm_name     = "l3main1_clkdm",
+        .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
+        .main_clk       = "l3_iclk_div",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = DRA7XX_CM_L3MAIN1_GPMC_CLKCTRL_OFFSET,
+                        .context_offs = DRA7XX_RM_L3MAIN1_GPMC_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_HWCTRL,
+                },
+        },
+};
+
+/*
+ * 'hdq1w' class
+ *
+ */
+
+static struct omap_hwmod_class_sysconfig dra7xx_hdq1w_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0014,
+        .syss_offs      = 0x0018,
+        .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SOFTRESET |
+                           SYSS_HAS_RESET_STATUS),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class dra7xx_hdq1w_hwmod_class = {
+        .name   = "hdq1w",
+        .sysc   = &dra7xx_hdq1w_sysc,
+};
+
+/* hdq1w */
+
+static struct omap_hwmod dra7xx_hdq1w_hwmod = {
+        .name           = "hdq1w",
+        .class          = &dra7xx_hdq1w_hwmod_class,
+        .clkdm_name     = "l4per_clkdm",
+        .flags          = HWMOD_INIT_NO_RESET,
+        .main_clk       = "func_12m_fclk",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = DRA7XX_CM_L4PER_HDQ1W_CLKCTRL_OFFSET,
+                        .context_offs = DRA7XX_RM_L4PER_HDQ1W_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+/*
+ * 'i2c' class
+ *
+ */
+
+static struct omap_hwmod_class_sysconfig dra7xx_i2c_sysc = {
+        .sysc_offs      = 0x0010,
+        .syss_offs      = 0x0090,
+        .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
+                           SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
+                           SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+                           SIDLE_SMART_WKUP),
+        .clockact       = CLOCKACT_TEST_ICLK,
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class dra7xx_i2c_hwmod_class = {
+        .name   = "i2c",
+        .sysc   = &dra7xx_i2c_sysc,
+        .reset  = &omap_i2c_reset,
+        .rev    = OMAP_I2C_IP_VERSION_2,
+};
+
+/* i2c dev_attr */
+static struct omap_i2c_dev_attr i2c_dev_attr = {
+        .flags  = OMAP_I2C_FLAG_BUS_SHIFT_NONE,
+};
+
+/* i2c1 */
+static struct omap_hwmod dra7xx_i2c1_hwmod = {
+        .name           = "i2c1",
+        .class          = &dra7xx_i2c_hwmod_class,
+        .clkdm_name     = "l4per_clkdm",
+        .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
+        .main_clk       = "func_96m_fclk",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = DRA7XX_CM_L4PER_I2C1_CLKCTRL_OFFSET,
+                        .context_offs = DRA7XX_RM_L4PER_I2C1_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
+                },
+        },
+        .dev_attr       = &i2c_dev_attr,
+};
+
+/* i2c2 */
+static struct omap_hwmod dra7xx_i2c2_hwmod = {
+        .name           = "i2c2",
+        .class          = &dra7xx_i2c_hwmod_class,
+        .clkdm_name     = "l4per_clkdm",
+        .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
+        .main_clk       = "func_96m_fclk",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = DRA7XX_CM_L4PER_I2C2_CLKCTRL_OFFSET,
+                        .context_offs = DRA7XX_RM_L4PER_I2C2_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
+                },
+        },
+        .dev_attr       = &i2c_dev_attr,
+};
+
+/* i2c3 */
+static struct omap_hwmod dra7xx_i2c3_hwmod = {
+        .name           = "i2c3",
+        .class          = &dra7xx_i2c_hwmod_class,
+        .clkdm_name     = "l4per_clkdm",
+        .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
+        .main_clk       = "func_96m_fclk",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = DRA7XX_CM_L4PER_I2C3_CLKCTRL_OFFSET,
+                        .context_offs = DRA7XX_RM_L4PER_I2C3_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
+                },
+        },
+        .dev_attr       = &i2c_dev_attr,
+};
+
+/* i2c4 */
+static struct omap_hwmod dra7xx_i2c4_hwmod = {
+        .name           = "i2c4",
+        .class          = &dra7xx_i2c_hwmod_class,
+        .clkdm_name     = "l4per_clkdm",
+        .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
+        .main_clk       = "func_96m_fclk",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = DRA7XX_CM_L4PER_I2C4_CLKCTRL_OFFSET,
+                        .context_offs = DRA7XX_RM_L4PER_I2C4_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
+                },
+        },
+        .dev_attr       = &i2c_dev_attr,
+};
+
+/* i2c5 */
+static struct omap_hwmod dra7xx_i2c5_hwmod = {
+        .name           = "i2c5",
+        .class          = &dra7xx_i2c_hwmod_class,
+        .clkdm_name     = "ipu_clkdm",
+        .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
+        .main_clk       = "func_96m_fclk",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = DRA7XX_CM_IPU_I2C5_CLKCTRL_OFFSET,
+                        .context_offs = DRA7XX_RM_IPU_I2C5_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
+                },
+        },
+        .dev_attr       = &i2c_dev_attr,
+};
+
+/*
+ * 'mcspi' class
+ *
+ */
+
+static struct omap_hwmod_class_sysconfig dra7xx_mcspi_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
+                           SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+                           SIDLE_SMART_WKUP),
+        .sysc_fields    = &omap_hwmod_sysc_type2,
+};
+
+static struct omap_hwmod_class dra7xx_mcspi_hwmod_class = {
+        .name   = "mcspi",
+        .sysc   = &dra7xx_mcspi_sysc,
+        .rev    = OMAP4_MCSPI_REV,
+};
+
+/* mcspi1 */
+/* mcspi1 dev_attr */
+static struct omap2_mcspi_dev_attr mcspi1_dev_attr = {
+        .num_chipselect = 4,
+};
+
+static struct omap_hwmod dra7xx_mcspi1_hwmod = {
+        .name           = "mcspi1",
+        .class          = &dra7xx_mcspi_hwmod_class,
+        .clkdm_name     = "l4per_clkdm",
+        .main_clk       = "func_48m_fclk",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI1_CLKCTRL_OFFSET,
+                        .context_offs = DRA7XX_RM_L4PER_MCSPI1_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
+                },
+        },
+        .dev_attr       = &mcspi1_dev_attr,
+};
+
+/* mcspi2 */
+/* mcspi2 dev_attr */
+static struct omap2_mcspi_dev_attr mcspi2_dev_attr = {
+        .num_chipselect = 2,
+};
+
+static struct omap_hwmod dra7xx_mcspi2_hwmod = {
+        .name           = "mcspi2",
+        .class          = &dra7xx_mcspi_hwmod_class,
+        .clkdm_name     = "l4per_clkdm",
+        .main_clk       = "func_48m_fclk",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI2_CLKCTRL_OFFSET,
+                        .context_offs = DRA7XX_RM_L4PER_MCSPI2_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
+                },
+        },
+        .dev_attr       = &mcspi2_dev_attr,
+};
+
+/* mcspi3 */
+/* mcspi3 dev_attr */
+static struct omap2_mcspi_dev_attr mcspi3_dev_attr = {
+        .num_chipselect = 2,
+};
+
+static struct omap_hwmod dra7xx_mcspi3_hwmod = {
+        .name           = "mcspi3",
+        .class          = &dra7xx_mcspi_hwmod_class,
+        .clkdm_name     = "l4per_clkdm",
+        .main_clk       = "func_48m_fclk",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI3_CLKCTRL_OFFSET,
+                        .context_offs = DRA7XX_RM_L4PER_MCSPI3_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
+                },
+        },
+        .dev_attr       = &mcspi3_dev_attr,
+};
+
+/* mcspi4 */
+/* mcspi4 dev_attr */
+static struct omap2_mcspi_dev_attr mcspi4_dev_attr = {
+        .num_chipselect = 1,
+};
+
+static struct omap_hwmod dra7xx_mcspi4_hwmod = {
+        .name           = "mcspi4",
+        .class          = &dra7xx_mcspi_hwmod_class,
+        .clkdm_name     = "l4per_clkdm",
+        .main_clk       = "func_48m_fclk",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI4_CLKCTRL_OFFSET,
+                        .context_offs = DRA7XX_RM_L4PER_MCSPI4_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
+                },
+        },
+        .dev_attr       = &mcspi4_dev_attr,
+};
+
+/*
+ * 'mmc' class
+ *
+ */
+
+static struct omap_hwmod_class_sysconfig dra7xx_mmc_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
+                           SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
+                           SYSC_HAS_SOFTRESET),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+                           SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
+                           MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
+        .sysc_fields    = &omap_hwmod_sysc_type2,
+};
+
+static struct omap_hwmod_class dra7xx_mmc_hwmod_class = {
+        .name   = "mmc",
+        .sysc   = &dra7xx_mmc_sysc,
+};
+
+/* mmc1 */
+static struct omap_hwmod_opt_clk mmc1_opt_clks[] = {
+        { .role = "clk32k", .clk = "mmc1_clk32k" },
+};
+
+/* mmc1 dev_attr */
+static struct omap_mmc_dev_attr mmc1_dev_attr = {
+        .flags  = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
+};
+
+static struct omap_hwmod dra7xx_mmc1_hwmod = {
+        .name           = "mmc1",
+        .class          = &dra7xx_mmc_hwmod_class,
+        .clkdm_name     = "l3init_clkdm",
+        .main_clk       = "mmc1_fclk_div",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = DRA7XX_CM_L3INIT_MMC1_CLKCTRL_OFFSET,
+                        .context_offs = DRA7XX_RM_L3INIT_MMC1_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
+                },
+        },
+        .opt_clks       = mmc1_opt_clks,
+        .opt_clks_cnt   = ARRAY_SIZE(mmc1_opt_clks),
+        .dev_attr       = &mmc1_dev_attr,
+};
+
+/* mmc2 */
+static struct omap_hwmod_opt_clk mmc2_opt_clks[] = {
+        { .role = "clk32k", .clk = "mmc2_clk32k" },
+};
+
+static struct omap_hwmod dra7xx_mmc2_hwmod = {
+        .name           = "mmc2",
+        .class          = &dra7xx_mmc_hwmod_class,
+        .clkdm_name     = "l3init_clkdm",
+        .main_clk       = "mmc2_fclk_div",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = DRA7XX_CM_L3INIT_MMC2_CLKCTRL_OFFSET,
+                        .context_offs = DRA7XX_RM_L3INIT_MMC2_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
+                },
+        },
+        .opt_clks       = mmc2_opt_clks,
+        .opt_clks_cnt   = ARRAY_SIZE(mmc2_opt_clks),
+};
+
+/* mmc3 */
+static struct omap_hwmod_opt_clk mmc3_opt_clks[] = {
+        { .role = "clk32k", .clk = "mmc3_clk32k" },
+};
+
+static struct omap_hwmod dra7xx_mmc3_hwmod = {
+        .name           = "mmc3",
+        .class          = &dra7xx_mmc_hwmod_class,
+        .clkdm_name     = "l4per_clkdm",
+        .main_clk       = "mmc3_gfclk_div",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = DRA7XX_CM_L4PER_MMC3_CLKCTRL_OFFSET,
+                        .context_offs = DRA7XX_RM_L4PER_MMC3_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
+                },
+        },
+        .opt_clks       = mmc3_opt_clks,
+        .opt_clks_cnt   = ARRAY_SIZE(mmc3_opt_clks),
+};
+
+/* mmc4 */
+static struct omap_hwmod_opt_clk mmc4_opt_clks[] = {
+        { .role = "clk32k", .clk = "mmc4_clk32k" },
+};
+
+static struct omap_hwmod dra7xx_mmc4_hwmod = {
+        .name           = "mmc4",
+        .class          = &dra7xx_mmc_hwmod_class,
+        .clkdm_name     = "l4per_clkdm",
+        .main_clk       = "mmc4_gfclk_div",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = DRA7XX_CM_L4PER_MMC4_CLKCTRL_OFFSET,
+                        .context_offs = DRA7XX_RM_L4PER_MMC4_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
+                },
+        },
+        .opt_clks       = mmc4_opt_clks,
+        .opt_clks_cnt   = ARRAY_SIZE(mmc4_opt_clks),
+};
+
+/*
+ * 'mpu' class
+ *
+ */
+
+static struct omap_hwmod_class dra7xx_mpu_hwmod_class = {
+        .name   = "mpu",
+};
+
+/* mpu */
+static struct omap_hwmod dra7xx_mpu_hwmod = {
+        .name           = "mpu",
+        .class          = &dra7xx_mpu_hwmod_class,
+        .clkdm_name     = "mpu_clkdm",
+        .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
+        .main_clk       = "dpll_mpu_m2_ck",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = DRA7XX_CM_MPU_MPU_CLKCTRL_OFFSET,
+                        .context_offs = DRA7XX_RM_MPU_MPU_CONTEXT_OFFSET,
+                },
+        },
+};
+
+/*
+ * 'ocp2scp' class
+ *
+ */
+
+static struct omap_hwmod_class_sysconfig dra7xx_ocp2scp_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        .syss_offs      = 0x0014,
+        .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
+                           SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+                           SIDLE_SMART_WKUP),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class dra7xx_ocp2scp_hwmod_class = {
+        .name   = "ocp2scp",
+        .sysc   = &dra7xx_ocp2scp_sysc,
+};
+
+/* ocp2scp1 */
+static struct omap_hwmod dra7xx_ocp2scp1_hwmod = {
+        .name           = "ocp2scp1",
+        .class          = &dra7xx_ocp2scp_hwmod_class,
+        .clkdm_name     = "l3init_clkdm",
+        .main_clk       = "l4_root_clk_div",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = DRA7XX_CM_L3INIT_OCP2SCP1_CLKCTRL_OFFSET,
+                        .context_offs = DRA7XX_RM_L3INIT_OCP2SCP1_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_HWCTRL,
+                },
+        },
+};
+
+/*
+ * 'qspi' class
+ *
+ */
+
+static struct omap_hwmod_class_sysconfig dra7xx_qspi_sysc = {
+        .sysc_offs      = 0x0010,
+        .sysc_flags     = SYSC_HAS_SIDLEMODE,
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+                           SIDLE_SMART_WKUP),
+        .sysc_fields    = &omap_hwmod_sysc_type2,
+};
+
+static struct omap_hwmod_class dra7xx_qspi_hwmod_class = {
+        .name   = "qspi",
+        .sysc   = &dra7xx_qspi_sysc,
+};
+
+/* qspi */
+static struct omap_hwmod dra7xx_qspi_hwmod = {
+        .name           = "qspi",
+        .class          = &dra7xx_qspi_hwmod_class,
+        .clkdm_name     = "l4per2_clkdm",
+        .main_clk       = "qspi_gfclk_div",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = DRA7XX_CM_L4PER2_QSPI_CLKCTRL_OFFSET,
+                        .context_offs = DRA7XX_RM_L4PER2_QSPI_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+/*
+ * 'sata' class
+ *
+ */
+
+static struct omap_hwmod_class_sysconfig dra7xx_sata_sysc = {
+        .sysc_offs      = 0x0000,
+        .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+                           SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
+                           MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
+        .sysc_fields    = &omap_hwmod_sysc_type2,
+};
+
+static struct omap_hwmod_class dra7xx_sata_hwmod_class = {
+        .name   = "sata",
+        .sysc   = &dra7xx_sata_sysc,
+};
+
+/* sata */
+static struct omap_hwmod_opt_clk sata_opt_clks[] = {
+        { .role = "ref_clk", .clk = "sata_ref_clk" },
+};
+
+static struct omap_hwmod dra7xx_sata_hwmod = {
+        .name           = "sata",
+        .class          = &dra7xx_sata_hwmod_class,
+        .clkdm_name     = "l3init_clkdm",
+        .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
+        .main_clk       = "func_48m_fclk",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = DRA7XX_CM_L3INIT_SATA_CLKCTRL_OFFSET,
+                        .context_offs = DRA7XX_RM_L3INIT_SATA_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
+                },
+        },
+        .opt_clks       = sata_opt_clks,
+        .opt_clks_cnt   = ARRAY_SIZE(sata_opt_clks),
+};
+
+/*
+ * 'smartreflex' class
+ *
+ */
+
+/* The IP is not compliant to type1 / type2 scheme */
+static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_smartreflex = {
+        .sidle_shift    = 24,
+        .enwkup_shift   = 26,
+};
+
+static struct omap_hwmod_class_sysconfig dra7xx_smartreflex_sysc = {
+        .sysc_offs      = 0x0038,
+        .sysc_flags     = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+                           SIDLE_SMART_WKUP),
+        .sysc_fields    = &omap_hwmod_sysc_type_smartreflex,
+};
+
+static struct omap_hwmod_class dra7xx_smartreflex_hwmod_class = {
+        .name   = "smartreflex",
+        .sysc   = &dra7xx_smartreflex_sysc,
+        .rev    = 2,
+};
+
+/* smartreflex_core */
+/* smartreflex_core dev_attr */
+static struct omap_smartreflex_dev_attr smartreflex_core_dev_attr = {
+        .sensor_voltdm_name     = "core",
+};
+
+static struct omap_hwmod dra7xx_smartreflex_core_hwmod = {
+        .name           = "smartreflex_core",
+        .class          = &dra7xx_smartreflex_hwmod_class,
+        .clkdm_name     = "coreaon_clkdm",
+        .main_clk       = "wkupaon_iclk_mux",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = DRA7XX_CM_COREAON_SMARTREFLEX_CORE_CLKCTRL_OFFSET,
+                        .context_offs = DRA7XX_RM_COREAON_SMARTREFLEX_CORE_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
+                },
+        },
+        .dev_attr       = &smartreflex_core_dev_attr,
+};
+
+/* smartreflex_mpu */
+/* smartreflex_mpu dev_attr */
+static struct omap_smartreflex_dev_attr smartreflex_mpu_dev_attr = {
+        .sensor_voltdm_name     = "mpu",
+};
+
+static struct omap_hwmod dra7xx_smartreflex_mpu_hwmod = {
+        .name           = "smartreflex_mpu",
+        .class          = &dra7xx_smartreflex_hwmod_class,
+        .clkdm_name     = "coreaon_clkdm",
+        .main_clk       = "wkupaon_iclk_mux",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = DRA7XX_CM_COREAON_SMARTREFLEX_MPU_CLKCTRL_OFFSET,
+                        .context_offs = DRA7XX_RM_COREAON_SMARTREFLEX_MPU_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
+                },
+        },
+        .dev_attr       = &smartreflex_mpu_dev_attr,
+};
+
+/*
+ * 'spinlock' class
+ *
+ */
+
+static struct omap_hwmod_class_sysconfig dra7xx_spinlock_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        .syss_offs      = 0x0014,
+        .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
+                           SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
+                           SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+                           SIDLE_SMART_WKUP),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class dra7xx_spinlock_hwmod_class = {
+        .name   = "spinlock",
+        .sysc   = &dra7xx_spinlock_sysc,
+};
+
+/* spinlock */
+static struct omap_hwmod dra7xx_spinlock_hwmod = {
+        .name           = "spinlock",
+        .class          = &dra7xx_spinlock_hwmod_class,
+        .clkdm_name     = "l4cfg_clkdm",
+        .main_clk       = "l3_iclk_div",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = DRA7XX_CM_L4CFG_SPINLOCK_CLKCTRL_OFFSET,
+                        .context_offs = DRA7XX_RM_L4CFG_SPINLOCK_CONTEXT_OFFSET,
+                },
+        },
+};
+
+/*
+ * 'timer' class
+ *
+ * This class contains several variants: ['timer_1ms', 'timer_secure',
+ * 'timer']
+ */
+
+static struct omap_hwmod_class_sysconfig dra7xx_timer_1ms_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
+                           SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+                           SIDLE_SMART_WKUP),
+        .sysc_fields    = &omap_hwmod_sysc_type2,
+};
+
+static struct omap_hwmod_class dra7xx_timer_1ms_hwmod_class = {
+        .name   = "timer",
+        .sysc   = &dra7xx_timer_1ms_sysc,
+};
+
+static struct omap_hwmod_class_sysconfig dra7xx_timer_secure_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
+                           SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+                           SIDLE_SMART_WKUP),
+        .sysc_fields    = &omap_hwmod_sysc_type2,
+};
+
+static struct omap_hwmod_class dra7xx_timer_secure_hwmod_class = {
+        .name   = "timer",
+        .sysc   = &dra7xx_timer_secure_sysc,
+};
+
+static struct omap_hwmod_class_sysconfig dra7xx_timer_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
+                           SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+                           SIDLE_SMART_WKUP),
+        .sysc_fields    = &omap_hwmod_sysc_type2,
+};
+
+static struct omap_hwmod_class dra7xx_timer_hwmod_class = {
+        .name   = "timer",
+        .sysc   = &dra7xx_timer_sysc,
+};
+
+/* timer1 */
+static struct omap_hwmod dra7xx_timer1_hwmod = {
+        .name           = "timer1",
+        .class          = &dra7xx_timer_1ms_hwmod_class,
+        .clkdm_name     = "wkupaon_clkdm",
+        .main_clk       = "timer1_gfclk_mux",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = DRA7XX_CM_WKUPAON_TIMER1_CLKCTRL_OFFSET,
+                        .context_offs = DRA7XX_RM_WKUPAON_TIMER1_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+/* timer2 */
+static struct omap_hwmod dra7xx_timer2_hwmod = {
+        .name           = "timer2",
+        .class          = &dra7xx_timer_1ms_hwmod_class,
+        .clkdm_name     = "l4per_clkdm",
+        .main_clk       = "timer2_gfclk_mux",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = DRA7XX_CM_L4PER_TIMER2_CLKCTRL_OFFSET,
+                        .context_offs = DRA7XX_RM_L4PER_TIMER2_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+/* timer3 */
+static struct omap_hwmod dra7xx_timer3_hwmod = {
+        .name           = "timer3",
+        .class          = &dra7xx_timer_hwmod_class,
+        .clkdm_name     = "l4per_clkdm",
+        .main_clk       = "timer3_gfclk_mux",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = DRA7XX_CM_L4PER_TIMER3_CLKCTRL_OFFSET,
+                        .context_offs = DRA7XX_RM_L4PER_TIMER3_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+/* timer4 */
+static struct omap_hwmod dra7xx_timer4_hwmod = {
+        .name           = "timer4",
+        .class          = &dra7xx_timer_secure_hwmod_class,
+        .clkdm_name     = "l4per_clkdm",
+        .main_clk       = "timer4_gfclk_mux",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = DRA7XX_CM_L4PER_TIMER4_CLKCTRL_OFFSET,
+                        .context_offs = DRA7XX_RM_L4PER_TIMER4_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+/* timer5 */
+static struct omap_hwmod dra7xx_timer5_hwmod = {
+        .name           = "timer5",
+        .class          = &dra7xx_timer_hwmod_class,
+        .clkdm_name     = "ipu_clkdm",
+        .main_clk       = "timer5_gfclk_mux",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = DRA7XX_CM_IPU_TIMER5_CLKCTRL_OFFSET,
+                        .context_offs = DRA7XX_RM_IPU_TIMER5_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+/* timer6 */
+static struct omap_hwmod dra7xx_timer6_hwmod = {
+        .name           = "timer6",
+        .class          = &dra7xx_timer_hwmod_class,
+        .clkdm_name     = "ipu_clkdm",
+        .main_clk       = "timer6_gfclk_mux",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = DRA7XX_CM_IPU_TIMER6_CLKCTRL_OFFSET,
+                        .context_offs = DRA7XX_RM_IPU_TIMER6_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+/* timer7 */
+static struct omap_hwmod dra7xx_timer7_hwmod = {
+        .name           = "timer7",
+        .class          = &dra7xx_timer_hwmod_class,
+        .clkdm_name     = "ipu_clkdm",
+        .main_clk       = "timer7_gfclk_mux",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = DRA7XX_CM_IPU_TIMER7_CLKCTRL_OFFSET,
+                        .context_offs = DRA7XX_RM_IPU_TIMER7_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+/* timer8 */
+static struct omap_hwmod dra7xx_timer8_hwmod = {
+        .name           = "timer8",
+        .class          = &dra7xx_timer_hwmod_class,
+        .clkdm_name     = "ipu_clkdm",
+        .main_clk       = "timer8_gfclk_mux",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = DRA7XX_CM_IPU_TIMER8_CLKCTRL_OFFSET,
+                        .context_offs = DRA7XX_RM_IPU_TIMER8_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+/* timer9 */
+static struct omap_hwmod dra7xx_timer9_hwmod = {
+        .name           = "timer9",
+        .class          = &dra7xx_timer_hwmod_class,
+        .clkdm_name     = "l4per_clkdm",
+        .main_clk       = "timer9_gfclk_mux",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = DRA7XX_CM_L4PER_TIMER9_CLKCTRL_OFFSET,
+                        .context_offs = DRA7XX_RM_L4PER_TIMER9_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+/* timer10 */
+static struct omap_hwmod dra7xx_timer10_hwmod = {
+        .name           = "timer10",
+        .class          = &dra7xx_timer_1ms_hwmod_class,
+        .clkdm_name     = "l4per_clkdm",
+        .main_clk       = "timer10_gfclk_mux",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = DRA7XX_CM_L4PER_TIMER10_CLKCTRL_OFFSET,
+                        .context_offs = DRA7XX_RM_L4PER_TIMER10_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+/* timer11 */
+static struct omap_hwmod dra7xx_timer11_hwmod = {
+        .name           = "timer11",
+        .class          = &dra7xx_timer_hwmod_class,
+        .clkdm_name     = "l4per_clkdm",
+        .main_clk       = "timer11_gfclk_mux",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = DRA7XX_CM_L4PER_TIMER11_CLKCTRL_OFFSET,
+                        .context_offs = DRA7XX_RM_L4PER_TIMER11_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+/*
+ * 'uart' class
+ *
+ */
+
+static struct omap_hwmod_class_sysconfig dra7xx_uart_sysc = {
+        .rev_offs       = 0x0050,
+        .sysc_offs      = 0x0054,
+        .syss_offs      = 0x0058,
+        .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
+                           SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
+                           SYSS_HAS_RESET_STATUS),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+                           SIDLE_SMART_WKUP),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class dra7xx_uart_hwmod_class = {
+        .name   = "uart",
+        .sysc   = &dra7xx_uart_sysc,
+};
+
+/* uart1 */
+static struct omap_hwmod dra7xx_uart1_hwmod = {
+        .name           = "uart1",
+        .class          = &dra7xx_uart_hwmod_class,
+        .clkdm_name     = "l4per_clkdm",
+        .main_clk       = "uart1_gfclk_mux",
+        .flags          = HWMOD_SWSUP_SIDLE_ACT,
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = DRA7XX_CM_L4PER_UART1_CLKCTRL_OFFSET,
+                        .context_offs = DRA7XX_RM_L4PER_UART1_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+/* uart2 */
+static struct omap_hwmod dra7xx_uart2_hwmod = {
+        .name           = "uart2",
+        .class          = &dra7xx_uart_hwmod_class,
+        .clkdm_name     = "l4per_clkdm",
+        .main_clk       = "uart2_gfclk_mux",
+        .flags          = HWMOD_SWSUP_SIDLE_ACT,
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = DRA7XX_CM_L4PER_UART2_CLKCTRL_OFFSET,
+                        .context_offs = DRA7XX_RM_L4PER_UART2_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+/* uart3 */
+static struct omap_hwmod dra7xx_uart3_hwmod = {
+        .name           = "uart3",
+        .class          = &dra7xx_uart_hwmod_class,
+        .clkdm_name     = "l4per_clkdm",
+        .main_clk       = "uart3_gfclk_mux",
+        .flags          = HWMOD_SWSUP_SIDLE_ACT,
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = DRA7XX_CM_L4PER_UART3_CLKCTRL_OFFSET,
+                        .context_offs = DRA7XX_RM_L4PER_UART3_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+/* uart4 */
+static struct omap_hwmod dra7xx_uart4_hwmod = {
+        .name           = "uart4",
+        .class          = &dra7xx_uart_hwmod_class,
+        .clkdm_name     = "l4per_clkdm",
+        .main_clk       = "uart4_gfclk_mux",
+        .flags          = HWMOD_SWSUP_SIDLE_ACT,
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = DRA7XX_CM_L4PER_UART4_CLKCTRL_OFFSET,
+                        .context_offs = DRA7XX_RM_L4PER_UART4_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+/* uart5 */
+static struct omap_hwmod dra7xx_uart5_hwmod = {
+        .name           = "uart5",
+        .class          = &dra7xx_uart_hwmod_class,
+        .clkdm_name     = "l4per_clkdm",
+        .main_clk       = "uart5_gfclk_mux",
+        .flags          = HWMOD_SWSUP_SIDLE_ACT,
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = DRA7XX_CM_L4PER_UART5_CLKCTRL_OFFSET,
+                        .context_offs = DRA7XX_RM_L4PER_UART5_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+/* uart6 */
+static struct omap_hwmod dra7xx_uart6_hwmod = {
+        .name           = "uart6",
+        .class          = &dra7xx_uart_hwmod_class,
+        .clkdm_name     = "ipu_clkdm",
+        .main_clk       = "uart6_gfclk_mux",
+        .flags          = HWMOD_SWSUP_SIDLE_ACT,
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = DRA7XX_CM_IPU_UART6_CLKCTRL_OFFSET,
+                        .context_offs = DRA7XX_RM_IPU_UART6_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+/*
+ * 'usb_otg_ss' class
+ *
+ */
+
+static struct omap_hwmod_class dra7xx_usb_otg_ss_hwmod_class = {
+        .name   = "usb_otg_ss",
+};
+
+/* usb_otg_ss1 */
+static struct omap_hwmod_opt_clk usb_otg_ss1_opt_clks[] = {
+        { .role = "refclk960m", .clk = "usb_otg_ss1_refclk960m" },
+};
+
+static struct omap_hwmod dra7xx_usb_otg_ss1_hwmod = {
+        .name           = "usb_otg_ss1",
+        .class          = &dra7xx_usb_otg_ss_hwmod_class,
+        .clkdm_name     = "l3init_clkdm",
+        .main_clk       = "dpll_core_h13x2_ck",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS1_CLKCTRL_OFFSET,
+                        .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS1_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_HWCTRL,
+                },
+        },
+        .opt_clks       = usb_otg_ss1_opt_clks,
+        .opt_clks_cnt   = ARRAY_SIZE(usb_otg_ss1_opt_clks),
+};
+
+/* usb_otg_ss2 */
+static struct omap_hwmod_opt_clk usb_otg_ss2_opt_clks[] = {
+        { .role = "refclk960m", .clk = "usb_otg_ss2_refclk960m" },
+};
+
+static struct omap_hwmod dra7xx_usb_otg_ss2_hwmod = {
+        .name           = "usb_otg_ss2",
+        .class          = &dra7xx_usb_otg_ss_hwmod_class,
+        .clkdm_name     = "l3init_clkdm",
+        .main_clk       = "dpll_core_h13x2_ck",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS2_CLKCTRL_OFFSET,
+                        .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS2_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_HWCTRL,
+                },
+        },
+        .opt_clks       = usb_otg_ss2_opt_clks,
+        .opt_clks_cnt   = ARRAY_SIZE(usb_otg_ss2_opt_clks),
+};
+
+/* usb_otg_ss3 */
+static struct omap_hwmod dra7xx_usb_otg_ss3_hwmod = {
+        .name           = "usb_otg_ss3",
+        .class          = &dra7xx_usb_otg_ss_hwmod_class,
+        .clkdm_name     = "l3init_clkdm",
+        .main_clk       = "dpll_core_h13x2_ck",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS3_CLKCTRL_OFFSET,
+                        .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS3_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_HWCTRL,
+                },
+        },
+};
+
+/* usb_otg_ss4 */
+static struct omap_hwmod dra7xx_usb_otg_ss4_hwmod = {
+        .name           = "usb_otg_ss4",
+        .class          = &dra7xx_usb_otg_ss_hwmod_class,
+        .clkdm_name     = "l3init_clkdm",
+        .main_clk       = "dpll_core_h13x2_ck",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS4_CLKCTRL_OFFSET,
+                        .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS4_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_HWCTRL,
+                },
+        },
+};
+
+/*
+ * 'vcp' class
+ *
+ */
+
+static struct omap_hwmod_class dra7xx_vcp_hwmod_class = {
+        .name   = "vcp",
+};
+
+/* vcp1 */
+static struct omap_hwmod dra7xx_vcp1_hwmod = {
+        .name           = "vcp1",
+        .class          = &dra7xx_vcp_hwmod_class,
+        .clkdm_name     = "l3main1_clkdm",
+        .main_clk       = "l3_iclk_div",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = DRA7XX_CM_L3MAIN1_VCP1_CLKCTRL_OFFSET,
+                        .context_offs = DRA7XX_RM_L3MAIN1_VCP1_CONTEXT_OFFSET,
+                },
+        },
+};
+
+/* vcp2 */
+static struct omap_hwmod dra7xx_vcp2_hwmod = {
+        .name           = "vcp2",
+        .class          = &dra7xx_vcp_hwmod_class,
+        .clkdm_name     = "l3main1_clkdm",
+        .main_clk       = "l3_iclk_div",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = DRA7XX_CM_L3MAIN1_VCP2_CLKCTRL_OFFSET,
+                        .context_offs = DRA7XX_RM_L3MAIN1_VCP2_CONTEXT_OFFSET,
+                },
+        },
+};
+
+/*
+ * 'wd_timer' class
+ *
+ */
+
+static struct omap_hwmod_class_sysconfig dra7xx_wd_timer_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        .syss_offs      = 0x0014,
+        .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
+                           SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+                           SIDLE_SMART_WKUP),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class dra7xx_wd_timer_hwmod_class = {
+        .name           = "wd_timer",
+        .sysc           = &dra7xx_wd_timer_sysc,
+        .pre_shutdown   = &omap2_wd_timer_disable,
+        .reset          = &omap2_wd_timer_reset,
+};
+
+/* wd_timer2 */
+static struct omap_hwmod dra7xx_wd_timer2_hwmod = {
+        .name           = "wd_timer2",
+        .class          = &dra7xx_wd_timer_hwmod_class,
+        .clkdm_name     = "wkupaon_clkdm",
+        .main_clk       = "sys_32k_ck",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = DRA7XX_CM_WKUPAON_WD_TIMER2_CLKCTRL_OFFSET,
+                        .context_offs = DRA7XX_RM_WKUPAON_WD_TIMER2_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+
+/*
+ * Interfaces
+ */
+
+/* l3_main_2 -> l3_instr */
+static struct omap_hwmod_ocp_if dra7xx_l3_main_2__l3_instr = {
+        .master         = &dra7xx_l3_main_2_hwmod,
+        .slave          = &dra7xx_l3_instr_hwmod,
+        .clk            = "l3_iclk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_cfg -> l3_main_1 */
+static struct omap_hwmod_ocp_if dra7xx_l4_cfg__l3_main_1 = {
+        .master         = &dra7xx_l4_cfg_hwmod,
+        .slave          = &dra7xx_l3_main_1_hwmod,
+        .clk            = "l3_iclk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* mpu -> l3_main_1 */
+static struct omap_hwmod_ocp_if dra7xx_mpu__l3_main_1 = {
+        .master         = &dra7xx_mpu_hwmod,
+        .slave          = &dra7xx_l3_main_1_hwmod,
+        .clk            = "l3_iclk_div",
+        .user           = OCP_USER_MPU,
+};
+
+/* l3_main_1 -> l3_main_2 */
+static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l3_main_2 = {
+        .master         = &dra7xx_l3_main_1_hwmod,
+        .slave          = &dra7xx_l3_main_2_hwmod,
+        .clk            = "l3_iclk_div",
+        .user           = OCP_USER_MPU,
+};
+
+/* l4_cfg -> l3_main_2 */
+static struct omap_hwmod_ocp_if dra7xx_l4_cfg__l3_main_2 = {
+        .master         = &dra7xx_l4_cfg_hwmod,
+        .slave          = &dra7xx_l3_main_2_hwmod,
+        .clk            = "l3_iclk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l3_main_1 -> l4_cfg */
+static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_cfg = {
+        .master         = &dra7xx_l3_main_1_hwmod,
+        .slave          = &dra7xx_l4_cfg_hwmod,
+        .clk            = "l3_iclk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l3_main_1 -> l4_per1 */
+static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per1 = {
+        .master         = &dra7xx_l3_main_1_hwmod,
+        .slave          = &dra7xx_l4_per1_hwmod,
+        .clk            = "l3_iclk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l3_main_1 -> l4_per2 */
+static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per2 = {
+        .master         = &dra7xx_l3_main_1_hwmod,
+        .slave          = &dra7xx_l4_per2_hwmod,
+        .clk            = "l3_iclk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l3_main_1 -> l4_per3 */
+static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per3 = {
+        .master         = &dra7xx_l3_main_1_hwmod,
+        .slave          = &dra7xx_l4_per3_hwmod,
+        .clk            = "l3_iclk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l3_main_1 -> l4_wkup */
+static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_wkup = {
+        .master         = &dra7xx_l3_main_1_hwmod,
+        .slave          = &dra7xx_l4_wkup_hwmod,
+        .clk            = "wkupaon_iclk_mux",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per2 -> atl */
+static struct omap_hwmod_ocp_if dra7xx_l4_per2__atl = {
+        .master         = &dra7xx_l4_per2_hwmod,
+        .slave          = &dra7xx_atl_hwmod,
+        .clk            = "l3_iclk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l3_main_1 -> bb2d */
+static struct omap_hwmod_ocp_if dra7xx_l3_main_1__bb2d = {
+        .master         = &dra7xx_l3_main_1_hwmod,
+        .slave          = &dra7xx_bb2d_hwmod,
+        .clk            = "l3_iclk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_wkup -> counter_32k */
+static struct omap_hwmod_ocp_if dra7xx_l4_wkup__counter_32k = {
+        .master         = &dra7xx_l4_wkup_hwmod,
+        .slave          = &dra7xx_counter_32k_hwmod,
+        .clk            = "wkupaon_iclk_mux",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_wkup -> ctrl_module_wkup */
+static struct omap_hwmod_ocp_if dra7xx_l4_wkup__ctrl_module_wkup = {
+        .master         = &dra7xx_l4_wkup_hwmod,
+        .slave          = &dra7xx_ctrl_module_wkup_hwmod,
+        .clk            = "wkupaon_iclk_mux",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_wkup -> dcan1 */
+static struct omap_hwmod_ocp_if dra7xx_l4_wkup__dcan1 = {
+        .master         = &dra7xx_l4_wkup_hwmod,
+        .slave          = &dra7xx_dcan1_hwmod,
+        .clk            = "wkupaon_iclk_mux",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per2 -> dcan2 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per2__dcan2 = {
+        .master         = &dra7xx_l4_per2_hwmod,
+        .slave          = &dra7xx_dcan2_hwmod,
+        .clk            = "l3_iclk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space dra7xx_dma_system_addrs[] = {
+        {
+                .pa_start       = 0x4a056000,
+                .pa_end         = 0x4a056fff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+/* l4_cfg -> dma_system */
+static struct omap_hwmod_ocp_if dra7xx_l4_cfg__dma_system = {
+        .master         = &dra7xx_l4_cfg_hwmod,
+        .slave          = &dra7xx_dma_system_hwmod,
+        .clk            = "l3_iclk_div",
+        .addr           = dra7xx_dma_system_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space dra7xx_dss_addrs[] = {
+        {
+                .name           = "family",
+                .pa_start       = 0x58000000,
+                .pa_end         = 0x5800007f,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l3_main_1 -> dss */
+static struct omap_hwmod_ocp_if dra7xx_l3_main_1__dss = {
+        .master         = &dra7xx_l3_main_1_hwmod,
+        .slave          = &dra7xx_dss_hwmod,
+        .clk            = "l3_iclk_div",
+        .addr           = dra7xx_dss_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space dra7xx_dss_dispc_addrs[] = {
+        {
+                .name           = "dispc",
+                .pa_start       = 0x58001000,
+                .pa_end         = 0x58001fff,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l3_main_1 -> dispc */
+static struct omap_hwmod_ocp_if dra7xx_l3_main_1__dispc = {
+        .master         = &dra7xx_l3_main_1_hwmod,
+        .slave          = &dra7xx_dss_dispc_hwmod,
+        .clk            = "l3_iclk_div",
+        .addr           = dra7xx_dss_dispc_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space dra7xx_dss_hdmi_addrs[] = {
+        {
+                .name           = "hdmi_wp",
+                .pa_start       = 0x58040000,
+                .pa_end         = 0x580400ff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+/* l3_main_1 -> dispc */
+static struct omap_hwmod_ocp_if dra7xx_l3_main_1__hdmi = {
+        .master         = &dra7xx_l3_main_1_hwmod,
+        .slave          = &dra7xx_dss_hdmi_hwmod,
+        .clk            = "l3_iclk_div",
+        .addr           = dra7xx_dss_hdmi_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space dra7xx_elm_addrs[] = {
+        {
+                .pa_start       = 0x48078000,
+                .pa_end         = 0x48078fff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+/* l4_per1 -> elm */
+static struct omap_hwmod_ocp_if dra7xx_l4_per1__elm = {
+        .master         = &dra7xx_l4_per1_hwmod,
+        .slave          = &dra7xx_elm_hwmod,
+        .clk            = "l3_iclk_div",
+        .addr           = dra7xx_elm_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_wkup -> gpio1 */
+static struct omap_hwmod_ocp_if dra7xx_l4_wkup__gpio1 = {
+        .master         = &dra7xx_l4_wkup_hwmod,
+        .slave          = &dra7xx_gpio1_hwmod,
+        .clk            = "wkupaon_iclk_mux",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per1 -> gpio2 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio2 = {
+        .master         = &dra7xx_l4_per1_hwmod,
+        .slave          = &dra7xx_gpio2_hwmod,
+        .clk            = "l3_iclk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per1 -> gpio3 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio3 = {
+        .master         = &dra7xx_l4_per1_hwmod,
+        .slave          = &dra7xx_gpio3_hwmod,
+        .clk            = "l3_iclk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per1 -> gpio4 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio4 = {
+        .master         = &dra7xx_l4_per1_hwmod,
+        .slave          = &dra7xx_gpio4_hwmod,
+        .clk            = "l3_iclk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per1 -> gpio5 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio5 = {
+        .master         = &dra7xx_l4_per1_hwmod,
+        .slave          = &dra7xx_gpio5_hwmod,
+        .clk            = "l3_iclk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per1 -> gpio6 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio6 = {
+        .master         = &dra7xx_l4_per1_hwmod,
+        .slave          = &dra7xx_gpio6_hwmod,
+        .clk            = "l3_iclk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per1 -> gpio7 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio7 = {
+        .master         = &dra7xx_l4_per1_hwmod,
+        .slave          = &dra7xx_gpio7_hwmod,
+        .clk            = "l3_iclk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per1 -> gpio8 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio8 = {
+        .master         = &dra7xx_l4_per1_hwmod,
+        .slave          = &dra7xx_gpio8_hwmod,
+        .clk            = "l3_iclk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space dra7xx_gpmc_addrs[] = {
+        {
+                .pa_start       = 0x50000000,
+                .pa_end         = 0x500003ff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+/* l3_main_1 -> gpmc */
+static struct omap_hwmod_ocp_if dra7xx_l3_main_1__gpmc = {
+        .master         = &dra7xx_l3_main_1_hwmod,
+        .slave          = &dra7xx_gpmc_hwmod,
+        .clk            = "l3_iclk_div",
+        .addr           = dra7xx_gpmc_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space dra7xx_hdq1w_addrs[] = {
+        {
+                .pa_start       = 0x480b2000,
+                .pa_end         = 0x480b201f,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+/* l4_per1 -> hdq1w */
+static struct omap_hwmod_ocp_if dra7xx_l4_per1__hdq1w = {
+        .master         = &dra7xx_l4_per1_hwmod,
+        .slave          = &dra7xx_hdq1w_hwmod,
+        .clk            = "l3_iclk_div",
+        .addr           = dra7xx_hdq1w_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per1 -> i2c1 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c1 = {
+        .master         = &dra7xx_l4_per1_hwmod,
+        .slave          = &dra7xx_i2c1_hwmod,
+        .clk            = "l3_iclk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per1 -> i2c2 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c2 = {
+        .master         = &dra7xx_l4_per1_hwmod,
+        .slave          = &dra7xx_i2c2_hwmod,
+        .clk            = "l3_iclk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per1 -> i2c3 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c3 = {
+        .master         = &dra7xx_l4_per1_hwmod,
+        .slave          = &dra7xx_i2c3_hwmod,
+        .clk            = "l3_iclk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per1 -> i2c4 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c4 = {
+        .master         = &dra7xx_l4_per1_hwmod,
+        .slave          = &dra7xx_i2c4_hwmod,
+        .clk            = "l3_iclk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per1 -> i2c5 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c5 = {
+        .master         = &dra7xx_l4_per1_hwmod,
+        .slave          = &dra7xx_i2c5_hwmod,
+        .clk            = "l3_iclk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per1 -> mcspi1 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi1 = {
+        .master         = &dra7xx_l4_per1_hwmod,
+        .slave          = &dra7xx_mcspi1_hwmod,
+        .clk            = "l3_iclk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per1 -> mcspi2 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi2 = {
+        .master         = &dra7xx_l4_per1_hwmod,
+        .slave          = &dra7xx_mcspi2_hwmod,
+        .clk            = "l3_iclk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per1 -> mcspi3 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi3 = {
+        .master         = &dra7xx_l4_per1_hwmod,
+        .slave          = &dra7xx_mcspi3_hwmod,
+        .clk            = "l3_iclk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per1 -> mcspi4 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi4 = {
+        .master         = &dra7xx_l4_per1_hwmod,
+        .slave          = &dra7xx_mcspi4_hwmod,
+        .clk            = "l3_iclk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per1 -> mmc1 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc1 = {
+        .master         = &dra7xx_l4_per1_hwmod,
+        .slave          = &dra7xx_mmc1_hwmod,
+        .clk            = "l3_iclk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per1 -> mmc2 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc2 = {
+        .master         = &dra7xx_l4_per1_hwmod,
+        .slave          = &dra7xx_mmc2_hwmod,
+        .clk            = "l3_iclk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per1 -> mmc3 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc3 = {
+        .master         = &dra7xx_l4_per1_hwmod,
+        .slave          = &dra7xx_mmc3_hwmod,
+        .clk            = "l3_iclk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per1 -> mmc4 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc4 = {
+        .master         = &dra7xx_l4_per1_hwmod,
+        .slave          = &dra7xx_mmc4_hwmod,
+        .clk            = "l3_iclk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_cfg -> mpu */
+static struct omap_hwmod_ocp_if dra7xx_l4_cfg__mpu = {
+        .master         = &dra7xx_l4_cfg_hwmod,
+        .slave          = &dra7xx_mpu_hwmod,
+        .clk            = "l3_iclk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space dra7xx_ocp2scp1_addrs[] = {
+        {
+                .pa_start       = 0x4a080000,
+                .pa_end         = 0x4a08001f,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+/* l4_cfg -> ocp2scp1 */
+static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp1 = {
+        .master         = &dra7xx_l4_cfg_hwmod,
+        .slave          = &dra7xx_ocp2scp1_hwmod,
+        .clk            = "l4_root_clk_div",
+        .addr           = dra7xx_ocp2scp1_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space dra7xx_qspi_addrs[] = {
+        {
+                .pa_start       = 0x4b300000,
+                .pa_end         = 0x4b30007f,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+/* l3_main_1 -> qspi */
+static struct omap_hwmod_ocp_if dra7xx_l3_main_1__qspi = {
+        .master         = &dra7xx_l3_main_1_hwmod,
+        .slave          = &dra7xx_qspi_hwmod,
+        .clk            = "l3_iclk_div",
+        .addr           = dra7xx_qspi_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space dra7xx_sata_addrs[] = {
+        {
+                .name           = "sysc",
+                .pa_start       = 0x4a141100,
+                .pa_end         = 0x4a141107,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+/* l4_cfg -> sata */
+static struct omap_hwmod_ocp_if dra7xx_l4_cfg__sata = {
+        .master         = &dra7xx_l4_cfg_hwmod,
+        .slave          = &dra7xx_sata_hwmod,
+        .clk            = "l3_iclk_div",
+        .addr           = dra7xx_sata_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space dra7xx_smartreflex_core_addrs[] = {
+        {
+                .pa_start       = 0x4a0dd000,
+                .pa_end         = 0x4a0dd07f,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+/* l4_cfg -> smartreflex_core */
+static struct omap_hwmod_ocp_if dra7xx_l4_cfg__smartreflex_core = {
+        .master         = &dra7xx_l4_cfg_hwmod,
+        .slave          = &dra7xx_smartreflex_core_hwmod,
+        .clk            = "l4_root_clk_div",
+        .addr           = dra7xx_smartreflex_core_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space dra7xx_smartreflex_mpu_addrs[] = {
+        {
+                .pa_start       = 0x4a0d9000,
+                .pa_end         = 0x4a0d907f,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+/* l4_cfg -> smartreflex_mpu */
+static struct omap_hwmod_ocp_if dra7xx_l4_cfg__smartreflex_mpu = {
+        .master         = &dra7xx_l4_cfg_hwmod,
+        .slave          = &dra7xx_smartreflex_mpu_hwmod,
+        .clk            = "l4_root_clk_div",
+        .addr           = dra7xx_smartreflex_mpu_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space dra7xx_spinlock_addrs[] = {
+        {
+                .pa_start       = 0x4a0f6000,
+                .pa_end         = 0x4a0f6fff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+/* l4_cfg -> spinlock */
+static struct omap_hwmod_ocp_if dra7xx_l4_cfg__spinlock = {
+        .master         = &dra7xx_l4_cfg_hwmod,
+        .slave          = &dra7xx_spinlock_hwmod,
+        .clk            = "l3_iclk_div",
+        .addr           = dra7xx_spinlock_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_wkup -> timer1 */
+static struct omap_hwmod_ocp_if dra7xx_l4_wkup__timer1 = {
+        .master         = &dra7xx_l4_wkup_hwmod,
+        .slave          = &dra7xx_timer1_hwmod,
+        .clk            = "wkupaon_iclk_mux",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per1 -> timer2 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer2 = {
+        .master         = &dra7xx_l4_per1_hwmod,
+        .slave          = &dra7xx_timer2_hwmod,
+        .clk            = "l3_iclk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per1 -> timer3 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer3 = {
+        .master         = &dra7xx_l4_per1_hwmod,
+        .slave          = &dra7xx_timer3_hwmod,
+        .clk            = "l3_iclk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per1 -> timer4 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer4 = {
+        .master         = &dra7xx_l4_per1_hwmod,
+        .slave          = &dra7xx_timer4_hwmod,
+        .clk            = "l3_iclk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per3 -> timer5 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer5 = {
+        .master         = &dra7xx_l4_per3_hwmod,
+        .slave          = &dra7xx_timer5_hwmod,
+        .clk            = "l3_iclk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per3 -> timer6 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer6 = {
+        .master         = &dra7xx_l4_per3_hwmod,
+        .slave          = &dra7xx_timer6_hwmod,
+        .clk            = "l3_iclk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per3 -> timer7 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer7 = {
+        .master         = &dra7xx_l4_per3_hwmod,
+        .slave          = &dra7xx_timer7_hwmod,
+        .clk            = "l3_iclk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per3 -> timer8 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer8 = {
+        .master         = &dra7xx_l4_per3_hwmod,
+        .slave          = &dra7xx_timer8_hwmod,
+        .clk            = "l3_iclk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per1 -> timer9 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer9 = {
+        .master         = &dra7xx_l4_per1_hwmod,
+        .slave          = &dra7xx_timer9_hwmod,
+        .clk            = "l3_iclk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per1 -> timer10 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer10 = {
+        .master         = &dra7xx_l4_per1_hwmod,
+        .slave          = &dra7xx_timer10_hwmod,
+        .clk            = "l3_iclk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per1 -> timer11 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer11 = {
+        .master         = &dra7xx_l4_per1_hwmod,
+        .slave          = &dra7xx_timer11_hwmod,
+        .clk            = "l3_iclk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per1 -> uart1 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart1 = {
+        .master         = &dra7xx_l4_per1_hwmod,
+        .slave          = &dra7xx_uart1_hwmod,
+        .clk            = "l3_iclk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per1 -> uart2 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart2 = {
+        .master         = &dra7xx_l4_per1_hwmod,
+        .slave          = &dra7xx_uart2_hwmod,
+        .clk            = "l3_iclk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per1 -> uart3 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart3 = {
+        .master         = &dra7xx_l4_per1_hwmod,
+        .slave          = &dra7xx_uart3_hwmod,
+        .clk            = "l3_iclk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per1 -> uart4 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart4 = {
+        .master         = &dra7xx_l4_per1_hwmod,
+        .slave          = &dra7xx_uart4_hwmod,
+        .clk            = "l3_iclk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per1 -> uart5 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart5 = {
+        .master         = &dra7xx_l4_per1_hwmod,
+        .slave          = &dra7xx_uart5_hwmod,
+        .clk            = "l3_iclk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per1 -> uart6 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart6 = {
+        .master         = &dra7xx_l4_per1_hwmod,
+        .slave          = &dra7xx_uart6_hwmod,
+        .clk            = "l3_iclk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per3 -> usb_otg_ss1 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss1 = {
+        .master         = &dra7xx_l4_per3_hwmod,
+        .slave          = &dra7xx_usb_otg_ss1_hwmod,
+        .clk            = "dpll_core_h13x2_ck",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per3 -> usb_otg_ss2 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss2 = {
+        .master         = &dra7xx_l4_per3_hwmod,
+        .slave          = &dra7xx_usb_otg_ss2_hwmod,
+        .clk            = "dpll_core_h13x2_ck",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per3 -> usb_otg_ss3 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss3 = {
+        .master         = &dra7xx_l4_per3_hwmod,
+        .slave          = &dra7xx_usb_otg_ss3_hwmod,
+        .clk            = "dpll_core_h13x2_ck",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per3 -> usb_otg_ss4 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss4 = {
+        .master         = &dra7xx_l4_per3_hwmod,
+        .slave          = &dra7xx_usb_otg_ss4_hwmod,
+        .clk            = "dpll_core_h13x2_ck",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l3_main_1 -> vcp1 */
+static struct omap_hwmod_ocp_if dra7xx_l3_main_1__vcp1 = {
+        .master         = &dra7xx_l3_main_1_hwmod,
+        .slave          = &dra7xx_vcp1_hwmod,
+        .clk            = "l3_iclk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per2 -> vcp1 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per2__vcp1 = {
+        .master         = &dra7xx_l4_per2_hwmod,
+        .slave          = &dra7xx_vcp1_hwmod,
+        .clk            = "l3_iclk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l3_main_1 -> vcp2 */
+static struct omap_hwmod_ocp_if dra7xx_l3_main_1__vcp2 = {
+        .master         = &dra7xx_l3_main_1_hwmod,
+        .slave          = &dra7xx_vcp2_hwmod,
+        .clk            = "l3_iclk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per2 -> vcp2 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per2__vcp2 = {
+        .master         = &dra7xx_l4_per2_hwmod,
+        .slave          = &dra7xx_vcp2_hwmod,
+        .clk            = "l3_iclk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_wkup -> wd_timer2 */
+static struct omap_hwmod_ocp_if dra7xx_l4_wkup__wd_timer2 = {
+        .master         = &dra7xx_l4_wkup_hwmod,
+        .slave          = &dra7xx_wd_timer2_hwmod,
+        .clk            = "wkupaon_iclk_mux",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = {
+        &dra7xx_l3_main_2__l3_instr,
+        &dra7xx_l4_cfg__l3_main_1,
+        &dra7xx_mpu__l3_main_1,
+        &dra7xx_l3_main_1__l3_main_2,
+        &dra7xx_l4_cfg__l3_main_2,
+        &dra7xx_l3_main_1__l4_cfg,
+        &dra7xx_l3_main_1__l4_per1,
+        &dra7xx_l3_main_1__l4_per2,
+        &dra7xx_l3_main_1__l4_per3,
+        &dra7xx_l3_main_1__l4_wkup,
+        &dra7xx_l4_per2__atl,
+        &dra7xx_l3_main_1__bb2d,
+        &dra7xx_l4_wkup__counter_32k,
+        &dra7xx_l4_wkup__ctrl_module_wkup,
+        &dra7xx_l4_wkup__dcan1,
+        &dra7xx_l4_per2__dcan2,
+        &dra7xx_l4_cfg__dma_system,
+        &dra7xx_l3_main_1__dss,
+        &dra7xx_l3_main_1__dispc,
+        &dra7xx_l3_main_1__hdmi,
+        &dra7xx_l4_per1__elm,
+        &dra7xx_l4_wkup__gpio1,
+        &dra7xx_l4_per1__gpio2,
+        &dra7xx_l4_per1__gpio3,
+        &dra7xx_l4_per1__gpio4,
+        &dra7xx_l4_per1__gpio5,
+        &dra7xx_l4_per1__gpio6,
+        &dra7xx_l4_per1__gpio7,
+        &dra7xx_l4_per1__gpio8,
+        &dra7xx_l3_main_1__gpmc,
+        &dra7xx_l4_per1__hdq1w,
+        &dra7xx_l4_per1__i2c1,
+        &dra7xx_l4_per1__i2c2,
+        &dra7xx_l4_per1__i2c3,
+        &dra7xx_l4_per1__i2c4,
+        &dra7xx_l4_per1__i2c5,
+        &dra7xx_l4_per1__mcspi1,
+        &dra7xx_l4_per1__mcspi2,
+        &dra7xx_l4_per1__mcspi3,
+        &dra7xx_l4_per1__mcspi4,
+        &dra7xx_l4_per1__mmc1,
+        &dra7xx_l4_per1__mmc2,
+        &dra7xx_l4_per1__mmc3,
+        &dra7xx_l4_per1__mmc4,
+        &dra7xx_l4_cfg__mpu,
+        &dra7xx_l4_cfg__ocp2scp1,
+        &dra7xx_l3_main_1__qspi,
+        &dra7xx_l4_cfg__sata,
+        &dra7xx_l4_cfg__smartreflex_core,
+        &dra7xx_l4_cfg__smartreflex_mpu,
+        &dra7xx_l4_cfg__spinlock,
+        &dra7xx_l4_wkup__timer1,
+        &dra7xx_l4_per1__timer2,
+        &dra7xx_l4_per1__timer3,
+        &dra7xx_l4_per1__timer4,
+        &dra7xx_l4_per3__timer5,
+        &dra7xx_l4_per3__timer6,
+        &dra7xx_l4_per3__timer7,
+        &dra7xx_l4_per3__timer8,
+        &dra7xx_l4_per1__timer9,
+        &dra7xx_l4_per1__timer10,
+        &dra7xx_l4_per1__timer11,
+        &dra7xx_l4_per1__uart1,
+        &dra7xx_l4_per1__uart2,
+        &dra7xx_l4_per1__uart3,
+        &dra7xx_l4_per1__uart4,
+        &dra7xx_l4_per1__uart5,
+        &dra7xx_l4_per1__uart6,
+        &dra7xx_l4_per3__usb_otg_ss1,
+        &dra7xx_l4_per3__usb_otg_ss2,
+        &dra7xx_l4_per3__usb_otg_ss3,
+        &dra7xx_l4_per3__usb_otg_ss4,
+        &dra7xx_l3_main_1__vcp1,
+        &dra7xx_l4_per2__vcp1,
+        &dra7xx_l3_main_1__vcp2,
+        &dra7xx_l4_per2__vcp2,
+        &dra7xx_l4_wkup__wd_timer2,
+        NULL,
+};
+
+int __init dra7xx_hwmod_init(void)
+{
+        omap_hwmod_init();
+        return omap_hwmod_register_links(dra7xx_hwmod_ocp_ifs);
+}
diff --git a/arch/arm/mach-omap2/powerdomain.h b/arch/arm/mach-omap2/powerdomain.h
index e4d7bd6f94b8..baf3d8bf6bea 100644
--- a/arch/arm/mach-omap2/powerdomain.h
+++ b/arch/arm/mach-omap2/powerdomain.h
@@ -256,6 +256,7 @@ extern void omap3xxx_powerdomains_init(void);
 extern void am33xx_powerdomains_init(void);
 extern void omap44xx_powerdomains_init(void);
 extern void omap54xx_powerdomains_init(void);
+extern void dra7xx_powerdomains_init(void);
 
 extern struct pwrdm_ops omap2_pwrdm_operations;
 extern struct pwrdm_ops omap3_pwrdm_operations;
diff --git a/arch/arm/mach-omap2/powerdomains3xxx_data.c b/arch/arm/mach-omap2/powerdomains3xxx_data.c
index e2d4bd804523..328c1037cb60 100644
--- a/arch/arm/mach-omap2/powerdomains3xxx_data.c
+++ b/arch/arm/mach-omap2/powerdomains3xxx_data.c
@@ -336,6 +336,13 @@ static struct powerdomain dpll5_pwrdm = {
         .voltdm           = { .name = "core" },
 };
 
+static struct powerdomain alwon_81xx_pwrdm = {
+        .name             = "alwon_pwrdm",
+        .prcm_offs        = TI81XX_PRM_ALWON_MOD,
+        .pwrsts           = PWRSTS_OFF_ON,
+        .voltdm           = { .name = "core" },
+};
+
 static struct powerdomain device_81xx_pwrdm = {
         .name             = "device_pwrdm",
         .prcm_offs        = TI81XX_PRM_DEVICE_MOD,
@@ -442,6 +449,7 @@ static struct powerdomain *powerdomains_am35x[] __initdata = {
 };
 
 static struct powerdomain *powerdomains_ti81xx[] __initdata = {
+        &alwon_81xx_pwrdm,
         &device_81xx_pwrdm,
         &active_816x_pwrdm,
         &default_816x_pwrdm,
diff --git a/arch/arm/mach-omap2/powerdomains7xx_data.c b/arch/arm/mach-omap2/powerdomains7xx_data.c
new file mode 100644
index 000000000000..48151d1cfde0
--- /dev/null
+++ b/arch/arm/mach-omap2/powerdomains7xx_data.c
@@ -0,0 +1,454 @@
+/*
+ * DRA7xx Power domains framework
+ *
+ * Copyright (C) 2009-2013 Texas Instruments, Inc.
+ * Copyright (C) 2009-2011 Nokia Corporation
+ *
+ * Generated by code originally written by:
+ * Abhijit Pagare (abhijitpagare@ti.com)
+ * Benoit Cousson (b-cousson@ti.com)
+ * Paul Walmsley (paul@pwsan.com)
+ *
+ * This file is automatically generated from the OMAP hardware databases.
+ * We respectfully ask that any modifications to this file be coordinated
+ * with the public linux-omap@vger.kernel.org mailing list and the
+ * authors above to ensure that the autogeneration scripts are kept
+ * up-to-date with the file contents.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+
+#include "powerdomain.h"
+
+#include "prcm-common.h"
+#include "prcm44xx.h"
+#include "prm7xx.h"
+#include "prcm_mpu7xx.h"
+
+/* iva_7xx_pwrdm: IVA-HD power domain */
+static struct powerdomain iva_7xx_pwrdm = {
+        .name             = "iva_pwrdm",
+        .prcm_offs        = DRA7XX_PRM_IVA_INST,
+        .prcm_partition   = DRA7XX_PRM_PARTITION,
+        .pwrsts           = PWRSTS_OFF_RET_ON,
+        .pwrsts_logic_ret = PWRSTS_OFF,
+        .banks            = 4,
+        .pwrsts_mem_ret = {
+                [0] = PWRSTS_OFF_RET,   /* hwa_mem */
+                [1] = PWRSTS_OFF_RET,   /* sl2_mem */
+                [2] = PWRSTS_OFF_RET,   /* tcm1_mem */
+                [3] = PWRSTS_OFF_RET,   /* tcm2_mem */
+        },
+        .pwrsts_mem_on  = {
+                [0] = PWRSTS_OFF_RET,   /* hwa_mem */
+                [1] = PWRSTS_OFF_RET,   /* sl2_mem */
+                [2] = PWRSTS_OFF_RET,   /* tcm1_mem */
+                [3] = PWRSTS_OFF_RET,   /* tcm2_mem */
+        },
+        .flags            = PWRDM_HAS_LOWPOWERSTATECHANGE,
+};
+
+/* rtc_7xx_pwrdm:  */
+static struct powerdomain rtc_7xx_pwrdm = {
+        .name             = "rtc_pwrdm",
+        .prcm_offs        = DRA7XX_PRM_RTC_INST,
+        .prcm_partition   = DRA7XX_PRM_PARTITION,
+        .pwrsts           = PWRSTS_ON,
+};
+
+/* custefuse_7xx_pwrdm: Customer efuse controller power domain */
+static struct powerdomain custefuse_7xx_pwrdm = {
+        .name             = "custefuse_pwrdm",
+        .prcm_offs        = DRA7XX_PRM_CUSTEFUSE_INST,
+        .prcm_partition   = DRA7XX_PRM_PARTITION,
+        .pwrsts           = PWRSTS_OFF_ON,
+        .flags            = PWRDM_HAS_LOWPOWERSTATECHANGE,
+};
+
+/* ipu_7xx_pwrdm: Audio back end power domain */
+static struct powerdomain ipu_7xx_pwrdm = {
+        .name             = "ipu_pwrdm",
+        .prcm_offs        = DRA7XX_PRM_IPU_INST,
+        .prcm_partition   = DRA7XX_PRM_PARTITION,
+        .pwrsts           = PWRSTS_OFF_RET_ON,
+        .pwrsts_logic_ret = PWRSTS_OFF,
+        .banks            = 2,
+        .pwrsts_mem_ret = {
+                [0] = PWRSTS_OFF_RET,   /* aessmem */
+                [1] = PWRSTS_OFF_RET,   /* periphmem */
+        },
+        .pwrsts_mem_on  = {
+                [0] = PWRSTS_OFF_RET,   /* aessmem */
+                [1] = PWRSTS_OFF_RET,   /* periphmem */
+        },
+        .flags            = PWRDM_HAS_LOWPOWERSTATECHANGE,
+};
+
+/* dss_7xx_pwrdm: Display subsystem power domain */
+static struct powerdomain dss_7xx_pwrdm = {
+        .name             = "dss_pwrdm",
+        .prcm_offs        = DRA7XX_PRM_DSS_INST,
+        .prcm_partition   = DRA7XX_PRM_PARTITION,
+        .pwrsts           = PWRSTS_OFF_RET_ON,
+        .pwrsts_logic_ret = PWRSTS_OFF,
+        .banks            = 1,
+        .pwrsts_mem_ret = {
+                [0] = PWRSTS_OFF_RET,   /* dss_mem */
+        },
+        .pwrsts_mem_on  = {
+                [0] = PWRSTS_OFF_RET,   /* dss_mem */
+        },
+        .flags            = PWRDM_HAS_LOWPOWERSTATECHANGE,
+};
+
+/* l4per_7xx_pwrdm: Target peripherals power domain */
+static struct powerdomain l4per_7xx_pwrdm = {
+        .name             = "l4per_pwrdm",
+        .prcm_offs        = DRA7XX_PRM_L4PER_INST,
+        .prcm_partition   = DRA7XX_PRM_PARTITION,
+        .pwrsts           = PWRSTS_RET_ON,
+        .pwrsts_logic_ret = PWRSTS_OFF_RET,
+        .banks            = 2,
+        .pwrsts_mem_ret = {
+                [0] = PWRSTS_OFF_RET,   /* nonretained_bank */
+                [1] = PWRSTS_OFF_RET,   /* retained_bank */
+        },
+        .pwrsts_mem_on  = {
+                [0] = PWRSTS_OFF_RET,   /* nonretained_bank */
+                [1] = PWRSTS_OFF_RET,   /* retained_bank */
+        },
+        .flags            = PWRDM_HAS_LOWPOWERSTATECHANGE,
+};
+
+/* gpu_7xx_pwrdm: 3D accelerator power domain */
+static struct powerdomain gpu_7xx_pwrdm = {
+        .name             = "gpu_pwrdm",
+        .prcm_offs        = DRA7XX_PRM_GPU_INST,
+        .prcm_partition   = DRA7XX_PRM_PARTITION,
+        .pwrsts           = PWRSTS_OFF_ON,
+        .banks            = 1,
+        .pwrsts_mem_ret = {
+                [0] = PWRSTS_OFF_RET,   /* gpu_mem */
+        },
+        .pwrsts_mem_on  = {
+                [0] = PWRSTS_OFF_RET,   /* gpu_mem */
+        },
+        .flags            = PWRDM_HAS_LOWPOWERSTATECHANGE,
+};
+
+/* wkupaon_7xx_pwrdm: Wake-up power domain */
+static struct powerdomain wkupaon_7xx_pwrdm = {
+        .name             = "wkupaon_pwrdm",
+        .prcm_offs        = DRA7XX_PRM_WKUPAON_INST,
+        .prcm_partition   = DRA7XX_PRM_PARTITION,
+        .pwrsts           = PWRSTS_ON,
+        .banks            = 1,
+        .pwrsts_mem_ret = {
+        },
+        .pwrsts_mem_on  = {
+                [0] = PWRSTS_ON,        /* wkup_bank */
+        },
+};
+
+/* core_7xx_pwrdm: CORE power domain */
+static struct powerdomain core_7xx_pwrdm = {
+        .name             = "core_pwrdm",
+        .prcm_offs        = DRA7XX_PRM_CORE_INST,
+        .prcm_partition   = DRA7XX_PRM_PARTITION,
+        .pwrsts           = PWRSTS_RET_ON,
+        .pwrsts_logic_ret = PWRSTS_OFF_RET,
+        .banks            = 5,
+        .pwrsts_mem_ret = {
+                [0] = PWRSTS_OFF_RET,   /* core_nret_bank */
+                [1] = PWRSTS_OFF_RET,   /* core_ocmram */
+                [2] = PWRSTS_OFF_RET,   /* core_other_bank */
+                [3] = PWRSTS_OFF_RET,   /* ipu_l2ram */
+                [4] = PWRSTS_OFF_RET,   /* ipu_unicache */
+        },
+        .pwrsts_mem_on  = {
+                [0] = PWRSTS_OFF_RET,   /* core_nret_bank */
+                [1] = PWRSTS_OFF_RET,   /* core_ocmram */
+                [2] = PWRSTS_OFF_RET,   /* core_other_bank */
+                [3] = PWRSTS_OFF_RET,   /* ipu_l2ram */
+                [4] = PWRSTS_OFF_RET,   /* ipu_unicache */
+        },
+        .flags            = PWRDM_HAS_LOWPOWERSTATECHANGE,
+};
+
+/* coreaon_7xx_pwrdm: Always ON logic that sits in VDD_CORE voltage domain */
+static struct powerdomain coreaon_7xx_pwrdm = {
+        .name             = "coreaon_pwrdm",
+        .prcm_offs        = DRA7XX_PRM_COREAON_INST,
+        .prcm_partition   = DRA7XX_PRM_PARTITION,
+        .pwrsts           = PWRSTS_ON,
+};
+
+/* cpu0_7xx_pwrdm: MPU0 processor and Neon coprocessor power domain */
+static struct powerdomain cpu0_7xx_pwrdm = {
+        .name             = "cpu0_pwrdm",
+        .prcm_offs        = DRA7XX_MPU_PRCM_PRM_C0_INST,
+        .prcm_partition   = DRA7XX_MPU_PRCM_PARTITION,
+        .pwrsts           = PWRSTS_OFF_RET_ON,
+        .pwrsts_logic_ret = PWRSTS_OFF_RET,
+        .banks            = 1,
+        .pwrsts_mem_ret = {
+                [0] = PWRSTS_OFF_RET,   /* cpu0_l1 */
+        },
+        .pwrsts_mem_on  = {
+                [0] = PWRSTS_ON,        /* cpu0_l1 */
+        },
+};
+
+/* cpu1_7xx_pwrdm: MPU1 processor and Neon coprocessor power domain */
+static struct powerdomain cpu1_7xx_pwrdm = {
+        .name             = "cpu1_pwrdm",
+        .prcm_offs        = DRA7XX_MPU_PRCM_PRM_C1_INST,
+        .prcm_partition   = DRA7XX_MPU_PRCM_PARTITION,
+        .pwrsts           = PWRSTS_OFF_RET_ON,
+        .pwrsts_logic_ret = PWRSTS_OFF_RET,
+        .banks            = 1,
+        .pwrsts_mem_ret = {
+                [0] = PWRSTS_OFF_RET,   /* cpu1_l1 */
+        },
+        .pwrsts_mem_on  = {
+                [0] = PWRSTS_ON,        /* cpu1_l1 */
+        },
+};
+
+/* vpe_7xx_pwrdm:  */
+static struct powerdomain vpe_7xx_pwrdm = {
+        .name             = "vpe_pwrdm",
+        .prcm_offs        = DRA7XX_PRM_VPE_INST,
+        .prcm_partition   = DRA7XX_PRM_PARTITION,
+        .pwrsts           = PWRSTS_OFF_RET_ON,
+        .pwrsts_logic_ret = PWRSTS_OFF_RET,
+        .banks            = 1,
+        .pwrsts_mem_ret = {
+                [0] = PWRSTS_OFF_RET,   /* vpe_bank */
+        },
+        .pwrsts_mem_on  = {
+                [0] = PWRSTS_OFF_RET,   /* vpe_bank */
+        },
+        .flags            = PWRDM_HAS_LOWPOWERSTATECHANGE,
+};
+
+/* mpu_7xx_pwrdm: Modena processor and the Neon coprocessor power domain */
+static struct powerdomain mpu_7xx_pwrdm = {
+        .name             = "mpu_pwrdm",
+        .prcm_offs        = DRA7XX_PRM_MPU_INST,
+        .prcm_partition   = DRA7XX_PRM_PARTITION,
+        .pwrsts           = PWRSTS_RET_ON,
+        .pwrsts_logic_ret = PWRSTS_OFF_RET,
+        .banks            = 2,
+        .pwrsts_mem_ret = {
+                [0] = PWRSTS_OFF_RET,   /* mpu_l2 */
+                [1] = PWRSTS_RET,       /* mpu_ram */
+        },
+        .pwrsts_mem_on  = {
+                [0] = PWRSTS_OFF_RET,   /* mpu_l2 */
+                [1] = PWRSTS_OFF_RET,   /* mpu_ram */
+        },
+};
+
+/* l3init_7xx_pwrdm: L3 initators pheripherals power domain  */
+static struct powerdomain l3init_7xx_pwrdm = {
+        .name             = "l3init_pwrdm",
+        .prcm_offs        = DRA7XX_PRM_L3INIT_INST,
+        .prcm_partition   = DRA7XX_PRM_PARTITION,
+        .pwrsts           = PWRSTS_RET_ON,
+        .pwrsts_logic_ret = PWRSTS_OFF_RET,
+        .banks            = 3,
+        .pwrsts_mem_ret = {
+                [0] = PWRSTS_OFF_RET,   /* gmac_bank */
+                [1] = PWRSTS_OFF_RET,   /* l3init_bank1 */
+                [2] = PWRSTS_OFF_RET,   /* l3init_bank2 */
+        },
+        .pwrsts_mem_on  = {
+                [0] = PWRSTS_OFF_RET,   /* gmac_bank */
+                [1] = PWRSTS_OFF_RET,   /* l3init_bank1 */
+                [2] = PWRSTS_OFF_RET,   /* l3init_bank2 */
+        },
+        .flags            = PWRDM_HAS_LOWPOWERSTATECHANGE,
+};
+
+/* eve3_7xx_pwrdm:  */
+static struct powerdomain eve3_7xx_pwrdm = {
+        .name             = "eve3_pwrdm",
+        .prcm_offs        = DRA7XX_PRM_EVE3_INST,
+        .prcm_partition   = DRA7XX_PRM_PARTITION,
+        .pwrsts           = PWRSTS_OFF_ON,
+        .banks            = 1,
+        .pwrsts_mem_ret = {
+                [0] = PWRSTS_OFF_RET,   /* eve3_bank */
+        },
+        .pwrsts_mem_on  = {
+                [0] = PWRSTS_OFF_RET,   /* eve3_bank */
+        },
+        .flags            = PWRDM_HAS_LOWPOWERSTATECHANGE,
+};
+
+/* emu_7xx_pwrdm: Emulation power domain */
+static struct powerdomain emu_7xx_pwrdm = {
+        .name             = "emu_pwrdm",
+        .prcm_offs        = DRA7XX_PRM_EMU_INST,
+        .prcm_partition   = DRA7XX_PRM_PARTITION,
+        .pwrsts           = PWRSTS_OFF_ON,
+        .banks            = 1,
+        .pwrsts_mem_ret = {
+                [0] = PWRSTS_OFF_RET,   /* emu_bank */
+        },
+        .pwrsts_mem_on  = {
+                [0] = PWRSTS_OFF_RET,   /* emu_bank */
+        },
+};
+
+/* dsp2_7xx_pwrdm:  */
+static struct powerdomain dsp2_7xx_pwrdm = {
+        .name             = "dsp2_pwrdm",
+        .prcm_offs        = DRA7XX_PRM_DSP2_INST,
+        .prcm_partition   = DRA7XX_PRM_PARTITION,
+        .pwrsts           = PWRSTS_OFF_ON,
+        .banks            = 3,
+        .pwrsts_mem_ret = {
+                [0] = PWRSTS_OFF_RET,   /* dsp2_edma */
+                [1] = PWRSTS_OFF_RET,   /* dsp2_l1 */
+                [2] = PWRSTS_OFF_RET,   /* dsp2_l2 */
+        },
+        .pwrsts_mem_on  = {
+                [0] = PWRSTS_OFF_RET,   /* dsp2_edma */
+                [1] = PWRSTS_OFF_RET,   /* dsp2_l1 */
+                [2] = PWRSTS_OFF_RET,   /* dsp2_l2 */
+        },
+        .flags            = PWRDM_HAS_LOWPOWERSTATECHANGE,
+};
+
+/* dsp1_7xx_pwrdm: Tesla processor power domain */
+static struct powerdomain dsp1_7xx_pwrdm = {
+        .name             = "dsp1_pwrdm",
+        .prcm_offs        = DRA7XX_PRM_DSP1_INST,
+        .prcm_partition   = DRA7XX_PRM_PARTITION,
+        .pwrsts           = PWRSTS_OFF_ON,
+        .banks            = 3,
+        .pwrsts_mem_ret = {
+                [0] = PWRSTS_OFF_RET,   /* dsp1_edma */
+                [1] = PWRSTS_OFF_RET,   /* dsp1_l1 */
+                [2] = PWRSTS_OFF_RET,   /* dsp1_l2 */
+        },
+        .pwrsts_mem_on  = {
+                [0] = PWRSTS_OFF_RET,   /* dsp1_edma */
+                [1] = PWRSTS_OFF_RET,   /* dsp1_l1 */
+                [2] = PWRSTS_OFF_RET,   /* dsp1_l2 */
+        },
+        .flags            = PWRDM_HAS_LOWPOWERSTATECHANGE,
+};
+
+/* cam_7xx_pwrdm: Camera subsystem power domain */
+static struct powerdomain cam_7xx_pwrdm = {
+        .name             = "cam_pwrdm",
+        .prcm_offs        = DRA7XX_PRM_CAM_INST,
+        .prcm_partition   = DRA7XX_PRM_PARTITION,
+        .pwrsts           = PWRSTS_OFF_ON,
+        .banks            = 1,
+        .pwrsts_mem_ret = {
+                [0] = PWRSTS_OFF_RET,   /* vip_bank */
+        },
+        .pwrsts_mem_on  = {
+                [0] = PWRSTS_OFF_RET,   /* vip_bank */
+        },
+        .flags            = PWRDM_HAS_LOWPOWERSTATECHANGE,
+};
+
+/* eve4_7xx_pwrdm:  */
+static struct powerdomain eve4_7xx_pwrdm = {
+        .name             = "eve4_pwrdm",
+        .prcm_offs        = DRA7XX_PRM_EVE4_INST,
+        .prcm_partition   = DRA7XX_PRM_PARTITION,
+        .pwrsts           = PWRSTS_OFF_ON,
+        .banks            = 1,
+        .pwrsts_mem_ret = {
+                [0] = PWRSTS_OFF_RET,   /* eve4_bank */
+        },
+        .pwrsts_mem_on  = {
+                [0] = PWRSTS_OFF_RET,   /* eve4_bank */
+        },
+        .flags            = PWRDM_HAS_LOWPOWERSTATECHANGE,
+};
+
+/* eve2_7xx_pwrdm:  */
+static struct powerdomain eve2_7xx_pwrdm = {
+        .name             = "eve2_pwrdm",
+        .prcm_offs        = DRA7XX_PRM_EVE2_INST,
+        .prcm_partition   = DRA7XX_PRM_PARTITION,
+        .pwrsts           = PWRSTS_OFF_ON,
+        .banks            = 1,
+        .pwrsts_mem_ret = {
+                [0] = PWRSTS_OFF_RET,   /* eve2_bank */
+        },
+        .pwrsts_mem_on  = {
+                [0] = PWRSTS_OFF_RET,   /* eve2_bank */
+        },
+        .flags            = PWRDM_HAS_LOWPOWERSTATECHANGE,
+};
+
+/* eve1_7xx_pwrdm:  */
+static struct powerdomain eve1_7xx_pwrdm = {
+        .name             = "eve1_pwrdm",
+        .prcm_offs        = DRA7XX_PRM_EVE1_INST,
+        .prcm_partition   = DRA7XX_PRM_PARTITION,
+        .pwrsts           = PWRSTS_OFF_ON,
+        .banks            = 1,
+        .pwrsts_mem_ret = {
+                [0] = PWRSTS_OFF_RET,   /* eve1_bank */
+        },
+        .pwrsts_mem_on  = {
+                [0] = PWRSTS_OFF_RET,   /* eve1_bank */
+        },
+        .flags            = PWRDM_HAS_LOWPOWERSTATECHANGE,
+};
+
+/*
+ * The following power domains are not under SW control
+ *
+ * mpuaon
+ * mmaon
+ */
+
+/* As powerdomains are added or removed above, this list must also be changed */
+static struct powerdomain *powerdomains_dra7xx[] __initdata = {
+        &iva_7xx_pwrdm,
+        &rtc_7xx_pwrdm,
+        &custefuse_7xx_pwrdm,
+        &ipu_7xx_pwrdm,
+        &dss_7xx_pwrdm,
+        &l4per_7xx_pwrdm,
+        &gpu_7xx_pwrdm,
+        &wkupaon_7xx_pwrdm,
+        &core_7xx_pwrdm,
+        &coreaon_7xx_pwrdm,
+        &cpu0_7xx_pwrdm,
+        &cpu1_7xx_pwrdm,
+        &vpe_7xx_pwrdm,
+        &mpu_7xx_pwrdm,
+        &l3init_7xx_pwrdm,
+        &eve3_7xx_pwrdm,
+        &emu_7xx_pwrdm,
+        &dsp2_7xx_pwrdm,
+        &dsp1_7xx_pwrdm,
+        &cam_7xx_pwrdm,
+        &eve4_7xx_pwrdm,
+        &eve2_7xx_pwrdm,
+        &eve1_7xx_pwrdm,
+        NULL
+};
+
+void __init dra7xx_powerdomains_init(void)
+{
+        pwrdm_register_platform_funcs(&omap4_pwrdm_operations);
+        pwrdm_register_pwrdms(powerdomains_dra7xx);
+        pwrdm_complete_init();
+}
diff --git a/arch/arm/mach-omap2/prcm-common.h b/arch/arm/mach-omap2/prcm-common.h
index ff1ac4a82a04..0e841fd9498a 100644
--- a/arch/arm/mach-omap2/prcm-common.h
+++ b/arch/arm/mach-omap2/prcm-common.h
@@ -58,6 +58,7 @@
 #define TI816X_PRM_IVAHD1_MOD                   0x0d00
 #define TI816X_PRM_IVAHD2_MOD                   0x0e00
 #define TI816X_PRM_SGX_MOD                              0x0f00
+#define TI81XX_PRM_ALWON_MOD                    0x1800
 
 /* 24XX register bits shared between CM & PRM registers */
 
diff --git a/arch/arm/mach-omap2/prcm44xx.h b/arch/arm/mach-omap2/prcm44xx.h
index f429cdd5a118..4fea2cfdf2c3 100644
--- a/arch/arm/mach-omap2/prcm44xx.h
+++ b/arch/arm/mach-omap2/prcm44xx.h
@@ -38,6 +38,11 @@
 #define OMAP54XX_SCRM_PARTITION                 4
 #define OMAP54XX_PRCM_MPU_PARTITION             5
 
+#define DRA7XX_PRM_PARTITION                   1
+#define DRA7XX_CM_CORE_AON_PARTITION           2
+#define DRA7XX_CM_CORE_PARTITION               3
+#define DRA7XX_MPU_PRCM_PARTITION              5
+
 /*
  * OMAP4_MAX_PRCM_PARTITIONS: set to the highest value of the PRCM partition
  * IDs, plus one
diff --git a/arch/arm/mach-omap2/prcm_mpu7xx.h b/arch/arm/mach-omap2/prcm_mpu7xx.h
new file mode 100644
index 000000000000..9ebb5ce0878f
--- /dev/null
+++ b/arch/arm/mach-omap2/prcm_mpu7xx.h
@@ -0,0 +1,78 @@
+/*
+ * DRA7xx PRCM MPU instance offset macros
+ *
+ * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
+ *
+ * Generated by code originally written by:
+ * Paul Walmsley (paul@pwsan.com)
+ * Rajendra Nayak (rnayak@ti.com)
+ * Benoit Cousson (b-cousson@ti.com)
+ *
+ * This file is automatically generated from the OMAP hardware databases.
+ * We respectfully ask that any modifications to this file be coordinated
+ * with the public linux-omap@vger.kernel.org mailing list and the
+ * authors above to ensure that the autogeneration scripts are kept
+ * up-to-date with the file contents.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ARCH_ARM_MACH_OMAP2_PRCM_MPU7XX_H
+#define __ARCH_ARM_MACH_OMAP2_PRCM_MPU7XX_H
+
+#include "prcm_mpu_44xx_54xx.h"
+
+#define DRA7XX_PRCM_MPU_BASE                    0x48243000
+
+#define DRA7XX_PRCM_MPU_REGADDR(inst, reg)                              \
+        OMAP2_L4_IO_ADDRESS(DRA7XX_PRCM_MPU_BASE + (inst) + (reg))
+
+/* MPU_PRCM instances */
+#define DRA7XX_MPU_PRCM_OCP_SOCKET_INST 0x0000
+#define DRA7XX_MPU_PRCM_DEVICE_INST     0x0200
+#define DRA7XX_MPU_PRCM_PRM_C0_INST     0x0400
+#define DRA7XX_MPU_PRCM_CM_C0_INST      0x0600
+#define DRA7XX_MPU_PRCM_PRM_C1_INST     0x0800
+#define DRA7XX_MPU_PRCM_CM_C1_INST      0x0a00
+
+/* PRCM_MPU clockdomain register offsets (from instance start) */
+#define DRA7XX_MPU_PRCM_CM_C0_CPU0_CDOFFS       0x0000
+#define DRA7XX_MPU_PRCM_CM_C1_CPU1_CDOFFS       0x0000
+
+
+/* MPU_PRCM */
+
+/* MPU_PRCM.PRCM_MPU_OCP_SOCKET register offsets */
+#define DRA7XX_REVISION_PRCM_MPU_OFFSET                         0x0000
+
+/* MPU_PRCM.PRCM_MPU_DEVICE register offsets */
+#define DRA7XX_PRM_FRAC_INCREMENTER_NUMERATOR_OFFSET            0x0010
+#define DRA7XX_PRM_FRAC_INCREMENTER_DENUMERATOR_RELOAD_OFFSET   0x0014
+
+/* MPU_PRCM.PRCM_MPU_PRM_C0 register offsets */
+#define DRA7XX_PM_CPU0_PWRSTCTRL_OFFSET                         0x0000
+#define DRA7XX_PM_CPU0_PWRSTST_OFFSET                           0x0004
+#define DRA7XX_RM_CPU0_CPU0_RSTCTRL_OFFSET                      0x0010
+#define DRA7XX_RM_CPU0_CPU0_RSTST_OFFSET                        0x0014
+#define DRA7XX_RM_CPU0_CPU0_CONTEXT_OFFSET                      0x0024
+
+/* MPU_PRCM.PRCM_MPU_CM_C0 register offsets */
+#define DRA7XX_CM_CPU0_CLKSTCTRL_OFFSET                         0x0000
+#define DRA7XX_CM_CPU0_CPU0_CLKCTRL_OFFSET                      0x0020
+#define DRA7XX_CM_CPU0_CPU0_CLKCTRL                             DRA7XX_MPU_PRCM_REGADDR(DRA7XX_MPU_PRCM_CM_C0_INST, 0x0020)
+
+/* MPU_PRCM.PRCM_MPU_PRM_C1 register offsets */
+#define DRA7XX_PM_CPU1_PWRSTCTRL_OFFSET                         0x0000
+#define DRA7XX_PM_CPU1_PWRSTST_OFFSET                           0x0004
+#define DRA7XX_RM_CPU1_CPU1_RSTCTRL_OFFSET                      0x0010
+#define DRA7XX_RM_CPU1_CPU1_RSTST_OFFSET                        0x0014
+#define DRA7XX_RM_CPU1_CPU1_CONTEXT_OFFSET                      0x0024
+
+/* MPU_PRCM.PRCM_MPU_CM_C1 register offsets */
+#define DRA7XX_CM_CPU1_CLKSTCTRL_OFFSET                         0x0000
+#define DRA7XX_CM_CPU1_CPU1_CLKCTRL_OFFSET                      0x0020
+#define DRA7XX_CM_CPU1_CPU1_CLKCTRL                             DRA7XX_MPU_PRCM_REGADDR(DRA7XX_MPU_PRCM_CM_C1_INST, 0x0020)
+
+#endif
diff --git a/arch/arm/mach-omap2/prm44xx.c b/arch/arm/mach-omap2/prm44xx.c
index 415c7e0c9393..03a603476cfc 100644
--- a/arch/arm/mach-omap2/prm44xx.c
+++ b/arch/arm/mach-omap2/prm44xx.c
@@ -620,6 +620,15 @@ static int omap4_pwrdm_wait_transition(struct powerdomain *pwrdm)
         return 0;
 }
 
+static int omap4_check_vcvp(void)
+{
+        /* No VC/VP on dra7xx devices */
+        if (soc_is_dra7xx())
+                return 0;
+
+        return 1;
+}
+
 struct pwrdm_ops omap4_pwrdm_operations = {
         .pwrdm_set_next_pwrst   = omap4_pwrdm_set_next_pwrst,
         .pwrdm_read_next_pwrst  = omap4_pwrdm_read_next_pwrst,
@@ -637,6 +646,7 @@ struct pwrdm_ops omap4_pwrdm_operations = {
         .pwrdm_set_mem_onst     = omap4_pwrdm_set_mem_onst,
         .pwrdm_set_mem_retst    = omap4_pwrdm_set_mem_retst,
         .pwrdm_wait_transition  = omap4_pwrdm_wait_transition,
+        .pwrdm_has_voltdm       = omap4_check_vcvp,
 };
 
 /*
@@ -650,7 +660,7 @@ static struct prm_ll_data omap44xx_prm_ll_data = {
 
 int __init omap44xx_prm_init(void)
 {
-        if (!cpu_is_omap44xx() && !soc_is_omap54xx())
+        if (!cpu_is_omap44xx() && !soc_is_omap54xx() && !soc_is_dra7xx())
                 return 0;
 
         return prm_register(&omap44xx_prm_ll_data);
diff --git a/arch/arm/mach-omap2/prm7xx.h b/arch/arm/mach-omap2/prm7xx.h
new file mode 100644
index 000000000000..d92a8404edc7
--- /dev/null
+++ b/arch/arm/mach-omap2/prm7xx.h
@@ -0,0 +1,678 @@
+/*
+ * DRA7xx PRM instance offset macros
+ *
+ * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
+ *
+ * Generated by code originally written by:
+ * Paul Walmsley (paul@pwsan.com)
+ * Rajendra Nayak (rnayak@ti.com)
+ * Benoit Cousson (b-cousson@ti.com)
+ *
+ * This file is automatically generated from the OMAP hardware databases.
+ * We respectfully ask that any modifications to this file be coordinated
+ * with the public linux-omap@vger.kernel.org mailing list and the
+ * authors above to ensure that the autogeneration scripts are kept
+ * up-to-date with the file contents.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ARCH_ARM_MACH_OMAP2_PRM7XX_H
+#define __ARCH_ARM_MACH_OMAP2_PRM7XX_H
+
+#include "prm44xx_54xx.h"
+#include "prcm-common.h"
+#include "prm.h"
+
+#define DRA7XX_PRM_BASE         0x4ae06000
+
+#define DRA7XX_PRM_REGADDR(inst, reg)                           \
+        OMAP2_L4_IO_ADDRESS(DRA7XX_PRM_BASE + (inst) + (reg))
+
+
+/* PRM instances */
+#define DRA7XX_PRM_OCP_SOCKET_INST      0x0000
+#define DRA7XX_PRM_CKGEN_INST           0x0100
+#define DRA7XX_PRM_MPU_INST             0x0300
+#define DRA7XX_PRM_DSP1_INST            0x0400
+#define DRA7XX_PRM_IPU_INST             0x0500
+#define DRA7XX_PRM_COREAON_INST         0x0628
+#define DRA7XX_PRM_CORE_INST            0x0700
+#define DRA7XX_PRM_IVA_INST             0x0f00
+#define DRA7XX_PRM_CAM_INST             0x1000
+#define DRA7XX_PRM_DSS_INST             0x1100
+#define DRA7XX_PRM_GPU_INST             0x1200
+#define DRA7XX_PRM_L3INIT_INST          0x1300
+#define DRA7XX_PRM_L4PER_INST           0x1400
+#define DRA7XX_PRM_CUSTEFUSE_INST       0x1600
+#define DRA7XX_PRM_WKUPAON_INST         0x1724
+#define DRA7XX_PRM_WKUPAON_CM_INST      0x1800
+#define DRA7XX_PRM_EMU_INST             0x1900
+#define DRA7XX_PRM_EMU_CM_INST          0x1a00
+#define DRA7XX_PRM_DSP2_INST            0x1b00
+#define DRA7XX_PRM_EVE1_INST            0x1b40
+#define DRA7XX_PRM_EVE2_INST            0x1b80
+#define DRA7XX_PRM_EVE3_INST            0x1bc0
+#define DRA7XX_PRM_EVE4_INST            0x1c00
+#define DRA7XX_PRM_RTC_INST             0x1c60
+#define DRA7XX_PRM_VPE_INST             0x1c80
+#define DRA7XX_PRM_DEVICE_INST          0x1d00
+#define DRA7XX_PRM_INSTR_INST           0x1f00
+
+/* PRM clockdomain register offsets (from instance start) */
+#define DRA7XX_PRM_WKUPAON_CM_WKUPAON_CDOFFS    0x0000
+#define DRA7XX_PRM_EMU_CM_EMU_CDOFFS            0x0000
+
+/* PRM */
+
+/* PRM.OCP_SOCKET_PRM register offsets */
+#define DRA7XX_REVISION_PRM_OFFSET                              0x0000
+#define DRA7XX_PRM_IRQSTATUS_MPU_OFFSET                         0x0010
+#define DRA7XX_PRM_IRQSTATUS_MPU_2_OFFSET                       0x0014
+#define DRA7XX_PRM_IRQENABLE_MPU_OFFSET                         0x0018
+#define DRA7XX_PRM_IRQENABLE_MPU_2_OFFSET                       0x001c
+#define DRA7XX_PRM_IRQSTATUS_IPU2_OFFSET                        0x0020
+#define DRA7XX_PRM_IRQENABLE_IPU2_OFFSET                        0x0028
+#define DRA7XX_PRM_IRQSTATUS_DSP1_OFFSET                        0x0030
+#define DRA7XX_PRM_IRQENABLE_DSP1_OFFSET                        0x0038
+#define DRA7XX_CM_PRM_PROFILING_CLKCTRL_OFFSET                  0x0040
+#define DRA7XX_CM_PRM_PROFILING_CLKCTRL                         DRA7XX_PRM_REGADDR(DRA7XX_PRM_OCP_SOCKET_INST, 0x0040)
+#define DRA7XX_PRM_IRQENABLE_DSP2_OFFSET                        0x0044
+#define DRA7XX_PRM_IRQENABLE_EVE1_OFFSET                        0x0048
+#define DRA7XX_PRM_IRQENABLE_EVE2_OFFSET                        0x004c
+#define DRA7XX_PRM_IRQENABLE_EVE3_OFFSET                        0x0050
+#define DRA7XX_PRM_IRQENABLE_EVE4_OFFSET                        0x0054
+#define DRA7XX_PRM_IRQENABLE_IPU1_OFFSET                        0x0058
+#define DRA7XX_PRM_IRQSTATUS_DSP2_OFFSET                        0x005c
+#define DRA7XX_PRM_IRQSTATUS_EVE1_OFFSET                        0x0060
+#define DRA7XX_PRM_IRQSTATUS_EVE2_OFFSET                        0x0064
+#define DRA7XX_PRM_IRQSTATUS_EVE3_OFFSET                        0x0068
+#define DRA7XX_PRM_IRQSTATUS_EVE4_OFFSET                        0x006c
+#define DRA7XX_PRM_IRQSTATUS_IPU1_OFFSET                        0x0070
+#define DRA7XX_PRM_DEBUG_CFG1_OFFSET                            0x00e4
+#define DRA7XX_PRM_DEBUG_CFG2_OFFSET                            0x00e8
+#define DRA7XX_PRM_DEBUG_CFG3_OFFSET                            0x00ec
+#define DRA7XX_PRM_DEBUG_OUT_OFFSET                             0x00f4
+
+/* PRM.CKGEN_PRM register offsets */
+#define DRA7XX_CM_CLKSEL_SYSCLK1_OFFSET                         0x0000
+#define DRA7XX_CM_CLKSEL_SYSCLK1                                DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0000)
+#define DRA7XX_CM_CLKSEL_WKUPAON_OFFSET                         0x0008
+#define DRA7XX_CM_CLKSEL_WKUPAON                                DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0008)
+#define DRA7XX_CM_CLKSEL_ABE_PLL_REF_OFFSET                     0x000c
+#define DRA7XX_CM_CLKSEL_ABE_PLL_REF                            DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x000c)
+#define DRA7XX_CM_CLKSEL_SYS_OFFSET                             0x0010
+#define DRA7XX_CM_CLKSEL_SYS                                    DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0010)
+#define DRA7XX_CM_CLKSEL_ABE_PLL_BYPAS_OFFSET                   0x0014
+#define DRA7XX_CM_CLKSEL_ABE_PLL_BYPAS                          DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0014)
+#define DRA7XX_CM_CLKSEL_ABE_PLL_SYS_OFFSET                     0x0018
+#define DRA7XX_CM_CLKSEL_ABE_PLL_SYS                            DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0018)
+#define DRA7XX_CM_CLKSEL_ABE_24M_OFFSET                         0x001c
+#define DRA7XX_CM_CLKSEL_ABE_24M                                DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x001c)
+#define DRA7XX_CM_CLKSEL_ABE_SYS_OFFSET                         0x0020
+#define DRA7XX_CM_CLKSEL_ABE_SYS                                DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0020)
+#define DRA7XX_CM_CLKSEL_HDMI_MCASP_AUX_OFFSET                  0x0024
+#define DRA7XX_CM_CLKSEL_HDMI_MCASP_AUX                         DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0024)
+#define DRA7XX_CM_CLKSEL_HDMI_TIMER_OFFSET                      0x0028
+#define DRA7XX_CM_CLKSEL_HDMI_TIMER                             DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0028)
+#define DRA7XX_CM_CLKSEL_MCASP_SYS_OFFSET                       0x002c
+#define DRA7XX_CM_CLKSEL_MCASP_SYS                              DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x002c)
+#define DRA7XX_CM_CLKSEL_MLBP_MCASP_OFFSET                      0x0030
+#define DRA7XX_CM_CLKSEL_MLBP_MCASP                             DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0030)
+#define DRA7XX_CM_CLKSEL_MLB_MCASP_OFFSET                       0x0034
+#define DRA7XX_CM_CLKSEL_MLB_MCASP                              DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0034)
+#define DRA7XX_CM_CLKSEL_PER_ABE_X1_GFCLK_MCASP_AUX_OFFSET      0x0038
+#define DRA7XX_CM_CLKSEL_PER_ABE_X1_GFCLK_MCASP_AUX             DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0038)
+#define DRA7XX_CM_CLKSEL_SYS_CLK1_32K_OFFSET                    0x0040
+#define DRA7XX_CM_CLKSEL_SYS_CLK1_32K                           DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0040)
+#define DRA7XX_CM_CLKSEL_TIMER_SYS_OFFSET                       0x0044
+#define DRA7XX_CM_CLKSEL_TIMER_SYS                              DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0044)
+#define DRA7XX_CM_CLKSEL_VIDEO1_MCASP_AUX_OFFSET                0x0048
+#define DRA7XX_CM_CLKSEL_VIDEO1_MCASP_AUX                       DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0048)
+#define DRA7XX_CM_CLKSEL_VIDEO1_TIMER_OFFSET                    0x004c
+#define DRA7XX_CM_CLKSEL_VIDEO1_TIMER                           DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x004c)
+#define DRA7XX_CM_CLKSEL_VIDEO2_MCASP_AUX_OFFSET                0x0050
+#define DRA7XX_CM_CLKSEL_VIDEO2_MCASP_AUX                       DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0050)
+#define DRA7XX_CM_CLKSEL_VIDEO2_TIMER_OFFSET                    0x0054
+#define DRA7XX_CM_CLKSEL_VIDEO2_TIMER                           DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0054)
+#define DRA7XX_CM_CLKSEL_CLKOUTMUX0_OFFSET                      0x0058
+#define DRA7XX_CM_CLKSEL_CLKOUTMUX0                             DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0058)
+#define DRA7XX_CM_CLKSEL_CLKOUTMUX1_OFFSET                      0x005c
+#define DRA7XX_CM_CLKSEL_CLKOUTMUX1                             DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x005c)
+#define DRA7XX_CM_CLKSEL_CLKOUTMUX2_OFFSET                      0x0060
+#define DRA7XX_CM_CLKSEL_CLKOUTMUX2                             DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0060)
+#define DRA7XX_CM_CLKSEL_HDMI_PLL_SYS_OFFSET                    0x0064
+#define DRA7XX_CM_CLKSEL_HDMI_PLL_SYS                           DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0064)
+#define DRA7XX_CM_CLKSEL_VIDEO1_PLL_SYS_OFFSET                  0x0068
+#define DRA7XX_CM_CLKSEL_VIDEO1_PLL_SYS                         DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0068)
+#define DRA7XX_CM_CLKSEL_VIDEO2_PLL_SYS_OFFSET                  0x006c
+#define DRA7XX_CM_CLKSEL_VIDEO2_PLL_SYS                         DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x006c)
+#define DRA7XX_CM_CLKSEL_ABE_CLK_DIV_OFFSET                     0x0070
+#define DRA7XX_CM_CLKSEL_ABE_CLK_DIV                            DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0070)
+#define DRA7XX_CM_CLKSEL_ABE_GICLK_DIV_OFFSET                   0x0074
+#define DRA7XX_CM_CLKSEL_ABE_GICLK_DIV                          DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0074)
+#define DRA7XX_CM_CLKSEL_AESS_FCLK_DIV_OFFSET                   0x0078
+#define DRA7XX_CM_CLKSEL_AESS_FCLK_DIV                          DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0078)
+#define DRA7XX_CM_CLKSEL_EVE_CLK_OFFSET                         0x0080
+#define DRA7XX_CM_CLKSEL_EVE_CLK                                DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0080)
+#define DRA7XX_CM_CLKSEL_USB_OTG_CLK_CLKOUTMUX_OFFSET           0x0084
+#define DRA7XX_CM_CLKSEL_USB_OTG_CLK_CLKOUTMUX                  DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0084)
+#define DRA7XX_CM_CLKSEL_CORE_DPLL_OUT_CLK_CLKOUTMUX_OFFSET     0x0088
+#define DRA7XX_CM_CLKSEL_CORE_DPLL_OUT_CLK_CLKOUTMUX            DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0088)
+#define DRA7XX_CM_CLKSEL_DSP_GFCLK_CLKOUTMUX_OFFSET             0x008c
+#define DRA7XX_CM_CLKSEL_DSP_GFCLK_CLKOUTMUX                    DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x008c)
+#define DRA7XX_CM_CLKSEL_EMIF_PHY_GCLK_CLKOUTMUX_OFFSET         0x0090
+#define DRA7XX_CM_CLKSEL_EMIF_PHY_GCLK_CLKOUTMUX                DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0090)
+#define DRA7XX_CM_CLKSEL_EMU_CLK_CLKOUTMUX_OFFSET               0x0094
+#define DRA7XX_CM_CLKSEL_EMU_CLK_CLKOUTMUX                      DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0094)
+#define DRA7XX_CM_CLKSEL_FUNC_96M_AON_CLK_CLKOUTMUX_OFFSET      0x0098
+#define DRA7XX_CM_CLKSEL_FUNC_96M_AON_CLK_CLKOUTMUX             DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0098)
+#define DRA7XX_CM_CLKSEL_GMAC_250M_CLK_CLKOUTMUX_OFFSET         0x009c
+#define DRA7XX_CM_CLKSEL_GMAC_250M_CLK_CLKOUTMUX                DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x009c)
+#define DRA7XX_CM_CLKSEL_GPU_GCLK_CLKOUTMUX_OFFSET              0x00a0
+#define DRA7XX_CM_CLKSEL_GPU_GCLK_CLKOUTMUX                     DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00a0)
+#define DRA7XX_CM_CLKSEL_HDMI_CLK_CLKOUTMUX_OFFSET              0x00a4
+#define DRA7XX_CM_CLKSEL_HDMI_CLK_CLKOUTMUX                     DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00a4)
+#define DRA7XX_CM_CLKSEL_IVA_GCLK_CLKOUTMUX_OFFSET              0x00a8
+#define DRA7XX_CM_CLKSEL_IVA_GCLK_CLKOUTMUX                     DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00a8)
+#define DRA7XX_CM_CLKSEL_L3INIT_480M_GFCLK_CLKOUTMUX_OFFSET     0x00ac
+#define DRA7XX_CM_CLKSEL_L3INIT_480M_GFCLK_CLKOUTMUX            DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00ac)
+#define DRA7XX_CM_CLKSEL_MPU_GCLK_CLKOUTMUX_OFFSET              0x00b0
+#define DRA7XX_CM_CLKSEL_MPU_GCLK_CLKOUTMUX                     DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00b0)
+#define DRA7XX_CM_CLKSEL_PCIE1_CLK_CLKOUTMUX_OFFSET             0x00b4
+#define DRA7XX_CM_CLKSEL_PCIE1_CLK_CLKOUTMUX                    DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00b4)
+#define DRA7XX_CM_CLKSEL_PCIE2_CLK_CLKOUTMUX_OFFSET             0x00b8
+#define DRA7XX_CM_CLKSEL_PCIE2_CLK_CLKOUTMUX                    DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00b8)
+#define DRA7XX_CM_CLKSEL_PER_ABE_X1_CLK_CLKOUTMUX_OFFSET        0x00bc
+#define DRA7XX_CM_CLKSEL_PER_ABE_X1_CLK_CLKOUTMUX               DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00bc)
+#define DRA7XX_CM_CLKSEL_SATA_CLK_CLKOUTMUX_OFFSET              0x00c0
+#define DRA7XX_CM_CLKSEL_SATA_CLK_CLKOUTMUX                     DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00c0)
+#define DRA7XX_CM_CLKSEL_SECURE_32K_CLK_CLKOUTMUX_OFFSET        0x00c4
+#define DRA7XX_CM_CLKSEL_SECURE_32K_CLK_CLKOUTMUX               DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00c4)
+#define DRA7XX_CM_CLKSEL_SYS_CLK1_CLKOUTMUX_OFFSET              0x00c8
+#define DRA7XX_CM_CLKSEL_SYS_CLK1_CLKOUTMUX                     DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00c8)
+#define DRA7XX_CM_CLKSEL_SYS_CLK2_CLKOUTMUX_OFFSET              0x00cc
+#define DRA7XX_CM_CLKSEL_SYS_CLK2_CLKOUTMUX                     DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00cc)
+#define DRA7XX_CM_CLKSEL_VIDEO1_CLK_CLKOUTMUX_OFFSET            0x00d0
+#define DRA7XX_CM_CLKSEL_VIDEO1_CLK_CLKOUTMUX                   DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00d0)
+#define DRA7XX_CM_CLKSEL_VIDEO2_CLK_CLKOUTMUX_OFFSET            0x00d4
+#define DRA7XX_CM_CLKSEL_VIDEO2_CLK_CLKOUTMUX                   DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00d4)
+#define DRA7XX_CM_CLKSEL_ABE_LP_CLK_OFFSET                      0x00d8
+#define DRA7XX_CM_CLKSEL_ABE_LP_CLK                             DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00d8)
+#define DRA7XX_CM_CLKSEL_ADC_GFCLK_OFFSET                       0x00dc
+#define DRA7XX_CM_CLKSEL_ADC_GFCLK                              DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00dc)
+#define DRA7XX_CM_CLKSEL_EVE_GFCLK_CLKOUTMUX_OFFSET             0x00e0
+#define DRA7XX_CM_CLKSEL_EVE_GFCLK_CLKOUTMUX                    DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00e0)
+
+/* PRM.MPU_PRM register offsets */
+#define DRA7XX_PM_MPU_PWRSTCTRL_OFFSET                          0x0000
+#define DRA7XX_PM_MPU_PWRSTST_OFFSET                            0x0004
+#define DRA7XX_RM_MPU_MPU_CONTEXT_OFFSET                        0x0024
+
+/* PRM.DSP1_PRM register offsets */
+#define DRA7XX_PM_DSP1_PWRSTCTRL_OFFSET                         0x0000
+#define DRA7XX_PM_DSP1_PWRSTST_OFFSET                           0x0004
+#define DRA7XX_RM_DSP1_RSTCTRL_OFFSET                           0x0010
+#define DRA7XX_RM_DSP1_RSTST_OFFSET                             0x0014
+#define DRA7XX_RM_DSP1_DSP1_CONTEXT_OFFSET                      0x0024
+
+/* PRM.IPU_PRM register offsets */
+#define DRA7XX_PM_IPU_PWRSTCTRL_OFFSET                          0x0000
+#define DRA7XX_PM_IPU_PWRSTST_OFFSET                            0x0004
+#define DRA7XX_RM_IPU1_RSTCTRL_OFFSET                           0x0010
+#define DRA7XX_RM_IPU1_RSTST_OFFSET                             0x0014
+#define DRA7XX_RM_IPU1_IPU1_CONTEXT_OFFSET                      0x0024
+#define DRA7XX_PM_IPU_MCASP1_WKDEP_OFFSET                       0x0050
+#define DRA7XX_RM_IPU_MCASP1_CONTEXT_OFFSET                     0x0054
+#define DRA7XX_PM_IPU_TIMER5_WKDEP_OFFSET                       0x0058
+#define DRA7XX_RM_IPU_TIMER5_CONTEXT_OFFSET                     0x005c
+#define DRA7XX_PM_IPU_TIMER6_WKDEP_OFFSET                       0x0060
+#define DRA7XX_RM_IPU_TIMER6_CONTEXT_OFFSET                     0x0064
+#define DRA7XX_PM_IPU_TIMER7_WKDEP_OFFSET                       0x0068
+#define DRA7XX_RM_IPU_TIMER7_CONTEXT_OFFSET                     0x006c
+#define DRA7XX_PM_IPU_TIMER8_WKDEP_OFFSET                       0x0070
+#define DRA7XX_RM_IPU_TIMER8_CONTEXT_OFFSET                     0x0074
+#define DRA7XX_PM_IPU_I2C5_WKDEP_OFFSET                         0x0078
+#define DRA7XX_RM_IPU_I2C5_CONTEXT_OFFSET                       0x007c
+#define DRA7XX_PM_IPU_UART6_WKDEP_OFFSET                        0x0080
+#define DRA7XX_RM_IPU_UART6_CONTEXT_OFFSET                      0x0084
+
+/* PRM.COREAON_PRM register offsets */
+#define DRA7XX_PM_COREAON_SMARTREFLEX_MPU_WKDEP_OFFSET          0x0000
+#define DRA7XX_RM_COREAON_SMARTREFLEX_MPU_CONTEXT_OFFSET        0x0004
+#define DRA7XX_PM_COREAON_SMARTREFLEX_CORE_WKDEP_OFFSET         0x0010
+#define DRA7XX_RM_COREAON_SMARTREFLEX_CORE_CONTEXT_OFFSET       0x0014
+#define DRA7XX_PM_COREAON_SMARTREFLEX_GPU_WKDEP_OFFSET          0x0030
+#define DRA7XX_RM_COREAON_SMARTREFLEX_GPU_CONTEXT_OFFSET        0x0034
+#define DRA7XX_PM_COREAON_SMARTREFLEX_DSPEVE_WKDEP_OFFSET       0x0040
+#define DRA7XX_RM_COREAON_SMARTREFLEX_DSPEVE_CONTEXT_OFFSET     0x0044
+#define DRA7XX_PM_COREAON_SMARTREFLEX_IVAHD_WKDEP_OFFSET        0x0050
+#define DRA7XX_RM_COREAON_SMARTREFLEX_IVAHD_CONTEXT_OFFSET      0x0054
+#define DRA7XX_RM_COREAON_DUMMY_MODULE1_CONTEXT_OFFSET          0x0084
+#define DRA7XX_RM_COREAON_DUMMY_MODULE2_CONTEXT_OFFSET          0x0094
+#define DRA7XX_RM_COREAON_DUMMY_MODULE3_CONTEXT_OFFSET          0x00a4
+#define DRA7XX_RM_COREAON_DUMMY_MODULE4_CONTEXT_OFFSET          0x00b4
+
+/* PRM.CORE_PRM register offsets */
+#define DRA7XX_PM_CORE_PWRSTCTRL_OFFSET                         0x0000
+#define DRA7XX_PM_CORE_PWRSTST_OFFSET                           0x0004
+#define DRA7XX_RM_L3MAIN1_L3_MAIN_1_CONTEXT_OFFSET              0x0024
+#define DRA7XX_RM_L3MAIN1_GPMC_CONTEXT_OFFSET                   0x002c
+#define DRA7XX_RM_L3MAIN1_MMU_EDMA_CONTEXT_OFFSET               0x0034
+#define DRA7XX_PM_L3MAIN1_OCMC_RAM1_WKDEP_OFFSET                0x0050
+#define DRA7XX_RM_L3MAIN1_OCMC_RAM1_CONTEXT_OFFSET              0x0054
+#define DRA7XX_PM_L3MAIN1_OCMC_RAM2_WKDEP_OFFSET                0x0058
+#define DRA7XX_RM_L3MAIN1_OCMC_RAM2_CONTEXT_OFFSET              0x005c
+#define DRA7XX_PM_L3MAIN1_OCMC_RAM3_WKDEP_OFFSET                0x0060
+#define DRA7XX_RM_L3MAIN1_OCMC_RAM3_CONTEXT_OFFSET              0x0064
+#define DRA7XX_RM_L3MAIN1_OCMC_ROM_CONTEXT_OFFSET               0x006c
+#define DRA7XX_PM_L3MAIN1_TPCC_WKDEP_OFFSET                     0x0070
+#define DRA7XX_RM_L3MAIN1_TPCC_CONTEXT_OFFSET                   0x0074
+#define DRA7XX_PM_L3MAIN1_TPTC1_WKDEP_OFFSET                    0x0078
+#define DRA7XX_RM_L3MAIN1_TPTC1_CONTEXT_OFFSET                  0x007c
+#define DRA7XX_PM_L3MAIN1_TPTC2_WKDEP_OFFSET                    0x0080
+#define DRA7XX_RM_L3MAIN1_TPTC2_CONTEXT_OFFSET                  0x0084
+#define DRA7XX_RM_L3MAIN1_VCP1_CONTEXT_OFFSET                   0x008c
+#define DRA7XX_RM_L3MAIN1_VCP2_CONTEXT_OFFSET                   0x0094
+#define DRA7XX_RM_L3MAIN1_SPARE_CME_CONTEXT_OFFSET              0x009c
+#define DRA7XX_RM_L3MAIN1_SPARE_HDMI_CONTEXT_OFFSET             0x00a4
+#define DRA7XX_RM_L3MAIN1_SPARE_ICM_CONTEXT_OFFSET              0x00ac
+#define DRA7XX_RM_L3MAIN1_SPARE_IVA2_CONTEXT_OFFSET             0x00b4
+#define DRA7XX_RM_L3MAIN1_SPARE_SATA2_CONTEXT_OFFSET            0x00bc
+#define DRA7XX_RM_L3MAIN1_SPARE_UNKNOWN4_CONTEXT_OFFSET         0x00c4
+#define DRA7XX_RM_L3MAIN1_SPARE_UNKNOWN5_CONTEXT_OFFSET         0x00cc
+#define DRA7XX_RM_L3MAIN1_SPARE_UNKNOWN6_CONTEXT_OFFSET         0x00d4
+#define DRA7XX_RM_L3MAIN1_SPARE_VIDEOPLL1_CONTEXT_OFFSET        0x00dc
+#define DRA7XX_RM_L3MAIN1_SPARE_VIDEOPLL2_CONTEXT_OFFSET        0x00f4
+#define DRA7XX_RM_L3MAIN1_SPARE_VIDEOPLL3_CONTEXT_OFFSET        0x00fc
+#define DRA7XX_RM_IPU2_RSTCTRL_OFFSET                           0x0210
+#define DRA7XX_RM_IPU2_RSTST_OFFSET                             0x0214
+#define DRA7XX_RM_IPU2_IPU2_CONTEXT_OFFSET                      0x0224
+#define DRA7XX_RM_DMA_DMA_SYSTEM_CONTEXT_OFFSET                 0x0324
+#define DRA7XX_RM_EMIF_DMM_CONTEXT_OFFSET                       0x0424
+#define DRA7XX_RM_EMIF_EMIF_OCP_FW_CONTEXT_OFFSET               0x042c
+#define DRA7XX_RM_EMIF_EMIF1_CONTEXT_OFFSET                     0x0434
+#define DRA7XX_RM_EMIF_EMIF2_CONTEXT_OFFSET                     0x043c
+#define DRA7XX_RM_EMIF_EMIF_DLL_CONTEXT_OFFSET                  0x0444
+#define DRA7XX_RM_ATL_ATL_CONTEXT_OFFSET                        0x0524
+#define DRA7XX_RM_L4CFG_L4_CFG_CONTEXT_OFFSET                   0x0624
+#define DRA7XX_RM_L4CFG_SPINLOCK_CONTEXT_OFFSET                 0x062c
+#define DRA7XX_RM_L4CFG_MAILBOX1_CONTEXT_OFFSET                 0x0634
+#define DRA7XX_RM_L4CFG_SAR_ROM_CONTEXT_OFFSET                  0x063c
+#define DRA7XX_RM_L4CFG_OCP2SCP2_CONTEXT_OFFSET                 0x0644
+#define DRA7XX_RM_L4CFG_MAILBOX2_CONTEXT_OFFSET                 0x064c
+#define DRA7XX_RM_L4CFG_MAILBOX3_CONTEXT_OFFSET                 0x0654
+#define DRA7XX_RM_L4CFG_MAILBOX4_CONTEXT_OFFSET                 0x065c
+#define DRA7XX_RM_L4CFG_MAILBOX5_CONTEXT_OFFSET                 0x0664
+#define DRA7XX_RM_L4CFG_MAILBOX6_CONTEXT_OFFSET                 0x066c
+#define DRA7XX_RM_L4CFG_MAILBOX7_CONTEXT_OFFSET                 0x0674
+#define DRA7XX_RM_L4CFG_MAILBOX8_CONTEXT_OFFSET                 0x067c
+#define DRA7XX_RM_L4CFG_MAILBOX9_CONTEXT_OFFSET                 0x0684
+#define DRA7XX_RM_L4CFG_MAILBOX10_CONTEXT_OFFSET                0x068c
+#define DRA7XX_RM_L4CFG_MAILBOX11_CONTEXT_OFFSET                0x0694
+#define DRA7XX_RM_L4CFG_MAILBOX12_CONTEXT_OFFSET                0x069c
+#define DRA7XX_RM_L4CFG_MAILBOX13_CONTEXT_OFFSET                0x06a4
+#define DRA7XX_RM_L4CFG_SPARE_SMARTREFLEX_RTC_CONTEXT_OFFSET    0x06ac
+#define DRA7XX_RM_L4CFG_SPARE_SMARTREFLEX_SDRAM_CONTEXT_OFFSET  0x06b4
+#define DRA7XX_RM_L4CFG_SPARE_SMARTREFLEX_WKUP_CONTEXT_OFFSET   0x06bc
+#define DRA7XX_RM_L4CFG_IO_DELAY_BLOCK_CONTEXT_OFFSET           0x06c4
+#define DRA7XX_RM_L3INSTR_L3_MAIN_2_CONTEXT_OFFSET              0x0724
+#define DRA7XX_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET               0x072c
+#define DRA7XX_RM_L3INSTR_OCP_WP_NOC_CONTEXT_OFFSET             0x0744
+
+/* PRM.IVA_PRM register offsets */
+#define DRA7XX_PM_IVA_PWRSTCTRL_OFFSET                          0x0000
+#define DRA7XX_PM_IVA_PWRSTST_OFFSET                            0x0004
+#define DRA7XX_RM_IVA_RSTCTRL_OFFSET                            0x0010
+#define DRA7XX_RM_IVA_RSTST_OFFSET                              0x0014
+#define DRA7XX_RM_IVA_IVA_CONTEXT_OFFSET                        0x0024
+#define DRA7XX_RM_IVA_SL2_CONTEXT_OFFSET                        0x002c
+
+/* PRM.CAM_PRM register offsets */
+#define DRA7XX_PM_CAM_PWRSTCTRL_OFFSET                          0x0000
+#define DRA7XX_PM_CAM_PWRSTST_OFFSET                            0x0004
+#define DRA7XX_PM_CAM_VIP1_WKDEP_OFFSET                         0x0020
+#define DRA7XX_RM_CAM_VIP1_CONTEXT_OFFSET                       0x0024
+#define DRA7XX_PM_CAM_VIP2_WKDEP_OFFSET                         0x0028
+#define DRA7XX_RM_CAM_VIP2_CONTEXT_OFFSET                       0x002c
+#define DRA7XX_PM_CAM_VIP3_WKDEP_OFFSET                         0x0030
+#define DRA7XX_RM_CAM_VIP3_CONTEXT_OFFSET                       0x0034
+#define DRA7XX_RM_CAM_LVDSRX_CONTEXT_OFFSET                     0x003c
+#define DRA7XX_RM_CAM_CSI1_CONTEXT_OFFSET                       0x0044
+#define DRA7XX_RM_CAM_CSI2_CONTEXT_OFFSET                       0x004c
+
+/* PRM.DSS_PRM register offsets */
+#define DRA7XX_PM_DSS_PWRSTCTRL_OFFSET                          0x0000
+#define DRA7XX_PM_DSS_PWRSTST_OFFSET                            0x0004
+#define DRA7XX_PM_DSS_DSS_WKDEP_OFFSET                          0x0020
+#define DRA7XX_RM_DSS_DSS_CONTEXT_OFFSET                        0x0024
+#define DRA7XX_PM_DSS_DSS2_WKDEP_OFFSET                         0x0028
+#define DRA7XX_RM_DSS_BB2D_CONTEXT_OFFSET                       0x0034
+#define DRA7XX_RM_DSS_SDVENC_CONTEXT_OFFSET                     0x003c
+
+/* PRM.GPU_PRM register offsets */
+#define DRA7XX_PM_GPU_PWRSTCTRL_OFFSET                          0x0000
+#define DRA7XX_PM_GPU_PWRSTST_OFFSET                            0x0004
+#define DRA7XX_RM_GPU_GPU_CONTEXT_OFFSET                        0x0024
+
+/* PRM.L3INIT_PRM register offsets */
+#define DRA7XX_PM_L3INIT_PWRSTCTRL_OFFSET                       0x0000
+#define DRA7XX_PM_L3INIT_PWRSTST_OFFSET                         0x0004
+#define DRA7XX_PM_L3INIT_MMC1_WKDEP_OFFSET                      0x0028
+#define DRA7XX_RM_L3INIT_MMC1_CONTEXT_OFFSET                    0x002c
+#define DRA7XX_PM_L3INIT_MMC2_WKDEP_OFFSET                      0x0030
+#define DRA7XX_RM_L3INIT_MMC2_CONTEXT_OFFSET                    0x0034
+#define DRA7XX_PM_L3INIT_USB_OTG_SS2_WKDEP_OFFSET               0x0040
+#define DRA7XX_RM_L3INIT_USB_OTG_SS2_CONTEXT_OFFSET             0x0044
+#define DRA7XX_PM_L3INIT_USB_OTG_SS3_WKDEP_OFFSET               0x0048
+#define DRA7XX_RM_L3INIT_USB_OTG_SS3_CONTEXT_OFFSET             0x004c
+#define DRA7XX_PM_L3INIT_USB_OTG_SS4_WKDEP_OFFSET               0x0050
+#define DRA7XX_RM_L3INIT_USB_OTG_SS4_CONTEXT_OFFSET             0x0054
+#define DRA7XX_RM_L3INIT_MLB_SS_CONTEXT_OFFSET                  0x005c
+#define DRA7XX_RM_L3INIT_IEEE1500_2_OCP_CONTEXT_OFFSET          0x007c
+#define DRA7XX_PM_L3INIT_SATA_WKDEP_OFFSET                      0x0088
+#define DRA7XX_RM_L3INIT_SATA_CONTEXT_OFFSET                    0x008c
+#define DRA7XX_RM_GMAC_GMAC_CONTEXT_OFFSET                      0x00d4
+#define DRA7XX_RM_L3INIT_OCP2SCP1_CONTEXT_OFFSET                0x00e4
+#define DRA7XX_RM_L3INIT_OCP2SCP3_CONTEXT_OFFSET                0x00ec
+#define DRA7XX_PM_L3INIT_USB_OTG_SS1_WKDEP_OFFSET               0x00f0
+#define DRA7XX_RM_L3INIT_USB_OTG_SS1_CONTEXT_OFFSET             0x00f4
+
+/* PRM.L4PER_PRM register offsets */
+#define DRA7XX_PM_L4PER_PWRSTCTRL_OFFSET                        0x0000
+#define DRA7XX_PM_L4PER_PWRSTST_OFFSET                          0x0004
+#define DRA7XX_RM_L4PER2_L4PER2_CONTEXT_OFFSET                  0x000c
+#define DRA7XX_RM_L4PER3_L4PER3_CONTEXT_OFFSET                  0x0014
+#define DRA7XX_RM_L4PER2_PRUSS1_CONTEXT_OFFSET                  0x001c
+#define DRA7XX_RM_L4PER2_PRUSS2_CONTEXT_OFFSET                  0x0024
+#define DRA7XX_PM_L4PER_TIMER10_WKDEP_OFFSET                    0x0028
+#define DRA7XX_RM_L4PER_TIMER10_CONTEXT_OFFSET                  0x002c
+#define DRA7XX_PM_L4PER_TIMER11_WKDEP_OFFSET                    0x0030
+#define DRA7XX_RM_L4PER_TIMER11_CONTEXT_OFFSET                  0x0034
+#define DRA7XX_PM_L4PER_TIMER2_WKDEP_OFFSET                     0x0038
+#define DRA7XX_RM_L4PER_TIMER2_CONTEXT_OFFSET                   0x003c
+#define DRA7XX_PM_L4PER_TIMER3_WKDEP_OFFSET                     0x0040
+#define DRA7XX_RM_L4PER_TIMER3_CONTEXT_OFFSET                   0x0044
+#define DRA7XX_PM_L4PER_TIMER4_WKDEP_OFFSET                     0x0048
+#define DRA7XX_RM_L4PER_TIMER4_CONTEXT_OFFSET                   0x004c
+#define DRA7XX_PM_L4PER_TIMER9_WKDEP_OFFSET                     0x0050
+#define DRA7XX_RM_L4PER_TIMER9_CONTEXT_OFFSET                   0x0054
+#define DRA7XX_RM_L4PER_ELM_CONTEXT_OFFSET                      0x005c
+#define DRA7XX_PM_L4PER_GPIO2_WKDEP_OFFSET                      0x0060
+#define DRA7XX_RM_L4PER_GPIO2_CONTEXT_OFFSET                    0x0064
+#define DRA7XX_PM_L4PER_GPIO3_WKDEP_OFFSET                      0x0068
+#define DRA7XX_RM_L4PER_GPIO3_CONTEXT_OFFSET                    0x006c
+#define DRA7XX_PM_L4PER_GPIO4_WKDEP_OFFSET                      0x0070
+#define DRA7XX_RM_L4PER_GPIO4_CONTEXT_OFFSET                    0x0074
+#define DRA7XX_PM_L4PER_GPIO5_WKDEP_OFFSET                      0x0078
+#define DRA7XX_RM_L4PER_GPIO5_CONTEXT_OFFSET                    0x007c
+#define DRA7XX_PM_L4PER_GPIO6_WKDEP_OFFSET                      0x0080
+#define DRA7XX_RM_L4PER_GPIO6_CONTEXT_OFFSET                    0x0084
+#define DRA7XX_RM_L4PER_HDQ1W_CONTEXT_OFFSET                    0x008c
+#define DRA7XX_RM_L4PER2_PWMSS2_CONTEXT_OFFSET                  0x0094
+#define DRA7XX_RM_L4PER2_PWMSS3_CONTEXT_OFFSET                  0x009c
+#define DRA7XX_PM_L4PER_I2C1_WKDEP_OFFSET                       0x00a0
+#define DRA7XX_RM_L4PER_I2C1_CONTEXT_OFFSET                     0x00a4
+#define DRA7XX_PM_L4PER_I2C2_WKDEP_OFFSET                       0x00a8
+#define DRA7XX_RM_L4PER_I2C2_CONTEXT_OFFSET                     0x00ac
+#define DRA7XX_PM_L4PER_I2C3_WKDEP_OFFSET                       0x00b0
+#define DRA7XX_RM_L4PER_I2C3_CONTEXT_OFFSET                     0x00b4
+#define DRA7XX_PM_L4PER_I2C4_WKDEP_OFFSET                       0x00b8
+#define DRA7XX_RM_L4PER_I2C4_CONTEXT_OFFSET                     0x00bc
+#define DRA7XX_RM_L4PER_L4PER1_CONTEXT_OFFSET                   0x00c0
+#define DRA7XX_RM_L4PER2_PWMSS1_CONTEXT_OFFSET                  0x00c4
+#define DRA7XX_PM_L4PER_TIMER13_WKDEP_OFFSET                    0x00c8
+#define DRA7XX_RM_L4PER3_TIMER13_CONTEXT_OFFSET                 0x00cc
+#define DRA7XX_PM_L4PER_TIMER14_WKDEP_OFFSET                    0x00d0
+#define DRA7XX_RM_L4PER3_TIMER14_CONTEXT_OFFSET                 0x00d4
+#define DRA7XX_PM_L4PER_TIMER15_WKDEP_OFFSET                    0x00d8
+#define DRA7XX_RM_L4PER3_TIMER15_CONTEXT_OFFSET                 0x00dc
+#define DRA7XX_PM_L4PER_MCSPI1_WKDEP_OFFSET                     0x00f0
+#define DRA7XX_RM_L4PER_MCSPI1_CONTEXT_OFFSET                   0x00f4
+#define DRA7XX_PM_L4PER_MCSPI2_WKDEP_OFFSET                     0x00f8
+#define DRA7XX_RM_L4PER_MCSPI2_CONTEXT_OFFSET                   0x00fc
+#define DRA7XX_PM_L4PER_MCSPI3_WKDEP_OFFSET                     0x0100
+#define DRA7XX_RM_L4PER_MCSPI3_CONTEXT_OFFSET                   0x0104
+#define DRA7XX_PM_L4PER_MCSPI4_WKDEP_OFFSET                     0x0108
+#define DRA7XX_RM_L4PER_MCSPI4_CONTEXT_OFFSET                   0x010c
+#define DRA7XX_PM_L4PER_GPIO7_WKDEP_OFFSET                      0x0110
+#define DRA7XX_RM_L4PER_GPIO7_CONTEXT_OFFSET                    0x0114
+#define DRA7XX_PM_L4PER_GPIO8_WKDEP_OFFSET                      0x0118
+#define DRA7XX_RM_L4PER_GPIO8_CONTEXT_OFFSET                    0x011c
+#define DRA7XX_PM_L4PER_MMC3_WKDEP_OFFSET                       0x0120
+#define DRA7XX_RM_L4PER_MMC3_CONTEXT_OFFSET                     0x0124
+#define DRA7XX_PM_L4PER_MMC4_WKDEP_OFFSET                       0x0128
+#define DRA7XX_RM_L4PER_MMC4_CONTEXT_OFFSET                     0x012c
+#define DRA7XX_PM_L4PER_TIMER16_WKDEP_OFFSET                    0x0130
+#define DRA7XX_RM_L4PER3_TIMER16_CONTEXT_OFFSET                 0x0134
+#define DRA7XX_PM_L4PER2_QSPI_WKDEP_OFFSET                      0x0138
+#define DRA7XX_RM_L4PER2_QSPI_CONTEXT_OFFSET                    0x013c
+#define DRA7XX_PM_L4PER_UART1_WKDEP_OFFSET                      0x0140
+#define DRA7XX_RM_L4PER_UART1_CONTEXT_OFFSET                    0x0144
+#define DRA7XX_PM_L4PER_UART2_WKDEP_OFFSET                      0x0148
+#define DRA7XX_RM_L4PER_UART2_CONTEXT_OFFSET                    0x014c
+#define DRA7XX_PM_L4PER_UART3_WKDEP_OFFSET                      0x0150
+#define DRA7XX_RM_L4PER_UART3_CONTEXT_OFFSET                    0x0154
+#define DRA7XX_PM_L4PER_UART4_WKDEP_OFFSET                      0x0158
+#define DRA7XX_RM_L4PER_UART4_CONTEXT_OFFSET                    0x015c
+#define DRA7XX_PM_L4PER2_MCASP2_WKDEP_OFFSET                    0x0160
+#define DRA7XX_RM_L4PER2_MCASP2_CONTEXT_OFFSET                  0x0164
+#define DRA7XX_PM_L4PER2_MCASP3_WKDEP_OFFSET                    0x0168
+#define DRA7XX_RM_L4PER2_MCASP3_CONTEXT_OFFSET                  0x016c
+#define DRA7XX_PM_L4PER_UART5_WKDEP_OFFSET                      0x0170
+#define DRA7XX_RM_L4PER_UART5_CONTEXT_OFFSET                    0x0174
+#define DRA7XX_PM_L4PER2_MCASP5_WKDEP_OFFSET                    0x0178
+#define DRA7XX_RM_L4PER2_MCASP5_CONTEXT_OFFSET                  0x017c
+#define DRA7XX_PM_L4PER2_MCASP6_WKDEP_OFFSET                    0x0180
+#define DRA7XX_RM_L4PER2_MCASP6_CONTEXT_OFFSET                  0x0184
+#define DRA7XX_PM_L4PER2_MCASP7_WKDEP_OFFSET                    0x0188
+#define DRA7XX_RM_L4PER2_MCASP7_CONTEXT_OFFSET                  0x018c
+#define DRA7XX_PM_L4PER2_MCASP8_WKDEP_OFFSET                    0x0190
+#define DRA7XX_RM_L4PER2_MCASP8_CONTEXT_OFFSET                  0x0194
+#define DRA7XX_PM_L4PER2_MCASP4_WKDEP_OFFSET                    0x0198
+#define DRA7XX_RM_L4PER2_MCASP4_CONTEXT_OFFSET                  0x019c
+#define DRA7XX_RM_L4SEC_AES1_CONTEXT_OFFSET                     0x01a4
+#define DRA7XX_RM_L4SEC_AES2_CONTEXT_OFFSET                     0x01ac
+#define DRA7XX_RM_L4SEC_DES3DES_CONTEXT_OFFSET                  0x01b4
+#define DRA7XX_RM_L4SEC_FPKA_CONTEXT_OFFSET                     0x01bc
+#define DRA7XX_RM_L4SEC_RNG_CONTEXT_OFFSET                      0x01c4
+#define DRA7XX_RM_L4SEC_SHA2MD51_CONTEXT_OFFSET                 0x01cc
+#define DRA7XX_PM_L4PER2_UART7_WKDEP_OFFSET                     0x01d0
+#define DRA7XX_RM_L4PER2_UART7_CONTEXT_OFFSET                   0x01d4
+#define DRA7XX_RM_L4SEC_DMA_CRYPTO_CONTEXT_OFFSET               0x01dc
+#define DRA7XX_PM_L4PER2_UART8_WKDEP_OFFSET                     0x01e0
+#define DRA7XX_RM_L4PER2_UART8_CONTEXT_OFFSET                   0x01e4
+#define DRA7XX_PM_L4PER2_UART9_WKDEP_OFFSET                     0x01e8
+#define DRA7XX_RM_L4PER2_UART9_CONTEXT_OFFSET                   0x01ec
+#define DRA7XX_PM_L4PER2_DCAN2_WKDEP_OFFSET                     0x01f0
+#define DRA7XX_RM_L4PER2_DCAN2_CONTEXT_OFFSET                   0x01f4
+#define DRA7XX_RM_L4SEC_SHA2MD52_CONTEXT_OFFSET                 0x01fc
+
+/* PRM.CUSTEFUSE_PRM register offsets */
+#define DRA7XX_PM_CUSTEFUSE_PWRSTCTRL_OFFSET                    0x0000
+#define DRA7XX_PM_CUSTEFUSE_PWRSTST_OFFSET                      0x0004
+#define DRA7XX_RM_CUSTEFUSE_EFUSE_CTRL_CUST_CONTEXT_OFFSET      0x0024
+
+/* PRM.WKUPAON_PRM register offsets */
+#define DRA7XX_RM_WKUPAON_L4_WKUP_CONTEXT_OFFSET                0x0000
+#define DRA7XX_PM_WKUPAON_WD_TIMER1_WKDEP_OFFSET                0x0004
+#define DRA7XX_RM_WKUPAON_WD_TIMER1_CONTEXT_OFFSET              0x0008
+#define DRA7XX_PM_WKUPAON_WD_TIMER2_WKDEP_OFFSET                0x000c
+#define DRA7XX_RM_WKUPAON_WD_TIMER2_CONTEXT_OFFSET              0x0010
+#define DRA7XX_PM_WKUPAON_GPIO1_WKDEP_OFFSET                    0x0014
+#define DRA7XX_RM_WKUPAON_GPIO1_CONTEXT_OFFSET                  0x0018
+#define DRA7XX_PM_WKUPAON_TIMER1_WKDEP_OFFSET                   0x001c
+#define DRA7XX_RM_WKUPAON_TIMER1_CONTEXT_OFFSET                 0x0020
+#define DRA7XX_PM_WKUPAON_TIMER12_WKDEP_OFFSET                  0x0024
+#define DRA7XX_RM_WKUPAON_TIMER12_CONTEXT_OFFSET                0x0028
+#define DRA7XX_RM_WKUPAON_COUNTER_32K_CONTEXT_OFFSET            0x0030
+#define DRA7XX_RM_WKUPAON_SAR_RAM_CONTEXT_OFFSET                0x0040
+#define DRA7XX_PM_WKUPAON_KBD_WKDEP_OFFSET                      0x0054
+#define DRA7XX_RM_WKUPAON_KBD_CONTEXT_OFFSET                    0x0058
+#define DRA7XX_PM_WKUPAON_UART10_WKDEP_OFFSET                   0x005c
+#define DRA7XX_RM_WKUPAON_UART10_CONTEXT_OFFSET                 0x0060
+#define DRA7XX_PM_WKUPAON_DCAN1_WKDEP_OFFSET                    0x0064
+#define DRA7XX_RM_WKUPAON_DCAN1_CONTEXT_OFFSET                  0x0068
+#define DRA7XX_PM_WKUPAON_ADC_WKDEP_OFFSET                              0x007c
+#define DRA7XX_RM_WKUPAON_ADC_CONTEXT_OFFSET                    0x0080
+#define DRA7XX_RM_WKUPAON_SPARE_SAFETY1_CONTEXT_OFFSET          0x0090
+#define DRA7XX_RM_WKUPAON_SPARE_SAFETY2_CONTEXT_OFFSET          0x0098
+#define DRA7XX_RM_WKUPAON_SPARE_SAFETY3_CONTEXT_OFFSET          0x00a0
+#define DRA7XX_RM_WKUPAON_SPARE_SAFETY4_CONTEXT_OFFSET          0x00a8
+#define DRA7XX_RM_WKUPAON_SPARE_UNKNOWN2_CONTEXT_OFFSET         0x00b0
+#define DRA7XX_RM_WKUPAON_SPARE_UNKNOWN3_CONTEXT_OFFSET         0x00b8
+
+/* PRM.WKUPAON_CM register offsets */
+#define DRA7XX_CM_WKUPAON_CLKSTCTRL_OFFSET                      0x0000
+#define DRA7XX_CM_WKUPAON_L4_WKUP_CLKCTRL_OFFSET                0x0020
+#define DRA7XX_CM_WKUPAON_L4_WKUP_CLKCTRL                       DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x0020)
+#define DRA7XX_CM_WKUPAON_WD_TIMER1_CLKCTRL_OFFSET              0x0028
+#define DRA7XX_CM_WKUPAON_WD_TIMER1_CLKCTRL                     DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x0028)
+#define DRA7XX_CM_WKUPAON_WD_TIMER2_CLKCTRL_OFFSET              0x0030
+#define DRA7XX_CM_WKUPAON_WD_TIMER2_CLKCTRL                     DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x0030)
+#define DRA7XX_CM_WKUPAON_GPIO1_CLKCTRL_OFFSET                  0x0038
+#define DRA7XX_CM_WKUPAON_GPIO1_CLKCTRL                         DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x0038)
+#define DRA7XX_CM_WKUPAON_TIMER1_CLKCTRL_OFFSET                 0x0040
+#define DRA7XX_CM_WKUPAON_TIMER1_CLKCTRL                        DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x0040)
+#define DRA7XX_CM_WKUPAON_TIMER12_CLKCTRL_OFFSET                0x0048
+#define DRA7XX_CM_WKUPAON_TIMER12_CLKCTRL                       DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x0048)
+#define DRA7XX_CM_WKUPAON_COUNTER_32K_CLKCTRL_OFFSET            0x0050
+#define DRA7XX_CM_WKUPAON_COUNTER_32K_CLKCTRL                   DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x0050)
+#define DRA7XX_CM_WKUPAON_SAR_RAM_CLKCTRL_OFFSET                0x0060
+#define DRA7XX_CM_WKUPAON_SAR_RAM_CLKCTRL                       DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x0060)
+#define DRA7XX_CM_WKUPAON_KBD_CLKCTRL_OFFSET                    0x0078
+#define DRA7XX_CM_WKUPAON_KBD_CLKCTRL                           DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x0078)
+#define DRA7XX_CM_WKUPAON_UART10_CLKCTRL_OFFSET                 0x0080
+#define DRA7XX_CM_WKUPAON_UART10_CLKCTRL                        DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x0080)
+#define DRA7XX_CM_WKUPAON_DCAN1_CLKCTRL_OFFSET                  0x0088
+#define DRA7XX_CM_WKUPAON_DCAN1_CLKCTRL                         DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x0088)
+#define DRA7XX_CM_WKUPAON_SCRM_CLKCTRL_OFFSET                   0x0090
+#define DRA7XX_CM_WKUPAON_SCRM_CLKCTRL                          DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x0090)
+#define DRA7XX_CM_WKUPAON_IO_SRCOMP_CLKCTRL_OFFSET              0x0098
+#define DRA7XX_CM_WKUPAON_IO_SRCOMP_CLKCTRL                     DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x0098)
+#define DRA7XX_CM_WKUPAON_ADC_CLKCTRL_OFFSET                    0x00a0
+#define DRA7XX_CM_WKUPAON_ADC_CLKCTRL                           DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x00a0)
+#define DRA7XX_CM_WKUPAON_SPARE_SAFETY1_CLKCTRL_OFFSET          0x00b0
+#define DRA7XX_CM_WKUPAON_SPARE_SAFETY1_CLKCTRL                 DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x00b0)
+#define DRA7XX_CM_WKUPAON_SPARE_SAFETY2_CLKCTRL_OFFSET          0x00b8
+#define DRA7XX_CM_WKUPAON_SPARE_SAFETY2_CLKCTRL                 DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x00b8)
+#define DRA7XX_CM_WKUPAON_SPARE_SAFETY3_CLKCTRL_OFFSET          0x00c0
+#define DRA7XX_CM_WKUPAON_SPARE_SAFETY3_CLKCTRL                 DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x00c0)
+#define DRA7XX_CM_WKUPAON_SPARE_SAFETY4_CLKCTRL_OFFSET          0x00c8
+#define DRA7XX_CM_WKUPAON_SPARE_SAFETY4_CLKCTRL                 DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x00c8)
+#define DRA7XX_CM_WKUPAON_SPARE_UNKNOWN2_CLKCTRL_OFFSET         0x00d0
+#define DRA7XX_CM_WKUPAON_SPARE_UNKNOWN2_CLKCTRL                DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x00d0)
+#define DRA7XX_CM_WKUPAON_SPARE_UNKNOWN3_CLKCTRL_OFFSET         0x00d8
+#define DRA7XX_CM_WKUPAON_SPARE_UNKNOWN3_CLKCTRL                DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x00d8)
+
+/* PRM.EMU_PRM register offsets */
+#define DRA7XX_PM_EMU_PWRSTCTRL_OFFSET                          0x0000
+#define DRA7XX_PM_EMU_PWRSTST_OFFSET                            0x0004
+#define DRA7XX_RM_EMU_DEBUGSS_CONTEXT_OFFSET                    0x0024
+
+/* PRM.EMU_CM register offsets */
+#define DRA7XX_CM_EMU_CLKSTCTRL_OFFSET                          0x0000
+#define DRA7XX_CM_EMU_DEBUGSS_CLKCTRL_OFFSET                    0x0004
+#define DRA7XX_CM_EMU_DEBUGSS_CLKCTRL                           DRA7XX_PRM_REGADDR(DRA7XX_PRM_EMU_CM_INST, 0x0004)
+#define DRA7XX_CM_EMU_DYNAMICDEP_OFFSET                         0x0008
+#define DRA7XX_CM_EMU_MPU_EMU_DBG_CLKCTRL_OFFSET                0x000c
+#define DRA7XX_CM_EMU_MPU_EMU_DBG_CLKCTRL                       DRA7XX_PRM_REGADDR(DRA7XX_PRM_EMU_CM_INST, 0x000c)
+
+/* PRM.DSP2_PRM register offsets */
+#define DRA7XX_PM_DSP2_PWRSTCTRL_OFFSET                         0x0000
+#define DRA7XX_PM_DSP2_PWRSTST_OFFSET                           0x0004
+#define DRA7XX_RM_DSP2_RSTCTRL_OFFSET                           0x0010
+#define DRA7XX_RM_DSP2_RSTST_OFFSET                             0x0014
+#define DRA7XX_RM_DSP2_DSP2_CONTEXT_OFFSET                      0x0024
+
+/* PRM.EVE1_PRM register offsets */
+#define DRA7XX_PM_EVE1_PWRSTCTRL_OFFSET                         0x0000
+#define DRA7XX_PM_EVE1_PWRSTST_OFFSET                           0x0004
+#define DRA7XX_RM_EVE1_RSTCTRL_OFFSET                           0x0010
+#define DRA7XX_RM_EVE1_RSTST_OFFSET                             0x0014
+#define DRA7XX_PM_EVE1_EVE1_WKDEP_OFFSET                        0x0020
+#define DRA7XX_RM_EVE1_EVE1_CONTEXT_OFFSET                      0x0024
+
+/* PRM.EVE2_PRM register offsets */
+#define DRA7XX_PM_EVE2_PWRSTCTRL_OFFSET                         0x0000
+#define DRA7XX_PM_EVE2_PWRSTST_OFFSET                           0x0004
+#define DRA7XX_RM_EVE2_RSTCTRL_OFFSET                           0x0010
+#define DRA7XX_RM_EVE2_RSTST_OFFSET                             0x0014
+#define DRA7XX_PM_EVE2_EVE2_WKDEP_OFFSET                        0x0020
+#define DRA7XX_RM_EVE2_EVE2_CONTEXT_OFFSET                      0x0024
+
+/* PRM.EVE3_PRM register offsets */
+#define DRA7XX_PM_EVE3_PWRSTCTRL_OFFSET                         0x0000
+#define DRA7XX_PM_EVE3_PWRSTST_OFFSET                           0x0004
+#define DRA7XX_RM_EVE3_RSTCTRL_OFFSET                           0x0010
+#define DRA7XX_RM_EVE3_RSTST_OFFSET                             0x0014
+#define DRA7XX_PM_EVE3_EVE3_WKDEP_OFFSET                        0x0020
+#define DRA7XX_RM_EVE3_EVE3_CONTEXT_OFFSET                      0x0024
+
+/* PRM.EVE4_PRM register offsets */
+#define DRA7XX_PM_EVE4_PWRSTCTRL_OFFSET                         0x0000
+#define DRA7XX_PM_EVE4_PWRSTST_OFFSET                           0x0004
+#define DRA7XX_RM_EVE4_RSTCTRL_OFFSET                           0x0010
+#define DRA7XX_RM_EVE4_RSTST_OFFSET                             0x0014
+#define DRA7XX_PM_EVE4_EVE4_WKDEP_OFFSET                        0x0020
+#define DRA7XX_RM_EVE4_EVE4_CONTEXT_OFFSET                      0x0024
+
+/* PRM.RTC_PRM register offsets */
+#define DRA7XX_PM_RTC_RTCSS_WKDEP_OFFSET                        0x0000
+#define DRA7XX_RM_RTC_RTCSS_CONTEXT_OFFSET                      0x0004
+
+/* PRM.VPE_PRM register offsets */
+#define DRA7XX_PM_VPE_PWRSTCTRL_OFFSET                          0x0000
+#define DRA7XX_PM_VPE_PWRSTST_OFFSET                            0x0004
+#define DRA7XX_PM_VPE_VPE_WKDEP_OFFSET                          0x0020
+#define DRA7XX_RM_VPE_VPE_CONTEXT_OFFSET                        0x0024
+
+/* PRM.DEVICE_PRM register offsets */
+#define DRA7XX_PRM_RSTCTRL_OFFSET                               0x0000
+#define DRA7XX_PRM_RSTST_OFFSET                                 0x0004
+#define DRA7XX_PRM_RSTTIME_OFFSET                               0x0008
+#define DRA7XX_PRM_CLKREQCTRL_OFFSET                            0x000c
+#define DRA7XX_PRM_VOLTCTRL_OFFSET                              0x0010
+#define DRA7XX_PRM_PWRREQCTRL_OFFSET                            0x0014
+#define DRA7XX_PRM_PSCON_COUNT_OFFSET                           0x0018
+#define DRA7XX_PRM_IO_COUNT_OFFSET                              0x001c
+#define DRA7XX_PRM_IO_PMCTRL_OFFSET                             0x0020
+#define DRA7XX_PRM_VOLTSETUP_WARMRESET_OFFSET                   0x0024
+#define DRA7XX_PRM_VOLTSETUP_CORE_OFF_OFFSET                    0x0028
+#define DRA7XX_PRM_VOLTSETUP_MPU_OFF_OFFSET                     0x002c
+#define DRA7XX_PRM_VOLTSETUP_MM_OFF_OFFSET                      0x0030
+#define DRA7XX_PRM_VOLTSETUP_CORE_RET_SLEEP_OFFSET              0x0034
+#define DRA7XX_PRM_VOLTSETUP_MPU_RET_SLEEP_OFFSET               0x0038
+#define DRA7XX_PRM_VOLTSETUP_MM_RET_SLEEP_OFFSET                0x003c
+#define DRA7XX_PRM_SRAM_COUNT_OFFSET                            0x00bc
+#define DRA7XX_PRM_SRAM_WKUP_SETUP_OFFSET                       0x00c0
+#define DRA7XX_PRM_SLDO_CORE_SETUP_OFFSET                       0x00c4
+#define DRA7XX_PRM_SLDO_CORE_CTRL_OFFSET                        0x00c8
+#define DRA7XX_PRM_SLDO_MPU_SETUP_OFFSET                        0x00cc
+#define DRA7XX_PRM_SLDO_MPU_CTRL_OFFSET                         0x00d0
+#define DRA7XX_PRM_SLDO_GPU_SETUP_OFFSET                        0x00d4
+#define DRA7XX_PRM_SLDO_GPU_CTRL_OFFSET                         0x00d8
+#define DRA7XX_PRM_ABBLDO_MPU_SETUP_OFFSET                      0x00dc
+#define DRA7XX_PRM_ABBLDO_MPU_CTRL_OFFSET                       0x00e0
+#define DRA7XX_PRM_ABBLDO_GPU_SETUP_OFFSET                      0x00e4
+#define DRA7XX_PRM_ABBLDO_GPU_CTRL_OFFSET                       0x00e8
+#define DRA7XX_PRM_BANDGAP_SETUP_OFFSET                         0x00ec
+#define DRA7XX_PRM_DEVICE_OFF_CTRL_OFFSET                       0x00f0
+#define DRA7XX_PRM_PHASE1_CNDP_OFFSET                           0x00f4
+#define DRA7XX_PRM_PHASE2A_CNDP_OFFSET                          0x00f8
+#define DRA7XX_PRM_PHASE2B_CNDP_OFFSET                          0x00fc
+#define DRA7XX_PRM_MODEM_IF_CTRL_OFFSET                         0x0100
+#define DRA7XX_PRM_VOLTST_MPU_OFFSET                            0x0110
+#define DRA7XX_PRM_VOLTST_MM_OFFSET                             0x0114
+#define DRA7XX_PRM_SLDO_DSPEVE_SETUP_OFFSET                     0x0118
+#define DRA7XX_PRM_SLDO_IVA_SETUP_OFFSET                        0x011c
+#define DRA7XX_PRM_ABBLDO_DSPEVE_CTRL_OFFSET                    0x0120
+#define DRA7XX_PRM_ABBLDO_IVA_CTRL_OFFSET                       0x0124
+#define DRA7XX_PRM_SLDO_DSPEVE_CTRL_OFFSET                      0x0128
+#define DRA7XX_PRM_SLDO_IVA_CTRL_OFFSET                         0x012c
+#define DRA7XX_PRM_ABBLDO_DSPEVE_SETUP_OFFSET                   0x0130
+#define DRA7XX_PRM_ABBLDO_IVA_SETUP_OFFSET                      0x0134
+
+#endif
diff --git a/arch/arm/mach-omap2/prminst44xx.c b/arch/arm/mach-omap2/prminst44xx.c
index c12320c0ae95..6334b96b4097 100644
--- a/arch/arm/mach-omap2/prminst44xx.c
+++ b/arch/arm/mach-omap2/prminst44xx.c
@@ -20,10 +20,13 @@
 #include "common.h"
 #include "prcm-common.h"
 #include "prm44xx.h"
+#include "prm54xx.h"
+#include "prm7xx.h"
 #include "prminst44xx.h"
 #include "prm-regbits-44xx.h"
 #include "prcm44xx.h"
 #include "prcm_mpu44xx.h"
+#include "soc.h"
 
 static void __iomem *_prm_bases[OMAP4_MAX_PRCM_PARTITIONS];
 
@@ -165,10 +168,19 @@ int omap4_prminst_deassert_hardreset(u8 shift, u8 part, s16 inst,
 void omap4_prminst_global_warm_sw_reset(void)
 {
         u32 v;
-
-        v = omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION,
-                                    OMAP4430_PRM_DEVICE_INST,
-                                    OMAP4_PRM_RSTCTRL_OFFSET);
+        s16 dev_inst;
+
+        if (cpu_is_omap44xx())
+                dev_inst = OMAP4430_PRM_DEVICE_INST;
+        else if (soc_is_omap54xx())
+                dev_inst = OMAP54XX_PRM_DEVICE_INST;
+        else if (soc_is_dra7xx())
+                dev_inst = DRA7XX_PRM_DEVICE_INST;
+        else
+                return;
+
+        v = omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION, dev_inst,
+                                        OMAP4_PRM_RSTCTRL_OFFSET);
         v |= OMAP4430_RST_GLOBAL_WARM_SW_MASK;
         omap4_prminst_write_inst_reg(v, OMAP4430_PRM_PARTITION,
                                  OMAP4430_PRM_DEVICE_INST,
diff --git a/arch/arm/mach-ux500/board-mop500-audio.c b/arch/arm/mach-ux500/board-mop500-audio.c
index bfe443daf4b0..ec0807247e60 100644
--- a/arch/arm/mach-ux500/board-mop500-audio.c
+++ b/arch/arm/mach-ux500/board-mop500-audio.c
@@ -17,7 +17,6 @@
 #include "ste-dma40-db8500.h"
 #include "board-mop500.h"
 #include "devices-db8500.h"
-#include "pins-db8500.h"
 
 static struct stedma40_chan_cfg msp0_dma_rx = {
         .high_priority = true,
diff --git a/arch/arm/mach-ux500/board-mop500-pins.c b/arch/arm/mach-ux500/board-mop500-pins.c
index 7936d40a5c37..0efb1560fc35 100644
--- a/arch/arm/mach-ux500/board-mop500-pins.c
+++ b/arch/arm/mach-ux500/board-mop500-pins.c
@@ -14,7 +14,6 @@
 
 #include <asm/mach-types.h>
 
-#include "pins-db8500.h"
 #include "board-mop500.h"
 
 enum custom_pin_cfg_t {
diff --git a/arch/arm/mach-ux500/board-mop500.c b/arch/arm/mach-ux500/board-mop500.c
index 4e7ab3a0dd60..ad0806eff762 100644
--- a/arch/arm/mach-ux500/board-mop500.c
+++ b/arch/arm/mach-ux500/board-mop500.c
@@ -324,21 +324,19 @@ static struct lp55xx_platform_data __initdata lp5521_sec_data = {
        .clock_mode     = LP55XX_CLOCK_EXT,
 };
 
+/* I2C0 devices only available on the first HREF/MOP500 */
 static struct i2c_board_info __initdata mop500_i2c0_devices[] = {
         {
                 I2C_BOARD_INFO("tc3589x", 0x42),
                 .irq            = NOMADIK_GPIO_TO_IRQ(217),
                 .platform_data  = &mop500_tc35892_data,
         },
-        /* I2C0 devices only available prior to HREFv60 */
         {
                 I2C_BOARD_INFO("tps61052", 0x33),
                 .platform_data  = &mop500_tps61052_data,
         },
 };
 
-#define NUM_PRE_V60_I2C0_DEVICES 1
-
 static struct i2c_board_info __initdata mop500_i2c2_devices[] = {
         {
                 /* lp5521 LED driver, 1st device */
@@ -356,6 +354,17 @@ static struct i2c_board_info __initdata mop500_i2c2_devices[] = {
         },
 };
 
+static int __init mop500_i2c_board_init(void)
+{
+        if (machine_is_u8500())
+                mop500_uib_i2c_add(0, mop500_i2c0_devices,
+                                   ARRAY_SIZE(mop500_i2c0_devices));
+        mop500_uib_i2c_add(2, mop500_i2c2_devices,
+                           ARRAY_SIZE(mop500_i2c2_devices));
+        return 0;
+}
+device_initcall(mop500_i2c_board_init);
+
 static void __init mop500_i2c_init(struct device *parent)
 {
         db8500_add_i2c0(parent, NULL);
@@ -564,7 +573,6 @@ static struct platform_device *snowball_platform_devs[] __initdata = {
 static void __init mop500_init_machine(void)
 {
         struct device *parent = NULL;
-        int i2c0_devs;
         int i;
 
         platform_device_register(&db8500_prcmu_device);
@@ -587,19 +595,13 @@ static void __init mop500_init_machine(void)
         mop500_spi_init(parent);
         mop500_audio_init(parent);
         mop500_uart_init(parent);
-
         u8500_cryp1_hash1_init(parent);
 
-        i2c0_devs = ARRAY_SIZE(mop500_i2c0_devices);
-
-        i2c_register_board_info(0, mop500_i2c0_devices, i2c0_devs);
-        i2c_register_board_info(2, mop500_i2c2_devices,
-                                ARRAY_SIZE(mop500_i2c2_devices));
-
         /* This board has full regulator constraints */
         regulator_has_full_constraints();
 }
 
+
 static void __init snowball_init_machine(void)
 {
         struct device *parent = NULL;
@@ -634,7 +636,6 @@ static void __init snowball_init_machine(void)
 static void __init hrefv60_init_machine(void)
 {
         struct device *parent = NULL;
-        int i2c0_devs;
         int i;
 
         platform_device_register(&db8500_prcmu_device);
@@ -663,14 +664,6 @@ static void __init hrefv60_init_machine(void)
         mop500_audio_init(parent);
         mop500_uart_init(parent);
 
-        i2c0_devs = ARRAY_SIZE(mop500_i2c0_devices);
-
-        i2c0_devs -= NUM_PRE_V60_I2C0_DEVICES;
-
-        i2c_register_board_info(0, mop500_i2c0_devices, i2c0_devs);
-        i2c_register_board_info(2, mop500_i2c2_devices,
-                                ARRAY_SIZE(mop500_i2c2_devices));
-
         /* This board has full regulator constraints */
         regulator_has_full_constraints();
 }
diff --git a/arch/arm/mach-ux500/cpu-db8500.c b/arch/arm/mach-ux500/cpu-db8500.c
index bfaf95d22cbb..301c3460d96a 100644
--- a/arch/arm/mach-ux500/cpu-db8500.c
+++ b/arch/arm/mach-ux500/cpu-db8500.c
@@ -156,7 +156,8 @@ static void __init db8500_add_gpios(struct device *parent)
                 .supports_sleepmode = true,
         };
 
-        dbx500_add_gpios(parent, ARRAY_AND_SIZE(db8500_gpio_base),
+        dbx500_add_gpios(parent, db8500_gpio_base,
+                         ARRAY_SIZE(db8500_gpio_base),
                          IRQ_DB8500_GPIO0, &pdata);
         dbx500_add_pinctrl(parent, "pinctrl-db8500", U8500_PRCMU_BASE);
 }
diff --git a/arch/arm/mach-ux500/pins-db8500.h b/arch/arm/mach-ux500/pins-db8500.h
deleted file mode 100644
index 062c7acf4576..000000000000
--- a/arch/arm/mach-ux500/pins-db8500.h
+++ /dev/null
@@ -1,746 +0,0 @@
-/*
- * Copyright (C) ST-Ericsson SA 2010
- *
- * License terms: GNU General Public License, version 2
- * Author: Rabin Vincent <rabin.vincent@stericsson.com>
- */
-
-#ifndef __MACH_PINS_DB8500_H
-#define __MACH_PINS_DB8500_H
-
-/*
- * TODO: Eventually encode all non-board specific pull up/down configuration
- * here.
- */
-
-#define GPIO0_GPIO              PIN_CFG(0, GPIO)
-#define GPIO0_U0_CTSn           PIN_CFG(0, ALT_A)
-#define GPIO0_TRIG_OUT          PIN_CFG(0, ALT_B)
-#define GPIO0_IP_TDO            PIN_CFG(0, ALT_C)
-
-#define GPIO1_GPIO              PIN_CFG(1, GPIO)
-#define GPIO1_U0_RTSn           PIN_CFG(1, ALT_A)
-#define GPIO1_TRIG_IN           PIN_CFG(1, ALT_B)
-#define GPIO1_IP_TDI            PIN_CFG(1, ALT_C)
-
-#define GPIO2_GPIO              PIN_CFG(2, GPIO)
-#define GPIO2_U0_RXD            PIN_CFG(2, ALT_A)
-#define GPIO2_NONE              PIN_CFG(2, ALT_B)
-#define GPIO2_IP_TMS            PIN_CFG(2, ALT_C)
-
-#define GPIO3_GPIO              PIN_CFG(3, GPIO)
-#define GPIO3_U0_TXD            PIN_CFG(3, ALT_A)
-#define GPIO3_NONE              PIN_CFG(3, ALT_B)
-#define GPIO3_IP_TCK            PIN_CFG(3, ALT_C)
-
-#define GPIO4_GPIO              PIN_CFG(4, GPIO)
-#define GPIO4_U1_RXD            PIN_CFG(4, ALT_A)
-#define GPIO4_I2C4_SCL          PIN_CFG(4, ALT_B)
-#define GPIO4_IP_TRSTn          PIN_CFG(4, ALT_C)
-
-#define GPIO5_GPIO              PIN_CFG(5, GPIO)
-#define GPIO5_U1_TXD            PIN_CFG(5, ALT_A)
-#define GPIO5_I2C4_SDA          PIN_CFG(5, ALT_B)
-#define GPIO5_IP_GPIO6          PIN_CFG(5, ALT_C)
-
-#define GPIO6_GPIO              PIN_CFG(6, GPIO)
-#define GPIO6_U1_CTSn           PIN_CFG(6, ALT_A)
-#define GPIO6_I2C1_SCL          PIN_CFG(6, ALT_B)
-#define GPIO6_IP_GPIO0          PIN_CFG(6, ALT_C)
-
-#define GPIO7_GPIO              PIN_CFG(7, GPIO)
-#define GPIO7_U1_RTSn           PIN_CFG(7, ALT_A)
-#define GPIO7_I2C1_SDA          PIN_CFG(7, ALT_B)
-#define GPIO7_IP_GPIO1          PIN_CFG(7, ALT_C)
-
-#define GPIO8_GPIO              PIN_CFG(8, GPIO)
-#define GPIO8_IPI2C_SDA         PIN_CFG(8, ALT_A)
-#define GPIO8_I2C2_SDA          PIN_CFG(8, ALT_B)
-
-#define GPIO9_GPIO              PIN_CFG(9, GPIO)
-#define GPIO9_IPI2C_SCL         PIN_CFG(9, ALT_A)
-#define GPIO9_I2C2_SCL          PIN_CFG(9, ALT_B)
-
-#define GPIO10_GPIO             PIN_CFG(10, GPIO)
-#define GPIO10_IPI2C_SDA        PIN_CFG(10, ALT_A)
-#define GPIO10_I2C2_SDA         PIN_CFG(10, ALT_B)
-#define GPIO10_IP_GPIO3         PIN_CFG(10, ALT_C)
-
-#define GPIO11_GPIO             PIN_CFG(11, GPIO)
-#define GPIO11_IPI2C_SCL        PIN_CFG(11, ALT_A)
-#define GPIO11_I2C2_SCL         PIN_CFG(11, ALT_B)
-#define GPIO11_IP_GPIO2         PIN_CFG(11, ALT_C)
-
-#define GPIO12_GPIO             PIN_CFG(12, GPIO)
-#define GPIO12_MSP0_TXD         PIN_CFG(12, ALT_A)
-#define GPIO12_MSP0_RXD         PIN_CFG(12, ALT_B)
-
-#define GPIO13_GPIO             PIN_CFG(13, GPIO)
-#define GPIO13_MSP0_TFS         PIN_CFG(13, ALT_A)
-
-#define GPIO14_GPIO             PIN_CFG(14, GPIO)
-#define GPIO14_MSP0_TCK         PIN_CFG(14, ALT_A)
-
-#define GPIO15_GPIO             PIN_CFG(15, GPIO)
-#define GPIO15_MSP0_RXD         PIN_CFG(15, ALT_A)
-#define GPIO15_MSP0_TXD         PIN_CFG(15, ALT_B)
-
-#define GPIO16_GPIO             PIN_CFG(16, GPIO)
-#define GPIO16_MSP0_RFS         PIN_CFG(16, ALT_A)
-#define GPIO16_I2C1_SCL         PIN_CFG(16, ALT_B)
-#define GPIO16_SLIM0_DAT        PIN_CFG(16, ALT_C)
-
-#define GPIO17_GPIO             PIN_CFG(17, GPIO)
-#define GPIO17_MSP0_RCK         PIN_CFG(17, ALT_A)
-#define GPIO17_I2C1_SDA         PIN_CFG(17, ALT_B)
-#define GPIO17_SLIM0_CLK        PIN_CFG(17, ALT_C)
-
-#define GPIO18_GPIO             PIN_CFG(18, GPIO)
-#define GPIO18_MC0_CMDDIR       PIN_CFG_INPUT(18, ALT_A, PULLUP)
-#define GPIO18_U2_RXD           PIN_CFG(18, ALT_B)
-#define GPIO18_MS_IEP           PIN_CFG(18, ALT_C)
-
-#define GPIO19_GPIO             PIN_CFG(19, GPIO)
-#define GPIO19_MC0_DAT0DIR      PIN_CFG_INPUT(19, ALT_A, PULLUP)
-#define GPIO19_U2_TXD           PIN_CFG(19, ALT_B)
-#define GPIO19_MS_DAT0DIR       PIN_CFG(19, ALT_C)
-
-#define GPIO20_GPIO             PIN_CFG(20, GPIO)
-#define GPIO20_MC0_DAT2DIR      PIN_CFG_INPUT(20, ALT_A, PULLUP)
-#define GPIO20_UARTMOD_TXD      PIN_CFG(20, ALT_B)
-#define GPIO20_IP_TRIGOUT       PIN_CFG(20, ALT_C)
-
-#define GPIO21_GPIO             PIN_CFG(21, GPIO)
-#define GPIO21_MC0_DAT31DIR     PIN_CFG_INPUT(21, ALT_A, PULLUP)
-#define GPIO21_MSP0_SCK         PIN_CFG(21, ALT_B)
-#define GPIO21_MS_DAT31DIR      PIN_CFG(21, ALT_C)
-
-#define GPIO22_GPIO             PIN_CFG(22, GPIO)
-#define GPIO22_MC0_FBCLK        PIN_CFG_INPUT(22, ALT_A, PULLUP)
-#define GPIO22_UARTMOD_RXD      PIN_CFG(22, ALT_B)
-#define GPIO22_MS_FBCLK         PIN_CFG(22, ALT_C)
-
-#define GPIO23_GPIO             PIN_CFG(23, GPIO)
-#define GPIO23_MC0_CLK          PIN_CFG_INPUT(23, ALT_A, PULLUP)
-#define GPIO23_STMMOD_CLK       PIN_CFG(23, ALT_B)
-#define GPIO23_MS_CLK           PIN_CFG(23, ALT_C)
-
-#define GPIO24_GPIO             PIN_CFG(24, GPIO)
-#define GPIO24_MC0_CMD          PIN_CFG_INPUT(24, ALT_A, PULLUP)
-#define GPIO24_UARTMOD_RXD      PIN_CFG(24, ALT_B)
-#define GPIO24_MS_BS            PIN_CFG(24, ALT_C)
-
-#define GPIO25_GPIO             PIN_CFG(25, GPIO)
-#define GPIO25_MC0_DAT0         PIN_CFG_INPUT(25, ALT_A, PULLUP)
-#define GPIO25_STMMOD_DAT0      PIN_CFG(25, ALT_B)
-#define GPIO25_MS_DAT0          PIN_CFG(25, ALT_C)
-
-#define GPIO26_GPIO             PIN_CFG(26, GPIO)
-#define GPIO26_MC0_DAT1         PIN_CFG_INPUT(26, ALT_A, PULLUP)
-#define GPIO26_STMMOD_DAT1      PIN_CFG(26, ALT_B)
-#define GPIO26_MS_DAT1          PIN_CFG(26, ALT_C)
-
-#define GPIO27_GPIO             PIN_CFG(27, GPIO)
-#define GPIO27_MC0_DAT2         PIN_CFG_INPUT(27, ALT_A, PULLUP)
-#define GPIO27_STMMOD_DAT2      PIN_CFG(27, ALT_B)
-#define GPIO27_MS_DAT2          PIN_CFG(27, ALT_C)
-
-#define GPIO28_GPIO             PIN_CFG(28, GPIO)
-#define GPIO28_MC0_DAT3         PIN_CFG_INPUT(28, ALT_A, PULLUP)
-#define GPIO28_STMMOD_DAT3      PIN_CFG(28, ALT_B)
-#define GPIO28_MS_DAT3          PIN_CFG(28, ALT_C)
-
-#define GPIO29_GPIO             PIN_CFG(29, GPIO)
-#define GPIO29_MC0_DAT4         PIN_CFG(29, ALT_A)
-#define GPIO29_SPI3_CLK         PIN_CFG(29, ALT_B)
-#define GPIO29_U2_RXD           PIN_CFG(29, ALT_C)
-
-#define GPIO30_GPIO             PIN_CFG(30, GPIO)
-#define GPIO30_MC0_DAT5         PIN_CFG(30, ALT_A)
-#define GPIO30_SPI3_RXD         PIN_CFG(30, ALT_B)
-#define GPIO30_U2_TXD           PIN_CFG(30, ALT_C)
-
-#define GPIO31_GPIO             PIN_CFG(31, GPIO)
-#define GPIO31_MC0_DAT6         PIN_CFG(31, ALT_A)
-#define GPIO31_SPI3_FRM         PIN_CFG(31, ALT_B)
-#define GPIO31_U2_CTSn          PIN_CFG(31, ALT_C)
-
-#define GPIO32_GPIO             PIN_CFG(32, GPIO)
-#define GPIO32_MC0_DAT7         PIN_CFG(32, ALT_A)
-#define GPIO32_SPI3_TXD         PIN_CFG(32, ALT_B)
-#define GPIO32_U2_RTSn          PIN_CFG(32, ALT_C)
-
-#define GPIO33_GPIO             PIN_CFG(33, GPIO)
-#define GPIO33_MSP1_TXD         PIN_CFG(33, ALT_A)
-#define GPIO33_MSP1_RXD         PIN_CFG(33, ALT_B)
-#define GPIO33_U0_DTRn          PIN_CFG(33, ALT_C)
-
-#define GPIO34_GPIO             PIN_CFG(34, GPIO)
-#define GPIO34_MSP1_TFS         PIN_CFG(34, ALT_A)
-#define GPIO34_NONE             PIN_CFG(34, ALT_B)
-#define GPIO34_U0_DCDn          PIN_CFG(34, ALT_C)
-
-#define GPIO35_GPIO             PIN_CFG(35, GPIO)
-#define GPIO35_MSP1_TCK         PIN_CFG(35, ALT_A)
-#define GPIO35_NONE             PIN_CFG(35, ALT_B)
-#define GPIO35_U0_DSRn          PIN_CFG(35, ALT_C)
-
-#define GPIO36_GPIO             PIN_CFG(36, GPIO)
-#define GPIO36_MSP1_RXD         PIN_CFG(36, ALT_A)
-#define GPIO36_MSP1_TXD         PIN_CFG(36, ALT_B)
-#define GPIO36_U0_RIn           PIN_CFG(36, ALT_C)
-
-#define GPIO64_GPIO             PIN_CFG(64, GPIO)
-#define GPIO64_LCDB_DE          PIN_CFG(64, ALT_A)
-#define GPIO64_KP_O1            PIN_CFG(64, ALT_B)
-#define GPIO64_IP_GPIO4         PIN_CFG(64, ALT_C)
-
-#define GPIO65_GPIO             PIN_CFG(65, GPIO)
-#define GPIO65_LCDB_HSO         PIN_CFG(65, ALT_A)
-#define GPIO65_KP_O0            PIN_CFG(65, ALT_B)
-#define GPIO65_IP_GPIO5         PIN_CFG(65, ALT_C)
-
-#define GPIO66_GPIO             PIN_CFG(66, GPIO)
-#define GPIO66_LCDB_VSO         PIN_CFG(66, ALT_A)
-#define GPIO66_KP_I1            PIN_CFG(66, ALT_B)
-#define GPIO66_IP_GPIO6         PIN_CFG(66, ALT_C)
-
-#define GPIO67_GPIO             PIN_CFG(67, GPIO)
-#define GPIO67_LCDB_CLK         PIN_CFG(67, ALT_A)
-#define GPIO67_KP_I0            PIN_CFG(67, ALT_B)
-#define GPIO67_IP_GPIO7         PIN_CFG(67, ALT_C)
-
-#define GPIO68_GPIO             PIN_CFG(68, GPIO)
-#define GPIO68_LCD_VSI0         PIN_CFG(68, ALT_A)
-#define GPIO68_KP_O7            PIN_CFG(68, ALT_B)
-#define GPIO68_SM_CLE           PIN_CFG(68, ALT_C)
-
-#define GPIO69_GPIO             PIN_CFG(69, GPIO)
-#define GPIO69_LCD_VSI1         PIN_CFG(69, ALT_A)
-#define GPIO69_KP_I7            PIN_CFG(69, ALT_B)
-#define GPIO69_SM_ALE           PIN_CFG(69, ALT_C)
-
-#define GPIO70_GPIO             PIN_CFG(70, GPIO)
-#define GPIO70_LCD_D0           PIN_CFG(70, ALT_A)
-#define GPIO70_KP_O5            PIN_CFG(70, ALT_B)
-#define GPIO70_STMAPE_CLK       PIN_CFG(70, ALT_C)
-
-#define GPIO71_GPIO             PIN_CFG(71, GPIO)
-#define GPIO71_LCD_D1           PIN_CFG(71, ALT_A)
-#define GPIO71_KP_O4            PIN_CFG(71, ALT_B)
-#define GPIO71_STMAPE_DAT3      PIN_CFG(71, ALT_C)
-
-#define GPIO72_GPIO             PIN_CFG(72, GPIO)
-#define GPIO72_LCD_D2           PIN_CFG(72, ALT_A)
-#define GPIO72_KP_O3            PIN_CFG(72, ALT_B)
-#define GPIO72_STMAPE_DAT2      PIN_CFG(72, ALT_C)
-
-#define GPIO73_GPIO             PIN_CFG(73, GPIO)
-#define GPIO73_LCD_D3           PIN_CFG(73, ALT_A)
-#define GPIO73_KP_O2            PIN_CFG(73, ALT_B)
-#define GPIO73_STMAPE_DAT1      PIN_CFG(73, ALT_C)
-
-#define GPIO74_GPIO             PIN_CFG(74, GPIO)
-#define GPIO74_LCD_D4           PIN_CFG(74, ALT_A)
-#define GPIO74_KP_I5            PIN_CFG(74, ALT_B)
-#define GPIO74_STMAPE_DAT0      PIN_CFG(74, ALT_C)
-
-#define GPIO75_GPIO             PIN_CFG(75, GPIO)
-#define GPIO75_LCD_D5           PIN_CFG(75, ALT_A)
-#define GPIO75_KP_I4            PIN_CFG(75, ALT_B)
-#define GPIO75_U2_RXD           PIN_CFG(75, ALT_C)
-
-#define GPIO76_GPIO             PIN_CFG(76, GPIO)
-#define GPIO76_LCD_D6           PIN_CFG(76, ALT_A)
-#define GPIO76_KP_I3            PIN_CFG(76, ALT_B)
-#define GPIO76_U2_TXD           PIN_CFG(76, ALT_C)
-
-#define GPIO77_GPIO             PIN_CFG(77, GPIO)
-#define GPIO77_LCD_D7           PIN_CFG(77, ALT_A)
-#define GPIO77_KP_I2            PIN_CFG(77, ALT_B)
-#define GPIO77_NONE             PIN_CFG(77, ALT_C)
-
-#define GPIO78_GPIO             PIN_CFG(78, GPIO)
-#define GPIO78_LCD_D8           PIN_CFG(78, ALT_A)
-#define GPIO78_KP_O6            PIN_CFG(78, ALT_B)
-#define GPIO78_IP_GPIO2         PIN_CFG(78, ALT_C)
-
-#define GPIO79_GPIO             PIN_CFG(79, GPIO)
-#define GPIO79_LCD_D9           PIN_CFG(79, ALT_A)
-#define GPIO79_KP_I6            PIN_CFG(79, ALT_B)
-#define GPIO79_IP_GPIO3         PIN_CFG(79, ALT_C)
-
-#define GPIO80_GPIO             PIN_CFG(80, GPIO)
-#define GPIO80_LCD_D10          PIN_CFG(80, ALT_A)
-#define GPIO80_KP_SKA0          PIN_CFG(80, ALT_B)
-#define GPIO80_IP_GPIO4         PIN_CFG(80, ALT_C)
-
-#define GPIO81_GPIO             PIN_CFG(81, GPIO)
-#define GPIO81_LCD_D11          PIN_CFG(81, ALT_A)
-#define GPIO81_KP_SKB0          PIN_CFG(81, ALT_B)
-#define GPIO81_IP_GPIO5         PIN_CFG(81, ALT_C)
-
-#define GPIO82_GPIO             PIN_CFG(82, GPIO)
-#define GPIO82_LCD_D12          PIN_CFG(82, ALT_A)
-#define GPIO82_KP_O5            PIN_CFG(82, ALT_B)
-
-#define GPIO83_GPIO             PIN_CFG(83, GPIO)
-#define GPIO83_LCD_D13          PIN_CFG(83, ALT_A)
-#define GPIO83_KP_O4            PIN_CFG(83, ALT_B)
-
-#define GPIO84_GPIO             PIN_CFG(84, GPIO)
-#define GPIO84_LCD_D14          PIN_CFG(84, ALT_A)
-#define GPIO84_KP_I5            PIN_CFG(84, ALT_B)
-
-#define GPIO85_GPIO             PIN_CFG(85, GPIO)
-#define GPIO85_LCD_D15          PIN_CFG(85, ALT_A)
-#define GPIO85_KP_I4            PIN_CFG(85, ALT_B)
-
-#define GPIO86_GPIO             PIN_CFG(86, GPIO)
-#define GPIO86_LCD_D16          PIN_CFG(86, ALT_A)
-#define GPIO86_SM_ADQ0          PIN_CFG(86, ALT_B)
-#define GPIO86_MC5_DAT0         PIN_CFG(86, ALT_C)
-
-#define GPIO87_GPIO             PIN_CFG(87, GPIO)
-#define GPIO87_LCD_D17          PIN_CFG(87, ALT_A)
-#define GPIO87_SM_ADQ1          PIN_CFG(87, ALT_B)
-#define GPIO87_MC5_DAT1         PIN_CFG(87, ALT_C)
-
-#define GPIO88_GPIO             PIN_CFG(88, GPIO)
-#define GPIO88_LCD_D18          PIN_CFG(88, ALT_A)
-#define GPIO88_SM_ADQ2          PIN_CFG(88, ALT_B)
-#define GPIO88_MC5_DAT2         PIN_CFG(88, ALT_C)
-
-#define GPIO89_GPIO             PIN_CFG(89, GPIO)
-#define GPIO89_LCD_D19          PIN_CFG(89, ALT_A)
-#define GPIO89_SM_ADQ3          PIN_CFG(89, ALT_B)
-#define GPIO89_MC5_DAT3         PIN_CFG(89, ALT_C)
-
-#define GPIO90_GPIO             PIN_CFG(90, GPIO)
-#define GPIO90_LCD_D20          PIN_CFG(90, ALT_A)
-#define GPIO90_SM_ADQ4          PIN_CFG(90, ALT_B)
-#define GPIO90_MC5_CMD          PIN_CFG(90, ALT_C)
-
-#define GPIO91_GPIO             PIN_CFG(91, GPIO)
-#define GPIO91_LCD_D21          PIN_CFG(91, ALT_A)
-#define GPIO91_SM_ADQ5          PIN_CFG(91, ALT_B)
-#define GPIO91_MC5_FBCLK        PIN_CFG(91, ALT_C)
-
-#define GPIO92_GPIO             PIN_CFG(92, GPIO)
-#define GPIO92_LCD_D22          PIN_CFG(92, ALT_A)
-#define GPIO92_SM_ADQ6          PIN_CFG(92, ALT_B)
-#define GPIO92_MC5_CLK          PIN_CFG(92, ALT_C)
-
-#define GPIO93_GPIO             PIN_CFG(93, GPIO)
-#define GPIO93_LCD_D23          PIN_CFG(93, ALT_A)
-#define GPIO93_SM_ADQ7          PIN_CFG(93, ALT_B)
-#define GPIO93_MC5_DAT4         PIN_CFG(93, ALT_C)
-
-#define GPIO94_GPIO             PIN_CFG(94, GPIO)
-#define GPIO94_KP_O7            PIN_CFG(94, ALT_A)
-#define GPIO94_SM_ADVn          PIN_CFG(94, ALT_B)
-#define GPIO94_MC5_DAT5         PIN_CFG(94, ALT_C)
-
-#define GPIO95_GPIO             PIN_CFG(95, GPIO)
-#define GPIO95_KP_I7            PIN_CFG(95, ALT_A)
-#define GPIO95_SM_CS0n          PIN_CFG(95, ALT_B)
-#define GPIO95_SM_PS0n          PIN_CFG(95, ALT_C)
-
-#define GPIO96_GPIO             PIN_CFG(96, GPIO)
-#define GPIO96_KP_O6            PIN_CFG(96, ALT_A)
-#define GPIO96_SM_OEn           PIN_CFG(96, ALT_B)
-#define GPIO96_MC5_DAT6         PIN_CFG(96, ALT_C)
-
-#define GPIO97_GPIO             PIN_CFG(97, GPIO)
-#define GPIO97_KP_I6            PIN_CFG(97, ALT_A)
-#define GPIO97_SM_WEn           PIN_CFG(97, ALT_B)
-#define GPIO97_MC5_DAT7         PIN_CFG(97, ALT_C)
-
-#define GPIO128_GPIO            PIN_CFG(128, GPIO)
-#define GPIO128_MC2_CLK         PIN_CFG_INPUT(128, ALT_A, PULLUP)
-#define GPIO128_SM_CKO          PIN_CFG(128, ALT_B)
-
-#define GPIO129_GPIO            PIN_CFG(129, GPIO)
-#define GPIO129_MC2_CMD         PIN_CFG_INPUT(129, ALT_A, PULLUP)
-#define GPIO129_SM_WAIT0n       PIN_CFG(129, ALT_B)
-
-#define GPIO130_GPIO            PIN_CFG(130, GPIO)
-#define GPIO130_MC2_FBCLK       PIN_CFG_INPUT(130, ALT_A, PULLUP)
-#define GPIO130_SM_FBCLK        PIN_CFG(130, ALT_B)
-#define GPIO130_MC2_RSTN        PIN_CFG(130, ALT_C)
-
-#define GPIO131_GPIO            PIN_CFG(131, GPIO)
-#define GPIO131_MC2_DAT0        PIN_CFG_INPUT(131, ALT_A, PULLUP)
-#define GPIO131_SM_ADQ8         PIN_CFG(131, ALT_B)
-
-#define GPIO132_GPIO            PIN_CFG(132, GPIO)
-#define GPIO132_MC2_DAT1        PIN_CFG_INPUT(132, ALT_A, PULLUP)
-#define GPIO132_SM_ADQ9         PIN_CFG(132, ALT_B)
-
-#define GPIO133_GPIO            PIN_CFG(133, GPIO)
-#define GPIO133_MC2_DAT2        PIN_CFG_INPUT(133, ALT_A, PULLUP)
-#define GPIO133_SM_ADQ10        PIN_CFG(133, ALT_B)
-
-#define GPIO134_GPIO            PIN_CFG(134, GPIO)
-#define GPIO134_MC2_DAT3        PIN_CFG_INPUT(134, ALT_A, PULLUP)
-#define GPIO134_SM_ADQ11        PIN_CFG(134, ALT_B)
-
-#define GPIO135_GPIO            PIN_CFG(135, GPIO)
-#define GPIO135_MC2_DAT4        PIN_CFG_INPUT(135, ALT_A, PULLUP)
-#define GPIO135_SM_ADQ12        PIN_CFG(135, ALT_B)
-
-#define GPIO136_GPIO            PIN_CFG(136, GPIO)
-#define GPIO136_MC2_DAT5        PIN_CFG_INPUT(136, ALT_A, PULLUP)
-#define GPIO136_SM_ADQ13        PIN_CFG(136, ALT_B)
-
-#define GPIO137_GPIO            PIN_CFG(137, GPIO)
-#define GPIO137_MC2_DAT6        PIN_CFG_INPUT(137, ALT_A, PULLUP)
-#define GPIO137_SM_ADQ14        PIN_CFG(137, ALT_B)
-
-#define GPIO138_GPIO            PIN_CFG(138, GPIO)
-#define GPIO138_MC2_DAT7        PIN_CFG_INPUT(138, ALT_A, PULLUP)
-#define GPIO138_SM_ADQ15        PIN_CFG(138, ALT_B)
-
-#define GPIO139_GPIO            PIN_CFG(139, GPIO)
-#define GPIO139_SSP1_RXD        PIN_CFG(139, ALT_A)
-#define GPIO139_SM_WAIT1n       PIN_CFG(139, ALT_B)
-#define GPIO139_KP_O8           PIN_CFG(139, ALT_C)
-
-#define GPIO140_GPIO            PIN_CFG(140, GPIO)
-#define GPIO140_SSP1_TXD        PIN_CFG(140, ALT_A)
-#define GPIO140_IP_GPIO7        PIN_CFG(140, ALT_B)
-#define GPIO140_KP_SKA1         PIN_CFG(140, ALT_C)
-
-#define GPIO141_GPIO            PIN_CFG(141, GPIO)
-#define GPIO141_SSP1_CLK        PIN_CFG(141, ALT_A)
-#define GPIO141_IP_GPIO2        PIN_CFG(141, ALT_B)
-#define GPIO141_KP_O9           PIN_CFG(141, ALT_C)
-
-#define GPIO142_GPIO            PIN_CFG(142, GPIO)
-#define GPIO142_SSP1_FRM        PIN_CFG(142, ALT_A)
-#define GPIO142_IP_GPIO3        PIN_CFG(142, ALT_B)
-#define GPIO142_KP_SKB1         PIN_CFG(142, ALT_C)
-
-#define GPIO143_GPIO            PIN_CFG(143, GPIO)
-#define GPIO143_SSP0_CLK        PIN_CFG(143, ALT_A)
-
-#define GPIO144_GPIO            PIN_CFG(144, GPIO)
-#define GPIO144_SSP0_FRM        PIN_CFG(144, ALT_A)
-
-#define GPIO145_GPIO            PIN_CFG(145, GPIO)
-#define GPIO145_SSP0_RXD        PIN_CFG(145, ALT_A)
-
-#define GPIO146_GPIO            PIN_CFG(146, GPIO)
-#define GPIO146_SSP0_TXD        PIN_CFG(146, ALT_A)
-
-#define GPIO147_GPIO            PIN_CFG(147, GPIO)
-#define GPIO147_I2C0_SCL        PIN_CFG(147, ALT_A)
-
-#define GPIO148_GPIO            PIN_CFG(148, GPIO)
-#define GPIO148_I2C0_SDA        PIN_CFG(148, ALT_A)
-
-#define GPIO149_GPIO            PIN_CFG(149, GPIO)
-#define GPIO149_IP_GPIO0        PIN_CFG(149, ALT_A)
-#define GPIO149_SM_CS1n         PIN_CFG(149, ALT_B)
-#define GPIO149_SM_PS1n         PIN_CFG(149, ALT_C)
-
-#define GPIO150_GPIO            PIN_CFG(150, GPIO)
-#define GPIO150_IP_GPIO1        PIN_CFG(150, ALT_A)
-#define GPIO150_LCDA_CLK        PIN_CFG(150, ALT_B)
-
-#define GPIO151_GPIO            PIN_CFG(151, GPIO)
-#define GPIO151_KP_SKA0         PIN_CFG(151, ALT_A)
-#define GPIO151_LCD_VSI0        PIN_CFG(151, ALT_B)
-#define GPIO151_KP_O8           PIN_CFG(151, ALT_C)
-
-#define GPIO152_GPIO            PIN_CFG(152, GPIO)
-#define GPIO152_KP_SKB0         PIN_CFG(152, ALT_A)
-#define GPIO152_LCD_VSI1        PIN_CFG(152, ALT_B)
-#define GPIO152_KP_O9           PIN_CFG(152, ALT_C)
-
-#define GPIO153_GPIO            PIN_CFG(153, GPIO)
-#define GPIO153_KP_I7           PIN_CFG(153, ALT_A)
-#define GPIO153_LCD_D24         PIN_CFG(153, ALT_B)
-#define GPIO153_U2_RXD          PIN_CFG(153, ALT_C)
-
-#define GPIO154_GPIO            PIN_CFG(154, GPIO)
-#define GPIO154_KP_I6           PIN_CFG(154, ALT_A)
-#define GPIO154_LCD_D25         PIN_CFG(154, ALT_B)
-#define GPIO154_U2_TXD          PIN_CFG(154, ALT_C)
-
-#define GPIO155_GPIO            PIN_CFG(155, GPIO)
-#define GPIO155_KP_I5           PIN_CFG(155, ALT_A)
-#define GPIO155_LCD_D26         PIN_CFG(155, ALT_B)
-#define GPIO155_STMAPE_CLK      PIN_CFG(155, ALT_C)
-
-#define GPIO156_GPIO            PIN_CFG(156, GPIO)
-#define GPIO156_KP_I4           PIN_CFG(156, ALT_A)
-#define GPIO156_LCD_D27         PIN_CFG(156, ALT_B)
-#define GPIO156_STMAPE_DAT3     PIN_CFG(156, ALT_C)
-
-#define GPIO157_GPIO            PIN_CFG(157, GPIO)
-#define GPIO157_KP_O7           PIN_CFG(157, ALT_A)
-#define GPIO157_LCD_D28         PIN_CFG(157, ALT_B)
-#define GPIO157_STMAPE_DAT2     PIN_CFG(157, ALT_C)
-
-#define GPIO158_GPIO            PIN_CFG(158, GPIO)
-#define GPIO158_KP_O6           PIN_CFG(158, ALT_A)
-#define GPIO158_LCD_D29         PIN_CFG(158, ALT_B)
-#define GPIO158_STMAPE_DAT1     PIN_CFG(158, ALT_C)
-
-#define GPIO159_GPIO            PIN_CFG(159, GPIO)
-#define GPIO159_KP_O5           PIN_CFG(159, ALT_A)
-#define GPIO159_LCD_D30         PIN_CFG(159, ALT_B)
-#define GPIO159_STMAPE_DAT0     PIN_CFG(159, ALT_C)
-
-#define GPIO160_GPIO            PIN_CFG(160, GPIO)
-#define GPIO160_KP_O4           PIN_CFG(160, ALT_A)
-#define GPIO160_LCD_D31         PIN_CFG(160, ALT_B)
-#define GPIO160_NONE            PIN_CFG(160, ALT_C)
-
-#define GPIO161_GPIO            PIN_CFG(161, GPIO)
-#define GPIO161_KP_I3           PIN_CFG(161, ALT_A)
-#define GPIO161_LCD_D32         PIN_CFG(161, ALT_B)
-#define GPIO161_UARTMOD_RXD     PIN_CFG(161, ALT_C)
-
-#define GPIO162_GPIO            PIN_CFG(162, GPIO)
-#define GPIO162_KP_I2           PIN_CFG(162, ALT_A)
-#define GPIO162_LCD_D33         PIN_CFG(162, ALT_B)
-#define GPIO162_UARTMOD_TXD     PIN_CFG(162, ALT_C)
-
-#define GPIO163_GPIO            PIN_CFG(163, GPIO)
-#define GPIO163_KP_I1           PIN_CFG(163, ALT_A)
-#define GPIO163_LCD_D34         PIN_CFG(163, ALT_B)
-#define GPIO163_STMMOD_CLK      PIN_CFG(163, ALT_C)
-
-#define GPIO164_GPIO            PIN_CFG(164, GPIO)
-#define GPIO164_KP_I0           PIN_CFG(164, ALT_A)
-#define GPIO164_LCD_D35         PIN_CFG(164, ALT_B)
-#define GPIO164_STMMOD_DAT3     PIN_CFG(164, ALT_C)
-
-#define GPIO165_GPIO            PIN_CFG(165, GPIO)
-#define GPIO165_KP_O3           PIN_CFG(165, ALT_A)
-#define GPIO165_LCD_D36         PIN_CFG(165, ALT_B)
-#define GPIO165_STMMOD_DAT2     PIN_CFG(165, ALT_C)
-
-#define GPIO166_GPIO            PIN_CFG(166, GPIO)
-#define GPIO166_KP_O2           PIN_CFG(166, ALT_A)
-#define GPIO166_LCD_D37         PIN_CFG(166, ALT_B)
-#define GPIO166_STMMOD_DAT1     PIN_CFG(166, ALT_C)
-
-#define GPIO167_GPIO            PIN_CFG(167, GPIO)
-#define GPIO167_KP_O1           PIN_CFG(167, ALT_A)
-#define GPIO167_LCD_D38         PIN_CFG(167, ALT_B)
-#define GPIO167_STMMOD_DAT0     PIN_CFG(167, ALT_C)
-
-#define GPIO168_GPIO            PIN_CFG(168, GPIO)
-#define GPIO168_KP_O0           PIN_CFG(168, ALT_A)
-#define GPIO168_LCD_D39         PIN_CFG(168, ALT_B)
-#define GPIO168_NONE            PIN_CFG(168, ALT_C)
-
-#define GPIO169_GPIO            PIN_CFG(169, GPIO)
-#define GPIO169_RF_PURn         PIN_CFG(169, ALT_A)
-#define GPIO169_LCDA_DE         PIN_CFG(169, ALT_B)
-#define GPIO169_USBSIM_PDC      PIN_CFG(169, ALT_C)
-
-#define GPIO170_GPIO            PIN_CFG(170, GPIO)
-#define GPIO170_MODEM_STATE     PIN_CFG(170, ALT_A)
-#define GPIO170_LCDA_VSO        PIN_CFG(170, ALT_B)
-#define GPIO170_KP_SKA1         PIN_CFG(170, ALT_C)
-
-#define GPIO171_GPIO            PIN_CFG(171, GPIO)
-#define GPIO171_MODEM_PWREN     PIN_CFG(171, ALT_A)
-#define GPIO171_LCDA_HSO        PIN_CFG(171, ALT_B)
-#define GPIO171_KP_SKB1         PIN_CFG(171, ALT_C)
-
-#define GPIO192_GPIO            PIN_CFG(192, GPIO)
-#define GPIO192_MSP2_SCK        PIN_CFG(192, ALT_A)
-
-#define GPIO193_GPIO            PIN_CFG(193, GPIO)
-#define GPIO193_MSP2_TXD        PIN_CFG(193, ALT_A)
-
-#define GPIO194_GPIO            PIN_CFG(194, GPIO)
-#define GPIO194_MSP2_TCK        PIN_CFG(194, ALT_A)
-
-#define GPIO195_GPIO            PIN_CFG(195, GPIO)
-#define GPIO195_MSP2_TFS        PIN_CFG(195, ALT_A)
-
-#define GPIO196_GPIO            PIN_CFG(196, GPIO)
-#define GPIO196_MSP2_RXD        PIN_CFG(196, ALT_A)
-
-#define GPIO197_GPIO            PIN_CFG(197, GPIO)
-#define GPIO197_MC4_DAT3        PIN_CFG_INPUT(197, ALT_A, PULLUP)
-
-#define GPIO198_GPIO            PIN_CFG(198, GPIO)
-#define GPIO198_MC4_DAT2        PIN_CFG_INPUT(198, ALT_A, PULLUP)
-
-#define GPIO199_GPIO            PIN_CFG(199, GPIO)
-#define GPIO199_MC4_DAT1        PIN_CFG_INPUT(199, ALT_A, PULLUP)
-
-#define GPIO200_GPIO            PIN_CFG(200, GPIO)
-#define GPIO200_MC4_DAT0        PIN_CFG_INPUT(200, ALT_A, PULLUP)
-
-#define GPIO201_GPIO            PIN_CFG(201, GPIO)
-#define GPIO201_MC4_CMD         PIN_CFG_INPUT(201, ALT_A, PULLUP)
-
-#define GPIO202_GPIO            PIN_CFG(202, GPIO)
-#define GPIO202_MC4_FBCLK       PIN_CFG_INPUT(202, ALT_A, PULLUP)
-#define GPIO202_PWL             PIN_CFG(202, ALT_B)
-#define GPIO202_MC4_RSTN        PIN_CFG(202, ALT_C)
-
-#define GPIO203_GPIO            PIN_CFG(203, GPIO)
-#define GPIO203_MC4_CLK         PIN_CFG_INPUT(203, ALT_A, PULLUP)
-
-#define GPIO204_GPIO            PIN_CFG(204, GPIO)
-#define GPIO204_MC4_DAT7        PIN_CFG_INPUT(204, ALT_A, PULLUP)
-
-#define GPIO205_GPIO            PIN_CFG(205, GPIO)
-#define GPIO205_MC4_DAT6        PIN_CFG_INPUT(205, ALT_A, PULLUP)
-
-#define GPIO206_GPIO            PIN_CFG(206, GPIO)
-#define GPIO206_MC4_DAT5        PIN_CFG_INPUT(206, ALT_A, PULLUP)
-
-#define GPIO207_GPIO            PIN_CFG(207, GPIO)
-#define GPIO207_MC4_DAT4        PIN_CFG_INPUT(207, ALT_A, PULLUP)
-
-#define GPIO208_GPIO            PIN_CFG(208, GPIO)
-#define GPIO208_MC1_CLK         PIN_CFG(208, ALT_A)
-
-#define GPIO209_GPIO            PIN_CFG(209, GPIO)
-#define GPIO209_MC1_FBCLK       PIN_CFG(209, ALT_A)
-#define GPIO209_SPI1_CLK        PIN_CFG(209, ALT_B)
-
-#define GPIO210_GPIO            PIN_CFG(210, GPIO)
-#define GPIO210_MC1_CMD         PIN_CFG(210, ALT_A)
-
-#define GPIO211_GPIO            PIN_CFG(211, GPIO)
-#define GPIO211_MC1_DAT0        PIN_CFG(211, ALT_A)
-
-#define GPIO212_GPIO            PIN_CFG(212, GPIO)
-#define GPIO212_MC1_DAT1        PIN_CFG(212, ALT_A)
-#define GPIO212_SPI1_FRM        PIN_CFG(212, ALT_B)
-
-#define GPIO213_GPIO            PIN_CFG(213, GPIO)
-#define GPIO213_MC1_DAT2        PIN_CFG(213, ALT_A)
-#define GPIO213_SPI1_TXD        PIN_CFG(213, ALT_B)
-
-#define GPIO214_GPIO            PIN_CFG(214, GPIO)
-#define GPIO214_MC1_DAT3        PIN_CFG(214, ALT_A)
-#define GPIO214_SPI1_RXD        PIN_CFG(214, ALT_B)
-
-#define GPIO215_GPIO            PIN_CFG(215, GPIO)
-#define GPIO215_MC1_CMDDIR      PIN_CFG(215, ALT_A)
-#define GPIO215_MC3_DAT2DIR     PIN_CFG(215, ALT_B)
-#define GPIO215_CLKOUT1         PIN_CFG(215, ALT_C)
-#define GPIO215_SPI2_TXD        PIN_CFG(215, ALT_C)
-
-#define GPIO216_GPIO            PIN_CFG(216, GPIO)
-#define GPIO216_MC1_DAT2DIR     PIN_CFG(216, ALT_A)
-#define GPIO216_MC3_CMDDIR      PIN_CFG(216, ALT_B)
-#define GPIO216_I2C3_SDA        PIN_CFG(216, ALT_C)
-#define GPIO216_SPI2_FRM        PIN_CFG(216, ALT_C)
-
-#define GPIO217_GPIO            PIN_CFG(217, GPIO)
-#define GPIO217_MC1_DAT0DIR     PIN_CFG(217, ALT_A)
-#define GPIO217_MC3_DAT31DIR    PIN_CFG(217, ALT_B)
-#define GPIO217_CLKOUT2         PIN_CFG(217, ALT_C)
-#define GPIO217_SPI2_CLK        PIN_CFG(217, ALT_C)
-
-#define GPIO218_GPIO            PIN_CFG(218, GPIO)
-#define GPIO218_MC1_DAT31DIR    PIN_CFG(218, ALT_A)
-#define GPIO218_MC3_DAT0DIR     PIN_CFG(218, ALT_B)
-#define GPIO218_I2C3_SCL        PIN_CFG(218, ALT_C)
-#define GPIO218_SPI2_RXD        PIN_CFG(218, ALT_C)
-
-#define GPIO219_GPIO            PIN_CFG(219, GPIO)
-#define GPIO219_HSIR_FLA0       PIN_CFG(219, ALT_A)
-#define GPIO219_MC3_CLK         PIN_CFG(219, ALT_B)
-
-#define GPIO220_GPIO            PIN_CFG(220, GPIO)
-#define GPIO220_HSIR_DAT0       PIN_CFG(220, ALT_A)
-#define GPIO220_MC3_FBCLK       PIN_CFG(220, ALT_B)
-#define GPIO220_SPI0_CLK        PIN_CFG(220, ALT_C)
-
-#define GPIO221_GPIO            PIN_CFG(221, GPIO)
-#define GPIO221_HSIR_RDY0       PIN_CFG(221, ALT_A)
-#define GPIO221_MC3_CMD         PIN_CFG(221, ALT_B)
-
-#define GPIO222_GPIO            PIN_CFG(222, GPIO)
-#define GPIO222_HSIT_FLA0       PIN_CFG(222, ALT_A)
-#define GPIO222_MC3_DAT0        PIN_CFG(222, ALT_B)
-
-#define GPIO223_GPIO            PIN_CFG(223, GPIO)
-#define GPIO223_HSIT_DAT0       PIN_CFG(223, ALT_A)
-#define GPIO223_MC3_DAT1        PIN_CFG(223, ALT_B)
-#define GPIO223_SPI0_FRM        PIN_CFG(223, ALT_C)
-
-#define GPIO224_GPIO            PIN_CFG(224, GPIO)
-#define GPIO224_HSIT_RDY0       PIN_CFG(224, ALT_A)
-#define GPIO224_MC3_DAT2        PIN_CFG(224, ALT_B)
-#define GPIO224_SPI0_TXD        PIN_CFG(224, ALT_C)
-
-#define GPIO225_GPIO            PIN_CFG(225, GPIO)
-#define GPIO225_HSIT_CAWAKE0    PIN_CFG(225, ALT_A)
-#define GPIO225_MC3_DAT3        PIN_CFG(225, ALT_B)
-#define GPIO225_SPI0_RXD        PIN_CFG(225, ALT_C)
-
-#define GPIO226_GPIO            PIN_CFG(226, GPIO)
-#define GPIO226_HSIT_ACWAKE0    PIN_CFG(226, ALT_A)
-#define GPIO226_PWL             PIN_CFG(226, ALT_B)
-#define GPIO226_USBSIM_PDC      PIN_CFG(226, ALT_C)
-
-#define GPIO227_GPIO            PIN_CFG(227, GPIO)
-#define GPIO227_CLKOUT1         PIN_CFG(227, ALT_A)
-
-#define GPIO228_GPIO            PIN_CFG(228, GPIO)
-#define GPIO228_CLKOUT2         PIN_CFG(228, ALT_A)
-
-#define GPIO229_GPIO            PIN_CFG(229, GPIO)
-#define GPIO229_CLKOUT1         PIN_CFG(229, ALT_A)
-#define GPIO229_PWL             PIN_CFG(229, ALT_B)
-#define GPIO229_I2C3_SDA        PIN_CFG(229, ALT_C)
-
-#define GPIO230_GPIO            PIN_CFG(230, GPIO)
-#define GPIO230_CLKOUT2         PIN_CFG(230, ALT_A)
-#define GPIO230_PWL             PIN_CFG(230, ALT_B)
-#define GPIO230_I2C3_SCL        PIN_CFG(230, ALT_C)
-
-#define GPIO256_GPIO            PIN_CFG(256, GPIO)
-#define GPIO256_USB_NXT         PIN_CFG(256, ALT_A)
-
-#define GPIO257_GPIO            PIN_CFG(257, GPIO)
-#define GPIO257_USB_STP         PIN_CFG(257, ALT_A)
-
-#define GPIO258_GPIO            PIN_CFG(258, GPIO)
-#define GPIO258_USB_XCLK        PIN_CFG(258, ALT_A)
-#define GPIO258_NONE            PIN_CFG(258, ALT_B)
-#define GPIO258_DDR_TRIG        PIN_CFG(258, ALT_C)
-
-#define GPIO259_GPIO            PIN_CFG(259, GPIO)
-#define GPIO259_USB_DIR         PIN_CFG(259, ALT_A)
-
-#define GPIO260_GPIO            PIN_CFG(260, GPIO)
-#define GPIO260_USB_DAT7        PIN_CFG(260, ALT_A)
-
-#define GPIO261_GPIO            PIN_CFG(261, GPIO)
-#define GPIO261_USB_DAT6        PIN_CFG(261, ALT_A)
-
-#define GPIO262_GPIO            PIN_CFG(262, GPIO)
-#define GPIO262_USB_DAT5        PIN_CFG(262, ALT_A)
-
-#define GPIO263_GPIO            PIN_CFG(263, GPIO)
-#define GPIO263_USB_DAT4        PIN_CFG(263, ALT_A)
-
-#define GPIO264_GPIO            PIN_CFG(264, GPIO)
-#define GPIO264_USB_DAT3        PIN_CFG(264, ALT_A)
-
-#define GPIO265_GPIO            PIN_CFG(265, GPIO)
-#define GPIO265_USB_DAT2        PIN_CFG(265, ALT_A)
-
-#define GPIO266_GPIO            PIN_CFG(266, GPIO)
-#define GPIO266_USB_DAT1        PIN_CFG(266, ALT_A)
-
-#define GPIO267_GPIO            PIN_CFG(267, GPIO)
-#define GPIO267_USB_DAT0        PIN_CFG(267, ALT_A)
-
-#endif
diff --git a/arch/arm/mm/init.c b/arch/arm/mm/init.c
index 7b0cb3b524f1..93cbf566a972 100644
--- a/arch/arm/mm/init.c
+++ b/arch/arm/mm/init.c
@@ -208,7 +208,7 @@ static void __init arm_bootmem_init(unsigned long start_pfn,
 
 #ifdef CONFIG_ZONE_DMA
 
-unsigned long arm_dma_zone_size __read_mostly;
+phys_addr_t arm_dma_zone_size __read_mostly;
 EXPORT_SYMBOL(arm_dma_zone_size);
 
 /*