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authorLinus Torvalds <torvalds@linux-foundation.org>2011-03-16 22:05:40 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2011-03-16 22:05:40 -0400
commit63a93699c6a58795b854ff573542a08367684dae (patch)
tree057ab4cbde66862c51867dde030be69a2fa7073f /arch
parent16d8775700f1815076f879719ce14b33f50a3171 (diff)
parent21bd6d37cf23e643020bf28b41844ff0040c9393 (diff)
Merge branch 'remove' of master.kernel.org:/home/rmk/linux-2.6-arm
* 'remove' of master.kernel.org:/home/rmk/linux-2.6-arm: ARM: 6629/2: aaec2000: remove support for mach-aaec2000 ARM: lh7a40x: remove unmaintained platform support Fix up trivial conflicts in - arch/arm/mach-{aaec2000,lh7a40x}/include/mach/memory.h (removed) - drivers/usb/gadget/Kconfig (USB_[GADGET_]LH7A40X removed, others added)
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/Kconfig24
-rw-r--r--arch/arm/Makefile2
-rw-r--r--arch/arm/configs/lpd7a400_defconfig68
-rw-r--r--arch/arm/configs/lpd7a404_defconfig81
-rw-r--r--arch/arm/include/asm/setup.h6
-rw-r--r--arch/arm/mach-aaec2000/Kconfig11
-rw-r--r--arch/arm/mach-aaec2000/Makefile9
-rw-r--r--arch/arm/mach-aaec2000/Makefile.boot1
-rw-r--r--arch/arm/mach-aaec2000/aaed2000.c102
-rw-r--r--arch/arm/mach-aaec2000/core.c298
-rw-r--r--arch/arm/mach-aaec2000/core.h28
-rw-r--r--arch/arm/mach-aaec2000/include/mach/aaec2000.h207
-rw-r--r--arch/arm/mach-aaec2000/include/mach/aaed2000.h40
-rw-r--r--arch/arm/mach-aaec2000/include/mach/debug-macro.S35
-rw-r--r--arch/arm/mach-aaec2000/include/mach/entry-macro.S40
-rw-r--r--arch/arm/mach-aaec2000/include/mach/hardware.h50
-rw-r--r--arch/arm/mach-aaec2000/include/mach/io.h18
-rw-r--r--arch/arm/mach-aaec2000/include/mach/irqs.h46
-rw-r--r--arch/arm/mach-aaec2000/include/mach/memory.h17
-rw-r--r--arch/arm/mach-aaec2000/include/mach/system.h24
-rw-r--r--arch/arm/mach-aaec2000/include/mach/timex.h18
-rw-r--r--arch/arm/mach-aaec2000/include/mach/uncompress.h46
-rw-r--r--arch/arm/mach-aaec2000/include/mach/vmalloc.h16
-rw-r--r--arch/arm/mach-lh7a40x/Kconfig74
-rw-r--r--arch/arm/mach-lh7a40x/Makefile17
-rw-r--r--arch/arm/mach-lh7a40x/Makefile.boot4
-rw-r--r--arch/arm/mach-lh7a40x/arch-kev7a400.c118
-rw-r--r--arch/arm/mach-lh7a40x/arch-lpd7a40x.c422
-rw-r--r--arch/arm/mach-lh7a40x/clcd.c241
-rw-r--r--arch/arm/mach-lh7a40x/clocks.c108
-rw-r--r--arch/arm/mach-lh7a40x/common.h17
-rw-r--r--arch/arm/mach-lh7a40x/include/mach/clocks.h18
-rw-r--r--arch/arm/mach-lh7a40x/include/mach/constants.h91
-rw-r--r--arch/arm/mach-lh7a40x/include/mach/debug-macro.S37
-rw-r--r--arch/arm/mach-lh7a40x/include/mach/dma.h86
-rw-r--r--arch/arm/mach-lh7a40x/include/mach/entry-macro.S149
-rw-r--r--arch/arm/mach-lh7a40x/include/mach/hardware.h62
-rw-r--r--arch/arm/mach-lh7a40x/include/mach/io.h20
-rw-r--r--arch/arm/mach-lh7a40x/include/mach/irqs.h200
-rw-r--r--arch/arm/mach-lh7a40x/include/mach/memory.h28
-rw-r--r--arch/arm/mach-lh7a40x/include/mach/registers.h224
-rw-r--r--arch/arm/mach-lh7a40x/include/mach/ssp.h70
-rw-r--r--arch/arm/mach-lh7a40x/include/mach/system.h19
-rw-r--r--arch/arm/mach-lh7a40x/include/mach/timex.h17
-rw-r--r--arch/arm/mach-lh7a40x/include/mach/uncompress.h38
-rw-r--r--arch/arm/mach-lh7a40x/include/mach/vmalloc.h10
-rw-r--r--arch/arm/mach-lh7a40x/irq-kev7a400.c93
-rw-r--r--arch/arm/mach-lh7a40x/irq-lh7a400.c91
-rw-r--r--arch/arm/mach-lh7a40x/irq-lh7a404.c175
-rw-r--r--arch/arm/mach-lh7a40x/irq-lpd7a40x.c128
-rw-r--r--arch/arm/mach-lh7a40x/lcd-panel.h345
-rw-r--r--arch/arm/mach-lh7a40x/ssp-cpld.c343
-rw-r--r--arch/arm/mach-lh7a40x/time.c71
53 files changed, 1 insertions, 4502 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 48a0628d93e8..e34bf0272da4 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -227,15 +227,6 @@ choice
227 prompt "ARM system type" 227 prompt "ARM system type"
228 default ARCH_VERSATILE 228 default ARCH_VERSATILE
229 229
230config ARCH_AAEC2000
231 bool "Agilent AAEC-2000 based"
232 select CPU_ARM920T
233 select ARM_AMBA
234 select HAVE_CLK
235 select ARCH_USES_GETTIMEOFFSET
236 help
237 This enables support for systems based on the Agilent AAEC-2000
238
239config ARCH_INTEGRATOR 230config ARCH_INTEGRATOR
240 bool "ARM Ltd. Integrator family" 231 bool "ARM Ltd. Integrator family"
241 select ARM_AMBA 232 select ARM_AMBA
@@ -811,17 +802,6 @@ config ARCH_TCC_926
811 help 802 help
812 Support for Telechips TCC ARM926-based systems. 803 Support for Telechips TCC ARM926-based systems.
813 804
814config ARCH_LH7A40X
815 bool "Sharp LH7A40X"
816 select CPU_ARM922T
817 select ARCH_SPARSEMEM_ENABLE if !LH7A40X_CONTIGMEM
818 select ARCH_USES_GETTIMEOFFSET
819 help
820 Say Y here for systems based on one of the Sharp LH7A40X
821 System on a Chip processors. These CPUs include an ARM922T
822 core with a wide array of integrated devices for
823 hand-held and low-power applications.
824
825config ARCH_U300 805config ARCH_U300
826 bool "ST-Ericsson U300 Series" 806 bool "ST-Ericsson U300 Series"
827 depends on MMU 807 depends on MMU
@@ -908,8 +888,6 @@ endchoice
908# Kconfigs may be included either alphabetically (according to the 888# Kconfigs may be included either alphabetically (according to the
909# plat- suffix) or along side the corresponding mach-* source. 889# plat- suffix) or along side the corresponding mach-* source.
910# 890#
911source "arch/arm/mach-aaec2000/Kconfig"
912
913source "arch/arm/mach-at91/Kconfig" 891source "arch/arm/mach-at91/Kconfig"
914 892
915source "arch/arm/mach-bcmring/Kconfig" 893source "arch/arm/mach-bcmring/Kconfig"
@@ -948,8 +926,6 @@ source "arch/arm/mach-kirkwood/Kconfig"
948 926
949source "arch/arm/mach-ks8695/Kconfig" 927source "arch/arm/mach-ks8695/Kconfig"
950 928
951source "arch/arm/mach-lh7a40x/Kconfig"
952
953source "arch/arm/mach-loki/Kconfig" 929source "arch/arm/mach-loki/Kconfig"
954 930
955source "arch/arm/mach-lpc32xx/Kconfig" 931source "arch/arm/mach-lpc32xx/Kconfig"
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 1e20c414d5cf..5c7114bb8a25 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -131,7 +131,6 @@ endif
131 131
132# Machine directory name. This list is sorted alphanumerically 132# Machine directory name. This list is sorted alphanumerically
133# by CONFIG_* macro name. 133# by CONFIG_* macro name.
134machine-$(CONFIG_ARCH_AAEC2000) := aaec2000
135machine-$(CONFIG_ARCH_AT91) := at91 134machine-$(CONFIG_ARCH_AT91) := at91
136machine-$(CONFIG_ARCH_BCMRING) := bcmring 135machine-$(CONFIG_ARCH_BCMRING) := bcmring
137machine-$(CONFIG_ARCH_CLPS711X) := clps711x 136machine-$(CONFIG_ARCH_CLPS711X) := clps711x
@@ -151,7 +150,6 @@ machine-$(CONFIG_ARCH_IXP23XX) := ixp23xx
151machine-$(CONFIG_ARCH_IXP4XX) := ixp4xx 150machine-$(CONFIG_ARCH_IXP4XX) := ixp4xx
152machine-$(CONFIG_ARCH_KIRKWOOD) := kirkwood 151machine-$(CONFIG_ARCH_KIRKWOOD) := kirkwood
153machine-$(CONFIG_ARCH_KS8695) := ks8695 152machine-$(CONFIG_ARCH_KS8695) := ks8695
154machine-$(CONFIG_ARCH_LH7A40X) := lh7a40x
155machine-$(CONFIG_ARCH_LOKI) := loki 153machine-$(CONFIG_ARCH_LOKI) := loki
156machine-$(CONFIG_ARCH_LPC32XX) := lpc32xx 154machine-$(CONFIG_ARCH_LPC32XX) := lpc32xx
157machine-$(CONFIG_ARCH_MMP) := mmp 155machine-$(CONFIG_ARCH_MMP) := mmp
diff --git a/arch/arm/configs/lpd7a400_defconfig b/arch/arm/configs/lpd7a400_defconfig
deleted file mode 100644
index 5a48f171204c..000000000000
--- a/arch/arm/configs/lpd7a400_defconfig
+++ /dev/null
@@ -1,68 +0,0 @@
1CONFIG_EXPERIMENTAL=y
2# CONFIG_SWAP is not set
3CONFIG_SYSVIPC=y
4CONFIG_IKCONFIG=y
5CONFIG_LOG_BUF_SHIFT=14
6CONFIG_EXPERT=y
7# CONFIG_HOTPLUG is not set
8# CONFIG_EPOLL is not set
9# CONFIG_IOSCHED_DEADLINE is not set
10CONFIG_ARCH_LH7A40X=y
11CONFIG_MACH_LPD7A400=y
12CONFIG_PREEMPT=y
13CONFIG_ZBOOT_ROM_TEXT=0x0
14CONFIG_ZBOOT_ROM_BSS=0x0
15CONFIG_FPE_NWFPE=y
16CONFIG_NET=y
17CONFIG_PACKET=y
18CONFIG_UNIX=y
19CONFIG_INET=y
20CONFIG_IP_PNP=y
21CONFIG_IP_PNP_DHCP=y
22CONFIG_IP_PNP_BOOTP=y
23CONFIG_IP_PNP_RARP=y
24# CONFIG_IPV6 is not set
25CONFIG_MTD=y
26CONFIG_MTD_PARTITIONS=y
27CONFIG_MTD_CMDLINE_PARTS=y
28CONFIG_MTD_CHAR=y
29CONFIG_MTD_BLOCK=y
30CONFIG_MTD_CFI=y
31CONFIG_MTD_CFI_INTELEXT=y
32CONFIG_MTD_PHYSMAP=y
33CONFIG_BLK_DEV_LOOP=y
34CONFIG_IDE=y
35CONFIG_SCSI=y
36# CONFIG_SCSI_PROC_FS is not set
37CONFIG_NETDEVICES=y
38CONFIG_NET_ETHERNET=y
39CONFIG_SMC91X=y
40# CONFIG_INPUT_MOUSEDEV is not set
41CONFIG_INPUT_EVDEV=y
42# CONFIG_INPUT_KEYBOARD is not set
43# CONFIG_INPUT_MOUSE is not set
44CONFIG_INPUT_TOUCHSCREEN=y
45# CONFIG_SERIO is not set
46CONFIG_SERIAL_LH7A40X=y
47CONFIG_SERIAL_LH7A40X_CONSOLE=y
48CONFIG_FB=y
49# CONFIG_VGA_CONSOLE is not set
50CONFIG_SOUND=y
51CONFIG_SND=y
52CONFIG_SND_MIXER_OSS=y
53CONFIG_SND_PCM_OSS=y
54CONFIG_EXT2_FS=y
55CONFIG_EXT3_FS=y
56CONFIG_VFAT_FS=y
57CONFIG_TMPFS=y
58CONFIG_JFFS2_FS=y
59CONFIG_CRAMFS=y
60CONFIG_NFS_FS=y
61CONFIG_NFS_V3=y
62CONFIG_ROOT_NFS=y
63CONFIG_PARTITION_ADVANCED=y
64CONFIG_MAGIC_SYSRQ=y
65CONFIG_DEBUG_KERNEL=y
66CONFIG_DEBUG_INFO=y
67CONFIG_DEBUG_USER=y
68CONFIG_DEBUG_ERRORS=y
diff --git a/arch/arm/configs/lpd7a404_defconfig b/arch/arm/configs/lpd7a404_defconfig
deleted file mode 100644
index 22d0631de009..000000000000
--- a/arch/arm/configs/lpd7a404_defconfig
+++ /dev/null
@@ -1,81 +0,0 @@
1CONFIG_EXPERIMENTAL=y
2# CONFIG_SWAP is not set
3CONFIG_SYSVIPC=y
4CONFIG_IKCONFIG=y
5CONFIG_LOG_BUF_SHIFT=16
6CONFIG_EXPERT=y
7# CONFIG_HOTPLUG is not set
8# CONFIG_EPOLL is not set
9CONFIG_SLAB=y
10# CONFIG_IOSCHED_DEADLINE is not set
11CONFIG_ARCH_LH7A40X=y
12CONFIG_MACH_LPD7A404=y
13CONFIG_PREEMPT=y
14CONFIG_DISCONTIGMEM_MANUAL=y
15CONFIG_ZBOOT_ROM_TEXT=0x0
16CONFIG_ZBOOT_ROM_BSS=0x0
17CONFIG_FPE_NWFPE=y
18CONFIG_NET=y
19CONFIG_PACKET=y
20CONFIG_UNIX=y
21CONFIG_INET=y
22CONFIG_IP_PNP=y
23CONFIG_IP_PNP_DHCP=y
24CONFIG_IP_PNP_BOOTP=y
25CONFIG_IP_PNP_RARP=y
26# CONFIG_IPV6 is not set
27CONFIG_MTD=y
28CONFIG_MTD_PARTITIONS=y
29CONFIG_MTD_CMDLINE_PARTS=y
30CONFIG_MTD_CHAR=y
31CONFIG_MTD_BLOCK=y
32CONFIG_MTD_CFI=y
33CONFIG_MTD_CFI_INTELEXT=y
34CONFIG_MTD_PHYSMAP=y
35CONFIG_BLK_DEV_LOOP=y
36CONFIG_IDE=y
37CONFIG_SCSI=y
38# CONFIG_SCSI_PROC_FS is not set
39CONFIG_NETDEVICES=y
40CONFIG_NET_ETHERNET=y
41CONFIG_SMC91X=y
42# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
43CONFIG_INPUT_EVDEV=y
44# CONFIG_INPUT_KEYBOARD is not set
45# CONFIG_INPUT_MOUSE is not set
46CONFIG_INPUT_TOUCHSCREEN=y
47# CONFIG_SERIO is not set
48CONFIG_SERIAL_LH7A40X=y
49CONFIG_SERIAL_LH7A40X_CONSOLE=y
50CONFIG_FB=y
51# CONFIG_VGA_CONSOLE is not set
52CONFIG_SOUND=y
53CONFIG_SND=y
54CONFIG_SND_MIXER_OSS=y
55CONFIG_SND_PCM_OSS=y
56CONFIG_USB=y
57CONFIG_USB_DEVICEFS=y
58CONFIG_USB_MON=y
59CONFIG_USB_OHCI_HCD=y
60CONFIG_USB_STORAGE=y
61CONFIG_USB_STORAGE_DEBUG=y
62CONFIG_USB_STORAGE_DATAFAB=y
63CONFIG_USB_GADGET=y
64CONFIG_USB_ZERO=y
65CONFIG_EXT2_FS=y
66CONFIG_EXT3_FS=y
67CONFIG_INOTIFY=y
68CONFIG_VFAT_FS=y
69CONFIG_TMPFS=y
70CONFIG_JFFS2_FS=y
71CONFIG_CRAMFS=y
72CONFIG_NFS_FS=y
73CONFIG_NFS_V3=y
74CONFIG_ROOT_NFS=y
75CONFIG_PARTITION_ADVANCED=y
76CONFIG_MAGIC_SYSRQ=y
77CONFIG_DEBUG_KERNEL=y
78CONFIG_DEBUG_MUTEXES=y
79CONFIG_DEBUG_INFO=y
80CONFIG_DEBUG_USER=y
81CONFIG_DEBUG_ERRORS=y
diff --git a/arch/arm/include/asm/setup.h b/arch/arm/include/asm/setup.h
index f1e5a9bca249..da8b52ec49cf 100644
--- a/arch/arm/include/asm/setup.h
+++ b/arch/arm/include/asm/setup.h
@@ -192,11 +192,7 @@ static struct tagtable __tagtable_##fn __tag = { tag, fn }
192/* 192/*
193 * Memory map description 193 * Memory map description
194 */ 194 */
195#ifdef CONFIG_ARCH_LH7A40X 195#define NR_BANKS 8
196# define NR_BANKS 16
197#else
198# define NR_BANKS 8
199#endif
200 196
201struct membank { 197struct membank {
202 unsigned long start; 198 unsigned long start;
diff --git a/arch/arm/mach-aaec2000/Kconfig b/arch/arm/mach-aaec2000/Kconfig
deleted file mode 100644
index 5e4bef93754c..000000000000
--- a/arch/arm/mach-aaec2000/Kconfig
+++ /dev/null
@@ -1,11 +0,0 @@
1if ARCH_AAEC2000
2
3menu "Agilent AAEC-2000 Implementations"
4
5config MACH_AAED2000
6 bool "Agilent AAED-2000 Development Platform"
7 select CPU_ARM920T
8
9endmenu
10
11endif
diff --git a/arch/arm/mach-aaec2000/Makefile b/arch/arm/mach-aaec2000/Makefile
deleted file mode 100644
index 20ec83896c37..000000000000
--- a/arch/arm/mach-aaec2000/Makefile
+++ /dev/null
@@ -1,9 +0,0 @@
1#
2# Makefile for the linux kernel.
3#
4
5# Common support (must be linked before board specific support)
6obj-y += core.o
7
8# Specific board support
9obj-$(CONFIG_MACH_AAED2000) += aaed2000.o
diff --git a/arch/arm/mach-aaec2000/Makefile.boot b/arch/arm/mach-aaec2000/Makefile.boot
deleted file mode 100644
index 8f5a8b7c53c7..000000000000
--- a/arch/arm/mach-aaec2000/Makefile.boot
+++ /dev/null
@@ -1 +0,0 @@
1 zreladdr-y := 0xf0008000
diff --git a/arch/arm/mach-aaec2000/aaed2000.c b/arch/arm/mach-aaec2000/aaed2000.c
deleted file mode 100644
index 0eb3e3e5b2d1..000000000000
--- a/arch/arm/mach-aaec2000/aaed2000.c
+++ /dev/null
@@ -1,102 +0,0 @@
1/*
2 * linux/arch/arm/mach-aaec2000/aaed2000.c
3 *
4 * Support for the Agilent AAED-2000 Development Platform.
5 *
6 * Copyright (c) 2005 Nicolas Bellido Y Ortega
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 */
13#include <linux/module.h>
14#include <linux/kernel.h>
15#include <linux/init.h>
16#include <linux/device.h>
17#include <linux/major.h>
18#include <linux/interrupt.h>
19
20#include <asm/setup.h>
21#include <asm/memory.h>
22#include <asm/mach-types.h>
23#include <mach/hardware.h>
24#include <asm/irq.h>
25
26#include <asm/mach/arch.h>
27#include <asm/mach/map.h>
28#include <asm/mach/irq.h>
29
30#include <mach/aaed2000.h>
31
32#include "core.h"
33
34static void aaed2000_clcd_disable(struct clcd_fb *fb)
35{
36 AAED_EXT_GPIO &= ~AAED_EGPIO_LCD_PWR_EN;
37}
38
39static void aaed2000_clcd_enable(struct clcd_fb *fb)
40{
41 AAED_EXT_GPIO |= AAED_EGPIO_LCD_PWR_EN;
42}
43
44struct aaec2000_clcd_info clcd_info = {
45 .enable = aaed2000_clcd_enable,
46 .disable = aaed2000_clcd_disable,
47 .panel = {
48 .mode = {
49 .name = "Sharp",
50 .refresh = 60,
51 .xres = 640,
52 .yres = 480,
53 .pixclock = 39721,
54 .left_margin = 20,
55 .right_margin = 44,
56 .upper_margin = 21,
57 .lower_margin = 34,
58 .hsync_len = 96,
59 .vsync_len = 2,
60 .sync = 0,
61 .vmode = FB_VMODE_NONINTERLACED,
62 },
63 .width = -1,
64 .height = -1,
65 .tim2 = TIM2_IVS | TIM2_IHS,
66 .cntl = CNTL_LCDTFT,
67 .bpp = 16,
68 },
69};
70
71static void __init aaed2000_init_irq(void)
72{
73 aaec2000_init_irq();
74}
75
76static void __init aaed2000_init(void)
77{
78 aaec2000_set_clcd_plat_data(&clcd_info);
79}
80
81static struct map_desc aaed2000_io_desc[] __initdata = {
82 {
83 .virtual = EXT_GPIO_VBASE,
84 .pfn = __phys_to_pfn(EXT_GPIO_PBASE),
85 .length = EXT_GPIO_LENGTH,
86 .type = MT_DEVICE
87 },
88};
89
90static void __init aaed2000_map_io(void)
91{
92 aaec2000_map_io();
93 iotable_init(aaed2000_io_desc, ARRAY_SIZE(aaed2000_io_desc));
94}
95
96MACHINE_START(AAED2000, "Agilent AAED-2000 Development Platform")
97 /* Maintainer: Nicolas Bellido Y Ortega */
98 .map_io = aaed2000_map_io,
99 .init_irq = aaed2000_init_irq,
100 .timer = &aaec2000_timer,
101 .init_machine = aaed2000_init,
102MACHINE_END
diff --git a/arch/arm/mach-aaec2000/core.c b/arch/arm/mach-aaec2000/core.c
deleted file mode 100644
index f8465bd17e67..000000000000
--- a/arch/arm/mach-aaec2000/core.c
+++ /dev/null
@@ -1,298 +0,0 @@
1/*
2 * linux/arch/arm/mach-aaec2000/core.c
3 *
4 * Code common to all AAEC-2000 machines
5 *
6 * Copyright (c) 2005 Nicolas Bellido Y Ortega
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12#include <linux/module.h>
13#include <linux/kernel.h>
14#include <linux/init.h>
15#include <linux/platform_device.h>
16#include <linux/list.h>
17#include <linux/errno.h>
18#include <linux/dma-mapping.h>
19#include <linux/interrupt.h>
20#include <linux/timex.h>
21#include <linux/signal.h>
22#include <linux/clk.h>
23#include <linux/gfp.h>
24
25#include <mach/hardware.h>
26#include <asm/irq.h>
27#include <asm/sizes.h>
28
29#include <asm/mach/flash.h>
30#include <asm/mach/irq.h>
31#include <asm/mach/time.h>
32#include <asm/mach/map.h>
33
34#include "core.h"
35
36/*
37 * Common I/O mapping:
38 *
39 * Static virtual address mappings are as follow:
40 *
41 * 0xf8000000-0xf8001ffff: Devices connected to APB bus
42 * 0xf8002000-0xf8003ffff: Devices connected to AHB bus
43 *
44 * Below 0xe8000000 is reserved for vm allocation.
45 *
46 * The machine specific code must provide the extra mapping beside the
47 * default mapping provided here.
48 */
49static struct map_desc standard_io_desc[] __initdata = {
50 {
51 .virtual = VIO_APB_BASE,
52 .pfn = __phys_to_pfn(PIO_APB_BASE),
53 .length = IO_APB_LENGTH,
54 .type = MT_DEVICE
55 }, {
56 .virtual = VIO_AHB_BASE,
57 .pfn = __phys_to_pfn(PIO_AHB_BASE),
58 .length = IO_AHB_LENGTH,
59 .type = MT_DEVICE
60 }
61};
62
63void __init aaec2000_map_io(void)
64{
65 iotable_init(standard_io_desc, ARRAY_SIZE(standard_io_desc));
66}
67
68/*
69 * Interrupt handling routines
70 */
71static void aaec2000_int_ack(struct irq_data *d)
72{
73 IRQ_INTSR = 1 << d->irq;
74}
75
76static void aaec2000_int_mask(struct irq_data *d)
77{
78 IRQ_INTENC |= (1 << d->irq);
79}
80
81static void aaec2000_int_unmask(struct irq_data *d)
82{
83 IRQ_INTENS |= (1 << d->irq);
84}
85
86static struct irq_chip aaec2000_irq_chip = {
87 .irq_ack = aaec2000_int_ack,
88 .irq_mask = aaec2000_int_mask,
89 .irq_unmask = aaec2000_int_unmask,
90};
91
92void __init aaec2000_init_irq(void)
93{
94 unsigned int i;
95
96 for (i = 0; i < NR_IRQS; i++) {
97 set_irq_handler(i, handle_level_irq);
98 set_irq_chip(i, &aaec2000_irq_chip);
99 set_irq_flags(i, IRQF_VALID);
100 }
101
102 /* Disable all interrupts */
103 IRQ_INTENC = 0xffffffff;
104
105 /* Clear any pending interrupts */
106 IRQ_INTSR = IRQ_INTSR;
107}
108
109/*
110 * Time keeping
111 */
112/* IRQs are disabled before entering here from do_gettimeofday() */
113static unsigned long aaec2000_gettimeoffset(void)
114{
115 unsigned long ticks_to_match, elapsed, usec;
116
117 /* Get ticks before next timer match */
118 ticks_to_match = TIMER1_LOAD - TIMER1_VAL;
119
120 /* We need elapsed ticks since last match */
121 elapsed = LATCH - ticks_to_match;
122
123 /* Now, convert them to usec */
124 usec = (unsigned long)(elapsed * (tick_nsec / 1000))/LATCH;
125
126 return usec;
127}
128
129/* We enter here with IRQs enabled */
130static irqreturn_t
131aaec2000_timer_interrupt(int irq, void *dev_id)
132{
133 /* TODO: Check timer accuracy */
134 timer_tick();
135 TIMER1_CLEAR = 1;
136
137 return IRQ_HANDLED;
138}
139
140static struct irqaction aaec2000_timer_irq = {
141 .name = "AAEC-2000 Timer Tick",
142 .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
143 .handler = aaec2000_timer_interrupt,
144};
145
146static void __init aaec2000_timer_init(void)
147{
148 /* Disable timer 1 */
149 TIMER1_CTRL = 0;
150
151 /* We have somehow to generate a 100Hz clock.
152 * We then use the 508KHz timer in periodic mode.
153 */
154 TIMER1_LOAD = LATCH;
155 TIMER1_CLEAR = 1; /* Clear interrupt */
156
157 setup_irq(INT_TMR1_OFL, &aaec2000_timer_irq);
158
159 TIMER1_CTRL = TIMER_CTRL_ENABLE |
160 TIMER_CTRL_PERIODIC |
161 TIMER_CTRL_CLKSEL_508K;
162}
163
164struct sys_timer aaec2000_timer = {
165 .init = aaec2000_timer_init,
166 .offset = aaec2000_gettimeoffset,
167};
168
169static struct clcd_panel mach_clcd_panel;
170
171static int aaec2000_clcd_setup(struct clcd_fb *fb)
172{
173 dma_addr_t dma;
174
175 fb->panel = &mach_clcd_panel;
176
177 fb->fb.screen_base = dma_alloc_writecombine(&fb->dev->dev, SZ_1M,
178 &dma, GFP_KERNEL);
179
180 if (!fb->fb.screen_base) {
181 printk(KERN_ERR "CLCD: unable to map framebuffer\n");
182 return -ENOMEM;
183 }
184
185 fb->fb.fix.smem_start = dma;
186 fb->fb.fix.smem_len = SZ_1M;
187
188 return 0;
189}
190
191static int aaec2000_clcd_mmap(struct clcd_fb *fb, struct vm_area_struct *vma)
192{
193 return dma_mmap_writecombine(&fb->dev->dev, vma,
194 fb->fb.screen_base,
195 fb->fb.fix.smem_start,
196 fb->fb.fix.smem_len);
197}
198
199static void aaec2000_clcd_remove(struct clcd_fb *fb)
200{
201 dma_free_writecombine(&fb->dev->dev, fb->fb.fix.smem_len,
202 fb->fb.screen_base, fb->fb.fix.smem_start);
203}
204
205static struct clcd_board clcd_plat_data = {
206 .name = "AAEC-2000",
207 .check = clcdfb_check,
208 .decode = clcdfb_decode,
209 .setup = aaec2000_clcd_setup,
210 .mmap = aaec2000_clcd_mmap,
211 .remove = aaec2000_clcd_remove,
212};
213
214static struct amba_device clcd_device = {
215 .dev = {
216 .init_name = "mb:16",
217 .coherent_dma_mask = ~0,
218 .platform_data = &clcd_plat_data,
219 },
220 .res = {
221 .start = AAEC_CLCD_PHYS,
222 .end = AAEC_CLCD_PHYS + SZ_4K - 1,
223 .flags = IORESOURCE_MEM,
224 },
225 .irq = { INT_LCD, NO_IRQ },
226 .periphid = 0x41110,
227};
228
229static struct amba_device *amba_devs[] __initdata = {
230 &clcd_device,
231};
232
233void clk_disable(struct clk *clk)
234{
235}
236
237int clk_set_rate(struct clk *clk, unsigned long rate)
238{
239 return 0;
240}
241
242int clk_enable(struct clk *clk)
243{
244 return 0;
245}
246
247struct clk *clk_get(struct device *dev, const char *id)
248{
249 return dev && strcmp(dev_name(dev), "mb:16") == 0 ? NULL : ERR_PTR(-ENOENT);
250}
251
252void clk_put(struct clk *clk)
253{
254}
255
256void __init aaec2000_set_clcd_plat_data(struct aaec2000_clcd_info *clcd)
257{
258 clcd_plat_data.enable = clcd->enable;
259 clcd_plat_data.disable = clcd->disable;
260 memcpy(&mach_clcd_panel, &clcd->panel, sizeof(struct clcd_panel));
261}
262
263static struct flash_platform_data aaec2000_flash_data = {
264 .map_name = "cfi_probe",
265 .width = 4,
266};
267
268static struct resource aaec2000_flash_resource = {
269 .start = AAEC_FLASH_BASE,
270 .end = AAEC_FLASH_BASE + AAEC_FLASH_SIZE,
271 .flags = IORESOURCE_MEM,
272};
273
274static struct platform_device aaec2000_flash_device = {
275 .name = "armflash",
276 .id = 0,
277 .dev = {
278 .platform_data = &aaec2000_flash_data,
279 },
280 .num_resources = 1,
281 .resource = &aaec2000_flash_resource,
282};
283
284static int __init aaec2000_init(void)
285{
286 int i;
287
288 for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
289 struct amba_device *d = amba_devs[i];
290 amba_device_register(d, &iomem_resource);
291 }
292
293 platform_device_register(&aaec2000_flash_device);
294
295 return 0;
296};
297arch_initcall(aaec2000_init);
298
diff --git a/arch/arm/mach-aaec2000/core.h b/arch/arm/mach-aaec2000/core.h
deleted file mode 100644
index 59501b573167..000000000000
--- a/arch/arm/mach-aaec2000/core.h
+++ /dev/null
@@ -1,28 +0,0 @@
1/*
2 * linux/arch/arm/mach-aaec2000/core.h
3 *
4 * Copyright (c) 2005 Nicolas Bellido Y Ortega
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 */
11
12#include <linux/amba/bus.h>
13#include <linux/amba/clcd.h>
14
15struct sys_timer;
16
17extern struct sys_timer aaec2000_timer;
18extern void __init aaec2000_map_io(void);
19extern void __init aaec2000_init_irq(void);
20
21struct aaec2000_clcd_info {
22 struct clcd_panel panel;
23 void (*disable)(struct clcd_fb *);
24 void (*enable)(struct clcd_fb *);
25};
26
27extern void __init aaec2000_set_clcd_plat_data(struct aaec2000_clcd_info *);
28
diff --git a/arch/arm/mach-aaec2000/include/mach/aaec2000.h b/arch/arm/mach-aaec2000/include/mach/aaec2000.h
deleted file mode 100644
index bc729c42f843..000000000000
--- a/arch/arm/mach-aaec2000/include/mach/aaec2000.h
+++ /dev/null
@@ -1,207 +0,0 @@
1/*
2 * arch/arm/mach-aaec2000/include/mach/aaec2000.h
3 *
4 * AAEC-2000 registers definition
5 *
6 * Copyright (c) 2005 Nicolas Bellido Y Ortega
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#ifndef __ASM_ARCH_AAEC2000_H
14#define __ASM_ARCH_AAEC2000_H
15
16#ifndef __ASM_ARCH_HARDWARE_H
17#error You must include hardware.h not this file
18#endif /* __ASM_ARCH_HARDWARE_H */
19
20/* Chip selects */
21#define AAEC_CS0 0x00000000
22#define AAEC_CS1 0x10000000
23#define AAEC_CS2 0x20000000
24#define AAEC_CS3 0x30000000
25
26/* Flash */
27#define AAEC_FLASH_BASE AAEC_CS0
28#define AAEC_FLASH_SIZE SZ_64M
29
30/* Interrupt controller */
31#define IRQ_BASE __REG(0x80000500)
32#define IRQ_INTSR __REG(0x80000500) /* Int Status Register */
33#define IRQ_INTRSR __REG(0x80000504) /* Int Raw (unmasked) Status */
34#define IRQ_INTENS __REG(0x80000508) /* Int Enable Set */
35#define IRQ_INTENC __REG(0x8000050c) /* Int Enable Clear */
36
37/* UART 1 */
38#define UART1_BASE __REG(0x80000600)
39#define UART1_DR __REG(0x80000600) /* Data/FIFO Register */
40#define UART1_LCR __REG(0x80000604) /* Link Control Register */
41#define UART1_BRCR __REG(0x80000608) /* Baud Rate Control Register */
42#define UART1_CR __REG(0x8000060c) /* Control Register */
43#define UART1_SR __REG(0x80000610) /* Status Register */
44#define UART1_INT __REG(0x80000614) /* Interrupt Status Register */
45#define UART1_INTM __REG(0x80000618) /* Interrupt Mask Register */
46#define UART1_INTRES __REG(0x8000061c) /* Int Result (masked status) Register */
47
48/* UART 2 */
49#define UART2_BASE __REG(0x80000700)
50#define UART2_DR __REG(0x80000700) /* Data/FIFO Register */
51#define UART2_LCR __REG(0x80000704) /* Link Control Register */
52#define UART2_BRCR __REG(0x80000708) /* Baud Rate Control Register */
53#define UART2_CR __REG(0x8000070c) /* Control Register */
54#define UART2_SR __REG(0x80000710) /* Status Register */
55#define UART2_INT __REG(0x80000714) /* Interrupt Status Register */
56#define UART2_INTM __REG(0x80000718) /* Interrupt Mask Register */
57#define UART2_INTRES __REG(0x8000071c) /* Int Result (masked status) Register */
58
59/* UART 3 */
60#define UART3_BASE __REG(0x80000800)
61#define UART3_DR __REG(0x80000800) /* Data/FIFO Register */
62#define UART3_LCR __REG(0x80000804) /* Link Control Register */
63#define UART3_BRCR __REG(0x80000808) /* Baud Rate Control Register */
64#define UART3_CR __REG(0x8000080c) /* Control Register */
65#define UART3_SR __REG(0x80000810) /* Status Register */
66#define UART3_INT __REG(0x80000814) /* Interrupt Status Register */
67#define UART3_INTM __REG(0x80000818) /* Interrupt Mask Register */
68#define UART3_INTRES __REG(0x8000081c) /* Int Result (masked status) Register */
69
70/* These are used in some places */
71#define _UART1_BASE __PREG(UART1_BASE)
72#define _UART2_BASE __PREG(UART2_BASE)
73#define _UART3_BASE __PREG(UART3_BASE)
74
75/* UART Registers Offsets */
76#define UART_DR 0x00
77#define UART_LCR 0x04
78#define UART_BRCR 0x08
79#define UART_CR 0x0c
80#define UART_SR 0x10
81#define UART_INT 0x14
82#define UART_INTM 0x18
83#define UART_INTRES 0x1c
84
85/* UART_LCR Bitmask */
86#define UART_LCR_BRK (1 << 0) /* Send Break */
87#define UART_LCR_PEN (1 << 1) /* Parity Enable */
88#define UART_LCR_EP (1 << 2) /* Even/Odd Parity */
89#define UART_LCR_S2 (1 << 3) /* One/Two Stop bits */
90#define UART_LCR_FIFO (1 << 4) /* FIFO Enable */
91#define UART_LCR_WL5 (0 << 5) /* Word Length - 5 bits */
92#define UART_LCR_WL6 (1 << 5) /* Word Length - 6 bits */
93#define UART_LCR_WL7 (1 << 6) /* Word Length - 7 bits */
94#define UART_LCR_WL8 (1 << 7) /* Word Length - 8 bits */
95
96/* UART_CR Bitmask */
97#define UART_CR_EN (1 << 0) /* UART Enable */
98#define UART_CR_SIR (1 << 1) /* IrDA SIR Enable */
99#define UART_CR_SIRLP (1 << 2) /* Low Power IrDA Enable */
100#define UART_CR_RXP (1 << 3) /* Receive Pin Polarity */
101#define UART_CR_TXP (1 << 4) /* Transmit Pin Polarity */
102#define UART_CR_MXP (1 << 5) /* Modem Pin Polarity */
103#define UART_CR_LOOP (1 << 6) /* Loopback Mode */
104
105/* UART_SR Bitmask */
106#define UART_SR_CTS (1 << 0) /* Clear To Send Status */
107#define UART_SR_DSR (1 << 1) /* Data Set Ready Status */
108#define UART_SR_DCD (1 << 2) /* Data Carrier Detect Status */
109#define UART_SR_TxBSY (1 << 3) /* Transmitter Busy Status */
110#define UART_SR_RxFE (1 << 4) /* Receive FIFO Empty Status */
111#define UART_SR_TxFF (1 << 5) /* Transmit FIFO Full Status */
112#define UART_SR_RxFF (1 << 6) /* Receive FIFO Full Status */
113#define UART_SR_TxFE (1 << 7) /* Transmit FIFO Empty Status */
114
115/* UART_INT Bitmask */
116#define UART_INT_RIS (1 << 0) /* Rx Interrupt */
117#define UART_INT_TIS (1 << 1) /* Tx Interrupt */
118#define UART_INT_MIS (1 << 2) /* Modem Interrupt */
119#define UART_INT_RTIS (1 << 3) /* Receive Timeout Interrupt */
120
121/* Timer 1 */
122#define TIMER1_BASE __REG(0x80000c00)
123#define TIMER1_LOAD __REG(0x80000c00) /* Timer 1 Load Register */
124#define TIMER1_VAL __REG(0x80000c04) /* Timer 1 Value Register */
125#define TIMER1_CTRL __REG(0x80000c08) /* Timer 1 Control Register */
126#define TIMER1_CLEAR __REG(0x80000c0c) /* Timer 1 Clear Register */
127
128/* Timer 2 */
129#define TIMER2_BASE __REG(0x80000d00)
130#define TIMER2_LOAD __REG(0x80000d00) /* Timer 2 Load Register */
131#define TIMER2_VAL __REG(0x80000d04) /* Timer 2 Value Register */
132#define TIMER2_CTRL __REG(0x80000d08) /* Timer 2 Control Register */
133#define TIMER2_CLEAR __REG(0x80000d0c) /* Timer 2 Clear Register */
134
135/* Timer 3 */
136#define TIMER3_BASE __REG(0x80000e00)
137#define TIMER3_LOAD __REG(0x80000e00) /* Timer 3 Load Register */
138#define TIMER3_VAL __REG(0x80000e04) /* Timer 3 Value Register */
139#define TIMER3_CTRL __REG(0x80000e08) /* Timer 3 Control Register */
140#define TIMER3_CLEAR __REG(0x80000e0c) /* Timer 3 Clear Register */
141
142/* Timer Control register bits */
143#define TIMER_CTRL_ENABLE (1 << 7) /* Enable (Start Timer) */
144#define TIMER_CTRL_PERIODIC (1 << 6) /* Periodic Running Mode */
145#define TIMER_CTRL_FREE_RUNNING (0 << 6) /* Normal Running Mode */
146#define TIMER_CTRL_CLKSEL_508K (1 << 3) /* 508KHz Clock select (Timer 1, 2) */
147#define TIMER_CTRL_CLKSEL_2K (0 << 3) /* 2KHz Clock Select (Timer 1, 2) */
148
149/* Power and State Control */
150#define POWER_BASE __REG(0x80000400)
151#define POWER_PWRSR __REG(0x80000400) /* Power Status Register */
152#define POWER_PWRCNT __REG(0x80000404) /* Power/Clock control */
153#define POWER_HALT __REG(0x80000408) /* Power Idle Mode */
154#define POWER_STDBY __REG(0x8000040c) /* Power Standby Mode */
155#define POWER_BLEOI __REG(0x80000410) /* Battery Low End of Interrupt */
156#define POWER_MCEOI __REG(0x80000414) /* Media Changed EoI */
157#define POWER_TEOI __REG(0x80000418) /* Tick EoI */
158#define POWER_STFCLR __REG(0x8000041c) /* NbFlg, RSTFlg, PFFlg, CLDFlg Clear */
159#define POWER_CLKSET __REG(0x80000420) /* Clock Speed Control */
160
161/* GPIO Registers */
162#define AAEC_GPIO_PHYS 0x80000e00
163
164#define AAEC_GPIO_PADR __REG(AAEC_GPIO_PHYS + 0x00)
165#define AAEC_GPIO_PBDR __REG(AAEC_GPIO_PHYS + 0x04)
166#define AAEC_GPIO_PCDR __REG(AAEC_GPIO_PHYS + 0x08)
167#define AAEC_GPIO_PDDR __REG(AAEC_GPIO_PHYS + 0x0c)
168#define AAEC_GPIO_PADDR __REG(AAEC_GPIO_PHYS + 0x10)
169#define AAEC_GPIO_PBDDR __REG(AAEC_GPIO_PHYS + 0x14)
170#define AAEC_GPIO_PCDDR __REG(AAEC_GPIO_PHYS + 0x18)
171#define AAEC_GPIO_PDDDR __REG(AAEC_GPIO_PHYS + 0x1c)
172#define AAEC_GPIO_PEDR __REG(AAEC_GPIO_PHYS + 0x20)
173#define AAEC_GPIO_PEDDR __REG(AAEC_GPIO_PHYS + 0x24)
174#define AAEC_GPIO_KSCAN __REG(AAEC_GPIO_PHYS + 0x28)
175#define AAEC_GPIO_PINMUX __REG(AAEC_GPIO_PHYS + 0x2c)
176#define AAEC_GPIO_PFDR __REG(AAEC_GPIO_PHYS + 0x30)
177#define AAEC_GPIO_PFDDR __REG(AAEC_GPIO_PHYS + 0x34)
178#define AAEC_GPIO_PGDR __REG(AAEC_GPIO_PHYS + 0x38)
179#define AAEC_GPIO_PGDDR __REG(AAEC_GPIO_PHYS + 0x3c)
180#define AAEC_GPIO_PHDR __REG(AAEC_GPIO_PHYS + 0x40)
181#define AAEC_GPIO_PHDDR __REG(AAEC_GPIO_PHYS + 0x44)
182#define AAEC_GPIO_RAZ __REG(AAEC_GPIO_PHYS + 0x48)
183#define AAEC_GPIO_INTTYPE1 __REG(AAEC_GPIO_PHYS + 0x4c)
184#define AAEC_GPIO_INTTYPE2 __REG(AAEC_GPIO_PHYS + 0x50)
185#define AAEC_GPIO_FEOI __REG(AAEC_GPIO_PHYS + 0x54)
186#define AAEC_GPIO_INTEN __REG(AAEC_GPIO_PHYS + 0x58)
187#define AAEC_GPIO_INTSTATUS __REG(AAEC_GPIO_PHYS + 0x5c)
188#define AAEC_GPIO_RAWINTSTATUS __REG(AAEC_GPIO_PHYS + 0x60)
189#define AAEC_GPIO_DB __REG(AAEC_GPIO_PHYS + 0x64)
190#define AAEC_GPIO_PAPINDR __REG(AAEC_GPIO_PHYS + 0x68)
191#define AAEC_GPIO_PBPINDR __REG(AAEC_GPIO_PHYS + 0x6c)
192#define AAEC_GPIO_PCPINDR __REG(AAEC_GPIO_PHYS + 0x70)
193#define AAEC_GPIO_PDPINDR __REG(AAEC_GPIO_PHYS + 0x74)
194#define AAEC_GPIO_PEPINDR __REG(AAEC_GPIO_PHYS + 0x78)
195#define AAEC_GPIO_PFPINDR __REG(AAEC_GPIO_PHYS + 0x7c)
196#define AAEC_GPIO_PGPINDR __REG(AAEC_GPIO_PHYS + 0x80)
197#define AAEC_GPIO_PHPINDR __REG(AAEC_GPIO_PHYS + 0x84)
198
199#define AAEC_GPIO_PINMUX_PE0CON (1 << 0)
200#define AAEC_GPIO_PINMUX_PD0CON (1 << 1)
201#define AAEC_GPIO_PINMUX_CODECON (1 << 2)
202#define AAEC_GPIO_PINMUX_UART3CON (1 << 3)
203
204/* LCD Controller */
205#define AAEC_CLCD_PHYS 0x80003000
206
207#endif /* __ARM_ARCH_AAEC2000_H */
diff --git a/arch/arm/mach-aaec2000/include/mach/aaed2000.h b/arch/arm/mach-aaec2000/include/mach/aaed2000.h
deleted file mode 100644
index f821295ca71b..000000000000
--- a/arch/arm/mach-aaec2000/include/mach/aaed2000.h
+++ /dev/null
@@ -1,40 +0,0 @@
1/*
2 * arch/arm/mach-aaec2000/include/mach/aaed2000.h
3 *
4 * AAED-2000 specific bits definition
5 *
6 * Copyright (c) 2005 Nicolas Bellido Y Ortega
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#ifndef __ASM_ARCH_AAED2000_H
14#define __ASM_ARCH_AAED2000_H
15
16/* External GPIOs. */
17
18#define EXT_GPIO_PBASE AAEC_CS3
19#define EXT_GPIO_VBASE 0xf8100000
20#define EXT_GPIO_LENGTH 0x00001000
21
22#define __ext_gpio_p2v(x) ((x) - EXT_GPIO_PBASE + EXT_GPIO_VBASE)
23#define __ext_gpio_v2p(x) ((x) + EXT_GPIO_PBASE - EXT_GPIO_VBASE)
24
25#define __EXT_GPIO_REG(x) (*((volatile u32 *)__ext_gpio_p2v(x)))
26#define __EXT_GPIO_PREG(x) (__ext_gpio_v2p((u32)&(x)))
27
28#define AAED_EXT_GPIO __EXT_GPIO_REG(EXT_GPIO_PBASE)
29
30#define AAED_EGPIO_KBD_SCAN 0x00003fff /* Keyboard scan data */
31#define AAED_EGPIO_PWR_INT 0x00008fff /* Smart battery charger interrupt */
32#define AAED_EGPIO_SWITCHED 0x000f0000 /* DIP Switches */
33#define AAED_EGPIO_USB_VBUS 0x00400000 /* USB Vbus sense */
34#define AAED_EGPIO_LCD_PWR_EN 0x02000000 /* LCD and backlight PWR enable */
35#define AAED_EGPIO_nLED0 0x20000000 /* LED 0 */
36#define AAED_EGPIO_nLED1 0x20000000 /* LED 1 */
37#define AAED_EGPIO_nLED2 0x20000000 /* LED 2 */
38
39
40#endif /* __ARM_ARCH_AAED2000_H */
diff --git a/arch/arm/mach-aaec2000/include/mach/debug-macro.S b/arch/arm/mach-aaec2000/include/mach/debug-macro.S
deleted file mode 100644
index bc7ad5561c4c..000000000000
--- a/arch/arm/mach-aaec2000/include/mach/debug-macro.S
+++ /dev/null
@@ -1,35 +0,0 @@
1/* arch/arm/mach-aaec2000/include/mach/debug-macro.S
2 *
3 * Debugging macro include header
4 *
5 * Copyright (c) 2005 Nicolas Bellido Y Ortega
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#include "hardware.h"
13 .macro addruart, rp, rv
14 mov \rp, 0x00000800
15 orr \rv, \rp, #io_p2v(0x80000000) @ virtual
16 orr \rp, \rp, #0x80000000 @ physical
17 .endm
18
19 .macro senduart,rd,rx
20 str \rd, [\rx, #0]
21 .endm
22
23 .macro busyuart,rd,rx
241002: ldr \rd, [\rx, #0x10]
25 tst \rd, #(1 << 7)
26 beq 1002b
27 .endm
28
29 .macro waituart,rd,rx
30#if 0
311001: ldr \rd, [\rx, #0x10]
32 tst \rd, #(1 << 5)
33 beq 1001b
34#endif
35 .endm
diff --git a/arch/arm/mach-aaec2000/include/mach/entry-macro.S b/arch/arm/mach-aaec2000/include/mach/entry-macro.S
deleted file mode 100644
index c8fb34469007..000000000000
--- a/arch/arm/mach-aaec2000/include/mach/entry-macro.S
+++ /dev/null
@@ -1,40 +0,0 @@
1/*
2 * arch/arm/mach-aaec2000/include/mach/entry-macro.S
3 *
4 * Low-level IRQ helper for aaec-2000 based platforms
5 *
6 * Copyright (c) 2005 Nicolas Bellido Y Ortega
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 */
13#include <mach/irqs.h>
14
15 .macro disable_fiq
16 .endm
17
18 .macro get_irqnr_preamble, base, tmp
19 .endm
20
21 .macro arch_ret_to_user, tmp1, tmp2
22 .endm
23
24 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
25 mov r4, #0xf8000000
26 add r4, r4, #0x00000500
27 mov \base, r4
28 ldr \irqstat, [\base, #0]
29 cmp \irqstat, #0
30 bne 1001f
31 ldr \irqnr, =NR_IRQS+1
32 b 1003f
331001: mov \irqnr, #0
341002: ands \tmp, \irqstat, #1
35 mov \irqstat, \irqstat, LSR #1
36 add \irqnr, \irqnr, #1
37 beq 1002b
38 sub \irqnr, \irqnr, #1
391003:
40 .endm
diff --git a/arch/arm/mach-aaec2000/include/mach/hardware.h b/arch/arm/mach-aaec2000/include/mach/hardware.h
deleted file mode 100644
index 965a6f6672d6..000000000000
--- a/arch/arm/mach-aaec2000/include/mach/hardware.h
+++ /dev/null
@@ -1,50 +0,0 @@
1/*
2 * arch/arm/mach-aaec2000/include/mach/hardware.h
3 *
4 * Copyright (c) 2005 Nicolas Bellido Y Ortega
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#ifndef __ASM_ARCH_HARDWARE_H
12#define __ASM_ARCH_HARDWARE_H
13
14#include <asm/sizes.h>
15#include <mach/aaec2000.h>
16
17/* The kernel is loaded at physical address 0xf8000000.
18 * We map the IO space a bit after
19 */
20#define PIO_APB_BASE 0x80000000
21#define VIO_APB_BASE 0xf8000000
22#define IO_APB_LENGTH 0x2000
23#define PIO_AHB_BASE 0x80002000
24#define VIO_AHB_BASE 0xf8002000
25#define IO_AHB_LENGTH 0x2000
26
27#define VIO_BASE VIO_APB_BASE
28#define PIO_BASE PIO_APB_BASE
29
30#define io_p2v(x) ( (x) - PIO_BASE + VIO_BASE )
31#define io_v2p(x) ( (x) + PIO_BASE - VIO_BASE )
32
33#ifndef __ASSEMBLY__
34
35#include <asm/types.h>
36
37/* FIXME: Is it needed to optimize this a la pxa ?? */
38#define __REG(x) (*((volatile u32 *)io_p2v(x)))
39#define __PREG(x) (io_v2p((u32)&(x)))
40
41#else /* __ASSEMBLY__ */
42
43#define __REG(x) io_p2v(x)
44#define __PREG(x) io_v2p(x)
45
46#endif
47
48#include "aaec2000.h"
49
50#endif /* __ASM_ARCH_HARDWARE_H */
diff --git a/arch/arm/mach-aaec2000/include/mach/io.h b/arch/arm/mach-aaec2000/include/mach/io.h
deleted file mode 100644
index ab4fe5d20eaf..000000000000
--- a/arch/arm/mach-aaec2000/include/mach/io.h
+++ /dev/null
@@ -1,18 +0,0 @@
1/*
2 * arch/arm/mach-aaec2000/include/mach/io.h
3 *
4 * Copied from asm/arch/sa1100/io.h
5 */
6#ifndef __ASM_ARM_ARCH_IO_H
7#define __ASM_ARM_ARCH_IO_H
8
9#define IO_SPACE_LIMIT 0xffffffff
10
11/*
12 * We don't actually have real ISA nor PCI buses, but there is so many
13 * drivers out there that might just work if we fake them...
14 */
15#define __io(a) __typesafe_io(a)
16#define __mem_pci(a) (a)
17
18#endif
diff --git a/arch/arm/mach-aaec2000/include/mach/irqs.h b/arch/arm/mach-aaec2000/include/mach/irqs.h
deleted file mode 100644
index bf45c6d2f294..000000000000
--- a/arch/arm/mach-aaec2000/include/mach/irqs.h
+++ /dev/null
@@ -1,46 +0,0 @@
1/*
2 * arch/arm/mach-aaec2000/include/mach/irqs.h
3 *
4 * Copyright (c) 2005 Nicolas Bellido Y Ortega
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#ifndef __ASM_ARCH_IRQS_H
12#define __ASM_ARCH_IRQS_H
13
14
15#define INT_GPIOF0_FIQ 0 /* External GPIO Port F O Fast Interrupt Input */
16#define INT_BL_FIQ 1 /* Battery Low Fast Interrupt */
17#define INT_WE_FIQ 2 /* Watchdog Expired Fast Interrupt */
18#define INT_MV_FIQ 3 /* Media Changed Interrupt */
19#define INT_SC 4 /* Sound Codec Interrupt */
20#define INT_GPIO1 5 /* GPIO Port F Configurable Int 1 */
21#define INT_GPIO2 6 /* GPIO Port F Configurable Int 2 */
22#define INT_GPIO3 7 /* GPIO Port F Configurable Int 3 */
23#define INT_TMR1_OFL 8 /* Timer 1 Overflow Interrupt */
24#define INT_TMR2_OFL 9 /* Timer 2 Overflow Interrupt */
25#define INT_RTC_CM 10 /* RTC Compare Match Interrupt */
26#define INT_TICK 11 /* 64Hz Tick Interrupt */
27#define INT_UART1 12 /* UART1 Interrupt */
28#define INT_UART2 13 /* UART2 & Modem State Changed Interrupt */
29#define INT_LCD 14 /* LCD Interrupt */
30#define INT_SSI 15 /* SSI End of Transfer Interrupt */
31#define INT_UART3 16 /* UART3 Interrupt */
32#define INT_SCI 17 /* SCI Interrupt */
33#define INT_AAC 18 /* Advanced Audio Codec Interrupt */
34#define INT_MMC 19 /* MMC Interrupt */
35#define INT_USB 20 /* USB Interrupt */
36#define INT_DMA 21 /* DMA Interrupt */
37#define INT_TMR3_UOFL 22 /* Timer 3 Underflow Interrupt */
38#define INT_GPIO4 23 /* GPIO Port F Configurable Int 4 */
39#define INT_GPIO5 24 /* GPIO Port F Configurable Int 4 */
40#define INT_GPIO6 25 /* GPIO Port F Configurable Int 4 */
41#define INT_GPIO7 26 /* GPIO Port F Configurable Int 4 */
42#define INT_BMI 27 /* BMI Interrupt */
43
44#define NR_IRQS (INT_BMI + 1)
45
46#endif /* __ASM_ARCH_IRQS_H */
diff --git a/arch/arm/mach-aaec2000/include/mach/memory.h b/arch/arm/mach-aaec2000/include/mach/memory.h
deleted file mode 100644
index 4a10bf0bd369..000000000000
--- a/arch/arm/mach-aaec2000/include/mach/memory.h
+++ /dev/null
@@ -1,17 +0,0 @@
1/*
2 * arch/arm/mach-aaec2000/include/mach/memory.h
3 *
4 * Copyright (c) 2005 Nicolas Bellido Y Ortega
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#ifndef __ASM_ARCH_MEMORY_H
12#define __ASM_ARCH_MEMORY_H
13
14
15#define PLAT_PHYS_OFFSET UL(0xf0000000)
16
17#endif /* __ASM_ARCH_MEMORY_H */
diff --git a/arch/arm/mach-aaec2000/include/mach/system.h b/arch/arm/mach-aaec2000/include/mach/system.h
deleted file mode 100644
index fe08ca1add6f..000000000000
--- a/arch/arm/mach-aaec2000/include/mach/system.h
+++ /dev/null
@@ -1,24 +0,0 @@
1/*
2 * arch/arm/mach-aaed2000/include/mach/system.h
3 *
4 * Copyright (c) 2005 Nicolas Bellido Y Ortega
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#ifndef __ASM_ARCH_SYSTEM_H
12#define __ASM_ARCH_SYSTEM_H
13
14static inline void arch_idle(void)
15{
16 cpu_do_idle();
17}
18
19static inline void arch_reset(char mode, const char *cmd)
20{
21 cpu_reset(0);
22}
23
24#endif /* __ASM_ARCH_SYSTEM_H */
diff --git a/arch/arm/mach-aaec2000/include/mach/timex.h b/arch/arm/mach-aaec2000/include/mach/timex.h
deleted file mode 100644
index 6c8edf4a8828..000000000000
--- a/arch/arm/mach-aaec2000/include/mach/timex.h
+++ /dev/null
@@ -1,18 +0,0 @@
1/*
2 * arch/arm/mach-aaec2000/include/mach/timex.h
3 *
4 * AAEC-2000 Architecture timex specification
5 *
6 * Copyright (c) 2005 Nicolas Bellido Y Ortega
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#ifndef __ASM_ARCH_TIMEX_H
14#define __ASM_ARCH_TIMEX_H
15
16#define CLOCK_TICK_RATE 508000
17
18#endif /* __ASM_ARCH_TIMEX_H */
diff --git a/arch/arm/mach-aaec2000/include/mach/uncompress.h b/arch/arm/mach-aaec2000/include/mach/uncompress.h
deleted file mode 100644
index 381ecad1a1bb..000000000000
--- a/arch/arm/mach-aaec2000/include/mach/uncompress.h
+++ /dev/null
@@ -1,46 +0,0 @@
1/*
2 * arch/arm/mach-aaec2000/include/mach/uncompress.h
3 *
4 * Copyright (c) 2005 Nicolas Bellido Y Ortega
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#ifndef __ASM_ARCH_UNCOMPRESS_H
12#define __ASM_ARCH_UNCOMPRESS_H
13
14#include "hardware.h"
15
16#define UART(x) (*(volatile unsigned long *)(serial_port + (x)))
17
18static void putc(int c)
19{
20 unsigned long serial_port;
21 do {
22 serial_port = _UART3_BASE;
23 if (UART(UART_CR) & UART_CR_EN) break;
24 serial_port = _UART1_BASE;
25 if (UART(UART_CR) & UART_CR_EN) break;
26 serial_port = _UART2_BASE;
27 if (UART(UART_CR) & UART_CR_EN) break;
28 return;
29 } while (0);
30
31 /* wait for space in the UART's transmitter */
32 while ((UART(UART_SR) & UART_SR_TxFF))
33 barrier();
34
35 /* send the character out. */
36 UART(UART_DR) = c;
37}
38
39static inline void flush(void)
40{
41}
42
43#define arch_decomp_setup()
44#define arch_decomp_wdog()
45
46#endif /* __ASM_ARCH_UNCOMPRESS_H */
diff --git a/arch/arm/mach-aaec2000/include/mach/vmalloc.h b/arch/arm/mach-aaec2000/include/mach/vmalloc.h
deleted file mode 100644
index a6299e8321bd..000000000000
--- a/arch/arm/mach-aaec2000/include/mach/vmalloc.h
+++ /dev/null
@@ -1,16 +0,0 @@
1/*
2 * arch/arm/mach-aaec2000/include/mach/vmalloc.h
3 *
4 * Copyright (c) 2005 Nicolas Bellido Y Ortega
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#ifndef __ASM_ARCH_VMALLOC_H
12#define __ASM_ARCH_VMALLOC_H
13
14#define VMALLOC_END 0xd0000000UL
15
16#endif /* __ASM_ARCH_VMALLOC_H */
diff --git a/arch/arm/mach-lh7a40x/Kconfig b/arch/arm/mach-lh7a40x/Kconfig
deleted file mode 100644
index 9be7466e346c..000000000000
--- a/arch/arm/mach-lh7a40x/Kconfig
+++ /dev/null
@@ -1,74 +0,0 @@
1if ARCH_LH7A40X
2
3menu "LH7A40X Implementations"
4
5config MACH_KEV7A400
6 bool "KEV7A400"
7 select ARCH_LH7A400
8 help
9 Say Y here if you are using the Sharp KEV7A400 development
10 board. This hardware is discontinued, so I'd be very
11 surprised if you wanted this option.
12
13config MACH_LPD7A400
14 bool "LPD7A400 Card Engine"
15 select ARCH_LH7A400
16# select IDE_POLL
17# select HAS_TOUCHSCREEN_ADS7843_LH7
18 help
19 Say Y here if you are using Logic Product Development's
20 LPD7A400 CardEngine. For the time being, the LPD7A400 and
21 LPD7A404 options are mutually exclusive.
22
23config MACH_LPD7A404
24 bool "LPD7A404 Card Engine"
25 select ARCH_LH7A404
26# select IDE_POLL
27# select HAS_TOUCHSCREEN_ADC_LH7
28 help
29 Say Y here if you are using Logic Product Development's
30 LPD7A404 CardEngine. For the time being, the LPD7A400 and
31 LPD7A404 options are mutually exclusive.
32
33config ARCH_LH7A400
34 bool
35
36config ARCH_LH7A404
37 bool
38
39config LPD7A40X_CPLD_SSP
40 bool
41
42config LH7A40X_CONTIGMEM
43 bool "Disable NUMA/SparseMEM Support"
44 help
45 Say Y here if your bootloader sets the SROMLL bit(s) in
46 the SDRAM controller, organizing memory as a contiguous
47 array. This option will disable sparse memory support
48 and force the kernel to manage all memory in one node.
49
50 Setting this option incorrectly may prevent the kernel
51 from booting. It is OK to leave it N.
52
53 For more information, consult
54 <file:Documentation/arm/Sharp-LH/SDRAM>.
55
56config LH7A40X_ONE_BANK_PER_NODE
57 bool "Optimize NUMA Node Tables for Size"
58 depends on !LH7A40X_CONTIGMEM
59 help
60 Say Y here to produce compact memory node tables. By
61 default pairs of adjacent physical RAM banks are managed
62 together in a single node, incurring some wasted overhead
63 in the node tables, however also maintaining compatibility
64 with systems where physical memory is truly contiguous.
65
66 Setting this option incorrectly may prevent the kernel from
67 booting. It is OK to leave it N.
68
69 For more information, consult
70 <file:Documentation/arm/Sharp-LH/SDRAM>.
71
72endmenu
73
74endif
diff --git a/arch/arm/mach-lh7a40x/Makefile b/arch/arm/mach-lh7a40x/Makefile
deleted file mode 100644
index 94b8615fb3c3..000000000000
--- a/arch/arm/mach-lh7a40x/Makefile
+++ /dev/null
@@ -1,17 +0,0 @@
1#
2# Makefile for the linux kernel.
3#
4
5# Object file lists.
6
7obj-y := time.o clocks.o
8obj-m :=
9obj-n :=
10obj- :=
11
12obj-$(CONFIG_MACH_KEV7A400) += arch-kev7a400.o irq-lh7a400.o
13obj-$(CONFIG_MACH_LPD7A400) += arch-lpd7a40x.o irq-lh7a400.o
14obj-$(CONFIG_MACH_LPD7A404) += arch-lpd7a40x.o irq-lh7a404.o
15obj-$(CONFIG_LPD7A40X_CPLD_SSP) += ssp-cpld.o
16obj-$(CONFIG_FB_ARMCLCD) += clcd.o
17
diff --git a/arch/arm/mach-lh7a40x/Makefile.boot b/arch/arm/mach-lh7a40x/Makefile.boot
deleted file mode 100644
index af941be076eb..000000000000
--- a/arch/arm/mach-lh7a40x/Makefile.boot
+++ /dev/null
@@ -1,4 +0,0 @@
1 zreladdr-y := 0xc0008000
2params_phys-y := 0xc0000100
3initrd_phys-y := 0xc4000000
4
diff --git a/arch/arm/mach-lh7a40x/arch-kev7a400.c b/arch/arm/mach-lh7a40x/arch-kev7a400.c
deleted file mode 100644
index 71129c33c7d2..000000000000
--- a/arch/arm/mach-lh7a40x/arch-kev7a400.c
+++ /dev/null
@@ -1,118 +0,0 @@
1/* arch/arm/mach-lh7a40x/arch-kev7a400.c
2 *
3 * Copyright (C) 2004 Logic Product Development
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * version 2 as published by the Free Software Foundation.
8 *
9 */
10
11#include <linux/tty.h>
12#include <linux/init.h>
13#include <linux/device.h>
14#include <linux/interrupt.h>
15
16#include <mach/hardware.h>
17#include <asm/setup.h>
18#include <asm/mach-types.h>
19#include <asm/mach/arch.h>
20#include <asm/irq.h>
21#include <asm/mach/irq.h>
22#include <asm/mach/map.h>
23
24#include "common.h"
25
26 /* This function calls the board specific IRQ initialization function. */
27
28static struct map_desc kev7a400_io_desc[] __initdata = {
29 {
30 .virtual = IO_VIRT,
31 .pfn = __phys_to_pfn(IO_PHYS),
32 .length = IO_SIZE,
33 .type = MT_DEVICE
34 }, {
35 .virtual = CPLD_VIRT,
36 .pfn = __phys_to_pfn(CPLD_PHYS),
37 .length = CPLD_SIZE,
38 .type = MT_DEVICE
39 }
40};
41
42void __init kev7a400_map_io(void)
43{
44 iotable_init (kev7a400_io_desc, ARRAY_SIZE (kev7a400_io_desc));
45}
46
47static u16 CPLD_IRQ_mask; /* Mask for CPLD IRQs, 1 == unmasked */
48
49static void kev7a400_ack_cpld_irq(struct irq_data *d)
50{
51 CPLD_CL_INT = 1 << (d->irq - IRQ_KEV7A400_CPLD);
52}
53
54static void kev7a400_mask_cpld_irq(struct irq_data *d)
55{
56 CPLD_IRQ_mask &= ~(1 << (d->irq - IRQ_KEV7A400_CPLD));
57 CPLD_WR_PB_INT_MASK = CPLD_IRQ_mask;
58}
59
60static void kev7a400_unmask_cpld_irq(struct irq_data *d)
61{
62 CPLD_IRQ_mask |= 1 << (d->irq - IRQ_KEV7A400_CPLD);
63 CPLD_WR_PB_INT_MASK = CPLD_IRQ_mask;
64}
65
66static struct irq_chip kev7a400_cpld_chip = {
67 .name = "CPLD",
68 .irq_ack = kev7a400_ack_cpld_irq,
69 .irq_mask = kev7a400_mask_cpld_irq,
70 .irq_unmask = kev7a400_unmask_cpld_irq,
71};
72
73
74static void kev7a400_cpld_handler (unsigned int irq, struct irq_desc *desc)
75{
76 u32 mask = CPLD_LATCHED_INTS;
77 irq = IRQ_KEV7A400_CPLD;
78 for (; mask; mask >>= 1, ++irq)
79 if (mask & 1)
80 generic_handle_irq(irq);
81}
82
83void __init lh7a40x_init_board_irq (void)
84{
85 int irq;
86
87 for (irq = IRQ_KEV7A400_CPLD;
88 irq < IRQ_KEV7A400_CPLD + NR_IRQ_BOARD; ++irq) {
89 set_irq_chip (irq, &kev7a400_cpld_chip);
90 set_irq_handler (irq, handle_edge_irq);
91 set_irq_flags (irq, IRQF_VALID);
92 }
93 set_irq_chained_handler (IRQ_CPLD, kev7a400_cpld_handler);
94
95 /* Clear all CPLD interrupts */
96 CPLD_CL_INT = 0xff; /* CPLD_INTR_MMC_CD | CPLD_INTR_ETH_INT; */
97
98 GPIO_GPIOINTEN = 0; /* Disable all GPIO interrupts */
99 barrier();
100
101#if 0
102 GPIO_INTTYPE1
103 = (GPIO_INTR_PCC1_CD | GPIO_INTR_PCC1_CD); /* Edge trig. */
104 GPIO_INTTYPE2 = 0; /* Falling edge & low-level */
105 GPIO_GPIOFEOI = 0xff; /* Clear all GPIO interrupts */
106 GPIO_GPIOINTEN = 0xff; /* Enable all GPIO interrupts */
107
108 init_FIQ();
109#endif
110}
111
112MACHINE_START (KEV7A400, "Sharp KEV7a400")
113 /* Maintainer: Marc Singer */
114 .boot_params = 0xc0000100,
115 .map_io = kev7a400_map_io,
116 .init_irq = lh7a400_init_irq,
117 .timer = &lh7a40x_timer,
118MACHINE_END
diff --git a/arch/arm/mach-lh7a40x/arch-lpd7a40x.c b/arch/arm/mach-lh7a40x/arch-lpd7a40x.c
deleted file mode 100644
index e735546181ad..000000000000
--- a/arch/arm/mach-lh7a40x/arch-lpd7a40x.c
+++ /dev/null
@@ -1,422 +0,0 @@
1/* arch/arm/mach-lh7a40x/arch-lpd7a40x.c
2 *
3 * Copyright (C) 2004 Logic Product Development
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * version 2 as published by the Free Software Foundation.
8 *
9 */
10
11#include <linux/tty.h>
12#include <linux/init.h>
13#include <linux/platform_device.h>
14#include <linux/interrupt.h>
15#include <linux/irq.h>
16
17#include <mach/hardware.h>
18#include <asm/setup.h>
19#include <asm/mach-types.h>
20#include <asm/mach/arch.h>
21#include <asm/irq.h>
22#include <asm/mach/irq.h>
23#include <asm/mach/map.h>
24
25#include "common.h"
26
27#define CPLD_INT_NETHERNET (1<<0)
28#define CPLD_INTMASK_ETHERNET (1<<2)
29#if defined (CONFIG_MACH_LPD7A400)
30# define CPLD_INT_NTOUCH (1<<1)
31# define CPLD_INTMASK_TOUCH (1<<3)
32# define CPLD_INT_PEN (1<<4)
33# define CPLD_INTMASK_PEN (1<<4)
34# define CPLD_INT_PIRQ (1<<4)
35#endif
36#define CPLD_INTMASK_CPLD (1<<7)
37#define CPLD_INT_CPLD (1<<6)
38
39#define CPLD_CONTROL_SWINT (1<<7) /* Disable all CPLD IRQs */
40#define CPLD_CONTROL_OCMSK (1<<6) /* Mask USB1 connect IRQ */
41#define CPLD_CONTROL_PDRV (1<<5) /* PCC_nDRV high */
42#define CPLD_CONTROL_USB1C (1<<4) /* USB1 connect IRQ active */
43#define CPLD_CONTROL_USB1P (1<<3) /* USB1 power disable */
44#define CPLD_CONTROL_AWKP (1<<2) /* Auto-wakeup disabled */
45#define CPLD_CONTROL_LCD_ENABLE (1<<1) /* LCD Vee enable */
46#define CPLD_CONTROL_WRLAN_NENABLE (1<<0) /* SMC91x power disable */
47
48
49static struct resource smc91x_resources[] = {
50 [0] = {
51 .start = CPLD00_PHYS,
52 .end = CPLD00_PHYS + CPLD00_SIZE - 1, /* Only needs 16B */
53 .flags = IORESOURCE_MEM,
54 },
55
56 [1] = {
57 .start = IRQ_LPD7A40X_ETH_INT,
58 .end = IRQ_LPD7A40X_ETH_INT,
59 .flags = IORESOURCE_IRQ,
60 },
61
62};
63
64static struct platform_device smc91x_device = {
65 .name = "smc91x",
66 .id = 0,
67 .num_resources = ARRAY_SIZE(smc91x_resources),
68 .resource = smc91x_resources,
69};
70
71static struct resource lh7a40x_usbclient_resources[] = {
72 [0] = {
73 .start = USB_PHYS,
74 .end = (USB_PHYS + PAGE_SIZE),
75 .flags = IORESOURCE_MEM,
76 },
77 [1] = {
78 .start = IRQ_USB,
79 .end = IRQ_USB,
80 .flags = IORESOURCE_IRQ,
81 },
82};
83
84static u64 lh7a40x_usbclient_dma_mask = 0xffffffffUL;
85
86static struct platform_device lh7a40x_usbclient_device = {
87// .name = "lh7a40x_udc",
88 .name = "lh7-udc",
89 .id = 0,
90 .dev = {
91 .dma_mask = &lh7a40x_usbclient_dma_mask,
92 .coherent_dma_mask = 0xffffffffUL,
93 },
94 .num_resources = ARRAY_SIZE (lh7a40x_usbclient_resources),
95 .resource = lh7a40x_usbclient_resources,
96};
97
98#if defined (CONFIG_ARCH_LH7A404)
99
100static struct resource lh7a404_usbhost_resources [] = {
101 [0] = {
102 .start = USBH_PHYS,
103 .end = (USBH_PHYS + 0xFF),
104 .flags = IORESOURCE_MEM,
105 },
106 [1] = {
107 .start = IRQ_USHINTR,
108 .end = IRQ_USHINTR,
109 .flags = IORESOURCE_IRQ,
110 },
111};
112
113static u64 lh7a404_usbhost_dma_mask = 0xffffffffUL;
114
115static struct platform_device lh7a404_usbhost_device = {
116 .name = "lh7a404-ohci",
117 .id = 0,
118 .dev = {
119 .dma_mask = &lh7a404_usbhost_dma_mask,
120 .coherent_dma_mask = 0xffffffffUL,
121 },
122 .num_resources = ARRAY_SIZE (lh7a404_usbhost_resources),
123 .resource = lh7a404_usbhost_resources,
124};
125
126#endif
127
128static struct platform_device* lpd7a40x_devs[] __initdata = {
129 &smc91x_device,
130 &lh7a40x_usbclient_device,
131#if defined (CONFIG_ARCH_LH7A404)
132 &lh7a404_usbhost_device,
133#endif
134};
135
136extern void lpd7a400_map_io (void);
137
138static void __init lpd7a40x_init (void)
139{
140#if defined (CONFIG_MACH_LPD7A400)
141 CPLD_CONTROL |= 0
142 | CPLD_CONTROL_SWINT /* Disable software interrupt */
143 | CPLD_CONTROL_OCMSK; /* Mask USB1 connection IRQ */
144 CPLD_CONTROL &= ~(0
145 | CPLD_CONTROL_LCD_ENABLE /* Disable LCD */
146 | CPLD_CONTROL_WRLAN_NENABLE /* Enable SMC91x */
147 );
148#endif
149
150#if defined (CONFIG_MACH_LPD7A404)
151 CPLD_CONTROL &= ~(0
152 | CPLD_CONTROL_WRLAN_NENABLE /* Enable SMC91x */
153 );
154#endif
155
156 platform_add_devices (lpd7a40x_devs, ARRAY_SIZE (lpd7a40x_devs));
157#if defined (CONFIG_FB_ARMCLCD)
158 lh7a40x_clcd_init ();
159#endif
160}
161
162static void lh7a40x_ack_cpld_irq(struct irq_data *d)
163{
164 /* CPLD doesn't have ack capability, but some devices may */
165
166#if defined (CPLD_INTMASK_TOUCH)
167 /* The touch control *must* mask the interrupt because the
168 * interrupt bit is read by the driver to determine if the pen
169 * is still down. */
170 if (d->irq == IRQ_TOUCH)
171 CPLD_INTERRUPTS |= CPLD_INTMASK_TOUCH;
172#endif
173}
174
175static void lh7a40x_mask_cpld_irq(struct irq_data *d)
176{
177 switch (d->irq) {
178 case IRQ_LPD7A40X_ETH_INT:
179 CPLD_INTERRUPTS |= CPLD_INTMASK_ETHERNET;
180 break;
181#if defined (IRQ_TOUCH)
182 case IRQ_TOUCH:
183 CPLD_INTERRUPTS |= CPLD_INTMASK_TOUCH;
184 break;
185#endif
186 }
187}
188
189static void lh7a40x_unmask_cpld_irq(struct irq_data *d)
190{
191 switch (d->irq) {
192 case IRQ_LPD7A40X_ETH_INT:
193 CPLD_INTERRUPTS &= ~CPLD_INTMASK_ETHERNET;
194 break;
195#if defined (IRQ_TOUCH)
196 case IRQ_TOUCH:
197 CPLD_INTERRUPTS &= ~CPLD_INTMASK_TOUCH;
198 break;
199#endif
200 }
201}
202
203static struct irq_chip lpd7a40x_cpld_chip = {
204 .name = "CPLD",
205 .irq_ack = lh7a40x_ack_cpld_irq,
206 .irq_mask = lh7a40x_mask_cpld_irq,
207 .irq_unmask = lh7a40x_unmask_cpld_irq,
208};
209
210static void lpd7a40x_cpld_handler (unsigned int irq, struct irq_desc *desc)
211{
212 unsigned int mask = CPLD_INTERRUPTS;
213
214 desc->irq_data.chip->irq_ack(&desc->irq_data);
215
216 if ((mask & (1<<0)) == 0) /* WLAN */
217 generic_handle_irq(IRQ_LPD7A40X_ETH_INT);
218
219#if defined (IRQ_TOUCH)
220 if ((mask & (1<<1)) == 0) /* Touch */
221 generic_handle_irq(IRQ_TOUCH);
222#endif
223
224 /* Level-triggered need this */
225 desc->irq_data.chip->irq_unmask(&desc->irq_data);
226}
227
228
229void __init lh7a40x_init_board_irq (void)
230{
231 int irq;
232
233 /* Rev A (v2.8): PF0, PF1, PF2, and PF3 are available IRQs.
234 PF7 supports the CPLD.
235 Rev B (v3.4): PF0, PF1, and PF2 are available IRQs.
236 PF3 supports the CPLD.
237 (Some) LPD7A404 prerelease boards report a version
238 number of 0x16, but we force an override since the
239 hardware is of the newer variety.
240 */
241
242 unsigned char cpld_version = CPLD_REVISION;
243 int pinCPLD = (cpld_version == 0x28) ? 7 : 3;
244
245#if defined CONFIG_MACH_LPD7A404
246 cpld_version = 0x34; /* Coerce LPD7A404 to RevB */
247#endif
248
249 /* First, configure user controlled GPIOF interrupts */
250
251 GPIO_PFDD &= ~0x0f; /* PF0-3 are inputs */
252 GPIO_INTTYPE1 &= ~0x0f; /* PF0-3 are level triggered */
253 GPIO_INTTYPE2 &= ~0x0f; /* PF0-3 are active low */
254 barrier ();
255 GPIO_GPIOFINTEN |= 0x0f; /* Enable PF0, PF1, PF2, and PF3 IRQs */
256
257 /* Then, configure CPLD interrupt */
258
259 /* Disable all CPLD interrupts */
260#if defined (CONFIG_MACH_LPD7A400)
261 CPLD_INTERRUPTS = CPLD_INTMASK_TOUCH | CPLD_INTMASK_PEN
262 | CPLD_INTMASK_ETHERNET;
263 /* *** FIXME: don't know why we need 7 and 4. 7 is way wrong
264 and 4 is uncefined. */
265 // (1<<7)|(1<<4)|(1<<3)|(1<<2);
266#endif
267#if defined (CONFIG_MACH_LPD7A404)
268 CPLD_INTERRUPTS = CPLD_INTMASK_ETHERNET;
269 /* *** FIXME: don't know why we need 6 and 5, neither is defined. */
270 // (1<<6)|(1<<5)|(1<<3);
271#endif
272 GPIO_PFDD &= ~(1 << pinCPLD); /* Make input */
273 GPIO_INTTYPE1 &= ~(1 << pinCPLD); /* Level triggered */
274 GPIO_INTTYPE2 &= ~(1 << pinCPLD); /* Active low */
275 barrier ();
276 GPIO_GPIOFINTEN |= (1 << pinCPLD); /* Enable */
277
278 /* Cascade CPLD interrupts */
279
280 for (irq = IRQ_BOARD_START;
281 irq < IRQ_BOARD_START + NR_IRQ_BOARD; ++irq) {
282 set_irq_chip (irq, &lpd7a40x_cpld_chip);
283 set_irq_handler (irq, handle_level_irq);
284 set_irq_flags (irq, IRQF_VALID);
285 }
286
287 set_irq_chained_handler ((cpld_version == 0x28)
288 ? IRQ_CPLD_V28
289 : IRQ_CPLD_V34,
290 lpd7a40x_cpld_handler);
291}
292
293static struct map_desc lpd7a40x_io_desc[] __initdata = {
294 {
295 .virtual = IO_VIRT,
296 .pfn = __phys_to_pfn(IO_PHYS),
297 .length = IO_SIZE,
298 .type = MT_DEVICE
299 },
300 { /* Mapping added to work around chip select problems */
301 .virtual = IOBARRIER_VIRT,
302 .pfn = __phys_to_pfn(IOBARRIER_PHYS),
303 .length = IOBARRIER_SIZE,
304 .type = MT_DEVICE
305 },
306 {
307 .virtual = CF_VIRT,
308 .pfn = __phys_to_pfn(CF_PHYS),
309 .length = CF_SIZE,
310 .type = MT_DEVICE
311 },
312 {
313 .virtual = CPLD02_VIRT,
314 .pfn = __phys_to_pfn(CPLD02_PHYS),
315 .length = CPLD02_SIZE,
316 .type = MT_DEVICE
317 },
318 {
319 .virtual = CPLD06_VIRT,
320 .pfn = __phys_to_pfn(CPLD06_PHYS),
321 .length = CPLD06_SIZE,
322 .type = MT_DEVICE
323 },
324 {
325 .virtual = CPLD08_VIRT,
326 .pfn = __phys_to_pfn(CPLD08_PHYS),
327 .length = CPLD08_SIZE,
328 .type = MT_DEVICE
329 },
330 {
331 .virtual = CPLD08_VIRT,
332 .pfn = __phys_to_pfn(CPLD08_PHYS),
333 .length = CPLD08_SIZE,
334 .type = MT_DEVICE
335 },
336 {
337 .virtual = CPLD0A_VIRT,
338 .pfn = __phys_to_pfn(CPLD0A_PHYS),
339 .length = CPLD0A_SIZE,
340 .type = MT_DEVICE
341 },
342 {
343 .virtual = CPLD0C_VIRT,
344 .pfn = __phys_to_pfn(CPLD0C_PHYS),
345 .length = CPLD0C_SIZE,
346 .type = MT_DEVICE
347 },
348 {
349 .virtual = CPLD0E_VIRT,
350 .pfn = __phys_to_pfn(CPLD0E_PHYS),
351 .length = CPLD0E_SIZE,
352 .type = MT_DEVICE
353 },
354 {
355 .virtual = CPLD10_VIRT,
356 .pfn = __phys_to_pfn(CPLD10_PHYS),
357 .length = CPLD10_SIZE,
358 .type = MT_DEVICE
359 },
360 {
361 .virtual = CPLD12_VIRT,
362 .pfn = __phys_to_pfn(CPLD12_PHYS),
363 .length = CPLD12_SIZE,
364 .type = MT_DEVICE
365 },
366 {
367 .virtual = CPLD14_VIRT,
368 .pfn = __phys_to_pfn(CPLD14_PHYS),
369 .length = CPLD14_SIZE,
370 .type = MT_DEVICE
371 },
372 {
373 .virtual = CPLD16_VIRT,
374 .pfn = __phys_to_pfn(CPLD16_PHYS),
375 .length = CPLD16_SIZE,
376 .type = MT_DEVICE
377 },
378 {
379 .virtual = CPLD18_VIRT,
380 .pfn = __phys_to_pfn(CPLD18_PHYS),
381 .length = CPLD18_SIZE,
382 .type = MT_DEVICE
383 },
384 {
385 .virtual = CPLD1A_VIRT,
386 .pfn = __phys_to_pfn(CPLD1A_PHYS),
387 .length = CPLD1A_SIZE,
388 .type = MT_DEVICE
389 },
390};
391
392void __init
393lpd7a40x_map_io(void)
394{
395 iotable_init (lpd7a40x_io_desc, ARRAY_SIZE (lpd7a40x_io_desc));
396}
397
398#ifdef CONFIG_MACH_LPD7A400
399
400MACHINE_START (LPD7A400, "Logic Product Development LPD7A400-10")
401 /* Maintainer: Marc Singer */
402 .boot_params = 0xc0000100,
403 .map_io = lpd7a40x_map_io,
404 .init_irq = lh7a400_init_irq,
405 .timer = &lh7a40x_timer,
406 .init_machine = lpd7a40x_init,
407MACHINE_END
408
409#endif
410
411#ifdef CONFIG_MACH_LPD7A404
412
413MACHINE_START (LPD7A404, "Logic Product Development LPD7A404-10")
414 /* Maintainer: Marc Singer */
415 .boot_params = 0xc0000100,
416 .map_io = lpd7a40x_map_io,
417 .init_irq = lh7a404_init_irq,
418 .timer = &lh7a40x_timer,
419 .init_machine = lpd7a40x_init,
420MACHINE_END
421
422#endif
diff --git a/arch/arm/mach-lh7a40x/clcd.c b/arch/arm/mach-lh7a40x/clcd.c
deleted file mode 100644
index 7fe4fd347c82..000000000000
--- a/arch/arm/mach-lh7a40x/clcd.c
+++ /dev/null
@@ -1,241 +0,0 @@
1/*
2 * arch/arm/mach-lh7a40x/clcd.c
3 *
4 * Copyright (C) 2004 Marc Singer
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * version 2 as published by the Free Software Foundation.
9 *
10 */
11
12#include <linux/init.h>
13#include <linux/gfp.h>
14#include <linux/device.h>
15#include <linux/dma-mapping.h>
16#include <linux/sysdev.h>
17#include <linux/interrupt.h>
18
19//#include <linux/module.h>
20//#include <linux/time.h>
21
22//#include <asm/mach/time.h>
23#include <asm/irq.h>
24#include <asm/mach/irq.h>
25
26#include <asm/system.h>
27#include <mach/hardware.h>
28#include <linux/amba/bus.h>
29#include <linux/amba/clcd.h>
30
31#define HRTFTC_HRSETUP __REG(HRTFTC_PHYS + 0x00)
32#define HRTFTC_HRCON __REG(HRTFTC_PHYS + 0x04)
33#define HRTFTC_HRTIMING1 __REG(HRTFTC_PHYS + 0x08)
34#define HRTFTC_HRTIMING2 __REG(HRTFTC_PHYS + 0x0c)
35
36#define ALI_SETUP __REG(ALI_PHYS + 0x00)
37#define ALI_CONTROL __REG(ALI_PHYS + 0x04)
38#define ALI_TIMING1 __REG(ALI_PHYS + 0x08)
39#define ALI_TIMING2 __REG(ALI_PHYS + 0x0c)
40
41#include "lcd-panel.h"
42
43static void lh7a40x_clcd_disable (struct clcd_fb *fb)
44{
45#if defined (CONFIG_MACH_LPD7A400)
46 CPLD_CONTROL &= ~(1<<1); /* Disable LCD Vee */
47#endif
48
49#if defined (CONFIG_MACH_LPD7A404)
50 GPIO_PCD &= ~(1<<3); /* Disable LCD Vee */
51#endif
52
53#if defined (CONFIG_ARCH_LH7A400)
54 HRTFTC_HRSETUP &= ~(1<<13); /* Disable HRTFT controller */
55#endif
56
57#if defined (CONFIG_ARCH_LH7A404)
58 ALI_SETUP &= ~(1<<13); /* Disable ALI */
59#endif
60}
61
62static void lh7a40x_clcd_enable (struct clcd_fb *fb)
63{
64 struct clcd_panel_extra* extra
65 = (struct clcd_panel_extra*) fb->board_data;
66
67#if defined (CONFIG_MACH_LPD7A400)
68 CPLD_CONTROL |= (1<<1); /* Enable LCD Vee */
69#endif
70
71#if defined (CONFIG_MACH_LPD7A404)
72 GPIO_PCDD &= ~(1<<3); /* Enable LCD Vee */
73 GPIO_PCD |= (1<<3);
74#endif
75
76#if defined (CONFIG_ARCH_LH7A400)
77
78 if (extra) {
79 HRTFTC_HRSETUP
80 = (1 << 13)
81 | ((fb->fb.var.xres - 1) << 4)
82 | 0xc
83 | (extra->hrmode ? 1 : 0);
84 HRTFTC_HRCON
85 = ((extra->clsen ? 1 : 0) << 1)
86 | ((extra->spsen ? 1 : 0) << 0);
87 HRTFTC_HRTIMING1
88 = (extra->pcdel << 8)
89 | (extra->revdel << 4)
90 | (extra->lpdel << 0);
91 HRTFTC_HRTIMING2
92 = (extra->spldel << 9)
93 | (extra->pc2del << 0);
94 }
95 else
96 HRTFTC_HRSETUP
97 = (1 << 13)
98 | 0xc;
99#endif
100
101#if defined (CONFIG_ARCH_LH7A404)
102
103 if (extra) {
104 ALI_SETUP
105 = (1 << 13)
106 | ((fb->fb.var.xres - 1) << 4)
107 | 0xc
108 | (extra->hrmode ? 1 : 0);
109 ALI_CONTROL
110 = ((extra->clsen ? 1 : 0) << 1)
111 | ((extra->spsen ? 1 : 0) << 0);
112 ALI_TIMING1
113 = (extra->pcdel << 8)
114 | (extra->revdel << 4)
115 | (extra->lpdel << 0);
116 ALI_TIMING2
117 = (extra->spldel << 9)
118 | (extra->pc2del << 0);
119 }
120 else
121 ALI_SETUP
122 = (1 << 13)
123 | 0xc;
124#endif
125
126}
127
128#define FRAMESIZE(s) (((s) + PAGE_SIZE - 1)&PAGE_MASK)
129
130static int lh7a40x_clcd_setup (struct clcd_fb *fb)
131{
132 dma_addr_t dma;
133 u32 len = FRAMESIZE (lcd_panel.mode.xres*lcd_panel.mode.yres
134 *(lcd_panel.bpp/8));
135
136 fb->panel = &lcd_panel;
137
138 /* Enforce the sync polarity defaults */
139 if (!(fb->panel->tim2 & TIM2_IHS))
140 fb->fb.var.sync |= FB_SYNC_HOR_HIGH_ACT;
141 if (!(fb->panel->tim2 & TIM2_IVS))
142 fb->fb.var.sync |= FB_SYNC_VERT_HIGH_ACT;
143
144#if defined (HAS_LCD_PANEL_EXTRA)
145 fb->board_data = &lcd_panel_extra;
146#endif
147
148 fb->fb.screen_base
149 = dma_alloc_writecombine (&fb->dev->dev, len,
150 &dma, GFP_KERNEL);
151 printk ("CLCD: LCD setup fb virt 0x%p phys 0x%p l %x io 0x%p \n",
152 fb->fb.screen_base, (void*) dma, len,
153 (void*) io_p2v (CLCDC_PHYS));
154 printk ("CLCD: pixclock %d\n", lcd_panel.mode.pixclock);
155
156 if (!fb->fb.screen_base) {
157 printk(KERN_ERR "CLCD: unable to map framebuffer\n");
158 return -ENOMEM;
159 }
160
161#if defined (USE_RGB555)
162 fb->fb.var.green.length = 5; /* Panel uses RGB 5:5:5 */
163#endif
164
165 fb->fb.fix.smem_start = dma;
166 fb->fb.fix.smem_len = len;
167
168 /* Drive PE4 high to prevent CPLD crash */
169 GPIO_PEDD |= (1<<4);
170 GPIO_PED |= (1<<4);
171
172 GPIO_PINMUX |= (1<<1) | (1<<0); /* LCDVD[15:4] */
173
174// fb->fb.fbops->fb_check_var (&fb->fb.var, &fb->fb);
175// fb->fb.fbops->fb_set_par (&fb->fb);
176
177 return 0;
178}
179
180static int lh7a40x_clcd_mmap (struct clcd_fb *fb, struct vm_area_struct *vma)
181{
182 return dma_mmap_writecombine(&fb->dev->dev, vma,
183 fb->fb.screen_base,
184 fb->fb.fix.smem_start,
185 fb->fb.fix.smem_len);
186}
187
188static void lh7a40x_clcd_remove (struct clcd_fb *fb)
189{
190 dma_free_writecombine (&fb->dev->dev, fb->fb.fix.smem_len,
191 fb->fb.screen_base, fb->fb.fix.smem_start);
192}
193
194static struct clcd_board clcd_platform_data = {
195 .name = "lh7a40x FB",
196 .check = clcdfb_check,
197 .decode = clcdfb_decode,
198 .enable = lh7a40x_clcd_enable,
199 .setup = lh7a40x_clcd_setup,
200 .mmap = lh7a40x_clcd_mmap,
201 .remove = lh7a40x_clcd_remove,
202 .disable = lh7a40x_clcd_disable,
203};
204
205#define IRQ_CLCDC (IRQ_LCDINTR)
206
207#define AMBA_DEVICE(name,busid,base,plat,pid) \
208static struct amba_device name##_device = { \
209 .dev = { \
210 .coherent_dma_mask = ~0, \
211 .init_name = busid, \
212 .platform_data = plat, \
213 }, \
214 .res = { \
215 .start = base##_PHYS, \
216 .end = (base##_PHYS) + (4*1024) - 1, \
217 .flags = IORESOURCE_MEM, \
218 }, \
219 .dma_mask = ~0, \
220 .irq = { IRQ_##base, }, \
221 /* .dma = base##_DMA,*/ \
222 .periphid = pid, \
223}
224
225AMBA_DEVICE(clcd, "cldc-lh7a40x", CLCDC, &clcd_platform_data, 0x41110);
226
227static struct amba_device *amba_devs[] __initdata = {
228 &clcd_device,
229};
230
231void __init lh7a40x_clcd_init (void)
232{
233 int i;
234 int result;
235 printk ("CLCD: registering amba devices\n");
236 for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
237 struct amba_device *d = amba_devs[i];
238 result = amba_device_register(d, &iomem_resource);
239 printk (" %d -> %d\n", i ,result);
240 }
241}
diff --git a/arch/arm/mach-lh7a40x/clocks.c b/arch/arm/mach-lh7a40x/clocks.c
deleted file mode 100644
index 0651f96653f9..000000000000
--- a/arch/arm/mach-lh7a40x/clocks.c
+++ /dev/null
@@ -1,108 +0,0 @@
1/* arch/arm/mach-lh7a40x/clocks.c
2 *
3 * Copyright (C) 2004 Marc Singer
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * version 2 as published by the Free Software Foundation.
8 *
9 */
10#include <mach/hardware.h>
11#include <mach/clocks.h>
12#include <linux/err.h>
13#include <linux/device.h>
14#include <linux/string.h>
15
16struct module;
17
18struct clk {
19 struct list_head node;
20 unsigned long rate;
21 struct module *owner;
22 const char *name;
23};
24
25/* ----- */
26
27#define MAINDIV1(c) (((c) >> 7) & 0x0f)
28#define MAINDIV2(c) (((c) >> 11) & 0x1f)
29#define PS(c) (((c) >> 18) & 0x03)
30#define PREDIV(c) (((c) >> 2) & 0x1f)
31#define HCLKDIV(c) (((c) >> 0) & 0x02)
32#define PCLKDIV(c) (((c) >> 16) & 0x03)
33
34unsigned int fclkfreq_get (void)
35{
36 unsigned int clkset = CSC_CLKSET;
37 unsigned int gclk
38 = XTAL_IN
39 / (1 << PS(clkset))
40 * (MAINDIV1(clkset) + 2)
41 / (PREDIV(clkset) + 2)
42 * (MAINDIV2(clkset) + 2)
43 ;
44 return gclk;
45}
46
47unsigned int hclkfreq_get (void)
48{
49 unsigned int clkset = CSC_CLKSET;
50 unsigned int hclk = fclkfreq_get () / (HCLKDIV(clkset) + 1);
51
52 return hclk;
53}
54
55unsigned int pclkfreq_get (void)
56{
57 unsigned int clkset = CSC_CLKSET;
58 int pclkdiv = PCLKDIV(clkset);
59 unsigned int pclk;
60 if (pclkdiv == 0x3)
61 pclkdiv = 0x2;
62 pclk = hclkfreq_get () / (1 << pclkdiv);
63
64 return pclk;
65}
66
67/* ----- */
68
69struct clk *clk_get (struct device *dev, const char *id)
70{
71 return dev && strcmp(dev_name(dev), "cldc-lh7a40x") == 0
72 ? NULL : ERR_PTR(-ENOENT);
73}
74EXPORT_SYMBOL(clk_get);
75
76void clk_put (struct clk *clk)
77{
78}
79EXPORT_SYMBOL(clk_put);
80
81int clk_enable (struct clk *clk)
82{
83 return 0;
84}
85EXPORT_SYMBOL(clk_enable);
86
87void clk_disable (struct clk *clk)
88{
89}
90EXPORT_SYMBOL(clk_disable);
91
92unsigned long clk_get_rate (struct clk *clk)
93{
94 return 0;
95}
96EXPORT_SYMBOL(clk_get_rate);
97
98long clk_round_rate (struct clk *clk, unsigned long rate)
99{
100 return rate;
101}
102EXPORT_SYMBOL(clk_round_rate);
103
104int clk_set_rate (struct clk *clk, unsigned long rate)
105{
106 return -EIO;
107}
108EXPORT_SYMBOL(clk_set_rate);
diff --git a/arch/arm/mach-lh7a40x/common.h b/arch/arm/mach-lh7a40x/common.h
deleted file mode 100644
index 6ed3f6b6db76..000000000000
--- a/arch/arm/mach-lh7a40x/common.h
+++ /dev/null
@@ -1,17 +0,0 @@
1/* arch/arm/mach-lh7a40x/common.h
2 *
3 * Copyright (C) 2004 Marc Singer
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * version 2 as published by the Free Software Foundation.
8 *
9 */
10
11extern struct sys_timer lh7a40x_timer;
12
13extern void lh7a400_init_irq (void);
14extern void lh7a404_init_irq (void);
15extern void lh7a40x_clcd_init (void);
16extern void lh7a40x_init_board_irq (void);
17
diff --git a/arch/arm/mach-lh7a40x/include/mach/clocks.h b/arch/arm/mach-lh7a40x/include/mach/clocks.h
deleted file mode 100644
index fe2e0255c084..000000000000
--- a/arch/arm/mach-lh7a40x/include/mach/clocks.h
+++ /dev/null
@@ -1,18 +0,0 @@
1/* arch/arm/mach-lh7a40x/include/mach/clocks.h
2 *
3 * Copyright (C) 2004 Marc Singer
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * version 2 as published by the Free Software Foundation.
8 *
9 */
10
11#ifndef __ASM_ARCH_CLOCKS_H
12#define __ASM_ARCH_CLOCKS_H
13
14unsigned int fclkfreq_get (void);
15unsigned int hclkfreq_get (void);
16unsigned int pclkfreq_get (void);
17
18#endif /* _ASM_ARCH_CLOCKS_H */
diff --git a/arch/arm/mach-lh7a40x/include/mach/constants.h b/arch/arm/mach-lh7a40x/include/mach/constants.h
deleted file mode 100644
index 55c6edbc2dfd..000000000000
--- a/arch/arm/mach-lh7a40x/include/mach/constants.h
+++ /dev/null
@@ -1,91 +0,0 @@
1/* arch/arm/mach-lh7a40x/include/mach/constants.h
2 *
3 * Copyright (C) 2004 Coastal Environmental Systems
4 * Copyright (C) 2004 Logic Product Development
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * version 2 as published by the Free Software Foundation.
9 *
10 */
11
12#ifndef __ASM_ARCH_CONSTANTS_H
13#define __ASM_ARCH_CONSTANTS_H
14
15
16/* Addressing constants */
17
18 /* SoC CPU IO addressing */
19#define IO_PHYS (0x80000000)
20#define IO_VIRT (0xf8000000)
21#define IO_SIZE (0x0000B000)
22
23#ifdef CONFIG_MACH_KEV7A400
24# define CPLD_PHYS (0x20000000)
25# define CPLD_VIRT (0xf2000000)
26# define CPLD_SIZE PAGE_SIZE
27#endif
28
29#if defined (CONFIG_MACH_LPD7A400) || defined (CONFIG_MACH_LPD7A404)
30
31# define IOBARRIER_PHYS 0x10000000 /* Second bank, fastest timing */
32# define IOBARRIER_VIRT 0xf0000000
33# define IOBARRIER_SIZE PAGE_SIZE
34
35# define CF_PHYS 0x60200000
36# define CF_VIRT 0xf6020000
37# define CF_SIZE (8*1024)
38
39 /* The IO mappings for the LPD CPLD are, unfortunately, sparse. */
40# define CPLDX_PHYS(x) (0x70000000 | ((x) << 20))
41# define CPLDX_VIRT(x) (0xf7000000 | ((x) << 16))
42# define CPLD00_PHYS CPLDX_PHYS (0x00) /* Wired LAN */
43# define CPLD00_VIRT CPLDX_VIRT (0x00)
44# define CPLD00_SIZE PAGE_SIZE
45# define CPLD02_PHYS CPLDX_PHYS (0x02)
46# define CPLD02_VIRT CPLDX_VIRT (0x02)
47# define CPLD02_SIZE PAGE_SIZE
48# define CPLD06_PHYS CPLDX_PHYS (0x06)
49# define CPLD06_VIRT CPLDX_VIRT (0x06)
50# define CPLD06_SIZE PAGE_SIZE
51# define CPLD08_PHYS CPLDX_PHYS (0x08)
52# define CPLD08_VIRT CPLDX_VIRT (0x08)
53# define CPLD08_SIZE PAGE_SIZE
54# define CPLD0A_PHYS CPLDX_PHYS (0x0a)
55# define CPLD0A_VIRT CPLDX_VIRT (0x0a)
56# define CPLD0A_SIZE PAGE_SIZE
57# define CPLD0C_PHYS CPLDX_PHYS (0x0c)
58# define CPLD0C_VIRT CPLDX_VIRT (0x0c)
59# define CPLD0C_SIZE PAGE_SIZE
60# define CPLD0E_PHYS CPLDX_PHYS (0x0e)
61# define CPLD0E_VIRT CPLDX_VIRT (0x0e)
62# define CPLD0E_SIZE PAGE_SIZE
63# define CPLD10_PHYS CPLDX_PHYS (0x10)
64# define CPLD10_VIRT CPLDX_VIRT (0x10)
65# define CPLD10_SIZE PAGE_SIZE
66# define CPLD12_PHYS CPLDX_PHYS (0x12)
67# define CPLD12_VIRT CPLDX_VIRT (0x12)
68# define CPLD12_SIZE PAGE_SIZE
69# define CPLD14_PHYS CPLDX_PHYS (0x14)
70# define CPLD14_VIRT CPLDX_VIRT (0x14)
71# define CPLD14_SIZE PAGE_SIZE
72# define CPLD16_PHYS CPLDX_PHYS (0x16)
73# define CPLD16_VIRT CPLDX_VIRT (0x16)
74# define CPLD16_SIZE PAGE_SIZE
75# define CPLD18_PHYS CPLDX_PHYS (0x18)
76# define CPLD18_VIRT CPLDX_VIRT (0x18)
77# define CPLD18_SIZE PAGE_SIZE
78# define CPLD1A_PHYS CPLDX_PHYS (0x1a)
79# define CPLD1A_VIRT CPLDX_VIRT (0x1a)
80# define CPLD1A_SIZE PAGE_SIZE
81#endif
82
83 /* Timing constants */
84
85#define XTAL_IN 14745600 /* 14.7456 MHz crystal */
86#define PLL_CLOCK (XTAL_IN * 21) /* 309 MHz PLL clock */
87#define MAX_HCLK_KHZ 100000 /* HCLK max limit ~100MHz */
88#define HCLK (99993600)
89//#define HCLK (119808000)
90
91#endif /* __ASM_ARCH_CONSTANTS_H */
diff --git a/arch/arm/mach-lh7a40x/include/mach/debug-macro.S b/arch/arm/mach-lh7a40x/include/mach/debug-macro.S
deleted file mode 100644
index cff33625276f..000000000000
--- a/arch/arm/mach-lh7a40x/include/mach/debug-macro.S
+++ /dev/null
@@ -1,37 +0,0 @@
1/* arch/arm/mach-lh7a40x/include/mach/debug-macro.S
2 *
3 * Debugging macro include header
4 *
5 * Copyright (C) 1994-1999 Russell King
6 * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12*/
13
14 @ It is not known if this will be appropriate for every 40x
15 @ board.
16
17 .macro addruart, rp, rv
18 mov \rp, #0x00000700 @ offset from base
19 orr \rv, \rp, #0xf8000000 @ virtual base
20 orr \rp, \rp, #0x80000000 @ physical base
21 .endm
22
23 .macro senduart,rd,rx
24 strb \rd, [\rx] @ DATA
25 .endm
26
27 .macro busyuart,rd,rx @ spin while busy
281001: ldr \rd, [\rx, #0x10] @ STATUS
29 tst \rd, #1 << 3 @ BUSY (TX FIFO not empty)
30 bne 1001b @ yes, spin
31 .endm
32
33 .macro waituart,rd,rx @ wait for Tx FIFO room
341001: ldrb \rd, [\rx, #0x10] @ STATUS
35 tst \rd, #1 << 5 @ TXFF (TX FIFO full)
36 bne 1001b @ yes, spin
37 .endm
diff --git a/arch/arm/mach-lh7a40x/include/mach/dma.h b/arch/arm/mach-lh7a40x/include/mach/dma.h
deleted file mode 100644
index baa3f8dbd04b..000000000000
--- a/arch/arm/mach-lh7a40x/include/mach/dma.h
+++ /dev/null
@@ -1,86 +0,0 @@
1/* arch/arm/mach-lh7a40x/include/mach/dma.h
2 *
3 * Copyright (C) 2005 Marc Singer
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * version 2 as published by the Free Software Foundation.
8 *
9 */
10
11typedef enum {
12 DMA_M2M0 = 0,
13 DMA_M2M1 = 1,
14 DMA_M2P0 = 2, /* Tx */
15 DMA_M2P1 = 3, /* Rx */
16 DMA_M2P2 = 4, /* Tx */
17 DMA_M2P3 = 5, /* Rx */
18 DMA_M2P4 = 6, /* Tx - AC97 */
19 DMA_M2P5 = 7, /* Rx - AC97 */
20 DMA_M2P6 = 8, /* Tx */
21 DMA_M2P7 = 9, /* Rx */
22} dma_device_t;
23
24#define DMA_LENGTH_MAX ((64*1024) - 4) /* bytes */
25
26#define DMAC_GCA __REG(DMAC_PHYS + 0x2b80)
27#define DMAC_GIR __REG(DMAC_PHYS + 0x2bc0)
28
29#define DMAC_GIR_MMI1 (1<<11)
30#define DMAC_GIR_MMI0 (1<<10)
31#define DMAC_GIR_MPI8 (1<<9)
32#define DMAC_GIR_MPI9 (1<<8)
33#define DMAC_GIR_MPI6 (1<<7)
34#define DMAC_GIR_MPI7 (1<<6)
35#define DMAC_GIR_MPI4 (1<<5)
36#define DMAC_GIR_MPI5 (1<<4)
37#define DMAC_GIR_MPI2 (1<<3)
38#define DMAC_GIR_MPI3 (1<<2)
39#define DMAC_GIR_MPI0 (1<<1)
40#define DMAC_GIR_MPI1 (1<<0)
41
42#define DMAC_M2P0 0x0000
43#define DMAC_M2P1 0x0040
44#define DMAC_M2P2 0x0080
45#define DMAC_M2P3 0x00c0
46#define DMAC_M2P4 0x0240
47#define DMAC_M2P5 0x0200
48#define DMAC_M2P6 0x02c0
49#define DMAC_M2P7 0x0280
50#define DMAC_M2P8 0x0340
51#define DMAC_M2P9 0x0300
52#define DMAC_M2M0 0x0100
53#define DMAC_M2M1 0x0140
54
55#define DMAC_P_PCONTROL(c) __REG(DMAC_PHYS + (c) + 0x00)
56#define DMAC_P_PINTERRUPT(c) __REG(DMAC_PHYS + (c) + 0x04)
57#define DMAC_P_PPALLOC(c) __REG(DMAC_PHYS + (c) + 0x08)
58#define DMAC_P_PSTATUS(c) __REG(DMAC_PHYS + (c) + 0x0c)
59#define DMAC_P_REMAIN(c) __REG(DMAC_PHYS + (c) + 0x14)
60#define DMAC_P_MAXCNT0(c) __REG(DMAC_PHYS + (c) + 0x20)
61#define DMAC_P_BASE0(c) __REG(DMAC_PHYS + (c) + 0x24)
62#define DMAC_P_CURRENT0(c) __REG(DMAC_PHYS + (c) + 0x28)
63#define DMAC_P_MAXCNT1(c) __REG(DMAC_PHYS + (c) + 0x30)
64#define DMAC_P_BASE1(c) __REG(DMAC_PHYS + (c) + 0x34)
65#define DMAC_P_CURRENT1(c) __REG(DMAC_PHYS + (c) + 0x38)
66
67#define DMAC_PCONTROL_ENABLE (1<<4)
68
69#define DMAC_PORT_USB 0
70#define DMAC_PORT_SDMMC 1
71#define DMAC_PORT_AC97_1 2
72#define DMAC_PORT_AC97_2 3
73#define DMAC_PORT_AC97_3 4
74#define DMAC_PORT_UART1 6
75#define DMAC_PORT_UART2 7
76#define DMAC_PORT_UART3 8
77
78#define DMAC_PSTATUS_CURRSTATE_SHIFT 4
79#define DMAC_PSTATUS_CURRSTATE_MASK 0x3
80
81#define DMAC_PSTATUS_NEXTBUF (1<<6)
82#define DMAC_PSTATUS_STALLRINT (1<<0)
83
84#define DMAC_INT_CHE (1<<3)
85#define DMAC_INT_NFB (1<<1)
86#define DMAC_INT_STALL (1<<0)
diff --git a/arch/arm/mach-lh7a40x/include/mach/entry-macro.S b/arch/arm/mach-lh7a40x/include/mach/entry-macro.S
deleted file mode 100644
index 069bb4cefff7..000000000000
--- a/arch/arm/mach-lh7a40x/include/mach/entry-macro.S
+++ /dev/null
@@ -1,149 +0,0 @@
1/*
2 * arch/arm/mach-lh7a40x/include/mach/entry-macro.S
3 *
4 * Low-level IRQ helper macros for LH7A40x platforms
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10#include <mach/hardware.h>
11#include <mach/irqs.h>
12
13/* In order to allow there to be support for both of the processor
14 classes at the same time, we make a hack here that isn't very
15 pretty. At startup, the link pointed to with the
16 branch_irq_lh7a400 symbol is replaced with a NOP when the CPU is
17 detected as a lh7a404.
18
19 *** FIXME: we should clean this up so that there is only one
20 implementation for each CPU's design.
21
22*/
23
24#if defined (CONFIG_ARCH_LH7A400) && defined (CONFIG_ARCH_LH7A404)
25
26 .macro disable_fiq
27 .endm
28
29 .macro get_irqnr_preamble, base, tmp
30 .endm
31
32 .macro arch_ret_to_user, tmp1, tmp2
33 .endm
34
35 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
36
37branch_irq_lh7a400: b 1000f
38
39@ Implementation of the LH7A404 get_irqnr_and_base.
40
41 mov \irqnr, #0 @ VIC1 irq base
42 mov \base, #io_p2v(0x80000000) @ APB registers
43 add \base, \base, #0x8000
44 ldr \tmp, [\base, #0x0030] @ VIC1_VECTADDR
45 tst \tmp, #VA_VECTORED @ Direct vectored
46 bne 1002f
47 tst \tmp, #VA_VIC1DEFAULT @ Default vectored VIC1
48 ldrne \irqstat, [\base, #0] @ VIC1_IRQSTATUS
49 bne 1001f
50 add \base, \base, #(0xa000 - 0x8000)
51 ldr \tmp, [\base, #0x0030] @ VIC2_VECTADDR
52 tst \tmp, #VA_VECTORED @ Direct vectored
53 bne 1002f
54 ldr \irqstat, [\base, #0] @ VIC2_IRQSTATUS
55 mov \irqnr, #32 @ VIC2 irq base
56
571001: movs \irqstat, \irqstat, lsr #1 @ Shift into carry
58 bcs 1008f @ Bit set; irq found
59 add \irqnr, \irqnr, #1
60 bne 1001b @ Until no bits
61 b 1009f @ Nothing? Hmm.
621002: and \irqnr, \tmp, #0x3f @ Mask for valid bits
631008: movs \irqstat, #1 @ Force !Z
64 str \tmp, [\base, #0x0030] @ Clear vector
65 b 1009f
66
67@ Implementation of the LH7A400 get_irqnr_and_base.
68
691000: mov \irqnr, #0
70 mov \base, #io_p2v(0x80000000) @ APB registers
71 ldr \irqstat, [\base, #0x500] @ PIC INTSR
72
731001: movs \irqstat, \irqstat, lsr #1 @ Shift into carry
74 bcs 1008f @ Bit set; irq found
75 add \irqnr, \irqnr, #1
76 bne 1001b @ Until no bits
77 b 1009f @ Nothing? Hmm.
781008: movs \irqstat, #1 @ Force !Z
79
801009:
81 .endm
82
83
84
85#elif defined (CONFIG_ARCH_LH7A400)
86 .macro disable_fiq
87 .endm
88
89 .macro get_irqnr_preamble, base, tmp
90 .endm
91
92 .macro arch_ret_to_user, tmp1, tmp2
93 .endm
94
95 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
96 mov \irqnr, #0
97 mov \base, #io_p2v(0x80000000) @ APB registers
98 ldr \irqstat, [\base, #0x500] @ PIC INTSR
99
1001001: movs \irqstat, \irqstat, lsr #1 @ Shift into carry
101 bcs 1008f @ Bit set; irq found
102 add \irqnr, \irqnr, #1
103 bne 1001b @ Until no bits
104 b 1009f @ Nothing? Hmm.
1051008: movs \irqstat, #1 @ Force !Z
1061009:
107 .endm
108
109#elif defined(CONFIG_ARCH_LH7A404)
110
111 .macro disable_fiq
112 .endm
113
114 .macro get_irqnr_preamble, base, tmp
115 .endm
116
117 .macro arch_ret_to_user, tmp1, tmp2
118 .endm
119
120 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
121 mov \irqnr, #0 @ VIC1 irq base
122 mov \base, #io_p2v(0x80000000) @ APB registers
123 add \base, \base, #0x8000
124 ldr \tmp, [\base, #0x0030] @ VIC1_VECTADDR
125 tst \tmp, #VA_VECTORED @ Direct vectored
126 bne 1002f
127 tst \tmp, #VA_VIC1DEFAULT @ Default vectored VIC1
128 ldrne \irqstat, [\base, #0] @ VIC1_IRQSTATUS
129 bne 1001f
130 add \base, \base, #(0xa000 - 0x8000)
131 ldr \tmp, [\base, #0x0030] @ VIC2_VECTADDR
132 tst \tmp, #VA_VECTORED @ Direct vectored
133 bne 1002f
134 ldr \irqstat, [\base, #0] @ VIC2_IRQSTATUS
135 mov \irqnr, #32 @ VIC2 irq base
136
1371001: movs \irqstat, \irqstat, lsr #1 @ Shift into carry
138 bcs 1008f @ Bit set; irq found
139 add \irqnr, \irqnr, #1
140 bne 1001b @ Until no bits
141 b 1009f @ Nothing? Hmm.
1421002: and \irqnr, \tmp, #0x3f @ Mask for valid bits
1431008: movs \irqstat, #1 @ Force !Z
144 str \tmp, [\base, #0x0030] @ Clear vector
1451009:
146 .endm
147#endif
148
149
diff --git a/arch/arm/mach-lh7a40x/include/mach/hardware.h b/arch/arm/mach-lh7a40x/include/mach/hardware.h
deleted file mode 100644
index 59d2ace35217..000000000000
--- a/arch/arm/mach-lh7a40x/include/mach/hardware.h
+++ /dev/null
@@ -1,62 +0,0 @@
1/* arch/arm/mach-lh7a40x/include/mach/hardware.h
2 *
3 * Copyright (C) 2004 Coastal Environmental Systems
4 *
5 * [ Substantially cribbed from arch/arm/mach-pxa/include/mach/hardware.h ]
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * version 2 as published by the Free Software Foundation.
10 *
11 */
12
13#ifndef __ASM_ARCH_HARDWARE_H
14#define __ASM_ARCH_HARDWARE_H
15
16#include <asm/sizes.h> /* Added for the sake of amba-clcd driver */
17
18#define io_p2v(x) (0xf0000000 | (((x) & 0xfff00000) >> 4) | ((x) & 0x0000ffff))
19#define io_v2p(x) ( (((x) & 0x0fff0000) << 4) | ((x) & 0x0000ffff))
20
21#ifdef __ASSEMBLY__
22
23# define __REG(x) io_p2v(x)
24# define __PREG(x) io_v2p(x)
25
26#else
27
28# if 0
29# define __REG(x) (*((volatile u32 *)io_p2v(x)))
30# else
31/*
32 * This __REG() version gives the same results as the one above, except
33 * that we are fooling gcc somehow so it generates far better and smaller
34 * assembly code for access to contiguous registers. It's a shame that gcc
35 * doesn't guess this by itself.
36 */
37#include <asm/types.h>
38typedef struct { volatile u32 offset[4096]; } __regbase;
39# define __REGP(x) ((__regbase *)((x)&~4095))->offset[((x)&4095)>>2]
40# define __REG(x) __REGP(io_p2v(x))
41typedef struct { volatile u16 offset[4096]; } __regbase16;
42# define __REGP16(x) ((__regbase16 *)((x)&~4095))->offset[((x)&4095)>>1]
43# define __REG16(x) __REGP16(io_p2v(x))
44typedef struct { volatile u8 offset[4096]; } __regbase8;
45# define __REGP8(x) ((__regbase8 *)((x)&~4095))->offset[(x)&4095]
46# define __REG8(x) __REGP8(io_p2v(x))
47#endif
48
49/* Let's kick gcc's ass again... */
50# define __REG2(x,y) \
51 ( __builtin_constant_p(y) ? (__REG((x) + (y))) \
52 : (*(volatile u32 *)((u32)&__REG(x) + (y))) )
53
54# define __PREG(x) (io_v2p((u32)&(x)))
55
56#endif
57
58#define MASK_AND_SET(v,m,s) (v) = ((v)&~(m))|(s)
59
60#include "registers.h"
61
62#endif /* _ASM_ARCH_HARDWARE_H */
diff --git a/arch/arm/mach-lh7a40x/include/mach/io.h b/arch/arm/mach-lh7a40x/include/mach/io.h
deleted file mode 100644
index 6ece45911cbc..000000000000
--- a/arch/arm/mach-lh7a40x/include/mach/io.h
+++ /dev/null
@@ -1,20 +0,0 @@
1/* arch/arm/mach-lh7a40x/include/mach/io.h
2 *
3 * Copyright (C) 2004 Coastal Environmental Systems
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * version 2 as published by the Free Software Foundation.
8 *
9 */
10
11#ifndef __ASM_ARCH_IO_H
12#define __ASM_ARCH_IO_H
13
14#define IO_SPACE_LIMIT 0xffffffff
15
16/* No ISA or PCI bus on this machine. */
17#define __io(a) __typesafe_io(a)
18#define __mem_pci(a) (a)
19
20#endif /* __ASM_ARCH_IO_H */
diff --git a/arch/arm/mach-lh7a40x/include/mach/irqs.h b/arch/arm/mach-lh7a40x/include/mach/irqs.h
deleted file mode 100644
index 0f9b83675935..000000000000
--- a/arch/arm/mach-lh7a40x/include/mach/irqs.h
+++ /dev/null
@@ -1,200 +0,0 @@
1/* arch/arm/mach-lh7a40x/include/mach/irqs.h
2 *
3 * Copyright (C) 2004 Coastal Environmental Systems
4 * Copyright (C) 2004 Logic Product Development
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * version 2 as published by the Free Software Foundation.
9 *
10 */
11
12/* It is to be seen whether or not we can build a kernel for more than
13 * one board. For the time being, these macros assume that we cannot.
14 * Thus, it is OK to ifdef machine/board specific IRQ assignments.
15 */
16
17
18#ifndef __ASM_ARCH_IRQS_H
19#define __ASM_ARCH_IRQS_H
20
21
22#define FIQ_START 80
23
24#if defined (CONFIG_ARCH_LH7A400)
25
26 /* FIQs */
27
28# define IRQ_GPIO0FIQ 0 /* GPIO External FIQ Interrupt on F0 */
29# define IRQ_BLINT 1 /* Battery Low */
30# define IRQ_WEINT 2 /* Watchdog Timer, WDT overflow */
31# define IRQ_MCINT 3 /* Media Change, MEDCHG pin rising */
32
33 /* IRQs */
34
35# define IRQ_CSINT 4 /* Audio Codec (ACI) */
36# define IRQ_GPIO1INTR 5 /* GPIO External IRQ Interrupt on F1 */
37# define IRQ_GPIO2INTR 6 /* GPIO External IRQ Interrupt on F2 */
38# define IRQ_GPIO3INTR 7 /* GPIO External IRQ Interrupt on F3 */
39# define IRQ_T1UI 8 /* Timer 1 underflow */
40# define IRQ_T2UI 9 /* Timer 2 underflow */
41# define IRQ_RTCMI 10
42# define IRQ_TINTR 11 /* Clock State Controller 64 Hz tick (CSC) */
43# define IRQ_UART1INTR 12
44# define IRQ_UART2INTR 13
45# define IRQ_LCDINTR 14
46# define IRQ_SSIEOT 15 /* Synchronous Serial Interface (SSI) */
47# define IRQ_UART3INTR 16
48# define IRQ_SCIINTR 17 /* Smart Card Interface (SCI) */
49# define IRQ_AACINTR 18 /* Advanced Audio Codec (AAC) */
50# define IRQ_MMCINTR 19 /* Multimedia Card (MMC) */
51# define IRQ_USBINTR 20
52# define IRQ_DMAINTR 21
53# define IRQ_T3UI 22 /* Timer 3 underflow */
54# define IRQ_GPIO4INTR 23 /* GPIO External IRQ Interrupt on F4 */
55# define IRQ_GPIO5INTR 24 /* GPIO External IRQ Interrupt on F5 */
56# define IRQ_GPIO6INTR 25 /* GPIO External IRQ Interrupt on F6 */
57# define IRQ_GPIO7INTR 26 /* GPIO External IRQ Interrupt on F7 */
58# define IRQ_BMIINTR 27 /* Battery Monitor Interface (BMI) */
59
60# define NR_IRQ_CPU 28 /* IRQs directly recognized by CPU */
61
62 /* Given IRQ, return GPIO interrupt number 0-7 */
63# define IRQ_TO_GPIO(i) ((i) \
64 - (((i) > IRQ_GPIO3INTR) ? IRQ_GPIO4INTR - IRQ_GPIO3INTR - 1 : 0)\
65 - (((i) > IRQ_GPIO0INTR) ? IRQ_GPIO1INTR - IRQ_GPIO0INTR - 1 : 0))
66
67#endif
68
69#if defined (CONFIG_ARCH_LH7A404)
70
71# define IRQ_BROWN 0 /* Brownout */
72# define IRQ_WDTINTR 1 /* Watchdog Timer */
73# define IRQ_COMMRX 2 /* ARM Comm Rx for Debug */
74# define IRQ_COMMTX 3 /* ARM Comm Tx for Debug */
75# define IRQ_T1UI 4 /* Timer 1 underflow */
76# define IRQ_T2UI 5 /* Timer 2 underflow */
77# define IRQ_CSINT 6 /* Codec Interrupt (shared by AAC on 404) */
78# define IRQ_DMAM2P0 7 /* -- DMA Memory to Peripheral */
79# define IRQ_DMAM2P1 8
80# define IRQ_DMAM2P2 9
81# define IRQ_DMAM2P3 10
82# define IRQ_DMAM2P4 11
83# define IRQ_DMAM2P5 12
84# define IRQ_DMAM2P6 13
85# define IRQ_DMAM2P7 14
86# define IRQ_DMAM2P8 15
87# define IRQ_DMAM2P9 16
88# define IRQ_DMAM2M0 17 /* -- DMA Memory to Memory */
89# define IRQ_DMAM2M1 18
90# define IRQ_GPIO0INTR 19 /* -- GPIOF Interrupt */
91# define IRQ_GPIO1INTR 20
92# define IRQ_GPIO2INTR 21
93# define IRQ_GPIO3INTR 22
94# define IRQ_SOFT_V1_23 23 /* -- Unassigned */
95# define IRQ_SOFT_V1_24 24
96# define IRQ_SOFT_V1_25 25
97# define IRQ_SOFT_V1_26 26
98# define IRQ_SOFT_V1_27 27
99# define IRQ_SOFT_V1_28 28
100# define IRQ_SOFT_V1_29 29
101# define IRQ_SOFT_V1_30 30
102# define IRQ_SOFT_V1_31 31
103
104# define IRQ_BLINT 32 /* Battery Low */
105# define IRQ_BMIINTR 33 /* Battery Monitor */
106# define IRQ_MCINTR 34 /* Media Change */
107# define IRQ_TINTR 35 /* 64Hz Tick */
108# define IRQ_WEINT 36 /* Watchdog Expired */
109# define IRQ_RTCMI 37 /* Real-time Clock Match */
110# define IRQ_UART1INTR 38 /* UART1 Interrupt (including error) */
111# define IRQ_UART1ERR 39 /* UART1 Error */
112# define IRQ_UART2INTR 40 /* UART2 Interrupt (including error) */
113# define IRQ_UART2ERR 41 /* UART2 Error */
114# define IRQ_UART3INTR 42 /* UART3 Interrupt (including error) */
115# define IRQ_UART3ERR 43 /* UART3 Error */
116# define IRQ_SCIINTR 44 /* Smart Card */
117# define IRQ_TSCINTR 45 /* Touchscreen */
118# define IRQ_KMIINTR 46 /* Keyboard/Mouse (PS/2) */
119# define IRQ_GPIO4INTR 47 /* -- GPIOF Interrupt */
120# define IRQ_GPIO5INTR 48
121# define IRQ_GPIO6INTR 49
122# define IRQ_GPIO7INTR 50
123# define IRQ_T3UI 51 /* Timer 3 underflow */
124# define IRQ_LCDINTR 52 /* LCD Controller */
125# define IRQ_SSPINTR 53 /* Synchronous Serial Port */
126# define IRQ_SDINTR 54 /* Secure Digital Port (MMC) */
127# define IRQ_USBINTR 55 /* USB Device Port */
128# define IRQ_USHINTR 56 /* USB Host Port */
129# define IRQ_SOFT_V2_25 57 /* -- Unassigned */
130# define IRQ_SOFT_V2_26 58
131# define IRQ_SOFT_V2_27 59
132# define IRQ_SOFT_V2_28 60
133# define IRQ_SOFT_V2_29 61
134# define IRQ_SOFT_V2_30 62
135# define IRQ_SOFT_V2_31 63
136
137# define NR_IRQ_CPU 64 /* IRQs directly recognized by CPU */
138
139 /* Given IRQ, return GPIO interrupt number 0-7 */
140# define IRQ_TO_GPIO(i) ((i) \
141 - (((i) > IRQ_GPIO3INTR) ? IRQ_GPIO4INTR - IRQ_GPIO3INTR - 1 : 0)\
142 - IRQ_GPIO0INTR)
143
144 /* Vector Address constants */
145# define VA_VECTORED 0x100 /* Set for vectored interrupt */
146# define VA_VIC1DEFAULT 0x200 /* Set as default VECTADDR for VIC1 */
147# define VA_VIC2DEFAULT 0x400 /* Set as default VECTADDR for VIC2 */
148
149#endif
150
151 /* IRQ aliases */
152
153#if !defined (IRQ_GPIO0INTR)
154# define IRQ_GPIO0INTR IRQ_GPIO0FIQ
155#endif
156#define IRQ_TICK IRQ_TINTR
157#define IRQ_PCC1_RDY IRQ_GPIO6INTR /* PCCard 1 ready */
158#define IRQ_PCC2_RDY IRQ_GPIO7INTR /* PCCard 2 ready */
159#define IRQ_USB IRQ_USBINTR /* USB device */
160
161#ifdef CONFIG_MACH_KEV7A400
162# define IRQ_TS IRQ_GPIOFIQ /* Touchscreen */
163# define IRQ_CPLD IRQ_GPIO1INTR /* CPLD cascade */
164# define IRQ_PCC1_CD IRQ_GPIO_F2 /* PCCard 1 card detect */
165# define IRQ_PCC2_CD IRQ_GPIO_F3 /* PCCard 2 card detect */
166#endif
167
168#if defined (CONFIG_MACH_LPD7A400) || defined (CONFIG_MACH_LPD7A404)
169# define IRQ_CPLD_V28 IRQ_GPIO7INTR /* CPLD cascade through GPIO_PF7 */
170# define IRQ_CPLD_V34 IRQ_GPIO3INTR /* CPLD cascade through GPIO_PF3 */
171#endif
172
173 /* System specific IRQs */
174
175#define IRQ_BOARD_START NR_IRQ_CPU
176
177#ifdef CONFIG_MACH_KEV7A400
178# define IRQ_KEV7A400_CPLD IRQ_BOARD_START
179# define NR_IRQ_BOARD 5
180# define IRQ_KEV7A400_MMC_CD IRQ_KEV7A400_CPLD + 0 /* MMC Card Detect */
181# define IRQ_KEV7A400_RI2 IRQ_KEV7A400_CPLD + 1 /* Ring Indicator 2 */
182# define IRQ_KEV7A400_IDE_CF IRQ_KEV7A400_CPLD + 2 /* Compact Flash (?) */
183# define IRQ_KEV7A400_ETH_INT IRQ_KEV7A400_CPLD + 3 /* Ethernet chip */
184# define IRQ_KEV7A400_INT IRQ_KEV7A400_CPLD + 4
185#endif
186
187#if defined (CONFIG_MACH_LPD7A400) || defined (CONFIG_MACH_LPD7A404)
188# define IRQ_LPD7A40X_CPLD IRQ_BOARD_START
189# define NR_IRQ_BOARD 2
190# define IRQ_LPD7A40X_ETH_INT IRQ_LPD7A40X_CPLD + 0 /* Ethernet chip */
191# define IRQ_LPD7A400_TS IRQ_LPD7A40X_CPLD + 1 /* Touch screen */
192#endif
193
194#if defined (CONFIG_MACH_LPD7A400)
195# define IRQ_TOUCH IRQ_LPD7A400_TS
196#endif
197
198#define NR_IRQS (NR_IRQ_CPU + NR_IRQ_BOARD)
199
200#endif
diff --git a/arch/arm/mach-lh7a40x/include/mach/memory.h b/arch/arm/mach-lh7a40x/include/mach/memory.h
deleted file mode 100644
index f77bde80fe41..000000000000
--- a/arch/arm/mach-lh7a40x/include/mach/memory.h
+++ /dev/null
@@ -1,28 +0,0 @@
1/* arch/arm/mach-lh7a40x/include/mach/memory.h
2 *
3 * Copyright (C) 2004 Coastal Environmental Systems
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * version 2 as published by the Free Software Foundation.
8 *
9 *
10 * Refer to <file:Documentation/arm/Sharp-LH/SDRAM> for more information.
11 *
12 */
13
14#ifndef __ASM_ARCH_MEMORY_H
15#define __ASM_ARCH_MEMORY_H
16
17/*
18 * Physical DRAM offset.
19 */
20#define PLAT_PHYS_OFFSET UL(0xc0000000)
21
22/*
23 * Sparsemem version of the above
24 */
25#define MAX_PHYSMEM_BITS 32
26#define SECTION_SIZE_BITS 24
27
28#endif
diff --git a/arch/arm/mach-lh7a40x/include/mach/registers.h b/arch/arm/mach-lh7a40x/include/mach/registers.h
deleted file mode 100644
index ea44396383a7..000000000000
--- a/arch/arm/mach-lh7a40x/include/mach/registers.h
+++ /dev/null
@@ -1,224 +0,0 @@
1/* arch/arm/mach-lh7a40x/include/mach/registers.h
2 *
3 * Copyright (C) 2004 Coastal Environmental Systems
4 * Copyright (C) 2004 Logic Product Development
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * version 2 as published by the Free Software Foundation.
9 *
10 */
11
12#include <mach/constants.h>
13
14#ifndef __ASM_ARCH_REGISTERS_H
15#define __ASM_ARCH_REGISTERS_H
16
17
18 /* Physical register base addresses */
19
20#define AC97C_PHYS (0x80000000) /* AC97 Controller */
21#define MMC_PHYS (0x80000100) /* Multimedia Card Controller */
22#define USB_PHYS (0x80000200) /* USB Client */
23#define SCI_PHYS (0x80000300) /* Secure Card Interface */
24#define CSC_PHYS (0x80000400) /* Clock/State Controller */
25#define INTC_PHYS (0x80000500) /* Interrupt Controller */
26#define UART1_PHYS (0x80000600) /* UART1 Controller */
27#define SIR_PHYS (0x80000600) /* IR Controller, same are UART1 */
28#define UART2_PHYS (0x80000700) /* UART2 Controller */
29#define UART3_PHYS (0x80000800) /* UART3 Controller */
30#define DCDC_PHYS (0x80000900) /* DC to DC Controller */
31#define ACI_PHYS (0x80000a00) /* Audio Codec Interface */
32#define SSP_PHYS (0x80000b00) /* Synchronous ... */
33#define TIMER_PHYS (0x80000c00) /* Timer Controller */
34#define RTC_PHYS (0x80000d00) /* Real-time Clock */
35#define GPIO_PHYS (0x80000e00) /* General Purpose IO */
36#define BMI_PHYS (0x80000f00) /* Battery Monitor Interface */
37#define HRTFTC_PHYS (0x80001000) /* High-res TFT Controller (LH7A400) */
38#define ALI_PHYS (0x80001000) /* Advanced LCD Interface (LH7A404) */
39#define WDT_PHYS (0x80001400) /* Watchdog Timer */
40#define SMC_PHYS (0x80002000) /* Static Memory Controller */
41#define SDRC_PHYS (0x80002400) /* SDRAM Controller */
42#define DMAC_PHYS (0x80002800) /* DMA Controller */
43#define CLCDC_PHYS (0x80003000) /* Color LCD Controller */
44
45 /* Physical registers of the LH7A404 */
46
47#define ADC_PHYS (0x80001300) /* A/D & Touchscreen Controller */
48#define VIC1_PHYS (0x80008000) /* Vectored Interrupt Controller 1 */
49#define USBH_PHYS (0x80009000) /* USB OHCI host controller */
50#define VIC2_PHYS (0x8000a000) /* Vectored Interrupt Controller 2 */
51
52/*#define KBD_PHYS (0x80000e00) */
53/*#define LCDICP_PHYS (0x80001000) */
54
55
56 /* Clock/State Controller register */
57
58#define CSC_PWRSR __REG(CSC_PHYS + 0x00) /* Reset register & ID */
59#define CSC_PWRCNT __REG(CSC_PHYS + 0x04) /* Power control */
60#define CSC_CLKSET __REG(CSC_PHYS + 0x20) /* Clock speed control */
61#define CSC_USBDRESET __REG(CSC_PHYS + 0x4c) /* USB Device resets */
62
63#define CSC_PWRCNT_USBH_EN (1<<28) /* USB Host power enable */
64#define CSC_PWRCNT_DMAC_M2M1_EN (1<<27)
65#define CSC_PWRCNT_DMAC_M2M0_EN (1<<26)
66#define CSC_PWRCNT_DMAC_M2P8_EN (1<<25)
67#define CSC_PWRCNT_DMAC_M2P9_EN (1<<24)
68#define CSC_PWRCNT_DMAC_M2P6_EN (1<<23)
69#define CSC_PWRCNT_DMAC_M2P7_EN (1<<22)
70#define CSC_PWRCNT_DMAC_M2P4_EN (1<<21)
71#define CSC_PWRCNT_DMAC_M2P5_EN (1<<20)
72#define CSC_PWRCNT_DMAC_M2P2_EN (1<<19)
73#define CSC_PWRCNT_DMAC_M2P3_EN (1<<18)
74#define CSC_PWRCNT_DMAC_M2P0_EN (1<<17)
75#define CSC_PWRCNT_DMAC_M2P1_EN (1<<16)
76
77#define CSC_PWRSR_CHIPMAN_SHIFT (24)
78#define CSC_PWRSR_CHIPMAN_MASK (0xff)
79#define CSC_PWRSR_CHIPID_SHIFT (16)
80#define CSC_PWRSR_CHIPID_MASK (0xff)
81
82#define CSC_USBDRESET_APBRESETREG (1<<1)
83#define CSC_USBDRESET_IORESETREG (1<<0)
84
85 /* Interrupt Controller registers */
86
87#define INTC_INTSR __REG(INTC_PHYS + 0x00) /* Status */
88#define INTC_INTRSR __REG(INTC_PHYS + 0x04) /* Raw Status */
89#define INTC_INTENS __REG(INTC_PHYS + 0x08) /* Enable Set */
90#define INTC_INTENC __REG(INTC_PHYS + 0x0c) /* Enable Clear */
91
92
93 /* Vectored Interrupted Controller registers */
94
95#define VIC1_IRQSTATUS __REG(VIC1_PHYS + 0x00)
96#define VIC1_FIQSTATUS __REG(VIC1_PHYS + 0x04)
97#define VIC1_RAWINTR __REG(VIC1_PHYS + 0x08)
98#define VIC1_INTSEL __REG(VIC1_PHYS + 0x0c)
99#define VIC1_INTEN __REG(VIC1_PHYS + 0x10)
100#define VIC1_INTENCLR __REG(VIC1_PHYS + 0x14)
101#define VIC1_SOFTINT __REG(VIC1_PHYS + 0x18)
102#define VIC1_SOFTINTCLR __REG(VIC1_PHYS + 0x1c)
103#define VIC1_PROTECT __REG(VIC1_PHYS + 0x20)
104#define VIC1_VECTADDR __REG(VIC1_PHYS + 0x30)
105#define VIC1_NVADDR __REG(VIC1_PHYS + 0x34)
106#define VIC1_VAD0 __REG(VIC1_PHYS + 0x100)
107#define VIC1_VECTCNTL0 __REG(VIC1_PHYS + 0x200)
108#define VIC2_IRQSTATUS __REG(VIC2_PHYS + 0x00)
109#define VIC2_FIQSTATUS __REG(VIC2_PHYS + 0x04)
110#define VIC2_RAWINTR __REG(VIC2_PHYS + 0x08)
111#define VIC2_INTSEL __REG(VIC2_PHYS + 0x0c)
112#define VIC2_INTEN __REG(VIC2_PHYS + 0x10)
113#define VIC2_INTENCLR __REG(VIC2_PHYS + 0x14)
114#define VIC2_SOFTINT __REG(VIC2_PHYS + 0x18)
115#define VIC2_SOFTINTCLR __REG(VIC2_PHYS + 0x1c)
116#define VIC2_PROTECT __REG(VIC2_PHYS + 0x20)
117#define VIC2_VECTADDR __REG(VIC2_PHYS + 0x30)
118#define VIC2_NVADDR __REG(VIC2_PHYS + 0x34)
119#define VIC2_VAD0 __REG(VIC2_PHYS + 0x100)
120#define VIC2_VECTCNTL0 __REG(VIC2_PHYS + 0x200)
121
122#define VIC_CNTL_ENABLE (0x20)
123
124 /* USB Host registers (Open HCI compatible) */
125
126#define USBH_CMDSTATUS __REG(USBH_PHYS + 0x08)
127
128
129 /* GPIO registers */
130
131#define GPIO_INTTYPE1 __REG(GPIO_PHYS + 0x4c) /* Interrupt Type 1 (Edge) */
132#define GPIO_INTTYPE2 __REG(GPIO_PHYS + 0x50) /* Interrupt Type 2 */
133#define GPIO_GPIOFEOI __REG(GPIO_PHYS + 0x54) /* GPIO End-of-Interrupt */
134#define GPIO_GPIOINTEN __REG(GPIO_PHYS + 0x58) /* GPIO Interrupt Enable */
135#define GPIO_INTSTATUS __REG(GPIO_PHYS + 0x5c) /* GPIO Interrupt Status */
136#define GPIO_PINMUX __REG(GPIO_PHYS + 0x2c)
137#define GPIO_PADD __REG(GPIO_PHYS + 0x10)
138#define GPIO_PAD __REG(GPIO_PHYS + 0x00)
139#define GPIO_PCD __REG(GPIO_PHYS + 0x08)
140#define GPIO_PCDD __REG(GPIO_PHYS + 0x18)
141#define GPIO_PEDD __REG(GPIO_PHYS + 0x24)
142#define GPIO_PED __REG(GPIO_PHYS + 0x20)
143
144
145 /* Static Memory Controller registers */
146
147#define SMC_BCR0 __REG(SMC_PHYS + 0x00) /* Bank 0 Configuration */
148#define SMC_BCR1 __REG(SMC_PHYS + 0x04) /* Bank 1 Configuration */
149#define SMC_BCR2 __REG(SMC_PHYS + 0x08) /* Bank 2 Configuration */
150#define SMC_BCR3 __REG(SMC_PHYS + 0x0C) /* Bank 3 Configuration */
151#define SMC_BCR6 __REG(SMC_PHYS + 0x18) /* Bank 6 Configuration */
152#define SMC_BCR7 __REG(SMC_PHYS + 0x1c) /* Bank 7 Configuration */
153
154
155#ifdef CONFIG_MACH_KEV7A400
156# define CPLD_RD_OPT_DIP_SW __REG16(CPLD_PHYS + 0x00) /* Read Option SW */
157# define CPLD_WR_IO_BRD_CTL __REG16(CPLD_PHYS + 0x00) /* Write Control */
158# define CPLD_RD_PB_KEYS __REG16(CPLD_PHYS + 0x02) /* Read Btn Keys */
159# define CPLD_LATCHED_INTS __REG16(CPLD_PHYS + 0x04) /* Read INTR stat. */
160# define CPLD_CL_INT __REG16(CPLD_PHYS + 0x04) /* Clear INTR stat */
161# define CPLD_BOOT_MMC_STATUS __REG16(CPLD_PHYS + 0x06) /* R/O */
162# define CPLD_RD_KPD_ROW_SENSE __REG16(CPLD_PHYS + 0x08)
163# define CPLD_WR_PB_INT_MASK __REG16(CPLD_PHYS + 0x08)
164# define CPLD_RD_BRD_DISP_SW __REG16(CPLD_PHYS + 0x0a)
165# define CPLD_WR_EXT_INT_MASK __REG16(CPLD_PHYS + 0x0a)
166# define CPLD_LCD_PWR_CNTL __REG16(CPLD_PHYS + 0x0c)
167# define CPLD_SEVEN_SEG __REG16(CPLD_PHYS + 0x0e) /* 7 seg. LED mask */
168
169#endif
170
171#if defined (CONFIG_MACH_LPD7A400) || defined (CONFIG_MACH_LPD7A404)
172
173# define CPLD_CONTROL __REG16(CPLD02_PHYS)
174# define CPLD_SPI_DATA __REG16(CPLD06_PHYS)
175# define CPLD_SPI_CONTROL __REG16(CPLD08_PHYS)
176# define CPLD_SPI_EEPROM __REG16(CPLD0A_PHYS)
177# define CPLD_INTERRUPTS __REG16(CPLD0C_PHYS) /* IRQ mask/status */
178# define CPLD_BOOT_MODE __REG16(CPLD0E_PHYS)
179# define CPLD_FLASH __REG16(CPLD10_PHYS)
180# define CPLD_POWER_MGMT __REG16(CPLD12_PHYS)
181# define CPLD_REVISION __REG16(CPLD14_PHYS)
182# define CPLD_GPIO_EXT __REG16(CPLD16_PHYS)
183# define CPLD_GPIO_DATA __REG16(CPLD18_PHYS)
184# define CPLD_GPIO_DIR __REG16(CPLD1A_PHYS)
185
186#endif
187
188 /* Timer registers */
189
190#define TIMER_LOAD1 __REG(TIMER_PHYS + 0x00) /* Timer 1 initial value */
191#define TIMER_VALUE1 __REG(TIMER_PHYS + 0x04) /* Timer 1 current value */
192#define TIMER_CONTROL1 __REG(TIMER_PHYS + 0x08) /* Timer 1 control word */
193#define TIMER_EOI1 __REG(TIMER_PHYS + 0x0c) /* Timer 1 interrupt clear */
194
195#define TIMER_LOAD2 __REG(TIMER_PHYS + 0x20) /* Timer 2 initial value */
196#define TIMER_VALUE2 __REG(TIMER_PHYS + 0x24) /* Timer 2 current value */
197#define TIMER_CONTROL2 __REG(TIMER_PHYS + 0x28) /* Timer 2 control word */
198#define TIMER_EOI2 __REG(TIMER_PHYS + 0x2c) /* Timer 2 interrupt clear */
199
200#define TIMER_BUZZCON __REG(TIMER_PHYS + 0x40) /* Buzzer configuration */
201
202#define TIMER_LOAD3 __REG(TIMER_PHYS + 0x80) /* Timer 3 initial value */
203#define TIMER_VALUE3 __REG(TIMER_PHYS + 0x84) /* Timer 3 current value */
204#define TIMER_CONTROL3 __REG(TIMER_PHYS + 0x88) /* Timer 3 control word */
205#define TIMER_EOI3 __REG(TIMER_PHYS + 0x8c) /* Timer 3 interrupt clear */
206
207#define TIMER_C_ENABLE (1<<7)
208#define TIMER_C_PERIODIC (1<<6)
209#define TIMER_C_FREERUNNING (0)
210#define TIMER_C_2KHZ (0x00) /* 1.986 kHz */
211#define TIMER_C_508KHZ (0x08)
212
213 /* GPIO registers */
214
215#define GPIO_PFDD __REG(GPIO_PHYS + 0x34) /* PF direction */
216#define GPIO_INTTYPE1 __REG(GPIO_PHYS + 0x4c) /* IRQ edge or lvl */
217#define GPIO_INTTYPE2 __REG(GPIO_PHYS + 0x50) /* IRQ activ hi/lo */
218#define GPIO_GPIOFEOI __REG(GPIO_PHYS + 0x54) /* GPIOF end of IRQ */
219#define GPIO_GPIOFINTEN __REG(GPIO_PHYS + 0x58) /* GPIOF IRQ enable */
220#define GPIO_INTSTATUS __REG(GPIO_PHYS + 0x5c) /* GPIOF IRQ latch */
221#define GPIO_RAWINTSTATUS __REG(GPIO_PHYS + 0x60) /* GPIOF IRQ raw */
222
223
224#endif /* _ASM_ARCH_REGISTERS_H */
diff --git a/arch/arm/mach-lh7a40x/include/mach/ssp.h b/arch/arm/mach-lh7a40x/include/mach/ssp.h
deleted file mode 100644
index 509916182e34..000000000000
--- a/arch/arm/mach-lh7a40x/include/mach/ssp.h
+++ /dev/null
@@ -1,70 +0,0 @@
1/* ssp.h
2
3 written by Marc Singer
4 6 Dec 2004
5
6 Copyright (C) 2004 Marc Singer
7
8 -----------
9 DESCRIPTION
10 -----------
11
12 This SSP header is available throughout the kernel, for this
13 machine/architecture, because drivers that use it may be dispersed.
14
15 This file was cloned from the 7952x implementation. It would be
16 better to share them, but we're taking an easier approach for the
17 time being.
18
19*/
20
21#if !defined (__SSP_H__)
22# define __SSP_H__
23
24/* ----- Includes */
25
26/* ----- Types */
27
28struct ssp_driver {
29 int (*init) (void);
30 void (*exit) (void);
31 void (*acquire) (void);
32 void (*release) (void);
33 int (*configure) (int device, int mode, int speed,
34 int frame_size_write, int frame_size_read);
35 void (*chip_select) (int enable);
36 void (*set_callbacks) (void* handle,
37 irqreturn_t (*callback_tx)(void*),
38 irqreturn_t (*callback_rx)(void*));
39 void (*enable) (void);
40 void (*disable) (void);
41// int (*save_state) (void*);
42// void (*restore_state) (void*);
43 int (*read) (void);
44 int (*write) (u16 data);
45 int (*write_read) (u16 data);
46 void (*flush) (void);
47 void (*write_async) (void* pv, size_t cb);
48 size_t (*write_pos) (void);
49};
50
51 /* These modes are only available on the LH79524 */
52#define SSP_MODE_SPI (1)
53#define SSP_MODE_SSI (2)
54#define SSP_MODE_MICROWIRE (3)
55#define SSP_MODE_I2S (4)
56
57 /* CPLD SPI devices */
58#define DEVICE_EEPROM 0 /* Configuration eeprom */
59#define DEVICE_MAC 1 /* MAC eeprom (LPD79524) */
60#define DEVICE_CODEC 2 /* Audio codec */
61#define DEVICE_TOUCH 3 /* Touch screen (LPD79520) */
62
63/* ----- Globals */
64
65/* ----- Prototypes */
66
67//extern struct ssp_driver lh79520_i2s_driver;
68extern struct ssp_driver lh7a400_cpld_ssp_driver;
69
70#endif /* __SSP_H__ */
diff --git a/arch/arm/mach-lh7a40x/include/mach/system.h b/arch/arm/mach-lh7a40x/include/mach/system.h
deleted file mode 100644
index 45a56d3b93d7..000000000000
--- a/arch/arm/mach-lh7a40x/include/mach/system.h
+++ /dev/null
@@ -1,19 +0,0 @@
1/* arch/arm/mach-lh7a40x/include/mach/system.h
2 *
3 * Copyright (C) 2004 Coastal Environmental Systems
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * version 2 as published by the Free Software Foundation.
8 *
9 */
10
11static inline void arch_idle(void)
12{
13 cpu_do_idle ();
14}
15
16static inline void arch_reset(char mode, const char *cmd)
17{
18 cpu_reset (0);
19}
diff --git a/arch/arm/mach-lh7a40x/include/mach/timex.h b/arch/arm/mach-lh7a40x/include/mach/timex.h
deleted file mode 100644
index 08028cef1b3b..000000000000
--- a/arch/arm/mach-lh7a40x/include/mach/timex.h
+++ /dev/null
@@ -1,17 +0,0 @@
1/* arch/arm/mach-lh7a40x/include/mach/timex.h
2 *
3 * Copyright (C) 2004 Coastal Environmental Systems
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * version 2 as published by the Free Software Foundation.
8 *
9 */
10
11#include <mach/constants.h>
12
13#define CLOCK_TICK_RATE (PLL_CLOCK/6/16)
14
15/*
16#define CLOCK_TICK_RATE 3686400
17*/
diff --git a/arch/arm/mach-lh7a40x/include/mach/uncompress.h b/arch/arm/mach-lh7a40x/include/mach/uncompress.h
deleted file mode 100644
index 55b80d479eb4..000000000000
--- a/arch/arm/mach-lh7a40x/include/mach/uncompress.h
+++ /dev/null
@@ -1,38 +0,0 @@
1/* arch/arm/mach-lh7a40x/include/mach/uncompress.h
2 *
3 * Copyright (C) 2004 Coastal Environmental Systems
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * version 2 as published by the Free Software Foundation.
8 *
9 */
10
11#include <mach/registers.h>
12
13#ifndef UART_R_DATA
14# define UART_R_DATA (0x00)
15#endif
16#ifndef UART_R_STATUS
17# define UART_R_STATUS (0x10)
18#endif
19#define nTxRdy (0x20) /* Not TxReady (literally Tx FIFO full) */
20
21 /* Access UART with physical addresses before MMU is setup */
22#define UART_STATUS (*(volatile unsigned long*) (UART2_PHYS + UART_R_STATUS))
23#define UART_DATA (*(volatile unsigned long*) (UART2_PHYS + UART_R_DATA))
24
25static inline void putc(int ch)
26{
27 while (UART_STATUS & nTxRdy)
28 barrier();
29 UART_DATA = ch;
30}
31
32static inline void flush(void)
33{
34}
35
36 /* NULL functions; we don't presently need them */
37#define arch_decomp_setup()
38#define arch_decomp_wdog()
diff --git a/arch/arm/mach-lh7a40x/include/mach/vmalloc.h b/arch/arm/mach-lh7a40x/include/mach/vmalloc.h
deleted file mode 100644
index d62da7358b16..000000000000
--- a/arch/arm/mach-lh7a40x/include/mach/vmalloc.h
+++ /dev/null
@@ -1,10 +0,0 @@
1/* arch/arm/mach-lh7a40x/include/mach/vmalloc.h
2 *
3 * Copyright (C) 2004 Coastal Environmental Systems
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * version 2 as published by the Free Software Foundation.
8 *
9 */
10#define VMALLOC_END (0xe8000000UL)
diff --git a/arch/arm/mach-lh7a40x/irq-kev7a400.c b/arch/arm/mach-lh7a40x/irq-kev7a400.c
deleted file mode 100644
index c7433b3c5812..000000000000
--- a/arch/arm/mach-lh7a40x/irq-kev7a400.c
+++ /dev/null
@@ -1,93 +0,0 @@
1/* arch/arm/mach-lh7a40x/irq-kev7a400.c
2 *
3 * Copyright (C) 2004 Coastal Environmental Systems
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * version 2 as published by the Free Software Foundation.
8 *
9 */
10
11#include <linux/interrupt.h>
12#include <linux/init.h>
13
14#include <asm/irq.h>
15#include <asm/mach/irq.h>
16#include <asm/mach/hardware.h>
17#include <asm/mach/irqs.h>
18
19#include "common.h"
20
21 /* KEV7a400 CPLD IRQ handling */
22
23static u16 CPLD_IRQ_mask; /* Mask for CPLD IRQs, 1 == unmasked */
24
25static void
26lh7a400_ack_cpld_irq (u32 irq)
27{
28 CPLD_CL_INT = 1 << (irq - IRQ_KEV7A400_CPLD);
29}
30
31static void
32lh7a400_mask_cpld_irq (u32 irq)
33{
34 CPLD_IRQ_mask &= ~(1 << (irq - IRQ_KEV7A400_CPLD));
35 CPLD_WR_PB_INT_MASK = CPLD_IRQ_mask;
36}
37
38static void
39lh7a400_unmask_cpld_irq (u32 irq)
40{
41 CPLD_IRQ_mask |= 1 << (irq - IRQ_KEV7A400_CPLD);
42 CPLD_WR_PB_INT_MASK = CPLD_IRQ_mask;
43}
44
45static struct
46irq_chip lh7a400_cpld_chip = {
47 .name = "CPLD",
48 .ack = lh7a400_ack_cpld_irq,
49 .mask = lh7a400_mask_cpld_irq,
50 .unmask = lh7a400_unmask_cpld_irq,
51};
52
53static void
54lh7a400_cpld_handler (unsigned int irq, struct irq_desc *desc)
55{
56 u32 mask = CPLD_LATCHED_INTS;
57 irq = IRQ_KEV_7A400_CPLD;
58 for (; mask; mask >>= 1, ++irq) {
59 if (mask & 1)
60 desc[irq].handle (irq, desc);
61 }
62}
63
64 /* IRQ initialization */
65
66void __init
67lh7a400_init_board_irq (void)
68{
69 int irq;
70
71 for (irq = IRQ_KEV7A400_CPLD;
72 irq < IRQ_KEV7A400_CPLD + NR_IRQ_KEV7A400_CPLD; ++irq) {
73 set_irq_chip (irq, &lh7a400_cpld_chip);
74 set_irq_handler (irq, handle_edge_irq);
75 set_irq_flags (irq, IRQF_VALID);
76 }
77 set_irq_chained_handler (IRQ_CPLD, kev7a400_cpld_handler);
78
79 /* Clear all CPLD interrupts */
80 CPLD_CL_INT = 0xff; /* CPLD_INTR_MMC_CD | CPLD_INTR_ETH_INT; */
81
82 /* *** FIXME CF enabled in ide-probe.c */
83
84 GPIO_GPIOINTEN = 0; /* Disable all GPIO interrupts */
85 barrier();
86 GPIO_INTTYPE1
87 = (GPIO_INTR_PCC1_CD | GPIO_INTR_PCC1_CD); /* Edge trig. */
88 GPIO_INTTYPE2 = 0; /* Falling edge & low-level */
89 GPIO_GPIOFEOI = 0xff; /* Clear all GPIO interrupts */
90 GPIO_GPIOINTEN = 0xff; /* Enable all GPIO interrupts */
91
92 init_FIQ();
93}
diff --git a/arch/arm/mach-lh7a40x/irq-lh7a400.c b/arch/arm/mach-lh7a40x/irq-lh7a400.c
deleted file mode 100644
index f2e7e655ca35..000000000000
--- a/arch/arm/mach-lh7a40x/irq-lh7a400.c
+++ /dev/null
@@ -1,91 +0,0 @@
1/* arch/arm/mach-lh7a40x/irq-lh7a400.c
2 *
3 * Copyright (C) 2004 Coastal Environmental Systems
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * version 2 as published by the Free Software Foundation.
8 *
9 */
10
11#include <linux/init.h>
12#include <linux/module.h>
13#include <linux/interrupt.h>
14
15#include <mach/hardware.h>
16#include <asm/irq.h>
17#include <asm/mach/irq.h>
18#include <mach/irqs.h>
19
20#include "common.h"
21
22 /* CPU IRQ handling */
23
24static void lh7a400_mask_irq(struct irq_data *d)
25{
26 INTC_INTENC = (1 << d->irq);
27}
28
29static void lh7a400_unmask_irq(struct irq_data *d)
30{
31 INTC_INTENS = (1 << d->irq);
32}
33
34static void lh7a400_ack_gpio_irq(struct irq_data *d)
35{
36 GPIO_GPIOFEOI = (1 << IRQ_TO_GPIO (d->irq));
37 INTC_INTENC = (1 << d->irq);
38}
39
40static struct irq_chip lh7a400_internal_chip = {
41 .name = "MPU",
42 .irq_ack = lh7a400_mask_irq, /* Level triggering -> mask is ack */
43 .irq_mask = lh7a400_mask_irq,
44 .irq_unmask = lh7a400_unmask_irq,
45};
46
47static struct irq_chip lh7a400_gpio_chip = {
48 .name = "GPIO",
49 .irq_ack = lh7a400_ack_gpio_irq,
50 .irq_mask = lh7a400_mask_irq,
51 .irq_unmask = lh7a400_unmask_irq,
52};
53
54
55 /* IRQ initialization */
56
57void __init lh7a400_init_irq (void)
58{
59 int irq;
60
61 INTC_INTENC = 0xffffffff; /* Disable all interrupts */
62 GPIO_GPIOFINTEN = 0x00; /* Disable all GPIOF interrupts */
63 barrier ();
64
65 for (irq = 0; irq < NR_IRQS; ++irq) {
66 switch (irq) {
67 case IRQ_GPIO0INTR:
68 case IRQ_GPIO1INTR:
69 case IRQ_GPIO2INTR:
70 case IRQ_GPIO3INTR:
71 case IRQ_GPIO4INTR:
72 case IRQ_GPIO5INTR:
73 case IRQ_GPIO6INTR:
74 case IRQ_GPIO7INTR:
75 set_irq_chip (irq, &lh7a400_gpio_chip);
76 set_irq_handler (irq, handle_level_irq); /* OK default */
77 break;
78 default:
79 set_irq_chip (irq, &lh7a400_internal_chip);
80 set_irq_handler (irq, handle_level_irq);
81 }
82 set_irq_flags (irq, IRQF_VALID);
83 }
84
85 lh7a40x_init_board_irq ();
86
87/* *** FIXME: the LH7a400 does use FIQ interrupts in some cases. For
88 the time being, these are not initialized. */
89
90/* init_FIQ(); */
91}
diff --git a/arch/arm/mach-lh7a40x/irq-lh7a404.c b/arch/arm/mach-lh7a40x/irq-lh7a404.c
deleted file mode 100644
index 14b173389573..000000000000
--- a/arch/arm/mach-lh7a40x/irq-lh7a404.c
+++ /dev/null
@@ -1,175 +0,0 @@
1/* arch/arm/mach-lh7a40x/irq-lh7a404.c
2 *
3 * Copyright (C) 2004 Logic Product Development
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * version 2 as published by the Free Software Foundation.
8 *
9 */
10
11#include <linux/init.h>
12#include <linux/module.h>
13#include <linux/interrupt.h>
14
15#include <mach/hardware.h>
16#include <asm/irq.h>
17#include <asm/mach/irq.h>
18#include <mach/irqs.h>
19
20#include "common.h"
21
22#define USE_PRIORITIES
23
24/* See Documentation/arm/Sharp-LH/VectoredInterruptController for more
25 * information on using the vectored interrupt controller's
26 * prioritizing feature. */
27
28static unsigned char irq_pri_vic1[] = {
29#if defined (USE_PRIORITIES)
30 IRQ_GPIO3INTR, /* CPLD */
31 IRQ_DMAM2P4, IRQ_DMAM2P5, /* AC97 */
32#endif
33};
34static unsigned char irq_pri_vic2[] = {
35#if defined (USE_PRIORITIES)
36 IRQ_T3UI, /* Timer */
37 IRQ_GPIO7INTR, /* CPLD */
38 IRQ_UART1INTR, IRQ_UART2INTR, IRQ_UART3INTR,
39 IRQ_LCDINTR, /* LCD */
40 IRQ_TSCINTR, /* ADC/Touchscreen */
41#endif
42};
43
44 /* CPU IRQ handling */
45
46static void lh7a404_vic1_mask_irq(struct irq_data *d)
47{
48 VIC1_INTENCLR = (1 << d->irq);
49}
50
51static void lh7a404_vic1_unmask_irq(struct irq_data *d)
52{
53 VIC1_INTEN = (1 << d->irq);
54}
55
56static void lh7a404_vic2_mask_irq(struct irq_data *d)
57{
58 VIC2_INTENCLR = (1 << (d->irq - 32));
59}
60
61static void lh7a404_vic2_unmask_irq(struct irq_data *d)
62{
63 VIC2_INTEN = (1 << (d->irq - 32));
64}
65
66static void lh7a404_vic1_ack_gpio_irq(struct irq_data *d)
67{
68 GPIO_GPIOFEOI = (1 << IRQ_TO_GPIO (d->irq));
69 VIC1_INTENCLR = (1 << d->irq);
70}
71
72static void lh7a404_vic2_ack_gpio_irq(struct irq_data *d)
73{
74 GPIO_GPIOFEOI = (1 << IRQ_TO_GPIO (d->irq));
75 VIC2_INTENCLR = (1 << d->irq);
76}
77
78static struct irq_chip lh7a404_vic1_chip = {
79 .name = "VIC1",
80 .irq_ack = lh7a404_vic1_mask_irq, /* Because level-triggered */
81 .irq_mask = lh7a404_vic1_mask_irq,
82 .irq_unmask = lh7a404_vic1_unmask_irq,
83};
84
85static struct irq_chip lh7a404_vic2_chip = {
86 .name = "VIC2",
87 .irq_ack = lh7a404_vic2_mask_irq, /* Because level-triggered */
88 .irq_mask = lh7a404_vic2_mask_irq,
89 .irq_unmask = lh7a404_vic2_unmask_irq,
90};
91
92static struct irq_chip lh7a404_gpio_vic1_chip = {
93 .name = "GPIO-VIC1",
94 .irq_ack = lh7a404_vic1_ack_gpio_irq,
95 .irq_mask = lh7a404_vic1_mask_irq,
96 .irq_unmask = lh7a404_vic1_unmask_irq,
97};
98
99static struct irq_chip lh7a404_gpio_vic2_chip = {
100 .name = "GPIO-VIC2",
101 .irq_ack = lh7a404_vic2_ack_gpio_irq,
102 .irq_mask = lh7a404_vic2_mask_irq,
103 .irq_unmask = lh7a404_vic2_unmask_irq,
104};
105
106 /* IRQ initialization */
107
108#if defined (CONFIG_ARCH_LH7A400) && defined (CONFIG_ARCH_LH7A404)
109extern void* branch_irq_lh7a400;
110#endif
111
112void __init lh7a404_init_irq (void)
113{
114 int irq;
115
116#if defined (CONFIG_ARCH_LH7A400) && defined (CONFIG_ARCH_LH7A404)
117#define NOP 0xe1a00000 /* mov r0, r0 */
118 branch_irq_lh7a400 = NOP;
119#endif
120
121 VIC1_INTENCLR = 0xffffffff;
122 VIC2_INTENCLR = 0xffffffff;
123 VIC1_INTSEL = 0; /* All IRQs */
124 VIC2_INTSEL = 0; /* All IRQs */
125 VIC1_NVADDR = VA_VIC1DEFAULT;
126 VIC2_NVADDR = VA_VIC2DEFAULT;
127 VIC1_VECTADDR = 0;
128 VIC2_VECTADDR = 0;
129
130 GPIO_GPIOFINTEN = 0x00; /* Disable all GPIOF interrupts */
131 barrier ();
132
133 /* Install prioritized interrupts, if there are any. */
134 /* The | 0x20*/
135 for (irq = 0; irq < 16; ++irq) {
136 (&VIC1_VAD0)[irq]
137 = (irq < ARRAY_SIZE (irq_pri_vic1))
138 ? (irq_pri_vic1[irq] | VA_VECTORED) : 0;
139 (&VIC1_VECTCNTL0)[irq]
140 = (irq < ARRAY_SIZE (irq_pri_vic1))
141 ? (irq_pri_vic1[irq] | VIC_CNTL_ENABLE) : 0;
142 (&VIC2_VAD0)[irq]
143 = (irq < ARRAY_SIZE (irq_pri_vic2))
144 ? (irq_pri_vic2[irq] | VA_VECTORED) : 0;
145 (&VIC2_VECTCNTL0)[irq]
146 = (irq < ARRAY_SIZE (irq_pri_vic2))
147 ? (irq_pri_vic2[irq] | VIC_CNTL_ENABLE) : 0;
148 }
149
150 for (irq = 0; irq < NR_IRQS; ++irq) {
151 switch (irq) {
152 case IRQ_GPIO0INTR:
153 case IRQ_GPIO1INTR:
154 case IRQ_GPIO2INTR:
155 case IRQ_GPIO3INTR:
156 case IRQ_GPIO4INTR:
157 case IRQ_GPIO5INTR:
158 case IRQ_GPIO6INTR:
159 case IRQ_GPIO7INTR:
160 set_irq_chip (irq, irq < 32
161 ? &lh7a404_gpio_vic1_chip
162 : &lh7a404_gpio_vic2_chip);
163 set_irq_handler (irq, handle_level_irq); /* OK default */
164 break;
165 default:
166 set_irq_chip (irq, irq < 32
167 ? &lh7a404_vic1_chip
168 : &lh7a404_vic2_chip);
169 set_irq_handler (irq, handle_level_irq);
170 }
171 set_irq_flags (irq, IRQF_VALID);
172 }
173
174 lh7a40x_init_board_irq ();
175}
diff --git a/arch/arm/mach-lh7a40x/irq-lpd7a40x.c b/arch/arm/mach-lh7a40x/irq-lpd7a40x.c
deleted file mode 100644
index 1bfdcddcb93e..000000000000
--- a/arch/arm/mach-lh7a40x/irq-lpd7a40x.c
+++ /dev/null
@@ -1,128 +0,0 @@
1/* arch/arm/mach-lh7a40x/irq-lpd7a40x.c
2 *
3 * Copyright (C) 2004 Coastal Environmental Systems
4 * Copyright (C) 2004 Logic Product Development
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * version 2 as published by the Free Software Foundation.
9 *
10 */
11
12#include <linux/init.h>
13#include <linux/module.h>
14#include <linux/interrupt.h>
15
16#include <mach/hardware.h>
17#include <asm/irq.h>
18#include <asm/mach/irq.h>
19#include <mach/irqs.h>
20
21#include "common.h"
22
23static void lh7a40x_ack_cpld_irq(struct irq_data *d)
24{
25 /* CPLD doesn't have ack capability */
26}
27
28static void lh7a40x_mask_cpld_irq(struct irq_data *d)
29{
30 switch (d->irq) {
31 case IRQ_LPD7A40X_ETH_INT:
32 CPLD_INTERRUPTS = CPLD_INTERRUPTS | 0x4;
33 break;
34 case IRQ_LPD7A400_TS:
35 CPLD_INTERRUPTS = CPLD_INTERRUPTS | 0x8;
36 break;
37 }
38}
39
40static void lh7a40x_unmask_cpld_irq(struct irq_data *d)
41{
42 switch (d->irq) {
43 case IRQ_LPD7A40X_ETH_INT:
44 CPLD_INTERRUPTS = CPLD_INTERRUPTS & ~ 0x4;
45 break;
46 case IRQ_LPD7A400_TS:
47 CPLD_INTERRUPTS = CPLD_INTERRUPTS & ~ 0x8;
48 break;
49 }
50}
51
52static struct irq_chip lh7a40x_cpld_chip = {
53 .name = "CPLD",
54 .irq_ack = lh7a40x_ack_cpld_irq,
55 .irq_mask = lh7a40x_mask_cpld_irq,
56 .irq_unmask = lh7a40x_unmask_cpld_irq,
57};
58
59static void lh7a40x_cpld_handler (unsigned int irq, struct irq_desc *desc)
60{
61 unsigned int mask = CPLD_INTERRUPTS;
62
63 desc->irq_data.chip->ack (irq);
64
65 if ((mask & 0x1) == 0) /* WLAN */
66 generic_handle_irq(IRQ_LPD7A40X_ETH_INT);
67
68 if ((mask & 0x2) == 0) /* Touch */
69 generic_handle_irq(IRQ_LPD7A400_TS);
70
71 desc->irq_data.chip->unmask (irq); /* Level-triggered need this */
72}
73
74
75 /* IRQ initialization */
76
77void __init lh7a40x_init_board_irq (void)
78{
79 int irq;
80
81 /* Rev A (v2.8): PF0, PF1, PF2, and PF3 are available IRQs.
82 PF7 supports the CPLD.
83 Rev B (v3.4): PF0, PF1, and PF2 are available IRQs.
84 PF3 supports the CPLD.
85 (Some) LPD7A404 prerelease boards report a version
86 number of 0x16, but we force an override since the
87 hardware is of the newer variety.
88 */
89
90 unsigned char cpld_version = CPLD_REVISION;
91 int pinCPLD;
92
93#if defined CONFIG_MACH_LPD7A404
94 cpld_version = 0x34; /* Override, for now */
95#endif
96 pinCPLD = (cpld_version == 0x28) ? 7 : 3;
97
98 /* First, configure user controlled GPIOF interrupts */
99
100 GPIO_PFDD &= ~0x0f; /* PF0-3 are inputs */
101 GPIO_INTTYPE1 &= ~0x0f; /* PF0-3 are level triggered */
102 GPIO_INTTYPE2 &= ~0x0f; /* PF0-3 are active low */
103 barrier ();
104 GPIO_GPIOFINTEN |= 0x0f; /* Enable PF0, PF1, PF2, and PF3 IRQs */
105
106 /* Then, configure CPLD interrupt */
107
108 CPLD_INTERRUPTS = 0x0c; /* Disable all CPLD interrupts */
109 GPIO_PFDD &= ~(1 << pinCPLD); /* Make input */
110 GPIO_INTTYPE1 |= (1 << pinCPLD); /* Edge triggered */
111 GPIO_INTTYPE2 &= ~(1 << pinCPLD); /* Active low */
112 barrier ();
113 GPIO_GPIOFINTEN |= (1 << pinCPLD); /* Enable */
114
115 /* Cascade CPLD interrupts */
116
117 for (irq = IRQ_BOARD_START;
118 irq < IRQ_BOARD_START + NR_IRQ_BOARD; ++irq) {
119 set_irq_chip (irq, &lh7a40x_cpld_chip);
120 set_irq_handler (irq, handle_edge_irq);
121 set_irq_flags (irq, IRQF_VALID);
122 }
123
124 set_irq_chained_handler ((cpld_version == 0x28)
125 ? IRQ_CPLD_V28
126 : IRQ_CPLD_V34,
127 lh7a40x_cpld_handler);
128}
diff --git a/arch/arm/mach-lh7a40x/lcd-panel.h b/arch/arm/mach-lh7a40x/lcd-panel.h
deleted file mode 100644
index a7f5027b2f78..000000000000
--- a/arch/arm/mach-lh7a40x/lcd-panel.h
+++ /dev/null
@@ -1,345 +0,0 @@
1/* lcd-panel.h
2
3 written by Marc Singer
4 18 Jul 2005
5
6 Copyright (C) 2005 Marc Singer
7
8 -----------
9 DESCRIPTION
10 -----------
11
12 Only one panel may be defined at a time.
13
14 The pixel clock is calculated to be no greater than the target.
15
16 Each timing value is accompanied by a specification comment.
17
18 UNITS/MIN/TYP/MAX
19
20 Most of the units will be in clocks.
21
22 USE_RGB555
23
24 Define this macro to configure the AMBA LCD controller to use an
25 RGB555 encoding for the pels instead of the normal RGB565.
26
27 LPD9520, LPD79524, LPD7A400, LPD7A404-10, LPD7A404-11
28
29 These boards are best approximated by 555 for all panels. Some
30 can use an extra low-order bit of blue in bit 16 of the color
31 value, but we don't have a way to communicate this non-linear
32 mapping to the kernel.
33
34*/
35
36#if !defined (__LCD_PANEL_H__)
37# define __LCD_PANEL_H__
38
39#if defined (MACH_LPD79520)\
40 || defined (MACH_LPD79524)\
41 || defined (MACH_LPD7A400)\
42 || defined (MACH_LPD7A404)
43# define USE_RGB555
44#endif
45
46struct clcd_panel_extra {
47 unsigned int hrmode;
48 unsigned int clsen;
49 unsigned int spsen;
50 unsigned int pcdel;
51 unsigned int revdel;
52 unsigned int lpdel;
53 unsigned int spldel;
54 unsigned int pc2del;
55};
56
57#define NS_TO_CLOCK(ns,c) ((((ns)*((c)/1000) + (1000000 - 1))/1000000))
58#define CLOCK_TO_DIV(e,c) (((c) + (e) - 1)/(e))
59
60#if defined CONFIG_FB_ARMCLCD_SHARP_LQ035Q7DB02_HRTFT
61
62 /* Logic Product Development LCD 3.5" QVGA HRTFT -10 */
63 /* Sharp PN LQ035Q7DB02 w/HRTFT controller chip */
64
65#define PIX_CLOCK_TARGET (6800000)
66#define PIX_CLOCK_DIVIDER CLOCK_TO_DIV (PIX_CLOCK_TARGET, HCLK)
67#define PIX_CLOCK (HCLK/PIX_CLOCK_DIVIDER)
68
69static struct clcd_panel lcd_panel = {
70 .mode = {
71 .name = "3.5in QVGA (LQ035Q7DB02)",
72 .xres = 240,
73 .yres = 320,
74 .pixclock = PIX_CLOCK,
75 .left_margin = 16,
76 .right_margin = 21,
77 .upper_margin = 8, // line/8/8/8
78 .lower_margin = 5,
79 .hsync_len = 61,
80 .vsync_len = NS_TO_CLOCK (60, PIX_CLOCK),
81 .vmode = FB_VMODE_NONINTERLACED,
82 },
83 .width = -1,
84 .height = -1,
85 .tim2 = TIM2_IPC | (PIX_CLOCK_DIVIDER - 2),
86 .cntl = CNTL_LCDTFT | CNTL_WATERMARK,
87 .bpp = 16,
88};
89
90#define HAS_LCD_PANEL_EXTRA
91
92static struct clcd_panel_extra lcd_panel_extra = {
93 .hrmode = 1,
94 .clsen = 1,
95 .spsen = 1,
96 .pcdel = 8,
97 .revdel = 7,
98 .lpdel = 13,
99 .spldel = 77,
100 .pc2del = 208,
101};
102
103#endif
104
105#if defined CONFIG_FB_ARMCLCD_SHARP_LQ057Q3DC02
106
107 /* Logic Product Development LCD 5.7" QVGA -10 */
108 /* Sharp PN LQ057Q3DC02 */
109 /* QVGA mode, V/Q=LOW */
110
111/* From Sharp on 2006.1.3. I believe some of the values are incorrect
112 * based on the datasheet.
113
114 Timing0 TIMING1 TIMING2 CONTROL
115 0x140A0C4C 0x080504EF 0x013F380D 0x00000829
116 HBP= 20 VBP= 8 BCD= 0
117 HFP= 10 VFP= 5 CPL=319
118 HSW= 12 VSW= 1 IOE= 0
119 PPL= 19 LPP=239 IPC= 1
120 IHS= 1
121 IVS= 1
122 ACB= 0
123 CSEL= 0
124 PCD= 13
125
126 */
127
128/* The full horizontal cycle (Th) is clock/360/400/450. */
129/* The full vertical cycle (Tv) is line/251/262/280. */
130
131#define PIX_CLOCK_TARGET (6300000) /* -/6.3/7 MHz */
132#define PIX_CLOCK_DIVIDER CLOCK_TO_DIV (PIX_CLOCK_TARGET, HCLK)
133#define PIX_CLOCK (HCLK/PIX_CLOCK_DIVIDER)
134
135static struct clcd_panel lcd_panel = {
136 .mode = {
137 .name = "5.7in QVGA (LQ057Q3DC02)",
138 .xres = 320,
139 .yres = 240,
140 .pixclock = PIX_CLOCK,
141 .left_margin = 11,
142 .right_margin = 400-11-320-2,
143 .upper_margin = 7, // line/7/7/7
144 .lower_margin = 262-7-240-2,
145 .hsync_len = 2, // clk/2/96/200
146 .vsync_len = 2, // line/2/-/34
147 .vmode = FB_VMODE_NONINTERLACED,
148 },
149 .width = -1,
150 .height = -1,
151 .tim2 = TIM2_IHS | TIM2_IVS
152 | (PIX_CLOCK_DIVIDER - 2),
153 .cntl = CNTL_LCDTFT | CNTL_WATERMARK,
154 .bpp = 16,
155};
156
157#endif
158
159#if defined CONFIG_FB_ARMCLCD_SHARP_LQ64D343
160
161 /* Logic Product Development LCD 6.4" VGA -10 */
162 /* Sharp PN LQ64D343 */
163
164/* The full horizontal cycle (Th) is clock/750/800/900. */
165/* The full vertical cycle (Tv) is line/515/525/560. */
166
167#define PIX_CLOCK_TARGET (28330000)
168#define PIX_CLOCK_DIVIDER CLOCK_TO_DIV (PIX_CLOCK_TARGET, HCLK)
169#define PIX_CLOCK (HCLK/PIX_CLOCK_DIVIDER)
170
171static struct clcd_panel lcd_panel = {
172 .mode = {
173 .name = "6.4in QVGA (LQ64D343)",
174 .xres = 640,
175 .yres = 480,
176 .pixclock = PIX_CLOCK,
177 .left_margin = 32,
178 .right_margin = 800-32-640-96,
179 .upper_margin = 32, // line/34/34/34
180 .lower_margin = 540-32-480-2,
181 .hsync_len = 96, // clk/2/96/200
182 .vsync_len = 2, // line/2/-/34
183 .vmode = FB_VMODE_NONINTERLACED,
184 },
185 .width = -1,
186 .height = -1,
187 .tim2 = TIM2_IHS | TIM2_IVS
188 | (PIX_CLOCK_DIVIDER - 2),
189 .cntl = CNTL_LCDTFT | CNTL_WATERMARK,
190 .bpp = 16,
191};
192
193#endif
194
195#if defined CONFIG_FB_ARMCLCD_SHARP_LQ10D368
196
197 /* Logic Product Development LCD 10.4" VGA -10 */
198 /* Sharp PN LQ10D368 */
199
200#define PIX_CLOCK_TARGET (28330000)
201#define PIX_CLOCK_DIVIDER CLOCK_TO_DIV (PIX_CLOCK_TARGET, HCLK)
202#define PIX_CLOCK (HCLK/PIX_CLOCK_DIVIDER)
203
204static struct clcd_panel lcd_panel = {
205 .mode = {
206 .name = "10.4in VGA (LQ10D368)",
207 .xres = 640,
208 .yres = 480,
209 .pixclock = PIX_CLOCK,
210 .left_margin = 21,
211 .right_margin = 15,
212 .upper_margin = 34,
213 .lower_margin = 5,
214 .hsync_len = 96,
215 .vsync_len = 16,
216 .vmode = FB_VMODE_NONINTERLACED,
217 },
218 .width = -1,
219 .height = -1,
220 .tim2 = TIM2_IHS | TIM2_IVS
221 | (PIX_CLOCK_DIVIDER - 2),
222 .cntl = CNTL_LCDTFT | CNTL_WATERMARK,
223 .bpp = 16,
224};
225
226#endif
227
228#if defined CONFIG_FB_ARMCLCD_SHARP_LQ121S1DG41
229
230 /* Logic Product Development LCD 12.1" SVGA -10 */
231 /* Sharp PN LQ121S1DG41, was LQ121S1DG31 */
232
233/* Note that with a 99993900 Hz HCLK, it is not possible to hit the
234 * target clock frequency range of 35MHz to 42MHz. */
235
236/* If the target pixel clock is substantially lower than the panel
237 * spec, this is done to prevent the LCD display from glitching when
238 * the CPU is under load. A pixel clock higher than 25MHz
239 * (empirically determined) will compete with the CPU for bus cycles
240 * for the Ethernet chip. However, even a pixel clock of 10MHz
241 * competes with Compact Flash interface during some operations
242 * (fdisk, e2fsck). And, at that speed the display may have a visible
243 * flicker. */
244
245/* The full horizontal cycle (Th) is clock/832/1056/1395. */
246
247#define PIX_CLOCK_TARGET (20000000)
248#define PIX_CLOCK_DIVIDER CLOCK_TO_DIV (PIX_CLOCK_TARGET, HCLK)
249#define PIX_CLOCK (HCLK/PIX_CLOCK_DIVIDER)
250
251static struct clcd_panel lcd_panel = {
252 .mode = {
253 .name = "12.1in SVGA (LQ121S1DG41)",
254 .xres = 800,
255 .yres = 600,
256 .pixclock = PIX_CLOCK,
257 .left_margin = 89, // ns/5/-/(1/PIX_CLOCK)-10
258 .right_margin = 1056-800-89-128,
259 .upper_margin = 23, // line/23/23/23
260 .lower_margin = 44,
261 .hsync_len = 128, // clk/2/128/200
262 .vsync_len = 4, // line/2/4/6
263 .vmode = FB_VMODE_NONINTERLACED,
264 },
265 .width = -1,
266 .height = -1,
267 .tim2 = TIM2_IHS | TIM2_IVS
268 | (PIX_CLOCK_DIVIDER - 2),
269 .cntl = CNTL_LCDTFT | CNTL_WATERMARK,
270 .bpp = 16,
271};
272
273#endif
274
275#if defined CONFIG_FB_ARMCLCD_HITACHI
276
277 /* Hitachi*/
278 /* Submitted by Michele Da Rold <michele.darold@ecsproject.com> */
279
280#define PIX_CLOCK_TARGET (49000000)
281#define PIX_CLOCK_DIVIDER CLOCK_TO_DIV (PIX_CLOCK_TARGET, HCLK)
282#define PIX_CLOCK (HCLK/PIX_CLOCK_DIVIDER)
283
284static struct clcd_panel lcd_panel = {
285 .mode = {
286 .name = "Hitachi 800x480",
287 .xres = 800,
288 .yres = 480,
289 .pixclock = PIX_CLOCK,
290 .left_margin = 88,
291 .right_margin = 40,
292 .upper_margin = 32,
293 .lower_margin = 11,
294 .hsync_len = 128,
295 .vsync_len = 2,
296 .vmode = FB_VMODE_NONINTERLACED,
297 },
298 .width = -1,
299 .height = -1,
300 .tim2 = TIM2_IPC | TIM2_IHS | TIM2_IVS
301 | (PIX_CLOCK_DIVIDER - 2),
302 .cntl = CNTL_LCDTFT | CNTL_WATERMARK,
303 .bpp = 16,
304};
305
306#endif
307
308
309#if defined CONFIG_FB_ARMCLCD_AUO_A070VW01_WIDE
310
311 /* AU Optotronics A070VW01 7.0 Wide Screen color Display*/
312 /* Submitted by Michele Da Rold <michele.darold@ecsproject.com> */
313
314#define PIX_CLOCK_TARGET (10000000)
315#define PIX_CLOCK_DIVIDER CLOCK_TO_DIV (PIX_CLOCK_TARGET, HCLK)
316#define PIX_CLOCK (HCLK/PIX_CLOCK_DIVIDER)
317
318static struct clcd_panel lcd_panel = {
319 .mode = {
320 .name = "7.0in Wide (A070VW01)",
321 .xres = 480,
322 .yres = 234,
323 .pixclock = PIX_CLOCK,
324 .left_margin = 30,
325 .right_margin = 25,
326 .upper_margin = 14,
327 .lower_margin = 12,
328 .hsync_len = 100,
329 .vsync_len = 1,
330 .vmode = FB_VMODE_NONINTERLACED,
331 },
332 .width = -1,
333 .height = -1,
334 .tim2 = TIM2_IPC | TIM2_IHS | TIM2_IVS
335 | (PIX_CLOCK_DIVIDER - 2),
336 .cntl = CNTL_LCDTFT | CNTL_WATERMARK,
337 .bpp = 16,
338};
339
340#endif
341
342#undef NS_TO_CLOCK
343#undef CLOCK_TO_DIV
344
345#endif /* __LCD_PANEL_H__ */
diff --git a/arch/arm/mach-lh7a40x/ssp-cpld.c b/arch/arm/mach-lh7a40x/ssp-cpld.c
deleted file mode 100644
index 2901d49d1484..000000000000
--- a/arch/arm/mach-lh7a40x/ssp-cpld.c
+++ /dev/null
@@ -1,343 +0,0 @@
1/* arch/arm/mach-lh7a40x/ssp-cpld.c
2 *
3 * Copyright (C) 2004,2005 Marc Singer
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * version 2 as published by the Free Software Foundation.
8 *
9 * SSP/SPI driver for the CardEngine CPLD.
10 *
11 */
12
13/* NOTES
14 -----
15
16 o *** This driver is cribbed from the 7952x implementation.
17 Some comments may not apply.
18
19 o This driver contains sufficient logic to control either the
20 serial EEPROMs or the audio codec. It is included in the kernel
21 to support the codec. The EEPROMs are really the responsibility
22 of the boot loader and should probably be left alone.
23
24 o The code must be augmented to cope with multiple, simultaneous
25 clients.
26 o The audio codec writes to the codec chip whenever playback
27 starts.
28 o The touchscreen driver writes to the ads chip every time it
29 samples.
30 o The audio codec must write 16 bits, but the touch chip writes
31 are 8 bits long.
32 o We need to be able to keep these configurations separate while
33 simultaneously active.
34
35 */
36
37#include <linux/module.h>
38#include <linux/kernel.h>
39//#include <linux/sched.h>
40#include <linux/errno.h>
41#include <linux/interrupt.h>
42//#include <linux/ioport.h>
43#include <linux/init.h>
44#include <linux/delay.h>
45#include <linux/spinlock.h>
46#include <linux/io.h>
47
48#include <asm/irq.h>
49#include <mach/hardware.h>
50
51#include <mach/ssp.h>
52
53//#define TALK
54
55#if defined (TALK)
56#define PRINTK(f...) printk (f)
57#else
58#define PRINTK(f...) do {} while (0)
59#endif
60
61#if defined (CONFIG_ARCH_LH7A400)
62# define CPLD_SPID __REGP16(CPLD06_VIRT) /* SPI data */
63# define CPLD_SPIC __REGP16(CPLD08_VIRT) /* SPI control */
64# define CPLD_SPIC_CS_CODEC (1<<0)
65# define CPLD_SPIC_CS_TOUCH (1<<1)
66# define CPLD_SPIC_WRITE (0<<2)
67# define CPLD_SPIC_READ (1<<2)
68# define CPLD_SPIC_DONE (1<<3) /* r/o */
69# define CPLD_SPIC_LOAD (1<<4)
70# define CPLD_SPIC_START (1<<4)
71# define CPLD_SPIC_LOADED (1<<5) /* r/o */
72#endif
73
74#define CPLD_SPI __REGP16(CPLD0A_VIRT) /* SPI operation */
75#define CPLD_SPI_CS_EEPROM (1<<3)
76#define CPLD_SPI_SCLK (1<<2)
77#define CPLD_SPI_TX_SHIFT (1)
78#define CPLD_SPI_TX (1<<CPLD_SPI_TX_SHIFT)
79#define CPLD_SPI_RX_SHIFT (0)
80#define CPLD_SPI_RX (1<<CPLD_SPI_RX_SHIFT)
81
82/* *** FIXME: these timing values are substantially larger than the
83 *** chip requires. We may implement an nsleep () function. */
84#define T_SKH 1 /* Clock time high (us) */
85#define T_SKL 1 /* Clock time low (us) */
86#define T_CS 1 /* Minimum chip select low time (us) */
87#define T_CSS 1 /* Minimum chip select setup time (us) */
88#define T_DIS 1 /* Data setup time (us) */
89
90 /* EEPROM SPI bits */
91#define P_START (1<<9)
92#define P_WRITE (1<<7)
93#define P_READ (2<<7)
94#define P_ERASE (3<<7)
95#define P_EWDS (0<<7)
96#define P_WRAL (0<<7)
97#define P_ERAL (0<<7)
98#define P_EWEN (0<<7)
99#define P_A_EWDS (0<<5)
100#define P_A_WRAL (1<<5)
101#define P_A_ERAL (2<<5)
102#define P_A_EWEN (3<<5)
103
104struct ssp_configuration {
105 int device;
106 int mode;
107 int speed;
108 int frame_size_write;
109 int frame_size_read;
110};
111
112static struct ssp_configuration ssp_configuration;
113static spinlock_t ssp_lock;
114
115static void enable_cs (void)
116{
117 switch (ssp_configuration.device) {
118 case DEVICE_EEPROM:
119 CPLD_SPI |= CPLD_SPI_CS_EEPROM;
120 break;
121 }
122 udelay (T_CSS);
123}
124
125static void disable_cs (void)
126{
127 switch (ssp_configuration.device) {
128 case DEVICE_EEPROM:
129 CPLD_SPI &= ~CPLD_SPI_CS_EEPROM;
130 break;
131 }
132 udelay (T_CS);
133}
134
135static void pulse_clock (void)
136{
137 CPLD_SPI |= CPLD_SPI_SCLK;
138 udelay (T_SKH);
139 CPLD_SPI &= ~CPLD_SPI_SCLK;
140 udelay (T_SKL);
141}
142
143
144/* execute_spi_command
145
146 sends an spi command to a device. It first sends cwrite bits from
147 v. If cread is greater than zero it will read cread bits
148 (discarding the leading 0 bit) and return them. If cread is less
149 than zero it will check for completetion status and return 0 on
150 success or -1 on timeout. If cread is zero it does nothing other
151 than sending the command.
152
153 On the LPD7A400, we can only read or write multiples of 8 bits on
154 the codec and the touch screen device. Here, we round up.
155
156*/
157
158static int execute_spi_command (int v, int cwrite, int cread)
159{
160 unsigned long l = 0;
161
162#if defined (CONFIG_MACH_LPD7A400)
163 /* The codec and touch devices cannot be bit-banged. Instead,
164 * the CPLD provides an eight-bit shift register and a crude
165 * interface. */
166 if ( ssp_configuration.device == DEVICE_CODEC
167 || ssp_configuration.device == DEVICE_TOUCH) {
168 int select = 0;
169
170 PRINTK ("spi(%d %d.%d) 0x%04x",
171 ssp_configuration.device, cwrite, cread,
172 v);
173#if defined (TALK)
174 if (ssp_configuration.device == DEVICE_CODEC)
175 PRINTK (" 0x%03x -> %2d", v & 0x1ff, (v >> 9) & 0x7f);
176#endif
177 PRINTK ("\n");
178
179 if (ssp_configuration.device == DEVICE_CODEC)
180 select = CPLD_SPIC_CS_CODEC;
181 if (ssp_configuration.device == DEVICE_TOUCH)
182 select = CPLD_SPIC_CS_TOUCH;
183 if (cwrite) {
184 for (cwrite = (cwrite + 7)/8; cwrite-- > 0; ) {
185 CPLD_SPID = (v >> (8*cwrite)) & 0xff;
186 CPLD_SPIC = select | CPLD_SPIC_LOAD;
187 while (!(CPLD_SPIC & CPLD_SPIC_LOADED))
188 ;
189 CPLD_SPIC = select;
190 while (!(CPLD_SPIC & CPLD_SPIC_DONE))
191 ;
192 }
193 v = 0;
194 }
195 if (cread) {
196 mdelay (2); /* *** FIXME: required by ads7843? */
197 v = 0;
198 for (cread = (cread + 7)/8; cread-- > 0;) {
199 CPLD_SPID = 0;
200 CPLD_SPIC = select | CPLD_SPIC_READ
201 | CPLD_SPIC_START;
202 while (!(CPLD_SPIC & CPLD_SPIC_LOADED))
203 ;
204 CPLD_SPIC = select | CPLD_SPIC_READ;
205 while (!(CPLD_SPIC & CPLD_SPIC_DONE))
206 ;
207 v = (v << 8) | CPLD_SPID;
208 }
209 }
210 return v;
211 }
212#endif
213
214 PRINTK ("spi(%d) 0x%04x -> 0x%x\r\n", ssp_configuration.device,
215 v & 0x1ff, (v >> 9) & 0x7f);
216
217 enable_cs ();
218
219 v <<= CPLD_SPI_TX_SHIFT; /* Correction for position of SPI_TX bit */
220 while (cwrite--) {
221 CPLD_SPI
222 = (CPLD_SPI & ~CPLD_SPI_TX)
223 | ((v >> cwrite) & CPLD_SPI_TX);
224 udelay (T_DIS);
225 pulse_clock ();
226 }
227
228 if (cread < 0) {
229 int delay = 10;
230 disable_cs ();
231 udelay (1);
232 enable_cs ();
233
234 l = -1;
235 do {
236 if (CPLD_SPI & CPLD_SPI_RX) {
237 l = 0;
238 break;
239 }
240 } while (udelay (1), --delay);
241 }
242 else
243 /* We pulse the clock before the data to skip the leading zero. */
244 while (cread-- > 0) {
245 pulse_clock ();
246 l = (l<<1)
247 | (((CPLD_SPI & CPLD_SPI_RX)
248 >> CPLD_SPI_RX_SHIFT) & 0x1);
249 }
250
251 disable_cs ();
252 return l;
253}
254
255static int ssp_init (void)
256{
257 spin_lock_init (&ssp_lock);
258 memset (&ssp_configuration, 0, sizeof (ssp_configuration));
259 return 0;
260}
261
262
263/* ssp_chip_select
264
265 drops the chip select line for the CPLD shift-register controlled
266 devices. It doesn't enable chip
267
268*/
269
270static void ssp_chip_select (int enable)
271{
272#if defined (CONFIG_MACH_LPD7A400)
273 int select;
274
275 if (ssp_configuration.device == DEVICE_CODEC)
276 select = CPLD_SPIC_CS_CODEC;
277 else if (ssp_configuration.device == DEVICE_TOUCH)
278 select = CPLD_SPIC_CS_TOUCH;
279 else
280 return;
281
282 if (enable)
283 CPLD_SPIC = select;
284 else
285 CPLD_SPIC = 0;
286#endif
287}
288
289static void ssp_acquire (void)
290{
291 spin_lock (&ssp_lock);
292}
293
294static void ssp_release (void)
295{
296 ssp_chip_select (0); /* just in case */
297 spin_unlock (&ssp_lock);
298}
299
300static int ssp_configure (int device, int mode, int speed,
301 int frame_size_write, int frame_size_read)
302{
303 ssp_configuration.device = device;
304 ssp_configuration.mode = mode;
305 ssp_configuration.speed = speed;
306 ssp_configuration.frame_size_write = frame_size_write;
307 ssp_configuration.frame_size_read = frame_size_read;
308
309 return 0;
310}
311
312static int ssp_read (void)
313{
314 return execute_spi_command (0, 0, ssp_configuration.frame_size_read);
315}
316
317static int ssp_write (u16 data)
318{
319 execute_spi_command (data, ssp_configuration.frame_size_write, 0);
320 return 0;
321}
322
323static int ssp_write_read (u16 data)
324{
325 return execute_spi_command (data, ssp_configuration.frame_size_write,
326 ssp_configuration.frame_size_read);
327}
328
329struct ssp_driver lh7a40x_cpld_ssp_driver = {
330 .init = ssp_init,
331 .acquire = ssp_acquire,
332 .release = ssp_release,
333 .configure = ssp_configure,
334 .chip_select = ssp_chip_select,
335 .read = ssp_read,
336 .write = ssp_write,
337 .write_read = ssp_write_read,
338};
339
340
341MODULE_AUTHOR("Marc Singer");
342MODULE_DESCRIPTION("LPD7A40X CPLD SPI driver");
343MODULE_LICENSE("GPL");
diff --git a/arch/arm/mach-lh7a40x/time.c b/arch/arm/mach-lh7a40x/time.c
deleted file mode 100644
index 4601e425bae3..000000000000
--- a/arch/arm/mach-lh7a40x/time.c
+++ /dev/null
@@ -1,71 +0,0 @@
1/*
2 * arch/arm/mach-lh7a40x/time.c
3 *
4 * Copyright (C) 2004 Logic Product Development
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * version 2 as published by the Free Software Foundation.
9 *
10 */
11#include <linux/module.h>
12#include <linux/kernel.h>
13#include <linux/interrupt.h>
14#include <linux/irq.h>
15#include <linux/time.h>
16#include <linux/io.h>
17
18#include <mach/hardware.h>
19#include <asm/irq.h>
20#include <asm/leds.h>
21
22#include <asm/mach/time.h>
23#include "common.h"
24
25#if HZ < 100
26# define TIMER_CONTROL TIMER_CONTROL2
27# define TIMER_LOAD TIMER_LOAD2
28# define TIMER_CONSTANT (508469/HZ)
29# define TIMER_MODE (TIMER_C_ENABLE | TIMER_C_PERIODIC | TIMER_C_508KHZ)
30# define TIMER_EOI TIMER_EOI2
31# define TIMER_IRQ IRQ_T2UI
32#else
33# define TIMER_CONTROL TIMER_CONTROL3
34# define TIMER_LOAD TIMER_LOAD3
35# define TIMER_CONSTANT (3686400/HZ)
36# define TIMER_MODE (TIMER_C_ENABLE | TIMER_C_PERIODIC)
37# define TIMER_EOI TIMER_EOI3
38# define TIMER_IRQ IRQ_T3UI
39#endif
40
41static irqreturn_t
42lh7a40x_timer_interrupt(int irq, void *dev_id)
43{
44 TIMER_EOI = 0;
45 timer_tick();
46
47 return IRQ_HANDLED;
48}
49
50static struct irqaction lh7a40x_timer_irq = {
51 .name = "LHA740x Timer Tick",
52 .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
53 .handler = lh7a40x_timer_interrupt,
54};
55
56static void __init lh7a40x_timer_init (void)
57{
58 /* Stop/disable all timers */
59 TIMER_CONTROL1 = 0;
60 TIMER_CONTROL2 = 0;
61 TIMER_CONTROL3 = 0;
62
63 setup_irq (TIMER_IRQ, &lh7a40x_timer_irq);
64
65 TIMER_LOAD = TIMER_CONSTANT;
66 TIMER_CONTROL = TIMER_MODE;
67}
68
69struct sys_timer lh7a40x_timer = {
70 .init = &lh7a40x_timer_init,
71};
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-16 19:05:00 -0500