Merge branch 'iommu/fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/linux-2.6-iommu into x86/urgent

1327 files changed, 78973 insertions, 35128 deletions

diff --git a/arch/alpha/boot/bootp.c b/arch/alpha/boot/bootp.c
index 3af21c789339..3c8d1b25c661 100644
--- a/arch/alpha/boot/bootp.c
+++ b/arch/alpha/boot/bootp.c
@@ -9,7 +9,7 @@
  */
 #include <linux/kernel.h>
 #include <linux/string.h>
-#include <linux/utsrelease.h>
+#include <generated/utsrelease.h>
 #include <linux/mm.h>
 
 #include <asm/system.h>
diff --git a/arch/alpha/boot/bootpz.c b/arch/alpha/boot/bootpz.c
index 1036b515e20c..ade3f129dc27 100644
--- a/arch/alpha/boot/bootpz.c
+++ b/arch/alpha/boot/bootpz.c
@@ -11,7 +11,7 @@
  */
 #include <linux/kernel.h>
 #include <linux/string.h>
-#include <linux/utsrelease.h>
+#include <generated/utsrelease.h>
 #include <linux/mm.h>
 
 #include <asm/system.h>
diff --git a/arch/alpha/boot/main.c b/arch/alpha/boot/main.c
index 89f3be071ae5..644b7db55438 100644
--- a/arch/alpha/boot/main.c
+++ b/arch/alpha/boot/main.c
@@ -7,7 +7,7 @@
  */
 #include <linux/kernel.h>
 #include <linux/string.h>
-#include <linux/utsrelease.h>
+#include <generated/utsrelease.h>
 #include <linux/mm.h>
 
 #include <asm/system.h>
diff --git a/arch/alpha/include/asm/asm-offsets.h b/arch/alpha/include/asm/asm-offsets.h
new file mode 100644
index 000000000000..d370ee36a182
--- /dev/null
+++ b/arch/alpha/include/asm/asm-offsets.h
@@ -0,0 +1 @@
+#include <generated/asm-offsets.h>
diff --git a/arch/alpha/include/asm/core_t2.h b/arch/alpha/include/asm/core_t2.h
index 46bfff58f670..471c07292e0b 100644
--- a/arch/alpha/include/asm/core_t2.h
+++ b/arch/alpha/include/asm/core_t2.h
@@ -435,7 +435,7 @@ extern inline void t2_outl(u32 b, unsigned long addr)
         set_hae(msb); \
 }
 
-extern spinlock_t t2_hae_lock;
+extern raw_spinlock_t t2_hae_lock;
 
 /*
  * NOTE: take T2_DENSE_MEM off in each readX/writeX routine, since
@@ -448,12 +448,12 @@ __EXTERN_INLINE u8 t2_readb(const volatile void __iomem *xaddr)
         unsigned long addr = (unsigned long) xaddr - T2_DENSE_MEM;
         unsigned long result, msb;
         unsigned long flags;
-        spin_lock_irqsave(&t2_hae_lock, flags);
+        raw_spin_lock_irqsave(&t2_hae_lock, flags);
 
         t2_set_hae;
 
         result = *(vip) ((addr << 5) + T2_SPARSE_MEM + 0x00);
-        spin_unlock_irqrestore(&t2_hae_lock, flags);
+        raw_spin_unlock_irqrestore(&t2_hae_lock, flags);
         return __kernel_extbl(result, addr & 3);
 }
 
@@ -462,12 +462,12 @@ __EXTERN_INLINE u16 t2_readw(const volatile void __iomem *xaddr)
         unsigned long addr = (unsigned long) xaddr - T2_DENSE_MEM;
         unsigned long result, msb;
         unsigned long flags;
-        spin_lock_irqsave(&t2_hae_lock, flags);
+        raw_spin_lock_irqsave(&t2_hae_lock, flags);
 
         t2_set_hae;
 
         result = *(vuip) ((addr << 5) + T2_SPARSE_MEM + 0x08);
-        spin_unlock_irqrestore(&t2_hae_lock, flags);
+        raw_spin_unlock_irqrestore(&t2_hae_lock, flags);
         return __kernel_extwl(result, addr & 3);
 }
 
@@ -480,12 +480,12 @@ __EXTERN_INLINE u32 t2_readl(const volatile void __iomem *xaddr)
         unsigned long addr = (unsigned long) xaddr - T2_DENSE_MEM;
         unsigned long result, msb;
         unsigned long flags;
-        spin_lock_irqsave(&t2_hae_lock, flags);
+        raw_spin_lock_irqsave(&t2_hae_lock, flags);
 
         t2_set_hae;
 
         result = *(vuip) ((addr << 5) + T2_SPARSE_MEM + 0x18);
-        spin_unlock_irqrestore(&t2_hae_lock, flags);
+        raw_spin_unlock_irqrestore(&t2_hae_lock, flags);
         return result & 0xffffffffUL;
 }
 
@@ -494,14 +494,14 @@ __EXTERN_INLINE u64 t2_readq(const volatile void __iomem *xaddr)
         unsigned long addr = (unsigned long) xaddr - T2_DENSE_MEM;
         unsigned long r0, r1, work, msb;
         unsigned long flags;
-        spin_lock_irqsave(&t2_hae_lock, flags);
+        raw_spin_lock_irqsave(&t2_hae_lock, flags);
 
         t2_set_hae;
 
         work = (addr << 5) + T2_SPARSE_MEM + 0x18;
         r0 = *(vuip)(work);
         r1 = *(vuip)(work + (4 << 5));
-        spin_unlock_irqrestore(&t2_hae_lock, flags);
+        raw_spin_unlock_irqrestore(&t2_hae_lock, flags);
         return r1 << 32 | r0;
 }
 
@@ -510,13 +510,13 @@ __EXTERN_INLINE void t2_writeb(u8 b, volatile void __iomem *xaddr)
         unsigned long addr = (unsigned long) xaddr - T2_DENSE_MEM;
         unsigned long msb, w;
         unsigned long flags;
-        spin_lock_irqsave(&t2_hae_lock, flags);
+        raw_spin_lock_irqsave(&t2_hae_lock, flags);
 
         t2_set_hae;
 
         w = __kernel_insbl(b, addr & 3);
         *(vuip) ((addr << 5) + T2_SPARSE_MEM + 0x00) = w;
-        spin_unlock_irqrestore(&t2_hae_lock, flags);
+        raw_spin_unlock_irqrestore(&t2_hae_lock, flags);
 }
 
 __EXTERN_INLINE void t2_writew(u16 b, volatile void __iomem *xaddr)
@@ -524,13 +524,13 @@ __EXTERN_INLINE void t2_writew(u16 b, volatile void __iomem *xaddr)
         unsigned long addr = (unsigned long) xaddr - T2_DENSE_MEM;
         unsigned long msb, w;
         unsigned long flags;
-        spin_lock_irqsave(&t2_hae_lock, flags);
+        raw_spin_lock_irqsave(&t2_hae_lock, flags);
 
         t2_set_hae;
 
         w = __kernel_inswl(b, addr & 3);
         *(vuip) ((addr << 5) + T2_SPARSE_MEM + 0x08) = w;
-        spin_unlock_irqrestore(&t2_hae_lock, flags);
+        raw_spin_unlock_irqrestore(&t2_hae_lock, flags);
 }
 
 /*
@@ -542,12 +542,12 @@ __EXTERN_INLINE void t2_writel(u32 b, volatile void __iomem *xaddr)
         unsigned long addr = (unsigned long) xaddr - T2_DENSE_MEM;
         unsigned long msb;
         unsigned long flags;
-        spin_lock_irqsave(&t2_hae_lock, flags);
+        raw_spin_lock_irqsave(&t2_hae_lock, flags);
 
         t2_set_hae;
 
         *(vuip) ((addr << 5) + T2_SPARSE_MEM + 0x18) = b;
-        spin_unlock_irqrestore(&t2_hae_lock, flags);
+        raw_spin_unlock_irqrestore(&t2_hae_lock, flags);
 }
 
 __EXTERN_INLINE void t2_writeq(u64 b, volatile void __iomem *xaddr)
@@ -555,14 +555,14 @@ __EXTERN_INLINE void t2_writeq(u64 b, volatile void __iomem *xaddr)
         unsigned long addr = (unsigned long) xaddr - T2_DENSE_MEM;
         unsigned long msb, work;
         unsigned long flags;
-        spin_lock_irqsave(&t2_hae_lock, flags);
+        raw_spin_lock_irqsave(&t2_hae_lock, flags);
 
         t2_set_hae;
 
         work = (addr << 5) + T2_SPARSE_MEM + 0x18;
         *(vuip)work = b;
         *(vuip)(work + (4 << 5)) = b >> 32;
-        spin_unlock_irqrestore(&t2_hae_lock, flags);
+        raw_spin_unlock_irqrestore(&t2_hae_lock, flags);
 }
 
 __EXTERN_INLINE void __iomem *t2_ioportmap(unsigned long addr)
diff --git a/arch/alpha/include/asm/elf.h b/arch/alpha/include/asm/elf.h
index 5c75c1b2352a..9baae8afe8a3 100644
--- a/arch/alpha/include/asm/elf.h
+++ b/arch/alpha/include/asm/elf.h
@@ -81,7 +81,6 @@ typedef elf_fpreg_t elf_fpregset_t[ELF_NFPREG];
 #define ELF_DATA        ELFDATA2LSB
 #define ELF_ARCH        EM_ALPHA
 
-#define USE_ELF_CORE_DUMP
 #define ELF_EXEC_PAGESIZE       8192
 
 /* This is the location that an ET_DYN program is loaded if exec'ed.  Typical
diff --git a/arch/alpha/include/asm/fcntl.h b/arch/alpha/include/asm/fcntl.h
index 25da0017ec87..70145cbb21cb 100644
--- a/arch/alpha/include/asm/fcntl.h
+++ b/arch/alpha/include/asm/fcntl.h
@@ -1,8 +1,6 @@
 #ifndef _ALPHA_FCNTL_H
 #define _ALPHA_FCNTL_H
 
-/* open/fcntl - O_SYNC is only implemented on blocks devices and on files
-   located on an ext2 file system */
 #define O_CREAT          01000  /* not fcntl */
 #define O_TRUNC          02000  /* not fcntl */
 #define O_EXCL           04000  /* not fcntl */
@@ -10,13 +8,28 @@
 
 #define O_NONBLOCK       00004
 #define O_APPEND         00010
-#define O_SYNC          040000
+#define O_DSYNC         040000  /* used to be O_SYNC, see below */
 #define O_DIRECTORY     0100000 /* must be a directory */
 #define O_NOFOLLOW      0200000 /* don't follow links */
 #define O_LARGEFILE     0400000 /* will be set by the kernel on every open */
 #define O_DIRECT        02000000 /* direct disk access - should check with OSF/1 */
 #define O_NOATIME       04000000
 #define O_CLOEXEC       010000000 /* set close_on_exec */
+/*
+ * Before Linux 2.6.33 only O_DSYNC semantics were implemented, but using
+ * the O_SYNC flag.  We continue to use the existing numerical value
+ * for O_DSYNC semantics now, but using the correct symbolic name for it.
+ * This new value is used to request true Posix O_SYNC semantics.  It is
+ * defined in this strange way to make sure applications compiled against
+ * new headers get at least O_DSYNC semantics on older kernels.
+ *
+ * This has the nice side-effect that we can simply test for O_DSYNC
+ * wherever we do not care if O_DSYNC or O_SYNC is used.
+ *
+ * Note: __O_SYNC must never be used directly.
+ */
+#define __O_SYNC        020000000
+#define O_SYNC          (__O_SYNC|O_DSYNC)
 
 #define F_GETLK         7
 #define F_SETLK         8
diff --git a/arch/alpha/include/asm/spinlock.h b/arch/alpha/include/asm/spinlock.h
index e38fb95cb335..d0faca1e992d 100644
--- a/arch/alpha/include/asm/spinlock.h
+++ b/arch/alpha/include/asm/spinlock.h
@@ -12,18 +12,18 @@
  * We make no fairness assumptions. They have a cost.
  */
 
-#define __raw_spin_lock_flags(lock, flags) __raw_spin_lock(lock)
-#define __raw_spin_is_locked(x) ((x)->lock != 0)
-#define __raw_spin_unlock_wait(x) \
+#define arch_spin_lock_flags(lock, flags) arch_spin_lock(lock)
+#define arch_spin_is_locked(x)  ((x)->lock != 0)
+#define arch_spin_unlock_wait(x) \
                 do { cpu_relax(); } while ((x)->lock)
 
-static inline void __raw_spin_unlock(raw_spinlock_t * lock)
+static inline void arch_spin_unlock(arch_spinlock_t * lock)
 {
         mb();
         lock->lock = 0;
 }
 
-static inline void __raw_spin_lock(raw_spinlock_t * lock)
+static inline void arch_spin_lock(arch_spinlock_t * lock)
 {
         long tmp;
 
@@ -43,24 +43,24 @@ static inline void __raw_spin_lock(raw_spinlock_t * lock)
         : "m"(lock->lock) : "memory");
 }
 
-static inline int __raw_spin_trylock(raw_spinlock_t *lock)
+static inline int arch_spin_trylock(arch_spinlock_t *lock)
 {
         return !test_and_set_bit(0, &lock->lock);
 }
 
 /***********************************************************/
 
-static inline int __raw_read_can_lock(raw_rwlock_t *lock)
+static inline int arch_read_can_lock(arch_rwlock_t *lock)
 {
         return (lock->lock & 1) == 0;
 }
 
-static inline int __raw_write_can_lock(raw_rwlock_t *lock)
+static inline int arch_write_can_lock(arch_rwlock_t *lock)
 {
         return lock->lock == 0;
 }
 
-static inline void __raw_read_lock(raw_rwlock_t *lock)
+static inline void arch_read_lock(arch_rwlock_t *lock)
 {
         long regx;
 
@@ -80,7 +80,7 @@ static inline void __raw_read_lock(raw_rwlock_t *lock)
         : "m" (*lock) : "memory");
 }
 
-static inline void __raw_write_lock(raw_rwlock_t *lock)
+static inline void arch_write_lock(arch_rwlock_t *lock)
 {
         long regx;
 
@@ -100,7 +100,7 @@ static inline void __raw_write_lock(raw_rwlock_t *lock)
         : "m" (*lock) : "memory");
 }
 
-static inline int __raw_read_trylock(raw_rwlock_t * lock)
+static inline int arch_read_trylock(arch_rwlock_t * lock)
 {
         long regx;
         int success;
@@ -122,7 +122,7 @@ static inline int __raw_read_trylock(raw_rwlock_t * lock)
         return success;
 }
 
-static inline int __raw_write_trylock(raw_rwlock_t * lock)
+static inline int arch_write_trylock(arch_rwlock_t * lock)
 {
         long regx;
         int success;
@@ -144,7 +144,7 @@ static inline int __raw_write_trylock(raw_rwlock_t * lock)
         return success;
 }
 
-static inline void __raw_read_unlock(raw_rwlock_t * lock)
+static inline void arch_read_unlock(arch_rwlock_t * lock)
 {
         long regx;
         __asm__ __volatile__(
@@ -160,17 +160,17 @@ static inline void __raw_read_unlock(raw_rwlock_t * lock)
         : "m" (*lock) : "memory");
 }
 
-static inline void __raw_write_unlock(raw_rwlock_t * lock)
+static inline void arch_write_unlock(arch_rwlock_t * lock)
 {
         mb();
         lock->lock = 0;
 }
 
-#define __raw_read_lock_flags(lock, flags) __raw_read_lock(lock)
-#define __raw_write_lock_flags(lock, flags) __raw_write_lock(lock)
+#define arch_read_lock_flags(lock, flags) arch_read_lock(lock)
+#define arch_write_lock_flags(lock, flags) arch_write_lock(lock)
 
-#define _raw_spin_relax(lock)   cpu_relax()
-#define _raw_read_relax(lock)   cpu_relax()
-#define _raw_write_relax(lock)  cpu_relax()
+#define arch_spin_relax(lock)   cpu_relax()
+#define arch_read_relax(lock)   cpu_relax()
+#define arch_write_relax(lock)  cpu_relax()
 
 #endif /* _ALPHA_SPINLOCK_H */
diff --git a/arch/alpha/include/asm/spinlock_types.h b/arch/alpha/include/asm/spinlock_types.h
index 8141eb5ebf0d..54c2afce0a1d 100644
--- a/arch/alpha/include/asm/spinlock_types.h
+++ b/arch/alpha/include/asm/spinlock_types.h
@@ -7,14 +7,14 @@
 
 typedef struct {
         volatile unsigned int lock;
-} raw_spinlock_t;
+} arch_spinlock_t;
 
-#define __RAW_SPIN_LOCK_UNLOCKED        { 0 }
+#define __ARCH_SPIN_LOCK_UNLOCKED       { 0 }
 
 typedef struct {
         volatile unsigned int lock;
-} raw_rwlock_t;
+} arch_rwlock_t;
 
-#define __RAW_RW_LOCK_UNLOCKED          { 0 }
+#define __ARCH_RW_LOCK_UNLOCKED         { 0 }
 
 #endif
diff --git a/arch/alpha/kernel/core_t2.c b/arch/alpha/kernel/core_t2.c
index d9980d47ab81..e6d90568b65d 100644
--- a/arch/alpha/kernel/core_t2.c
+++ b/arch/alpha/kernel/core_t2.c
@@ -74,7 +74,7 @@
 # define DBG(args)
 #endif
 
-DEFINE_SPINLOCK(t2_hae_lock);
+DEFINE_RAW_SPINLOCK(t2_hae_lock);
 
 static volatile unsigned int t2_mcheck_any_expected;
 static volatile unsigned int t2_mcheck_last_taken;
diff --git a/arch/alpha/kernel/irq.c b/arch/alpha/kernel/irq.c
index c0de072b8305..5f2cf23c4648 100644
--- a/arch/alpha/kernel/irq.c
+++ b/arch/alpha/kernel/irq.c
@@ -81,7 +81,7 @@ show_interrupts(struct seq_file *p, void *v)
 #endif
 
         if (irq < ACTUAL_NR_IRQS) {
-                spin_lock_irqsave(&irq_desc[irq].lock, flags);
+                raw_spin_lock_irqsave(&irq_desc[irq].lock, flags);
                 action = irq_desc[irq].action;
                 if (!action) 
                         goto unlock;
@@ -105,7 +105,7 @@ show_interrupts(struct seq_file *p, void *v)
 
                 seq_putc(p, '\n');
 unlock:
-                spin_unlock_irqrestore(&irq_desc[irq].lock, flags);
+                raw_spin_unlock_irqrestore(&irq_desc[irq].lock, flags);
         } else if (irq == ACTUAL_NR_IRQS) {
 #ifdef CONFIG_SMP
                 seq_puts(p, "IPI: ");
diff --git a/arch/alpha/kernel/osf_sys.c b/arch/alpha/kernel/osf_sys.c
index 9a3334ae282e..62619f25132f 100644
--- a/arch/alpha/kernel/osf_sys.c
+++ b/arch/alpha/kernel/osf_sys.c
@@ -178,25 +178,18 @@ SYSCALL_DEFINE6(osf_mmap, unsigned long, addr, unsigned long, len,
                 unsigned long, prot, unsigned long, flags, unsigned long, fd,
                 unsigned long, off)
 {
-        struct file *file = NULL;
-        unsigned long ret = -EBADF;
+        unsigned long ret = -EINVAL;
 
 #if 0
         if (flags & (_MAP_HASSEMAPHORE | _MAP_INHERIT | _MAP_UNALIGNED))
                 printk("%s: unimplemented OSF mmap flags %04lx\n", 
                         current->comm, flags);
 #endif
-        if (!(flags & MAP_ANONYMOUS)) {
-                file = fget(fd);
-                if (!file)
-                        goto out;
-        }
-        flags &= ~(MAP_EXECUTABLE | MAP_DENYWRITE);
-        down_write(&current->mm->mmap_sem);
-        ret = do_mmap(file, addr, len, prot, flags, off);
-        up_write(&current->mm->mmap_sem);
-        if (file)
-                fput(file);
+        if ((off + PAGE_ALIGN(len)) < off)
+                goto out;
+        if (off & ~PAGE_MASK)
+                goto out;
+        ret = sys_mmap_pgoff(addr, len, prot, flags, fd, off >> PAGE_SHIFT);
  out:
         return ret;
 }
diff --git a/arch/alpha/kernel/srm_env.c b/arch/alpha/kernel/srm_env.c
index d12af472e1c0..dbbf04f9230e 100644
--- a/arch/alpha/kernel/srm_env.c
+++ b/arch/alpha/kernel/srm_env.c
@@ -33,6 +33,7 @@
 #include <linux/module.h>
 #include <linux/init.h>
 #include <linux/proc_fs.h>
+#include <linux/seq_file.h>
 #include <asm/console.h>
 #include <asm/uaccess.h>
 #include <asm/machvec.h>
@@ -79,42 +80,41 @@ static srm_env_t	srm_named_entries[] = {
 static srm_env_t        srm_numbered_entries[256];
 
 
-static int
-srm_env_read(char *page, char **start, off_t off, int count, int *eof,
-                void *data)
+static int srm_env_proc_show(struct seq_file *m, void *v)
 {
-        int             nbytes;
         unsigned long   ret;
         srm_env_t       *entry;
+        char            *page;
 
-        if (off != 0) {
-                *eof = 1;
-                return 0;
-        }
+        entry = (srm_env_t *)m->private;
+        page = (char *)__get_free_page(GFP_USER);
+        if (!page)
+                return -ENOMEM;
 
-        entry   = (srm_env_t *) data;
-        ret     = callback_getenv(entry->id, page, count);
+        ret = callback_getenv(entry->id, page, PAGE_SIZE);
 
         if ((ret >> 61) == 0) {
-                nbytes = (int) ret;
-                *eof = 1;
+                seq_write(m, page, ret);
+                ret = 0;
         } else
-                nbytes = -EFAULT;
+                ret = -EFAULT;
+        free_page((unsigned long)page);
+        return ret;
+}
 
-        return nbytes;
+static int srm_env_proc_open(struct inode *inode, struct file *file)
+{
+        return single_open(file, srm_env_proc_show, PDE(inode)->data);
 }
 
-static int
-srm_env_write(struct file *file, const char __user *buffer, unsigned long count,
-                void *data)
+static ssize_t srm_env_proc_write(struct file *file, const char __user *buffer,
+                                  size_t count, loff_t *pos)
 {
         int res;
-        srm_env_t       *entry;
+        srm_env_t       *entry = PDE(file->f_path.dentry->d_inode)->data;
         char            *buf = (char *) __get_free_page(GFP_USER);
         unsigned long   ret1, ret2;
 
-        entry = (srm_env_t *) data;
-
         if (!buf)
                 return -ENOMEM;
 
@@ -140,6 +140,15 @@ srm_env_write(struct file *file, const char __user *buffer, unsigned long count,
         return res;
 }
 
+static const struct file_operations srm_env_proc_fops = {
+        .owner          = THIS_MODULE,
+        .open           = srm_env_proc_open,
+        .read           = seq_read,
+        .llseek         = seq_lseek,
+        .release        = single_release,
+        .write          = srm_env_proc_write,
+};
+
 static void
 srm_env_cleanup(void)
 {
@@ -245,15 +254,10 @@ srm_env_init(void)
          */
         entry = srm_named_entries;
         while (entry->name && entry->id) {
-                entry->proc_entry = create_proc_entry(entry->name,
-                                0644, named_dir);
+                entry->proc_entry = proc_create_data(entry->name, 0644, named_dir,
+                                                     &srm_env_proc_fops, entry);
                 if (!entry->proc_entry)
                         goto cleanup;
-
-                entry->proc_entry->data         = (void *) entry;
-                entry->proc_entry->read_proc    = srm_env_read;
-                entry->proc_entry->write_proc   = srm_env_write;
-
                 entry++;
         }
 
@@ -264,15 +268,12 @@ srm_env_init(void)
                 entry = &srm_numbered_entries[var_num];
                 entry->name = number[var_num];
 
-                entry->proc_entry = create_proc_entry(entry->name,
-                                0644, numbered_dir);
+                entry->proc_entry = proc_create_data(entry->name, 0644, numbered_dir,
+                                                     &srm_env_proc_fops, entry);
                 if (!entry->proc_entry)
                         goto cleanup;
 
                 entry->id                       = var_num;
-                entry->proc_entry->data         = (void *) entry;
-                entry->proc_entry->read_proc    = srm_env_read;
-                entry->proc_entry->write_proc   = srm_env_write;
         }
 
         printk(KERN_INFO "%s: version %s loaded successfully\n", NAME,
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index cf8a99f19dc4..233a222752c0 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -603,6 +603,7 @@ config ARCH_SA1100
         select ARCH_SPARSEMEM_ENABLE
         select ARCH_MTD_XIP
         select ARCH_HAS_CPUFREQ
+        select CPU_FREQ
         select GENERIC_GPIO
         select GENERIC_TIME
         select GENERIC_CLOCKEVENTS
@@ -1359,13 +1360,9 @@ source "drivers/cpufreq/Kconfig"
 
 config CPU_FREQ_SA1100
         bool
-        depends on CPU_FREQ && (SA1100_H3100 || SA1100_H3600 || SA1100_LART || SA1100_PLEB || SA1100_BADGE4 || SA1100_HACKKIT)
-        default y
 
 config CPU_FREQ_SA1110
         bool
-        depends on CPU_FREQ && (SA1100_ASSABET || SA1100_CERF || SA1100_PT_SYSTEM3)
-        default y
 
 config CPU_FREQ_INTEGRATOR
         tristate "CPUfreq driver for ARM Integrator CPUs"
diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
index ff54c23d085e..5cb9326df7a7 100644
--- a/arch/arm/Kconfig.debug
+++ b/arch/arm/Kconfig.debug
@@ -71,6 +71,14 @@ config DEBUG_LL
           in the kernel.  This is helpful if you are debugging code that
           executes before the console is initialized.
 
+config EARLY_PRINTK
+        bool "Early printk"
+        depends on DEBUG_LL
+        help
+          Say Y here if you want to have an early console using the
+          kernel low-level debugging functions. Add earlyprintk to your
+          kernel parameters to enable this console.
+
 config DEBUG_ICEDCC
         bool "Kernel low-level debugging via EmbeddedICE DCC channel"
         depends on DEBUG_LL
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index fa0cdab2e1d3..e9da08483b3c 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -242,15 +242,8 @@ all:	$(KBUILD_IMAGE)
 
 boot := arch/arm/boot
 
-#       Update machine arch and proc symlinks if something which affects
-#       them changed.  We use .arch to indicate when they were updated
-#       last, otherwise make uses the target directory mtime.
-
-archprepare: maketools
-
-PHONY += maketools FORCE
-maketools: include/linux/version.h FORCE
-        $(Q)$(MAKE) $(build)=arch/arm/tools include/asm-arm/mach-types.h
+archprepare:
+        $(Q)$(MAKE) $(build)=arch/arm/tools include/generated/mach-types.h
 
 # Convert bzImage to zImage
 bzImage: zImage
@@ -261,9 +254,6 @@ zImage Image xipImage bootpImage uImage: vmlinux
 zinstall install: vmlinux
         $(Q)$(MAKE) $(build)=$(boot) MACHINE=$(MACHINE) $@
 
-CLEAN_FILES += include/asm-arm/mach-types.h \
-               include/asm-arm/arch include/asm-arm/.arch
-
 # We use MRPROPER_FILES and CLEAN_FILES now
 archclean:
         $(Q)$(MAKE) $(clean)=$(boot)
diff --git a/arch/arm/common/dmabounce.c b/arch/arm/common/dmabounce.c
index 5a375e5fef21..bc90364a96c7 100644
--- a/arch/arm/common/dmabounce.c
+++ b/arch/arm/common/dmabounce.c
@@ -308,15 +308,11 @@ static inline void unmap_single(struct device *dev, dma_addr_t dma_addr,
                         memcpy(ptr, buf->safe, size);
 
                         /*
-                         * DMA buffers must have the same cache properties
-                         * as if they were really used for DMA - which means
-                         * data must be written back to RAM.  Note that
-                         * we don't use dmac_flush_range() here for the
-                         * bidirectional case because we know the cache
-                         * lines will be coherent with the data written.
+                         * Since we may have written to a page cache page,
+                         * we need to ensure that the data will be coherent
+                         * with user mappings.
                          */
-                        dmac_clean_range(ptr, ptr + size);
-                        outer_clean_range(__pa(ptr), __pa(ptr) + size);
+                        __cpuc_flush_kernel_dcache_area(ptr, size);
                 }
                 free_safe_buffer(dev->archdata.dmabounce, buf);
         }
diff --git a/arch/arm/configs/htcherald_defconfig b/arch/arm/configs/htcherald_defconfig
index 338267674075..1b39691b816f 100644
--- a/arch/arm/configs/htcherald_defconfig
+++ b/arch/arm/configs/htcherald_defconfig
@@ -1,7 +1,7 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.32-rc6
-# Sat Nov 14 10:56:01 2009
+# Linux kernel version: 2.6.32-rc8
+# Sat Dec  5 12:16:24 2009
 #
 CONFIG_ARM=y
 CONFIG_SYS_SUPPORTS_APM_EMULATION=y
@@ -198,7 +198,9 @@ CONFIG_ARCH_OMAP1=y
 # OMAP Feature Selections
 #
 # CONFIG_OMAP_RESET_CLOCKS is not set
-# CONFIG_OMAP_MUX is not set
+CONFIG_OMAP_MUX=y
+# CONFIG_OMAP_MUX_DEBUG is not set
+CONFIG_OMAP_MUX_WARNINGS=y
 CONFIG_OMAP_MCBSP=y
 # CONFIG_OMAP_MBOX_FWK is not set
 CONFIG_OMAP_MPU_TIMER=y
@@ -207,6 +209,7 @@ CONFIG_OMAP_LL_DEBUG_UART1=y
 # CONFIG_OMAP_LL_DEBUG_UART2 is not set
 # CONFIG_OMAP_LL_DEBUG_UART3 is not set
 # CONFIG_OMAP_LL_DEBUG_NONE is not set
+CONFIG_OMAP_SERIAL_WAKE=y
 # CONFIG_OMAP_PM_NONE is not set
 CONFIG_OMAP_PM_NOOP=y
 
diff --git a/arch/arm/configs/omap3_touchbook_defconfig b/arch/arm/configs/omap3_touchbook_defconfig
new file mode 100644
index 000000000000..7c8515e65c02
--- /dev/null
+++ b/arch/arm/configs/omap3_touchbook_defconfig
@@ -0,0 +1,2431 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.32-rc8
+# Fri Dec  4 16:02:17 2009
+#
+CONFIG_ARM=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_GENERIC_GPIO=y
+CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_HAVE_LATENCYTOP_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+CONFIG_ARCH_HAS_CPUFREQ=y
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
+CONFIG_OPROFILE_ARMV7=y
+CONFIG_VECTORS_BASE=0xffff0000
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+CONFIG_CONSTRUCTORS=y
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_LOCK_KERNEL=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION=""
+# CONFIG_LOCALVERSION_AUTO is not set
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+# CONFIG_POSIX_MQUEUE is not set
+CONFIG_BSD_PROCESS_ACCT=y
+# CONFIG_BSD_PROCESS_ACCT_V3 is not set
+CONFIG_TASKSTATS=y
+CONFIG_TASK_DELAY_ACCT=y
+CONFIG_TASK_XACCT=y
+CONFIG_TASK_IO_ACCOUNTING=y
+# CONFIG_AUDIT is not set
+
+#
+# RCU Subsystem
+#
+CONFIG_TREE_RCU=y
+# CONFIG_TREE_PREEMPT_RCU is not set
+# CONFIG_RCU_TRACE is not set
+CONFIG_RCU_FANOUT=32
+# CONFIG_RCU_FANOUT_EXACT is not set
+# CONFIG_TREE_RCU_TRACE is not set
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=15
+CONFIG_GROUP_SCHED=y
+CONFIG_FAIR_GROUP_SCHED=y
+# CONFIG_RT_GROUP_SCHED is not set
+CONFIG_USER_SCHED=y
+# CONFIG_CGROUP_SCHED is not set
+# CONFIG_CGROUPS is not set
+# CONFIG_SYSFS_DEPRECATED_V2 is not set
+# CONFIG_RELAY is not set
+# CONFIG_NAMESPACES is not set
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_RD_GZIP=y
+# CONFIG_RD_BZIP2 is not set
+# CONFIG_RD_LZMA is not set
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_SYSCTL=y
+CONFIG_ANON_INODES=y
+CONFIG_EMBEDDED=y
+CONFIG_UID16=y
+# CONFIG_SYSCTL_SYSCALL is not set
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_ALL is not set
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+# CONFIG_ELF_CORE is not set
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_AIO=y
+
+#
+# Kernel Performance Events And Counters
+#
+CONFIG_VM_EVENT_COUNTERS=y
+# CONFIG_COMPAT_BRK is not set
+CONFIG_SLAB=y
+# CONFIG_SLUB is not set
+# CONFIG_SLOB is not set
+CONFIG_PROFILING=y
+CONFIG_TRACEPOINTS=y
+CONFIG_OPROFILE=y
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_KPROBES is not set
+CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_KRETPROBES=y
+CONFIG_HAVE_CLK=y
+
+#
+# GCOV-based kernel profiling
+#
+# CONFIG_GCOV_KERNEL is not set
+CONFIG_SLOW_WORK=y
+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+CONFIG_MODULE_FORCE_LOAD=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODULE_FORCE_UNLOAD=y
+CONFIG_MODVERSIONS=y
+CONFIG_MODULE_SRCVERSION_ALL=y
+CONFIG_BLOCK=y
+CONFIG_LBDAF=y
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_BLK_DEV_INTEGRITY is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+# CONFIG_DEFAULT_AS is not set
+# CONFIG_DEFAULT_DEADLINE is not set
+CONFIG_DEFAULT_CFQ=y
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="cfq"
+CONFIG_FREEZER=y
+
+#
+# System Type
+#
+CONFIG_MMU=y
+# CONFIG_ARCH_AAEC2000 is not set
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_REALVIEW is not set
+# CONFIG_ARCH_VERSATILE is not set
+# CONFIG_ARCH_AT91 is not set
+# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_GEMINI is not set
+# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_EP93XX is not set
+# CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_MXC is not set
+# CONFIG_ARCH_STMP3XXX is not set
+# CONFIG_ARCH_NETX is not set
+# CONFIG_ARCH_H720X is not set
+# CONFIG_ARCH_NOMADIK is not set
+# CONFIG_ARCH_IOP13XX is not set
+# CONFIG_ARCH_IOP32X is not set
+# CONFIG_ARCH_IOP33X is not set
+# CONFIG_ARCH_IXP23XX is not set
+# CONFIG_ARCH_IXP2000 is not set
+# CONFIG_ARCH_IXP4XX is not set
+# CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_KIRKWOOD is not set
+# CONFIG_ARCH_LOKI is not set
+# CONFIG_ARCH_MV78XX0 is not set
+# CONFIG_ARCH_ORION5X is not set
+# CONFIG_ARCH_MMP is not set
+# CONFIG_ARCH_KS8695 is not set
+# CONFIG_ARCH_NS9XXX is not set
+# CONFIG_ARCH_W90X900 is not set
+# CONFIG_ARCH_PNX4008 is not set
+# CONFIG_ARCH_PXA is not set
+# CONFIG_ARCH_MSM is not set
+# CONFIG_ARCH_RPC is not set
+# CONFIG_ARCH_SA1100 is not set
+# CONFIG_ARCH_S3C2410 is not set
+# CONFIG_ARCH_S3C64XX is not set
+# CONFIG_ARCH_S5PC1XX is not set
+# CONFIG_ARCH_SHARK is not set
+# CONFIG_ARCH_LH7A40X is not set
+# CONFIG_ARCH_U300 is not set
+# CONFIG_ARCH_DAVINCI is not set
+CONFIG_ARCH_OMAP=y
+# CONFIG_ARCH_BCMRING is not set
+
+#
+# TI OMAP Implementations
+#
+CONFIG_ARCH_OMAP_OTG=y
+# CONFIG_ARCH_OMAP1 is not set
+# CONFIG_ARCH_OMAP2 is not set
+CONFIG_ARCH_OMAP3=y
+# CONFIG_ARCH_OMAP4 is not set
+
+#
+# OMAP Feature Selections
+#
+# CONFIG_OMAP_DEBUG_POWERDOMAIN is not set
+# CONFIG_OMAP_DEBUG_CLOCKDOMAIN is not set
+CONFIG_OMAP_RESET_CLOCKS=y
+# CONFIG_OMAP_MUX is not set
+CONFIG_OMAP_MCBSP=y
+# CONFIG_OMAP_MBOX_FWK is not set
+# CONFIG_OMAP_MPU_TIMER is not set
+CONFIG_OMAP_32K_TIMER=y
+CONFIG_OMAP_32K_TIMER_HZ=128
+CONFIG_OMAP_DM_TIMER=y
+# CONFIG_OMAP_LL_DEBUG_UART1 is not set
+# CONFIG_OMAP_LL_DEBUG_UART2 is not set
+CONFIG_OMAP_LL_DEBUG_UART3=y
+# CONFIG_OMAP_LL_DEBUG_NONE is not set
+# CONFIG_OMAP_PM_NONE is not set
+CONFIG_OMAP_PM_NOOP=y
+CONFIG_ARCH_OMAP34XX=y
+CONFIG_ARCH_OMAP3430=y
+
+#
+# OMAP Board Type
+#
+# CONFIG_MACH_OMAP3_BEAGLE is not set
+# CONFIG_MACH_OMAP_LDP is not set
+# CONFIG_MACH_OVERO is not set
+# CONFIG_MACH_OMAP3EVM is not set
+# CONFIG_MACH_OMAP3517EVM is not set
+# CONFIG_MACH_OMAP3_PANDORA is not set
+CONFIG_MACH_OMAP3_TOUCHBOOK=y
+# CONFIG_MACH_OMAP_3430SDP is not set
+# CONFIG_MACH_NOKIA_RX51 is not set
+# CONFIG_MACH_OMAP_ZOOM2 is not set
+# CONFIG_MACH_OMAP_ZOOM3 is not set
+# CONFIG_MACH_CM_T35 is not set
+# CONFIG_MACH_IGEP0020 is not set
+# CONFIG_MACH_OMAP_3630SDP is not set
+
+#
+# Processor Type
+#
+CONFIG_CPU_32=y
+CONFIG_CPU_32v6K=y
+CONFIG_CPU_V7=y
+CONFIG_CPU_32v7=y
+CONFIG_CPU_ABRT_EV7=y
+CONFIG_CPU_PABRT_V7=y
+CONFIG_CPU_CACHE_V7=y
+CONFIG_CPU_CACHE_VIPT=y
+CONFIG_CPU_COPY_V6=y
+CONFIG_CPU_TLB_V7=y
+CONFIG_CPU_HAS_ASID=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+
+#
+# Processor Features
+#
+CONFIG_ARM_THUMB=y
+CONFIG_ARM_THUMBEE=y
+# CONFIG_CPU_ICACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_DISABLE is not set
+# CONFIG_CPU_BPREDICT_DISABLE is not set
+CONFIG_HAS_TLS_REG=y
+CONFIG_ARM_L1_CACHE_SHIFT=6
+# CONFIG_ARM_ERRATA_430973 is not set
+# CONFIG_ARM_ERRATA_458693 is not set
+# CONFIG_ARM_ERRATA_460075 is not set
+CONFIG_COMMON_CLKDEV=y
+
+#
+# Bus support
+#
+# CONFIG_PCI_SYSCALL is not set
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+# CONFIG_PCCARD is not set
+
+#
+# Kernel Features
+#
+CONFIG_TICK_ONESHOT=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+CONFIG_VMSPLIT_3G=y
+# CONFIG_VMSPLIT_2G is not set
+# CONFIG_VMSPLIT_1G is not set
+CONFIG_PAGE_OFFSET=0xC0000000
+# CONFIG_PREEMPT_NONE is not set
+# CONFIG_PREEMPT_VOLUNTARY is not set
+CONFIG_PREEMPT=y
+CONFIG_HZ=128
+# CONFIG_THUMB2_KERNEL is not set
+CONFIG_AEABI=y
+# CONFIG_OABI_COMPAT is not set
+# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
+# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
+# CONFIG_HIGHMEM is not set
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_SPLIT_PTLOCK_CPUS=4
+# CONFIG_PHYS_ADDR_T_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=0
+CONFIG_VIRT_TO_BUS=y
+CONFIG_HAVE_MLOCK=y
+CONFIG_HAVE_MLOCKED_PAGE_BIT=y
+# CONFIG_KSM is not set
+CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
+CONFIG_LEDS=y
+CONFIG_ALIGNMENT_TRAP=y
+# CONFIG_UACCESS_WITH_MEMCPY is not set
+
+#
+# Boot options
+#
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_CMDLINE=" debug "
+# CONFIG_XIP_KERNEL is not set
+CONFIG_KEXEC=y
+CONFIG_ATAGS_PROC=y
+
+#
+# CPU Power Management
+#
+# CONFIG_CPU_FREQ is not set
+# CONFIG_CPU_IDLE is not set
+
+#
+# Floating point emulation
+#
+
+#
+# At least one emulation must be selected
+#
+CONFIG_VFP=y
+CONFIG_VFPv3=y
+CONFIG_NEON=y
+
+#
+# Userspace binary formats
+#
+CONFIG_BINFMT_ELF=y
+CONFIG_HAVE_AOUT=y
+CONFIG_BINFMT_AOUT=m
+CONFIG_BINFMT_MISC=y
+
+#
+# Power management options
+#
+CONFIG_PM=y
+CONFIG_PM_DEBUG=y
+# CONFIG_PM_VERBOSE is not set
+CONFIG_CAN_PM_TRACE=y
+CONFIG_PM_SLEEP=y
+CONFIG_SUSPEND=y
+# CONFIG_PM_TEST_SUSPEND is not set
+CONFIG_SUSPEND_FREEZER=y
+# CONFIG_APM_EMULATION is not set
+# CONFIG_PM_RUNTIME is not set
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+CONFIG_PACKET_MMAP=y
+CONFIG_UNIX=y
+CONFIG_XFRM=y
+# CONFIG_XFRM_USER is not set
+# CONFIG_XFRM_SUB_POLICY is not set
+# CONFIG_XFRM_MIGRATE is not set
+# CONFIG_XFRM_STATISTICS is not set
+CONFIG_XFRM_IPCOMP=m
+CONFIG_NET_KEY=y
+# CONFIG_NET_KEY_MIGRATE is not set
+CONFIG_INET=y
+# CONFIG_IP_MULTICAST is not set
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+CONFIG_IP_PNP_RARP=y
+CONFIG_NET_IPIP=m
+CONFIG_NET_IPGRE=m
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
+CONFIG_INET_AH=m
+CONFIG_INET_ESP=m
+CONFIG_INET_IPCOMP=m
+CONFIG_INET_XFRM_TUNNEL=m
+CONFIG_INET_TUNNEL=m
+CONFIG_INET_XFRM_MODE_TRANSPORT=y
+CONFIG_INET_XFRM_MODE_TUNNEL=y
+CONFIG_INET_XFRM_MODE_BEET=y
+CONFIG_INET_LRO=y
+CONFIG_INET_DIAG=m
+CONFIG_INET_TCP_DIAG=m
+CONFIG_TCP_CONG_ADVANCED=y
+CONFIG_TCP_CONG_BIC=m
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_TCP_CONG_WESTWOOD=m
+CONFIG_TCP_CONG_HTCP=m
+CONFIG_TCP_CONG_HSTCP=m
+CONFIG_TCP_CONG_HYBLA=m
+CONFIG_TCP_CONG_VEGAS=m
+CONFIG_TCP_CONG_SCALABLE=m
+CONFIG_TCP_CONG_LP=m
+CONFIG_TCP_CONG_VENO=m
+CONFIG_TCP_CONG_YEAH=m
+CONFIG_TCP_CONG_ILLINOIS=m
+# CONFIG_DEFAULT_BIC is not set
+CONFIG_DEFAULT_CUBIC=y
+# CONFIG_DEFAULT_HTCP is not set
+# CONFIG_DEFAULT_VEGAS is not set
+# CONFIG_DEFAULT_WESTWOOD is not set
+# CONFIG_DEFAULT_RENO is not set
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+CONFIG_IPV6=m
+# CONFIG_IPV6_PRIVACY is not set
+# CONFIG_IPV6_ROUTER_PREF is not set
+# CONFIG_IPV6_OPTIMISTIC_DAD is not set
+CONFIG_INET6_AH=m
+CONFIG_INET6_ESP=m
+CONFIG_INET6_IPCOMP=m
+CONFIG_IPV6_MIP6=m
+CONFIG_INET6_XFRM_TUNNEL=m
+CONFIG_INET6_TUNNEL=m
+CONFIG_INET6_XFRM_MODE_TRANSPORT=m
+CONFIG_INET6_XFRM_MODE_TUNNEL=m
+CONFIG_INET6_XFRM_MODE_BEET=m
+CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION=m
+CONFIG_IPV6_SIT=m
+CONFIG_IPV6_NDISC_NODETYPE=y
+CONFIG_IPV6_TUNNEL=m
+CONFIG_IPV6_MULTIPLE_TABLES=y
+CONFIG_IPV6_SUBTREES=y
+CONFIG_IPV6_MROUTE=y
+# CONFIG_IPV6_PIMSM_V2 is not set
+# CONFIG_NETWORK_SECMARK is not set
+CONFIG_NETFILTER=y
+# CONFIG_NETFILTER_DEBUG is not set
+CONFIG_NETFILTER_ADVANCED=y
+CONFIG_BRIDGE_NETFILTER=y
+
+#
+# Core Netfilter Configuration
+#
+CONFIG_NETFILTER_NETLINK=m
+CONFIG_NETFILTER_NETLINK_QUEUE=m
+CONFIG_NETFILTER_NETLINK_LOG=m
+CONFIG_NF_CONNTRACK=m
+CONFIG_NF_CT_ACCT=y
+CONFIG_NF_CONNTRACK_MARK=y
+CONFIG_NF_CONNTRACK_EVENTS=y
+CONFIG_NF_CT_PROTO_DCCP=m
+CONFIG_NF_CT_PROTO_GRE=m
+CONFIG_NF_CT_PROTO_SCTP=m
+CONFIG_NF_CT_PROTO_UDPLITE=m
+CONFIG_NF_CONNTRACK_AMANDA=m
+CONFIG_NF_CONNTRACK_FTP=m
+CONFIG_NF_CONNTRACK_H323=m
+CONFIG_NF_CONNTRACK_IRC=m
+CONFIG_NF_CONNTRACK_NETBIOS_NS=m
+CONFIG_NF_CONNTRACK_PPTP=m
+CONFIG_NF_CONNTRACK_SANE=m
+CONFIG_NF_CONNTRACK_SIP=m
+CONFIG_NF_CONNTRACK_TFTP=m
+CONFIG_NF_CT_NETLINK=m
+# CONFIG_NETFILTER_TPROXY is not set
+CONFIG_NETFILTER_XTABLES=m
+CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m
+CONFIG_NETFILTER_XT_TARGET_CONNMARK=m
+# CONFIG_NETFILTER_XT_TARGET_DSCP is not set
+CONFIG_NETFILTER_XT_TARGET_HL=m
+# CONFIG_NETFILTER_XT_TARGET_LED is not set
+CONFIG_NETFILTER_XT_TARGET_MARK=m
+CONFIG_NETFILTER_XT_TARGET_NFLOG=m
+CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m
+# CONFIG_NETFILTER_XT_TARGET_NOTRACK is not set
+CONFIG_NETFILTER_XT_TARGET_RATEEST=m
+# CONFIG_NETFILTER_XT_TARGET_TRACE is not set
+CONFIG_NETFILTER_XT_TARGET_TCPMSS=m
+# CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP is not set
+# CONFIG_NETFILTER_XT_MATCH_CLUSTER is not set
+CONFIG_NETFILTER_XT_MATCH_COMMENT=m
+CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m
+CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m
+CONFIG_NETFILTER_XT_MATCH_CONNMARK=m
+CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
+CONFIG_NETFILTER_XT_MATCH_DCCP=m
+CONFIG_NETFILTER_XT_MATCH_DSCP=m
+CONFIG_NETFILTER_XT_MATCH_ESP=m
+CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m
+CONFIG_NETFILTER_XT_MATCH_HELPER=m
+CONFIG_NETFILTER_XT_MATCH_HL=m
+CONFIG_NETFILTER_XT_MATCH_IPRANGE=m
+CONFIG_NETFILTER_XT_MATCH_LENGTH=m
+CONFIG_NETFILTER_XT_MATCH_LIMIT=m
+CONFIG_NETFILTER_XT_MATCH_MAC=m
+CONFIG_NETFILTER_XT_MATCH_MARK=m
+CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m
+CONFIG_NETFILTER_XT_MATCH_OWNER=m
+CONFIG_NETFILTER_XT_MATCH_POLICY=m
+# CONFIG_NETFILTER_XT_MATCH_PHYSDEV is not set
+CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m
+CONFIG_NETFILTER_XT_MATCH_QUOTA=m
+CONFIG_NETFILTER_XT_MATCH_RATEEST=m
+CONFIG_NETFILTER_XT_MATCH_REALM=m
+CONFIG_NETFILTER_XT_MATCH_RECENT=m
+# CONFIG_NETFILTER_XT_MATCH_RECENT_PROC_COMPAT is not set
+CONFIG_NETFILTER_XT_MATCH_SCTP=m
+CONFIG_NETFILTER_XT_MATCH_STATE=m
+CONFIG_NETFILTER_XT_MATCH_STATISTIC=m
+CONFIG_NETFILTER_XT_MATCH_STRING=m
+CONFIG_NETFILTER_XT_MATCH_TCPMSS=m
+CONFIG_NETFILTER_XT_MATCH_TIME=m
+CONFIG_NETFILTER_XT_MATCH_U32=m
+# CONFIG_NETFILTER_XT_MATCH_OSF is not set
+CONFIG_IP_VS=m
+CONFIG_IP_VS_IPV6=y
+CONFIG_IP_VS_DEBUG=y
+CONFIG_IP_VS_TAB_BITS=12
+
+#
+# IPVS transport protocol load balancing support
+#
+CONFIG_IP_VS_PROTO_TCP=y
+CONFIG_IP_VS_PROTO_UDP=y
+CONFIG_IP_VS_PROTO_AH_ESP=y
+CONFIG_IP_VS_PROTO_ESP=y
+CONFIG_IP_VS_PROTO_AH=y
+
+#
+# IPVS scheduler
+#
+CONFIG_IP_VS_RR=m
+CONFIG_IP_VS_WRR=m
+CONFIG_IP_VS_LC=m
+CONFIG_IP_VS_WLC=m
+CONFIG_IP_VS_LBLC=m
+CONFIG_IP_VS_LBLCR=m
+CONFIG_IP_VS_DH=m
+CONFIG_IP_VS_SH=m
+CONFIG_IP_VS_SED=m
+CONFIG_IP_VS_NQ=m
+
+#
+# IPVS application helper
+#
+CONFIG_IP_VS_FTP=m
+
+#
+# IP: Netfilter Configuration
+#
+CONFIG_NF_DEFRAG_IPV4=m
+CONFIG_NF_CONNTRACK_IPV4=m
+CONFIG_NF_CONNTRACK_PROC_COMPAT=y
+CONFIG_IP_NF_QUEUE=m
+CONFIG_IP_NF_IPTABLES=m
+CONFIG_IP_NF_MATCH_ADDRTYPE=m
+CONFIG_IP_NF_MATCH_AH=m
+CONFIG_IP_NF_MATCH_ECN=m
+CONFIG_IP_NF_MATCH_TTL=m
+CONFIG_IP_NF_FILTER=m
+CONFIG_IP_NF_TARGET_REJECT=m
+CONFIG_IP_NF_TARGET_LOG=m
+CONFIG_IP_NF_TARGET_ULOG=m
+CONFIG_NF_NAT=m
+CONFIG_NF_NAT_NEEDED=y
+CONFIG_IP_NF_TARGET_MASQUERADE=m
+CONFIG_IP_NF_TARGET_NETMAP=m
+CONFIG_IP_NF_TARGET_REDIRECT=m
+CONFIG_NF_NAT_SNMP_BASIC=m
+CONFIG_NF_NAT_PROTO_DCCP=m
+CONFIG_NF_NAT_PROTO_GRE=m
+CONFIG_NF_NAT_PROTO_UDPLITE=m
+CONFIG_NF_NAT_PROTO_SCTP=m
+CONFIG_NF_NAT_FTP=m
+CONFIG_NF_NAT_IRC=m
+CONFIG_NF_NAT_TFTP=m
+CONFIG_NF_NAT_AMANDA=m
+CONFIG_NF_NAT_PPTP=m
+CONFIG_NF_NAT_H323=m
+CONFIG_NF_NAT_SIP=m
+CONFIG_IP_NF_MANGLE=m
+CONFIG_IP_NF_TARGET_CLUSTERIP=m
+CONFIG_IP_NF_TARGET_ECN=m
+CONFIG_IP_NF_TARGET_TTL=m
+CONFIG_IP_NF_RAW=m
+CONFIG_IP_NF_ARPTABLES=m
+CONFIG_IP_NF_ARPFILTER=m
+CONFIG_IP_NF_ARP_MANGLE=m
+
+#
+# IPv6: Netfilter Configuration
+#
+CONFIG_NF_CONNTRACK_IPV6=m
+CONFIG_IP6_NF_QUEUE=m
+CONFIG_IP6_NF_IPTABLES=m
+CONFIG_IP6_NF_MATCH_AH=m
+CONFIG_IP6_NF_MATCH_EUI64=m
+CONFIG_IP6_NF_MATCH_FRAG=m
+CONFIG_IP6_NF_MATCH_OPTS=m
+CONFIG_IP6_NF_MATCH_HL=m
+CONFIG_IP6_NF_MATCH_IPV6HEADER=m
+CONFIG_IP6_NF_MATCH_MH=m
+CONFIG_IP6_NF_MATCH_RT=m
+CONFIG_IP6_NF_TARGET_HL=m
+CONFIG_IP6_NF_TARGET_LOG=m
+CONFIG_IP6_NF_FILTER=m
+CONFIG_IP6_NF_TARGET_REJECT=m
+CONFIG_IP6_NF_MANGLE=m
+CONFIG_IP6_NF_RAW=m
+# CONFIG_BRIDGE_NF_EBTABLES is not set
+CONFIG_IP_DCCP=m
+CONFIG_INET_DCCP_DIAG=m
+
+#
+# DCCP CCIDs Configuration (EXPERIMENTAL)
+#
+# CONFIG_IP_DCCP_CCID2_DEBUG is not set
+CONFIG_IP_DCCP_CCID3=y
+# CONFIG_IP_DCCP_CCID3_DEBUG is not set
+CONFIG_IP_DCCP_CCID3_RTO=100
+CONFIG_IP_DCCP_TFRC_LIB=y
+
+#
+# DCCP Kernel Hacking
+#
+# CONFIG_IP_DCCP_DEBUG is not set
+CONFIG_IP_SCTP=m
+# CONFIG_SCTP_DBG_MSG is not set
+# CONFIG_SCTP_DBG_OBJCNT is not set
+# CONFIG_SCTP_HMAC_NONE is not set
+# CONFIG_SCTP_HMAC_SHA1 is not set
+CONFIG_SCTP_HMAC_MD5=y
+# CONFIG_RDS is not set
+CONFIG_TIPC=m
+# CONFIG_TIPC_ADVANCED is not set
+# CONFIG_TIPC_DEBUG is not set
+CONFIG_ATM=m
+CONFIG_ATM_CLIP=m
+# CONFIG_ATM_CLIP_NO_ICMP is not set
+CONFIG_ATM_LANE=m
+CONFIG_ATM_MPOA=m
+CONFIG_ATM_BR2684=m
+# CONFIG_ATM_BR2684_IPFILTER is not set
+CONFIG_STP=m
+CONFIG_GARP=m
+CONFIG_BRIDGE=m
+# CONFIG_NET_DSA is not set
+CONFIG_VLAN_8021Q=m
+CONFIG_VLAN_8021Q_GVRP=y
+# CONFIG_DECNET is not set
+CONFIG_LLC=m
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+CONFIG_WAN_ROUTER=m
+# CONFIG_PHONET is not set
+# CONFIG_IEEE802154 is not set
+CONFIG_NET_SCHED=y
+
+#
+# Queueing/Scheduling
+#
+CONFIG_NET_SCH_CBQ=m
+CONFIG_NET_SCH_HTB=m
+CONFIG_NET_SCH_HFSC=m
+CONFIG_NET_SCH_ATM=m
+CONFIG_NET_SCH_PRIO=m
+CONFIG_NET_SCH_MULTIQ=m
+CONFIG_NET_SCH_RED=m
+CONFIG_NET_SCH_SFQ=m
+CONFIG_NET_SCH_TEQL=m
+CONFIG_NET_SCH_TBF=m
+CONFIG_NET_SCH_GRED=m
+CONFIG_NET_SCH_DSMARK=m
+CONFIG_NET_SCH_NETEM=m
+CONFIG_NET_SCH_DRR=m
+
+#
+# Classification
+#
+CONFIG_NET_CLS=y
+CONFIG_NET_CLS_BASIC=m
+CONFIG_NET_CLS_TCINDEX=m
+CONFIG_NET_CLS_ROUTE4=m
+CONFIG_NET_CLS_ROUTE=y
+CONFIG_NET_CLS_FW=m
+CONFIG_NET_CLS_U32=m
+CONFIG_CLS_U32_PERF=y
+CONFIG_CLS_U32_MARK=y
+CONFIG_NET_CLS_RSVP=m
+CONFIG_NET_CLS_RSVP6=m
+CONFIG_NET_CLS_FLOW=m
+# CONFIG_NET_EMATCH is not set
+# CONFIG_NET_CLS_ACT is not set
+CONFIG_NET_CLS_IND=y
+CONFIG_NET_SCH_FIFO=y
+# CONFIG_DCB is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_NET_DROP_MONITOR is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
+# CONFIG_IRDA is not set
+CONFIG_BT=y
+CONFIG_BT_L2CAP=y
+CONFIG_BT_SCO=y
+CONFIG_BT_RFCOMM=y
+CONFIG_BT_RFCOMM_TTY=y
+CONFIG_BT_BNEP=y
+CONFIG_BT_BNEP_MC_FILTER=y
+CONFIG_BT_BNEP_PROTO_FILTER=y
+CONFIG_BT_HIDP=y
+
+#
+# Bluetooth device drivers
+#
+CONFIG_BT_HCIBTUSB=y
+CONFIG_BT_HCIBTSDIO=y
+CONFIG_BT_HCIUART=y
+CONFIG_BT_HCIUART_H4=y
+CONFIG_BT_HCIUART_BCSP=y
+CONFIG_BT_HCIUART_LL=y
+CONFIG_BT_HCIBCM203X=y
+CONFIG_BT_HCIBPA10X=y
+CONFIG_BT_HCIBFUSB=y
+# CONFIG_BT_HCIVHCI is not set
+# CONFIG_BT_MRVL is not set
+CONFIG_AF_RXRPC=m
+# CONFIG_AF_RXRPC_DEBUG is not set
+# CONFIG_RXKAD is not set
+CONFIG_FIB_RULES=y
+CONFIG_WIRELESS=y
+CONFIG_CFG80211=m
+# CONFIG_NL80211_TESTMODE is not set
+# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set
+# CONFIG_CFG80211_REG_DEBUG is not set
+CONFIG_CFG80211_DEFAULT_PS=y
+CONFIG_CFG80211_DEFAULT_PS_VALUE=1
+# CONFIG_CFG80211_DEBUGFS is not set
+# CONFIG_WIRELESS_OLD_REGULATORY is not set
+CONFIG_WIRELESS_EXT=y
+CONFIG_WIRELESS_EXT_SYSFS=y
+CONFIG_LIB80211=y
+# CONFIG_LIB80211_DEBUG is not set
+CONFIG_MAC80211=m
+CONFIG_MAC80211_RC_PID=y
+# CONFIG_MAC80211_RC_MINSTREL is not set
+CONFIG_MAC80211_RC_DEFAULT_PID=y
+# CONFIG_MAC80211_RC_DEFAULT_MINSTREL is not set
+CONFIG_MAC80211_RC_DEFAULT="pid"
+# CONFIG_MAC80211_MESH is not set
+# CONFIG_MAC80211_LEDS is not set
+# CONFIG_MAC80211_DEBUGFS is not set
+# CONFIG_MAC80211_DEBUG_MENU is not set
+CONFIG_WIMAX=m
+CONFIG_WIMAX_DEBUG_LEVEL=8
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+# CONFIG_DEVTMPFS is not set
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+CONFIG_FW_LOADER=y
+CONFIG_FIRMWARE_IN_KERNEL=y
+CONFIG_EXTRA_FIRMWARE=""
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
+# CONFIG_SYS_HYPERVISOR is not set
+# CONFIG_CONNECTOR is not set
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+# CONFIG_MTD_TESTS is not set
+CONFIG_MTD_CONCAT=y
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_REDBOOT_PARTS is not set
+# CONFIG_MTD_CMDLINE_PARTS is not set
+# CONFIG_MTD_AFS_PARTS is not set
+# CONFIG_MTD_AR7_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+# CONFIG_MTD_CFI is not set
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+# CONFIG_MTD_PLATRAM is not set
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_DATAFLASH is not set
+# CONFIG_MTD_M25P80 is not set
+# CONFIG_MTD_SST25L is not set
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+CONFIG_MTD_NAND=y
+# CONFIG_MTD_NAND_VERIFY_WRITE is not set
+# CONFIG_MTD_NAND_ECC_SMC is not set
+# CONFIG_MTD_NAND_MUSEUM_IDS is not set
+# CONFIG_MTD_NAND_GPIO is not set
+CONFIG_MTD_NAND_OMAP2=y
+CONFIG_MTD_NAND_OMAP_PREFETCH=y
+# CONFIG_MTD_NAND_OMAP_PREFETCH_DMA is not set
+CONFIG_MTD_NAND_IDS=y
+# CONFIG_MTD_NAND_DISKONCHIP is not set
+# CONFIG_MTD_NAND_NANDSIM is not set
+CONFIG_MTD_NAND_PLATFORM=y
+# CONFIG_MTD_ALAUDA is not set
+# CONFIG_MTD_ONENAND is not set
+
+#
+# LPDDR flash memory drivers
+#
+# CONFIG_MTD_LPDDR is not set
+
+#
+# UBI - Unsorted block images
+#
+CONFIG_MTD_UBI=y
+CONFIG_MTD_UBI_WL_THRESHOLD=4096
+CONFIG_MTD_UBI_BEB_RESERVE=1
+# CONFIG_MTD_UBI_GLUEBI is not set
+
+#
+# UBI debugging options
+#
+# CONFIG_MTD_UBI_DEBUG is not set
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_CRYPTOLOOP=m
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_UB is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=16384
+# CONFIG_BLK_DEV_XIP is not set
+CONFIG_CDROM_PKTCDVD=m
+CONFIG_CDROM_PKTCDVD_BUFFERS=8
+# CONFIG_CDROM_PKTCDVD_WCACHE is not set
+# CONFIG_ATA_OVER_ETH is not set
+# CONFIG_MG_DISK is not set
+CONFIG_MISC_DEVICES=y
+# CONFIG_ICS932S401 is not set
+# CONFIG_ENCLOSURE_SERVICES is not set
+# CONFIG_ISL29003 is not set
+# CONFIG_C2PORT is not set
+
+#
+# EEPROM support
+#
+# CONFIG_EEPROM_AT24 is not set
+# CONFIG_EEPROM_AT25 is not set
+# CONFIG_EEPROM_LEGACY is not set
+# CONFIG_EEPROM_MAX6875 is not set
+CONFIG_EEPROM_93CX6=y
+CONFIG_HAVE_IDE=y
+# CONFIG_IDE is not set
+
+#
+# SCSI device support
+#
+CONFIG_RAID_ATTRS=m
+CONFIG_SCSI=y
+CONFIG_SCSI_DMA=y
+# CONFIG_SCSI_TGT is not set
+# CONFIG_SCSI_NETLINK is not set
+CONFIG_SCSI_PROC_FS=y
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+CONFIG_BLK_DEV_SR=y
+CONFIG_BLK_DEV_SR_VENDOR=y
+CONFIG_CHR_DEV_SG=y
+CONFIG_CHR_DEV_SCH=m
+CONFIG_SCSI_MULTI_LUN=y
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+# CONFIG_SCSI_SCAN_ASYNC is not set
+CONFIG_SCSI_WAIT_SCAN=m
+
+#
+# SCSI Transports
+#
+# CONFIG_SCSI_SPI_ATTRS is not set
+# CONFIG_SCSI_FC_ATTRS is not set
+CONFIG_SCSI_ISCSI_ATTRS=m
+# CONFIG_SCSI_SAS_LIBSAS is not set
+# CONFIG_SCSI_SRP_ATTRS is not set
+CONFIG_SCSI_LOWLEVEL=y
+CONFIG_ISCSI_TCP=m
+# CONFIG_LIBFC is not set
+# CONFIG_LIBFCOE is not set
+# CONFIG_SCSI_DEBUG is not set
+# CONFIG_SCSI_DH is not set
+# CONFIG_SCSI_OSD_INITIATOR is not set
+# CONFIG_ATA is not set
+CONFIG_MD=y
+CONFIG_BLK_DEV_MD=m
+CONFIG_MD_LINEAR=m
+CONFIG_MD_RAID0=m
+CONFIG_MD_RAID1=m
+CONFIG_MD_RAID10=m
+CONFIG_MD_RAID456=m
+CONFIG_MD_RAID6_PQ=m
+# CONFIG_ASYNC_RAID6_TEST is not set
+CONFIG_MD_MULTIPATH=m
+CONFIG_MD_FAULTY=m
+CONFIG_BLK_DEV_DM=m
+# CONFIG_DM_DEBUG is not set
+CONFIG_DM_CRYPT=m
+CONFIG_DM_SNAPSHOT=m
+CONFIG_DM_MIRROR=m
+# CONFIG_DM_LOG_USERSPACE is not set
+CONFIG_DM_ZERO=m
+CONFIG_DM_MULTIPATH=m
+# CONFIG_DM_MULTIPATH_QL is not set
+# CONFIG_DM_MULTIPATH_ST is not set
+CONFIG_DM_DELAY=m
+# CONFIG_DM_UEVENT is not set
+CONFIG_NETDEVICES=y
+CONFIG_DUMMY=m
+CONFIG_BONDING=m
+CONFIG_MACVLAN=m
+CONFIG_EQUALIZER=m
+CONFIG_TUN=m
+CONFIG_VETH=m
+# CONFIG_NET_ETHERNET is not set
+# CONFIG_NETDEV_1000 is not set
+# CONFIG_NETDEV_10000 is not set
+CONFIG_WLAN=y
+# CONFIG_WLAN_PRE80211 is not set
+CONFIG_WLAN_80211=y
+# CONFIG_LIBERTAS is not set
+# CONFIG_LIBERTAS_THINFIRM is not set
+# CONFIG_AT76C50X_USB is not set
+# CONFIG_USB_ZD1201 is not set
+# CONFIG_USB_NET_RNDIS_WLAN is not set
+# CONFIG_RTL8187 is not set
+# CONFIG_MAC80211_HWSIM is not set
+# CONFIG_P54_COMMON is not set
+# CONFIG_ATH_COMMON is not set
+# CONFIG_HOSTAP is not set
+# CONFIG_B43 is not set
+# CONFIG_B43LEGACY is not set
+# CONFIG_ZD1211RW is not set
+# CONFIG_RT2X00 is not set
+# CONFIG_WL12XX is not set
+# CONFIG_IWM is not set
+
+#
+# WiMAX Wireless Broadband devices
+#
+# CONFIG_WIMAX_I2400M_USB is not set
+# CONFIG_WIMAX_I2400M_SDIO is not set
+
+#
+# USB Network Adapters
+#
+# CONFIG_USB_CATC is not set
+# CONFIG_USB_KAWETH is not set
+# CONFIG_USB_PEGASUS is not set
+# CONFIG_USB_RTL8150 is not set
+# CONFIG_USB_USBNET is not set
+# CONFIG_WAN is not set
+# CONFIG_ATM_DRIVERS is not set
+CONFIG_PPP=m
+CONFIG_PPP_MULTILINK=y
+CONFIG_PPP_FILTER=y
+CONFIG_PPP_ASYNC=m
+CONFIG_PPP_SYNC_TTY=m
+CONFIG_PPP_DEFLATE=m
+CONFIG_PPP_BSDCOMP=m
+CONFIG_PPP_MPPE=m
+CONFIG_PPPOE=m
+# CONFIG_PPPOATM is not set
+CONFIG_PPPOL2TP=m
+# CONFIG_SLIP is not set
+CONFIG_SLHC=m
+CONFIG_NETCONSOLE=m
+CONFIG_NETCONSOLE_DYNAMIC=y
+CONFIG_NETPOLL=y
+CONFIG_NETPOLL_TRAP=y
+CONFIG_NET_POLL_CONTROLLER=y
+# CONFIG_ISDN is not set
+# CONFIG_PHONE is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+CONFIG_INPUT_FF_MEMLESS=y
+# CONFIG_INPUT_POLLDEV is not set
+
+#
+# Userland interfaces
+#
+CONFIG_INPUT_MOUSEDEV=y
+CONFIG_INPUT_MOUSEDEV_PSAUX=y
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+# CONFIG_INPUT_JOYDEV is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input Device Drivers
+#
+CONFIG_INPUT_KEYBOARD=y
+# CONFIG_KEYBOARD_ADP5588 is not set
+# CONFIG_KEYBOARD_ATKBD is not set
+# CONFIG_QT2160 is not set
+# CONFIG_KEYBOARD_LKKBD is not set
+CONFIG_KEYBOARD_GPIO=y
+# CONFIG_KEYBOARD_MATRIX is not set
+# CONFIG_KEYBOARD_LM8323 is not set
+# CONFIG_KEYBOARD_MAX7359 is not set
+# CONFIG_KEYBOARD_NEWTON is not set
+# CONFIG_KEYBOARD_OPENCORES is not set
+# CONFIG_KEYBOARD_STOWAWAY is not set
+# CONFIG_KEYBOARD_SUNKBD is not set
+# CONFIG_KEYBOARD_TWL4030 is not set
+# CONFIG_KEYBOARD_XTKBD is not set
+CONFIG_INPUT_MOUSE=y
+CONFIG_MOUSE_PS2=y
+CONFIG_MOUSE_PS2_ALPS=y
+CONFIG_MOUSE_PS2_LOGIPS2PP=y
+CONFIG_MOUSE_PS2_SYNAPTICS=y
+CONFIG_MOUSE_PS2_TRACKPOINT=y
+# CONFIG_MOUSE_PS2_ELANTECH is not set
+# CONFIG_MOUSE_PS2_SENTELIC is not set
+# CONFIG_MOUSE_PS2_TOUCHKIT is not set
+# CONFIG_MOUSE_SERIAL is not set
+# CONFIG_MOUSE_APPLETOUCH is not set
+# CONFIG_MOUSE_BCM5974 is not set
+# CONFIG_MOUSE_VSXXXAA is not set
+# CONFIG_MOUSE_GPIO is not set
+# CONFIG_MOUSE_SYNAPTICS_I2C is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+CONFIG_INPUT_TOUCHSCREEN=y
+CONFIG_TOUCHSCREEN_ADS7846=y
+# CONFIG_TOUCHSCREEN_AD7877 is not set
+# CONFIG_TOUCHSCREEN_AD7879_I2C is not set
+# CONFIG_TOUCHSCREEN_AD7879_SPI is not set
+# CONFIG_TOUCHSCREEN_AD7879 is not set
+# CONFIG_TOUCHSCREEN_EETI is not set
+# CONFIG_TOUCHSCREEN_FUJITSU is not set
+# CONFIG_TOUCHSCREEN_GUNZE is not set
+# CONFIG_TOUCHSCREEN_ELO is not set
+# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set
+# CONFIG_TOUCHSCREEN_MCS5000 is not set
+# CONFIG_TOUCHSCREEN_MTOUCH is not set
+# CONFIG_TOUCHSCREEN_INEXIO is not set
+# CONFIG_TOUCHSCREEN_MK712 is not set
+# CONFIG_TOUCHSCREEN_PENMOUNT is not set
+# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
+# CONFIG_TOUCHSCREEN_TOUCHWIN is not set
+# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set
+# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set
+# CONFIG_TOUCHSCREEN_TSC2007 is not set
+# CONFIG_TOUCHSCREEN_W90X900 is not set
+CONFIG_INPUT_MISC=y
+# CONFIG_INPUT_ATI_REMOTE is not set
+# CONFIG_INPUT_ATI_REMOTE2 is not set
+# CONFIG_INPUT_KEYSPAN_REMOTE is not set
+# CONFIG_INPUT_POWERMATE is not set
+# CONFIG_INPUT_YEALINK is not set
+# CONFIG_INPUT_CM109 is not set
+CONFIG_INPUT_TWL4030_PWRBUTTON=y
+CONFIG_INPUT_UINPUT=y
+# CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set
+
+#
+# Hardware I/O ports
+#
+CONFIG_SERIO=y
+CONFIG_SERIO_SERPORT=y
+CONFIG_SERIO_LIBPS2=y
+# CONFIG_SERIO_RAW is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+CONFIG_VT_HW_CONSOLE_BINDING=y
+CONFIG_DEVKMEM=y
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_NR_UARTS=32
+CONFIG_SERIAL_8250_RUNTIME_UARTS=4
+CONFIG_SERIAL_8250_EXTENDED=y
+CONFIG_SERIAL_8250_MANY_PORTS=y
+CONFIG_SERIAL_8250_SHARE_IRQ=y
+CONFIG_SERIAL_8250_DETECT_IRQ=y
+CONFIG_SERIAL_8250_RSA=y
+
+#
+# Non-8250 serial port support
+#
+# CONFIG_SERIAL_MAX3100 is not set
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_UNIX98_PTYS=y
+# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
+# CONFIG_LEGACY_PTYS is not set
+# CONFIG_IPMI_HANDLER is not set
+CONFIG_HW_RANDOM=y
+# CONFIG_HW_RANDOM_TIMERIOMEM is not set
+# CONFIG_R3964 is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_COMPAT=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_HELPER_AUTO=y
+
+#
+# I2C Hardware Bus support
+#
+
+#
+# I2C system bus drivers (mostly embedded / system-on-chip)
+#
+# CONFIG_I2C_DESIGNWARE is not set
+# CONFIG_I2C_GPIO is not set
+# CONFIG_I2C_OCORES is not set
+CONFIG_I2C_OMAP=y
+# CONFIG_I2C_SIMTEC is not set
+
+#
+# External I2C/SMBus adapter drivers
+#
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_TAOS_EVM is not set
+# CONFIG_I2C_TINY_USB is not set
+
+#
+# Other I2C/SMBus bus drivers
+#
+# CONFIG_I2C_PCA_PLATFORM is not set
+# CONFIG_I2C_STUB is not set
+
+#
+# Miscellaneous I2C Chip support
+#
+# CONFIG_DS1682 is not set
+# CONFIG_SENSORS_TSL2550 is not set
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+# CONFIG_I2C_DEBUG_CHIP is not set
+CONFIG_SPI=y
+# CONFIG_SPI_DEBUG is not set
+CONFIG_SPI_MASTER=y
+
+#
+# SPI Master Controller Drivers
+#
+# CONFIG_SPI_BITBANG is not set
+# CONFIG_SPI_GPIO is not set
+CONFIG_SPI_OMAP24XX=y
+
+#
+# SPI Protocol Masters
+#
+CONFIG_SPI_SPIDEV=y
+# CONFIG_SPI_TLE62X0 is not set
+
+#
+# PPS support
+#
+# CONFIG_PPS is not set
+CONFIG_ARCH_REQUIRE_GPIOLIB=y
+CONFIG_GPIOLIB=y
+# CONFIG_DEBUG_GPIO is not set
+CONFIG_GPIO_SYSFS=y
+
+#
+# Memory mapped GPIO expanders:
+#
+
+#
+# I2C GPIO expanders:
+#
+# CONFIG_GPIO_MAX732X is not set
+# CONFIG_GPIO_PCA953X is not set
+# CONFIG_GPIO_PCF857X is not set
+CONFIG_GPIO_TWL4030=y
+
+#
+# PCI GPIO expanders:
+#
+
+#
+# SPI GPIO expanders:
+#
+# CONFIG_GPIO_MAX7301 is not set
+# CONFIG_GPIO_MCP23S08 is not set
+# CONFIG_GPIO_MC33880 is not set
+
+#
+# AC97 GPIO expanders:
+#
+# CONFIG_W1 is not set
+CONFIG_POWER_SUPPLY=y
+# CONFIG_POWER_SUPPLY_DEBUG is not set
+# CONFIG_PDA_POWER is not set
+# CONFIG_BATTERY_DS2760 is not set
+# CONFIG_BATTERY_DS2782 is not set
+CONFIG_BATTERY_BQ27x00=y
+# CONFIG_BATTERY_MAX17040 is not set
+CONFIG_HWMON=y
+# CONFIG_HWMON_VID is not set
+# CONFIG_HWMON_DEBUG_CHIP is not set
+
+#
+# Native drivers
+#
+# CONFIG_SENSORS_AD7414 is not set
+# CONFIG_SENSORS_AD7418 is not set
+# CONFIG_SENSORS_ADCXX is not set
+# CONFIG_SENSORS_ADM1021 is not set
+# CONFIG_SENSORS_ADM1025 is not set
+# CONFIG_SENSORS_ADM1026 is not set
+# CONFIG_SENSORS_ADM1029 is not set
+# CONFIG_SENSORS_ADM1031 is not set
+# CONFIG_SENSORS_ADM9240 is not set
+# CONFIG_SENSORS_ADT7462 is not set
+# CONFIG_SENSORS_ADT7470 is not set
+# CONFIG_SENSORS_ADT7473 is not set
+# CONFIG_SENSORS_ADT7475 is not set
+# CONFIG_SENSORS_ATXP1 is not set
+# CONFIG_SENSORS_DS1621 is not set
+# CONFIG_SENSORS_F71805F is not set
+# CONFIG_SENSORS_F71882FG is not set
+# CONFIG_SENSORS_F75375S is not set
+# CONFIG_SENSORS_G760A is not set
+# CONFIG_SENSORS_GL518SM is not set
+# CONFIG_SENSORS_GL520SM is not set
+# CONFIG_SENSORS_IT87 is not set
+# CONFIG_SENSORS_LM63 is not set
+# CONFIG_SENSORS_LM70 is not set
+# CONFIG_SENSORS_LM75 is not set
+# CONFIG_SENSORS_LM77 is not set
+# CONFIG_SENSORS_LM78 is not set
+# CONFIG_SENSORS_LM80 is not set
+# CONFIG_SENSORS_LM83 is not set
+# CONFIG_SENSORS_LM85 is not set
+# CONFIG_SENSORS_LM87 is not set
+# CONFIG_SENSORS_LM90 is not set
+# CONFIG_SENSORS_LM92 is not set
+# CONFIG_SENSORS_LM93 is not set
+# CONFIG_SENSORS_LTC4215 is not set
+# CONFIG_SENSORS_LTC4245 is not set
+# CONFIG_SENSORS_LM95241 is not set
+# CONFIG_SENSORS_MAX1111 is not set
+# CONFIG_SENSORS_MAX1619 is not set
+# CONFIG_SENSORS_MAX6650 is not set
+# CONFIG_SENSORS_PC87360 is not set
+# CONFIG_SENSORS_PC87427 is not set
+# CONFIG_SENSORS_PCF8591 is not set
+# CONFIG_SENSORS_SHT15 is not set
+# CONFIG_SENSORS_DME1737 is not set
+# CONFIG_SENSORS_SMSC47M1 is not set
+# CONFIG_SENSORS_SMSC47M192 is not set
+# CONFIG_SENSORS_SMSC47B397 is not set
+# CONFIG_SENSORS_ADS7828 is not set
+# CONFIG_SENSORS_THMC50 is not set
+# CONFIG_SENSORS_TMP401 is not set
+# CONFIG_SENSORS_TMP421 is not set
+# CONFIG_SENSORS_VT1211 is not set
+# CONFIG_SENSORS_W83781D is not set
+# CONFIG_SENSORS_W83791D is not set
+# CONFIG_SENSORS_W83792D is not set
+# CONFIG_SENSORS_W83793 is not set
+# CONFIG_SENSORS_W83L785TS is not set
+# CONFIG_SENSORS_W83L786NG is not set
+# CONFIG_SENSORS_W83627HF is not set
+# CONFIG_SENSORS_W83627EHF is not set
+# CONFIG_SENSORS_LIS3_SPI is not set
+CONFIG_THERMAL=y
+CONFIG_THERMAL_HWMON=y
+CONFIG_WATCHDOG=y
+CONFIG_WATCHDOG_NOWAYOUT=y
+
+#
+# Watchdog Device Drivers
+#
+# CONFIG_SOFT_WATCHDOG is not set
+CONFIG_OMAP_WATCHDOG=y
+# CONFIG_TWL4030_WATCHDOG is not set
+
+#
+# USB-based Watchdog Cards
+#
+# CONFIG_USBPCWATCHDOG is not set
+CONFIG_SSB_POSSIBLE=y
+
+#
+# Sonics Silicon Backplane
+#
+# CONFIG_SSB is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_CORE is not set
+# CONFIG_MFD_SM501 is not set
+# CONFIG_MFD_ASIC3 is not set
+# CONFIG_HTC_EGPIO is not set
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_TPS65010 is not set
+CONFIG_TWL4030_CORE=y
+# CONFIG_TWL4030_POWER is not set
+# CONFIG_TWL4030_CODEC is not set
+# CONFIG_MFD_TMIO is not set
+# CONFIG_MFD_T7L66XB is not set
+# CONFIG_MFD_TC6387XB is not set
+# CONFIG_MFD_TC6393XB is not set
+# CONFIG_PMIC_DA903X is not set
+# CONFIG_MFD_WM8400 is not set
+# CONFIG_MFD_WM831X is not set
+# CONFIG_MFD_WM8350_I2C is not set
+# CONFIG_MFD_PCF50633 is not set
+# CONFIG_MFD_MC13783 is not set
+# CONFIG_AB3100_CORE is not set
+# CONFIG_EZX_PCAP is not set
+CONFIG_REGULATOR=y
+# CONFIG_REGULATOR_DEBUG is not set
+# CONFIG_REGULATOR_FIXED_VOLTAGE is not set
+# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set
+# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set
+# CONFIG_REGULATOR_BQ24022 is not set
+# CONFIG_REGULATOR_MAX1586 is not set
+CONFIG_REGULATOR_TWL4030=y
+# CONFIG_REGULATOR_LP3971 is not set
+# CONFIG_REGULATOR_TPS65023 is not set
+# CONFIG_REGULATOR_TPS6507X is not set
+# CONFIG_MEDIA_SUPPORT is not set
+
+#
+# Graphics support
+#
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+CONFIG_FB=y
+# CONFIG_FIRMWARE_EDID is not set
+# CONFIG_FB_DDC is not set
+# CONFIG_FB_BOOT_VESA_SUPPORT is not set
+# CONFIG_FB_CFB_FILLRECT is not set
+# CONFIG_FB_CFB_COPYAREA is not set
+# CONFIG_FB_CFB_IMAGEBLIT is not set
+# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
+# CONFIG_FB_SYS_FILLRECT is not set
+# CONFIG_FB_SYS_COPYAREA is not set
+# CONFIG_FB_SYS_IMAGEBLIT is not set
+# CONFIG_FB_FOREIGN_ENDIAN is not set
+# CONFIG_FB_SYS_FOPS is not set
+# CONFIG_FB_SVGALIB is not set
+# CONFIG_FB_MACMODES is not set
+# CONFIG_FB_BACKLIGHT is not set
+# CONFIG_FB_MODE_HELPERS is not set
+# CONFIG_FB_TILEBLITTING is not set
+
+#
+# Frame buffer hardware drivers
+#
+# CONFIG_FB_S1D13XXX is not set
+# CONFIG_FB_VIRTUAL is not set
+# CONFIG_FB_METRONOME is not set
+# CONFIG_FB_MB862XX is not set
+# CONFIG_FB_BROADSHEET is not set
+# CONFIG_FB_OMAP is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+CONFIG_BACKLIGHT_CLASS_DEVICE=y
+CONFIG_BACKLIGHT_GENERIC=y
+
+#
+# Display device support
+#
+CONFIG_DISPLAY_SUPPORT=y
+
+#
+# Display hardware drivers
+#
+
+#
+# Console display driver support
+#
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_DUMMY_CONSOLE=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
+# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
+CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y
+# CONFIG_FONTS is not set
+CONFIG_FONT_8x8=y
+CONFIG_FONT_8x16=y
+CONFIG_LOGO=y
+CONFIG_LOGO_LINUX_MONO=y
+CONFIG_LOGO_LINUX_VGA16=y
+CONFIG_LOGO_LINUX_CLUT224=y
+CONFIG_SOUND=y
+CONFIG_SOUND_OSS_CORE=y
+CONFIG_SOUND_OSS_CORE_PRECLAIM=y
+CONFIG_SND=y
+CONFIG_SND_TIMER=y
+CONFIG_SND_PCM=y
+CONFIG_SND_HWDEP=y
+CONFIG_SND_RAWMIDI=y
+CONFIG_SND_JACK=y
+CONFIG_SND_SEQUENCER=m
+# CONFIG_SND_SEQ_DUMMY is not set
+CONFIG_SND_OSSEMUL=y
+CONFIG_SND_MIXER_OSS=y
+CONFIG_SND_PCM_OSS=y
+CONFIG_SND_PCM_OSS_PLUGINS=y
+CONFIG_SND_SEQUENCER_OSS=y
+CONFIG_SND_HRTIMER=m
+CONFIG_SND_SEQ_HRTIMER_DEFAULT=y
+# CONFIG_SND_DYNAMIC_MINORS is not set
+CONFIG_SND_SUPPORT_OLD_API=y
+CONFIG_SND_VERBOSE_PROCFS=y
+# CONFIG_SND_VERBOSE_PRINTK is not set
+# CONFIG_SND_DEBUG is not set
+CONFIG_SND_RAWMIDI_SEQ=m
+# CONFIG_SND_OPL3_LIB_SEQ is not set
+# CONFIG_SND_OPL4_LIB_SEQ is not set
+# CONFIG_SND_SBAWE_SEQ is not set
+# CONFIG_SND_EMU10K1_SEQ is not set
+CONFIG_SND_DRIVERS=y
+# CONFIG_SND_DUMMY is not set
+# CONFIG_SND_VIRMIDI is not set
+# CONFIG_SND_MTPAV is not set
+# CONFIG_SND_SERIAL_U16550 is not set
+# CONFIG_SND_MPU401 is not set
+# CONFIG_SND_ARM is not set
+CONFIG_SND_SPI=y
+CONFIG_SND_USB=y
+CONFIG_SND_USB_AUDIO=y
+CONFIG_SND_USB_CAIAQ=m
+CONFIG_SND_USB_CAIAQ_INPUT=y
+CONFIG_SND_SOC=y
+CONFIG_SND_OMAP_SOC=y
+CONFIG_SND_SOC_I2C_AND_SPI=y
+# CONFIG_SND_SOC_ALL_CODECS is not set
+# CONFIG_SOUND_PRIME is not set
+CONFIG_HID_SUPPORT=y
+CONFIG_HID=y
+# CONFIG_HIDRAW is not set
+
+#
+# USB Input Devices
+#
+CONFIG_USB_HID=y
+# CONFIG_HID_PID is not set
+# CONFIG_USB_HIDDEV is not set
+
+#
+# Special HID drivers
+#
+# CONFIG_HID_A4TECH is not set
+# CONFIG_HID_APPLE is not set
+# CONFIG_HID_BELKIN is not set
+# CONFIG_HID_CHERRY is not set
+# CONFIG_HID_CHICONY is not set
+# CONFIG_HID_CYPRESS is not set
+# CONFIG_HID_DRAGONRISE is not set
+# CONFIG_HID_EZKEY is not set
+# CONFIG_HID_KYE is not set
+# CONFIG_HID_GYRATION is not set
+# CONFIG_HID_TWINHAN is not set
+# CONFIG_HID_KENSINGTON is not set
+# CONFIG_HID_LOGITECH is not set
+# CONFIG_HID_MICROSOFT is not set
+# CONFIG_HID_MONTEREY is not set
+# CONFIG_HID_NTRIG is not set
+# CONFIG_HID_PANTHERLORD is not set
+# CONFIG_HID_PETALYNX is not set
+# CONFIG_HID_SAMSUNG is not set
+# CONFIG_HID_SONY is not set
+# CONFIG_HID_SUNPLUS is not set
+# CONFIG_HID_GREENASIA is not set
+# CONFIG_HID_SMARTJOYPLUS is not set
+# CONFIG_HID_TOPSEED is not set
+# CONFIG_HID_THRUSTMASTER is not set
+# CONFIG_HID_WACOM is not set
+# CONFIG_HID_ZEROPLUS is not set
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_ARCH_HAS_HCD=y
+CONFIG_USB_ARCH_HAS_OHCI=y
+# CONFIG_USB_ARCH_HAS_EHCI is not set
+CONFIG_USB=y
+# CONFIG_USB_DEBUG is not set
+# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
+
+#
+# Miscellaneous USB options
+#
+CONFIG_USB_DEVICEFS=y
+CONFIG_USB_DEVICE_CLASS=y
+# CONFIG_USB_DYNAMIC_MINORS is not set
+CONFIG_USB_SUSPEND=y
+CONFIG_USB_OTG=y
+# CONFIG_USB_OTG_WHITELIST is not set
+# CONFIG_USB_OTG_BLACKLIST_HUB is not set
+CONFIG_USB_MON=y
+# CONFIG_USB_WUSB is not set
+# CONFIG_USB_WUSB_CBAF is not set
+
+#
+# USB Host Controller Drivers
+#
+# CONFIG_USB_C67X00_HCD is not set
+CONFIG_USB_OXU210HP_HCD=y
+# CONFIG_USB_ISP116X_HCD is not set
+# CONFIG_USB_ISP1760_HCD is not set
+# CONFIG_USB_ISP1362_HCD is not set
+# CONFIG_USB_OHCI_HCD is not set
+# CONFIG_USB_SL811_HCD is not set
+# CONFIG_USB_R8A66597_HCD is not set
+# CONFIG_USB_HWA_HCD is not set
+CONFIG_USB_MUSB_HDRC=y
+CONFIG_USB_MUSB_SOC=y
+
+#
+# OMAP 343x high speed USB support
+#
+# CONFIG_USB_MUSB_HOST is not set
+# CONFIG_USB_MUSB_PERIPHERAL is not set
+CONFIG_USB_MUSB_OTG=y
+CONFIG_USB_GADGET_MUSB_HDRC=y
+CONFIG_USB_MUSB_HDRC_HCD=y
+# CONFIG_MUSB_PIO_ONLY is not set
+CONFIG_USB_INVENTRA_DMA=y
+# CONFIG_USB_TI_CPPI_DMA is not set
+# CONFIG_USB_MUSB_DEBUG is not set
+
+#
+# USB Device Class drivers
+#
+CONFIG_USB_ACM=m
+CONFIG_USB_PRINTER=m
+CONFIG_USB_WDM=m
+CONFIG_USB_TMC=m
+
+#
+# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
+#
+
+#
+# also be needed; see USB_STORAGE Help for more info
+#
+CONFIG_USB_STORAGE=y
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
+# CONFIG_USB_STORAGE_USBAT is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_SDDR55 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_STORAGE_ALAUDA is not set
+# CONFIG_USB_STORAGE_ONETOUCH is not set
+# CONFIG_USB_STORAGE_KARMA is not set
+# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
+# CONFIG_USB_LIBUSUAL is not set
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_MICROTEK is not set
+
+#
+# USB port drivers
+#
+CONFIG_USB_SERIAL=m
+CONFIG_USB_EZUSB=y
+CONFIG_USB_SERIAL_GENERIC=y
+CONFIG_USB_SERIAL_AIRCABLE=m
+CONFIG_USB_SERIAL_ARK3116=m
+CONFIG_USB_SERIAL_BELKIN=m
+CONFIG_USB_SERIAL_CH341=m
+CONFIG_USB_SERIAL_WHITEHEAT=m
+CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m
+# CONFIG_USB_SERIAL_CP210X is not set
+CONFIG_USB_SERIAL_CYPRESS_M8=m
+CONFIG_USB_SERIAL_EMPEG=m
+CONFIG_USB_SERIAL_FTDI_SIO=m
+CONFIG_USB_SERIAL_FUNSOFT=m
+CONFIG_USB_SERIAL_VISOR=m
+CONFIG_USB_SERIAL_IPAQ=m
+CONFIG_USB_SERIAL_IR=m
+CONFIG_USB_SERIAL_EDGEPORT=m
+CONFIG_USB_SERIAL_EDGEPORT_TI=m
+CONFIG_USB_SERIAL_GARMIN=m
+CONFIG_USB_SERIAL_IPW=m
+CONFIG_USB_SERIAL_IUU=m
+CONFIG_USB_SERIAL_KEYSPAN_PDA=m
+CONFIG_USB_SERIAL_KEYSPAN=m
+CONFIG_USB_SERIAL_KEYSPAN_MPR=y
+CONFIG_USB_SERIAL_KEYSPAN_USA28=y
+CONFIG_USB_SERIAL_KEYSPAN_USA28X=y
+CONFIG_USB_SERIAL_KEYSPAN_USA28XA=y
+CONFIG_USB_SERIAL_KEYSPAN_USA28XB=y
+CONFIG_USB_SERIAL_KEYSPAN_USA19=y
+CONFIG_USB_SERIAL_KEYSPAN_USA18X=y
+CONFIG_USB_SERIAL_KEYSPAN_USA19W=y
+CONFIG_USB_SERIAL_KEYSPAN_USA19QW=y
+CONFIG_USB_SERIAL_KEYSPAN_USA19QI=y
+CONFIG_USB_SERIAL_KEYSPAN_USA49W=y
+CONFIG_USB_SERIAL_KEYSPAN_USA49WLC=y
+CONFIG_USB_SERIAL_KLSI=m
+CONFIG_USB_SERIAL_KOBIL_SCT=m
+CONFIG_USB_SERIAL_MCT_U232=m
+CONFIG_USB_SERIAL_MOS7720=m
+CONFIG_USB_SERIAL_MOS7840=m
+CONFIG_USB_SERIAL_MOTOROLA=m
+CONFIG_USB_SERIAL_NAVMAN=m
+CONFIG_USB_SERIAL_PL2303=m
+CONFIG_USB_SERIAL_OTI6858=m
+# CONFIG_USB_SERIAL_QUALCOMM is not set
+CONFIG_USB_SERIAL_SPCP8X5=m
+CONFIG_USB_SERIAL_HP4X=m
+CONFIG_USB_SERIAL_SAFE=m
+# CONFIG_USB_SERIAL_SAFE_PADDED is not set
+CONFIG_USB_SERIAL_SIEMENS_MPI=m
+CONFIG_USB_SERIAL_SIERRAWIRELESS=m
+# CONFIG_USB_SERIAL_SYMBOL is not set
+CONFIG_USB_SERIAL_TI=m
+CONFIG_USB_SERIAL_CYBERJACK=m
+CONFIG_USB_SERIAL_XIRCOM=m
+CONFIG_USB_SERIAL_OPTION=m
+CONFIG_USB_SERIAL_OMNINET=m
+CONFIG_USB_SERIAL_OPTICON=m
+CONFIG_USB_SERIAL_DEBUG=m
+
+#
+# USB Miscellaneous drivers
+#
+CONFIG_USB_EMI62=m
+CONFIG_USB_EMI26=m
+# CONFIG_USB_ADUTUX is not set
+# CONFIG_USB_SEVSEG is not set
+# CONFIG_USB_RIO500 is not set
+# CONFIG_USB_LEGOTOWER is not set
+# CONFIG_USB_LCD is not set
+# CONFIG_USB_BERRY_CHARGE is not set
+# CONFIG_USB_LED is not set
+# CONFIG_USB_CYPRESS_CY7C63 is not set
+# CONFIG_USB_CYTHERM is not set
+# CONFIG_USB_IDMOUSE is not set
+# CONFIG_USB_FTDI_ELAN is not set
+# CONFIG_USB_APPLEDISPLAY is not set
+CONFIG_USB_SISUSBVGA=m
+CONFIG_USB_SISUSBVGA_CON=y
+# CONFIG_USB_LD is not set
+# CONFIG_USB_TRANCEVIBRATOR is not set
+# CONFIG_USB_IOWARRIOR is not set
+CONFIG_USB_TEST=m
+# CONFIG_USB_ISIGHTFW is not set
+# CONFIG_USB_VST is not set
+# CONFIG_USB_ATM is not set
+CONFIG_USB_GADGET=m
+# CONFIG_USB_GADGET_DEBUG is not set
+# CONFIG_USB_GADGET_DEBUG_FILES is not set
+CONFIG_USB_GADGET_DEBUG_FS=y
+CONFIG_USB_GADGET_VBUS_DRAW=2
+CONFIG_USB_GADGET_SELECTED=y
+# CONFIG_USB_GADGET_AT91 is not set
+# CONFIG_USB_GADGET_ATMEL_USBA is not set
+# CONFIG_USB_GADGET_FSL_USB2 is not set
+# CONFIG_USB_GADGET_LH7A40X is not set
+# CONFIG_USB_GADGET_OMAP is not set
+# CONFIG_USB_GADGET_PXA25X is not set
+# CONFIG_USB_GADGET_R8A66597 is not set
+# CONFIG_USB_GADGET_PXA27X is not set
+# CONFIG_USB_GADGET_S3C_HSOTG is not set
+# CONFIG_USB_GADGET_IMX is not set
+# CONFIG_USB_GADGET_S3C2410 is not set
+# CONFIG_USB_GADGET_M66592 is not set
+# CONFIG_USB_GADGET_AMD5536UDC is not set
+# CONFIG_USB_GADGET_FSL_QE is not set
+# CONFIG_USB_GADGET_CI13XXX is not set
+# CONFIG_USB_GADGET_NET2280 is not set
+# CONFIG_USB_GADGET_GOKU is not set
+# CONFIG_USB_GADGET_LANGWELL is not set
+# CONFIG_USB_GADGET_DUMMY_HCD is not set
+CONFIG_USB_GADGET_DUALSPEED=y
+CONFIG_USB_ZERO=m
+CONFIG_USB_ZERO_HNPTEST=y
+# CONFIG_USB_AUDIO is not set
+CONFIG_USB_ETH=m
+CONFIG_USB_ETH_RNDIS=y
+# CONFIG_USB_ETH_EEM is not set
+CONFIG_USB_GADGETFS=m
+CONFIG_USB_FILE_STORAGE=m
+# CONFIG_USB_FILE_STORAGE_TEST is not set
+CONFIG_USB_G_SERIAL=m
+CONFIG_USB_MIDI_GADGET=m
+CONFIG_USB_G_PRINTER=m
+CONFIG_USB_CDC_COMPOSITE=m
+
+#
+# OTG and related infrastructure
+#
+CONFIG_USB_OTG_UTILS=y
+CONFIG_USB_GPIO_VBUS=y
+# CONFIG_ISP1301_OMAP is not set
+CONFIG_TWL4030_USB=y
+# CONFIG_NOP_USB_XCEIV is not set
+CONFIG_MMC=y
+# CONFIG_MMC_DEBUG is not set
+CONFIG_MMC_UNSAFE_RESUME=y
+
+#
+# MMC/SD/SDIO Card Drivers
+#
+CONFIG_MMC_BLOCK=y
+CONFIG_MMC_BLOCK_BOUNCE=y
+CONFIG_SDIO_UART=y
+# CONFIG_MMC_TEST is not set
+
+#
+# MMC/SD/SDIO Host Controller Drivers
+#
+# CONFIG_MMC_SDHCI is not set
+# CONFIG_MMC_OMAP is not set
+CONFIG_MMC_OMAP_HS=y
+# CONFIG_MMC_AT91 is not set
+# CONFIG_MMC_ATMELMCI is not set
+CONFIG_MMC_SPI=m
+# CONFIG_MEMSTICK is not set
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
+
+#
+# LED drivers
+#
+# CONFIG_LEDS_PCA9532 is not set
+CONFIG_LEDS_GPIO=y
+CONFIG_LEDS_GPIO_PLATFORM=y
+# CONFIG_LEDS_LP3944 is not set
+# CONFIG_LEDS_PCA955X is not set
+# CONFIG_LEDS_DAC124S085 is not set
+# CONFIG_LEDS_BD2802 is not set
+
+#
+# LED Triggers
+#
+CONFIG_LEDS_TRIGGERS=y
+CONFIG_LEDS_TRIGGER_TIMER=m
+CONFIG_LEDS_TRIGGER_HEARTBEAT=y
+CONFIG_LEDS_TRIGGER_BACKLIGHT=m
+# CONFIG_LEDS_TRIGGER_GPIO is not set
+CONFIG_LEDS_TRIGGER_DEFAULT_ON=m
+
+#
+# iptables trigger is under Netfilter config (LED target)
+#
+# CONFIG_ACCESSIBILITY is not set
+CONFIG_RTC_LIB=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_HCTOSYS=y
+CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
+# CONFIG_RTC_DEBUG is not set
+
+#
+# RTC interfaces
+#
+CONFIG_RTC_INTF_SYSFS=y
+CONFIG_RTC_INTF_PROC=y
+CONFIG_RTC_INTF_DEV=y
+# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
+# CONFIG_RTC_DRV_TEST is not set
+
+#
+# I2C RTC drivers
+#
+# CONFIG_RTC_DRV_DS1307 is not set
+# CONFIG_RTC_DRV_DS1374 is not set
+# CONFIG_RTC_DRV_DS1672 is not set
+# CONFIG_RTC_DRV_MAX6900 is not set
+# CONFIG_RTC_DRV_RS5C372 is not set
+# CONFIG_RTC_DRV_ISL1208 is not set
+# CONFIG_RTC_DRV_X1205 is not set
+# CONFIG_RTC_DRV_PCF8563 is not set
+# CONFIG_RTC_DRV_PCF8583 is not set
+# CONFIG_RTC_DRV_M41T80 is not set
+CONFIG_RTC_DRV_TWL4030=y
+# CONFIG_RTC_DRV_S35390A is not set
+# CONFIG_RTC_DRV_FM3130 is not set
+# CONFIG_RTC_DRV_RX8581 is not set
+# CONFIG_RTC_DRV_RX8025 is not set
+
+#
+# SPI RTC drivers
+#
+# CONFIG_RTC_DRV_M41T94 is not set
+# CONFIG_RTC_DRV_DS1305 is not set
+# CONFIG_RTC_DRV_DS1390 is not set
+# CONFIG_RTC_DRV_MAX6902 is not set
+# CONFIG_RTC_DRV_R9701 is not set
+# CONFIG_RTC_DRV_RS5C348 is not set
+# CONFIG_RTC_DRV_DS3234 is not set
+# CONFIG_RTC_DRV_PCF2123 is not set
+
+#
+# Platform RTC drivers
+#
+# CONFIG_RTC_DRV_CMOS is not set
+# CONFIG_RTC_DRV_DS1286 is not set
+# CONFIG_RTC_DRV_DS1511 is not set
+# CONFIG_RTC_DRV_DS1553 is not set
+# CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_STK17TA8 is not set
+# CONFIG_RTC_DRV_M48T86 is not set
+# CONFIG_RTC_DRV_M48T35 is not set
+# CONFIG_RTC_DRV_M48T59 is not set
+# CONFIG_RTC_DRV_BQ4802 is not set
+# CONFIG_RTC_DRV_V3020 is not set
+
+#
+# on-CPU RTC drivers
+#
+# CONFIG_DMADEVICES is not set
+# CONFIG_AUXDISPLAY is not set
+CONFIG_UIO=m
+CONFIG_UIO_PDRV=m
+CONFIG_UIO_PDRV_GENIRQ=m
+# CONFIG_UIO_SMX is not set
+# CONFIG_UIO_SERCOS3 is not set
+
+#
+# TI VLYNQ
+#
+CONFIG_STAGING=y
+# CONFIG_STAGING_EXCLUDE_BUILD is not set
+# CONFIG_USB_IP_COMMON is not set
+# CONFIG_W35UND is not set
+# CONFIG_PRISM2_USB is not set
+# CONFIG_ECHO is not set
+# CONFIG_OTUS is not set
+# CONFIG_COMEDI is not set
+# CONFIG_ASUS_OLED is not set
+# CONFIG_INPUT_MIMIO is not set
+# CONFIG_TRANZPORT is not set
+
+#
+# Android
+#
+
+#
+# Qualcomm MSM Camera And Video
+#
+
+#
+# Camera Sensor Selection
+#
+# CONFIG_INPUT_GPIO is not set
+# CONFIG_DST is not set
+# CONFIG_POHMELFS is not set
+# CONFIG_PLAN9AUTH is not set
+# CONFIG_LINE6_USB is not set
+# CONFIG_USB_SERIAL_QUATECH2 is not set
+# CONFIG_USB_SERIAL_QUATECH_USB2 is not set
+# CONFIG_VT6656 is not set
+# CONFIG_FB_UDL is not set
+
+#
+# RAR Register Driver
+#
+# CONFIG_RAR_REGISTER is not set
+# CONFIG_IIO is not set
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+# CONFIG_EXT2_FS_XATTR is not set
+# CONFIG_EXT2_FS_XIP is not set
+CONFIG_EXT3_FS=y
+# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
+# CONFIG_EXT3_FS_XATTR is not set
+CONFIG_EXT4_FS=m
+CONFIG_EXT4_FS_XATTR=y
+# CONFIG_EXT4_FS_POSIX_ACL is not set
+# CONFIG_EXT4_FS_SECURITY is not set
+# CONFIG_EXT4_DEBUG is not set
+CONFIG_JBD=y
+# CONFIG_JBD_DEBUG is not set
+CONFIG_JBD2=m
+# CONFIG_JBD2_DEBUG is not set
+CONFIG_FS_MBCACHE=m
+CONFIG_REISERFS_FS=m
+# CONFIG_REISERFS_CHECK is not set
+CONFIG_REISERFS_PROC_INFO=y
+CONFIG_REISERFS_FS_XATTR=y
+# CONFIG_REISERFS_FS_POSIX_ACL is not set
+# CONFIG_REISERFS_FS_SECURITY is not set
+CONFIG_JFS_FS=m
+# CONFIG_JFS_POSIX_ACL is not set
+# CONFIG_JFS_SECURITY is not set
+# CONFIG_JFS_DEBUG is not set
+# CONFIG_JFS_STATISTICS is not set
+CONFIG_FS_POSIX_ACL=y
+CONFIG_XFS_FS=m
+# CONFIG_XFS_QUOTA is not set
+# CONFIG_XFS_POSIX_ACL is not set
+# CONFIG_XFS_RT is not set
+# CONFIG_XFS_DEBUG is not set
+# CONFIG_GFS2_FS is not set
+# CONFIG_OCFS2_FS is not set
+# CONFIG_BTRFS_FS is not set
+# CONFIG_NILFS2_FS is not set
+CONFIG_FILE_LOCKING=y
+CONFIG_FSNOTIFY=y
+CONFIG_DNOTIFY=y
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
+CONFIG_QUOTA=y
+# CONFIG_QUOTA_NETLINK_INTERFACE is not set
+CONFIG_PRINT_QUOTA_WARNING=y
+CONFIG_QUOTA_TREE=y
+# CONFIG_QFMT_V1 is not set
+CONFIG_QFMT_V2=y
+CONFIG_QUOTACTL=y
+# CONFIG_AUTOFS_FS is not set
+CONFIG_AUTOFS4_FS=m
+CONFIG_FUSE_FS=y
+# CONFIG_CUSE is not set
+
+#
+# Caches
+#
+# CONFIG_FSCACHE is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+CONFIG_ISO9660_FS=m
+CONFIG_JOLIET=y
+CONFIG_ZISOFS=y
+CONFIG_UDF_FS=m
+CONFIG_UDF_NLS=y
+
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
+CONFIG_NTFS_FS=m
+# CONFIG_NTFS_DEBUG is not set
+CONFIG_NTFS_RW=y
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_HUGETLB_PAGE is not set
+CONFIG_CONFIGFS_FS=m
+CONFIG_MISC_FILESYSTEMS=y
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_ECRYPT_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_DEBUG=0
+CONFIG_JFFS2_FS_WRITEBUFFER=y
+# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
+CONFIG_JFFS2_SUMMARY=y
+CONFIG_JFFS2_FS_XATTR=y
+CONFIG_JFFS2_FS_POSIX_ACL=y
+CONFIG_JFFS2_FS_SECURITY=y
+CONFIG_JFFS2_COMPRESSION_OPTIONS=y
+CONFIG_JFFS2_ZLIB=y
+CONFIG_JFFS2_LZO=y
+CONFIG_JFFS2_RTIME=y
+CONFIG_JFFS2_RUBIN=y
+# CONFIG_JFFS2_CMODE_NONE is not set
+# CONFIG_JFFS2_CMODE_PRIORITY is not set
+# CONFIG_JFFS2_CMODE_SIZE is not set
+CONFIG_JFFS2_CMODE_FAVOURLZO=y
+CONFIG_UBIFS_FS=y
+CONFIG_UBIFS_FS_XATTR=y
+CONFIG_UBIFS_FS_ADVANCED_COMPR=y
+CONFIG_UBIFS_FS_LZO=y
+CONFIG_UBIFS_FS_ZLIB=y
+# CONFIG_UBIFS_FS_DEBUG is not set
+# CONFIG_CRAMFS is not set
+CONFIG_SQUASHFS=y
+# CONFIG_SQUASHFS_EMBEDDED is not set
+CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3
+# CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_OMFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+# CONFIG_NFS_V3_ACL is not set
+CONFIG_NFS_V4=y
+# CONFIG_NFS_V4_1 is not set
+CONFIG_ROOT_NFS=y
+CONFIG_NFSD=m
+CONFIG_NFSD_V2_ACL=y
+CONFIG_NFSD_V3=y
+CONFIG_NFSD_V3_ACL=y
+CONFIG_NFSD_V4=y
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+CONFIG_EXPORTFS=m
+CONFIG_NFS_ACL_SUPPORT=m
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=y
+CONFIG_SUNRPC_GSS=y
+CONFIG_RPCSEC_GSS_KRB5=y
+# CONFIG_RPCSEC_GSS_SPKM3 is not set
+# CONFIG_SMB_FS is not set
+CONFIG_CIFS=m
+CONFIG_CIFS_STATS=y
+CONFIG_CIFS_STATS2=y
+# CONFIG_CIFS_WEAK_PW_HASH is not set
+# CONFIG_CIFS_UPCALL is not set
+# CONFIG_CIFS_XATTR is not set
+# CONFIG_CIFS_DEBUG2 is not set
+# CONFIG_CIFS_DFS_UPCALL is not set
+CONFIG_CIFS_EXPERIMENTAL=y
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+
+#
+# Partition Types
+#
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_ACORN_PARTITION is not set
+# CONFIG_OSF_PARTITION is not set
+# CONFIG_AMIGA_PARTITION is not set
+# CONFIG_ATARI_PARTITION is not set
+# CONFIG_MAC_PARTITION is not set
+CONFIG_MSDOS_PARTITION=y
+CONFIG_BSD_DISKLABEL=y
+CONFIG_MINIX_SUBPARTITION=y
+CONFIG_SOLARIS_X86_PARTITION=y
+CONFIG_UNIXWARE_DISKLABEL=y
+# CONFIG_LDM_PARTITION is not set
+# CONFIG_SGI_PARTITION is not set
+# CONFIG_ULTRIX_PARTITION is not set
+# CONFIG_SUN_PARTITION is not set
+# CONFIG_KARMA_PARTITION is not set
+CONFIG_EFI_PARTITION=y
+# CONFIG_SYSV68_PARTITION is not set
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="iso8859-1"
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_CODEPAGE_737=m
+CONFIG_NLS_CODEPAGE_775=m
+CONFIG_NLS_CODEPAGE_850=m
+CONFIG_NLS_CODEPAGE_852=m
+CONFIG_NLS_CODEPAGE_855=m
+CONFIG_NLS_CODEPAGE_857=m
+CONFIG_NLS_CODEPAGE_860=m
+CONFIG_NLS_CODEPAGE_861=m
+CONFIG_NLS_CODEPAGE_862=m
+CONFIG_NLS_CODEPAGE_863=m
+CONFIG_NLS_CODEPAGE_864=m
+CONFIG_NLS_CODEPAGE_865=m
+CONFIG_NLS_CODEPAGE_866=m
+CONFIG_NLS_CODEPAGE_869=m
+CONFIG_NLS_CODEPAGE_936=m
+CONFIG_NLS_CODEPAGE_950=m
+CONFIG_NLS_CODEPAGE_932=m
+CONFIG_NLS_CODEPAGE_949=m
+CONFIG_NLS_CODEPAGE_874=m
+CONFIG_NLS_ISO8859_8=m
+CONFIG_NLS_CODEPAGE_1250=m
+CONFIG_NLS_CODEPAGE_1251=m
+CONFIG_NLS_ASCII=m
+CONFIG_NLS_ISO8859_1=m
+CONFIG_NLS_ISO8859_2=m
+CONFIG_NLS_ISO8859_3=m
+CONFIG_NLS_ISO8859_4=m
+CONFIG_NLS_ISO8859_5=m
+CONFIG_NLS_ISO8859_6=m
+CONFIG_NLS_ISO8859_7=m
+CONFIG_NLS_ISO8859_9=m
+CONFIG_NLS_ISO8859_13=m
+CONFIG_NLS_ISO8859_14=m
+CONFIG_NLS_ISO8859_15=m
+CONFIG_NLS_KOI8_R=m
+CONFIG_NLS_KOI8_U=m
+CONFIG_NLS_UTF8=y
+# CONFIG_DLM is not set
+
+#
+# Kernel hacking
+#
+CONFIG_PRINTK_TIME=y
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_FRAME_WARN=1024
+CONFIG_MAGIC_SYSRQ=y
+# CONFIG_STRIP_ASM_SYMS is not set
+# CONFIG_UNUSED_SYMBOLS is not set
+CONFIG_DEBUG_FS=y
+# CONFIG_HEADERS_CHECK is not set
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_SHIRQ is not set
+CONFIG_DETECT_SOFTLOCKUP=y
+# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
+CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
+CONFIG_DETECT_HUNG_TASK=y
+# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set
+CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0
+CONFIG_SCHED_DEBUG=y
+CONFIG_SCHEDSTATS=y
+CONFIG_TIMER_STATS=y
+# CONFIG_DEBUG_OBJECTS is not set
+# CONFIG_DEBUG_SLAB is not set
+# CONFIG_DEBUG_KMEMLEAK is not set
+CONFIG_DEBUG_PREEMPT=y
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_RT_MUTEX_TESTER is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+CONFIG_DEBUG_MUTEXES=y
+# CONFIG_DEBUG_LOCK_ALLOC is not set
+# CONFIG_PROVE_LOCKING is not set
+# CONFIG_LOCK_STAT is not set
+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+CONFIG_STACKTRACE=y
+# CONFIG_DEBUG_KOBJECT is not set
+# CONFIG_DEBUG_BUGVERBOSE is not set
+# CONFIG_DEBUG_INFO is not set
+# CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_WRITECOUNT is not set
+# CONFIG_DEBUG_MEMORY_INIT is not set
+# CONFIG_DEBUG_LIST is not set
+# CONFIG_DEBUG_SG is not set
+# CONFIG_DEBUG_NOTIFIERS is not set
+# CONFIG_DEBUG_CREDENTIALS is not set
+# CONFIG_BOOT_PRINTK_DELAY is not set
+# CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_RCU_CPU_STALL_DETECTOR is not set
+# CONFIG_BACKTRACE_SELF_TEST is not set
+# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
+# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
+# CONFIG_FAULT_INJECTION is not set
+# CONFIG_LATENCYTOP is not set
+# CONFIG_PAGE_POISONING is not set
+CONFIG_NOP_TRACER=y
+CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_RING_BUFFER=y
+CONFIG_EVENT_TRACING=y
+CONFIG_CONTEXT_SWITCH_TRACER=y
+CONFIG_RING_BUFFER_ALLOW_SWAP=y
+CONFIG_TRACING=y
+CONFIG_TRACING_SUPPORT=y
+CONFIG_FTRACE=y
+# CONFIG_FUNCTION_TRACER is not set
+# CONFIG_IRQSOFF_TRACER is not set
+# CONFIG_PREEMPT_TRACER is not set
+# CONFIG_SCHED_TRACER is not set
+# CONFIG_ENABLE_DEFAULT_TRACERS is not set
+# CONFIG_BOOT_TRACER is not set
+CONFIG_BRANCH_PROFILE_NONE=y
+# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set
+# CONFIG_PROFILE_ALL_BRANCHES is not set
+# CONFIG_STACK_TRACER is not set
+# CONFIG_KMEMTRACE is not set
+# CONFIG_WORKQUEUE_TRACER is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_RING_BUFFER_BENCHMARK is not set
+# CONFIG_DYNAMIC_DEBUG is not set
+# CONFIG_SAMPLES is not set
+CONFIG_HAVE_ARCH_KGDB=y
+# CONFIG_KGDB is not set
+CONFIG_ARM_UNWIND=y
+# CONFIG_DEBUG_USER is not set
+# CONFIG_DEBUG_ERRORS is not set
+# CONFIG_DEBUG_STACK_USAGE is not set
+# CONFIG_DEBUG_LL is not set
+
+#
+# Security options
+#
+CONFIG_KEYS=y
+# CONFIG_KEYS_DEBUG_PROC_KEYS is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITYFS is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+CONFIG_XOR_BLOCKS=m
+CONFIG_ASYNC_CORE=m
+CONFIG_ASYNC_MEMCPY=m
+CONFIG_ASYNC_XOR=m
+CONFIG_ASYNC_PQ=m
+CONFIG_ASYNC_RAID6_RECOV=m
+CONFIG_CRYPTO=y
+
+#
+# Crypto core or helper
+#
+CONFIG_CRYPTO_FIPS=y
+CONFIG_CRYPTO_ALGAPI=y
+CONFIG_CRYPTO_ALGAPI2=y
+CONFIG_CRYPTO_AEAD=m
+CONFIG_CRYPTO_AEAD2=y
+CONFIG_CRYPTO_BLKCIPHER=y
+CONFIG_CRYPTO_BLKCIPHER2=y
+CONFIG_CRYPTO_HASH=y
+CONFIG_CRYPTO_HASH2=y
+CONFIG_CRYPTO_RNG=m
+CONFIG_CRYPTO_RNG2=y
+CONFIG_CRYPTO_PCOMP=y
+CONFIG_CRYPTO_MANAGER=y
+CONFIG_CRYPTO_MANAGER2=y
+CONFIG_CRYPTO_GF128MUL=m
+CONFIG_CRYPTO_NULL=m
+CONFIG_CRYPTO_WORKQUEUE=y
+CONFIG_CRYPTO_CRYPTD=m
+CONFIG_CRYPTO_AUTHENC=m
+CONFIG_CRYPTO_TEST=m
+
+#
+# Authenticated Encryption with Associated Data
+#
+CONFIG_CRYPTO_CCM=m
+CONFIG_CRYPTO_GCM=m
+CONFIG_CRYPTO_SEQIV=m
+
+#
+# Block modes
+#
+CONFIG_CRYPTO_CBC=y
+CONFIG_CRYPTO_CTR=m
+CONFIG_CRYPTO_CTS=m
+CONFIG_CRYPTO_ECB=y
+CONFIG_CRYPTO_LRW=m
+CONFIG_CRYPTO_PCBC=m
+CONFIG_CRYPTO_XTS=m
+
+#
+# Hash modes
+#
+CONFIG_CRYPTO_HMAC=m
+CONFIG_CRYPTO_XCBC=m
+# CONFIG_CRYPTO_VMAC is not set
+
+#
+# Digest
+#
+CONFIG_CRYPTO_CRC32C=y
+CONFIG_CRYPTO_GHASH=m
+CONFIG_CRYPTO_MD4=m
+CONFIG_CRYPTO_MD5=y
+CONFIG_CRYPTO_MICHAEL_MIC=y
+CONFIG_CRYPTO_RMD128=m
+CONFIG_CRYPTO_RMD160=m
+CONFIG_CRYPTO_RMD256=m
+CONFIG_CRYPTO_RMD320=m
+CONFIG_CRYPTO_SHA1=m
+CONFIG_CRYPTO_SHA256=m
+CONFIG_CRYPTO_SHA512=m
+CONFIG_CRYPTO_TGR192=m
+CONFIG_CRYPTO_WP512=m
+
+#
+# Ciphers
+#
+CONFIG_CRYPTO_AES=y
+CONFIG_CRYPTO_ANUBIS=m
+CONFIG_CRYPTO_ARC4=y
+CONFIG_CRYPTO_BLOWFISH=m
+CONFIG_CRYPTO_CAMELLIA=m
+CONFIG_CRYPTO_CAST5=m
+CONFIG_CRYPTO_CAST6=m
+CONFIG_CRYPTO_DES=y
+CONFIG_CRYPTO_FCRYPT=m
+CONFIG_CRYPTO_KHAZAD=m
+CONFIG_CRYPTO_SALSA20=m
+CONFIG_CRYPTO_SEED=m
+CONFIG_CRYPTO_SERPENT=m
+CONFIG_CRYPTO_TEA=m
+CONFIG_CRYPTO_TWOFISH=m
+CONFIG_CRYPTO_TWOFISH_COMMON=m
+
+#
+# Compression
+#
+CONFIG_CRYPTO_DEFLATE=y
+# CONFIG_CRYPTO_ZLIB is not set
+CONFIG_CRYPTO_LZO=y
+
+#
+# Random Number Generation
+#
+CONFIG_CRYPTO_ANSI_CPRNG=m
+CONFIG_CRYPTO_HW=y
+CONFIG_BINARY_PRINTF=y
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+CONFIG_GENERIC_FIND_LAST_BIT=y
+CONFIG_CRC_CCITT=y
+CONFIG_CRC16=y
+CONFIG_CRC_T10DIF=y
+CONFIG_CRC_ITU_T=y
+CONFIG_CRC32=y
+CONFIG_CRC7=y
+CONFIG_LIBCRC32C=y
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_LZO_COMPRESS=y
+CONFIG_LZO_DECOMPRESS=y
+CONFIG_DECOMPRESS_GZIP=y
+CONFIG_TEXTSEARCH=y
+CONFIG_TEXTSEARCH_KMP=m
+CONFIG_TEXTSEARCH_BM=m
+CONFIG_TEXTSEARCH_FSM=m
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
+CONFIG_NLATTR=y
diff --git a/arch/arm/configs/omap_4430sdp_defconfig b/arch/arm/configs/omap_4430sdp_defconfig
index a464ca332a23..2319113c86bf 100644
--- a/arch/arm/configs/omap_4430sdp_defconfig
+++ b/arch/arm/configs/omap_4430sdp_defconfig
@@ -1,26 +1,29 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.30-rc7
-# Tue Jun  9 12:36:23 2009
+# Linux kernel version: 2.6.32
+# Sun Dec  6 23:37:45 2009
 #
 CONFIG_ARM=y
 CONFIG_SYS_SUPPORTS_APM_EMULATION=y
 CONFIG_GENERIC_GPIO=y
 CONFIG_GENERIC_TIME=y
 CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_MMU=y
+CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
 CONFIG_GENERIC_HARDIRQS=y
 CONFIG_STACKTRACE_SUPPORT=y
 CONFIG_LOCKDEP_SUPPORT=y
 CONFIG_TRACE_IRQFLAGS_SUPPORT=y
 CONFIG_HARDIRQS_SW_RESEND=y
 CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_GENERIC_LOCKBREAK=y
 CONFIG_RWSEM_GENERIC_SPINLOCK=y
+CONFIG_ARCH_HAS_CPUFREQ=y
 CONFIG_GENERIC_HWEIGHT=y
 CONFIG_GENERIC_CALIBRATE_DELAY=y
 CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
 CONFIG_VECTORS_BASE=0xffff0000
 CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+CONFIG_CONSTRUCTORS=y
 
 #
 # General setup
@@ -39,11 +42,12 @@ CONFIG_BSD_PROCESS_ACCT=y
 #
 # RCU Subsystem
 #
-CONFIG_CLASSIC_RCU=y
-# CONFIG_TREE_RCU is not set
-# CONFIG_PREEMPT_RCU is not set
+CONFIG_TREE_RCU=y
+# CONFIG_TREE_PREEMPT_RCU is not set
+# CONFIG_RCU_TRACE is not set
+CONFIG_RCU_FANOUT=32
+# CONFIG_RCU_FANOUT_EXACT is not set
 # CONFIG_TREE_RCU_TRACE is not set
-# CONFIG_PREEMPT_RCU_TRACE is not set
 # CONFIG_IKCONFIG is not set
 CONFIG_LOG_BUF_SHIFT=14
 CONFIG_GROUP_SCHED=y
@@ -52,8 +56,7 @@ CONFIG_FAIR_GROUP_SCHED=y
 CONFIG_USER_SCHED=y
 # CONFIG_CGROUP_SCHED is not set
 # CONFIG_CGROUPS is not set
-# CONFIG_SYSFS_DEPRECATED=y is not set
-# CONFIG_SYSFS_DEPRECATED_V2=y is not set
+# CONFIG_SYSFS_DEPRECATED_V2 is not set
 # CONFIG_RELAY is not set
 # CONFIG_NAMESPACES is not set
 CONFIG_BLK_DEV_INITRD=y
@@ -70,7 +73,6 @@ CONFIG_UID16=y
 CONFIG_KALLSYMS=y
 # CONFIG_KALLSYMS_ALL is not set
 # CONFIG_KALLSYMS_EXTRA_PASS is not set
-# CONFIG_STRIP_ASM_SYMS is not set
 CONFIG_HOTPLUG=y
 CONFIG_PRINTK=y
 CONFIG_BUG=y
@@ -83,6 +85,10 @@ CONFIG_TIMERFD=y
 CONFIG_EVENTFD=y
 CONFIG_SHMEM=y
 CONFIG_AIO=y
+
+#
+# Kernel Performance Events And Counters
+#
 CONFIG_VM_EVENT_COUNTERS=y
 CONFIG_SLUB_DEBUG=y
 CONFIG_COMPAT_BRK=y
@@ -90,13 +96,16 @@ CONFIG_COMPAT_BRK=y
 CONFIG_SLUB=y
 # CONFIG_SLOB is not set
 # CONFIG_PROFILING is not set
-# CONFIG_MARKERS is not set
 CONFIG_HAVE_OPROFILE=y
 # CONFIG_KPROBES is not set
 CONFIG_HAVE_KPROBES=y
 CONFIG_HAVE_KRETPROBES=y
 CONFIG_USE_GENERIC_SMP_HELPERS=y
 CONFIG_HAVE_CLK=y
+
+#
+# GCOV-based kernel profiling
+#
 # CONFIG_SLOW_WORK is not set
 CONFIG_HAVE_GENERIC_DMA_COHERENT=y
 CONFIG_SLABINFO=y
@@ -110,7 +119,7 @@ CONFIG_MODVERSIONS=y
 CONFIG_MODULE_SRCVERSION_ALL=y
 CONFIG_STOP_MACHINE=y
 CONFIG_BLOCK=y
-# CONFIG_LBD is not set
+CONFIG_LBDAF=y
 # CONFIG_BLK_DEV_BSG is not set
 # CONFIG_BLK_DEV_INTEGRITY is not set
 
@@ -131,6 +140,7 @@ CONFIG_DEFAULT_IOSCHED="anticipatory"
 #
 # System Type
 #
+CONFIG_MMU=y
 # CONFIG_ARCH_AAEC2000 is not set
 # CONFIG_ARCH_INTEGRATOR is not set
 # CONFIG_ARCH_REALVIEW is not set
@@ -142,8 +152,10 @@ CONFIG_DEFAULT_IOSCHED="anticipatory"
 # CONFIG_ARCH_EP93XX is not set
 # CONFIG_ARCH_FOOTBRIDGE is not set
 # CONFIG_ARCH_MXC is not set
+# CONFIG_ARCH_STMP3XXX is not set
 # CONFIG_ARCH_NETX is not set
 # CONFIG_ARCH_H720X is not set
+# CONFIG_ARCH_NOMADIK is not set
 # CONFIG_ARCH_IOP13XX is not set
 # CONFIG_ARCH_IOP32X is not set
 # CONFIG_ARCH_IOP33X is not set
@@ -166,10 +178,13 @@ CONFIG_DEFAULT_IOSCHED="anticipatory"
 # CONFIG_ARCH_SA1100 is not set
 # CONFIG_ARCH_S3C2410 is not set
 # CONFIG_ARCH_S3C64XX is not set
+# CONFIG_ARCH_S5PC1XX is not set
 # CONFIG_ARCH_SHARK is not set
 # CONFIG_ARCH_LH7A40X is not set
+# CONFIG_ARCH_U300 is not set
 # CONFIG_ARCH_DAVINCI is not set
 CONFIG_ARCH_OMAP=y
+# CONFIG_ARCH_BCMRING is not set
 
 #
 # TI OMAP Implementations
@@ -190,9 +205,12 @@ CONFIG_ARCH_OMAP4=y
 CONFIG_OMAP_32K_TIMER=y
 CONFIG_OMAP_32K_TIMER_HZ=128
 CONFIG_OMAP_DM_TIMER=y
-CONFIG_OMAP_LL_DEBUG_UART1=y
+# CONFIG_OMAP_LL_DEBUG_UART1 is not set
 # CONFIG_OMAP_LL_DEBUG_UART2 is not set
-# CONFIG_OMAP_LL_DEBUG_UART3 is not set
+CONFIG_OMAP_LL_DEBUG_UART3=y
+# CONFIG_OMAP_LL_DEBUG_NONE is not set
+# CONFIG_OMAP_PM_NONE is not set
+CONFIG_OMAP_PM_NOOP=y
 
 #
 # OMAP Board Type
@@ -207,7 +225,7 @@ CONFIG_CPU_32v6K=y
 CONFIG_CPU_V7=y
 CONFIG_CPU_32v7=y
 CONFIG_CPU_ABRT_EV7=y
-CONFIG_CPU_PABRT_IFAR=y
+CONFIG_CPU_PABRT_V7=y
 CONFIG_CPU_CACHE_V7=y
 CONFIG_CPU_CACHE_VIPT=y
 CONFIG_CPU_COPY_V6=y
@@ -222,9 +240,10 @@ CONFIG_CPU_CP15_MMU=y
 # CONFIG_ARM_THUMB is not set
 # CONFIG_ARM_THUMBEE is not set
 # CONFIG_CPU_ICACHE_DISABLE is not set
-CONFIG_CPU_DCACHE_DISABLE=y
+# CONFIG_CPU_DCACHE_DISABLE is not set
 # CONFIG_CPU_BPREDICT_DISABLE is not set
 CONFIG_HAS_TLS_REG=y
+CONFIG_ARM_L1_CACHE_SHIFT=5
 # CONFIG_ARM_ERRATA_430973 is not set
 # CONFIG_ARM_ERRATA_458693 is not set
 # CONFIG_ARM_ERRATA_460075 is not set
@@ -245,18 +264,20 @@ CONFIG_ARM_GIC=y
 CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
 CONFIG_SMP=y
 CONFIG_HAVE_ARM_SCU=y
-CONFIG_HAVE_ARM_TWD=y
 CONFIG_VMSPLIT_3G=y
 # CONFIG_VMSPLIT_2G is not set
 # CONFIG_VMSPLIT_1G is not set
 CONFIG_PAGE_OFFSET=0xC0000000
 CONFIG_NR_CPUS=2
 # CONFIG_HOTPLUG_CPU is not set
-CONFIG_LOCAL_TIMERS=y
-# CONFIG_PREEMPT is not set
+# CONFIG_LOCAL_TIMERS is not set
+# CONFIG_PREEMPT_NONE is not set
+# CONFIG_PREEMPT_VOLUNTARY is not set
+CONFIG_PREEMPT=y
 CONFIG_HZ=128
+# CONFIG_THUMB2_KERNEL is not set
 CONFIG_AEABI=y
-# CONFIG_OABI_COMPAT is not set
+CONFIG_OABI_COMPAT=y
 # CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
 # CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
 # CONFIG_HIGHMEM is not set
@@ -271,10 +292,13 @@ CONFIG_SPLIT_PTLOCK_CPUS=4
 # CONFIG_PHYS_ADDR_T_64BIT is not set
 CONFIG_ZONE_DMA_FLAG=0
 CONFIG_VIRT_TO_BUS=y
-# CONFIG_UNEVICTABLE_LRU is not set
 CONFIG_HAVE_MLOCK=y
+CONFIG_HAVE_MLOCKED_PAGE_BIT=y
+# CONFIG_KSM is not set
+CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
 # CONFIG_LEDS is not set
 CONFIG_ALIGNMENT_TRAP=y
+# CONFIG_UACCESS_WITH_MEMCPY is not set
 
 #
 # Boot options
@@ -298,9 +322,11 @@ CONFIG_CMDLINE="root=/dev/ram0 rw mem=128M console=ttyS0,115200n8 initrd=0x81600
 #
 # At least one emulation must be selected
 #
+# CONFIG_FPE_NWFPE is not set
+# CONFIG_FPE_FASTFPE is not set
 CONFIG_VFP=y
 CONFIG_VFPv3=y
-# CONFIG_NEON is not set
+CONFIG_NEON=y
 
 #
 # Userspace binary formats
@@ -325,6 +351,7 @@ CONFIG_ARCH_SUSPEND_POSSIBLE=y
 # Generic Driver Options
 #
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+# CONFIG_DEVTMPFS is not set
 CONFIG_STANDALONE=y
 CONFIG_PREVENT_FIRMWARE_BUILD=y
 # CONFIG_FW_LOADER is not set
@@ -342,6 +369,7 @@ CONFIG_BLK_DEV_RAM_COUNT=16
 CONFIG_BLK_DEV_RAM_SIZE=16384
 # CONFIG_BLK_DEV_XIP is not set
 # CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_MG_DISK is not set
 # CONFIG_MISC_DEVICES is not set
 CONFIG_HAVE_IDE=y
 # CONFIG_IDE is not set
@@ -355,6 +383,7 @@ CONFIG_HAVE_IDE=y
 # CONFIG_SCSI_NETLINK is not set
 # CONFIG_ATA is not set
 # CONFIG_MD is not set
+# CONFIG_PHONE is not set
 
 #
 # Input device support
@@ -427,6 +456,11 @@ CONFIG_HW_RANDOM=y
 # CONFIG_TCG_TPM is not set
 # CONFIG_I2C is not set
 # CONFIG_SPI is not set
+
+#
+# PPS support
+#
+# CONFIG_PPS is not set
 CONFIG_ARCH_REQUIRE_GPIOLIB=y
 CONFIG_GPIOLIB=y
 # CONFIG_DEBUG_GPIO is not set
@@ -447,11 +481,14 @@ CONFIG_GPIOLIB=y
 #
 # SPI GPIO expanders:
 #
+
+#
+# AC97 GPIO expanders:
+#
 # CONFIG_W1 is not set
 # CONFIG_POWER_SUPPLY is not set
 # CONFIG_HWMON is not set
 # CONFIG_THERMAL is not set
-# CONFIG_THERMAL_HWMON is not set
 # CONFIG_WATCHDOG is not set
 CONFIG_SSB_POSSIBLE=y
 
@@ -472,21 +509,8 @@ CONFIG_SSB_POSSIBLE=y
 # CONFIG_MFD_T7L66XB is not set
 # CONFIG_MFD_TC6387XB is not set
 # CONFIG_MFD_TC6393XB is not set
-
-#
-# Multimedia devices
-#
-
-#
-# Multimedia core support
-#
-# CONFIG_VIDEO_DEV is not set
-# CONFIG_VIDEO_MEDIA is not set
-
-#
-# Multimedia drivers
-#
-CONFIG_DAB=y
+# CONFIG_REGULATOR is not set
+# CONFIG_MEDIA_SUPPORT is not set
 
 #
 # Graphics support
@@ -511,14 +535,17 @@ CONFIG_DUMMY_CONSOLE=y
 # CONFIG_USB_SUPPORT is not set
 # CONFIG_MMC is not set
 # CONFIG_MEMSTICK is not set
-# CONFIG_ACCESSIBILITY is not set
 # CONFIG_NEW_LEDS is not set
+# CONFIG_ACCESSIBILITY is not set
 CONFIG_RTC_LIB=y
 # CONFIG_RTC_CLASS is not set
 # CONFIG_DMADEVICES is not set
 # CONFIG_AUXDISPLAY is not set
-# CONFIG_REGULATOR is not set
 # CONFIG_UIO is not set
+
+#
+# TI VLYNQ
+#
 # CONFIG_STAGING is not set
 
 #
@@ -535,9 +562,12 @@ CONFIG_JBD=y
 # CONFIG_REISERFS_FS is not set
 # CONFIG_JFS_FS is not set
 # CONFIG_FS_POSIX_ACL is not set
-CONFIG_FILE_LOCKING=y
 # CONFIG_XFS_FS is not set
+# CONFIG_GFS2_FS is not set
 # CONFIG_BTRFS_FS is not set
+# CONFIG_NILFS2_FS is not set
+CONFIG_FILE_LOCKING=y
+CONFIG_FSNOTIFY=y
 CONFIG_DNOTIFY=y
 CONFIG_INOTIFY=y
 CONFIG_INOTIFY_USER=y
@@ -601,7 +631,6 @@ CONFIG_MISC_FILESYSTEMS=y
 # CONFIG_ROMFS_FS is not set
 # CONFIG_SYSV_FS is not set
 # CONFIG_UFS_FS is not set
-# CONFIG_NILFS2_FS is not set
 
 #
 # Partition Types
@@ -673,23 +702,24 @@ CONFIG_NLS_ISO8859_1=y
 # CONFIG_ENABLE_MUST_CHECK is not set
 CONFIG_FRAME_WARN=1024
 CONFIG_MAGIC_SYSRQ=y
+# CONFIG_STRIP_ASM_SYMS is not set
 # CONFIG_UNUSED_SYMBOLS is not set
 # CONFIG_DEBUG_FS is not set
 # CONFIG_HEADERS_CHECK is not set
 CONFIG_DEBUG_KERNEL=y
 # CONFIG_DEBUG_SHIRQ is not set
-CONFIG_DETECT_SOFTLOCKUP=y
-# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
-CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
+# CONFIG_DETECT_SOFTLOCKUP is not set
 CONFIG_DETECT_HUNG_TASK=y
 # CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set
 CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0
-CONFIG_SCHED_DEBUG=y
+# CONFIG_SCHED_DEBUG is not set
 # CONFIG_SCHEDSTATS is not set
 # CONFIG_TIMER_STATS is not set
 # CONFIG_DEBUG_OBJECTS is not set
 # CONFIG_SLUB_DEBUG_ON is not set
 # CONFIG_SLUB_STATS is not set
+# CONFIG_DEBUG_KMEMLEAK is not set
+# CONFIG_DEBUG_PREEMPT is not set
 # CONFIG_DEBUG_RT_MUTEXES is not set
 # CONFIG_RT_MUTEX_TESTER is not set
 # CONFIG_DEBUG_SPINLOCK is not set
@@ -708,31 +738,22 @@ CONFIG_DEBUG_INFO=y
 # CONFIG_DEBUG_LIST is not set
 # CONFIG_DEBUG_SG is not set
 # CONFIG_DEBUG_NOTIFIERS is not set
+# CONFIG_DEBUG_CREDENTIALS is not set
 CONFIG_FRAME_POINTER=y
 # CONFIG_BOOT_PRINTK_DELAY is not set
 # CONFIG_RCU_TORTURE_TEST is not set
 # CONFIG_RCU_CPU_STALL_DETECTOR is not set
 # CONFIG_BACKTRACE_SELF_TEST is not set
 # CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
+# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
 # CONFIG_FAULT_INJECTION is not set
 # CONFIG_PAGE_POISONING is not set
 CONFIG_HAVE_FUNCTION_TRACER=y
 CONFIG_TRACING_SUPPORT=y
-
-#
-# Tracers
-#
-# CONFIG_FUNCTION_TRACER is not set
-# CONFIG_IRQSOFF_TRACER is not set
-# CONFIG_SCHED_TRACER is not set
-# CONFIG_CONTEXT_SWITCH_TRACER is not set
-# CONFIG_EVENT_TRACER is not set
-# CONFIG_BOOT_TRACER is not set
-# CONFIG_TRACE_BRANCH_PROFILING is not set
-# CONFIG_STACK_TRACER is not set
-# CONFIG_KMEMTRACE is not set
-# CONFIG_WORKQUEUE_TRACER is not set
-# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_FTRACE is not set
+# CONFIG_BRANCH_PROFILE_NONE is not set
+# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set
+# CONFIG_PROFILE_ALL_BRANCHES is not set
 # CONFIG_SAMPLES is not set
 CONFIG_HAVE_ARCH_KGDB=y
 # CONFIG_KGDB is not set
@@ -754,7 +775,6 @@ CONFIG_CRYPTO=y
 #
 # Crypto core or helper
 #
-# CONFIG_CRYPTO_FIPS is not set
 CONFIG_CRYPTO_ALGAPI=y
 CONFIG_CRYPTO_ALGAPI2=y
 CONFIG_CRYPTO_AEAD2=y
@@ -796,11 +816,13 @@ CONFIG_CRYPTO_PCBC=m
 #
 # CONFIG_CRYPTO_HMAC is not set
 # CONFIG_CRYPTO_XCBC is not set
+# CONFIG_CRYPTO_VMAC is not set
 
 #
 # Digest
 #
 CONFIG_CRYPTO_CRC32C=y
+# CONFIG_CRYPTO_GHASH is not set
 # CONFIG_CRYPTO_MD4 is not set
 CONFIG_CRYPTO_MD5=y
 # CONFIG_CRYPTO_MICHAEL_MIC is not set
diff --git a/arch/arm/configs/omap_zoom2_defconfig b/arch/arm/configs/omap_zoom2_defconfig
index eef93627fb13..4b00a4306812 100644
--- a/arch/arm/configs/omap_zoom2_defconfig
+++ b/arch/arm/configs/omap_zoom2_defconfig
@@ -610,7 +610,8 @@ CONFIG_INPUT_EVDEV=y
 #
 # Input Device Drivers
 #
-# CONFIG_INPUT_KEYBOARD is not set
+CONFIG_INPUT_KEYBOARD=y
+CONFIG_KEYBOARD_TWL4030=y
 # CONFIG_INPUT_MOUSE is not set
 # CONFIG_INPUT_JOYSTICK is not set
 # CONFIG_INPUT_TABLET is not set
diff --git a/arch/arm/configs/omap_zoom3_defconfig b/arch/arm/configs/omap_zoom3_defconfig
index f0e7d0f85582..0d7e37a3651b 100644
--- a/arch/arm/configs/omap_zoom3_defconfig
+++ b/arch/arm/configs/omap_zoom3_defconfig
@@ -629,7 +629,8 @@ CONFIG_INPUT_EVDEV=y
 #
 # Input Device Drivers
 #
-# CONFIG_INPUT_KEYBOARD is not set
+CONFIG_INPUT_KEYBOARD=y
+CONFIG_KEYBOARD_TWL4030=y
 # CONFIG_INPUT_MOUSE is not set
 # CONFIG_INPUT_JOYSTICK is not set
 # CONFIG_INPUT_TABLET is not set
diff --git a/arch/arm/configs/zeus_defconfig b/arch/arm/configs/zeus_defconfig
new file mode 100644
index 000000000000..823b11e7091a
--- /dev/null
+++ b/arch/arm/configs/zeus_defconfig
@@ -0,0 +1,2032 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.32
+# Tue Dec  8 20:27:05 2009
+#
+CONFIG_ARM=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_GENERIC_GPIO=y
+CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_HAVE_LATENCYTOP_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+CONFIG_ARCH_HAS_CPUFREQ=y
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_ARCH_MTD_XIP=y
+CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
+CONFIG_VECTORS_BASE=0xffff0000
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+CONFIG_CONSTRUCTORS=y
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION=""
+CONFIG_LOCALVERSION_AUTO=y
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+# CONFIG_POSIX_MQUEUE is not set
+# CONFIG_BSD_PROCESS_ACCT is not set
+# CONFIG_TASKSTATS is not set
+# CONFIG_AUDIT is not set
+
+#
+# RCU Subsystem
+#
+# CONFIG_TREE_RCU is not set
+# CONFIG_TREE_PREEMPT_RCU is not set
+CONFIG_TINY_RCU=y
+# CONFIG_TREE_RCU_TRACE is not set
+# CONFIG_IKCONFIG is not set
+CONFIG_LOG_BUF_SHIFT=13
+# CONFIG_GROUP_SCHED is not set
+# CONFIG_CGROUPS is not set
+# CONFIG_SYSFS_DEPRECATED_V2 is not set
+# CONFIG_RELAY is not set
+CONFIG_NAMESPACES=y
+# CONFIG_UTS_NS is not set
+# CONFIG_IPC_NS is not set
+# CONFIG_USER_NS is not set
+# CONFIG_PID_NS is not set
+# CONFIG_NET_NS is not set
+# CONFIG_BLK_DEV_INITRD is not set
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_SYSCTL=y
+CONFIG_ANON_INODES=y
+# CONFIG_EMBEDDED is not set
+CONFIG_UID16=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_ALL is not set
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_AIO=y
+
+#
+# Kernel Performance Events And Counters
+#
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLUB_DEBUG=y
+CONFIG_COMPAT_BRK=y
+# CONFIG_SLAB is not set
+CONFIG_SLUB=y
+# CONFIG_SLOB is not set
+# CONFIG_PROFILING is not set
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_KPROBES is not set
+CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_KRETPROBES=y
+CONFIG_HAVE_CLK=y
+
+#
+# GCOV-based kernel profiling
+#
+# CONFIG_SLOW_WORK is not set
+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+# CONFIG_MODULE_FORCE_LOAD is not set
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODULE_FORCE_UNLOAD is not set
+# CONFIG_MODVERSIONS is not set
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+CONFIG_BLOCK=y
+CONFIG_LBDAF=y
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_BLK_DEV_INTEGRITY is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_DEADLINE=y
+# CONFIG_IOSCHED_CFQ is not set
+CONFIG_DEFAULT_DEADLINE=y
+# CONFIG_DEFAULT_CFQ is not set
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="deadline"
+# CONFIG_INLINE_SPIN_TRYLOCK is not set
+# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set
+# CONFIG_INLINE_SPIN_LOCK is not set
+# CONFIG_INLINE_SPIN_LOCK_BH is not set
+# CONFIG_INLINE_SPIN_LOCK_IRQ is not set
+# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set
+CONFIG_INLINE_SPIN_UNLOCK=y
+# CONFIG_INLINE_SPIN_UNLOCK_BH is not set
+CONFIG_INLINE_SPIN_UNLOCK_IRQ=y
+# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set
+# CONFIG_INLINE_READ_TRYLOCK is not set
+# CONFIG_INLINE_READ_LOCK is not set
+# CONFIG_INLINE_READ_LOCK_BH is not set
+# CONFIG_INLINE_READ_LOCK_IRQ is not set
+# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set
+CONFIG_INLINE_READ_UNLOCK=y
+# CONFIG_INLINE_READ_UNLOCK_BH is not set
+CONFIG_INLINE_READ_UNLOCK_IRQ=y
+# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set
+# CONFIG_INLINE_WRITE_TRYLOCK is not set
+# CONFIG_INLINE_WRITE_LOCK is not set
+# CONFIG_INLINE_WRITE_LOCK_BH is not set
+# CONFIG_INLINE_WRITE_LOCK_IRQ is not set
+# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set
+CONFIG_INLINE_WRITE_UNLOCK=y
+# CONFIG_INLINE_WRITE_UNLOCK_BH is not set
+CONFIG_INLINE_WRITE_UNLOCK_IRQ=y
+# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set
+# CONFIG_MUTEX_SPIN_ON_OWNER is not set
+CONFIG_FREEZER=y
+
+#
+# System Type
+#
+CONFIG_MMU=y
+# CONFIG_ARCH_AAEC2000 is not set
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_REALVIEW is not set
+# CONFIG_ARCH_VERSATILE is not set
+# CONFIG_ARCH_AT91 is not set
+# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_GEMINI is not set
+# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_EP93XX is not set
+# CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_MXC is not set
+# CONFIG_ARCH_STMP3XXX is not set
+# CONFIG_ARCH_NETX is not set
+# CONFIG_ARCH_H720X is not set
+# CONFIG_ARCH_NOMADIK is not set
+# CONFIG_ARCH_IOP13XX is not set
+# CONFIG_ARCH_IOP32X is not set
+# CONFIG_ARCH_IOP33X is not set
+# CONFIG_ARCH_IXP23XX is not set
+# CONFIG_ARCH_IXP2000 is not set
+# CONFIG_ARCH_IXP4XX is not set
+# CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_DOVE is not set
+# CONFIG_ARCH_KIRKWOOD is not set
+# CONFIG_ARCH_LOKI is not set
+# CONFIG_ARCH_MV78XX0 is not set
+# CONFIG_ARCH_ORION5X is not set
+# CONFIG_ARCH_MMP is not set
+# CONFIG_ARCH_KS8695 is not set
+# CONFIG_ARCH_NS9XXX is not set
+# CONFIG_ARCH_W90X900 is not set
+# CONFIG_ARCH_PNX4008 is not set
+CONFIG_ARCH_PXA=y
+# CONFIG_ARCH_MSM is not set
+# CONFIG_ARCH_RPC is not set
+# CONFIG_ARCH_SA1100 is not set
+# CONFIG_ARCH_S3C2410 is not set
+# CONFIG_ARCH_S3C64XX is not set
+# CONFIG_ARCH_S5PC1XX is not set
+# CONFIG_ARCH_SHARK is not set
+# CONFIG_ARCH_LH7A40X is not set
+# CONFIG_ARCH_U300 is not set
+# CONFIG_ARCH_DAVINCI is not set
+# CONFIG_ARCH_OMAP is not set
+# CONFIG_ARCH_BCMRING is not set
+# CONFIG_ARCH_U8500 is not set
+
+#
+# Intel PXA2xx/PXA3xx Implementations
+#
+
+#
+# Intel/Marvell Dev Platforms (sorted by hardware release time)
+#
+# CONFIG_ARCH_LUBBOCK is not set
+# CONFIG_MACH_MAINSTONE is not set
+# CONFIG_MACH_ZYLONITE300 is not set
+# CONFIG_MACH_ZYLONITE320 is not set
+# CONFIG_MACH_LITTLETON is not set
+# CONFIG_MACH_TAVOREVB is not set
+# CONFIG_MACH_SAAR is not set
+
+#
+# Third Party Dev Platforms (sorted by vendor name)
+#
+# CONFIG_ARCH_PXA_IDP is not set
+# CONFIG_ARCH_VIPER is not set
+CONFIG_MACH_ARCOM_ZEUS=y
+# CONFIG_MACH_BALLOON3 is not set
+# CONFIG_MACH_CSB726 is not set
+# CONFIG_MACH_ARMCORE is not set
+# CONFIG_MACH_EM_X270 is not set
+# CONFIG_MACH_EXEDA is not set
+# CONFIG_MACH_CM_X300 is not set
+# CONFIG_ARCH_GUMSTIX is not set
+# CONFIG_MACH_INTELMOTE2 is not set
+# CONFIG_MACH_STARGATE2 is not set
+# CONFIG_MACH_XCEP is not set
+# CONFIG_TRIZEPS_PXA is not set
+CONFIG_ARCOM_PCMCIA=y
+# CONFIG_MACH_LOGICPD_PXA270 is not set
+# CONFIG_MACH_PCM027 is not set
+# CONFIG_MACH_COLIBRI is not set
+# CONFIG_MACH_COLIBRI300 is not set
+# CONFIG_MACH_COLIBRI320 is not set
+
+#
+# End-user Products (sorted by vendor name)
+#
+# CONFIG_MACH_H4700 is not set
+# CONFIG_MACH_H5000 is not set
+# CONFIG_MACH_HIMALAYA is not set
+# CONFIG_MACH_MAGICIAN is not set
+# CONFIG_MACH_MIOA701 is not set
+# CONFIG_PXA_EZX is not set
+# CONFIG_MACH_MP900C is not set
+# CONFIG_ARCH_PXA_PALM is not set
+# CONFIG_PXA_SHARPSL is not set
+# CONFIG_ARCH_PXA_ESERIES is not set
+CONFIG_PXA27x=y
+CONFIG_PXA_SSP=y
+CONFIG_PXA_HAVE_BOARD_IRQS=y
+CONFIG_PXA_HAVE_ISA_IRQS=y
+CONFIG_PLAT_PXA=y
+
+#
+# Processor Type
+#
+CONFIG_CPU_32=y
+CONFIG_CPU_XSCALE=y
+CONFIG_CPU_32v5=y
+CONFIG_CPU_ABRT_EV5T=y
+CONFIG_CPU_PABRT_LEGACY=y
+CONFIG_CPU_CACHE_VIVT=y
+CONFIG_CPU_TLB_V4WBI=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+
+#
+# Processor Features
+#
+CONFIG_ARM_THUMB=y
+# CONFIG_CPU_DCACHE_DISABLE is not set
+CONFIG_ARM_L1_CACHE_SHIFT=5
+CONFIG_IWMMXT=y
+CONFIG_XSCALE_PMU=y
+CONFIG_COMMON_CLKDEV=y
+
+#
+# Bus support
+#
+CONFIG_ISA=y
+# CONFIG_PCI_SYSCALL is not set
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+CONFIG_PCCARD=m
+CONFIG_PCMCIA=m
+CONFIG_PCMCIA_LOAD_CIS=y
+CONFIG_PCMCIA_IOCTL=y
+
+#
+# PC-card bridges
+#
+# CONFIG_I82365 is not set
+# CONFIG_TCIC is not set
+CONFIG_PCMCIA_SOC_COMMON=m
+CONFIG_PCMCIA_PXA2XX=m
+# CONFIG_PCMCIA_DEBUG is not set
+CONFIG_PCMCIA_PROBE=y
+
+#
+# Kernel Features
+#
+CONFIG_TICK_ONESHOT=y
+# CONFIG_NO_HZ is not set
+# CONFIG_HIGH_RES_TIMERS is not set
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+CONFIG_VMSPLIT_3G=y
+# CONFIG_VMSPLIT_2G is not set
+# CONFIG_VMSPLIT_1G is not set
+CONFIG_PAGE_OFFSET=0xC0000000
+CONFIG_PREEMPT_NONE=y
+# CONFIG_PREEMPT_VOLUNTARY is not set
+# CONFIG_PREEMPT is not set
+CONFIG_HZ=100
+CONFIG_AEABI=y
+CONFIG_OABI_COMPAT=y
+# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
+# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
+# CONFIG_HIGHMEM is not set
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_SPLIT_PTLOCK_CPUS=4096
+# CONFIG_PHYS_ADDR_T_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=0
+CONFIG_VIRT_TO_BUS=y
+CONFIG_HAVE_MLOCK=y
+CONFIG_HAVE_MLOCKED_PAGE_BIT=y
+# CONFIG_KSM is not set
+CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
+CONFIG_ALIGNMENT_TRAP=y
+# CONFIG_UACCESS_WITH_MEMCPY is not set
+
+#
+# Boot options
+#
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_CMDLINE="root=31:02 rootfstype=jffs2 ro console=ttyS0,115200"
+# CONFIG_XIP_KERNEL is not set
+# CONFIG_KEXEC is not set
+
+#
+# CPU Power Management
+#
+CONFIG_CPU_FREQ=y
+CONFIG_CPU_FREQ_TABLE=y
+# CONFIG_CPU_FREQ_DEBUG is not set
+CONFIG_CPU_FREQ_STAT=y
+# CONFIG_CPU_FREQ_STAT_DETAILS is not set
+CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y
+# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set
+CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
+CONFIG_CPU_FREQ_GOV_POWERSAVE=m
+CONFIG_CPU_FREQ_GOV_USERSPACE=m
+CONFIG_CPU_FREQ_GOV_ONDEMAND=m
+CONFIG_CPU_FREQ_GOV_CONSERVATIVE=m
+# CONFIG_CPU_IDLE is not set
+
+#
+# Floating point emulation
+#
+
+#
+# At least one emulation must be selected
+#
+CONFIG_FPE_NWFPE=y
+# CONFIG_FPE_NWFPE_XP is not set
+# CONFIG_FPE_FASTFPE is not set
+
+#
+# Userspace binary formats
+#
+CONFIG_BINFMT_ELF=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_HAVE_AOUT=y
+# CONFIG_BINFMT_AOUT is not set
+# CONFIG_BINFMT_MISC is not set
+
+#
+# Power management options
+#
+CONFIG_PM=y
+# CONFIG_PM_DEBUG is not set
+CONFIG_PM_SLEEP=y
+CONFIG_SUSPEND=y
+CONFIG_SUSPEND_FREEZER=y
+CONFIG_APM_EMULATION=y
+# CONFIG_PM_RUNTIME is not set
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+# CONFIG_PACKET_MMAP is not set
+CONFIG_UNIX=y
+CONFIG_XFRM=y
+# CONFIG_XFRM_USER is not set
+# CONFIG_XFRM_SUB_POLICY is not set
+# CONFIG_XFRM_MIGRATE is not set
+# CONFIG_XFRM_STATISTICS is not set
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+# CONFIG_IP_MULTICAST is not set
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+# CONFIG_IP_PNP_BOOTP is not set
+# CONFIG_IP_PNP_RARP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_ARPD is not set
+CONFIG_SYN_COOKIES=y
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
+# CONFIG_INET_TUNNEL is not set
+CONFIG_INET_XFRM_MODE_TRANSPORT=y
+CONFIG_INET_XFRM_MODE_TUNNEL=y
+CONFIG_INET_XFRM_MODE_BEET=y
+# CONFIG_INET_LRO is not set
+CONFIG_INET_DIAG=y
+CONFIG_INET_TCP_DIAG=y
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+# CONFIG_IPV6 is not set
+# CONFIG_NETWORK_SECMARK is not set
+# CONFIG_NETFILTER is not set
+# CONFIG_IP_DCCP is not set
+# CONFIG_IP_SCTP is not set
+# CONFIG_RDS is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_NET_DSA is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_PHONET is not set
+# CONFIG_IEEE802154 is not set
+# CONFIG_NET_SCHED is not set
+# CONFIG_DCB is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
+# CONFIG_IRDA is not set
+CONFIG_BT=m
+CONFIG_BT_L2CAP=m
+# CONFIG_BT_SCO is not set
+CONFIG_BT_RFCOMM=m
+CONFIG_BT_RFCOMM_TTY=y
+CONFIG_BT_BNEP=m
+# CONFIG_BT_BNEP_MC_FILTER is not set
+# CONFIG_BT_BNEP_PROTO_FILTER is not set
+# CONFIG_BT_HIDP is not set
+
+#
+# Bluetooth device drivers
+#
+# CONFIG_BT_HCIBTUSB is not set
+# CONFIG_BT_HCIBTSDIO is not set
+CONFIG_BT_HCIUART=m
+CONFIG_BT_HCIUART_H4=y
+CONFIG_BT_HCIUART_BCSP=y
+# CONFIG_BT_HCIUART_LL is not set
+# CONFIG_BT_HCIBCM203X is not set
+# CONFIG_BT_HCIBPA10X is not set
+# CONFIG_BT_HCIBFUSB is not set
+# CONFIG_BT_HCIDTL1 is not set
+# CONFIG_BT_HCIBT3C is not set
+# CONFIG_BT_HCIBLUECARD is not set
+# CONFIG_BT_HCIBTUART is not set
+# CONFIG_BT_HCIVHCI is not set
+# CONFIG_BT_MRVL is not set
+# CONFIG_AF_RXRPC is not set
+CONFIG_WIRELESS=y
+CONFIG_WIRELESS_EXT=y
+CONFIG_WEXT_CORE=y
+CONFIG_WEXT_PROC=y
+CONFIG_WEXT_SPY=y
+CONFIG_WEXT_PRIV=y
+CONFIG_CFG80211=m
+# CONFIG_NL80211_TESTMODE is not set
+# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set
+# CONFIG_CFG80211_REG_DEBUG is not set
+CONFIG_CFG80211_DEFAULT_PS=y
+# CONFIG_WIRELESS_OLD_REGULATORY is not set
+CONFIG_CFG80211_WEXT=y
+CONFIG_WIRELESS_EXT_SYSFS=y
+CONFIG_LIB80211=m
+# CONFIG_LIB80211_DEBUG is not set
+CONFIG_MAC80211=m
+CONFIG_MAC80211_RC_MINSTREL=y
+# CONFIG_MAC80211_RC_DEFAULT_PID is not set
+CONFIG_MAC80211_RC_DEFAULT_MINSTREL=y
+CONFIG_MAC80211_RC_DEFAULT="minstrel"
+# CONFIG_MAC80211_MESH is not set
+# CONFIG_MAC80211_LEDS is not set
+# CONFIG_MAC80211_DEBUG_MENU is not set
+# CONFIG_WIMAX is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+# CONFIG_DEVTMPFS is not set
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+CONFIG_FW_LOADER=y
+CONFIG_FIRMWARE_IN_KERNEL=y
+CONFIG_EXTRA_FIRMWARE=""
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
+# CONFIG_SYS_HYPERVISOR is not set
+# CONFIG_CONNECTOR is not set
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+# CONFIG_MTD_TESTS is not set
+# CONFIG_MTD_CONCAT is not set
+CONFIG_MTD_PARTITIONS=y
+CONFIG_MTD_REDBOOT_PARTS=y
+CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK=-1
+# CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED is not set
+CONFIG_MTD_REDBOOT_PARTS_READONLY=y
+# CONFIG_MTD_CMDLINE_PARTS is not set
+# CONFIG_MTD_AFS_PARTS is not set
+# CONFIG_MTD_AR7_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=m
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+CONFIG_MTD_CFI=y
+CONFIG_MTD_JEDECPROBE=y
+CONFIG_MTD_GEN_PROBE=y
+CONFIG_MTD_CFI_ADV_OPTIONS=y
+CONFIG_MTD_CFI_NOSWAP=y
+# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set
+# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set
+CONFIG_MTD_CFI_GEOMETRY=y
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+# CONFIG_MTD_MAP_BANK_WIDTH_4 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+# CONFIG_MTD_CFI_I2 is not set
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+# CONFIG_MTD_OTP is not set
+CONFIG_MTD_CFI_INTELEXT=y
+CONFIG_MTD_CFI_AMDSTD=y
+# CONFIG_MTD_CFI_STAA is not set
+CONFIG_MTD_CFI_UTIL=y
+CONFIG_MTD_RAM=y
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+# CONFIG_MTD_XIP is not set
+
+#
+# Mapping drivers for chip access
+#
+CONFIG_MTD_COMPLEX_MAPPINGS=y
+CONFIG_MTD_PHYSMAP=y
+# CONFIG_MTD_PHYSMAP_COMPAT is not set
+CONFIG_MTD_PXA2XX=y
+# CONFIG_MTD_ARM_INTEGRATOR is not set
+# CONFIG_MTD_IMPA7 is not set
+# CONFIG_MTD_GPIO_ADDR is not set
+# CONFIG_MTD_PLATRAM is not set
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_DATAFLASH is not set
+# CONFIG_MTD_M25P80 is not set
+# CONFIG_MTD_SST25L is not set
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+# CONFIG_MTD_NAND is not set
+# CONFIG_MTD_ONENAND is not set
+
+#
+# LPDDR flash memory drivers
+#
+# CONFIG_MTD_LPDDR is not set
+
+#
+# UBI - Unsorted block images
+#
+# CONFIG_MTD_UBI is not set
+# CONFIG_PARPORT is not set
+# CONFIG_PNP is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=m
+# CONFIG_BLK_DEV_CRYPTOLOOP is not set
+
+#
+# DRBD disabled because PROC_FS, INET or CONNECTOR not selected
+#
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_UB is not set
+# CONFIG_BLK_DEV_RAM is not set
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+# CONFIG_MG_DISK is not set
+CONFIG_MISC_DEVICES=y
+# CONFIG_ICS932S401 is not set
+# CONFIG_ENCLOSURE_SERVICES is not set
+# CONFIG_ISL29003 is not set
+# CONFIG_DS1682 is not set
+# CONFIG_C2PORT is not set
+
+#
+# EEPROM support
+#
+CONFIG_EEPROM_AT24=m
+# CONFIG_EEPROM_AT25 is not set
+# CONFIG_EEPROM_LEGACY is not set
+# CONFIG_EEPROM_MAX6875 is not set
+# CONFIG_EEPROM_93CX6 is not set
+# CONFIG_IWMC3200TOP is not set
+CONFIG_HAVE_IDE=y
+# CONFIG_IDE is not set
+
+#
+# SCSI device support
+#
+# CONFIG_RAID_ATTRS is not set
+CONFIG_SCSI=m
+CONFIG_SCSI_DMA=y
+# CONFIG_SCSI_TGT is not set
+# CONFIG_SCSI_NETLINK is not set
+# CONFIG_SCSI_PROC_FS is not set
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=m
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+# CONFIG_BLK_DEV_SR is not set
+# CONFIG_CHR_DEV_SG is not set
+# CONFIG_CHR_DEV_SCH is not set
+# CONFIG_SCSI_MULTI_LUN is not set
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+# CONFIG_SCSI_SCAN_ASYNC is not set
+CONFIG_SCSI_WAIT_SCAN=m
+
+#
+# SCSI Transports
+#
+# CONFIG_SCSI_SPI_ATTRS is not set
+# CONFIG_SCSI_FC_ATTRS is not set
+# CONFIG_SCSI_ISCSI_ATTRS is not set
+# CONFIG_SCSI_SAS_LIBSAS is not set
+# CONFIG_SCSI_SRP_ATTRS is not set
+CONFIG_SCSI_LOWLEVEL=y
+# CONFIG_ISCSI_TCP is not set
+# CONFIG_SCSI_AHA152X is not set
+# CONFIG_SCSI_AIC7XXX_OLD is not set
+# CONFIG_SCSI_ADVANSYS is not set
+# CONFIG_SCSI_IN2000 is not set
+# CONFIG_LIBFC is not set
+# CONFIG_LIBFCOE is not set
+# CONFIG_SCSI_DTC3280 is not set
+# CONFIG_SCSI_FUTURE_DOMAIN is not set
+# CONFIG_SCSI_GENERIC_NCR5380 is not set
+# CONFIG_SCSI_GENERIC_NCR5380_MMIO is not set
+# CONFIG_SCSI_NCR53C406A is not set
+# CONFIG_SCSI_PAS16 is not set
+# CONFIG_SCSI_QLOGIC_FAS is not set
+# CONFIG_SCSI_SYM53C416 is not set
+# CONFIG_SCSI_T128 is not set
+# CONFIG_SCSI_DEBUG is not set
+# CONFIG_SCSI_LOWLEVEL_PCMCIA is not set
+# CONFIG_SCSI_DH is not set
+# CONFIG_SCSI_OSD_INITIATOR is not set
+CONFIG_ATA=m
+# CONFIG_ATA_NONSTANDARD is not set
+CONFIG_ATA_VERBOSE_ERROR=y
+# CONFIG_SATA_PMP is not set
+CONFIG_ATA_SFF=y
+# CONFIG_SATA_MV is not set
+# CONFIG_PATA_LEGACY is not set
+CONFIG_PATA_PCMCIA=m
+# CONFIG_PATA_QDI is not set
+# CONFIG_PATA_WINBOND_VLB is not set
+# CONFIG_MD is not set
+CONFIG_NETDEVICES=y
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_VETH is not set
+# CONFIG_ARCNET is not set
+# CONFIG_PHYLIB is not set
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
+# CONFIG_AX88796 is not set
+# CONFIG_NET_VENDOR_3COM is not set
+# CONFIG_NET_VENDOR_SMC is not set
+# CONFIG_SMC91X is not set
+CONFIG_DM9000=y
+CONFIG_DM9000_DEBUGLEVEL=4
+# CONFIG_DM9000_FORCE_SIMPLE_PHY_POLL is not set
+# CONFIG_ENC28J60 is not set
+# CONFIG_ETHOC is not set
+# CONFIG_SMC911X is not set
+# CONFIG_SMSC911X is not set
+# CONFIG_NET_VENDOR_RACAL is not set
+# CONFIG_DNET is not set
+# CONFIG_AT1700 is not set
+# CONFIG_DEPCA is not set
+# CONFIG_HP100 is not set
+# CONFIG_NET_ISA is not set
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
+# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
+# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
+# CONFIG_NET_PCI is not set
+# CONFIG_B44 is not set
+# CONFIG_CS89x0 is not set
+# CONFIG_KS8842 is not set
+# CONFIG_KS8851 is not set
+# CONFIG_KS8851_MLL is not set
+# CONFIG_NETDEV_1000 is not set
+# CONFIG_NETDEV_10000 is not set
+# CONFIG_TR is not set
+CONFIG_WLAN=y
+# CONFIG_PCMCIA_RAYCS is not set
+# CONFIG_LIBERTAS_THINFIRM is not set
+# CONFIG_ATMEL is not set
+# CONFIG_AT76C50X_USB is not set
+# CONFIG_AIRO_CS is not set
+# CONFIG_PCMCIA_WL3501 is not set
+# CONFIG_USB_ZD1201 is not set
+# CONFIG_USB_NET_RNDIS_WLAN is not set
+# CONFIG_RTL8187 is not set
+# CONFIG_MAC80211_HWSIM is not set
+# CONFIG_ATH_COMMON is not set
+# CONFIG_B43 is not set
+# CONFIG_B43LEGACY is not set
+# CONFIG_HOSTAP is not set
+# CONFIG_IWM is not set
+# CONFIG_LIBERTAS is not set
+CONFIG_HERMES=m
+CONFIG_HERMES_CACHE_FW_ON_INIT=y
+CONFIG_PCMCIA_HERMES=m
+# CONFIG_PCMCIA_SPECTRUM is not set
+# CONFIG_P54_COMMON is not set
+CONFIG_RT2X00=m
+# CONFIG_RT2500USB is not set
+CONFIG_RT73USB=m
+# CONFIG_RT2800USB is not set
+CONFIG_RT2X00_LIB_USB=m
+CONFIG_RT2X00_LIB=m
+CONFIG_RT2X00_LIB_FIRMWARE=y
+CONFIG_RT2X00_LIB_CRYPTO=y
+CONFIG_RT2X00_LIB_LEDS=y
+# CONFIG_RT2X00_DEBUG is not set
+# CONFIG_WL12XX is not set
+# CONFIG_ZD1211RW is not set
+
+#
+# Enable WiMAX (Networking options) to see the WiMAX drivers
+#
+
+#
+# USB Network Adapters
+#
+# CONFIG_USB_CATC is not set
+# CONFIG_USB_KAWETH is not set
+# CONFIG_USB_PEGASUS is not set
+# CONFIG_USB_RTL8150 is not set
+# CONFIG_USB_USBNET is not set
+CONFIG_NET_PCMCIA=y
+# CONFIG_PCMCIA_3C589 is not set
+# CONFIG_PCMCIA_3C574 is not set
+# CONFIG_PCMCIA_FMVJ18X is not set
+# CONFIG_PCMCIA_PCNET is not set
+# CONFIG_PCMCIA_NMCLAN is not set
+# CONFIG_PCMCIA_SMC91C92 is not set
+# CONFIG_PCMCIA_XIRC2PS is not set
+# CONFIG_PCMCIA_AXNET is not set
+# CONFIG_WAN is not set
+CONFIG_PPP=m
+# CONFIG_PPP_MULTILINK is not set
+# CONFIG_PPP_FILTER is not set
+CONFIG_PPP_ASYNC=m
+# CONFIG_PPP_SYNC_TTY is not set
+CONFIG_PPP_DEFLATE=m
+CONFIG_PPP_BSDCOMP=m
+# CONFIG_PPP_MPPE is not set
+# CONFIG_PPPOE is not set
+# CONFIG_PPPOL2TP is not set
+# CONFIG_SLIP is not set
+CONFIG_SLHC=m
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_ISDN is not set
+# CONFIG_PHONE is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
+
+#
+# Userland interfaces
+#
+CONFIG_INPUT_MOUSEDEV=y
+# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+# CONFIG_INPUT_JOYDEV is not set
+CONFIG_INPUT_EVDEV=m
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input Device Drivers
+#
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+CONFIG_INPUT_TOUCHSCREEN=y
+# CONFIG_TOUCHSCREEN_ADS7846 is not set
+# CONFIG_TOUCHSCREEN_AD7877 is not set
+# CONFIG_TOUCHSCREEN_AD7879_I2C is not set
+# CONFIG_TOUCHSCREEN_AD7879_SPI is not set
+# CONFIG_TOUCHSCREEN_AD7879 is not set
+# CONFIG_TOUCHSCREEN_EETI is not set
+CONFIG_TOUCHSCREEN_FUJITSU=m
+# CONFIG_TOUCHSCREEN_GUNZE is not set
+CONFIG_TOUCHSCREEN_ELO=m
+# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set
+# CONFIG_TOUCHSCREEN_MCS5000 is not set
+CONFIG_TOUCHSCREEN_MTOUCH=m
+CONFIG_TOUCHSCREEN_INEXIO=m
+# CONFIG_TOUCHSCREEN_MK712 is not set
+CONFIG_TOUCHSCREEN_HTCPEN=m
+CONFIG_TOUCHSCREEN_PENMOUNT=m
+CONFIG_TOUCHSCREEN_TOUCHRIGHT=m
+CONFIG_TOUCHSCREEN_TOUCHWIN=m
+# CONFIG_TOUCHSCREEN_WM97XX is not set
+# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set
+CONFIG_TOUCHSCREEN_TOUCHIT213=m
+# CONFIG_TOUCHSCREEN_TSC2007 is not set
+# CONFIG_TOUCHSCREEN_W90X900 is not set
+CONFIG_INPUT_MISC=y
+# CONFIG_INPUT_ATI_REMOTE is not set
+# CONFIG_INPUT_ATI_REMOTE2 is not set
+# CONFIG_INPUT_KEYSPAN_REMOTE is not set
+# CONFIG_INPUT_POWERMATE is not set
+# CONFIG_INPUT_YEALINK is not set
+# CONFIG_INPUT_CM109 is not set
+CONFIG_INPUT_UINPUT=m
+# CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set
+
+#
+# Hardware I/O ports
+#
+CONFIG_SERIO=y
+CONFIG_SERIO_SERPORT=y
+# CONFIG_SERIO_RAW is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+# CONFIG_VT_HW_CONSOLE_BINDING is not set
+CONFIG_DEVKMEM=y
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+# CONFIG_SERIAL_8250_CS is not set
+CONFIG_SERIAL_8250_NR_UARTS=7
+CONFIG_SERIAL_8250_RUNTIME_UARTS=7
+# CONFIG_SERIAL_8250_EXTENDED is not set
+
+#
+# Non-8250 serial port support
+#
+# CONFIG_SERIAL_MAX3100 is not set
+# CONFIG_SERIAL_PXA is not set
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_UNIX98_PTYS=y
+# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
+# CONFIG_LEGACY_PTYS is not set
+# CONFIG_IPMI_HANDLER is not set
+CONFIG_HW_RANDOM=m
+# CONFIG_HW_RANDOM_TIMERIOMEM is not set
+# CONFIG_DTLK is not set
+# CONFIG_R3964 is not set
+
+#
+# PCMCIA character devices
+#
+# CONFIG_SYNCLINK_CS is not set
+# CONFIG_CARDMAN_4000 is not set
+# CONFIG_CARDMAN_4040 is not set
+# CONFIG_IPWIRELESS is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+CONFIG_DEVPORT=y
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_COMPAT=y
+CONFIG_I2C_CHARDEV=y
+# CONFIG_I2C_HELPER_AUTO is not set
+
+#
+# I2C Algorithms
+#
+CONFIG_I2C_ALGOBIT=y
+# CONFIG_I2C_ALGOPCF is not set
+# CONFIG_I2C_ALGOPCA is not set
+
+#
+# I2C Hardware Bus support
+#
+
+#
+# I2C system bus drivers (mostly embedded / system-on-chip)
+#
+# CONFIG_I2C_DESIGNWARE is not set
+CONFIG_I2C_GPIO=y
+# CONFIG_I2C_OCORES is not set
+CONFIG_I2C_PXA=y
+# CONFIG_I2C_PXA_SLAVE is not set
+# CONFIG_I2C_SIMTEC is not set
+
+#
+# External I2C/SMBus adapter drivers
+#
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_TAOS_EVM is not set
+# CONFIG_I2C_TINY_USB is not set
+
+#
+# Other I2C/SMBus bus drivers
+#
+# CONFIG_I2C_ELEKTOR is not set
+# CONFIG_I2C_PCA_ISA is not set
+# CONFIG_I2C_PCA_PLATFORM is not set
+# CONFIG_I2C_STUB is not set
+
+#
+# Miscellaneous I2C Chip support
+#
+# CONFIG_SENSORS_TSL2550 is not set
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+# CONFIG_I2C_DEBUG_CHIP is not set
+CONFIG_SPI=y
+# CONFIG_SPI_DEBUG is not set
+CONFIG_SPI_MASTER=y
+
+#
+# SPI Master Controller Drivers
+#
+# CONFIG_SPI_BITBANG is not set
+# CONFIG_SPI_GPIO is not set
+CONFIG_SPI_PXA2XX=y
+
+#
+# SPI Protocol Masters
+#
+# CONFIG_SPI_SPIDEV is not set
+# CONFIG_SPI_TLE62X0 is not set
+
+#
+# PPS support
+#
+# CONFIG_PPS is not set
+CONFIG_ARCH_REQUIRE_GPIOLIB=y
+CONFIG_GPIOLIB=y
+# CONFIG_DEBUG_GPIO is not set
+CONFIG_GPIO_SYSFS=y
+
+#
+# Memory mapped GPIO expanders:
+#
+
+#
+# I2C GPIO expanders:
+#
+# CONFIG_GPIO_MAX732X is not set
+CONFIG_GPIO_PCA953X=y
+# CONFIG_GPIO_PCF857X is not set
+
+#
+# PCI GPIO expanders:
+#
+
+#
+# SPI GPIO expanders:
+#
+# CONFIG_GPIO_MAX7301 is not set
+# CONFIG_GPIO_MCP23S08 is not set
+# CONFIG_GPIO_MC33880 is not set
+
+#
+# AC97 GPIO expanders:
+#
+# CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
+CONFIG_HWMON=y
+# CONFIG_HWMON_VID is not set
+# CONFIG_HWMON_DEBUG_CHIP is not set
+
+#
+# Native drivers
+#
+# CONFIG_SENSORS_AD7414 is not set
+# CONFIG_SENSORS_AD7418 is not set
+# CONFIG_SENSORS_ADCXX is not set
+# CONFIG_SENSORS_ADM1021 is not set
+# CONFIG_SENSORS_ADM1025 is not set
+# CONFIG_SENSORS_ADM1026 is not set
+# CONFIG_SENSORS_ADM1029 is not set
+# CONFIG_SENSORS_ADM1031 is not set
+# CONFIG_SENSORS_ADM9240 is not set
+# CONFIG_SENSORS_ADT7462 is not set
+# CONFIG_SENSORS_ADT7470 is not set
+# CONFIG_SENSORS_ADT7473 is not set
+# CONFIG_SENSORS_ADT7475 is not set
+# CONFIG_SENSORS_ATXP1 is not set
+# CONFIG_SENSORS_DS1621 is not set
+# CONFIG_SENSORS_F71805F is not set
+# CONFIG_SENSORS_F71882FG is not set
+# CONFIG_SENSORS_F75375S is not set
+# CONFIG_SENSORS_G760A is not set
+# CONFIG_SENSORS_GL518SM is not set
+# CONFIG_SENSORS_GL520SM is not set
+# CONFIG_SENSORS_IT87 is not set
+# CONFIG_SENSORS_LM63 is not set
+# CONFIG_SENSORS_LM70 is not set
+CONFIG_SENSORS_LM75=m
+# CONFIG_SENSORS_LM77 is not set
+# CONFIG_SENSORS_LM78 is not set
+# CONFIG_SENSORS_LM80 is not set
+# CONFIG_SENSORS_LM83 is not set
+# CONFIG_SENSORS_LM85 is not set
+# CONFIG_SENSORS_LM87 is not set
+# CONFIG_SENSORS_LM90 is not set
+# CONFIG_SENSORS_LM92 is not set
+# CONFIG_SENSORS_LM93 is not set
+# CONFIG_SENSORS_LTC4215 is not set
+# CONFIG_SENSORS_LTC4245 is not set
+# CONFIG_SENSORS_LM95241 is not set
+# CONFIG_SENSORS_MAX1111 is not set
+# CONFIG_SENSORS_MAX1619 is not set
+# CONFIG_SENSORS_MAX6650 is not set
+# CONFIG_SENSORS_PC87360 is not set
+# CONFIG_SENSORS_PC87427 is not set
+# CONFIG_SENSORS_PCF8591 is not set
+# CONFIG_SENSORS_SHT15 is not set
+# CONFIG_SENSORS_DME1737 is not set
+# CONFIG_SENSORS_SMSC47M1 is not set
+# CONFIG_SENSORS_SMSC47M192 is not set
+# CONFIG_SENSORS_SMSC47B397 is not set
+# CONFIG_SENSORS_ADS7828 is not set
+# CONFIG_SENSORS_THMC50 is not set
+# CONFIG_SENSORS_TMP401 is not set
+# CONFIG_SENSORS_TMP421 is not set
+# CONFIG_SENSORS_VT1211 is not set
+# CONFIG_SENSORS_W83781D is not set
+# CONFIG_SENSORS_W83791D is not set
+# CONFIG_SENSORS_W83792D is not set
+# CONFIG_SENSORS_W83793 is not set
+# CONFIG_SENSORS_W83L785TS is not set
+# CONFIG_SENSORS_W83L786NG is not set
+# CONFIG_SENSORS_W83627HF is not set
+# CONFIG_SENSORS_W83627EHF is not set
+# CONFIG_SENSORS_LIS3_SPI is not set
+# CONFIG_THERMAL is not set
+CONFIG_WATCHDOG=y
+# CONFIG_WATCHDOG_NOWAYOUT is not set
+
+#
+# Watchdog Device Drivers
+#
+# CONFIG_SOFT_WATCHDOG is not set
+# CONFIG_SA1100_WATCHDOG is not set
+
+#
+# ISA-based Watchdog Cards
+#
+# CONFIG_PCWATCHDOG is not set
+# CONFIG_MIXCOMWD is not set
+# CONFIG_WDT is not set
+
+#
+# USB-based Watchdog Cards
+#
+# CONFIG_USBPCWATCHDOG is not set
+CONFIG_SSB_POSSIBLE=y
+
+#
+# Sonics Silicon Backplane
+#
+# CONFIG_SSB is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_CORE is not set
+# CONFIG_MFD_SM501 is not set
+# CONFIG_MFD_ASIC3 is not set
+# CONFIG_HTC_EGPIO is not set
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_UCB1400_CORE is not set
+# CONFIG_TPS65010 is not set
+# CONFIG_TWL4030_CORE is not set
+# CONFIG_MFD_TMIO is not set
+# CONFIG_MFD_T7L66XB is not set
+# CONFIG_MFD_TC6387XB is not set
+# CONFIG_MFD_TC6393XB is not set
+# CONFIG_PMIC_DA903X is not set
+# CONFIG_MFD_WM8400 is not set
+# CONFIG_MFD_WM831X is not set
+# CONFIG_MFD_WM8350_I2C is not set
+# CONFIG_MFD_PCF50633 is not set
+# CONFIG_MFD_MC13783 is not set
+# CONFIG_AB3100_CORE is not set
+# CONFIG_EZX_PCAP is not set
+# CONFIG_REGULATOR is not set
+# CONFIG_MEDIA_SUPPORT is not set
+
+#
+# Graphics support
+#
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+CONFIG_FB=y
+# CONFIG_FIRMWARE_EDID is not set
+# CONFIG_FB_DDC is not set
+# CONFIG_FB_BOOT_VESA_SUPPORT is not set
+CONFIG_FB_CFB_FILLRECT=m
+CONFIG_FB_CFB_COPYAREA=m
+CONFIG_FB_CFB_IMAGEBLIT=m
+# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
+# CONFIG_FB_SYS_FILLRECT is not set
+# CONFIG_FB_SYS_COPYAREA is not set
+# CONFIG_FB_SYS_IMAGEBLIT is not set
+# CONFIG_FB_FOREIGN_ENDIAN is not set
+# CONFIG_FB_SYS_FOPS is not set
+# CONFIG_FB_SVGALIB is not set
+# CONFIG_FB_MACMODES is not set
+# CONFIG_FB_BACKLIGHT is not set
+# CONFIG_FB_MODE_HELPERS is not set
+# CONFIG_FB_TILEBLITTING is not set
+
+#
+# Frame buffer hardware drivers
+#
+# CONFIG_FB_S1D13XXX is not set
+CONFIG_FB_PXA=m
+# CONFIG_FB_PXA_OVERLAY is not set
+# CONFIG_FB_PXA_SMARTPANEL is not set
+CONFIG_FB_PXA_PARAMETERS=y
+# CONFIG_FB_MBX is not set
+# CONFIG_FB_W100 is not set
+# CONFIG_FB_VIRTUAL is not set
+# CONFIG_FB_METRONOME is not set
+# CONFIG_FB_MB862XX is not set
+# CONFIG_FB_BROADSHEET is not set
+CONFIG_BACKLIGHT_LCD_SUPPORT=y
+CONFIG_LCD_CLASS_DEVICE=m
+# CONFIG_LCD_LMS283GF05 is not set
+# CONFIG_LCD_LTV350QV is not set
+# CONFIG_LCD_ILI9320 is not set
+# CONFIG_LCD_TDO24M is not set
+# CONFIG_LCD_VGG2432A4 is not set
+# CONFIG_LCD_PLATFORM is not set
+CONFIG_BACKLIGHT_CLASS_DEVICE=m
+CONFIG_BACKLIGHT_GENERIC=m
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+
+#
+# Console display driver support
+#
+# CONFIG_VGA_CONSOLE is not set
+# CONFIG_MDA_CONSOLE is not set
+CONFIG_DUMMY_CONSOLE=y
+CONFIG_FRAMEBUFFER_CONSOLE=m
+# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
+# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
+# CONFIG_FONTS is not set
+CONFIG_FONT_8x8=y
+CONFIG_FONT_8x16=y
+CONFIG_LOGO=y
+CONFIG_LOGO_LINUX_MONO=y
+CONFIG_LOGO_LINUX_VGA16=y
+CONFIG_LOGO_LINUX_CLUT224=y
+CONFIG_SOUND=m
+CONFIG_SOUND_OSS_CORE=y
+CONFIG_SOUND_OSS_CORE_PRECLAIM=y
+CONFIG_SND=m
+CONFIG_SND_TIMER=m
+CONFIG_SND_PCM=m
+CONFIG_SND_JACK=y
+# CONFIG_SND_SEQUENCER is not set
+CONFIG_SND_OSSEMUL=y
+CONFIG_SND_MIXER_OSS=m
+CONFIG_SND_PCM_OSS=m
+CONFIG_SND_PCM_OSS_PLUGINS=y
+# CONFIG_SND_DYNAMIC_MINORS is not set
+# CONFIG_SND_SUPPORT_OLD_API is not set
+CONFIG_SND_VERBOSE_PROCFS=y
+# CONFIG_SND_VERBOSE_PRINTK is not set
+# CONFIG_SND_DEBUG is not set
+CONFIG_SND_VMASTER=y
+# CONFIG_SND_RAWMIDI_SEQ is not set
+# CONFIG_SND_OPL3_LIB_SEQ is not set
+# CONFIG_SND_OPL4_LIB_SEQ is not set
+# CONFIG_SND_SBAWE_SEQ is not set
+# CONFIG_SND_EMU10K1_SEQ is not set
+CONFIG_SND_AC97_CODEC=m
+CONFIG_SND_DRIVERS=y
+# CONFIG_SND_DUMMY is not set
+# CONFIG_SND_MTPAV is not set
+# CONFIG_SND_SERIAL_U16550 is not set
+# CONFIG_SND_MPU401 is not set
+# CONFIG_SND_AC97_POWER_SAVE is not set
+CONFIG_SND_ARM=y
+CONFIG_SND_PXA2XX_PCM=m
+CONFIG_SND_PXA2XX_LIB=m
+CONFIG_SND_PXA2XX_LIB_AC97=y
+CONFIG_SND_PXA2XX_AC97=m
+# CONFIG_SND_SPI is not set
+CONFIG_SND_USB=y
+# CONFIG_SND_USB_AUDIO is not set
+# CONFIG_SND_USB_CAIAQ is not set
+# CONFIG_SND_PCMCIA is not set
+CONFIG_SND_SOC=m
+CONFIG_SND_PXA2XX_SOC=m
+CONFIG_SND_SOC_I2C_AND_SPI=m
+# CONFIG_SND_SOC_ALL_CODECS is not set
+# CONFIG_SOUND_PRIME is not set
+CONFIG_AC97_BUS=m
+# CONFIG_HID_SUPPORT is not set
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_ARCH_HAS_HCD=y
+CONFIG_USB_ARCH_HAS_OHCI=y
+# CONFIG_USB_ARCH_HAS_EHCI is not set
+CONFIG_USB=m
+# CONFIG_USB_DEBUG is not set
+# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
+
+#
+# Miscellaneous USB options
+#
+CONFIG_USB_DEVICEFS=y
+CONFIG_USB_DEVICE_CLASS=y
+# CONFIG_USB_DYNAMIC_MINORS is not set
+CONFIG_USB_SUSPEND=y
+# CONFIG_USB_OTG is not set
+# CONFIG_USB_MON is not set
+# CONFIG_USB_WUSB is not set
+# CONFIG_USB_WUSB_CBAF is not set
+
+#
+# USB Host Controller Drivers
+#
+# CONFIG_USB_C67X00_HCD is not set
+# CONFIG_USB_OXU210HP_HCD is not set
+# CONFIG_USB_ISP116X_HCD is not set
+# CONFIG_USB_ISP1760_HCD is not set
+# CONFIG_USB_ISP1362_HCD is not set
+CONFIG_USB_OHCI_HCD=m
+# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
+# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
+CONFIG_USB_OHCI_LITTLE_ENDIAN=y
+# CONFIG_USB_SL811_HCD is not set
+# CONFIG_USB_R8A66597_HCD is not set
+# CONFIG_USB_HWA_HCD is not set
+# CONFIG_USB_MUSB_HDRC is not set
+# CONFIG_USB_GADGET_MUSB_HDRC is not set
+
+#
+# USB Device Class drivers
+#
+CONFIG_USB_ACM=m
+# CONFIG_USB_PRINTER is not set
+# CONFIG_USB_WDM is not set
+# CONFIG_USB_TMC is not set
+
+#
+# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
+#
+
+#
+# also be needed; see USB_STORAGE Help for more info
+#
+CONFIG_USB_STORAGE=m
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
+# CONFIG_USB_STORAGE_USBAT is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_SDDR55 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_STORAGE_ALAUDA is not set
+# CONFIG_USB_STORAGE_ONETOUCH is not set
+# CONFIG_USB_STORAGE_KARMA is not set
+# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
+# CONFIG_USB_LIBUSUAL is not set
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_MICROTEK is not set
+
+#
+# USB port drivers
+#
+CONFIG_USB_SERIAL=m
+# CONFIG_USB_EZUSB is not set
+CONFIG_USB_SERIAL_GENERIC=y
+# CONFIG_USB_SERIAL_AIRCABLE is not set
+# CONFIG_USB_SERIAL_ARK3116 is not set
+# CONFIG_USB_SERIAL_BELKIN is not set
+# CONFIG_USB_SERIAL_CH341 is not set
+# CONFIG_USB_SERIAL_WHITEHEAT is not set
+# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set
+# CONFIG_USB_SERIAL_CP210X is not set
+# CONFIG_USB_SERIAL_CYPRESS_M8 is not set
+# CONFIG_USB_SERIAL_EMPEG is not set
+# CONFIG_USB_SERIAL_FTDI_SIO is not set
+# CONFIG_USB_SERIAL_FUNSOFT is not set
+# CONFIG_USB_SERIAL_VISOR is not set
+# CONFIG_USB_SERIAL_IPAQ is not set
+# CONFIG_USB_SERIAL_IR is not set
+# CONFIG_USB_SERIAL_EDGEPORT is not set
+# CONFIG_USB_SERIAL_EDGEPORT_TI is not set
+# CONFIG_USB_SERIAL_GARMIN is not set
+# CONFIG_USB_SERIAL_IPW is not set
+# CONFIG_USB_SERIAL_IUU is not set
+# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set
+# CONFIG_USB_SERIAL_KEYSPAN is not set
+# CONFIG_USB_SERIAL_KLSI is not set
+# CONFIG_USB_SERIAL_KOBIL_SCT is not set
+CONFIG_USB_SERIAL_MCT_U232=m
+# CONFIG_USB_SERIAL_MOS7720 is not set
+# CONFIG_USB_SERIAL_MOS7840 is not set
+# CONFIG_USB_SERIAL_MOTOROLA is not set
+# CONFIG_USB_SERIAL_NAVMAN is not set
+# CONFIG_USB_SERIAL_PL2303 is not set
+# CONFIG_USB_SERIAL_OTI6858 is not set
+# CONFIG_USB_SERIAL_QUALCOMM is not set
+# CONFIG_USB_SERIAL_SPCP8X5 is not set
+# CONFIG_USB_SERIAL_HP4X is not set
+# CONFIG_USB_SERIAL_SAFE is not set
+# CONFIG_USB_SERIAL_SIEMENS_MPI is not set
+# CONFIG_USB_SERIAL_SIERRAWIRELESS is not set
+# CONFIG_USB_SERIAL_SYMBOL is not set
+# CONFIG_USB_SERIAL_TI is not set
+# CONFIG_USB_SERIAL_CYBERJACK is not set
+# CONFIG_USB_SERIAL_XIRCOM is not set
+# CONFIG_USB_SERIAL_OPTION is not set
+# CONFIG_USB_SERIAL_OMNINET is not set
+# CONFIG_USB_SERIAL_OPTICON is not set
+# CONFIG_USB_SERIAL_DEBUG is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_EMI62 is not set
+# CONFIG_USB_EMI26 is not set
+# CONFIG_USB_ADUTUX is not set
+# CONFIG_USB_SEVSEG is not set
+# CONFIG_USB_RIO500 is not set
+# CONFIG_USB_LEGOTOWER is not set
+# CONFIG_USB_LCD is not set
+# CONFIG_USB_BERRY_CHARGE is not set
+# CONFIG_USB_LED is not set
+# CONFIG_USB_CYPRESS_CY7C63 is not set
+# CONFIG_USB_CYTHERM is not set
+# CONFIG_USB_IDMOUSE is not set
+# CONFIG_USB_FTDI_ELAN is not set
+# CONFIG_USB_APPLEDISPLAY is not set
+# CONFIG_USB_LD is not set
+# CONFIG_USB_TRANCEVIBRATOR is not set
+# CONFIG_USB_IOWARRIOR is not set
+# CONFIG_USB_TEST is not set
+# CONFIG_USB_ISIGHTFW is not set
+# CONFIG_USB_VST is not set
+CONFIG_USB_GADGET=m
+# CONFIG_USB_GADGET_DEBUG is not set
+# CONFIG_USB_GADGET_DEBUG_FILES is not set
+CONFIG_USB_GADGET_VBUS_DRAW=2
+CONFIG_USB_GADGET_SELECTED=y
+# CONFIG_USB_GADGET_AT91 is not set
+# CONFIG_USB_GADGET_ATMEL_USBA is not set
+# CONFIG_USB_GADGET_FSL_USB2 is not set
+# CONFIG_USB_GADGET_LH7A40X is not set
+# CONFIG_USB_GADGET_OMAP is not set
+# CONFIG_USB_GADGET_PXA25X is not set
+# CONFIG_USB_GADGET_R8A66597 is not set
+CONFIG_USB_GADGET_PXA27X=y
+CONFIG_USB_PXA27X=m
+# CONFIG_USB_GADGET_S3C_HSOTG is not set
+# CONFIG_USB_GADGET_IMX is not set
+# CONFIG_USB_GADGET_S3C2410 is not set
+# CONFIG_USB_GADGET_M66592 is not set
+# CONFIG_USB_GADGET_AMD5536UDC is not set
+# CONFIG_USB_GADGET_FSL_QE is not set
+# CONFIG_USB_GADGET_CI13XXX is not set
+# CONFIG_USB_GADGET_NET2280 is not set
+# CONFIG_USB_GADGET_GOKU is not set
+# CONFIG_USB_GADGET_LANGWELL is not set
+# CONFIG_USB_GADGET_DUMMY_HCD is not set
+# CONFIG_USB_GADGET_DUALSPEED is not set
+# CONFIG_USB_ZERO is not set
+# CONFIG_USB_AUDIO is not set
+CONFIG_USB_ETH=m
+CONFIG_USB_ETH_RNDIS=y
+# CONFIG_USB_ETH_EEM is not set
+CONFIG_USB_GADGETFS=m
+CONFIG_USB_FILE_STORAGE=m
+# CONFIG_USB_FILE_STORAGE_TEST is not set
+CONFIG_USB_G_SERIAL=m
+# CONFIG_USB_MIDI_GADGET is not set
+CONFIG_USB_G_PRINTER=m
+# CONFIG_USB_CDC_COMPOSITE is not set
+
+#
+# OTG and related infrastructure
+#
+CONFIG_USB_OTG_UTILS=y
+# CONFIG_USB_GPIO_VBUS is not set
+# CONFIG_NOP_USB_XCEIV is not set
+CONFIG_MMC=y
+# CONFIG_MMC_DEBUG is not set
+# CONFIG_MMC_UNSAFE_RESUME is not set
+
+#
+# MMC/SD/SDIO Card Drivers
+#
+CONFIG_MMC_BLOCK=y
+# CONFIG_MMC_BLOCK_BOUNCE is not set
+# CONFIG_SDIO_UART is not set
+# CONFIG_MMC_TEST is not set
+
+#
+# MMC/SD/SDIO Host Controller Drivers
+#
+CONFIG_MMC_PXA=y
+# CONFIG_MMC_SDHCI is not set
+# CONFIG_MMC_AT91 is not set
+# CONFIG_MMC_ATMELMCI is not set
+# CONFIG_MMC_SPI is not set
+# CONFIG_MEMSTICK is not set
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=m
+
+#
+# LED drivers
+#
+# CONFIG_LEDS_PCA9532 is not set
+CONFIG_LEDS_GPIO=m
+CONFIG_LEDS_GPIO_PLATFORM=y
+# CONFIG_LEDS_LP3944 is not set
+# CONFIG_LEDS_PCA955X is not set
+# CONFIG_LEDS_DAC124S085 is not set
+# CONFIG_LEDS_BD2802 is not set
+
+#
+# LED Triggers
+#
+CONFIG_LEDS_TRIGGERS=y
+CONFIG_LEDS_TRIGGER_TIMER=m
+CONFIG_LEDS_TRIGGER_HEARTBEAT=m
+CONFIG_LEDS_TRIGGER_BACKLIGHT=m
+CONFIG_LEDS_TRIGGER_GPIO=m
+CONFIG_LEDS_TRIGGER_DEFAULT_ON=m
+
+#
+# iptables trigger is under Netfilter config (LED target)
+#
+# CONFIG_ACCESSIBILITY is not set
+CONFIG_RTC_LIB=y
+CONFIG_RTC_CLASS=m
+
+#
+# RTC interfaces
+#
+CONFIG_RTC_INTF_SYSFS=y
+CONFIG_RTC_INTF_PROC=y
+CONFIG_RTC_INTF_DEV=y
+# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
+# CONFIG_RTC_DRV_TEST is not set
+
+#
+# I2C RTC drivers
+#
+# CONFIG_RTC_DRV_DS1307 is not set
+# CONFIG_RTC_DRV_DS1374 is not set
+# CONFIG_RTC_DRV_DS1672 is not set
+# CONFIG_RTC_DRV_MAX6900 is not set
+# CONFIG_RTC_DRV_RS5C372 is not set
+CONFIG_RTC_DRV_ISL1208=m
+# CONFIG_RTC_DRV_X1205 is not set
+# CONFIG_RTC_DRV_PCF8563 is not set
+# CONFIG_RTC_DRV_PCF8583 is not set
+# CONFIG_RTC_DRV_M41T80 is not set
+# CONFIG_RTC_DRV_S35390A is not set
+# CONFIG_RTC_DRV_FM3130 is not set
+# CONFIG_RTC_DRV_RX8581 is not set
+# CONFIG_RTC_DRV_RX8025 is not set
+
+#
+# SPI RTC drivers
+#
+# CONFIG_RTC_DRV_M41T94 is not set
+# CONFIG_RTC_DRV_DS1305 is not set
+# CONFIG_RTC_DRV_DS1390 is not set
+# CONFIG_RTC_DRV_MAX6902 is not set
+# CONFIG_RTC_DRV_R9701 is not set
+# CONFIG_RTC_DRV_RS5C348 is not set
+# CONFIG_RTC_DRV_DS3234 is not set
+# CONFIG_RTC_DRV_PCF2123 is not set
+
+#
+# Platform RTC drivers
+#
+# CONFIG_RTC_DRV_CMOS is not set
+# CONFIG_RTC_DRV_DS1286 is not set
+# CONFIG_RTC_DRV_DS1511 is not set
+# CONFIG_RTC_DRV_DS1553 is not set
+# CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_STK17TA8 is not set
+# CONFIG_RTC_DRV_M48T86 is not set
+# CONFIG_RTC_DRV_M48T35 is not set
+# CONFIG_RTC_DRV_M48T59 is not set
+# CONFIG_RTC_DRV_MSM6242 is not set
+# CONFIG_RTC_DRV_BQ4802 is not set
+# CONFIG_RTC_DRV_RP5C01 is not set
+# CONFIG_RTC_DRV_V3020 is not set
+
+#
+# on-CPU RTC drivers
+#
+# CONFIG_RTC_DRV_SA1100 is not set
+CONFIG_RTC_DRV_PXA=m
+# CONFIG_DMADEVICES is not set
+# CONFIG_AUXDISPLAY is not set
+# CONFIG_UIO is not set
+
+#
+# TI VLYNQ
+#
+# CONFIG_STAGING is not set
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+# CONFIG_EXT2_FS_XATTR is not set
+# CONFIG_EXT2_FS_XIP is not set
+CONFIG_EXT3_FS=y
+# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
+# CONFIG_EXT3_FS_XATTR is not set
+# CONFIG_EXT4_FS is not set
+CONFIG_JBD=y
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+# CONFIG_FS_POSIX_ACL is not set
+# CONFIG_XFS_FS is not set
+# CONFIG_GFS2_FS is not set
+# CONFIG_OCFS2_FS is not set
+# CONFIG_BTRFS_FS is not set
+# CONFIG_NILFS2_FS is not set
+CONFIG_FILE_LOCKING=y
+CONFIG_FSNOTIFY=y
+# CONFIG_DNOTIFY is not set
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_FUSE_FS is not set
+
+#
+# Caches
+#
+# CONFIG_FSCACHE is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=m
+# CONFIG_MSDOS_FS is not set
+CONFIG_VFAT_FS=m
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_HUGETLB_PAGE is not set
+# CONFIG_CONFIGFS_FS is not set
+CONFIG_MISC_FILESYSTEMS=y
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_DEBUG=0
+CONFIG_JFFS2_FS_WRITEBUFFER=y
+# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
+# CONFIG_JFFS2_SUMMARY is not set
+# CONFIG_JFFS2_FS_XATTR is not set
+# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
+CONFIG_JFFS2_ZLIB=y
+# CONFIG_JFFS2_LZO is not set
+CONFIG_JFFS2_RTIME=y
+# CONFIG_JFFS2_RUBIN is not set
+# CONFIG_CRAMFS is not set
+# CONFIG_SQUASHFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_OMFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+# CONFIG_NFS_V3_ACL is not set
+# CONFIG_NFS_V4 is not set
+CONFIG_ROOT_NFS=y
+CONFIG_NFSD=m
+CONFIG_NFSD_V3=y
+# CONFIG_NFSD_V3_ACL is not set
+# CONFIG_NFSD_V4 is not set
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+CONFIG_EXPORTFS=m
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=y
+# CONFIG_RPCSEC_GSS_KRB5 is not set
+# CONFIG_RPCSEC_GSS_SPKM3 is not set
+# CONFIG_SMB_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+
+#
+# Partition Types
+#
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_ACORN_PARTITION is not set
+# CONFIG_OSF_PARTITION is not set
+# CONFIG_AMIGA_PARTITION is not set
+# CONFIG_ATARI_PARTITION is not set
+# CONFIG_MAC_PARTITION is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_BSD_DISKLABEL is not set
+# CONFIG_MINIX_SUBPARTITION is not set
+# CONFIG_SOLARIS_X86_PARTITION is not set
+# CONFIG_UNIXWARE_DISKLABEL is not set
+# CONFIG_LDM_PARTITION is not set
+# CONFIG_SGI_PARTITION is not set
+# CONFIG_ULTRIX_PARTITION is not set
+# CONFIG_SUN_PARTITION is not set
+# CONFIG_KARMA_PARTITION is not set
+# CONFIG_EFI_PARTITION is not set
+# CONFIG_SYSV68_PARTITION is not set
+CONFIG_NLS=m
+CONFIG_NLS_DEFAULT="iso8859-1"
+CONFIG_NLS_CODEPAGE_437=m
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+CONFIG_NLS_CODEPAGE_850=m
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+# CONFIG_NLS_ASCII is not set
+CONFIG_NLS_ISO8859_1=m
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+CONFIG_NLS_ISO8859_15=m
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+CONFIG_NLS_UTF8=m
+# CONFIG_DLM is not set
+
+#
+# Kernel hacking
+#
+# CONFIG_PRINTK_TIME is not set
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_FRAME_WARN=1024
+CONFIG_MAGIC_SYSRQ=y
+# CONFIG_STRIP_ASM_SYMS is not set
+# CONFIG_UNUSED_SYMBOLS is not set
+# CONFIG_DEBUG_FS is not set
+# CONFIG_HEADERS_CHECK is not set
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_SHIRQ is not set
+CONFIG_DETECT_SOFTLOCKUP=y
+# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
+CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
+CONFIG_DETECT_HUNG_TASK=y
+# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set
+CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0
+CONFIG_SCHED_DEBUG=y
+# CONFIG_SCHEDSTATS is not set
+# CONFIG_TIMER_STATS is not set
+# CONFIG_DEBUG_OBJECTS is not set
+# CONFIG_SLUB_DEBUG_ON is not set
+# CONFIG_SLUB_STATS is not set
+# CONFIG_DEBUG_KMEMLEAK is not set
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_RT_MUTEX_TESTER is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+CONFIG_DEBUG_MUTEXES=y
+# CONFIG_DEBUG_LOCK_ALLOC is not set
+# CONFIG_PROVE_LOCKING is not set
+# CONFIG_LOCK_STAT is not set
+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+# CONFIG_DEBUG_KOBJECT is not set
+CONFIG_DEBUG_BUGVERBOSE=y
+# CONFIG_DEBUG_INFO is not set
+# CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_WRITECOUNT is not set
+CONFIG_DEBUG_MEMORY_INIT=y
+# CONFIG_DEBUG_LIST is not set
+# CONFIG_DEBUG_SG is not set
+# CONFIG_DEBUG_NOTIFIERS is not set
+# CONFIG_DEBUG_CREDENTIALS is not set
+# CONFIG_BOOT_PRINTK_DELAY is not set
+# CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_BACKTRACE_SELF_TEST is not set
+# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
+# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
+# CONFIG_FAULT_INJECTION is not set
+# CONFIG_LATENCYTOP is not set
+CONFIG_SYSCTL_SYSCALL_CHECK=y
+# CONFIG_PAGE_POISONING is not set
+CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_TRACING_SUPPORT=y
+CONFIG_FTRACE=y
+# CONFIG_FUNCTION_TRACER is not set
+# CONFIG_IRQSOFF_TRACER is not set
+# CONFIG_SCHED_TRACER is not set
+# CONFIG_ENABLE_DEFAULT_TRACERS is not set
+# CONFIG_BOOT_TRACER is not set
+CONFIG_BRANCH_PROFILE_NONE=y
+# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set
+# CONFIG_PROFILE_ALL_BRANCHES is not set
+# CONFIG_STACK_TRACER is not set
+# CONFIG_KMEMTRACE is not set
+# CONFIG_WORKQUEUE_TRACER is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_SAMPLES is not set
+CONFIG_HAVE_ARCH_KGDB=y
+# CONFIG_KGDB is not set
+CONFIG_ARM_UNWIND=y
+# CONFIG_DEBUG_USER is not set
+CONFIG_DEBUG_ERRORS=y
+# CONFIG_DEBUG_STACK_USAGE is not set
+# CONFIG_DEBUG_LL is not set
+# CONFIG_OC_ETM is not set
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITYFS is not set
+# CONFIG_DEFAULT_SECURITY_SELINUX is not set
+# CONFIG_DEFAULT_SECURITY_SMACK is not set
+# CONFIG_DEFAULT_SECURITY_TOMOYO is not set
+CONFIG_DEFAULT_SECURITY_DAC=y
+CONFIG_DEFAULT_SECURITY=""
+CONFIG_CRYPTO=y
+
+#
+# Crypto core or helper
+#
+CONFIG_CRYPTO_ALGAPI=m
+CONFIG_CRYPTO_ALGAPI2=m
+CONFIG_CRYPTO_AEAD2=m
+CONFIG_CRYPTO_BLKCIPHER=m
+CONFIG_CRYPTO_BLKCIPHER2=m
+CONFIG_CRYPTO_HASH=m
+CONFIG_CRYPTO_HASH2=m
+CONFIG_CRYPTO_RNG2=m
+CONFIG_CRYPTO_PCOMP=m
+CONFIG_CRYPTO_MANAGER=m
+CONFIG_CRYPTO_MANAGER2=m
+# CONFIG_CRYPTO_GF128MUL is not set
+# CONFIG_CRYPTO_NULL is not set
+CONFIG_CRYPTO_WORKQUEUE=m
+# CONFIG_CRYPTO_CRYPTD is not set
+# CONFIG_CRYPTO_AUTHENC is not set
+# CONFIG_CRYPTO_TEST is not set
+
+#
+# Authenticated Encryption with Associated Data
+#
+# CONFIG_CRYPTO_CCM is not set
+# CONFIG_CRYPTO_GCM is not set
+# CONFIG_CRYPTO_SEQIV is not set
+
+#
+# Block modes
+#
+# CONFIG_CRYPTO_CBC is not set
+# CONFIG_CRYPTO_CTR is not set
+# CONFIG_CRYPTO_CTS is not set
+CONFIG_CRYPTO_ECB=m
+# CONFIG_CRYPTO_LRW is not set
+# CONFIG_CRYPTO_PCBC is not set
+# CONFIG_CRYPTO_XTS is not set
+
+#
+# Hash modes
+#
+# CONFIG_CRYPTO_HMAC is not set
+# CONFIG_CRYPTO_XCBC is not set
+# CONFIG_CRYPTO_VMAC is not set
+
+#
+# Digest
+#
+# CONFIG_CRYPTO_CRC32C is not set
+# CONFIG_CRYPTO_GHASH is not set
+# CONFIG_CRYPTO_MD4 is not set
+# CONFIG_CRYPTO_MD5 is not set
+CONFIG_CRYPTO_MICHAEL_MIC=m
+# CONFIG_CRYPTO_RMD128 is not set
+# CONFIG_CRYPTO_RMD160 is not set
+# CONFIG_CRYPTO_RMD256 is not set
+# CONFIG_CRYPTO_RMD320 is not set
+# CONFIG_CRYPTO_SHA1 is not set
+# CONFIG_CRYPTO_SHA256 is not set
+# CONFIG_CRYPTO_SHA512 is not set
+# CONFIG_CRYPTO_TGR192 is not set
+# CONFIG_CRYPTO_WP512 is not set
+
+#
+# Ciphers
+#
+CONFIG_CRYPTO_AES=m
+# CONFIG_CRYPTO_ANUBIS is not set
+CONFIG_CRYPTO_ARC4=m
+# CONFIG_CRYPTO_BLOWFISH is not set
+# CONFIG_CRYPTO_CAMELLIA is not set
+# CONFIG_CRYPTO_CAST5 is not set
+# CONFIG_CRYPTO_CAST6 is not set
+# CONFIG_CRYPTO_DES is not set
+# CONFIG_CRYPTO_FCRYPT is not set
+# CONFIG_CRYPTO_KHAZAD is not set
+# CONFIG_CRYPTO_SALSA20 is not set
+# CONFIG_CRYPTO_SEED is not set
+# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_TEA is not set
+# CONFIG_CRYPTO_TWOFISH is not set
+
+#
+# Compression
+#
+# CONFIG_CRYPTO_DEFLATE is not set
+# CONFIG_CRYPTO_ZLIB is not set
+# CONFIG_CRYPTO_LZO is not set
+
+#
+# Random Number Generation
+#
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
+CONFIG_CRYPTO_HW=y
+# CONFIG_BINARY_PRINTF is not set
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+CONFIG_GENERIC_FIND_LAST_BIT=y
+CONFIG_CRC_CCITT=m
+CONFIG_CRC16=m
+CONFIG_CRC_T10DIF=m
+CONFIG_CRC_ITU_T=m
+CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
+# CONFIG_LIBCRC32C is not set
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
+CONFIG_NLATTR=y
diff --git a/arch/arm/include/asm/asm-offsets.h b/arch/arm/include/asm/asm-offsets.h
new file mode 100644
index 000000000000..d370ee36a182
--- /dev/null
+++ b/arch/arm/include/asm/asm-offsets.h
@@ -0,0 +1 @@
+#include <generated/asm-offsets.h>
diff --git a/arch/arm/include/asm/cacheflush.h b/arch/arm/include/asm/cacheflush.h
index 73eceb87e588..730aefcfbee3 100644
--- a/arch/arm/include/asm/cacheflush.h
+++ b/arch/arm/include/asm/cacheflush.h
@@ -211,7 +211,7 @@ struct cpu_cache_fns {
 
         void (*coherent_kern_range)(unsigned long, unsigned long);
         void (*coherent_user_range)(unsigned long, unsigned long);
-        void (*flush_kern_dcache_page)(void *);
+        void (*flush_kern_dcache_area)(void *, size_t);
 
         void (*dma_inv_range)(const void *, const void *);
         void (*dma_clean_range)(const void *, const void *);
@@ -236,7 +236,7 @@ extern struct cpu_cache_fns cpu_cache;
 #define __cpuc_flush_user_range         cpu_cache.flush_user_range
 #define __cpuc_coherent_kern_range      cpu_cache.coherent_kern_range
 #define __cpuc_coherent_user_range      cpu_cache.coherent_user_range
-#define __cpuc_flush_dcache_page        cpu_cache.flush_kern_dcache_page
+#define __cpuc_flush_dcache_area        cpu_cache.flush_kern_dcache_area
 
 /*
  * These are private to the dma-mapping API.  Do not use directly.
@@ -255,14 +255,14 @@ extern struct cpu_cache_fns cpu_cache;
 #define __cpuc_flush_user_range         __glue(_CACHE,_flush_user_cache_range)
 #define __cpuc_coherent_kern_range      __glue(_CACHE,_coherent_kern_range)
 #define __cpuc_coherent_user_range      __glue(_CACHE,_coherent_user_range)
-#define __cpuc_flush_dcache_page        __glue(_CACHE,_flush_kern_dcache_page)
+#define __cpuc_flush_dcache_area        __glue(_CACHE,_flush_kern_dcache_area)
 
 extern void __cpuc_flush_kern_all(void);
 extern void __cpuc_flush_user_all(void);
 extern void __cpuc_flush_user_range(unsigned long, unsigned long, unsigned int);
 extern void __cpuc_coherent_kern_range(unsigned long, unsigned long);
 extern void __cpuc_coherent_user_range(unsigned long, unsigned long);
-extern void __cpuc_flush_dcache_page(void *);
+extern void __cpuc_flush_dcache_area(void *, size_t);
 
 /*
  * These are private to the dma-mapping API.  Do not use directly.
@@ -448,7 +448,7 @@ static inline void flush_kernel_dcache_page(struct page *page)
 {
         /* highmem pages are always flushed upon kunmap already */
         if ((cache_is_vivt() || cache_is_vipt_aliasing()) && !PageHighMem(page))
-                __cpuc_flush_dcache_page(page_address(page));
+                __cpuc_flush_dcache_area(page_address(page), PAGE_SIZE);
 }
 
 #define flush_dcache_mmap_lock(mapping) \
@@ -465,13 +465,6 @@ static inline void flush_kernel_dcache_page(struct page *page)
  */
 #define flush_icache_page(vma,page)     do { } while (0)
 
-static inline void flush_ioremap_region(unsigned long phys, void __iomem *virt,
-        unsigned offset, size_t size)
-{
-        const void *start = (void __force *)virt + offset;
-        dmac_inv_range(start, start + size);
-}
-
 /*
  * flush_cache_vmap() is used when creating mappings (eg, via vmap,
  * vmalloc, ioremap etc) in kernel space for pages.  On non-VIPT
diff --git a/arch/arm/include/asm/elf.h b/arch/arm/include/asm/elf.h
index 6aac3f5bb2f3..a399bb5730f1 100644
--- a/arch/arm/include/asm/elf.h
+++ b/arch/arm/include/asm/elf.h
@@ -101,7 +101,6 @@ extern int arm_elf_read_implies_exec(const struct elf32_hdr *, int);
 int dump_task_regs(struct task_struct *t, elf_gregset_t *elfregs);
 #define ELF_CORE_COPY_TASK_REGS dump_task_regs
 
-#define USE_ELF_CORE_DUMP
 #define ELF_EXEC_PAGESIZE       4096
 
 /* This is the location that an ET_DYN program is loaded if exec'ed.  Typical
diff --git a/arch/arm/include/asm/mach-types.h b/arch/arm/include/asm/mach-types.h
new file mode 100644
index 000000000000..948178cc6ba8
--- /dev/null
+++ b/arch/arm/include/asm/mach-types.h
@@ -0,0 +1 @@
+#include <generated/mach-types.h>
diff --git a/arch/arm/include/asm/mach/irq.h b/arch/arm/include/asm/mach/irq.h
index acac5302e4ea..8920b2d6e3b8 100644
--- a/arch/arm/include/asm/mach/irq.h
+++ b/arch/arm/include/asm/mach/irq.h
@@ -26,9 +26,9 @@ extern int show_fiq_list(struct seq_file *, void *);
  */
 #define do_bad_IRQ(irq,desc)                            \
 do {                                                    \
-        spin_lock(&desc->lock);                         \
+        raw_spin_lock(&desc->lock);                     \
         handle_bad_irq(irq, desc);                      \
-        spin_unlock(&desc->lock);                       \
+        raw_spin_unlock(&desc->lock);                   \
 } while(0)
 
 #endif
diff --git a/arch/arm/include/asm/mman.h b/arch/arm/include/asm/mman.h
index 8eebf89f5ab1..41f99c573b93 100644
--- a/arch/arm/include/asm/mman.h
+++ b/arch/arm/include/asm/mman.h
@@ -1 +1,4 @@
 #include <asm-generic/mman.h>
+
+#define arch_mmap_check(addr, len, flags) \
+        (((flags) & MAP_FIXED && (addr) < FIRST_USER_ADDRESS) ? -EINVAL : 0)
diff --git a/arch/arm/include/asm/spinlock.h b/arch/arm/include/asm/spinlock.h
index c13681ac1ede..c91c64cab922 100644
--- a/arch/arm/include/asm/spinlock.h
+++ b/arch/arm/include/asm/spinlock.h
@@ -17,13 +17,13 @@
  * Locked value: 1
  */
 
-#define __raw_spin_is_locked(x)         ((x)->lock != 0)
-#define __raw_spin_unlock_wait(lock) \
-        do { while (__raw_spin_is_locked(lock)) cpu_relax(); } while (0)
+#define arch_spin_is_locked(x)          ((x)->lock != 0)
+#define arch_spin_unlock_wait(lock) \
+        do { while (arch_spin_is_locked(lock)) cpu_relax(); } while (0)
 
-#define __raw_spin_lock_flags(lock, flags) __raw_spin_lock(lock)
+#define arch_spin_lock_flags(lock, flags) arch_spin_lock(lock)
 
-static inline void __raw_spin_lock(raw_spinlock_t *lock)
+static inline void arch_spin_lock(arch_spinlock_t *lock)
 {
         unsigned long tmp;
 
@@ -43,7 +43,7 @@ static inline void __raw_spin_lock(raw_spinlock_t *lock)
         smp_mb();
 }
 
-static inline int __raw_spin_trylock(raw_spinlock_t *lock)
+static inline int arch_spin_trylock(arch_spinlock_t *lock)
 {
         unsigned long tmp;
 
@@ -63,7 +63,7 @@ static inline int __raw_spin_trylock(raw_spinlock_t *lock)
         }
 }
 
-static inline void __raw_spin_unlock(raw_spinlock_t *lock)
+static inline void arch_spin_unlock(arch_spinlock_t *lock)
 {
         smp_mb();
 
@@ -86,7 +86,7 @@ static inline void __raw_spin_unlock(raw_spinlock_t *lock)
  * just write zero since the lock is exclusively held.
  */
 
-static inline void __raw_write_lock(raw_rwlock_t *rw)
+static inline void arch_write_lock(arch_rwlock_t *rw)
 {
         unsigned long tmp;
 
@@ -106,7 +106,7 @@ static inline void __raw_write_lock(raw_rwlock_t *rw)
         smp_mb();
 }
 
-static inline int __raw_write_trylock(raw_rwlock_t *rw)
+static inline int arch_write_trylock(arch_rwlock_t *rw)
 {
         unsigned long tmp;
 
@@ -126,7 +126,7 @@ static inline int __raw_write_trylock(raw_rwlock_t *rw)
         }
 }
 
-static inline void __raw_write_unlock(raw_rwlock_t *rw)
+static inline void arch_write_unlock(arch_rwlock_t *rw)
 {
         smp_mb();
 
@@ -142,7 +142,7 @@ static inline void __raw_write_unlock(raw_rwlock_t *rw)
 }
 
 /* write_can_lock - would write_trylock() succeed? */
-#define __raw_write_can_lock(x)         ((x)->lock == 0)
+#define arch_write_can_lock(x)          ((x)->lock == 0)
 
 /*
  * Read locks are a bit more hairy:
@@ -156,7 +156,7 @@ static inline void __raw_write_unlock(raw_rwlock_t *rw)
  * currently active.  However, we know we won't have any write
  * locks.
  */
-static inline void __raw_read_lock(raw_rwlock_t *rw)
+static inline void arch_read_lock(arch_rwlock_t *rw)
 {
         unsigned long tmp, tmp2;
 
@@ -176,7 +176,7 @@ static inline void __raw_read_lock(raw_rwlock_t *rw)
         smp_mb();
 }
 
-static inline void __raw_read_unlock(raw_rwlock_t *rw)
+static inline void arch_read_unlock(arch_rwlock_t *rw)
 {
         unsigned long tmp, tmp2;
 
@@ -198,7 +198,7 @@ static inline void __raw_read_unlock(raw_rwlock_t *rw)
         : "cc");
 }
 
-static inline int __raw_read_trylock(raw_rwlock_t *rw)
+static inline int arch_read_trylock(arch_rwlock_t *rw)
 {
         unsigned long tmp, tmp2 = 1;
 
@@ -215,13 +215,13 @@ static inline int __raw_read_trylock(raw_rwlock_t *rw)
 }
 
 /* read_can_lock - would read_trylock() succeed? */
-#define __raw_read_can_lock(x)          ((x)->lock < 0x80000000)
+#define arch_read_can_lock(x)           ((x)->lock < 0x80000000)
 
-#define __raw_read_lock_flags(lock, flags) __raw_read_lock(lock)
-#define __raw_write_lock_flags(lock, flags) __raw_write_lock(lock)
+#define arch_read_lock_flags(lock, flags) arch_read_lock(lock)
+#define arch_write_lock_flags(lock, flags) arch_write_lock(lock)
 
-#define _raw_spin_relax(lock)   cpu_relax()
-#define _raw_read_relax(lock)   cpu_relax()
-#define _raw_write_relax(lock)  cpu_relax()
+#define arch_spin_relax(lock)   cpu_relax()
+#define arch_read_relax(lock)   cpu_relax()
+#define arch_write_relax(lock)  cpu_relax()
 
 #endif /* __ASM_SPINLOCK_H */
diff --git a/arch/arm/include/asm/spinlock_types.h b/arch/arm/include/asm/spinlock_types.h
index 43e83f6d2ee5..d14d197ae04a 100644
--- a/arch/arm/include/asm/spinlock_types.h
+++ b/arch/arm/include/asm/spinlock_types.h
@@ -7,14 +7,14 @@
 
 typedef struct {
         volatile unsigned int lock;
-} raw_spinlock_t;
+} arch_spinlock_t;
 
-#define __RAW_SPIN_LOCK_UNLOCKED        { 0 }
+#define __ARCH_SPIN_LOCK_UNLOCKED       { 0 }
 
 typedef struct {
         volatile unsigned int lock;
-} raw_rwlock_t;
+} arch_rwlock_t;
 
-#define __RAW_RW_LOCK_UNLOCKED          { 0 }
+#define __ARCH_RW_LOCK_UNLOCKED         { 0 }
 
 #endif
diff --git a/arch/arm/kernel/Makefile b/arch/arm/kernel/Makefile
index e7ccf7e697ce..dd00f747e2ad 100644
--- a/arch/arm/kernel/Makefile
+++ b/arch/arm/kernel/Makefile
@@ -54,5 +54,6 @@ endif
 
 head-y                  := head$(MMUEXT).o
 obj-$(CONFIG_DEBUG_LL)  += debug.o
+obj-$(CONFIG_EARLY_PRINTK)      += early_printk.o
 
 extra-y := $(head-y) init_task.o vmlinux.lds
diff --git a/arch/arm/kernel/armksyms.c b/arch/arm/kernel/armksyms.c
index 0e627705f746..8214bfebfaca 100644
--- a/arch/arm/kernel/armksyms.c
+++ b/arch/arm/kernel/armksyms.c
@@ -48,27 +48,7 @@ extern void __aeabi_uidivmod(void);
 extern void __aeabi_ulcmp(void);
 
 extern void fpundefinstr(void);
-extern void fp_enter(void);
 
-/*
- * This has a special calling convention; it doesn't
- * modify any of the usual registers, except for LR.
- */
-#define EXPORT_CRC_ALIAS(sym) __CRC_SYMBOL(sym, "")
-
-#define EXPORT_SYMBOL_ALIAS(sym,orig)           \
- EXPORT_CRC_ALIAS(sym)                          \
- static const struct kernel_symbol __ksymtab_##sym      \
-  __used __attribute__((section("__ksymtab"))) =        \
-    { (unsigned long)&orig, #sym };
-
-/*
- * floating point math emulator support.
- * These symbols will never change their calling convention...
- */
-EXPORT_SYMBOL_ALIAS(kern_fp_enter,fp_enter);
-EXPORT_SYMBOL_ALIAS(fp_printk,printk);
-EXPORT_SYMBOL_ALIAS(fp_send_sig,send_sig);
 
 EXPORT_SYMBOL(__backtrace);
 
diff --git a/arch/arm/kernel/calls.S b/arch/arm/kernel/calls.S
index f58c1156e779..9314a2d681f1 100644
--- a/arch/arm/kernel/calls.S
+++ b/arch/arm/kernel/calls.S
@@ -172,7 +172,7 @@
 /* 160 */       CALL(sys_sched_get_priority_min)
                 CALL(sys_sched_rr_get_interval)
                 CALL(sys_nanosleep)
-                CALL(sys_arm_mremap)
+                CALL(sys_mremap)
                 CALL(sys_setresuid16)
 /* 165 */       CALL(sys_getresuid16)
                 CALL(sys_ni_syscall)            /* vm86 */
diff --git a/arch/arm/kernel/early_printk.c b/arch/arm/kernel/early_printk.c
new file mode 100644
index 000000000000..85aa2b292692
--- /dev/null
+++ b/arch/arm/kernel/early_printk.c
@@ -0,0 +1,57 @@
+/*
+ *  linux/arch/arm/kernel/early_printk.c
+ *
+ *  Copyright (C) 2009 Sascha Hauer <s.hauer@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/console.h>
+#include <linux/init.h>
+
+extern void printch(int);
+
+static void early_write(const char *s, unsigned n)
+{
+        while (n-- > 0) {
+                if (*s == '\n')
+                        printch('\r');
+                printch(*s);
+                s++;
+        }
+}
+
+static void early_console_write(struct console *con, const char *s, unsigned n)
+{
+        early_write(s, n);
+}
+
+static struct console early_console = {
+        .name =         "earlycon",
+        .write =        early_console_write,
+        .flags =        CON_PRINTBUFFER | CON_BOOT,
+        .index =        -1,
+};
+
+asmlinkage void early_printk(const char *fmt, ...)
+{
+        char buf[512];
+        int n;
+        va_list ap;
+
+        va_start(ap, fmt);
+        n = vscnprintf(buf, sizeof(buf), fmt, ap);
+        early_write(buf, n);
+        va_end(ap);
+}
+
+static int __init setup_early_printk(char *buf)
+{
+        register_console(&early_console);
+        return 0;
+}
+
+early_param("earlyprintk", setup_early_printk);
diff --git a/arch/arm/kernel/entry-common.S b/arch/arm/kernel/entry-common.S
index f0fe95b7085d..2c1db77d7848 100644
--- a/arch/arm/kernel/entry-common.S
+++ b/arch/arm/kernel/entry-common.S
@@ -416,12 +416,12 @@ sys_mmap2:
                 tst     r5, #PGOFF_MASK
                 moveq   r5, r5, lsr #PAGE_SHIFT - 12
                 streq   r5, [sp, #4]
-                beq     do_mmap2
+                beq     sys_mmap_pgoff
                 mov     r0, #-EINVAL
                 mov     pc, lr
 #else
                 str     r5, [sp, #4]
-                b       do_mmap2
+                b       sys_mmap_pgoff
 #endif
 ENDPROC(sys_mmap2)
 
diff --git a/arch/arm/kernel/irq.c b/arch/arm/kernel/irq.c
index c9a8619f3856..b7cb45bb91e8 100644
--- a/arch/arm/kernel/irq.c
+++ b/arch/arm/kernel/irq.c
@@ -69,7 +69,7 @@ int show_interrupts(struct seq_file *p, void *v)
         }
 
         if (i < NR_IRQS) {
-                spin_lock_irqsave(&irq_desc[i].lock, flags);
+                raw_spin_lock_irqsave(&irq_desc[i].lock, flags);
                 action = irq_desc[i].action;
                 if (!action)
                         goto unlock;
@@ -84,7 +84,7 @@ int show_interrupts(struct seq_file *p, void *v)
 
                 seq_putc(p, '\n');
 unlock:
-                spin_unlock_irqrestore(&irq_desc[i].lock, flags);
+                raw_spin_unlock_irqrestore(&irq_desc[i].lock, flags);
         } else if (i == NR_IRQS) {
 #ifdef CONFIG_FIQ
                 show_fiq_list(p, v);
@@ -139,7 +139,7 @@ void set_irq_flags(unsigned int irq, unsigned int iflags)
         }
 
         desc = irq_desc + irq;
-        spin_lock_irqsave(&desc->lock, flags);
+        raw_spin_lock_irqsave(&desc->lock, flags);
         desc->status |= IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
         if (iflags & IRQF_VALID)
                 desc->status &= ~IRQ_NOREQUEST;
@@ -147,7 +147,7 @@ void set_irq_flags(unsigned int irq, unsigned int iflags)
                 desc->status &= ~IRQ_NOPROBE;
         if (!(iflags & IRQF_NOAUTOEN))
                 desc->status &= ~IRQ_NOAUTOEN;
-        spin_unlock_irqrestore(&desc->lock, flags);
+        raw_spin_unlock_irqrestore(&desc->lock, flags);
 }
 
 void __init init_IRQ(void)
@@ -166,9 +166,9 @@ static void route_irq(struct irq_desc *desc, unsigned int irq, unsigned int cpu)
 {
         pr_debug("IRQ%u: moving from cpu%u to cpu%u\n", irq, desc->node, cpu);
 
-        spin_lock_irq(&desc->lock);
+        raw_spin_lock_irq(&desc->lock);
         desc->chip->set_affinity(irq, cpumask_of(cpu));
-        spin_unlock_irq(&desc->lock);
+        raw_spin_unlock_irq(&desc->lock);
 }
 
 /*
diff --git a/arch/arm/kernel/smp_twd.c b/arch/arm/kernel/smp_twd.c
index a73a34dccf2a..ea02a7b1c244 100644
--- a/arch/arm/kernel/smp_twd.c
+++ b/arch/arm/kernel/smp_twd.c
@@ -160,6 +160,7 @@ void __cpuinit twd_timer_setup(struct clock_event_device *clk)
 
         /* Make sure our local interrupt controller has this enabled */
         local_irq_save(flags);
+        irq_to_desc(clk->irq)->status |= IRQ_NOPROBE;
         get_irq_chip(clk->irq)->unmask(clk->irq);
         local_irq_restore(flags);
 
diff --git a/arch/arm/kernel/sys_arm.c b/arch/arm/kernel/sys_arm.c
index 78ecaac65206..ae4027bd01bd 100644
--- a/arch/arm/kernel/sys_arm.c
+++ b/arch/arm/kernel/sys_arm.c
@@ -28,41 +28,6 @@
 #include <linux/ipc.h>
 #include <linux/uaccess.h>
 
-extern unsigned long do_mremap(unsigned long addr, unsigned long old_len,
-                               unsigned long new_len, unsigned long flags,
-                               unsigned long new_addr);
-
-/* common code for old and new mmaps */
-inline long do_mmap2(
-        unsigned long addr, unsigned long len,
-        unsigned long prot, unsigned long flags,
-        unsigned long fd, unsigned long pgoff)
-{
-        int error = -EINVAL;
-        struct file * file = NULL;
-
-        flags &= ~(MAP_EXECUTABLE | MAP_DENYWRITE);
-
-        if (flags & MAP_FIXED && addr < FIRST_USER_ADDRESS)
-                goto out;
-
-        error = -EBADF;
-        if (!(flags & MAP_ANONYMOUS)) {
-                file = fget(fd);
-                if (!file)
-                        goto out;
-        }
-
-        down_write(&current->mm->mmap_sem);
-        error = do_mmap_pgoff(file, addr, len, prot, flags, pgoff);
-        up_write(&current->mm->mmap_sem);
-
-        if (file)
-                fput(file);
-out:
-        return error;
-}
-
 struct mmap_arg_struct {
         unsigned long addr;
         unsigned long len;
@@ -84,29 +49,11 @@ asmlinkage int old_mmap(struct mmap_arg_struct __user *arg)
         if (a.offset & ~PAGE_MASK)
                 goto out;
 
-        error = do_mmap2(a.addr, a.len, a.prot, a.flags, a.fd, a.offset >> PAGE_SHIFT);
+        error = sys_mmap_pgoff(a.addr, a.len, a.prot, a.flags, a.fd, a.offset >> PAGE_SHIFT);
 out:
         return error;
 }
 
-asmlinkage unsigned long
-sys_arm_mremap(unsigned long addr, unsigned long old_len,
-               unsigned long new_len, unsigned long flags,
-               unsigned long new_addr)
-{
-        unsigned long ret = -EINVAL;
-
-        if (flags & MREMAP_FIXED && new_addr < FIRST_USER_ADDRESS)
-                goto out;
-
-        down_write(&current->mm->mmap_sem);
-        ret = do_mremap(addr, old_len, new_len, flags, new_addr);
-        up_write(&current->mm->mmap_sem);
-
-out:
-        return ret;
-}
-
 /*
  * Perform the select(nd, in, out, ex, tv) and mmap() system
  * calls.
diff --git a/arch/arm/kernel/vmlinux.lds.S b/arch/arm/kernel/vmlinux.lds.S
index 71151bd87a36..4957e13ef55b 100644
--- a/arch/arm/kernel/vmlinux.lds.S
+++ b/arch/arm/kernel/vmlinux.lds.S
@@ -65,11 +65,11 @@ SECTIONS
         __init_end = .;
 #endif
 
-        /DISCARD/ : {                   /* Exit code and data           */
-                EXIT_TEXT
-                EXIT_DATA
-                *(.exitcall.exit)
-                *(.discard)
+        /*
+         * unwind exit sections must be discarded before the rest of the
+         * unwind sections get included.
+         */
+        /DISCARD/ : {
                 *(.ARM.exidx.exit.text)
                 *(.ARM.extab.exit.text)
 #ifndef CONFIG_HOTPLUG_CPU
@@ -238,6 +238,9 @@ SECTIONS
 
         STABS_DEBUG
         .comment 0 : { *(.comment) }
+
+        /* Default discards */
+        DISCARDS
 }
 
 /*
diff --git a/arch/arm/mach-at91/include/mach/atmel-mci.h b/arch/arm/mach-at91/include/mach/atmel-mci.h
new file mode 100644
index 000000000000..998cb0c07135
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/atmel-mci.h
@@ -0,0 +1,24 @@
+#ifndef __MACH_ATMEL_MCI_H
+#define __MACH_ATMEL_MCI_H
+
+#include <mach/at_hdmac.h>
+
+/**
+ * struct mci_dma_data - DMA data for MCI interface
+ */
+struct mci_dma_data {
+        struct at_dma_slave     sdata;
+};
+
+/* accessor macros */
+#define slave_data_ptr(s)       (&(s)->sdata)
+#define find_slave_dev(s)       ((s)->sdata.dma_dev)
+
+#define setup_dma_addr(s, t, r) do {            \
+        if (s) {                                \
+                (s)->sdata.tx_reg = (t);        \
+                (s)->sdata.rx_reg = (r);        \
+        }                                       \
+} while (0)
+
+#endif /* __MACH_ATMEL_MCI_H */
diff --git a/arch/arm/mach-bcmring/arch.c b/arch/arm/mach-bcmring/arch.c
index fbe6fa02c882..53dd2a9eecf9 100644
--- a/arch/arm/mach-bcmring/arch.c
+++ b/arch/arm/mach-bcmring/arch.c
@@ -70,9 +70,19 @@ static struct ctl_table bcmring_sysctl_reboot[] = {
         {}
 };
 
+static struct resource nand_resource[] = {
+        [0] = {
+                .start = MM_ADDR_IO_NAND,
+                .end = MM_ADDR_IO_NAND + 0x1000 - 1,
+                .flags = IORESOURCE_MEM,
+        },
+};
+
 static struct platform_device nand_device = {
         .name = "bcm-nand",
         .id = -1,
+        .resource = nand_resource,
+        .num_resources  = ARRAY_SIZE(nand_resource),
 };
 
 static struct platform_device *devices[] __initdata = {
diff --git a/arch/arm/mach-bcmring/include/mach/reg_nand.h b/arch/arm/mach-bcmring/include/mach/reg_nand.h
new file mode 100644
index 000000000000..387376ffb56b
--- /dev/null
+++ b/arch/arm/mach-bcmring/include/mach/reg_nand.h
@@ -0,0 +1,66 @@
+/*****************************************************************************
+* Copyright 2001 - 2008 Broadcom Corporation.  All rights reserved.
+*
+* Unless you and Broadcom execute a separate written software license
+* agreement governing use of this software, this software is licensed to you
+* under the terms of the GNU General Public License version 2, available at
+* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
+*
+* Notwithstanding the above, under no circumstances may you combine this
+* software in any way with any other Broadcom software provided under a
+* license other than the GPL, without Broadcom's express prior written
+* consent.
+*****************************************************************************/
+
+/*
+*
+*****************************************************************************
+*
+*  REG_NAND.h
+*
+*  PURPOSE:
+*
+*     This file contains definitions for the nand registers:
+*
+*  NOTES:
+*
+*****************************************************************************/
+
+#if !defined(__ASM_ARCH_REG_NAND_H)
+#define __ASM_ARCH_REG_NAND_H
+
+/* ---- Include Files ---------------------------------------------------- */
+#include <csp/reg.h>
+#include <mach/reg_umi.h>
+
+/* ---- Constants and Types ---------------------------------------------- */
+
+#define HW_NAND_BASE       MM_IO_BASE_NAND      /* NAND Flash */
+
+/* DMA accesses by the bootstrap need hard nonvirtual addresses */
+#define REG_NAND_CMD            __REG16(HW_NAND_BASE + 0)
+#define REG_NAND_ADDR           __REG16(HW_NAND_BASE + 4)
+
+#define REG_NAND_PHYS_DATA16   (HW_NAND_BASE + 8)
+#define REG_NAND_PHYS_DATA8    (HW_NAND_BASE + 8)
+#define REG_NAND_DATA16         __REG16(REG_NAND_PHYS_DATA16)
+#define REG_NAND_DATA8          __REG8(REG_NAND_PHYS_DATA8)
+
+/* use appropriate offset to make sure it start at the 1K boundary */
+#define REG_NAND_PHYS_DATA_DMA   (HW_NAND_BASE + 0x400)
+#define REG_NAND_DATA_DMA         __REG32(REG_NAND_PHYS_DATA_DMA)
+
+/* Linux DMA requires physical address of the data register */
+#define REG_NAND_DATA16_PADDR    HW_IO_VIRT_TO_PHYS(REG_NAND_PHYS_DATA16)
+#define REG_NAND_DATA8_PADDR     HW_IO_VIRT_TO_PHYS(REG_NAND_PHYS_DATA8)
+#define REG_NAND_DATA_PADDR      HW_IO_VIRT_TO_PHYS(REG_NAND_PHYS_DATA_DMA)
+
+#define NAND_BUS_16BIT()        (0)
+#define NAND_BUS_8BIT()         (!NAND_BUS_16BIT())
+
+/* Register offsets */
+#define REG_NAND_CMD_OFFSET     (0)
+#define REG_NAND_ADDR_OFFSET    (4)
+#define REG_NAND_DATA8_OFFSET   (8)
+
+#endif
diff --git a/arch/arm/mach-bcmring/include/mach/reg_umi.h b/arch/arm/mach-bcmring/include/mach/reg_umi.h
new file mode 100644
index 000000000000..06a355481ea6
--- /dev/null
+++ b/arch/arm/mach-bcmring/include/mach/reg_umi.h
@@ -0,0 +1,237 @@
+/*****************************************************************************
+* Copyright 2005 - 2008 Broadcom Corporation.  All rights reserved.
+*
+* Unless you and Broadcom execute a separate written software license
+* agreement governing use of this software, this software is licensed to you
+* under the terms of the GNU General Public License version 2, available at
+* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
+*
+* Notwithstanding the above, under no circumstances may you combine this
+* software in any way with any other Broadcom software provided under a
+* license other than the GPL, without Broadcom's express prior written
+* consent.
+*****************************************************************************/
+
+/*
+*
+*****************************************************************************
+*
+*  REG_UMI.h
+*
+*  PURPOSE:
+*
+*     This file contains definitions for the nand registers:
+*
+*  NOTES:
+*
+*****************************************************************************/
+
+#if !defined(__ASM_ARCH_REG_UMI_H)
+#define __ASM_ARCH_REG_UMI_H
+
+/* ---- Include Files ---------------------------------------------------- */
+#include <csp/reg.h>
+#include <mach/csp/mm_io.h>
+
+/* ---- Constants and Types ---------------------------------------------- */
+
+/* Unified Memory Interface Ctrl Register */
+#define HW_UMI_BASE       MM_IO_BASE_UMI
+
+/* Flash bank 0 timing and control register */
+#define REG_UMI_FLASH0_TCR         __REG32(HW_UMI_BASE  + 0x00)
+/* Flash bank 1 timing and control register */
+#define REG_UMI_FLASH1_TCR         __REG32(HW_UMI_BASE  + 0x04)
+/* Flash bank 2 timing and control register */
+#define REG_UMI_FLASH2_TCR         __REG32(HW_UMI_BASE  + 0x08)
+/* MMD interface and control register */
+#define REG_UMI_MMD_ICR            __REG32(HW_UMI_BASE  + 0x0c)
+/* NAND timing and control register */
+#define REG_UMI_NAND_TCR           __REG32(HW_UMI_BASE  + 0x18)
+/* NAND ready/chip select register */
+#define REG_UMI_NAND_RCSR          __REG32(HW_UMI_BASE  + 0x1c)
+/* NAND ECC control & status register */
+#define REG_UMI_NAND_ECC_CSR       __REG32(HW_UMI_BASE  + 0x20)
+/* NAND ECC data register XXB2B1B0 */
+#define REG_UMI_NAND_ECC_DATA      __REG32(HW_UMI_BASE  + 0x24)
+/* BCH ECC Parameter N */
+#define REG_UMI_BCH_N              __REG32(HW_UMI_BASE  + 0x40)
+/* BCH ECC Parameter T */
+#define REG_UMI_BCH_K              __REG32(HW_UMI_BASE  + 0x44)
+/* BCH ECC Parameter K */
+#define REG_UMI_BCH_T              __REG32(HW_UMI_BASE  + 0x48)
+/* BCH ECC Contro Status */
+#define REG_UMI_BCH_CTRL_STATUS    __REG32(HW_UMI_BASE  + 0x4C)
+/* BCH WR ECC 31:0 */
+#define REG_UMI_BCH_WR_ECC_0       __REG32(HW_UMI_BASE  + 0x50)
+/* BCH WR ECC 63:32 */
+#define REG_UMI_BCH_WR_ECC_1       __REG32(HW_UMI_BASE  + 0x54)
+/* BCH WR ECC 95:64 */
+#define REG_UMI_BCH_WR_ECC_2       __REG32(HW_UMI_BASE  + 0x58)
+/* BCH WR ECC 127:96 */
+#define REG_UMI_BCH_WR_ECC_3       __REG32(HW_UMI_BASE  + 0x5c)
+/* BCH WR ECC 155:128 */
+#define REG_UMI_BCH_WR_ECC_4       __REG32(HW_UMI_BASE  + 0x60)
+/* BCH Read Error Location 1,0 */
+#define REG_UMI_BCH_RD_ERR_LOC_1_0 __REG32(HW_UMI_BASE  + 0x64)
+/* BCH Read Error Location 3,2 */
+#define REG_UMI_BCH_RD_ERR_LOC_3_2 __REG32(HW_UMI_BASE  + 0x68)
+/* BCH Read Error Location 5,4 */
+#define REG_UMI_BCH_RD_ERR_LOC_5_4 __REG32(HW_UMI_BASE  + 0x6c)
+/* BCH Read Error Location 7,6 */
+#define REG_UMI_BCH_RD_ERR_LOC_7_6 __REG32(HW_UMI_BASE  + 0x70)
+/* BCH Read Error Location 9,8 */
+#define REG_UMI_BCH_RD_ERR_LOC_9_8 __REG32(HW_UMI_BASE  + 0x74)
+/* BCH Read Error Location 11,10 */
+#define REG_UMI_BCH_RD_ERR_LOC_B_A __REG32(HW_UMI_BASE  + 0x78)
+
+/* REG_UMI_FLASH0/1/2_TCR, REG_UMI_SRAM0/1_TCR bits */
+/* Enable wait pin during burst write or read */
+#define REG_UMI_TCR_WAITEN              0x80000000
+/* Enable mem ctrlr to work iwth ext mem of lower freq than AHB clk */
+#define REG_UMI_TCR_LOWFREQ             0x40000000
+/* 1=synch write, 0=async write */
+#define REG_UMI_TCR_MEMTYPE_SYNCWRITE   0x20000000
+/* 1=synch read, 0=async read */
+#define REG_UMI_TCR_MEMTYPE_SYNCREAD    0x10000000
+/* 1=page mode read, 0=normal mode read */
+#define REG_UMI_TCR_MEMTYPE_PAGEREAD    0x08000000
+/* page size/burst size (wrap only) */
+#define REG_UMI_TCR_MEMTYPE_PGSZ_MASK   0x07000000
+/* 4 word */
+#define REG_UMI_TCR_MEMTYPE_PGSZ_4      0x00000000
+/* 8 word */
+#define REG_UMI_TCR_MEMTYPE_PGSZ_8      0x01000000
+/* 16 word */
+#define REG_UMI_TCR_MEMTYPE_PGSZ_16     0x02000000
+/* 32 word */
+#define REG_UMI_TCR_MEMTYPE_PGSZ_32     0x03000000
+/* 64 word */
+#define REG_UMI_TCR_MEMTYPE_PGSZ_64     0x04000000
+/* 128 word */
+#define REG_UMI_TCR_MEMTYPE_PGSZ_128    0x05000000
+/* 256 word */
+#define REG_UMI_TCR_MEMTYPE_PGSZ_256    0x06000000
+/* 512 word */
+#define REG_UMI_TCR_MEMTYPE_PGSZ_512    0x07000000
+/* Page read access cycle / Burst write latency (n+2 / n+1) */
+#define REG_UMI_TCR_TPRC_TWLC_MASK      0x00f80000
+/* Bus turnaround cycle (n) */
+#define REG_UMI_TCR_TBTA_MASK           0x00070000
+/* Write pulse width cycle (n+1) */
+#define REG_UMI_TCR_TWP_MASK            0x0000f800
+/* Write recovery cycle (n+1) */
+#define REG_UMI_TCR_TWR_MASK            0x00000600
+/* Write address setup cycle (n+1) */
+#define REG_UMI_TCR_TAS_MASK            0x00000180
+/* Output enable delay cycle (n) */
+#define REG_UMI_TCR_TOE_MASK            0x00000060
+/* Read access cycle / Burst read latency (n+2 / n+1) */
+#define REG_UMI_TCR_TRC_TLC_MASK        0x0000001f
+
+/* REG_UMI_MMD_ICR bits */
+/* Flash write protection pin control */
+#define REG_UMI_MMD_ICR_FLASH_WP            0x8000
+/* Extend hold time for sram0, sram1 csn (39 MHz operation) */
+#define REG_UMI_MMD_ICR_XHCS                0x4000
+/* Enable SDRAM 2 interface control */
+#define REG_UMI_MMD_ICR_SDRAM2EN            0x2000
+/* Enable merge of flash banks 0/1 to 512 MBit bank */
+#define REG_UMI_MMD_ICR_INST512             0x1000
+/* Enable merge of flash banks 1/2 to 512 MBit bank */
+#define REG_UMI_MMD_ICR_DATA512             0x0800
+/* Enable SDRAM interface control */
+#define REG_UMI_MMD_ICR_SDRAMEN             0x0400
+/* Polarity of busy state of Burst Wait Signal */
+#define REG_UMI_MMD_ICR_WAITPOL             0x0200
+/* Enable burst clock stopped when not accessing external burst flash/sram */
+#define REG_UMI_MMD_ICR_BCLKSTOP            0x0100
+/* Enable the peri1_csn to replace flash1_csn in 512 Mb flash mode */
+#define REG_UMI_MMD_ICR_PERI1EN             0x0080
+/* Enable the peri2_csn to replace sdram_csn */
+#define REG_UMI_MMD_ICR_PERI2EN             0x0040
+/* Enable the peri3_csn to replace sdram2_csn */
+#define REG_UMI_MMD_ICR_PERI3EN             0x0020
+/* Enable sram bank1 for H/W controlled MRS */
+#define REG_UMI_MMD_ICR_MRSB1               0x0010
+/* Enable sram bank0 for H/W controlled MRS */
+#define REG_UMI_MMD_ICR_MRSB0               0x0008
+/* Polarity for assert3ed state of H/W controlled MRS */
+#define REG_UMI_MMD_ICR_MRSPOL              0x0004
+/* 0: S/W controllable ZZ/MRS/CRE/P-Mode pin */
+/* 1: H/W controlled ZZ/MRS/CRE/P-Mode, same timing as CS */
+#define REG_UMI_MMD_ICR_MRSMODE             0x0002
+/* MRS state for S/W controlled mode */
+#define REG_UMI_MMD_ICR_MRSSTATE            0x0001
+
+/* REG_UMI_NAND_TCR bits */
+/* Enable software to control CS */
+#define REG_UMI_NAND_TCR_CS_SWCTRL          0x80000000
+/* 16-bit nand wordsize if set */
+#define REG_UMI_NAND_TCR_WORD16             0x40000000
+/* Bus turnaround cycle (n) */
+#define REG_UMI_NAND_TCR_TBTA_MASK          0x00070000
+/* Write pulse width cycle (n+1) */
+#define REG_UMI_NAND_TCR_TWP_MASK           0x0000f800
+/* Write recovery cycle (n+1) */
+#define REG_UMI_NAND_TCR_TWR_MASK           0x00000600
+/* Write address setup cycle (n+1) */
+#define REG_UMI_NAND_TCR_TAS_MASK           0x00000180
+/* Output enable delay cycle (n) */
+#define REG_UMI_NAND_TCR_TOE_MASK           0x00000060
+/* Read access cycle (n+2) */
+#define REG_UMI_NAND_TCR_TRC_TLC_MASK       0x0000001f
+
+/* REG_UMI_NAND_RCSR bits */
+/* Status: Ready=1, Busy=0 */
+#define REG_UMI_NAND_RCSR_RDY               0x02
+/* Keep CS asserted during operation */
+#define REG_UMI_NAND_RCSR_CS_ASSERTED       0x01
+
+/* REG_UMI_NAND_ECC_CSR bits */
+/* Interrupt status - read-only */
+#define REG_UMI_NAND_ECC_CSR_NANDINT        0x80000000
+/* Read: Status of ECC done, Write: clear ECC interrupt */
+#define REG_UMI_NAND_ECC_CSR_ECCINT_RAW     0x00800000
+/* Read: Status of R/B, Write: clear R/B interrupt */
+#define REG_UMI_NAND_ECC_CSR_RBINT_RAW      0x00400000
+/* 1 = Enable ECC Interrupt */
+#define REG_UMI_NAND_ECC_CSR_ECCINT_ENABLE  0x00008000
+/* 1 = Assert interrupt at rising edge of R/B_ */
+#define REG_UMI_NAND_ECC_CSR_RBINT_ENABLE   0x00004000
+/* Calculate ECC by 0=512 bytes, 1=256 bytes */
+#define REG_UMI_NAND_ECC_CSR_256BYTE        0x00000080
+/* Enable ECC in hardware */
+#define REG_UMI_NAND_ECC_CSR_ECC_ENABLE     0x00000001
+
+/* REG_UMI_BCH_CTRL_STATUS bits */
+/* Shift to Indicate Number of correctable errors detected */
+#define REG_UMI_BCH_CTRL_STATUS_NB_CORR_ERROR_SHIFT 20
+/* Indicate Number of correctable errors detected */
+#define REG_UMI_BCH_CTRL_STATUS_NB_CORR_ERROR 0x00F00000
+/* Indicate Errors detected during read but uncorrectable */
+#define REG_UMI_BCH_CTRL_STATUS_UNCORR_ERR    0x00080000
+/* Indicate Errors detected during read and are correctable */
+#define REG_UMI_BCH_CTRL_STATUS_CORR_ERR      0x00040000
+/* Flag indicates BCH's ECC status of read process are valid */
+#define REG_UMI_BCH_CTRL_STATUS_RD_ECC_VALID  0x00020000
+/* Flag indicates BCH's ECC status of write process are valid */
+#define REG_UMI_BCH_CTRL_STATUS_WR_ECC_VALID  0x00010000
+/* Pause ECC calculation */
+#define REG_UMI_BCH_CTRL_STATUS_PAUSE_ECC_DEC 0x00000010
+/* Enable Interrupt */
+#define REG_UMI_BCH_CTRL_STATUS_INT_EN        0x00000004
+/* Enable ECC during read */
+#define REG_UMI_BCH_CTRL_STATUS_ECC_RD_EN     0x00000002
+/* Enable ECC during write */
+#define REG_UMI_BCH_CTRL_STATUS_ECC_WR_EN     0x00000001
+/* Mask for location */
+#define REG_UMI_BCH_ERR_LOC_MASK              0x00001FFF
+/* location within a byte */
+#define REG_UMI_BCH_ERR_LOC_BYTE              0x00000007
+/* location within a word */
+#define REG_UMI_BCH_ERR_LOC_WORD              0x00000018
+/* location within a page (512 byte) */
+#define REG_UMI_BCH_ERR_LOC_PAGE              0x00001FE0
+#define REG_UMI_BCH_ERR_LOC_ADDR(index)     (__REG32(HW_UMI_BASE + 0x64 + (index / 2)*4) >> ((index % 2) * 16))
+#endif
diff --git a/arch/arm/mach-clps711x/include/mach/memory.h b/arch/arm/mach-clps711x/include/mach/memory.h
index e522b20bcbc2..f70d52be48a2 100644
--- a/arch/arm/mach-clps711x/include/mach/memory.h
+++ b/arch/arm/mach-clps711x/include/mach/memory.h
@@ -30,6 +30,8 @@
 
 #define __virt_to_bus(x)        ((x) - PAGE_OFFSET)
 #define __bus_to_virt(x)        ((x) + PAGE_OFFSET)
+#define __pfn_to_bus(x)         (__pfn_to_phys(x) - PHYS_OFFSET)
+#define __bus_to_pfn(x)         __phys_to_pfn((x) + PHYS_OFFSET)
 
 #endif
 
diff --git a/arch/arm/mach-davinci/board-da850-evm.c b/arch/arm/mach-davinci/board-da850-evm.c
index 62b98bffc158..07de8db14581 100644
--- a/arch/arm/mach-davinci/board-da850-evm.c
+++ b/arch/arm/mach-davinci/board-da850-evm.c
@@ -339,6 +339,15 @@ static struct davinci_mmc_config da850_mmc_config = {
         .version        = MMC_CTLR_VERSION_2,
 };
 
+static void da850_panel_power_ctrl(int val)
+{
+        /* lcd backlight */
+        gpio_set_value(DA850_LCD_BL_PIN, val);
+
+        /* lcd power */
+        gpio_set_value(DA850_LCD_PWR_PIN, val);
+}
+
 static int da850_lcd_hw_init(void)
 {
         int status;
@@ -356,17 +365,11 @@ static int da850_lcd_hw_init(void)
         gpio_direction_output(DA850_LCD_BL_PIN, 0);
         gpio_direction_output(DA850_LCD_PWR_PIN, 0);
 
-        /* disable lcd backlight */
-        gpio_set_value(DA850_LCD_BL_PIN, 0);
-
-        /* disable lcd power */
-        gpio_set_value(DA850_LCD_PWR_PIN, 0);
-
-        /* enable lcd power */
-        gpio_set_value(DA850_LCD_PWR_PIN, 1);
+        /* Switch off panel power and backlight */
+        da850_panel_power_ctrl(0);
 
-        /* enable lcd backlight */
-        gpio_set_value(DA850_LCD_BL_PIN, 1);
+        /* Switch on panel power and backlight */
+        da850_panel_power_ctrl(1);
 
         return 0;
 }
@@ -674,6 +677,7 @@ static __init void da850_evm_init(void)
                 pr_warning("da850_evm_init: lcd initialization failed: %d\n",
                                 ret);
 
+        sharp_lk043t1dg01_pdata.panel_power_ctrl = da850_panel_power_ctrl,
         ret = da8xx_register_lcdc(&sharp_lk043t1dg01_pdata);
         if (ret)
                 pr_warning("da850_evm_init: lcdc registration failed: %d\n",
diff --git a/arch/arm/mach-davinci/include/mach/nand.h b/arch/arm/mach-davinci/include/mach/nand.h
index b520c4b5678a..b2ad8090bd10 100644
--- a/arch/arm/mach-davinci/include/mach/nand.h
+++ b/arch/arm/mach-davinci/include/mach/nand.h
@@ -79,6 +79,10 @@ struct davinci_nand_pdata {		/* platform_data */
 
         /* e.g. NAND_BUSWIDTH_16 or NAND_USE_FLASH_BBT */
         unsigned                options;
+
+        /* Main and mirror bbt descriptor overrides */
+        struct nand_bbt_descr   *bbt_td;
+        struct nand_bbt_descr   *bbt_md;
 };
 
 #endif  /* __ARCH_ARM_DAVINCI_NAND_H */
diff --git a/arch/arm/mach-ep93xx/include/mach/ep93xx_keypad.h b/arch/arm/mach-ep93xx/include/mach/ep93xx_keypad.h
index 83f31cd0a274..62d17421e48c 100644
--- a/arch/arm/mach-ep93xx/include/mach/ep93xx_keypad.h
+++ b/arch/arm/mach-ep93xx/include/mach/ep93xx_keypad.h
@@ -5,9 +5,6 @@
 #ifndef __ASM_ARCH_EP93XX_KEYPAD_H
 #define __ASM_ARCH_EP93XX_KEYPAD_H
 
-#define MAX_MATRIX_KEY_ROWS             (8)
-#define MAX_MATRIX_KEY_COLS             (8)
-
 /* flags for the ep93xx_keypad driver */
 #define EP93XX_KEYPAD_DISABLE_3_KEY     (1<<0)  /* disable 3-key reset */
 #define EP93XX_KEYPAD_DIAG_MODE         (1<<1)  /* diagnostic mode */
@@ -18,8 +15,6 @@
 
 /**
  * struct ep93xx_keypad_platform_data - platform specific device structure
- * @matrix_key_rows:            number of rows in the keypad matrix
- * @matrix_key_cols:            number of columns in the keypad matrix
  * @matrix_key_map:             array of keycodes defining the keypad matrix
  * @matrix_key_map_size:        ARRAY_SIZE(matrix_key_map)
  * @debounce:                   debounce start count; terminal count is 0xff
@@ -27,8 +22,6 @@
  * @flags:                      see above
  */
 struct ep93xx_keypad_platform_data {
-        unsigned int    matrix_key_rows;
-        unsigned int    matrix_key_cols;
         unsigned int    *matrix_key_map;
         int             matrix_key_map_size;
         unsigned int    debounce;
@@ -36,7 +29,7 @@ struct ep93xx_keypad_platform_data {
         unsigned int    flags;
 };
 
-/* macro for creating the matrix_key_map table */
-#define KEY(row, col, val)      (((row) << 28) | ((col) << 24) | (val))
+#define EP93XX_MATRIX_ROWS              (8)
+#define EP93XX_MATRIX_COLS              (8)
 
 #endif  /* __ASM_ARCH_EP93XX_KEYPAD_H */
diff --git a/arch/arm/mach-footbridge/common.c b/arch/arm/mach-footbridge/common.c
index b97f529e58e8..41febc796b1c 100644
--- a/arch/arm/mach-footbridge/common.c
+++ b/arch/arm/mach-footbridge/common.c
@@ -201,6 +201,11 @@ void __init footbridge_map_io(void)
 
 #ifdef CONFIG_FOOTBRIDGE_ADDIN
 
+static inline unsigned long fb_bus_sdram_offset(void)
+{
+        return *CSR_PCISDRAMBASE & 0xfffffff0;
+}
+
 /*
  * These two functions convert virtual addresses to PCI addresses and PCI
  * addresses to virtual addresses.  Note that it is only legal to use these
@@ -210,14 +215,13 @@ unsigned long __virt_to_bus(unsigned long res)
 {
         WARN_ON(res < PAGE_OFFSET || res >= (unsigned long)high_memory);
 
-        return (res - PAGE_OFFSET) + (*CSR_PCISDRAMBASE & 0xfffffff0);
+        return res + (fb_bus_sdram_offset() - PAGE_OFFSET);
 }
 EXPORT_SYMBOL(__virt_to_bus);
 
 unsigned long __bus_to_virt(unsigned long res)
 {
-        res -= (*CSR_PCISDRAMBASE & 0xfffffff0);
-        res += PAGE_OFFSET;
+        res = res - (fb_bus_sdram_offset() - PAGE_OFFSET);
 
         WARN_ON(res < PAGE_OFFSET || res >= (unsigned long)high_memory);
 
@@ -225,4 +229,16 @@ unsigned long __bus_to_virt(unsigned long res)
 }
 EXPORT_SYMBOL(__bus_to_virt);
 
+unsigned long __pfn_to_bus(unsigned long pfn)
+{
+        return __pfn_to_phys(pfn) + (fb_bus_sdram_offset() - PHYS_OFFSET));
+}
+EXPORT_SYMBOL(__pfn_to_bus);
+
+unsigned long __bus_to_pfn(unsigned long bus)
+{
+        return __phys_to_pfn(bus - (fb_bus_sdram_offset() - PHYS_OFFSET));
+}
+EXPORT_SYMBOL(__bus_to_pfn);
+
 #endif
diff --git a/arch/arm/mach-footbridge/include/mach/memory.h b/arch/arm/mach-footbridge/include/mach/memory.h
index cb16e59d87b6..8d64f4574087 100644
--- a/arch/arm/mach-footbridge/include/mach/memory.h
+++ b/arch/arm/mach-footbridge/include/mach/memory.h
@@ -29,6 +29,8 @@
 #ifndef __ASSEMBLY__
 extern unsigned long __virt_to_bus(unsigned long);
 extern unsigned long __bus_to_virt(unsigned long);
+extern unsigned long __pfn_to_bus(unsigned long);
+extern unsigned long __bus_to_pfn(unsigned long);
 #endif
 #define __virt_to_bus   __virt_to_bus
 #define __bus_to_virt   __bus_to_virt
@@ -36,14 +38,15 @@ extern unsigned long __bus_to_virt(unsigned long);
 #elif defined(CONFIG_FOOTBRIDGE_HOST)
 
 /*
- * The footbridge is programmed to expose the system RAM at the corresponding
- * address.  So, if PAGE_OFFSET is 0xc0000000, RAM appears at 0xe0000000.
- * If 0x80000000, then its exposed at 0xa0000000 on the bus. etc.
- * The only requirement is that the RAM isn't placed at bus address 0 which
+ * The footbridge is programmed to expose the system RAM at 0xe0000000.
+ * The requirement is that the RAM isn't placed at bus address 0, which
  * would clash with VGA cards.
  */
-#define __virt_to_bus(x)        ((x) - 0xe0000000)
-#define __bus_to_virt(x)        ((x) + 0xe0000000)
+#define BUS_OFFSET              0xe0000000
+#define __virt_to_bus(x)        ((x) + (BUS_OFFSET - PAGE_OFFSET))
+#define __bus_to_virt(x)        ((x) - (BUS_OFFSET - PAGE_OFFSET))
+#define __pfn_to_bus(x)         (__pfn_to_phys(x) + (BUS_OFFSET - PHYS_OFFSET))
+#define __bus_to_pfn(x)         __phys_to_pfn((x) - (BUS_OFFSET - PHYS_OFFSET))
 
 #else
 
diff --git a/arch/arm/mach-integrator/include/mach/memory.h b/arch/arm/mach-integrator/include/mach/memory.h
index 4891828454f5..991f24d2c115 100644
--- a/arch/arm/mach-integrator/include/mach/memory.h
+++ b/arch/arm/mach-integrator/include/mach/memory.h
@@ -28,6 +28,7 @@
 #define BUS_OFFSET      UL(0x80000000)
 #define __virt_to_bus(x)        ((x) - PAGE_OFFSET + BUS_OFFSET)
 #define __bus_to_virt(x)        ((x) - BUS_OFFSET + PAGE_OFFSET)
-#define __pfn_to_bus(x)         (((x) << PAGE_SHIFT) + BUS_OFFSET)
+#define __pfn_to_bus(x)         (__pfn_to_phys(x) + (BUS_OFFSET - PHYS_OFFSET))
+#define __bus_to_pfn(x)         __phys_to_pfn((x) - (BUS_OFFSET - PHYS_OFFSET))
 
 #endif
diff --git a/arch/arm/mach-ixp2000/include/mach/memory.h b/arch/arm/mach-ixp2000/include/mach/memory.h
index aee7eb8a71b2..98e3471be15b 100644
--- a/arch/arm/mach-ixp2000/include/mach/memory.h
+++ b/arch/arm/mach-ixp2000/include/mach/memory.h
@@ -17,11 +17,15 @@
 
 #include <mach/ixp2000-regs.h>
 
-#define __virt_to_bus(v) \
-        (((__virt_to_phys(v) - 0x0) + (*IXP2000_PCI_SDRAM_BAR & 0xfffffff0)))
+#define IXP2000_PCI_SDRAM_OFFSET        (*IXP2000_PCI_SDRAM_BAR & 0xfffffff0)
 
-#define __bus_to_virt(b) \
-        __phys_to_virt((((b - (*IXP2000_PCI_SDRAM_BAR & 0xfffffff0)) + 0x0)))
+#define __phys_to_bus(x)        ((x) + (IXP2000_PCI_SDRAM_OFFSET - PHYS_OFFSET))
+#define __bus_to_phys(x)        ((x) - (IXP2000_PCI_SDRAM_OFFSET - PHYS_OFFSET))
+
+#define __virt_to_bus(v)        __phys_to_bus(__virt_to_phys(v))
+#define __bus_to_virt(b)        __phys_to_virt(__bus_to_phys(b))
+#define __pfn_to_bus(p)         __phys_to_bus(__pfn_to_phys(p))
+#define __bus_to_pfn(b)         __phys_to_pfn(__bus_to_phys(b))
 
 #endif
 
diff --git a/arch/arm/mach-ixp23xx/include/mach/memory.h b/arch/arm/mach-ixp23xx/include/mach/memory.h
index fdd138706c70..94a3a86cfeb8 100644
--- a/arch/arm/mach-ixp23xx/include/mach/memory.h
+++ b/arch/arm/mach-ixp23xx/include/mach/memory.h
@@ -19,16 +19,15 @@
  */
 #define PHYS_OFFSET             (0x00000000)
 
-#define __virt_to_bus(v)                                                \
-        ({ unsigned int ret;                                            \
-        ret = ((__virt_to_phys(v) - 0x00000000) +                       \
-         (*((volatile int *)IXP23XX_PCI_SDRAM_BAR) & 0xfffffff0));      \
-        ret; })
-
-#define __bus_to_virt(b)                                                \
-        ({ unsigned int data;                                           \
-        data = *((volatile int *)IXP23XX_PCI_SDRAM_BAR);                \
-         __phys_to_virt((((b - (data & 0xfffffff0)) + 0x00000000))); })
+#define IXP23XX_PCI_SDRAM_OFFSET (*((volatile int *)IXP23XX_PCI_SDRAM_BAR) & 0xfffffff0))
+
+#define __phys_to_bus(x)        ((x) + (IXP23XX_PCI_SDRAM_OFFSET - PHYS_OFFSET))
+#define __bus_to_phys(x)        ((x) - (IXP23XX_PCI_SDRAM_OFFSET - PHYS_OFFSET))
+
+#define __virt_to_bus(v)        __phys_to_bus(__virt_to_phys(v))
+#define __bus_to_virt(b)        __phys_to_virt(__bus_to_phys(b))
+#define __pfn_to_bus(p)         __phys_to_bus(__pfn_to_phys(p))
+#define __bus_to_pfn(b)         __phys_to_pfn(__bus_to_phys(b))
 
 #define arch_is_coherent()      1
 
diff --git a/arch/arm/mach-ixp4xx/Kconfig b/arch/arm/mach-ixp4xx/Kconfig
index 264f4d59f898..9e5070da17ae 100644
--- a/arch/arm/mach-ixp4xx/Kconfig
+++ b/arch/arm/mach-ixp4xx/Kconfig
@@ -179,21 +179,21 @@ config IXP4XX_INDIRECT_PCI
         help
           IXP4xx provides two methods of accessing PCI memory space:
 
-          1) A direct mapped window from 0x48000000 to 0x4bffffff (64MB).
+          1) A direct mapped window from 0x48000000 to 0x4BFFFFFF (64MB).
              To access PCI via this space, we simply ioremap() the BAR
              into the kernel and we can use the standard read[bwl]/write[bwl]
              macros. This is the preferred method due to speed but it
-             limits the system to just 64MB of PCI memory. This can be 
+             limits the system to just 64MB of PCI memory. This can be
              problematic if using video cards and other memory-heavy devices.
-          
-          2) If > 64MB of memory space is required, the IXP4xx can be 
-             configured to use indirect registers to access PCI This allows 
-             for up to 128MB (0x48000000 to 0x4fffffff) of memory on the bus. 
-             The disadvantage of this is that every PCI access requires 
-             three local register accesses plus a spinlock, but in some 
-             cases the performance hit is acceptable. In addition, you cannot 
-             mmap() PCI devices in this case due to the indirect nature
-             of the PCI window.
+
+          2) If > 64MB of memory space is required, the IXP4xx can be
+             configured to use indirect registers to access the whole PCI
+             memory space. This currently allows for up to 1 GB (0x10000000
+             to 0x4FFFFFFF) of memory on the bus. The disadvantage of this
+             is that every PCI access requires three local register accesses
+             plus a spinlock, but in some cases the performance hit is
+             acceptable. In addition, you cannot mmap() PCI devices in this
+             case due to the indirect nature of the PCI window.
 
           By default, the direct method is used. Choose this option if you
           need to use the indirect method instead. If you don't know
diff --git a/arch/arm/mach-ixp4xx/avila-pci.c b/arch/arm/mach-ixp4xx/avila-pci.c
index 08d65dcdb5fe..845e1b500548 100644
--- a/arch/arm/mach-ixp4xx/avila-pci.c
+++ b/arch/arm/mach-ixp4xx/avila-pci.c
@@ -22,40 +22,45 @@
 #include <linux/init.h>
 #include <linux/irq.h>
 #include <linux/delay.h>
-
 #include <asm/mach/pci.h>
 #include <asm/irq.h>
 #include <mach/hardware.h>
 #include <asm/mach-types.h>
 
+#define AVILA_MAX_DEV   4
+#define LOFT_MAX_DEV    6
+#define IRQ_LINES       4
+
+/* PCI controller GPIO to IRQ pin mappings */
+#define INTA            11
+#define INTB            10
+#define INTC            9
+#define INTD            8
+
 void __init avila_pci_preinit(void)
 {
-        set_irq_type(IRQ_AVILA_PCI_INTA, IRQ_TYPE_LEVEL_LOW);
-        set_irq_type(IRQ_AVILA_PCI_INTB, IRQ_TYPE_LEVEL_LOW);
-        set_irq_type(IRQ_AVILA_PCI_INTC, IRQ_TYPE_LEVEL_LOW);
-        set_irq_type(IRQ_AVILA_PCI_INTD, IRQ_TYPE_LEVEL_LOW);
-
+        set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW);
+        set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW);
+        set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW);
+        set_irq_type(IXP4XX_GPIO_IRQ(INTD), IRQ_TYPE_LEVEL_LOW);
         ixp4xx_pci_preinit();
 }
 
 static int __init avila_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
 {
-        static int pci_irq_table[AVILA_PCI_IRQ_LINES] = {
-                IRQ_AVILA_PCI_INTA,
-                IRQ_AVILA_PCI_INTB,
-                IRQ_AVILA_PCI_INTC,
-                IRQ_AVILA_PCI_INTD
+        static int pci_irq_table[IRQ_LINES] = {
+                IXP4XX_GPIO_IRQ(INTA),
+                IXP4XX_GPIO_IRQ(INTB),
+                IXP4XX_GPIO_IRQ(INTC),
+                IXP4XX_GPIO_IRQ(INTD)
         };
 
-        int irq = -1;
-
         if (slot >= 1 &&
-        slot <= (machine_is_loft() ? LOFT_PCI_MAX_DEV : AVILA_PCI_MAX_DEV) &&
-                pin >= 1 && pin <= AVILA_PCI_IRQ_LINES) {
-                irq = pci_irq_table[(slot + pin - 2) % 4];
-        }
+            slot <= (machine_is_loft() ? LOFT_MAX_DEV : AVILA_MAX_DEV) &&
+            pin >= 1 && pin <= IRQ_LINES)
+                return pci_irq_table[(slot + pin - 2) % 4];
 
-        return irq;
+        return -1;
 }
 
 struct hw_pci avila_pci __initdata = {
@@ -75,4 +80,3 @@ int __init avila_pci_init(void)
 }
 
 subsys_initcall(avila_pci_init);
-
diff --git a/arch/arm/mach-ixp4xx/avila-setup.c b/arch/arm/mach-ixp4xx/avila-setup.c
index 797995ce18b9..6e558a76457d 100644
--- a/arch/arm/mach-ixp4xx/avila-setup.c
+++ b/arch/arm/mach-ixp4xx/avila-setup.c
@@ -19,7 +19,6 @@
 #include <linux/serial_8250.h>
 #include <linux/slab.h>
 #include <linux/i2c-gpio.h>
-
 #include <asm/types.h>
 #include <asm/setup.h>
 #include <asm/memory.h>
@@ -29,6 +28,9 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/flash.h>
 
+#define AVILA_SDA_PIN   7
+#define AVILA_SCL_PIN   6
+
 static struct flash_platform_data avila_flash_data = {
         .map_name       = "cfi_probe",
         .width          = 2,
diff --git a/arch/arm/mach-ixp4xx/common-pci.c b/arch/arm/mach-ixp4xx/common-pci.c
index 70afcfe5b881..c4a01594c761 100644
--- a/arch/arm/mach-ixp4xx/common-pci.c
+++ b/arch/arm/mach-ixp4xx/common-pci.c
@@ -481,11 +481,7 @@ int ixp4xx_setup(int nr, struct pci_sys_data *sys)
 
         res[1].name = "PCI Memory Space";
         res[1].start = PCIBIOS_MIN_MEM;
-#ifndef CONFIG_IXP4XX_INDIRECT_PCI
-        res[1].end = 0x4bffffff;
-#else
-        res[1].end = 0x4fffffff;
-#endif
+        res[1].end = PCIBIOS_MAX_MEM;
         res[1].flags = IORESOURCE_MEM;
 
         request_resource(&ioport_resource, &res[0]);
diff --git a/arch/arm/mach-ixp4xx/common.c b/arch/arm/mach-ixp4xx/common.c
index cfd52fb341cb..3bbf40f6d964 100644
--- a/arch/arm/mach-ixp4xx/common.c
+++ b/arch/arm/mach-ixp4xx/common.c
@@ -117,7 +117,7 @@ int gpio_to_irq(int gpio)
 }
 EXPORT_SYMBOL(gpio_to_irq);
 
-int irq_to_gpio(int irq)
+int irq_to_gpio(unsigned int irq)
 {
         int gpio = (irq < 32) ? irq2gpio[irq] : -EINVAL;
 
diff --git a/arch/arm/mach-ixp4xx/coyote-pci.c b/arch/arm/mach-ixp4xx/coyote-pci.c
index efddf01ed17b..b978ea8bd6f0 100644
--- a/arch/arm/mach-ixp4xx/coyote-pci.c
+++ b/arch/arm/mach-ixp4xx/coyote-pci.c
@@ -18,27 +18,31 @@
 #include <linux/pci.h>
 #include <linux/init.h>
 #include <linux/irq.h>
-
 #include <asm/mach-types.h>
 #include <mach/hardware.h>
 #include <asm/irq.h>
-
 #include <asm/mach/pci.h>
 
+#define SLOT0_DEVID     14
+#define SLOT1_DEVID     15
+
+/* PCI controller GPIO to IRQ pin mappings */
+#define SLOT0_INTA      6
+#define SLOT1_INTA      11
+
 void __init coyote_pci_preinit(void)
 {
-        set_irq_type(IRQ_COYOTE_PCI_SLOT0, IRQ_TYPE_LEVEL_LOW);
-        set_irq_type(IRQ_COYOTE_PCI_SLOT1, IRQ_TYPE_LEVEL_LOW);
-
+        set_irq_type(IXP4XX_GPIO_IRQ(SLOT0_INTA), IRQ_TYPE_LEVEL_LOW);
+        set_irq_type(IXP4XX_GPIO_IRQ(SLOT1_INTA), IRQ_TYPE_LEVEL_LOW);
         ixp4xx_pci_preinit();
 }
 
 static int __init coyote_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
 {
-        if (slot == COYOTE_PCI_SLOT0_DEVID)
-                return IRQ_COYOTE_PCI_SLOT0;
-        else if (slot == COYOTE_PCI_SLOT1_DEVID)
-                return IRQ_COYOTE_PCI_SLOT1;
+        if (slot == SLOT0_DEVID)
+                return IXP4XX_GPIO_IRQ(SLOT0_INTA);
+        else if (slot == SLOT1_DEVID)
+                return IXP4XX_GPIO_IRQ(SLOT1_INTA);
         else return -1;
 }
 
diff --git a/arch/arm/mach-ixp4xx/coyote-setup.c b/arch/arm/mach-ixp4xx/coyote-setup.c
index aab1954e2747..25bf5ad770ea 100644
--- a/arch/arm/mach-ixp4xx/coyote-setup.c
+++ b/arch/arm/mach-ixp4xx/coyote-setup.c
@@ -25,6 +25,15 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/flash.h>
 
+#define COYOTE_IDE_BASE_PHYS    IXP4XX_EXP_BUS_BASE(3)
+#define COYOTE_IDE_BASE_VIRT    0xFFFE1000
+#define COYOTE_IDE_REGION_SIZE  0x1000
+
+#define COYOTE_IDE_DATA_PORT    0xFFFE10E0
+#define COYOTE_IDE_CTRL_PORT    0xFFFE10FC
+#define COYOTE_IDE_ERROR_PORT   0xFFFE10E2
+#define IRQ_COYOTE_IDE          IRQ_IXP4XX_GPIO5
+
 static struct flash_platform_data coyote_flash_data = {
         .map_name       = "cfi_probe",
         .width          = 2,
diff --git a/arch/arm/mach-ixp4xx/dsmg600-pci.c b/arch/arm/mach-ixp4xx/dsmg600-pci.c
index 926d15f885fb..fa70fed462ba 100644
--- a/arch/arm/mach-ixp4xx/dsmg600-pci.c
+++ b/arch/arm/mach-ixp4xx/dsmg600-pci.c
@@ -19,39 +19,45 @@
 #include <linux/pci.h>
 #include <linux/init.h>
 #include <linux/irq.h>
-
 #include <asm/mach/pci.h>
 #include <asm/mach-types.h>
 
+#define MAX_DEV         4
+#define IRQ_LINES       3
+
+/* PCI controller GPIO to IRQ pin mappings */
+#define INTA            11
+#define INTB            10
+#define INTC            9
+#define INTD            8
+#define INTE            7
+#define INTF            6
+
 void __init dsmg600_pci_preinit(void)
 {
-        set_irq_type(IRQ_DSMG600_PCI_INTA, IRQ_TYPE_LEVEL_LOW);
-        set_irq_type(IRQ_DSMG600_PCI_INTB, IRQ_TYPE_LEVEL_LOW);
-        set_irq_type(IRQ_DSMG600_PCI_INTC, IRQ_TYPE_LEVEL_LOW);
-        set_irq_type(IRQ_DSMG600_PCI_INTD, IRQ_TYPE_LEVEL_LOW);
-        set_irq_type(IRQ_DSMG600_PCI_INTE, IRQ_TYPE_LEVEL_LOW);
-        set_irq_type(IRQ_DSMG600_PCI_INTF, IRQ_TYPE_LEVEL_LOW);
-
+        set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW);
+        set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW);
+        set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW);
+        set_irq_type(IXP4XX_GPIO_IRQ(INTD), IRQ_TYPE_LEVEL_LOW);
+        set_irq_type(IXP4XX_GPIO_IRQ(INTE), IRQ_TYPE_LEVEL_LOW);
+        set_irq_type(IXP4XX_GPIO_IRQ(INTF), IRQ_TYPE_LEVEL_LOW);
         ixp4xx_pci_preinit();
 }
 
 static int __init dsmg600_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
 {
-        static int pci_irq_table[DSMG600_PCI_MAX_DEV][DSMG600_PCI_IRQ_LINES] =
-        {
-                { IRQ_DSMG600_PCI_INTE, -1, -1 },
-                { IRQ_DSMG600_PCI_INTA, -1, -1 },
-                { IRQ_DSMG600_PCI_INTB, IRQ_DSMG600_PCI_INTC, IRQ_DSMG600_PCI_INTD },
-                { IRQ_DSMG600_PCI_INTF, -1, -1 },
+        static int pci_irq_table[MAX_DEV][IRQ_LINES] = {
+                { IXP4XX_GPIO_IRQ(INTE), -1, -1 },
+                { IXP4XX_GPIO_IRQ(INTA), -1, -1 },
+                { IXP4XX_GPIO_IRQ(INTB), IXP4XX_GPIO_IRQ(INTC),
+                  IXP4XX_GPIO_IRQ(INTD) },
+                { IXP4XX_GPIO_IRQ(INTF), -1, -1 },
         };
 
-        int irq = -1;
-
-        if (slot >= 1 && slot <= DSMG600_PCI_MAX_DEV &&
-                pin >= 1 && pin <= DSMG600_PCI_IRQ_LINES)
-                irq = pci_irq_table[slot-1][pin-1];
+        if (slot >= 1 && slot <= MAX_DEV && pin >= 1 && pin <= IRQ_LINES)
+                return pci_irq_table[slot - 1][pin - 1];
 
-        return irq;
+        return -1;
 }
 
 struct hw_pci __initdata dsmg600_pci = {
diff --git a/arch/arm/mach-ixp4xx/dsmg600-setup.c b/arch/arm/mach-ixp4xx/dsmg600-setup.c
index a51bfa6978b6..7c1fa54a6145 100644
--- a/arch/arm/mach-ixp4xx/dsmg600-setup.c
+++ b/arch/arm/mach-ixp4xx/dsmg600-setup.c
@@ -33,6 +33,23 @@
 #include <asm/mach/time.h>
 #include <asm/gpio.h>
 
+#define DSMG600_SDA_PIN         5
+#define DSMG600_SCL_PIN         4
+
+/* DSM-G600 Timer Setting */
+#define DSMG600_FREQ            66000000
+
+/* Buttons */
+#define DSMG600_PB_GPIO         15      /* power button */
+#define DSMG600_RB_GPIO         3       /* reset button */
+
+/* Power control */
+#define DSMG600_PO_GPIO         2       /* power off */
+
+/* LEDs */
+#define DSMG600_LED_PWR_GPIO    0
+#define DSMG600_LED_WLAN_GPIO   14
+
 static struct flash_platform_data dsmg600_flash_data = {
         .map_name               = "cfi_probe",
         .width                  = 2,
diff --git a/arch/arm/mach-ixp4xx/fsg-pci.c b/arch/arm/mach-ixp4xx/fsg-pci.c
index ca12a9ca0830..5a810c930624 100644
--- a/arch/arm/mach-ixp4xx/fsg-pci.c
+++ b/arch/arm/mach-ixp4xx/fsg-pci.c
@@ -19,33 +19,38 @@
 #include <linux/pci.h>
 #include <linux/init.h>
 #include <linux/irq.h>
-
 #include <asm/mach/pci.h>
 #include <asm/mach-types.h>
 
+#define MAX_DEV         3
+#define IRQ_LINES       3
+
+/* PCI controller GPIO to IRQ pin mappings */
+#define INTA    6
+#define INTB    7
+#define INTC    5
+
 void __init fsg_pci_preinit(void)
 {
-        set_irq_type(IRQ_FSG_PCI_INTA, IRQ_TYPE_LEVEL_LOW);
-        set_irq_type(IRQ_FSG_PCI_INTB, IRQ_TYPE_LEVEL_LOW);
-        set_irq_type(IRQ_FSG_PCI_INTC, IRQ_TYPE_LEVEL_LOW);
-
+        set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW);
+        set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW);
+        set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW);
         ixp4xx_pci_preinit();
 }
 
 static int __init fsg_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
 {
-        static int pci_irq_table[FSG_PCI_IRQ_LINES] = {
-                IRQ_FSG_PCI_INTC,
-                IRQ_FSG_PCI_INTB,
-                IRQ_FSG_PCI_INTA,
+        static int pci_irq_table[IRQ_LINES] = {
+                IXP4XX_GPIO_IRQ(INTC),
+                IXP4XX_GPIO_IRQ(INTB),
+                IXP4XX_GPIO_IRQ(INTA),
         };
 
         int irq = -1;
-        slot = slot - 11;
+        slot -= 11;
 
-        if (slot >= 1 && slot <= FSG_PCI_MAX_DEV &&
-            pin >= 1 && pin <= FSG_PCI_IRQ_LINES)
-                irq = pci_irq_table[(slot - 1)];
+        if (slot >= 1 && slot <= MAX_DEV && pin >= 1 && pin <= IRQ_LINES)
+                irq = pci_irq_table[slot - 1];
         printk(KERN_INFO "%s: Mapped slot %d pin %d to IRQ %d\n",
                __func__, slot, pin, irq);
 
diff --git a/arch/arm/mach-ixp4xx/fsg-setup.c b/arch/arm/mach-ixp4xx/fsg-setup.c
index 5add22fc9899..e7f4befba422 100644
--- a/arch/arm/mach-ixp4xx/fsg-setup.c
+++ b/arch/arm/mach-ixp4xx/fsg-setup.c
@@ -24,12 +24,18 @@
 #include <linux/i2c.h>
 #include <linux/i2c-gpio.h>
 #include <linux/io.h>
-
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/flash.h>
 #include <asm/gpio.h>
 
+#define FSG_SDA_PIN             12
+#define FSG_SCL_PIN             13
+
+#define FSG_SB_GPIO             4       /* sync button */
+#define FSG_RB_GPIO             9       /* reset button */
+#define FSG_UB_GPIO             10      /* usb button */
+
 static struct flash_platform_data fsg_flash_data = {
         .map_name               = "cfi_probe",
         .width                  = 2,
diff --git a/arch/arm/mach-ixp4xx/goramo_mlr.c b/arch/arm/mach-ixp4xx/goramo_mlr.c
index a733b8ff3cec..1c28048209c1 100644
--- a/arch/arm/mach-ixp4xx/goramo_mlr.c
+++ b/arch/arm/mach-ixp4xx/goramo_mlr.c
@@ -17,29 +17,28 @@
 #include <asm/mach/flash.h>
 #include <asm/mach/pci.h>
 
-#define xgpio_irq(n)            (IRQ_IXP4XX_GPIO ## n)
-#define gpio_irq(n)             xgpio_irq(n)
-
 #define SLOT_ETHA               0x0B    /* IDSEL = AD21 */
 #define SLOT_ETHB               0x0C    /* IDSEL = AD20 */
 #define SLOT_MPCI               0x0D    /* IDSEL = AD19 */
 #define SLOT_NEC                0x0E    /* IDSEL = AD18 */
 
-#define IRQ_ETHA                IRQ_IXP4XX_GPIO4
-#define IRQ_ETHB                IRQ_IXP4XX_GPIO5
-#define IRQ_NEC                 IRQ_IXP4XX_GPIO3
-#define IRQ_MPCI                IRQ_IXP4XX_GPIO12
-
 /* GPIO lines */
 #define GPIO_SCL                0
 #define GPIO_SDA                1
 #define GPIO_STR                2
+#define GPIO_IRQ_NEC            3
+#define GPIO_IRQ_ETHA           4
+#define GPIO_IRQ_ETHB           5
 #define GPIO_HSS0_DCD_N         6
 #define GPIO_HSS1_DCD_N         7
+#define GPIO_UART0_DCD          8
+#define GPIO_UART1_DCD          9
 #define GPIO_HSS0_CTS_N         10
 #define GPIO_HSS1_CTS_N         11
+#define GPIO_IRQ_MPCI           12
 #define GPIO_HSS1_RTS_N         13
 #define GPIO_HSS0_RTS_N         14
+/* GPIO15 is not connected */
 
 /* Control outputs from 74HC4094 */
 #define CONTROL_HSS0_CLK_INT    0
@@ -152,7 +151,7 @@ static int hss_set_clock(int port, unsigned int clock_type)
 
 static irqreturn_t hss_dcd_irq(int irq, void *pdev)
 {
-        int i, port = (irq == gpio_irq(GPIO_HSS1_DCD_N));
+        int i, port = (irq == IXP4XX_GPIO_IRQ(GPIO_HSS1_DCD_N));
         gpio_line_get(port ? GPIO_HSS1_DCD_N : GPIO_HSS0_DCD_N, &i);
         set_carrier_cb_tab[port](pdev, !i);
         return IRQ_HANDLED;
@@ -165,9 +164,9 @@ static int hss_open(int port, void *pdev,
         int i, irq;
 
         if (!port)
-                irq = gpio_irq(GPIO_HSS0_DCD_N);
+                irq = IXP4XX_GPIO_IRQ(GPIO_HSS0_DCD_N);
         else
-                irq = gpio_irq(GPIO_HSS1_DCD_N);
+                irq = IXP4XX_GPIO_IRQ(GPIO_HSS1_DCD_N);
 
         gpio_line_get(port ? GPIO_HSS1_DCD_N : GPIO_HSS0_DCD_N, &i);
         set_carrier_cb(pdev, !i);
@@ -188,8 +187,8 @@ static int hss_open(int port, void *pdev,
 
 static void hss_close(int port, void *pdev)
 {
-        free_irq(port ? gpio_irq(GPIO_HSS1_DCD_N) : gpio_irq(GPIO_HSS0_DCD_N),
-                 pdev);
+        free_irq(port ? IXP4XX_GPIO_IRQ(GPIO_HSS1_DCD_N) :
+                 IXP4XX_GPIO_IRQ(GPIO_HSS0_DCD_N), pdev);
         set_carrier_cb_tab[!!port] = NULL; /* catch bugs */
 
         set_control(port ? CONTROL_HSS1_DTR_N : CONTROL_HSS0_DTR_N, 1);
@@ -421,8 +420,8 @@ static void __init gmlr_init(void)
         gpio_line_config(GPIO_HSS1_RTS_N, IXP4XX_GPIO_OUT);
         gpio_line_config(GPIO_HSS0_DCD_N, IXP4XX_GPIO_IN);
         gpio_line_config(GPIO_HSS1_DCD_N, IXP4XX_GPIO_IN);
-        set_irq_type(gpio_irq(GPIO_HSS0_DCD_N), IRQ_TYPE_EDGE_BOTH);
-        set_irq_type(gpio_irq(GPIO_HSS1_DCD_N), IRQ_TYPE_EDGE_BOTH);
+        set_irq_type(IXP4XX_GPIO_IRQ(GPIO_HSS0_DCD_N), IRQ_TYPE_EDGE_BOTH);
+        set_irq_type(IXP4XX_GPIO_IRQ(GPIO_HSS1_DCD_N), IRQ_TYPE_EDGE_BOTH);
 
         set_control(CONTROL_HSS0_DTR_N, 1);
         set_control(CONTROL_HSS1_DTR_N, 1);
@@ -442,10 +441,10 @@ static void __init gmlr_init(void)
 #ifdef CONFIG_PCI
 static void __init gmlr_pci_preinit(void)
 {
-        set_irq_type(IRQ_ETHA, IRQ_TYPE_LEVEL_LOW);
-        set_irq_type(IRQ_ETHB, IRQ_TYPE_LEVEL_LOW);
-        set_irq_type(IRQ_NEC, IRQ_TYPE_LEVEL_LOW);
-        set_irq_type(IRQ_MPCI, IRQ_TYPE_LEVEL_LOW);
+        set_irq_type(IXP4XX_GPIO_IRQ(GPIO_IRQ_ETHA), IRQ_TYPE_LEVEL_LOW);
+        set_irq_type(IXP4XX_GPIO_IRQ(GPIO_IRQ_ETHB), IRQ_TYPE_LEVEL_LOW);
+        set_irq_type(IXP4XX_GPIO_IRQ(GPIO_IRQ_NEC), IRQ_TYPE_LEVEL_LOW);
+        set_irq_type(IXP4XX_GPIO_IRQ(GPIO_IRQ_MPCI), IRQ_TYPE_LEVEL_LOW);
         ixp4xx_pci_preinit();
 }
 
@@ -466,10 +465,10 @@ static void __init gmlr_pci_postinit(void)
 static int __init gmlr_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
 {
         switch(slot) {
-        case SLOT_ETHA: return IRQ_ETHA;
-        case SLOT_ETHB: return IRQ_ETHB;
-        case SLOT_NEC:  return IRQ_NEC;
-        default:        return IRQ_MPCI;
+        case SLOT_ETHA: return IXP4XX_GPIO_IRQ(GPIO_IRQ_ETHA);
+        case SLOT_ETHB: return IXP4XX_GPIO_IRQ(GPIO_IRQ_ETHB);
+        case SLOT_NEC:  return IXP4XX_GPIO_IRQ(GPIO_IRQ_NEC);
+        default:        return IXP4XX_GPIO_IRQ(GPIO_IRQ_MPCI);
         }
 }
 
diff --git a/arch/arm/mach-ixp4xx/gtwx5715-pci.c b/arch/arm/mach-ixp4xx/gtwx5715-pci.c
index 7b8a2c323840..25d2c333c204 100644
--- a/arch/arm/mach-ixp4xx/gtwx5715-pci.c
+++ b/arch/arm/mach-ixp4xx/gtwx5715-pci.c
@@ -26,14 +26,16 @@
 #include <linux/init.h>
 #include <linux/delay.h>
 #include <linux/irq.h>
-
 #include <asm/mach-types.h>
 #include <mach/hardware.h>
-#include <mach/gtwx5715.h>
 #include <asm/mach/pci.h>
 
+#define SLOT0_DEVID     0
+#define SLOT1_DEVID     1
+#define INTA            10 /* slot 1 has INTA and INTB crossed */
+#define INTB            11
+
 /*
- * The exact GPIO pins and IRQs are defined in arch-ixp4xx/gtwx5715.h
  * Slot 0 isn't actually populated with a card connector but
  * we initialize it anyway in case a future version has the
  * slot populated or someone with good soldering skills has
@@ -41,32 +43,26 @@
  */
 void __init gtwx5715_pci_preinit(void)
 {
-        set_irq_type(GTWX5715_PCI_SLOT0_INTA_IRQ, IRQ_TYPE_LEVEL_LOW);
-        set_irq_type(GTWX5715_PCI_SLOT0_INTB_IRQ, IRQ_TYPE_LEVEL_LOW);
-        set_irq_type(GTWX5715_PCI_SLOT1_INTA_IRQ, IRQ_TYPE_LEVEL_LOW);
-        set_irq_type(GTWX5715_PCI_SLOT1_INTB_IRQ, IRQ_TYPE_LEVEL_LOW);
-
+        set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW);
+        set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW);
         ixp4xx_pci_preinit();
 }
 
 
 static int __init gtwx5715_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
 {
-        int rc;
-        static int gtwx5715_irqmap
-                        [GTWX5715_PCI_SLOT_COUNT]
-                        [GTWX5715_PCI_INT_PIN_COUNT] = {
-        {GTWX5715_PCI_SLOT0_INTA_IRQ, GTWX5715_PCI_SLOT0_INTB_IRQ},
-        {GTWX5715_PCI_SLOT1_INTA_IRQ, GTWX5715_PCI_SLOT1_INTB_IRQ},
-};
+        int rc = -1;
 
-        if (slot >= GTWX5715_PCI_SLOT_COUNT ||
-                        pin >= GTWX5715_PCI_INT_PIN_COUNT) rc = -1;
-        else
-                rc = gtwx5715_irqmap[slot][pin-1];
+        if ((slot == SLOT0_DEVID && pin == 1) ||
+            (slot == SLOT1_DEVID && pin == 2))
+                rc = IXP4XX_GPIO_IRQ(INTA);
+        else if ((slot == SLOT0_DEVID && pin == 2) ||
+                 (slot == SLOT1_DEVID && pin == 1))
+                rc = IXP4XX_GPIO_IRQ(INTB);
 
-        printk("%s: Mapped slot %d pin %d to IRQ %d\n", __func__, slot, pin, rc);
-        return(rc);
+        printk(KERN_INFO "%s: Mapped slot %d pin %d to IRQ %d\n",
+               __func__, slot, pin, rc);
+        return rc;
 }
 
 struct hw_pci gtwx5715_pci __initdata = {
@@ -81,9 +77,7 @@ struct hw_pci gtwx5715_pci __initdata = {
 int __init gtwx5715_pci_init(void)
 {
         if (machine_is_gtwx5715())
-        {
                 pci_common_init(&gtwx5715_pci);
-        }
 
         return 0;
 }
diff --git a/arch/arm/mach-ixp4xx/gtwx5715-setup.c b/arch/arm/mach-ixp4xx/gtwx5715-setup.c
index 25c21d6665ec..0bc7185cb6f7 100644
--- a/arch/arm/mach-ixp4xx/gtwx5715-setup.c
+++ b/arch/arm/mach-ixp4xx/gtwx5715-setup.c
@@ -28,7 +28,6 @@
 #include <linux/tty.h>
 #include <linux/serial_8250.h>
 #include <linux/slab.h>
-
 #include <asm/types.h>
 #include <asm/setup.h>
 #include <asm/memory.h>
@@ -37,7 +36,34 @@
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/flash.h>
-#include <mach/gtwx5715.h>
+
+/* GPIO 5,6,7 and 12 are hard wired to the Kendin KS8995M Switch
+   and operate as an SPI type interface.  The details of the interface
+   are available on Kendin/Micrel's web site. */
+
+#define GTWX5715_KSSPI_SELECT   5
+#define GTWX5715_KSSPI_TXD      6
+#define GTWX5715_KSSPI_CLOCK    7
+#define GTWX5715_KSSPI_RXD      12
+
+/* The "reset" button is wired to GPIO 3.
+   The GPIO is brought "low" when the button is pushed. */
+
+#define GTWX5715_BUTTON_GPIO    3
+
+/* Board Label      Front Label
+   LED1             Power
+   LED2             Wireless-G
+   LED3             not populated but could be
+   LED4             Internet
+   LED5 - LED8      Controlled by KS8995M Switch
+   LED9             DMZ */
+
+#define GTWX5715_LED1_GPIO      2
+#define GTWX5715_LED2_GPIO      9
+#define GTWX5715_LED3_GPIO      8
+#define GTWX5715_LED4_GPIO      1
+#define GTWX5715_LED9_GPIO      4
 
 /*
  * Xscale UART registers are 32 bits wide with only the least
diff --git a/arch/arm/mach-ixp4xx/include/mach/avila.h b/arch/arm/mach-ixp4xx/include/mach/avila.h
deleted file mode 100644
index 1640cb61972b..000000000000
--- a/arch/arm/mach-ixp4xx/include/mach/avila.h
+++ /dev/null
@@ -1,39 +0,0 @@
-/*
- * arch/arm/mach-ixp4xx/include/mach/avila.h
- *
- * Gateworks Avila platform specific definitions
- *
- * Author: Michael-Luke Jones <mlj28@cam.ac.uk>
- *
- * Based on ixdp425.h
- * Author: Deepak Saxena <dsaxena@plexity.net>
- *
- * Copyright 2004 (c) MontaVista, Software, Inc.
- *
- * This file is licensed under  the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#ifndef __ASM_ARCH_HARDWARE_H__
-#error "Do not include this directly, instead #include <mach/hardware.h>"
-#endif
-
-#define AVILA_SDA_PIN           7
-#define AVILA_SCL_PIN           6
-
-/*
- * AVILA PCI IRQs
- */
-#define AVILA_PCI_MAX_DEV       4
-#define LOFT_PCI_MAX_DEV    6
-#define AVILA_PCI_IRQ_LINES     4
-
-
-/* PCI controller GPIO to IRQ pin mappings */
-#define AVILA_PCI_INTA_PIN      11
-#define AVILA_PCI_INTB_PIN      10
-#define AVILA_PCI_INTC_PIN      9
-#define AVILA_PCI_INTD_PIN      8
-
-
diff --git a/arch/arm/mach-ixp4xx/include/mach/coyote.h b/arch/arm/mach-ixp4xx/include/mach/coyote.h
deleted file mode 100644
index 717ac6d16f55..000000000000
--- a/arch/arm/mach-ixp4xx/include/mach/coyote.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/*
- * arch/arm/mach-ixp4xx/include/mach/coyote.h
- *
- * ADI Engineering platform specific definitions
- *
- * Author: Deepak Saxena <dsaxena@plexity.net>
- *
- * Copyright 2004 (c) MontaVista, Software, Inc. 
- * 
- * This file is licensed under  the terms of the GNU General Public 
- * License version 2. This program is licensed "as is" without any 
- * warranty of any kind, whether express or implied.
- */
-
-#ifndef __ASM_ARCH_HARDWARE_H__
-#error "Do not include this directly, instead #include <mach/hardware.h>"
-#endif
-
-/* PCI controller GPIO to IRQ pin mappings */
-#define COYOTE_PCI_SLOT0_PIN    6
-#define COYOTE_PCI_SLOT1_PIN    11
-
-#define COYOTE_PCI_SLOT0_DEVID  14
-#define COYOTE_PCI_SLOT1_DEVID  15
-
-#define COYOTE_IDE_BASE_PHYS    IXP4XX_EXP_BUS_BASE(3)
-#define COYOTE_IDE_BASE_VIRT    0xFFFE1000
-#define COYOTE_IDE_REGION_SIZE  0x1000
-
-#define COYOTE_IDE_DATA_PORT    0xFFFE10E0
-#define COYOTE_IDE_CTRL_PORT    0xFFFE10FC
-#define COYOTE_IDE_ERROR_PORT   0xFFFE10E2
-
diff --git a/arch/arm/mach-ixp4xx/include/mach/dsmg600.h b/arch/arm/mach-ixp4xx/include/mach/dsmg600.h
deleted file mode 100644
index dc087a34a268..000000000000
--- a/arch/arm/mach-ixp4xx/include/mach/dsmg600.h
+++ /dev/null
@@ -1,52 +0,0 @@
-/*
- * DSM-G600 platform specific definitions
- *
- * Copyright (C) 2006 Tower Technologies
- * Author: Alessandro Zummo <a.zummo@towertech.it>
- *
- * based on ixdp425.h:
- *      Copyright 2004 (C) MontaVista, Software, Inc.
- *
- * This file is licensed under  the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#ifndef __ASM_ARCH_HARDWARE_H__
-#error "Do not include this directly, instead #include <mach/hardware.h>"
-#endif
-
-#define DSMG600_SDA_PIN         5
-#define DSMG600_SCL_PIN         4
-
-/*
- * DSMG600 PCI IRQs
- */
-#define DSMG600_PCI_MAX_DEV     4
-#define DSMG600_PCI_IRQ_LINES   3
-
-
-/* PCI controller GPIO to IRQ pin mappings */
-#define DSMG600_PCI_INTA_PIN    11
-#define DSMG600_PCI_INTB_PIN    10
-#define DSMG600_PCI_INTC_PIN    9
-#define DSMG600_PCI_INTD_PIN    8
-#define DSMG600_PCI_INTE_PIN    7
-#define DSMG600_PCI_INTF_PIN    6
-
-/* DSM-G600 Timer Setting */
-#define DSMG600_FREQ 66000000
-
-/* Buttons */
-
-#define DSMG600_PB_GPIO         15      /* power button */
-#define DSMG600_RB_GPIO         3       /* reset button */
-
-/* Power control */
-
-#define DSMG600_PO_GPIO         2       /* power off */
-
-/* LEDs */
-
-#define DSMG600_LED_PWR_GPIO    0
-#define DSMG600_LED_WLAN_GPIO   14
diff --git a/arch/arm/mach-ixp4xx/include/mach/fsg.h b/arch/arm/mach-ixp4xx/include/mach/fsg.h
deleted file mode 100644
index 1f02b7e22a13..000000000000
--- a/arch/arm/mach-ixp4xx/include/mach/fsg.h
+++ /dev/null
@@ -1,50 +0,0 @@
-/*
- * arch/arm/mach-ixp4xx/include/mach/fsg.h
- *
- * Freecom FSG-3 platform specific definitions
- *
- * Author: Rod Whitby <rod@whitby.id.au>
- * Author: Tomasz Chmielewski <mangoo@wpkg.org>
- * Maintainers: http://www.nslu2-linux.org
- *
- * Based on coyote.h by
- * Copyright 2004 (c) MontaVista, Software, Inc.
- *
- * This file is licensed under  the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#ifndef __ASM_ARCH_HARDWARE_H__
-#error "Do not include this directly, instead #include <mach/hardware.h>"
-#endif
-
-#define FSG_SDA_PIN             12
-#define FSG_SCL_PIN             13
-
-/*
- * FSG PCI IRQs
- */
-#define FSG_PCI_MAX_DEV         3
-#define FSG_PCI_IRQ_LINES       3
-
-
-/* PCI controller GPIO to IRQ pin mappings */
-#define FSG_PCI_INTA_PIN        6
-#define FSG_PCI_INTB_PIN        7
-#define FSG_PCI_INTC_PIN        5
-
-/* Buttons */
-
-#define FSG_SB_GPIO             4       /* sync button */
-#define FSG_RB_GPIO             9       /* reset button */
-#define FSG_UB_GPIO             10      /* usb button */
-
-/* LEDs */
-
-#define FSG_LED_WLAN_BIT        0
-#define FSG_LED_WAN_BIT         1
-#define FSG_LED_SATA_BIT        2
-#define FSG_LED_USB_BIT         4
-#define FSG_LED_RING_BIT        5
-#define FSG_LED_SYNC_BIT        7
diff --git a/arch/arm/mach-ixp4xx/include/mach/gpio.h b/arch/arm/mach-ixp4xx/include/mach/gpio.h
index cd5aec26c072..a5f87ded2f28 100644
--- a/arch/arm/mach-ixp4xx/include/mach/gpio.h
+++ b/arch/arm/mach-ixp4xx/include/mach/gpio.h
@@ -70,7 +70,7 @@ static inline void gpio_set_value(unsigned gpio, int value)
 #include <asm-generic/gpio.h>                   /* cansleep wrappers */
 
 extern int gpio_to_irq(int gpio);
-extern int irq_to_gpio(int gpio);
+extern int irq_to_gpio(unsigned int irq);
 
 #endif
 
diff --git a/arch/arm/mach-ixp4xx/include/mach/gtwx5715.h b/arch/arm/mach-ixp4xx/include/mach/gtwx5715.h
deleted file mode 100644
index 5d5e201cac7e..000000000000
--- a/arch/arm/mach-ixp4xx/include/mach/gtwx5715.h
+++ /dev/null
@@ -1,116 +0,0 @@
-/*
- * arch/arm/mach-ixp4xx/include/mach/gtwx5715.h
- *
- * Gemtek GTWX5715 Gateway (Linksys WRV54G)
- *
- * Copyright 2004 (c) George T. Joseph
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
- */
-
-#ifndef __ASM_ARCH_HARDWARE_H__
-#error "Do not include this directly, instead #include <mach/hardware.h>"
-#endif
-#include "irqs.h"
-
-#define GTWX5715_GPIO0  0
-#define GTWX5715_GPIO1  1
-#define GTWX5715_GPIO2  2
-#define GTWX5715_GPIO3  3
-#define GTWX5715_GPIO4  4
-#define GTWX5715_GPIO5  5
-#define GTWX5715_GPIO6  6
-#define GTWX5715_GPIO7  7
-#define GTWX5715_GPIO8  8
-#define GTWX5715_GPIO9  9
-#define GTWX5715_GPIO10 10
-#define GTWX5715_GPIO11 11
-#define GTWX5715_GPIO12 12
-#define GTWX5715_GPIO13 13
-#define GTWX5715_GPIO14 14
-
-#define GTWX5715_GPIO0_IRQ                      IRQ_IXP4XX_GPIO0
-#define GTWX5715_GPIO1_IRQ                      IRQ_IXP4XX_GPIO1
-#define GTWX5715_GPIO2_IRQ                      IRQ_IXP4XX_GPIO2
-#define GTWX5715_GPIO3_IRQ                      IRQ_IXP4XX_GPIO3
-#define GTWX5715_GPIO4_IRQ                      IRQ_IXP4XX_GPIO4
-#define GTWX5715_GPIO5_IRQ                      IRQ_IXP4XX_GPIO5
-#define GTWX5715_GPIO6_IRQ                      IRQ_IXP4XX_GPIO6
-#define GTWX5715_GPIO7_IRQ                      IRQ_IXP4XX_GPIO7
-#define GTWX5715_GPIO8_IRQ                      IRQ_IXP4XX_GPIO8
-#define GTWX5715_GPIO9_IRQ                      IRQ_IXP4XX_GPIO9
-#define GTWX5715_GPIO10_IRQ             IRQ_IXP4XX_GPIO10
-#define GTWX5715_GPIO11_IRQ             IRQ_IXP4XX_GPIO11
-#define GTWX5715_GPIO12_IRQ             IRQ_IXP4XX_GPIO12
-#define GTWX5715_GPIO13_IRQ             IRQ_IXP4XX_SW_INT1
-#define GTWX5715_GPIO14_IRQ             IRQ_IXP4XX_SW_INT2
-
-/* PCI controller GPIO to IRQ pin mappings
-
-                        INTA    INTB
-SLOT 0  10              11
-SLOT 1  11              10
-
-*/
-
-#define GTWX5715_PCI_SLOT0_DEVID        0
-#define GTWX5715_PCI_SLOT0_INTA_GPIO    GTWX5715_GPIO10
-#define GTWX5715_PCI_SLOT0_INTB_GPIO    GTWX5715_GPIO11
-#define GTWX5715_PCI_SLOT0_INTA_IRQ     GTWX5715_GPIO10_IRQ
-#define GTWX5715_PCI_SLOT0_INTB_IRQ     GTWX5715_GPIO11_IRQ
-
-#define GTWX5715_PCI_SLOT1_DEVID        1
-#define GTWX5715_PCI_SLOT1_INTA_GPIO    GTWX5715_GPIO11
-#define GTWX5715_PCI_SLOT1_INTB_GPIO    GTWX5715_GPIO10
-#define GTWX5715_PCI_SLOT1_INTA_IRQ     GTWX5715_GPIO11_IRQ
-#define GTWX5715_PCI_SLOT1_INTB_IRQ     GTWX5715_GPIO10_IRQ
-
-#define GTWX5715_PCI_SLOT_COUNT                 2
-#define GTWX5715_PCI_INT_PIN_COUNT              2
-
-/*
- * GPIO 5,6,7 and12 are hard wired to the Kendin KS8995M Switch
- * and operate as an SPI type interface.  The details of the interface
- * are available on Kendin/Micrel's web site.
- */
-
-#define GTWX5715_KSSPI_SELECT   GTWX5715_GPIO5
-#define GTWX5715_KSSPI_TXD              GTWX5715_GPIO6
-#define GTWX5715_KSSPI_CLOCK    GTWX5715_GPIO7
-#define GTWX5715_KSSPI_RXD              GTWX5715_GPIO12
-
-/*
- * The "reset" button is wired to GPIO 3.
- * The GPIO is brought "low" when the button is pushed.
- */
-
-#define GTWX5715_BUTTON_GPIO    GTWX5715_GPIO3
-#define GTWX5715_BUTTON_IRQ     GTWX5715_GPIO3_IRQ
-
-/*
- *  Board Label      Front Label
- *  LED1             Power
- *  LED2             Wireless-G
- *  LED3             not populated but could be
- *  LED4             Internet
- *  LED5 - LED8      Controlled by KS8995M Switch
- *  LED9             DMZ
- */
-
-#define GTWX5715_LED1_GPIO              GTWX5715_GPIO2
-#define GTWX5715_LED2_GPIO              GTWX5715_GPIO9
-#define GTWX5715_LED3_GPIO              GTWX5715_GPIO8
-#define GTWX5715_LED4_GPIO              GTWX5715_GPIO1
-#define GTWX5715_LED9_GPIO              GTWX5715_GPIO4
diff --git a/arch/arm/mach-ixp4xx/include/mach/hardware.h b/arch/arm/mach-ixp4xx/include/mach/hardware.h
index f58a43a23966..f9d1c43e4a54 100644
--- a/arch/arm/mach-ixp4xx/include/mach/hardware.h
+++ b/arch/arm/mach-ixp4xx/include/mach/hardware.h
@@ -18,7 +18,13 @@
 #define __ASM_ARCH_HARDWARE_H__
 
 #define PCIBIOS_MIN_IO          0x00001000
-#define PCIBIOS_MIN_MEM         (cpu_is_ixp43x() ? 0x40000000 : 0x48000000)
+#ifdef CONFIG_IXP4XX_INDIRECT_PCI
+#define PCIBIOS_MIN_MEM         0x10000000 /* 1 GB of indirect PCI MMIO space */
+#define PCIBIOS_MAX_MEM         0x4FFFFFFF
+#else
+#define PCIBIOS_MIN_MEM         0x48000000 /* 64 MB of PCI MMIO space */
+#define PCIBIOS_MAX_MEM         0x4BFFFFFF
+#endif
 
 /*
  * We override the standard dma-mask routines for bouncing.
@@ -37,14 +43,4 @@
 /* Platform helper functions and definitions */
 #include "platform.h"
 
-/* Platform specific details */
-#include "ixdp425.h"
-#include "avila.h"
-#include "coyote.h"
-#include "prpmc1100.h"
-#include "nslu2.h"
-#include "nas100d.h"
-#include "dsmg600.h"
-#include "fsg.h"
-
 #endif  /* _ASM_ARCH_HARDWARE_H */
diff --git a/arch/arm/mach-ixp4xx/include/mach/io.h b/arch/arm/mach-ixp4xx/include/mach/io.h
index 8a947d42a6f1..6ea7e2fb2701 100644
--- a/arch/arm/mach-ixp4xx/include/mach/io.h
+++ b/arch/arm/mach-ixp4xx/include/mach/io.h
@@ -26,22 +26,20 @@ extern int ixp4xx_pci_write(u32 addr, u32 cmd, u32 data);
 /*
  * IXP4xx provides two methods of accessing PCI memory space:
  *
- * 1) A direct mapped window from 0x48000000 to 0x4bffffff (64MB).
+ * 1) A direct mapped window from 0x48000000 to 0x4BFFFFFF (64MB).
  *    To access PCI via this space, we simply ioremap() the BAR
  *    into the kernel and we can use the standard read[bwl]/write[bwl]
  *    macros. This is the preffered method due to speed but it
- *    limits the system to just 64MB of PCI memory. This can be 
- *    problamatic if using video cards and other memory-heavy
- *    targets.
- *
- * 2) If > 64MB of memory space is required, the IXP4xx can be configured
- *    to use indirect registers to access PCI (as we do below for I/O
- *    transactions). This allows for up to 128MB (0x48000000 to 0x4fffffff)
- *    of memory on the bus. The disadvantage of this is that every 
- *    PCI access requires three local register accesses plus a spinlock,
- *    but in some cases the performance hit is acceptable. In addition,
- *    you cannot mmap() PCI devices in this case.
+ *    limits the system to just 64MB of PCI memory. This can be
+ *    problematic if using video cards and other memory-heavy targets.
  *
+ * 2) If > 64MB of memory space is required, the IXP4xx can use indirect
+ *    registers to access the whole 4 GB of PCI memory space (as we do below
+ *    for I/O transactions). This allows currently for up to 1 GB (0x10000000
+ *    to 0x4FFFFFFF) of memory on the bus. The disadvantage of this is that
+ *    every PCI access requires three local register accesses plus a spinlock,
+ *    but in some cases the performance hit is acceptable. In addition, you
+ *    cannot mmap() PCI devices in this case.
  */
 #ifndef CONFIG_IXP4XX_INDIRECT_PCI
 
@@ -55,48 +53,52 @@ extern int ixp4xx_pci_write(u32 addr, u32 cmd, u32 data);
  * access registers. If something outside of PCI is ioremap'd, we
  * fallback to the default.
  */
-static inline void __iomem *
-__ixp4xx_ioremap(unsigned long addr, size_t size, unsigned int mtype)
+
+static inline int is_pci_memory(u32 addr)
+{
+        return (addr >= PCIBIOS_MIN_MEM) && (addr <= 0x4FFFFFFF);
+}
+
+static inline void __iomem * __indirect_ioremap(unsigned long addr, size_t size,
+                                                unsigned int mtype)
 {
-        if((addr < PCIBIOS_MIN_MEM) || (addr > 0x4fffffff))
+        if (!is_pci_memory(addr))
                 return __arm_ioremap(addr, size, mtype);
 
         return (void __iomem *)addr;
 }
 
-static inline void
-__ixp4xx_iounmap(void __iomem *addr)
+static inline void __indirect_iounmap(void __iomem *addr)
 {
-        if ((__force u32)addr >= VMALLOC_START)
+        if (!is_pci_memory((__force u32)addr))
                 __iounmap(addr);
 }
 
-#define __arch_ioremap(a, s, f)         __ixp4xx_ioremap(a, s, f)
-#define __arch_iounmap(a)               __ixp4xx_iounmap(a)
+#define __arch_ioremap(a, s, f)         __indirect_ioremap(a, s, f)
+#define __arch_iounmap(a)               __indirect_iounmap(a)
 
-#define writeb(v, p)                    __ixp4xx_writeb(v, p)
-#define writew(v, p)                    __ixp4xx_writew(v, p)
-#define writel(v, p)                    __ixp4xx_writel(v, p)
+#define writeb(v, p)                    __indirect_writeb(v, p)
+#define writew(v, p)                    __indirect_writew(v, p)
+#define writel(v, p)                    __indirect_writel(v, p)
 
-#define writesb(p, v, l)                __ixp4xx_writesb(p, v, l)
-#define writesw(p, v, l)                __ixp4xx_writesw(p, v, l)
-#define writesl(p, v, l)                __ixp4xx_writesl(p, v, l)
-        
-#define readb(p)                        __ixp4xx_readb(p)
-#define readw(p)                        __ixp4xx_readw(p)
-#define readl(p)                        __ixp4xx_readl(p)
-        
-#define readsb(p, v, l)                 __ixp4xx_readsb(p, v, l)
-#define readsw(p, v, l)                 __ixp4xx_readsw(p, v, l)
-#define readsl(p, v, l)                 __ixp4xx_readsl(p, v, l)
+#define writesb(p, v, l)                __indirect_writesb(p, v, l)
+#define writesw(p, v, l)                __indirect_writesw(p, v, l)
+#define writesl(p, v, l)                __indirect_writesl(p, v, l)
 
-static inline void 
-__ixp4xx_writeb(u8 value, volatile void __iomem *p)
+#define readb(p)                        __indirect_readb(p)
+#define readw(p)                        __indirect_readw(p)
+#define readl(p)                        __indirect_readl(p)
+
+#define readsb(p, v, l)                 __indirect_readsb(p, v, l)
+#define readsw(p, v, l)                 __indirect_readsw(p, v, l)
+#define readsl(p, v, l)                 __indirect_readsl(p, v, l)
+
+static inline void __indirect_writeb(u8 value, volatile void __iomem *p)
 {
         u32 addr = (u32)p;
         u32 n, byte_enables, data;
 
-        if (addr >= VMALLOC_START) {
+        if (!is_pci_memory(addr)) {
                 __raw_writeb(value, addr);
                 return;
         }
@@ -107,20 +109,19 @@ __ixp4xx_writeb(u8 value, volatile void __iomem *p)
         ixp4xx_pci_write(addr, byte_enables | NP_CMD_MEMWRITE, data);
 }
 
-static inline void
-__ixp4xx_writesb(volatile void __iomem *bus_addr, const u8 *vaddr, int count)
+static inline void __indirect_writesb(volatile void __iomem *bus_addr,
+                                      const u8 *vaddr, int count)
 {
         while (count--)
                 writeb(*vaddr++, bus_addr);
 }
 
-static inline void 
-__ixp4xx_writew(u16 value, volatile void __iomem *p)
+static inline void __indirect_writew(u16 value, volatile void __iomem *p)
 {
         u32 addr = (u32)p;
         u32 n, byte_enables, data;
 
-        if (addr >= VMALLOC_START) {
+        if (!is_pci_memory(addr)) {
                 __raw_writew(value, addr);
                 return;
         }
@@ -131,18 +132,18 @@ __ixp4xx_writew(u16 value, volatile void __iomem *p)
         ixp4xx_pci_write(addr, byte_enables | NP_CMD_MEMWRITE, data);
 }
 
-static inline void
-__ixp4xx_writesw(volatile void __iomem *bus_addr, const u16 *vaddr, int count)
+static inline void __indirect_writesw(volatile void __iomem *bus_addr,
+                                      const u16 *vaddr, int count)
 {
         while (count--)
                 writew(*vaddr++, bus_addr);
 }
 
-static inline void 
-__ixp4xx_writel(u32 value, volatile void __iomem *p)
+static inline void __indirect_writel(u32 value, volatile void __iomem *p)
 {
         u32 addr = (__force u32)p;
-        if (addr >= VMALLOC_START) {
+
+        if (!is_pci_memory(addr)) {
                 __raw_writel(value, p);
                 return;
         }
@@ -150,20 +151,19 @@ __ixp4xx_writel(u32 value, volatile void __iomem *p)
         ixp4xx_pci_write(addr, NP_CMD_MEMWRITE, value);
 }
 
-static inline void
-__ixp4xx_writesl(volatile void __iomem *bus_addr, const u32 *vaddr, int count)
+static inline void __indirect_writesl(volatile void __iomem *bus_addr,
+                                      const u32 *vaddr, int count)
 {
         while (count--)
                 writel(*vaddr++, bus_addr);
 }
 
-static inline unsigned char 
-__ixp4xx_readb(const volatile void __iomem *p)
+static inline unsigned char __indirect_readb(const volatile void __iomem *p)
 {
         u32 addr = (u32)p;
         u32 n, byte_enables, data;
 
-        if (addr >= VMALLOC_START)
+        if (!is_pci_memory(addr))
                 return __raw_readb(addr);
 
         n = addr % 4;
@@ -174,20 +174,19 @@ __ixp4xx_readb(const volatile void __iomem *p)
         return data >> (8*n);
 }
 
-static inline void
-__ixp4xx_readsb(const volatile void __iomem *bus_addr, u8 *vaddr, u32 count)
+static inline void __indirect_readsb(const volatile void __iomem *bus_addr,
+                                     u8 *vaddr, u32 count)
 {
         while (count--)
                 *vaddr++ = readb(bus_addr);
 }
 
-static inline unsigned short 
-__ixp4xx_readw(const volatile void __iomem *p)
+static inline unsigned short __indirect_readw(const volatile void __iomem *p)
 {
         u32 addr = (u32)p;
         u32 n, byte_enables, data;
 
-        if (addr >= VMALLOC_START)
+        if (!is_pci_memory(addr))
                 return __raw_readw(addr);
 
         n = addr % 4;
@@ -198,20 +197,19 @@ __ixp4xx_readw(const volatile void __iomem *p)
         return data>>(8*n);
 }
 
-static inline void 
-__ixp4xx_readsw(const volatile void __iomem *bus_addr, u16 *vaddr, u32 count)
+static inline void __indirect_readsw(const volatile void __iomem *bus_addr,
+                                     u16 *vaddr, u32 count)
 {
         while (count--)
                 *vaddr++ = readw(bus_addr);
 }
 
-static inline unsigned long 
-__ixp4xx_readl(const volatile void __iomem *p)
+static inline unsigned long __indirect_readl(const volatile void __iomem *p)
 {
         u32 addr = (__force u32)p;
         u32 data;
 
-        if (addr >= VMALLOC_START)
+        if (!is_pci_memory(addr))
                 return __raw_readl(p);
 
         if (ixp4xx_pci_read(addr, NP_CMD_MEMREAD, &data))
@@ -220,8 +218,8 @@ __ixp4xx_readl(const volatile void __iomem *p)
         return data;
 }
 
-static inline void 
-__ixp4xx_readsl(const volatile void __iomem *bus_addr, u32 *vaddr, u32 count)
+static inline void __indirect_readsl(const volatile void __iomem *bus_addr,
+                                     u32 *vaddr, u32 count)
 {
         while (count--)
                 *vaddr++ = readl(bus_addr);
@@ -235,7 +233,7 @@ __ixp4xx_readsl(const volatile void __iomem *bus_addr, u32 *vaddr, u32 count)
 #define memcpy_fromio(a,c,l)            _memcpy_fromio((a),(c),(l))
 #define memcpy_toio(c,a,l)              _memcpy_toio((c),(a),(l))
 
-#endif
+#endif /* CONFIG_IXP4XX_INDIRECT_PCI */
 
 #ifndef CONFIG_PCI
 
@@ -250,25 +248,8 @@ __ixp4xx_readsl(const volatile void __iomem *bus_addr, u32 *vaddr, u32 count)
  * transaction.  This means that we need to override the default
  * I/O functions.
  */
-#define outb(p, v)                      __ixp4xx_outb(p, v)
-#define outw(p, v)                      __ixp4xx_outw(p, v)
-#define outl(p, v)                      __ixp4xx_outl(p, v)
-        
-#define outsb(p, v, l)                  __ixp4xx_outsb(p, v, l)
-#define outsw(p, v, l)                  __ixp4xx_outsw(p, v, l)
-#define outsl(p, v, l)                  __ixp4xx_outsl(p, v, l)
 
-#define inb(p)                          __ixp4xx_inb(p)
-#define inw(p)                          __ixp4xx_inw(p)
-#define inl(p)                          __ixp4xx_inl(p)
-
-#define insb(p, v, l)                   __ixp4xx_insb(p, v, l)
-#define insw(p, v, l)                   __ixp4xx_insw(p, v, l)
-#define insl(p, v, l)                   __ixp4xx_insl(p, v, l)
-
-
-static inline void 
-__ixp4xx_outb(u8 value, u32 addr)
+static inline void outb(u8 value, u32 addr)
 {
         u32 n, byte_enables, data;
         n = addr % 4;
@@ -277,15 +258,13 @@ __ixp4xx_outb(u8 value, u32 addr)
         ixp4xx_pci_write(addr, byte_enables | NP_CMD_IOWRITE, data);
 }
 
-static inline void 
-__ixp4xx_outsb(u32 io_addr, const u8 *vaddr, u32 count)
+static inline void outsb(u32 io_addr, const u8 *vaddr, u32 count)
 {
         while (count--)
                 outb(*vaddr++, io_addr);
 }
 
-static inline void 
-__ixp4xx_outw(u16 value, u32 addr)
+static inline void outw(u16 value, u32 addr)
 {
         u32 n, byte_enables, data;
         n = addr % 4;
@@ -294,28 +273,24 @@ __ixp4xx_outw(u16 value, u32 addr)
         ixp4xx_pci_write(addr, byte_enables | NP_CMD_IOWRITE, data);
 }
 
-static inline void 
-__ixp4xx_outsw(u32 io_addr, const u16 *vaddr, u32 count)
+static inline void outsw(u32 io_addr, const u16 *vaddr, u32 count)
 {
         while (count--)
                 outw(cpu_to_le16(*vaddr++), io_addr);
 }
 
-static inline void 
-__ixp4xx_outl(u32 value, u32 addr)
+static inline void outl(u32 value, u32 addr)
 {
         ixp4xx_pci_write(addr, NP_CMD_IOWRITE, value);
 }
 
-static inline void 
-__ixp4xx_outsl(u32 io_addr, const u32 *vaddr, u32 count)
+static inline void outsl(u32 io_addr, const u32 *vaddr, u32 count)
 {
         while (count--)
-                outl(*vaddr++, io_addr);
+                outl(cpu_to_le32(*vaddr++), io_addr);
 }
 
-static inline u8 
-__ixp4xx_inb(u32 addr)
+static inline u8 inb(u32 addr)
 {
         u32 n, byte_enables, data;
         n = addr % 4;
@@ -326,15 +301,13 @@ __ixp4xx_inb(u32 addr)
         return data >> (8*n);
 }
 
-static inline void 
-__ixp4xx_insb(u32 io_addr, u8 *vaddr, u32 count)
+static inline void insb(u32 io_addr, u8 *vaddr, u32 count)
 {
         while (count--)
                 *vaddr++ = inb(io_addr);
 }
 
-static inline u16 
-__ixp4xx_inw(u32 addr)
+static inline u16 inw(u32 addr)
 {
         u32 n, byte_enables, data;
         n = addr % 4;
@@ -345,15 +318,13 @@ __ixp4xx_inw(u32 addr)
         return data>>(8*n);
 }
 
-static inline void 
-__ixp4xx_insw(u32 io_addr, u16 *vaddr, u32 count)
+static inline void insw(u32 io_addr, u16 *vaddr, u32 count)
 {
         while (count--)
                 *vaddr++ = le16_to_cpu(inw(io_addr));
 }
 
-static inline u32 
-__ixp4xx_inl(u32 addr)
+static inline u32 inl(u32 addr)
 {
         u32 data;
         if (ixp4xx_pci_read(addr, NP_CMD_IOREAD, &data))
@@ -362,11 +333,10 @@ __ixp4xx_inl(u32 addr)
         return data;
 }
 
-static inline void 
-__ixp4xx_insl(u32 io_addr, u32 *vaddr, u32 count)
+static inline void insl(u32 io_addr, u32 *vaddr, u32 count)
 {
         while (count--)
-                *vaddr++ = inl(io_addr);
+                *vaddr++ = le32_to_cpu(inl(io_addr));
 }
 
 #define PIO_OFFSET      0x10000UL
@@ -374,194 +344,183 @@ __ixp4xx_insl(u32 io_addr, u32 *vaddr, u32 count)
 
 #define __is_io_address(p)      (((unsigned long)p >= PIO_OFFSET) && \
                                         ((unsigned long)p <= (PIO_MASK + PIO_OFFSET)))
-static inline unsigned int
-__ixp4xx_ioread8(const void __iomem *addr)
+
+#define ioread8(p)                      ioread8(p)
+static inline unsigned int ioread8(const void __iomem *addr)
 {
         unsigned long port = (unsigned long __force)addr;
         if (__is_io_address(port))
-                return  (unsigned int)__ixp4xx_inb(port & PIO_MASK);
+                return (unsigned int)inb(port & PIO_MASK);
         else
 #ifndef CONFIG_IXP4XX_INDIRECT_PCI
                 return (unsigned int)__raw_readb(port);
 #else
-                return (unsigned int)__ixp4xx_readb(addr);
+                return (unsigned int)__indirect_readb(addr);
 #endif
 }
 
-static inline void
-__ixp4xx_ioread8_rep(const void __iomem *addr, void *vaddr, u32 count)
+#define ioread8_rep(p, v, c)            ioread8_rep(p, v, c)
+static inline void ioread8_rep(const void __iomem *addr, void *vaddr, u32 count)
 {
         unsigned long port = (unsigned long __force)addr;
         if (__is_io_address(port))
-                __ixp4xx_insb(port & PIO_MASK, vaddr, count);
+                insb(port & PIO_MASK, vaddr, count);
         else
 #ifndef CONFIG_IXP4XX_INDIRECT_PCI
                 __raw_readsb(addr, vaddr, count);
 #else
-                __ixp4xx_readsb(addr, vaddr, count);
+                __indirect_readsb(addr, vaddr, count);
 #endif
 }
 
-static inline unsigned int
-__ixp4xx_ioread16(const void __iomem *addr)
+#define ioread16(p)                     ioread16(p)
+static inline unsigned int ioread16(const void __iomem *addr)
 {
         unsigned long port = (unsigned long __force)addr;
         if (__is_io_address(port))
-                return  (unsigned int)__ixp4xx_inw(port & PIO_MASK);
+                return  (unsigned int)inw(port & PIO_MASK);
         else
 #ifndef CONFIG_IXP4XX_INDIRECT_PCI
                 return le16_to_cpu(__raw_readw((u32)port));
 #else
-                return (unsigned int)__ixp4xx_readw(addr);
+                return (unsigned int)__indirect_readw(addr);
 #endif
 }
 
-static inline void
-__ixp4xx_ioread16_rep(const void __iomem *addr, void *vaddr, u32 count)
+#define ioread16_rep(p, v, c)           ioread16_rep(p, v, c)
+static inline void ioread16_rep(const void __iomem *addr, void *vaddr,
+                                u32 count)
 {
         unsigned long port = (unsigned long __force)addr;
         if (__is_io_address(port))
-                __ixp4xx_insw(port & PIO_MASK, vaddr, count);
+                insw(port & PIO_MASK, vaddr, count);
         else
 #ifndef CONFIG_IXP4XX_INDIRECT_PCI
                 __raw_readsw(addr, vaddr, count);
 #else
-                __ixp4xx_readsw(addr, vaddr, count);
+                __indirect_readsw(addr, vaddr, count);
 #endif
 }
 
-static inline unsigned int
-__ixp4xx_ioread32(const void __iomem *addr)
+#define ioread32(p)                     ioread32(p)
+static inline unsigned int ioread32(const void __iomem *addr)
 {
         unsigned long port = (unsigned long __force)addr;
         if (__is_io_address(port))
-                return  (unsigned int)__ixp4xx_inl(port & PIO_MASK);
+                return  (unsigned int)inl(port & PIO_MASK);
         else {
 #ifndef CONFIG_IXP4XX_INDIRECT_PCI
                 return le32_to_cpu((__force __le32)__raw_readl(addr));
 #else
-                return (unsigned int)__ixp4xx_readl(addr);
+                return (unsigned int)__indirect_readl(addr);
 #endif
         }
 }
 
-static inline void
-__ixp4xx_ioread32_rep(const void __iomem *addr, void *vaddr, u32 count)
+#define ioread32_rep(p, v, c)           ioread32_rep(p, v, c)
+static inline void ioread32_rep(const void __iomem *addr, void *vaddr,
+                                u32 count)
 {
         unsigned long port = (unsigned long __force)addr;
         if (__is_io_address(port))
-                __ixp4xx_insl(port & PIO_MASK, vaddr, count);
+                insl(port & PIO_MASK, vaddr, count);
         else
 #ifndef CONFIG_IXP4XX_INDIRECT_PCI
                 __raw_readsl(addr, vaddr, count);
 #else
-                __ixp4xx_readsl(addr, vaddr, count);
+                __indirect_readsl(addr, vaddr, count);
 #endif
 }
 
-static inline void
-__ixp4xx_iowrite8(u8 value, void __iomem *addr)
+#define iowrite8(v, p)                  iowrite8(v, p)
+static inline void iowrite8(u8 value, void __iomem *addr)
 {
         unsigned long port = (unsigned long __force)addr;
         if (__is_io_address(port))
-                __ixp4xx_outb(value, port & PIO_MASK);
+                outb(value, port & PIO_MASK);
         else
 #ifndef CONFIG_IXP4XX_INDIRECT_PCI
                 __raw_writeb(value, port);
 #else
-                __ixp4xx_writeb(value, addr);
+                __indirect_writeb(value, addr);
 #endif
 }
 
-static inline void
-__ixp4xx_iowrite8_rep(void __iomem *addr, const void *vaddr, u32 count)
+#define iowrite8_rep(p, v, c)           iowrite8_rep(p, v, c)
+static inline void iowrite8_rep(void __iomem *addr, const void *vaddr,
+                                u32 count)
 {
         unsigned long port = (unsigned long __force)addr;
         if (__is_io_address(port))
-                __ixp4xx_outsb(port & PIO_MASK, vaddr, count);
+                outsb(port & PIO_MASK, vaddr, count);
         else
 #ifndef CONFIG_IXP4XX_INDIRECT_PCI
                 __raw_writesb(addr, vaddr, count);
 #else
-                __ixp4xx_writesb(addr, vaddr, count);
+                __indirect_writesb(addr, vaddr, count);
 #endif
 }
 
-static inline void
-__ixp4xx_iowrite16(u16 value, void __iomem *addr)
+#define iowrite16(v, p)                 iowrite16(v, p)
+static inline void iowrite16(u16 value, void __iomem *addr)
 {
         unsigned long port = (unsigned long __force)addr;
         if (__is_io_address(port))
-                __ixp4xx_outw(value, port & PIO_MASK);
+                outw(value, port & PIO_MASK);
         else
 #ifndef CONFIG_IXP4XX_INDIRECT_PCI
                 __raw_writew(cpu_to_le16(value), addr);
 #else
-                __ixp4xx_writew(value, addr);
+                __indirect_writew(value, addr);
 #endif
 }
 
-static inline void
-__ixp4xx_iowrite16_rep(void __iomem *addr, const void *vaddr, u32 count)
+#define iowrite16_rep(p, v, c)          iowrite16_rep(p, v, c)
+static inline void iowrite16_rep(void __iomem *addr, const void *vaddr,
+                                 u32 count)
 {
         unsigned long port = (unsigned long __force)addr;
         if (__is_io_address(port))
-                __ixp4xx_outsw(port & PIO_MASK, vaddr, count);
+                outsw(port & PIO_MASK, vaddr, count);
         else
 #ifndef CONFIG_IXP4XX_INDIRECT_PCI
                 __raw_writesw(addr, vaddr, count);
 #else
-                __ixp4xx_writesw(addr, vaddr, count);
+                __indirect_writesw(addr, vaddr, count);
 #endif
 }
 
-static inline void
-__ixp4xx_iowrite32(u32 value, void __iomem *addr)
+#define iowrite32(v, p)                 iowrite32(v, p)
+static inline void iowrite32(u32 value, void __iomem *addr)
 {
         unsigned long port = (unsigned long __force)addr;
         if (__is_io_address(port))
-                __ixp4xx_outl(value, port & PIO_MASK);
+                outl(value, port & PIO_MASK);
         else
 #ifndef CONFIG_IXP4XX_INDIRECT_PCI
                 __raw_writel((u32 __force)cpu_to_le32(value), addr);
 #else
-                __ixp4xx_writel(value, addr);
+                __indirect_writel(value, addr);
 #endif
 }
 
-static inline void
-__ixp4xx_iowrite32_rep(void __iomem *addr, const void *vaddr, u32 count)
+#define iowrite32_rep(p, v, c)          iowrite32_rep(p, v, c)
+static inline void iowrite32_rep(void __iomem *addr, const void *vaddr,
+                                 u32 count)
 {
         unsigned long port = (unsigned long __force)addr;
         if (__is_io_address(port))
-                __ixp4xx_outsl(port & PIO_MASK, vaddr, count);
+                outsl(port & PIO_MASK, vaddr, count);
         else
 #ifndef CONFIG_IXP4XX_INDIRECT_PCI
                 __raw_writesl(addr, vaddr, count);
 #else
-                __ixp4xx_writesl(addr, vaddr, count);
+                __indirect_writesl(addr, vaddr, count);
 #endif
 }
 
-#define ioread8(p)                      __ixp4xx_ioread8(p)
-#define ioread16(p)                     __ixp4xx_ioread16(p)
-#define ioread32(p)                     __ixp4xx_ioread32(p)
-
-#define ioread8_rep(p, v, c)            __ixp4xx_ioread8_rep(p, v, c)
-#define ioread16_rep(p, v, c)           __ixp4xx_ioread16_rep(p, v, c)
-#define ioread32_rep(p, v, c)           __ixp4xx_ioread32_rep(p, v, c)
-
-#define iowrite8(v,p)                   __ixp4xx_iowrite8(v,p)
-#define iowrite16(v,p)                  __ixp4xx_iowrite16(v,p)
-#define iowrite32(v,p)                  __ixp4xx_iowrite32(v,p)
-
-#define iowrite8_rep(p, v, c)           __ixp4xx_iowrite8_rep(p, v, c)
-#define iowrite16_rep(p, v, c)          __ixp4xx_iowrite16_rep(p, v, c)
-#define iowrite32_rep(p, v, c)          __ixp4xx_iowrite32_rep(p, v, c)
-
 #define ioport_map(port, nr)            ((void __iomem*)(port + PIO_OFFSET))
 #define ioport_unmap(addr)
-#endif  // !CONFIG_PCI
-
-#endif  //  __ASM_ARM_ARCH_IO_H
+#endif /* CONFIG_PCI */
 
+#endif /* __ASM_ARM_ARCH_IO_H */
diff --git a/arch/arm/mach-ixp4xx/include/mach/irqs.h b/arch/arm/mach-ixp4xx/include/mach/irqs.h
index f4d74de1566a..7e6d4cce7c27 100644
--- a/arch/arm/mach-ixp4xx/include/mach/irqs.h
+++ b/arch/arm/mach-ixp4xx/include/mach/irqs.h
@@ -15,7 +15,6 @@
 #ifndef _ARCH_IXP4XX_IRQS_H_
 #define _ARCH_IXP4XX_IRQS_H_
 
-
 #define IRQ_IXP4XX_NPEA         0
 #define IRQ_IXP4XX_NPEB         1
 #define IRQ_IXP4XX_NPEC         2
@@ -59,6 +58,9 @@
 #define IRQ_IXP4XX_MCU_ECC      61
 #define IRQ_IXP4XX_EXP_PE       62
 
+#define _IXP4XX_GPIO_IRQ(n)     (IRQ_IXP4XX_GPIO ## n)
+#define IXP4XX_GPIO_IRQ(n)      _IXP4XX_GPIO_IRQ(n)
+
 /*
  * Only first 32 sources are valid if running on IXP42x systems
  */
@@ -70,69 +72,4 @@
 
 #define XSCALE_PMU_IRQ          (IRQ_IXP4XX_XSCALE_PMU)
 
-/*
- * IXDP425 board IRQs
- */
-#define IRQ_IXDP425_PCI_INTA    IRQ_IXP4XX_GPIO11
-#define IRQ_IXDP425_PCI_INTB    IRQ_IXP4XX_GPIO10
-#define IRQ_IXDP425_PCI_INTC    IRQ_IXP4XX_GPIO9
-#define IRQ_IXDP425_PCI_INTD    IRQ_IXP4XX_GPIO8
-
-/*
- * Gateworks Avila board IRQs
- */
-#define IRQ_AVILA_PCI_INTA      IRQ_IXP4XX_GPIO11
-#define IRQ_AVILA_PCI_INTB      IRQ_IXP4XX_GPIO10
-#define IRQ_AVILA_PCI_INTC      IRQ_IXP4XX_GPIO9
-#define IRQ_AVILA_PCI_INTD      IRQ_IXP4XX_GPIO8
-
-
-/*
- * PrPMC1100 Board IRQs
- */
-#define IRQ_PRPMC1100_PCI_INTA  IRQ_IXP4XX_GPIO11
-#define IRQ_PRPMC1100_PCI_INTB  IRQ_IXP4XX_GPIO10
-#define IRQ_PRPMC1100_PCI_INTC  IRQ_IXP4XX_GPIO9
-#define IRQ_PRPMC1100_PCI_INTD  IRQ_IXP4XX_GPIO8
-
-/*
- * ADI Coyote Board IRQs
- */
-#define IRQ_COYOTE_PCI_SLOT0    IRQ_IXP4XX_GPIO6
-#define IRQ_COYOTE_PCI_SLOT1    IRQ_IXP4XX_GPIO11
-#define IRQ_COYOTE_IDE          IRQ_IXP4XX_GPIO5
-
-/*
- * NSLU2 board IRQs
- */
-#define        IRQ_NSLU2_PCI_INTA      IRQ_IXP4XX_GPIO11
-#define        IRQ_NSLU2_PCI_INTB      IRQ_IXP4XX_GPIO10
-#define        IRQ_NSLU2_PCI_INTC      IRQ_IXP4XX_GPIO9
-
-/*
- * NAS100D board IRQs
- */
-#define        IRQ_NAS100D_PCI_INTA    IRQ_IXP4XX_GPIO11
-#define        IRQ_NAS100D_PCI_INTB    IRQ_IXP4XX_GPIO10
-#define        IRQ_NAS100D_PCI_INTC    IRQ_IXP4XX_GPIO9
-#define        IRQ_NAS100D_PCI_INTD    IRQ_IXP4XX_GPIO8
-#define        IRQ_NAS100D_PCI_INTE    IRQ_IXP4XX_GPIO7
-
-/*
- * D-Link DSM-G600 RevA board IRQs
- */
-#define        IRQ_DSMG600_PCI_INTA    IRQ_IXP4XX_GPIO11
-#define        IRQ_DSMG600_PCI_INTB    IRQ_IXP4XX_GPIO10
-#define        IRQ_DSMG600_PCI_INTC    IRQ_IXP4XX_GPIO9
-#define        IRQ_DSMG600_PCI_INTD    IRQ_IXP4XX_GPIO8
-#define        IRQ_DSMG600_PCI_INTE    IRQ_IXP4XX_GPIO7
-#define        IRQ_DSMG600_PCI_INTF    IRQ_IXP4XX_GPIO6
-
-/*
- * Freecom FSG-3 Board IRQs
- */
-#define        IRQ_FSG_PCI_INTA        IRQ_IXP4XX_GPIO6
-#define        IRQ_FSG_PCI_INTB        IRQ_IXP4XX_GPIO7
-#define        IRQ_FSG_PCI_INTC        IRQ_IXP4XX_GPIO5
-
 #endif
diff --git a/arch/arm/mach-ixp4xx/include/mach/ixdp425.h b/arch/arm/mach-ixp4xx/include/mach/ixdp425.h
deleted file mode 100644
index 2cafe65ebfee..000000000000
--- a/arch/arm/mach-ixp4xx/include/mach/ixdp425.h
+++ /dev/null
@@ -1,39 +0,0 @@
-/*
- * arch/arm/mach-ixp4xx/include/mach/ixdp425.h
- *
- * IXDP425 platform specific definitions
- *
- * Author: Deepak Saxena <dsaxena@plexity.net>
- *
- * Copyright 2004 (c) MontaVista, Software, Inc. 
- * 
- * This file is licensed under  the terms of the GNU General Public 
- * License version 2. This program is licensed "as is" without any 
- * warranty of any kind, whether express or implied.
- */
-
-#ifndef __ASM_ARCH_HARDWARE_H__
-#error "Do not include this directly, instead #include <mach/hardware.h>"
-#endif
-
-#define IXDP425_SDA_PIN         7
-#define IXDP425_SCL_PIN         6
-
-/*
- * IXDP425 PCI IRQs
- */
-#define IXDP425_PCI_MAX_DEV     4
-#define IXDP425_PCI_IRQ_LINES   4
-
-
-/* PCI controller GPIO to IRQ pin mappings */
-#define IXDP425_PCI_INTA_PIN    11
-#define IXDP425_PCI_INTB_PIN    10
-#define IXDP425_PCI_INTC_PIN    9
-#define IXDP425_PCI_INTD_PIN    8
-
-/* NAND Flash pins */
-#define IXDP425_NAND_NCE_PIN    12
-
-#define IXDP425_NAND_CMD_BYTE   0x01
-#define IXDP425_NAND_ADDR_BYTE  0x02
diff --git a/arch/arm/mach-ixp4xx/include/mach/nas100d.h b/arch/arm/mach-ixp4xx/include/mach/nas100d.h
deleted file mode 100644
index 3771d62a9748..000000000000
--- a/arch/arm/mach-ixp4xx/include/mach/nas100d.h
+++ /dev/null
@@ -1,52 +0,0 @@
-/*
- * arch/arm/mach-ixp4xx/include/mach/nas100d.h
- *
- * NAS100D platform specific definitions
- *
- * Copyright (c) 2005 Tower Technologies
- *
- * Author: Alessandro Zummo <a.zummo@towertech.it>
- *
- * based on ixdp425.h:
- *      Copyright 2004 (c) MontaVista, Software, Inc.
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#ifndef __ASM_ARCH_HARDWARE_H__
-#error "Do not include this directly, instead #include <mach/hardware.h>"
-#endif
-
-#define NAS100D_SDA_PIN         5
-#define NAS100D_SCL_PIN         6
-
-/*
- * NAS100D PCI IRQs
- */
-#define NAS100D_PCI_MAX_DEV     3
-#define NAS100D_PCI_IRQ_LINES   3
-
-
-/* PCI controller GPIO to IRQ pin mappings */
-#define NAS100D_PCI_INTA_PIN    11
-#define NAS100D_PCI_INTB_PIN    10
-#define NAS100D_PCI_INTC_PIN    9
-#define NAS100D_PCI_INTD_PIN    8
-#define NAS100D_PCI_INTE_PIN    7
-
-/* Buttons */
-
-#define NAS100D_PB_GPIO         14   /* power button */
-#define NAS100D_RB_GPIO         4    /* reset button */
-
-/* Power control */
-
-#define NAS100D_PO_GPIO         12   /* power off */
-
-/* LEDs */
-
-#define NAS100D_LED_WLAN_GPIO   0
-#define NAS100D_LED_DISK_GPIO   3
-#define NAS100D_LED_PWR_GPIO    15
diff --git a/arch/arm/mach-ixp4xx/include/mach/npe.h b/arch/arm/mach-ixp4xx/include/mach/npe.h
index 37d0511689dc..e320db2457ae 100644
--- a/arch/arm/mach-ixp4xx/include/mach/npe.h
+++ b/arch/arm/mach-ixp4xx/include/mach/npe.h
@@ -33,7 +33,7 @@ int npe_send_message(struct npe *npe, const void *msg, const char *what);
 int npe_recv_message(struct npe *npe, void *msg, const char *what);
 int npe_send_recv_message(struct npe *npe, void *msg, const char *what);
 int npe_load_firmware(struct npe *npe, const char *name, struct device *dev);
-struct npe *npe_request(int id);
+struct npe *npe_request(unsigned id);
 void npe_release(struct npe *npe);
 
 #endif /* __IXP4XX_NPE_H */
diff --git a/arch/arm/mach-ixp4xx/include/mach/nslu2.h b/arch/arm/mach-ixp4xx/include/mach/nslu2.h
deleted file mode 100644
index 85d00adbfb92..000000000000
--- a/arch/arm/mach-ixp4xx/include/mach/nslu2.h
+++ /dev/null
@@ -1,55 +0,0 @@
-/*
- * arch/arm/mach-ixp4xx/include/mach/nslu2.h
- *
- * NSLU2 platform specific definitions
- *
- * Author: Mark Rakes <mrakes AT mac.com>
- * Maintainers: http://www.nslu2-linux.org
- *
- * based on ixdp425.h:
- *      Copyright 2004 (c) MontaVista, Software, Inc.
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#ifndef __ASM_ARCH_HARDWARE_H__
-#error "Do not include this directly, instead #include <mach/hardware.h>"
-#endif
-
-#define NSLU2_SDA_PIN           7
-#define NSLU2_SCL_PIN           6
-
-/*
- * NSLU2 PCI IRQs
- */
-#define NSLU2_PCI_MAX_DEV       3
-#define NSLU2_PCI_IRQ_LINES     3
-
-
-/* PCI controller GPIO to IRQ pin mappings */
-#define NSLU2_PCI_INTA_PIN      11
-#define NSLU2_PCI_INTB_PIN      10
-#define NSLU2_PCI_INTC_PIN      9
-#define NSLU2_PCI_INTD_PIN      8
-
-/* NSLU2 Timer */
-#define NSLU2_FREQ 66000000
-
-/* Buttons */
-
-#define NSLU2_PB_GPIO           5       /* power button */
-#define NSLU2_PO_GPIO           8       /* power off */
-#define NSLU2_RB_GPIO           12      /* reset button */
-
-/* Buzzer */
-
-#define NSLU2_GPIO_BUZZ         4
-
-/* LEDs */
-
-#define NSLU2_LED_RED_GPIO      0
-#define NSLU2_LED_GRN_GPIO      1
-#define NSLU2_LED_DISK1_GPIO    3
-#define NSLU2_LED_DISK2_GPIO    2
diff --git a/arch/arm/mach-ixp4xx/include/mach/prpmc1100.h b/arch/arm/mach-ixp4xx/include/mach/prpmc1100.h
deleted file mode 100644
index 17274a2e3dec..000000000000
--- a/arch/arm/mach-ixp4xx/include/mach/prpmc1100.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/*
- * arch/arm/mach-ixp4xx/include/mach/prpmc1100.h
- *
- * Motorolla PrPMC1100 platform specific definitions
- *
- * Author: Deepak Saxena <dsaxena@plexity.net>
- *
- * Copyright 2004 (c) MontaVista, Software, Inc. 
- * 
- * This file is licensed under  the terms of the GNU General Public 
- * License version 2. This program is licensed "as is" without any 
- * warranty of any kind, whether express or implied.
- */
-
-#ifndef __ASM_ARCH_HARDWARE_H__
-#error "Do not include this directly, instead #include <mach/hardware.h>"
-#endif
-
-#define PRPMC1100_FLASH_BASE    IXP4XX_EXP_BUS_CS0_BASE_PHYS
-#define PRPMC1100_FLASH_SIZE    IXP4XX_EXP_BUS_CSX_REGION_SIZE
-
-#define PRPMC1100_PCI_MIN_DEVID 10
-#define PRPMC1100_PCI_MAX_DEVID 16
-#define PRPMC1100_PCI_IRQ_LINES 4
-
-
-/* PCI controller GPIO to IRQ pin mappings */
-#define PRPMC1100_PCI_INTA_PIN  11
-#define PRPMC1100_PCI_INTB_PIN  10
-#define PRPMC1100_PCI_INTC_PIN  9
-#define PRPMC1100_PCI_INTD_PIN  8
-
-
diff --git a/arch/arm/mach-ixp4xx/include/mach/timex.h b/arch/arm/mach-ixp4xx/include/mach/timex.h
index 89ce3ee84698..2c3f93c3eb79 100644
--- a/arch/arm/mach-ixp4xx/include/mach/timex.h
+++ b/arch/arm/mach-ixp4xx/include/mach/timex.h
@@ -10,6 +10,6 @@
  * 66.66... MHz. We do a convulted calculation of CLOCK_TICK_RATE b/c the
  * timer register ignores the bottom 2 bits of the LATCH value.
  */
-#define FREQ 66666666
+#define FREQ 66666000
 #define CLOCK_TICK_RATE (((FREQ / HZ & ~IXP4XX_OST_RELOAD_MASK) + 1) * HZ)
 
diff --git a/arch/arm/mach-ixp4xx/ixdp425-pci.c b/arch/arm/mach-ixp4xx/ixdp425-pci.c
index 64c29aacaac9..1ba165a6edac 100644
--- a/arch/arm/mach-ixp4xx/ixdp425-pci.c
+++ b/arch/arm/mach-ixp4xx/ixdp425-pci.c
@@ -1,5 +1,5 @@
 /*
- * arch/arm/mach-ixp4xx/ixdp425-pci.c 
+ * arch/arm/mach-ixp4xx/ixdp425-pci.c
  *
  * IXDP425 board-level PCI initialization
  *
@@ -19,39 +19,43 @@
 #include <linux/init.h>
 #include <linux/irq.h>
 #include <linux/delay.h>
-
 #include <asm/mach/pci.h>
 #include <asm/irq.h>
 #include <mach/hardware.h>
 #include <asm/mach-types.h>
 
+#define MAX_DEV         4
+#define IRQ_LINES       4
+
+/* PCI controller GPIO to IRQ pin mappings */
+#define INTA            11
+#define INTB            10
+#define INTC            9
+#define INTD            8
+
+
 void __init ixdp425_pci_preinit(void)
 {
-        set_irq_type(IRQ_IXDP425_PCI_INTA, IRQ_TYPE_LEVEL_LOW);
-        set_irq_type(IRQ_IXDP425_PCI_INTB, IRQ_TYPE_LEVEL_LOW);
-        set_irq_type(IRQ_IXDP425_PCI_INTC, IRQ_TYPE_LEVEL_LOW);
-        set_irq_type(IRQ_IXDP425_PCI_INTD, IRQ_TYPE_LEVEL_LOW);
-
+        set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW);
+        set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW);
+        set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW);
+        set_irq_type(IXP4XX_GPIO_IRQ(INTD), IRQ_TYPE_LEVEL_LOW);
         ixp4xx_pci_preinit();
 }
 
 static int __init ixdp425_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
 {
-        static int pci_irq_table[IXDP425_PCI_IRQ_LINES] = {
-                IRQ_IXDP425_PCI_INTA,
-                IRQ_IXDP425_PCI_INTB,
-                IRQ_IXDP425_PCI_INTC,
-                IRQ_IXDP425_PCI_INTD
+        static int pci_irq_table[IRQ_LINES] = {
+                IXP4XX_GPIO_IRQ(INTA),
+                IXP4XX_GPIO_IRQ(INTB),
+                IXP4XX_GPIO_IRQ(INTC),
+                IXP4XX_GPIO_IRQ(INTD)
         };
 
-        int irq = -1;
-
-        if (slot >= 1 && slot <= IXDP425_PCI_MAX_DEV && 
-                pin >= 1 && pin <= IXDP425_PCI_IRQ_LINES) {
-                irq = pci_irq_table[(slot + pin - 2) % 4];
-        }
+        if (slot >= 1 && slot <= MAX_DEV && pin >= 1 && pin <= IRQ_LINES)
+                return pci_irq_table[(slot + pin - 2) % 4];
 
-        return irq;
+        return -1;
 }
 
 struct hw_pci ixdp425_pci __initdata = {
@@ -72,4 +76,3 @@ int __init ixdp425_pci_init(void)
 }
 
 subsys_initcall(ixdp425_pci_init);
-
diff --git a/arch/arm/mach-ixp4xx/ixdp425-setup.c b/arch/arm/mach-ixp4xx/ixdp425-setup.c
index f4a0c1bc1331..bbb768988845 100644
--- a/arch/arm/mach-ixp4xx/ixdp425-setup.c
+++ b/arch/arm/mach-ixp4xx/ixdp425-setup.c
@@ -1,7 +1,7 @@
 /*
  * arch/arm/mach-ixp4xx/ixdp425-setup.c
  *
- * IXDP425/IXCDP1100 board-setup 
+ * IXDP425/IXCDP1100 board-setup
  *
  * Copyright (C) 2003-2005 MontaVista Software, Inc.
  *
@@ -21,7 +21,6 @@
 #include <linux/mtd/nand.h>
 #include <linux/mtd/partitions.h>
 #include <linux/delay.h>
-
 #include <asm/types.h>
 #include <asm/setup.h>
 #include <asm/memory.h>
@@ -31,6 +30,15 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/flash.h>
 
+#define IXDP425_SDA_PIN         7
+#define IXDP425_SCL_PIN         6
+
+/* NAND Flash pins */
+#define IXDP425_NAND_NCE_PIN    12
+
+#define IXDP425_NAND_CMD_BYTE   0x01
+#define IXDP425_NAND_ADDR_BYTE  0x02
+
 static struct flash_platform_data ixdp425_flash_data = {
         .map_name       = "cfi_probe",
         .width          = 2,
diff --git a/arch/arm/mach-ixp4xx/ixp4xx_npe.c b/arch/arm/mach-ixp4xx/ixp4xx_npe.c
index 47ac69c7ec78..e8bb25778166 100644
--- a/arch/arm/mach-ixp4xx/ixp4xx_npe.c
+++ b/arch/arm/mach-ixp4xx/ixp4xx_npe.c
@@ -665,7 +665,7 @@ err:
 }
 
 
-struct npe *npe_request(int id)
+struct npe *npe_request(unsigned id)
 {
         if (id < NPE_COUNT)
                 if (npe_tab[id].valid)
diff --git a/arch/arm/mach-ixp4xx/nas100d-pci.c b/arch/arm/mach-ixp4xx/nas100d-pci.c
index 1088426fdcee..d0cea34cf61e 100644
--- a/arch/arm/mach-ixp4xx/nas100d-pci.c
+++ b/arch/arm/mach-ixp4xx/nas100d-pci.c
@@ -18,37 +18,42 @@
 #include <linux/pci.h>
 #include <linux/init.h>
 #include <linux/irq.h>
-
 #include <asm/mach/pci.h>
 #include <asm/mach-types.h>
 
+#define MAX_DEV         3
+#define IRQ_LINES       3
+
+/* PCI controller GPIO to IRQ pin mappings */
+#define INTA            11
+#define INTB            10
+#define INTC            9
+#define INTD            8
+#define INTE            7
+
 void __init nas100d_pci_preinit(void)
 {
-        set_irq_type(IRQ_NAS100D_PCI_INTA, IRQ_TYPE_LEVEL_LOW);
-        set_irq_type(IRQ_NAS100D_PCI_INTB, IRQ_TYPE_LEVEL_LOW);
-        set_irq_type(IRQ_NAS100D_PCI_INTC, IRQ_TYPE_LEVEL_LOW);
-        set_irq_type(IRQ_NAS100D_PCI_INTD, IRQ_TYPE_LEVEL_LOW);
-        set_irq_type(IRQ_NAS100D_PCI_INTE, IRQ_TYPE_LEVEL_LOW);
-
+        set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW);
+        set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW);
+        set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW);
+        set_irq_type(IXP4XX_GPIO_IRQ(INTD), IRQ_TYPE_LEVEL_LOW);
+        set_irq_type(IXP4XX_GPIO_IRQ(INTE), IRQ_TYPE_LEVEL_LOW);
         ixp4xx_pci_preinit();
 }
 
 static int __init nas100d_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
 {
-        static int pci_irq_table[NAS100D_PCI_MAX_DEV][NAS100D_PCI_IRQ_LINES] =
-        {
-                { IRQ_NAS100D_PCI_INTA, -1, -1 },
-                { IRQ_NAS100D_PCI_INTB, -1, -1 },
-                { IRQ_NAS100D_PCI_INTC, IRQ_NAS100D_PCI_INTD, IRQ_NAS100D_PCI_INTE },
+        static int pci_irq_table[MAX_DEV][IRQ_LINES] = {
+                { IXP4XX_GPIO_IRQ(INTA), -1, -1 },
+                { IXP4XX_GPIO_IRQ(INTB), -1, -1 },
+                { IXP4XX_GPIO_IRQ(INTC), IXP4XX_GPIO_IRQ(INTD),
+                  IXP4XX_GPIO_IRQ(INTE) },
         };
 
-        int irq = -1;
-
-        if (slot >= 1 && slot <= NAS100D_PCI_MAX_DEV &&
-                pin >= 1 && pin <= NAS100D_PCI_IRQ_LINES)
-                irq = pci_irq_table[slot-1][pin-1];
+        if (slot >= 1 && slot <= MAX_DEV && pin >= 1 && pin <= IRQ_LINES)
+                return pci_irq_table[slot - 1][pin - 1];
 
-        return irq;
+        return -1;
 }
 
 struct hw_pci __initdata nas100d_pci = {
diff --git a/arch/arm/mach-ixp4xx/nas100d-setup.c b/arch/arm/mach-ixp4xx/nas100d-setup.c
index 921c947b5b6b..e3ee880aa1e6 100644
--- a/arch/arm/mach-ixp4xx/nas100d-setup.c
+++ b/arch/arm/mach-ixp4xx/nas100d-setup.c
@@ -29,12 +29,26 @@
 #include <linux/i2c.h>
 #include <linux/i2c-gpio.h>
 #include <linux/io.h>
-
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/flash.h>
 #include <asm/gpio.h>
 
+#define NAS100D_SDA_PIN         5
+#define NAS100D_SCL_PIN         6
+
+/* Buttons */
+#define NAS100D_PB_GPIO         14   /* power button */
+#define NAS100D_RB_GPIO         4    /* reset button */
+
+/* Power control */
+#define NAS100D_PO_GPIO         12   /* power off */
+
+/* LEDs */
+#define NAS100D_LED_WLAN_GPIO   0
+#define NAS100D_LED_DISK_GPIO   3
+#define NAS100D_LED_PWR_GPIO    15
+
 static struct flash_platform_data nas100d_flash_data = {
         .map_name               = "cfi_probe",
         .width                  = 2,
diff --git a/arch/arm/mach-ixp4xx/nslu2-pci.c b/arch/arm/mach-ixp4xx/nslu2-pci.c
index 4429b8448b61..1eb5a90470bc 100644
--- a/arch/arm/mach-ixp4xx/nslu2-pci.c
+++ b/arch/arm/mach-ixp4xx/nslu2-pci.c
@@ -18,35 +18,38 @@
 #include <linux/pci.h>
 #include <linux/init.h>
 #include <linux/irq.h>
-
 #include <asm/mach/pci.h>
 #include <asm/mach-types.h>
 
+#define MAX_DEV         3
+#define IRQ_LINES       3
+
+/* PCI controller GPIO to IRQ pin mappings */
+#define INTA            11
+#define INTB            10
+#define INTC            9
+#define INTD            8
+
 void __init nslu2_pci_preinit(void)
 {
-        set_irq_type(IRQ_NSLU2_PCI_INTA, IRQ_TYPE_LEVEL_LOW);
-        set_irq_type(IRQ_NSLU2_PCI_INTB, IRQ_TYPE_LEVEL_LOW);
-        set_irq_type(IRQ_NSLU2_PCI_INTC, IRQ_TYPE_LEVEL_LOW);
-
+        set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW);
+        set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW);
+        set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW);
         ixp4xx_pci_preinit();
 }
 
 static int __init nslu2_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
 {
-        static int pci_irq_table[NSLU2_PCI_IRQ_LINES] = {
-                IRQ_NSLU2_PCI_INTA,
-                IRQ_NSLU2_PCI_INTB,
-                IRQ_NSLU2_PCI_INTC,
+        static int pci_irq_table[IRQ_LINES] = {
+                IXP4XX_GPIO_IRQ(INTA),
+                IXP4XX_GPIO_IRQ(INTB),
+                IXP4XX_GPIO_IRQ(INTC),
         };
 
-        int irq = -1;
-
-        if (slot >= 1 && slot <= NSLU2_PCI_MAX_DEV &&
-                pin >= 1 && pin <= NSLU2_PCI_IRQ_LINES) {
-                        irq = pci_irq_table[(slot + pin - 2) % NSLU2_PCI_IRQ_LINES];
-        }
+        if (slot >= 1 && slot <= MAX_DEV && pin >= 1 && pin <= IRQ_LINES)
+                return pci_irq_table[(slot + pin - 2) % IRQ_LINES];
 
-        return irq;
+        return -1;
 }
 
 struct hw_pci __initdata nslu2_pci = {
diff --git a/arch/arm/mach-ixp4xx/nslu2-setup.c b/arch/arm/mach-ixp4xx/nslu2-setup.c
index ff6a08d02cc4..c14e0034be4b 100644
--- a/arch/arm/mach-ixp4xx/nslu2-setup.c
+++ b/arch/arm/mach-ixp4xx/nslu2-setup.c
@@ -26,13 +26,32 @@
 #include <linux/i2c.h>
 #include <linux/i2c-gpio.h>
 #include <linux/io.h>
-
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/flash.h>
 #include <asm/mach/time.h>
 #include <asm/gpio.h>
 
+#define NSLU2_SDA_PIN           7
+#define NSLU2_SCL_PIN           6
+
+/* NSLU2 Timer */
+#define NSLU2_FREQ 66000000
+
+/* Buttons */
+#define NSLU2_PB_GPIO           5       /* power button */
+#define NSLU2_PO_GPIO           8       /* power off */
+#define NSLU2_RB_GPIO           12      /* reset button */
+
+/* Buzzer */
+#define NSLU2_GPIO_BUZZ         4
+
+/* LEDs */
+#define NSLU2_LED_RED_GPIO      0
+#define NSLU2_LED_GRN_GPIO      1
+#define NSLU2_LED_DISK1_GPIO    3
+#define NSLU2_LED_DISK2_GPIO    2
+
 static struct flash_platform_data nslu2_flash_data = {
         .map_name               = "cfi_probe",
         .width                  = 2,
diff --git a/arch/arm/mach-kirkwood/Kconfig b/arch/arm/mach-kirkwood/Kconfig
index 8bf09ae5b347..f6c6196a51fa 100644
--- a/arch/arm/mach-kirkwood/Kconfig
+++ b/arch/arm/mach-kirkwood/Kconfig
@@ -52,6 +52,12 @@ config MACH_OPENRD_BASE
           Say 'Y' here if you want your kernel to support the
           Marvell OpenRD Base Board.
 
+config MACH_NETSPACE_V2
+        bool "LaCie Network Space v2 NAS Board"
+        help
+          Say 'Y' here if you want your kernel to support the
+          LaCie Network Space v2 NAS.
+
 endmenu
 
 endif
diff --git a/arch/arm/mach-kirkwood/Makefile b/arch/arm/mach-kirkwood/Makefile
index 9f2f67b2b63d..d4d7f53b0fb9 100644
--- a/arch/arm/mach-kirkwood/Makefile
+++ b/arch/arm/mach-kirkwood/Makefile
@@ -8,5 +8,6 @@ obj-$(CONFIG_MACH_SHEEVAPLUG)		+= sheevaplug-setup.o
 obj-$(CONFIG_MACH_TS219)                += ts219-setup.o tsx1x-common.o
 obj-$(CONFIG_MACH_TS41X)                += ts41x-setup.o tsx1x-common.o
 obj-$(CONFIG_MACH_OPENRD_BASE)          += openrd_base-setup.o
+obj-$(CONFIG_MACH_NETSPACE_V2)          += netspace_v2-setup.o
 
 obj-$(CONFIG_CPU_IDLE)                  += cpuidle.o
diff --git a/arch/arm/mach-kirkwood/netspace_v2-setup.c b/arch/arm/mach-kirkwood/netspace_v2-setup.c
new file mode 100644
index 000000000000..9a064065bebe
--- /dev/null
+++ b/arch/arm/mach-kirkwood/netspace_v2-setup.c
@@ -0,0 +1,325 @@
+/*
+ * arch/arm/mach-kirkwood/netspace_v2-setup.c
+ *
+ * LaCie Network Space v2 board setup
+ *
+ * Copyright (C) 2009 Simon Guinot <sguinot@lacie.com>
+ * Copyright (C) 2009 Benoît Canet <benoit.canet@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/mtd/physmap.h>
+#include <linux/spi/flash.h>
+#include <linux/spi/spi.h>
+#include <linux/ata_platform.h>
+#include <linux/mv643xx_eth.h>
+#include <linux/i2c.h>
+#include <linux/i2c/at24.h>
+#include <linux/input.h>
+#include <linux/gpio.h>
+#include <linux/gpio_keys.h>
+#include <linux/leds.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/time.h>
+#include <mach/kirkwood.h>
+#include <plat/time.h>
+#include "common.h"
+#include "mpp.h"
+
+/*****************************************************************************
+ * 512KB SPI Flash on Boot Device (MACRONIX MX25L4005)
+ ****************************************************************************/
+
+static struct mtd_partition netspace_v2_flash_parts[] = {
+        {
+                .name = "u-boot",
+                .size = MTDPART_SIZ_FULL,
+                .offset = 0,
+                .mask_flags = MTD_WRITEABLE, /* force read-only */
+        },
+};
+
+static const struct flash_platform_data netspace_v2_flash = {
+        .type           = "mx25l4005a",
+        .name           = "spi_flash",
+        .parts          = netspace_v2_flash_parts,
+        .nr_parts       = ARRAY_SIZE(netspace_v2_flash_parts),
+};
+
+static struct spi_board_info __initdata netspace_v2_spi_slave_info[] = {
+        {
+                .modalias       = "m25p80",
+                .platform_data  = &netspace_v2_flash,
+                .irq            = -1,
+                .max_speed_hz   = 20000000,
+                .bus_num        = 0,
+                .chip_select    = 0,
+        },
+};
+
+/*****************************************************************************
+ * Ethernet
+ ****************************************************************************/
+
+static struct mv643xx_eth_platform_data netspace_v2_ge00_data = {
+        .phy_addr       = MV643XX_ETH_PHY_ADDR(8),
+};
+
+/*****************************************************************************
+ * I2C devices
+ ****************************************************************************/
+
+static struct at24_platform_data at24c04 = {
+        .byte_len       = SZ_4K / 8,
+        .page_size      = 16,
+};
+
+/*
+ * i2c addr | chip         | description
+ * 0x50     | HT24LC04     | eeprom (512B)
+ */
+
+static struct i2c_board_info __initdata netspace_v2_i2c_info[] = {
+        {
+                I2C_BOARD_INFO("24c04", 0x50),
+                .platform_data  = &at24c04,
+        }
+};
+
+/*****************************************************************************
+ * SATA
+ ****************************************************************************/
+
+static struct mv_sata_platform_data netspace_v2_sata_data = {
+        .n_ports        = 2,
+};
+
+#define NETSPACE_V2_GPIO_SATA0_POWER    16
+#define NETSPACE_V2_GPIO_SATA1_POWER    17
+
+static void __init netspace_v2_sata_power_init(void)
+{
+        int err;
+
+        err = gpio_request(NETSPACE_V2_GPIO_SATA0_POWER, "SATA0 power");
+        if (err == 0) {
+                err = gpio_direction_output(NETSPACE_V2_GPIO_SATA0_POWER, 1);
+                if (err)
+                        gpio_free(NETSPACE_V2_GPIO_SATA0_POWER);
+        }
+        if (err)
+                pr_err("netspace_v2: failed to setup SATA0 power\n");
+}
+
+/*****************************************************************************
+ * GPIO keys
+ ****************************************************************************/
+
+#define NETSPACE_V2_PUSH_BUTTON         32
+
+static struct gpio_keys_button netspace_v2_buttons[] = {
+        [0] = {
+                .code           = KEY_POWER,
+                .gpio           = NETSPACE_V2_PUSH_BUTTON,
+                .desc           = "Power push button",
+                .active_low     = 0,
+        },
+};
+
+static struct gpio_keys_platform_data netspace_v2_button_data = {
+        .buttons        = netspace_v2_buttons,
+        .nbuttons       = ARRAY_SIZE(netspace_v2_buttons),
+};
+
+static struct platform_device netspace_v2_gpio_buttons = {
+        .name           = "gpio-keys",
+        .id             = -1,
+        .dev            = {
+                .platform_data  = &netspace_v2_button_data,
+        },
+};
+
+/*****************************************************************************
+ * GPIO LEDs
+ ****************************************************************************/
+
+/*
+ * The blue front LED is wired to a CPLD and can blink in relation with the
+ * SATA activity.
+ *
+ * The following array detail the different LED registers and the combination
+ * of their possible values:
+ *
+ *  cmd_led   |  slow_led  | /SATA active | LED state
+ *            |            |              |
+ *     1      |     0      |      x       |  off
+ *     -      |     1      |      x       |  on
+ *     0      |     0      |      1       |  on
+ *     0      |     0      |      0       |  blink (rate 300ms)
+ */
+
+#define NETSPACE_V2_GPIO_RED_LED        12
+#define NETSPACE_V2_GPIO_BLUE_LED_SLOW  29
+#define NETSPACE_V2_GPIO_BLUE_LED_CMD   30
+
+
+static struct gpio_led netspace_v2_gpio_led_pins[] = {
+        {
+                .name   = "ns_v2:red:fail",
+                .gpio   = NETSPACE_V2_GPIO_RED_LED,
+        },
+};
+
+static struct gpio_led_platform_data netspace_v2_gpio_leds_data = {
+        .num_leds       = ARRAY_SIZE(netspace_v2_gpio_led_pins),
+        .leds           = netspace_v2_gpio_led_pins,
+};
+
+static struct platform_device netspace_v2_gpio_leds = {
+        .name           = "leds-gpio",
+        .id             = -1,
+        .dev            = {
+                .platform_data  = &netspace_v2_gpio_leds_data,
+        },
+};
+
+static void __init netspace_v2_gpio_leds_init(void)
+{
+        platform_device_register(&netspace_v2_gpio_leds);
+
+        /*
+         * Configure the front blue LED to blink in relation with the SATA
+         * activity.
+         */
+        if (gpio_request(NETSPACE_V2_GPIO_BLUE_LED_SLOW,
+                         "SATA blue LED slow") != 0)
+                return;
+        if (gpio_direction_output(NETSPACE_V2_GPIO_BLUE_LED_SLOW, 0) != 0)
+                goto err_free_1;
+        if (gpio_request(NETSPACE_V2_GPIO_BLUE_LED_CMD,
+                         "SATA blue LED command") != 0)
+                goto err_free_1;
+        if (gpio_direction_output(NETSPACE_V2_GPIO_BLUE_LED_CMD, 0) != 0)
+                goto err_free_2;
+
+        return;
+
+err_free_2:
+        gpio_free(NETSPACE_V2_GPIO_BLUE_LED_CMD);
+err_free_1:
+        gpio_free(NETSPACE_V2_GPIO_BLUE_LED_SLOW);
+        pr_err("netspace_v2: failed to configure SATA blue LED\n");
+}
+
+/*****************************************************************************
+ * Timer
+ ****************************************************************************/
+
+static void netspace_v2_timer_init(void)
+{
+        kirkwood_tclk = 166666667;
+        orion_time_init(IRQ_KIRKWOOD_BRIDGE, kirkwood_tclk);
+}
+
+struct sys_timer netspace_v2_timer = {
+        .init = netspace_v2_timer_init,
+};
+
+/*****************************************************************************
+ * General Setup
+ ****************************************************************************/
+
+static unsigned int netspace_v2_mpp_config[] __initdata = {
+        MPP0_SPI_SCn,
+        MPP1_SPI_MOSI,
+        MPP2_SPI_SCK,
+        MPP3_SPI_MISO,
+        MPP4_NF_IO6,
+        MPP5_NF_IO7,
+        MPP6_SYSRST_OUTn,
+        MPP8_TW_SDA,
+        MPP9_TW_SCK,
+        MPP10_UART0_TXD,
+        MPP11_UART0_RXD,
+        MPP12_GPO,              /* Red led */
+        MPP14_GPIO,             /* USB fuse */
+        MPP16_GPIO,             /* SATA 0 power */
+        MPP18_NF_IO0,
+        MPP19_NF_IO1,
+        MPP20_SATA1_ACTn,
+        MPP21_SATA0_ACTn,
+        MPP24_GPIO,             /* USB mode select */
+        MPP25_GPIO,             /* Fan rotation fail */
+        MPP26_GPIO,             /* USB device vbus */
+        MPP28_GPIO,             /* USB enable host vbus */
+        MPP29_GPIO,             /* Blue led (slow register) */
+        MPP30_GPIO,             /* Blue led (command register) */
+        MPP31_GPIO,             /* Board power off */
+        MPP32_GPIO,             /* Power button (0 = Released, 1 = Pushed) */
+        0
+};
+
+#define NETSPACE_V2_GPIO_POWER_OFF      31
+
+static void netspace_v2_power_off(void)
+{
+        gpio_set_value(NETSPACE_V2_GPIO_POWER_OFF, 1);
+}
+
+static void __init netspace_v2_init(void)
+{
+        /*
+         * Basic setup. Needs to be called early.
+         */
+        kirkwood_init();
+        kirkwood_mpp_conf(netspace_v2_mpp_config);
+
+        netspace_v2_sata_power_init();
+
+        kirkwood_ehci_init();
+        kirkwood_ge00_init(&netspace_v2_ge00_data);
+        kirkwood_sata_init(&netspace_v2_sata_data);
+        kirkwood_uart0_init();
+        spi_register_board_info(netspace_v2_spi_slave_info,
+                                ARRAY_SIZE(netspace_v2_spi_slave_info));
+        kirkwood_spi_init();
+        kirkwood_i2c_init();
+        i2c_register_board_info(0, netspace_v2_i2c_info,
+                                ARRAY_SIZE(netspace_v2_i2c_info));
+
+        netspace_v2_gpio_leds_init();
+        platform_device_register(&netspace_v2_gpio_buttons);
+
+        if (gpio_request(NETSPACE_V2_GPIO_POWER_OFF, "power-off") == 0 &&
+            gpio_direction_output(NETSPACE_V2_GPIO_POWER_OFF, 0) == 0)
+                pm_power_off = netspace_v2_power_off;
+        else
+                pr_err("netspace_v2: failed to configure power-off GPIO\n");
+}
+
+MACHINE_START(NETSPACE_V2, "LaCie Network Space v2")
+        .phys_io        = KIRKWOOD_REGS_PHYS_BASE,
+        .io_pg_offst    = ((KIRKWOOD_REGS_VIRT_BASE) >> 18) & 0xfffc,
+        .boot_params    = 0x00000100,
+        .init_machine   = netspace_v2_init,
+        .map_io         = kirkwood_map_io,
+        .init_irq       = kirkwood_init_irq,
+        .timer          = &netspace_v2_timer,
+MACHINE_END
diff --git a/arch/arm/mach-lh7a40x/clocks.c b/arch/arm/mach-lh7a40x/clocks.c
index 6182f5410b4d..fcaf876f19b6 100644
--- a/arch/arm/mach-lh7a40x/clocks.c
+++ b/arch/arm/mach-lh7a40x/clocks.c
@@ -7,8 +7,6 @@
  *  version 2 as published by the Free Software Foundation.
  *
  */
-
-#include <linux/cpufreq.h>
 #include <mach/hardware.h>
 #include <mach/clocks.h>
 #include <linux/err.h>
@@ -31,12 +29,6 @@ struct clk {
 #define HCLKDIV(c)      (((c) >>  0) & 0x02)
 #define PCLKDIV(c)      (((c) >> 16) & 0x03)
 
-unsigned int cpufreq_get (unsigned int cpu) /* in kHz */
-{
-        return fclkfreq_get ()/1000;
-}
-EXPORT_SYMBOL(cpufreq_get);
-
 unsigned int fclkfreq_get (void)
 {
         unsigned int clkset = CSC_CLKSET;
diff --git a/arch/arm/mach-msm/Kconfig b/arch/arm/mach-msm/Kconfig
index d140abca690a..f780086befd7 100644
--- a/arch/arm/mach-msm/Kconfig
+++ b/arch/arm/mach-msm/Kconfig
@@ -3,6 +3,30 @@ if ARCH_MSM
 comment "MSM Board Type"
         depends on ARCH_MSM
 
+config MSM_DEBUG_UART
+        int
+        default 1 if MSM_DEBUG_UART1
+        default 2 if MSM_DEBUG_UART2
+        default 3 if MSM_DEBUG_UART3
+
+choice
+        prompt "Debug UART"
+
+        default MSM_DEBUG_UART_NONE
+
+        config MSM_DEBUG_UART_NONE
+                bool "None"
+
+        config MSM_DEBUG_UART1
+                bool "UART1"
+
+        config MSM_DEBUG_UART2
+                bool "UART2"
+
+        config MSM_DEBUG_UART3
+                bool "UART3"
+endchoice
+
 config MACH_HALIBUT
         depends on ARCH_MSM
         default y
@@ -10,4 +34,10 @@ config MACH_HALIBUT
         help
           Support for the Qualcomm SURF7201A eval board.
 
+config MACH_TROUT
+        default y
+        bool "HTC Dream (aka trout)"
+        help
+          Support for the HTC Dream, T-Mobile G1, Android ADP1 devices.
+
 endif
diff --git a/arch/arm/mach-msm/Makefile b/arch/arm/mach-msm/Makefile
index 1aa47001aa3b..91e6f5c95dc1 100644
--- a/arch/arm/mach-msm/Makefile
+++ b/arch/arm/mach-msm/Makefile
@@ -6,3 +6,4 @@ obj-y += clock.o clock-7x01a.o
 
 obj-$(CONFIG_MACH_HALIBUT) += board-halibut.o
 
+obj-$(CONFIG_MACH_TROUT) += board-dream.o
diff --git a/arch/arm/mach-msm/board-dream.c b/arch/arm/mach-msm/board-dream.c
new file mode 100644
index 000000000000..21afa8513168
--- /dev/null
+++ b/arch/arm/mach-msm/board-dream.c
@@ -0,0 +1,93 @@
+/* linux/arch/arm/mach-msm/board-dream.c
+ *
+ * Copyright (C) 2009 Google, Inc.
+ * Author: Brian Swetland <swetland@google.com>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/setup.h>
+
+#include <mach/board.h>
+#include <mach/hardware.h>
+#include <mach/msm_iomap.h>
+
+#include "devices.h"
+#include "board-dream.h"
+
+static struct platform_device *devices[] __initdata = {
+        &msm_device_uart3,
+        &msm_device_smd,
+        &msm_device_nand,
+        &msm_device_hsusb,
+        &msm_device_i2c,
+};
+
+extern struct sys_timer msm_timer;
+
+static void __init trout_init_irq(void)
+{
+        msm_init_irq();
+}
+
+static void __init trout_fixup(struct machine_desc *desc, struct tag *tags,
+                                char **cmdline, struct meminfo *mi)
+{
+        mi->nr_banks = 1;
+        mi->bank[0].start = PHYS_OFFSET;
+        mi->bank[0].node = PHYS_TO_NID(PHYS_OFFSET);
+        mi->bank[0].size = (101*1024*1024);
+}
+
+static void __init trout_init(void)
+{
+        platform_add_devices(devices, ARRAY_SIZE(devices));
+}
+
+static struct map_desc trout_io_desc[] __initdata = {
+        {
+                .virtual = TROUT_CPLD_BASE,
+                .pfn     = __phys_to_pfn(TROUT_CPLD_START),
+                .length  = TROUT_CPLD_SIZE,
+                .type    = MT_DEVICE_NONSHARED
+        }
+};
+
+static void __init trout_map_io(void)
+{
+        msm_map_common_io();
+        iotable_init(trout_io_desc, ARRAY_SIZE(trout_io_desc));
+
+#ifdef CONFIG_MSM_DEBUG_UART3
+        /* route UART3 to the "H2W" extended usb connector */
+        writeb(0x80, TROUT_CPLD_BASE + 0x00);
+#endif
+
+        msm_clock_init();
+}
+
+MACHINE_START(TROUT, "HTC Dream")
+        .phys_io        = MSM_DEBUG_UART_PHYS,
+        .io_pg_offst    = ((MSM_DEBUG_UART_BASE) >> 18) & 0xfffc,
+        .boot_params    = 0x10000100,
+        .fixup          = trout_fixup,
+        .map_io         = trout_map_io,
+        .init_irq       = trout_init_irq,
+        .init_machine   = trout_init,
+        .timer          = &msm_timer,
+MACHINE_END
diff --git a/arch/arm/mach-msm/board-dream.h b/arch/arm/mach-msm/board-dream.h
new file mode 100644
index 000000000000..4f345a5a0a61
--- /dev/null
+++ b/arch/arm/mach-msm/board-dream.h
@@ -0,0 +1,5 @@
+
+#define TROUT_CPLD_BASE   0xE8100000
+#define TROUT_CPLD_START  0x98000000
+#define TROUT_CPLD_SIZE   SZ_4K
+
diff --git a/arch/arm/mach-msm/include/mach/debug-macro.S b/arch/arm/mach-msm/include/mach/debug-macro.S
index 1db3c97dbc49..d48747ebcd3d 100644
--- a/arch/arm/mach-msm/include/mach/debug-macro.S
+++ b/arch/arm/mach-msm/include/mach/debug-macro.S
@@ -14,15 +14,18 @@
  *
  */
 
+
+
 #include <mach/hardware.h>
 #include <mach/msm_iomap.h>
 
+#ifdef CONFIG_MSM_DEBUG_UART
         .macro  addruart,rx
         @ see if the MMU is enabled and select appropriate base address
         mrc     p15, 0, \rx, c1, c0
         tst     \rx, #1
-        ldreq   \rx, =MSM_UART1_PHYS
-        movne   \rx, #0
+        ldreq   \rx, =MSM_DEBUG_UART_PHYS
+        ldrne   \rx, =MSM_DEBUG_UART_BASE
         .endm
 
         .macro  senduart,rd,rx
@@ -32,13 +35,20 @@
 
         .macro  waituart,rd,rx
         @ wait for TX_READY
-        teq     \rx, #0
-        bne     2f
-1:      ldr     \rd, [\rx, #0x08]
+1001:   ldr     \rd, [\rx, #0x08]
         tst     \rd, #0x04
-        beq     1b
-2:
+        beq     1001b
+        .endm
+#else
+        .macro  addruart,rx
+        .endm
+
+        .macro  senduart,rd,rx
+        .endm
+
+        .macro  waituart,rd,rx
         .endm
+#endif
 
         .macro  busyuart,rd,rx
         .endm
diff --git a/arch/arm/mach-msm/include/mach/mmc.h b/arch/arm/mach-msm/include/mach/mmc.h
new file mode 100644
index 000000000000..0ecf25426284
--- /dev/null
+++ b/arch/arm/mach-msm/include/mach/mmc.h
@@ -0,0 +1,26 @@
+/*
+ *  arch/arm/include/asm/mach/mmc.h
+ */
+#ifndef ASMARM_MACH_MMC_H
+#define ASMARM_MACH_MMC_H
+
+#include <linux/mmc/host.h>
+#include <linux/mmc/card.h>
+#include <linux/mmc/sdio_func.h>
+
+struct embedded_sdio_data {
+        struct sdio_cis cis;
+        struct sdio_cccr cccr;
+        struct sdio_embedded_func *funcs;
+        int num_funcs;
+};
+
+struct mmc_platform_data {
+        unsigned int ocr_mask;                  /* available voltages */
+        u32 (*translate_vdd)(struct device *, unsigned int);
+        unsigned int (*status)(struct device *);
+        struct embedded_sdio_data *embedded_sdio;
+        int (*register_status_notify)(void (*callback)(int card_present, void *dev_id), void *dev_id);
+};
+
+#endif
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap.h b/arch/arm/mach-msm/include/mach/msm_iomap.h
index 2f7b4c8620d9..9dae1a98c77a 100644
--- a/arch/arm/mach-msm/include/mach/msm_iomap.h
+++ b/arch/arm/mach-msm/include/mach/msm_iomap.h
@@ -84,6 +84,18 @@
 #define MSM_UART3_PHYS        0xA9C00000
 #define MSM_UART3_SIZE        SZ_4K
 
+#ifdef CONFIG_MSM_DEBUG_UART
+#define MSM_DEBUG_UART_BASE   0xE1000000
+#if CONFIG_MSM_DEBUG_UART == 1
+#define MSM_DEBUG_UART_PHYS   MSM_UART1_PHYS
+#elif CONFIG_MSM_DEBUG_UART == 2
+#define MSM_DEBUG_UART_PHYS   MSM_UART2_PHYS
+#elif CONFIG_MSM_DEBUG_UART == 3
+#define MSM_DEBUG_UART_PHYS   MSM_UART3_PHYS
+#endif
+#define MSM_DEBUG_UART_SIZE   SZ_4K
+#endif
+
 #define MSM_SDC1_PHYS         0xA0400000
 #define MSM_SDC1_SIZE         SZ_4K
 
diff --git a/arch/arm/mach-msm/include/mach/uncompress.h b/arch/arm/mach-msm/include/mach/uncompress.h
index 026e8955ace9..d94292c29d8e 100644
--- a/arch/arm/mach-msm/include/mach/uncompress.h
+++ b/arch/arm/mach-msm/include/mach/uncompress.h
@@ -16,9 +16,16 @@
 #ifndef __ASM_ARCH_MSM_UNCOMPRESS_H
 
 #include "hardware.h"
+#include "linux/io.h"
+#include "mach/msm_iomap.h"
 
 static void putc(int c)
 {
+#if defined(MSM_DEBUG_UART_PHYS)
+        unsigned base = MSM_DEBUG_UART_PHYS;
+        while (!(readl(base + 0x08) & 0x04)) ;
+        writel(c, base + 0x0c);
+#endif
 }
 
 static inline void flush(void)
diff --git a/arch/arm/mach-msm/io.c b/arch/arm/mach-msm/io.c
index 6e7692ff6f2c..1c5e7dac086f 100644
--- a/arch/arm/mach-msm/io.c
+++ b/arch/arm/mach-msm/io.c
@@ -42,6 +42,9 @@ static struct map_desc msm_io_desc[] __initdata = {
         MSM_DEVICE(GPIO1),
         MSM_DEVICE(GPIO2),
         MSM_DEVICE(CLK_CTL),
+#ifdef CONFIG_MSM_DEBUG_UART
+        MSM_DEVICE(DEBUG_UART),
+#endif
         {
                 .virtual =  (unsigned long) MSM_SHARED_RAM_BASE,
                 .pfn =      __phys_to_pfn(MSM_SHARED_RAM_PHYS),
diff --git a/arch/arm/mach-nomadik/board-nhk8815.c b/arch/arm/mach-nomadik/board-nhk8815.c
index 116394484e71..9438bf6613a3 100644
--- a/arch/arm/mach-nomadik/board-nhk8815.c
+++ b/arch/arm/mach-nomadik/board-nhk8815.c
@@ -18,6 +18,7 @@
 #include <linux/gpio.h>
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/nand.h>
+#include <linux/mtd/onenand.h>
 #include <linux/mtd/partitions.h>
 #include <linux/io.h>
 #include <asm/sizes.h>
@@ -149,7 +150,7 @@ static struct mtd_partition nhk8815_onenand_partitions[] = {
         }
 };
 
-static struct flash_platform_data nhk8815_onenand_data = {
+static struct onenand_platform_data nhk8815_onenand_data = {
         .parts          = nhk8815_onenand_partitions,
         .nr_parts       = ARRAY_SIZE(nhk8815_onenand_partitions),
 };
@@ -163,7 +164,7 @@ static struct resource nhk8815_onenand_resource[] = {
 };
 
 static struct platform_device nhk8815_onenand_device = {
-        .name           = "onenand",
+        .name           = "onenand-flash",
         .id             = -1,
         .dev            = {
                 .platform_data  = &nhk8815_onenand_data,
@@ -174,10 +175,10 @@ static struct platform_device nhk8815_onenand_device = {
 
 static void __init nhk8815_onenand_init(void)
 {
-#ifdef CONFIG_ONENAND
+#ifdef CONFIG_MTD_ONENAND
        /* Set up SMCS0 for OneNand */
-       writel(0x000030db, FSMC_BCR0);
-       writel(0x02100551, FSMC_BTR0);
+        writel(0x000030db, FSMC_BCR(0));
+        writel(0x02100551, FSMC_BTR(0));
 #endif
 }
 
diff --git a/arch/arm/mach-ns9xxx/irq.c b/arch/arm/mach-ns9xxx/irq.c
index feb0e54a91de..038f24d47023 100644
--- a/arch/arm/mach-ns9xxx/irq.c
+++ b/arch/arm/mach-ns9xxx/irq.c
@@ -66,7 +66,7 @@ static void handle_prio_irq(unsigned int irq, struct irq_desc *desc)
         struct irqaction *action;
         irqreturn_t action_ret;
 
-        spin_lock(&desc->lock);
+        raw_spin_lock(&desc->lock);
 
         BUG_ON(desc->status & IRQ_INPROGRESS);
 
@@ -78,7 +78,7 @@ static void handle_prio_irq(unsigned int irq, struct irq_desc *desc)
                 goto out_mask;
 
         desc->status |= IRQ_INPROGRESS;
-        spin_unlock(&desc->lock);
+        raw_spin_unlock(&desc->lock);
 
         action_ret = handle_IRQ_event(irq, action);
 
@@ -87,7 +87,7 @@ static void handle_prio_irq(unsigned int irq, struct irq_desc *desc)
          * Maybe this function should go to kernel/irq/chip.c? */
         note_interrupt(irq, desc, action_ret);
 
-        spin_lock(&desc->lock);
+        raw_spin_lock(&desc->lock);
         desc->status &= ~IRQ_INPROGRESS;
 
         if (desc->status & IRQ_DISABLED)
@@ -97,7 +97,7 @@ out_mask:
         /* ack unconditionally to unmask lower prio irqs */
         desc->chip->ack(irq);
 
-        spin_unlock(&desc->lock);
+        raw_spin_unlock(&desc->lock);
 }
 #define handle_irq handle_prio_irq
 #endif
diff --git a/arch/arm/mach-omap1/Makefile b/arch/arm/mach-omap1/Makefile
index 87e539aa8ad9..9ce17f13d3f1 100644
--- a/arch/arm/mach-omap1/Makefile
+++ b/arch/arm/mach-omap1/Makefile
@@ -3,7 +3,8 @@
 #
 
 # Common support
-obj-y := io.o id.o sram.o clock.o irq.o mux.o serial.o devices.o
+obj-y := io.o id.o sram.o irq.o mux.o serial.o devices.o
+obj-y += clock.o clock_data.o opp_data.o
 
 obj-$(CONFIG_OMAP_MCBSP) += mcbsp.o
 
@@ -17,6 +18,9 @@ obj-$(CONFIG_PM) += pm.o sleep.o
 obj-$(CONFIG_OMAP_MBOX_FWK)     += mailbox_mach.o
 mailbox_mach-objs               := mailbox.o
 
+i2c-omap-$(CONFIG_I2C_OMAP)             := i2c.o
+obj-y                                   += $(i2c-omap-m) $(i2c-omap-y)
+
 led-y := leds.o
 
 # Specific board support
@@ -48,3 +52,7 @@ led-$(CONFIG_MACH_OMAP_INNOVATOR)	+= leds-innovator.o
 led-$(CONFIG_MACH_OMAP_PERSEUS2)        += leds-h2p2-debug.o
 led-$(CONFIG_MACH_OMAP_OSK)             += leds-osk.o
 obj-$(CONFIG_LEDS)                      += $(led-y)
+
+ifneq ($(CONFIG_FB_OMAP),)
+obj-y += lcd_dma.o
+endif
diff --git a/arch/arm/mach-omap1/board-fsample.c b/arch/arm/mach-omap1/board-fsample.c
index f4b72c1654f5..7e70c3c08da6 100644
--- a/arch/arm/mach-omap1/board-fsample.c
+++ b/arch/arm/mach-omap1/board-fsample.c
@@ -19,6 +19,7 @@
 #include <linux/mtd/nand.h>
 #include <linux/mtd/partitions.h>
 #include <linux/input.h>
+#include <linux/smc91x.h>
 
 #include <mach/hardware.h>
 #include <asm/mach-types.h>
@@ -30,7 +31,6 @@
 #include <mach/gpio.h>
 #include <plat/mux.h>
 #include <plat/fpga.h>
-#include <plat/nand.h>
 #include <plat/keypad.h>
 #include <plat/common.h>
 #include <plat/board.h>
@@ -100,6 +100,12 @@ static int fsample_keymap[] = {
         0
 };
 
+static struct smc91x_platdata smc91x_info = {
+        .flags  = SMC91X_USE_16BIT | SMC91X_NOWAIT,
+        .leda   = RPC_LED_100_10,
+        .ledb   = RPC_LED_TX_RX,
+};
+
 static struct resource smc91x_resources[] = {
         [0] = {
                 .start  = H2P2_DBG_FPGA_ETHR_START,     /* Physical */
@@ -167,8 +173,40 @@ static struct platform_device nor_device = {
         .resource       = &nor_resource,
 };
 
-static struct omap_nand_platform_data nand_data = {
-        .options        = NAND_SAMSUNG_LP_OPTIONS,
+static void nand_cmd_ctl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
+{
+        struct nand_chip *this = mtd->priv;
+        unsigned long mask;
+
+        if (cmd == NAND_CMD_NONE)
+                return;
+
+        mask = (ctrl & NAND_CLE) ? 0x02 : 0;
+        if (ctrl & NAND_ALE)
+                mask |= 0x04;
+        writeb(cmd, (unsigned long)this->IO_ADDR_W | mask);
+}
+
+#define FSAMPLE_NAND_RB_GPIO_PIN        62
+
+static int nand_dev_ready(struct mtd_info *mtd)
+{
+        return gpio_get_value(FSAMPLE_NAND_RB_GPIO_PIN);
+}
+
+static const char *part_probes[] = { "cmdlinepart", NULL };
+
+static struct platform_nand_data nand_data = {
+        .chip   = {
+                .nr_chips               = 1,
+                .chip_offset            = 0,
+                .options                = NAND_SAMSUNG_LP_OPTIONS,
+                .part_probe_types       = part_probes,
+        },
+        .ctrl   = {
+                .cmd_ctrl       = nand_cmd_ctl,
+                .dev_ready      = nand_dev_ready,
+        },
 };
 
 static struct resource nand_resource = {
@@ -178,7 +216,7 @@ static struct resource nand_resource = {
 };
 
 static struct platform_device nand_device = {
-        .name           = "omapnand",
+        .name           = "gen_nand",
         .id             = 0,
         .dev            = {
                 .platform_data  = &nand_data,
@@ -190,6 +228,9 @@ static struct platform_device nand_device = {
 static struct platform_device smc91x_device = {
         .name           = "smc91x",
         .id             = 0,
+        .dev    = {
+                .platform_data  = &smc91x_info,
+        },
         .num_resources  = ARRAY_SIZE(smc91x_resources),
         .resource       = smc91x_resources,
 };
@@ -233,13 +274,6 @@ static struct platform_device *devices[] __initdata = {
         &lcd_device,
 };
 
-#define P2_NAND_RB_GPIO_PIN     62
-
-static int nand_dev_ready(struct omap_nand_platform_data *data)
-{
-        return gpio_get_value(P2_NAND_RB_GPIO_PIN);
-}
-
 static struct omap_lcd_config fsample_lcd_config __initdata = {
         .ctrl_name      = "internal",
 };
@@ -250,9 +284,9 @@ static struct omap_board_config_kernel fsample_config[] = {
 
 static void __init omap_fsample_init(void)
 {
-        if (gpio_request(P2_NAND_RB_GPIO_PIN, "NAND ready") < 0)
+        if (gpio_request(FSAMPLE_NAND_RB_GPIO_PIN, "NAND ready") < 0)
                 BUG();
-        nand_data.dev_ready = nand_dev_ready;
+        gpio_direction_input(FSAMPLE_NAND_RB_GPIO_PIN);
 
         omap_cfg_reg(L3_1610_FLASH_CS2B_OE);
         omap_cfg_reg(M8_1610_FLASH_CS2B_WE);
diff --git a/arch/arm/mach-omap1/board-h2.c b/arch/arm/mach-omap1/board-h2.c
index 89ba8ec4bbf4..fa7cecea19f9 100644
--- a/arch/arm/mach-omap1/board-h2.c
+++ b/arch/arm/mach-omap1/board-h2.c
@@ -28,6 +28,7 @@
 #include <linux/mtd/partitions.h>
 #include <linux/input.h>
 #include <linux/i2c/tps65010.h>
+#include <linux/smc91x.h>
 
 #include <mach/hardware.h>
 #include <asm/gpio.h>
@@ -40,7 +41,6 @@
 #include <plat/mux.h>
 #include <plat/dma.h>
 #include <plat/tc.h>
-#include <plat/nand.h>
 #include <plat/irda.h>
 #include <plat/usb.h>
 #include <plat/keypad.h>
@@ -179,11 +179,43 @@ static struct mtd_partition h2_nand_partitions[] = {
         },
 };
 
-/* dip switches control NAND chip access:  8 bit, 16 bit, or neither */
-static struct omap_nand_platform_data h2_nand_data = {
-        .options        = NAND_SAMSUNG_LP_OPTIONS,
-        .parts          = h2_nand_partitions,
-        .nr_parts       = ARRAY_SIZE(h2_nand_partitions),
+static void h2_nand_cmd_ctl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
+{
+        struct nand_chip *this = mtd->priv;
+        unsigned long mask;
+
+        if (cmd == NAND_CMD_NONE)
+                return;
+
+        mask = (ctrl & NAND_CLE) ? 0x02 : 0;
+        if (ctrl & NAND_ALE)
+                mask |= 0x04;
+        writeb(cmd, (unsigned long)this->IO_ADDR_W | mask);
+}
+
+#define H2_NAND_RB_GPIO_PIN     62
+
+static int h2_nand_dev_ready(struct mtd_info *mtd)
+{
+        return gpio_get_value(H2_NAND_RB_GPIO_PIN);
+}
+
+static const char *h2_part_probes[] = { "cmdlinepart", NULL };
+
+struct platform_nand_data h2_nand_platdata = {
+        .chip   = {
+                .nr_chips               = 1,
+                .chip_offset            = 0,
+                .nr_partitions          = ARRAY_SIZE(h2_nand_partitions),
+                .partitions             = h2_nand_partitions,
+                .options                = NAND_SAMSUNG_LP_OPTIONS,
+                .part_probe_types       = h2_part_probes,
+        },
+        .ctrl   = {
+                .cmd_ctrl       = h2_nand_cmd_ctl,
+                .dev_ready      = h2_nand_dev_ready,
+
+        },
 };
 
 static struct resource h2_nand_resource = {
@@ -191,15 +223,21 @@ static struct resource h2_nand_resource = {
 };
 
 static struct platform_device h2_nand_device = {
-        .name           = "omapnand",
+        .name           = "gen_nand",
         .id             = 0,
         .dev            = {
-                .platform_data  = &h2_nand_data,
+                .platform_data  = &h2_nand_platdata,
         },
         .num_resources  = 1,
         .resource       = &h2_nand_resource,
 };
 
+static struct smc91x_platdata h2_smc91x_info = {
+        .flags  = SMC91X_USE_16BIT | SMC91X_NOWAIT,
+        .leda   = RPC_LED_100_10,
+        .ledb   = RPC_LED_TX_RX,
+};
+
 static struct resource h2_smc91x_resources[] = {
         [0] = {
                 .start  = OMAP1610_ETHR_START,          /* Physical */
@@ -216,6 +254,9 @@ static struct resource h2_smc91x_resources[] = {
 static struct platform_device h2_smc91x_device = {
         .name           = "smc91x",
         .id             = 0,
+        .dev    = {
+                .platform_data  = &h2_smc91x_info,
+        },
         .num_resources  = ARRAY_SIZE(h2_smc91x_resources),
         .resource       = h2_smc91x_resources,
 };
@@ -368,8 +409,6 @@ static struct omap_board_config_kernel h2_config[] __initdata = {
         { OMAP_TAG_LCD,         &h2_lcd_config },
 };
 
-#define H2_NAND_RB_GPIO_PIN     62
-
 static void __init h2_init(void)
 {
         /* Here we assume the NOR boot config:  NOR on CS3 (possibly swapped
diff --git a/arch/arm/mach-omap1/board-h3.c b/arch/arm/mach-omap1/board-h3.c
index f5cc0a730524..6a7f9c391cf1 100644
--- a/arch/arm/mach-omap1/board-h3.c
+++ b/arch/arm/mach-omap1/board-h3.c
@@ -28,6 +28,7 @@
 #include <linux/input.h>
 #include <linux/spi/spi.h>
 #include <linux/i2c/tps65010.h>
+#include <linux/smc91x.h>
 
 #include <asm/setup.h>
 #include <asm/page.h>
@@ -42,7 +43,6 @@
 #include <mach/irqs.h>
 #include <plat/mux.h>
 #include <plat/tc.h>
-#include <plat/nand.h>
 #include <plat/usb.h>
 #include <plat/keypad.h>
 #include <plat/dma.h>
@@ -181,11 +181,43 @@ static struct mtd_partition nand_partitions[] = {
         },
 };
 
-/* dip switches control NAND chip access:  8 bit, 16 bit, or neither */
-static struct omap_nand_platform_data nand_data = {
-        .options        = NAND_SAMSUNG_LP_OPTIONS,
-        .parts          = nand_partitions,
-        .nr_parts       = ARRAY_SIZE(nand_partitions),
+static void nand_cmd_ctl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
+{
+        struct nand_chip *this = mtd->priv;
+        unsigned long mask;
+
+        if (cmd == NAND_CMD_NONE)
+                return;
+
+        mask = (ctrl & NAND_CLE) ? 0x02 : 0;
+        if (ctrl & NAND_ALE)
+                mask |= 0x04;
+        writeb(cmd, (unsigned long)this->IO_ADDR_W | mask);
+}
+
+#define H3_NAND_RB_GPIO_PIN     10
+
+static int nand_dev_ready(struct mtd_info *mtd)
+{
+        return gpio_get_value(H3_NAND_RB_GPIO_PIN);
+}
+
+static const char *part_probes[] = { "cmdlinepart", NULL };
+
+struct platform_nand_data nand_platdata = {
+        .chip   = {
+                .nr_chips               = 1,
+                .chip_offset            = 0,
+                .nr_partitions          = ARRAY_SIZE(nand_partitions),
+                .partitions             = nand_partitions,
+                .options                = NAND_SAMSUNG_LP_OPTIONS,
+                .part_probe_types       = part_probes,
+        },
+        .ctrl   = {
+                .cmd_ctrl       = nand_cmd_ctl,
+                .dev_ready      = nand_dev_ready,
+
+        },
 };
 
 static struct resource nand_resource = {
@@ -193,15 +225,21 @@ static struct resource nand_resource = {
 };
 
 static struct platform_device nand_device = {
-        .name           = "omapnand",
+        .name           = "gen_nand",
         .id             = 0,
         .dev            = {
-                .platform_data  = &nand_data,
+                .platform_data  = &nand_platdata,
         },
         .num_resources  = 1,
         .resource       = &nand_resource,
 };
 
+static struct smc91x_platdata smc91x_info = {
+        .flags  = SMC91X_USE_16BIT | SMC91X_NOWAIT,
+        .leda   = RPC_LED_100_10,
+        .ledb   = RPC_LED_TX_RX,
+};
+
 static struct resource smc91x_resources[] = {
         [0] = {
                 .start  = OMAP1710_ETHR_START,          /* Physical */
@@ -218,6 +256,9 @@ static struct resource smc91x_resources[] = {
 static struct platform_device smc91x_device = {
         .name           = "smc91x",
         .id             = 0,
+        .dev    = {
+                .platform_data  = &smc91x_info,
+        },
         .num_resources  = ARRAY_SIZE(smc91x_resources),
         .resource       = smc91x_resources,
 };
@@ -332,13 +373,6 @@ static struct i2c_board_info __initdata h3_i2c_board_info[] = {
         },
 };
 
-#define H3_NAND_RB_GPIO_PIN     10
-
-static int nand_dev_ready(struct omap_nand_platform_data *data)
-{
-        return gpio_get_value(H3_NAND_RB_GPIO_PIN);
-}
-
 static void __init h3_init(void)
 {
         /* Here we assume the NOR boot config:  NOR on CS3 (possibly swapped
@@ -356,7 +390,7 @@ static void __init h3_init(void)
         nand_resource.end += SZ_4K - 1;
         if (gpio_request(H3_NAND_RB_GPIO_PIN, "NAND ready") < 0)
                 BUG();
-        nand_data.dev_ready = nand_dev_ready;
+        gpio_direction_input(H3_NAND_RB_GPIO_PIN);
 
         /* GPIO10 Func_MUX_CTRL reg bit 29:27, Configure V2 to mode1 as GPIO */
         /* GPIO10 pullup/down register, Enable pullup on GPIO10 */
diff --git a/arch/arm/mach-omap1/board-htcherald.c b/arch/arm/mach-omap1/board-htcherald.c
index 5f28a5ceacac..e36639f66150 100644
--- a/arch/arm/mach-omap1/board-htcherald.c
+++ b/arch/arm/mach-omap1/board-htcherald.c
@@ -39,6 +39,7 @@
 #include <plat/common.h>
 #include <plat/board.h>
 #include <plat/keypad.h>
+#include <plat/usb.h>
 
 #include <mach/irqs.h>
 
@@ -140,6 +141,15 @@ static struct platform_device kp_device = {
         .resource       = kp_resources,
 };
 
+/* USB Device */
+static struct omap_usb_config htcherald_usb_config __initdata = {
+        .otg = 0,
+        .register_host = 0,
+        .register_dev  = 1,
+        .hmc_mode = 4,
+        .pins[0] = 2,
+};
+
 /* LCD Device resources */
 static struct platform_device lcd_device = {
         .name           = "lcd_htcherald",
@@ -214,6 +224,57 @@ static void __init htcherald_disable_watchdog(void)
         }
 }
 
+#define HTCHERALD_GPIO_USB_EN1 33
+#define HTCHERALD_GPIO_USB_EN2 73
+#define HTCHERALD_GPIO_USB_DM  35
+#define HTCHERALD_GPIO_USB_DP  36
+
+static void __init htcherald_usb_enable(void)
+{
+        unsigned int tries = 20;
+        unsigned int value = 0;
+
+        /* Request the GPIOs we need to control here */
+        if (gpio_request(HTCHERALD_GPIO_USB_EN1, "herald_usb") < 0)
+                goto err1;
+
+        if (gpio_request(HTCHERALD_GPIO_USB_EN2, "herald_usb") < 0)
+                goto err2;
+
+        if (gpio_request(HTCHERALD_GPIO_USB_DM, "herald_usb") < 0)
+                goto err3;
+
+        if (gpio_request(HTCHERALD_GPIO_USB_DP, "herald_usb") < 0)
+                goto err4;
+
+        /* force USB_EN GPIO to 0 */
+        do {
+                /* output low */
+                gpio_direction_output(HTCHERALD_GPIO_USB_EN1, 0);
+        } while ((value = gpio_get_value(HTCHERALD_GPIO_USB_EN1)) == 1 &&
+                        --tries);
+
+        if (value == 1)
+                printk(KERN_WARNING "Unable to reset USB, trying to continue\n");
+
+        gpio_direction_output(HTCHERALD_GPIO_USB_EN2, 0); /* output low */
+        gpio_direction_input(HTCHERALD_GPIO_USB_DM); /* input */
+        gpio_direction_input(HTCHERALD_GPIO_USB_DP); /* input */
+
+        goto done;
+
+err4:
+        gpio_free(HTCHERALD_GPIO_USB_DM);
+err3:
+        gpio_free(HTCHERALD_GPIO_USB_EN2);
+err2:
+        gpio_free(HTCHERALD_GPIO_USB_EN1);
+err1:
+        printk(KERN_ERR "Unabled to request GPIO for USB\n");
+done:
+        printk(KERN_INFO "USB setup complete.\n");
+}
+
 static void __init htcherald_init(void)
 {
         printk(KERN_INFO "HTC Herald init.\n");
@@ -225,6 +286,9 @@ static void __init htcherald_init(void)
         platform_add_devices(devices, ARRAY_SIZE(devices));
 
         htcherald_disable_watchdog();
+
+        htcherald_usb_enable();
+        omap_usb_init(&htcherald_usb_config);
 }
 
 static void __init htcherald_init_irq(void)
diff --git a/arch/arm/mach-omap1/board-innovator.c b/arch/arm/mach-omap1/board-innovator.c
index cf0fdb9c182f..2133b006f6a3 100644
--- a/arch/arm/mach-omap1/board-innovator.c
+++ b/arch/arm/mach-omap1/board-innovator.c
@@ -23,6 +23,7 @@
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/partitions.h>
 #include <linux/input.h>
+#include <linux/smc91x.h>
 
 #include <mach/hardware.h>
 #include <asm/mach-types.h>
@@ -142,6 +143,11 @@ static struct platform_device innovator_kp_device = {
         .resource       = innovator_kp_resources,
 };
 
+static struct smc91x_platdata innovator_smc91x_info = {
+        .flags  = SMC91X_USE_16BIT | SMC91X_NOWAIT,
+        .leda   = RPC_LED_100_10,
+        .ledb   = RPC_LED_TX_RX,
+};
 
 #ifdef CONFIG_ARCH_OMAP15XX
 
@@ -175,6 +181,9 @@ static struct resource innovator1510_smc91x_resources[] = {
 static struct platform_device innovator1510_smc91x_device = {
         .name           = "smc91x",
         .id             = 0,
+        .dev    = {
+                .platform_data  = &innovator_smc91x_info,
+        },
         .num_resources  = ARRAY_SIZE(innovator1510_smc91x_resources),
         .resource       = innovator1510_smc91x_resources,
 };
@@ -241,6 +250,9 @@ static struct resource innovator1610_smc91x_resources[] = {
 static struct platform_device innovator1610_smc91x_device = {
         .name           = "smc91x",
         .id             = 0,
+        .dev    = {
+                .platform_data  = &innovator_smc91x_info,
+        },
         .num_resources  = ARRAY_SIZE(innovator1610_smc91x_resources),
         .resource       = innovator1610_smc91x_resources,
 };
diff --git a/arch/arm/mach-omap1/board-osk.c b/arch/arm/mach-omap1/board-osk.c
index 50c92c13e48a..ccea4f448e9a 100644
--- a/arch/arm/mach-omap1/board-osk.c
+++ b/arch/arm/mach-omap1/board-osk.c
@@ -33,6 +33,7 @@
 #include <linux/irq.h>
 #include <linux/i2c.h>
 #include <linux/leds.h>
+#include <linux/smc91x.h>
 
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/partitions.h>
@@ -115,6 +116,12 @@ static struct platform_device osk5912_flash_device = {
         .resource       = &osk_flash_resource,
 };
 
+static struct smc91x_platdata osk5912_smc91x_info = {
+        .flags  = SMC91X_USE_16BIT | SMC91X_NOWAIT,
+        .leda   = RPC_LED_100_10,
+        .ledb   = RPC_LED_TX_RX,
+};
+
 static struct resource osk5912_smc91x_resources[] = {
         [0] = {
                 .start  = OMAP_OSK_ETHR_START,          /* Physical */
@@ -131,6 +138,9 @@ static struct resource osk5912_smc91x_resources[] = {
 static struct platform_device osk5912_smc91x_device = {
         .name           = "smc91x",
         .id             = -1,
+        .dev    = {
+                .platform_data  = &osk5912_smc91x_info,
+        },
         .num_resources  = ARRAY_SIZE(osk5912_smc91x_resources),
         .resource       = osk5912_smc91x_resources,
 };
diff --git a/arch/arm/mach-omap1/board-perseus2.c b/arch/arm/mach-omap1/board-perseus2.c
index ca7df1e93efc..1387a4f15da9 100644
--- a/arch/arm/mach-omap1/board-perseus2.c
+++ b/arch/arm/mach-omap1/board-perseus2.c
@@ -19,6 +19,7 @@
 #include <linux/mtd/nand.h>
 #include <linux/mtd/partitions.h>
 #include <linux/input.h>
+#include <linux/smc91x.h>
 
 #include <mach/hardware.h>
 #include <asm/mach-types.h>
@@ -30,7 +31,6 @@
 #include <mach/gpio.h>
 #include <plat/mux.h>
 #include <plat/fpga.h>
-#include <plat/nand.h>
 #include <plat/keypad.h>
 #include <plat/common.h>
 #include <plat/board.h>
@@ -67,6 +67,12 @@ static int p2_keymap[] = {
         0
 };
 
+static struct smc91x_platdata smc91x_info = {
+        .flags  = SMC91X_USE_16BIT | SMC91X_NOWAIT,
+        .leda   = RPC_LED_100_10,
+        .ledb   = RPC_LED_TX_RX,
+};
+
 static struct resource smc91x_resources[] = {
         [0] = {
                 .start  = H2P2_DBG_FPGA_ETHR_START,     /* Physical */
@@ -134,8 +140,40 @@ static struct platform_device nor_device = {
         .resource       = &nor_resource,
 };
 
-static struct omap_nand_platform_data nand_data = {
-        .options        = NAND_SAMSUNG_LP_OPTIONS,
+static void nand_cmd_ctl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
+{
+        struct nand_chip *this = mtd->priv;
+        unsigned long mask;
+
+        if (cmd == NAND_CMD_NONE)
+                return;
+
+        mask = (ctrl & NAND_CLE) ? 0x02 : 0;
+        if (ctrl & NAND_ALE)
+                mask |= 0x04;
+        writeb(cmd, (unsigned long)this->IO_ADDR_W | mask);
+}
+
+#define P2_NAND_RB_GPIO_PIN     62
+
+static int nand_dev_ready(struct mtd_info *mtd)
+{
+        return gpio_get_value(P2_NAND_RB_GPIO_PIN);
+}
+
+static const char *part_probes[] = { "cmdlinepart", NULL };
+
+static struct platform_nand_data nand_data = {
+        .chip   = {
+                .nr_chips               = 1,
+                .chip_offset            = 0,
+                .options                = NAND_SAMSUNG_LP_OPTIONS,
+                .part_probe_types       = part_probes,
+        },
+        .ctrl   = {
+                .cmd_ctrl       = nand_cmd_ctl,
+                .dev_ready      = nand_dev_ready,
+        },
 };
 
 static struct resource nand_resource = {
@@ -145,7 +183,7 @@ static struct resource nand_resource = {
 };
 
 static struct platform_device nand_device = {
-        .name           = "omapnand",
+        .name           = "gen_nand",
         .id             = 0,
         .dev            = {
                 .platform_data  = &nand_data,
@@ -157,6 +195,9 @@ static struct platform_device nand_device = {
 static struct platform_device smc91x_device = {
         .name           = "smc91x",
         .id             = 0,
+        .dev    = {
+                .platform_data  = &smc91x_info,
+        },
         .num_resources  = ARRAY_SIZE(smc91x_resources),
         .resource       = smc91x_resources,
 };
@@ -201,13 +242,6 @@ static struct platform_device *devices[] __initdata = {
         &lcd_device,
 };
 
-#define P2_NAND_RB_GPIO_PIN     62
-
-static int nand_dev_ready(struct omap_nand_platform_data *data)
-{
-        return gpio_get_value(P2_NAND_RB_GPIO_PIN);
-}
-
 static struct omap_lcd_config perseus2_lcd_config __initdata = {
         .ctrl_name      = "internal",
 };
@@ -220,7 +254,7 @@ static void __init omap_perseus2_init(void)
 {
         if (gpio_request(P2_NAND_RB_GPIO_PIN, "NAND ready") < 0)
                 BUG();
-        nand_data.dev_ready = nand_dev_ready;
+        gpio_direction_input(P2_NAND_RB_GPIO_PIN);
 
         omap_cfg_reg(L3_1610_FLASH_CS2B_OE);
         omap_cfg_reg(M8_1610_FLASH_CS2B_WE);
diff --git a/arch/arm/mach-omap1/board-voiceblue.c b/arch/arm/mach-omap1/board-voiceblue.c
index 35c75c1bd0aa..169183537997 100644
--- a/arch/arm/mach-omap1/board-voiceblue.c
+++ b/arch/arm/mach-omap1/board-voiceblue.c
@@ -22,6 +22,7 @@
 #include <linux/reboot.h>
 #include <linux/serial_8250.h>
 #include <linux/serial_reg.h>
+#include <linux/smc91x.h>
 
 #include <mach/hardware.h>
 #include <asm/mach-types.h>
@@ -106,6 +107,12 @@ static struct platform_device voiceblue_flash_device = {
         .resource       = &voiceblue_flash_resource,
 };
 
+static struct smc91x_platdata voiceblue_smc91x_info = {
+        .flags  = SMC91X_USE_16BIT | SMC91X_NOWAIT,
+        .leda   = RPC_LED_100_10,
+        .ledb   = RPC_LED_TX_RX,
+};
+
 static struct resource voiceblue_smc91x_resources[] = {
         [0] = {
                 .start  = OMAP_CS2_PHYS + 0x300,
@@ -122,6 +129,9 @@ static struct resource voiceblue_smc91x_resources[] = {
 static struct platform_device voiceblue_smc91x_device = {
         .name           = "smc91x",
         .id             = 0,
+        .dev    = {
+                .platform_data  = &voiceblue_smc91x_info,
+        },
         .num_resources  = ARRAY_SIZE(voiceblue_smc91x_resources),
         .resource       = voiceblue_smc91x_resources,
 };
diff --git a/arch/arm/mach-omap1/clock.c b/arch/arm/mach-omap1/clock.c
index 42cbe203da36..2ba9ab953731 100644
--- a/arch/arm/mach-omap1/clock.c
+++ b/arch/arm/mach-omap1/clock.c
@@ -1,7 +1,7 @@
 /*
  *  linux/arch/arm/mach-omap1/clock.c
  *
- *  Copyright (C) 2004 - 2005 Nokia corporation
+ *  Copyright (C) 2004 - 2005, 2009 Nokia corporation
  *  Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
  *
  *  Modified to use omap shared clock framework by
@@ -26,12 +26,17 @@
 #include <plat/usb.h>
 #include <plat/clock.h>
 #include <plat/sram.h>
-
-static const struct clkops clkops_generic;
-static const struct clkops clkops_uart;
-static const struct clkops clkops_dspck;
+#include <plat/clkdev_omap.h>
 
 #include "clock.h"
+#include "opp.h"
+
+__u32 arm_idlect1_mask;
+struct clk *api_ck_p, *ck_dpll1_p, *ck_ref_p;
+
+/*-------------------------------------------------------------------------
+ * Omap1 specific clock functions
+ *-------------------------------------------------------------------------*/
 
 static int clk_omap1_dummy_enable(struct clk *clk)
 {
@@ -42,134 +47,24 @@ static void clk_omap1_dummy_disable(struct clk *clk)
 {
 }
 
-static const struct clkops clkops_dummy = {
-        .enable = clk_omap1_dummy_enable,
-        .disable = clk_omap1_dummy_disable,
-};
-
-static struct clk dummy_ck = {
-        .name   = "dummy",
-        .ops    = &clkops_dummy,
-        .flags  = RATE_FIXED,
-};
-
-struct omap_clk {
-        u32             cpu;
-        struct clk_lookup lk;
+const struct clkops clkops_dummy = {
+        .enable         = clk_omap1_dummy_enable,
+        .disable        = clk_omap1_dummy_disable,
 };
 
-#define CLK(dev, con, ck, cp)           \
-        {                               \
-                 .cpu = cp,             \
-                .lk = {                 \
-                        .dev_id = dev,  \
-                        .con_id = con,  \
-                        .clk = ck,      \
-                },                      \
-        }
-
-#define CK_310  (1 << 0)
-#define CK_7XX  (1 << 1)
-#define CK_1510 (1 << 2)
-#define CK_16XX (1 << 3)
-
-static struct omap_clk omap_clks[] = {
-        /* non-ULPD clocks */
-        CLK(NULL,       "ck_ref",       &ck_ref,        CK_16XX | CK_1510 | CK_310 | CK_7XX),
-        CLK(NULL,       "ck_dpll1",     &ck_dpll1,      CK_16XX | CK_1510 | CK_310),
-        /* CK_GEN1 clocks */
-        CLK(NULL,       "ck_dpll1out",  &ck_dpll1out.clk, CK_16XX),
-        CLK(NULL,       "ck_sossi",     &sossi_ck,      CK_16XX),
-        CLK(NULL,       "arm_ck",       &arm_ck,        CK_16XX | CK_1510 | CK_310),
-        CLK(NULL,       "armper_ck",    &armper_ck.clk, CK_16XX | CK_1510 | CK_310),
-        CLK(NULL,       "arm_gpio_ck",  &arm_gpio_ck,   CK_1510 | CK_310),
-        CLK(NULL,       "armxor_ck",    &armxor_ck.clk, CK_16XX | CK_1510 | CK_310 | CK_7XX),
-        CLK(NULL,       "armtim_ck",    &armtim_ck.clk, CK_16XX | CK_1510 | CK_310),
-        CLK("omap_wdt", "fck",          &armwdt_ck.clk, CK_16XX | CK_1510 | CK_310),
-        CLK("omap_wdt", "ick",          &armper_ck.clk, CK_16XX),
-        CLK("omap_wdt", "ick",          &dummy_ck,      CK_1510 | CK_310),
-        CLK(NULL,       "arminth_ck",   &arminth_ck1510, CK_1510 | CK_310),
-        CLK(NULL,       "arminth_ck",   &arminth_ck16xx, CK_16XX),
-        /* CK_GEN2 clocks */
-        CLK(NULL,       "dsp_ck",       &dsp_ck,        CK_16XX | CK_1510 | CK_310),
-        CLK(NULL,       "dspmmu_ck",    &dspmmu_ck,     CK_16XX | CK_1510 | CK_310),
-        CLK(NULL,       "dspper_ck",    &dspper_ck,     CK_16XX | CK_1510 | CK_310),
-        CLK(NULL,       "dspxor_ck",    &dspxor_ck,     CK_16XX | CK_1510 | CK_310),
-        CLK(NULL,       "dsptim_ck",    &dsptim_ck,     CK_16XX | CK_1510 | CK_310),
-        /* CK_GEN3 clocks */
-        CLK(NULL,       "tc_ck",        &tc_ck.clk,     CK_16XX | CK_1510 | CK_310 | CK_7XX),
-        CLK(NULL,       "tipb_ck",      &tipb_ck,       CK_1510 | CK_310),
-        CLK(NULL,       "l3_ocpi_ck",   &l3_ocpi_ck,    CK_16XX | CK_7XX),
-        CLK(NULL,       "tc1_ck",       &tc1_ck,        CK_16XX),
-        CLK(NULL,       "tc2_ck",       &tc2_ck,        CK_16XX),
-        CLK(NULL,       "dma_ck",       &dma_ck,        CK_16XX | CK_1510 | CK_310),
-        CLK(NULL,       "dma_lcdfree_ck", &dma_lcdfree_ck, CK_16XX),
-        CLK(NULL,       "api_ck",       &api_ck.clk,    CK_16XX | CK_1510 | CK_310),
-        CLK(NULL,       "lb_ck",        &lb_ck.clk,     CK_1510 | CK_310),
-        CLK(NULL,       "rhea1_ck",     &rhea1_ck,      CK_16XX),
-        CLK(NULL,       "rhea2_ck",     &rhea2_ck,      CK_16XX),
-        CLK(NULL,       "lcd_ck",       &lcd_ck_16xx,   CK_16XX | CK_7XX),
-        CLK(NULL,       "lcd_ck",       &lcd_ck_1510.clk, CK_1510 | CK_310),
-        /* ULPD clocks */
-        CLK(NULL,       "uart1_ck",     &uart1_1510,    CK_1510 | CK_310),
-        CLK(NULL,       "uart1_ck",     &uart1_16xx.clk, CK_16XX),
-        CLK(NULL,       "uart2_ck",     &uart2_ck,      CK_16XX | CK_1510 | CK_310),
-        CLK(NULL,       "uart3_ck",     &uart3_1510,    CK_1510 | CK_310),
-        CLK(NULL,       "uart3_ck",     &uart3_16xx.clk, CK_16XX),
-        CLK(NULL,       "usb_clko",     &usb_clko,      CK_16XX | CK_1510 | CK_310),
-        CLK(NULL,       "usb_hhc_ck",   &usb_hhc_ck1510, CK_1510 | CK_310),
-        CLK(NULL,       "usb_hhc_ck",   &usb_hhc_ck16xx, CK_16XX),
-        CLK(NULL,       "usb_dc_ck",    &usb_dc_ck,     CK_16XX),
-        CLK(NULL,       "usb_dc_ck",    &usb_dc_ck7xx,  CK_7XX),
-        CLK(NULL,       "mclk",         &mclk_1510,     CK_1510 | CK_310),
-        CLK(NULL,       "mclk",         &mclk_16xx,     CK_16XX),
-        CLK(NULL,       "bclk",         &bclk_1510,     CK_1510 | CK_310),
-        CLK(NULL,       "bclk",         &bclk_16xx,     CK_16XX),
-        CLK("mmci-omap.0", "fck",       &mmc1_ck,       CK_16XX | CK_1510 | CK_310),
-        CLK("mmci-omap.0", "fck",       &mmc3_ck,       CK_7XX),
-        CLK("mmci-omap.0", "ick",       &armper_ck.clk, CK_16XX | CK_1510 | CK_310 | CK_7XX),
-        CLK("mmci-omap.1", "fck",       &mmc2_ck,       CK_16XX),
-        CLK("mmci-omap.1", "ick",       &armper_ck.clk, CK_16XX),
-        /* Virtual clocks */
-        CLK(NULL,       "mpu",          &virtual_ck_mpu, CK_16XX | CK_1510 | CK_310),
-        CLK("i2c_omap.1", "fck",        &i2c_fck,       CK_16XX | CK_1510 | CK_310),
-        CLK("i2c_omap.1", "ick",        &i2c_ick,       CK_16XX),
-        CLK("i2c_omap.1", "ick",        &dummy_ck,      CK_1510 | CK_310),
-        CLK("omap_uwire", "fck",        &armxor_ck.clk, CK_16XX | CK_1510 | CK_310),
-        CLK("omap-mcbsp.1", "ick",      &dspper_ck,     CK_16XX),
-        CLK("omap-mcbsp.1", "ick",      &dummy_ck,      CK_1510 | CK_310),
-        CLK("omap-mcbsp.2", "ick",      &armper_ck.clk, CK_16XX),
-        CLK("omap-mcbsp.2", "ick",      &dummy_ck,      CK_1510 | CK_310),
-        CLK("omap-mcbsp.3", "ick",      &dspper_ck,     CK_16XX),
-        CLK("omap-mcbsp.3", "ick",      &dummy_ck,      CK_1510 | CK_310),
-        CLK("omap-mcbsp.1", "fck",      &dspxor_ck,     CK_16XX | CK_1510 | CK_310),
-        CLK("omap-mcbsp.2", "fck",      &armper_ck.clk, CK_16XX | CK_1510 | CK_310),
-        CLK("omap-mcbsp.3", "fck",      &dspxor_ck,     CK_16XX | CK_1510 | CK_310),
-};
-
-static int omap1_clk_enable_generic(struct clk * clk);
-static int omap1_clk_enable(struct clk *clk);
-static void omap1_clk_disable_generic(struct clk * clk);
-static void omap1_clk_disable(struct clk *clk);
-
-__u32 arm_idlect1_mask;
-
-/*-------------------------------------------------------------------------
- * Omap1 specific clock functions
- *-------------------------------------------------------------------------*/
-
-static unsigned long omap1_watchdog_recalc(struct clk *clk)
+/* XXX can be replaced with a fixed_divisor_recalc */
+unsigned long omap1_watchdog_recalc(struct clk *clk)
 {
         return clk->parent->rate / 14;
 }
 
-static unsigned long omap1_uart_recalc(struct clk *clk)
+unsigned long omap1_uart_recalc(struct clk *clk)
 {
         unsigned int val = __raw_readl(clk->enable_reg);
         return val & clk->enable_bit ? 48000000 : 12000000;
 }
 
-static unsigned long omap1_sossi_recalc(struct clk *clk)
+unsigned long omap1_sossi_recalc(struct clk *clk)
 {
         u32 div = omap_readl(MOD_CONF_CTRL_1);
 
@@ -179,64 +74,6 @@ static unsigned long omap1_sossi_recalc(struct clk *clk)
         return clk->parent->rate / div;
 }
 
-static int omap1_clk_enable_dsp_domain(struct clk *clk)
-{
-        int retval;
-
-        retval = omap1_clk_enable(&api_ck.clk);
-        if (!retval) {
-                retval = omap1_clk_enable_generic(clk);
-                omap1_clk_disable(&api_ck.clk);
-        }
-
-        return retval;
-}
-
-static void omap1_clk_disable_dsp_domain(struct clk *clk)
-{
-        if (omap1_clk_enable(&api_ck.clk) == 0) {
-                omap1_clk_disable_generic(clk);
-                omap1_clk_disable(&api_ck.clk);
-        }
-}
-
-static const struct clkops clkops_dspck = {
-        .enable         = &omap1_clk_enable_dsp_domain,
-        .disable        = &omap1_clk_disable_dsp_domain,
-};
-
-static int omap1_clk_enable_uart_functional(struct clk *clk)
-{
-        int ret;
-        struct uart_clk *uclk;
-
-        ret = omap1_clk_enable_generic(clk);
-        if (ret == 0) {
-                /* Set smart idle acknowledgement mode */
-                uclk = (struct uart_clk *)clk;
-                omap_writeb((omap_readb(uclk->sysc_addr) & ~0x10) | 8,
-                            uclk->sysc_addr);
-        }
-
-        return ret;
-}
-
-static void omap1_clk_disable_uart_functional(struct clk *clk)
-{
-        struct uart_clk *uclk;
-
-        /* Set force idle acknowledgement mode */
-        uclk = (struct uart_clk *)clk;
-        omap_writeb((omap_readb(uclk->sysc_addr) & ~0x18), uclk->sysc_addr);
-
-        omap1_clk_disable_generic(clk);
-}
-
-static const struct clkops clkops_uart = {
-        .enable         = &omap1_clk_enable_uart_functional,
-        .disable        = &omap1_clk_disable_uart_functional,
-};
-
 static void omap1_clk_allow_idle(struct clk *clk)
 {
         struct arm_idlect1_clk * iclk = (struct arm_idlect1_clk *)clk;
@@ -344,7 +181,7 @@ static int calc_dsor_exp(struct clk *clk, unsigned long rate)
         return dsor_exp;
 }
 
-static unsigned long omap1_ckctl_recalc(struct clk *clk)
+unsigned long omap1_ckctl_recalc(struct clk *clk)
 {
         /* Calculate divisor encoded as 2-bit exponent */
         int dsor = 1 << (3 & (omap_readw(ARM_CKCTL) >> clk->rate_offset));
@@ -352,7 +189,7 @@ static unsigned long omap1_ckctl_recalc(struct clk *clk)
         return clk->parent->rate / dsor;
 }
 
-static unsigned long omap1_ckctl_recalc_dsp_domain(struct clk *clk)
+unsigned long omap1_ckctl_recalc_dsp_domain(struct clk *clk)
 {
         int dsor;
 
@@ -363,28 +200,29 @@ static unsigned long omap1_ckctl_recalc_dsp_domain(struct clk *clk)
          * Note that DSP_CKCTL virt addr = phys addr, so
          * we must use __raw_readw() instead of omap_readw().
          */
-        omap1_clk_enable(&api_ck.clk);
+        omap1_clk_enable(api_ck_p);
         dsor = 1 << (3 & (__raw_readw(DSP_CKCTL) >> clk->rate_offset));
-        omap1_clk_disable(&api_ck.clk);
+        omap1_clk_disable(api_ck_p);
 
         return clk->parent->rate / dsor;
 }
 
 /* MPU virtual clock functions */
-static int omap1_select_table_rate(struct clk * clk, unsigned long rate)
+int omap1_select_table_rate(struct clk *clk, unsigned long rate)
 {
         /* Find the highest supported frequency <= rate and switch to it */
         struct mpu_rate * ptr;
+        unsigned long dpll1_rate, ref_rate;
 
-        if (clk != &virtual_ck_mpu)
-                return -EINVAL;
+        dpll1_rate = clk_get_rate(ck_dpll1_p);
+        ref_rate = clk_get_rate(ck_ref_p);
 
-        for (ptr = rate_table; ptr->rate; ptr++) {
-                if (ptr->xtal != ck_ref.rate)
+        for (ptr = omap1_rate_table; ptr->rate; ptr++) {
+                if (ptr->xtal != ref_rate)
                         continue;
 
                 /* DPLL1 cannot be reprogrammed without risking system crash */
-                if (likely(ck_dpll1.rate!=0) && ptr->pll_rate != ck_dpll1.rate)
+                if (likely(dpll1_rate != 0) && ptr->pll_rate != dpll1_rate)
                         continue;
 
                 /* Can check only after xtal frequency check */
@@ -405,11 +243,13 @@ static int omap1_select_table_rate(struct clk * clk, unsigned long rate)
         else
                 omap_sram_reprogram_clock(ptr->dpllctl_val, ptr->ckctl_val);
 
-        ck_dpll1.rate = ptr->pll_rate;
+        /* XXX Do we need to recalculate the tree below DPLL1 at this point? */
+        ck_dpll1_p->rate = ptr->pll_rate;
+
         return 0;
 }
 
-static int omap1_clk_set_rate_dsp_domain(struct clk *clk, unsigned long rate)
+int omap1_clk_set_rate_dsp_domain(struct clk *clk, unsigned long rate)
 {
         int dsor_exp;
         u16 regval;
@@ -429,7 +269,7 @@ static int omap1_clk_set_rate_dsp_domain(struct clk *clk, unsigned long rate)
         return 0;
 }
 
-static long omap1_clk_round_rate_ckctl_arm(struct clk *clk, unsigned long rate)
+long omap1_clk_round_rate_ckctl_arm(struct clk *clk, unsigned long rate)
 {
         int dsor_exp = calc_dsor_exp(clk, rate);
         if (dsor_exp < 0)
@@ -439,7 +279,7 @@ static long omap1_clk_round_rate_ckctl_arm(struct clk *clk, unsigned long rate)
         return clk->parent->rate / (1 << dsor_exp);
 }
 
-static int omap1_clk_set_rate_ckctl_arm(struct clk *clk, unsigned long rate)
+int omap1_clk_set_rate_ckctl_arm(struct clk *clk, unsigned long rate)
 {
         int dsor_exp;
         u16 regval;
@@ -459,19 +299,19 @@ static int omap1_clk_set_rate_ckctl_arm(struct clk *clk, unsigned long rate)
         return 0;
 }
 
-static long omap1_round_to_table_rate(struct clk * clk, unsigned long rate)
+long omap1_round_to_table_rate(struct clk *clk, unsigned long rate)
 {
         /* Find the highest supported frequency <= rate */
         struct mpu_rate * ptr;
-        long  highest_rate;
+        long highest_rate;
+        unsigned long ref_rate;
 
-        if (clk != &virtual_ck_mpu)
-                return -EINVAL;
+        ref_rate = clk_get_rate(ck_ref_p);
 
         highest_rate = -EINVAL;
 
-        for (ptr = rate_table; ptr->rate; ptr++) {
-                if (ptr->xtal != ck_ref.rate)
+        for (ptr = omap1_rate_table; ptr->rate; ptr++) {
+                if (ptr->xtal != ref_rate)
                         continue;
 
                 highest_rate = ptr->rate;
@@ -506,8 +346,8 @@ static unsigned calc_ext_dsor(unsigned long rate)
         return dsor;
 }
 
-/* Only needed on 1510 */
-static int omap1_set_uart_rate(struct clk * clk, unsigned long rate)
+/* XXX Only needed on 1510 */
+int omap1_set_uart_rate(struct clk *clk, unsigned long rate)
 {
         unsigned int val;
 
@@ -525,7 +365,7 @@ static int omap1_set_uart_rate(struct clk * clk, unsigned long rate)
 }
 
 /* External clock (MCLK & BCLK) functions */
-static int omap1_set_ext_clk_rate(struct clk * clk, unsigned long rate)
+int omap1_set_ext_clk_rate(struct clk *clk, unsigned long rate)
 {
         unsigned dsor;
         __u16 ratio_bits;
@@ -543,7 +383,7 @@ static int omap1_set_ext_clk_rate(struct clk * clk, unsigned long rate)
         return 0;
 }
 
-static int omap1_set_sossi_rate(struct clk *clk, unsigned long rate)
+int omap1_set_sossi_rate(struct clk *clk, unsigned long rate)
 {
         u32 l;
         int div;
@@ -566,12 +406,12 @@ static int omap1_set_sossi_rate(struct clk *clk, unsigned long rate)
         return 0;
 }
 
-static long omap1_round_ext_clk_rate(struct clk * clk, unsigned long rate)
+long omap1_round_ext_clk_rate(struct clk *clk, unsigned long rate)
 {
         return 96000000 / calc_ext_dsor(rate);
 }
 
-static void omap1_init_ext_clk(struct clk * clk)
+void omap1_init_ext_clk(struct clk *clk)
 {
         unsigned dsor;
         __u16 ratio_bits;
@@ -589,7 +429,7 @@ static void omap1_init_ext_clk(struct clk * clk)
         clk-> rate = 96000000 / dsor;
 }
 
-static int omap1_clk_enable(struct clk *clk)
+int omap1_clk_enable(struct clk *clk)
 {
         int ret = 0;
 
@@ -617,7 +457,7 @@ err:
         return ret;
 }
 
-static void omap1_clk_disable(struct clk *clk)
+void omap1_clk_disable(struct clk *clk)
 {
         if (clk->usecount > 0 && !(--clk->usecount)) {
                 clk->ops->disable(clk);
@@ -672,12 +512,70 @@ static void omap1_clk_disable_generic(struct clk *clk)
         }
 }
 
-static const struct clkops clkops_generic = {
-        .enable         = &omap1_clk_enable_generic,
-        .disable        = &omap1_clk_disable_generic,
+const struct clkops clkops_generic = {
+        .enable         = omap1_clk_enable_generic,
+        .disable        = omap1_clk_disable_generic,
+};
+
+static int omap1_clk_enable_dsp_domain(struct clk *clk)
+{
+        int retval;
+
+        retval = omap1_clk_enable(api_ck_p);
+        if (!retval) {
+                retval = omap1_clk_enable_generic(clk);
+                omap1_clk_disable(api_ck_p);
+        }
+
+        return retval;
+}
+
+static void omap1_clk_disable_dsp_domain(struct clk *clk)
+{
+        if (omap1_clk_enable(api_ck_p) == 0) {
+                omap1_clk_disable_generic(clk);
+                omap1_clk_disable(api_ck_p);
+        }
+}
+
+const struct clkops clkops_dspck = {
+        .enable         = omap1_clk_enable_dsp_domain,
+        .disable        = omap1_clk_disable_dsp_domain,
+};
+
+static int omap1_clk_enable_uart_functional(struct clk *clk)
+{
+        int ret;
+        struct uart_clk *uclk;
+
+        ret = omap1_clk_enable_generic(clk);
+        if (ret == 0) {
+                /* Set smart idle acknowledgement mode */
+                uclk = (struct uart_clk *)clk;
+                omap_writeb((omap_readb(uclk->sysc_addr) & ~0x10) | 8,
+                            uclk->sysc_addr);
+        }
+
+        return ret;
+}
+
+static void omap1_clk_disable_uart_functional(struct clk *clk)
+{
+        struct uart_clk *uclk;
+
+        /* Set force idle acknowledgement mode */
+        uclk = (struct uart_clk *)clk;
+        omap_writeb((omap_readb(uclk->sysc_addr) & ~0x18), uclk->sysc_addr);
+
+        omap1_clk_disable_generic(clk);
+}
+
+const struct clkops clkops_uart = {
+        .enable         = omap1_clk_enable_uart_functional,
+        .disable        = omap1_clk_disable_uart_functional,
 };
 
-static long omap1_clk_round_rate(struct clk *clk, unsigned long rate)
+long omap1_clk_round_rate(struct clk *clk, unsigned long rate)
 {
         if (clk->flags & RATE_FIXED)
                 return clk->rate;
@@ -688,7 +586,7 @@ static long omap1_clk_round_rate(struct clk *clk, unsigned long rate)
         return clk->rate;
 }
 
-static int omap1_clk_set_rate(struct clk *clk, unsigned long rate)
+int omap1_clk_set_rate(struct clk *clk, unsigned long rate)
 {
         int  ret = -EINVAL;
 
@@ -703,7 +601,7 @@ static int omap1_clk_set_rate(struct clk *clk, unsigned long rate)
 
 #ifdef CONFIG_OMAP_RESET_CLOCKS
 
-static void __init omap1_clk_disable_unused(struct clk *clk)
+void __init omap1_clk_disable_unused(struct clk *clk)
 {
         __u32 regval32;
 
@@ -724,184 +622,9 @@ static void __init omap1_clk_disable_unused(struct clk *clk)
         if ((regval32 & (1 << clk->enable_bit)) == 0)
                 return;
 
-        /* FIXME: This clock seems to be necessary but no-one
-         * has asked for its activation. */
-        if (clk == &tc2_ck              /* FIX: pm.c (SRAM), CCP, Camera */
-            || clk == &ck_dpll1out.clk  /* FIX: SoSSI, SSR */
-            || clk == &arm_gpio_ck      /* FIX: GPIO code for 1510 */
-                ) {
-                printk(KERN_INFO "FIXME: Clock \"%s\" seems unused\n",
-                       clk->name);
-                return;
-        }
-
         printk(KERN_INFO "Disabling unused clock \"%s\"... ", clk->name);
         clk->ops->disable(clk);
         printk(" done\n");
 }
 
-#else
-#define omap1_clk_disable_unused        NULL
 #endif
-
-static struct clk_functions omap1_clk_functions = {
-        .clk_enable             = omap1_clk_enable,
-        .clk_disable            = omap1_clk_disable,
-        .clk_round_rate         = omap1_clk_round_rate,
-        .clk_set_rate           = omap1_clk_set_rate,
-        .clk_disable_unused     = omap1_clk_disable_unused,
-};
-
-int __init omap1_clk_init(void)
-{
-        struct omap_clk *c;
-        const struct omap_clock_config *info;
-        int crystal_type = 0; /* Default 12 MHz */
-        u32 reg, cpu_mask;
-
-#ifdef CONFIG_DEBUG_LL
-        /* Resets some clocks that may be left on from bootloader,
-         * but leaves serial clocks on.
-         */
-        omap_writel(0x3 << 29, MOD_CONF_CTRL_0);
-#endif
-
-        /* USB_REQ_EN will be disabled later if necessary (usb_dc_ck) */
-        reg = omap_readw(SOFT_REQ_REG) & (1 << 4);
-        omap_writew(reg, SOFT_REQ_REG);
-        if (!cpu_is_omap15xx())
-                omap_writew(0, SOFT_REQ_REG2);
-
-        clk_init(&omap1_clk_functions);
-
-        /* By default all idlect1 clocks are allowed to idle */
-        arm_idlect1_mask = ~0;
-
-        for (c = omap_clks; c < omap_clks + ARRAY_SIZE(omap_clks); c++)
-                clk_preinit(c->lk.clk);
-
-        cpu_mask = 0;
-        if (cpu_is_omap16xx())
-                cpu_mask |= CK_16XX;
-        if (cpu_is_omap1510())
-                cpu_mask |= CK_1510;
-        if (cpu_is_omap7xx())
-                cpu_mask |= CK_7XX;
-        if (cpu_is_omap310())
-                cpu_mask |= CK_310;
-
-        for (c = omap_clks; c < omap_clks + ARRAY_SIZE(omap_clks); c++)
-                if (c->cpu & cpu_mask) {
-                        clkdev_add(&c->lk);
-                        clk_register(c->lk.clk);
-                }
-
-        info = omap_get_config(OMAP_TAG_CLOCK, struct omap_clock_config);
-        if (info != NULL) {
-                if (!cpu_is_omap15xx())
-                        crystal_type = info->system_clock_type;
-        }
-
-#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
-        ck_ref.rate = 13000000;
-#elif defined(CONFIG_ARCH_OMAP16XX)
-        if (crystal_type == 2)
-                ck_ref.rate = 19200000;
-#endif
-
-        printk("Clocks: ARM_SYSST: 0x%04x DPLL_CTL: 0x%04x ARM_CKCTL: 0x%04x\n",
-               omap_readw(ARM_SYSST), omap_readw(DPLL_CTL),
-               omap_readw(ARM_CKCTL));
-
-        /* We want to be in syncronous scalable mode */
-        omap_writew(0x1000, ARM_SYSST);
-
-#ifdef CONFIG_OMAP_CLOCKS_SET_BY_BOOTLOADER
-        /* Use values set by bootloader. Determine PLL rate and recalculate
-         * dependent clocks as if kernel had changed PLL or divisors.
-         */
-        {
-                unsigned pll_ctl_val = omap_readw(DPLL_CTL);
-
-                ck_dpll1.rate = ck_ref.rate; /* Base xtal rate */
-                if (pll_ctl_val & 0x10) {
-                        /* PLL enabled, apply multiplier and divisor */
-                        if (pll_ctl_val & 0xf80)
-                                ck_dpll1.rate *= (pll_ctl_val & 0xf80) >> 7;
-                        ck_dpll1.rate /= ((pll_ctl_val & 0x60) >> 5) + 1;
-                } else {
-                        /* PLL disabled, apply bypass divisor */
-                        switch (pll_ctl_val & 0xc) {
-                        case 0:
-                                break;
-                        case 0x4:
-                                ck_dpll1.rate /= 2;
-                                break;
-                        default:
-                                ck_dpll1.rate /= 4;
-                                break;
-                        }
-                }
-        }
-#else
-        /* Find the highest supported frequency and enable it */
-        if (omap1_select_table_rate(&virtual_ck_mpu, ~0)) {
-                printk(KERN_ERR "System frequencies not set. Check your config.\n");
-                /* Guess sane values (60MHz) */
-                omap_writew(0x2290, DPLL_CTL);
-                omap_writew(cpu_is_omap7xx() ? 0x3005 : 0x1005, ARM_CKCTL);
-                ck_dpll1.rate = 60000000;
-        }
-#endif
-        propagate_rate(&ck_dpll1);
-        /* Cache rates for clocks connected to ck_ref (not dpll1) */
-        propagate_rate(&ck_ref);
-        printk(KERN_INFO "Clocking rate (xtal/DPLL1/MPU): "
-                "%ld.%01ld/%ld.%01ld/%ld.%01ld MHz\n",
-               ck_ref.rate / 1000000, (ck_ref.rate / 100000) % 10,
-               ck_dpll1.rate / 1000000, (ck_dpll1.rate / 100000) % 10,
-               arm_ck.rate / 1000000, (arm_ck.rate / 100000) % 10);
-
-#if defined(CONFIG_MACH_OMAP_PERSEUS2) || defined(CONFIG_MACH_OMAP_FSAMPLE)
-        /* Select slicer output as OMAP input clock */
-        omap_writew(omap_readw(OMAP7XX_PCC_UPLD_CTRL) & ~0x1, OMAP7XX_PCC_UPLD_CTRL);
-#endif
-
-        /* Amstrad Delta wants BCLK high when inactive */
-        if (machine_is_ams_delta())
-                omap_writel(omap_readl(ULPD_CLOCK_CTRL) |
-                                (1 << SDW_MCLK_INV_BIT),
-                                ULPD_CLOCK_CTRL);
-
-        /* Turn off DSP and ARM_TIMXO. Make sure ARM_INTHCK is not divided */
-        /* (on 730, bit 13 must not be cleared) */
-        if (cpu_is_omap7xx())
-                omap_writew(omap_readw(ARM_CKCTL) & 0x2fff, ARM_CKCTL);
-        else
-                omap_writew(omap_readw(ARM_CKCTL) & 0x0fff, ARM_CKCTL);
-
-        /* Put DSP/MPUI into reset until needed */
-        omap_writew(0, ARM_RSTCT1);
-        omap_writew(1, ARM_RSTCT2);
-        omap_writew(0x400, ARM_IDLECT1);
-
-        /*
-         * According to OMAP5910 Erratum SYS_DMA_1, bit DMACK_REQ (bit 8)
-         * of the ARM_IDLECT2 register must be set to zero. The power-on
-         * default value of this bit is one.
-         */
-        omap_writew(0x0000, ARM_IDLECT2);       /* Turn LCD clock off also */
-
-        /*
-         * Only enable those clocks we will need, let the drivers
-         * enable other clocks as necessary
-         */
-        clk_enable(&armper_ck.clk);
-        clk_enable(&armxor_ck.clk);
-        clk_enable(&armtim_ck.clk); /* This should be done by timer code */
-
-        if (cpu_is_omap15xx())
-                clk_enable(&arm_gpio_ck);
-
-        return 0;
-}
diff --git a/arch/arm/mach-omap1/clock.h b/arch/arm/mach-omap1/clock.h
index 29ffa97dc7f3..a4190afb8614 100644
--- a/arch/arm/mach-omap1/clock.h
+++ b/arch/arm/mach-omap1/clock.h
@@ -1,7 +1,7 @@
 /*
  *  linux/arch/arm/mach-omap1/clock.h
  *
- *  Copyright (C) 2004 - 2005 Nokia corporation
+ *  Copyright (C) 2004 - 2005, 2009 Nokia corporation
  *  Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
  *  Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc
  *
@@ -13,30 +13,36 @@
 #ifndef __ARCH_ARM_MACH_OMAP1_CLOCK_H
 #define __ARCH_ARM_MACH_OMAP1_CLOCK_H
 
-static unsigned long omap1_ckctl_recalc(struct clk *clk);
-static unsigned long omap1_watchdog_recalc(struct clk *clk);
-static int omap1_set_sossi_rate(struct clk *clk, unsigned long rate);
-static unsigned long omap1_sossi_recalc(struct clk *clk);
-static unsigned long omap1_ckctl_recalc_dsp_domain(struct clk *clk);
-static int omap1_clk_set_rate_dsp_domain(struct clk * clk, unsigned long rate);
-static int omap1_set_uart_rate(struct clk * clk, unsigned long rate);
-static unsigned long omap1_uart_recalc(struct clk *clk);
-static int omap1_set_ext_clk_rate(struct clk * clk, unsigned long rate);
-static long omap1_round_ext_clk_rate(struct clk * clk, unsigned long rate);
-static void omap1_init_ext_clk(struct clk * clk);
-static int omap1_select_table_rate(struct clk * clk, unsigned long rate);
-static long omap1_round_to_table_rate(struct clk * clk, unsigned long rate);
-
-static int omap1_clk_set_rate_ckctl_arm(struct clk *clk, unsigned long rate);
-static long omap1_clk_round_rate_ckctl_arm(struct clk *clk, unsigned long rate);
-
-struct mpu_rate {
-        unsigned long           rate;
-        unsigned long           xtal;
-        unsigned long           pll_rate;
-        __u16                   ckctl_val;
-        __u16                   dpllctl_val;
-};
+#include <linux/clk.h>
+
+#include <plat/clock.h>
+
+extern int __init omap1_clk_init(void);
+extern int omap1_clk_enable(struct clk *clk);
+extern void omap1_clk_disable(struct clk *clk);
+extern long omap1_clk_round_rate(struct clk *clk, unsigned long rate);
+extern int omap1_clk_set_rate(struct clk *clk, unsigned long rate);
+extern unsigned long omap1_ckctl_recalc(struct clk *clk);
+extern int omap1_set_sossi_rate(struct clk *clk, unsigned long rate);
+extern unsigned long omap1_sossi_recalc(struct clk *clk);
+extern unsigned long omap1_ckctl_recalc_dsp_domain(struct clk *clk);
+extern int omap1_clk_set_rate_dsp_domain(struct clk *clk, unsigned long rate);
+extern int omap1_set_uart_rate(struct clk *clk, unsigned long rate);
+extern unsigned long omap1_uart_recalc(struct clk *clk);
+extern int omap1_set_ext_clk_rate(struct clk *clk, unsigned long rate);
+extern long omap1_round_ext_clk_rate(struct clk *clk, unsigned long rate);
+extern void omap1_init_ext_clk(struct clk *clk);
+extern int omap1_select_table_rate(struct clk *clk, unsigned long rate);
+extern long omap1_round_to_table_rate(struct clk *clk, unsigned long rate);
+extern int omap1_clk_set_rate_ckctl_arm(struct clk *clk, unsigned long rate);
+extern long omap1_clk_round_rate_ckctl_arm(struct clk *clk, unsigned long rate);
+extern unsigned long omap1_watchdog_recalc(struct clk *clk);
+
+#ifdef CONFIG_OMAP_RESET_CLOCKS
+extern void __init omap1_clk_disable_unused(struct clk *clk);
+#else
+#define omap1_clk_disable_unused        NULL
+#endif
 
 struct uart_clk {
         struct clk      clk;
@@ -96,596 +102,12 @@ struct arm_idlect1_clk {
 #define SOFT_REQ_REG            0xfffe0834
 #define SOFT_REQ_REG2           0xfffe0880
 
-/*-------------------------------------------------------------------------
- * Omap1 MPU rate table
- *-------------------------------------------------------------------------*/
-static struct mpu_rate rate_table[] = {
-        /* MPU MHz, xtal MHz, dpll1 MHz, CKCTL, DPLL_CTL
-         * NOTE: Comment order here is different from bits in CKCTL value:
-         * armdiv, dspdiv, dspmmu, tcdiv, perdiv, lcddiv
-         */
-#if defined(CONFIG_OMAP_ARM_216MHZ)
-        { 216000000, 12000000, 216000000, 0x050d, 0x2910 }, /* 1/1/2/2/2/8 */
-#endif
-#if defined(CONFIG_OMAP_ARM_195MHZ)
-        { 195000000, 13000000, 195000000, 0x050e, 0x2790 }, /* 1/1/2/2/4/8 */
-#endif
-#if defined(CONFIG_OMAP_ARM_192MHZ)
-        { 192000000, 19200000, 192000000, 0x050f, 0x2510 }, /* 1/1/2/2/8/8 */
-        { 192000000, 12000000, 192000000, 0x050f, 0x2810 }, /* 1/1/2/2/8/8 */
-        {  96000000, 12000000, 192000000, 0x055f, 0x2810 }, /* 2/2/2/2/8/8 */
-        {  48000000, 12000000, 192000000, 0x0baf, 0x2810 }, /* 4/4/4/8/8/8 */
-        {  24000000, 12000000, 192000000, 0x0fff, 0x2810 }, /* 8/8/8/8/8/8 */
-#endif
-#if defined(CONFIG_OMAP_ARM_182MHZ)
-        { 182000000, 13000000, 182000000, 0x050e, 0x2710 }, /* 1/1/2/2/4/8 */
-#endif
-#if defined(CONFIG_OMAP_ARM_168MHZ)
-        { 168000000, 12000000, 168000000, 0x010f, 0x2710 }, /* 1/1/1/2/8/8 */
-#endif
-#if defined(CONFIG_OMAP_ARM_150MHZ)
-        { 150000000, 12000000, 150000000, 0x010a, 0x2cb0 }, /* 1/1/1/2/4/4 */
-#endif
-#if defined(CONFIG_OMAP_ARM_120MHZ)
-        { 120000000, 12000000, 120000000, 0x010a, 0x2510 }, /* 1/1/1/2/4/4 */
-#endif
-#if defined(CONFIG_OMAP_ARM_96MHZ)
-        {  96000000, 12000000,  96000000, 0x0005, 0x2410 }, /* 1/1/1/1/2/2 */
-#endif
-#if defined(CONFIG_OMAP_ARM_60MHZ)
-        {  60000000, 12000000,  60000000, 0x0005, 0x2290 }, /* 1/1/1/1/2/2 */
-#endif
-#if defined(CONFIG_OMAP_ARM_30MHZ)
-        {  30000000, 12000000,  60000000, 0x0555, 0x2290 }, /* 2/2/2/2/2/2 */
-#endif
-        { 0, 0, 0, 0, 0 },
-};
-
-/*-------------------------------------------------------------------------
- * Omap1 clocks
- *-------------------------------------------------------------------------*/
-
-static struct clk ck_ref = {
-        .name           = "ck_ref",
-        .ops            = &clkops_null,
-        .rate           = 12000000,
-};
-
-static struct clk ck_dpll1 = {
-        .name           = "ck_dpll1",
-        .ops            = &clkops_null,
-        .parent         = &ck_ref,
-};
-
-static struct arm_idlect1_clk ck_dpll1out = {
-        .clk = {
-                .name           = "ck_dpll1out",
-                .ops            = &clkops_generic,
-                .parent         = &ck_dpll1,
-                .flags          = CLOCK_IDLE_CONTROL | ENABLE_REG_32BIT,
-                .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT2),
-                .enable_bit     = EN_CKOUT_ARM,
-                .recalc         = &followparent_recalc,
-        },
-        .idlect_shift   = 12,
-};
-
-static struct clk sossi_ck = {
-        .name           = "ck_sossi",
-        .ops            = &clkops_generic,
-        .parent         = &ck_dpll1out.clk,
-        .flags          = CLOCK_NO_IDLE_PARENT | ENABLE_REG_32BIT,
-        .enable_reg     = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_1),
-        .enable_bit     = 16,
-        .recalc         = &omap1_sossi_recalc,
-        .set_rate       = &omap1_set_sossi_rate,
-};
-
-static struct clk arm_ck = {
-        .name           = "arm_ck",
-        .ops            = &clkops_null,
-        .parent         = &ck_dpll1,
-        .rate_offset    = CKCTL_ARMDIV_OFFSET,
-        .recalc         = &omap1_ckctl_recalc,
-        .round_rate     = omap1_clk_round_rate_ckctl_arm,
-        .set_rate       = omap1_clk_set_rate_ckctl_arm,
-};
-
-static struct arm_idlect1_clk armper_ck = {
-        .clk = {
-                .name           = "armper_ck",
-                .ops            = &clkops_generic,
-                .parent         = &ck_dpll1,
-                .flags          = CLOCK_IDLE_CONTROL,
-                .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT2),
-                .enable_bit     = EN_PERCK,
-                .rate_offset    = CKCTL_PERDIV_OFFSET,
-                .recalc         = &omap1_ckctl_recalc,
-                .round_rate     = omap1_clk_round_rate_ckctl_arm,
-                .set_rate       = omap1_clk_set_rate_ckctl_arm,
-        },
-        .idlect_shift   = 2,
-};
-
-static struct clk arm_gpio_ck = {
-        .name           = "arm_gpio_ck",
-        .ops            = &clkops_generic,
-        .parent         = &ck_dpll1,
-        .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT2),
-        .enable_bit     = EN_GPIOCK,
-        .recalc         = &followparent_recalc,
-};
-
-static struct arm_idlect1_clk armxor_ck = {
-        .clk = {
-                .name           = "armxor_ck",
-                .ops            = &clkops_generic,
-                .parent         = &ck_ref,
-                .flags          = CLOCK_IDLE_CONTROL,
-                .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT2),
-                .enable_bit     = EN_XORPCK,
-                .recalc         = &followparent_recalc,
-        },
-        .idlect_shift   = 1,
-};
-
-static struct arm_idlect1_clk armtim_ck = {
-        .clk = {
-                .name           = "armtim_ck",
-                .ops            = &clkops_generic,
-                .parent         = &ck_ref,
-                .flags          = CLOCK_IDLE_CONTROL,
-                .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT2),
-                .enable_bit     = EN_TIMCK,
-                .recalc         = &followparent_recalc,
-        },
-        .idlect_shift   = 9,
-};
-
-static struct arm_idlect1_clk armwdt_ck = {
-        .clk = {
-                .name           = "armwdt_ck",
-                .ops            = &clkops_generic,
-                .parent         = &ck_ref,
-                .flags          = CLOCK_IDLE_CONTROL,
-                .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT2),
-                .enable_bit     = EN_WDTCK,
-                .recalc         = &omap1_watchdog_recalc,
-        },
-        .idlect_shift   = 0,
-};
-
-static struct clk arminth_ck16xx = {
-        .name           = "arminth_ck",
-        .ops            = &clkops_null,
-        .parent         = &arm_ck,
-        .recalc         = &followparent_recalc,
-        /* Note: On 16xx the frequency can be divided by 2 by programming
-         * ARM_CKCTL:ARM_INTHCK_SEL(14) to 1
-         *
-         * 1510 version is in TC clocks.
-         */
-};
-
-static struct clk dsp_ck = {
-        .name           = "dsp_ck",
-        .ops            = &clkops_generic,
-        .parent         = &ck_dpll1,
-        .enable_reg     = OMAP1_IO_ADDRESS(ARM_CKCTL),
-        .enable_bit     = EN_DSPCK,
-        .rate_offset    = CKCTL_DSPDIV_OFFSET,
-        .recalc         = &omap1_ckctl_recalc,
-        .round_rate     = omap1_clk_round_rate_ckctl_arm,
-        .set_rate       = omap1_clk_set_rate_ckctl_arm,
-};
-
-static struct clk dspmmu_ck = {
-        .name           = "dspmmu_ck",
-        .ops            = &clkops_null,
-        .parent         = &ck_dpll1,
-        .rate_offset    = CKCTL_DSPMMUDIV_OFFSET,
-        .recalc         = &omap1_ckctl_recalc,
-        .round_rate     = omap1_clk_round_rate_ckctl_arm,
-        .set_rate       = omap1_clk_set_rate_ckctl_arm,
-};
-
-static struct clk dspper_ck = {
-        .name           = "dspper_ck",
-        .ops            = &clkops_dspck,
-        .parent         = &ck_dpll1,
-        .enable_reg     = DSP_IDLECT2,
-        .enable_bit     = EN_PERCK,
-        .rate_offset    = CKCTL_PERDIV_OFFSET,
-        .recalc         = &omap1_ckctl_recalc_dsp_domain,
-        .round_rate     = omap1_clk_round_rate_ckctl_arm,
-        .set_rate       = &omap1_clk_set_rate_dsp_domain,
-};
-
-static struct clk dspxor_ck = {
-        .name           = "dspxor_ck",
-        .ops            = &clkops_dspck,
-        .parent         = &ck_ref,
-        .enable_reg     = DSP_IDLECT2,
-        .enable_bit     = EN_XORPCK,
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk dsptim_ck = {
-        .name           = "dsptim_ck",
-        .ops            = &clkops_dspck,
-        .parent         = &ck_ref,
-        .enable_reg     = DSP_IDLECT2,
-        .enable_bit     = EN_DSPTIMCK,
-        .recalc         = &followparent_recalc,
-};
-
-/* Tie ARM_IDLECT1:IDLIF_ARM to this logical clock structure */
-static struct arm_idlect1_clk tc_ck = {
-        .clk = {
-                .name           = "tc_ck",
-                .ops            = &clkops_null,
-                .parent         = &ck_dpll1,
-                .flags          = CLOCK_IDLE_CONTROL,
-                .rate_offset    = CKCTL_TCDIV_OFFSET,
-                .recalc         = &omap1_ckctl_recalc,
-                .round_rate     = omap1_clk_round_rate_ckctl_arm,
-                .set_rate       = omap1_clk_set_rate_ckctl_arm,
-        },
-        .idlect_shift   = 6,
-};
-
-static struct clk arminth_ck1510 = {
-        .name           = "arminth_ck",
-        .ops            = &clkops_null,
-        .parent         = &tc_ck.clk,
-        .recalc         = &followparent_recalc,
-        /* Note: On 1510 the frequency follows TC_CK
-         *
-         * 16xx version is in MPU clocks.
-         */
-};
-
-static struct clk tipb_ck = {
-        /* No-idle controlled by "tc_ck" */
-        .name           = "tipb_ck",
-        .ops            = &clkops_null,
-        .parent         = &tc_ck.clk,
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk l3_ocpi_ck = {
-        /* No-idle controlled by "tc_ck" */
-        .name           = "l3_ocpi_ck",
-        .ops            = &clkops_generic,
-        .parent         = &tc_ck.clk,
-        .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT3),
-        .enable_bit     = EN_OCPI_CK,
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk tc1_ck = {
-        .name           = "tc1_ck",
-        .ops            = &clkops_generic,
-        .parent         = &tc_ck.clk,
-        .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT3),
-        .enable_bit     = EN_TC1_CK,
-        .recalc         = &followparent_recalc,
-};
+extern __u32 arm_idlect1_mask;
+extern struct clk *api_ck_p, *ck_dpll1_p, *ck_ref_p;
 
-static struct clk tc2_ck = {
-        .name           = "tc2_ck",
-        .ops            = &clkops_generic,
-        .parent         = &tc_ck.clk,
-        .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT3),
-        .enable_bit     = EN_TC2_CK,
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk dma_ck = {
-        /* No-idle controlled by "tc_ck" */
-        .name           = "dma_ck",
-        .ops            = &clkops_null,
-        .parent         = &tc_ck.clk,
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk dma_lcdfree_ck = {
-        .name           = "dma_lcdfree_ck",
-        .ops            = &clkops_null,
-        .parent         = &tc_ck.clk,
-        .recalc         = &followparent_recalc,
-};
-
-static struct arm_idlect1_clk api_ck = {
-        .clk = {
-                .name           = "api_ck",
-                .ops            = &clkops_generic,
-                .parent         = &tc_ck.clk,
-                .flags          = CLOCK_IDLE_CONTROL,
-                .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT2),
-                .enable_bit     = EN_APICK,
-                .recalc         = &followparent_recalc,
-        },
-        .idlect_shift   = 8,
-};
-
-static struct arm_idlect1_clk lb_ck = {
-        .clk = {
-                .name           = "lb_ck",
-                .ops            = &clkops_generic,
-                .parent         = &tc_ck.clk,
-                .flags          = CLOCK_IDLE_CONTROL,
-                .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT2),
-                .enable_bit     = EN_LBCK,
-                .recalc         = &followparent_recalc,
-        },
-        .idlect_shift   = 4,
-};
-
-static struct clk rhea1_ck = {
-        .name           = "rhea1_ck",
-        .ops            = &clkops_null,
-        .parent         = &tc_ck.clk,
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk rhea2_ck = {
-        .name           = "rhea2_ck",
-        .ops            = &clkops_null,
-        .parent         = &tc_ck.clk,
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk lcd_ck_16xx = {
-        .name           = "lcd_ck",
-        .ops            = &clkops_generic,
-        .parent         = &ck_dpll1,
-        .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT2),
-        .enable_bit     = EN_LCDCK,
-        .rate_offset    = CKCTL_LCDDIV_OFFSET,
-        .recalc         = &omap1_ckctl_recalc,
-        .round_rate     = omap1_clk_round_rate_ckctl_arm,
-        .set_rate       = omap1_clk_set_rate_ckctl_arm,
-};
-
-static struct arm_idlect1_clk lcd_ck_1510 = {
-        .clk = {
-                .name           = "lcd_ck",
-                .ops            = &clkops_generic,
-                .parent         = &ck_dpll1,
-                .flags          = CLOCK_IDLE_CONTROL,
-                .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT2),
-                .enable_bit     = EN_LCDCK,
-                .rate_offset    = CKCTL_LCDDIV_OFFSET,
-                .recalc         = &omap1_ckctl_recalc,
-                .round_rate     = omap1_clk_round_rate_ckctl_arm,
-                .set_rate       = omap1_clk_set_rate_ckctl_arm,
-        },
-        .idlect_shift   = 3,
-};
-
-static struct clk uart1_1510 = {
-        .name           = "uart1_ck",
-        .ops            = &clkops_null,
-        /* Direct from ULPD, no real parent */
-        .parent         = &armper_ck.clk,
-        .rate           = 12000000,
-        .flags          = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
-        .enable_reg     = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
-        .enable_bit     = 29,   /* Chooses between 12MHz and 48MHz */
-        .set_rate       = &omap1_set_uart_rate,
-        .recalc         = &omap1_uart_recalc,
-};
-
-static struct uart_clk uart1_16xx = {
-        .clk    = {
-                .name           = "uart1_ck",
-                .ops            = &clkops_uart,
-                /* Direct from ULPD, no real parent */
-                .parent         = &armper_ck.clk,
-                .rate           = 48000000,
-                .flags          = RATE_FIXED | ENABLE_REG_32BIT |
-                                  CLOCK_NO_IDLE_PARENT,
-                .enable_reg     = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
-                .enable_bit     = 29,
-        },
-        .sysc_addr      = 0xfffb0054,
-};
-
-static struct clk uart2_ck = {
-        .name           = "uart2_ck",
-        .ops            = &clkops_null,
-        /* Direct from ULPD, no real parent */
-        .parent         = &armper_ck.clk,
-        .rate           = 12000000,
-        .flags          = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
-        .enable_reg     = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
-        .enable_bit     = 30,   /* Chooses between 12MHz and 48MHz */
-        .set_rate       = &omap1_set_uart_rate,
-        .recalc         = &omap1_uart_recalc,
-};
-
-static struct clk uart3_1510 = {
-        .name           = "uart3_ck",
-        .ops            = &clkops_null,
-        /* Direct from ULPD, no real parent */
-        .parent         = &armper_ck.clk,
-        .rate           = 12000000,
-        .flags          = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
-        .enable_reg     = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
-        .enable_bit     = 31,   /* Chooses between 12MHz and 48MHz */
-        .set_rate       = &omap1_set_uart_rate,
-        .recalc         = &omap1_uart_recalc,
-};
-
-static struct uart_clk uart3_16xx = {
-        .clk    = {
-                .name           = "uart3_ck",
-                .ops            = &clkops_uart,
-                /* Direct from ULPD, no real parent */
-                .parent         = &armper_ck.clk,
-                .rate           = 48000000,
-                .flags          = RATE_FIXED | ENABLE_REG_32BIT |
-                                  CLOCK_NO_IDLE_PARENT,
-                .enable_reg     = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
-                .enable_bit     = 31,
-        },
-        .sysc_addr      = 0xfffb9854,
-};
-
-static struct clk usb_clko = {  /* 6 MHz output on W4_USB_CLKO */
-        .name           = "usb_clko",
-        .ops            = &clkops_generic,
-        /* Direct from ULPD, no parent */
-        .rate           = 6000000,
-        .flags          = RATE_FIXED | ENABLE_REG_32BIT,
-        .enable_reg     = OMAP1_IO_ADDRESS(ULPD_CLOCK_CTRL),
-        .enable_bit     = USB_MCLK_EN_BIT,
-};
-
-static struct clk usb_hhc_ck1510 = {
-        .name           = "usb_hhc_ck",
-        .ops            = &clkops_generic,
-        /* Direct from ULPD, no parent */
-        .rate           = 48000000, /* Actually 2 clocks, 12MHz and 48MHz */
-        .flags          = RATE_FIXED | ENABLE_REG_32BIT,
-        .enable_reg     = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
-        .enable_bit     = USB_HOST_HHC_UHOST_EN,
-};
-
-static struct clk usb_hhc_ck16xx = {
-        .name           = "usb_hhc_ck",
-        .ops            = &clkops_generic,
-        /* Direct from ULPD, no parent */
-        .rate           = 48000000,
-        /* OTG_SYSCON_2.OTG_PADEN == 0 (not 1510-compatible) */
-        .flags          = RATE_FIXED | ENABLE_REG_32BIT,
-        .enable_reg     = OMAP1_IO_ADDRESS(OTG_BASE + 0x08), /* OTG_SYSCON_2 */
-        .enable_bit     = 8 /* UHOST_EN */,
-};
-
-static struct clk usb_dc_ck = {
-        .name           = "usb_dc_ck",
-        .ops            = &clkops_generic,
-        /* Direct from ULPD, no parent */
-        .rate           = 48000000,
-        .flags          = RATE_FIXED,
-        .enable_reg     = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
-        .enable_bit     = 4,
-};
-
-static struct clk usb_dc_ck7xx = {
-        .name           = "usb_dc_ck",
-        .ops            = &clkops_generic,
-        /* Direct from ULPD, no parent */
-        .rate           = 48000000,
-        .flags          = RATE_FIXED,
-        .enable_reg     = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
-        .enable_bit     = 8,
-};
-
-static struct clk mclk_1510 = {
-        .name           = "mclk",
-        .ops            = &clkops_generic,
-        /* Direct from ULPD, no parent. May be enabled by ext hardware. */
-        .rate           = 12000000,
-        .flags          = RATE_FIXED,
-        .enable_reg     = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
-        .enable_bit     = 6,
-};
-
-static struct clk mclk_16xx = {
-        .name           = "mclk",
-        .ops            = &clkops_generic,
-        /* Direct from ULPD, no parent. May be enabled by ext hardware. */
-        .enable_reg     = OMAP1_IO_ADDRESS(COM_CLK_DIV_CTRL_SEL),
-        .enable_bit     = COM_ULPD_PLL_CLK_REQ,
-        .set_rate       = &omap1_set_ext_clk_rate,
-        .round_rate     = &omap1_round_ext_clk_rate,
-        .init           = &omap1_init_ext_clk,
-};
-
-static struct clk bclk_1510 = {
-        .name           = "bclk",
-        .ops            = &clkops_generic,
-        /* Direct from ULPD, no parent. May be enabled by ext hardware. */
-        .rate           = 12000000,
-        .flags          = RATE_FIXED,
-};
-
-static struct clk bclk_16xx = {
-        .name           = "bclk",
-        .ops            = &clkops_generic,
-        /* Direct from ULPD, no parent. May be enabled by ext hardware. */
-        .enable_reg     = OMAP1_IO_ADDRESS(SWD_CLK_DIV_CTRL_SEL),
-        .enable_bit     = SWD_ULPD_PLL_CLK_REQ,
-        .set_rate       = &omap1_set_ext_clk_rate,
-        .round_rate     = &omap1_round_ext_clk_rate,
-        .init           = &omap1_init_ext_clk,
-};
-
-static struct clk mmc1_ck = {
-        .name           = "mmc_ck",
-        .ops            = &clkops_generic,
-        /* Functional clock is direct from ULPD, interface clock is ARMPER */
-        .parent         = &armper_ck.clk,
-        .rate           = 48000000,
-        .flags          = RATE_FIXED | ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
-        .enable_reg     = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
-        .enable_bit     = 23,
-};
-
-static struct clk mmc2_ck = {
-        .name           = "mmc_ck",
-        .id             = 1,
-        .ops            = &clkops_generic,
-        /* Functional clock is direct from ULPD, interface clock is ARMPER */
-        .parent         = &armper_ck.clk,
-        .rate           = 48000000,
-        .flags          = RATE_FIXED | ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
-        .enable_reg     = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
-        .enable_bit     = 20,
-};
-
-static struct clk mmc3_ck = {
-        .name           = "mmc_ck",
-        .id             = 2,
-        .ops            = &clkops_generic,
-        /* Functional clock is direct from ULPD, interface clock is ARMPER */
-        .parent         = &armper_ck.clk,
-        .rate           = 48000000,
-        .flags          = RATE_FIXED | ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
-        .enable_reg     = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
-        .enable_bit     = 12,
-};
-
-static struct clk virtual_ck_mpu = {
-        .name           = "mpu",
-        .ops            = &clkops_null,
-        .parent         = &arm_ck, /* Is smarter alias for */
-        .recalc         = &followparent_recalc,
-        .set_rate       = &omap1_select_table_rate,
-        .round_rate     = &omap1_round_to_table_rate,
-};
-
-/* virtual functional clock domain for I2C. Just for making sure that ARMXOR_CK
-remains active during MPU idle whenever this is enabled */
-static struct clk i2c_fck = {
-        .name           = "i2c_fck",
-        .id             = 1,
-        .ops            = &clkops_null,
-        .flags          = CLOCK_NO_IDLE_PARENT,
-        .parent         = &armxor_ck.clk,
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk i2c_ick = {
-        .name           = "i2c_ick",
-        .id             = 1,
-        .ops            = &clkops_null,
-        .flags          = CLOCK_NO_IDLE_PARENT,
-        .parent         = &armper_ck.clk,
-        .recalc         = &followparent_recalc,
-};
+extern const struct clkops clkops_dspck;
+extern const struct clkops clkops_dummy;
+extern const struct clkops clkops_uart;
+extern const struct clkops clkops_generic;
 
 #endif
diff --git a/arch/arm/mach-omap1/clock_data.c b/arch/arm/mach-omap1/clock_data.c
new file mode 100644
index 000000000000..ab995a9c606c
--- /dev/null
+++ b/arch/arm/mach-omap1/clock_data.c
@@ -0,0 +1,843 @@
+/*
+ *  linux/arch/arm/mach-omap1/clock_data.c
+ *
+ *  Copyright (C) 2004 - 2005, 2009 Nokia corporation
+ *  Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
+ *  Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+
+#include <asm/mach-types.h>  /* for machine_is_* */
+
+#include <plat/clock.h>
+#include <plat/cpu.h>
+#include <plat/clkdev_omap.h>
+#include <plat/usb.h>   /* for OTG_BASE */
+
+#include "clock.h"
+
+/*------------------------------------------------------------------------
+ * Omap1 clocks
+ *-------------------------------------------------------------------------*/
+
+/* XXX is this necessary? */
+static struct clk dummy_ck = {
+        .name   = "dummy",
+        .ops    = &clkops_dummy,
+        .flags  = RATE_FIXED,
+};
+
+static struct clk ck_ref = {
+        .name           = "ck_ref",
+        .ops            = &clkops_null,
+        .rate           = 12000000,
+};
+
+static struct clk ck_dpll1 = {
+        .name           = "ck_dpll1",
+        .ops            = &clkops_null,
+        .parent         = &ck_ref,
+};
+
+/*
+ * FIXME: This clock seems to be necessary but no-one has asked for its
+ * activation.  [ FIX: SoSSI, SSR ]
+ */
+static struct arm_idlect1_clk ck_dpll1out = {
+        .clk = {
+                .name           = "ck_dpll1out",
+                .ops            = &clkops_generic,
+                .parent         = &ck_dpll1,
+                .flags          = CLOCK_IDLE_CONTROL | ENABLE_REG_32BIT |
+                                  ENABLE_ON_INIT,
+                .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT2),
+                .enable_bit     = EN_CKOUT_ARM,
+                .recalc         = &followparent_recalc,
+        },
+        .idlect_shift   = 12,
+};
+
+static struct clk sossi_ck = {
+        .name           = "ck_sossi",
+        .ops            = &clkops_generic,
+        .parent         = &ck_dpll1out.clk,
+        .flags          = CLOCK_NO_IDLE_PARENT | ENABLE_REG_32BIT,
+        .enable_reg     = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_1),
+        .enable_bit     = 16,
+        .recalc         = &omap1_sossi_recalc,
+        .set_rate       = &omap1_set_sossi_rate,
+};
+
+static struct clk arm_ck = {
+        .name           = "arm_ck",
+        .ops            = &clkops_null,
+        .parent         = &ck_dpll1,
+        .rate_offset    = CKCTL_ARMDIV_OFFSET,
+        .recalc         = &omap1_ckctl_recalc,
+        .round_rate     = omap1_clk_round_rate_ckctl_arm,
+        .set_rate       = omap1_clk_set_rate_ckctl_arm,
+};
+
+static struct arm_idlect1_clk armper_ck = {
+        .clk = {
+                .name           = "armper_ck",
+                .ops            = &clkops_generic,
+                .parent         = &ck_dpll1,
+                .flags          = CLOCK_IDLE_CONTROL,
+                .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT2),
+                .enable_bit     = EN_PERCK,
+                .rate_offset    = CKCTL_PERDIV_OFFSET,
+                .recalc         = &omap1_ckctl_recalc,
+                .round_rate     = omap1_clk_round_rate_ckctl_arm,
+                .set_rate       = omap1_clk_set_rate_ckctl_arm,
+        },
+        .idlect_shift   = 2,
+};
+
+/*
+ * FIXME: This clock seems to be necessary but no-one has asked for its
+ * activation.  [ GPIO code for 1510 ]
+ */
+static struct clk arm_gpio_ck = {
+        .name           = "arm_gpio_ck",
+        .ops            = &clkops_generic,
+        .parent         = &ck_dpll1,
+        .flags          = ENABLE_ON_INIT,
+        .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT2),
+        .enable_bit     = EN_GPIOCK,
+        .recalc         = &followparent_recalc,
+};
+
+static struct arm_idlect1_clk armxor_ck = {
+        .clk = {
+                .name           = "armxor_ck",
+                .ops            = &clkops_generic,
+                .parent         = &ck_ref,
+                .flags          = CLOCK_IDLE_CONTROL,
+                .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT2),
+                .enable_bit     = EN_XORPCK,
+                .recalc         = &followparent_recalc,
+        },
+        .idlect_shift   = 1,
+};
+
+static struct arm_idlect1_clk armtim_ck = {
+        .clk = {
+                .name           = "armtim_ck",
+                .ops            = &clkops_generic,
+                .parent         = &ck_ref,
+                .flags          = CLOCK_IDLE_CONTROL,
+                .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT2),
+                .enable_bit     = EN_TIMCK,
+                .recalc         = &followparent_recalc,
+        },
+        .idlect_shift   = 9,
+};
+
+static struct arm_idlect1_clk armwdt_ck = {
+        .clk = {
+                .name           = "armwdt_ck",
+                .ops            = &clkops_generic,
+                .parent         = &ck_ref,
+                .flags          = CLOCK_IDLE_CONTROL,
+                .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT2),
+                .enable_bit     = EN_WDTCK,
+                .recalc         = &omap1_watchdog_recalc,
+        },
+        .idlect_shift   = 0,
+};
+
+static struct clk arminth_ck16xx = {
+        .name           = "arminth_ck",
+        .ops            = &clkops_null,
+        .parent         = &arm_ck,
+        .recalc         = &followparent_recalc,
+        /* Note: On 16xx the frequency can be divided by 2 by programming
+         * ARM_CKCTL:ARM_INTHCK_SEL(14) to 1
+         *
+         * 1510 version is in TC clocks.
+         */
+};
+
+static struct clk dsp_ck = {
+        .name           = "dsp_ck",
+        .ops            = &clkops_generic,
+        .parent         = &ck_dpll1,
+        .enable_reg     = OMAP1_IO_ADDRESS(ARM_CKCTL),
+        .enable_bit     = EN_DSPCK,
+        .rate_offset    = CKCTL_DSPDIV_OFFSET,
+        .recalc         = &omap1_ckctl_recalc,
+        .round_rate     = omap1_clk_round_rate_ckctl_arm,
+        .set_rate       = omap1_clk_set_rate_ckctl_arm,
+};
+
+static struct clk dspmmu_ck = {
+        .name           = "dspmmu_ck",
+        .ops            = &clkops_null,
+        .parent         = &ck_dpll1,
+        .rate_offset    = CKCTL_DSPMMUDIV_OFFSET,
+        .recalc         = &omap1_ckctl_recalc,
+        .round_rate     = omap1_clk_round_rate_ckctl_arm,
+        .set_rate       = omap1_clk_set_rate_ckctl_arm,
+};
+
+static struct clk dspper_ck = {
+        .name           = "dspper_ck",
+        .ops            = &clkops_dspck,
+        .parent         = &ck_dpll1,
+        .enable_reg     = DSP_IDLECT2,
+        .enable_bit     = EN_PERCK,
+        .rate_offset    = CKCTL_PERDIV_OFFSET,
+        .recalc         = &omap1_ckctl_recalc_dsp_domain,
+        .round_rate     = omap1_clk_round_rate_ckctl_arm,
+        .set_rate       = &omap1_clk_set_rate_dsp_domain,
+};
+
+static struct clk dspxor_ck = {
+        .name           = "dspxor_ck",
+        .ops            = &clkops_dspck,
+        .parent         = &ck_ref,
+        .enable_reg     = DSP_IDLECT2,
+        .enable_bit     = EN_XORPCK,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk dsptim_ck = {
+        .name           = "dsptim_ck",
+        .ops            = &clkops_dspck,
+        .parent         = &ck_ref,
+        .enable_reg     = DSP_IDLECT2,
+        .enable_bit     = EN_DSPTIMCK,
+        .recalc         = &followparent_recalc,
+};
+
+/* Tie ARM_IDLECT1:IDLIF_ARM to this logical clock structure */
+static struct arm_idlect1_clk tc_ck = {
+        .clk = {
+                .name           = "tc_ck",
+                .ops            = &clkops_null,
+                .parent         = &ck_dpll1,
+                .flags          = CLOCK_IDLE_CONTROL,
+                .rate_offset    = CKCTL_TCDIV_OFFSET,
+                .recalc         = &omap1_ckctl_recalc,
+                .round_rate     = omap1_clk_round_rate_ckctl_arm,
+                .set_rate       = omap1_clk_set_rate_ckctl_arm,
+        },
+        .idlect_shift   = 6,
+};
+
+static struct clk arminth_ck1510 = {
+        .name           = "arminth_ck",
+        .ops            = &clkops_null,
+        .parent         = &tc_ck.clk,
+        .recalc         = &followparent_recalc,
+        /* Note: On 1510 the frequency follows TC_CK
+         *
+         * 16xx version is in MPU clocks.
+         */
+};
+
+static struct clk tipb_ck = {
+        /* No-idle controlled by "tc_ck" */
+        .name           = "tipb_ck",
+        .ops            = &clkops_null,
+        .parent         = &tc_ck.clk,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk l3_ocpi_ck = {
+        /* No-idle controlled by "tc_ck" */
+        .name           = "l3_ocpi_ck",
+        .ops            = &clkops_generic,
+        .parent         = &tc_ck.clk,
+        .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT3),
+        .enable_bit     = EN_OCPI_CK,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk tc1_ck = {
+        .name           = "tc1_ck",
+        .ops            = &clkops_generic,
+        .parent         = &tc_ck.clk,
+        .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT3),
+        .enable_bit     = EN_TC1_CK,
+        .recalc         = &followparent_recalc,
+};
+
+/*
+ * FIXME: This clock seems to be necessary but no-one has asked for its
+ * activation.  [ pm.c (SRAM), CCP, Camera ]
+ */
+static struct clk tc2_ck = {
+        .name           = "tc2_ck",
+        .ops            = &clkops_generic,
+        .parent         = &tc_ck.clk,
+        .flags          = ENABLE_ON_INIT,
+        .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT3),
+        .enable_bit     = EN_TC2_CK,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk dma_ck = {
+        /* No-idle controlled by "tc_ck" */
+        .name           = "dma_ck",
+        .ops            = &clkops_null,
+        .parent         = &tc_ck.clk,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk dma_lcdfree_ck = {
+        .name           = "dma_lcdfree_ck",
+        .ops            = &clkops_null,
+        .parent         = &tc_ck.clk,
+        .recalc         = &followparent_recalc,
+};
+
+static struct arm_idlect1_clk api_ck = {
+        .clk = {
+                .name           = "api_ck",
+                .ops            = &clkops_generic,
+                .parent         = &tc_ck.clk,
+                .flags          = CLOCK_IDLE_CONTROL,
+                .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT2),
+                .enable_bit     = EN_APICK,
+                .recalc         = &followparent_recalc,
+        },
+        .idlect_shift   = 8,
+};
+
+static struct arm_idlect1_clk lb_ck = {
+        .clk = {
+                .name           = "lb_ck",
+                .ops            = &clkops_generic,
+                .parent         = &tc_ck.clk,
+                .flags          = CLOCK_IDLE_CONTROL,
+                .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT2),
+                .enable_bit     = EN_LBCK,
+                .recalc         = &followparent_recalc,
+        },
+        .idlect_shift   = 4,
+};
+
+static struct clk rhea1_ck = {
+        .name           = "rhea1_ck",
+        .ops            = &clkops_null,
+        .parent         = &tc_ck.clk,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk rhea2_ck = {
+        .name           = "rhea2_ck",
+        .ops            = &clkops_null,
+        .parent         = &tc_ck.clk,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk lcd_ck_16xx = {
+        .name           = "lcd_ck",
+        .ops            = &clkops_generic,
+        .parent         = &ck_dpll1,
+        .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT2),
+        .enable_bit     = EN_LCDCK,
+        .rate_offset    = CKCTL_LCDDIV_OFFSET,
+        .recalc         = &omap1_ckctl_recalc,
+        .round_rate     = omap1_clk_round_rate_ckctl_arm,
+        .set_rate       = omap1_clk_set_rate_ckctl_arm,
+};
+
+static struct arm_idlect1_clk lcd_ck_1510 = {
+        .clk = {
+                .name           = "lcd_ck",
+                .ops            = &clkops_generic,
+                .parent         = &ck_dpll1,
+                .flags          = CLOCK_IDLE_CONTROL,
+                .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT2),
+                .enable_bit     = EN_LCDCK,
+                .rate_offset    = CKCTL_LCDDIV_OFFSET,
+                .recalc         = &omap1_ckctl_recalc,
+                .round_rate     = omap1_clk_round_rate_ckctl_arm,
+                .set_rate       = omap1_clk_set_rate_ckctl_arm,
+        },
+        .idlect_shift   = 3,
+};
+
+static struct clk uart1_1510 = {
+        .name           = "uart1_ck",
+        .ops            = &clkops_null,
+        /* Direct from ULPD, no real parent */
+        .parent         = &armper_ck.clk,
+        .rate           = 12000000,
+        .flags          = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
+        .enable_reg     = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
+        .enable_bit     = 29,   /* Chooses between 12MHz and 48MHz */
+        .set_rate       = &omap1_set_uart_rate,
+        .recalc         = &omap1_uart_recalc,
+};
+
+static struct uart_clk uart1_16xx = {
+        .clk    = {
+                .name           = "uart1_ck",
+                .ops            = &clkops_uart,
+                /* Direct from ULPD, no real parent */
+                .parent         = &armper_ck.clk,
+                .rate           = 48000000,
+                .flags          = RATE_FIXED | ENABLE_REG_32BIT |
+                                  CLOCK_NO_IDLE_PARENT,
+                .enable_reg     = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
+                .enable_bit     = 29,
+        },
+        .sysc_addr      = 0xfffb0054,
+};
+
+static struct clk uart2_ck = {
+        .name           = "uart2_ck",
+        .ops            = &clkops_null,
+        /* Direct from ULPD, no real parent */
+        .parent         = &armper_ck.clk,
+        .rate           = 12000000,
+        .flags          = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
+        .enable_reg     = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
+        .enable_bit     = 30,   /* Chooses between 12MHz and 48MHz */
+        .set_rate       = &omap1_set_uart_rate,
+        .recalc         = &omap1_uart_recalc,
+};
+
+static struct clk uart3_1510 = {
+        .name           = "uart3_ck",
+        .ops            = &clkops_null,
+        /* Direct from ULPD, no real parent */
+        .parent         = &armper_ck.clk,
+        .rate           = 12000000,
+        .flags          = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
+        .enable_reg     = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
+        .enable_bit     = 31,   /* Chooses between 12MHz and 48MHz */
+        .set_rate       = &omap1_set_uart_rate,
+        .recalc         = &omap1_uart_recalc,
+};
+
+static struct uart_clk uart3_16xx = {
+        .clk    = {
+                .name           = "uart3_ck",
+                .ops            = &clkops_uart,
+                /* Direct from ULPD, no real parent */
+                .parent         = &armper_ck.clk,
+                .rate           = 48000000,
+                .flags          = RATE_FIXED | ENABLE_REG_32BIT |
+                                  CLOCK_NO_IDLE_PARENT,
+                .enable_reg     = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
+                .enable_bit     = 31,
+        },
+        .sysc_addr      = 0xfffb9854,
+};
+
+static struct clk usb_clko = {  /* 6 MHz output on W4_USB_CLKO */
+        .name           = "usb_clko",
+        .ops            = &clkops_generic,
+        /* Direct from ULPD, no parent */
+        .rate           = 6000000,
+        .flags          = RATE_FIXED | ENABLE_REG_32BIT,
+        .enable_reg     = OMAP1_IO_ADDRESS(ULPD_CLOCK_CTRL),
+        .enable_bit     = USB_MCLK_EN_BIT,
+};
+
+static struct clk usb_hhc_ck1510 = {
+        .name           = "usb_hhc_ck",
+        .ops            = &clkops_generic,
+        /* Direct from ULPD, no parent */
+        .rate           = 48000000, /* Actually 2 clocks, 12MHz and 48MHz */
+        .flags          = RATE_FIXED | ENABLE_REG_32BIT,
+        .enable_reg     = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
+        .enable_bit     = USB_HOST_HHC_UHOST_EN,
+};
+
+static struct clk usb_hhc_ck16xx = {
+        .name           = "usb_hhc_ck",
+        .ops            = &clkops_generic,
+        /* Direct from ULPD, no parent */
+        .rate           = 48000000,
+        /* OTG_SYSCON_2.OTG_PADEN == 0 (not 1510-compatible) */
+        .flags          = RATE_FIXED | ENABLE_REG_32BIT,
+        .enable_reg     = OMAP1_IO_ADDRESS(OTG_BASE + 0x08), /* OTG_SYSCON_2 */
+        .enable_bit     = 8 /* UHOST_EN */,
+};
+
+static struct clk usb_dc_ck = {
+        .name           = "usb_dc_ck",
+        .ops            = &clkops_generic,
+        /* Direct from ULPD, no parent */
+        .rate           = 48000000,
+        .flags          = RATE_FIXED,
+        .enable_reg     = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
+        .enable_bit     = 4,
+};
+
+static struct clk usb_dc_ck7xx = {
+        .name           = "usb_dc_ck",
+        .ops            = &clkops_generic,
+        /* Direct from ULPD, no parent */
+        .rate           = 48000000,
+        .flags          = RATE_FIXED,
+        .enable_reg     = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
+        .enable_bit     = 8,
+};
+
+static struct clk mclk_1510 = {
+        .name           = "mclk",
+        .ops            = &clkops_generic,
+        /* Direct from ULPD, no parent. May be enabled by ext hardware. */
+        .rate           = 12000000,
+        .flags          = RATE_FIXED,
+        .enable_reg     = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
+        .enable_bit     = 6,
+};
+
+static struct clk mclk_16xx = {
+        .name           = "mclk",
+        .ops            = &clkops_generic,
+        /* Direct from ULPD, no parent. May be enabled by ext hardware. */
+        .enable_reg     = OMAP1_IO_ADDRESS(COM_CLK_DIV_CTRL_SEL),
+        .enable_bit     = COM_ULPD_PLL_CLK_REQ,
+        .set_rate       = &omap1_set_ext_clk_rate,
+        .round_rate     = &omap1_round_ext_clk_rate,
+        .init           = &omap1_init_ext_clk,
+};
+
+static struct clk bclk_1510 = {
+        .name           = "bclk",
+        .ops            = &clkops_generic,
+        /* Direct from ULPD, no parent. May be enabled by ext hardware. */
+        .rate           = 12000000,
+        .flags          = RATE_FIXED,
+};
+
+static struct clk bclk_16xx = {
+        .name           = "bclk",
+        .ops            = &clkops_generic,
+        /* Direct from ULPD, no parent. May be enabled by ext hardware. */
+        .enable_reg     = OMAP1_IO_ADDRESS(SWD_CLK_DIV_CTRL_SEL),
+        .enable_bit     = SWD_ULPD_PLL_CLK_REQ,
+        .set_rate       = &omap1_set_ext_clk_rate,
+        .round_rate     = &omap1_round_ext_clk_rate,
+        .init           = &omap1_init_ext_clk,
+};
+
+static struct clk mmc1_ck = {
+        .name           = "mmc_ck",
+        .ops            = &clkops_generic,
+        /* Functional clock is direct from ULPD, interface clock is ARMPER */
+        .parent         = &armper_ck.clk,
+        .rate           = 48000000,
+        .flags          = RATE_FIXED | ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
+        .enable_reg     = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
+        .enable_bit     = 23,
+};
+
+static struct clk mmc2_ck = {
+        .name           = "mmc_ck",
+        .id             = 1,
+        .ops            = &clkops_generic,
+        /* Functional clock is direct from ULPD, interface clock is ARMPER */
+        .parent         = &armper_ck.clk,
+        .rate           = 48000000,
+        .flags          = RATE_FIXED | ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
+        .enable_reg     = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
+        .enable_bit     = 20,
+};
+
+static struct clk mmc3_ck = {
+        .name           = "mmc_ck",
+        .id             = 2,
+        .ops            = &clkops_generic,
+        /* Functional clock is direct from ULPD, interface clock is ARMPER */
+        .parent         = &armper_ck.clk,
+        .rate           = 48000000,
+        .flags          = RATE_FIXED | ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
+        .enable_reg     = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
+        .enable_bit     = 12,
+};
+
+static struct clk virtual_ck_mpu = {
+        .name           = "mpu",
+        .ops            = &clkops_null,
+        .parent         = &arm_ck, /* Is smarter alias for */
+        .recalc         = &followparent_recalc,
+        .set_rate       = &omap1_select_table_rate,
+        .round_rate     = &omap1_round_to_table_rate,
+};
+
+/* virtual functional clock domain for I2C. Just for making sure that ARMXOR_CK
+remains active during MPU idle whenever this is enabled */
+static struct clk i2c_fck = {
+        .name           = "i2c_fck",
+        .id             = 1,
+        .ops            = &clkops_null,
+        .flags          = CLOCK_NO_IDLE_PARENT,
+        .parent         = &armxor_ck.clk,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk i2c_ick = {
+        .name           = "i2c_ick",
+        .id             = 1,
+        .ops            = &clkops_null,
+        .flags          = CLOCK_NO_IDLE_PARENT,
+        .parent         = &armper_ck.clk,
+        .recalc         = &followparent_recalc,
+};
+
+/*
+ * clkdev integration
+ */
+
+static struct omap_clk omap_clks[] = {
+        /* non-ULPD clocks */
+        CLK(NULL,       "ck_ref",       &ck_ref,        CK_16XX | CK_1510 | CK_310 | CK_7XX),
+        CLK(NULL,       "ck_dpll1",     &ck_dpll1,      CK_16XX | CK_1510 | CK_310),
+        /* CK_GEN1 clocks */
+        CLK(NULL,       "ck_dpll1out",  &ck_dpll1out.clk, CK_16XX),
+        CLK(NULL,       "ck_sossi",     &sossi_ck,      CK_16XX),
+        CLK(NULL,       "arm_ck",       &arm_ck,        CK_16XX | CK_1510 | CK_310),
+        CLK(NULL,       "armper_ck",    &armper_ck.clk, CK_16XX | CK_1510 | CK_310),
+        CLK(NULL,       "arm_gpio_ck",  &arm_gpio_ck,   CK_1510 | CK_310),
+        CLK(NULL,       "armxor_ck",    &armxor_ck.clk, CK_16XX | CK_1510 | CK_310 | CK_7XX),
+        CLK(NULL,       "armtim_ck",    &armtim_ck.clk, CK_16XX | CK_1510 | CK_310),
+        CLK("omap_wdt", "fck",          &armwdt_ck.clk, CK_16XX | CK_1510 | CK_310),
+        CLK("omap_wdt", "ick",          &armper_ck.clk, CK_16XX),
+        CLK("omap_wdt", "ick",          &dummy_ck,      CK_1510 | CK_310),
+        CLK(NULL,       "arminth_ck",   &arminth_ck1510, CK_1510 | CK_310),
+        CLK(NULL,       "arminth_ck",   &arminth_ck16xx, CK_16XX),
+        /* CK_GEN2 clocks */
+        CLK(NULL,       "dsp_ck",       &dsp_ck,        CK_16XX | CK_1510 | CK_310),
+        CLK(NULL,       "dspmmu_ck",    &dspmmu_ck,     CK_16XX | CK_1510 | CK_310),
+        CLK(NULL,       "dspper_ck",    &dspper_ck,     CK_16XX | CK_1510 | CK_310),
+        CLK(NULL,       "dspxor_ck",    &dspxor_ck,     CK_16XX | CK_1510 | CK_310),
+        CLK(NULL,       "dsptim_ck",    &dsptim_ck,     CK_16XX | CK_1510 | CK_310),
+        /* CK_GEN3 clocks */
+        CLK(NULL,       "tc_ck",        &tc_ck.clk,     CK_16XX | CK_1510 | CK_310 | CK_7XX),
+        CLK(NULL,       "tipb_ck",      &tipb_ck,       CK_1510 | CK_310),
+        CLK(NULL,       "l3_ocpi_ck",   &l3_ocpi_ck,    CK_16XX | CK_7XX),
+        CLK(NULL,       "tc1_ck",       &tc1_ck,        CK_16XX),
+        CLK(NULL,       "tc2_ck",       &tc2_ck,        CK_16XX),
+        CLK(NULL,       "dma_ck",       &dma_ck,        CK_16XX | CK_1510 | CK_310),
+        CLK(NULL,       "dma_lcdfree_ck", &dma_lcdfree_ck, CK_16XX),
+        CLK(NULL,       "api_ck",       &api_ck.clk,    CK_16XX | CK_1510 | CK_310),
+        CLK(NULL,       "lb_ck",        &lb_ck.clk,     CK_1510 | CK_310),
+        CLK(NULL,       "rhea1_ck",     &rhea1_ck,      CK_16XX),
+        CLK(NULL,       "rhea2_ck",     &rhea2_ck,      CK_16XX),
+        CLK(NULL,       "lcd_ck",       &lcd_ck_16xx,   CK_16XX | CK_7XX),
+        CLK(NULL,       "lcd_ck",       &lcd_ck_1510.clk, CK_1510 | CK_310),
+        /* ULPD clocks */
+        CLK(NULL,       "uart1_ck",     &uart1_1510,    CK_1510 | CK_310),
+        CLK(NULL,       "uart1_ck",     &uart1_16xx.clk, CK_16XX),
+        CLK(NULL,       "uart2_ck",     &uart2_ck,      CK_16XX | CK_1510 | CK_310),
+        CLK(NULL,       "uart3_ck",     &uart3_1510,    CK_1510 | CK_310),
+        CLK(NULL,       "uart3_ck",     &uart3_16xx.clk, CK_16XX),
+        CLK(NULL,       "usb_clko",     &usb_clko,      CK_16XX | CK_1510 | CK_310),
+        CLK(NULL,       "usb_hhc_ck",   &usb_hhc_ck1510, CK_1510 | CK_310),
+        CLK(NULL,       "usb_hhc_ck",   &usb_hhc_ck16xx, CK_16XX),
+        CLK(NULL,       "usb_dc_ck",    &usb_dc_ck,     CK_16XX),
+        CLK(NULL,       "usb_dc_ck",    &usb_dc_ck7xx,  CK_7XX),
+        CLK(NULL,       "mclk",         &mclk_1510,     CK_1510 | CK_310),
+        CLK(NULL,       "mclk",         &mclk_16xx,     CK_16XX),
+        CLK(NULL,       "bclk",         &bclk_1510,     CK_1510 | CK_310),
+        CLK(NULL,       "bclk",         &bclk_16xx,     CK_16XX),
+        CLK("mmci-omap.0", "fck",       &mmc1_ck,       CK_16XX | CK_1510 | CK_310),
+        CLK("mmci-omap.0", "fck",       &mmc3_ck,       CK_7XX),
+        CLK("mmci-omap.0", "ick",       &armper_ck.clk, CK_16XX | CK_1510 | CK_310 | CK_7XX),
+        CLK("mmci-omap.1", "fck",       &mmc2_ck,       CK_16XX),
+        CLK("mmci-omap.1", "ick",       &armper_ck.clk, CK_16XX),
+        /* Virtual clocks */
+        CLK(NULL,       "mpu",          &virtual_ck_mpu, CK_16XX | CK_1510 | CK_310),
+        CLK("i2c_omap.1", "fck",        &i2c_fck,       CK_16XX | CK_1510 | CK_310 | CK_7XX),
+        CLK("i2c_omap.1", "ick",        &i2c_ick,       CK_16XX),
+        CLK("i2c_omap.1", "ick",        &dummy_ck,      CK_1510 | CK_310 | CK_7XX),
+        CLK("omap_uwire", "fck",        &armxor_ck.clk, CK_16XX | CK_1510 | CK_310),
+        CLK("omap-mcbsp.1", "ick",      &dspper_ck,     CK_16XX),
+        CLK("omap-mcbsp.1", "ick",      &dummy_ck,      CK_1510 | CK_310),
+        CLK("omap-mcbsp.2", "ick",      &armper_ck.clk, CK_16XX),
+        CLK("omap-mcbsp.2", "ick",      &dummy_ck,      CK_1510 | CK_310),
+        CLK("omap-mcbsp.3", "ick",      &dspper_ck,     CK_16XX),
+        CLK("omap-mcbsp.3", "ick",      &dummy_ck,      CK_1510 | CK_310),
+        CLK("omap-mcbsp.1", "fck",      &dspxor_ck,     CK_16XX | CK_1510 | CK_310),
+        CLK("omap-mcbsp.2", "fck",      &armper_ck.clk, CK_16XX | CK_1510 | CK_310),
+        CLK("omap-mcbsp.3", "fck",      &dspxor_ck,     CK_16XX | CK_1510 | CK_310),
+};
+
+/*
+ * init
+ */
+
+static struct clk_functions omap1_clk_functions __initdata = {
+        .clk_enable             = omap1_clk_enable,
+        .clk_disable            = omap1_clk_disable,
+        .clk_round_rate         = omap1_clk_round_rate,
+        .clk_set_rate           = omap1_clk_set_rate,
+        .clk_disable_unused     = omap1_clk_disable_unused,
+};
+
+int __init omap1_clk_init(void)
+{
+        struct omap_clk *c;
+        const struct omap_clock_config *info;
+        int crystal_type = 0; /* Default 12 MHz */
+        u32 reg, cpu_mask;
+
+#ifdef CONFIG_DEBUG_LL
+        /*
+         * Resets some clocks that may be left on from bootloader,
+         * but leaves serial clocks on.
+         */
+        omap_writel(0x3 << 29, MOD_CONF_CTRL_0);
+#endif
+
+        /* USB_REQ_EN will be disabled later if necessary (usb_dc_ck) */
+        reg = omap_readw(SOFT_REQ_REG) & (1 << 4);
+        omap_writew(reg, SOFT_REQ_REG);
+        if (!cpu_is_omap15xx())
+                omap_writew(0, SOFT_REQ_REG2);
+
+        clk_init(&omap1_clk_functions);
+
+        /* By default all idlect1 clocks are allowed to idle */
+        arm_idlect1_mask = ~0;
+
+        for (c = omap_clks; c < omap_clks + ARRAY_SIZE(omap_clks); c++)
+                clk_preinit(c->lk.clk);
+
+        cpu_mask = 0;
+        if (cpu_is_omap16xx())
+                cpu_mask |= CK_16XX;
+        if (cpu_is_omap1510())
+                cpu_mask |= CK_1510;
+        if (cpu_is_omap7xx())
+                cpu_mask |= CK_7XX;
+        if (cpu_is_omap310())
+                cpu_mask |= CK_310;
+
+        for (c = omap_clks; c < omap_clks + ARRAY_SIZE(omap_clks); c++)
+                if (c->cpu & cpu_mask) {
+                        clkdev_add(&c->lk);
+                        clk_register(c->lk.clk);
+                }
+
+        /* Pointers to these clocks are needed by code in clock.c */
+        api_ck_p = clk_get(NULL, "api_ck");
+        ck_dpll1_p = clk_get(NULL, "ck_dpll1");
+        ck_ref_p = clk_get(NULL, "ck_ref");
+
+        info = omap_get_config(OMAP_TAG_CLOCK, struct omap_clock_config);
+        if (info != NULL) {
+                if (!cpu_is_omap15xx())
+                        crystal_type = info->system_clock_type;
+        }
+
+#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
+        ck_ref.rate = 13000000;
+#elif defined(CONFIG_ARCH_OMAP16XX)
+        if (crystal_type == 2)
+                ck_ref.rate = 19200000;
+#endif
+
+        pr_info("Clocks: ARM_SYSST: 0x%04x DPLL_CTL: 0x%04x ARM_CKCTL: "
+                "0x%04x\n", omap_readw(ARM_SYSST), omap_readw(DPLL_CTL),
+                omap_readw(ARM_CKCTL));
+
+        /* We want to be in syncronous scalable mode */
+        omap_writew(0x1000, ARM_SYSST);
+
+#ifdef CONFIG_OMAP_CLOCKS_SET_BY_BOOTLOADER
+        /* Use values set by bootloader. Determine PLL rate and recalculate
+         * dependent clocks as if kernel had changed PLL or divisors.
+         */
+        {
+                unsigned pll_ctl_val = omap_readw(DPLL_CTL);
+
+                ck_dpll1.rate = ck_ref.rate; /* Base xtal rate */
+                if (pll_ctl_val & 0x10) {
+                        /* PLL enabled, apply multiplier and divisor */
+                        if (pll_ctl_val & 0xf80)
+                                ck_dpll1.rate *= (pll_ctl_val & 0xf80) >> 7;
+                        ck_dpll1.rate /= ((pll_ctl_val & 0x60) >> 5) + 1;
+                } else {
+                        /* PLL disabled, apply bypass divisor */
+                        switch (pll_ctl_val & 0xc) {
+                        case 0:
+                                break;
+                        case 0x4:
+                                ck_dpll1.rate /= 2;
+                                break;
+                        default:
+                                ck_dpll1.rate /= 4;
+                                break;
+                        }
+                }
+        }
+#else
+        /* Find the highest supported frequency and enable it */
+        if (omap1_select_table_rate(&virtual_ck_mpu, ~0)) {
+                printk(KERN_ERR "System frequencies not set. Check your config.\n");
+                /* Guess sane values (60MHz) */
+                omap_writew(0x2290, DPLL_CTL);
+                omap_writew(cpu_is_omap7xx() ? 0x3005 : 0x1005, ARM_CKCTL);
+                ck_dpll1.rate = 60000000;
+        }
+#endif
+        propagate_rate(&ck_dpll1);
+        /* Cache rates for clocks connected to ck_ref (not dpll1) */
+        propagate_rate(&ck_ref);
+        printk(KERN_INFO "Clocking rate (xtal/DPLL1/MPU): "
+                "%ld.%01ld/%ld.%01ld/%ld.%01ld MHz\n",
+               ck_ref.rate / 1000000, (ck_ref.rate / 100000) % 10,
+               ck_dpll1.rate / 1000000, (ck_dpll1.rate / 100000) % 10,
+               arm_ck.rate / 1000000, (arm_ck.rate / 100000) % 10);
+
+#if defined(CONFIG_MACH_OMAP_PERSEUS2) || defined(CONFIG_MACH_OMAP_FSAMPLE)
+        /* Select slicer output as OMAP input clock */
+        omap_writew(omap_readw(OMAP7XX_PCC_UPLD_CTRL) & ~0x1, OMAP7XX_PCC_UPLD_CTRL);
+#endif
+
+        /* Amstrad Delta wants BCLK high when inactive */
+        if (machine_is_ams_delta())
+                omap_writel(omap_readl(ULPD_CLOCK_CTRL) |
+                                (1 << SDW_MCLK_INV_BIT),
+                                ULPD_CLOCK_CTRL);
+
+        /* Turn off DSP and ARM_TIMXO. Make sure ARM_INTHCK is not divided */
+        /* (on 730, bit 13 must not be cleared) */
+        if (cpu_is_omap7xx())
+                omap_writew(omap_readw(ARM_CKCTL) & 0x2fff, ARM_CKCTL);
+        else
+                omap_writew(omap_readw(ARM_CKCTL) & 0x0fff, ARM_CKCTL);
+
+        /* Put DSP/MPUI into reset until needed */
+        omap_writew(0, ARM_RSTCT1);
+        omap_writew(1, ARM_RSTCT2);
+        omap_writew(0x400, ARM_IDLECT1);
+
+        /*
+         * According to OMAP5910 Erratum SYS_DMA_1, bit DMACK_REQ (bit 8)
+         * of the ARM_IDLECT2 register must be set to zero. The power-on
+         * default value of this bit is one.
+         */
+        omap_writew(0x0000, ARM_IDLECT2);       /* Turn LCD clock off also */
+
+        /*
+         * Only enable those clocks we will need, let the drivers
+         * enable other clocks as necessary
+         */
+        clk_enable(&armper_ck.clk);
+        clk_enable(&armxor_ck.clk);
+        clk_enable(&armtim_ck.clk); /* This should be done by timer code */
+
+        if (cpu_is_omap15xx())
+                clk_enable(&arm_gpio_ck);
+
+        return 0;
+}
diff --git a/arch/arm/mach-omap1/i2c.c b/arch/arm/mach-omap1/i2c.c
new file mode 100644
index 000000000000..1bf4735e27a6
--- /dev/null
+++ b/arch/arm/mach-omap1/i2c.c
@@ -0,0 +1,39 @@
+/*
+ * Helper module for board specific I2C bus registration
+ *
+ * Copyright (C) 2009 Nokia Corporation.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
+ * 02110-1301 USA
+ *
+ */
+
+#include <plat/i2c.h>
+#include <plat/mux.h>
+#include <plat/cpu.h>
+
+int __init omap_register_i2c_bus(int bus_id, u32 clkrate,
+                          struct i2c_board_info const *info,
+                          unsigned len)
+{
+        if (cpu_is_omap7xx()) {
+                omap_cfg_reg(I2C_7XX_SDA);
+                omap_cfg_reg(I2C_7XX_SCL);
+        } else {
+                omap_cfg_reg(I2C_SDA);
+                omap_cfg_reg(I2C_SCL);
+        }
+
+        return omap_plat_register_i2c_bus(bus_id, clkrate, info, len);
+}
diff --git a/arch/arm/mach-omap1/include/mach/lcd_dma.h b/arch/arm/mach-omap1/include/mach/lcd_dma.h
new file mode 100644
index 000000000000..d7a457bbcb7f
--- /dev/null
+++ b/arch/arm/mach-omap1/include/mach/lcd_dma.h
@@ -0,0 +1,78 @@
+/*
+ *  arch/arm/mach-omap1/include/mach/lcd_dma.h
+ *
+ * Extracted from arch/arm/plat-omap/include/plat/dma.h
+ *  Copyright (C) 2003 Nokia Corporation
+ *  Author: Juha Yrjölä <juha.yrjola@nokia.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+#ifndef __MACH_OMAP1_LCD_DMA_H__
+#define __MACH_OMAP1_LCD_DMA_H__
+
+/* Hardware registers for LCD DMA */
+#define OMAP1510_DMA_LCD_BASE           (0xfffedb00)
+#define OMAP1510_DMA_LCD_CTRL           (OMAP1510_DMA_LCD_BASE + 0x00)
+#define OMAP1510_DMA_LCD_TOP_F1_L       (OMAP1510_DMA_LCD_BASE + 0x02)
+#define OMAP1510_DMA_LCD_TOP_F1_U       (OMAP1510_DMA_LCD_BASE + 0x04)
+#define OMAP1510_DMA_LCD_BOT_F1_L       (OMAP1510_DMA_LCD_BASE + 0x06)
+#define OMAP1510_DMA_LCD_BOT_F1_U       (OMAP1510_DMA_LCD_BASE + 0x08)
+
+#define OMAP1610_DMA_LCD_BASE           (0xfffee300)
+#define OMAP1610_DMA_LCD_CSDP           (OMAP1610_DMA_LCD_BASE + 0xc0)
+#define OMAP1610_DMA_LCD_CCR            (OMAP1610_DMA_LCD_BASE + 0xc2)
+#define OMAP1610_DMA_LCD_CTRL           (OMAP1610_DMA_LCD_BASE + 0xc4)
+#define OMAP1610_DMA_LCD_TOP_B1_L       (OMAP1610_DMA_LCD_BASE + 0xc8)
+#define OMAP1610_DMA_LCD_TOP_B1_U       (OMAP1610_DMA_LCD_BASE + 0xca)
+#define OMAP1610_DMA_LCD_BOT_B1_L       (OMAP1610_DMA_LCD_BASE + 0xcc)
+#define OMAP1610_DMA_LCD_BOT_B1_U       (OMAP1610_DMA_LCD_BASE + 0xce)
+#define OMAP1610_DMA_LCD_TOP_B2_L       (OMAP1610_DMA_LCD_BASE + 0xd0)
+#define OMAP1610_DMA_LCD_TOP_B2_U       (OMAP1610_DMA_LCD_BASE + 0xd2)
+#define OMAP1610_DMA_LCD_BOT_B2_L       (OMAP1610_DMA_LCD_BASE + 0xd4)
+#define OMAP1610_DMA_LCD_BOT_B2_U       (OMAP1610_DMA_LCD_BASE + 0xd6)
+#define OMAP1610_DMA_LCD_SRC_EI_B1      (OMAP1610_DMA_LCD_BASE + 0xd8)
+#define OMAP1610_DMA_LCD_SRC_FI_B1_L    (OMAP1610_DMA_LCD_BASE + 0xda)
+#define OMAP1610_DMA_LCD_SRC_EN_B1      (OMAP1610_DMA_LCD_BASE + 0xe0)
+#define OMAP1610_DMA_LCD_SRC_FN_B1      (OMAP1610_DMA_LCD_BASE + 0xe4)
+#define OMAP1610_DMA_LCD_LCH_CTRL       (OMAP1610_DMA_LCD_BASE + 0xea)
+#define OMAP1610_DMA_LCD_SRC_FI_B1_U    (OMAP1610_DMA_LCD_BASE + 0xf4)
+
+/* LCD DMA block numbers */
+enum {
+        OMAP_LCD_DMA_B1_TOP,
+        OMAP_LCD_DMA_B1_BOTTOM,
+        OMAP_LCD_DMA_B2_TOP,
+        OMAP_LCD_DMA_B2_BOTTOM
+};
+
+/* LCD DMA functions */
+extern int omap_request_lcd_dma(void (*callback)(u16 status, void *data),
+                                void *data);
+extern void omap_free_lcd_dma(void);
+extern void omap_setup_lcd_dma(void);
+extern void omap_enable_lcd_dma(void);
+extern void omap_stop_lcd_dma(void);
+extern void omap_set_lcd_dma_ext_controller(int external);
+extern void omap_set_lcd_dma_single_transfer(int single);
+extern void omap_set_lcd_dma_b1(unsigned long addr, u16 fb_xres, u16 fb_yres,
+                                int data_type);
+extern void omap_set_lcd_dma_b1_rotation(int rotate);
+extern void omap_set_lcd_dma_b1_vxres(unsigned long vxres);
+extern void omap_set_lcd_dma_b1_mirror(int mirror);
+extern void omap_set_lcd_dma_b1_scale(unsigned int xscale, unsigned int yscale);
+
+extern int omap_lcd_dma_running(void);
+
+#endif /* __MACH_OMAP1_LCD_DMA_H__ */
diff --git a/arch/arm/mach-omap1/include/mach/lcdc.h b/arch/arm/mach-omap1/include/mach/lcdc.h
new file mode 100644
index 000000000000..89bd703adaf6
--- /dev/null
+++ b/arch/arm/mach-omap1/include/mach/lcdc.h
@@ -0,0 +1,57 @@
+/*
+ * arch/arm/mach-omap1/include/mach/lcdc.h
+ *
+ * Extracted from drivers/video/omap/lcdc.c
+ * Copyright (C) 2004 Nokia Corporation
+ * Author: Imre Deak <imre.deak@nokia.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
+ */
+#ifndef __MACH_LCDC_H__
+#define __MACH_LCDC_H__
+
+#define OMAP_LCDC_BASE                  0xfffec000
+#define OMAP_LCDC_SIZE                  256
+#define OMAP_LCDC_IRQ                   INT_LCD_CTRL
+
+#define OMAP_LCDC_CONTROL               (OMAP_LCDC_BASE + 0x00)
+#define OMAP_LCDC_TIMING0               (OMAP_LCDC_BASE + 0x04)
+#define OMAP_LCDC_TIMING1               (OMAP_LCDC_BASE + 0x08)
+#define OMAP_LCDC_TIMING2               (OMAP_LCDC_BASE + 0x0c)
+#define OMAP_LCDC_STATUS                (OMAP_LCDC_BASE + 0x10)
+#define OMAP_LCDC_SUBPANEL              (OMAP_LCDC_BASE + 0x14)
+#define OMAP_LCDC_LINE_INT              (OMAP_LCDC_BASE + 0x18)
+#define OMAP_LCDC_DISPLAY_STATUS        (OMAP_LCDC_BASE + 0x1c)
+
+#define OMAP_LCDC_STAT_DONE             (1 << 0)
+#define OMAP_LCDC_STAT_VSYNC            (1 << 1)
+#define OMAP_LCDC_STAT_SYNC_LOST        (1 << 2)
+#define OMAP_LCDC_STAT_ABC              (1 << 3)
+#define OMAP_LCDC_STAT_LINE_INT         (1 << 4)
+#define OMAP_LCDC_STAT_FUF              (1 << 5)
+#define OMAP_LCDC_STAT_LOADED_PALETTE   (1 << 6)
+
+#define OMAP_LCDC_CTRL_LCD_EN           (1 << 0)
+#define OMAP_LCDC_CTRL_LCD_TFT          (1 << 7)
+#define OMAP_LCDC_CTRL_LINE_IRQ_CLR_SEL (1 << 10)
+
+#define OMAP_LCDC_IRQ_VSYNC             (1 << 2)
+#define OMAP_LCDC_IRQ_DONE              (1 << 3)
+#define OMAP_LCDC_IRQ_LOADED_PALETTE    (1 << 4)
+#define OMAP_LCDC_IRQ_LINE_NIRQ         (1 << 5)
+#define OMAP_LCDC_IRQ_LINE              (1 << 6)
+#define OMAP_LCDC_IRQ_MASK              (((1 << 5) - 1) << 2)
+
+#endif /* __MACH_LCDC_H__ */
diff --git a/arch/arm/mach-omap1/io.c b/arch/arm/mach-omap1/io.c
index 2a6d68aa3489..d9b8d82530ae 100644
--- a/arch/arm/mach-omap1/io.c
+++ b/arch/arm/mach-omap1/io.c
@@ -18,7 +18,8 @@
 #include <plat/mux.h>
 #include <plat/tc.h>
 
-extern int omap1_clk_init(void);
+#include "clock.h"
+
 extern void omap_check_revision(void);
 extern void omap_sram_init(void);
 extern void omapfb_reserve_sdram(void);
diff --git a/arch/arm/mach-omap1/lcd_dma.c b/arch/arm/mach-omap1/lcd_dma.c
new file mode 100644
index 000000000000..3be11af687bb
--- /dev/null
+++ b/arch/arm/mach-omap1/lcd_dma.c
@@ -0,0 +1,448 @@
+/*
+ * linux/arch/arm/mach-omap1/lcd_dma.c
+ *
+ * Extracted from arch/arm/plat-omap/dma.c
+ * Copyright (C) 2003 - 2008 Nokia Corporation
+ * Author: Juha Yrjölä <juha.yrjola@nokia.com>
+ * DMA channel linking for 1610 by Samuel Ortiz <samuel.ortiz@nokia.com>
+ * Graphics DMA and LCD DMA graphics tranformations
+ * by Imre Deak <imre.deak@nokia.com>
+ * OMAP2/3 support Copyright (C) 2004-2007 Texas Instruments, Inc.
+ * Merged to support both OMAP1 and OMAP2 by Tony Lindgren <tony@atomide.com>
+ * Some functions based on earlier dma-omap.c Copyright (C) 2001 RidgeRun, Inc.
+ *
+ * Copyright (C) 2009 Texas Instruments
+ * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
+ *
+ * Support functions for the OMAP internal DMA channels.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include <linux/module.h>
+#include <linux/spinlock.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+
+#include <mach/hardware.h>
+#include <mach/lcdc.h>
+#include <plat/dma.h>
+
+int omap_lcd_dma_running(void)
+{
+        /*
+         * On OMAP1510, internal LCD controller will start the transfer
+         * when it gets enabled, so assume DMA running if LCD enabled.
+         */
+        if (cpu_is_omap1510())
+                if (omap_readw(OMAP_LCDC_CONTROL) & OMAP_LCDC_CTRL_LCD_EN)
+                        return 1;
+
+        /* Check if LCD DMA is running */
+        if (cpu_is_omap16xx())
+                if (omap_readw(OMAP1610_DMA_LCD_CCR) & OMAP_DMA_CCR_EN)
+                        return 1;
+
+        return 0;
+}
+
+static struct lcd_dma_info {
+        spinlock_t lock;
+        int reserved;
+        void (*callback)(u16 status, void *data);
+        void *cb_data;
+
+        int active;
+        unsigned long addr, size;
+        int rotate, data_type, xres, yres;
+        int vxres;
+        int mirror;
+        int xscale, yscale;
+        int ext_ctrl;
+        int src_port;
+        int single_transfer;
+} lcd_dma;
+
+void omap_set_lcd_dma_b1(unsigned long addr, u16 fb_xres, u16 fb_yres,
+                         int data_type)
+{
+        lcd_dma.addr = addr;
+        lcd_dma.data_type = data_type;
+        lcd_dma.xres = fb_xres;
+        lcd_dma.yres = fb_yres;
+}
+EXPORT_SYMBOL(omap_set_lcd_dma_b1);
+
+void omap_set_lcd_dma_src_port(int port)
+{
+        lcd_dma.src_port = port;
+}
+
+void omap_set_lcd_dma_ext_controller(int external)
+{
+        lcd_dma.ext_ctrl = external;
+}
+EXPORT_SYMBOL(omap_set_lcd_dma_ext_controller);
+
+void omap_set_lcd_dma_single_transfer(int single)
+{
+        lcd_dma.single_transfer = single;
+}
+EXPORT_SYMBOL(omap_set_lcd_dma_single_transfer);
+
+void omap_set_lcd_dma_b1_rotation(int rotate)
+{
+        if (cpu_is_omap1510()) {
+                printk(KERN_ERR "DMA rotation is not supported in 1510 mode\n");
+                BUG();
+                return;
+        }
+        lcd_dma.rotate = rotate;
+}
+EXPORT_SYMBOL(omap_set_lcd_dma_b1_rotation);
+
+void omap_set_lcd_dma_b1_mirror(int mirror)
+{
+        if (cpu_is_omap1510()) {
+                printk(KERN_ERR "DMA mirror is not supported in 1510 mode\n");
+                BUG();
+        }
+        lcd_dma.mirror = mirror;
+}
+EXPORT_SYMBOL(omap_set_lcd_dma_b1_mirror);
+
+void omap_set_lcd_dma_b1_vxres(unsigned long vxres)
+{
+        if (cpu_is_omap1510()) {
+                printk(KERN_ERR "DMA virtual resulotion is not supported "
+                                "in 1510 mode\n");
+                BUG();
+        }
+        lcd_dma.vxres = vxres;
+}
+EXPORT_SYMBOL(omap_set_lcd_dma_b1_vxres);
+
+void omap_set_lcd_dma_b1_scale(unsigned int xscale, unsigned int yscale)
+{
+        if (cpu_is_omap1510()) {
+                printk(KERN_ERR "DMA scale is not supported in 1510 mode\n");
+                BUG();
+        }
+        lcd_dma.xscale = xscale;
+        lcd_dma.yscale = yscale;
+}
+EXPORT_SYMBOL(omap_set_lcd_dma_b1_scale);
+
+static void set_b1_regs(void)
+{
+        unsigned long top, bottom;
+        int es;
+        u16 w;
+        unsigned long en, fn;
+        long ei, fi;
+        unsigned long vxres;
+        unsigned int xscale, yscale;
+
+        switch (lcd_dma.data_type) {
+        case OMAP_DMA_DATA_TYPE_S8:
+                es = 1;
+                break;
+        case OMAP_DMA_DATA_TYPE_S16:
+                es = 2;
+                break;
+        case OMAP_DMA_DATA_TYPE_S32:
+                es = 4;
+                break;
+        default:
+                BUG();
+                return;
+        }
+
+        vxres = lcd_dma.vxres ? lcd_dma.vxres : lcd_dma.xres;
+        xscale = lcd_dma.xscale ? lcd_dma.xscale : 1;
+        yscale = lcd_dma.yscale ? lcd_dma.yscale : 1;
+        BUG_ON(vxres < lcd_dma.xres);
+
+#define PIXADDR(x, y) (lcd_dma.addr +                                   \
+                ((y) * vxres * yscale + (x) * xscale) * es)
+#define PIXSTEP(sx, sy, dx, dy) (PIXADDR(dx, dy) - PIXADDR(sx, sy) - es + 1)
+
+        switch (lcd_dma.rotate) {
+        case 0:
+                if (!lcd_dma.mirror) {
+                        top = PIXADDR(0, 0);
+                        bottom = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1);
+                        /* 1510 DMA requires the bottom address to be 2 more
+                         * than the actual last memory access location. */
+                        if (cpu_is_omap1510() &&
+                                lcd_dma.data_type == OMAP_DMA_DATA_TYPE_S32)
+                                        bottom += 2;
+                        ei = PIXSTEP(0, 0, 1, 0);
+                        fi = PIXSTEP(lcd_dma.xres - 1, 0, 0, 1);
+                } else {
+                        top = PIXADDR(lcd_dma.xres - 1, 0);
+                        bottom = PIXADDR(0, lcd_dma.yres - 1);
+                        ei = PIXSTEP(1, 0, 0, 0);
+                        fi = PIXSTEP(0, 0, lcd_dma.xres - 1, 1);
+                }
+                en = lcd_dma.xres;
+                fn = lcd_dma.yres;
+                break;
+        case 90:
+                if (!lcd_dma.mirror) {
+                        top = PIXADDR(0, lcd_dma.yres - 1);
+                        bottom = PIXADDR(lcd_dma.xres - 1, 0);
+                        ei = PIXSTEP(0, 1, 0, 0);
+                        fi = PIXSTEP(0, 0, 1, lcd_dma.yres - 1);
+                } else {
+                        top = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1);
+                        bottom = PIXADDR(0, 0);
+                        ei = PIXSTEP(0, 1, 0, 0);
+                        fi = PIXSTEP(1, 0, 0, lcd_dma.yres - 1);
+                }
+                en = lcd_dma.yres;
+                fn = lcd_dma.xres;
+                break;
+        case 180:
+                if (!lcd_dma.mirror) {
+                        top = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1);
+                        bottom = PIXADDR(0, 0);
+                        ei = PIXSTEP(1, 0, 0, 0);
+                        fi = PIXSTEP(0, 1, lcd_dma.xres - 1, 0);
+                } else {
+                        top = PIXADDR(0, lcd_dma.yres - 1);
+                        bottom = PIXADDR(lcd_dma.xres - 1, 0);
+                        ei = PIXSTEP(0, 0, 1, 0);
+                        fi = PIXSTEP(lcd_dma.xres - 1, 1, 0, 0);
+                }
+                en = lcd_dma.xres;
+                fn = lcd_dma.yres;
+                break;
+        case 270:
+                if (!lcd_dma.mirror) {
+                        top = PIXADDR(lcd_dma.xres - 1, 0);
+                        bottom = PIXADDR(0, lcd_dma.yres - 1);
+                        ei = PIXSTEP(0, 0, 0, 1);
+                        fi = PIXSTEP(1, lcd_dma.yres - 1, 0, 0);
+                } else {
+                        top = PIXADDR(0, 0);
+                        bottom = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1);
+                        ei = PIXSTEP(0, 0, 0, 1);
+                        fi = PIXSTEP(0, lcd_dma.yres - 1, 1, 0);
+                }
+                en = lcd_dma.yres;
+                fn = lcd_dma.xres;
+                break;
+        default:
+                BUG();
+                return; /* Suppress warning about uninitialized vars */
+        }
+
+        if (cpu_is_omap1510()) {
+                omap_writew(top >> 16, OMAP1510_DMA_LCD_TOP_F1_U);
+                omap_writew(top, OMAP1510_DMA_LCD_TOP_F1_L);
+                omap_writew(bottom >> 16, OMAP1510_DMA_LCD_BOT_F1_U);
+                omap_writew(bottom, OMAP1510_DMA_LCD_BOT_F1_L);
+
+                return;
+        }
+
+        /* 1610 regs */
+        omap_writew(top >> 16, OMAP1610_DMA_LCD_TOP_B1_U);
+        omap_writew(top, OMAP1610_DMA_LCD_TOP_B1_L);
+        omap_writew(bottom >> 16, OMAP1610_DMA_LCD_BOT_B1_U);
+        omap_writew(bottom, OMAP1610_DMA_LCD_BOT_B1_L);
+
+        omap_writew(en, OMAP1610_DMA_LCD_SRC_EN_B1);
+        omap_writew(fn, OMAP1610_DMA_LCD_SRC_FN_B1);
+
+        w = omap_readw(OMAP1610_DMA_LCD_CSDP);
+        w &= ~0x03;
+        w |= lcd_dma.data_type;
+        omap_writew(w, OMAP1610_DMA_LCD_CSDP);
+
+        w = omap_readw(OMAP1610_DMA_LCD_CTRL);
+        /* Always set the source port as SDRAM for now*/
+        w &= ~(0x03 << 6);
+        if (lcd_dma.callback != NULL)
+                w |= 1 << 1;            /* Block interrupt enable */
+        else
+                w &= ~(1 << 1);
+        omap_writew(w, OMAP1610_DMA_LCD_CTRL);
+
+        if (!(lcd_dma.rotate || lcd_dma.mirror ||
+              lcd_dma.vxres || lcd_dma.xscale || lcd_dma.yscale))
+                return;
+
+        w = omap_readw(OMAP1610_DMA_LCD_CCR);
+        /* Set the double-indexed addressing mode */
+        w |= (0x03 << 12);
+        omap_writew(w, OMAP1610_DMA_LCD_CCR);
+
+        omap_writew(ei, OMAP1610_DMA_LCD_SRC_EI_B1);
+        omap_writew(fi >> 16, OMAP1610_DMA_LCD_SRC_FI_B1_U);
+        omap_writew(fi, OMAP1610_DMA_LCD_SRC_FI_B1_L);
+}
+
+static irqreturn_t lcd_dma_irq_handler(int irq, void *dev_id)
+{
+        u16 w;
+
+        w = omap_readw(OMAP1610_DMA_LCD_CTRL);
+        if (unlikely(!(w & (1 << 3)))) {
+                printk(KERN_WARNING "Spurious LCD DMA IRQ\n");
+                return IRQ_NONE;
+        }
+        /* Ack the IRQ */
+        w |= (1 << 3);
+        omap_writew(w, OMAP1610_DMA_LCD_CTRL);
+        lcd_dma.active = 0;
+        if (lcd_dma.callback != NULL)
+                lcd_dma.callback(w, lcd_dma.cb_data);
+
+        return IRQ_HANDLED;
+}
+
+int omap_request_lcd_dma(void (*callback)(u16 status, void *data),
+                         void *data)
+{
+        spin_lock_irq(&lcd_dma.lock);
+        if (lcd_dma.reserved) {
+                spin_unlock_irq(&lcd_dma.lock);
+                printk(KERN_ERR "LCD DMA channel already reserved\n");
+                BUG();
+                return -EBUSY;
+        }
+        lcd_dma.reserved = 1;
+        spin_unlock_irq(&lcd_dma.lock);
+        lcd_dma.callback = callback;
+        lcd_dma.cb_data = data;
+        lcd_dma.active = 0;
+        lcd_dma.single_transfer = 0;
+        lcd_dma.rotate = 0;
+        lcd_dma.vxres = 0;
+        lcd_dma.mirror = 0;
+        lcd_dma.xscale = 0;
+        lcd_dma.yscale = 0;
+        lcd_dma.ext_ctrl = 0;
+        lcd_dma.src_port = 0;
+
+        return 0;
+}
+EXPORT_SYMBOL(omap_request_lcd_dma);
+
+void omap_free_lcd_dma(void)
+{
+        spin_lock(&lcd_dma.lock);
+        if (!lcd_dma.reserved) {
+                spin_unlock(&lcd_dma.lock);
+                printk(KERN_ERR "LCD DMA is not reserved\n");
+                BUG();
+                return;
+        }
+        if (!cpu_is_omap1510())
+                omap_writew(omap_readw(OMAP1610_DMA_LCD_CCR) & ~1,
+                            OMAP1610_DMA_LCD_CCR);
+        lcd_dma.reserved = 0;
+        spin_unlock(&lcd_dma.lock);
+}
+EXPORT_SYMBOL(omap_free_lcd_dma);
+
+void omap_enable_lcd_dma(void)
+{
+        u16 w;
+
+        /*
+         * Set the Enable bit only if an external controller is
+         * connected. Otherwise the OMAP internal controller will
+         * start the transfer when it gets enabled.
+         */
+        if (cpu_is_omap1510() || !lcd_dma.ext_ctrl)
+                return;
+
+        w = omap_readw(OMAP1610_DMA_LCD_CTRL);
+        w |= 1 << 8;
+        omap_writew(w, OMAP1610_DMA_LCD_CTRL);
+
+        lcd_dma.active = 1;
+
+        w = omap_readw(OMAP1610_DMA_LCD_CCR);
+        w |= 1 << 7;
+        omap_writew(w, OMAP1610_DMA_LCD_CCR);
+}
+EXPORT_SYMBOL(omap_enable_lcd_dma);
+
+void omap_setup_lcd_dma(void)
+{
+        BUG_ON(lcd_dma.active);
+        if (!cpu_is_omap1510()) {
+                /* Set some reasonable defaults */
+                omap_writew(0x5440, OMAP1610_DMA_LCD_CCR);
+                omap_writew(0x9102, OMAP1610_DMA_LCD_CSDP);
+                omap_writew(0x0004, OMAP1610_DMA_LCD_LCH_CTRL);
+        }
+        set_b1_regs();
+        if (!cpu_is_omap1510()) {
+                u16 w;
+
+                w = omap_readw(OMAP1610_DMA_LCD_CCR);
+                /*
+                 * If DMA was already active set the end_prog bit to have
+                 * the programmed register set loaded into the active
+                 * register set.
+                 */
+                w |= 1 << 11;           /* End_prog */
+                if (!lcd_dma.single_transfer)
+                        w |= (3 << 8);  /* Auto_init, repeat */
+                omap_writew(w, OMAP1610_DMA_LCD_CCR);
+        }
+}
+EXPORT_SYMBOL(omap_setup_lcd_dma);
+
+void omap_stop_lcd_dma(void)
+{
+        u16 w;
+
+        lcd_dma.active = 0;
+        if (cpu_is_omap1510() || !lcd_dma.ext_ctrl)
+                return;
+
+        w = omap_readw(OMAP1610_DMA_LCD_CCR);
+        w &= ~(1 << 7);
+        omap_writew(w, OMAP1610_DMA_LCD_CCR);
+
+        w = omap_readw(OMAP1610_DMA_LCD_CTRL);
+        w &= ~(1 << 8);
+        omap_writew(w, OMAP1610_DMA_LCD_CTRL);
+}
+EXPORT_SYMBOL(omap_stop_lcd_dma);
+
+static int __init omap_init_lcd_dma(void)
+{
+        int r;
+
+        if (cpu_is_omap16xx()) {
+                u16 w;
+
+                /* this would prevent OMAP sleep */
+                w = omap_readw(OMAP1610_DMA_LCD_CTRL);
+                w &= ~(1 << 8);
+                omap_writew(w, OMAP1610_DMA_LCD_CTRL);
+        }
+
+        spin_lock_init(&lcd_dma.lock);
+
+        r = request_irq(INT_DMA_LCD, lcd_dma_irq_handler, 0,
+                        "LCD DMA", NULL);
+        if (r != 0)
+                printk(KERN_ERR "unable to request IRQ for LCD DMA "
+                               "(error %d)\n", r);
+
+        return r;
+}
+
+arch_initcall(omap_init_lcd_dma);
+
diff --git a/arch/arm/mach-omap1/mux.c b/arch/arm/mach-omap1/mux.c
index 785371e982fc..07212cc621ae 100644
--- a/arch/arm/mach-omap1/mux.c
+++ b/arch/arm/mach-omap1/mux.c
@@ -50,12 +50,18 @@ MUX_CFG_7XX("E3_7XX_KBC4",        13,   25,    0,   24,   1, 0)
 
 MUX_CFG_7XX("AA17_7XX_USB_DM",     2,   21,    0,   20,   0, 0)
 MUX_CFG_7XX("W16_7XX_USB_PU_EN",   2,   25,    0,   24,   0, 0)
-MUX_CFG_7XX("W17_7XX_USB_VBUSI",   2,   29,    0,   28,   0, 0)
+MUX_CFG_7XX("W17_7XX_USB_VBUSI",   2,   29,    6,   28,   1, 0)
+MUX_CFG_7XX("W18_7XX_USB_DMCK_OUT",3,    3,    1,    2,   0, 0)
+MUX_CFG_7XX("W19_7XX_USB_DCRST",   3,    7,    1,    6,   0, 0)
 
 /* MMC Pins */
 MUX_CFG_7XX("MMC_7XX_CMD",         2,    9,    0,    8,   1, 0)
 MUX_CFG_7XX("MMC_7XX_CLK",         2,   13,    0,   12,   1, 0)
 MUX_CFG_7XX("MMC_7XX_DAT0",        2,   17,    0,   16,   1, 0)
+
+/* I2C interface */
+MUX_CFG_7XX("I2C_7XX_SCL",         5,    1,    0,    0,   1, 0)
+MUX_CFG_7XX("I2C_7XX_SDA",         5,    5,    0,    0,   1, 0)
 };
 #define OMAP7XX_PINS_SZ         ARRAY_SIZE(omap7xx_pins)
 #else
diff --git a/arch/arm/mach-omap1/opp.h b/arch/arm/mach-omap1/opp.h
new file mode 100644
index 000000000000..07074d79adce
--- /dev/null
+++ b/arch/arm/mach-omap1/opp.h
@@ -0,0 +1,28 @@
+/*
+ *  linux/arch/arm/mach-omap1/opp.h
+ *
+ *  Copyright (C) 2004 - 2005 Nokia corporation
+ *  Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
+ *  Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ARCH_ARM_MACH_OMAP1_OPP_H
+#define __ARCH_ARM_MACH_OMAP1_OPP_H
+
+#include <linux/types.h>
+
+struct mpu_rate {
+        unsigned long           rate;
+        unsigned long           xtal;
+        unsigned long           pll_rate;
+        __u16                   ckctl_val;
+        __u16                   dpllctl_val;
+};
+
+extern struct mpu_rate omap1_rate_table[];
+
+#endif
diff --git a/arch/arm/mach-omap1/opp_data.c b/arch/arm/mach-omap1/opp_data.c
new file mode 100644
index 000000000000..75a546514994
--- /dev/null
+++ b/arch/arm/mach-omap1/opp_data.c
@@ -0,0 +1,59 @@
+/*
+ *  linux/arch/arm/mach-omap1/opp_data.c
+ *
+ *  Copyright (C) 2004 - 2005 Nokia corporation
+ *  Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
+ *  Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include "opp.h"
+
+/*-------------------------------------------------------------------------
+ * Omap1 MPU rate table
+ *-------------------------------------------------------------------------*/
+struct mpu_rate omap1_rate_table[] = {
+        /* MPU MHz, xtal MHz, dpll1 MHz, CKCTL, DPLL_CTL
+         * NOTE: Comment order here is different from bits in CKCTL value:
+         * armdiv, dspdiv, dspmmu, tcdiv, perdiv, lcddiv
+         */
+#if defined(CONFIG_OMAP_ARM_216MHZ)
+        { 216000000, 12000000, 216000000, 0x050d, 0x2910 }, /* 1/1/2/2/2/8 */
+#endif
+#if defined(CONFIG_OMAP_ARM_195MHZ)
+        { 195000000, 13000000, 195000000, 0x050e, 0x2790 }, /* 1/1/2/2/4/8 */
+#endif
+#if defined(CONFIG_OMAP_ARM_192MHZ)
+        { 192000000, 19200000, 192000000, 0x050f, 0x2510 }, /* 1/1/2/2/8/8 */
+        { 192000000, 12000000, 192000000, 0x050f, 0x2810 }, /* 1/1/2/2/8/8 */
+        {  96000000, 12000000, 192000000, 0x055f, 0x2810 }, /* 2/2/2/2/8/8 */
+        {  48000000, 12000000, 192000000, 0x0baf, 0x2810 }, /* 4/4/4/8/8/8 */
+        {  24000000, 12000000, 192000000, 0x0fff, 0x2810 }, /* 8/8/8/8/8/8 */
+#endif
+#if defined(CONFIG_OMAP_ARM_182MHZ)
+        { 182000000, 13000000, 182000000, 0x050e, 0x2710 }, /* 1/1/2/2/4/8 */
+#endif
+#if defined(CONFIG_OMAP_ARM_168MHZ)
+        { 168000000, 12000000, 168000000, 0x010f, 0x2710 }, /* 1/1/1/2/8/8 */
+#endif
+#if defined(CONFIG_OMAP_ARM_150MHZ)
+        { 150000000, 12000000, 150000000, 0x010a, 0x2cb0 }, /* 1/1/1/2/4/4 */
+#endif
+#if defined(CONFIG_OMAP_ARM_120MHZ)
+        { 120000000, 12000000, 120000000, 0x010a, 0x2510 }, /* 1/1/1/2/4/4 */
+#endif
+#if defined(CONFIG_OMAP_ARM_96MHZ)
+        {  96000000, 12000000,  96000000, 0x0005, 0x2410 }, /* 1/1/1/1/2/2 */
+#endif
+#if defined(CONFIG_OMAP_ARM_60MHZ)
+        {  60000000, 12000000,  60000000, 0x0005, 0x2290 }, /* 1/1/1/1/2/2 */
+#endif
+#if defined(CONFIG_OMAP_ARM_30MHZ)
+        {  30000000, 12000000,  60000000, 0x0555, 0x2290 }, /* 2/2/2/2/2/2 */
+#endif
+        { 0, 0, 0, 0, 0 },
+};
+
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index 7309aab305a9..10eafa70a909 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -18,12 +18,25 @@ config ARCH_OMAP2430
 config ARCH_OMAP34XX
         bool "OMAP34xx Based System"
         depends on ARCH_OMAP3
+        select USB_ARCH_HAS_EHCI
 
 config ARCH_OMAP3430
         bool "OMAP3430 support"
         depends on ARCH_OMAP3 && ARCH_OMAP34XX
         select ARCH_OMAP_OTG
 
+config OMAP_PACKAGE_CBC
+       bool
+
+config OMAP_PACKAGE_CBB
+       bool
+
+config OMAP_PACKAGE_CUS
+       bool
+
+config OMAP_PACKAGE_CBP
+       bool
+
 comment "OMAP Board Type"
         depends on ARCH_OMAP2 || ARCH_OMAP3 || ARCH_OMAP4
 
@@ -52,14 +65,17 @@ config MACH_OMAP_2430SDP
 config MACH_OMAP3_BEAGLE
         bool "OMAP3 BEAGLE board"
         depends on ARCH_OMAP3 && ARCH_OMAP34XX
+        select OMAP_PACKAGE_CBB
 
 config MACH_OMAP_LDP
         bool "OMAP3 LDP board"
         depends on ARCH_OMAP3 && ARCH_OMAP34XX
+        select OMAP_PACKAGE_CBB
 
 config MACH_OVERO
         bool "Gumstix Overo board"
         depends on ARCH_OMAP3 && ARCH_OMAP34XX
+        select OMAP_PACKAGE_CBB
 
 config MACH_OMAP3EVM
         bool "OMAP 3530 EVM board"
@@ -68,14 +84,22 @@ config MACH_OMAP3EVM
 config MACH_OMAP3517EVM
         bool "OMAP3517/ AM3517 EVM board"
         depends on ARCH_OMAP3 && ARCH_OMAP34XX
+        select OMAP_PACKAGE_CBB
 
 config MACH_OMAP3_PANDORA
         bool "OMAP3 Pandora"
         depends on ARCH_OMAP3 && ARCH_OMAP34XX
+        select OMAP_PACKAGE_CBB
+
+config MACH_OMAP3_TOUCHBOOK
+        bool "OMAP3 Touch Book"
+        depends on ARCH_OMAP3 && ARCH_OMAP34XX
+        select BACKLIGHT_CLASS_DEVICE
 
 config MACH_OMAP_3430SDP
         bool "OMAP 3430 SDP board"
         depends on ARCH_OMAP3 && ARCH_OMAP34XX
+        select OMAP_PACKAGE_CBB
 
 config MACH_NOKIA_N800
        bool
@@ -96,26 +120,33 @@ config MACH_NOKIA_N8X0
 config MACH_NOKIA_RX51
         bool "Nokia RX-51 board"
         depends on ARCH_OMAP3 && ARCH_OMAP34XX
+        select OMAP_PACKAGE_CBB
 
 config MACH_OMAP_ZOOM2
         bool "OMAP3 Zoom2 board"
         depends on ARCH_OMAP3 && ARCH_OMAP34XX
+        select OMAP_PACKAGE_CBB
 
 config MACH_OMAP_ZOOM3
         bool "OMAP3630 Zoom3 board"
         depends on ARCH_OMAP3 && ARCH_OMAP34XX
+        select OMAP_PACKAGE_CBP
 
 config MACH_CM_T35
         bool "CompuLab CM-T35 module"
         depends on ARCH_OMAP3 && ARCH_OMAP34XX
+        select OMAP_PACKAGE_CUS
+        select OMAP_MUX
 
 config MACH_IGEP0020
         bool "IGEP0020"
         depends on ARCH_OMAP3 && ARCH_OMAP34XX
+        select OMAP_PACKAGE_CBB
 
 config MACH_OMAP_3630SDP
         bool "OMAP3630 SDP board"
         depends on ARCH_OMAP3 && ARCH_OMAP34XX
+        select OMAP_PACKAGE_CBP
 
 config MACH_OMAP_4430SDP
         bool "OMAP 4430 SDP board"
@@ -128,3 +159,15 @@ config OMAP3_EMU
         help
           Say Y here to enable debugging hardware of omap3
 
+config OMAP3_SDRC_AC_TIMING
+        bool "Enable SDRC AC timing register changes"
+        depends on ARCH_OMAP3 && ARCH_OMAP34XX
+        default n
+        help
+          If you know that none of your system initiators will attempt to
+          access SDRAM during CORE DVFS, select Y here.  This should boost
+          SDRAM performance at lower CORE OPPs.  There are relatively few
+          users who will wish to say yes at this point - almost everyone will
+          wish to say no.  Selecting yes without understanding what is
+          going on could result in system crashes;
+
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index 32548a4510c5..b32678b848bc 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -6,11 +6,14 @@
 obj-y := id.o io.o control.o mux.o devices.o serial.o gpmc.o timer-gp.o
 
 omap-2-3-common                         = irq.o sdrc.o omap_hwmod.o
+omap-3-4-common                         = dpll.o
 prcm-common                             = prcm.o powerdomain.o
-clock-common                            = clock.o clockdomain.o
+clock-common                            = clock.o clock_common_data.o clockdomain.o
 
 obj-$(CONFIG_ARCH_OMAP2) += $(omap-2-3-common) $(prcm-common) $(clock-common)
-obj-$(CONFIG_ARCH_OMAP3) += $(omap-2-3-common) $(prcm-common) $(clock-common)
+obj-$(CONFIG_ARCH_OMAP3) += $(omap-2-3-common) $(prcm-common) $(clock-common) \
+                            $(omap-3-4-common)
+obj-$(CONFIG_ARCH_OMAP4) += $(omap-3-4-common) prcm.o clock.o
 
 obj-$(CONFIG_OMAP_MCBSP) += mcbsp.o
 
@@ -23,6 +26,9 @@ obj-$(CONFIG_ARCH_OMAP2420)		+= sram242x.o
 obj-$(CONFIG_ARCH_OMAP2430)             += sram243x.o
 obj-$(CONFIG_ARCH_OMAP3)                += sram34xx.o
 
+# Pin multiplexing
+obj-$(CONFIG_ARCH_OMAP3)                += mux34xx.o
+
 # SMS/SDRC
 obj-$(CONFIG_ARCH_OMAP2)                += sdrc2xxx.o
 # obj-$(CONFIG_ARCH_OMAP3)              += sdrc3xxx.o
@@ -41,8 +47,11 @@ obj-$(CONFIG_ARCH_OMAP3)		+= cm.o
 obj-$(CONFIG_ARCH_OMAP4)                += cm4xxx.o
 
 # Clock framework
-obj-$(CONFIG_ARCH_OMAP2)                += clock24xx.o
-obj-$(CONFIG_ARCH_OMAP3)                += clock34xx.o
+obj-$(CONFIG_ARCH_OMAP2)                += clock2xxx.o clock2xxx_data.o
+obj-$(CONFIG_ARCH_OMAP2420)             += opp2420_data.o
+obj-$(CONFIG_ARCH_OMAP3)                += clock34xx.o clock34xx_data.o
+obj-$(CONFIG_ARCH_OMAP2430)             += opp2430_data.o
+obj-$(CONFIG_ARCH_OMAP4)                += clock44xx.o clock44xx_data.o
 
 # EMU peripherals
 obj-$(CONFIG_OMAP3_EMU)         += emu.o
@@ -55,6 +64,9 @@ iommu-$(CONFIG_ARCH_OMAP3)		+= omap3-iommu.o
 
 obj-$(CONFIG_OMAP_IOMMU)                += $(iommu-y)
 
+i2c-omap-$(CONFIG_I2C_OMAP)             := i2c.o
+obj-y                                   += $(i2c-omap-m) $(i2c-omap-y)
+
 # Specific board support
 obj-$(CONFIG_MACH_OMAP_GENERIC)         += board-generic.o
 obj-$(CONFIG_MACH_OMAP_H4)              += board-h4.o
@@ -93,7 +105,8 @@ obj-$(CONFIG_MACH_CM_T35)		+= board-cm-t35.o \
                                            mmc-twl4030.o
 obj-$(CONFIG_MACH_IGEP0020)             += board-igep0020.o \
                                            mmc-twl4030.o
-
+obj-$(CONFIG_MACH_OMAP3_TOUCHBOOK)      += board-omap3touchbook.o \
+                                           mmc-twl4030.o
 obj-$(CONFIG_MACH_OMAP_4430SDP)         += board-4430sdp.o
 
 obj-$(CONFIG_MACH_OMAP3517EVM)     += board-am3517evm.o
diff --git a/arch/arm/mach-omap2/board-2430sdp.c b/arch/arm/mach-omap2/board-2430sdp.c
index db9374bc528b..e508904fb67e 100644
--- a/arch/arm/mach-omap2/board-2430sdp.c
+++ b/arch/arm/mach-omap2/board-2430sdp.c
@@ -19,7 +19,7 @@
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/partitions.h>
 #include <linux/delay.h>
-#include <linux/i2c/twl4030.h>
+#include <linux/i2c/twl.h>
 #include <linux/err.h>
 #include <linux/clk.h>
 #include <linux/io.h>
diff --git a/arch/arm/mach-omap2/board-3430sdp.c b/arch/arm/mach-omap2/board-3430sdp.c
index 5bda9fdbee9e..c90b0d0b1927 100644
--- a/arch/arm/mach-omap2/board-3430sdp.c
+++ b/arch/arm/mach-omap2/board-3430sdp.c
@@ -20,7 +20,7 @@
 #include <linux/input/matrix_keypad.h>
 #include <linux/spi/spi.h>
 #include <linux/spi/ads7846.h>
-#include <linux/i2c/twl4030.h>
+#include <linux/i2c/twl.h>
 #include <linux/regulator/machine.h>
 #include <linux/io.h>
 #include <linux/gpio.h>
@@ -31,7 +31,6 @@
 #include <asm/mach/map.h>
 
 #include <plat/mcspi.h>
-#include <plat/mux.h>
 #include <plat/board.h>
 #include <plat/usb.h>
 #include <plat/common.h>
@@ -42,6 +41,7 @@
 #include <plat/control.h>
 #include <plat/gpmc-smc91x.h>
 
+#include "mux.h"
 #include "sdram-qimonda-hyb18m512160af-6.h"
 #include "mmc-twl4030.h"
 
@@ -625,7 +625,9 @@ static inline void board_smc91x_init(void)
 
 static void enable_board_wakeup_source(void)
 {
-        omap_cfg_reg(AF26_34XX_SYS_NIRQ); /* T2 interrupt line (keypad) */
+        /* T2 interrupt line (keypad) */
+        omap_mux_init_signal("sys_nirq",
+                OMAP_WAKEUP_EN | OMAP_PIN_INPUT_PULLUP);
 }
 
 static struct ehci_hcd_omap_platform_data ehci_pdata __initconst = {
@@ -640,8 +642,17 @@ static struct ehci_hcd_omap_platform_data ehci_pdata __initconst = {
         .reset_gpio_port[2]  = -EINVAL
 };
 
+#ifdef CONFIG_OMAP_MUX
+static struct omap_board_mux board_mux[] __initdata = {
+        { .reg_offset = OMAP_MUX_TERMINATOR },
+};
+#else
+#define board_mux       NULL
+#endif
+
 static void __init omap_3430sdp_init(void)
 {
+        omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
         omap3430_i2c_init();
         platform_add_devices(sdp3430_devices, ARRAY_SIZE(sdp3430_devices));
         if (omap_rev() > OMAP3430_REV_ES1_0)
diff --git a/arch/arm/mach-omap2/board-3630sdp.c b/arch/arm/mach-omap2/board-3630sdp.c
index 348b70b98336..739059632811 100755
--- a/arch/arm/mach-omap2/board-3630sdp.c
+++ b/arch/arm/mach-omap2/board-3630sdp.c
@@ -23,6 +23,7 @@
 
 #include <mach/board-zoom.h>
 
+#include "mux.h"
 #include "sdram-hynix-h8mbx00u0mer-0em.h"
 
 #if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
@@ -48,7 +49,9 @@ static inline void board_smc91x_init(void)
 
 static void enable_board_wakeup_source(void)
 {
-        omap_cfg_reg(AF26_34XX_SYS_NIRQ); /* T2 interrupt line (keypad) */
+        /* T2 interrupt line (keypad) */
+        omap_mux_init_signal("sys_nirq",
+                OMAP_WAKEUP_EN | OMAP_PIN_INPUT_PULLUP);
 }
 
 static struct ehci_hcd_omap_platform_data ehci_pdata __initconst = {
@@ -82,8 +85,17 @@ static void __init omap_sdp_init_irq(void)
         omap_gpio_init();
 }
 
+#ifdef CONFIG_OMAP_MUX
+static struct omap_board_mux board_mux[] __initdata = {
+        { .reg_offset = OMAP_MUX_TERMINATOR },
+};
+#else
+#define board_mux       NULL
+#endif
+
 static void __init omap_sdp_init(void)
 {
+        omap3_mux_init(board_mux, OMAP_PACKAGE_CBP);
         zoom_peripherals_init();
         board_smc91x_init();
         enable_board_wakeup_source();
diff --git a/arch/arm/mach-omap2/board-am3517evm.c b/arch/arm/mach-omap2/board-am3517evm.c
index 415a13d767cc..b4e6eca0e8a9 100644
--- a/arch/arm/mach-omap2/board-am3517evm.c
+++ b/arch/arm/mach-omap2/board-am3517evm.c
@@ -30,6 +30,8 @@
 #include <plat/common.h>
 #include <plat/usb.h>
 
+#include "mux.h"
+
 /*
  * Board initialization
  */
@@ -60,8 +62,17 @@ static struct ehci_hcd_omap_platform_data ehci_pdata __initdata = {
         .reset_gpio_port[2]  = -EINVAL
 };
 
+#ifdef CONFIG_OMAP_MUX
+static struct omap_board_mux board_mux[] __initdata = {
+        { .reg_offset = OMAP_MUX_TERMINATOR },
+};
+#else
+#define board_mux       NULL
+#endif
+
 static void __init am3517_evm_init(void)
 {
+        omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
         platform_add_devices(am3517_evm_devices,
                                 ARRAY_SIZE(am3517_evm_devices));
 
diff --git a/arch/arm/mach-omap2/board-apollon.c b/arch/arm/mach-omap2/board-apollon.c
index 8a2ce77a02ec..fbbd68d69cc8 100644
--- a/arch/arm/mach-omap2/board-apollon.c
+++ b/arch/arm/mach-omap2/board-apollon.c
@@ -26,6 +26,7 @@
 #include <linux/leds.h>
 #include <linux/err.h>
 #include <linux/clk.h>
+#include <linux/smc91x.h>
 
 #include <mach/hardware.h>
 #include <asm/mach-types.h>
@@ -120,6 +121,12 @@ static void __init apollon_flash_init(void)
         apollon_flash_resource[0].end   = base + SZ_128K - 1;
 }
 
+static struct smc91x_platdata appolon_smc91x_info = {
+        .flags  = SMC91X_USE_16BIT | SMC91X_NOWAIT,
+        .leda   = RPC_LED_100_10,
+        .ledb   = RPC_LED_TX_RX,
+};
+
 static struct resource apollon_smc91x_resources[] = {
         [0] = {
                 .flags  = IORESOURCE_MEM,
@@ -134,6 +141,9 @@ static struct resource apollon_smc91x_resources[] = {
 static struct platform_device apollon_smc91x_device = {
         .name           = "smc91x",
         .id             = -1,
+        .dev    = {
+                .platform_data  = &appolon_smc91x_info,
+        },
         .num_resources  = ARRAY_SIZE(apollon_smc91x_resources),
         .resource       = apollon_smc91x_resources,
 };
diff --git a/arch/arm/mach-omap2/board-cm-t35.c b/arch/arm/mach-omap2/board-cm-t35.c
index 22c45290db63..2626a9f8a73a 100644
--- a/arch/arm/mach-omap2/board-cm-t35.c
+++ b/arch/arm/mach-omap2/board-cm-t35.c
@@ -29,7 +29,7 @@
 #include <linux/gpio.h>
 
 #include <linux/i2c/at24.h>
-#include <linux/i2c/twl4030.h>
+#include <linux/i2c/twl.h>
 #include <linux/regulator/machine.h>
 
 #include <asm/mach-types.h>
@@ -38,13 +38,13 @@
 
 #include <plat/board.h>
 #include <plat/common.h>
-#include <plat/mux.h>
 #include <plat/nand.h>
 #include <plat/gpmc.h>
 #include <plat/usb.h>
 
 #include <mach/hardware.h>
 
+#include "mux.h"
 #include "sdram-micron-mt46h32m32lf-6.h"
 #include "mmc-twl4030.h"
 
@@ -482,8 +482,102 @@ static void __init cm_t35_map_io(void)
         omap2_map_common_io();
 }
 
+static struct omap_board_mux board_mux[] __initdata = {
+        /* nCS and IRQ for CM-T35 ethernet */
+        OMAP3_MUX(GPMC_NCS5, OMAP_MUX_MODE0),
+        OMAP3_MUX(UART3_CTS_RCTX, OMAP_MUX_MODE4 | OMAP_PIN_INPUT_PULLUP),
+
+        /* nCS and IRQ for SB-T35 ethernet */
+        OMAP3_MUX(GPMC_NCS4, OMAP_MUX_MODE0),
+        OMAP3_MUX(GPMC_WAIT3, OMAP_MUX_MODE4 | OMAP_PIN_INPUT_PULLUP),
+
+        /* PENDOWN GPIO */
+        OMAP3_MUX(GPMC_NCS6, OMAP_MUX_MODE4 | OMAP_PIN_INPUT),
+
+        /* mUSB */
+        OMAP3_MUX(HSUSB0_CLK, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
+        OMAP3_MUX(HSUSB0_STP, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
+        OMAP3_MUX(HSUSB0_DIR, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
+        OMAP3_MUX(HSUSB0_NXT, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
+        OMAP3_MUX(HSUSB0_DATA0, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
+        OMAP3_MUX(HSUSB0_DATA1, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
+        OMAP3_MUX(HSUSB0_DATA2, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
+        OMAP3_MUX(HSUSB0_DATA3, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
+        OMAP3_MUX(HSUSB0_DATA4, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
+        OMAP3_MUX(HSUSB0_DATA5, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
+        OMAP3_MUX(HSUSB0_DATA6, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
+        OMAP3_MUX(HSUSB0_DATA7, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
+
+        /* MMC 2 */
+        OMAP3_MUX(SDMMC2_DAT4, OMAP_MUX_MODE1 | OMAP_PIN_OUTPUT),
+        OMAP3_MUX(SDMMC2_DAT5, OMAP_MUX_MODE1 | OMAP_PIN_OUTPUT),
+        OMAP3_MUX(SDMMC2_DAT6, OMAP_MUX_MODE1 | OMAP_PIN_OUTPUT),
+        OMAP3_MUX(SDMMC2_DAT7, OMAP_MUX_MODE1 | OMAP_PIN_INPUT),
+
+        /* McSPI 1 */
+        OMAP3_MUX(MCSPI1_CLK, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
+        OMAP3_MUX(MCSPI1_SIMO, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
+        OMAP3_MUX(MCSPI1_SOMI, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
+        OMAP3_MUX(MCSPI1_CS0, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLDOWN),
+
+        /* McSPI 4 */
+        OMAP3_MUX(MCBSP1_CLKR, OMAP_MUX_MODE1 | OMAP_PIN_INPUT),
+        OMAP3_MUX(MCBSP1_DX, OMAP_MUX_MODE1 | OMAP_PIN_INPUT),
+        OMAP3_MUX(MCBSP1_DR, OMAP_MUX_MODE1 | OMAP_PIN_INPUT),
+        OMAP3_MUX(MCBSP1_FSX, OMAP_MUX_MODE1 | OMAP_PIN_INPUT_PULLUP),
+
+        /* McBSP 2 */
+        OMAP3_MUX(MCBSP2_FSX, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
+        OMAP3_MUX(MCBSP2_CLKX, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
+        OMAP3_MUX(MCBSP2_DR, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
+        OMAP3_MUX(MCBSP2_DX, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
+
+        /* serial ports */
+        OMAP3_MUX(MCBSP3_CLKX, OMAP_MUX_MODE1 | OMAP_PIN_OUTPUT),
+        OMAP3_MUX(MCBSP3_FSX, OMAP_MUX_MODE1 | OMAP_PIN_INPUT),
+        OMAP3_MUX(UART1_TX, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
+        OMAP3_MUX(UART1_RX, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
+
+        /* DSS */
+        OMAP3_MUX(DSS_PCLK, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
+        OMAP3_MUX(DSS_HSYNC, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
+        OMAP3_MUX(DSS_VSYNC, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
+        OMAP3_MUX(DSS_ACBIAS, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
+        OMAP3_MUX(DSS_DATA0, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
+        OMAP3_MUX(DSS_DATA1, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
+        OMAP3_MUX(DSS_DATA2, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
+        OMAP3_MUX(DSS_DATA3, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
+        OMAP3_MUX(DSS_DATA4, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
+        OMAP3_MUX(DSS_DATA5, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
+        OMAP3_MUX(DSS_DATA6, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
+        OMAP3_MUX(DSS_DATA7, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
+        OMAP3_MUX(DSS_DATA8, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
+        OMAP3_MUX(DSS_DATA9, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
+        OMAP3_MUX(DSS_DATA10, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
+        OMAP3_MUX(DSS_DATA11, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
+        OMAP3_MUX(DSS_DATA12, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
+        OMAP3_MUX(DSS_DATA13, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
+        OMAP3_MUX(DSS_DATA14, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
+        OMAP3_MUX(DSS_DATA15, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
+        OMAP3_MUX(DSS_DATA16, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
+        OMAP3_MUX(DSS_DATA17, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
+        OMAP3_MUX(DSS_DATA18, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
+        OMAP3_MUX(DSS_DATA19, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
+        OMAP3_MUX(DSS_DATA20, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
+        OMAP3_MUX(DSS_DATA21, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
+        OMAP3_MUX(DSS_DATA22, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
+        OMAP3_MUX(DSS_DATA23, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
+
+        /* TPS IRQ */
+        OMAP3_MUX(SYS_NIRQ, OMAP_MUX_MODE0 | OMAP_WAKEUP_EN | \
+                  OMAP_PIN_INPUT_PULLUP),
+
+        { .reg_offset = OMAP_MUX_TERMINATOR },
+};
+
 static void __init cm_t35_init(void)
 {
+        omap3_mux_init(board_mux, OMAP_PACKAGE_CUS);
         omap_serial_init();
         cm_t35_init_i2c();
         cm_t35_init_nand();
@@ -492,8 +586,6 @@ static void __init cm_t35_init(void)
         cm_t35_init_led();
 
         usb_musb_init();
-
-        omap_cfg_reg(AF26_34XX_SYS_NIRQ);
 }
 
 MACHINE_START(CM_T35, "Compulab CM-T35")
diff --git a/arch/arm/mach-omap2/board-igep0020.c b/arch/arm/mach-omap2/board-igep0020.c
index fa62e80c13b7..117b8fd7e3a6 100644
--- a/arch/arm/mach-omap2/board-igep0020.c
+++ b/arch/arm/mach-omap2/board-igep0020.c
@@ -19,7 +19,7 @@
 #include <linux/interrupt.h>
 
 #include <linux/regulator/machine.h>
-#include <linux/i2c/twl4030.h>
+#include <linux/i2c/twl.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -27,9 +27,9 @@
 #include <plat/board.h>
 #include <plat/common.h>
 #include <plat/gpmc.h>
-#include <plat/mux.h>
 #include <plat/usb.h>
 
+#include "mux.h"
 #include "mmc-twl4030.h"
 
 #define IGEP2_SMSC911X_CS       5
@@ -203,8 +203,17 @@ static int __init igep2_i2c_init(void)
         return 0;
 }
 
+#ifdef CONFIG_OMAP_MUX
+static struct omap_board_mux board_mux[] __initdata = {
+        { .reg_offset = OMAP_MUX_TERMINATOR },
+};
+#else
+#define board_mux       NULL
+#endif
+
 static void __init igep2_init(void)
 {
+        omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
         igep2_i2c_init();
         omap_serial_init();
         usb_musb_init();
diff --git a/arch/arm/mach-omap2/board-ldp.c b/arch/arm/mach-omap2/board-ldp.c
index c062238fe881..995d4a2b2dfd 100644
--- a/arch/arm/mach-omap2/board-ldp.c
+++ b/arch/arm/mach-omap2/board-ldp.c
@@ -24,7 +24,7 @@
 #include <linux/spi/spi.h>
 #include <linux/spi/ads7846.h>
 #include <linux/regulator/machine.h>
-#include <linux/i2c/twl4030.h>
+#include <linux/i2c/twl.h>
 #include <linux/io.h>
 #include <linux/smsc911x.h>
 
@@ -43,6 +43,7 @@
 #include <plat/control.h>
 #include <plat/usb.h>
 
+#include "mux.h"
 #include "mmc-twl4030.h"
 
 #define LDP_SMSC911X_CS         1
@@ -374,8 +375,17 @@ static struct platform_device *ldp_devices[] __initdata = {
         &ldp_gpio_keys_device,
 };
 
+#ifdef CONFIG_OMAP_MUX
+static struct omap_board_mux board_mux[] __initdata = {
+        { .reg_offset = OMAP_MUX_TERMINATOR },
+};
+#else
+#define board_mux       NULL
+#endif
+
 static void __init omap_ldp_init(void)
 {
+        omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
         omap_i2c_init();
         platform_add_devices(ldp_devices, ARRAY_SIZE(ldp_devices));
         ts_gpio = 54;
diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c
index 41480bd0e58a..231cb4ec1847 100644
--- a/arch/arm/mach-omap2/board-omap3beagle.c
+++ b/arch/arm/mach-omap2/board-omap3beagle.c
@@ -29,7 +29,7 @@
 #include <linux/mtd/nand.h>
 
 #include <linux/regulator/machine.h>
-#include <linux/i2c/twl4030.h>
+#include <linux/i2c/twl.h>
 
 #include <mach/hardware.h>
 #include <asm/mach-types.h>
@@ -41,10 +41,10 @@
 #include <plat/common.h>
 #include <plat/gpmc.h>
 #include <plat/nand.h>
-#include <plat/mux.h>
 #include <plat/usb.h>
 #include <plat/timer-gp.h>
 
+#include "mux.h"
 #include "mmc-twl4030.h"
 
 #define GPMC_CS0_BASE  0x60
@@ -140,10 +140,10 @@ static int beagle_twl_gpio_setup(struct device *dev,
                 unsigned gpio, unsigned ngpio)
 {
         if (system_rev >= 0x20 && system_rev <= 0x34301000) {
-                omap_cfg_reg(AG9_34XX_GPIO23);
+                omap_mux_init_gpio(23, OMAP_PIN_INPUT);
                 mmc[0].gpio_wp = 23;
         } else {
-                omap_cfg_reg(AH8_34XX_GPIO29);
+                omap_mux_init_gpio(29, OMAP_PIN_INPUT);
         }
         /* gpio + 0 is "mmc0_cd" (input/IRQ) */
         mmc[0].gpio_cd = gpio + 0;
@@ -422,14 +422,23 @@ static struct ehci_hcd_omap_platform_data ehci_pdata __initconst = {
         .reset_gpio_port[2]  = -EINVAL
 };
 
+#ifdef CONFIG_OMAP_MUX
+static struct omap_board_mux board_mux[] __initdata = {
+        { .reg_offset = OMAP_MUX_TERMINATOR },
+};
+#else
+#define board_mux       NULL
+#endif
+
 static void __init omap3_beagle_init(void)
 {
+        omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
         omap3_beagle_i2c_init();
         platform_add_devices(omap3_beagle_devices,
                         ARRAY_SIZE(omap3_beagle_devices));
         omap_serial_init();
 
-        omap_cfg_reg(J25_34XX_GPIO170);
+        omap_mux_init_gpio(170, OMAP_PIN_INPUT);
         gpio_request(170, "DVI_nPD");
         /* REVISIT leave DVI powered down until it's needed ... */
         gpio_direction_output(170, true);
@@ -439,8 +448,8 @@ static void __init omap3_beagle_init(void)
         omap3beagle_flash_init();
 
         /* Ensure SDRC pins are mux'd for self-refresh */
-        omap_cfg_reg(H16_34XX_SDRC_CKE0);
-        omap_cfg_reg(H17_34XX_SDRC_CKE1);
+        omap_mux_init_signal("sdrc_cke0", OMAP_PIN_OUTPUT);
+        omap_mux_init_signal("sdrc_cke1", OMAP_PIN_OUTPUT);
 }
 
 static void __init omap3_beagle_map_io(void)
diff --git a/arch/arm/mach-omap2/board-omap3evm.c b/arch/arm/mach-omap2/board-omap3evm.c
index 5efc2e9068db..34de17851572 100644
--- a/arch/arm/mach-omap2/board-omap3evm.c
+++ b/arch/arm/mach-omap2/board-omap3evm.c
@@ -26,7 +26,7 @@
 
 #include <linux/spi/spi.h>
 #include <linux/spi/ads7846.h>
-#include <linux/i2c/twl4030.h>
+#include <linux/i2c/twl.h>
 #include <linux/usb/otg.h>
 #include <linux/smsc911x.h>
 
@@ -38,11 +38,11 @@
 #include <asm/mach/map.h>
 
 #include <plat/board.h>
-#include <plat/mux.h>
 #include <plat/usb.h>
 #include <plat/common.h>
 #include <plat/mcspi.h>
 
+#include "mux.h"
 #include "sdram-micron-mt46h32m32lf-6.h"
 #include "mmc-twl4030.h"
 
@@ -223,7 +223,7 @@ static int omap3evm_twl_gpio_setup(struct device *dev,
                 unsigned gpio, unsigned ngpio)
 {
         /* gpio + 0 is "mmc0_cd" (input/IRQ) */
-        omap_cfg_reg(L8_34XX_GPIO63);
+        omap_mux_init_gpio(63, OMAP_PIN_INPUT);
         mmc[0].gpio_cd = gpio + 0;
         twl4030_mmc_init(mmc);
 
@@ -422,9 +422,18 @@ static struct ehci_hcd_omap_platform_data ehci_pdata __initconst = {
         .reset_gpio_port[2]  = -EINVAL
 };
 
+#ifdef CONFIG_OMAP_MUX
+static struct omap_board_mux board_mux[] __initdata = {
+        { .reg_offset = OMAP_MUX_TERMINATOR },
+};
+#else
+#define board_mux       NULL
+#endif
+
 static void __init omap3_evm_init(void)
 {
         omap3_evm_get_revision();
+        omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
 
         omap3_evm_i2c_init();
 
@@ -440,24 +449,24 @@ static void __init omap3_evm_init(void)
 #endif
         if (get_omap3_evm_rev() >= OMAP3EVM_BOARD_GEN_2) {
                 /* enable EHCI VBUS using GPIO22 */
-                omap_cfg_reg(AF9_34XX_GPIO22);
+                omap_mux_init_gpio(22, OMAP_PIN_INPUT_PULLUP);
                 gpio_request(OMAP3_EVM_EHCI_VBUS, "enable EHCI VBUS");
                 gpio_direction_output(OMAP3_EVM_EHCI_VBUS, 0);
                 gpio_set_value(OMAP3_EVM_EHCI_VBUS, 1);
 
                 /* Select EHCI port on main board */
-                omap_cfg_reg(U3_34XX_GPIO61);
+                omap_mux_init_gpio(61, OMAP_PIN_INPUT_PULLUP);
                 gpio_request(OMAP3_EVM_EHCI_SELECT, "select EHCI port");
                 gpio_direction_output(OMAP3_EVM_EHCI_SELECT, 0);
                 gpio_set_value(OMAP3_EVM_EHCI_SELECT, 0);
 
                 /* setup EHCI phy reset config */
-                omap_cfg_reg(AH14_34XX_GPIO21);
+                omap_mux_init_gpio(21, OMAP_PIN_INPUT_PULLUP);
                 ehci_pdata.reset_gpio_port[1] = 21;
 
         } else {
                 /* setup EHCI phy reset on MDC */
-                omap_cfg_reg(AF4_34XX_GPIO135_OUT);
+                omap_mux_init_gpio(135, OMAP_PIN_OUTPUT);
                 ehci_pdata.reset_gpio_port[1] = 135;
         }
         usb_musb_init();
diff --git a/arch/arm/mach-omap2/board-omap3pandora.c b/arch/arm/mach-omap2/board-omap3pandora.c
index 2db5ba5b3bf7..ef17cf1ab6d7 100644
--- a/arch/arm/mach-omap2/board-omap3pandora.c
+++ b/arch/arm/mach-omap2/board-omap3pandora.c
@@ -24,7 +24,7 @@
 #include <linux/spi/spi.h>
 #include <linux/spi/ads7846.h>
 #include <linux/regulator/machine.h>
-#include <linux/i2c/twl4030.h>
+#include <linux/i2c/twl.h>
 #include <linux/leds.h>
 #include <linux/input.h>
 #include <linux/input/matrix_keypad.h>
@@ -40,8 +40,8 @@
 #include <mach/hardware.h>
 #include <plat/mcspi.h>
 #include <plat/usb.h>
-#include <plat/mux.h>
 
+#include "mux.h"
 #include "sdram-micron-mt46h32m32lf-6.h"
 #include "mmc-twl4030.h"
 
@@ -98,10 +98,10 @@ static struct gpio_keys_button pandora_gpio_keys[] = {
         GPIO_BUTTON_LOW(103,    KEY_DOWN,       "down"),
         GPIO_BUTTON_LOW(96,     KEY_LEFT,       "left"),
         GPIO_BUTTON_LOW(98,     KEY_RIGHT,      "right"),
-        GPIO_BUTTON_LOW(111,    BTN_A,          "a"),
-        GPIO_BUTTON_LOW(106,    BTN_B,          "b"),
-        GPIO_BUTTON_LOW(109,    BTN_X,          "x"),
-        GPIO_BUTTON_LOW(101,    BTN_Y,          "y"),
+        GPIO_BUTTON_LOW(109,    KEY_KP1,        "game 1"),
+        GPIO_BUTTON_LOW(111,    KEY_KP2,        "game 2"),
+        GPIO_BUTTON_LOW(106,    KEY_KP3,        "game 3"),
+        GPIO_BUTTON_LOW(101,    KEY_KP4,        "game 4"),
         GPIO_BUTTON_LOW(102,    BTN_TL,         "l"),
         GPIO_BUTTON_LOW(97,     BTN_TL2,        "l2"),
         GPIO_BUTTON_LOW(105,    BTN_TR,         "r"),
@@ -315,7 +315,7 @@ static int __init omap3pandora_i2c_init(void)
         omap_register_i2c_bus(1, 2600, omap3pandora_i2c_boardinfo,
                         ARRAY_SIZE(omap3pandora_i2c_boardinfo));
         /* i2c2 pins are not connected */
-        omap_register_i2c_bus(3, 400, NULL, 0);
+        omap_register_i2c_bus(3, 100, NULL, 0);
         return 0;
 }
 
@@ -368,23 +368,8 @@ static struct spi_board_info omap3pandora_spi_board_info[] __initdata = {
         }
 };
 
-static struct platform_device omap3pandora_lcd_device = {
-        .name           = "pandora_lcd",
-        .id             = -1,
-};
-
-static struct omap_lcd_config omap3pandora_lcd_config __initdata = {
-        .ctrl_name      = "internal",
-};
-
-static struct omap_board_config_kernel omap3pandora_config[] __initdata = {
-        { OMAP_TAG_LCD,         &omap3pandora_lcd_config },
-};
-
 static void __init omap3pandora_init_irq(void)
 {
-        omap_board_config = omap3pandora_config;
-        omap_board_config_size = ARRAY_SIZE(omap3pandora_config);
         omap2_init_common_hw(mt46h32m32lf6_sdrc_params,
                              mt46h32m32lf6_sdrc_params);
         omap_init_irq();
@@ -392,7 +377,6 @@ static void __init omap3pandora_init_irq(void)
 }
 
 static struct platform_device *omap3pandora_devices[] __initdata = {
-        &omap3pandora_lcd_device,
         &pandora_leds_gpio,
         &pandora_keys_gpio,
 };
@@ -409,8 +393,17 @@ static struct ehci_hcd_omap_platform_data ehci_pdata __initconst = {
         .reset_gpio_port[2]  = -EINVAL
 };
 
+#ifdef CONFIG_OMAP_MUX
+static struct omap_board_mux board_mux[] __initdata = {
+        { .reg_offset = OMAP_MUX_TERMINATOR },
+};
+#else
+#define board_mux       NULL
+#endif
+
 static void __init omap3pandora_init(void)
 {
+        omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
         omap3pandora_i2c_init();
         platform_add_devices(omap3pandora_devices,
                         ARRAY_SIZE(omap3pandora_devices));
@@ -423,8 +416,8 @@ static void __init omap3pandora_init(void)
         usb_musb_init();
 
         /* Ensure SDRC pins are mux'd for self-refresh */
-        omap_cfg_reg(H16_34XX_SDRC_CKE0);
-        omap_cfg_reg(H17_34XX_SDRC_CKE1);
+        omap_mux_init_signal("sdrc_cke0", OMAP_PIN_OUTPUT);
+        omap_mux_init_signal("sdrc_cke1", OMAP_PIN_OUTPUT);
 }
 
 static void __init omap3pandora_map_io(void)
diff --git a/arch/arm/mach-omap2/board-omap3touchbook.c b/arch/arm/mach-omap2/board-omap3touchbook.c
new file mode 100644
index 000000000000..fe3d22cb2457
--- /dev/null
+++ b/arch/arm/mach-omap2/board-omap3touchbook.c
@@ -0,0 +1,572 @@
+/*
+ * linux/arch/arm/mach-omap2/board-omap3touchbook.c
+ *
+ * Copyright (C) 2009 Always Innovating
+ *
+ * Modified from mach-omap2/board-omap3beagleboard.c
+ *
+ * Initial code: Grégoire Gentil, Tim Yamin
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/leds.h>
+#include <linux/gpio.h>
+#include <linux/input.h>
+#include <linux/gpio_keys.h>
+
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/partitions.h>
+#include <linux/mtd/nand.h>
+
+#include <plat/mcspi.h>
+#include <linux/spi/spi.h>
+
+#include <linux/spi/ads7846.h>
+
+#include <linux/regulator/machine.h>
+#include <linux/i2c/twl.h>
+
+#include <mach/hardware.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/mach/flash.h>
+
+#include <plat/board.h>
+#include <plat/common.h>
+#include <plat/gpmc.h>
+#include <plat/nand.h>
+#include <plat/usb.h>
+#include <plat/timer-gp.h>
+
+#include "mux.h"
+#include "mmc-twl4030.h"
+
+#include <asm/setup.h>
+
+#define GPMC_CS0_BASE  0x60
+#define GPMC_CS_SIZE   0x30
+
+#define NAND_BLOCK_SIZE         SZ_128K
+
+#define OMAP3_AC_GPIO           136
+#define OMAP3_TS_GPIO           162
+#define TB_BL_PWM_TIMER         9
+#define TB_KILL_POWER_GPIO      168
+
+unsigned long touchbook_revision;
+
+static struct mtd_partition omap3touchbook_nand_partitions[] = {
+        /* All the partition sizes are listed in terms of NAND block size */
+        {
+                .name           = "X-Loader",
+                .offset         = 0,
+                .size           = 4 * NAND_BLOCK_SIZE,
+                .mask_flags     = MTD_WRITEABLE,        /* force read-only */
+        },
+        {
+                .name           = "U-Boot",
+                .offset         = MTDPART_OFS_APPEND,   /* Offset = 0x80000 */
+                .size           = 15 * NAND_BLOCK_SIZE,
+                .mask_flags     = MTD_WRITEABLE,        /* force read-only */
+        },
+        {
+                .name           = "U-Boot Env",
+                .offset         = MTDPART_OFS_APPEND,   /* Offset = 0x260000 */
+                .size           = 1 * NAND_BLOCK_SIZE,
+        },
+        {
+                .name           = "Kernel",
+                .offset         = MTDPART_OFS_APPEND,   /* Offset = 0x280000 */
+                .size           = 32 * NAND_BLOCK_SIZE,
+        },
+        {
+                .name           = "File System",
+                .offset         = MTDPART_OFS_APPEND,   /* Offset = 0x680000 */
+                .size           = MTDPART_SIZ_FULL,
+        },
+};
+
+static struct omap_nand_platform_data omap3touchbook_nand_data = {
+        .options        = NAND_BUSWIDTH_16,
+        .parts          = omap3touchbook_nand_partitions,
+        .nr_parts       = ARRAY_SIZE(omap3touchbook_nand_partitions),
+        .dma_channel    = -1,           /* disable DMA in OMAP NAND driver */
+        .nand_setup     = NULL,
+        .dev_ready      = NULL,
+};
+
+static struct resource omap3touchbook_nand_resource = {
+        .flags          = IORESOURCE_MEM,
+};
+
+static struct platform_device omap3touchbook_nand_device = {
+        .name           = "omap2-nand",
+        .id             = -1,
+        .dev            = {
+                .platform_data  = &omap3touchbook_nand_data,
+        },
+        .num_resources  = 1,
+        .resource       = &omap3touchbook_nand_resource,
+};
+
+#include "sdram-micron-mt46h32m32lf-6.h"
+
+static struct twl4030_hsmmc_info mmc[] = {
+        {
+                .mmc            = 1,
+                .wires          = 8,
+                .gpio_wp        = 29,
+        },
+        {}      /* Terminator */
+};
+
+static struct platform_device omap3_touchbook_lcd_device = {
+        .name           = "omap3touchbook_lcd",
+        .id             = -1,
+};
+
+static struct omap_lcd_config omap3_touchbook_lcd_config __initdata = {
+        .ctrl_name      = "internal",
+};
+
+static struct regulator_consumer_supply touchbook_vmmc1_supply = {
+        .supply                 = "vmmc",
+};
+
+static struct regulator_consumer_supply touchbook_vsim_supply = {
+        .supply                 = "vmmc_aux",
+};
+
+static struct gpio_led gpio_leds[];
+
+static int touchbook_twl_gpio_setup(struct device *dev,
+                unsigned gpio, unsigned ngpio)
+{
+        if (system_rev >= 0x20 && system_rev <= 0x34301000) {
+                omap_mux_init_gpio(23, OMAP_PIN_INPUT);
+                mmc[0].gpio_wp = 23;
+        } else {
+                omap_mux_init_gpio(29, OMAP_PIN_INPUT);
+        }
+        /* gpio + 0 is "mmc0_cd" (input/IRQ) */
+        mmc[0].gpio_cd = gpio + 0;
+        twl4030_mmc_init(mmc);
+
+        /* link regulators to MMC adapters */
+        touchbook_vmmc1_supply.dev = mmc[0].dev;
+        touchbook_vsim_supply.dev = mmc[0].dev;
+
+        /* REVISIT: need ehci-omap hooks for external VBUS
+         * power switch and overcurrent detect
+         */
+
+        gpio_request(gpio + 1, "EHCI_nOC");
+        gpio_direction_input(gpio + 1);
+
+        /* TWL4030_GPIO_MAX + 0 == ledA, EHCI nEN_USB_PWR (out, active low) */
+        gpio_request(gpio + TWL4030_GPIO_MAX, "nEN_USB_PWR");
+        gpio_direction_output(gpio + TWL4030_GPIO_MAX, 0);
+
+        /* TWL4030_GPIO_MAX + 1 == ledB, PMU_STAT (out, active low LED) */
+        gpio_leds[2].gpio = gpio + TWL4030_GPIO_MAX + 1;
+
+        return 0;
+}
+
+static struct twl4030_gpio_platform_data touchbook_gpio_data = {
+        .gpio_base      = OMAP_MAX_GPIO_LINES,
+        .irq_base       = TWL4030_GPIO_IRQ_BASE,
+        .irq_end        = TWL4030_GPIO_IRQ_END,
+        .use_leds       = true,
+        .pullups        = BIT(1),
+        .pulldowns      = BIT(2) | BIT(6) | BIT(7) | BIT(8) | BIT(13)
+                                | BIT(15) | BIT(16) | BIT(17),
+        .setup          = touchbook_twl_gpio_setup,
+};
+
+static struct regulator_consumer_supply touchbook_vdac_supply = {
+        .supply         = "vdac",
+        .dev            = &omap3_touchbook_lcd_device.dev,
+};
+
+static struct regulator_consumer_supply touchbook_vdvi_supply = {
+        .supply         = "vdvi",
+        .dev            = &omap3_touchbook_lcd_device.dev,
+};
+
+/* VMMC1 for MMC1 pins CMD, CLK, DAT0..DAT3 (20 mA, plus card == max 220 mA) */
+static struct regulator_init_data touchbook_vmmc1 = {
+        .constraints = {
+                .min_uV                 = 1850000,
+                .max_uV                 = 3150000,
+                .valid_modes_mask       = REGULATOR_MODE_NORMAL
+                                        | REGULATOR_MODE_STANDBY,
+                .valid_ops_mask         = REGULATOR_CHANGE_VOLTAGE
+                                        | REGULATOR_CHANGE_MODE
+                                        | REGULATOR_CHANGE_STATUS,
+        },
+        .num_consumer_supplies  = 1,
+        .consumer_supplies      = &touchbook_vmmc1_supply,
+};
+
+/* VSIM for MMC1 pins DAT4..DAT7 (2 mA, plus card == max 50 mA) */
+static struct regulator_init_data touchbook_vsim = {
+        .constraints = {
+                .min_uV                 = 1800000,
+                .max_uV                 = 3000000,
+                .valid_modes_mask       = REGULATOR_MODE_NORMAL
+                                        | REGULATOR_MODE_STANDBY,
+                .valid_ops_mask         = REGULATOR_CHANGE_VOLTAGE
+                                        | REGULATOR_CHANGE_MODE
+                                        | REGULATOR_CHANGE_STATUS,
+        },
+        .num_consumer_supplies  = 1,
+        .consumer_supplies      = &touchbook_vsim_supply,
+};
+
+/* VDAC for DSS driving S-Video (8 mA unloaded, max 65 mA) */
+static struct regulator_init_data touchbook_vdac = {
+        .constraints = {
+                .min_uV                 = 1800000,
+                .max_uV                 = 1800000,
+                .valid_modes_mask       = REGULATOR_MODE_NORMAL
+                                        | REGULATOR_MODE_STANDBY,
+                .valid_ops_mask         = REGULATOR_CHANGE_MODE
+                                        | REGULATOR_CHANGE_STATUS,
+        },
+        .num_consumer_supplies  = 1,
+        .consumer_supplies      = &touchbook_vdac_supply,
+};
+
+/* VPLL2 for digital video outputs */
+static struct regulator_init_data touchbook_vpll2 = {
+        .constraints = {
+                .name                   = "VDVI",
+                .min_uV                 = 1800000,
+                .max_uV                 = 1800000,
+                .valid_modes_mask       = REGULATOR_MODE_NORMAL
+                                        | REGULATOR_MODE_STANDBY,
+                .valid_ops_mask         = REGULATOR_CHANGE_MODE
+                                        | REGULATOR_CHANGE_STATUS,
+        },
+        .num_consumer_supplies  = 1,
+        .consumer_supplies      = &touchbook_vdvi_supply,
+};
+
+static struct twl4030_usb_data touchbook_usb_data = {
+        .usb_mode       = T2_USB_MODE_ULPI,
+};
+
+static struct twl4030_codec_audio_data touchbook_audio_data = {
+        .audio_mclk = 26000000,
+};
+
+static struct twl4030_codec_data touchbook_codec_data = {
+        .audio_mclk = 26000000,
+        .audio = &touchbook_audio_data,
+};
+
+static struct twl4030_platform_data touchbook_twldata = {
+        .irq_base       = TWL4030_IRQ_BASE,
+        .irq_end        = TWL4030_IRQ_END,
+
+        /* platform_data for children goes here */
+        .usb            = &touchbook_usb_data,
+        .gpio           = &touchbook_gpio_data,
+        .codec          = &touchbook_codec_data,
+        .vmmc1          = &touchbook_vmmc1,
+        .vsim           = &touchbook_vsim,
+        .vdac           = &touchbook_vdac,
+        .vpll2          = &touchbook_vpll2,
+};
+
+static struct i2c_board_info __initdata touchbook_i2c_boardinfo[] = {
+        {
+                I2C_BOARD_INFO("twl4030", 0x48),
+                .flags = I2C_CLIENT_WAKE,
+                .irq = INT_34XX_SYS_NIRQ,
+                .platform_data = &touchbook_twldata,
+        },
+};
+
+static struct i2c_board_info __initdata touchBook_i2c_boardinfo[] = {
+        {
+                I2C_BOARD_INFO("bq27200", 0x55),
+        },
+};
+
+static int __init omap3_touchbook_i2c_init(void)
+{
+        /* Standard TouchBook bus */
+        omap_register_i2c_bus(1, 2600, touchbook_i2c_boardinfo,
+                        ARRAY_SIZE(touchbook_i2c_boardinfo));
+
+        /* Additional TouchBook bus */
+        omap_register_i2c_bus(3, 100, touchBook_i2c_boardinfo,
+                        ARRAY_SIZE(touchBook_i2c_boardinfo));
+
+        return 0;
+}
+
+static void __init omap3_ads7846_init(void)
+{
+        if (gpio_request(OMAP3_TS_GPIO, "ads7846_pen_down")) {
+                printk(KERN_ERR "Failed to request GPIO %d for "
+                                "ads7846 pen down IRQ\n", OMAP3_TS_GPIO);
+                return;
+        }
+
+        gpio_direction_input(OMAP3_TS_GPIO);
+        omap_set_gpio_debounce(OMAP3_TS_GPIO, 1);
+        omap_set_gpio_debounce_time(OMAP3_TS_GPIO, 0xa);
+}
+
+static struct ads7846_platform_data ads7846_config = {
+        .x_min                  = 100,
+        .y_min                  = 265,
+        .x_max                  = 3950,
+        .y_max                  = 3750,
+        .x_plate_ohms           = 40,
+        .pressure_max           = 255,
+        .debounce_max           = 10,
+        .debounce_tol           = 5,
+        .debounce_rep           = 1,
+        .gpio_pendown           = OMAP3_TS_GPIO,
+        .keep_vref_on           = 1,
+};
+
+static struct omap2_mcspi_device_config ads7846_mcspi_config = {
+        .turbo_mode     = 0,
+        .single_channel = 1,    /* 0: slave, 1: master */
+};
+
+static struct spi_board_info omap3_ads7846_spi_board_info[] __initdata = {
+        {
+                .modalias               = "ads7846",
+                .bus_num                = 4,
+                .chip_select            = 0,
+                .max_speed_hz           = 1500000,
+                .controller_data        = &ads7846_mcspi_config,
+                .irq                    = OMAP_GPIO_IRQ(OMAP3_TS_GPIO),
+                .platform_data          = &ads7846_config,
+        }
+};
+
+static struct gpio_led gpio_leds[] = {
+        {
+                .name                   = "touchbook::usr0",
+                .default_trigger        = "heartbeat",
+                .gpio                   = 150,
+        },
+        {
+                .name                   = "touchbook::usr1",
+                .default_trigger        = "mmc0",
+                .gpio                   = 149,
+        },
+        {
+                .name                   = "touchbook::pmu_stat",
+                .gpio                   = -EINVAL,      /* gets replaced */
+                .active_low             = true,
+        },
+};
+
+static struct gpio_led_platform_data gpio_led_info = {
+        .leds           = gpio_leds,
+        .num_leds       = ARRAY_SIZE(gpio_leds),
+};
+
+static struct platform_device leds_gpio = {
+        .name   = "leds-gpio",
+        .id     = -1,
+        .dev    = {
+                .platform_data  = &gpio_led_info,
+        },
+};
+
+static struct gpio_keys_button gpio_buttons[] = {
+        {
+                .code                   = BTN_EXTRA,
+                .gpio                   = 7,
+                .desc                   = "user",
+                .wakeup                 = 1,
+        },
+        {
+                .code                   = KEY_POWER,
+                .gpio                   = 183,
+                .desc                   = "power",
+                .wakeup                 = 1,
+        },
+};
+
+static struct gpio_keys_platform_data gpio_key_info = {
+        .buttons        = gpio_buttons,
+        .nbuttons       = ARRAY_SIZE(gpio_buttons),
+};
+
+static struct platform_device keys_gpio = {
+        .name   = "gpio-keys",
+        .id     = -1,
+        .dev    = {
+                .platform_data  = &gpio_key_info,
+        },
+};
+
+static struct omap_board_config_kernel omap3_touchbook_config[] __initdata = {
+        { OMAP_TAG_LCD,         &omap3_touchbook_lcd_config },
+};
+
+#ifdef CONFIG_OMAP_MUX
+static struct omap_board_mux board_mux[] __initdata = {
+        { .reg_offset = OMAP_MUX_TERMINATOR },
+};
+#else
+#define board_mux       NULL
+#endif
+
+static void __init omap3_touchbook_init_irq(void)
+{
+        omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
+        omap_board_config = omap3_touchbook_config;
+        omap_board_config_size = ARRAY_SIZE(omap3_touchbook_config);
+        omap2_init_common_hw(mt46h32m32lf6_sdrc_params,
+                             mt46h32m32lf6_sdrc_params);
+        omap_init_irq();
+#ifdef CONFIG_OMAP_32K_TIMER
+        omap2_gp_clockevent_set_gptimer(12);
+#endif
+        omap_gpio_init();
+}
+
+static struct platform_device *omap3_touchbook_devices[] __initdata = {
+        &omap3_touchbook_lcd_device,
+        &leds_gpio,
+        &keys_gpio,
+};
+
+static void __init omap3touchbook_flash_init(void)
+{
+        u8 cs = 0;
+        u8 nandcs = GPMC_CS_NUM + 1;
+
+        u32 gpmc_base_add = OMAP34XX_GPMC_VIRT;
+
+        /* find out the chip-select on which NAND exists */
+        while (cs < GPMC_CS_NUM) {
+                u32 ret = 0;
+                ret = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
+
+                if ((ret & 0xC00) == 0x800) {
+                        printk(KERN_INFO "Found NAND on CS%d\n", cs);
+                        if (nandcs > GPMC_CS_NUM)
+                                nandcs = cs;
+                }
+                cs++;
+        }
+
+        if (nandcs > GPMC_CS_NUM) {
+                printk(KERN_INFO "NAND: Unable to find configuration "
+                                 "in GPMC\n ");
+                return;
+        }
+
+        if (nandcs < GPMC_CS_NUM) {
+                omap3touchbook_nand_data.cs = nandcs;
+                omap3touchbook_nand_data.gpmc_cs_baseaddr = (void *)
+                        (gpmc_base_add + GPMC_CS0_BASE + nandcs * GPMC_CS_SIZE);
+                omap3touchbook_nand_data.gpmc_baseaddr =
+                                                (void *) (gpmc_base_add);
+
+                printk(KERN_INFO "Registering NAND on CS%d\n", nandcs);
+                if (platform_device_register(&omap3touchbook_nand_device) < 0)
+                        printk(KERN_ERR "Unable to register NAND device\n");
+        }
+}
+
+static struct ehci_hcd_omap_platform_data ehci_pdata __initconst = {
+
+        .port_mode[0] = EHCI_HCD_OMAP_MODE_PHY,
+        .port_mode[1] = EHCI_HCD_OMAP_MODE_PHY,
+        .port_mode[2] = EHCI_HCD_OMAP_MODE_UNKNOWN,
+
+        .phy_reset  = true,
+        .reset_gpio_port[0]  = -EINVAL,
+        .reset_gpio_port[1]  = 147,
+        .reset_gpio_port[2]  = -EINVAL
+};
+
+static void omap3_touchbook_poweroff(void)
+{
+        int r;
+
+        r = gpio_request(TB_KILL_POWER_GPIO, "DVI reset");
+        if (r < 0) {
+                printk(KERN_ERR "Unable to get kill power GPIO\n");
+                return;
+        }
+
+        gpio_direction_output(TB_KILL_POWER_GPIO, 0);
+}
+
+static void __init early_touchbook_revision(char **p)
+{
+        if (!*p)
+                return;
+
+        strict_strtoul(*p, 10, &touchbook_revision);
+}
+__early_param("tbr=", early_touchbook_revision);
+
+static void __init omap3_touchbook_init(void)
+{
+        pm_power_off = omap3_touchbook_poweroff;
+
+        omap3_touchbook_i2c_init();
+        platform_add_devices(omap3_touchbook_devices,
+                        ARRAY_SIZE(omap3_touchbook_devices));
+        omap_serial_init();
+
+        omap_mux_init_gpio(170, OMAP_PIN_INPUT);
+        gpio_request(176, "DVI_nPD");
+        /* REVISIT leave DVI powered down until it's needed ... */
+        gpio_direction_output(176, true);
+
+        /* Touchscreen and accelerometer */
+        spi_register_board_info(omap3_ads7846_spi_board_info,
+                                ARRAY_SIZE(omap3_ads7846_spi_board_info));
+        omap3_ads7846_init();
+        usb_musb_init();
+        usb_ehci_init(&ehci_pdata);
+        omap3touchbook_flash_init();
+
+        /* Ensure SDRC pins are mux'd for self-refresh */
+        omap_mux_init_signal("sdrc_cke0", OMAP_PIN_OUTPUT);
+        omap_mux_init_signal("sdrc_cke1", OMAP_PIN_OUTPUT);
+}
+
+static void __init omap3_touchbook_map_io(void)
+{
+        omap2_set_globals_343x();
+        omap2_map_common_io();
+}
+
+MACHINE_START(TOUCHBOOK, "OMAP3 touchbook Board")
+        /* Maintainer: Gregoire Gentil - http://www.alwaysinnovating.com */
+        .phys_io        = 0x48000000,
+        .io_pg_offst    = ((0xd8000000) >> 18) & 0xfffc,
+        .boot_params    = 0x80000100,
+        .map_io         = omap3_touchbook_map_io,
+        .init_irq       = omap3_touchbook_init_irq,
+        .init_machine   = omap3_touchbook_init,
+        .timer          = &omap_timer,
+MACHINE_END
diff --git a/arch/arm/mach-omap2/board-overo.c b/arch/arm/mach-omap2/board-overo.c
index 52dfd51a938e..d192dd98a591 100644
--- a/arch/arm/mach-omap2/board-overo.c
+++ b/arch/arm/mach-omap2/board-overo.c
@@ -26,7 +26,7 @@
 #include <linux/io.h>
 #include <linux/kernel.h>
 #include <linux/platform_device.h>
-#include <linux/i2c/twl4030.h>
+#include <linux/i2c/twl.h>
 #include <linux/regulator/machine.h>
 
 #include <linux/mtd/mtd.h>
@@ -44,9 +44,9 @@
 #include <plat/gpmc.h>
 #include <mach/hardware.h>
 #include <plat/nand.h>
-#include <plat/mux.h>
 #include <plat/usb.h>
 
+#include "mux.h"
 #include "sdram-micron-mt46h32m32lf-6.h"
 #include "mmc-twl4030.h"
 
@@ -405,9 +405,17 @@ static struct ehci_hcd_omap_platform_data ehci_pdata __initconst = {
         .reset_gpio_port[2]  = -EINVAL
 };
 
+#ifdef CONFIG_OMAP_MUX
+static struct omap_board_mux board_mux[] __initdata = {
+        { .reg_offset = OMAP_MUX_TERMINATOR },
+};
+#else
+#define board_mux       NULL
+#endif
 
 static void __init overo_init(void)
 {
+        omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
         overo_i2c_init();
         platform_add_devices(overo_devices, ARRAY_SIZE(overo_devices));
         omap_serial_init();
@@ -418,8 +426,8 @@ static void __init overo_init(void)
         overo_init_smsc911x();
 
         /* Ensure SDRC pins are mux'd for self-refresh */
-        omap_cfg_reg(H16_34XX_SDRC_CKE0);
-        omap_cfg_reg(H17_34XX_SDRC_CKE1);
+        omap_mux_init_signal("sdrc_cke0", OMAP_PIN_OUTPUT);
+        omap_mux_init_signal("sdrc_cke1", OMAP_PIN_OUTPUT);
 
         if ((gpio_request(OVERO_GPIO_W2W_NRESET,
                           "OVERO_GPIO_W2W_NRESET") == 0) &&
diff --git a/arch/arm/mach-omap2/board-rx51-peripherals.c b/arch/arm/mach-omap2/board-rx51-peripherals.c
index 15ce6514c5fd..acafdbc8aa16 100644
--- a/arch/arm/mach-omap2/board-rx51-peripherals.c
+++ b/arch/arm/mach-omap2/board-rx51-peripherals.c
@@ -16,7 +16,7 @@
 #include <linux/spi/spi.h>
 #include <linux/spi/wl12xx.h>
 #include <linux/i2c.h>
-#include <linux/i2c/twl4030.h>
+#include <linux/i2c/twl.h>
 #include <linux/clk.h>
 #include <linux/delay.h>
 #include <linux/regulator/machine.h>
@@ -33,6 +33,7 @@
 #include <plat/onenand.h>
 #include <plat/gpmc-smc91x.h>
 
+#include "mux.h"
 #include "mmc-twl4030.h"
 
 #define SYSTEM_REV_B_USES_VAUX3 0x1699
@@ -59,7 +60,7 @@ static struct spi_board_info rx51_peripherals_spi_board_info[] __initdata = {
                 .bus_num                = 4,
                 .chip_select            = 0,
                 .max_speed_hz           = 48000000,
-                .mode                   = SPI_MODE_2,
+                .mode                   = SPI_MODE_3,
                 .controller_data        = &wl1251_mcspi_config,
                 .platform_data          = &wl1251_pdata,
         },
@@ -401,15 +402,9 @@ static struct twl4030_usb_data rx51_usb_data = {
 
 static struct twl4030_ins sleep_on_seq[] __initdata = {
 /*
- * Turn off VDD1 and VDD2.
+ * Turn off everything
  */
-        {MSG_SINGULAR(DEV_GRP_P1, 0xf, RES_STATE_OFF), 4},
-        {MSG_SINGULAR(DEV_GRP_P1, 0x10, RES_STATE_OFF), 2},
-/*
- * And also turn off the OMAP3 PLLs and the sysclk output.
- */
-        {MSG_SINGULAR(DEV_GRP_P1, 0x7, RES_STATE_OFF), 3},
-        {MSG_SINGULAR(DEV_GRP_P1, 0x17, RES_STATE_OFF), 3},
+        {MSG_BROADCAST(DEV_GRP_NULL, RES_GRP_ALL, 1, 0, RES_STATE_SLEEP), 2},
 };
 
 static struct twl4030_script sleep_on_script __initdata = {
@@ -420,14 +415,9 @@ static struct twl4030_script sleep_on_script __initdata = {
 
 static struct twl4030_ins wakeup_seq[] __initdata = {
 /*
- * Reenable the OMAP3 PLLs.
- * Wakeup VDD1 and VDD2.
- * Reenable sysclk output.
+ * Reenable everything
  */
-        {MSG_SINGULAR(DEV_GRP_P1, 0x7, RES_STATE_ACTIVE), 0x30},
-        {MSG_SINGULAR(DEV_GRP_P1, 0xf, RES_STATE_ACTIVE), 0x30},
-        {MSG_SINGULAR(DEV_GRP_P1, 0x10, RES_STATE_ACTIVE), 0x37},
-        {MSG_SINGULAR(DEV_GRP_P1, 0x19, RES_STATE_ACTIVE), 3},
+        {MSG_BROADCAST(DEV_GRP_NULL, RES_GRP_ALL, 1, 0, RES_STATE_ACTIVE), 2},
 };
 
 static struct twl4030_script wakeup_script __initdata = {
@@ -438,10 +428,9 @@ static struct twl4030_script wakeup_script __initdata = {
 
 static struct twl4030_ins wakeup_p3_seq[] __initdata = {
 /*
- * Wakeup VDD1 (dummy to be able to insert a delay)
- * Enable CLKEN
+ * Reenable everything
  */
-        {MSG_SINGULAR(DEV_GRP_P1, 0x17, RES_STATE_ACTIVE), 3},
+        {MSG_BROADCAST(DEV_GRP_NULL, RES_GRP_ALL, 1, 0, RES_STATE_ACTIVE), 2},
 };
 
 static struct twl4030_script wakeup_p3_script __initdata = {
@@ -462,12 +451,11 @@ static struct twl4030_ins wrst_seq[] __initdata = {
         {MSG_SINGULAR(DEV_GRP_NULL, RES_RESET, RES_STATE_OFF), 2},
         {MSG_BROADCAST(DEV_GRP_NULL, RES_GRP_ALL, 0, 1, RES_STATE_ACTIVE),
                 0x13},
-        {MSG_BROADCAST(DEV_GRP_NULL, RES_GRP_PP, 0, 2, RES_STATE_WRST), 0x13},
         {MSG_BROADCAST(DEV_GRP_NULL, RES_GRP_PP, 0, 3, RES_STATE_OFF), 0x13},
         {MSG_SINGULAR(DEV_GRP_NULL, RES_VDD1, RES_STATE_WRST), 0x13},
         {MSG_SINGULAR(DEV_GRP_NULL, RES_VDD2, RES_STATE_WRST), 0x13},
         {MSG_SINGULAR(DEV_GRP_NULL, RES_VPLL1, RES_STATE_WRST), 0x35},
-        {MSG_SINGULAR(DEV_GRP_P1, RES_HFCLKOUT, RES_STATE_ACTIVE), 2},
+        {MSG_SINGULAR(DEV_GRP_P3, RES_HFCLKOUT, RES_STATE_ACTIVE), 2},
         {MSG_SINGULAR(DEV_GRP_NULL, RES_RESET, RES_STATE_ACTIVE), 2},
 };
 
@@ -489,22 +477,81 @@ static struct twl4030_script *twl4030_scripts[] __initdata = {
 };
 
 static struct twl4030_resconfig twl4030_rconfig[] __initdata = {
-        { .resource = RES_VINTANA1, .devgroup = -1, .type = -1, .type2 = 1 },
-        { .resource = RES_VINTANA2, .devgroup = -1, .type = -1, .type2 = 1 },
-        { .resource = RES_VINTDIG, .devgroup = -1, .type = -1, .type2 = 1 },
-        { .resource = RES_VMMC1, .devgroup = -1, .type = -1, .type2 = 3},
-        { .resource = RES_VMMC2, .devgroup = DEV_GRP_NULL, .type = -1,
-          .type2 = 3},
-        { .resource = RES_VAUX1, .devgroup = -1, .type = -1, .type2 = 3},
-        { .resource = RES_VAUX2, .devgroup = -1, .type = -1, .type2 = 3},
-        { .resource = RES_VAUX3, .devgroup = -1, .type = -1, .type2 = 3},
-        { .resource = RES_VAUX4, .devgroup = -1, .type = -1, .type2 = 3},
-        { .resource = RES_VPLL2, .devgroup = -1, .type = -1, .type2 = 3},
-        { .resource = RES_VDAC, .devgroup = -1, .type = -1, .type2 = 3},
-        { .resource = RES_VSIM, .devgroup = DEV_GRP_NULL, .type = -1,
-          .type2 = 3},
-        { .resource = RES_CLKEN, .devgroup = DEV_GRP_P3, .type = -1,
-                .type2 = 1 },
+        { .resource = RES_VDD1, .devgroup = -1,
+          .type = 1, .type2 = -1, .remap_off = RES_STATE_OFF,
+          .remap_sleep = RES_STATE_OFF
+        },
+        { .resource = RES_VDD2, .devgroup = -1,
+          .type = 1, .type2 = -1, .remap_off = RES_STATE_OFF,
+          .remap_sleep = RES_STATE_OFF
+        },
+        { .resource = RES_VPLL1, .devgroup = -1,
+          .type = 1, .type2 = -1, .remap_off = RES_STATE_OFF,
+          .remap_sleep = RES_STATE_OFF
+        },
+        { .resource = RES_VPLL2, .devgroup = -1,
+          .type = -1, .type2 = 3, .remap_off = -1, .remap_sleep = -1
+        },
+        { .resource = RES_VAUX1, .devgroup = -1,
+          .type = -1, .type2 = 3, .remap_off = -1, .remap_sleep = -1
+        },
+        { .resource = RES_VAUX2, .devgroup = -1,
+          .type = -1, .type2 = 3, .remap_off = -1, .remap_sleep = -1
+        },
+        { .resource = RES_VAUX3, .devgroup = -1,
+          .type = -1, .type2 = 3, .remap_off = -1, .remap_sleep = -1
+        },
+        { .resource = RES_VAUX4, .devgroup = -1,
+          .type = -1, .type2 = 3, .remap_off = -1, .remap_sleep = -1
+        },
+        { .resource = RES_VMMC1, .devgroup = -1,
+          .type = -1, .type2 = 3, .remap_off = -1, .remap_sleep = -1
+        },
+        { .resource = RES_VMMC2, .devgroup = -1,
+          .type = -1, .type2 = 3, .remap_off = -1, .remap_sleep = -1
+        },
+        { .resource = RES_VDAC, .devgroup = -1,
+          .type = -1, .type2 = 3, .remap_off = -1, .remap_sleep = -1
+        },
+        { .resource = RES_VSIM, .devgroup = -1,
+          .type = -1, .type2 = 3, .remap_off = -1, .remap_sleep = -1
+        },
+        { .resource = RES_VINTANA1, .devgroup = DEV_GRP_P1 | DEV_GRP_P3,
+          .type = -1, .type2 = -1, .remap_off = -1, .remap_sleep = -1
+        },
+        { .resource = RES_VINTANA2, .devgroup = DEV_GRP_P1 | DEV_GRP_P3,
+          .type = 1, .type2 = -1, .remap_off = -1, .remap_sleep = -1
+        },
+        { .resource = RES_VINTDIG, .devgroup = DEV_GRP_P1 | DEV_GRP_P3,
+          .type = -1, .type2 = -1, .remap_off = -1, .remap_sleep = -1
+        },
+        { .resource = RES_VIO, .devgroup = DEV_GRP_P3,
+          .type = 1, .type2 = -1, .remap_off = -1, .remap_sleep = -1
+        },
+        { .resource = RES_CLKEN, .devgroup = DEV_GRP_P1 | DEV_GRP_P3,
+          .type = 1, .type2 = -1 , .remap_off = -1, .remap_sleep = -1
+        },
+        { .resource = RES_REGEN, .devgroup = DEV_GRP_P1 | DEV_GRP_P3,
+          .type = 1, .type2 = -1, .remap_off = -1, .remap_sleep = -1
+        },
+        { .resource = RES_NRES_PWRON, .devgroup = DEV_GRP_P1 | DEV_GRP_P3,
+          .type = 1, .type2 = -1, .remap_off = -1, .remap_sleep = -1
+        },
+        { .resource = RES_SYSEN, .devgroup = DEV_GRP_P1 | DEV_GRP_P3,
+          .type = 1, .type2 = -1, .remap_off = -1, .remap_sleep = -1
+        },
+        { .resource = RES_HFCLKOUT, .devgroup = DEV_GRP_P3,
+          .type = 1, .type2 = -1, .remap_off = -1, .remap_sleep = -1
+        },
+        { .resource = RES_32KCLKOUT, .devgroup = -1,
+          .type = 1, .type2 = -1, .remap_off = -1, .remap_sleep = -1
+        },
+        { .resource = RES_RESET, .devgroup = -1,
+          .type = 1, .type2 = -1, .remap_off = -1, .remap_sleep = -1
+        },
+        { .resource = RES_Main_Ref, .devgroup = -1,
+          .type = 1, .type2 = -1, .remap_off = -1, .remap_sleep = -1
+        },
         { 0, 0},
 };
 
@@ -630,9 +677,9 @@ static struct omap_smc91x_platform_data board_smc91x_data = {
 
 static void __init board_smc91x_init(void)
 {
-        omap_cfg_reg(U8_34XX_GPIO54_DOWN);
-        omap_cfg_reg(G25_34XX_GPIO86_OUT);
-        omap_cfg_reg(H19_34XX_GPIO164_OUT);
+        omap_mux_init_gpio(54, OMAP_PIN_INPUT_PULLDOWN);
+        omap_mux_init_gpio(86, OMAP_PIN_OUTPUT);
+        omap_mux_init_gpio(164, OMAP_PIN_OUTPUT);
 
         gpmc_smc91x_init(&board_smc91x_data);
 }
diff --git a/arch/arm/mach-omap2/board-rx51.c b/arch/arm/mach-omap2/board-rx51.c
index 1bb1de245917..67bb3476b707 100644
--- a/arch/arm/mach-omap2/board-rx51.c
+++ b/arch/arm/mach-omap2/board-rx51.c
@@ -23,13 +23,14 @@
 #include <asm/mach/map.h>
 
 #include <plat/mcspi.h>
-#include <plat/mux.h>
 #include <plat/board.h>
 #include <plat/common.h>
 #include <plat/dma.h>
 #include <plat/gpmc.h>
 #include <plat/usb.h>
 
+#include "mux.h"
+
 struct omap_sdrc_params *rx51_get_sdram_timings(void);
 
 static struct omap_lcd_config rx51_lcd_config = {
@@ -69,15 +70,24 @@ static void __init rx51_init_irq(void)
 
 extern void __init rx51_peripherals_init(void);
 
+#ifdef CONFIG_OMAP_MUX
+static struct omap_board_mux board_mux[] __initdata = {
+        { .reg_offset = OMAP_MUX_TERMINATOR },
+};
+#else
+#define board_mux       NULL
+#endif
+
 static void __init rx51_init(void)
 {
+        omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
         omap_serial_init();
         usb_musb_init();
         rx51_peripherals_init();
 
         /* Ensure SDRC pins are mux'd for self-refresh */
-        omap_cfg_reg(H16_34XX_SDRC_CKE0);
-        omap_cfg_reg(H17_34XX_SDRC_CKE1);
+        omap_mux_init_signal("sdrc_cke0", OMAP_PIN_OUTPUT);
+        omap_mux_init_signal("sdrc_cke1", OMAP_PIN_OUTPUT);
 }
 
 static void __init rx51_map_io(void)
diff --git a/arch/arm/mach-omap2/board-zoom-peripherals.c b/arch/arm/mach-omap2/board-zoom-peripherals.c
index f14baa392760..8dd277c36661 100755
--- a/arch/arm/mach-omap2/board-zoom-peripherals.c
+++ b/arch/arm/mach-omap2/board-zoom-peripherals.c
@@ -14,7 +14,7 @@
 #include <linux/input.h>
 #include <linux/input/matrix_keypad.h>
 #include <linux/gpio.h>
-#include <linux/i2c/twl4030.h>
+#include <linux/i2c/twl.h>
 #include <linux/regulator/machine.h>
 
 #include <asm/mach-types.h>
@@ -152,14 +152,20 @@ static struct regulator_init_data zoom_vsim = {
 
 static struct twl4030_hsmmc_info mmc[] __initdata = {
         {
+                .name           = "external",
                 .mmc            = 1,
                 .wires          = 4,
                 .gpio_wp        = -EINVAL,
+                .power_saving   = true,
         },
         {
+                .name           = "internal",
                 .mmc            = 2,
-                .wires          = 4,
+                .wires          = 8,
+                .gpio_cd        = -EINVAL,
                 .gpio_wp        = -EINVAL,
+                .nonremovable   = true,
+                .power_saving   = true,
         },
         {}      /* Terminator */
 };
@@ -167,11 +173,8 @@ static struct twl4030_hsmmc_info mmc[] __initdata = {
 static int zoom_twl_gpio_setup(struct device *dev,
                 unsigned gpio, unsigned ngpio)
 {
-        /* gpio + 0 is "mmc0_cd" (input/IRQ),
-         * gpio + 1 is "mmc1_cd" (input/IRQ)
-         */
+        /* gpio + 0 is "mmc0_cd" (input/IRQ) */
         mmc[0].gpio_cd = gpio + 0;
-        mmc[1].gpio_cd = gpio + 1;
         twl4030_mmc_init(mmc);
 
         /* link regulators to MMC adapters ... we "know" the
@@ -236,6 +239,7 @@ static struct twl4030_platform_data zoom_twldata = {
         .gpio           = &zoom_gpio_data,
         .keypad         = &zoom_kp_twl4030_data,
         .codec          = &zoom_codec_data,
+        .vmmc1          = &zoom_vmmc1,
         .vmmc2          = &zoom_vmmc2,
         .vsim           = &zoom_vsim,
 
diff --git a/arch/arm/mach-omap2/board-zoom2.c b/arch/arm/mach-omap2/board-zoom2.c
index d94d047c7dce..bb87cf7878ff 100644
--- a/arch/arm/mach-omap2/board-zoom2.c
+++ b/arch/arm/mach-omap2/board-zoom2.c
@@ -23,6 +23,7 @@
 
 #include <mach/board-zoom.h>
 
+#include "mux.h"
 #include "sdram-micron-mt46h32m32lf-6.h"
 
 static void __init omap_zoom2_init_irq(void)
@@ -68,8 +69,17 @@ static struct twl4030_platform_data zoom2_twldata = {
 
 #endif
 
+#ifdef CONFIG_OMAP_MUX
+static struct omap_board_mux board_mux[] __initdata = {
+        { .reg_offset = OMAP_MUX_TERMINATOR },
+};
+#else
+#define board_mux       NULL
+#endif
+
 static void __init omap_zoom2_init(void)
 {
+        omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
         zoom_peripherals_init();
         zoom_debugboard_init();
 }
diff --git a/arch/arm/mach-omap2/board-zoom3.c b/arch/arm/mach-omap2/board-zoom3.c
index 8d965a6516c8..a9fe9181b010 100644
--- a/arch/arm/mach-omap2/board-zoom3.c
+++ b/arch/arm/mach-omap2/board-zoom3.c
@@ -21,6 +21,7 @@
 #include <plat/common.h>
 #include <plat/board.h>
 
+#include "mux.h"
 #include "sdram-hynix-h8mbx00u0mer-0em.h"
 
 static void __init omap_zoom_map_io(void)
@@ -42,8 +43,17 @@ static void __init omap_zoom_init_irq(void)
         omap_gpio_init();
 }
 
+#ifdef CONFIG_OMAP_MUX
+static struct omap_board_mux board_mux[] __initdata = {
+        { .reg_offset = OMAP_MUX_TERMINATOR },
+};
+#else
+#define board_mux       NULL
+#endif
+
 static void __init omap_zoom_init(void)
 {
+        omap3_mux_init(board_mux, OMAP_PACKAGE_CBP);
         zoom_peripherals_init();
         zoom_debugboard_init();
 }
diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index 4716206547ac..759c72a48f7f 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -70,9 +70,41 @@
 u8 cpu_mask;
 
 /*-------------------------------------------------------------------------
- * OMAP2/3 specific clock functions
+ * OMAP2/3/4 specific clock functions
  *-------------------------------------------------------------------------*/
 
+void omap2_init_dpll_parent(struct clk *clk)
+{
+        u32 v;
+        struct dpll_data *dd;
+
+        dd = clk->dpll_data;
+        if (!dd)
+                return;
+
+        /* Return bypass rate if DPLL is bypassed */
+        v = __raw_readl(dd->control_reg);
+        v &= dd->enable_mask;
+        v >>= __ffs(dd->enable_mask);
+
+        /* Reparent in case the dpll is in bypass */
+        if (cpu_is_omap24xx()) {
+                if (v == OMAP2XXX_EN_DPLL_LPBYPASS ||
+                    v == OMAP2XXX_EN_DPLL_FRBYPASS)
+                        clk_reparent(clk, dd->clk_bypass);
+        } else if (cpu_is_omap34xx()) {
+                if (v == OMAP3XXX_EN_DPLL_LPBYPASS ||
+                    v == OMAP3XXX_EN_DPLL_FRBYPASS)
+                        clk_reparent(clk, dd->clk_bypass);
+        } else if (cpu_is_omap44xx()) {
+                if (v == OMAP4XXX_EN_DPLL_LPBYPASS ||
+                    v == OMAP4XXX_EN_DPLL_FRBYPASS ||
+                    v == OMAP4XXX_EN_DPLL_MNBYPASS)
+                        clk_reparent(clk, dd->clk_bypass);
+        }
+        return;
+}
+
 /**
  * _omap2xxx_clk_commit - commit clock parent/rate changes in hardware
  * @clk: struct clk *
@@ -149,6 +181,7 @@ static int _dpll_test_fint(struct clk *clk, u8 n)
  * clockdomain pointer, and save it into the struct clk.  Intended to be
  * called during clk_register().  No return value.
  */
+#ifndef CONFIG_ARCH_OMAP4 /* FIXME: Remove this once clkdm f/w is in place */
 void omap2_init_clk_clkdm(struct clk *clk)
 {
         struct clockdomain *clkdm;
@@ -166,6 +199,7 @@ void omap2_init_clk_clkdm(struct clk *clk)
                          "clkdm %s\n", clk->name, clk->clkdm_name);
         }
 }
+#endif
 
 /**
  * omap2_init_clksel_parent - set a clksel clk's parent field from the hardware
@@ -247,6 +281,11 @@ u32 omap2_get_dpll_rate(struct clk *clk)
                 if (v == OMAP3XXX_EN_DPLL_LPBYPASS ||
                     v == OMAP3XXX_EN_DPLL_FRBYPASS)
                         return dd->clk_bypass->rate;
+        } else if (cpu_is_omap44xx()) {
+                if (v == OMAP4XXX_EN_DPLL_LPBYPASS ||
+                    v == OMAP4XXX_EN_DPLL_FRBYPASS ||
+                    v == OMAP4XXX_EN_DPLL_MNBYPASS)
+                        return dd->clk_bypass->rate;
         }
 
         v = __raw_readl(dd->mult_div1_reg);
@@ -437,8 +476,10 @@ void omap2_clk_disable(struct clk *clk)
                 _omap2_clk_disable(clk);
                 if (clk->parent)
                         omap2_clk_disable(clk->parent);
+#ifndef CONFIG_ARCH_OMAP4 /* FIXME: Remove this once clkdm f/w is in place */
                 if (clk->clkdm)
                         omap2_clkdm_clk_disable(clk->clkdm, clk);
+#endif
 
         }
 }
@@ -448,8 +489,10 @@ int omap2_clk_enable(struct clk *clk)
         int ret = 0;
 
         if (clk->usecount++ == 0) {
+#ifndef CONFIG_ARCH_OMAP4 /* FIXME: Remove this once clkdm f/w is in place */
                 if (clk->clkdm)
                         omap2_clkdm_clk_enable(clk->clkdm, clk);
+#endif
 
                 if (clk->parent) {
                         ret = omap2_clk_enable(clk->parent);
@@ -468,8 +511,10 @@ int omap2_clk_enable(struct clk *clk)
         return ret;
 
 err:
+#ifndef CONFIG_ARCH_OMAP4 /* FIXME: Remove this once clkdm f/w is in place */
         if (clk->clkdm)
                 omap2_clkdm_clk_disable(clk->clkdm, clk);
+#endif
         clk->usecount--;
         return ret;
 }
diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
index 43b6bedaafd6..93c48df3b5b1 100644
--- a/arch/arm/mach-omap2/clock.h
+++ b/arch/arm/mach-omap2/clock.h
@@ -1,8 +1,8 @@
 /*
  *  linux/arch/arm/mach-omap2/clock.h
  *
- *  Copyright (C) 2005-2008 Texas Instruments, Inc.
- *  Copyright (C) 2004-2008 Nokia Corporation
+ *  Copyright (C) 2005-2009 Texas Instruments, Inc.
+ *  Copyright (C) 2004-2009 Nokia Corporation
  *
  *  Contacts:
  *  Richard Woodruff <r-woodruff2@ti.com>
@@ -36,6 +36,17 @@
 #define OMAP3XXX_EN_DPLL_FRBYPASS               0x6
 #define OMAP3XXX_EN_DPLL_LOCKED                 0x7
 
+/* OMAP4xxx CM_CLKMODE_DPLL*.EN_*_DPLL bits - for omap2_get_dpll_rate() */
+#define OMAP4XXX_EN_DPLL_MNBYPASS               0x4
+#define OMAP4XXX_EN_DPLL_LPBYPASS               0x5
+#define OMAP4XXX_EN_DPLL_FRBYPASS               0x6
+#define OMAP4XXX_EN_DPLL_LOCKED                 0x7
+
+/* CM_CLKEN_PLL*.EN* bit values - not all are available for every DPLL */
+#define DPLL_LOW_POWER_STOP     0x1
+#define DPLL_LOW_POWER_BYPASS   0x5
+#define DPLL_LOCKED             0x7
+
 int omap2_clk_init(void);
 int omap2_clk_enable(struct clk *clk);
 void omap2_clk_disable(struct clk *clk);
@@ -44,6 +55,14 @@ int omap2_clk_set_rate(struct clk *clk, unsigned long rate);
 int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent);
 int omap2_dpll_set_rate_tolerance(struct clk *clk, unsigned int tolerance);
 long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate);
+unsigned long omap3_dpll_recalc(struct clk *clk);
+unsigned long omap3_clkoutx2_recalc(struct clk *clk);
+void omap3_dpll_allow_idle(struct clk *clk);
+void omap3_dpll_deny_idle(struct clk *clk);
+u32 omap3_dpll_autoidle_read(struct clk *clk);
+int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate);
+int omap3_noncore_dpll_enable(struct clk *clk);
+void omap3_noncore_dpll_disable(struct clk *clk);
 
 #ifdef CONFIG_OMAP_RESET_CLOCKS
 void omap2_clk_disable_unused(struct clk *clk);
@@ -63,6 +82,7 @@ unsigned long omap2_fixed_divisor_recalc(struct clk *clk);
 long omap2_clksel_round_rate(struct clk *clk, unsigned long target_rate);
 int omap2_clksel_set_rate(struct clk *clk, unsigned long rate);
 u32 omap2_get_dpll_rate(struct clk *clk);
+void omap2_init_dpll_parent(struct clk *clk);
 int omap2_wait_clock_ready(void __iomem *reg, u32 cval, const char *name);
 void omap2_clk_prepare_for_reboot(void);
 int omap2_dflt_clk_enable(struct clk *clk);
@@ -72,29 +92,17 @@ void omap2_clk_dflt_find_companion(struct clk *clk, void __iomem **other_reg,
 void omap2_clk_dflt_find_idlest(struct clk *clk, void __iomem **idlest_reg,
                                 u8 *idlest_bit);
 
+extern u8 cpu_mask;
+
 extern const struct clkops clkops_omap2_dflt_wait;
 extern const struct clkops clkops_omap2_dflt;
 
-extern u8 cpu_mask;
+extern struct clk_functions omap2_clk_functions;
+extern struct clk *vclk, *sclk;
 
-/* clksel_rate data common to 24xx/343x */
-static const struct clksel_rate gpt_32k_rates[] = {
-         { .div = 1, .val = 0, .flags = RATE_IN_24XX | RATE_IN_343X | DEFAULT_RATE },
-         { .div = 0 }
-};
-
-static const struct clksel_rate gpt_sys_rates[] = {
-         { .div = 1, .val = 1, .flags = RATE_IN_24XX | RATE_IN_343X | DEFAULT_RATE },
-         { .div = 0 }
-};
-
-static const struct clksel_rate gfx_l3_rates[] = {
-        { .div = 1, .val = 1, .flags = RATE_IN_24XX | RATE_IN_343X },
-        { .div = 2, .val = 2, .flags = RATE_IN_24XX | RATE_IN_343X | DEFAULT_RATE },
-        { .div = 3, .val = 3, .flags = RATE_IN_243X | RATE_IN_343X },
-        { .div = 4, .val = 4, .flags = RATE_IN_243X | RATE_IN_343X },
-        { .div = 0 }
-};
+extern const struct clksel_rate gpt_32k_rates[];
+extern const struct clksel_rate gpt_sys_rates[];
+extern const struct clksel_rate gfx_l3_rates[];
 
 
 #endif
diff --git a/arch/arm/mach-omap2/clock24xx.c b/arch/arm/mach-omap2/clock24xx.c
deleted file mode 100644
index 845b478ebeee..000000000000
--- a/arch/arm/mach-omap2/clock24xx.c
+++ /dev/null
@@ -1,805 +0,0 @@
-/*
- *  linux/arch/arm/mach-omap2/clock.c
- *
- *  Copyright (C) 2005-2008 Texas Instruments, Inc.
- *  Copyright (C) 2004-2008 Nokia Corporation
- *
- *  Contacts:
- *  Richard Woodruff <r-woodruff2@ti.com>
- *  Paul Walmsley
- *
- *  Based on earlier work by Tuukka Tikkanen, Tony Lindgren,
- *  Gordon McNutt and RidgeRun, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#undef DEBUG
-
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/device.h>
-#include <linux/list.h>
-#include <linux/errno.h>
-#include <linux/delay.h>
-#include <linux/clk.h>
-#include <linux/io.h>
-#include <linux/cpufreq.h>
-#include <linux/bitops.h>
-
-#include <plat/clock.h>
-#include <plat/sram.h>
-#include <plat/prcm.h>
-#include <asm/div64.h>
-#include <asm/clkdev.h>
-
-#include <plat/sdrc.h>
-#include "clock.h"
-#include "prm.h"
-#include "prm-regbits-24xx.h"
-#include "cm.h"
-#include "cm-regbits-24xx.h"
-
-static const struct clkops clkops_oscck;
-static const struct clkops clkops_fixed;
-
-static void omap2430_clk_i2chs_find_idlest(struct clk *clk,
-                                           void __iomem **idlest_reg,
-                                           u8 *idlest_bit);
-
-/* 2430 I2CHS has non-standard IDLEST register */
-static const struct clkops clkops_omap2430_i2chs_wait = {
-        .enable         = omap2_dflt_clk_enable,
-        .disable        = omap2_dflt_clk_disable,
-        .find_idlest    = omap2430_clk_i2chs_find_idlest,
-        .find_companion = omap2_clk_dflt_find_companion,
-};
-
-#include "clock24xx.h"
-
-struct omap_clk {
-        u32             cpu;
-        struct clk_lookup lk;
-};
-
-#define CLK(dev, con, ck, cp)           \
-        {                               \
-                 .cpu = cp,             \
-                .lk = {                 \
-                        .dev_id = dev,  \
-                        .con_id = con,  \
-                        .clk = ck,      \
-                },                      \
-        }
-
-#define CK_243X                 RATE_IN_243X
-#define CK_242X                 RATE_IN_242X
-
-static struct omap_clk omap24xx_clks[] = {
-        /* external root sources */
-        CLK(NULL,       "func_32k_ck",  &func_32k_ck,   CK_243X | CK_242X),
-        CLK(NULL,       "secure_32k_ck", &secure_32k_ck, CK_243X | CK_242X),
-        CLK(NULL,       "osc_ck",       &osc_ck,        CK_243X | CK_242X),
-        CLK(NULL,       "sys_ck",       &sys_ck,        CK_243X | CK_242X),
-        CLK(NULL,       "alt_ck",       &alt_ck,        CK_243X | CK_242X),
-        /* internal analog sources */
-        CLK(NULL,       "dpll_ck",      &dpll_ck,       CK_243X | CK_242X),
-        CLK(NULL,       "apll96_ck",    &apll96_ck,     CK_243X | CK_242X),
-        CLK(NULL,       "apll54_ck",    &apll54_ck,     CK_243X | CK_242X),
-        /* internal prcm root sources */
-        CLK(NULL,       "func_54m_ck",  &func_54m_ck,   CK_243X | CK_242X),
-        CLK(NULL,       "core_ck",      &core_ck,       CK_243X | CK_242X),
-        CLK(NULL,       "func_96m_ck",  &func_96m_ck,   CK_243X | CK_242X),
-        CLK(NULL,       "func_48m_ck",  &func_48m_ck,   CK_243X | CK_242X),
-        CLK(NULL,       "func_12m_ck",  &func_12m_ck,   CK_243X | CK_242X),
-        CLK(NULL,       "ck_wdt1_osc",  &wdt1_osc_ck,   CK_243X | CK_242X),
-        CLK(NULL,       "sys_clkout_src", &sys_clkout_src, CK_243X | CK_242X),
-        CLK(NULL,       "sys_clkout",   &sys_clkout,    CK_243X | CK_242X),
-        CLK(NULL,       "sys_clkout2_src", &sys_clkout2_src, CK_242X),
-        CLK(NULL,       "sys_clkout2",  &sys_clkout2,   CK_242X),
-        CLK(NULL,       "emul_ck",      &emul_ck,       CK_242X),
-        /* mpu domain clocks */
-        CLK(NULL,       "mpu_ck",       &mpu_ck,        CK_243X | CK_242X),
-        /* dsp domain clocks */
-        CLK(NULL,       "dsp_fck",      &dsp_fck,       CK_243X | CK_242X),
-        CLK(NULL,       "dsp_irate_ick", &dsp_irate_ick, CK_243X | CK_242X),
-        CLK(NULL,       "dsp_ick",      &dsp_ick,       CK_242X),
-        CLK(NULL,       "iva2_1_ick",   &iva2_1_ick,    CK_243X),
-        CLK(NULL,       "iva1_ifck",    &iva1_ifck,     CK_242X),
-        CLK(NULL,       "iva1_mpu_int_ifck", &iva1_mpu_int_ifck, CK_242X),
-        /* GFX domain clocks */
-        CLK(NULL,       "gfx_3d_fck",   &gfx_3d_fck,    CK_243X | CK_242X),
-        CLK(NULL,       "gfx_2d_fck",   &gfx_2d_fck,    CK_243X | CK_242X),
-        CLK(NULL,       "gfx_ick",      &gfx_ick,       CK_243X | CK_242X),
-        /* Modem domain clocks */
-        CLK(NULL,       "mdm_ick",      &mdm_ick,       CK_243X),
-        CLK(NULL,       "mdm_osc_ck",   &mdm_osc_ck,    CK_243X),
-        /* DSS domain clocks */
-        CLK("omapdss",  "ick",          &dss_ick,       CK_243X | CK_242X),
-        CLK("omapdss",  "dss1_fck",     &dss1_fck,      CK_243X | CK_242X),
-        CLK("omapdss",  "dss2_fck",     &dss2_fck,      CK_243X | CK_242X),
-        CLK("omapdss",  "tv_fck",       &dss_54m_fck,   CK_243X | CK_242X),
-        /* L3 domain clocks */
-        CLK(NULL,       "core_l3_ck",   &core_l3_ck,    CK_243X | CK_242X),
-        CLK(NULL,       "ssi_fck",      &ssi_ssr_sst_fck, CK_243X | CK_242X),
-        CLK(NULL,       "usb_l4_ick",   &usb_l4_ick,    CK_243X | CK_242X),
-        /* L4 domain clocks */
-        CLK(NULL,       "l4_ck",        &l4_ck,         CK_243X | CK_242X),
-        CLK(NULL,       "ssi_l4_ick",   &ssi_l4_ick,    CK_243X | CK_242X),
-        /* virtual meta-group clock */
-        CLK(NULL,       "virt_prcm_set", &virt_prcm_set, CK_243X | CK_242X),
-        /* general l4 interface ck, multi-parent functional clk */
-        CLK(NULL,       "gpt1_ick",     &gpt1_ick,      CK_243X | CK_242X),
-        CLK(NULL,       "gpt1_fck",     &gpt1_fck,      CK_243X | CK_242X),
-        CLK(NULL,       "gpt2_ick",     &gpt2_ick,      CK_243X | CK_242X),
-        CLK(NULL,       "gpt2_fck",     &gpt2_fck,      CK_243X | CK_242X),
-        CLK(NULL,       "gpt3_ick",     &gpt3_ick,      CK_243X | CK_242X),
-        CLK(NULL,       "gpt3_fck",     &gpt3_fck,      CK_243X | CK_242X),
-        CLK(NULL,       "gpt4_ick",     &gpt4_ick,      CK_243X | CK_242X),
-        CLK(NULL,       "gpt4_fck",     &gpt4_fck,      CK_243X | CK_242X),
-        CLK(NULL,       "gpt5_ick",     &gpt5_ick,      CK_243X | CK_242X),
-        CLK(NULL,       "gpt5_fck",     &gpt5_fck,      CK_243X | CK_242X),
-        CLK(NULL,       "gpt6_ick",     &gpt6_ick,      CK_243X | CK_242X),
-        CLK(NULL,       "gpt6_fck",     &gpt6_fck,      CK_243X | CK_242X),
-        CLK(NULL,       "gpt7_ick",     &gpt7_ick,      CK_243X | CK_242X),
-        CLK(NULL,       "gpt7_fck",     &gpt7_fck,      CK_243X | CK_242X),
-        CLK(NULL,       "gpt8_ick",     &gpt8_ick,      CK_243X | CK_242X),
-        CLK(NULL,       "gpt8_fck",     &gpt8_fck,      CK_243X | CK_242X),
-        CLK(NULL,       "gpt9_ick",     &gpt9_ick,      CK_243X | CK_242X),
-        CLK(NULL,       "gpt9_fck",     &gpt9_fck,      CK_243X | CK_242X),
-        CLK(NULL,       "gpt10_ick",    &gpt10_ick,     CK_243X | CK_242X),
-        CLK(NULL,       "gpt10_fck",    &gpt10_fck,     CK_243X | CK_242X),
-        CLK(NULL,       "gpt11_ick",    &gpt11_ick,     CK_243X | CK_242X),
-        CLK(NULL,       "gpt11_fck",    &gpt11_fck,     CK_243X | CK_242X),
-        CLK(NULL,       "gpt12_ick",    &gpt12_ick,     CK_243X | CK_242X),
-        CLK(NULL,       "gpt12_fck",    &gpt12_fck,     CK_243X | CK_242X),
-        CLK("omap-mcbsp.1", "ick",      &mcbsp1_ick,    CK_243X | CK_242X),
-        CLK("omap-mcbsp.1", "fck",      &mcbsp1_fck,    CK_243X | CK_242X),
-        CLK("omap-mcbsp.2", "ick",      &mcbsp2_ick,    CK_243X | CK_242X),
-        CLK("omap-mcbsp.2", "fck",      &mcbsp2_fck,    CK_243X | CK_242X),
-        CLK("omap-mcbsp.3", "ick",      &mcbsp3_ick,    CK_243X),
-        CLK("omap-mcbsp.3", "fck",      &mcbsp3_fck,    CK_243X),
-        CLK("omap-mcbsp.4", "ick",      &mcbsp4_ick,    CK_243X),
-        CLK("omap-mcbsp.4", "fck",      &mcbsp4_fck,    CK_243X),
-        CLK("omap-mcbsp.5", "ick",      &mcbsp5_ick,    CK_243X),
-        CLK("omap-mcbsp.5", "fck",      &mcbsp5_fck,    CK_243X),
-        CLK("omap2_mcspi.1", "ick",     &mcspi1_ick,    CK_243X | CK_242X),
-        CLK("omap2_mcspi.1", "fck",     &mcspi1_fck,    CK_243X | CK_242X),
-        CLK("omap2_mcspi.2", "ick",     &mcspi2_ick,    CK_243X | CK_242X),
-        CLK("omap2_mcspi.2", "fck",     &mcspi2_fck,    CK_243X | CK_242X),
-        CLK("omap2_mcspi.3", "ick",     &mcspi3_ick,    CK_243X),
-        CLK("omap2_mcspi.3", "fck",     &mcspi3_fck,    CK_243X),
-        CLK(NULL,       "uart1_ick",    &uart1_ick,     CK_243X | CK_242X),
-        CLK(NULL,       "uart1_fck",    &uart1_fck,     CK_243X | CK_242X),
-        CLK(NULL,       "uart2_ick",    &uart2_ick,     CK_243X | CK_242X),
-        CLK(NULL,       "uart2_fck",    &uart2_fck,     CK_243X | CK_242X),
-        CLK(NULL,       "uart3_ick",    &uart3_ick,     CK_243X | CK_242X),
-        CLK(NULL,       "uart3_fck",    &uart3_fck,     CK_243X | CK_242X),
-        CLK(NULL,       "gpios_ick",    &gpios_ick,     CK_243X | CK_242X),
-        CLK(NULL,       "gpios_fck",    &gpios_fck,     CK_243X | CK_242X),
-        CLK("omap_wdt", "ick",          &mpu_wdt_ick,   CK_243X | CK_242X),
-        CLK("omap_wdt", "fck",          &mpu_wdt_fck,   CK_243X | CK_242X),
-        CLK(NULL,       "sync_32k_ick", &sync_32k_ick,  CK_243X | CK_242X),
-        CLK(NULL,       "wdt1_ick",     &wdt1_ick,      CK_243X | CK_242X),
-        CLK(NULL,       "omapctrl_ick", &omapctrl_ick,  CK_243X | CK_242X),
-        CLK(NULL,       "icr_ick",      &icr_ick,       CK_243X),
-        CLK("omap24xxcam", "fck",       &cam_fck,       CK_243X | CK_242X),
-        CLK("omap24xxcam", "ick",       &cam_ick,       CK_243X | CK_242X),
-        CLK(NULL,       "mailboxes_ick", &mailboxes_ick,        CK_243X | CK_242X),
-        CLK(NULL,       "wdt4_ick",     &wdt4_ick,      CK_243X | CK_242X),
-        CLK(NULL,       "wdt4_fck",     &wdt4_fck,      CK_243X | CK_242X),
-        CLK(NULL,       "wdt3_ick",     &wdt3_ick,      CK_242X),
-        CLK(NULL,       "wdt3_fck",     &wdt3_fck,      CK_242X),
-        CLK(NULL,       "mspro_ick",    &mspro_ick,     CK_243X | CK_242X),
-        CLK(NULL,       "mspro_fck",    &mspro_fck,     CK_243X | CK_242X),
-        CLK("mmci-omap.0", "ick",       &mmc_ick,       CK_242X),
-        CLK("mmci-omap.0", "fck",       &mmc_fck,       CK_242X),
-        CLK(NULL,       "fac_ick",      &fac_ick,       CK_243X | CK_242X),
-        CLK(NULL,       "fac_fck",      &fac_fck,       CK_243X | CK_242X),
-        CLK(NULL,       "eac_ick",      &eac_ick,       CK_242X),
-        CLK(NULL,       "eac_fck",      &eac_fck,       CK_242X),
-        CLK("omap_hdq.0", "ick",        &hdq_ick,       CK_243X | CK_242X),
-        CLK("omap_hdq.1", "fck",        &hdq_fck,       CK_243X | CK_242X),
-        CLK("i2c_omap.1", "ick",        &i2c1_ick,      CK_243X | CK_242X),
-        CLK("i2c_omap.1", "fck",        &i2c1_fck,      CK_242X),
-        CLK("i2c_omap.1", "fck",        &i2chs1_fck,    CK_243X),
-        CLK("i2c_omap.2", "ick",        &i2c2_ick,      CK_243X | CK_242X),
-        CLK("i2c_omap.2", "fck",        &i2c2_fck,      CK_242X),
-        CLK("i2c_omap.2", "fck",        &i2chs2_fck,    CK_243X),
-        CLK(NULL,       "gpmc_fck",     &gpmc_fck,      CK_243X | CK_242X),
-        CLK(NULL,       "sdma_fck",     &sdma_fck,      CK_243X | CK_242X),
-        CLK(NULL,       "sdma_ick",     &sdma_ick,      CK_243X | CK_242X),
-        CLK(NULL,       "vlynq_ick",    &vlynq_ick,     CK_242X),
-        CLK(NULL,       "vlynq_fck",    &vlynq_fck,     CK_242X),
-        CLK(NULL,       "sdrc_ick",     &sdrc_ick,      CK_243X),
-        CLK(NULL,       "des_ick",      &des_ick,       CK_243X | CK_242X),
-        CLK(NULL,       "sha_ick",      &sha_ick,       CK_243X | CK_242X),
-        CLK("omap_rng", "ick",          &rng_ick,       CK_243X | CK_242X),
-        CLK(NULL,       "aes_ick",      &aes_ick,       CK_243X | CK_242X),
-        CLK(NULL,       "pka_ick",      &pka_ick,       CK_243X | CK_242X),
-        CLK(NULL,       "usb_fck",      &usb_fck,       CK_243X | CK_242X),
-        CLK("musb_hdrc",        "ick",  &usbhs_ick,     CK_243X),
-        CLK("mmci-omap-hs.0", "ick",    &mmchs1_ick,    CK_243X),
-        CLK("mmci-omap-hs.0", "fck",    &mmchs1_fck,    CK_243X),
-        CLK("mmci-omap-hs.1", "ick",    &mmchs2_ick,    CK_243X),
-        CLK("mmci-omap-hs.1", "fck",    &mmchs2_fck,    CK_243X),
-        CLK(NULL,       "gpio5_ick",    &gpio5_ick,     CK_243X),
-        CLK(NULL,       "gpio5_fck",    &gpio5_fck,     CK_243X),
-        CLK(NULL,       "mdm_intc_ick", &mdm_intc_ick,  CK_243X),
-        CLK("mmci-omap-hs.0", "mmchsdb_fck",    &mmchsdb1_fck,  CK_243X),
-        CLK("mmci-omap-hs.1", "mmchsdb_fck",    &mmchsdb2_fck,  CK_243X),
-};
-
-/* CM_CLKEN_PLL.EN_{54,96}M_PLL options (24XX) */
-#define EN_APLL_STOPPED                 0
-#define EN_APLL_LOCKED                  3
-
-/* CM_CLKSEL1_PLL.APLLS_CLKIN options (24XX) */
-#define APLLS_CLKIN_19_2MHZ             0
-#define APLLS_CLKIN_13MHZ               2
-#define APLLS_CLKIN_12MHZ               3
-
-/* #define DOWN_VARIABLE_DPLL 1 */              /* Experimental */
-
-static struct prcm_config *curr_prcm_set;
-static struct clk *vclk;
-static struct clk *sclk;
-
-static void __iomem *prcm_clksrc_ctrl;
-
-/*-------------------------------------------------------------------------
- * Omap24xx specific clock functions
- *-------------------------------------------------------------------------*/
-
-/**
- * omap2430_clk_i2chs_find_idlest - return CM_IDLEST info for 2430 I2CHS
- * @clk: struct clk * being enabled
- * @idlest_reg: void __iomem ** to store CM_IDLEST reg address into
- * @idlest_bit: pointer to a u8 to store the CM_IDLEST bit shift into
- *
- * OMAP2430 I2CHS CM_IDLEST bits are in CM_IDLEST1_CORE, but the
- * CM_*CLKEN bits are in CM_{I,F}CLKEN2_CORE.  This custom function
- * passes back the correct CM_IDLEST register address for I2CHS
- * modules.  No return value.
- */
-static void omap2430_clk_i2chs_find_idlest(struct clk *clk,
-                                           void __iomem **idlest_reg,
-                                           u8 *idlest_bit)
-{
-        *idlest_reg = OMAP_CM_REGADDR(CORE_MOD, CM_IDLEST);
-        *idlest_bit = clk->enable_bit;
-}
-
-
-/**
- * omap2xxx_clk_get_core_rate - return the CORE_CLK rate
- * @clk: pointer to the combined dpll_ck + core_ck (currently "dpll_ck")
- *
- * Returns the CORE_CLK rate.  CORE_CLK can have one of three rate
- * sources on OMAP2xxx: the DPLL CLKOUT rate, DPLL CLKOUTX2, or 32KHz
- * (the latter is unusual).  This currently should be called with
- * struct clk *dpll_ck, which is a composite clock of dpll_ck and
- * core_ck.
- */
-static unsigned long omap2xxx_clk_get_core_rate(struct clk *clk)
-{
-        long long core_clk;
-        u32 v;
-
-        core_clk = omap2_get_dpll_rate(clk);
-
-        v = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
-        v &= OMAP24XX_CORE_CLK_SRC_MASK;
-
-        if (v == CORE_CLK_SRC_32K)
-                core_clk = 32768;
-        else
-                core_clk *= v;
-
-        return core_clk;
-}
-
-static int omap2_enable_osc_ck(struct clk *clk)
-{
-        u32 pcc;
-
-        pcc = __raw_readl(prcm_clksrc_ctrl);
-
-        __raw_writel(pcc & ~OMAP_AUTOEXTCLKMODE_MASK, prcm_clksrc_ctrl);
-
-        return 0;
-}
-
-static void omap2_disable_osc_ck(struct clk *clk)
-{
-        u32 pcc;
-
-        pcc = __raw_readl(prcm_clksrc_ctrl);
-
-        __raw_writel(pcc | OMAP_AUTOEXTCLKMODE_MASK, prcm_clksrc_ctrl);
-}
-
-static const struct clkops clkops_oscck = {
-        .enable         = &omap2_enable_osc_ck,
-        .disable        = &omap2_disable_osc_ck,
-};
-
-#ifdef OLD_CK
-/* Recalculate SYST_CLK */
-static void omap2_sys_clk_recalc(struct clk * clk)
-{
-        u32 div = PRCM_CLKSRC_CTRL;
-        div &= (1 << 7) | (1 << 6);     /* Test if ext clk divided by 1 or 2 */
-        div >>= clk->rate_offset;
-        clk->rate = (clk->parent->rate / div);
-        propagate_rate(clk);
-}
-#endif  /* OLD_CK */
-
-/* Enable an APLL if off */
-static int omap2_clk_fixed_enable(struct clk *clk)
-{
-        u32 cval, apll_mask;
-
-        apll_mask = EN_APLL_LOCKED << clk->enable_bit;
-
-        cval = cm_read_mod_reg(PLL_MOD, CM_CLKEN);
-
-        if ((cval & apll_mask) == apll_mask)
-                return 0;   /* apll already enabled */
-
-        cval &= ~apll_mask;
-        cval |= apll_mask;
-        cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN);
-
-        if (clk == &apll96_ck)
-                cval = OMAP24XX_ST_96M_APLL;
-        else if (clk == &apll54_ck)
-                cval = OMAP24XX_ST_54M_APLL;
-
-        omap2_cm_wait_idlest(OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), cval,
-                             clk->name);
-
-        /*
-         * REVISIT: Should we return an error code if omap2_wait_clock_ready()
-         * fails?
-         */
-        return 0;
-}
-
-/* Stop APLL */
-static void omap2_clk_fixed_disable(struct clk *clk)
-{
-        u32 cval;
-
-        cval = cm_read_mod_reg(PLL_MOD, CM_CLKEN);
-        cval &= ~(EN_APLL_LOCKED << clk->enable_bit);
-        cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN);
-}
-
-static const struct clkops clkops_fixed = {
-        .enable         = &omap2_clk_fixed_enable,
-        .disable        = &omap2_clk_fixed_disable,
-};
-
-/*
- * Uses the current prcm set to tell if a rate is valid.
- * You can go slower, but not faster within a given rate set.
- */
-static long omap2_dpllcore_round_rate(unsigned long target_rate)
-{
-        u32 high, low, core_clk_src;
-
-        core_clk_src = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
-        core_clk_src &= OMAP24XX_CORE_CLK_SRC_MASK;
-
-        if (core_clk_src == CORE_CLK_SRC_DPLL) {        /* DPLL clockout */
-                high = curr_prcm_set->dpll_speed * 2;
-                low = curr_prcm_set->dpll_speed;
-        } else {                                /* DPLL clockout x 2 */
-                high = curr_prcm_set->dpll_speed;
-                low = curr_prcm_set->dpll_speed / 2;
-        }
-
-#ifdef DOWN_VARIABLE_DPLL
-        if (target_rate > high)
-                return high;
-        else
-                return target_rate;
-#else
-        if (target_rate > low)
-                return high;
-        else
-                return low;
-#endif
-
-}
-
-static unsigned long omap2_dpllcore_recalc(struct clk *clk)
-{
-        return omap2xxx_clk_get_core_rate(clk);
-}
-
-static int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate)
-{
-        u32 cur_rate, low, mult, div, valid_rate, done_rate;
-        u32 bypass = 0;
-        struct prcm_config tmpset;
-        const struct dpll_data *dd;
-
-        cur_rate = omap2xxx_clk_get_core_rate(&dpll_ck);
-        mult = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
-        mult &= OMAP24XX_CORE_CLK_SRC_MASK;
-
-        if ((rate == (cur_rate / 2)) && (mult == 2)) {
-                omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL, 1);
-        } else if ((rate == (cur_rate * 2)) && (mult == 1)) {
-                omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL_X2, 1);
-        } else if (rate != cur_rate) {
-                valid_rate = omap2_dpllcore_round_rate(rate);
-                if (valid_rate != rate)
-                        return -EINVAL;
-
-                if (mult == 1)
-                        low = curr_prcm_set->dpll_speed;
-                else
-                        low = curr_prcm_set->dpll_speed / 2;
-
-                dd = clk->dpll_data;
-                if (!dd)
-                        return -EINVAL;
-
-                tmpset.cm_clksel1_pll = __raw_readl(dd->mult_div1_reg);
-                tmpset.cm_clksel1_pll &= ~(dd->mult_mask |
-                                           dd->div1_mask);
-                div = ((curr_prcm_set->xtal_speed / 1000000) - 1);
-                tmpset.cm_clksel2_pll = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
-                tmpset.cm_clksel2_pll &= ~OMAP24XX_CORE_CLK_SRC_MASK;
-                if (rate > low) {
-                        tmpset.cm_clksel2_pll |= CORE_CLK_SRC_DPLL_X2;
-                        mult = ((rate / 2) / 1000000);
-                        done_rate = CORE_CLK_SRC_DPLL_X2;
-                } else {
-                        tmpset.cm_clksel2_pll |= CORE_CLK_SRC_DPLL;
-                        mult = (rate / 1000000);
-                        done_rate = CORE_CLK_SRC_DPLL;
-                }
-                tmpset.cm_clksel1_pll |= (div << __ffs(dd->mult_mask));
-                tmpset.cm_clksel1_pll |= (mult << __ffs(dd->div1_mask));
-
-                /* Worst case */
-                tmpset.base_sdrc_rfr = SDRC_RFR_CTRL_BYPASS;
-
-                if (rate == curr_prcm_set->xtal_speed)  /* If asking for 1-1 */
-                        bypass = 1;
-
-                /* For omap2xxx_sdrc_init_params() */
-                omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL_X2, 1);
-
-                /* Force dll lock mode */
-                omap2_set_prcm(tmpset.cm_clksel1_pll, tmpset.base_sdrc_rfr,
-                               bypass);
-
-                /* Errata: ret dll entry state */
-                omap2xxx_sdrc_init_params(omap2xxx_sdrc_dll_is_unlocked());
-                omap2xxx_sdrc_reprogram(done_rate, 0);
-        }
-
-        return 0;
-}
-
-/**
- * omap2_table_mpu_recalc - just return the MPU speed
- * @clk: virt_prcm_set struct clk
- *
- * Set virt_prcm_set's rate to the mpu_speed field of the current PRCM set.
- */
-static unsigned long omap2_table_mpu_recalc(struct clk *clk)
-{
-        return curr_prcm_set->mpu_speed;
-}
-
-/*
- * Look for a rate equal or less than the target rate given a configuration set.
- *
- * What's not entirely clear is "which" field represents the key field.
- * Some might argue L3-DDR, others ARM, others IVA. This code is simple and
- * just uses the ARM rates.
- */
-static long omap2_round_to_table_rate(struct clk *clk, unsigned long rate)
-{
-        struct prcm_config *ptr;
-        long highest_rate;
-
-        if (clk != &virt_prcm_set)
-                return -EINVAL;
-
-        highest_rate = -EINVAL;
-
-        for (ptr = rate_table; ptr->mpu_speed; ptr++) {
-                if (!(ptr->flags & cpu_mask))
-                        continue;
-                if (ptr->xtal_speed != sys_ck.rate)
-                        continue;
-
-                highest_rate = ptr->mpu_speed;
-
-                /* Can check only after xtal frequency check */
-                if (ptr->mpu_speed <= rate)
-                        break;
-        }
-        return highest_rate;
-}
-
-/* Sets basic clocks based on the specified rate */
-static int omap2_select_table_rate(struct clk *clk, unsigned long rate)
-{
-        u32 cur_rate, done_rate, bypass = 0, tmp;
-        struct prcm_config *prcm;
-        unsigned long found_speed = 0;
-        unsigned long flags;
-
-        if (clk != &virt_prcm_set)
-                return -EINVAL;
-
-        for (prcm = rate_table; prcm->mpu_speed; prcm++) {
-                if (!(prcm->flags & cpu_mask))
-                        continue;
-
-                if (prcm->xtal_speed != sys_ck.rate)
-                        continue;
-
-                if (prcm->mpu_speed <= rate) {
-                        found_speed = prcm->mpu_speed;
-                        break;
-                }
-        }
-
-        if (!found_speed) {
-                printk(KERN_INFO "Could not set MPU rate to %luMHz\n",
-                       rate / 1000000);
-                return -EINVAL;
-        }
-
-        curr_prcm_set = prcm;
-        cur_rate = omap2xxx_clk_get_core_rate(&dpll_ck);
-
-        if (prcm->dpll_speed == cur_rate / 2) {
-                omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL, 1);
-        } else if (prcm->dpll_speed == cur_rate * 2) {
-                omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL_X2, 1);
-        } else if (prcm->dpll_speed != cur_rate) {
-                local_irq_save(flags);
-
-                if (prcm->dpll_speed == prcm->xtal_speed)
-                        bypass = 1;
-
-                if ((prcm->cm_clksel2_pll & OMAP24XX_CORE_CLK_SRC_MASK) ==
-                    CORE_CLK_SRC_DPLL_X2)
-                        done_rate = CORE_CLK_SRC_DPLL_X2;
-                else
-                        done_rate = CORE_CLK_SRC_DPLL;
-
-                /* MPU divider */
-                cm_write_mod_reg(prcm->cm_clksel_mpu, MPU_MOD, CM_CLKSEL);
-
-                /* dsp + iva1 div(2420), iva2.1(2430) */
-                cm_write_mod_reg(prcm->cm_clksel_dsp,
-                                 OMAP24XX_DSP_MOD, CM_CLKSEL);
-
-                cm_write_mod_reg(prcm->cm_clksel_gfx, GFX_MOD, CM_CLKSEL);
-
-                /* Major subsystem dividers */
-                tmp = cm_read_mod_reg(CORE_MOD, CM_CLKSEL1) & OMAP24XX_CLKSEL_DSS2_MASK;
-                cm_write_mod_reg(prcm->cm_clksel1_core | tmp, CORE_MOD,
-                                 CM_CLKSEL1);
-
-                if (cpu_is_omap2430())
-                        cm_write_mod_reg(prcm->cm_clksel_mdm,
-                                         OMAP2430_MDM_MOD, CM_CLKSEL);
-
-                /* x2 to enter omap2xxx_sdrc_init_params() */
-                omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL_X2, 1);
-
-                omap2_set_prcm(prcm->cm_clksel1_pll, prcm->base_sdrc_rfr,
-                               bypass);
-
-                omap2xxx_sdrc_init_params(omap2xxx_sdrc_dll_is_unlocked());
-                omap2xxx_sdrc_reprogram(done_rate, 0);
-
-                local_irq_restore(flags);
-        }
-
-        return 0;
-}
-
-#ifdef CONFIG_CPU_FREQ
-/*
- * Walk PRCM rate table and fillout cpufreq freq_table
- */
-static struct cpufreq_frequency_table freq_table[ARRAY_SIZE(rate_table)];
-
-void omap2_clk_init_cpufreq_table(struct cpufreq_frequency_table **table)
-{
-        struct prcm_config *prcm;
-        int i = 0;
-
-        for (prcm = rate_table; prcm->mpu_speed; prcm++) {
-                if (!(prcm->flags & cpu_mask))
-                        continue;
-                if (prcm->xtal_speed != sys_ck.rate)
-                        continue;
-
-                /* don't put bypass rates in table */
-                if (prcm->dpll_speed == prcm->xtal_speed)
-                        continue;
-
-                freq_table[i].index = i;
-                freq_table[i].frequency = prcm->mpu_speed / 1000;
-                i++;
-        }
-
-        if (i == 0) {
-                printk(KERN_WARNING "%s: failed to initialize frequency "
-                       "table\n", __func__);
-                return;
-        }
-
-        freq_table[i].index = i;
-        freq_table[i].frequency = CPUFREQ_TABLE_END;
-
-        *table = &freq_table[0];
-}
-#endif
-
-static struct clk_functions omap2_clk_functions = {
-        .clk_enable             = omap2_clk_enable,
-        .clk_disable            = omap2_clk_disable,
-        .clk_round_rate         = omap2_clk_round_rate,
-        .clk_set_rate           = omap2_clk_set_rate,
-        .clk_set_parent         = omap2_clk_set_parent,
-        .clk_disable_unused     = omap2_clk_disable_unused,
-#ifdef  CONFIG_CPU_FREQ
-        .clk_init_cpufreq_table = omap2_clk_init_cpufreq_table,
-#endif
-};
-
-static u32 omap2_get_apll_clkin(void)
-{
-        u32 aplls, srate = 0;
-
-        aplls = cm_read_mod_reg(PLL_MOD, CM_CLKSEL1);
-        aplls &= OMAP24XX_APLLS_CLKIN_MASK;
-        aplls >>= OMAP24XX_APLLS_CLKIN_SHIFT;
-
-        if (aplls == APLLS_CLKIN_19_2MHZ)
-                srate = 19200000;
-        else if (aplls == APLLS_CLKIN_13MHZ)
-                srate = 13000000;
-        else if (aplls == APLLS_CLKIN_12MHZ)
-                srate = 12000000;
-
-        return srate;
-}
-
-static u32 omap2_get_sysclkdiv(void)
-{
-        u32 div;
-
-        div = __raw_readl(prcm_clksrc_ctrl);
-        div &= OMAP_SYSCLKDIV_MASK;
-        div >>= OMAP_SYSCLKDIV_SHIFT;
-
-        return div;
-}
-
-static unsigned long omap2_osc_clk_recalc(struct clk *clk)
-{
-        return omap2_get_apll_clkin() * omap2_get_sysclkdiv();
-}
-
-static unsigned long omap2_sys_clk_recalc(struct clk *clk)
-{
-        return clk->parent->rate / omap2_get_sysclkdiv();
-}
-
-/*
- * Set clocks for bypass mode for reboot to work.
- */
-void omap2_clk_prepare_for_reboot(void)
-{
-        u32 rate;
-
-        if (vclk == NULL || sclk == NULL)
-                return;
-
-        rate = clk_get_rate(sclk);
-        clk_set_rate(vclk, rate);
-}
-
-/*
- * Switch the MPU rate if specified on cmdline.
- * We cannot do this early until cmdline is parsed.
- */
-static int __init omap2_clk_arch_init(void)
-{
-        if (!mpurate)
-                return -EINVAL;
-
-        if (clk_set_rate(&virt_prcm_set, mpurate))
-                printk(KERN_ERR "Could not find matching MPU rate\n");
-
-        recalculate_root_clocks();
-
-        printk(KERN_INFO "Switched to new clocking rate (Crystal/DPLL/MPU): "
-               "%ld.%01ld/%ld/%ld MHz\n",
-               (sys_ck.rate / 1000000), (sys_ck.rate / 100000) % 10,
-               (dpll_ck.rate / 1000000), (mpu_ck.rate / 1000000)) ;
-
-        return 0;
-}
-arch_initcall(omap2_clk_arch_init);
-
-int __init omap2_clk_init(void)
-{
-        struct prcm_config *prcm;
-        struct omap_clk *c;
-        u32 clkrate;
-
-        if (cpu_is_omap242x()) {
-                prcm_clksrc_ctrl = OMAP2420_PRCM_CLKSRC_CTRL;
-                cpu_mask = RATE_IN_242X;
-        } else if (cpu_is_omap2430()) {
-                prcm_clksrc_ctrl = OMAP2430_PRCM_CLKSRC_CTRL;
-                cpu_mask = RATE_IN_243X;
-        }
-
-        clk_init(&omap2_clk_functions);
-
-        for (c = omap24xx_clks; c < omap24xx_clks + ARRAY_SIZE(omap24xx_clks); c++)
-                clk_preinit(c->lk.clk);
-
-        osc_ck.rate = omap2_osc_clk_recalc(&osc_ck);
-        propagate_rate(&osc_ck);
-        sys_ck.rate = omap2_sys_clk_recalc(&sys_ck);
-        propagate_rate(&sys_ck);
-
-        for (c = omap24xx_clks; c < omap24xx_clks + ARRAY_SIZE(omap24xx_clks); c++)
-                if (c->cpu & cpu_mask) {
-                        clkdev_add(&c->lk);
-                        clk_register(c->lk.clk);
-                        omap2_init_clk_clkdm(c->lk.clk);
-                }
-
-        /* Check the MPU rate set by bootloader */
-        clkrate = omap2xxx_clk_get_core_rate(&dpll_ck);
-        for (prcm = rate_table; prcm->mpu_speed; prcm++) {
-                if (!(prcm->flags & cpu_mask))
-                        continue;
-                if (prcm->xtal_speed != sys_ck.rate)
-                        continue;
-                if (prcm->dpll_speed <= clkrate)
-                         break;
-        }
-        curr_prcm_set = prcm;
-
-        recalculate_root_clocks();
-
-        printk(KERN_INFO "Clocking rate (Crystal/DPLL/MPU): "
-               "%ld.%01ld/%ld/%ld MHz\n",
-               (sys_ck.rate / 1000000), (sys_ck.rate / 100000) % 10,
-               (dpll_ck.rate / 1000000), (mpu_ck.rate / 1000000)) ;
-
-        /*
-         * Only enable those clocks we will need, let the drivers
-         * enable other clocks as necessary
-         */
-        clk_enable_init_clocks();
-
-        /* Avoid sleeping sleeping during omap2_clk_prepare_for_reboot() */
-        vclk = clk_get(NULL, "virt_prcm_set");
-        sclk = clk_get(NULL, "sys_ck");
-
-        return 0;
-}
diff --git a/arch/arm/mach-omap2/clock2xxx.c b/arch/arm/mach-omap2/clock2xxx.c
new file mode 100644
index 000000000000..d0e3fb7f9298
--- /dev/null
+++ b/arch/arm/mach-omap2/clock2xxx.c
@@ -0,0 +1,587 @@
+/*
+ *  linux/arch/arm/mach-omap2/clock.c
+ *
+ *  Copyright (C) 2005-2008 Texas Instruments, Inc.
+ *  Copyright (C) 2004-2008 Nokia Corporation
+ *
+ *  Contacts:
+ *  Richard Woodruff <r-woodruff2@ti.com>
+ *  Paul Walmsley
+ *
+ *  Based on earlier work by Tuukka Tikkanen, Tony Lindgren,
+ *  Gordon McNutt and RidgeRun, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#undef DEBUG
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/device.h>
+#include <linux/list.h>
+#include <linux/errno.h>
+#include <linux/delay.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/cpufreq.h>
+#include <linux/bitops.h>
+
+#include <plat/clock.h>
+#include <plat/sram.h>
+#include <plat/prcm.h>
+#include <plat/clkdev_omap.h>
+#include <asm/div64.h>
+#include <asm/clkdev.h>
+
+#include <plat/sdrc.h>
+#include "clock.h"
+#include "clock2xxx.h"
+#include "opp2xxx.h"
+#include "prm.h"
+#include "prm-regbits-24xx.h"
+#include "cm.h"
+#include "cm-regbits-24xx.h"
+
+
+/* CM_CLKEN_PLL.EN_{54,96}M_PLL options (24XX) */
+#define EN_APLL_STOPPED                 0
+#define EN_APLL_LOCKED                  3
+
+/* CM_CLKSEL1_PLL.APLLS_CLKIN options (24XX) */
+#define APLLS_CLKIN_19_2MHZ             0
+#define APLLS_CLKIN_13MHZ               2
+#define APLLS_CLKIN_12MHZ               3
+
+/* #define DOWN_VARIABLE_DPLL 1 */              /* Experimental */
+
+const struct prcm_config *curr_prcm_set;
+const struct prcm_config *rate_table;
+
+struct clk *vclk, *sclk, *dclk;
+
+void __iomem *prcm_clksrc_ctrl;
+
+/*-------------------------------------------------------------------------
+ * Omap24xx specific clock functions
+ *-------------------------------------------------------------------------*/
+
+/**
+ * omap2430_clk_i2chs_find_idlest - return CM_IDLEST info for 2430 I2CHS
+ * @clk: struct clk * being enabled
+ * @idlest_reg: void __iomem ** to store CM_IDLEST reg address into
+ * @idlest_bit: pointer to a u8 to store the CM_IDLEST bit shift into
+ *
+ * OMAP2430 I2CHS CM_IDLEST bits are in CM_IDLEST1_CORE, but the
+ * CM_*CLKEN bits are in CM_{I,F}CLKEN2_CORE.  This custom function
+ * passes back the correct CM_IDLEST register address for I2CHS
+ * modules.  No return value.
+ */
+static void omap2430_clk_i2chs_find_idlest(struct clk *clk,
+                                           void __iomem **idlest_reg,
+                                           u8 *idlest_bit)
+{
+        *idlest_reg = OMAP_CM_REGADDR(CORE_MOD, CM_IDLEST);
+        *idlest_bit = clk->enable_bit;
+}
+
+/* 2430 I2CHS has non-standard IDLEST register */
+const struct clkops clkops_omap2430_i2chs_wait = {
+        .enable         = omap2_dflt_clk_enable,
+        .disable        = omap2_dflt_clk_disable,
+        .find_idlest    = omap2430_clk_i2chs_find_idlest,
+        .find_companion = omap2_clk_dflt_find_companion,
+};
+
+/**
+ * omap2xxx_clk_get_core_rate - return the CORE_CLK rate
+ * @clk: pointer to the combined dpll_ck + core_ck (currently "dpll_ck")
+ *
+ * Returns the CORE_CLK rate.  CORE_CLK can have one of three rate
+ * sources on OMAP2xxx: the DPLL CLKOUT rate, DPLL CLKOUTX2, or 32KHz
+ * (the latter is unusual).  This currently should be called with
+ * struct clk *dpll_ck, which is a composite clock of dpll_ck and
+ * core_ck.
+ */
+unsigned long omap2xxx_clk_get_core_rate(struct clk *clk)
+{
+        long long core_clk;
+        u32 v;
+
+        core_clk = omap2_get_dpll_rate(clk);
+
+        v = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
+        v &= OMAP24XX_CORE_CLK_SRC_MASK;
+
+        if (v == CORE_CLK_SRC_32K)
+                core_clk = 32768;
+        else
+                core_clk *= v;
+
+        return core_clk;
+}
+
+static int omap2_enable_osc_ck(struct clk *clk)
+{
+        u32 pcc;
+
+        pcc = __raw_readl(prcm_clksrc_ctrl);
+
+        __raw_writel(pcc & ~OMAP_AUTOEXTCLKMODE_MASK, prcm_clksrc_ctrl);
+
+        return 0;
+}
+
+static void omap2_disable_osc_ck(struct clk *clk)
+{
+        u32 pcc;
+
+        pcc = __raw_readl(prcm_clksrc_ctrl);
+
+        __raw_writel(pcc | OMAP_AUTOEXTCLKMODE_MASK, prcm_clksrc_ctrl);
+}
+
+const struct clkops clkops_oscck = {
+        .enable         = omap2_enable_osc_ck,
+        .disable        = omap2_disable_osc_ck,
+};
+
+#ifdef OLD_CK
+/* Recalculate SYST_CLK */
+static void omap2_sys_clk_recalc(struct clk *clk)
+{
+        u32 div = PRCM_CLKSRC_CTRL;
+        div &= (1 << 7) | (1 << 6);     /* Test if ext clk divided by 1 or 2 */
+        div >>= clk->rate_offset;
+        clk->rate = (clk->parent->rate / div);
+        propagate_rate(clk);
+}
+#endif  /* OLD_CK */
+
+/* Enable an APLL if off */
+static int omap2_clk_apll_enable(struct clk *clk, u32 status_mask)
+{
+        u32 cval, apll_mask;
+
+        apll_mask = EN_APLL_LOCKED << clk->enable_bit;
+
+        cval = cm_read_mod_reg(PLL_MOD, CM_CLKEN);
+
+        if ((cval & apll_mask) == apll_mask)
+                return 0;   /* apll already enabled */
+
+        cval &= ~apll_mask;
+        cval |= apll_mask;
+        cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN);
+
+        omap2_cm_wait_idlest(OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), status_mask,
+                             clk->name);
+
+        /*
+         * REVISIT: Should we return an error code if omap2_wait_clock_ready()
+         * fails?
+         */
+        return 0;
+}
+
+static int omap2_clk_apll96_enable(struct clk *clk)
+{
+        return omap2_clk_apll_enable(clk, OMAP24XX_ST_96M_APLL);
+}
+
+static int omap2_clk_apll54_enable(struct clk *clk)
+{
+        return omap2_clk_apll_enable(clk, OMAP24XX_ST_54M_APLL);
+}
+
+/* Stop APLL */
+static void omap2_clk_apll_disable(struct clk *clk)
+{
+        u32 cval;
+
+        cval = cm_read_mod_reg(PLL_MOD, CM_CLKEN);
+        cval &= ~(EN_APLL_LOCKED << clk->enable_bit);
+        cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN);
+}
+
+const struct clkops clkops_apll96 = {
+        .enable         = omap2_clk_apll96_enable,
+        .disable        = omap2_clk_apll_disable,
+};
+
+const struct clkops clkops_apll54 = {
+        .enable         = omap2_clk_apll54_enable,
+        .disable        = omap2_clk_apll_disable,
+};
+
+/*
+ * Uses the current prcm set to tell if a rate is valid.
+ * You can go slower, but not faster within a given rate set.
+ */
+long omap2_dpllcore_round_rate(unsigned long target_rate)
+{
+        u32 high, low, core_clk_src;
+
+        core_clk_src = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
+        core_clk_src &= OMAP24XX_CORE_CLK_SRC_MASK;
+
+        if (core_clk_src == CORE_CLK_SRC_DPLL) {        /* DPLL clockout */
+                high = curr_prcm_set->dpll_speed * 2;
+                low = curr_prcm_set->dpll_speed;
+        } else {                                /* DPLL clockout x 2 */
+                high = curr_prcm_set->dpll_speed;
+                low = curr_prcm_set->dpll_speed / 2;
+        }
+
+#ifdef DOWN_VARIABLE_DPLL
+        if (target_rate > high)
+                return high;
+        else
+                return target_rate;
+#else
+        if (target_rate > low)
+                return high;
+        else
+                return low;
+#endif
+
+}
+
+unsigned long omap2_dpllcore_recalc(struct clk *clk)
+{
+        return omap2xxx_clk_get_core_rate(clk);
+}
+
+int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate)
+{
+        u32 cur_rate, low, mult, div, valid_rate, done_rate;
+        u32 bypass = 0;
+        struct prcm_config tmpset;
+        const struct dpll_data *dd;
+
+        cur_rate = omap2xxx_clk_get_core_rate(dclk);
+        mult = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
+        mult &= OMAP24XX_CORE_CLK_SRC_MASK;
+
+        if ((rate == (cur_rate / 2)) && (mult == 2)) {
+                omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL, 1);
+        } else if ((rate == (cur_rate * 2)) && (mult == 1)) {
+                omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL_X2, 1);
+        } else if (rate != cur_rate) {
+                valid_rate = omap2_dpllcore_round_rate(rate);
+                if (valid_rate != rate)
+                        return -EINVAL;
+
+                if (mult == 1)
+                        low = curr_prcm_set->dpll_speed;
+                else
+                        low = curr_prcm_set->dpll_speed / 2;
+
+                dd = clk->dpll_data;
+                if (!dd)
+                        return -EINVAL;
+
+                tmpset.cm_clksel1_pll = __raw_readl(dd->mult_div1_reg);
+                tmpset.cm_clksel1_pll &= ~(dd->mult_mask |
+                                           dd->div1_mask);
+                div = ((curr_prcm_set->xtal_speed / 1000000) - 1);
+                tmpset.cm_clksel2_pll = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
+                tmpset.cm_clksel2_pll &= ~OMAP24XX_CORE_CLK_SRC_MASK;
+                if (rate > low) {
+                        tmpset.cm_clksel2_pll |= CORE_CLK_SRC_DPLL_X2;
+                        mult = ((rate / 2) / 1000000);
+                        done_rate = CORE_CLK_SRC_DPLL_X2;
+                } else {
+                        tmpset.cm_clksel2_pll |= CORE_CLK_SRC_DPLL;
+                        mult = (rate / 1000000);
+                        done_rate = CORE_CLK_SRC_DPLL;
+                }
+                tmpset.cm_clksel1_pll |= (div << __ffs(dd->mult_mask));
+                tmpset.cm_clksel1_pll |= (mult << __ffs(dd->div1_mask));
+
+                /* Worst case */
+                tmpset.base_sdrc_rfr = SDRC_RFR_CTRL_BYPASS;
+
+                if (rate == curr_prcm_set->xtal_speed)  /* If asking for 1-1 */
+                        bypass = 1;
+
+                /* For omap2xxx_sdrc_init_params() */
+                omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL_X2, 1);
+
+                /* Force dll lock mode */
+                omap2_set_prcm(tmpset.cm_clksel1_pll, tmpset.base_sdrc_rfr,
+                               bypass);
+
+                /* Errata: ret dll entry state */
+                omap2xxx_sdrc_init_params(omap2xxx_sdrc_dll_is_unlocked());
+                omap2xxx_sdrc_reprogram(done_rate, 0);
+        }
+
+        return 0;
+}
+
+/**
+ * omap2_table_mpu_recalc - just return the MPU speed
+ * @clk: virt_prcm_set struct clk
+ *
+ * Set virt_prcm_set's rate to the mpu_speed field of the current PRCM set.
+ */
+unsigned long omap2_table_mpu_recalc(struct clk *clk)
+{
+        return curr_prcm_set->mpu_speed;
+}
+
+/*
+ * Look for a rate equal or less than the target rate given a configuration set.
+ *
+ * What's not entirely clear is "which" field represents the key field.
+ * Some might argue L3-DDR, others ARM, others IVA. This code is simple and
+ * just uses the ARM rates.
+ */
+long omap2_round_to_table_rate(struct clk *clk, unsigned long rate)
+{
+        const struct prcm_config *ptr;
+        long highest_rate;
+        long sys_ck_rate;
+
+        sys_ck_rate = clk_get_rate(sclk);
+
+        highest_rate = -EINVAL;
+
+        for (ptr = rate_table; ptr->mpu_speed; ptr++) {
+                if (!(ptr->flags & cpu_mask))
+                        continue;
+                if (ptr->xtal_speed != sys_ck_rate)
+                        continue;
+
+                highest_rate = ptr->mpu_speed;
+
+                /* Can check only after xtal frequency check */
+                if (ptr->mpu_speed <= rate)
+                        break;
+        }
+        return highest_rate;
+}
+
+/* Sets basic clocks based on the specified rate */
+int omap2_select_table_rate(struct clk *clk, unsigned long rate)
+{
+        u32 cur_rate, done_rate, bypass = 0, tmp;
+        const struct prcm_config *prcm;
+        unsigned long found_speed = 0;
+        unsigned long flags;
+        long sys_ck_rate;
+
+        sys_ck_rate = clk_get_rate(sclk);
+
+        for (prcm = rate_table; prcm->mpu_speed; prcm++) {
+                if (!(prcm->flags & cpu_mask))
+                        continue;
+
+                if (prcm->xtal_speed != sys_ck_rate)
+                        continue;
+
+                if (prcm->mpu_speed <= rate) {
+                        found_speed = prcm->mpu_speed;
+                        break;
+                }
+        }
+
+        if (!found_speed) {
+                printk(KERN_INFO "Could not set MPU rate to %luMHz\n",
+                       rate / 1000000);
+                return -EINVAL;
+        }
+
+        curr_prcm_set = prcm;
+        cur_rate = omap2xxx_clk_get_core_rate(dclk);
+
+        if (prcm->dpll_speed == cur_rate / 2) {
+                omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL, 1);
+        } else if (prcm->dpll_speed == cur_rate * 2) {
+                omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL_X2, 1);
+        } else if (prcm->dpll_speed != cur_rate) {
+                local_irq_save(flags);
+
+                if (prcm->dpll_speed == prcm->xtal_speed)
+                        bypass = 1;
+
+                if ((prcm->cm_clksel2_pll & OMAP24XX_CORE_CLK_SRC_MASK) ==
+                    CORE_CLK_SRC_DPLL_X2)
+                        done_rate = CORE_CLK_SRC_DPLL_X2;
+                else
+                        done_rate = CORE_CLK_SRC_DPLL;
+
+                /* MPU divider */
+                cm_write_mod_reg(prcm->cm_clksel_mpu, MPU_MOD, CM_CLKSEL);
+
+                /* dsp + iva1 div(2420), iva2.1(2430) */
+                cm_write_mod_reg(prcm->cm_clksel_dsp,
+                                 OMAP24XX_DSP_MOD, CM_CLKSEL);
+
+                cm_write_mod_reg(prcm->cm_clksel_gfx, GFX_MOD, CM_CLKSEL);
+
+                /* Major subsystem dividers */
+                tmp = cm_read_mod_reg(CORE_MOD, CM_CLKSEL1) & OMAP24XX_CLKSEL_DSS2_MASK;
+                cm_write_mod_reg(prcm->cm_clksel1_core | tmp, CORE_MOD,
+                                 CM_CLKSEL1);
+
+                if (cpu_is_omap2430())
+                        cm_write_mod_reg(prcm->cm_clksel_mdm,
+                                         OMAP2430_MDM_MOD, CM_CLKSEL);
+
+                /* x2 to enter omap2xxx_sdrc_init_params() */
+                omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL_X2, 1);
+
+                omap2_set_prcm(prcm->cm_clksel1_pll, prcm->base_sdrc_rfr,
+                               bypass);
+
+                omap2xxx_sdrc_init_params(omap2xxx_sdrc_dll_is_unlocked());
+                omap2xxx_sdrc_reprogram(done_rate, 0);
+
+                local_irq_restore(flags);
+        }
+
+        return 0;
+}
+
+#ifdef CONFIG_CPU_FREQ
+/*
+ * Walk PRCM rate table and fillout cpufreq freq_table
+ */
+static struct cpufreq_frequency_table freq_table[ARRAY_SIZE(rate_table)];
+
+void omap2_clk_init_cpufreq_table(struct cpufreq_frequency_table **table)
+{
+        struct prcm_config *prcm;
+        int i = 0;
+
+        for (prcm = rate_table; prcm->mpu_speed; prcm++) {
+                if (!(prcm->flags & cpu_mask))
+                        continue;
+                if (prcm->xtal_speed != sys_ck.rate)
+                        continue;
+
+                /* don't put bypass rates in table */
+                if (prcm->dpll_speed == prcm->xtal_speed)
+                        continue;
+
+                freq_table[i].index = i;
+                freq_table[i].frequency = prcm->mpu_speed / 1000;
+                i++;
+        }
+
+        if (i == 0) {
+                printk(KERN_WARNING "%s: failed to initialize frequency "
+                       "table\n", __func__);
+                return;
+        }
+
+        freq_table[i].index = i;
+        freq_table[i].frequency = CPUFREQ_TABLE_END;
+
+        *table = &freq_table[0];
+}
+#endif
+
+struct clk_functions omap2_clk_functions = {
+        .clk_enable             = omap2_clk_enable,
+        .clk_disable            = omap2_clk_disable,
+        .clk_round_rate         = omap2_clk_round_rate,
+        .clk_set_rate           = omap2_clk_set_rate,
+        .clk_set_parent         = omap2_clk_set_parent,
+        .clk_disable_unused     = omap2_clk_disable_unused,
+#ifdef  CONFIG_CPU_FREQ
+        .clk_init_cpufreq_table = omap2_clk_init_cpufreq_table,
+#endif
+};
+
+static u32 omap2_get_apll_clkin(void)
+{
+        u32 aplls, srate = 0;
+
+        aplls = cm_read_mod_reg(PLL_MOD, CM_CLKSEL1);
+        aplls &= OMAP24XX_APLLS_CLKIN_MASK;
+        aplls >>= OMAP24XX_APLLS_CLKIN_SHIFT;
+
+        if (aplls == APLLS_CLKIN_19_2MHZ)
+                srate = 19200000;
+        else if (aplls == APLLS_CLKIN_13MHZ)
+                srate = 13000000;
+        else if (aplls == APLLS_CLKIN_12MHZ)
+                srate = 12000000;
+
+        return srate;
+}
+
+static u32 omap2_get_sysclkdiv(void)
+{
+        u32 div;
+
+        div = __raw_readl(prcm_clksrc_ctrl);
+        div &= OMAP_SYSCLKDIV_MASK;
+        div >>= OMAP_SYSCLKDIV_SHIFT;
+
+        return div;
+}
+
+unsigned long omap2_osc_clk_recalc(struct clk *clk)
+{
+        return omap2_get_apll_clkin() * omap2_get_sysclkdiv();
+}
+
+unsigned long omap2_sys_clk_recalc(struct clk *clk)
+{
+        return clk->parent->rate / omap2_get_sysclkdiv();
+}
+
+/*
+ * Set clocks for bypass mode for reboot to work.
+ */
+void omap2_clk_prepare_for_reboot(void)
+{
+        u32 rate;
+
+        if (vclk == NULL || sclk == NULL)
+                return;
+
+        rate = clk_get_rate(sclk);
+        clk_set_rate(vclk, rate);
+}
+
+/*
+ * Switch the MPU rate if specified on cmdline.
+ * We cannot do this early until cmdline is parsed.
+ */
+static int __init omap2_clk_arch_init(void)
+{
+        struct clk *virt_prcm_set, *sys_ck, *dpll_ck, *mpu_ck;
+        unsigned long sys_ck_rate;
+
+        if (!mpurate)
+                return -EINVAL;
+
+        virt_prcm_set = clk_get(NULL, "virt_prcm_set");
+        sys_ck = clk_get(NULL, "sys_ck");
+        dpll_ck = clk_get(NULL, "dpll_ck");
+        mpu_ck = clk_get(NULL, "mpu_ck");
+
+        if (clk_set_rate(virt_prcm_set, mpurate))
+                printk(KERN_ERR "Could not find matching MPU rate\n");
+
+        recalculate_root_clocks();
+
+        sys_ck_rate = clk_get_rate(sys_ck);
+
+        pr_info("Switched to new clocking rate (Crystal/DPLL/MPU): "
+                "%ld.%01ld/%ld/%ld MHz\n",
+                (sys_ck_rate / 1000000), (sys_ck_rate / 100000) % 10,
+                (clk_get_rate(dpll_ck) / 1000000),
+                (clk_get_rate(mpu_ck) / 1000000));
+
+        return 0;
+}
+arch_initcall(omap2_clk_arch_init);
+
+
diff --git a/arch/arm/mach-omap2/clock2xxx.h b/arch/arm/mach-omap2/clock2xxx.h
new file mode 100644
index 000000000000..e35efde4bd80
--- /dev/null
+++ b/arch/arm/mach-omap2/clock2xxx.h
@@ -0,0 +1,41 @@
+/*
+ * OMAP2 clock function prototypes and macros
+ *
+ * Copyright (C) 2005-2009 Texas Instruments, Inc.
+ * Copyright (C) 2004-2009 Nokia Corporation
+ */
+
+#ifndef __ARCH_ARM_MACH_OMAP2_CLOCK_24XX_H
+#define __ARCH_ARM_MACH_OMAP2_CLOCK_24XX_H
+
+unsigned long omap2_table_mpu_recalc(struct clk *clk);
+int omap2_select_table_rate(struct clk *clk, unsigned long rate);
+long omap2_round_to_table_rate(struct clk *clk, unsigned long rate);
+unsigned long omap2_sys_clk_recalc(struct clk *clk);
+unsigned long omap2_osc_clk_recalc(struct clk *clk);
+unsigned long omap2_sys_clk_recalc(struct clk *clk);
+unsigned long omap2_dpllcore_recalc(struct clk *clk);
+int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate);
+unsigned long omap2xxx_clk_get_core_rate(struct clk *clk);
+
+/* REVISIT: These should be set dynamically for CONFIG_MULTI_OMAP2 */
+#ifdef CONFIG_ARCH_OMAP2420
+#define OMAP_CM_REGADDR                 OMAP2420_CM_REGADDR
+#define OMAP24XX_PRCM_CLKOUT_CTRL       OMAP2420_PRCM_CLKOUT_CTRL
+#define OMAP24XX_PRCM_CLKEMUL_CTRL      OMAP2420_PRCM_CLKEMUL_CTRL
+#else
+#define OMAP_CM_REGADDR                 OMAP2430_CM_REGADDR
+#define OMAP24XX_PRCM_CLKOUT_CTRL       OMAP2430_PRCM_CLKOUT_CTRL
+#define OMAP24XX_PRCM_CLKEMUL_CTRL      OMAP2430_PRCM_CLKEMUL_CTRL
+#endif
+
+extern void __iomem *prcm_clksrc_ctrl;
+
+extern struct clk *dclk;
+
+extern const struct clkops clkops_omap2430_i2chs_wait;
+extern const struct clkops clkops_oscck;
+extern const struct clkops clkops_apll96;
+extern const struct clkops clkops_apll54;
+
+#endif
diff --git a/arch/arm/mach-omap2/clock24xx.h b/arch/arm/mach-omap2/clock2xxx_data.c
index d19cf7a7d8db..97dc7cf7751d 100644
--- a/arch/arm/mach-omap2/clock24xx.h
+++ b/arch/arm/mach-omap2/clock2xxx_data.c
@@ -1,8 +1,8 @@
 /*
- *  linux/arch/arm/mach-omap2/clock24xx.h
+ *  linux/arch/arm/mach-omap2/clock2xxx_data.c
  *
- *  Copyright (C) 2005-2008 Texas Instruments, Inc.
- *  Copyright (C) 2004-2008 Nokia Corporation
+ *  Copyright (C) 2005-2009 Texas Instruments, Inc.
+ *  Copyright (C) 2004-2009 Nokia Corporation
  *
  *  Contacts:
  *  Richard Woodruff <r-woodruff2@ti.com>
@@ -13,600 +13,21 @@
  * published by the Free Software Foundation.
  */
 
-#ifndef __ARCH_ARM_MACH_OMAP2_CLOCK24XX_H
-#define __ARCH_ARM_MACH_OMAP2_CLOCK24XX_H
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/clk.h>
 
-#include "clock.h"
+#include <plat/clkdev_omap.h>
 
+#include "clock.h"
+#include "clock2xxx.h"
+#include "opp2xxx.h"
 #include "prm.h"
 #include "cm.h"
 #include "prm-regbits-24xx.h"
 #include "cm-regbits-24xx.h"
 #include "sdrc.h"
 
-/* REVISIT: These should be set dynamically for CONFIG_MULTI_OMAP2 */
-#ifdef CONFIG_ARCH_OMAP2420
-#define OMAP_CM_REGADDR                 OMAP2420_CM_REGADDR
-#define OMAP24XX_PRCM_CLKOUT_CTRL       OMAP2420_PRCM_CLKOUT_CTRL
-#define OMAP24XX_PRCM_CLKEMUL_CTRL      OMAP2420_PRCM_CLKEMUL_CTRL
-#else
-#define OMAP_CM_REGADDR                 OMAP2430_CM_REGADDR
-#define OMAP24XX_PRCM_CLKOUT_CTRL       OMAP2430_PRCM_CLKOUT_CTRL
-#define OMAP24XX_PRCM_CLKEMUL_CTRL      OMAP2430_PRCM_CLKEMUL_CTRL
-#endif
-
-static unsigned long omap2_table_mpu_recalc(struct clk *clk);
-static int omap2_select_table_rate(struct clk *clk, unsigned long rate);
-static long omap2_round_to_table_rate(struct clk *clk, unsigned long rate);
-static unsigned long omap2_sys_clk_recalc(struct clk *clk);
-static unsigned long omap2_osc_clk_recalc(struct clk *clk);
-static unsigned long omap2_sys_clk_recalc(struct clk *clk);
-static unsigned long omap2_dpllcore_recalc(struct clk *clk);
-static int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate);
-
-/* Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated.
- * xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU,CM_CLKSEL_DSP
- * CM_CLKSEL_GFX, CM_CLKSEL1_CORE, CM_CLKSEL1_PLL CM_CLKSEL2_PLL, CM_CLKSEL_MDM
- */
-struct prcm_config {
-        unsigned long xtal_speed;       /* crystal rate */
-        unsigned long dpll_speed;       /* dpll: out*xtal*M/(N-1)table_recalc */
-        unsigned long mpu_speed;        /* speed of MPU */
-        unsigned long cm_clksel_mpu;    /* mpu divider */
-        unsigned long cm_clksel_dsp;    /* dsp+iva1 div(2420), iva2.1(2430) */
-        unsigned long cm_clksel_gfx;    /* gfx dividers */
-        unsigned long cm_clksel1_core;  /* major subsystem dividers */
-        unsigned long cm_clksel1_pll;   /* m,n */
-        unsigned long cm_clksel2_pll;   /* dpllx1 or x2 out */
-        unsigned long cm_clksel_mdm;    /* modem dividers 2430 only */
-        unsigned long base_sdrc_rfr;    /* base refresh timing for a set */
-        unsigned char flags;
-};
-
-/*
- * The OMAP2 processor can be run at several discrete 'PRCM configurations'.
- * These configurations are characterized by voltage and speed for clocks.
- * The device is only validated for certain combinations. One way to express
- * these combinations is via the 'ratio's' which the clocks operate with
- * respect to each other. These ratio sets are for a given voltage/DPLL
- * setting. All configurations can be described by a DPLL setting and a ratio
- * There are 3 ratio sets for the 2430 and X ratio sets for 2420.
- *
- * 2430 differs from 2420 in that there are no more phase synchronizers used.
- * They both have a slightly different clock domain setup. 2420(iva1,dsp) vs
- * 2430 (iva2.1, NOdsp, mdm)
- */
-
-/* Core fields for cm_clksel, not ratio governed */
-#define RX_CLKSEL_DSS1                  (0x10 << 8)
-#define RX_CLKSEL_DSS2                  (0x0 << 13)
-#define RX_CLKSEL_SSI                   (0x5 << 20)
-
-/*-------------------------------------------------------------------------
- * Voltage/DPLL ratios
- *-------------------------------------------------------------------------*/
-
-/* 2430 Ratio's, 2430-Ratio Config 1 */
-#define R1_CLKSEL_L3                    (4 << 0)
-#define R1_CLKSEL_L4                    (2 << 5)
-#define R1_CLKSEL_USB                   (4 << 25)
-#define R1_CM_CLKSEL1_CORE_VAL          R1_CLKSEL_USB | RX_CLKSEL_SSI | \
-                                        RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
-                                        R1_CLKSEL_L4 | R1_CLKSEL_L3
-#define R1_CLKSEL_MPU                   (2 << 0)
-#define R1_CM_CLKSEL_MPU_VAL            R1_CLKSEL_MPU
-#define R1_CLKSEL_DSP                   (2 << 0)
-#define R1_CLKSEL_DSP_IF                (2 << 5)
-#define R1_CM_CLKSEL_DSP_VAL            R1_CLKSEL_DSP | R1_CLKSEL_DSP_IF
-#define R1_CLKSEL_GFX                   (2 << 0)
-#define R1_CM_CLKSEL_GFX_VAL            R1_CLKSEL_GFX
-#define R1_CLKSEL_MDM                   (4 << 0)
-#define R1_CM_CLKSEL_MDM_VAL            R1_CLKSEL_MDM
-
-/* 2430-Ratio Config 2 */
-#define R2_CLKSEL_L3                    (6 << 0)
-#define R2_CLKSEL_L4                    (2 << 5)
-#define R2_CLKSEL_USB                   (2 << 25)
-#define R2_CM_CLKSEL1_CORE_VAL          R2_CLKSEL_USB | RX_CLKSEL_SSI | \
-                                        RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
-                                        R2_CLKSEL_L4 | R2_CLKSEL_L3
-#define R2_CLKSEL_MPU                   (2 << 0)
-#define R2_CM_CLKSEL_MPU_VAL            R2_CLKSEL_MPU
-#define R2_CLKSEL_DSP                   (2 << 0)
-#define R2_CLKSEL_DSP_IF                (3 << 5)
-#define R2_CM_CLKSEL_DSP_VAL            R2_CLKSEL_DSP | R2_CLKSEL_DSP_IF
-#define R2_CLKSEL_GFX                   (2 << 0)
-#define R2_CM_CLKSEL_GFX_VAL            R2_CLKSEL_GFX
-#define R2_CLKSEL_MDM                   (6 << 0)
-#define R2_CM_CLKSEL_MDM_VAL            R2_CLKSEL_MDM
-
-/* 2430-Ratio Bootm (BYPASS) */
-#define RB_CLKSEL_L3                    (1 << 0)
-#define RB_CLKSEL_L4                    (1 << 5)
-#define RB_CLKSEL_USB                   (1 << 25)
-#define RB_CM_CLKSEL1_CORE_VAL          RB_CLKSEL_USB | RX_CLKSEL_SSI | \
-                                        RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
-                                        RB_CLKSEL_L4 | RB_CLKSEL_L3
-#define RB_CLKSEL_MPU                   (1 << 0)
-#define RB_CM_CLKSEL_MPU_VAL            RB_CLKSEL_MPU
-#define RB_CLKSEL_DSP                   (1 << 0)
-#define RB_CLKSEL_DSP_IF                (1 << 5)
-#define RB_CM_CLKSEL_DSP_VAL            RB_CLKSEL_DSP | RB_CLKSEL_DSP_IF
-#define RB_CLKSEL_GFX                   (1 << 0)
-#define RB_CM_CLKSEL_GFX_VAL            RB_CLKSEL_GFX
-#define RB_CLKSEL_MDM                   (1 << 0)
-#define RB_CM_CLKSEL_MDM_VAL            RB_CLKSEL_MDM
-
-/* 2420 Ratio Equivalents */
-#define RXX_CLKSEL_VLYNQ                (0x12 << 15)
-#define RXX_CLKSEL_SSI                  (0x8 << 20)
-
-/* 2420-PRCM III 532MHz core */
-#define RIII_CLKSEL_L3                  (4 << 0)        /* 133MHz */
-#define RIII_CLKSEL_L4                  (2 << 5)        /* 66.5MHz */
-#define RIII_CLKSEL_USB                 (4 << 25)       /* 33.25MHz */
-#define RIII_CM_CLKSEL1_CORE_VAL        RIII_CLKSEL_USB | RXX_CLKSEL_SSI | \
-                                        RXX_CLKSEL_VLYNQ | RX_CLKSEL_DSS2 | \
-                                        RX_CLKSEL_DSS1 | RIII_CLKSEL_L4 | \
-                                        RIII_CLKSEL_L3
-#define RIII_CLKSEL_MPU                 (2 << 0)        /* 266MHz */
-#define RIII_CM_CLKSEL_MPU_VAL          RIII_CLKSEL_MPU
-#define RIII_CLKSEL_DSP                 (3 << 0)        /* c5x - 177.3MHz */
-#define RIII_CLKSEL_DSP_IF              (2 << 5)        /* c5x - 88.67MHz */
-#define RIII_SYNC_DSP                   (1 << 7)        /* Enable sync */
-#define RIII_CLKSEL_IVA                 (6 << 8)        /* iva1 - 88.67MHz */
-#define RIII_SYNC_IVA                   (1 << 13)       /* Enable sync */
-#define RIII_CM_CLKSEL_DSP_VAL          RIII_SYNC_IVA | RIII_CLKSEL_IVA | \
-                                        RIII_SYNC_DSP | RIII_CLKSEL_DSP_IF | \
-                                        RIII_CLKSEL_DSP
-#define RIII_CLKSEL_GFX                 (2 << 0)        /* 66.5MHz */
-#define RIII_CM_CLKSEL_GFX_VAL          RIII_CLKSEL_GFX
-
-/* 2420-PRCM II 600MHz core */
-#define RII_CLKSEL_L3                   (6 << 0)        /* 100MHz */
-#define RII_CLKSEL_L4                   (2 << 5)        /* 50MHz */
-#define RII_CLKSEL_USB                  (2 << 25)       /* 50MHz */
-#define RII_CM_CLKSEL1_CORE_VAL         RII_CLKSEL_USB | \
-                                        RXX_CLKSEL_SSI | RXX_CLKSEL_VLYNQ | \
-                                        RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
-                                        RII_CLKSEL_L4 | RII_CLKSEL_L3
-#define RII_CLKSEL_MPU                  (2 << 0)        /* 300MHz */
-#define RII_CM_CLKSEL_MPU_VAL           RII_CLKSEL_MPU
-#define RII_CLKSEL_DSP                  (3 << 0)        /* c5x - 200MHz */
-#define RII_CLKSEL_DSP_IF               (2 << 5)        /* c5x - 100MHz */
-#define RII_SYNC_DSP                    (0 << 7)        /* Bypass sync */
-#define RII_CLKSEL_IVA                  (3 << 8)        /* iva1 - 200MHz */
-#define RII_SYNC_IVA                    (0 << 13)       /* Bypass sync */
-#define RII_CM_CLKSEL_DSP_VAL           RII_SYNC_IVA | RII_CLKSEL_IVA | \
-                                        RII_SYNC_DSP | RII_CLKSEL_DSP_IF | \
-                                        RII_CLKSEL_DSP
-#define RII_CLKSEL_GFX                  (2 << 0)        /* 50MHz */
-#define RII_CM_CLKSEL_GFX_VAL           RII_CLKSEL_GFX
-
-/* 2420-PRCM I 660MHz core */
-#define RI_CLKSEL_L3                    (4 << 0)        /* 165MHz */
-#define RI_CLKSEL_L4                    (2 << 5)        /* 82.5MHz */
-#define RI_CLKSEL_USB                   (4 << 25)       /* 41.25MHz */
-#define RI_CM_CLKSEL1_CORE_VAL          RI_CLKSEL_USB | \
-                                        RXX_CLKSEL_SSI | RXX_CLKSEL_VLYNQ | \
-                                        RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
-                                        RI_CLKSEL_L4 | RI_CLKSEL_L3
-#define RI_CLKSEL_MPU                   (2 << 0)        /* 330MHz */
-#define RI_CM_CLKSEL_MPU_VAL            RI_CLKSEL_MPU
-#define RI_CLKSEL_DSP                   (3 << 0)        /* c5x - 220MHz */
-#define RI_CLKSEL_DSP_IF                (2 << 5)        /* c5x - 110MHz */
-#define RI_SYNC_DSP                     (1 << 7)        /* Activate sync */
-#define RI_CLKSEL_IVA                   (4 << 8)        /* iva1 - 165MHz */
-#define RI_SYNC_IVA                     (0 << 13)       /* Bypass sync */
-#define RI_CM_CLKSEL_DSP_VAL            RI_SYNC_IVA | RI_CLKSEL_IVA | \
-                                        RI_SYNC_DSP | RI_CLKSEL_DSP_IF | \
-                                        RI_CLKSEL_DSP
-#define RI_CLKSEL_GFX                   (1 << 0)        /* 165MHz */
-#define RI_CM_CLKSEL_GFX_VAL            RI_CLKSEL_GFX
-
-/* 2420-PRCM VII (boot) */
-#define RVII_CLKSEL_L3                  (1 << 0)
-#define RVII_CLKSEL_L4                  (1 << 5)
-#define RVII_CLKSEL_DSS1                (1 << 8)
-#define RVII_CLKSEL_DSS2                (0 << 13)
-#define RVII_CLKSEL_VLYNQ               (1 << 15)
-#define RVII_CLKSEL_SSI                 (1 << 20)
-#define RVII_CLKSEL_USB                 (1 << 25)
-
-#define RVII_CM_CLKSEL1_CORE_VAL        RVII_CLKSEL_USB | RVII_CLKSEL_SSI | \
-                                        RVII_CLKSEL_VLYNQ | RVII_CLKSEL_DSS2 | \
-                                        RVII_CLKSEL_DSS1 | RVII_CLKSEL_L4 | RVII_CLKSEL_L3
-
-#define RVII_CLKSEL_MPU                 (1 << 0) /* all divide by 1 */
-#define RVII_CM_CLKSEL_MPU_VAL          RVII_CLKSEL_MPU
-
-#define RVII_CLKSEL_DSP                 (1 << 0)
-#define RVII_CLKSEL_DSP_IF              (1 << 5)
-#define RVII_SYNC_DSP                   (0 << 7)
-#define RVII_CLKSEL_IVA                 (1 << 8)
-#define RVII_SYNC_IVA                   (0 << 13)
-#define RVII_CM_CLKSEL_DSP_VAL          RVII_SYNC_IVA | RVII_CLKSEL_IVA | RVII_SYNC_DSP | \
-                                        RVII_CLKSEL_DSP_IF | RVII_CLKSEL_DSP
-
-#define RVII_CLKSEL_GFX                 (1 << 0)
-#define RVII_CM_CLKSEL_GFX_VAL          RVII_CLKSEL_GFX
-
-/*-------------------------------------------------------------------------
- * 2430 Target modes: Along with each configuration the CPU has several
- * modes which goes along with them. Modes mainly are the addition of
- * describe DPLL combinations to go along with a ratio.
- *-------------------------------------------------------------------------*/
-
-/* Hardware governed */
-#define MX_48M_SRC                      (0 << 3)
-#define MX_54M_SRC                      (0 << 5)
-#define MX_APLLS_CLIKIN_12              (3 << 23)
-#define MX_APLLS_CLIKIN_13              (2 << 23)
-#define MX_APLLS_CLIKIN_19_2            (0 << 23)
-
-/*
- * 2430 - standalone, 2*ref*M/(n+1), M/N is for exactness not relock speed
- * #5a  (ratio1) baseport-target, target DPLL = 266*2 = 532MHz
- */
-#define M5A_DPLL_MULT_12                (133 << 12)
-#define M5A_DPLL_DIV_12                 (5 << 8)
-#define M5A_CM_CLKSEL1_PLL_12_VAL       MX_48M_SRC | MX_54M_SRC | \
-                                        M5A_DPLL_DIV_12 | M5A_DPLL_MULT_12 | \
-                                        MX_APLLS_CLIKIN_12
-#define M5A_DPLL_MULT_13                (61 << 12)
-#define M5A_DPLL_DIV_13                 (2 << 8)
-#define M5A_CM_CLKSEL1_PLL_13_VAL       MX_48M_SRC | MX_54M_SRC | \
-                                        M5A_DPLL_DIV_13 | M5A_DPLL_MULT_13 | \
-                                        MX_APLLS_CLIKIN_13
-#define M5A_DPLL_MULT_19                (55 << 12)
-#define M5A_DPLL_DIV_19                 (3 << 8)
-#define M5A_CM_CLKSEL1_PLL_19_VAL       MX_48M_SRC | MX_54M_SRC | \
-                                        M5A_DPLL_DIV_19 | M5A_DPLL_MULT_19 | \
-                                        MX_APLLS_CLIKIN_19_2
-/* #5b  (ratio1) target DPLL = 200*2 = 400MHz */
-#define M5B_DPLL_MULT_12                (50 << 12)
-#define M5B_DPLL_DIV_12                 (2 << 8)
-#define M5B_CM_CLKSEL1_PLL_12_VAL       MX_48M_SRC | MX_54M_SRC | \
-                                        M5B_DPLL_DIV_12 | M5B_DPLL_MULT_12 | \
-                                        MX_APLLS_CLIKIN_12
-#define M5B_DPLL_MULT_13                (200 << 12)
-#define M5B_DPLL_DIV_13                 (12 << 8)
-
-#define M5B_CM_CLKSEL1_PLL_13_VAL       MX_48M_SRC | MX_54M_SRC | \
-                                        M5B_DPLL_DIV_13 | M5B_DPLL_MULT_13 | \
-                                        MX_APLLS_CLIKIN_13
-#define M5B_DPLL_MULT_19                (125 << 12)
-#define M5B_DPLL_DIV_19                 (31 << 8)
-#define M5B_CM_CLKSEL1_PLL_19_VAL       MX_48M_SRC | MX_54M_SRC | \
-                                        M5B_DPLL_DIV_19 | M5B_DPLL_MULT_19 | \
-                                        MX_APLLS_CLIKIN_19_2
-/*
- * #4   (ratio2), DPLL = 399*2 = 798MHz, L3=133MHz
- */
-#define M4_DPLL_MULT_12                 (133 << 12)
-#define M4_DPLL_DIV_12                  (3 << 8)
-#define M4_CM_CLKSEL1_PLL_12_VAL        MX_48M_SRC | MX_54M_SRC | \
-                                        M4_DPLL_DIV_12 | M4_DPLL_MULT_12 | \
-                                        MX_APLLS_CLIKIN_12
-
-#define M4_DPLL_MULT_13                 (399 << 12)
-#define M4_DPLL_DIV_13                  (12 << 8)
-#define M4_CM_CLKSEL1_PLL_13_VAL        MX_48M_SRC | MX_54M_SRC | \
-                                        M4_DPLL_DIV_13 | M4_DPLL_MULT_13 | \
-                                        MX_APLLS_CLIKIN_13
-
-#define M4_DPLL_MULT_19                 (145 << 12)
-#define M4_DPLL_DIV_19                  (6 << 8)
-#define M4_CM_CLKSEL1_PLL_19_VAL        MX_48M_SRC | MX_54M_SRC | \
-                                        M4_DPLL_DIV_19 | M4_DPLL_MULT_19 | \
-                                        MX_APLLS_CLIKIN_19_2
-
-/*
- * #3   (ratio2) baseport-target, target DPLL = 330*2 = 660MHz
- */
-#define M3_DPLL_MULT_12                 (55 << 12)
-#define M3_DPLL_DIV_12                  (1 << 8)
-#define M3_CM_CLKSEL1_PLL_12_VAL        MX_48M_SRC | MX_54M_SRC | \
-                                        M3_DPLL_DIV_12 | M3_DPLL_MULT_12 | \
-                                        MX_APLLS_CLIKIN_12
-#define M3_DPLL_MULT_13                 (76 << 12)
-#define M3_DPLL_DIV_13                  (2 << 8)
-#define M3_CM_CLKSEL1_PLL_13_VAL        MX_48M_SRC | MX_54M_SRC | \
-                                        M3_DPLL_DIV_13 | M3_DPLL_MULT_13 | \
-                                        MX_APLLS_CLIKIN_13
-#define M3_DPLL_MULT_19                 (17 << 12)
-#define M3_DPLL_DIV_19                  (0 << 8)
-#define M3_CM_CLKSEL1_PLL_19_VAL        MX_48M_SRC | MX_54M_SRC | \
-                                        M3_DPLL_DIV_19 | M3_DPLL_MULT_19 | \
-                                        MX_APLLS_CLIKIN_19_2
-
-/*
- * #2   (ratio1) DPLL = 330*2 = 660MHz, L3=165MHz
- */
-#define M2_DPLL_MULT_12                 (55 << 12)
-#define M2_DPLL_DIV_12                  (1 << 8)
-#define M2_CM_CLKSEL1_PLL_12_VAL        MX_48M_SRC | MX_54M_SRC | \
-                                        M2_DPLL_DIV_12 | M2_DPLL_MULT_12 | \
-                                        MX_APLLS_CLIKIN_12
-
-/* Speed changes - Used 658.7MHz instead of 660MHz for LP-Refresh M=76 N=2,
- * relock time issue */
-/* Core frequency changed from 330/165 to 329/164 MHz*/
-#define M2_DPLL_MULT_13                 (76 << 12)
-#define M2_DPLL_DIV_13                  (2 << 8)
-#define M2_CM_CLKSEL1_PLL_13_VAL        MX_48M_SRC | MX_54M_SRC | \
-                                        M2_DPLL_DIV_13 | M2_DPLL_MULT_13 | \
-                                        MX_APLLS_CLIKIN_13
-
-#define M2_DPLL_MULT_19                 (17 << 12)
-#define M2_DPLL_DIV_19                  (0 << 8)
-#define M2_CM_CLKSEL1_PLL_19_VAL        MX_48M_SRC | MX_54M_SRC | \
-                                        M2_DPLL_DIV_19 | M2_DPLL_MULT_19 | \
-                                        MX_APLLS_CLIKIN_19_2
-
-/* boot (boot) */
-#define MB_DPLL_MULT                    (1 << 12)
-#define MB_DPLL_DIV                     (0 << 8)
-#define MB_CM_CLKSEL1_PLL_12_VAL        MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV |\
-                                        MB_DPLL_MULT | MX_APLLS_CLIKIN_12
-
-#define MB_CM_CLKSEL1_PLL_13_VAL        MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV |\
-                                        MB_DPLL_MULT | MX_APLLS_CLIKIN_13
-
-#define MB_CM_CLKSEL1_PLL_19_VAL        MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV |\
-                                        MB_DPLL_MULT | MX_APLLS_CLIKIN_19
-
-/*
- * 2430 - chassis (sedna)
- * 165 (ratio1) same as above #2
- * 150 (ratio1)
- * 133 (ratio2) same as above #4
- * 110 (ratio2) same as above #3
- * 104 (ratio2)
- * boot (boot)
- */
-
-/* PRCM I target DPLL = 2*330MHz = 660MHz */
-#define MI_DPLL_MULT_12                 (55 << 12)
-#define MI_DPLL_DIV_12                  (1 << 8)
-#define MI_CM_CLKSEL1_PLL_12_VAL        MX_48M_SRC | MX_54M_SRC | \
-                                        MI_DPLL_DIV_12 | MI_DPLL_MULT_12 | \
-                                        MX_APLLS_CLIKIN_12
-
-/*
- * 2420 Equivalent - mode registers
- * PRCM II , target DPLL = 2*300MHz = 600MHz
- */
-#define MII_DPLL_MULT_12                (50 << 12)
-#define MII_DPLL_DIV_12                 (1 << 8)
-#define MII_CM_CLKSEL1_PLL_12_VAL       MX_48M_SRC | MX_54M_SRC | \
-                                        MII_DPLL_DIV_12 | MII_DPLL_MULT_12 | \
-                                        MX_APLLS_CLIKIN_12
-#define MII_DPLL_MULT_13                (300 << 12)
-#define MII_DPLL_DIV_13                 (12 << 8)
-#define MII_CM_CLKSEL1_PLL_13_VAL       MX_48M_SRC | MX_54M_SRC | \
-                                        MII_DPLL_DIV_13 | MII_DPLL_MULT_13 | \
-                                        MX_APLLS_CLIKIN_13
-
-/* PRCM III target DPLL = 2*266 = 532MHz*/
-#define MIII_DPLL_MULT_12               (133 << 12)
-#define MIII_DPLL_DIV_12                (5 << 8)
-#define MIII_CM_CLKSEL1_PLL_12_VAL      MX_48M_SRC | MX_54M_SRC | \
-                                        MIII_DPLL_DIV_12 | MIII_DPLL_MULT_12 | \
-                                        MX_APLLS_CLIKIN_12
-#define MIII_DPLL_MULT_13               (266 << 12)
-#define MIII_DPLL_DIV_13                (12 << 8)
-#define MIII_CM_CLKSEL1_PLL_13_VAL      MX_48M_SRC | MX_54M_SRC | \
-                                        MIII_DPLL_DIV_13 | MIII_DPLL_MULT_13 | \
-                                        MX_APLLS_CLIKIN_13
-
-/* PRCM VII (boot bypass) */
-#define MVII_CM_CLKSEL1_PLL_12_VAL      MB_CM_CLKSEL1_PLL_12_VAL
-#define MVII_CM_CLKSEL1_PLL_13_VAL      MB_CM_CLKSEL1_PLL_13_VAL
-
-/* High and low operation value */
-#define MX_CLKSEL2_PLL_2x_VAL           (2 << 0)
-#define MX_CLKSEL2_PLL_1x_VAL           (1 << 0)
-
-/* MPU speed defines */
-#define S12M    12000000
-#define S13M    13000000
-#define S19M    19200000
-#define S26M    26000000
-#define S100M   100000000
-#define S133M   133000000
-#define S150M   150000000
-#define S164M   164000000
-#define S165M   165000000
-#define S199M   199000000
-#define S200M   200000000
-#define S266M   266000000
-#define S300M   300000000
-#define S329M   329000000
-#define S330M   330000000
-#define S399M   399000000
-#define S400M   400000000
-#define S532M   532000000
-#define S600M   600000000
-#define S658M   658000000
-#define S660M   660000000
-#define S798M   798000000
-
-/*-------------------------------------------------------------------------
- * Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated.
- * xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU,
- * CM_CLKSEL_DSP, CM_CLKSEL_GFX, CM_CLKSEL1_CORE, CM_CLKSEL1_PLL,
- * CM_CLKSEL2_PLL, CM_CLKSEL_MDM
- *
- * Filling in table based on H4 boards and 2430-SDPs variants available.
- * There are quite a few more rates combinations which could be defined.
- *
- * When multiple values are defined the start up will try and choose the
- * fastest one. If a 'fast' value is defined, then automatically, the /2
- * one should be included as it can be used.    Generally having more that
- * one fast set does not make sense, as static timings need to be changed
- * to change the set.    The exception is the bypass setting which is
- * availble for low power bypass.
- *
- * Note: This table needs to be sorted, fastest to slowest.
- *-------------------------------------------------------------------------*/
-static struct prcm_config rate_table[] = {
-        /* PRCM I - FAST */
-        {S12M, S660M, S330M, RI_CM_CLKSEL_MPU_VAL,              /* 330MHz ARM */
-                RI_CM_CLKSEL_DSP_VAL, RI_CM_CLKSEL_GFX_VAL,
-                RI_CM_CLKSEL1_CORE_VAL, MI_CM_CLKSEL1_PLL_12_VAL,
-                MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_165MHz,
-                RATE_IN_242X},
-
-        /* PRCM II - FAST */
-        {S12M, S600M, S300M, RII_CM_CLKSEL_MPU_VAL,             /* 300MHz ARM */
-                RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
-                RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_12_VAL,
-                MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
-                RATE_IN_242X},
-
-        {S13M, S600M, S300M, RII_CM_CLKSEL_MPU_VAL,             /* 300MHz ARM */
-                RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
-                RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_13_VAL,
-                MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
-                RATE_IN_242X},
-
-        /* PRCM III - FAST */
-        {S12M, S532M, S266M, RIII_CM_CLKSEL_MPU_VAL,            /* 266MHz ARM */
-                RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
-                RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_12_VAL,
-                MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
-                RATE_IN_242X},
-
-        {S13M, S532M, S266M, RIII_CM_CLKSEL_MPU_VAL,            /* 266MHz ARM */
-                RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
-                RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_13_VAL,
-                MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
-                RATE_IN_242X},
-
-        /* PRCM II - SLOW */
-        {S12M, S300M, S150M, RII_CM_CLKSEL_MPU_VAL,             /* 150MHz ARM */
-                RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
-                RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_12_VAL,
-                MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
-                RATE_IN_242X},
-
-        {S13M, S300M, S150M, RII_CM_CLKSEL_MPU_VAL,             /* 150MHz ARM */
-                RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
-                RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_13_VAL,
-                MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
-                RATE_IN_242X},
-
-        /* PRCM III - SLOW */
-        {S12M, S266M, S133M, RIII_CM_CLKSEL_MPU_VAL,            /* 133MHz ARM */
-                RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
-                RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_12_VAL,
-                MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
-                RATE_IN_242X},
-
-        {S13M, S266M, S133M, RIII_CM_CLKSEL_MPU_VAL,            /* 133MHz ARM */
-                RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
-                RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_13_VAL,
-                MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
-                RATE_IN_242X},
-
-        /* PRCM-VII (boot-bypass) */
-        {S12M, S12M, S12M, RVII_CM_CLKSEL_MPU_VAL,              /* 12MHz ARM*/
-                RVII_CM_CLKSEL_DSP_VAL, RVII_CM_CLKSEL_GFX_VAL,
-                RVII_CM_CLKSEL1_CORE_VAL, MVII_CM_CLKSEL1_PLL_12_VAL,
-                MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_BYPASS,
-                RATE_IN_242X},
-
-        /* PRCM-VII (boot-bypass) */
-        {S13M, S13M, S13M, RVII_CM_CLKSEL_MPU_VAL,              /* 13MHz ARM */
-                RVII_CM_CLKSEL_DSP_VAL, RVII_CM_CLKSEL_GFX_VAL,
-                RVII_CM_CLKSEL1_CORE_VAL, MVII_CM_CLKSEL1_PLL_13_VAL,
-                MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_BYPASS,
-                RATE_IN_242X},
-
-        /* PRCM #4 - ratio2 (ES2.1) - FAST */
-        {S13M, S798M, S399M, R2_CM_CLKSEL_MPU_VAL,              /* 399MHz ARM */
-                R2_CM_CLKSEL_DSP_VAL, R2_CM_CLKSEL_GFX_VAL,
-                R2_CM_CLKSEL1_CORE_VAL, M4_CM_CLKSEL1_PLL_13_VAL,
-                MX_CLKSEL2_PLL_2x_VAL, R2_CM_CLKSEL_MDM_VAL,
-                SDRC_RFR_CTRL_133MHz,
-                RATE_IN_243X},
-
-        /* PRCM #2 - ratio1 (ES2) - FAST */
-        {S13M, S658M, S329M, R1_CM_CLKSEL_MPU_VAL,              /* 330MHz ARM */
-                R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
-                R1_CM_CLKSEL1_CORE_VAL, M2_CM_CLKSEL1_PLL_13_VAL,
-                MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL,
-                SDRC_RFR_CTRL_165MHz,
-                RATE_IN_243X},
-
-        /* PRCM #5a - ratio1 - FAST */
-        {S13M, S532M, S266M, R1_CM_CLKSEL_MPU_VAL,              /* 266MHz ARM */
-                R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
-                R1_CM_CLKSEL1_CORE_VAL, M5A_CM_CLKSEL1_PLL_13_VAL,
-                MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL,
-                SDRC_RFR_CTRL_133MHz,
-                RATE_IN_243X},
-
-        /* PRCM #5b - ratio1 - FAST */
-        {S13M, S400M, S200M, R1_CM_CLKSEL_MPU_VAL,              /* 200MHz ARM */
-                R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
-                R1_CM_CLKSEL1_CORE_VAL, M5B_CM_CLKSEL1_PLL_13_VAL,
-                MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL,
-                SDRC_RFR_CTRL_100MHz,
-                RATE_IN_243X},
-
-        /* PRCM #4 - ratio1 (ES2.1) - SLOW */
-        {S13M, S399M, S199M, R2_CM_CLKSEL_MPU_VAL,              /* 200MHz ARM */
-                R2_CM_CLKSEL_DSP_VAL, R2_CM_CLKSEL_GFX_VAL,
-                R2_CM_CLKSEL1_CORE_VAL, M4_CM_CLKSEL1_PLL_13_VAL,
-                MX_CLKSEL2_PLL_1x_VAL, R2_CM_CLKSEL_MDM_VAL,
-                SDRC_RFR_CTRL_133MHz,
-                RATE_IN_243X},
-
-        /* PRCM #2 - ratio1 (ES2) - SLOW */
-        {S13M, S329M, S164M, R1_CM_CLKSEL_MPU_VAL,              /* 165MHz ARM */
-                R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
-                R1_CM_CLKSEL1_CORE_VAL, M2_CM_CLKSEL1_PLL_13_VAL,
-                MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL,
-                SDRC_RFR_CTRL_165MHz,
-                RATE_IN_243X},
-
-        /* PRCM #5a - ratio1 - SLOW */
-        {S13M, S266M, S133M, R1_CM_CLKSEL_MPU_VAL,              /* 133MHz ARM */
-                R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
-                R1_CM_CLKSEL1_CORE_VAL, M5A_CM_CLKSEL1_PLL_13_VAL,
-                MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL,
-                SDRC_RFR_CTRL_133MHz,
-                RATE_IN_243X},
-
-        /* PRCM #5b - ratio1 - SLOW*/
-        {S13M, S200M, S100M, R1_CM_CLKSEL_MPU_VAL,              /* 100MHz ARM */
-                R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
-                R1_CM_CLKSEL1_CORE_VAL, M5B_CM_CLKSEL1_PLL_13_VAL,
-                MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL,
-                SDRC_RFR_CTRL_100MHz,
-                RATE_IN_243X},
-
-        /* PRCM-boot/bypass */
-        {S13M, S13M, S13M, RB_CM_CLKSEL_MPU_VAL,                /* 13Mhz */
-                RB_CM_CLKSEL_DSP_VAL, RB_CM_CLKSEL_GFX_VAL,
-                RB_CM_CLKSEL1_CORE_VAL, MB_CM_CLKSEL1_PLL_13_VAL,
-                MX_CLKSEL2_PLL_2x_VAL, RB_CM_CLKSEL_MDM_VAL,
-                SDRC_RFR_CTRL_BYPASS,
-                RATE_IN_243X},
-
-        /* PRCM-boot/bypass */
-        {S12M, S12M, S12M, RB_CM_CLKSEL_MPU_VAL,                /* 12Mhz */
-                RB_CM_CLKSEL_DSP_VAL, RB_CM_CLKSEL_GFX_VAL,
-                RB_CM_CLKSEL1_CORE_VAL, MB_CM_CLKSEL1_PLL_12_VAL,
-                MX_CLKSEL2_PLL_2x_VAL, RB_CM_CLKSEL_MDM_VAL,
-                SDRC_RFR_CTRL_BYPASS,
-                RATE_IN_243X},
-
-        { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
-};
-
 /*-------------------------------------------------------------------------
  * 24xx clock tree.
  *
@@ -708,7 +129,7 @@ static struct clk dpll_ck = {
 
 static struct clk apll96_ck = {
         .name           = "apll96_ck",
-        .ops            = &clkops_fixed,
+        .ops            = &clkops_apll96,
         .parent         = &sys_ck,
         .rate           = 96000000,
         .flags          = RATE_FIXED | ENABLE_ON_INIT,
@@ -719,7 +140,7 @@ static struct clk apll96_ck = {
 
 static struct clk apll54_ck = {
         .name           = "apll54_ck",
-        .ops            = &clkops_fixed,
+        .ops            = &clkops_apll54,
         .parent         = &sys_ck,
         .rate           = 54000000,
         .flags          = RATE_FIXED | ENABLE_ON_INIT,
@@ -2653,5 +2074,236 @@ static struct clk virt_prcm_set = {
         .round_rate     = &omap2_round_to_table_rate,
 };
 
-#endif
+
+/*
+ * clkdev integration
+ */
+
+static struct omap_clk omap24xx_clks[] = {
+        /* external root sources */
+        CLK(NULL,       "func_32k_ck",  &func_32k_ck,   CK_243X | CK_242X),
+        CLK(NULL,       "secure_32k_ck", &secure_32k_ck, CK_243X | CK_242X),
+        CLK(NULL,       "osc_ck",       &osc_ck,        CK_243X | CK_242X),
+        CLK(NULL,       "sys_ck",       &sys_ck,        CK_243X | CK_242X),
+        CLK(NULL,       "alt_ck",       &alt_ck,        CK_243X | CK_242X),
+        /* internal analog sources */
+        CLK(NULL,       "dpll_ck",      &dpll_ck,       CK_243X | CK_242X),
+        CLK(NULL,       "apll96_ck",    &apll96_ck,     CK_243X | CK_242X),
+        CLK(NULL,       "apll54_ck",    &apll54_ck,     CK_243X | CK_242X),
+        /* internal prcm root sources */
+        CLK(NULL,       "func_54m_ck",  &func_54m_ck,   CK_243X | CK_242X),
+        CLK(NULL,       "core_ck",      &core_ck,       CK_243X | CK_242X),
+        CLK(NULL,       "func_96m_ck",  &func_96m_ck,   CK_243X | CK_242X),
+        CLK(NULL,       "func_48m_ck",  &func_48m_ck,   CK_243X | CK_242X),
+        CLK(NULL,       "func_12m_ck",  &func_12m_ck,   CK_243X | CK_242X),
+        CLK(NULL,       "ck_wdt1_osc",  &wdt1_osc_ck,   CK_243X | CK_242X),
+        CLK(NULL,       "sys_clkout_src", &sys_clkout_src, CK_243X | CK_242X),
+        CLK(NULL,       "sys_clkout",   &sys_clkout,    CK_243X | CK_242X),
+        CLK(NULL,       "sys_clkout2_src", &sys_clkout2_src, CK_242X),
+        CLK(NULL,       "sys_clkout2",  &sys_clkout2,   CK_242X),
+        CLK(NULL,       "emul_ck",      &emul_ck,       CK_242X),
+        /* mpu domain clocks */
+        CLK(NULL,       "mpu_ck",       &mpu_ck,        CK_243X | CK_242X),
+        /* dsp domain clocks */
+        CLK(NULL,       "dsp_fck",      &dsp_fck,       CK_243X | CK_242X),
+        CLK(NULL,       "dsp_irate_ick", &dsp_irate_ick, CK_243X | CK_242X),
+        CLK(NULL,       "dsp_ick",      &dsp_ick,       CK_242X),
+        CLK(NULL,       "iva2_1_ick",   &iva2_1_ick,    CK_243X),
+        CLK(NULL,       "iva1_ifck",    &iva1_ifck,     CK_242X),
+        CLK(NULL,       "iva1_mpu_int_ifck", &iva1_mpu_int_ifck, CK_242X),
+        /* GFX domain clocks */
+        CLK(NULL,       "gfx_3d_fck",   &gfx_3d_fck,    CK_243X | CK_242X),
+        CLK(NULL,       "gfx_2d_fck",   &gfx_2d_fck,    CK_243X | CK_242X),
+        CLK(NULL,       "gfx_ick",      &gfx_ick,       CK_243X | CK_242X),
+        /* Modem domain clocks */
+        CLK(NULL,       "mdm_ick",      &mdm_ick,       CK_243X),
+        CLK(NULL,       "mdm_osc_ck",   &mdm_osc_ck,    CK_243X),
+        /* DSS domain clocks */
+        CLK("omapdss",  "ick",          &dss_ick,       CK_243X | CK_242X),
+        CLK("omapdss",  "dss1_fck",     &dss1_fck,      CK_243X | CK_242X),
+        CLK("omapdss",  "dss2_fck",     &dss2_fck,      CK_243X | CK_242X),
+        CLK("omapdss",  "tv_fck",       &dss_54m_fck,   CK_243X | CK_242X),
+        /* L3 domain clocks */
+        CLK(NULL,       "core_l3_ck",   &core_l3_ck,    CK_243X | CK_242X),
+        CLK(NULL,       "ssi_fck",      &ssi_ssr_sst_fck, CK_243X | CK_242X),
+        CLK(NULL,       "usb_l4_ick",   &usb_l4_ick,    CK_243X | CK_242X),
+        /* L4 domain clocks */
+        CLK(NULL,       "l4_ck",        &l4_ck,         CK_243X | CK_242X),
+        CLK(NULL,       "ssi_l4_ick",   &ssi_l4_ick,    CK_243X | CK_242X),
+        /* virtual meta-group clock */
+        CLK(NULL,       "virt_prcm_set", &virt_prcm_set, CK_243X | CK_242X),
+        /* general l4 interface ck, multi-parent functional clk */
+        CLK(NULL,       "gpt1_ick",     &gpt1_ick,      CK_243X | CK_242X),
+        CLK(NULL,       "gpt1_fck",     &gpt1_fck,      CK_243X | CK_242X),
+        CLK(NULL,       "gpt2_ick",     &gpt2_ick,      CK_243X | CK_242X),
+        CLK(NULL,       "gpt2_fck",     &gpt2_fck,      CK_243X | CK_242X),
+        CLK(NULL,       "gpt3_ick",     &gpt3_ick,      CK_243X | CK_242X),
+        CLK(NULL,       "gpt3_fck",     &gpt3_fck,      CK_243X | CK_242X),
+        CLK(NULL,       "gpt4_ick",     &gpt4_ick,      CK_243X | CK_242X),
+        CLK(NULL,       "gpt4_fck",     &gpt4_fck,      CK_243X | CK_242X),
+        CLK(NULL,       "gpt5_ick",     &gpt5_ick,      CK_243X | CK_242X),
+        CLK(NULL,       "gpt5_fck",     &gpt5_fck,      CK_243X | CK_242X),
+        CLK(NULL,       "gpt6_ick",     &gpt6_ick,      CK_243X | CK_242X),
+        CLK(NULL,       "gpt6_fck",     &gpt6_fck,      CK_243X | CK_242X),
+        CLK(NULL,       "gpt7_ick",     &gpt7_ick,      CK_243X | CK_242X),
+        CLK(NULL,       "gpt7_fck",     &gpt7_fck,      CK_243X | CK_242X),
+        CLK(NULL,       "gpt8_ick",     &gpt8_ick,      CK_243X | CK_242X),
+        CLK(NULL,       "gpt8_fck",     &gpt8_fck,      CK_243X | CK_242X),
+        CLK(NULL,       "gpt9_ick",     &gpt9_ick,      CK_243X | CK_242X),
+        CLK(NULL,       "gpt9_fck",     &gpt9_fck,      CK_243X | CK_242X),
+        CLK(NULL,       "gpt10_ick",    &gpt10_ick,     CK_243X | CK_242X),
+        CLK(NULL,       "gpt10_fck",    &gpt10_fck,     CK_243X | CK_242X),
+        CLK(NULL,       "gpt11_ick",    &gpt11_ick,     CK_243X | CK_242X),
+        CLK(NULL,       "gpt11_fck",    &gpt11_fck,     CK_243X | CK_242X),
+        CLK(NULL,       "gpt12_ick",    &gpt12_ick,     CK_243X | CK_242X),
+        CLK(NULL,       "gpt12_fck",    &gpt12_fck,     CK_243X | CK_242X),
+        CLK("omap-mcbsp.1", "ick",      &mcbsp1_ick,    CK_243X | CK_242X),
+        CLK("omap-mcbsp.1", "fck",      &mcbsp1_fck,    CK_243X | CK_242X),
+        CLK("omap-mcbsp.2", "ick",      &mcbsp2_ick,    CK_243X | CK_242X),
+        CLK("omap-mcbsp.2", "fck",      &mcbsp2_fck,    CK_243X | CK_242X),
+        CLK("omap-mcbsp.3", "ick",      &mcbsp3_ick,    CK_243X),
+        CLK("omap-mcbsp.3", "fck",      &mcbsp3_fck,    CK_243X),
+        CLK("omap-mcbsp.4", "ick",      &mcbsp4_ick,    CK_243X),
+        CLK("omap-mcbsp.4", "fck",      &mcbsp4_fck,    CK_243X),
+        CLK("omap-mcbsp.5", "ick",      &mcbsp5_ick,    CK_243X),
+        CLK("omap-mcbsp.5", "fck",      &mcbsp5_fck,    CK_243X),
+        CLK("omap2_mcspi.1", "ick",     &mcspi1_ick,    CK_243X | CK_242X),
+        CLK("omap2_mcspi.1", "fck",     &mcspi1_fck,    CK_243X | CK_242X),
+        CLK("omap2_mcspi.2", "ick",     &mcspi2_ick,    CK_243X | CK_242X),
+        CLK("omap2_mcspi.2", "fck",     &mcspi2_fck,    CK_243X | CK_242X),
+        CLK("omap2_mcspi.3", "ick",     &mcspi3_ick,    CK_243X),
+        CLK("omap2_mcspi.3", "fck",     &mcspi3_fck,    CK_243X),
+        CLK(NULL,       "uart1_ick",    &uart1_ick,     CK_243X | CK_242X),
+        CLK(NULL,       "uart1_fck",    &uart1_fck,     CK_243X | CK_242X),
+        CLK(NULL,       "uart2_ick",    &uart2_ick,     CK_243X | CK_242X),
+        CLK(NULL,       "uart2_fck",    &uart2_fck,     CK_243X | CK_242X),
+        CLK(NULL,       "uart3_ick",    &uart3_ick,     CK_243X | CK_242X),
+        CLK(NULL,       "uart3_fck",    &uart3_fck,     CK_243X | CK_242X),
+        CLK(NULL,       "gpios_ick",    &gpios_ick,     CK_243X | CK_242X),
+        CLK(NULL,       "gpios_fck",    &gpios_fck,     CK_243X | CK_242X),
+        CLK("omap_wdt", "ick",          &mpu_wdt_ick,   CK_243X | CK_242X),
+        CLK("omap_wdt", "fck",          &mpu_wdt_fck,   CK_243X | CK_242X),
+        CLK(NULL,       "sync_32k_ick", &sync_32k_ick,  CK_243X | CK_242X),
+        CLK(NULL,       "wdt1_ick",     &wdt1_ick,      CK_243X | CK_242X),
+        CLK(NULL,       "omapctrl_ick", &omapctrl_ick,  CK_243X | CK_242X),
+        CLK(NULL,       "icr_ick",      &icr_ick,       CK_243X),
+        CLK("omap24xxcam", "fck",       &cam_fck,       CK_243X | CK_242X),
+        CLK("omap24xxcam", "ick",       &cam_ick,       CK_243X | CK_242X),
+        CLK(NULL,       "mailboxes_ick", &mailboxes_ick,        CK_243X | CK_242X),
+        CLK(NULL,       "wdt4_ick",     &wdt4_ick,      CK_243X | CK_242X),
+        CLK(NULL,       "wdt4_fck",     &wdt4_fck,      CK_243X | CK_242X),
+        CLK(NULL,       "wdt3_ick",     &wdt3_ick,      CK_242X),
+        CLK(NULL,       "wdt3_fck",     &wdt3_fck,      CK_242X),
+        CLK(NULL,       "mspro_ick",    &mspro_ick,     CK_243X | CK_242X),
+        CLK(NULL,       "mspro_fck",    &mspro_fck,     CK_243X | CK_242X),
+        CLK("mmci-omap.0", "ick",       &mmc_ick,       CK_242X),
+        CLK("mmci-omap.0", "fck",       &mmc_fck,       CK_242X),
+        CLK(NULL,       "fac_ick",      &fac_ick,       CK_243X | CK_242X),
+        CLK(NULL,       "fac_fck",      &fac_fck,       CK_243X | CK_242X),
+        CLK(NULL,       "eac_ick",      &eac_ick,       CK_242X),
+        CLK(NULL,       "eac_fck",      &eac_fck,       CK_242X),
+        CLK("omap_hdq.0", "ick",        &hdq_ick,       CK_243X | CK_242X),
+        CLK("omap_hdq.1", "fck",        &hdq_fck,       CK_243X | CK_242X),
+        CLK("i2c_omap.1", "ick",        &i2c1_ick,      CK_243X | CK_242X),
+        CLK("i2c_omap.1", "fck",        &i2c1_fck,      CK_242X),
+        CLK("i2c_omap.1", "fck",        &i2chs1_fck,    CK_243X),
+        CLK("i2c_omap.2", "ick",        &i2c2_ick,      CK_243X | CK_242X),
+        CLK("i2c_omap.2", "fck",        &i2c2_fck,      CK_242X),
+        CLK("i2c_omap.2", "fck",        &i2chs2_fck,    CK_243X),
+        CLK(NULL,       "gpmc_fck",     &gpmc_fck,      CK_243X | CK_242X),
+        CLK(NULL,       "sdma_fck",     &sdma_fck,      CK_243X | CK_242X),
+        CLK(NULL,       "sdma_ick",     &sdma_ick,      CK_243X | CK_242X),
+        CLK(NULL,       "vlynq_ick",    &vlynq_ick,     CK_242X),
+        CLK(NULL,       "vlynq_fck",    &vlynq_fck,     CK_242X),
+        CLK(NULL,       "sdrc_ick",     &sdrc_ick,      CK_243X),
+        CLK(NULL,       "des_ick",      &des_ick,       CK_243X | CK_242X),
+        CLK(NULL,       "sha_ick",      &sha_ick,       CK_243X | CK_242X),
+        CLK("omap_rng", "ick",          &rng_ick,       CK_243X | CK_242X),
+        CLK(NULL,       "aes_ick",      &aes_ick,       CK_243X | CK_242X),
+        CLK(NULL,       "pka_ick",      &pka_ick,       CK_243X | CK_242X),
+        CLK(NULL,       "usb_fck",      &usb_fck,       CK_243X | CK_242X),
+        CLK("musb_hdrc",        "ick",  &usbhs_ick,     CK_243X),
+        CLK("mmci-omap-hs.0", "ick",    &mmchs1_ick,    CK_243X),
+        CLK("mmci-omap-hs.0", "fck",    &mmchs1_fck,    CK_243X),
+        CLK("mmci-omap-hs.1", "ick",    &mmchs2_ick,    CK_243X),
+        CLK("mmci-omap-hs.1", "fck",    &mmchs2_fck,    CK_243X),
+        CLK(NULL,       "gpio5_ick",    &gpio5_ick,     CK_243X),
+        CLK(NULL,       "gpio5_fck",    &gpio5_fck,     CK_243X),
+        CLK(NULL,       "mdm_intc_ick", &mdm_intc_ick,  CK_243X),
+        CLK("mmci-omap-hs.0", "mmchsdb_fck",    &mmchsdb1_fck,  CK_243X),
+        CLK("mmci-omap-hs.1", "mmchsdb_fck",    &mmchsdb2_fck,  CK_243X),
+};
+
+/*
+ * init code
+ */
+
+int __init omap2_clk_init(void)
+{
+        const struct prcm_config *prcm;
+        struct omap_clk *c;
+        u32 clkrate;
+        u16 cpu_clkflg;
+
+        if (cpu_is_omap242x()) {
+                prcm_clksrc_ctrl = OMAP2420_PRCM_CLKSRC_CTRL;
+                cpu_mask = RATE_IN_242X;
+                cpu_clkflg = CK_242X;
+                rate_table = omap2420_rate_table;
+        } else if (cpu_is_omap2430()) {
+                prcm_clksrc_ctrl = OMAP2430_PRCM_CLKSRC_CTRL;
+                cpu_mask = RATE_IN_243X;
+                cpu_clkflg = CK_243X;
+                rate_table = omap2430_rate_table;
+        }
+
+        clk_init(&omap2_clk_functions);
+
+        for (c = omap24xx_clks; c < omap24xx_clks + ARRAY_SIZE(omap24xx_clks); c++)
+                clk_preinit(c->lk.clk);
+
+        osc_ck.rate = omap2_osc_clk_recalc(&osc_ck);
+        propagate_rate(&osc_ck);
+        sys_ck.rate = omap2_sys_clk_recalc(&sys_ck);
+        propagate_rate(&sys_ck);
+
+        for (c = omap24xx_clks; c < omap24xx_clks + ARRAY_SIZE(omap24xx_clks); c++)
+                if (c->cpu & cpu_clkflg) {
+                        clkdev_add(&c->lk);
+                        clk_register(c->lk.clk);
+                        omap2_init_clk_clkdm(c->lk.clk);
+                }
+
+        /* Check the MPU rate set by bootloader */
+        clkrate = omap2xxx_clk_get_core_rate(&dpll_ck);
+        for (prcm = rate_table; prcm->mpu_speed; prcm++) {
+                if (!(prcm->flags & cpu_mask))
+                        continue;
+                if (prcm->xtal_speed != sys_ck.rate)
+                        continue;
+                if (prcm->dpll_speed <= clkrate)
+                        break;
+        }
+        curr_prcm_set = prcm;
+
+        recalculate_root_clocks();
+
+        printk(KERN_INFO "Clocking rate (Crystal/DPLL/MPU): "
+               "%ld.%01ld/%ld/%ld MHz\n",
+               (sys_ck.rate / 1000000), (sys_ck.rate / 100000) % 10,
+               (dpll_ck.rate / 1000000), (mpu_ck.rate / 1000000)) ;
+
+        /*
+         * Only enable those clocks we will need, let the drivers
+         * enable other clocks as necessary
+         */
+        clk_enable_init_clocks();
+
+        /* Avoid sleeping sleeping during omap2_clk_prepare_for_reboot() */
+        vclk = clk_get(NULL, "virt_prcm_set");
+        sclk = clk_get(NULL, "sys_ck");
+        dclk = clk_get(NULL, "dpll_ck");
+
+        return 0;
+}
 
diff --git a/arch/arm/mach-omap2/clock34xx.c b/arch/arm/mach-omap2/clock34xx.c
index ecbb5cd8eec8..ded32364f32b 100644
--- a/arch/arm/mach-omap2/clock34xx.c
+++ b/arch/arm/mach-omap2/clock34xx.c
@@ -30,314 +30,21 @@
 #include <plat/cpu.h>
 #include <plat/clock.h>
 #include <plat/sram.h>
+#include <plat/sdrc.h>
 #include <asm/div64.h>
 #include <asm/clkdev.h>
 
 #include <plat/sdrc.h>
 #include "clock.h"
+#include "clock34xx.h"
+#include "sdrc.h"
 #include "prm.h"
 #include "prm-regbits-34xx.h"
 #include "cm.h"
 #include "cm-regbits-34xx.h"
 
-static const struct clkops clkops_noncore_dpll_ops;
-
-static void omap3430es2_clk_ssi_find_idlest(struct clk *clk,
-                                            void __iomem **idlest_reg,
-                                            u8 *idlest_bit);
-static void omap3430es2_clk_hsotgusb_find_idlest(struct clk *clk,
-                                            void __iomem **idlest_reg,
-                                            u8 *idlest_bit);
-static void omap3430es2_clk_dss_usbhost_find_idlest(struct clk *clk,
-                                                    void __iomem **idlest_reg,
-                                                    u8 *idlest_bit);
-
-static const struct clkops clkops_omap3430es2_ssi_wait = {
-        .enable         = omap2_dflt_clk_enable,
-        .disable        = omap2_dflt_clk_disable,
-        .find_idlest    = omap3430es2_clk_ssi_find_idlest,
-        .find_companion = omap2_clk_dflt_find_companion,
-};
-
-static const struct clkops clkops_omap3430es2_hsotgusb_wait = {
-        .enable         = omap2_dflt_clk_enable,
-        .disable        = omap2_dflt_clk_disable,
-        .find_idlest    = omap3430es2_clk_hsotgusb_find_idlest,
-        .find_companion = omap2_clk_dflt_find_companion,
-};
-
-static const struct clkops clkops_omap3430es2_dss_usbhost_wait = {
-        .enable         = omap2_dflt_clk_enable,
-        .disable        = omap2_dflt_clk_disable,
-        .find_idlest    = omap3430es2_clk_dss_usbhost_find_idlest,
-        .find_companion = omap2_clk_dflt_find_companion,
-};
-
-#include "clock34xx.h"
-
-struct omap_clk {
-        u32             cpu;
-        struct clk_lookup lk;
-};
-
-#define CLK(dev, con, ck, cp)           \
-        {                               \
-                 .cpu = cp,             \
-                .lk = {                 \
-                        .dev_id = dev,  \
-                        .con_id = con,  \
-                        .clk = ck,      \
-                },                      \
-        }
-
-#define CK_343X         (1 << 0)
-#define CK_3430ES1      (1 << 1)
-#define CK_3430ES2      (1 << 2)
-
-static struct omap_clk omap34xx_clks[] = {
-        CLK(NULL,       "omap_32k_fck", &omap_32k_fck,  CK_343X),
-        CLK(NULL,       "virt_12m_ck",  &virt_12m_ck,   CK_343X),
-        CLK(NULL,       "virt_13m_ck",  &virt_13m_ck,   CK_343X),
-        CLK(NULL,       "virt_16_8m_ck", &virt_16_8m_ck, CK_3430ES2),
-        CLK(NULL,       "virt_19_2m_ck", &virt_19_2m_ck, CK_343X),
-        CLK(NULL,       "virt_26m_ck",  &virt_26m_ck,   CK_343X),
-        CLK(NULL,       "virt_38_4m_ck", &virt_38_4m_ck, CK_343X),
-        CLK(NULL,       "osc_sys_ck",   &osc_sys_ck,    CK_343X),
-        CLK(NULL,       "sys_ck",       &sys_ck,        CK_343X),
-        CLK(NULL,       "sys_altclk",   &sys_altclk,    CK_343X),
-        CLK(NULL,       "mcbsp_clks",   &mcbsp_clks,    CK_343X),
-        CLK(NULL,       "sys_clkout1",  &sys_clkout1,   CK_343X),
-        CLK(NULL,       "dpll1_ck",     &dpll1_ck,      CK_343X),
-        CLK(NULL,       "dpll1_x2_ck",  &dpll1_x2_ck,   CK_343X),
-        CLK(NULL,       "dpll1_x2m2_ck", &dpll1_x2m2_ck, CK_343X),
-        CLK(NULL,       "dpll2_ck",     &dpll2_ck,      CK_343X),
-        CLK(NULL,       "dpll2_m2_ck",  &dpll2_m2_ck,   CK_343X),
-        CLK(NULL,       "dpll3_ck",     &dpll3_ck,      CK_343X),
-        CLK(NULL,       "core_ck",      &core_ck,       CK_343X),
-        CLK(NULL,       "dpll3_x2_ck",  &dpll3_x2_ck,   CK_343X),
-        CLK(NULL,       "dpll3_m2_ck",  &dpll3_m2_ck,   CK_343X),
-        CLK(NULL,       "dpll3_m2x2_ck", &dpll3_m2x2_ck, CK_343X),
-        CLK(NULL,       "dpll3_m3_ck",  &dpll3_m3_ck,   CK_343X),
-        CLK(NULL,       "dpll3_m3x2_ck", &dpll3_m3x2_ck, CK_343X),
-        CLK("etb",      "emu_core_alwon_ck", &emu_core_alwon_ck, CK_343X),
-        CLK(NULL,       "dpll4_ck",     &dpll4_ck,      CK_343X),
-        CLK(NULL,       "dpll4_x2_ck",  &dpll4_x2_ck,   CK_343X),
-        CLK(NULL,       "omap_96m_alwon_fck", &omap_96m_alwon_fck, CK_343X),
-        CLK(NULL,       "omap_96m_fck", &omap_96m_fck,  CK_343X),
-        CLK(NULL,       "cm_96m_fck",   &cm_96m_fck,    CK_343X),
-        CLK(NULL,       "omap_54m_fck", &omap_54m_fck,  CK_343X),
-        CLK(NULL,       "omap_48m_fck", &omap_48m_fck,  CK_343X),
-        CLK(NULL,       "omap_12m_fck", &omap_12m_fck,  CK_343X),
-        CLK(NULL,       "dpll4_m2_ck",  &dpll4_m2_ck,   CK_343X),
-        CLK(NULL,       "dpll4_m2x2_ck", &dpll4_m2x2_ck, CK_343X),
-        CLK(NULL,       "dpll4_m3_ck",  &dpll4_m3_ck,   CK_343X),
-        CLK(NULL,       "dpll4_m3x2_ck", &dpll4_m3x2_ck, CK_343X),
-        CLK(NULL,       "dpll4_m4_ck",  &dpll4_m4_ck,   CK_343X),
-        CLK(NULL,       "dpll4_m4x2_ck", &dpll4_m4x2_ck, CK_343X),
-        CLK(NULL,       "dpll4_m5_ck",  &dpll4_m5_ck,   CK_343X),
-        CLK(NULL,       "dpll4_m5x2_ck", &dpll4_m5x2_ck, CK_343X),
-        CLK(NULL,       "dpll4_m6_ck",  &dpll4_m6_ck,   CK_343X),
-        CLK(NULL,       "dpll4_m6x2_ck", &dpll4_m6x2_ck, CK_343X),
-        CLK("etb",      "emu_per_alwon_ck", &emu_per_alwon_ck, CK_343X),
-        CLK(NULL,       "dpll5_ck",     &dpll5_ck,      CK_3430ES2),
-        CLK(NULL,       "dpll5_m2_ck",  &dpll5_m2_ck,   CK_3430ES2),
-        CLK(NULL,       "clkout2_src_ck", &clkout2_src_ck, CK_343X),
-        CLK(NULL,       "sys_clkout2",  &sys_clkout2,   CK_343X),
-        CLK(NULL,       "corex2_fck",   &corex2_fck,    CK_343X),
-        CLK(NULL,       "dpll1_fck",    &dpll1_fck,     CK_343X),
-        CLK(NULL,       "mpu_ck",       &mpu_ck,        CK_343X),
-        CLK(NULL,       "arm_fck",      &arm_fck,       CK_343X),
-        CLK("etb",      "emu_mpu_alwon_ck", &emu_mpu_alwon_ck, CK_343X),
-        CLK(NULL,       "dpll2_fck",    &dpll2_fck,     CK_343X),
-        CLK(NULL,       "iva2_ck",      &iva2_ck,       CK_343X),
-        CLK(NULL,       "l3_ick",       &l3_ick,        CK_343X),
-        CLK(NULL,       "l4_ick",       &l4_ick,        CK_343X),
-        CLK(NULL,       "rm_ick",       &rm_ick,        CK_343X),
-        CLK(NULL,       "gfx_l3_ck",    &gfx_l3_ck,     CK_3430ES1),
-        CLK(NULL,       "gfx_l3_fck",   &gfx_l3_fck,    CK_3430ES1),
-        CLK(NULL,       "gfx_l3_ick",   &gfx_l3_ick,    CK_3430ES1),
-        CLK(NULL,       "gfx_cg1_ck",   &gfx_cg1_ck,    CK_3430ES1),
-        CLK(NULL,       "gfx_cg2_ck",   &gfx_cg2_ck,    CK_3430ES1),
-        CLK(NULL,       "sgx_fck",      &sgx_fck,       CK_3430ES2),
-        CLK(NULL,       "sgx_ick",      &sgx_ick,       CK_3430ES2),
-        CLK(NULL,       "d2d_26m_fck",  &d2d_26m_fck,   CK_3430ES1),
-        CLK(NULL,       "modem_fck",    &modem_fck,     CK_343X),
-        CLK(NULL,       "sad2d_ick",    &sad2d_ick,     CK_343X),
-        CLK(NULL,       "mad2d_ick",    &mad2d_ick,     CK_343X),
-        CLK(NULL,       "gpt10_fck",    &gpt10_fck,     CK_343X),
-        CLK(NULL,       "gpt11_fck",    &gpt11_fck,     CK_343X),
-        CLK(NULL,       "cpefuse_fck",  &cpefuse_fck,   CK_3430ES2),
-        CLK(NULL,       "ts_fck",       &ts_fck,        CK_3430ES2),
-        CLK(NULL,       "usbtll_fck",   &usbtll_fck,    CK_3430ES2),
-        CLK(NULL,       "core_96m_fck", &core_96m_fck,  CK_343X),
-        CLK("mmci-omap-hs.2",   "fck",  &mmchs3_fck,    CK_3430ES2),
-        CLK("mmci-omap-hs.1",   "fck",  &mmchs2_fck,    CK_343X),
-        CLK(NULL,       "mspro_fck",    &mspro_fck,     CK_343X),
-        CLK("mmci-omap-hs.0",   "fck",  &mmchs1_fck,    CK_343X),
-        CLK("i2c_omap.3", "fck",        &i2c3_fck,      CK_343X),
-        CLK("i2c_omap.2", "fck",        &i2c2_fck,      CK_343X),
-        CLK("i2c_omap.1", "fck",        &i2c1_fck,      CK_343X),
-        CLK("omap-mcbsp.5", "fck",      &mcbsp5_fck,    CK_343X),
-        CLK("omap-mcbsp.1", "fck",      &mcbsp1_fck,    CK_343X),
-        CLK(NULL,       "core_48m_fck", &core_48m_fck,  CK_343X),
-        CLK("omap2_mcspi.4", "fck",     &mcspi4_fck,    CK_343X),
-        CLK("omap2_mcspi.3", "fck",     &mcspi3_fck,    CK_343X),
-        CLK("omap2_mcspi.2", "fck",     &mcspi2_fck,    CK_343X),
-        CLK("omap2_mcspi.1", "fck",     &mcspi1_fck,    CK_343X),
-        CLK(NULL,       "uart2_fck",    &uart2_fck,     CK_343X),
-        CLK(NULL,       "uart1_fck",    &uart1_fck,     CK_343X),
-        CLK(NULL,       "fshostusb_fck", &fshostusb_fck, CK_3430ES1),
-        CLK(NULL,       "core_12m_fck", &core_12m_fck,  CK_343X),
-        CLK("omap_hdq.0", "fck",        &hdq_fck,       CK_343X),
-        CLK(NULL,       "ssi_ssr_fck",  &ssi_ssr_fck_3430es1,   CK_3430ES1),
-        CLK(NULL,       "ssi_ssr_fck",  &ssi_ssr_fck_3430es2,   CK_3430ES2),
-        CLK(NULL,       "ssi_sst_fck",  &ssi_sst_fck_3430es1,   CK_3430ES1),
-        CLK(NULL,       "ssi_sst_fck",  &ssi_sst_fck_3430es2,   CK_3430ES2),
-        CLK(NULL,       "core_l3_ick",  &core_l3_ick,   CK_343X),
-        CLK("musb_hdrc",        "ick",  &hsotgusb_ick_3430es1,  CK_3430ES1),
-        CLK("musb_hdrc",        "ick",  &hsotgusb_ick_3430es2,  CK_3430ES2),
-        CLK(NULL,       "sdrc_ick",     &sdrc_ick,      CK_343X),
-        CLK(NULL,       "gpmc_fck",     &gpmc_fck,      CK_343X),
-        CLK(NULL,       "security_l3_ick", &security_l3_ick, CK_343X),
-        CLK(NULL,       "pka_ick",      &pka_ick,       CK_343X),
-        CLK(NULL,       "core_l4_ick",  &core_l4_ick,   CK_343X),
-        CLK(NULL,       "usbtll_ick",   &usbtll_ick,    CK_3430ES2),
-        CLK("mmci-omap-hs.2",   "ick",  &mmchs3_ick,    CK_3430ES2),
-        CLK(NULL,       "icr_ick",      &icr_ick,       CK_343X),
-        CLK(NULL,       "aes2_ick",     &aes2_ick,      CK_343X),
-        CLK(NULL,       "sha12_ick",    &sha12_ick,     CK_343X),
-        CLK(NULL,       "des2_ick",     &des2_ick,      CK_343X),
-        CLK("mmci-omap-hs.1",   "ick",  &mmchs2_ick,    CK_343X),
-        CLK("mmci-omap-hs.0",   "ick",  &mmchs1_ick,    CK_343X),
-        CLK(NULL,       "mspro_ick",    &mspro_ick,     CK_343X),
-        CLK("omap_hdq.0", "ick",        &hdq_ick,       CK_343X),
-        CLK("omap2_mcspi.4", "ick",     &mcspi4_ick,    CK_343X),
-        CLK("omap2_mcspi.3", "ick",     &mcspi3_ick,    CK_343X),
-        CLK("omap2_mcspi.2", "ick",     &mcspi2_ick,    CK_343X),
-        CLK("omap2_mcspi.1", "ick",     &mcspi1_ick,    CK_343X),
-        CLK("i2c_omap.3", "ick",        &i2c3_ick,      CK_343X),
-        CLK("i2c_omap.2", "ick",        &i2c2_ick,      CK_343X),
-        CLK("i2c_omap.1", "ick",        &i2c1_ick,      CK_343X),
-        CLK(NULL,       "uart2_ick",    &uart2_ick,     CK_343X),
-        CLK(NULL,       "uart1_ick",    &uart1_ick,     CK_343X),
-        CLK(NULL,       "gpt11_ick",    &gpt11_ick,     CK_343X),
-        CLK(NULL,       "gpt10_ick",    &gpt10_ick,     CK_343X),
-        CLK("omap-mcbsp.5", "ick",      &mcbsp5_ick,    CK_343X),
-        CLK("omap-mcbsp.1", "ick",      &mcbsp1_ick,    CK_343X),
-        CLK(NULL,       "fac_ick",      &fac_ick,       CK_3430ES1),
-        CLK(NULL,       "mailboxes_ick", &mailboxes_ick, CK_343X),
-        CLK(NULL,       "omapctrl_ick", &omapctrl_ick,  CK_343X),
-        CLK(NULL,       "ssi_l4_ick",   &ssi_l4_ick,    CK_343X),
-        CLK(NULL,       "ssi_ick",      &ssi_ick_3430es1,       CK_3430ES1),
-        CLK(NULL,       "ssi_ick",      &ssi_ick_3430es2,       CK_3430ES2),
-        CLK(NULL,       "usb_l4_ick",   &usb_l4_ick,    CK_3430ES1),
-        CLK(NULL,       "security_l4_ick2", &security_l4_ick2, CK_343X),
-        CLK(NULL,       "aes1_ick",     &aes1_ick,      CK_343X),
-        CLK("omap_rng", "ick",          &rng_ick,       CK_343X),
-        CLK(NULL,       "sha11_ick",    &sha11_ick,     CK_343X),
-        CLK(NULL,       "des1_ick",     &des1_ick,      CK_343X),
-        CLK("omapdss",  "dss1_fck",     &dss1_alwon_fck_3430es1, CK_3430ES1),
-        CLK("omapdss",  "dss1_fck",     &dss1_alwon_fck_3430es2, CK_3430ES2),
-        CLK("omapdss",  "tv_fck",       &dss_tv_fck,    CK_343X),
-        CLK("omapdss",  "video_fck",    &dss_96m_fck,   CK_343X),
-        CLK("omapdss",  "dss2_fck",     &dss2_alwon_fck, CK_343X),
-        CLK("omapdss",  "ick",          &dss_ick_3430es1,       CK_3430ES1),
-        CLK("omapdss",  "ick",          &dss_ick_3430es2,       CK_3430ES2),
-        CLK(NULL,       "cam_mclk",     &cam_mclk,      CK_343X),
-        CLK(NULL,       "cam_ick",      &cam_ick,       CK_343X),
-        CLK(NULL,       "csi2_96m_fck", &csi2_96m_fck,  CK_343X),
-        CLK(NULL,       "usbhost_120m_fck", &usbhost_120m_fck, CK_3430ES2),
-        CLK(NULL,       "usbhost_48m_fck", &usbhost_48m_fck, CK_3430ES2),
-        CLK(NULL,       "usbhost_ick",  &usbhost_ick,   CK_3430ES2),
-        CLK(NULL,       "usim_fck",     &usim_fck,      CK_3430ES2),
-        CLK(NULL,       "gpt1_fck",     &gpt1_fck,      CK_343X),
-        CLK(NULL,       "wkup_32k_fck", &wkup_32k_fck,  CK_343X),
-        CLK(NULL,       "gpio1_dbck",   &gpio1_dbck,    CK_343X),
-        CLK("omap_wdt", "fck",          &wdt2_fck,      CK_343X),
-        CLK(NULL,       "wkup_l4_ick",  &wkup_l4_ick,   CK_343X),
-        CLK(NULL,       "usim_ick",     &usim_ick,      CK_3430ES2),
-        CLK("omap_wdt", "ick",          &wdt2_ick,      CK_343X),
-        CLK(NULL,       "wdt1_ick",     &wdt1_ick,      CK_343X),
-        CLK(NULL,       "gpio1_ick",    &gpio1_ick,     CK_343X),
-        CLK(NULL,       "omap_32ksync_ick", &omap_32ksync_ick, CK_343X),
-        CLK(NULL,       "gpt12_ick",    &gpt12_ick,     CK_343X),
-        CLK(NULL,       "gpt1_ick",     &gpt1_ick,      CK_343X),
-        CLK(NULL,       "per_96m_fck",  &per_96m_fck,   CK_343X),
-        CLK(NULL,       "per_48m_fck",  &per_48m_fck,   CK_343X),
-        CLK(NULL,       "uart3_fck",    &uart3_fck,     CK_343X),
-        CLK(NULL,       "gpt2_fck",     &gpt2_fck,      CK_343X),
-        CLK(NULL,       "gpt3_fck",     &gpt3_fck,      CK_343X),
-        CLK(NULL,       "gpt4_fck",     &gpt4_fck,      CK_343X),
-        CLK(NULL,       "gpt5_fck",     &gpt5_fck,      CK_343X),
-        CLK(NULL,       "gpt6_fck",     &gpt6_fck,      CK_343X),
-        CLK(NULL,       "gpt7_fck",     &gpt7_fck,      CK_343X),
-        CLK(NULL,       "gpt8_fck",     &gpt8_fck,      CK_343X),
-        CLK(NULL,       "gpt9_fck",     &gpt9_fck,      CK_343X),
-        CLK(NULL,       "per_32k_alwon_fck", &per_32k_alwon_fck, CK_343X),
-        CLK(NULL,       "gpio6_dbck",   &gpio6_dbck,    CK_343X),
-        CLK(NULL,       "gpio5_dbck",   &gpio5_dbck,    CK_343X),
-        CLK(NULL,       "gpio4_dbck",   &gpio4_dbck,    CK_343X),
-        CLK(NULL,       "gpio3_dbck",   &gpio3_dbck,    CK_343X),
-        CLK(NULL,       "gpio2_dbck",   &gpio2_dbck,    CK_343X),
-        CLK(NULL,       "wdt3_fck",     &wdt3_fck,      CK_343X),
-        CLK(NULL,       "per_l4_ick",   &per_l4_ick,    CK_343X),
-        CLK(NULL,       "gpio6_ick",    &gpio6_ick,     CK_343X),
-        CLK(NULL,       "gpio5_ick",    &gpio5_ick,     CK_343X),
-        CLK(NULL,       "gpio4_ick",    &gpio4_ick,     CK_343X),
-        CLK(NULL,       "gpio3_ick",    &gpio3_ick,     CK_343X),
-        CLK(NULL,       "gpio2_ick",    &gpio2_ick,     CK_343X),
-        CLK(NULL,       "wdt3_ick",     &wdt3_ick,      CK_343X),
-        CLK(NULL,       "uart3_ick",    &uart3_ick,     CK_343X),
-        CLK(NULL,       "gpt9_ick",     &gpt9_ick,      CK_343X),
-        CLK(NULL,       "gpt8_ick",     &gpt8_ick,      CK_343X),
-        CLK(NULL,       "gpt7_ick",     &gpt7_ick,      CK_343X),
-        CLK(NULL,       "gpt6_ick",     &gpt6_ick,      CK_343X),
-        CLK(NULL,       "gpt5_ick",     &gpt5_ick,      CK_343X),
-        CLK(NULL,       "gpt4_ick",     &gpt4_ick,      CK_343X),
-        CLK(NULL,       "gpt3_ick",     &gpt3_ick,      CK_343X),
-        CLK(NULL,       "gpt2_ick",     &gpt2_ick,      CK_343X),
-        CLK("omap-mcbsp.2", "ick",      &mcbsp2_ick,    CK_343X),
-        CLK("omap-mcbsp.3", "ick",      &mcbsp3_ick,    CK_343X),
-        CLK("omap-mcbsp.4", "ick",      &mcbsp4_ick,    CK_343X),
-        CLK("omap-mcbsp.2", "fck",      &mcbsp2_fck,    CK_343X),
-        CLK("omap-mcbsp.3", "fck",      &mcbsp3_fck,    CK_343X),
-        CLK("omap-mcbsp.4", "fck",      &mcbsp4_fck,    CK_343X),
-        CLK("etb",      "emu_src_ck",   &emu_src_ck,    CK_343X),
-        CLK(NULL,       "pclk_fck",     &pclk_fck,      CK_343X),
-        CLK(NULL,       "pclkx2_fck",   &pclkx2_fck,    CK_343X),
-        CLK(NULL,       "atclk_fck",    &atclk_fck,     CK_343X),
-        CLK(NULL,       "traceclk_src_fck", &traceclk_src_fck, CK_343X),
-        CLK(NULL,       "traceclk_fck", &traceclk_fck,  CK_343X),
-        CLK(NULL,       "sr1_fck",      &sr1_fck,       CK_343X),
-        CLK(NULL,       "sr2_fck",      &sr2_fck,       CK_343X),
-        CLK(NULL,       "sr_l4_ick",    &sr_l4_ick,     CK_343X),
-        CLK(NULL,       "secure_32k_fck", &secure_32k_fck, CK_343X),
-        CLK(NULL,       "gpt12_fck",    &gpt12_fck,     CK_343X),
-        CLK(NULL,       "wdt1_fck",     &wdt1_fck,      CK_343X),
-};
-
-/* CM_AUTOIDLE_PLL*.AUTO_* bit values */
-#define DPLL_AUTOIDLE_DISABLE                   0x0
-#define DPLL_AUTOIDLE_LOW_POWER_STOP            0x1
-
-#define MAX_DPLL_WAIT_TRIES             1000000
-
-#define MIN_SDRC_DLL_LOCK_FREQ          83000000
-
 #define CYCLES_PER_MHZ                  1000000
 
-/* Scale factor for fixed-point arith in omap3_core_dpll_m2_set_rate() */
-#define SDRC_MPURATE_SCALE              8
-
-/* 2^SDRC_MPURATE_BASE_SHIFT: MPU MHz that SDRC_MPURATE_LOOPS is defined for */
-#define SDRC_MPURATE_BASE_SHIFT         9
-
-/*
- * SDRC_MPURATE_LOOPS: Number of MPU loops to execute at
- * 2^MPURATE_BASE_SHIFT MHz for SDRC to stabilize
- */
-#define SDRC_MPURATE_LOOPS              96
-
 /*
  * DPLL5_FREQ_FOR_USBHOST: USBHOST and USBTLL are the only clocks
  * that are sourced by DPLL5, and both of these require this clock
@@ -345,6 +52,9 @@ static struct omap_clk omap34xx_clks[] = {
  */
 #define DPLL5_FREQ_FOR_USBHOST          120000000
 
+/* needed by omap3_core_dpll_m2_set_rate() */
+struct clk *sdrc_ick_p, *arm_fck_p;
+
 /**
  * omap3430es2_clk_ssi_find_idlest - return CM_IDLEST info for SSI
  * @clk: struct clk * being enabled
@@ -366,6 +76,13 @@ static void omap3430es2_clk_ssi_find_idlest(struct clk *clk,
         *idlest_bit = OMAP3430ES2_ST_SSI_IDLE_SHIFT;
 }
 
+const struct clkops clkops_omap3430es2_ssi_wait = {
+        .enable         = omap2_dflt_clk_enable,
+        .disable        = omap2_dflt_clk_disable,
+        .find_idlest    = omap3430es2_clk_ssi_find_idlest,
+        .find_companion = omap2_clk_dflt_find_companion,
+};
+
 /**
  * omap3430es2_clk_dss_usbhost_find_idlest - CM_IDLEST info for DSS, USBHOST
  * @clk: struct clk * being enabled
@@ -391,6 +108,13 @@ static void omap3430es2_clk_dss_usbhost_find_idlest(struct clk *clk,
         *idlest_bit = OMAP3430ES2_ST_DSS_IDLE_SHIFT;
 }
 
+const struct clkops clkops_omap3430es2_dss_usbhost_wait = {
+        .enable         = omap2_dflt_clk_enable,
+        .disable        = omap2_dflt_clk_disable,
+        .find_idlest    = omap3430es2_clk_dss_usbhost_find_idlest,
+        .find_companion = omap2_clk_dflt_find_companion,
+};
+
 /**
  * omap3430es2_clk_hsotgusb_find_idlest - return CM_IDLEST info for HSOTGUSB
  * @clk: struct clk * being enabled
@@ -412,395 +136,19 @@ static void omap3430es2_clk_hsotgusb_find_idlest(struct clk *clk,
         *idlest_bit = OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT;
 }
 
-/**
- * omap3_dpll_recalc - recalculate DPLL rate
- * @clk: DPLL struct clk
- *
- * Recalculate and propagate the DPLL rate.
- */
-static unsigned long omap3_dpll_recalc(struct clk *clk)
-{
-        return omap2_get_dpll_rate(clk);
-}
-
-/* _omap3_dpll_write_clken - write clken_bits arg to a DPLL's enable bits */
-static void _omap3_dpll_write_clken(struct clk *clk, u8 clken_bits)
-{
-        const struct dpll_data *dd;
-        u32 v;
-
-        dd = clk->dpll_data;
-
-        v = __raw_readl(dd->control_reg);
-        v &= ~dd->enable_mask;
-        v |= clken_bits << __ffs(dd->enable_mask);
-        __raw_writel(v, dd->control_reg);
-}
-
-/* _omap3_wait_dpll_status: wait for a DPLL to enter a specific state */
-static int _omap3_wait_dpll_status(struct clk *clk, u8 state)
-{
-        const struct dpll_data *dd;
-        int i = 0;
-        int ret = -EINVAL;
-
-        dd = clk->dpll_data;
-
-        state <<= __ffs(dd->idlest_mask);
-
-        while (((__raw_readl(dd->idlest_reg) & dd->idlest_mask) != state) &&
-               i < MAX_DPLL_WAIT_TRIES) {
-                i++;
-                udelay(1);
-        }
-
-        if (i == MAX_DPLL_WAIT_TRIES) {
-                printk(KERN_ERR "clock: %s failed transition to '%s'\n",
-                       clk->name, (state) ? "locked" : "bypassed");
-        } else {
-                pr_debug("clock: %s transition to '%s' in %d loops\n",
-                         clk->name, (state) ? "locked" : "bypassed", i);
-
-                ret = 0;
-        }
-
-        return ret;
-}
-
-/* From 3430 TRM ES2 4.7.6.2 */
-static u16 _omap3_dpll_compute_freqsel(struct clk *clk, u8 n)
-{
-        unsigned long fint;
-        u16 f = 0;
-
-        fint = clk->dpll_data->clk_ref->rate / n;
-
-        pr_debug("clock: fint is %lu\n", fint);
-
-        if (fint >= 750000 && fint <= 1000000)
-                f = 0x3;
-        else if (fint > 1000000 && fint <= 1250000)
-                f = 0x4;
-        else if (fint > 1250000 && fint <= 1500000)
-                f = 0x5;
-        else if (fint > 1500000 && fint <= 1750000)
-                f = 0x6;
-        else if (fint > 1750000 && fint <= 2100000)
-                f = 0x7;
-        else if (fint > 7500000 && fint <= 10000000)
-                f = 0xB;
-        else if (fint > 10000000 && fint <= 12500000)
-                f = 0xC;
-        else if (fint > 12500000 && fint <= 15000000)
-                f = 0xD;
-        else if (fint > 15000000 && fint <= 17500000)
-                f = 0xE;
-        else if (fint > 17500000 && fint <= 21000000)
-                f = 0xF;
-        else
-                pr_debug("clock: unknown freqsel setting for %d\n", n);
-
-        return f;
-}
-
-/* Non-CORE DPLL (e.g., DPLLs that do not control SDRC) clock functions */
-
-/*
- * _omap3_noncore_dpll_lock - instruct a DPLL to lock and wait for readiness
- * @clk: pointer to a DPLL struct clk
- *
- * Instructs a non-CORE DPLL to lock.  Waits for the DPLL to report
- * readiness before returning.  Will save and restore the DPLL's
- * autoidle state across the enable, per the CDP code.  If the DPLL
- * locked successfully, return 0; if the DPLL did not lock in the time
- * allotted, or DPLL3 was passed in, return -EINVAL.
- */
-static int _omap3_noncore_dpll_lock(struct clk *clk)
-{
-        u8 ai;
-        int r;
-
-        if (clk == &dpll3_ck)
-                return -EINVAL;
-
-        pr_debug("clock: locking DPLL %s\n", clk->name);
-
-        ai = omap3_dpll_autoidle_read(clk);
-
-        omap3_dpll_deny_idle(clk);
-
-        _omap3_dpll_write_clken(clk, DPLL_LOCKED);
-
-        r = _omap3_wait_dpll_status(clk, 1);
-
-        if (ai)
-                omap3_dpll_allow_idle(clk);
-
-        return r;
-}
-
-/*
- * _omap3_noncore_dpll_bypass - instruct a DPLL to bypass and wait for readiness
- * @clk: pointer to a DPLL struct clk
- *
- * Instructs a non-CORE DPLL to enter low-power bypass mode.  In
- * bypass mode, the DPLL's rate is set equal to its parent clock's
- * rate.  Waits for the DPLL to report readiness before returning.
- * Will save and restore the DPLL's autoidle state across the enable,
- * per the CDP code.  If the DPLL entered bypass mode successfully,
- * return 0; if the DPLL did not enter bypass in the time allotted, or
- * DPLL3 was passed in, or the DPLL does not support low-power bypass,
- * return -EINVAL.
- */
-static int _omap3_noncore_dpll_bypass(struct clk *clk)
-{
-        int r;
-        u8 ai;
-
-        if (clk == &dpll3_ck)
-                return -EINVAL;
-
-        if (!(clk->dpll_data->modes & (1 << DPLL_LOW_POWER_BYPASS)))
-                return -EINVAL;
-
-        pr_debug("clock: configuring DPLL %s for low-power bypass\n",
-                 clk->name);
-
-        ai = omap3_dpll_autoidle_read(clk);
-
-        _omap3_dpll_write_clken(clk, DPLL_LOW_POWER_BYPASS);
-
-        r = _omap3_wait_dpll_status(clk, 0);
-
-        if (ai)
-                omap3_dpll_allow_idle(clk);
-        else
-                omap3_dpll_deny_idle(clk);
-
-        return r;
-}
-
-/*
- * _omap3_noncore_dpll_stop - instruct a DPLL to stop
- * @clk: pointer to a DPLL struct clk
- *
- * Instructs a non-CORE DPLL to enter low-power stop. Will save and
- * restore the DPLL's autoidle state across the stop, per the CDP
- * code.  If DPLL3 was passed in, or the DPLL does not support
- * low-power stop, return -EINVAL; otherwise, return 0.
- */
-static int _omap3_noncore_dpll_stop(struct clk *clk)
-{
-        u8 ai;
-
-        if (clk == &dpll3_ck)
-                return -EINVAL;
-
-        if (!(clk->dpll_data->modes & (1 << DPLL_LOW_POWER_STOP)))
-                return -EINVAL;
-
-        pr_debug("clock: stopping DPLL %s\n", clk->name);
-
-        ai = omap3_dpll_autoidle_read(clk);
-
-        _omap3_dpll_write_clken(clk, DPLL_LOW_POWER_STOP);
-
-        if (ai)
-                omap3_dpll_allow_idle(clk);
-        else
-                omap3_dpll_deny_idle(clk);
-
-        return 0;
-}
-
-/**
- * omap3_noncore_dpll_enable - instruct a DPLL to enter bypass or lock mode
- * @clk: pointer to a DPLL struct clk
- *
- * Instructs a non-CORE DPLL to enable, e.g., to enter bypass or lock.
- * The choice of modes depends on the DPLL's programmed rate: if it is
- * the same as the DPLL's parent clock, it will enter bypass;
- * otherwise, it will enter lock.  This code will wait for the DPLL to
- * indicate readiness before returning, unless the DPLL takes too long
- * to enter the target state.  Intended to be used as the struct clk's
- * enable function.  If DPLL3 was passed in, or the DPLL does not
- * support low-power stop, or if the DPLL took too long to enter
- * bypass or lock, return -EINVAL; otherwise, return 0.
- */
-static int omap3_noncore_dpll_enable(struct clk *clk)
-{
-        int r;
-        struct dpll_data *dd;
-
-        if (clk == &dpll3_ck)
-                return -EINVAL;
-
-        dd = clk->dpll_data;
-        if (!dd)
-                return -EINVAL;
-
-        if (clk->rate == dd->clk_bypass->rate) {
-                WARN_ON(clk->parent != dd->clk_bypass);
-                r = _omap3_noncore_dpll_bypass(clk);
-        } else {
-                WARN_ON(clk->parent != dd->clk_ref);
-                r = _omap3_noncore_dpll_lock(clk);
-        }
-        /* FIXME: this is dubious - if clk->rate has changed, what about propagating? */
-        if (!r)
-                clk->rate = omap2_get_dpll_rate(clk);
-
-        return r;
-}
-
-/**
- * omap3_noncore_dpll_enable - instruct a DPLL to enter bypass or lock mode
- * @clk: pointer to a DPLL struct clk
- *
- * Instructs a non-CORE DPLL to enable, e.g., to enter bypass or lock.
- * The choice of modes depends on the DPLL's programmed rate: if it is
- * the same as the DPLL's parent clock, it will enter bypass;
- * otherwise, it will enter lock.  This code will wait for the DPLL to
- * indicate readiness before returning, unless the DPLL takes too long
- * to enter the target state.  Intended to be used as the struct clk's
- * enable function.  If DPLL3 was passed in, or the DPLL does not
- * support low-power stop, or if the DPLL took too long to enter
- * bypass or lock, return -EINVAL; otherwise, return 0.
- */
-static void omap3_noncore_dpll_disable(struct clk *clk)
-{
-        if (clk == &dpll3_ck)
-                return;
-
-        _omap3_noncore_dpll_stop(clk);
-}
-
-
-/* Non-CORE DPLL rate set code */
-
-/*
- * omap3_noncore_dpll_program - set non-core DPLL M,N values directly
- * @clk: struct clk * of DPLL to set
- * @m: DPLL multiplier to set
- * @n: DPLL divider to set
- * @freqsel: FREQSEL value to set
- *
- * Program the DPLL with the supplied M, N values, and wait for the DPLL to
- * lock..  Returns -EINVAL upon error, or 0 upon success.
- */
-static int omap3_noncore_dpll_program(struct clk *clk, u16 m, u8 n, u16 freqsel)
-{
-        struct dpll_data *dd = clk->dpll_data;
-        u32 v;
-
-        /* 3430 ES2 TRM: 4.7.6.9 DPLL Programming Sequence */
-        _omap3_noncore_dpll_bypass(clk);
-
-        /* Set jitter correction */
-        v = __raw_readl(dd->control_reg);
-        v &= ~dd->freqsel_mask;
-        v |= freqsel << __ffs(dd->freqsel_mask);
-        __raw_writel(v, dd->control_reg);
-
-        /* Set DPLL multiplier, divider */
-        v = __raw_readl(dd->mult_div1_reg);
-        v &= ~(dd->mult_mask | dd->div1_mask);
-        v |= m << __ffs(dd->mult_mask);
-        v |= (n - 1) << __ffs(dd->div1_mask);
-        __raw_writel(v, dd->mult_div1_reg);
-
-        /* We let the clock framework set the other output dividers later */
-
-        /* REVISIT: Set ramp-up delay? */
-
-        _omap3_noncore_dpll_lock(clk);
-
-        return 0;
-}
-
-/**
- * omap3_noncore_dpll_set_rate - set non-core DPLL rate
- * @clk: struct clk * of DPLL to set
- * @rate: rounded target rate
- *
- * Set the DPLL CLKOUT to the target rate.  If the DPLL can enter
- * low-power bypass, and the target rate is the bypass source clock
- * rate, then configure the DPLL for bypass.  Otherwise, round the
- * target rate if it hasn't been done already, then program and lock
- * the DPLL.  Returns -EINVAL upon error, or 0 upon success.
- */
-static int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate)
-{
-        struct clk *new_parent = NULL;
-        u16 freqsel;
-        struct dpll_data *dd;
-        int ret;
-
-        if (!clk || !rate)
-                return -EINVAL;
-
-        dd = clk->dpll_data;
-        if (!dd)
-                return -EINVAL;
-
-        if (rate == omap2_get_dpll_rate(clk))
-                return 0;
-
-        /*
-         * Ensure both the bypass and ref clocks are enabled prior to
-         * doing anything; we need the bypass clock running to reprogram
-         * the DPLL.
-         */
-        omap2_clk_enable(dd->clk_bypass);
-        omap2_clk_enable(dd->clk_ref);
-
-        if (dd->clk_bypass->rate == rate &&
-            (clk->dpll_data->modes & (1 << DPLL_LOW_POWER_BYPASS))) {
-                pr_debug("clock: %s: set rate: entering bypass.\n", clk->name);
-
-                ret = _omap3_noncore_dpll_bypass(clk);
-                if (!ret)
-                        new_parent = dd->clk_bypass;
-        } else {
-                if (dd->last_rounded_rate != rate)
-                        omap2_dpll_round_rate(clk, rate);
-
-                if (dd->last_rounded_rate == 0)
-                        return -EINVAL;
-
-                freqsel = _omap3_dpll_compute_freqsel(clk, dd->last_rounded_n);
-                if (!freqsel)
-                        WARN_ON(1);
-
-                pr_debug("clock: %s: set rate: locking rate to %lu.\n",
-                         clk->name, rate);
-
-                ret = omap3_noncore_dpll_program(clk, dd->last_rounded_m,
-                                                 dd->last_rounded_n, freqsel);
-                if (!ret)
-                        new_parent = dd->clk_ref;
-        }
-        if (!ret) {
-                /*
-                 * Switch the parent clock in the heirarchy, and make sure
-                 * that the new parent's usecount is correct.  Note: we
-                 * enable the new parent before disabling the old to avoid
-                 * any unnecessary hardware disable->enable transitions.
-                 */
-                if (clk->usecount) {
-                        omap2_clk_enable(new_parent);
-                        omap2_clk_disable(clk->parent);
-                }
-                clk_reparent(clk, new_parent);
-                clk->rate = rate;
-        }
-        omap2_clk_disable(dd->clk_ref);
-        omap2_clk_disable(dd->clk_bypass);
+const struct clkops clkops_omap3430es2_hsotgusb_wait = {
+        .enable         = omap2_dflt_clk_enable,
+        .disable        = omap2_dflt_clk_disable,
+        .find_idlest    = omap3430es2_clk_hsotgusb_find_idlest,
+        .find_companion = omap2_clk_dflt_find_companion,
+};
 
-        return 0;
-}
+const struct clkops clkops_noncore_dpll_ops = {
+        .enable         = omap3_noncore_dpll_enable,
+        .disable        = omap3_noncore_dpll_disable,
+};
 
-static int omap3_dpll4_set_rate(struct clk *clk, unsigned long rate)
+int omap3_dpll4_set_rate(struct clk *clk, unsigned long rate)
 {
         /*
          * According to the 12-5 CDP code from TI, "Limitation 2.5"
@@ -831,12 +179,12 @@ static int omap3_dpll4_set_rate(struct clk *clk, unsigned long rate)
  * Program the DPLL M2 divider with the rounded target rate.  Returns
  * -EINVAL upon error, or 0 upon success.
  */
-static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
+int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
 {
         u32 new_div = 0;
         u32 unlock_dll = 0;
         u32 c;
-        unsigned long validrate, sdrcrate, mpurate;
+        unsigned long validrate, sdrcrate, _mpurate;
         struct omap_sdrc_params *sdrc_cs0;
         struct omap_sdrc_params *sdrc_cs1;
         int ret;
@@ -844,14 +192,11 @@ static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
         if (!clk || !rate)
                 return -EINVAL;
 
-        if (clk != &dpll3_m2_ck)
-                return -EINVAL;
-
         validrate = omap2_clksel_round_rate_div(clk, rate, &new_div);
         if (validrate != rate)
                 return -EINVAL;
 
-        sdrcrate = sdrc_ick.rate;
+        sdrcrate = sdrc_ick_p->rate;
         if (rate > clk->rate)
                 sdrcrate <<= ((rate / clk->rate) >> 1);
         else
@@ -869,8 +214,8 @@ static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
         /*
          * XXX This only needs to be done when the CPU frequency changes
          */
-        mpurate = arm_fck.rate / CYCLES_PER_MHZ;
-        c = (mpurate << SDRC_MPURATE_SCALE) >> SDRC_MPURATE_BASE_SHIFT;
+        _mpurate = arm_fck_p->rate / CYCLES_PER_MHZ;
+        c = (_mpurate << SDRC_MPURATE_SCALE) >> SDRC_MPURATE_BASE_SHIFT;
         c += 1;  /* for safety */
         c *= SDRC_MPURATE_LOOPS;
         c >>= SDRC_MPURATE_SCALE;
@@ -906,129 +251,6 @@ static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
         return 0;
 }
 
-
-static const struct clkops clkops_noncore_dpll_ops = {
-        .enable         = &omap3_noncore_dpll_enable,
-        .disable        = &omap3_noncore_dpll_disable,
-};
-
-/* DPLL autoidle read/set code */
-
-
-/**
- * omap3_dpll_autoidle_read - read a DPLL's autoidle bits
- * @clk: struct clk * of the DPLL to read
- *
- * Return the DPLL's autoidle bits, shifted down to bit 0.  Returns
- * -EINVAL if passed a null pointer or if the struct clk does not
- * appear to refer to a DPLL.
- */
-static u32 omap3_dpll_autoidle_read(struct clk *clk)
-{
-        const struct dpll_data *dd;
-        u32 v;
-
-        if (!clk || !clk->dpll_data)
-                return -EINVAL;
-
-        dd = clk->dpll_data;
-
-        v = __raw_readl(dd->autoidle_reg);
-        v &= dd->autoidle_mask;
-        v >>= __ffs(dd->autoidle_mask);
-
-        return v;
-}
-
-/**
- * omap3_dpll_allow_idle - enable DPLL autoidle bits
- * @clk: struct clk * of the DPLL to operate on
- *
- * Enable DPLL automatic idle control.  This automatic idle mode
- * switching takes effect only when the DPLL is locked, at least on
- * OMAP3430.  The DPLL will enter low-power stop when its downstream
- * clocks are gated.  No return value.
- */
-static void omap3_dpll_allow_idle(struct clk *clk)
-{
-        const struct dpll_data *dd;
-        u32 v;
-
-        if (!clk || !clk->dpll_data)
-                return;
-
-        dd = clk->dpll_data;
-
-        /*
-         * REVISIT: CORE DPLL can optionally enter low-power bypass
-         * by writing 0x5 instead of 0x1.  Add some mechanism to
-         * optionally enter this mode.
-         */
-        v = __raw_readl(dd->autoidle_reg);
-        v &= ~dd->autoidle_mask;
-        v |= DPLL_AUTOIDLE_LOW_POWER_STOP << __ffs(dd->autoidle_mask);
-        __raw_writel(v, dd->autoidle_reg);
-}
-
-/**
- * omap3_dpll_deny_idle - prevent DPLL from automatically idling
- * @clk: struct clk * of the DPLL to operate on
- *
- * Disable DPLL automatic idle control.  No return value.
- */
-static void omap3_dpll_deny_idle(struct clk *clk)
-{
-        const struct dpll_data *dd;
-        u32 v;
-
-        if (!clk || !clk->dpll_data)
-                return;
-
-        dd = clk->dpll_data;
-
-        v = __raw_readl(dd->autoidle_reg);
-        v &= ~dd->autoidle_mask;
-        v |= DPLL_AUTOIDLE_DISABLE << __ffs(dd->autoidle_mask);
-        __raw_writel(v, dd->autoidle_reg);
-}
-
-/* Clock control for DPLL outputs */
-
-/**
- * omap3_clkoutx2_recalc - recalculate DPLL X2 output virtual clock rate
- * @clk: DPLL output struct clk
- *
- * Using parent clock DPLL data, look up DPLL state.  If locked, set our
- * rate to the dpll_clk * 2; otherwise, just use dpll_clk.
- */
-static unsigned long omap3_clkoutx2_recalc(struct clk *clk)
-{
-        const struct dpll_data *dd;
-        unsigned long rate;
-        u32 v;
-        struct clk *pclk;
-
-        /* Walk up the parents of clk, looking for a DPLL */
-        pclk = clk->parent;
-        while (pclk && !pclk->dpll_data)
-                pclk = pclk->parent;
-
-        /* clk does not have a DPLL as a parent? */
-        WARN_ON(!pclk);
-
-        dd = pclk->dpll_data;
-
-        WARN_ON(!dd->enable_mask);
-
-        v = __raw_readl(dd->control_reg) & dd->enable_mask;
-        v >>= __ffs(dd->enable_mask);
-        if (v != OMAP3XXX_EN_DPLL_LOCKED)
-                rate = clk->parent->rate;
-        else
-                rate = clk->parent->rate * 2;
-        return rate;
-}
-
 /* Common clock code */
 
 /*
@@ -1037,7 +259,7 @@ static unsigned long omap3_clkoutx2_recalc(struct clk *clk)
  */
 #if defined(CONFIG_ARCH_OMAP3)
 
-static struct clk_functions omap2_clk_functions = {
+struct clk_functions omap2_clk_functions = {
         .clk_enable             = omap2_clk_enable,
         .clk_disable            = omap2_clk_disable,
         .clk_round_rate         = omap2_clk_round_rate,
@@ -1063,7 +285,7 @@ void omap2_clk_prepare_for_reboot(void)
 #endif
 }
 
-static void omap3_clk_lock_dpll5(void)
+void omap3_clk_lock_dpll5(void)
 {
         struct clk *dpll5_clk;
         struct clk *dpll5_m2_clk;
@@ -1093,19 +315,32 @@ static void omap3_clk_lock_dpll5(void)
  */
 static int __init omap2_clk_arch_init(void)
 {
+        struct clk *osc_sys_ck, *dpll1_ck, *arm_fck, *core_ck;
+        unsigned long osc_sys_rate;
+
         if (!mpurate)
                 return -EINVAL;
 
+        /* XXX test these for success */
+        dpll1_ck = clk_get(NULL, "dpll1_ck");
+        arm_fck = clk_get(NULL, "arm_fck");
+        core_ck = clk_get(NULL, "core_ck");
+        osc_sys_ck = clk_get(NULL, "osc_sys_ck");
+
         /* REVISIT: not yet ready for 343x */
-        if (clk_set_rate(&dpll1_ck, mpurate))
+        if (clk_set_rate(dpll1_ck, mpurate))
                 printk(KERN_ERR "*** Unable to set MPU rate\n");
 
         recalculate_root_clocks();
 
-        printk(KERN_INFO "Switched to new clocking rate (Crystal/Core/MPU): "
-               "%ld.%01ld/%ld/%ld MHz\n",
-               (osc_sys_ck.rate / 1000000), ((osc_sys_ck.rate / 100000) % 10),
-               (core_ck.rate / 1000000), (arm_fck.rate / 1000000)) ;
+        osc_sys_rate = clk_get_rate(osc_sys_ck);
+
+        pr_info("Switched to new clocking rate (Crystal/Core/MPU): "
+                "%ld.%01ld/%ld/%ld MHz\n",
+                (osc_sys_rate / 1000000),
+                ((osc_sys_rate / 100000) % 10),
+                (clk_get_rate(core_ck) / 1000000),
+                (clk_get_rate(arm_fck) / 1000000));
 
         calibrate_delay();
 
@@ -1113,83 +348,7 @@ static int __init omap2_clk_arch_init(void)
 }
 arch_initcall(omap2_clk_arch_init);
 
-int __init omap2_clk_init(void)
-{
-        /* struct prcm_config *prcm; */
-        struct omap_clk *c;
-        /* u32 clkrate; */
-        u32 cpu_clkflg;
-
-        if (cpu_is_omap34xx()) {
-                cpu_mask = RATE_IN_343X;
-                cpu_clkflg = CK_343X;
-
-                /*
-                 * Update this if there are further clock changes between ES2
-                 * and production parts
-                 */
-                if (omap_rev() == OMAP3430_REV_ES1_0) {
-                        /* No 3430ES1-only rates exist, so no RATE_IN_3430ES1 */
-                        cpu_clkflg |= CK_3430ES1;
-                } else {
-                        cpu_mask |= RATE_IN_3430ES2;
-                        cpu_clkflg |= CK_3430ES2;
-                }
-        }
-
-        clk_init(&omap2_clk_functions);
-
-        for (c = omap34xx_clks; c < omap34xx_clks + ARRAY_SIZE(omap34xx_clks); c++)
-                clk_preinit(c->lk.clk);
 
-        for (c = omap34xx_clks; c < omap34xx_clks + ARRAY_SIZE(omap34xx_clks); c++)
-                if (c->cpu & cpu_clkflg) {
-                        clkdev_add(&c->lk);
-                        clk_register(c->lk.clk);
-                        omap2_init_clk_clkdm(c->lk.clk);
-                }
-
-        /* REVISIT: Not yet ready for OMAP3 */
-#if 0
-        /* Check the MPU rate set by bootloader */
-        clkrate = omap2_get_dpll_rate_24xx(&dpll_ck);
-        for (prcm = rate_table; prcm->mpu_speed; prcm++) {
-                if (!(prcm->flags & cpu_mask))
-                        continue;
-                if (prcm->xtal_speed != sys_ck.rate)
-                        continue;
-                if (prcm->dpll_speed <= clkrate)
-                         break;
-        }
-        curr_prcm_set = prcm;
 #endif
 
-        recalculate_root_clocks();
-
-        printk(KERN_INFO "Clocking rate (Crystal/Core/MPU): "
-               "%ld.%01ld/%ld/%ld MHz\n",
-               (osc_sys_ck.rate / 1000000), (osc_sys_ck.rate / 100000) % 10,
-               (core_ck.rate / 1000000), (arm_fck.rate / 1000000));
-
-        /*
-         * Only enable those clocks we will need, let the drivers
-         * enable other clocks as necessary
-         */
-        clk_enable_init_clocks();
-
-        /*
-         * Lock DPLL5 and put it in autoidle.
-         */
-        if (omap_rev() >= OMAP3430_REV_ES2_0)
-                omap3_clk_lock_dpll5();
 
-        /* Avoid sleeping during omap2_clk_prepare_for_reboot() */
-        /* REVISIT: not yet ready for 343x */
-#if 0
-        vclk = clk_get(NULL, "virt_prcm_set");
-        sclk = clk_get(NULL, "sys_ck");
-#endif
-        return 0;
-}
-
-#endif
diff --git a/arch/arm/mach-omap2/clock34xx.h b/arch/arm/mach-omap2/clock34xx.h
index 8fe1bcb23dd9..9a2c07eac9ad 100644
--- a/arch/arm/mach-omap2/clock34xx.h
+++ b/arch/arm/mach-omap2/clock34xx.h
@@ -1,2993 +1,24 @@
 /*
- * OMAP3 clock framework
+ * OMAP3 clock function prototypes and macros
  *
- * Copyright (C) 2007-2008 Texas Instruments, Inc.
- * Copyright (C) 2007-2008 Nokia Corporation
- *
- * Written by Paul Walmsley
- * With many device clock fixes by Kevin Hilman and Jouni Högander
- * DPLL bypass clock support added by Roman Tereshonkov
- *
- */
-
-/*
- * Virtual clocks are introduced as convenient tools.
- * They are sources for other clocks and not supposed
- * to be requested from drivers directly.
- */
-
-#ifndef __ARCH_ARM_MACH_OMAP2_CLOCK34XX_H
-#define __ARCH_ARM_MACH_OMAP2_CLOCK34XX_H
-
-#include <plat/control.h>
-
-#include "clock.h"
-#include "cm.h"
-#include "cm-regbits-34xx.h"
-#include "prm.h"
-#include "prm-regbits-34xx.h"
-
-#define OMAP_CM_REGADDR         OMAP34XX_CM_REGADDR
-
-static unsigned long omap3_dpll_recalc(struct clk *clk);
-static unsigned long omap3_clkoutx2_recalc(struct clk *clk);
-static void omap3_dpll_allow_idle(struct clk *clk);
-static void omap3_dpll_deny_idle(struct clk *clk);
-static u32 omap3_dpll_autoidle_read(struct clk *clk);
-static int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate);
-static int omap3_dpll4_set_rate(struct clk *clk, unsigned long rate);
-static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate);
-
-/* Maximum DPLL multiplier, divider values for OMAP3 */
-#define OMAP3_MAX_DPLL_MULT             2048
-#define OMAP3_MAX_DPLL_DIV              128
-
-/*
- * DPLL1 supplies clock to the MPU.
- * DPLL2 supplies clock to the IVA2.
- * DPLL3 supplies CORE domain clocks.
- * DPLL4 supplies peripheral clocks.
- * DPLL5 supplies other peripheral clocks (USBHOST, USIM).
- */
-
-/* Forward declarations for DPLL bypass clocks */
-static struct clk dpll1_fck;
-static struct clk dpll2_fck;
-
-/* CM_CLKEN_PLL*.EN* bit values - not all are available for every DPLL */
-#define DPLL_LOW_POWER_STOP             0x1
-#define DPLL_LOW_POWER_BYPASS           0x5
-#define DPLL_LOCKED                     0x7
-
-/* PRM CLOCKS */
-
-/* According to timer32k.c, this is a 32768Hz clock, not a 32000Hz clock. */
-static struct clk omap_32k_fck = {
-        .name           = "omap_32k_fck",
-        .ops            = &clkops_null,
-        .rate           = 32768,
-        .flags          = RATE_FIXED,
-};
-
-static struct clk secure_32k_fck = {
-        .name           = "secure_32k_fck",
-        .ops            = &clkops_null,
-        .rate           = 32768,
-        .flags          = RATE_FIXED,
-};
-
-/* Virtual source clocks for osc_sys_ck */
-static struct clk virt_12m_ck = {
-        .name           = "virt_12m_ck",
-        .ops            = &clkops_null,
-        .rate           = 12000000,
-        .flags          = RATE_FIXED,
-};
-
-static struct clk virt_13m_ck = {
-        .name           = "virt_13m_ck",
-        .ops            = &clkops_null,
-        .rate           = 13000000,
-        .flags          = RATE_FIXED,
-};
-
-static struct clk virt_16_8m_ck = {
-        .name           = "virt_16_8m_ck",
-        .ops            = &clkops_null,
-        .rate           = 16800000,
-        .flags          = RATE_FIXED,
-};
-
-static struct clk virt_19_2m_ck = {
-        .name           = "virt_19_2m_ck",
-        .ops            = &clkops_null,
-        .rate           = 19200000,
-        .flags          = RATE_FIXED,
-};
-
-static struct clk virt_26m_ck = {
-        .name           = "virt_26m_ck",
-        .ops            = &clkops_null,
-        .rate           = 26000000,
-        .flags          = RATE_FIXED,
-};
-
-static struct clk virt_38_4m_ck = {
-        .name           = "virt_38_4m_ck",
-        .ops            = &clkops_null,
-        .rate           = 38400000,
-        .flags          = RATE_FIXED,
-};
-
-static const struct clksel_rate osc_sys_12m_rates[] = {
-        { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
-        { .div = 0 }
-};
-
-static const struct clksel_rate osc_sys_13m_rates[] = {
-        { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
-        { .div = 0 }
-};
-
-static const struct clksel_rate osc_sys_16_8m_rates[] = {
-        { .div = 1, .val = 5, .flags = RATE_IN_3430ES2 | DEFAULT_RATE },
-        { .div = 0 }
-};
-
-static const struct clksel_rate osc_sys_19_2m_rates[] = {
-        { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
-        { .div = 0 }
-};
-
-static const struct clksel_rate osc_sys_26m_rates[] = {
-        { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
-        { .div = 0 }
-};
-
-static const struct clksel_rate osc_sys_38_4m_rates[] = {
-        { .div = 1, .val = 4, .flags = RATE_IN_343X | DEFAULT_RATE },
-        { .div = 0 }
-};
-
-static const struct clksel osc_sys_clksel[] = {
-        { .parent = &virt_12m_ck,   .rates = osc_sys_12m_rates },
-        { .parent = &virt_13m_ck,   .rates = osc_sys_13m_rates },
-        { .parent = &virt_16_8m_ck, .rates = osc_sys_16_8m_rates },
-        { .parent = &virt_19_2m_ck, .rates = osc_sys_19_2m_rates },
-        { .parent = &virt_26m_ck,   .rates = osc_sys_26m_rates },
-        { .parent = &virt_38_4m_ck, .rates = osc_sys_38_4m_rates },
-        { .parent = NULL },
-};
-
-/* Oscillator clock */
-/* 12, 13, 16.8, 19.2, 26, or 38.4 MHz */
-static struct clk osc_sys_ck = {
-        .name           = "osc_sys_ck",
-        .ops            = &clkops_null,
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP3430_PRM_CLKSEL,
-        .clksel_mask    = OMAP3430_SYS_CLKIN_SEL_MASK,
-        .clksel         = osc_sys_clksel,
-        /* REVISIT: deal with autoextclkmode? */
-        .flags          = RATE_FIXED,
-        .recalc         = &omap2_clksel_recalc,
-};
-
-static const struct clksel_rate div2_rates[] = {
-        { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
-        { .div = 2, .val = 2, .flags = RATE_IN_343X },
-        { .div = 0 }
-};
-
-static const struct clksel sys_clksel[] = {
-        { .parent = &osc_sys_ck, .rates = div2_rates },
-        { .parent = NULL }
-};
-
-/* Latency: this clock is only enabled after PRM_CLKSETUP.SETUP_TIME */
-/* Feeds DPLLs - divided first by PRM_CLKSRC_CTRL.SYSCLKDIV? */
-static struct clk sys_ck = {
-        .name           = "sys_ck",
-        .ops            = &clkops_null,
-        .parent         = &osc_sys_ck,
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP3430_PRM_CLKSRC_CTRL,
-        .clksel_mask    = OMAP_SYSCLKDIV_MASK,
-        .clksel         = sys_clksel,
-        .recalc         = &omap2_clksel_recalc,
-};
-
-static struct clk sys_altclk = {
-        .name           = "sys_altclk",
-        .ops            = &clkops_null,
-};
-
-/* Optional external clock input for some McBSPs */
-static struct clk mcbsp_clks = {
-        .name           = "mcbsp_clks",
-        .ops            = &clkops_null,
-};
-
-/* PRM EXTERNAL CLOCK OUTPUT */
-
-static struct clk sys_clkout1 = {
-        .name           = "sys_clkout1",
-        .ops            = &clkops_omap2_dflt,
-        .parent         = &osc_sys_ck,
-        .enable_reg     = OMAP3430_PRM_CLKOUT_CTRL,
-        .enable_bit     = OMAP3430_CLKOUT_EN_SHIFT,
-        .recalc         = &followparent_recalc,
-};
-
-/* DPLLS */
-
-/* CM CLOCKS */
-
-static const struct clksel_rate div16_dpll_rates[] = {
-        { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
-        { .div = 2, .val = 2, .flags = RATE_IN_343X },
-        { .div = 3, .val = 3, .flags = RATE_IN_343X },
-        { .div = 4, .val = 4, .flags = RATE_IN_343X },
-        { .div = 5, .val = 5, .flags = RATE_IN_343X },
-        { .div = 6, .val = 6, .flags = RATE_IN_343X },
-        { .div = 7, .val = 7, .flags = RATE_IN_343X },
-        { .div = 8, .val = 8, .flags = RATE_IN_343X },
-        { .div = 9, .val = 9, .flags = RATE_IN_343X },
-        { .div = 10, .val = 10, .flags = RATE_IN_343X },
-        { .div = 11, .val = 11, .flags = RATE_IN_343X },
-        { .div = 12, .val = 12, .flags = RATE_IN_343X },
-        { .div = 13, .val = 13, .flags = RATE_IN_343X },
-        { .div = 14, .val = 14, .flags = RATE_IN_343X },
-        { .div = 15, .val = 15, .flags = RATE_IN_343X },
-        { .div = 16, .val = 16, .flags = RATE_IN_343X },
-        { .div = 0 }
-};
-
-/* DPLL1 */
-/* MPU clock source */
-/* Type: DPLL */
-static struct dpll_data dpll1_dd = {
-        .mult_div1_reg  = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
-        .mult_mask      = OMAP3430_MPU_DPLL_MULT_MASK,
-        .div1_mask      = OMAP3430_MPU_DPLL_DIV_MASK,
-        .clk_bypass     = &dpll1_fck,
-        .clk_ref        = &sys_ck,
-        .freqsel_mask   = OMAP3430_MPU_DPLL_FREQSEL_MASK,
-        .control_reg    = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKEN_PLL),
-        .enable_mask    = OMAP3430_EN_MPU_DPLL_MASK,
-        .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
-        .auto_recal_bit = OMAP3430_EN_MPU_DPLL_DRIFTGUARD_SHIFT,
-        .recal_en_bit   = OMAP3430_MPU_DPLL_RECAL_EN_SHIFT,
-        .recal_st_bit   = OMAP3430_MPU_DPLL_ST_SHIFT,
-        .autoidle_reg   = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_AUTOIDLE_PLL),
-        .autoidle_mask  = OMAP3430_AUTO_MPU_DPLL_MASK,
-        .idlest_reg     = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
-        .idlest_mask    = OMAP3430_ST_MPU_CLK_MASK,
-        .max_multiplier = OMAP3_MAX_DPLL_MULT,
-        .min_divider    = 1,
-        .max_divider    = OMAP3_MAX_DPLL_DIV,
-        .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
-};
-
-static struct clk dpll1_ck = {
-        .name           = "dpll1_ck",
-        .ops            = &clkops_null,
-        .parent         = &sys_ck,
-        .dpll_data      = &dpll1_dd,
-        .round_rate     = &omap2_dpll_round_rate,
-        .set_rate       = &omap3_noncore_dpll_set_rate,
-        .clkdm_name     = "dpll1_clkdm",
-        .recalc         = &omap3_dpll_recalc,
-};
-
-/*
- * This virtual clock provides the CLKOUTX2 output from the DPLL if the
- * DPLL isn't bypassed.
- */
-static struct clk dpll1_x2_ck = {
-        .name           = "dpll1_x2_ck",
-        .ops            = &clkops_null,
-        .parent         = &dpll1_ck,
-        .clkdm_name     = "dpll1_clkdm",
-        .recalc         = &omap3_clkoutx2_recalc,
-};
-
-/* On DPLL1, unlike other DPLLs, the divider is downstream from CLKOUTX2 */
-static const struct clksel div16_dpll1_x2m2_clksel[] = {
-        { .parent = &dpll1_x2_ck, .rates = div16_dpll_rates },
-        { .parent = NULL }
-};
-
-/*
- * Does not exist in the TRM - needed to separate the M2 divider from
- * bypass selection in mpu_ck
- */
-static struct clk dpll1_x2m2_ck = {
-        .name           = "dpll1_x2m2_ck",
-        .ops            = &clkops_null,
-        .parent         = &dpll1_x2_ck,
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL),
-        .clksel_mask    = OMAP3430_MPU_DPLL_CLKOUT_DIV_MASK,
-        .clksel         = div16_dpll1_x2m2_clksel,
-        .clkdm_name     = "dpll1_clkdm",
-        .recalc         = &omap2_clksel_recalc,
-};
-
-/* DPLL2 */
-/* IVA2 clock source */
-/* Type: DPLL */
-
-static struct dpll_data dpll2_dd = {
-        .mult_div1_reg  = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
-        .mult_mask      = OMAP3430_IVA2_DPLL_MULT_MASK,
-        .div1_mask      = OMAP3430_IVA2_DPLL_DIV_MASK,
-        .clk_bypass     = &dpll2_fck,
-        .clk_ref        = &sys_ck,
-        .freqsel_mask   = OMAP3430_IVA2_DPLL_FREQSEL_MASK,
-        .control_reg    = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKEN_PLL),
-        .enable_mask    = OMAP3430_EN_IVA2_DPLL_MASK,
-        .modes          = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED) |
-                                (1 << DPLL_LOW_POWER_BYPASS),
-        .auto_recal_bit = OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT,
-        .recal_en_bit   = OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_SHIFT,
-        .recal_st_bit   = OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_SHIFT,
-        .autoidle_reg   = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_AUTOIDLE_PLL),
-        .autoidle_mask  = OMAP3430_AUTO_IVA2_DPLL_MASK,
-        .idlest_reg     = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_IDLEST_PLL),
-        .idlest_mask    = OMAP3430_ST_IVA2_CLK_MASK,
-        .max_multiplier = OMAP3_MAX_DPLL_MULT,
-        .min_divider    = 1,
-        .max_divider    = OMAP3_MAX_DPLL_DIV,
-        .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
-};
-
-static struct clk dpll2_ck = {
-        .name           = "dpll2_ck",
-        .ops            = &clkops_noncore_dpll_ops,
-        .parent         = &sys_ck,
-        .dpll_data      = &dpll2_dd,
-        .round_rate     = &omap2_dpll_round_rate,
-        .set_rate       = &omap3_noncore_dpll_set_rate,
-        .clkdm_name     = "dpll2_clkdm",
-        .recalc         = &omap3_dpll_recalc,
-};
-
-static const struct clksel div16_dpll2_m2x2_clksel[] = {
-        { .parent = &dpll2_ck, .rates = div16_dpll_rates },
-        { .parent = NULL }
-};
-
-/*
- * The TRM is conflicted on whether IVA2 clock comes from DPLL2 CLKOUT
- * or CLKOUTX2. CLKOUT seems most plausible.
- */
-static struct clk dpll2_m2_ck = {
-        .name           = "dpll2_m2_ck",
-        .ops            = &clkops_null,
-        .parent         = &dpll2_ck,
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD,
-                                          OMAP3430_CM_CLKSEL2_PLL),
-        .clksel_mask    = OMAP3430_IVA2_DPLL_CLKOUT_DIV_MASK,
-        .clksel         = div16_dpll2_m2x2_clksel,
-        .clkdm_name     = "dpll2_clkdm",
-        .recalc         = &omap2_clksel_recalc,
-};
-
-/*
- * DPLL3
- * Source clock for all interfaces and for some device fclks
- * REVISIT: Also supports fast relock bypass - not included below
- */
-static struct dpll_data dpll3_dd = {
-        .mult_div1_reg  = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
-        .mult_mask      = OMAP3430_CORE_DPLL_MULT_MASK,
-        .div1_mask      = OMAP3430_CORE_DPLL_DIV_MASK,
-        .clk_bypass     = &sys_ck,
-        .clk_ref        = &sys_ck,
-        .freqsel_mask   = OMAP3430_CORE_DPLL_FREQSEL_MASK,
-        .control_reg    = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
-        .enable_mask    = OMAP3430_EN_CORE_DPLL_MASK,
-        .auto_recal_bit = OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT,
-        .recal_en_bit   = OMAP3430_CORE_DPLL_RECAL_EN_SHIFT,
-        .recal_st_bit   = OMAP3430_CORE_DPLL_ST_SHIFT,
-        .autoidle_reg   = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
-        .autoidle_mask  = OMAP3430_AUTO_CORE_DPLL_MASK,
-        .idlest_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
-        .idlest_mask    = OMAP3430_ST_CORE_CLK_MASK,
-        .max_multiplier = OMAP3_MAX_DPLL_MULT,
-        .min_divider    = 1,
-        .max_divider    = OMAP3_MAX_DPLL_DIV,
-        .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
-};
-
-static struct clk dpll3_ck = {
-        .name           = "dpll3_ck",
-        .ops            = &clkops_null,
-        .parent         = &sys_ck,
-        .dpll_data      = &dpll3_dd,
-        .round_rate     = &omap2_dpll_round_rate,
-        .clkdm_name     = "dpll3_clkdm",
-        .recalc         = &omap3_dpll_recalc,
-};
-
-/*
- * This virtual clock provides the CLKOUTX2 output from the DPLL if the
- * DPLL isn't bypassed
- */
-static struct clk dpll3_x2_ck = {
-        .name           = "dpll3_x2_ck",
-        .ops            = &clkops_null,
-        .parent         = &dpll3_ck,
-        .clkdm_name     = "dpll3_clkdm",
-        .recalc         = &omap3_clkoutx2_recalc,
-};
-
-static const struct clksel_rate div31_dpll3_rates[] = {
-        { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
-        { .div = 2, .val = 2, .flags = RATE_IN_343X },
-        { .div = 3, .val = 3, .flags = RATE_IN_3430ES2 },
-        { .div = 4, .val = 4, .flags = RATE_IN_3430ES2 },
-        { .div = 5, .val = 5, .flags = RATE_IN_3430ES2 },
-        { .div = 6, .val = 6, .flags = RATE_IN_3430ES2 },
-        { .div = 7, .val = 7, .flags = RATE_IN_3430ES2 },
-        { .div = 8, .val = 8, .flags = RATE_IN_3430ES2 },
-        { .div = 9, .val = 9, .flags = RATE_IN_3430ES2 },
-        { .div = 10, .val = 10, .flags = RATE_IN_3430ES2 },
-        { .div = 11, .val = 11, .flags = RATE_IN_3430ES2 },
-        { .div = 12, .val = 12, .flags = RATE_IN_3430ES2 },
-        { .div = 13, .val = 13, .flags = RATE_IN_3430ES2 },
-        { .div = 14, .val = 14, .flags = RATE_IN_3430ES2 },
-        { .div = 15, .val = 15, .flags = RATE_IN_3430ES2 },
-        { .div = 16, .val = 16, .flags = RATE_IN_3430ES2 },
-        { .div = 17, .val = 17, .flags = RATE_IN_3430ES2 },
-        { .div = 18, .val = 18, .flags = RATE_IN_3430ES2 },
-        { .div = 19, .val = 19, .flags = RATE_IN_3430ES2 },
-        { .div = 20, .val = 20, .flags = RATE_IN_3430ES2 },
-        { .div = 21, .val = 21, .flags = RATE_IN_3430ES2 },
-        { .div = 22, .val = 22, .flags = RATE_IN_3430ES2 },
-        { .div = 23, .val = 23, .flags = RATE_IN_3430ES2 },
-        { .div = 24, .val = 24, .flags = RATE_IN_3430ES2 },
-        { .div = 25, .val = 25, .flags = RATE_IN_3430ES2 },
-        { .div = 26, .val = 26, .flags = RATE_IN_3430ES2 },
-        { .div = 27, .val = 27, .flags = RATE_IN_3430ES2 },
-        { .div = 28, .val = 28, .flags = RATE_IN_3430ES2 },
-        { .div = 29, .val = 29, .flags = RATE_IN_3430ES2 },
-        { .div = 30, .val = 30, .flags = RATE_IN_3430ES2 },
-        { .div = 31, .val = 31, .flags = RATE_IN_3430ES2 },
-        { .div = 0 },
-};
-
-static const struct clksel div31_dpll3m2_clksel[] = {
-        { .parent = &dpll3_ck, .rates = div31_dpll3_rates },
-        { .parent = NULL }
-};
-
-/* DPLL3 output M2 - primary control point for CORE speed */
-static struct clk dpll3_m2_ck = {
-        .name           = "dpll3_m2_ck",
-        .ops            = &clkops_null,
-        .parent         = &dpll3_ck,
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
-        .clksel_mask    = OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK,
-        .clksel         = div31_dpll3m2_clksel,
-        .clkdm_name     = "dpll3_clkdm",
-        .round_rate     = &omap2_clksel_round_rate,
-        .set_rate       = &omap3_core_dpll_m2_set_rate,
-        .recalc         = &omap2_clksel_recalc,
-};
-
-static struct clk core_ck = {
-        .name           = "core_ck",
-        .ops            = &clkops_null,
-        .parent         = &dpll3_m2_ck,
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk dpll3_m2x2_ck = {
-        .name           = "dpll3_m2x2_ck",
-        .ops            = &clkops_null,
-        .parent         = &dpll3_m2_ck,
-        .clkdm_name     = "dpll3_clkdm",
-        .recalc         = &omap3_clkoutx2_recalc,
-};
-
-/* The PWRDN bit is apparently only available on 3430ES2 and above */
-static const struct clksel div16_dpll3_clksel[] = {
-        { .parent = &dpll3_ck, .rates = div16_dpll_rates },
-        { .parent = NULL }
-};
-
-/* This virtual clock is the source for dpll3_m3x2_ck */
-static struct clk dpll3_m3_ck = {
-        .name           = "dpll3_m3_ck",
-        .ops            = &clkops_null,
-        .parent         = &dpll3_ck,
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
-        .clksel_mask    = OMAP3430_DIV_DPLL3_MASK,
-        .clksel         = div16_dpll3_clksel,
-        .clkdm_name     = "dpll3_clkdm",
-        .recalc         = &omap2_clksel_recalc,
-};
-
-/* The PWRDN bit is apparently only available on 3430ES2 and above */
-static struct clk dpll3_m3x2_ck = {
-        .name           = "dpll3_m3x2_ck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &dpll3_m3_ck,
-        .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
-        .enable_bit     = OMAP3430_PWRDN_EMU_CORE_SHIFT,
-        .flags          = INVERT_ENABLE,
-        .clkdm_name     = "dpll3_clkdm",
-        .recalc         = &omap3_clkoutx2_recalc,
-};
-
-static struct clk emu_core_alwon_ck = {
-        .name           = "emu_core_alwon_ck",
-        .ops            = &clkops_null,
-        .parent         = &dpll3_m3x2_ck,
-        .clkdm_name     = "dpll3_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-/* DPLL4 */
-/* Supplies 96MHz, 54Mhz TV DAC, DSS fclk, CAM sensor clock, emul trace clk */
-/* Type: DPLL */
-static struct dpll_data dpll4_dd = {
-        .mult_div1_reg  = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2),
-        .mult_mask      = OMAP3430_PERIPH_DPLL_MULT_MASK,
-        .div1_mask      = OMAP3430_PERIPH_DPLL_DIV_MASK,
-        .clk_bypass     = &sys_ck,
-        .clk_ref        = &sys_ck,
-        .freqsel_mask   = OMAP3430_PERIPH_DPLL_FREQSEL_MASK,
-        .control_reg    = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
-        .enable_mask    = OMAP3430_EN_PERIPH_DPLL_MASK,
-        .modes          = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
-        .auto_recal_bit = OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT,
-        .recal_en_bit   = OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT,
-        .recal_st_bit   = OMAP3430_PERIPH_DPLL_ST_SHIFT,
-        .autoidle_reg   = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
-        .autoidle_mask  = OMAP3430_AUTO_PERIPH_DPLL_MASK,
-        .idlest_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
-        .idlest_mask    = OMAP3430_ST_PERIPH_CLK_MASK,
-        .max_multiplier = OMAP3_MAX_DPLL_MULT,
-        .min_divider    = 1,
-        .max_divider    = OMAP3_MAX_DPLL_DIV,
-        .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
-};
-
-static struct clk dpll4_ck = {
-        .name           = "dpll4_ck",
-        .ops            = &clkops_noncore_dpll_ops,
-        .parent         = &sys_ck,
-        .dpll_data      = &dpll4_dd,
-        .round_rate     = &omap2_dpll_round_rate,
-        .set_rate       = &omap3_dpll4_set_rate,
-        .clkdm_name     = "dpll4_clkdm",
-        .recalc         = &omap3_dpll_recalc,
-};
-
-/*
- * This virtual clock provides the CLKOUTX2 output from the DPLL if the
- * DPLL isn't bypassed --
- * XXX does this serve any downstream clocks?
- */
-static struct clk dpll4_x2_ck = {
-        .name           = "dpll4_x2_ck",
-        .ops            = &clkops_null,
-        .parent         = &dpll4_ck,
-        .clkdm_name     = "dpll4_clkdm",
-        .recalc         = &omap3_clkoutx2_recalc,
-};
-
-static const struct clksel div16_dpll4_clksel[] = {
-        { .parent = &dpll4_ck, .rates = div16_dpll_rates },
-        { .parent = NULL }
-};
-
-/* This virtual clock is the source for dpll4_m2x2_ck */
-static struct clk dpll4_m2_ck = {
-        .name           = "dpll4_m2_ck",
-        .ops            = &clkops_null,
-        .parent         = &dpll4_ck,
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, OMAP3430_CM_CLKSEL3),
-        .clksel_mask    = OMAP3430_DIV_96M_MASK,
-        .clksel         = div16_dpll4_clksel,
-        .clkdm_name     = "dpll4_clkdm",
-        .recalc         = &omap2_clksel_recalc,
-};
-
-/* The PWRDN bit is apparently only available on 3430ES2 and above */
-static struct clk dpll4_m2x2_ck = {
-        .name           = "dpll4_m2x2_ck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &dpll4_m2_ck,
-        .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
-        .enable_bit     = OMAP3430_PWRDN_96M_SHIFT,
-        .flags          = INVERT_ENABLE,
-        .clkdm_name     = "dpll4_clkdm",
-        .recalc         = &omap3_clkoutx2_recalc,
-};
-
-/*
- * DPLL4 generates DPLL4_M2X2_CLK which is then routed into the PRM as
- * PRM_96M_ALWON_(F)CLK.  Two clocks then emerge from the PRM:
- * 96M_ALWON_FCLK (called "omap_96m_alwon_fck" below) and
- * CM_96K_(F)CLK.
- */
-static struct clk omap_96m_alwon_fck = {
-        .name           = "omap_96m_alwon_fck",
-        .ops            = &clkops_null,
-        .parent         = &dpll4_m2x2_ck,
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk cm_96m_fck = {
-        .name           = "cm_96m_fck",
-        .ops            = &clkops_null,
-        .parent         = &omap_96m_alwon_fck,
-        .recalc         = &followparent_recalc,
-};
-
-static const struct clksel_rate omap_96m_dpll_rates[] = {
-        { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
-        { .div = 0 }
-};
-
-static const struct clksel_rate omap_96m_sys_rates[] = {
-        { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
-        { .div = 0 }
-};
-
-static const struct clksel omap_96m_fck_clksel[] = {
-        { .parent = &cm_96m_fck, .rates = omap_96m_dpll_rates },
-        { .parent = &sys_ck,     .rates = omap_96m_sys_rates },
-        { .parent = NULL }
-};
-
-static struct clk omap_96m_fck = {
-        .name           = "omap_96m_fck",
-        .ops            = &clkops_null,
-        .parent         = &sys_ck,
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
-        .clksel_mask    = OMAP3430_SOURCE_96M_MASK,
-        .clksel         = omap_96m_fck_clksel,
-        .recalc         = &omap2_clksel_recalc,
-};
-
-/* This virtual clock is the source for dpll4_m3x2_ck */
-static struct clk dpll4_m3_ck = {
-        .name           = "dpll4_m3_ck",
-        .ops            = &clkops_null,
-        .parent         = &dpll4_ck,
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
-        .clksel_mask    = OMAP3430_CLKSEL_TV_MASK,
-        .clksel         = div16_dpll4_clksel,
-        .clkdm_name     = "dpll4_clkdm",
-        .recalc         = &omap2_clksel_recalc,
-};
-
-/* The PWRDN bit is apparently only available on 3430ES2 and above */
-static struct clk dpll4_m3x2_ck = {
-        .name           = "dpll4_m3x2_ck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &dpll4_m3_ck,
-        .init           = &omap2_init_clksel_parent,
-        .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
-        .enable_bit     = OMAP3430_PWRDN_TV_SHIFT,
-        .flags          = INVERT_ENABLE,
-        .clkdm_name     = "dpll4_clkdm",
-        .recalc         = &omap3_clkoutx2_recalc,
-};
-
-static const struct clksel_rate omap_54m_d4m3x2_rates[] = {
-        { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
-        { .div = 0 }
-};
-
-static const struct clksel_rate omap_54m_alt_rates[] = {
-        { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
-        { .div = 0 }
-};
-
-static const struct clksel omap_54m_clksel[] = {
-        { .parent = &dpll4_m3x2_ck, .rates = omap_54m_d4m3x2_rates },
-        { .parent = &sys_altclk,    .rates = omap_54m_alt_rates },
-        { .parent = NULL }
-};
-
-static struct clk omap_54m_fck = {
-        .name           = "omap_54m_fck",
-        .ops            = &clkops_null,
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
-        .clksel_mask    = OMAP3430_SOURCE_54M_MASK,
-        .clksel         = omap_54m_clksel,
-        .recalc         = &omap2_clksel_recalc,
-};
-
-static const struct clksel_rate omap_48m_cm96m_rates[] = {
-        { .div = 2, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
-        { .div = 0 }
-};
-
-static const struct clksel_rate omap_48m_alt_rates[] = {
-        { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
-        { .div = 0 }
-};
-
-static const struct clksel omap_48m_clksel[] = {
-        { .parent = &cm_96m_fck, .rates = omap_48m_cm96m_rates },
-        { .parent = &sys_altclk, .rates = omap_48m_alt_rates },
-        { .parent = NULL }
-};
-
-static struct clk omap_48m_fck = {
-        .name           = "omap_48m_fck",
-        .ops            = &clkops_null,
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
-        .clksel_mask    = OMAP3430_SOURCE_48M_MASK,
-        .clksel         = omap_48m_clksel,
-        .recalc         = &omap2_clksel_recalc,
-};
-
-static struct clk omap_12m_fck = {
-        .name           = "omap_12m_fck",
-        .ops            = &clkops_null,
-        .parent         = &omap_48m_fck,
-        .fixed_div      = 4,
-        .recalc         = &omap2_fixed_divisor_recalc,
-};
-
-/* This virstual clock is the source for dpll4_m4x2_ck */
-static struct clk dpll4_m4_ck = {
-        .name           = "dpll4_m4_ck",
-        .ops            = &clkops_null,
-        .parent         = &dpll4_ck,
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
-        .clksel_mask    = OMAP3430_CLKSEL_DSS1_MASK,
-        .clksel         = div16_dpll4_clksel,
-        .clkdm_name     = "dpll4_clkdm",
-        .recalc         = &omap2_clksel_recalc,
-        .set_rate       = &omap2_clksel_set_rate,
-        .round_rate     = &omap2_clksel_round_rate,
-};
-
-/* The PWRDN bit is apparently only available on 3430ES2 and above */
-static struct clk dpll4_m4x2_ck = {
-        .name           = "dpll4_m4x2_ck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &dpll4_m4_ck,
-        .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
-        .enable_bit     = OMAP3430_PWRDN_CAM_SHIFT,
-        .flags          = INVERT_ENABLE,
-        .clkdm_name     = "dpll4_clkdm",
-        .recalc         = &omap3_clkoutx2_recalc,
-};
-
-/* This virtual clock is the source for dpll4_m5x2_ck */
-static struct clk dpll4_m5_ck = {
-        .name           = "dpll4_m5_ck",
-        .ops            = &clkops_null,
-        .parent         = &dpll4_ck,
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_CLKSEL),
-        .clksel_mask    = OMAP3430_CLKSEL_CAM_MASK,
-        .clksel         = div16_dpll4_clksel,
-        .clkdm_name     = "dpll4_clkdm",
-        .recalc         = &omap2_clksel_recalc,
-};
-
-/* The PWRDN bit is apparently only available on 3430ES2 and above */
-static struct clk dpll4_m5x2_ck = {
-        .name           = "dpll4_m5x2_ck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &dpll4_m5_ck,
-        .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
-        .enable_bit     = OMAP3430_PWRDN_CAM_SHIFT,
-        .flags          = INVERT_ENABLE,
-        .clkdm_name     = "dpll4_clkdm",
-        .recalc         = &omap3_clkoutx2_recalc,
-};
-
-/* This virtual clock is the source for dpll4_m6x2_ck */
-static struct clk dpll4_m6_ck = {
-        .name           = "dpll4_m6_ck",
-        .ops            = &clkops_null,
-        .parent         = &dpll4_ck,
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
-        .clksel_mask    = OMAP3430_DIV_DPLL4_MASK,
-        .clksel         = div16_dpll4_clksel,
-        .clkdm_name     = "dpll4_clkdm",
-        .recalc         = &omap2_clksel_recalc,
-};
-
-/* The PWRDN bit is apparently only available on 3430ES2 and above */
-static struct clk dpll4_m6x2_ck = {
-        .name           = "dpll4_m6x2_ck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &dpll4_m6_ck,
-        .init           = &omap2_init_clksel_parent,
-        .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
-        .enable_bit     = OMAP3430_PWRDN_EMU_PERIPH_SHIFT,
-        .flags          = INVERT_ENABLE,
-        .clkdm_name     = "dpll4_clkdm",
-        .recalc         = &omap3_clkoutx2_recalc,
-};
-
-static struct clk emu_per_alwon_ck = {
-        .name           = "emu_per_alwon_ck",
-        .ops            = &clkops_null,
-        .parent         = &dpll4_m6x2_ck,
-        .clkdm_name     = "dpll4_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-/* DPLL5 */
-/* Supplies 120MHz clock, USIM source clock */
-/* Type: DPLL */
-/* 3430ES2 only */
-static struct dpll_data dpll5_dd = {
-        .mult_div1_reg  = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL4),
-        .mult_mask      = OMAP3430ES2_PERIPH2_DPLL_MULT_MASK,
-        .div1_mask      = OMAP3430ES2_PERIPH2_DPLL_DIV_MASK,
-        .clk_bypass     = &sys_ck,
-        .clk_ref        = &sys_ck,
-        .freqsel_mask   = OMAP3430ES2_PERIPH2_DPLL_FREQSEL_MASK,
-        .control_reg    = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKEN2),
-        .enable_mask    = OMAP3430ES2_EN_PERIPH2_DPLL_MASK,
-        .modes          = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
-        .auto_recal_bit = OMAP3430ES2_EN_PERIPH2_DPLL_DRIFTGUARD_SHIFT,
-        .recal_en_bit   = OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_SHIFT,
-        .recal_st_bit   = OMAP3430ES2_SND_PERIPH_DPLL_ST_SHIFT,
-        .autoidle_reg   = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_AUTOIDLE2_PLL),
-        .autoidle_mask  = OMAP3430ES2_AUTO_PERIPH2_DPLL_MASK,
-        .idlest_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST2),
-        .idlest_mask    = OMAP3430ES2_ST_PERIPH2_CLK_MASK,
-        .max_multiplier = OMAP3_MAX_DPLL_MULT,
-        .min_divider    = 1,
-        .max_divider    = OMAP3_MAX_DPLL_DIV,
-        .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
-};
-
-static struct clk dpll5_ck = {
-        .name           = "dpll5_ck",
-        .ops            = &clkops_noncore_dpll_ops,
-        .parent         = &sys_ck,
-        .dpll_data      = &dpll5_dd,
-        .round_rate     = &omap2_dpll_round_rate,
-        .set_rate       = &omap3_noncore_dpll_set_rate,
-        .clkdm_name     = "dpll5_clkdm",
-        .recalc         = &omap3_dpll_recalc,
-};
-
-static const struct clksel div16_dpll5_clksel[] = {
-        { .parent = &dpll5_ck, .rates = div16_dpll_rates },
-        { .parent = NULL }
-};
-
-static struct clk dpll5_m2_ck = {
-        .name           = "dpll5_m2_ck",
-        .ops            = &clkops_null,
-        .parent         = &dpll5_ck,
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL5),
-        .clksel_mask    = OMAP3430ES2_DIV_120M_MASK,
-        .clksel         = div16_dpll5_clksel,
-        .clkdm_name     = "dpll5_clkdm",
-        .recalc         = &omap2_clksel_recalc,
-};
-
-/* CM EXTERNAL CLOCK OUTPUTS */
-
-static const struct clksel_rate clkout2_src_core_rates[] = {
-        { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
-        { .div = 0 }
-};
-
-static const struct clksel_rate clkout2_src_sys_rates[] = {
-        { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
-        { .div = 0 }
-};
-
-static const struct clksel_rate clkout2_src_96m_rates[] = {
-        { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
-        { .div = 0 }
-};
-
-static const struct clksel_rate clkout2_src_54m_rates[] = {
-        { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
-        { .div = 0 }
-};
-
-static const struct clksel clkout2_src_clksel[] = {
-        { .parent = &core_ck,           .rates = clkout2_src_core_rates },
-        { .parent = &sys_ck,            .rates = clkout2_src_sys_rates },
-        { .parent = &cm_96m_fck,        .rates = clkout2_src_96m_rates },
-        { .parent = &omap_54m_fck,      .rates = clkout2_src_54m_rates },
-        { .parent = NULL }
-};
-
-static struct clk clkout2_src_ck = {
-        .name           = "clkout2_src_ck",
-        .ops            = &clkops_omap2_dflt,
-        .init           = &omap2_init_clksel_parent,
-        .enable_reg     = OMAP3430_CM_CLKOUT_CTRL,
-        .enable_bit     = OMAP3430_CLKOUT2_EN_SHIFT,
-        .clksel_reg     = OMAP3430_CM_CLKOUT_CTRL,
-        .clksel_mask    = OMAP3430_CLKOUT2SOURCE_MASK,
-        .clksel         = clkout2_src_clksel,
-        .clkdm_name     = "core_clkdm",
-        .recalc         = &omap2_clksel_recalc,
-};
-
-static const struct clksel_rate sys_clkout2_rates[] = {
-        { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
-        { .div = 2, .val = 1, .flags = RATE_IN_343X },
-        { .div = 4, .val = 2, .flags = RATE_IN_343X },
-        { .div = 8, .val = 3, .flags = RATE_IN_343X },
-        { .div = 16, .val = 4, .flags = RATE_IN_343X },
-        { .div = 0 },
-};
-
-static const struct clksel sys_clkout2_clksel[] = {
-        { .parent = &clkout2_src_ck, .rates = sys_clkout2_rates },
-        { .parent = NULL },
-};
-
-static struct clk sys_clkout2 = {
-        .name           = "sys_clkout2",
-        .ops            = &clkops_null,
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP3430_CM_CLKOUT_CTRL,
-        .clksel_mask    = OMAP3430_CLKOUT2_DIV_MASK,
-        .clksel         = sys_clkout2_clksel,
-        .recalc         = &omap2_clksel_recalc,
-};
-
-/* CM OUTPUT CLOCKS */
-
-static struct clk corex2_fck = {
-        .name           = "corex2_fck",
-        .ops            = &clkops_null,
-        .parent         = &dpll3_m2x2_ck,
-        .recalc         = &followparent_recalc,
-};
-
-/* DPLL power domain clock controls */
-
-static const struct clksel_rate div4_rates[] = {
-        { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
-        { .div = 2, .val = 2, .flags = RATE_IN_343X },
-        { .div = 4, .val = 4, .flags = RATE_IN_343X },
-        { .div = 0 }
-};
-
-static const struct clksel div4_core_clksel[] = {
-        { .parent = &core_ck, .rates = div4_rates },
-        { .parent = NULL }
-};
-
-/*
- * REVISIT: Are these in DPLL power domain or CM power domain? docs
- * may be inconsistent here?
- */
-static struct clk dpll1_fck = {
-        .name           = "dpll1_fck",
-        .ops            = &clkops_null,
-        .parent         = &core_ck,
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
-        .clksel_mask    = OMAP3430_MPU_CLK_SRC_MASK,
-        .clksel         = div4_core_clksel,
-        .recalc         = &omap2_clksel_recalc,
-};
-
-static struct clk mpu_ck = {
-        .name           = "mpu_ck",
-        .ops            = &clkops_null,
-        .parent         = &dpll1_x2m2_ck,
-        .clkdm_name     = "mpu_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-/* arm_fck is divided by two when DPLL1 locked; otherwise, passthrough mpu_ck */
-static const struct clksel_rate arm_fck_rates[] = {
-        { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
-        { .div = 2, .val = 1, .flags = RATE_IN_343X },
-        { .div = 0 },
-};
-
-static const struct clksel arm_fck_clksel[] = {
-        { .parent = &mpu_ck, .rates = arm_fck_rates },
-        { .parent = NULL }
-};
-
-static struct clk arm_fck = {
-        .name           = "arm_fck",
-        .ops            = &clkops_null,
-        .parent         = &mpu_ck,
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
-        .clksel_mask    = OMAP3430_ST_MPU_CLK_MASK,
-        .clksel         = arm_fck_clksel,
-        .clkdm_name     = "mpu_clkdm",
-        .recalc         = &omap2_clksel_recalc,
-};
-
-/* XXX What about neon_clkdm ? */
-
-/*
- * REVISIT: This clock is never specifically defined in the 3430 TRM,
- * although it is referenced - so this is a guess
- */
-static struct clk emu_mpu_alwon_ck = {
-        .name           = "emu_mpu_alwon_ck",
-        .ops            = &clkops_null,
-        .parent         = &mpu_ck,
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk dpll2_fck = {
-        .name           = "dpll2_fck",
-        .ops            = &clkops_null,
-        .parent         = &core_ck,
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
-        .clksel_mask    = OMAP3430_IVA2_CLK_SRC_MASK,
-        .clksel         = div4_core_clksel,
-        .recalc         = &omap2_clksel_recalc,
-};
-
-static struct clk iva2_ck = {
-        .name           = "iva2_ck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &dpll2_m2_ck,
-        .init           = &omap2_init_clksel_parent,
-        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, CM_FCLKEN),
-        .enable_bit     = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT,
-        .clkdm_name     = "iva2_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-/* Common interface clocks */
-
-static const struct clksel div2_core_clksel[] = {
-        { .parent = &core_ck, .rates = div2_rates },
-        { .parent = NULL }
-};
-
-static struct clk l3_ick = {
-        .name           = "l3_ick",
-        .ops            = &clkops_null,
-        .parent         = &core_ck,
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
-        .clksel_mask    = OMAP3430_CLKSEL_L3_MASK,
-        .clksel         = div2_core_clksel,
-        .clkdm_name     = "core_l3_clkdm",
-        .recalc         = &omap2_clksel_recalc,
-};
-
-static const struct clksel div2_l3_clksel[] = {
-        { .parent = &l3_ick, .rates = div2_rates },
-        { .parent = NULL }
-};
-
-static struct clk l4_ick = {
-        .name           = "l4_ick",
-        .ops            = &clkops_null,
-        .parent         = &l3_ick,
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
-        .clksel_mask    = OMAP3430_CLKSEL_L4_MASK,
-        .clksel         = div2_l3_clksel,
-        .clkdm_name     = "core_l4_clkdm",
-        .recalc         = &omap2_clksel_recalc,
-
-};
-
-static const struct clksel div2_l4_clksel[] = {
-        { .parent = &l4_ick, .rates = div2_rates },
-        { .parent = NULL }
-};
-
-static struct clk rm_ick = {
-        .name           = "rm_ick",
-        .ops            = &clkops_null,
-        .parent         = &l4_ick,
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
-        .clksel_mask    = OMAP3430_CLKSEL_RM_MASK,
-        .clksel         = div2_l4_clksel,
-        .recalc         = &omap2_clksel_recalc,
-};
-
-/* GFX power domain */
-
-/* GFX clocks are in 3430ES1 only. 3430ES2 and later uses the SGX instead */
-
-static const struct clksel gfx_l3_clksel[] = {
-        { .parent = &l3_ick, .rates = gfx_l3_rates },
-        { .parent = NULL }
-};
-
-/* Virtual parent clock for gfx_l3_ick and gfx_l3_fck */
-static struct clk gfx_l3_ck = {
-        .name           = "gfx_l3_ck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &l3_ick,
-        .init           = &omap2_init_clksel_parent,
-        .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),
-        .enable_bit     = OMAP_EN_GFX_SHIFT,
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk gfx_l3_fck = {
-        .name           = "gfx_l3_fck",
-        .ops            = &clkops_null,
-        .parent         = &gfx_l3_ck,
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
-        .clksel_mask    = OMAP_CLKSEL_GFX_MASK,
-        .clksel         = gfx_l3_clksel,
-        .clkdm_name     = "gfx_3430es1_clkdm",
-        .recalc         = &omap2_clksel_recalc,
-};
-
-static struct clk gfx_l3_ick = {
-        .name           = "gfx_l3_ick",
-        .ops            = &clkops_null,
-        .parent         = &gfx_l3_ck,
-        .clkdm_name     = "gfx_3430es1_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk gfx_cg1_ck = {
-        .name           = "gfx_cg1_ck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &gfx_l3_fck, /* REVISIT: correct? */
-        .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
-        .enable_bit     = OMAP3430ES1_EN_2D_SHIFT,
-        .clkdm_name     = "gfx_3430es1_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk gfx_cg2_ck = {
-        .name           = "gfx_cg2_ck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &gfx_l3_fck, /* REVISIT: correct? */
-        .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
-        .enable_bit     = OMAP3430ES1_EN_3D_SHIFT,
-        .clkdm_name     = "gfx_3430es1_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-/* SGX power domain - 3430ES2 only */
-
-static const struct clksel_rate sgx_core_rates[] = {
-        { .div = 3, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
-        { .div = 4, .val = 1, .flags = RATE_IN_343X },
-        { .div = 6, .val = 2, .flags = RATE_IN_343X },
-        { .div = 0 },
-};
-
-static const struct clksel_rate sgx_96m_rates[] = {
-        { .div = 1,  .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
-        { .div = 0 },
-};
-
-static const struct clksel sgx_clksel[] = {
-        { .parent = &core_ck,    .rates = sgx_core_rates },
-        { .parent = &cm_96m_fck, .rates = sgx_96m_rates },
-        { .parent = NULL },
-};
-
-static struct clk sgx_fck = {
-        .name           = "sgx_fck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .init           = &omap2_init_clksel_parent,
-        .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_FCLKEN),
-        .enable_bit     = OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_SHIFT,
-        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_CLKSEL),
-        .clksel_mask    = OMAP3430ES2_CLKSEL_SGX_MASK,
-        .clksel         = sgx_clksel,
-        .clkdm_name     = "sgx_clkdm",
-        .recalc         = &omap2_clksel_recalc,
-};
-
-static struct clk sgx_ick = {
-        .name           = "sgx_ick",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &l3_ick,
-        .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_ICLKEN),
-        .enable_bit     = OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_SHIFT,
-        .clkdm_name     = "sgx_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-/* CORE power domain */
-
-static struct clk d2d_26m_fck = {
-        .name           = "d2d_26m_fck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &sys_ck,
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
-        .enable_bit     = OMAP3430ES1_EN_D2D_SHIFT,
-        .clkdm_name     = "d2d_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk modem_fck = {
-        .name           = "modem_fck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &sys_ck,
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
-        .enable_bit     = OMAP3430_EN_MODEM_SHIFT,
-        .clkdm_name     = "d2d_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk sad2d_ick = {
-        .name           = "sad2d_ick",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &l3_ick,
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
-        .enable_bit     = OMAP3430_EN_SAD2D_SHIFT,
-        .clkdm_name     = "d2d_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk mad2d_ick = {
-        .name           = "mad2d_ick",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &l3_ick,
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
-        .enable_bit     = OMAP3430_EN_MAD2D_SHIFT,
-        .clkdm_name     = "d2d_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-static const struct clksel omap343x_gpt_clksel[] = {
-        { .parent = &omap_32k_fck, .rates = gpt_32k_rates },
-        { .parent = &sys_ck,       .rates = gpt_sys_rates },
-        { .parent = NULL}
-};
-
-static struct clk gpt10_fck = {
-        .name           = "gpt10_fck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &sys_ck,
-        .init           = &omap2_init_clksel_parent,
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
-        .enable_bit     = OMAP3430_EN_GPT10_SHIFT,
-        .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
-        .clksel_mask    = OMAP3430_CLKSEL_GPT10_MASK,
-        .clksel         = omap343x_gpt_clksel,
-        .clkdm_name     = "core_l4_clkdm",
-        .recalc         = &omap2_clksel_recalc,
-};
-
-static struct clk gpt11_fck = {
-        .name           = "gpt11_fck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &sys_ck,
-        .init           = &omap2_init_clksel_parent,
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
-        .enable_bit     = OMAP3430_EN_GPT11_SHIFT,
-        .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
-        .clksel_mask    = OMAP3430_CLKSEL_GPT11_MASK,
-        .clksel         = omap343x_gpt_clksel,
-        .clkdm_name     = "core_l4_clkdm",
-        .recalc         = &omap2_clksel_recalc,
-};
-
-static struct clk cpefuse_fck = {
-        .name           = "cpefuse_fck",
-        .ops            = &clkops_omap2_dflt,
-        .parent         = &sys_ck,
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
-        .enable_bit     = OMAP3430ES2_EN_CPEFUSE_SHIFT,
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk ts_fck = {
-        .name           = "ts_fck",
-        .ops            = &clkops_omap2_dflt,
-        .parent         = &omap_32k_fck,
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
-        .enable_bit     = OMAP3430ES2_EN_TS_SHIFT,
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk usbtll_fck = {
-        .name           = "usbtll_fck",
-        .ops            = &clkops_omap2_dflt,
-        .parent         = &dpll5_m2_ck,
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
-        .enable_bit     = OMAP3430ES2_EN_USBTLL_SHIFT,
-        .recalc         = &followparent_recalc,
-};
-
-/* CORE 96M FCLK-derived clocks */
-
-static struct clk core_96m_fck = {
-        .name           = "core_96m_fck",
-        .ops            = &clkops_null,
-        .parent         = &omap_96m_fck,
-        .clkdm_name     = "core_l4_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk mmchs3_fck = {
-        .name           = "mmchs_fck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .id             = 2,
-        .parent         = &core_96m_fck,
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
-        .enable_bit     = OMAP3430ES2_EN_MMC3_SHIFT,
-        .clkdm_name     = "core_l4_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk mmchs2_fck = {
-        .name           = "mmchs_fck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .id             = 1,
-        .parent         = &core_96m_fck,
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
-        .enable_bit     = OMAP3430_EN_MMC2_SHIFT,
-        .clkdm_name     = "core_l4_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk mspro_fck = {
-        .name           = "mspro_fck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &core_96m_fck,
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
-        .enable_bit     = OMAP3430_EN_MSPRO_SHIFT,
-        .clkdm_name     = "core_l4_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk mmchs1_fck = {
-        .name           = "mmchs_fck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &core_96m_fck,
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
-        .enable_bit     = OMAP3430_EN_MMC1_SHIFT,
-        .clkdm_name     = "core_l4_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk i2c3_fck = {
-        .name           = "i2c_fck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .id             = 3,
-        .parent         = &core_96m_fck,
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
-        .enable_bit     = OMAP3430_EN_I2C3_SHIFT,
-        .clkdm_name     = "core_l4_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk i2c2_fck = {
-        .name           = "i2c_fck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .id             = 2,
-        .parent         = &core_96m_fck,
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
-        .enable_bit     = OMAP3430_EN_I2C2_SHIFT,
-        .clkdm_name     = "core_l4_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk i2c1_fck = {
-        .name           = "i2c_fck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .id             = 1,
-        .parent         = &core_96m_fck,
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
-        .enable_bit     = OMAP3430_EN_I2C1_SHIFT,
-        .clkdm_name     = "core_l4_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-/*
- * MCBSP 1 & 5 get their 96MHz clock from core_96m_fck;
- * MCBSP 2, 3, 4 get their 96MHz clock from per_96m_fck.
- */
-static const struct clksel_rate common_mcbsp_96m_rates[] = {
-        { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
-        { .div = 0 }
-};
-
-static const struct clksel_rate common_mcbsp_mcbsp_rates[] = {
-        { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
-        { .div = 0 }
-};
-
-static const struct clksel mcbsp_15_clksel[] = {
-        { .parent = &core_96m_fck, .rates = common_mcbsp_96m_rates },
-        { .parent = &mcbsp_clks,   .rates = common_mcbsp_mcbsp_rates },
-        { .parent = NULL }
-};
-
-static struct clk mcbsp5_fck = {
-        .name           = "mcbsp_fck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .id             = 5,
-        .init           = &omap2_init_clksel_parent,
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
-        .enable_bit     = OMAP3430_EN_MCBSP5_SHIFT,
-        .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
-        .clksel_mask    = OMAP2_MCBSP5_CLKS_MASK,
-        .clksel         = mcbsp_15_clksel,
-        .clkdm_name     = "core_l4_clkdm",
-        .recalc         = &omap2_clksel_recalc,
-};
-
-static struct clk mcbsp1_fck = {
-        .name           = "mcbsp_fck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .id             = 1,
-        .init           = &omap2_init_clksel_parent,
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
-        .enable_bit     = OMAP3430_EN_MCBSP1_SHIFT,
-        .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
-        .clksel_mask    = OMAP2_MCBSP1_CLKS_MASK,
-        .clksel         = mcbsp_15_clksel,
-        .clkdm_name     = "core_l4_clkdm",
-        .recalc         = &omap2_clksel_recalc,
-};
-
-/* CORE_48M_FCK-derived clocks */
-
-static struct clk core_48m_fck = {
-        .name           = "core_48m_fck",
-        .ops            = &clkops_null,
-        .parent         = &omap_48m_fck,
-        .clkdm_name     = "core_l4_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk mcspi4_fck = {
-        .name           = "mcspi_fck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .id             = 4,
-        .parent         = &core_48m_fck,
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
-        .enable_bit     = OMAP3430_EN_MCSPI4_SHIFT,
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk mcspi3_fck = {
-        .name           = "mcspi_fck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .id             = 3,
-        .parent         = &core_48m_fck,
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
-        .enable_bit     = OMAP3430_EN_MCSPI3_SHIFT,
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk mcspi2_fck = {
-        .name           = "mcspi_fck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .id             = 2,
-        .parent         = &core_48m_fck,
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
-        .enable_bit     = OMAP3430_EN_MCSPI2_SHIFT,
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk mcspi1_fck = {
-        .name           = "mcspi_fck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .id             = 1,
-        .parent         = &core_48m_fck,
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
-        .enable_bit     = OMAP3430_EN_MCSPI1_SHIFT,
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk uart2_fck = {
-        .name           = "uart2_fck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &core_48m_fck,
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
-        .enable_bit     = OMAP3430_EN_UART2_SHIFT,
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk uart1_fck = {
-        .name           = "uart1_fck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &core_48m_fck,
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
-        .enable_bit     = OMAP3430_EN_UART1_SHIFT,
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk fshostusb_fck = {
-        .name           = "fshostusb_fck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &core_48m_fck,
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
-        .enable_bit     = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
-        .recalc         = &followparent_recalc,
-};
-
-/* CORE_12M_FCK based clocks */
-
-static struct clk core_12m_fck = {
-        .name           = "core_12m_fck",
-        .ops            = &clkops_null,
-        .parent         = &omap_12m_fck,
-        .clkdm_name     = "core_l4_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk hdq_fck = {
-        .name           = "hdq_fck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &core_12m_fck,
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
-        .enable_bit     = OMAP3430_EN_HDQ_SHIFT,
-        .recalc         = &followparent_recalc,
-};
-
-/* DPLL3-derived clock */
-
-static const struct clksel_rate ssi_ssr_corex2_rates[] = {
-        { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
-        { .div = 2, .val = 2, .flags = RATE_IN_343X },
-        { .div = 3, .val = 3, .flags = RATE_IN_343X },
-        { .div = 4, .val = 4, .flags = RATE_IN_343X },
-        { .div = 6, .val = 6, .flags = RATE_IN_343X },
-        { .div = 8, .val = 8, .flags = RATE_IN_343X },
-        { .div = 0 }
-};
-
-static const struct clksel ssi_ssr_clksel[] = {
-        { .parent = &corex2_fck, .rates = ssi_ssr_corex2_rates },
-        { .parent = NULL }
-};
-
-static struct clk ssi_ssr_fck_3430es1 = {
-        .name           = "ssi_ssr_fck",
-        .ops            = &clkops_omap2_dflt,
-        .init           = &omap2_init_clksel_parent,
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
-        .enable_bit     = OMAP3430_EN_SSI_SHIFT,
-        .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
-        .clksel_mask    = OMAP3430_CLKSEL_SSI_MASK,
-        .clksel         = ssi_ssr_clksel,
-        .clkdm_name     = "core_l4_clkdm",
-        .recalc         = &omap2_clksel_recalc,
-};
-
-static struct clk ssi_ssr_fck_3430es2 = {
-        .name           = "ssi_ssr_fck",
-        .ops            = &clkops_omap3430es2_ssi_wait,
-        .init           = &omap2_init_clksel_parent,
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
-        .enable_bit     = OMAP3430_EN_SSI_SHIFT,
-        .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
-        .clksel_mask    = OMAP3430_CLKSEL_SSI_MASK,
-        .clksel         = ssi_ssr_clksel,
-        .clkdm_name     = "core_l4_clkdm",
-        .recalc         = &omap2_clksel_recalc,
-};
-
-static struct clk ssi_sst_fck_3430es1 = {
-        .name           = "ssi_sst_fck",
-        .ops            = &clkops_null,
-        .parent         = &ssi_ssr_fck_3430es1,
-        .fixed_div      = 2,
-        .recalc         = &omap2_fixed_divisor_recalc,
-};
-
-static struct clk ssi_sst_fck_3430es2 = {
-        .name           = "ssi_sst_fck",
-        .ops            = &clkops_null,
-        .parent         = &ssi_ssr_fck_3430es2,
-        .fixed_div      = 2,
-        .recalc         = &omap2_fixed_divisor_recalc,
-};
-
-
-
-/* CORE_L3_ICK based clocks */
-
-/*
- * XXX must add clk_enable/clk_disable for these if standard code won't
- * handle it
- */
-static struct clk core_l3_ick = {
-        .name           = "core_l3_ick",
-        .ops            = &clkops_null,
-        .parent         = &l3_ick,
-        .clkdm_name     = "core_l3_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk hsotgusb_ick_3430es1 = {
-        .name           = "hsotgusb_ick",
-        .ops            = &clkops_omap2_dflt,
-        .parent         = &core_l3_ick,
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
-        .enable_bit     = OMAP3430_EN_HSOTGUSB_SHIFT,
-        .clkdm_name     = "core_l3_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk hsotgusb_ick_3430es2 = {
-        .name           = "hsotgusb_ick",
-        .ops            = &clkops_omap3430es2_hsotgusb_wait,
-        .parent         = &core_l3_ick,
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
-        .enable_bit     = OMAP3430_EN_HSOTGUSB_SHIFT,
-        .clkdm_name     = "core_l3_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk sdrc_ick = {
-        .name           = "sdrc_ick",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &core_l3_ick,
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
-        .enable_bit     = OMAP3430_EN_SDRC_SHIFT,
-        .flags          = ENABLE_ON_INIT,
-        .clkdm_name     = "core_l3_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk gpmc_fck = {
-        .name           = "gpmc_fck",
-        .ops            = &clkops_null,
-        .parent         = &core_l3_ick,
-        .flags          = ENABLE_ON_INIT, /* huh? */
-        .clkdm_name     = "core_l3_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-/* SECURITY_L3_ICK based clocks */
-
-static struct clk security_l3_ick = {
-        .name           = "security_l3_ick",
-        .ops            = &clkops_null,
-        .parent         = &l3_ick,
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk pka_ick = {
-        .name           = "pka_ick",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &security_l3_ick,
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
-        .enable_bit     = OMAP3430_EN_PKA_SHIFT,
-        .recalc         = &followparent_recalc,
-};
-
-/* CORE_L4_ICK based clocks */
-
-static struct clk core_l4_ick = {
-        .name           = "core_l4_ick",
-        .ops            = &clkops_null,
-        .parent         = &l4_ick,
-        .clkdm_name     = "core_l4_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk usbtll_ick = {
-        .name           = "usbtll_ick",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &core_l4_ick,
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
-        .enable_bit     = OMAP3430ES2_EN_USBTLL_SHIFT,
-        .clkdm_name     = "core_l4_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk mmchs3_ick = {
-        .name           = "mmchs_ick",
-        .ops            = &clkops_omap2_dflt_wait,
-        .id             = 2,
-        .parent         = &core_l4_ick,
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
-        .enable_bit     = OMAP3430ES2_EN_MMC3_SHIFT,
-        .clkdm_name     = "core_l4_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-/* Intersystem Communication Registers - chassis mode only */
-static struct clk icr_ick = {
-        .name           = "icr_ick",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &core_l4_ick,
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
-        .enable_bit     = OMAP3430_EN_ICR_SHIFT,
-        .clkdm_name     = "core_l4_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk aes2_ick = {
-        .name           = "aes2_ick",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &core_l4_ick,
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
-        .enable_bit     = OMAP3430_EN_AES2_SHIFT,
-        .clkdm_name     = "core_l4_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk sha12_ick = {
-        .name           = "sha12_ick",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &core_l4_ick,
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
-        .enable_bit     = OMAP3430_EN_SHA12_SHIFT,
-        .clkdm_name     = "core_l4_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk des2_ick = {
-        .name           = "des2_ick",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &core_l4_ick,
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
-        .enable_bit     = OMAP3430_EN_DES2_SHIFT,
-        .clkdm_name     = "core_l4_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk mmchs2_ick = {
-        .name           = "mmchs_ick",
-        .ops            = &clkops_omap2_dflt_wait,
-        .id             = 1,
-        .parent         = &core_l4_ick,
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
-        .enable_bit     = OMAP3430_EN_MMC2_SHIFT,
-        .clkdm_name     = "core_l4_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk mmchs1_ick = {
-        .name           = "mmchs_ick",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &core_l4_ick,
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
-        .enable_bit     = OMAP3430_EN_MMC1_SHIFT,
-        .clkdm_name     = "core_l4_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk mspro_ick = {
-        .name           = "mspro_ick",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &core_l4_ick,
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
-        .enable_bit     = OMAP3430_EN_MSPRO_SHIFT,
-        .clkdm_name     = "core_l4_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk hdq_ick = {
-        .name           = "hdq_ick",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &core_l4_ick,
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
-        .enable_bit     = OMAP3430_EN_HDQ_SHIFT,
-        .clkdm_name     = "core_l4_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk mcspi4_ick = {
-        .name           = "mcspi_ick",
-        .ops            = &clkops_omap2_dflt_wait,
-        .id             = 4,
-        .parent         = &core_l4_ick,
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
-        .enable_bit     = OMAP3430_EN_MCSPI4_SHIFT,
-        .clkdm_name     = "core_l4_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk mcspi3_ick = {
-        .name           = "mcspi_ick",
-        .ops            = &clkops_omap2_dflt_wait,
-        .id             = 3,
-        .parent         = &core_l4_ick,
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
-        .enable_bit     = OMAP3430_EN_MCSPI3_SHIFT,
-        .clkdm_name     = "core_l4_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk mcspi2_ick = {
-        .name           = "mcspi_ick",
-        .ops            = &clkops_omap2_dflt_wait,
-        .id             = 2,
-        .parent         = &core_l4_ick,
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
-        .enable_bit     = OMAP3430_EN_MCSPI2_SHIFT,
-        .clkdm_name     = "core_l4_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk mcspi1_ick = {
-        .name           = "mcspi_ick",
-        .ops            = &clkops_omap2_dflt_wait,
-        .id             = 1,
-        .parent         = &core_l4_ick,
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
-        .enable_bit     = OMAP3430_EN_MCSPI1_SHIFT,
-        .clkdm_name     = "core_l4_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk i2c3_ick = {
-        .name           = "i2c_ick",
-        .ops            = &clkops_omap2_dflt_wait,
-        .id             = 3,
-        .parent         = &core_l4_ick,
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
-        .enable_bit     = OMAP3430_EN_I2C3_SHIFT,
-        .clkdm_name     = "core_l4_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk i2c2_ick = {
-        .name           = "i2c_ick",
-        .ops            = &clkops_omap2_dflt_wait,
-        .id             = 2,
-        .parent         = &core_l4_ick,
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
-        .enable_bit     = OMAP3430_EN_I2C2_SHIFT,
-        .clkdm_name     = "core_l4_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk i2c1_ick = {
-        .name           = "i2c_ick",
-        .ops            = &clkops_omap2_dflt_wait,
-        .id             = 1,
-        .parent         = &core_l4_ick,
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
-        .enable_bit     = OMAP3430_EN_I2C1_SHIFT,
-        .clkdm_name     = "core_l4_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk uart2_ick = {
-        .name           = "uart2_ick",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &core_l4_ick,
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
-        .enable_bit     = OMAP3430_EN_UART2_SHIFT,
-        .clkdm_name     = "core_l4_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk uart1_ick = {
-        .name           = "uart1_ick",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &core_l4_ick,
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
-        .enable_bit     = OMAP3430_EN_UART1_SHIFT,
-        .clkdm_name     = "core_l4_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk gpt11_ick = {
-        .name           = "gpt11_ick",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &core_l4_ick,
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
-        .enable_bit     = OMAP3430_EN_GPT11_SHIFT,
-        .clkdm_name     = "core_l4_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk gpt10_ick = {
-        .name           = "gpt10_ick",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &core_l4_ick,
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
-        .enable_bit     = OMAP3430_EN_GPT10_SHIFT,
-        .clkdm_name     = "core_l4_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk mcbsp5_ick = {
-        .name           = "mcbsp_ick",
-        .ops            = &clkops_omap2_dflt_wait,
-        .id             = 5,
-        .parent         = &core_l4_ick,
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
-        .enable_bit     = OMAP3430_EN_MCBSP5_SHIFT,
-        .clkdm_name     = "core_l4_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk mcbsp1_ick = {
-        .name           = "mcbsp_ick",
-        .ops            = &clkops_omap2_dflt_wait,
-        .id             = 1,
-        .parent         = &core_l4_ick,
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
-        .enable_bit     = OMAP3430_EN_MCBSP1_SHIFT,
-        .clkdm_name     = "core_l4_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk fac_ick = {
-        .name           = "fac_ick",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &core_l4_ick,
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
-        .enable_bit     = OMAP3430ES1_EN_FAC_SHIFT,
-        .clkdm_name     = "core_l4_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk mailboxes_ick = {
-        .name           = "mailboxes_ick",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &core_l4_ick,
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
-        .enable_bit     = OMAP3430_EN_MAILBOXES_SHIFT,
-        .clkdm_name     = "core_l4_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk omapctrl_ick = {
-        .name           = "omapctrl_ick",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &core_l4_ick,
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
-        .enable_bit     = OMAP3430_EN_OMAPCTRL_SHIFT,
-        .flags          = ENABLE_ON_INIT,
-        .recalc         = &followparent_recalc,
-};
-
-/* SSI_L4_ICK based clocks */
-
-static struct clk ssi_l4_ick = {
-        .name           = "ssi_l4_ick",
-        .ops            = &clkops_null,
-        .parent         = &l4_ick,
-        .clkdm_name     = "core_l4_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk ssi_ick_3430es1 = {
-        .name           = "ssi_ick",
-        .ops            = &clkops_omap2_dflt,
-        .parent         = &ssi_l4_ick,
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
-        .enable_bit     = OMAP3430_EN_SSI_SHIFT,
-        .clkdm_name     = "core_l4_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk ssi_ick_3430es2 = {
-        .name           = "ssi_ick",
-        .ops            = &clkops_omap3430es2_ssi_wait,
-        .parent         = &ssi_l4_ick,
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
-        .enable_bit     = OMAP3430_EN_SSI_SHIFT,
-        .clkdm_name     = "core_l4_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-/* REVISIT: Technically the TRM claims that this is CORE_CLK based,
- * but l4_ick makes more sense to me */
-
-static const struct clksel usb_l4_clksel[] = {
-        { .parent = &l4_ick, .rates = div2_rates },
-        { .parent = NULL },
-};
-
-static struct clk usb_l4_ick = {
-        .name           = "usb_l4_ick",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &l4_ick,
-        .init           = &omap2_init_clksel_parent,
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
-        .enable_bit     = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
-        .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
-        .clksel_mask    = OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK,
-        .clksel         = usb_l4_clksel,
-        .recalc         = &omap2_clksel_recalc,
-};
-
-/* SECURITY_L4_ICK2 based clocks */
-
-static struct clk security_l4_ick2 = {
-        .name           = "security_l4_ick2",
-        .ops            = &clkops_null,
-        .parent         = &l4_ick,
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk aes1_ick = {
-        .name           = "aes1_ick",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &security_l4_ick2,
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
-        .enable_bit     = OMAP3430_EN_AES1_SHIFT,
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk rng_ick = {
-        .name           = "rng_ick",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &security_l4_ick2,
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
-        .enable_bit     = OMAP3430_EN_RNG_SHIFT,
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk sha11_ick = {
-        .name           = "sha11_ick",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &security_l4_ick2,
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
-        .enable_bit     = OMAP3430_EN_SHA11_SHIFT,
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk des1_ick = {
-        .name           = "des1_ick",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &security_l4_ick2,
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
-        .enable_bit     = OMAP3430_EN_DES1_SHIFT,
-        .recalc         = &followparent_recalc,
-};
-
-/* DSS */
-static struct clk dss1_alwon_fck_3430es1 = {
-        .name           = "dss1_alwon_fck",
-        .ops            = &clkops_omap2_dflt,
-        .parent         = &dpll4_m4x2_ck,
-        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
-        .enable_bit     = OMAP3430_EN_DSS1_SHIFT,
-        .clkdm_name     = "dss_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk dss1_alwon_fck_3430es2 = {
-        .name           = "dss1_alwon_fck",
-        .ops            = &clkops_omap3430es2_dss_usbhost_wait,
-        .parent         = &dpll4_m4x2_ck,
-        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
-        .enable_bit     = OMAP3430_EN_DSS1_SHIFT,
-        .clkdm_name     = "dss_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk dss_tv_fck = {
-        .name           = "dss_tv_fck",
-        .ops            = &clkops_omap2_dflt,
-        .parent         = &omap_54m_fck,
-        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
-        .enable_bit     = OMAP3430_EN_TV_SHIFT,
-        .clkdm_name     = "dss_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk dss_96m_fck = {
-        .name           = "dss_96m_fck",
-        .ops            = &clkops_omap2_dflt,
-        .parent         = &omap_96m_fck,
-        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
-        .enable_bit     = OMAP3430_EN_TV_SHIFT,
-        .clkdm_name     = "dss_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk dss2_alwon_fck = {
-        .name           = "dss2_alwon_fck",
-        .ops            = &clkops_omap2_dflt,
-        .parent         = &sys_ck,
-        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
-        .enable_bit     = OMAP3430_EN_DSS2_SHIFT,
-        .clkdm_name     = "dss_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk dss_ick_3430es1 = {
-        /* Handles both L3 and L4 clocks */
-        .name           = "dss_ick",
-        .ops            = &clkops_omap2_dflt,
-        .parent         = &l4_ick,
-        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN),
-        .enable_bit     = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT,
-        .clkdm_name     = "dss_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk dss_ick_3430es2 = {
-        /* Handles both L3 and L4 clocks */
-        .name           = "dss_ick",
-        .ops            = &clkops_omap3430es2_dss_usbhost_wait,
-        .parent         = &l4_ick,
-        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN),
-        .enable_bit     = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT,
-        .clkdm_name     = "dss_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-/* CAM */
-
-static struct clk cam_mclk = {
-        .name           = "cam_mclk",
-        .ops            = &clkops_omap2_dflt,
-        .parent         = &dpll4_m5x2_ck,
-        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN),
-        .enable_bit     = OMAP3430_EN_CAM_SHIFT,
-        .clkdm_name     = "cam_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk cam_ick = {
-        /* Handles both L3 and L4 clocks */
-        .name           = "cam_ick",
-        .ops            = &clkops_omap2_dflt,
-        .parent         = &l4_ick,
-        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN),
-        .enable_bit     = OMAP3430_EN_CAM_SHIFT,
-        .clkdm_name     = "cam_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk csi2_96m_fck = {
-        .name           = "csi2_96m_fck",
-        .ops            = &clkops_omap2_dflt,
-        .parent         = &core_96m_fck,
-        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN),
-        .enable_bit     = OMAP3430_EN_CSI2_SHIFT,
-        .clkdm_name     = "cam_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-/* USBHOST - 3430ES2 only */
-
-static struct clk usbhost_120m_fck = {
-        .name           = "usbhost_120m_fck",
-        .ops            = &clkops_omap2_dflt,
-        .parent         = &dpll5_m2_ck,
-        .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
-        .enable_bit     = OMAP3430ES2_EN_USBHOST2_SHIFT,
-        .clkdm_name     = "usbhost_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk usbhost_48m_fck = {
-        .name           = "usbhost_48m_fck",
-        .ops            = &clkops_omap3430es2_dss_usbhost_wait,
-        .parent         = &omap_48m_fck,
-        .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
-        .enable_bit     = OMAP3430ES2_EN_USBHOST1_SHIFT,
-        .clkdm_name     = "usbhost_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk usbhost_ick = {
-        /* Handles both L3 and L4 clocks */
-        .name           = "usbhost_ick",
-        .ops            = &clkops_omap3430es2_dss_usbhost_wait,
-        .parent         = &l4_ick,
-        .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN),
-        .enable_bit     = OMAP3430ES2_EN_USBHOST_SHIFT,
-        .clkdm_name     = "usbhost_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-/* WKUP */
-
-static const struct clksel_rate usim_96m_rates[] = {
-        { .div = 2,  .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
-        { .div = 4,  .val = 4, .flags = RATE_IN_343X },
-        { .div = 8,  .val = 5, .flags = RATE_IN_343X },
-        { .div = 10, .val = 6, .flags = RATE_IN_343X },
-        { .div = 0 },
-};
-
-static const struct clksel_rate usim_120m_rates[] = {
-        { .div = 4,  .val = 7,  .flags = RATE_IN_343X | DEFAULT_RATE },
-        { .div = 8,  .val = 8,  .flags = RATE_IN_343X },
-        { .div = 16, .val = 9,  .flags = RATE_IN_343X },
-        { .div = 20, .val = 10, .flags = RATE_IN_343X },
-        { .div = 0 },
-};
-
-static const struct clksel usim_clksel[] = {
-        { .parent = &omap_96m_fck,      .rates = usim_96m_rates },
-        { .parent = &dpll5_m2_ck,       .rates = usim_120m_rates },
-        { .parent = &sys_ck,            .rates = div2_rates },
-        { .parent = NULL },
-};
-
-/* 3430ES2 only */
-static struct clk usim_fck = {
-        .name           = "usim_fck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .init           = &omap2_init_clksel_parent,
-        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
-        .enable_bit     = OMAP3430ES2_EN_USIMOCP_SHIFT,
-        .clksel_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
-        .clksel_mask    = OMAP3430ES2_CLKSEL_USIMOCP_MASK,
-        .clksel         = usim_clksel,
-        .recalc         = &omap2_clksel_recalc,
-};
-
-/* XXX should gpt1's clksel have wkup_32k_fck as the 32k opt? */
-static struct clk gpt1_fck = {
-        .name           = "gpt1_fck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .init           = &omap2_init_clksel_parent,
-        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
-        .enable_bit     = OMAP3430_EN_GPT1_SHIFT,
-        .clksel_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
-        .clksel_mask    = OMAP3430_CLKSEL_GPT1_MASK,
-        .clksel         = omap343x_gpt_clksel,
-        .clkdm_name     = "wkup_clkdm",
-        .recalc         = &omap2_clksel_recalc,
-};
-
-static struct clk wkup_32k_fck = {
-        .name           = "wkup_32k_fck",
-        .ops            = &clkops_null,
-        .parent         = &omap_32k_fck,
-        .clkdm_name     = "wkup_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk gpio1_dbck = {
-        .name           = "gpio1_dbck",
-        .ops            = &clkops_omap2_dflt,
-        .parent         = &wkup_32k_fck,
-        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
-        .enable_bit     = OMAP3430_EN_GPIO1_SHIFT,
-        .clkdm_name     = "wkup_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk wdt2_fck = {
-        .name           = "wdt2_fck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &wkup_32k_fck,
-        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
-        .enable_bit     = OMAP3430_EN_WDT2_SHIFT,
-        .clkdm_name     = "wkup_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk wkup_l4_ick = {
-        .name           = "wkup_l4_ick",
-        .ops            = &clkops_null,
-        .parent         = &sys_ck,
-        .clkdm_name     = "wkup_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-/* 3430ES2 only */
-/* Never specifically named in the TRM, so we have to infer a likely name */
-static struct clk usim_ick = {
-        .name           = "usim_ick",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &wkup_l4_ick,
-        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
-        .enable_bit     = OMAP3430ES2_EN_USIMOCP_SHIFT,
-        .clkdm_name     = "wkup_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk wdt2_ick = {
-        .name           = "wdt2_ick",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &wkup_l4_ick,
-        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
-        .enable_bit     = OMAP3430_EN_WDT2_SHIFT,
-        .clkdm_name     = "wkup_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk wdt1_ick = {
-        .name           = "wdt1_ick",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &wkup_l4_ick,
-        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
-        .enable_bit     = OMAP3430_EN_WDT1_SHIFT,
-        .clkdm_name     = "wkup_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk gpio1_ick = {
-        .name           = "gpio1_ick",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &wkup_l4_ick,
-        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
-        .enable_bit     = OMAP3430_EN_GPIO1_SHIFT,
-        .clkdm_name     = "wkup_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk omap_32ksync_ick = {
-        .name           = "omap_32ksync_ick",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &wkup_l4_ick,
-        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
-        .enable_bit     = OMAP3430_EN_32KSYNC_SHIFT,
-        .clkdm_name     = "wkup_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-/* XXX This clock no longer exists in 3430 TRM rev F */
-static struct clk gpt12_ick = {
-        .name           = "gpt12_ick",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &wkup_l4_ick,
-        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
-        .enable_bit     = OMAP3430_EN_GPT12_SHIFT,
-        .clkdm_name     = "wkup_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk gpt1_ick = {
-        .name           = "gpt1_ick",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &wkup_l4_ick,
-        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
-        .enable_bit     = OMAP3430_EN_GPT1_SHIFT,
-        .clkdm_name     = "wkup_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-
-
-/* PER clock domain */
-
-static struct clk per_96m_fck = {
-        .name           = "per_96m_fck",
-        .ops            = &clkops_null,
-        .parent         = &omap_96m_alwon_fck,
-        .clkdm_name     = "per_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk per_48m_fck = {
-        .name           = "per_48m_fck",
-        .ops            = &clkops_null,
-        .parent         = &omap_48m_fck,
-        .clkdm_name     = "per_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk uart3_fck = {
-        .name           = "uart3_fck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &per_48m_fck,
-        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
-        .enable_bit     = OMAP3430_EN_UART3_SHIFT,
-        .clkdm_name     = "per_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk gpt2_fck = {
-        .name           = "gpt2_fck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .init           = &omap2_init_clksel_parent,
-        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
-        .enable_bit     = OMAP3430_EN_GPT2_SHIFT,
-        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
-        .clksel_mask    = OMAP3430_CLKSEL_GPT2_MASK,
-        .clksel         = omap343x_gpt_clksel,
-        .clkdm_name     = "per_clkdm",
-        .recalc         = &omap2_clksel_recalc,
-};
-
-static struct clk gpt3_fck = {
-        .name           = "gpt3_fck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .init           = &omap2_init_clksel_parent,
-        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
-        .enable_bit     = OMAP3430_EN_GPT3_SHIFT,
-        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
-        .clksel_mask    = OMAP3430_CLKSEL_GPT3_MASK,
-        .clksel         = omap343x_gpt_clksel,
-        .clkdm_name     = "per_clkdm",
-        .recalc         = &omap2_clksel_recalc,
-};
-
-static struct clk gpt4_fck = {
-        .name           = "gpt4_fck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .init           = &omap2_init_clksel_parent,
-        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
-        .enable_bit     = OMAP3430_EN_GPT4_SHIFT,
-        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
-        .clksel_mask    = OMAP3430_CLKSEL_GPT4_MASK,
-        .clksel         = omap343x_gpt_clksel,
-        .clkdm_name     = "per_clkdm",
-        .recalc         = &omap2_clksel_recalc,
-};
-
-static struct clk gpt5_fck = {
-        .name           = "gpt5_fck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .init           = &omap2_init_clksel_parent,
-        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
-        .enable_bit     = OMAP3430_EN_GPT5_SHIFT,
-        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
-        .clksel_mask    = OMAP3430_CLKSEL_GPT5_MASK,
-        .clksel         = omap343x_gpt_clksel,
-        .clkdm_name     = "per_clkdm",
-        .recalc         = &omap2_clksel_recalc,
-};
-
-static struct clk gpt6_fck = {
-        .name           = "gpt6_fck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .init           = &omap2_init_clksel_parent,
-        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
-        .enable_bit     = OMAP3430_EN_GPT6_SHIFT,
-        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
-        .clksel_mask    = OMAP3430_CLKSEL_GPT6_MASK,
-        .clksel         = omap343x_gpt_clksel,
-        .clkdm_name     = "per_clkdm",
-        .recalc         = &omap2_clksel_recalc,
-};
-
-static struct clk gpt7_fck = {
-        .name           = "gpt7_fck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .init           = &omap2_init_clksel_parent,
-        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
-        .enable_bit     = OMAP3430_EN_GPT7_SHIFT,
-        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
-        .clksel_mask    = OMAP3430_CLKSEL_GPT7_MASK,
-        .clksel         = omap343x_gpt_clksel,
-        .clkdm_name     = "per_clkdm",
-        .recalc         = &omap2_clksel_recalc,
-};
-
-static struct clk gpt8_fck = {
-        .name           = "gpt8_fck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .init           = &omap2_init_clksel_parent,
-        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
-        .enable_bit     = OMAP3430_EN_GPT8_SHIFT,
-        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
-        .clksel_mask    = OMAP3430_CLKSEL_GPT8_MASK,
-        .clksel         = omap343x_gpt_clksel,
-        .clkdm_name     = "per_clkdm",
-        .recalc         = &omap2_clksel_recalc,
-};
-
-static struct clk gpt9_fck = {
-        .name           = "gpt9_fck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .init           = &omap2_init_clksel_parent,
-        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
-        .enable_bit     = OMAP3430_EN_GPT9_SHIFT,
-        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
-        .clksel_mask    = OMAP3430_CLKSEL_GPT9_MASK,
-        .clksel         = omap343x_gpt_clksel,
-        .clkdm_name     = "per_clkdm",
-        .recalc         = &omap2_clksel_recalc,
-};
-
-static struct clk per_32k_alwon_fck = {
-        .name           = "per_32k_alwon_fck",
-        .ops            = &clkops_null,
-        .parent         = &omap_32k_fck,
-        .clkdm_name     = "per_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk gpio6_dbck = {
-        .name           = "gpio6_dbck",
-        .ops            = &clkops_omap2_dflt,
-        .parent         = &per_32k_alwon_fck,
-        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
-        .enable_bit     = OMAP3430_EN_GPIO6_SHIFT,
-        .clkdm_name     = "per_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk gpio5_dbck = {
-        .name           = "gpio5_dbck",
-        .ops            = &clkops_omap2_dflt,
-        .parent         = &per_32k_alwon_fck,
-        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
-        .enable_bit     = OMAP3430_EN_GPIO5_SHIFT,
-        .clkdm_name     = "per_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk gpio4_dbck = {
-        .name           = "gpio4_dbck",
-        .ops            = &clkops_omap2_dflt,
-        .parent         = &per_32k_alwon_fck,
-        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
-        .enable_bit     = OMAP3430_EN_GPIO4_SHIFT,
-        .clkdm_name     = "per_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk gpio3_dbck = {
-        .name           = "gpio3_dbck",
-        .ops            = &clkops_omap2_dflt,
-        .parent         = &per_32k_alwon_fck,
-        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
-        .enable_bit     = OMAP3430_EN_GPIO3_SHIFT,
-        .clkdm_name     = "per_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk gpio2_dbck = {
-        .name           = "gpio2_dbck",
-        .ops            = &clkops_omap2_dflt,
-        .parent         = &per_32k_alwon_fck,
-        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
-        .enable_bit     = OMAP3430_EN_GPIO2_SHIFT,
-        .clkdm_name     = "per_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk wdt3_fck = {
-        .name           = "wdt3_fck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &per_32k_alwon_fck,
-        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
-        .enable_bit     = OMAP3430_EN_WDT3_SHIFT,
-        .clkdm_name     = "per_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk per_l4_ick = {
-        .name           = "per_l4_ick",
-        .ops            = &clkops_null,
-        .parent         = &l4_ick,
-        .clkdm_name     = "per_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk gpio6_ick = {
-        .name           = "gpio6_ick",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &per_l4_ick,
-        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
-        .enable_bit     = OMAP3430_EN_GPIO6_SHIFT,
-        .clkdm_name     = "per_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk gpio5_ick = {
-        .name           = "gpio5_ick",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &per_l4_ick,
-        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
-        .enable_bit     = OMAP3430_EN_GPIO5_SHIFT,
-        .clkdm_name     = "per_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk gpio4_ick = {
-        .name           = "gpio4_ick",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &per_l4_ick,
-        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
-        .enable_bit     = OMAP3430_EN_GPIO4_SHIFT,
-        .clkdm_name     = "per_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk gpio3_ick = {
-        .name           = "gpio3_ick",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &per_l4_ick,
-        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
-        .enable_bit     = OMAP3430_EN_GPIO3_SHIFT,
-        .clkdm_name     = "per_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk gpio2_ick = {
-        .name           = "gpio2_ick",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &per_l4_ick,
-        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
-        .enable_bit     = OMAP3430_EN_GPIO2_SHIFT,
-        .clkdm_name     = "per_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk wdt3_ick = {
-        .name           = "wdt3_ick",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &per_l4_ick,
-        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
-        .enable_bit     = OMAP3430_EN_WDT3_SHIFT,
-        .clkdm_name     = "per_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk uart3_ick = {
-        .name           = "uart3_ick",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &per_l4_ick,
-        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
-        .enable_bit     = OMAP3430_EN_UART3_SHIFT,
-        .clkdm_name     = "per_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk gpt9_ick = {
-        .name           = "gpt9_ick",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &per_l4_ick,
-        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
-        .enable_bit     = OMAP3430_EN_GPT9_SHIFT,
-        .clkdm_name     = "per_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk gpt8_ick = {
-        .name           = "gpt8_ick",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &per_l4_ick,
-        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
-        .enable_bit     = OMAP3430_EN_GPT8_SHIFT,
-        .clkdm_name     = "per_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk gpt7_ick = {
-        .name           = "gpt7_ick",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &per_l4_ick,
-        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
-        .enable_bit     = OMAP3430_EN_GPT7_SHIFT,
-        .clkdm_name     = "per_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk gpt6_ick = {
-        .name           = "gpt6_ick",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &per_l4_ick,
-        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
-        .enable_bit     = OMAP3430_EN_GPT6_SHIFT,
-        .clkdm_name     = "per_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk gpt5_ick = {
-        .name           = "gpt5_ick",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &per_l4_ick,
-        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
-        .enable_bit     = OMAP3430_EN_GPT5_SHIFT,
-        .clkdm_name     = "per_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk gpt4_ick = {
-        .name           = "gpt4_ick",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &per_l4_ick,
-        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
-        .enable_bit     = OMAP3430_EN_GPT4_SHIFT,
-        .clkdm_name     = "per_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk gpt3_ick = {
-        .name           = "gpt3_ick",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &per_l4_ick,
-        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
-        .enable_bit     = OMAP3430_EN_GPT3_SHIFT,
-        .clkdm_name     = "per_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk gpt2_ick = {
-        .name           = "gpt2_ick",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &per_l4_ick,
-        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
-        .enable_bit     = OMAP3430_EN_GPT2_SHIFT,
-        .clkdm_name     = "per_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk mcbsp2_ick = {
-        .name           = "mcbsp_ick",
-        .ops            = &clkops_omap2_dflt_wait,
-        .id             = 2,
-        .parent         = &per_l4_ick,
-        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
-        .enable_bit     = OMAP3430_EN_MCBSP2_SHIFT,
-        .clkdm_name     = "per_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk mcbsp3_ick = {
-        .name           = "mcbsp_ick",
-        .ops            = &clkops_omap2_dflt_wait,
-        .id             = 3,
-        .parent         = &per_l4_ick,
-        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
-        .enable_bit     = OMAP3430_EN_MCBSP3_SHIFT,
-        .clkdm_name     = "per_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk mcbsp4_ick = {
-        .name           = "mcbsp_ick",
-        .ops            = &clkops_omap2_dflt_wait,
-        .id             = 4,
-        .parent         = &per_l4_ick,
-        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
-        .enable_bit     = OMAP3430_EN_MCBSP4_SHIFT,
-        .clkdm_name     = "per_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-static const struct clksel mcbsp_234_clksel[] = {
-        { .parent = &core_96m_fck, .rates = common_mcbsp_96m_rates },
-        { .parent = &mcbsp_clks,   .rates = common_mcbsp_mcbsp_rates },
-        { .parent = NULL }
-};
-
-static struct clk mcbsp2_fck = {
-        .name           = "mcbsp_fck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .id             = 2,
-        .init           = &omap2_init_clksel_parent,
-        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
-        .enable_bit     = OMAP3430_EN_MCBSP2_SHIFT,
-        .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
-        .clksel_mask    = OMAP2_MCBSP2_CLKS_MASK,
-        .clksel         = mcbsp_234_clksel,
-        .clkdm_name     = "per_clkdm",
-        .recalc         = &omap2_clksel_recalc,
-};
-
-static struct clk mcbsp3_fck = {
-        .name           = "mcbsp_fck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .id             = 3,
-        .init           = &omap2_init_clksel_parent,
-        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
-        .enable_bit     = OMAP3430_EN_MCBSP3_SHIFT,
-        .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
-        .clksel_mask    = OMAP2_MCBSP3_CLKS_MASK,
-        .clksel         = mcbsp_234_clksel,
-        .clkdm_name     = "per_clkdm",
-        .recalc         = &omap2_clksel_recalc,
-};
-
-static struct clk mcbsp4_fck = {
-        .name           = "mcbsp_fck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .id             = 4,
-        .init           = &omap2_init_clksel_parent,
-        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
-        .enable_bit     = OMAP3430_EN_MCBSP4_SHIFT,
-        .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
-        .clksel_mask    = OMAP2_MCBSP4_CLKS_MASK,
-        .clksel         = mcbsp_234_clksel,
-        .clkdm_name     = "per_clkdm",
-        .recalc         = &omap2_clksel_recalc,
-};
-
-/* EMU clocks */
-
-/* More information: ARM Cortex-A8 Technical Reference Manual, sect 10.1 */
-
-static const struct clksel_rate emu_src_sys_rates[] = {
-        { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
-        { .div = 0 },
-};
-
-static const struct clksel_rate emu_src_core_rates[] = {
-        { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
-        { .div = 0 },
-};
-
-static const struct clksel_rate emu_src_per_rates[] = {
-        { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
-        { .div = 0 },
-};
-
-static const struct clksel_rate emu_src_mpu_rates[] = {
-        { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
-        { .div = 0 },
-};
-
-static const struct clksel emu_src_clksel[] = {
-        { .parent = &sys_ck,            .rates = emu_src_sys_rates },
-        { .parent = &emu_core_alwon_ck, .rates = emu_src_core_rates },
-        { .parent = &emu_per_alwon_ck,  .rates = emu_src_per_rates },
-        { .parent = &emu_mpu_alwon_ck,  .rates = emu_src_mpu_rates },
-        { .parent = NULL },
-};
-
-/*
- * Like the clkout_src clocks, emu_src_clk is a virtual clock, existing only
- * to switch the source of some of the EMU clocks.
- * XXX Are there CLKEN bits for these EMU clks?
+ * Copyright (C) 2007-2009 Texas Instruments, Inc.
+ * Copyright (C) 2007-2009 Nokia Corporation
  */
-static struct clk emu_src_ck = {
-        .name           = "emu_src_ck",
-        .ops            = &clkops_null,
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
-        .clksel_mask    = OMAP3430_MUX_CTRL_MASK,
-        .clksel         = emu_src_clksel,
-        .clkdm_name     = "emu_clkdm",
-        .recalc         = &omap2_clksel_recalc,
-};
-
-static const struct clksel_rate pclk_emu_rates[] = {
-        { .div = 2, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
-        { .div = 3, .val = 3, .flags = RATE_IN_343X },
-        { .div = 4, .val = 4, .flags = RATE_IN_343X },
-        { .div = 6, .val = 6, .flags = RATE_IN_343X },
-        { .div = 0 },
-};
-
-static const struct clksel pclk_emu_clksel[] = {
-        { .parent = &emu_src_ck, .rates = pclk_emu_rates },
-        { .parent = NULL },
-};
-
-static struct clk pclk_fck = {
-        .name           = "pclk_fck",
-        .ops            = &clkops_null,
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
-        .clksel_mask    = OMAP3430_CLKSEL_PCLK_MASK,
-        .clksel         = pclk_emu_clksel,
-        .clkdm_name     = "emu_clkdm",
-        .recalc         = &omap2_clksel_recalc,
-};
-
-static const struct clksel_rate pclkx2_emu_rates[] = {
-        { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
-        { .div = 2, .val = 2, .flags = RATE_IN_343X },
-        { .div = 3, .val = 3, .flags = RATE_IN_343X },
-        { .div = 0 },
-};
-
-static const struct clksel pclkx2_emu_clksel[] = {
-        { .parent = &emu_src_ck, .rates = pclkx2_emu_rates },
-        { .parent = NULL },
-};
-
-static struct clk pclkx2_fck = {
-        .name           = "pclkx2_fck",
-        .ops            = &clkops_null,
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
-        .clksel_mask    = OMAP3430_CLKSEL_PCLKX2_MASK,
-        .clksel         = pclkx2_emu_clksel,
-        .clkdm_name     = "emu_clkdm",
-        .recalc         = &omap2_clksel_recalc,
-};
-
-static const struct clksel atclk_emu_clksel[] = {
-        { .parent = &emu_src_ck, .rates = div2_rates },
-        { .parent = NULL },
-};
-
-static struct clk atclk_fck = {
-        .name           = "atclk_fck",
-        .ops            = &clkops_null,
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
-        .clksel_mask    = OMAP3430_CLKSEL_ATCLK_MASK,
-        .clksel         = atclk_emu_clksel,
-        .clkdm_name     = "emu_clkdm",
-        .recalc         = &omap2_clksel_recalc,
-};
-
-static struct clk traceclk_src_fck = {
-        .name           = "traceclk_src_fck",
-        .ops            = &clkops_null,
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
-        .clksel_mask    = OMAP3430_TRACE_MUX_CTRL_MASK,
-        .clksel         = emu_src_clksel,
-        .clkdm_name     = "emu_clkdm",
-        .recalc         = &omap2_clksel_recalc,
-};
-
-static const struct clksel_rate traceclk_rates[] = {
-        { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
-        { .div = 2, .val = 2, .flags = RATE_IN_343X },
-        { .div = 4, .val = 4, .flags = RATE_IN_343X },
-        { .div = 0 },
-};
-
-static const struct clksel traceclk_clksel[] = {
-        { .parent = &traceclk_src_fck, .rates = traceclk_rates },
-        { .parent = NULL },
-};
-
-static struct clk traceclk_fck = {
-        .name           = "traceclk_fck",
-        .ops            = &clkops_null,
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
-        .clksel_mask    = OMAP3430_CLKSEL_TRACECLK_MASK,
-        .clksel         = traceclk_clksel,
-        .clkdm_name     = "emu_clkdm",
-        .recalc         = &omap2_clksel_recalc,
-};
-
-/* SR clocks */
-
-/* SmartReflex fclk (VDD1) */
-static struct clk sr1_fck = {
-        .name           = "sr1_fck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &sys_ck,
-        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
-        .enable_bit     = OMAP3430_EN_SR1_SHIFT,
-        .recalc         = &followparent_recalc,
-};
-
-/* SmartReflex fclk (VDD2) */
-static struct clk sr2_fck = {
-        .name           = "sr2_fck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &sys_ck,
-        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
-        .enable_bit     = OMAP3430_EN_SR2_SHIFT,
-        .recalc         = &followparent_recalc,
-};
 
-static struct clk sr_l4_ick = {
-        .name           = "sr_l4_ick",
-        .ops            = &clkops_null, /* RMK: missing? */
-        .parent         = &l4_ick,
-        .clkdm_name     = "core_l4_clkdm",
-        .recalc         = &followparent_recalc,
-};
+#ifndef __ARCH_ARM_MACH_OMAP2_CLOCK_34XX_H
+#define __ARCH_ARM_MACH_OMAP2_CLOCK_34XX_H
 
-/* SECURE_32K_FCK clocks */
+int omap3_dpll4_set_rate(struct clk *clk, unsigned long rate);
+int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate);
+void omap3_clk_lock_dpll5(void);
 
-static struct clk gpt12_fck = {
-        .name           = "gpt12_fck",
-        .ops            = &clkops_null,
-        .parent         = &secure_32k_fck,
-        .recalc         = &followparent_recalc,
-};
+extern struct clk *sdrc_ick_p;
+extern struct clk *arm_fck_p;
 
-static struct clk wdt1_fck = {
-        .name           = "wdt1_fck",
-        .ops            = &clkops_null,
-        .parent         = &secure_32k_fck,
-        .recalc         = &followparent_recalc,
-};
+/* OMAP34xx-specific clkops */
+extern const struct clkops clkops_omap3430es2_ssi_wait;
+extern const struct clkops clkops_omap3430es2_hsotgusb_wait;
+extern const struct clkops clkops_omap3430es2_dss_usbhost_wait;
+extern const struct clkops clkops_noncore_dpll_ops;
 
 #endif
diff --git a/arch/arm/mach-omap2/clock34xx_data.c b/arch/arm/mach-omap2/clock34xx_data.c
new file mode 100644
index 000000000000..8bdcc9cc7f9a
--- /dev/null
+++ b/arch/arm/mach-omap2/clock34xx_data.c
@@ -0,0 +1,3289 @@
+/*
+ * OMAP3 clock data
+ *
+ * Copyright (C) 2007-2009 Texas Instruments, Inc.
+ * Copyright (C) 2007-2009 Nokia Corporation
+ *
+ * Written by Paul Walmsley
+ * With many device clock fixes by Kevin Hilman and Jouni Högander
+ * DPLL bypass clock support added by Roman Tereshonkov
+ *
+ */
+
+/*
+ * Virtual clocks are introduced as convenient tools.
+ * They are sources for other clocks and not supposed
+ * to be requested from drivers directly.
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/clk.h>
+
+#include <plat/control.h>
+#include <plat/clkdev_omap.h>
+
+#include "clock.h"
+#include "clock34xx.h"
+#include "cm.h"
+#include "cm-regbits-34xx.h"
+#include "prm.h"
+#include "prm-regbits-34xx.h"
+
+/*
+ * clocks
+ */
+
+#define OMAP_CM_REGADDR         OMAP34XX_CM_REGADDR
+
+/* Maximum DPLL multiplier, divider values for OMAP3 */
+#define OMAP3_MAX_DPLL_MULT             2048
+#define OMAP3_MAX_DPLL_DIV              128
+
+/*
+ * DPLL1 supplies clock to the MPU.
+ * DPLL2 supplies clock to the IVA2.
+ * DPLL3 supplies CORE domain clocks.
+ * DPLL4 supplies peripheral clocks.
+ * DPLL5 supplies other peripheral clocks (USBHOST, USIM).
+ */
+
+/* Forward declarations for DPLL bypass clocks */
+static struct clk dpll1_fck;
+static struct clk dpll2_fck;
+
+/* PRM CLOCKS */
+
+/* According to timer32k.c, this is a 32768Hz clock, not a 32000Hz clock. */
+static struct clk omap_32k_fck = {
+        .name           = "omap_32k_fck",
+        .ops            = &clkops_null,
+        .rate           = 32768,
+        .flags          = RATE_FIXED,
+};
+
+static struct clk secure_32k_fck = {
+        .name           = "secure_32k_fck",
+        .ops            = &clkops_null,
+        .rate           = 32768,
+        .flags          = RATE_FIXED,
+};
+
+/* Virtual source clocks for osc_sys_ck */
+static struct clk virt_12m_ck = {
+        .name           = "virt_12m_ck",
+        .ops            = &clkops_null,
+        .rate           = 12000000,
+        .flags          = RATE_FIXED,
+};
+
+static struct clk virt_13m_ck = {
+        .name           = "virt_13m_ck",
+        .ops            = &clkops_null,
+        .rate           = 13000000,
+        .flags          = RATE_FIXED,
+};
+
+static struct clk virt_16_8m_ck = {
+        .name           = "virt_16_8m_ck",
+        .ops            = &clkops_null,
+        .rate           = 16800000,
+        .flags          = RATE_FIXED,
+};
+
+static struct clk virt_19_2m_ck = {
+        .name           = "virt_19_2m_ck",
+        .ops            = &clkops_null,
+        .rate           = 19200000,
+        .flags          = RATE_FIXED,
+};
+
+static struct clk virt_26m_ck = {
+        .name           = "virt_26m_ck",
+        .ops            = &clkops_null,
+        .rate           = 26000000,
+        .flags          = RATE_FIXED,
+};
+
+static struct clk virt_38_4m_ck = {
+        .name           = "virt_38_4m_ck",
+        .ops            = &clkops_null,
+        .rate           = 38400000,
+        .flags          = RATE_FIXED,
+};
+
+static const struct clksel_rate osc_sys_12m_rates[] = {
+        { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
+        { .div = 0 }
+};
+
+static const struct clksel_rate osc_sys_13m_rates[] = {
+        { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
+        { .div = 0 }
+};
+
+static const struct clksel_rate osc_sys_16_8m_rates[] = {
+        { .div = 1, .val = 5, .flags = RATE_IN_3430ES2 | DEFAULT_RATE },
+        { .div = 0 }
+};
+
+static const struct clksel_rate osc_sys_19_2m_rates[] = {
+        { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
+        { .div = 0 }
+};
+
+static const struct clksel_rate osc_sys_26m_rates[] = {
+        { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
+        { .div = 0 }
+};
+
+static const struct clksel_rate osc_sys_38_4m_rates[] = {
+        { .div = 1, .val = 4, .flags = RATE_IN_343X | DEFAULT_RATE },
+        { .div = 0 }
+};
+
+static const struct clksel osc_sys_clksel[] = {
+        { .parent = &virt_12m_ck,   .rates = osc_sys_12m_rates },
+        { .parent = &virt_13m_ck,   .rates = osc_sys_13m_rates },
+        { .parent = &virt_16_8m_ck, .rates = osc_sys_16_8m_rates },
+        { .parent = &virt_19_2m_ck, .rates = osc_sys_19_2m_rates },
+        { .parent = &virt_26m_ck,   .rates = osc_sys_26m_rates },
+        { .parent = &virt_38_4m_ck, .rates = osc_sys_38_4m_rates },
+        { .parent = NULL },
+};
+
+/* Oscillator clock */
+/* 12, 13, 16.8, 19.2, 26, or 38.4 MHz */
+static struct clk osc_sys_ck = {
+        .name           = "osc_sys_ck",
+        .ops            = &clkops_null,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP3430_PRM_CLKSEL,
+        .clksel_mask    = OMAP3430_SYS_CLKIN_SEL_MASK,
+        .clksel         = osc_sys_clksel,
+        /* REVISIT: deal with autoextclkmode? */
+        .flags          = RATE_FIXED,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static const struct clksel_rate div2_rates[] = {
+        { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
+        { .div = 2, .val = 2, .flags = RATE_IN_343X },
+        { .div = 0 }
+};
+
+static const struct clksel sys_clksel[] = {
+        { .parent = &osc_sys_ck, .rates = div2_rates },
+        { .parent = NULL }
+};
+
+/* Latency: this clock is only enabled after PRM_CLKSETUP.SETUP_TIME */
+/* Feeds DPLLs - divided first by PRM_CLKSRC_CTRL.SYSCLKDIV? */
+static struct clk sys_ck = {
+        .name           = "sys_ck",
+        .ops            = &clkops_null,
+        .parent         = &osc_sys_ck,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP3430_PRM_CLKSRC_CTRL,
+        .clksel_mask    = OMAP_SYSCLKDIV_MASK,
+        .clksel         = sys_clksel,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static struct clk sys_altclk = {
+        .name           = "sys_altclk",
+        .ops            = &clkops_null,
+};
+
+/* Optional external clock input for some McBSPs */
+static struct clk mcbsp_clks = {
+        .name           = "mcbsp_clks",
+        .ops            = &clkops_null,
+};
+
+/* PRM EXTERNAL CLOCK OUTPUT */
+
+static struct clk sys_clkout1 = {
+        .name           = "sys_clkout1",
+        .ops            = &clkops_omap2_dflt,
+        .parent         = &osc_sys_ck,
+        .enable_reg     = OMAP3430_PRM_CLKOUT_CTRL,
+        .enable_bit     = OMAP3430_CLKOUT_EN_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+/* DPLLS */
+
+/* CM CLOCKS */
+
+static const struct clksel_rate div16_dpll_rates[] = {
+        { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
+        { .div = 2, .val = 2, .flags = RATE_IN_343X },
+        { .div = 3, .val = 3, .flags = RATE_IN_343X },
+        { .div = 4, .val = 4, .flags = RATE_IN_343X },
+        { .div = 5, .val = 5, .flags = RATE_IN_343X },
+        { .div = 6, .val = 6, .flags = RATE_IN_343X },
+        { .div = 7, .val = 7, .flags = RATE_IN_343X },
+        { .div = 8, .val = 8, .flags = RATE_IN_343X },
+        { .div = 9, .val = 9, .flags = RATE_IN_343X },
+        { .div = 10, .val = 10, .flags = RATE_IN_343X },
+        { .div = 11, .val = 11, .flags = RATE_IN_343X },
+        { .div = 12, .val = 12, .flags = RATE_IN_343X },
+        { .div = 13, .val = 13, .flags = RATE_IN_343X },
+        { .div = 14, .val = 14, .flags = RATE_IN_343X },
+        { .div = 15, .val = 15, .flags = RATE_IN_343X },
+        { .div = 16, .val = 16, .flags = RATE_IN_343X },
+        { .div = 0 }
+};
+
+/* DPLL1 */
+/* MPU clock source */
+/* Type: DPLL */
+static struct dpll_data dpll1_dd = {
+        .mult_div1_reg  = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
+        .mult_mask      = OMAP3430_MPU_DPLL_MULT_MASK,
+        .div1_mask      = OMAP3430_MPU_DPLL_DIV_MASK,
+        .clk_bypass     = &dpll1_fck,
+        .clk_ref        = &sys_ck,
+        .freqsel_mask   = OMAP3430_MPU_DPLL_FREQSEL_MASK,
+        .control_reg    = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKEN_PLL),
+        .enable_mask    = OMAP3430_EN_MPU_DPLL_MASK,
+        .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
+        .auto_recal_bit = OMAP3430_EN_MPU_DPLL_DRIFTGUARD_SHIFT,
+        .recal_en_bit   = OMAP3430_MPU_DPLL_RECAL_EN_SHIFT,
+        .recal_st_bit   = OMAP3430_MPU_DPLL_ST_SHIFT,
+        .autoidle_reg   = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_AUTOIDLE_PLL),
+        .autoidle_mask  = OMAP3430_AUTO_MPU_DPLL_MASK,
+        .idlest_reg     = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
+        .idlest_mask    = OMAP3430_ST_MPU_CLK_MASK,
+        .max_multiplier = OMAP3_MAX_DPLL_MULT,
+        .min_divider    = 1,
+        .max_divider    = OMAP3_MAX_DPLL_DIV,
+        .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
+};
+
+static struct clk dpll1_ck = {
+        .name           = "dpll1_ck",
+        .ops            = &clkops_null,
+        .parent         = &sys_ck,
+        .dpll_data      = &dpll1_dd,
+        .round_rate     = &omap2_dpll_round_rate,
+        .set_rate       = &omap3_noncore_dpll_set_rate,
+        .clkdm_name     = "dpll1_clkdm",
+        .recalc         = &omap3_dpll_recalc,
+};
+
+/*
+ * This virtual clock provides the CLKOUTX2 output from the DPLL if the
+ * DPLL isn't bypassed.
+ */
+static struct clk dpll1_x2_ck = {
+        .name           = "dpll1_x2_ck",
+        .ops            = &clkops_null,
+        .parent         = &dpll1_ck,
+        .clkdm_name     = "dpll1_clkdm",
+        .recalc         = &omap3_clkoutx2_recalc,
+};
+
+/* On DPLL1, unlike other DPLLs, the divider is downstream from CLKOUTX2 */
+static const struct clksel div16_dpll1_x2m2_clksel[] = {
+        { .parent = &dpll1_x2_ck, .rates = div16_dpll_rates },
+        { .parent = NULL }
+};
+
+/*
+ * Does not exist in the TRM - needed to separate the M2 divider from
+ * bypass selection in mpu_ck
+ */
+static struct clk dpll1_x2m2_ck = {
+        .name           = "dpll1_x2m2_ck",
+        .ops            = &clkops_null,
+        .parent         = &dpll1_x2_ck,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL),
+        .clksel_mask    = OMAP3430_MPU_DPLL_CLKOUT_DIV_MASK,
+        .clksel         = div16_dpll1_x2m2_clksel,
+        .clkdm_name     = "dpll1_clkdm",
+        .recalc         = &omap2_clksel_recalc,
+};
+
+/* DPLL2 */
+/* IVA2 clock source */
+/* Type: DPLL */
+
+static struct dpll_data dpll2_dd = {
+        .mult_div1_reg  = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
+        .mult_mask      = OMAP3430_IVA2_DPLL_MULT_MASK,
+        .div1_mask      = OMAP3430_IVA2_DPLL_DIV_MASK,
+        .clk_bypass     = &dpll2_fck,
+        .clk_ref        = &sys_ck,
+        .freqsel_mask   = OMAP3430_IVA2_DPLL_FREQSEL_MASK,
+        .control_reg    = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKEN_PLL),
+        .enable_mask    = OMAP3430_EN_IVA2_DPLL_MASK,
+        .modes          = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED) |
+                                (1 << DPLL_LOW_POWER_BYPASS),
+        .auto_recal_bit = OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT,
+        .recal_en_bit   = OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_SHIFT,
+        .recal_st_bit   = OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_SHIFT,
+        .autoidle_reg   = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_AUTOIDLE_PLL),
+        .autoidle_mask  = OMAP3430_AUTO_IVA2_DPLL_MASK,
+        .idlest_reg     = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_IDLEST_PLL),
+        .idlest_mask    = OMAP3430_ST_IVA2_CLK_MASK,
+        .max_multiplier = OMAP3_MAX_DPLL_MULT,
+        .min_divider    = 1,
+        .max_divider    = OMAP3_MAX_DPLL_DIV,
+        .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
+};
+
+static struct clk dpll2_ck = {
+        .name           = "dpll2_ck",
+        .ops            = &clkops_noncore_dpll_ops,
+        .parent         = &sys_ck,
+        .dpll_data      = &dpll2_dd,
+        .round_rate     = &omap2_dpll_round_rate,
+        .set_rate       = &omap3_noncore_dpll_set_rate,
+        .clkdm_name     = "dpll2_clkdm",
+        .recalc         = &omap3_dpll_recalc,
+};
+
+static const struct clksel div16_dpll2_m2x2_clksel[] = {
+        { .parent = &dpll2_ck, .rates = div16_dpll_rates },
+        { .parent = NULL }
+};
+
+/*
+ * The TRM is conflicted on whether IVA2 clock comes from DPLL2 CLKOUT
+ * or CLKOUTX2. CLKOUT seems most plausible.
+ */
+static struct clk dpll2_m2_ck = {
+        .name           = "dpll2_m2_ck",
+        .ops            = &clkops_null,
+        .parent         = &dpll2_ck,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD,
+                                          OMAP3430_CM_CLKSEL2_PLL),
+        .clksel_mask    = OMAP3430_IVA2_DPLL_CLKOUT_DIV_MASK,
+        .clksel         = div16_dpll2_m2x2_clksel,
+        .clkdm_name     = "dpll2_clkdm",
+        .recalc         = &omap2_clksel_recalc,
+};
+
+/*
+ * DPLL3
+ * Source clock for all interfaces and for some device fclks
+ * REVISIT: Also supports fast relock bypass - not included below
+ */
+static struct dpll_data dpll3_dd = {
+        .mult_div1_reg  = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
+        .mult_mask      = OMAP3430_CORE_DPLL_MULT_MASK,
+        .div1_mask      = OMAP3430_CORE_DPLL_DIV_MASK,
+        .clk_bypass     = &sys_ck,
+        .clk_ref        = &sys_ck,
+        .freqsel_mask   = OMAP3430_CORE_DPLL_FREQSEL_MASK,
+        .control_reg    = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
+        .enable_mask    = OMAP3430_EN_CORE_DPLL_MASK,
+        .auto_recal_bit = OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT,
+        .recal_en_bit   = OMAP3430_CORE_DPLL_RECAL_EN_SHIFT,
+        .recal_st_bit   = OMAP3430_CORE_DPLL_ST_SHIFT,
+        .autoidle_reg   = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
+        .autoidle_mask  = OMAP3430_AUTO_CORE_DPLL_MASK,
+        .idlest_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
+        .idlest_mask    = OMAP3430_ST_CORE_CLK_MASK,
+        .max_multiplier = OMAP3_MAX_DPLL_MULT,
+        .min_divider    = 1,
+        .max_divider    = OMAP3_MAX_DPLL_DIV,
+        .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
+};
+
+static struct clk dpll3_ck = {
+        .name           = "dpll3_ck",
+        .ops            = &clkops_null,
+        .parent         = &sys_ck,
+        .dpll_data      = &dpll3_dd,
+        .round_rate     = &omap2_dpll_round_rate,
+        .clkdm_name     = "dpll3_clkdm",
+        .recalc         = &omap3_dpll_recalc,
+};
+
+/*
+ * This virtual clock provides the CLKOUTX2 output from the DPLL if the
+ * DPLL isn't bypassed
+ */
+static struct clk dpll3_x2_ck = {
+        .name           = "dpll3_x2_ck",
+        .ops            = &clkops_null,
+        .parent         = &dpll3_ck,
+        .clkdm_name     = "dpll3_clkdm",
+        .recalc         = &omap3_clkoutx2_recalc,
+};
+
+static const struct clksel_rate div31_dpll3_rates[] = {
+        { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
+        { .div = 2, .val = 2, .flags = RATE_IN_343X },
+        { .div = 3, .val = 3, .flags = RATE_IN_3430ES2 },
+        { .div = 4, .val = 4, .flags = RATE_IN_3430ES2 },
+        { .div = 5, .val = 5, .flags = RATE_IN_3430ES2 },
+        { .div = 6, .val = 6, .flags = RATE_IN_3430ES2 },
+        { .div = 7, .val = 7, .flags = RATE_IN_3430ES2 },
+        { .div = 8, .val = 8, .flags = RATE_IN_3430ES2 },
+        { .div = 9, .val = 9, .flags = RATE_IN_3430ES2 },
+        { .div = 10, .val = 10, .flags = RATE_IN_3430ES2 },
+        { .div = 11, .val = 11, .flags = RATE_IN_3430ES2 },
+        { .div = 12, .val = 12, .flags = RATE_IN_3430ES2 },
+        { .div = 13, .val = 13, .flags = RATE_IN_3430ES2 },
+        { .div = 14, .val = 14, .flags = RATE_IN_3430ES2 },
+        { .div = 15, .val = 15, .flags = RATE_IN_3430ES2 },
+        { .div = 16, .val = 16, .flags = RATE_IN_3430ES2 },
+        { .div = 17, .val = 17, .flags = RATE_IN_3430ES2 },
+        { .div = 18, .val = 18, .flags = RATE_IN_3430ES2 },
+        { .div = 19, .val = 19, .flags = RATE_IN_3430ES2 },
+        { .div = 20, .val = 20, .flags = RATE_IN_3430ES2 },
+        { .div = 21, .val = 21, .flags = RATE_IN_3430ES2 },
+        { .div = 22, .val = 22, .flags = RATE_IN_3430ES2 },
+        { .div = 23, .val = 23, .flags = RATE_IN_3430ES2 },
+        { .div = 24, .val = 24, .flags = RATE_IN_3430ES2 },
+        { .div = 25, .val = 25, .flags = RATE_IN_3430ES2 },
+        { .div = 26, .val = 26, .flags = RATE_IN_3430ES2 },
+        { .div = 27, .val = 27, .flags = RATE_IN_3430ES2 },
+        { .div = 28, .val = 28, .flags = RATE_IN_3430ES2 },
+        { .div = 29, .val = 29, .flags = RATE_IN_3430ES2 },
+        { .div = 30, .val = 30, .flags = RATE_IN_3430ES2 },
+        { .div = 31, .val = 31, .flags = RATE_IN_3430ES2 },
+        { .div = 0 },
+};
+
+static const struct clksel div31_dpll3m2_clksel[] = {
+        { .parent = &dpll3_ck, .rates = div31_dpll3_rates },
+        { .parent = NULL }
+};
+
+/* DPLL3 output M2 - primary control point for CORE speed */
+static struct clk dpll3_m2_ck = {
+        .name           = "dpll3_m2_ck",
+        .ops            = &clkops_null,
+        .parent         = &dpll3_ck,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
+        .clksel_mask    = OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK,
+        .clksel         = div31_dpll3m2_clksel,
+        .clkdm_name     = "dpll3_clkdm",
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap3_core_dpll_m2_set_rate,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static struct clk core_ck = {
+        .name           = "core_ck",
+        .ops            = &clkops_null,
+        .parent         = &dpll3_m2_ck,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk dpll3_m2x2_ck = {
+        .name           = "dpll3_m2x2_ck",
+        .ops            = &clkops_null,
+        .parent         = &dpll3_m2_ck,
+        .clkdm_name     = "dpll3_clkdm",
+        .recalc         = &omap3_clkoutx2_recalc,
+};
+
+/* The PWRDN bit is apparently only available on 3430ES2 and above */
+static const struct clksel div16_dpll3_clksel[] = {
+        { .parent = &dpll3_ck, .rates = div16_dpll_rates },
+        { .parent = NULL }
+};
+
+/* This virtual clock is the source for dpll3_m3x2_ck */
+static struct clk dpll3_m3_ck = {
+        .name           = "dpll3_m3_ck",
+        .ops            = &clkops_null,
+        .parent         = &dpll3_ck,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
+        .clksel_mask    = OMAP3430_DIV_DPLL3_MASK,
+        .clksel         = div16_dpll3_clksel,
+        .clkdm_name     = "dpll3_clkdm",
+        .recalc         = &omap2_clksel_recalc,
+};
+
+/* The PWRDN bit is apparently only available on 3430ES2 and above */
+static struct clk dpll3_m3x2_ck = {
+        .name           = "dpll3_m3x2_ck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &dpll3_m3_ck,
+        .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
+        .enable_bit     = OMAP3430_PWRDN_EMU_CORE_SHIFT,
+        .flags          = INVERT_ENABLE,
+        .clkdm_name     = "dpll3_clkdm",
+        .recalc         = &omap3_clkoutx2_recalc,
+};
+
+static struct clk emu_core_alwon_ck = {
+        .name           = "emu_core_alwon_ck",
+        .ops            = &clkops_null,
+        .parent         = &dpll3_m3x2_ck,
+        .clkdm_name     = "dpll3_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+/* DPLL4 */
+/* Supplies 96MHz, 54Mhz TV DAC, DSS fclk, CAM sensor clock, emul trace clk */
+/* Type: DPLL */
+static struct dpll_data dpll4_dd = {
+        .mult_div1_reg  = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2),
+        .mult_mask      = OMAP3430_PERIPH_DPLL_MULT_MASK,
+        .div1_mask      = OMAP3430_PERIPH_DPLL_DIV_MASK,
+        .clk_bypass     = &sys_ck,
+        .clk_ref        = &sys_ck,
+        .freqsel_mask   = OMAP3430_PERIPH_DPLL_FREQSEL_MASK,
+        .control_reg    = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
+        .enable_mask    = OMAP3430_EN_PERIPH_DPLL_MASK,
+        .modes          = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
+        .auto_recal_bit = OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT,
+        .recal_en_bit   = OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT,
+        .recal_st_bit   = OMAP3430_PERIPH_DPLL_ST_SHIFT,
+        .autoidle_reg   = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
+        .autoidle_mask  = OMAP3430_AUTO_PERIPH_DPLL_MASK,
+        .idlest_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
+        .idlest_mask    = OMAP3430_ST_PERIPH_CLK_MASK,
+        .max_multiplier = OMAP3_MAX_DPLL_MULT,
+        .min_divider    = 1,
+        .max_divider    = OMAP3_MAX_DPLL_DIV,
+        .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
+};
+
+static struct clk dpll4_ck = {
+        .name           = "dpll4_ck",
+        .ops            = &clkops_noncore_dpll_ops,
+        .parent         = &sys_ck,
+        .dpll_data      = &dpll4_dd,
+        .round_rate     = &omap2_dpll_round_rate,
+        .set_rate       = &omap3_dpll4_set_rate,
+        .clkdm_name     = "dpll4_clkdm",
+        .recalc         = &omap3_dpll_recalc,
+};
+
+/*
+ * This virtual clock provides the CLKOUTX2 output from the DPLL if the
+ * DPLL isn't bypassed --
+ * XXX does this serve any downstream clocks?
+ */
+static struct clk dpll4_x2_ck = {
+        .name           = "dpll4_x2_ck",
+        .ops            = &clkops_null,
+        .parent         = &dpll4_ck,
+        .clkdm_name     = "dpll4_clkdm",
+        .recalc         = &omap3_clkoutx2_recalc,
+};
+
+static const struct clksel div16_dpll4_clksel[] = {
+        { .parent = &dpll4_ck, .rates = div16_dpll_rates },
+        { .parent = NULL }
+};
+
+/* This virtual clock is the source for dpll4_m2x2_ck */
+static struct clk dpll4_m2_ck = {
+        .name           = "dpll4_m2_ck",
+        .ops            = &clkops_null,
+        .parent         = &dpll4_ck,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, OMAP3430_CM_CLKSEL3),
+        .clksel_mask    = OMAP3430_DIV_96M_MASK,
+        .clksel         = div16_dpll4_clksel,
+        .clkdm_name     = "dpll4_clkdm",
+        .recalc         = &omap2_clksel_recalc,
+};
+
+/* The PWRDN bit is apparently only available on 3430ES2 and above */
+static struct clk dpll4_m2x2_ck = {
+        .name           = "dpll4_m2x2_ck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &dpll4_m2_ck,
+        .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
+        .enable_bit     = OMAP3430_PWRDN_96M_SHIFT,
+        .flags          = INVERT_ENABLE,
+        .clkdm_name     = "dpll4_clkdm",
+        .recalc         = &omap3_clkoutx2_recalc,
+};
+
+/*
+ * DPLL4 generates DPLL4_M2X2_CLK which is then routed into the PRM as
+ * PRM_96M_ALWON_(F)CLK.  Two clocks then emerge from the PRM:
+ * 96M_ALWON_FCLK (called "omap_96m_alwon_fck" below) and
+ * CM_96K_(F)CLK.
+ */
+static struct clk omap_96m_alwon_fck = {
+        .name           = "omap_96m_alwon_fck",
+        .ops            = &clkops_null,
+        .parent         = &dpll4_m2x2_ck,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk cm_96m_fck = {
+        .name           = "cm_96m_fck",
+        .ops            = &clkops_null,
+        .parent         = &omap_96m_alwon_fck,
+        .recalc         = &followparent_recalc,
+};
+
+static const struct clksel_rate omap_96m_dpll_rates[] = {
+        { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
+        { .div = 0 }
+};
+
+static const struct clksel_rate omap_96m_sys_rates[] = {
+        { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
+        { .div = 0 }
+};
+
+static const struct clksel omap_96m_fck_clksel[] = {
+        { .parent = &cm_96m_fck, .rates = omap_96m_dpll_rates },
+        { .parent = &sys_ck,     .rates = omap_96m_sys_rates },
+        { .parent = NULL }
+};
+
+static struct clk omap_96m_fck = {
+        .name           = "omap_96m_fck",
+        .ops            = &clkops_null,
+        .parent         = &sys_ck,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
+        .clksel_mask    = OMAP3430_SOURCE_96M_MASK,
+        .clksel         = omap_96m_fck_clksel,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+/* This virtual clock is the source for dpll4_m3x2_ck */
+static struct clk dpll4_m3_ck = {
+        .name           = "dpll4_m3_ck",
+        .ops            = &clkops_null,
+        .parent         = &dpll4_ck,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
+        .clksel_mask    = OMAP3430_CLKSEL_TV_MASK,
+        .clksel         = div16_dpll4_clksel,
+        .clkdm_name     = "dpll4_clkdm",
+        .recalc         = &omap2_clksel_recalc,
+};
+
+/* The PWRDN bit is apparently only available on 3430ES2 and above */
+static struct clk dpll4_m3x2_ck = {
+        .name           = "dpll4_m3x2_ck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &dpll4_m3_ck,
+        .init           = &omap2_init_clksel_parent,
+        .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
+        .enable_bit     = OMAP3430_PWRDN_TV_SHIFT,
+        .flags          = INVERT_ENABLE,
+        .clkdm_name     = "dpll4_clkdm",
+        .recalc         = &omap3_clkoutx2_recalc,
+};
+
+static const struct clksel_rate omap_54m_d4m3x2_rates[] = {
+        { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
+        { .div = 0 }
+};
+
+static const struct clksel_rate omap_54m_alt_rates[] = {
+        { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
+        { .div = 0 }
+};
+
+static const struct clksel omap_54m_clksel[] = {
+        { .parent = &dpll4_m3x2_ck, .rates = omap_54m_d4m3x2_rates },
+        { .parent = &sys_altclk,    .rates = omap_54m_alt_rates },
+        { .parent = NULL }
+};
+
+static struct clk omap_54m_fck = {
+        .name           = "omap_54m_fck",
+        .ops            = &clkops_null,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
+        .clksel_mask    = OMAP3430_SOURCE_54M_MASK,
+        .clksel         = omap_54m_clksel,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static const struct clksel_rate omap_48m_cm96m_rates[] = {
+        { .div = 2, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
+        { .div = 0 }
+};
+
+static const struct clksel_rate omap_48m_alt_rates[] = {
+        { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
+        { .div = 0 }
+};
+
+static const struct clksel omap_48m_clksel[] = {
+        { .parent = &cm_96m_fck, .rates = omap_48m_cm96m_rates },
+        { .parent = &sys_altclk, .rates = omap_48m_alt_rates },
+        { .parent = NULL }
+};
+
+static struct clk omap_48m_fck = {
+        .name           = "omap_48m_fck",
+        .ops            = &clkops_null,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
+        .clksel_mask    = OMAP3430_SOURCE_48M_MASK,
+        .clksel         = omap_48m_clksel,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static struct clk omap_12m_fck = {
+        .name           = "omap_12m_fck",
+        .ops            = &clkops_null,
+        .parent         = &omap_48m_fck,
+        .fixed_div      = 4,
+        .recalc         = &omap2_fixed_divisor_recalc,
+};
+
+/* This virstual clock is the source for dpll4_m4x2_ck */
+static struct clk dpll4_m4_ck = {
+        .name           = "dpll4_m4_ck",
+        .ops            = &clkops_null,
+        .parent         = &dpll4_ck,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
+        .clksel_mask    = OMAP3430_CLKSEL_DSS1_MASK,
+        .clksel         = div16_dpll4_clksel,
+        .clkdm_name     = "dpll4_clkdm",
+        .recalc         = &omap2_clksel_recalc,
+        .set_rate       = &omap2_clksel_set_rate,
+        .round_rate     = &omap2_clksel_round_rate,
+};
+
+/* The PWRDN bit is apparently only available on 3430ES2 and above */
+static struct clk dpll4_m4x2_ck = {
+        .name           = "dpll4_m4x2_ck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &dpll4_m4_ck,
+        .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
+        .enable_bit     = OMAP3430_PWRDN_CAM_SHIFT,
+        .flags          = INVERT_ENABLE,
+        .clkdm_name     = "dpll4_clkdm",
+        .recalc         = &omap3_clkoutx2_recalc,
+};
+
+/* This virtual clock is the source for dpll4_m5x2_ck */
+static struct clk dpll4_m5_ck = {
+        .name           = "dpll4_m5_ck",
+        .ops            = &clkops_null,
+        .parent         = &dpll4_ck,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_CLKSEL),
+        .clksel_mask    = OMAP3430_CLKSEL_CAM_MASK,
+        .clksel         = div16_dpll4_clksel,
+        .clkdm_name     = "dpll4_clkdm",
+        .recalc         = &omap2_clksel_recalc,
+};
+
+/* The PWRDN bit is apparently only available on 3430ES2 and above */
+static struct clk dpll4_m5x2_ck = {
+        .name           = "dpll4_m5x2_ck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &dpll4_m5_ck,
+        .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
+        .enable_bit     = OMAP3430_PWRDN_CAM_SHIFT,
+        .flags          = INVERT_ENABLE,
+        .clkdm_name     = "dpll4_clkdm",
+        .recalc         = &omap3_clkoutx2_recalc,
+};
+
+/* This virtual clock is the source for dpll4_m6x2_ck */
+static struct clk dpll4_m6_ck = {
+        .name           = "dpll4_m6_ck",
+        .ops            = &clkops_null,
+        .parent         = &dpll4_ck,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
+        .clksel_mask    = OMAP3430_DIV_DPLL4_MASK,
+        .clksel         = div16_dpll4_clksel,
+        .clkdm_name     = "dpll4_clkdm",
+        .recalc         = &omap2_clksel_recalc,
+};
+
+/* The PWRDN bit is apparently only available on 3430ES2 and above */
+static struct clk dpll4_m6x2_ck = {
+        .name           = "dpll4_m6x2_ck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &dpll4_m6_ck,
+        .init           = &omap2_init_clksel_parent,
+        .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
+        .enable_bit     = OMAP3430_PWRDN_EMU_PERIPH_SHIFT,
+        .flags          = INVERT_ENABLE,
+        .clkdm_name     = "dpll4_clkdm",
+        .recalc         = &omap3_clkoutx2_recalc,
+};
+
+static struct clk emu_per_alwon_ck = {
+        .name           = "emu_per_alwon_ck",
+        .ops            = &clkops_null,
+        .parent         = &dpll4_m6x2_ck,
+        .clkdm_name     = "dpll4_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+/* DPLL5 */
+/* Supplies 120MHz clock, USIM source clock */
+/* Type: DPLL */
+/* 3430ES2 only */
+static struct dpll_data dpll5_dd = {
+        .mult_div1_reg  = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL4),
+        .mult_mask      = OMAP3430ES2_PERIPH2_DPLL_MULT_MASK,
+        .div1_mask      = OMAP3430ES2_PERIPH2_DPLL_DIV_MASK,
+        .clk_bypass     = &sys_ck,
+        .clk_ref        = &sys_ck,
+        .freqsel_mask   = OMAP3430ES2_PERIPH2_DPLL_FREQSEL_MASK,
+        .control_reg    = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKEN2),
+        .enable_mask    = OMAP3430ES2_EN_PERIPH2_DPLL_MASK,
+        .modes          = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
+        .auto_recal_bit = OMAP3430ES2_EN_PERIPH2_DPLL_DRIFTGUARD_SHIFT,
+        .recal_en_bit   = OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_SHIFT,
+        .recal_st_bit   = OMAP3430ES2_SND_PERIPH_DPLL_ST_SHIFT,
+        .autoidle_reg   = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_AUTOIDLE2_PLL),
+        .autoidle_mask  = OMAP3430ES2_AUTO_PERIPH2_DPLL_MASK,
+        .idlest_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST2),
+        .idlest_mask    = OMAP3430ES2_ST_PERIPH2_CLK_MASK,
+        .max_multiplier = OMAP3_MAX_DPLL_MULT,
+        .min_divider    = 1,
+        .max_divider    = OMAP3_MAX_DPLL_DIV,
+        .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
+};
+
+static struct clk dpll5_ck = {
+        .name           = "dpll5_ck",
+        .ops            = &clkops_noncore_dpll_ops,
+        .parent         = &sys_ck,
+        .dpll_data      = &dpll5_dd,
+        .round_rate     = &omap2_dpll_round_rate,
+        .set_rate       = &omap3_noncore_dpll_set_rate,
+        .clkdm_name     = "dpll5_clkdm",
+        .recalc         = &omap3_dpll_recalc,
+};
+
+static const struct clksel div16_dpll5_clksel[] = {
+        { .parent = &dpll5_ck, .rates = div16_dpll_rates },
+        { .parent = NULL }
+};
+
+static struct clk dpll5_m2_ck = {
+        .name           = "dpll5_m2_ck",
+        .ops            = &clkops_null,
+        .parent         = &dpll5_ck,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL5),
+        .clksel_mask    = OMAP3430ES2_DIV_120M_MASK,
+        .clksel         = div16_dpll5_clksel,
+        .clkdm_name     = "dpll5_clkdm",
+        .recalc         = &omap2_clksel_recalc,
+};
+
+/* CM EXTERNAL CLOCK OUTPUTS */
+
+static const struct clksel_rate clkout2_src_core_rates[] = {
+        { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
+        { .div = 0 }
+};
+
+static const struct clksel_rate clkout2_src_sys_rates[] = {
+        { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
+        { .div = 0 }
+};
+
+static const struct clksel_rate clkout2_src_96m_rates[] = {
+        { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
+        { .div = 0 }
+};
+
+static const struct clksel_rate clkout2_src_54m_rates[] = {
+        { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
+        { .div = 0 }
+};
+
+static const struct clksel clkout2_src_clksel[] = {
+        { .parent = &core_ck,           .rates = clkout2_src_core_rates },
+        { .parent = &sys_ck,            .rates = clkout2_src_sys_rates },
+        { .parent = &cm_96m_fck,        .rates = clkout2_src_96m_rates },
+        { .parent = &omap_54m_fck,      .rates = clkout2_src_54m_rates },
+        { .parent = NULL }
+};
+
+static struct clk clkout2_src_ck = {
+        .name           = "clkout2_src_ck",
+        .ops            = &clkops_omap2_dflt,
+        .init           = &omap2_init_clksel_parent,
+        .enable_reg     = OMAP3430_CM_CLKOUT_CTRL,
+        .enable_bit     = OMAP3430_CLKOUT2_EN_SHIFT,
+        .clksel_reg     = OMAP3430_CM_CLKOUT_CTRL,
+        .clksel_mask    = OMAP3430_CLKOUT2SOURCE_MASK,
+        .clksel         = clkout2_src_clksel,
+        .clkdm_name     = "core_clkdm",
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static const struct clksel_rate sys_clkout2_rates[] = {
+        { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
+        { .div = 2, .val = 1, .flags = RATE_IN_343X },
+        { .div = 4, .val = 2, .flags = RATE_IN_343X },
+        { .div = 8, .val = 3, .flags = RATE_IN_343X },
+        { .div = 16, .val = 4, .flags = RATE_IN_343X },
+        { .div = 0 },
+};
+
+static const struct clksel sys_clkout2_clksel[] = {
+        { .parent = &clkout2_src_ck, .rates = sys_clkout2_rates },
+        { .parent = NULL },
+};
+
+static struct clk sys_clkout2 = {
+        .name           = "sys_clkout2",
+        .ops            = &clkops_null,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP3430_CM_CLKOUT_CTRL,
+        .clksel_mask    = OMAP3430_CLKOUT2_DIV_MASK,
+        .clksel         = sys_clkout2_clksel,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+/* CM OUTPUT CLOCKS */
+
+static struct clk corex2_fck = {
+        .name           = "corex2_fck",
+        .ops            = &clkops_null,
+        .parent         = &dpll3_m2x2_ck,
+        .recalc         = &followparent_recalc,
+};
+
+/* DPLL power domain clock controls */
+
+static const struct clksel_rate div4_rates[] = {
+        { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
+        { .div = 2, .val = 2, .flags = RATE_IN_343X },
+        { .div = 4, .val = 4, .flags = RATE_IN_343X },
+        { .div = 0 }
+};
+
+static const struct clksel div4_core_clksel[] = {
+        { .parent = &core_ck, .rates = div4_rates },
+        { .parent = NULL }
+};
+
+/*
+ * REVISIT: Are these in DPLL power domain or CM power domain? docs
+ * may be inconsistent here?
+ */
+static struct clk dpll1_fck = {
+        .name           = "dpll1_fck",
+        .ops            = &clkops_null,
+        .parent         = &core_ck,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
+        .clksel_mask    = OMAP3430_MPU_CLK_SRC_MASK,
+        .clksel         = div4_core_clksel,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static struct clk mpu_ck = {
+        .name           = "mpu_ck",
+        .ops            = &clkops_null,
+        .parent         = &dpll1_x2m2_ck,
+        .clkdm_name     = "mpu_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+/* arm_fck is divided by two when DPLL1 locked; otherwise, passthrough mpu_ck */
+static const struct clksel_rate arm_fck_rates[] = {
+        { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
+        { .div = 2, .val = 1, .flags = RATE_IN_343X },
+        { .div = 0 },
+};
+
+static const struct clksel arm_fck_clksel[] = {
+        { .parent = &mpu_ck, .rates = arm_fck_rates },
+        { .parent = NULL }
+};
+
+static struct clk arm_fck = {
+        .name           = "arm_fck",
+        .ops            = &clkops_null,
+        .parent         = &mpu_ck,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
+        .clksel_mask    = OMAP3430_ST_MPU_CLK_MASK,
+        .clksel         = arm_fck_clksel,
+        .clkdm_name     = "mpu_clkdm",
+        .recalc         = &omap2_clksel_recalc,
+};
+
+/* XXX What about neon_clkdm ? */
+
+/*
+ * REVISIT: This clock is never specifically defined in the 3430 TRM,
+ * although it is referenced - so this is a guess
+ */
+static struct clk emu_mpu_alwon_ck = {
+        .name           = "emu_mpu_alwon_ck",
+        .ops            = &clkops_null,
+        .parent         = &mpu_ck,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk dpll2_fck = {
+        .name           = "dpll2_fck",
+        .ops            = &clkops_null,
+        .parent         = &core_ck,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
+        .clksel_mask    = OMAP3430_IVA2_CLK_SRC_MASK,
+        .clksel         = div4_core_clksel,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static struct clk iva2_ck = {
+        .name           = "iva2_ck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &dpll2_m2_ck,
+        .init           = &omap2_init_clksel_parent,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT,
+        .clkdm_name     = "iva2_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+/* Common interface clocks */
+
+static const struct clksel div2_core_clksel[] = {
+        { .parent = &core_ck, .rates = div2_rates },
+        { .parent = NULL }
+};
+
+static struct clk l3_ick = {
+        .name           = "l3_ick",
+        .ops            = &clkops_null,
+        .parent         = &core_ck,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
+        .clksel_mask    = OMAP3430_CLKSEL_L3_MASK,
+        .clksel         = div2_core_clksel,
+        .clkdm_name     = "core_l3_clkdm",
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static const struct clksel div2_l3_clksel[] = {
+        { .parent = &l3_ick, .rates = div2_rates },
+        { .parent = NULL }
+};
+
+static struct clk l4_ick = {
+        .name           = "l4_ick",
+        .ops            = &clkops_null,
+        .parent         = &l3_ick,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
+        .clksel_mask    = OMAP3430_CLKSEL_L4_MASK,
+        .clksel         = div2_l3_clksel,
+        .clkdm_name     = "core_l4_clkdm",
+        .recalc         = &omap2_clksel_recalc,
+
+};
+
+static const struct clksel div2_l4_clksel[] = {
+        { .parent = &l4_ick, .rates = div2_rates },
+        { .parent = NULL }
+};
+
+static struct clk rm_ick = {
+        .name           = "rm_ick",
+        .ops            = &clkops_null,
+        .parent         = &l4_ick,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
+        .clksel_mask    = OMAP3430_CLKSEL_RM_MASK,
+        .clksel         = div2_l4_clksel,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+/* GFX power domain */
+
+/* GFX clocks are in 3430ES1 only. 3430ES2 and later uses the SGX instead */
+
+static const struct clksel gfx_l3_clksel[] = {
+        { .parent = &l3_ick, .rates = gfx_l3_rates },
+        { .parent = NULL }
+};
+
+/* Virtual parent clock for gfx_l3_ick and gfx_l3_fck */
+static struct clk gfx_l3_ck = {
+        .name           = "gfx_l3_ck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &l3_ick,
+        .init           = &omap2_init_clksel_parent,
+        .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP_EN_GFX_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk gfx_l3_fck = {
+        .name           = "gfx_l3_fck",
+        .ops            = &clkops_null,
+        .parent         = &gfx_l3_ck,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
+        .clksel_mask    = OMAP_CLKSEL_GFX_MASK,
+        .clksel         = gfx_l3_clksel,
+        .clkdm_name     = "gfx_3430es1_clkdm",
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static struct clk gfx_l3_ick = {
+        .name           = "gfx_l3_ick",
+        .ops            = &clkops_null,
+        .parent         = &gfx_l3_ck,
+        .clkdm_name     = "gfx_3430es1_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk gfx_cg1_ck = {
+        .name           = "gfx_cg1_ck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &gfx_l3_fck, /* REVISIT: correct? */
+        .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430ES1_EN_2D_SHIFT,
+        .clkdm_name     = "gfx_3430es1_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk gfx_cg2_ck = {
+        .name           = "gfx_cg2_ck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &gfx_l3_fck, /* REVISIT: correct? */
+        .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430ES1_EN_3D_SHIFT,
+        .clkdm_name     = "gfx_3430es1_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+/* SGX power domain - 3430ES2 only */
+
+static const struct clksel_rate sgx_core_rates[] = {
+        { .div = 3, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
+        { .div = 4, .val = 1, .flags = RATE_IN_343X },
+        { .div = 6, .val = 2, .flags = RATE_IN_343X },
+        { .div = 0 },
+};
+
+static const struct clksel_rate sgx_96m_rates[] = {
+        { .div = 1,  .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
+        { .div = 0 },
+};
+
+static const struct clksel sgx_clksel[] = {
+        { .parent = &core_ck,    .rates = sgx_core_rates },
+        { .parent = &cm_96m_fck, .rates = sgx_96m_rates },
+        { .parent = NULL },
+};
+
+static struct clk sgx_fck = {
+        .name           = "sgx_fck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .init           = &omap2_init_clksel_parent,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_SHIFT,
+        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_CLKSEL),
+        .clksel_mask    = OMAP3430ES2_CLKSEL_SGX_MASK,
+        .clksel         = sgx_clksel,
+        .clkdm_name     = "sgx_clkdm",
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static struct clk sgx_ick = {
+        .name           = "sgx_ick",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &l3_ick,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_SHIFT,
+        .clkdm_name     = "sgx_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+/* CORE power domain */
+
+static struct clk d2d_26m_fck = {
+        .name           = "d2d_26m_fck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &sys_ck,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP3430ES1_EN_D2D_SHIFT,
+        .clkdm_name     = "d2d_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk modem_fck = {
+        .name           = "modem_fck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &sys_ck,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP3430_EN_MODEM_SHIFT,
+        .clkdm_name     = "d2d_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk sad2d_ick = {
+        .name           = "sad2d_ick",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &l3_ick,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430_EN_SAD2D_SHIFT,
+        .clkdm_name     = "d2d_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mad2d_ick = {
+        .name           = "mad2d_ick",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &l3_ick,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
+        .enable_bit     = OMAP3430_EN_MAD2D_SHIFT,
+        .clkdm_name     = "d2d_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+static const struct clksel omap343x_gpt_clksel[] = {
+        { .parent = &omap_32k_fck, .rates = gpt_32k_rates },
+        { .parent = &sys_ck,       .rates = gpt_sys_rates },
+        { .parent = NULL}
+};
+
+static struct clk gpt10_fck = {
+        .name           = "gpt10_fck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &sys_ck,
+        .init           = &omap2_init_clksel_parent,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP3430_EN_GPT10_SHIFT,
+        .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
+        .clksel_mask    = OMAP3430_CLKSEL_GPT10_MASK,
+        .clksel         = omap343x_gpt_clksel,
+        .clkdm_name     = "core_l4_clkdm",
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static struct clk gpt11_fck = {
+        .name           = "gpt11_fck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &sys_ck,
+        .init           = &omap2_init_clksel_parent,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP3430_EN_GPT11_SHIFT,
+        .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
+        .clksel_mask    = OMAP3430_CLKSEL_GPT11_MASK,
+        .clksel         = omap343x_gpt_clksel,
+        .clkdm_name     = "core_l4_clkdm",
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static struct clk cpefuse_fck = {
+        .name           = "cpefuse_fck",
+        .ops            = &clkops_omap2_dflt,
+        .parent         = &sys_ck,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
+        .enable_bit     = OMAP3430ES2_EN_CPEFUSE_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk ts_fck = {
+        .name           = "ts_fck",
+        .ops            = &clkops_omap2_dflt,
+        .parent         = &omap_32k_fck,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
+        .enable_bit     = OMAP3430ES2_EN_TS_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk usbtll_fck = {
+        .name           = "usbtll_fck",
+        .ops            = &clkops_omap2_dflt,
+        .parent         = &dpll5_m2_ck,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
+        .enable_bit     = OMAP3430ES2_EN_USBTLL_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+/* CORE 96M FCLK-derived clocks */
+
+static struct clk core_96m_fck = {
+        .name           = "core_96m_fck",
+        .ops            = &clkops_null,
+        .parent         = &omap_96m_fck,
+        .clkdm_name     = "core_l4_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mmchs3_fck = {
+        .name           = "mmchs_fck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .id             = 2,
+        .parent         = &core_96m_fck,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP3430ES2_EN_MMC3_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mmchs2_fck = {
+        .name           = "mmchs_fck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .id             = 1,
+        .parent         = &core_96m_fck,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP3430_EN_MMC2_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mspro_fck = {
+        .name           = "mspro_fck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &core_96m_fck,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP3430_EN_MSPRO_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mmchs1_fck = {
+        .name           = "mmchs_fck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &core_96m_fck,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP3430_EN_MMC1_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk i2c3_fck = {
+        .name           = "i2c_fck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .id             = 3,
+        .parent         = &core_96m_fck,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP3430_EN_I2C3_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk i2c2_fck = {
+        .name           = "i2c_fck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .id             = 2,
+        .parent         = &core_96m_fck,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP3430_EN_I2C2_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk i2c1_fck = {
+        .name           = "i2c_fck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .id             = 1,
+        .parent         = &core_96m_fck,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP3430_EN_I2C1_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+/*
+ * MCBSP 1 & 5 get their 96MHz clock from core_96m_fck;
+ * MCBSP 2, 3, 4 get their 96MHz clock from per_96m_fck.
+ */
+static const struct clksel_rate common_mcbsp_96m_rates[] = {
+        { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
+        { .div = 0 }
+};
+
+static const struct clksel_rate common_mcbsp_mcbsp_rates[] = {
+        { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
+        { .div = 0 }
+};
+
+static const struct clksel mcbsp_15_clksel[] = {
+        { .parent = &core_96m_fck, .rates = common_mcbsp_96m_rates },
+        { .parent = &mcbsp_clks,   .rates = common_mcbsp_mcbsp_rates },
+        { .parent = NULL }
+};
+
+static struct clk mcbsp5_fck = {
+        .name           = "mcbsp_fck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .id             = 5,
+        .init           = &omap2_init_clksel_parent,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP3430_EN_MCBSP5_SHIFT,
+        .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
+        .clksel_mask    = OMAP2_MCBSP5_CLKS_MASK,
+        .clksel         = mcbsp_15_clksel,
+        .clkdm_name     = "core_l4_clkdm",
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static struct clk mcbsp1_fck = {
+        .name           = "mcbsp_fck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .id             = 1,
+        .init           = &omap2_init_clksel_parent,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP3430_EN_MCBSP1_SHIFT,
+        .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
+        .clksel_mask    = OMAP2_MCBSP1_CLKS_MASK,
+        .clksel         = mcbsp_15_clksel,
+        .clkdm_name     = "core_l4_clkdm",
+        .recalc         = &omap2_clksel_recalc,
+};
+
+/* CORE_48M_FCK-derived clocks */
+
+static struct clk core_48m_fck = {
+        .name           = "core_48m_fck",
+        .ops            = &clkops_null,
+        .parent         = &omap_48m_fck,
+        .clkdm_name     = "core_l4_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mcspi4_fck = {
+        .name           = "mcspi_fck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .id             = 4,
+        .parent         = &core_48m_fck,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP3430_EN_MCSPI4_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mcspi3_fck = {
+        .name           = "mcspi_fck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .id             = 3,
+        .parent         = &core_48m_fck,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP3430_EN_MCSPI3_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mcspi2_fck = {
+        .name           = "mcspi_fck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .id             = 2,
+        .parent         = &core_48m_fck,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP3430_EN_MCSPI2_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mcspi1_fck = {
+        .name           = "mcspi_fck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .id             = 1,
+        .parent         = &core_48m_fck,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP3430_EN_MCSPI1_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk uart2_fck = {
+        .name           = "uart2_fck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &core_48m_fck,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP3430_EN_UART2_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk uart1_fck = {
+        .name           = "uart1_fck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &core_48m_fck,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP3430_EN_UART1_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk fshostusb_fck = {
+        .name           = "fshostusb_fck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &core_48m_fck,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+/* CORE_12M_FCK based clocks */
+
+static struct clk core_12m_fck = {
+        .name           = "core_12m_fck",
+        .ops            = &clkops_null,
+        .parent         = &omap_12m_fck,
+        .clkdm_name     = "core_l4_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk hdq_fck = {
+        .name           = "hdq_fck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &core_12m_fck,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP3430_EN_HDQ_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+/* DPLL3-derived clock */
+
+static const struct clksel_rate ssi_ssr_corex2_rates[] = {
+        { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
+        { .div = 2, .val = 2, .flags = RATE_IN_343X },
+        { .div = 3, .val = 3, .flags = RATE_IN_343X },
+        { .div = 4, .val = 4, .flags = RATE_IN_343X },
+        { .div = 6, .val = 6, .flags = RATE_IN_343X },
+        { .div = 8, .val = 8, .flags = RATE_IN_343X },
+        { .div = 0 }
+};
+
+static const struct clksel ssi_ssr_clksel[] = {
+        { .parent = &corex2_fck, .rates = ssi_ssr_corex2_rates },
+        { .parent = NULL }
+};
+
+static struct clk ssi_ssr_fck_3430es1 = {
+        .name           = "ssi_ssr_fck",
+        .ops            = &clkops_omap2_dflt,
+        .init           = &omap2_init_clksel_parent,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP3430_EN_SSI_SHIFT,
+        .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
+        .clksel_mask    = OMAP3430_CLKSEL_SSI_MASK,
+        .clksel         = ssi_ssr_clksel,
+        .clkdm_name     = "core_l4_clkdm",
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static struct clk ssi_ssr_fck_3430es2 = {
+        .name           = "ssi_ssr_fck",
+        .ops            = &clkops_omap3430es2_ssi_wait,
+        .init           = &omap2_init_clksel_parent,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP3430_EN_SSI_SHIFT,
+        .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
+        .clksel_mask    = OMAP3430_CLKSEL_SSI_MASK,
+        .clksel         = ssi_ssr_clksel,
+        .clkdm_name     = "core_l4_clkdm",
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static struct clk ssi_sst_fck_3430es1 = {
+        .name           = "ssi_sst_fck",
+        .ops            = &clkops_null,
+        .parent         = &ssi_ssr_fck_3430es1,
+        .fixed_div      = 2,
+        .recalc         = &omap2_fixed_divisor_recalc,
+};
+
+static struct clk ssi_sst_fck_3430es2 = {
+        .name           = "ssi_sst_fck",
+        .ops            = &clkops_null,
+        .parent         = &ssi_ssr_fck_3430es2,
+        .fixed_div      = 2,
+        .recalc         = &omap2_fixed_divisor_recalc,
+};
+
+
+
+/* CORE_L3_ICK based clocks */
+
+/*
+ * XXX must add clk_enable/clk_disable for these if standard code won't
+ * handle it
+ */
+static struct clk core_l3_ick = {
+        .name           = "core_l3_ick",
+        .ops            = &clkops_null,
+        .parent         = &l3_ick,
+        .clkdm_name     = "core_l3_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk hsotgusb_ick_3430es1 = {
+        .name           = "hsotgusb_ick",
+        .ops            = &clkops_omap2_dflt,
+        .parent         = &core_l3_ick,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430_EN_HSOTGUSB_SHIFT,
+        .clkdm_name     = "core_l3_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk hsotgusb_ick_3430es2 = {
+        .name           = "hsotgusb_ick",
+        .ops            = &clkops_omap3430es2_hsotgusb_wait,
+        .parent         = &core_l3_ick,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430_EN_HSOTGUSB_SHIFT,
+        .clkdm_name     = "core_l3_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk sdrc_ick = {
+        .name           = "sdrc_ick",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &core_l3_ick,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430_EN_SDRC_SHIFT,
+        .flags          = ENABLE_ON_INIT,
+        .clkdm_name     = "core_l3_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk gpmc_fck = {
+        .name           = "gpmc_fck",
+        .ops            = &clkops_null,
+        .parent         = &core_l3_ick,
+        .flags          = ENABLE_ON_INIT, /* huh? */
+        .clkdm_name     = "core_l3_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+/* SECURITY_L3_ICK based clocks */
+
+static struct clk security_l3_ick = {
+        .name           = "security_l3_ick",
+        .ops            = &clkops_null,
+        .parent         = &l3_ick,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk pka_ick = {
+        .name           = "pka_ick",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &security_l3_ick,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
+        .enable_bit     = OMAP3430_EN_PKA_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+/* CORE_L4_ICK based clocks */
+
+static struct clk core_l4_ick = {
+        .name           = "core_l4_ick",
+        .ops            = &clkops_null,
+        .parent         = &l4_ick,
+        .clkdm_name     = "core_l4_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk usbtll_ick = {
+        .name           = "usbtll_ick",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &core_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
+        .enable_bit     = OMAP3430ES2_EN_USBTLL_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mmchs3_ick = {
+        .name           = "mmchs_ick",
+        .ops            = &clkops_omap2_dflt_wait,
+        .id             = 2,
+        .parent         = &core_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430ES2_EN_MMC3_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+/* Intersystem Communication Registers - chassis mode only */
+static struct clk icr_ick = {
+        .name           = "icr_ick",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &core_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430_EN_ICR_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk aes2_ick = {
+        .name           = "aes2_ick",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &core_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430_EN_AES2_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk sha12_ick = {
+        .name           = "sha12_ick",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &core_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430_EN_SHA12_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk des2_ick = {
+        .name           = "des2_ick",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &core_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430_EN_DES2_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mmchs2_ick = {
+        .name           = "mmchs_ick",
+        .ops            = &clkops_omap2_dflt_wait,
+        .id             = 1,
+        .parent         = &core_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430_EN_MMC2_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mmchs1_ick = {
+        .name           = "mmchs_ick",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &core_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430_EN_MMC1_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mspro_ick = {
+        .name           = "mspro_ick",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &core_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430_EN_MSPRO_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk hdq_ick = {
+        .name           = "hdq_ick",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &core_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430_EN_HDQ_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mcspi4_ick = {
+        .name           = "mcspi_ick",
+        .ops            = &clkops_omap2_dflt_wait,
+        .id             = 4,
+        .parent         = &core_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430_EN_MCSPI4_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mcspi3_ick = {
+        .name           = "mcspi_ick",
+        .ops            = &clkops_omap2_dflt_wait,
+        .id             = 3,
+        .parent         = &core_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430_EN_MCSPI3_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mcspi2_ick = {
+        .name           = "mcspi_ick",
+        .ops            = &clkops_omap2_dflt_wait,
+        .id             = 2,
+        .parent         = &core_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430_EN_MCSPI2_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mcspi1_ick = {
+        .name           = "mcspi_ick",
+        .ops            = &clkops_omap2_dflt_wait,
+        .id             = 1,
+        .parent         = &core_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430_EN_MCSPI1_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk i2c3_ick = {
+        .name           = "i2c_ick",
+        .ops            = &clkops_omap2_dflt_wait,
+        .id             = 3,
+        .parent         = &core_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430_EN_I2C3_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk i2c2_ick = {
+        .name           = "i2c_ick",
+        .ops            = &clkops_omap2_dflt_wait,
+        .id             = 2,
+        .parent         = &core_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430_EN_I2C2_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk i2c1_ick = {
+        .name           = "i2c_ick",
+        .ops            = &clkops_omap2_dflt_wait,
+        .id             = 1,
+        .parent         = &core_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430_EN_I2C1_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk uart2_ick = {
+        .name           = "uart2_ick",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &core_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430_EN_UART2_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk uart1_ick = {
+        .name           = "uart1_ick",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &core_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430_EN_UART1_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk gpt11_ick = {
+        .name           = "gpt11_ick",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &core_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430_EN_GPT11_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk gpt10_ick = {
+        .name           = "gpt10_ick",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &core_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430_EN_GPT10_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mcbsp5_ick = {
+        .name           = "mcbsp_ick",
+        .ops            = &clkops_omap2_dflt_wait,
+        .id             = 5,
+        .parent         = &core_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430_EN_MCBSP5_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mcbsp1_ick = {
+        .name           = "mcbsp_ick",
+        .ops            = &clkops_omap2_dflt_wait,
+        .id             = 1,
+        .parent         = &core_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430_EN_MCBSP1_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk fac_ick = {
+        .name           = "fac_ick",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &core_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430ES1_EN_FAC_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mailboxes_ick = {
+        .name           = "mailboxes_ick",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &core_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430_EN_MAILBOXES_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk omapctrl_ick = {
+        .name           = "omapctrl_ick",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &core_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430_EN_OMAPCTRL_SHIFT,
+        .flags          = ENABLE_ON_INIT,
+        .recalc         = &followparent_recalc,
+};
+
+/* SSI_L4_ICK based clocks */
+
+static struct clk ssi_l4_ick = {
+        .name           = "ssi_l4_ick",
+        .ops            = &clkops_null,
+        .parent         = &l4_ick,
+        .clkdm_name     = "core_l4_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk ssi_ick_3430es1 = {
+        .name           = "ssi_ick",
+        .ops            = &clkops_omap2_dflt,
+        .parent         = &ssi_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430_EN_SSI_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk ssi_ick_3430es2 = {
+        .name           = "ssi_ick",
+        .ops            = &clkops_omap3430es2_ssi_wait,
+        .parent         = &ssi_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430_EN_SSI_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+/* REVISIT: Technically the TRM claims that this is CORE_CLK based,
+ * but l4_ick makes more sense to me */
+
+static const struct clksel usb_l4_clksel[] = {
+        { .parent = &l4_ick, .rates = div2_rates },
+        { .parent = NULL },
+};
+
+static struct clk usb_l4_ick = {
+        .name           = "usb_l4_ick",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &l4_ick,
+        .init           = &omap2_init_clksel_parent,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
+        .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
+        .clksel_mask    = OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK,
+        .clksel         = usb_l4_clksel,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+/* SECURITY_L4_ICK2 based clocks */
+
+static struct clk security_l4_ick2 = {
+        .name           = "security_l4_ick2",
+        .ops            = &clkops_null,
+        .parent         = &l4_ick,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk aes1_ick = {
+        .name           = "aes1_ick",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &security_l4_ick2,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
+        .enable_bit     = OMAP3430_EN_AES1_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk rng_ick = {
+        .name           = "rng_ick",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &security_l4_ick2,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
+        .enable_bit     = OMAP3430_EN_RNG_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk sha11_ick = {
+        .name           = "sha11_ick",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &security_l4_ick2,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
+        .enable_bit     = OMAP3430_EN_SHA11_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk des1_ick = {
+        .name           = "des1_ick",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &security_l4_ick2,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
+        .enable_bit     = OMAP3430_EN_DES1_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+/* DSS */
+static struct clk dss1_alwon_fck_3430es1 = {
+        .name           = "dss1_alwon_fck",
+        .ops            = &clkops_omap2_dflt,
+        .parent         = &dpll4_m4x2_ck,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430_EN_DSS1_SHIFT,
+        .clkdm_name     = "dss_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk dss1_alwon_fck_3430es2 = {
+        .name           = "dss1_alwon_fck",
+        .ops            = &clkops_omap3430es2_dss_usbhost_wait,
+        .parent         = &dpll4_m4x2_ck,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430_EN_DSS1_SHIFT,
+        .clkdm_name     = "dss_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk dss_tv_fck = {
+        .name           = "dss_tv_fck",
+        .ops            = &clkops_omap2_dflt,
+        .parent         = &omap_54m_fck,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430_EN_TV_SHIFT,
+        .clkdm_name     = "dss_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk dss_96m_fck = {
+        .name           = "dss_96m_fck",
+        .ops            = &clkops_omap2_dflt,
+        .parent         = &omap_96m_fck,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430_EN_TV_SHIFT,
+        .clkdm_name     = "dss_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk dss2_alwon_fck = {
+        .name           = "dss2_alwon_fck",
+        .ops            = &clkops_omap2_dflt,
+        .parent         = &sys_ck,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430_EN_DSS2_SHIFT,
+        .clkdm_name     = "dss_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk dss_ick_3430es1 = {
+        /* Handles both L3 and L4 clocks */
+        .name           = "dss_ick",
+        .ops            = &clkops_omap2_dflt,
+        .parent         = &l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT,
+        .clkdm_name     = "dss_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk dss_ick_3430es2 = {
+        /* Handles both L3 and L4 clocks */
+        .name           = "dss_ick",
+        .ops            = &clkops_omap3430es2_dss_usbhost_wait,
+        .parent         = &l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT,
+        .clkdm_name     = "dss_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+/* CAM */
+
+static struct clk cam_mclk = {
+        .name           = "cam_mclk",
+        .ops            = &clkops_omap2_dflt,
+        .parent         = &dpll4_m5x2_ck,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430_EN_CAM_SHIFT,
+        .clkdm_name     = "cam_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk cam_ick = {
+        /* Handles both L3 and L4 clocks */
+        .name           = "cam_ick",
+        .ops            = &clkops_omap2_dflt,
+        .parent         = &l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430_EN_CAM_SHIFT,
+        .clkdm_name     = "cam_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk csi2_96m_fck = {
+        .name           = "csi2_96m_fck",
+        .ops            = &clkops_omap2_dflt,
+        .parent         = &core_96m_fck,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430_EN_CSI2_SHIFT,
+        .clkdm_name     = "cam_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+/* USBHOST - 3430ES2 only */
+
+static struct clk usbhost_120m_fck = {
+        .name           = "usbhost_120m_fck",
+        .ops            = &clkops_omap2_dflt,
+        .parent         = &dpll5_m2_ck,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430ES2_EN_USBHOST2_SHIFT,
+        .clkdm_name     = "usbhost_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk usbhost_48m_fck = {
+        .name           = "usbhost_48m_fck",
+        .ops            = &clkops_omap3430es2_dss_usbhost_wait,
+        .parent         = &omap_48m_fck,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430ES2_EN_USBHOST1_SHIFT,
+        .clkdm_name     = "usbhost_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk usbhost_ick = {
+        /* Handles both L3 and L4 clocks */
+        .name           = "usbhost_ick",
+        .ops            = &clkops_omap3430es2_dss_usbhost_wait,
+        .parent         = &l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430ES2_EN_USBHOST_SHIFT,
+        .clkdm_name     = "usbhost_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+/* WKUP */
+
+static const struct clksel_rate usim_96m_rates[] = {
+        { .div = 2,  .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
+        { .div = 4,  .val = 4, .flags = RATE_IN_343X },
+        { .div = 8,  .val = 5, .flags = RATE_IN_343X },
+        { .div = 10, .val = 6, .flags = RATE_IN_343X },
+        { .div = 0 },
+};
+
+static const struct clksel_rate usim_120m_rates[] = {
+        { .div = 4,  .val = 7,  .flags = RATE_IN_343X | DEFAULT_RATE },
+        { .div = 8,  .val = 8,  .flags = RATE_IN_343X },
+        { .div = 16, .val = 9,  .flags = RATE_IN_343X },
+        { .div = 20, .val = 10, .flags = RATE_IN_343X },
+        { .div = 0 },
+};
+
+static const struct clksel usim_clksel[] = {
+        { .parent = &omap_96m_fck,      .rates = usim_96m_rates },
+        { .parent = &dpll5_m2_ck,       .rates = usim_120m_rates },
+        { .parent = &sys_ck,            .rates = div2_rates },
+        { .parent = NULL },
+};
+
+/* 3430ES2 only */
+static struct clk usim_fck = {
+        .name           = "usim_fck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .init           = &omap2_init_clksel_parent,
+        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430ES2_EN_USIMOCP_SHIFT,
+        .clksel_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
+        .clksel_mask    = OMAP3430ES2_CLKSEL_USIMOCP_MASK,
+        .clksel         = usim_clksel,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+/* XXX should gpt1's clksel have wkup_32k_fck as the 32k opt? */
+static struct clk gpt1_fck = {
+        .name           = "gpt1_fck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .init           = &omap2_init_clksel_parent,
+        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430_EN_GPT1_SHIFT,
+        .clksel_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
+        .clksel_mask    = OMAP3430_CLKSEL_GPT1_MASK,
+        .clksel         = omap343x_gpt_clksel,
+        .clkdm_name     = "wkup_clkdm",
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static struct clk wkup_32k_fck = {
+        .name           = "wkup_32k_fck",
+        .ops            = &clkops_null,
+        .parent         = &omap_32k_fck,
+        .clkdm_name     = "wkup_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk gpio1_dbck = {
+        .name           = "gpio1_dbck",
+        .ops            = &clkops_omap2_dflt,
+        .parent         = &wkup_32k_fck,
+        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430_EN_GPIO1_SHIFT,
+        .clkdm_name     = "wkup_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk wdt2_fck = {
+        .name           = "wdt2_fck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &wkup_32k_fck,
+        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430_EN_WDT2_SHIFT,
+        .clkdm_name     = "wkup_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk wkup_l4_ick = {
+        .name           = "wkup_l4_ick",
+        .ops            = &clkops_null,
+        .parent         = &sys_ck,
+        .clkdm_name     = "wkup_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+/* 3430ES2 only */
+/* Never specifically named in the TRM, so we have to infer a likely name */
+static struct clk usim_ick = {
+        .name           = "usim_ick",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &wkup_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430ES2_EN_USIMOCP_SHIFT,
+        .clkdm_name     = "wkup_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk wdt2_ick = {
+        .name           = "wdt2_ick",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &wkup_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430_EN_WDT2_SHIFT,
+        .clkdm_name     = "wkup_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk wdt1_ick = {
+        .name           = "wdt1_ick",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &wkup_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430_EN_WDT1_SHIFT,
+        .clkdm_name     = "wkup_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk gpio1_ick = {
+        .name           = "gpio1_ick",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &wkup_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430_EN_GPIO1_SHIFT,
+        .clkdm_name     = "wkup_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk omap_32ksync_ick = {
+        .name           = "omap_32ksync_ick",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &wkup_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430_EN_32KSYNC_SHIFT,
+        .clkdm_name     = "wkup_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+/* XXX This clock no longer exists in 3430 TRM rev F */
+static struct clk gpt12_ick = {
+        .name           = "gpt12_ick",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &wkup_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430_EN_GPT12_SHIFT,
+        .clkdm_name     = "wkup_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk gpt1_ick = {
+        .name           = "gpt1_ick",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &wkup_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430_EN_GPT1_SHIFT,
+        .clkdm_name     = "wkup_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+
+
+/* PER clock domain */
+
+static struct clk per_96m_fck = {
+        .name           = "per_96m_fck",
+        .ops            = &clkops_null,
+        .parent         = &omap_96m_alwon_fck,
+        .clkdm_name     = "per_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk per_48m_fck = {
+        .name           = "per_48m_fck",
+        .ops            = &clkops_null,
+        .parent         = &omap_48m_fck,
+        .clkdm_name     = "per_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk uart3_fck = {
+        .name           = "uart3_fck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &per_48m_fck,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430_EN_UART3_SHIFT,
+        .clkdm_name     = "per_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk gpt2_fck = {
+        .name           = "gpt2_fck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .init           = &omap2_init_clksel_parent,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430_EN_GPT2_SHIFT,
+        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
+        .clksel_mask    = OMAP3430_CLKSEL_GPT2_MASK,
+        .clksel         = omap343x_gpt_clksel,
+        .clkdm_name     = "per_clkdm",
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static struct clk gpt3_fck = {
+        .name           = "gpt3_fck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .init           = &omap2_init_clksel_parent,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430_EN_GPT3_SHIFT,
+        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
+        .clksel_mask    = OMAP3430_CLKSEL_GPT3_MASK,
+        .clksel         = omap343x_gpt_clksel,
+        .clkdm_name     = "per_clkdm",
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static struct clk gpt4_fck = {
+        .name           = "gpt4_fck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .init           = &omap2_init_clksel_parent,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430_EN_GPT4_SHIFT,
+        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
+        .clksel_mask    = OMAP3430_CLKSEL_GPT4_MASK,
+        .clksel         = omap343x_gpt_clksel,
+        .clkdm_name     = "per_clkdm",
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static struct clk gpt5_fck = {
+        .name           = "gpt5_fck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .init           = &omap2_init_clksel_parent,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430_EN_GPT5_SHIFT,
+        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
+        .clksel_mask    = OMAP3430_CLKSEL_GPT5_MASK,
+        .clksel         = omap343x_gpt_clksel,
+        .clkdm_name     = "per_clkdm",
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static struct clk gpt6_fck = {
+        .name           = "gpt6_fck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .init           = &omap2_init_clksel_parent,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430_EN_GPT6_SHIFT,
+        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
+        .clksel_mask    = OMAP3430_CLKSEL_GPT6_MASK,
+        .clksel         = omap343x_gpt_clksel,
+        .clkdm_name     = "per_clkdm",
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static struct clk gpt7_fck = {
+        .name           = "gpt7_fck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .init           = &omap2_init_clksel_parent,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430_EN_GPT7_SHIFT,
+        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
+        .clksel_mask    = OMAP3430_CLKSEL_GPT7_MASK,
+        .clksel         = omap343x_gpt_clksel,
+        .clkdm_name     = "per_clkdm",
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static struct clk gpt8_fck = {
+        .name           = "gpt8_fck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .init           = &omap2_init_clksel_parent,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430_EN_GPT8_SHIFT,
+        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
+        .clksel_mask    = OMAP3430_CLKSEL_GPT8_MASK,
+        .clksel         = omap343x_gpt_clksel,
+        .clkdm_name     = "per_clkdm",
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static struct clk gpt9_fck = {
+        .name           = "gpt9_fck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .init           = &omap2_init_clksel_parent,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430_EN_GPT9_SHIFT,
+        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
+        .clksel_mask    = OMAP3430_CLKSEL_GPT9_MASK,
+        .clksel         = omap343x_gpt_clksel,
+        .clkdm_name     = "per_clkdm",
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static struct clk per_32k_alwon_fck = {
+        .name           = "per_32k_alwon_fck",
+        .ops            = &clkops_null,
+        .parent         = &omap_32k_fck,
+        .clkdm_name     = "per_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk gpio6_dbck = {
+        .name           = "gpio6_dbck",
+        .ops            = &clkops_omap2_dflt,
+        .parent         = &per_32k_alwon_fck,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430_EN_GPIO6_SHIFT,
+        .clkdm_name     = "per_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk gpio5_dbck = {
+        .name           = "gpio5_dbck",
+        .ops            = &clkops_omap2_dflt,
+        .parent         = &per_32k_alwon_fck,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430_EN_GPIO5_SHIFT,
+        .clkdm_name     = "per_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk gpio4_dbck = {
+        .name           = "gpio4_dbck",
+        .ops            = &clkops_omap2_dflt,
+        .parent         = &per_32k_alwon_fck,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430_EN_GPIO4_SHIFT,
+        .clkdm_name     = "per_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk gpio3_dbck = {
+        .name           = "gpio3_dbck",
+        .ops            = &clkops_omap2_dflt,
+        .parent         = &per_32k_alwon_fck,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430_EN_GPIO3_SHIFT,
+        .clkdm_name     = "per_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk gpio2_dbck = {
+        .name           = "gpio2_dbck",
+        .ops            = &clkops_omap2_dflt,
+        .parent         = &per_32k_alwon_fck,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430_EN_GPIO2_SHIFT,
+        .clkdm_name     = "per_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk wdt3_fck = {
+        .name           = "wdt3_fck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &per_32k_alwon_fck,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430_EN_WDT3_SHIFT,
+        .clkdm_name     = "per_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk per_l4_ick = {
+        .name           = "per_l4_ick",
+        .ops            = &clkops_null,
+        .parent         = &l4_ick,
+        .clkdm_name     = "per_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk gpio6_ick = {
+        .name           = "gpio6_ick",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &per_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430_EN_GPIO6_SHIFT,
+        .clkdm_name     = "per_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk gpio5_ick = {
+        .name           = "gpio5_ick",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &per_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430_EN_GPIO5_SHIFT,
+        .clkdm_name     = "per_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk gpio4_ick = {
+        .name           = "gpio4_ick",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &per_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430_EN_GPIO4_SHIFT,
+        .clkdm_name     = "per_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk gpio3_ick = {
+        .name           = "gpio3_ick",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &per_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430_EN_GPIO3_SHIFT,
+        .clkdm_name     = "per_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk gpio2_ick = {
+        .name           = "gpio2_ick",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &per_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430_EN_GPIO2_SHIFT,
+        .clkdm_name     = "per_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk wdt3_ick = {
+        .name           = "wdt3_ick",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &per_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430_EN_WDT3_SHIFT,
+        .clkdm_name     = "per_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk uart3_ick = {
+        .name           = "uart3_ick",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &per_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430_EN_UART3_SHIFT,
+        .clkdm_name     = "per_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk gpt9_ick = {
+        .name           = "gpt9_ick",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &per_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430_EN_GPT9_SHIFT,
+        .clkdm_name     = "per_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk gpt8_ick = {
+        .name           = "gpt8_ick",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &per_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430_EN_GPT8_SHIFT,
+        .clkdm_name     = "per_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk gpt7_ick = {
+        .name           = "gpt7_ick",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &per_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430_EN_GPT7_SHIFT,
+        .clkdm_name     = "per_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk gpt6_ick = {
+        .name           = "gpt6_ick",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &per_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430_EN_GPT6_SHIFT,
+        .clkdm_name     = "per_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk gpt5_ick = {
+        .name           = "gpt5_ick",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &per_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430_EN_GPT5_SHIFT,
+        .clkdm_name     = "per_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk gpt4_ick = {
+        .name           = "gpt4_ick",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &per_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430_EN_GPT4_SHIFT,
+        .clkdm_name     = "per_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk gpt3_ick = {
+        .name           = "gpt3_ick",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &per_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430_EN_GPT3_SHIFT,
+        .clkdm_name     = "per_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk gpt2_ick = {
+        .name           = "gpt2_ick",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &per_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430_EN_GPT2_SHIFT,
+        .clkdm_name     = "per_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mcbsp2_ick = {
+        .name           = "mcbsp_ick",
+        .ops            = &clkops_omap2_dflt_wait,
+        .id             = 2,
+        .parent         = &per_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430_EN_MCBSP2_SHIFT,
+        .clkdm_name     = "per_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mcbsp3_ick = {
+        .name           = "mcbsp_ick",
+        .ops            = &clkops_omap2_dflt_wait,
+        .id             = 3,
+        .parent         = &per_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430_EN_MCBSP3_SHIFT,
+        .clkdm_name     = "per_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mcbsp4_ick = {
+        .name           = "mcbsp_ick",
+        .ops            = &clkops_omap2_dflt_wait,
+        .id             = 4,
+        .parent         = &per_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430_EN_MCBSP4_SHIFT,
+        .clkdm_name     = "per_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+static const struct clksel mcbsp_234_clksel[] = {
+        { .parent = &core_96m_fck, .rates = common_mcbsp_96m_rates },
+        { .parent = &mcbsp_clks,   .rates = common_mcbsp_mcbsp_rates },
+        { .parent = NULL }
+};
+
+static struct clk mcbsp2_fck = {
+        .name           = "mcbsp_fck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .id             = 2,
+        .init           = &omap2_init_clksel_parent,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430_EN_MCBSP2_SHIFT,
+        .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
+        .clksel_mask    = OMAP2_MCBSP2_CLKS_MASK,
+        .clksel         = mcbsp_234_clksel,
+        .clkdm_name     = "per_clkdm",
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static struct clk mcbsp3_fck = {
+        .name           = "mcbsp_fck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .id             = 3,
+        .init           = &omap2_init_clksel_parent,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430_EN_MCBSP3_SHIFT,
+        .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
+        .clksel_mask    = OMAP2_MCBSP3_CLKS_MASK,
+        .clksel         = mcbsp_234_clksel,
+        .clkdm_name     = "per_clkdm",
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static struct clk mcbsp4_fck = {
+        .name           = "mcbsp_fck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .id             = 4,
+        .init           = &omap2_init_clksel_parent,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430_EN_MCBSP4_SHIFT,
+        .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
+        .clksel_mask    = OMAP2_MCBSP4_CLKS_MASK,
+        .clksel         = mcbsp_234_clksel,
+        .clkdm_name     = "per_clkdm",
+        .recalc         = &omap2_clksel_recalc,
+};
+
+/* EMU clocks */
+
+/* More information: ARM Cortex-A8 Technical Reference Manual, sect 10.1 */
+
+static const struct clksel_rate emu_src_sys_rates[] = {
+        { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
+        { .div = 0 },
+};
+
+static const struct clksel_rate emu_src_core_rates[] = {
+        { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
+        { .div = 0 },
+};
+
+static const struct clksel_rate emu_src_per_rates[] = {
+        { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
+        { .div = 0 },
+};
+
+static const struct clksel_rate emu_src_mpu_rates[] = {
+        { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
+        { .div = 0 },
+};
+
+static const struct clksel emu_src_clksel[] = {
+        { .parent = &sys_ck,            .rates = emu_src_sys_rates },
+        { .parent = &emu_core_alwon_ck, .rates = emu_src_core_rates },
+        { .parent = &emu_per_alwon_ck,  .rates = emu_src_per_rates },
+        { .parent = &emu_mpu_alwon_ck,  .rates = emu_src_mpu_rates },
+        { .parent = NULL },
+};
+
+/*
+ * Like the clkout_src clocks, emu_src_clk is a virtual clock, existing only
+ * to switch the source of some of the EMU clocks.
+ * XXX Are there CLKEN bits for these EMU clks?
+ */
+static struct clk emu_src_ck = {
+        .name           = "emu_src_ck",
+        .ops            = &clkops_null,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
+        .clksel_mask    = OMAP3430_MUX_CTRL_MASK,
+        .clksel         = emu_src_clksel,
+        .clkdm_name     = "emu_clkdm",
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static const struct clksel_rate pclk_emu_rates[] = {
+        { .div = 2, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
+        { .div = 3, .val = 3, .flags = RATE_IN_343X },
+        { .div = 4, .val = 4, .flags = RATE_IN_343X },
+        { .div = 6, .val = 6, .flags = RATE_IN_343X },
+        { .div = 0 },
+};
+
+static const struct clksel pclk_emu_clksel[] = {
+        { .parent = &emu_src_ck, .rates = pclk_emu_rates },
+        { .parent = NULL },
+};
+
+static struct clk pclk_fck = {
+        .name           = "pclk_fck",
+        .ops            = &clkops_null,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
+        .clksel_mask    = OMAP3430_CLKSEL_PCLK_MASK,
+        .clksel         = pclk_emu_clksel,
+        .clkdm_name     = "emu_clkdm",
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static const struct clksel_rate pclkx2_emu_rates[] = {
+        { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
+        { .div = 2, .val = 2, .flags = RATE_IN_343X },
+        { .div = 3, .val = 3, .flags = RATE_IN_343X },
+        { .div = 0 },
+};
+
+static const struct clksel pclkx2_emu_clksel[] = {
+        { .parent = &emu_src_ck, .rates = pclkx2_emu_rates },
+        { .parent = NULL },
+};
+
+static struct clk pclkx2_fck = {
+        .name           = "pclkx2_fck",
+        .ops            = &clkops_null,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
+        .clksel_mask    = OMAP3430_CLKSEL_PCLKX2_MASK,
+        .clksel         = pclkx2_emu_clksel,
+        .clkdm_name     = "emu_clkdm",
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static const struct clksel atclk_emu_clksel[] = {
+        { .parent = &emu_src_ck, .rates = div2_rates },
+        { .parent = NULL },
+};
+
+static struct clk atclk_fck = {
+        .name           = "atclk_fck",
+        .ops            = &clkops_null,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
+        .clksel_mask    = OMAP3430_CLKSEL_ATCLK_MASK,
+        .clksel         = atclk_emu_clksel,
+        .clkdm_name     = "emu_clkdm",
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static struct clk traceclk_src_fck = {
+        .name           = "traceclk_src_fck",
+        .ops            = &clkops_null,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
+        .clksel_mask    = OMAP3430_TRACE_MUX_CTRL_MASK,
+        .clksel         = emu_src_clksel,
+        .clkdm_name     = "emu_clkdm",
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static const struct clksel_rate traceclk_rates[] = {
+        { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
+        { .div = 2, .val = 2, .flags = RATE_IN_343X },
+        { .div = 4, .val = 4, .flags = RATE_IN_343X },
+        { .div = 0 },
+};
+
+static const struct clksel traceclk_clksel[] = {
+        { .parent = &traceclk_src_fck, .rates = traceclk_rates },
+        { .parent = NULL },
+};
+
+static struct clk traceclk_fck = {
+        .name           = "traceclk_fck",
+        .ops            = &clkops_null,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
+        .clksel_mask    = OMAP3430_CLKSEL_TRACECLK_MASK,
+        .clksel         = traceclk_clksel,
+        .clkdm_name     = "emu_clkdm",
+        .recalc         = &omap2_clksel_recalc,
+};
+
+/* SR clocks */
+
+/* SmartReflex fclk (VDD1) */
+static struct clk sr1_fck = {
+        .name           = "sr1_fck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &sys_ck,
+        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430_EN_SR1_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+/* SmartReflex fclk (VDD2) */
+static struct clk sr2_fck = {
+        .name           = "sr2_fck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &sys_ck,
+        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430_EN_SR2_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk sr_l4_ick = {
+        .name           = "sr_l4_ick",
+        .ops            = &clkops_null, /* RMK: missing? */
+        .parent         = &l4_ick,
+        .clkdm_name     = "core_l4_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+/* SECURE_32K_FCK clocks */
+
+static struct clk gpt12_fck = {
+        .name           = "gpt12_fck",
+        .ops            = &clkops_null,
+        .parent         = &secure_32k_fck,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk wdt1_fck = {
+        .name           = "wdt1_fck",
+        .ops            = &clkops_null,
+        .parent         = &secure_32k_fck,
+        .recalc         = &followparent_recalc,
+};
+
+
+/*
+ * clkdev
+ */
+
+static struct omap_clk omap34xx_clks[] = {
+        CLK(NULL,       "omap_32k_fck", &omap_32k_fck,  CK_343X),
+        CLK(NULL,       "virt_12m_ck",  &virt_12m_ck,   CK_343X),
+        CLK(NULL,       "virt_13m_ck",  &virt_13m_ck,   CK_343X),
+        CLK(NULL,       "virt_16_8m_ck", &virt_16_8m_ck, CK_3430ES2),
+        CLK(NULL,       "virt_19_2m_ck", &virt_19_2m_ck, CK_343X),
+        CLK(NULL,       "virt_26m_ck",  &virt_26m_ck,   CK_343X),
+        CLK(NULL,       "virt_38_4m_ck", &virt_38_4m_ck, CK_343X),
+        CLK(NULL,       "osc_sys_ck",   &osc_sys_ck,    CK_343X),
+        CLK(NULL,       "sys_ck",       &sys_ck,        CK_343X),
+        CLK(NULL,       "sys_altclk",   &sys_altclk,    CK_343X),
+        CLK(NULL,       "mcbsp_clks",   &mcbsp_clks,    CK_343X),
+        CLK(NULL,       "sys_clkout1",  &sys_clkout1,   CK_343X),
+        CLK(NULL,       "dpll1_ck",     &dpll1_ck,      CK_343X),
+        CLK(NULL,       "dpll1_x2_ck",  &dpll1_x2_ck,   CK_343X),
+        CLK(NULL,       "dpll1_x2m2_ck", &dpll1_x2m2_ck, CK_343X),
+        CLK(NULL,       "dpll2_ck",     &dpll2_ck,      CK_343X),
+        CLK(NULL,       "dpll2_m2_ck",  &dpll2_m2_ck,   CK_343X),
+        CLK(NULL,       "dpll3_ck",     &dpll3_ck,      CK_343X),
+        CLK(NULL,       "core_ck",      &core_ck,       CK_343X),
+        CLK(NULL,       "dpll3_x2_ck",  &dpll3_x2_ck,   CK_343X),
+        CLK(NULL,       "dpll3_m2_ck",  &dpll3_m2_ck,   CK_343X),
+        CLK(NULL,       "dpll3_m2x2_ck", &dpll3_m2x2_ck, CK_343X),
+        CLK(NULL,       "dpll3_m3_ck",  &dpll3_m3_ck,   CK_343X),
+        CLK(NULL,       "dpll3_m3x2_ck", &dpll3_m3x2_ck, CK_343X),
+        CLK("etb",      "emu_core_alwon_ck", &emu_core_alwon_ck, CK_343X),
+        CLK(NULL,       "dpll4_ck",     &dpll4_ck,      CK_343X),
+        CLK(NULL,       "dpll4_x2_ck",  &dpll4_x2_ck,   CK_343X),
+        CLK(NULL,       "omap_96m_alwon_fck", &omap_96m_alwon_fck, CK_343X),
+        CLK(NULL,       "omap_96m_fck", &omap_96m_fck,  CK_343X),
+        CLK(NULL,       "cm_96m_fck",   &cm_96m_fck,    CK_343X),
+        CLK(NULL,       "omap_54m_fck", &omap_54m_fck,  CK_343X),
+        CLK(NULL,       "omap_48m_fck", &omap_48m_fck,  CK_343X),
+        CLK(NULL,       "omap_12m_fck", &omap_12m_fck,  CK_343X),
+        CLK(NULL,       "dpll4_m2_ck",  &dpll4_m2_ck,   CK_343X),
+        CLK(NULL,       "dpll4_m2x2_ck", &dpll4_m2x2_ck, CK_343X),
+        CLK(NULL,       "dpll4_m3_ck",  &dpll4_m3_ck,   CK_343X),
+        CLK(NULL,       "dpll4_m3x2_ck", &dpll4_m3x2_ck, CK_343X),
+        CLK(NULL,       "dpll4_m4_ck",  &dpll4_m4_ck,   CK_343X),
+        CLK(NULL,       "dpll4_m4x2_ck", &dpll4_m4x2_ck, CK_343X),
+        CLK(NULL,       "dpll4_m5_ck",  &dpll4_m5_ck,   CK_343X),
+        CLK(NULL,       "dpll4_m5x2_ck", &dpll4_m5x2_ck, CK_343X),
+        CLK(NULL,       "dpll4_m6_ck",  &dpll4_m6_ck,   CK_343X),
+        CLK(NULL,       "dpll4_m6x2_ck", &dpll4_m6x2_ck, CK_343X),
+        CLK("etb",      "emu_per_alwon_ck", &emu_per_alwon_ck, CK_343X),
+        CLK(NULL,       "dpll5_ck",     &dpll5_ck,      CK_3430ES2),
+        CLK(NULL,       "dpll5_m2_ck",  &dpll5_m2_ck,   CK_3430ES2),
+        CLK(NULL,       "clkout2_src_ck", &clkout2_src_ck, CK_343X),
+        CLK(NULL,       "sys_clkout2",  &sys_clkout2,   CK_343X),
+        CLK(NULL,       "corex2_fck",   &corex2_fck,    CK_343X),
+        CLK(NULL,       "dpll1_fck",    &dpll1_fck,     CK_343X),
+        CLK(NULL,       "mpu_ck",       &mpu_ck,        CK_343X),
+        CLK(NULL,       "arm_fck",      &arm_fck,       CK_343X),
+        CLK("etb",      "emu_mpu_alwon_ck", &emu_mpu_alwon_ck, CK_343X),
+        CLK(NULL,       "dpll2_fck",    &dpll2_fck,     CK_343X),
+        CLK(NULL,       "iva2_ck",      &iva2_ck,       CK_343X),
+        CLK(NULL,       "l3_ick",       &l3_ick,        CK_343X),
+        CLK(NULL,       "l4_ick",       &l4_ick,        CK_343X),
+        CLK(NULL,       "rm_ick",       &rm_ick,        CK_343X),
+        CLK(NULL,       "gfx_l3_ck",    &gfx_l3_ck,     CK_3430ES1),
+        CLK(NULL,       "gfx_l3_fck",   &gfx_l3_fck,    CK_3430ES1),
+        CLK(NULL,       "gfx_l3_ick",   &gfx_l3_ick,    CK_3430ES1),
+        CLK(NULL,       "gfx_cg1_ck",   &gfx_cg1_ck,    CK_3430ES1),
+        CLK(NULL,       "gfx_cg2_ck",   &gfx_cg2_ck,    CK_3430ES1),
+        CLK(NULL,       "sgx_fck",      &sgx_fck,       CK_3430ES2),
+        CLK(NULL,       "sgx_ick",      &sgx_ick,       CK_3430ES2),
+        CLK(NULL,       "d2d_26m_fck",  &d2d_26m_fck,   CK_3430ES1),
+        CLK(NULL,       "modem_fck",    &modem_fck,     CK_343X),
+        CLK(NULL,       "sad2d_ick",    &sad2d_ick,     CK_343X),
+        CLK(NULL,       "mad2d_ick",    &mad2d_ick,     CK_343X),
+        CLK(NULL,       "gpt10_fck",    &gpt10_fck,     CK_343X),
+        CLK(NULL,       "gpt11_fck",    &gpt11_fck,     CK_343X),
+        CLK(NULL,       "cpefuse_fck",  &cpefuse_fck,   CK_3430ES2),
+        CLK(NULL,       "ts_fck",       &ts_fck,        CK_3430ES2),
+        CLK(NULL,       "usbtll_fck",   &usbtll_fck,    CK_3430ES2),
+        CLK(NULL,       "core_96m_fck", &core_96m_fck,  CK_343X),
+        CLK("mmci-omap-hs.2",   "fck",  &mmchs3_fck,    CK_3430ES2),
+        CLK("mmci-omap-hs.1",   "fck",  &mmchs2_fck,    CK_343X),
+        CLK(NULL,       "mspro_fck",    &mspro_fck,     CK_343X),
+        CLK("mmci-omap-hs.0",   "fck",  &mmchs1_fck,    CK_343X),
+        CLK("i2c_omap.3", "fck",        &i2c3_fck,      CK_343X),
+        CLK("i2c_omap.2", "fck",        &i2c2_fck,      CK_343X),
+        CLK("i2c_omap.1", "fck",        &i2c1_fck,      CK_343X),
+        CLK("omap-mcbsp.5", "fck",      &mcbsp5_fck,    CK_343X),
+        CLK("omap-mcbsp.1", "fck",      &mcbsp1_fck,    CK_343X),
+        CLK(NULL,       "core_48m_fck", &core_48m_fck,  CK_343X),
+        CLK("omap2_mcspi.4", "fck",     &mcspi4_fck,    CK_343X),
+        CLK("omap2_mcspi.3", "fck",     &mcspi3_fck,    CK_343X),
+        CLK("omap2_mcspi.2", "fck",     &mcspi2_fck,    CK_343X),
+        CLK("omap2_mcspi.1", "fck",     &mcspi1_fck,    CK_343X),
+        CLK(NULL,       "uart2_fck",    &uart2_fck,     CK_343X),
+        CLK(NULL,       "uart1_fck",    &uart1_fck,     CK_343X),
+        CLK(NULL,       "fshostusb_fck", &fshostusb_fck, CK_3430ES1),
+        CLK(NULL,       "core_12m_fck", &core_12m_fck,  CK_343X),
+        CLK("omap_hdq.0", "fck",        &hdq_fck,       CK_343X),
+        CLK(NULL,       "ssi_ssr_fck",  &ssi_ssr_fck_3430es1,   CK_3430ES1),
+        CLK(NULL,       "ssi_ssr_fck",  &ssi_ssr_fck_3430es2,   CK_3430ES2),
+        CLK(NULL,       "ssi_sst_fck",  &ssi_sst_fck_3430es1,   CK_3430ES1),
+        CLK(NULL,       "ssi_sst_fck",  &ssi_sst_fck_3430es2,   CK_3430ES2),
+        CLK(NULL,       "core_l3_ick",  &core_l3_ick,   CK_343X),
+        CLK("musb_hdrc",        "ick",  &hsotgusb_ick_3430es1,  CK_3430ES1),
+        CLK("musb_hdrc",        "ick",  &hsotgusb_ick_3430es2,  CK_3430ES2),
+        CLK(NULL,       "sdrc_ick",     &sdrc_ick,      CK_343X),
+        CLK(NULL,       "gpmc_fck",     &gpmc_fck,      CK_343X),
+        CLK(NULL,       "security_l3_ick", &security_l3_ick, CK_343X),
+        CLK(NULL,       "pka_ick",      &pka_ick,       CK_343X),
+        CLK(NULL,       "core_l4_ick",  &core_l4_ick,   CK_343X),
+        CLK(NULL,       "usbtll_ick",   &usbtll_ick,    CK_3430ES2),
+        CLK("mmci-omap-hs.2",   "ick",  &mmchs3_ick,    CK_3430ES2),
+        CLK(NULL,       "icr_ick",      &icr_ick,       CK_343X),
+        CLK(NULL,       "aes2_ick",     &aes2_ick,      CK_343X),
+        CLK(NULL,       "sha12_ick",    &sha12_ick,     CK_343X),
+        CLK(NULL,       "des2_ick",     &des2_ick,      CK_343X),
+        CLK("mmci-omap-hs.1",   "ick",  &mmchs2_ick,    CK_343X),
+        CLK("mmci-omap-hs.0",   "ick",  &mmchs1_ick,    CK_343X),
+        CLK(NULL,       "mspro_ick",    &mspro_ick,     CK_343X),
+        CLK("omap_hdq.0", "ick",        &hdq_ick,       CK_343X),
+        CLK("omap2_mcspi.4", "ick",     &mcspi4_ick,    CK_343X),
+        CLK("omap2_mcspi.3", "ick",     &mcspi3_ick,    CK_343X),
+        CLK("omap2_mcspi.2", "ick",     &mcspi2_ick,    CK_343X),
+        CLK("omap2_mcspi.1", "ick",     &mcspi1_ick,    CK_343X),
+        CLK("i2c_omap.3", "ick",        &i2c3_ick,      CK_343X),
+        CLK("i2c_omap.2", "ick",        &i2c2_ick,      CK_343X),
+        CLK("i2c_omap.1", "ick",        &i2c1_ick,      CK_343X),
+        CLK(NULL,       "uart2_ick",    &uart2_ick,     CK_343X),
+        CLK(NULL,       "uart1_ick",    &uart1_ick,     CK_343X),
+        CLK(NULL,       "gpt11_ick",    &gpt11_ick,     CK_343X),
+        CLK(NULL,       "gpt10_ick",    &gpt10_ick,     CK_343X),
+        CLK("omap-mcbsp.5", "ick",      &mcbsp5_ick,    CK_343X),
+        CLK("omap-mcbsp.1", "ick",      &mcbsp1_ick,    CK_343X),
+        CLK(NULL,       "fac_ick",      &fac_ick,       CK_3430ES1),
+        CLK(NULL,       "mailboxes_ick", &mailboxes_ick, CK_343X),
+        CLK(NULL,       "omapctrl_ick", &omapctrl_ick,  CK_343X),
+        CLK(NULL,       "ssi_l4_ick",   &ssi_l4_ick,    CK_343X),
+        CLK(NULL,       "ssi_ick",      &ssi_ick_3430es1,       CK_3430ES1),
+        CLK(NULL,       "ssi_ick",      &ssi_ick_3430es2,       CK_3430ES2),
+        CLK(NULL,       "usb_l4_ick",   &usb_l4_ick,    CK_3430ES1),
+        CLK(NULL,       "security_l4_ick2", &security_l4_ick2, CK_343X),
+        CLK(NULL,       "aes1_ick",     &aes1_ick,      CK_343X),
+        CLK("omap_rng", "ick",          &rng_ick,       CK_343X),
+        CLK(NULL,       "sha11_ick",    &sha11_ick,     CK_343X),
+        CLK(NULL,       "des1_ick",     &des1_ick,      CK_343X),
+        CLK("omapdss",  "dss1_fck",     &dss1_alwon_fck_3430es1, CK_3430ES1),
+        CLK("omapdss",  "dss1_fck",     &dss1_alwon_fck_3430es2, CK_3430ES2),
+        CLK("omapdss",  "tv_fck",       &dss_tv_fck,    CK_343X),
+        CLK("omapdss",  "video_fck",    &dss_96m_fck,   CK_343X),
+        CLK("omapdss",  "dss2_fck",     &dss2_alwon_fck, CK_343X),
+        CLK("omapdss",  "ick",          &dss_ick_3430es1,       CK_3430ES1),
+        CLK("omapdss",  "ick",          &dss_ick_3430es2,       CK_3430ES2),
+        CLK(NULL,       "cam_mclk",     &cam_mclk,      CK_343X),
+        CLK(NULL,       "cam_ick",      &cam_ick,       CK_343X),
+        CLK(NULL,       "csi2_96m_fck", &csi2_96m_fck,  CK_343X),
+        CLK(NULL,       "usbhost_120m_fck", &usbhost_120m_fck, CK_3430ES2),
+        CLK(NULL,       "usbhost_48m_fck", &usbhost_48m_fck, CK_3430ES2),
+        CLK(NULL,       "usbhost_ick",  &usbhost_ick,   CK_3430ES2),
+        CLK(NULL,       "usim_fck",     &usim_fck,      CK_3430ES2),
+        CLK(NULL,       "gpt1_fck",     &gpt1_fck,      CK_343X),
+        CLK(NULL,       "wkup_32k_fck", &wkup_32k_fck,  CK_343X),
+        CLK(NULL,       "gpio1_dbck",   &gpio1_dbck,    CK_343X),
+        CLK("omap_wdt", "fck",          &wdt2_fck,      CK_343X),
+        CLK(NULL,       "wkup_l4_ick",  &wkup_l4_ick,   CK_343X),
+        CLK(NULL,       "usim_ick",     &usim_ick,      CK_3430ES2),
+        CLK("omap_wdt", "ick",          &wdt2_ick,      CK_343X),
+        CLK(NULL,       "wdt1_ick",     &wdt1_ick,      CK_343X),
+        CLK(NULL,       "gpio1_ick",    &gpio1_ick,     CK_343X),
+        CLK(NULL,       "omap_32ksync_ick", &omap_32ksync_ick, CK_343X),
+        CLK(NULL,       "gpt12_ick",    &gpt12_ick,     CK_343X),
+        CLK(NULL,       "gpt1_ick",     &gpt1_ick,      CK_343X),
+        CLK(NULL,       "per_96m_fck",  &per_96m_fck,   CK_343X),
+        CLK(NULL,       "per_48m_fck",  &per_48m_fck,   CK_343X),
+        CLK(NULL,       "uart3_fck",    &uart3_fck,     CK_343X),
+        CLK(NULL,       "gpt2_fck",     &gpt2_fck,      CK_343X),
+        CLK(NULL,       "gpt3_fck",     &gpt3_fck,      CK_343X),
+        CLK(NULL,       "gpt4_fck",     &gpt4_fck,      CK_343X),
+        CLK(NULL,       "gpt5_fck",     &gpt5_fck,      CK_343X),
+        CLK(NULL,       "gpt6_fck",     &gpt6_fck,      CK_343X),
+        CLK(NULL,       "gpt7_fck",     &gpt7_fck,      CK_343X),
+        CLK(NULL,       "gpt8_fck",     &gpt8_fck,      CK_343X),
+        CLK(NULL,       "gpt9_fck",     &gpt9_fck,      CK_343X),
+        CLK(NULL,       "per_32k_alwon_fck", &per_32k_alwon_fck, CK_343X),
+        CLK(NULL,       "gpio6_dbck",   &gpio6_dbck,    CK_343X),
+        CLK(NULL,       "gpio5_dbck",   &gpio5_dbck,    CK_343X),
+        CLK(NULL,       "gpio4_dbck",   &gpio4_dbck,    CK_343X),
+        CLK(NULL,       "gpio3_dbck",   &gpio3_dbck,    CK_343X),
+        CLK(NULL,       "gpio2_dbck",   &gpio2_dbck,    CK_343X),
+        CLK(NULL,       "wdt3_fck",     &wdt3_fck,      CK_343X),
+        CLK(NULL,       "per_l4_ick",   &per_l4_ick,    CK_343X),
+        CLK(NULL,       "gpio6_ick",    &gpio6_ick,     CK_343X),
+        CLK(NULL,       "gpio5_ick",    &gpio5_ick,     CK_343X),
+        CLK(NULL,       "gpio4_ick",    &gpio4_ick,     CK_343X),
+        CLK(NULL,       "gpio3_ick",    &gpio3_ick,     CK_343X),
+        CLK(NULL,       "gpio2_ick",    &gpio2_ick,     CK_343X),
+        CLK(NULL,       "wdt3_ick",     &wdt3_ick,      CK_343X),
+        CLK(NULL,       "uart3_ick",    &uart3_ick,     CK_343X),
+        CLK(NULL,       "gpt9_ick",     &gpt9_ick,      CK_343X),
+        CLK(NULL,       "gpt8_ick",     &gpt8_ick,      CK_343X),
+        CLK(NULL,       "gpt7_ick",     &gpt7_ick,      CK_343X),
+        CLK(NULL,       "gpt6_ick",     &gpt6_ick,      CK_343X),
+        CLK(NULL,       "gpt5_ick",     &gpt5_ick,      CK_343X),
+        CLK(NULL,       "gpt4_ick",     &gpt4_ick,      CK_343X),
+        CLK(NULL,       "gpt3_ick",     &gpt3_ick,      CK_343X),
+        CLK(NULL,       "gpt2_ick",     &gpt2_ick,      CK_343X),
+        CLK("omap-mcbsp.2", "ick",      &mcbsp2_ick,    CK_343X),
+        CLK("omap-mcbsp.3", "ick",      &mcbsp3_ick,    CK_343X),
+        CLK("omap-mcbsp.4", "ick",      &mcbsp4_ick,    CK_343X),
+        CLK("omap-mcbsp.2", "fck",      &mcbsp2_fck,    CK_343X),
+        CLK("omap-mcbsp.3", "fck",      &mcbsp3_fck,    CK_343X),
+        CLK("omap-mcbsp.4", "fck",      &mcbsp4_fck,    CK_343X),
+        CLK("etb",      "emu_src_ck",   &emu_src_ck,    CK_343X),
+        CLK(NULL,       "pclk_fck",     &pclk_fck,      CK_343X),
+        CLK(NULL,       "pclkx2_fck",   &pclkx2_fck,    CK_343X),
+        CLK(NULL,       "atclk_fck",    &atclk_fck,     CK_343X),
+        CLK(NULL,       "traceclk_src_fck", &traceclk_src_fck, CK_343X),
+        CLK(NULL,       "traceclk_fck", &traceclk_fck,  CK_343X),
+        CLK(NULL,       "sr1_fck",      &sr1_fck,       CK_343X),
+        CLK(NULL,       "sr2_fck",      &sr2_fck,       CK_343X),
+        CLK(NULL,       "sr_l4_ick",    &sr_l4_ick,     CK_343X),
+        CLK(NULL,       "secure_32k_fck", &secure_32k_fck, CK_343X),
+        CLK(NULL,       "gpt12_fck",    &gpt12_fck,     CK_343X),
+        CLK(NULL,       "wdt1_fck",     &wdt1_fck,      CK_343X),
+};
+
+
+int __init omap2_clk_init(void)
+{
+        /* struct prcm_config *prcm; */
+        struct omap_clk *c;
+        /* u32 clkrate; */
+        u32 cpu_clkflg;
+
+        if (cpu_is_omap34xx()) {
+                cpu_mask = RATE_IN_343X;
+                cpu_clkflg = CK_343X;
+
+                /*
+                 * Update this if there are further clock changes between ES2
+                 * and production parts
+                 */
+                if (omap_rev() == OMAP3430_REV_ES1_0) {
+                        /* No 3430ES1-only rates exist, so no RATE_IN_3430ES1 */
+                        cpu_clkflg |= CK_3430ES1;
+                } else {
+                        cpu_mask |= RATE_IN_3430ES2;
+                        cpu_clkflg |= CK_3430ES2;
+                }
+        }
+
+        clk_init(&omap2_clk_functions);
+
+        for (c = omap34xx_clks; c < omap34xx_clks + ARRAY_SIZE(omap34xx_clks); c++)
+                clk_preinit(c->lk.clk);
+
+        for (c = omap34xx_clks; c < omap34xx_clks + ARRAY_SIZE(omap34xx_clks); c++)
+                if (c->cpu & cpu_clkflg) {
+                        clkdev_add(&c->lk);
+                        clk_register(c->lk.clk);
+                        omap2_init_clk_clkdm(c->lk.clk);
+                }
+
+        /* REVISIT: Not yet ready for OMAP3 */
+#if 0
+        /* Check the MPU rate set by bootloader */
+        clkrate = omap2_get_dpll_rate_24xx(&dpll_ck);
+        for (prcm = rate_table; prcm->mpu_speed; prcm++) {
+                if (!(prcm->flags & cpu_mask))
+                        continue;
+                if (prcm->xtal_speed != sys_ck.rate)
+                        continue;
+                if (prcm->dpll_speed <= clkrate)
+                        break;
+        }
+        curr_prcm_set = prcm;
+#endif
+
+        recalculate_root_clocks();
+
+        printk(KERN_INFO "Clocking rate (Crystal/Core/MPU): "
+               "%ld.%01ld/%ld/%ld MHz\n",
+               (osc_sys_ck.rate / 1000000), (osc_sys_ck.rate / 100000) % 10,
+               (core_ck.rate / 1000000), (arm_fck.rate / 1000000));
+
+        /*
+         * Only enable those clocks we will need, let the drivers
+         * enable other clocks as necessary
+         */
+        clk_enable_init_clocks();
+
+        /*
+         * Lock DPLL5 and put it in autoidle.
+         */
+        if (omap_rev() >= OMAP3430_REV_ES2_0)
+                omap3_clk_lock_dpll5();
+
+        /* Avoid sleeping during omap3_core_dpll_m2_set_rate() */
+        sdrc_ick_p = clk_get(NULL, "sdrc_ick");
+        arm_fck_p = clk_get(NULL, "arm_fck");
+
+        return 0;
+}
diff --git a/arch/arm/mach-omap2/clock44xx.c b/arch/arm/mach-omap2/clock44xx.c
new file mode 100644
index 000000000000..e370868a79a8
--- /dev/null
+++ b/arch/arm/mach-omap2/clock44xx.c
@@ -0,0 +1,33 @@
+/*
+ * OMAP4-specific clock framework functions
+ *
+ * Copyright (C) 2009 Texas Instruments, Inc.
+ *
+ * Rajendra Nayak (rnayak@ti.com)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/errno.h>
+#include "clock.h"
+
+struct clk_functions omap2_clk_functions = {
+        .clk_enable             = omap2_clk_enable,
+        .clk_disable            = omap2_clk_disable,
+        .clk_round_rate         = omap2_clk_round_rate,
+        .clk_set_rate           = omap2_clk_set_rate,
+        .clk_set_parent         = omap2_clk_set_parent,
+        .clk_disable_unused     = omap2_clk_disable_unused,
+};
+
+const struct clkops clkops_noncore_dpll_ops = {
+        .enable         = &omap3_noncore_dpll_enable,
+        .disable        = &omap3_noncore_dpll_disable,
+};
+
+void omap2_clk_prepare_for_reboot(void)
+{
+        return;
+}
diff --git a/arch/arm/mach-omap2/clock44xx.h b/arch/arm/mach-omap2/clock44xx.h
new file mode 100644
index 000000000000..59b9ced4daa1
--- /dev/null
+++ b/arch/arm/mach-omap2/clock44xx.h
@@ -0,0 +1,15 @@
+/*
+ * OMAP4 clock function prototypes and macros
+ *
+ * Copyright (C) 2009 Texas Instruments, Inc.
+ */
+
+#ifndef __ARCH_ARM_MACH_OMAP2_CLOCK_44XX_H
+#define __ARCH_ARM_MACH_OMAP2_CLOCK_44XX_H
+
+#define OMAP4430_MAX_DPLL_MULT  2048
+#define OMAP4430_MAX_DPLL_DIV   128
+
+extern const struct clkops clkops_noncore_dpll_ops;
+
+#endif
diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c
new file mode 100644
index 000000000000..2210e227d78a
--- /dev/null
+++ b/arch/arm/mach-omap2/clock44xx_data.c
@@ -0,0 +1,2766 @@
+/*
+ * OMAP4 Clock data
+ *
+ * Copyright (C) 2009 Texas Instruments, Inc.
+ * Copyright (C) 2009 Nokia Corporation
+ *
+ * Paul Walmsley (paul@pwsan.com)
+ * Rajendra Nayak (rnayak@ti.com)
+ * Benoit Cousson (b-cousson@ti.com)
+ *
+ * This file is automatically generated from the OMAP hardware databases.
+ * We respectfully ask that any modifications to this file be coordinated
+ * with the public linux-omap@vger.kernel.org mailing list and the
+ * authors above to ensure that the autogeneration scripts are kept
+ * up-to-date with the file contents.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/clk.h>
+
+#include <plat/control.h>
+#include <plat/clkdev_omap.h>
+
+#include "clock.h"
+#include "clock44xx.h"
+#include "cm.h"
+#include "cm-regbits-44xx.h"
+#include "prm.h"
+#include "prm-regbits-44xx.h"
+
+/* Root clocks */
+
+static struct clk extalt_clkin_ck = {
+        .name           = "extalt_clkin_ck",
+        .rate           = 59000000,
+        .ops            = &clkops_null,
+        .flags          = CLOCK_IN_OMAP4430 | ALWAYS_ENABLED,
+};
+
+static struct clk pad_clks_ck = {
+        .name           = "pad_clks_ck",
+        .rate           = 12000000,
+        .ops            = &clkops_null,
+        .flags          = CLOCK_IN_OMAP4430 | ALWAYS_ENABLED,
+};
+
+static struct clk pad_slimbus_core_clks_ck = {
+        .name           = "pad_slimbus_core_clks_ck",
+        .rate           = 12000000,
+        .ops            = &clkops_null,
+        .flags          = CLOCK_IN_OMAP4430 | ALWAYS_ENABLED,
+};
+
+static struct clk secure_32k_clk_src_ck = {
+        .name           = "secure_32k_clk_src_ck",
+        .rate           = 32768,
+        .ops            = &clkops_null,
+        .flags          = CLOCK_IN_OMAP4430 | ALWAYS_ENABLED,
+};
+
+static struct clk slimbus_clk = {
+        .name           = "slimbus_clk",
+        .rate           = 12000000,
+        .ops            = &clkops_null,
+        .flags          = CLOCK_IN_OMAP4430 | ALWAYS_ENABLED,
+};
+
+static struct clk sys_32k_ck = {
+        .name           = "sys_32k_ck",
+        .rate           = 32768,
+        .ops            = &clkops_null,
+        .flags          = CLOCK_IN_OMAP4430 | ALWAYS_ENABLED,
+};
+
+static struct clk virt_12000000_ck = {
+        .name           = "virt_12000000_ck",
+        .ops            = &clkops_null,
+        .rate           = 12000000,
+};
+
+static struct clk virt_13000000_ck = {
+        .name           = "virt_13000000_ck",
+        .ops            = &clkops_null,
+        .rate           = 13000000,
+};
+
+static struct clk virt_16800000_ck = {
+        .name           = "virt_16800000_ck",
+        .ops            = &clkops_null,
+        .rate           = 16800000,
+};
+
+static struct clk virt_19200000_ck = {
+        .name           = "virt_19200000_ck",
+        .ops            = &clkops_null,
+        .rate           = 19200000,
+};
+
+static struct clk virt_26000000_ck = {
+        .name           = "virt_26000000_ck",
+        .ops            = &clkops_null,
+        .rate           = 26000000,
+};
+
+static struct clk virt_27000000_ck = {
+        .name           = "virt_27000000_ck",
+        .ops            = &clkops_null,
+        .rate           = 27000000,
+};
+
+static struct clk virt_38400000_ck = {
+        .name           = "virt_38400000_ck",
+        .ops            = &clkops_null,
+        .rate           = 38400000,
+};
+
+static const struct clksel_rate div_1_0_rates[] = {
+        { .div = 1, .val = 0, .flags = RATE_IN_4430 },
+        { .div = 0 },
+};
+
+static const struct clksel_rate div_1_1_rates[] = {
+        { .div = 1, .val = 1, .flags = RATE_IN_4430 },
+        { .div = 0 },
+};
+
+static const struct clksel_rate div_1_2_rates[] = {
+        { .div = 1, .val = 2, .flags = RATE_IN_4430 },
+        { .div = 0 },
+};
+
+static const struct clksel_rate div_1_3_rates[] = {
+        { .div = 1, .val = 3, .flags = RATE_IN_4430 },
+        { .div = 0 },
+};
+
+static const struct clksel_rate div_1_4_rates[] = {
+        { .div = 1, .val = 4, .flags = RATE_IN_4430 },
+        { .div = 0 },
+};
+
+static const struct clksel_rate div_1_5_rates[] = {
+        { .div = 1, .val = 5, .flags = RATE_IN_4430 },
+        { .div = 0 },
+};
+
+static const struct clksel_rate div_1_6_rates[] = {
+        { .div = 1, .val = 6, .flags = RATE_IN_4430 },
+        { .div = 0 },
+};
+
+static const struct clksel_rate div_1_7_rates[] = {
+        { .div = 1, .val = 7, .flags = RATE_IN_4430 },
+        { .div = 0 },
+};
+
+static const struct clksel sys_clkin_sel[] = {
+        { .parent = &virt_12000000_ck, .rates = div_1_1_rates },
+        { .parent = &virt_13000000_ck, .rates = div_1_2_rates },
+        { .parent = &virt_16800000_ck, .rates = div_1_3_rates },
+        { .parent = &virt_19200000_ck, .rates = div_1_4_rates },
+        { .parent = &virt_26000000_ck, .rates = div_1_5_rates },
+        { .parent = &virt_27000000_ck, .rates = div_1_6_rates },
+        { .parent = &virt_38400000_ck, .rates = div_1_7_rates },
+        { .parent = NULL },
+};
+
+static struct clk sys_clkin_ck = {
+        .name           = "sys_clkin_ck",
+        .rate           = 38400000,
+        .clksel         = sys_clkin_sel,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP4430_CM_SYS_CLKSEL,
+        .clksel_mask    = OMAP4430_SYS_CLKSEL_MASK,
+        .ops            = &clkops_null,
+        .recalc         = &omap2_clksel_recalc,
+        .flags          = CLOCK_IN_OMAP4430 | ALWAYS_ENABLED,
+};
+
+static struct clk utmi_phy_clkout_ck = {
+        .name           = "utmi_phy_clkout_ck",
+        .rate           = 12000000,
+        .ops            = &clkops_null,
+        .flags          = CLOCK_IN_OMAP4430 | ALWAYS_ENABLED,
+};
+
+static struct clk xclk60mhsp1_ck = {
+        .name           = "xclk60mhsp1_ck",
+        .rate           = 12000000,
+        .ops            = &clkops_null,
+        .flags          = CLOCK_IN_OMAP4430 | ALWAYS_ENABLED,
+};
+
+static struct clk xclk60mhsp2_ck = {
+        .name           = "xclk60mhsp2_ck",
+        .rate           = 12000000,
+        .ops            = &clkops_null,
+        .flags          = CLOCK_IN_OMAP4430 | ALWAYS_ENABLED,
+};
+
+static struct clk xclk60motg_ck = {
+        .name           = "xclk60motg_ck",
+        .rate           = 60000000,
+        .ops            = &clkops_null,
+        .flags          = CLOCK_IN_OMAP4430 | ALWAYS_ENABLED,
+};
+
+/* Module clocks and DPLL outputs */
+
+static const struct clksel_rate div2_1to2_rates[] = {
+        { .div = 1, .val = 0, .flags = RATE_IN_4430 },
+        { .div = 2, .val = 1, .flags = RATE_IN_4430 },
+        { .div = 0 },
+};
+
+static const struct clksel dpll_sys_ref_clk_div[] = {
+        { .parent = &sys_clkin_ck, .rates = div2_1to2_rates },
+        { .parent = NULL },
+};
+
+static struct clk dpll_sys_ref_clk = {
+        .name           = "dpll_sys_ref_clk",
+        .parent         = &sys_clkin_ck,
+        .clksel         = dpll_sys_ref_clk_div,
+        .clksel_reg     = OMAP4430_CM_DPLL_SYS_REF_CLKSEL,
+        .clksel_mask    = OMAP4430_CLKSEL_0_0_MASK,
+        .ops            = &clkops_null,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate,
+        .flags          = CLOCK_IN_OMAP4430,
+};
+
+static const struct clksel abe_dpll_refclk_mux_sel[] = {
+        { .parent = &dpll_sys_ref_clk, .rates = div_1_0_rates },
+        { .parent = &sys_32k_ck, .rates = div_1_1_rates },
+        { .parent = NULL },
+};
+
+static struct clk abe_dpll_refclk_mux_ck = {
+        .name           = "abe_dpll_refclk_mux_ck",
+        .parent         = &dpll_sys_ref_clk,
+        .clksel         = abe_dpll_refclk_mux_sel,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP4430_CM_ABE_PLL_REF_CLKSEL,
+        .clksel_mask    = OMAP4430_CLKSEL_0_0_MASK,
+        .ops            = &clkops_null,
+        .recalc         = &omap2_clksel_recalc,
+        .flags          = CLOCK_IN_OMAP4430,
+};
+
+/* DPLL_ABE */
+static struct dpll_data dpll_abe_dd = {
+        .mult_div1_reg  = OMAP4430_CM_CLKSEL_DPLL_ABE,
+        .clk_bypass     = &sys_clkin_ck,
+        .clk_ref        = &abe_dpll_refclk_mux_ck,
+        .control_reg    = OMAP4430_CM_CLKMODE_DPLL_ABE,
+        .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
+        .autoidle_reg   = OMAP4430_CM_AUTOIDLE_DPLL_ABE,
+        .idlest_reg     = OMAP4430_CM_IDLEST_DPLL_ABE,
+        .mult_mask      = OMAP4430_DPLL_MULT_MASK,
+        .div1_mask      = OMAP4430_DPLL_DIV_MASK,
+        .enable_mask    = OMAP4430_DPLL_EN_MASK,
+        .autoidle_mask  = OMAP4430_AUTO_DPLL_MODE_MASK,
+        .idlest_mask    = OMAP4430_ST_DPLL_CLK_MASK,
+        .max_multiplier = OMAP4430_MAX_DPLL_MULT,
+        .max_divider    = OMAP4430_MAX_DPLL_DIV,
+        .min_divider    = 1,
+};
+
+
+static struct clk dpll_abe_ck = {
+        .name           = "dpll_abe_ck",
+        .parent         = &abe_dpll_refclk_mux_ck,
+        .dpll_data      = &dpll_abe_dd,
+        .init           = &omap2_init_dpll_parent,
+        .ops            = &clkops_noncore_dpll_ops,
+        .recalc         = &omap3_dpll_recalc,
+        .round_rate     = &omap2_dpll_round_rate,
+        .set_rate       = &omap3_noncore_dpll_set_rate,
+        .flags          = CLOCK_IN_OMAP4430,
+};
+
+static struct clk dpll_abe_m2x2_ck = {
+        .name           = "dpll_abe_m2x2_ck",
+        .parent         = &dpll_abe_ck,
+        .ops            = &clkops_null,
+        .recalc         = &followparent_recalc,
+        .flags          = CLOCK_IN_OMAP4430,
+};
+
+static struct clk abe_24m_fclk = {
+        .name           = "abe_24m_fclk",
+        .parent         = &dpll_abe_m2x2_ck,
+        .ops            = &clkops_null,
+        .recalc         = &followparent_recalc,
+        .flags          = CLOCK_IN_OMAP4430,
+};
+
+static const struct clksel_rate div3_1to4_rates[] = {
+        { .div = 1, .val = 0, .flags = RATE_IN_4430 },
+        { .div = 2, .val = 1, .flags = RATE_IN_4430 },
+        { .div = 4, .val = 2, .flags = RATE_IN_4430 },
+        { .div = 0 },
+};
+
+static const struct clksel abe_clk_div[] = {
+        { .parent = &dpll_abe_m2x2_ck, .rates = div3_1to4_rates },
+        { .parent = NULL },
+};
+
+static struct clk abe_clk = {
+        .name           = "abe_clk",
+        .parent         = &dpll_abe_m2x2_ck,
+        .clksel         = abe_clk_div,
+        .clksel_reg     = OMAP4430_CM_CLKSEL_ABE,
+        .clksel_mask    = OMAP4430_CLKSEL_OPP_MASK,
+        .ops            = &clkops_null,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate,
+        .flags          = CLOCK_IN_OMAP4430,
+};
+
+static const struct clksel aess_fclk_div[] = {
+        { .parent = &abe_clk, .rates = div2_1to2_rates },
+        { .parent = NULL },
+};
+
+static struct clk aess_fclk = {
+        .name           = "aess_fclk",
+        .parent         = &abe_clk,
+        .clksel         = aess_fclk_div,
+        .clksel_reg     = OMAP4430_CM1_ABE_AESS_CLKCTRL,
+        .clksel_mask    = OMAP4430_CLKSEL_AESS_FCLK_MASK,
+        .ops            = &clkops_null,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate,
+        .flags          = CLOCK_IN_OMAP4430,
+};
+
+static const struct clksel_rate div31_1to31_rates[] = {
+        { .div = 1, .val = 0, .flags = RATE_IN_4430 },
+        { .div = 2, .val = 1, .flags = RATE_IN_4430 },
+        { .div = 3, .val = 2, .flags = RATE_IN_4430 },
+        { .div = 4, .val = 3, .flags = RATE_IN_4430 },
+        { .div = 5, .val = 4, .flags = RATE_IN_4430 },
+        { .div = 6, .val = 5, .flags = RATE_IN_4430 },
+        { .div = 7, .val = 6, .flags = RATE_IN_4430 },
+        { .div = 8, .val = 7, .flags = RATE_IN_4430 },
+        { .div = 9, .val = 8, .flags = RATE_IN_4430 },
+        { .div = 10, .val = 9, .flags = RATE_IN_4430 },
+        { .div = 11, .val = 10, .flags = RATE_IN_4430 },
+        { .div = 12, .val = 11, .flags = RATE_IN_4430 },
+        { .div = 13, .val = 12, .flags = RATE_IN_4430 },
+        { .div = 14, .val = 13, .flags = RATE_IN_4430 },
+        { .div = 15, .val = 14, .flags = RATE_IN_4430 },
+        { .div = 16, .val = 15, .flags = RATE_IN_4430 },
+        { .div = 17, .val = 16, .flags = RATE_IN_4430 },
+        { .div = 18, .val = 17, .flags = RATE_IN_4430 },
+        { .div = 19, .val = 18, .flags = RATE_IN_4430 },
+        { .div = 20, .val = 19, .flags = RATE_IN_4430 },
+        { .div = 21, .val = 20, .flags = RATE_IN_4430 },
+        { .div = 22, .val = 21, .flags = RATE_IN_4430 },
+        { .div = 23, .val = 22, .flags = RATE_IN_4430 },
+        { .div = 24, .val = 23, .flags = RATE_IN_4430 },
+        { .div = 25, .val = 24, .flags = RATE_IN_4430 },
+        { .div = 26, .val = 25, .flags = RATE_IN_4430 },
+        { .div = 27, .val = 26, .flags = RATE_IN_4430 },
+        { .div = 28, .val = 27, .flags = RATE_IN_4430 },
+        { .div = 29, .val = 28, .flags = RATE_IN_4430 },
+        { .div = 30, .val = 29, .flags = RATE_IN_4430 },
+        { .div = 31, .val = 30, .flags = RATE_IN_4430 },
+        { .div = 0 },
+};
+
+static const struct clksel dpll_abe_m3_div[] = {
+        { .parent = &dpll_abe_ck, .rates = div31_1to31_rates },
+        { .parent = NULL },
+};
+
+static struct clk dpll_abe_m3_ck = {
+        .name           = "dpll_abe_m3_ck",
+        .parent         = &dpll_abe_ck,
+        .clksel         = dpll_abe_m3_div,
+        .clksel_reg     = OMAP4430_CM_DIV_M3_DPLL_ABE,
+        .clksel_mask    = OMAP4430_DPLL_CLKOUTHIF_DIV_MASK,
+        .ops            = &clkops_null,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate,
+        .flags          = CLOCK_IN_OMAP4430,
+};
+
+static const struct clksel core_hsd_byp_clk_mux_sel[] = {
+        { .parent = &dpll_sys_ref_clk, .rates = div_1_0_rates },
+        { .parent = &dpll_abe_m3_ck, .rates = div_1_1_rates },
+        { .parent = NULL },
+};
+
+static struct clk core_hsd_byp_clk_mux_ck = {
+        .name           = "core_hsd_byp_clk_mux_ck",
+        .parent         = &dpll_sys_ref_clk,
+        .clksel         = core_hsd_byp_clk_mux_sel,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP4430_CM_CLKSEL_DPLL_CORE,
+        .clksel_mask    = OMAP4430_DPLL_BYP_CLKSEL_MASK,
+        .ops            = &clkops_null,
+        .recalc         = &omap2_clksel_recalc,
+        .flags          = CLOCK_IN_OMAP4430,
+};
+
+/* DPLL_CORE */
+static struct dpll_data dpll_core_dd = {
+        .mult_div1_reg  = OMAP4430_CM_CLKSEL_DPLL_CORE,
+        .clk_bypass     = &core_hsd_byp_clk_mux_ck,
+        .clk_ref        = &dpll_sys_ref_clk,
+        .control_reg    = OMAP4430_CM_CLKMODE_DPLL_CORE,
+        .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
+        .autoidle_reg   = OMAP4430_CM_AUTOIDLE_DPLL_CORE,
+        .idlest_reg     = OMAP4430_CM_IDLEST_DPLL_CORE,
+        .mult_mask      = OMAP4430_DPLL_MULT_MASK,
+        .div1_mask      = OMAP4430_DPLL_DIV_MASK,
+        .enable_mask    = OMAP4430_DPLL_EN_MASK,
+        .autoidle_mask  = OMAP4430_AUTO_DPLL_MODE_MASK,
+        .idlest_mask    = OMAP4430_ST_DPLL_CLK_MASK,
+        .max_multiplier = OMAP4430_MAX_DPLL_MULT,
+        .max_divider    = OMAP4430_MAX_DPLL_DIV,
+        .min_divider    = 1,
+};
+
+
+static struct clk dpll_core_ck = {
+        .name           = "dpll_core_ck",
+        .parent         = &dpll_sys_ref_clk,
+        .dpll_data      = &dpll_core_dd,
+        .init           = &omap2_init_dpll_parent,
+        .ops            = &clkops_null,
+        .recalc         = &omap3_dpll_recalc,
+        .flags          = CLOCK_IN_OMAP4430,
+};
+
+static const struct clksel dpll_core_m6_div[] = {
+        { .parent = &dpll_core_ck, .rates = div31_1to31_rates },
+        { .parent = NULL },
+};
+
+static struct clk dpll_core_m6_ck = {
+        .name           = "dpll_core_m6_ck",
+        .parent         = &dpll_core_ck,
+        .clksel         = dpll_core_m6_div,
+        .clksel_reg     = OMAP4430_CM_DIV_M6_DPLL_CORE,
+        .clksel_mask    = OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK,
+        .ops            = &clkops_null,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate,
+        .flags          = CLOCK_IN_OMAP4430,
+};
+
+static const struct clksel dbgclk_mux_sel[] = {
+        { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
+        { .parent = &dpll_core_m6_ck, .rates = div_1_1_rates },
+        { .parent = NULL },
+};
+
+static struct clk dbgclk_mux_ck = {
+        .name           = "dbgclk_mux_ck",
+        .parent         = &sys_clkin_ck,
+        .ops            = &clkops_null,
+        .recalc         = &followparent_recalc,
+        .flags          = CLOCK_IN_OMAP4430,
+};
+
+static struct clk dpll_core_m2_ck = {
+        .name           = "dpll_core_m2_ck",
+        .parent         = &dpll_core_ck,
+        .clksel         = dpll_core_m6_div,
+        .clksel_reg     = OMAP4430_CM_DIV_M2_DPLL_CORE,
+        .clksel_mask    = OMAP4430_DPLL_CLKOUT_DIV_MASK,
+        .ops            = &clkops_null,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate,
+        .flags          = CLOCK_IN_OMAP4430,
+};
+
+static struct clk ddrphy_ck = {
+        .name           = "ddrphy_ck",
+        .parent         = &dpll_core_m2_ck,
+        .ops            = &clkops_null,
+        .recalc         = &followparent_recalc,
+        .flags          = CLOCK_IN_OMAP4430,
+};
+
+static struct clk dpll_core_m5_ck = {
+        .name           = "dpll_core_m5_ck",
+        .parent         = &dpll_core_ck,
+        .clksel         = dpll_core_m6_div,
+        .clksel_reg     = OMAP4430_CM_DIV_M5_DPLL_CORE,
+        .clksel_mask    = OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK,
+        .ops            = &clkops_null,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate,
+        .flags          = CLOCK_IN_OMAP4430,
+};
+
+static const struct clksel div_core_div[] = {
+        { .parent = &dpll_core_m5_ck, .rates = div2_1to2_rates },
+        { .parent = NULL },
+};
+
+static struct clk div_core_ck = {
+        .name           = "div_core_ck",
+        .parent         = &dpll_core_m5_ck,
+        .clksel         = div_core_div,
+        .clksel_reg     = OMAP4430_CM_CLKSEL_CORE,
+        .clksel_mask    = OMAP4430_CLKSEL_CORE_MASK,
+        .ops            = &clkops_null,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate,
+        .flags          = CLOCK_IN_OMAP4430,
+};
+
+static const struct clksel_rate div4_1to8_rates[] = {
+        { .div = 1, .val = 0, .flags = RATE_IN_4430 },
+        { .div = 2, .val = 1, .flags = RATE_IN_4430 },
+        { .div = 4, .val = 2, .flags = RATE_IN_4430 },
+        { .div = 8, .val = 3, .flags = RATE_IN_4430 },
+        { .div = 0 },
+};
+
+static const struct clksel div_iva_hs_clk_div[] = {
+        { .parent = &dpll_core_m5_ck, .rates = div4_1to8_rates },
+        { .parent = NULL },
+};
+
+static struct clk div_iva_hs_clk = {
+        .name           = "div_iva_hs_clk",
+        .parent         = &dpll_core_m5_ck,
+        .clksel         = div_iva_hs_clk_div,
+        .clksel_reg     = OMAP4430_CM_BYPCLK_DPLL_IVA,
+        .clksel_mask    = OMAP4430_CLKSEL_0_1_MASK,
+        .ops            = &clkops_null,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate,
+        .flags          = CLOCK_IN_OMAP4430,
+};
+
+static struct clk div_mpu_hs_clk = {
+        .name           = "div_mpu_hs_clk",
+        .parent         = &dpll_core_m5_ck,
+        .clksel         = div_iva_hs_clk_div,
+        .clksel_reg     = OMAP4430_CM_BYPCLK_DPLL_MPU,
+        .clksel_mask    = OMAP4430_CLKSEL_0_1_MASK,
+        .ops            = &clkops_null,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate,
+        .flags          = CLOCK_IN_OMAP4430,
+};
+
+static struct clk dpll_core_m4_ck = {
+        .name           = "dpll_core_m4_ck",
+        .parent         = &dpll_core_ck,
+        .clksel         = dpll_core_m6_div,
+        .clksel_reg     = OMAP4430_CM_DIV_M4_DPLL_CORE,
+        .clksel_mask    = OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK,
+        .ops            = &clkops_null,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate,
+        .flags          = CLOCK_IN_OMAP4430,
+};
+
+static struct clk dll_clk_div_ck = {
+        .name           = "dll_clk_div_ck",
+        .parent         = &dpll_core_m4_ck,
+        .ops            = &clkops_null,
+        .recalc         = &followparent_recalc,
+        .flags          = CLOCK_IN_OMAP4430,
+};
+
+static struct clk dpll_abe_m2_ck = {
+        .name           = "dpll_abe_m2_ck",
+        .parent         = &dpll_abe_ck,
+        .clksel         = dpll_abe_m3_div,
+        .clksel_reg     = OMAP4430_CM_DIV_M2_DPLL_ABE,
+        .clksel_mask    = OMAP4430_DPLL_CLKOUT_DIV_MASK,
+        .ops            = &clkops_null,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate,
+        .flags          = CLOCK_IN_OMAP4430,
+};
+
+static struct clk dpll_core_m3_ck = {
+        .name           = "dpll_core_m3_ck",
+        .parent         = &dpll_core_ck,
+        .clksel         = dpll_core_m6_div,
+        .clksel_reg     = OMAP4430_CM_DIV_M3_DPLL_CORE,
+        .clksel_mask    = OMAP4430_DPLL_CLKOUTHIF_DIV_MASK,
+        .ops            = &clkops_null,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate,
+        .flags          = CLOCK_IN_OMAP4430,
+};
+
+static struct clk dpll_core_m7_ck = {
+        .name           = "dpll_core_m7_ck",
+        .parent         = &dpll_core_ck,
+        .clksel         = dpll_core_m6_div,
+        .clksel_reg     = OMAP4430_CM_DIV_M7_DPLL_CORE,
+        .clksel_mask    = OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK,
+        .ops            = &clkops_null,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate,
+        .flags          = CLOCK_IN_OMAP4430,
+};
+
+static const struct clksel iva_hsd_byp_clk_mux_sel[] = {
+        { .parent = &dpll_sys_ref_clk, .rates = div_1_0_rates },
+        { .parent = &div_iva_hs_clk, .rates = div_1_1_rates },
+        { .parent = NULL },
+};
+
+static struct clk iva_hsd_byp_clk_mux_ck = {
+        .name           = "iva_hsd_byp_clk_mux_ck",
+        .parent         = &dpll_sys_ref_clk,
+        .ops            = &clkops_null,
+        .recalc         = &followparent_recalc,
+        .flags          = CLOCK_IN_OMAP4430,
+};
+
+/* DPLL_IVA */
+static struct dpll_data dpll_iva_dd = {
+        .mult_div1_reg  = OMAP4430_CM_CLKSEL_DPLL_IVA,
+        .clk_bypass     = &iva_hsd_byp_clk_mux_ck,
+        .clk_ref        = &dpll_sys_ref_clk,
+        .control_reg    = OMAP4430_CM_CLKMODE_DPLL_IVA,
+        .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
+        .autoidle_reg   = OMAP4430_CM_AUTOIDLE_DPLL_IVA,
+        .idlest_reg     = OMAP4430_CM_IDLEST_DPLL_IVA,
+        .mult_mask      = OMAP4430_DPLL_MULT_MASK,
+        .div1_mask      = OMAP4430_DPLL_DIV_MASK,
+        .enable_mask    = OMAP4430_DPLL_EN_MASK,
+        .autoidle_mask  = OMAP4430_AUTO_DPLL_MODE_MASK,
+        .idlest_mask    = OMAP4430_ST_DPLL_CLK_MASK,
+        .max_multiplier = OMAP4430_MAX_DPLL_MULT,
+        .max_divider    = OMAP4430_MAX_DPLL_DIV,
+        .min_divider    = 1,
+};
+
+
+static struct clk dpll_iva_ck = {
+        .name           = "dpll_iva_ck",
+        .parent         = &dpll_sys_ref_clk,
+        .dpll_data      = &dpll_iva_dd,
+        .init           = &omap2_init_dpll_parent,
+        .ops            = &clkops_noncore_dpll_ops,
+        .recalc         = &omap3_dpll_recalc,
+        .round_rate     = &omap2_dpll_round_rate,
+        .set_rate       = &omap3_noncore_dpll_set_rate,
+        .flags          = CLOCK_IN_OMAP4430,
+};
+
+static const struct clksel dpll_iva_m4_div[] = {
+        { .parent = &dpll_iva_ck, .rates = div31_1to31_rates },
+        { .parent = NULL },
+};
+
+static struct clk dpll_iva_m4_ck = {
+        .name           = "dpll_iva_m4_ck",
+        .parent         = &dpll_iva_ck,
+        .clksel         = dpll_iva_m4_div,
+        .clksel_reg     = OMAP4430_CM_DIV_M4_DPLL_IVA,
+        .clksel_mask    = OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK,
+        .ops            = &clkops_null,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate,
+        .flags          = CLOCK_IN_OMAP4430,
+};
+
+static struct clk dpll_iva_m5_ck = {
+        .name           = "dpll_iva_m5_ck",
+        .parent         = &dpll_iva_ck,
+        .clksel         = dpll_iva_m4_div,
+        .clksel_reg     = OMAP4430_CM_DIV_M5_DPLL_IVA,
+        .clksel_mask    = OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK,
+        .ops            = &clkops_null,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate,
+        .flags          = CLOCK_IN_OMAP4430,
+};
+
+/* DPLL_MPU */
+static struct dpll_data dpll_mpu_dd = {
+        .mult_div1_reg  = OMAP4430_CM_CLKSEL_DPLL_MPU,
+        .clk_bypass     = &div_mpu_hs_clk,
+        .clk_ref        = &dpll_sys_ref_clk,
+        .control_reg    = OMAP4430_CM_CLKMODE_DPLL_MPU,
+        .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
+        .autoidle_reg   = OMAP4430_CM_AUTOIDLE_DPLL_MPU,
+        .idlest_reg     = OMAP4430_CM_IDLEST_DPLL_MPU,
+        .mult_mask      = OMAP4430_DPLL_MULT_MASK,
+        .div1_mask      = OMAP4430_DPLL_DIV_MASK,
+        .enable_mask    = OMAP4430_DPLL_EN_MASK,
+        .autoidle_mask  = OMAP4430_AUTO_DPLL_MODE_MASK,
+        .idlest_mask    = OMAP4430_ST_DPLL_CLK_MASK,
+        .max_multiplier = OMAP4430_MAX_DPLL_MULT,
+        .max_divider    = OMAP4430_MAX_DPLL_DIV,
+        .min_divider    = 1,
+};
+
+
+static struct clk dpll_mpu_ck = {
+        .name           = "dpll_mpu_ck",
+        .parent         = &dpll_sys_ref_clk,
+        .dpll_data      = &dpll_mpu_dd,
+        .init           = &omap2_init_dpll_parent,
+        .ops            = &clkops_noncore_dpll_ops,
+        .recalc         = &omap3_dpll_recalc,
+        .round_rate     = &omap2_dpll_round_rate,
+        .set_rate       = &omap3_noncore_dpll_set_rate,
+        .flags          = CLOCK_IN_OMAP4430,
+};
+
+static const struct clksel dpll_mpu_m2_div[] = {
+        { .parent = &dpll_mpu_ck, .rates = div31_1to31_rates },
+        { .parent = NULL },
+};
+
+static struct clk dpll_mpu_m2_ck = {
+        .name           = "dpll_mpu_m2_ck",
+        .parent         = &dpll_mpu_ck,
+        .clksel         = dpll_mpu_m2_div,
+        .clksel_reg     = OMAP4430_CM_DIV_M2_DPLL_MPU,
+        .clksel_mask    = OMAP4430_DPLL_CLKOUT_DIV_MASK,
+        .ops            = &clkops_null,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate,
+        .flags          = CLOCK_IN_OMAP4430,
+};
+
+static struct clk per_hs_clk_div_ck = {
+        .name           = "per_hs_clk_div_ck",
+        .parent         = &dpll_abe_m3_ck,
+        .ops            = &clkops_null,
+        .recalc         = &followparent_recalc,
+        .flags          = CLOCK_IN_OMAP4430,
+};
+
+static const struct clksel per_hsd_byp_clk_mux_sel[] = {
+        { .parent = &dpll_sys_ref_clk, .rates = div_1_0_rates },
+        { .parent = &per_hs_clk_div_ck, .rates = div_1_1_rates },
+        { .parent = NULL },
+};
+
+static struct clk per_hsd_byp_clk_mux_ck = {
+        .name           = "per_hsd_byp_clk_mux_ck",
+        .parent         = &dpll_sys_ref_clk,
+        .clksel         = per_hsd_byp_clk_mux_sel,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP4430_CM_CLKSEL_DPLL_PER,
+        .clksel_mask    = OMAP4430_DPLL_BYP_CLKSEL_MASK,
+        .ops            = &clkops_null,
+        .recalc         = &omap2_clksel_recalc,
+        .flags          = CLOCK_IN_OMAP4430,
+};
+
+/* DPLL_PER */
+static struct dpll_data dpll_per_dd = {
+        .mult_div1_reg  = OMAP4430_CM_CLKSEL_DPLL_PER,
+        .clk_bypass     = &per_hsd_byp_clk_mux_ck,
+        .clk_ref        = &dpll_sys_ref_clk,
+        .control_reg    = OMAP4430_CM_CLKMODE_DPLL_PER,
+        .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
+        .autoidle_reg   = OMAP4430_CM_AUTOIDLE_DPLL_PER,
+        .idlest_reg     = OMAP4430_CM_IDLEST_DPLL_PER,
+        .mult_mask      = OMAP4430_DPLL_MULT_MASK,
+        .div1_mask      = OMAP4430_DPLL_DIV_MASK,
+        .enable_mask    = OMAP4430_DPLL_EN_MASK,
+        .autoidle_mask  = OMAP4430_AUTO_DPLL_MODE_MASK,
+        .idlest_mask    = OMAP4430_ST_DPLL_CLK_MASK,
+        .max_multiplier = OMAP4430_MAX_DPLL_MULT,
+        .max_divider    = OMAP4430_MAX_DPLL_DIV,
+        .min_divider    = 1,
+};
+
+
+static struct clk dpll_per_ck = {
+        .name           = "dpll_per_ck",
+        .parent         = &dpll_sys_ref_clk,
+        .dpll_data      = &dpll_per_dd,
+        .init           = &omap2_init_dpll_parent,
+        .ops            = &clkops_noncore_dpll_ops,
+        .recalc         = &omap3_dpll_recalc,
+        .round_rate     = &omap2_dpll_round_rate,
+        .set_rate       = &omap3_noncore_dpll_set_rate,
+        .flags          = CLOCK_IN_OMAP4430,
+};
+
+static const struct clksel dpll_per_m2_div[] = {
+        { .parent = &dpll_per_ck, .rates = div31_1to31_rates },
+        { .parent = NULL },
+};
+
+static struct clk dpll_per_m2_ck = {
+        .name           = "dpll_per_m2_ck",
+        .parent         = &dpll_per_ck,
+        .clksel         = dpll_per_m2_div,
+        .clksel_reg     = OMAP4430_CM_DIV_M2_DPLL_PER,
+        .clksel_mask    = OMAP4430_DPLL_CLKOUT_DIV_MASK,
+        .ops            = &clkops_null,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate,
+        .flags          = CLOCK_IN_OMAP4430,
+};
+
+static struct clk dpll_per_m2x2_ck = {
+        .name           = "dpll_per_m2x2_ck",
+        .parent         = &dpll_per_ck,
+        .ops            = &clkops_null,
+        .recalc         = &followparent_recalc,
+        .flags          = CLOCK_IN_OMAP4430,
+};
+
+static struct clk dpll_per_m3_ck = {
+        .name           = "dpll_per_m3_ck",
+        .parent         = &dpll_per_ck,
+        .clksel         = dpll_per_m2_div,
+        .clksel_reg     = OMAP4430_CM_DIV_M3_DPLL_PER,
+        .clksel_mask    = OMAP4430_DPLL_CLKOUTHIF_DIV_MASK,
+        .ops            = &clkops_null,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate,
+        .flags          = CLOCK_IN_OMAP4430,
+};
+
+static struct clk dpll_per_m4_ck = {
+        .name           = "dpll_per_m4_ck",
+        .parent         = &dpll_per_ck,
+        .clksel         = dpll_per_m2_div,
+        .clksel_reg     = OMAP4430_CM_DIV_M4_DPLL_PER,
+        .clksel_mask    = OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK,
+        .ops            = &clkops_null,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate,
+        .flags          = CLOCK_IN_OMAP4430,
+};
+
+static struct clk dpll_per_m5_ck = {
+        .name           = "dpll_per_m5_ck",
+        .parent         = &dpll_per_ck,
+        .clksel         = dpll_per_m2_div,
+        .clksel_reg     = OMAP4430_CM_DIV_M5_DPLL_PER,
+        .clksel_mask    = OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK,
+        .ops            = &clkops_null,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate,
+        .flags          = CLOCK_IN_OMAP4430,
+};
+
+static struct clk dpll_per_m6_ck = {
+        .name           = "dpll_per_m6_ck",
+        .parent         = &dpll_per_ck,
+        .clksel         = dpll_per_m2_div,
+        .clksel_reg     = OMAP4430_CM_DIV_M6_DPLL_PER,
+        .clksel_mask    = OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK,
+        .ops            = &clkops_null,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate,
+        .flags          = CLOCK_IN_OMAP4430,
+};
+
+static struct clk dpll_per_m7_ck = {
+        .name           = "dpll_per_m7_ck",
+        .parent         = &dpll_per_ck,
+        .clksel         = dpll_per_m2_div,
+        .clksel_reg     = OMAP4430_CM_DIV_M7_DPLL_PER,
+        .clksel_mask    = OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK,
+        .ops            = &clkops_null,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate,
+        .flags          = CLOCK_IN_OMAP4430,
+};
+
+/* DPLL_UNIPRO */
+static struct dpll_data dpll_unipro_dd = {
+        .mult_div1_reg  = OMAP4430_CM_CLKSEL_DPLL_UNIPRO,
+        .clk_bypass     = &dpll_sys_ref_clk,
+        .clk_ref        = &dpll_sys_ref_clk,
+        .control_reg    = OMAP4430_CM_CLKMODE_DPLL_UNIPRO,
+        .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
+        .autoidle_reg   = OMAP4430_CM_AUTOIDLE_DPLL_UNIPRO,
+        .idlest_reg     = OMAP4430_CM_IDLEST_DPLL_UNIPRO,
+        .mult_mask      = OMAP4430_DPLL_MULT_MASK,
+        .div1_mask      = OMAP4430_DPLL_DIV_MASK,
+        .enable_mask    = OMAP4430_DPLL_EN_MASK,
+        .autoidle_mask  = OMAP4430_AUTO_DPLL_MODE_MASK,
+        .idlest_mask    = OMAP4430_ST_DPLL_CLK_MASK,
+        .max_multiplier = OMAP4430_MAX_DPLL_MULT,
+        .max_divider    = OMAP4430_MAX_DPLL_DIV,
+        .min_divider    = 1,
+};
+
+
+static struct clk dpll_unipro_ck = {
+        .name           = "dpll_unipro_ck",
+        .parent         = &dpll_sys_ref_clk,
+        .dpll_data      = &dpll_unipro_dd,
+        .init           = &omap2_init_dpll_parent,
+        .ops            = &clkops_noncore_dpll_ops,
+        .recalc         = &omap3_dpll_recalc,
+        .round_rate     = &omap2_dpll_round_rate,
+        .set_rate       = &omap3_noncore_dpll_set_rate,
+        .flags          = CLOCK_IN_OMAP4430,
+};
+
+static const struct clksel dpll_unipro_m2x2_div[] = {
+        { .parent = &dpll_unipro_ck, .rates = div31_1to31_rates },
+        { .parent = NULL },
+};
+
+static struct clk dpll_unipro_m2x2_ck = {
+        .name           = "dpll_unipro_m2x2_ck",
+        .parent         = &dpll_unipro_ck,
+        .clksel         = dpll_unipro_m2x2_div,
+        .clksel_reg     = OMAP4430_CM_DIV_M2_DPLL_UNIPRO,
+        .clksel_mask    = OMAP4430_DPLL_CLKOUT_DIV_MASK,
+        .ops            = &clkops_null,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate,
+        .flags          = CLOCK_IN_OMAP4430,
+};
+
+static struct clk usb_hs_clk_div_ck = {
+        .name           = "usb_hs_clk_div_ck",
+        .parent         = &dpll_abe_m3_ck,
+        .ops            = &clkops_null,
+        .recalc         = &followparent_recalc,
+        .flags          = CLOCK_IN_OMAP4430,
+};
+
+/* DPLL_USB */
+static struct dpll_data dpll_usb_dd = {
+        .mult_div1_reg  = OMAP4430_CM_CLKSEL_DPLL_USB,
+        .clk_bypass     = &usb_hs_clk_div_ck,
+        .clk_ref        = &dpll_sys_ref_clk,
+        .control_reg    = OMAP4430_CM_CLKMODE_DPLL_USB,
+        .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
+        .autoidle_reg   = OMAP4430_CM_AUTOIDLE_DPLL_USB,
+        .idlest_reg     = OMAP4430_CM_IDLEST_DPLL_USB,
+        .mult_mask      = OMAP4430_DPLL_MULT_MASK,
+        .div1_mask      = OMAP4430_DPLL_DIV_MASK,
+        .enable_mask    = OMAP4430_DPLL_EN_MASK,
+        .autoidle_mask  = OMAP4430_AUTO_DPLL_MODE_MASK,
+        .idlest_mask    = OMAP4430_ST_DPLL_CLK_MASK,
+        .max_multiplier = OMAP4430_MAX_DPLL_MULT,
+        .max_divider    = OMAP4430_MAX_DPLL_DIV,
+        .min_divider    = 1,
+};
+
+
+static struct clk dpll_usb_ck = {
+        .name           = "dpll_usb_ck",
+        .parent         = &dpll_sys_ref_clk,
+        .dpll_data      = &dpll_usb_dd,
+        .init           = &omap2_init_dpll_parent,
+        .ops            = &clkops_noncore_dpll_ops,
+        .recalc         = &omap3_dpll_recalc,
+        .round_rate     = &omap2_dpll_round_rate,
+        .set_rate       = &omap3_noncore_dpll_set_rate,
+        .flags          = CLOCK_IN_OMAP4430,
+};
+
+static struct clk dpll_usb_clkdcoldo_ck = {
+        .name           = "dpll_usb_clkdcoldo_ck",
+        .parent         = &dpll_usb_ck,
+        .ops            = &clkops_null,
+        .recalc         = &followparent_recalc,
+        .flags          = CLOCK_IN_OMAP4430,
+};
+
+static const struct clksel dpll_usb_m2_div[] = {
+        { .parent = &dpll_usb_ck, .rates = div31_1to31_rates },
+        { .parent = NULL },
+};
+
+static struct clk dpll_usb_m2_ck = {
+        .name           = "dpll_usb_m2_ck",
+        .parent         = &dpll_usb_ck,
+        .clksel         = dpll_usb_m2_div,
+        .clksel_reg     = OMAP4430_CM_DIV_M2_DPLL_USB,
+        .clksel_mask    = OMAP4430_DPLL_CLKOUT_DIV_0_6_MASK,
+        .ops            = &clkops_null,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate,
+        .flags          = CLOCK_IN_OMAP4430,
+};
+
+static const struct clksel ducati_clk_mux_sel[] = {
+        { .parent = &div_core_ck, .rates = div_1_0_rates },
+        { .parent = &dpll_per_m6_ck, .rates = div_1_1_rates },
+        { .parent = NULL },
+};
+
+static struct clk ducati_clk_mux_ck = {
+        .name           = "ducati_clk_mux_ck",
+        .parent         = &div_core_ck,
+        .clksel         = ducati_clk_mux_sel,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP4430_CM_CLKSEL_DUCATI_ISS_ROOT,
+        .clksel_mask    = OMAP4430_CLKSEL_0_0_MASK,
+        .ops            = &clkops_null,
+        .recalc         = &omap2_clksel_recalc,
+        .flags          = CLOCK_IN_OMAP4430,
+};
+
+static struct clk func_12m_fclk = {
+        .name           = "func_12m_fclk",
+        .parent         = &dpll_per_m2x2_ck,
+        .ops            = &clkops_null,
+        .recalc         = &followparent_recalc,
+        .flags          = CLOCK_IN_OMAP4430,
+};
+
+static struct clk func_24m_clk = {
+        .name           = "func_24m_clk",
+        .parent         = &dpll_per_m2_ck,
+        .ops            = &clkops_null,
+        .recalc         = &followparent_recalc,
+        .flags          = CLOCK_IN_OMAP4430,
+};
+
+static struct clk func_24mc_fclk = {
+        .name           = "func_24mc_fclk",
+        .parent         = &dpll_per_m2x2_ck,
+        .ops            = &clkops_null,
+        .recalc         = &followparent_recalc,
+        .flags          = CLOCK_IN_OMAP4430,
+};
+
+static const struct clksel_rate div2_4to8_rates[] = {
+        { .div = 4, .val = 0, .flags = RATE_IN_4430 },
+        { .div = 8, .val = 1, .flags = RATE_IN_4430 },
+        { .div = 0 },
+};
+
+static const struct clksel func_48m_fclk_div[] = {
+        { .parent = &dpll_per_m2x2_ck, .rates = div2_4to8_rates },
+        { .parent = NULL },
+};
+
+static struct clk func_48m_fclk = {
+        .name           = "func_48m_fclk",
+        .parent         = &dpll_per_m2x2_ck,
+        .clksel         = func_48m_fclk_div,
+        .clksel_reg     = OMAP4430_CM_SCALE_FCLK,
+        .clksel_mask    = OMAP4430_SCALE_FCLK_MASK,
+        .ops            = &clkops_null,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate,
+        .flags          = CLOCK_IN_OMAP4430,
+};
+
+static struct clk func_48mc_fclk = {
+        .name           = "func_48mc_fclk",
+        .parent         = &dpll_per_m2x2_ck,
+        .ops            = &clkops_null,
+        .recalc         = &followparent_recalc,
+        .flags          = CLOCK_IN_OMAP4430,
+};
+
+static const struct clksel_rate div2_2to4_rates[] = {
+        { .div = 2, .val = 0, .flags = RATE_IN_4430 },
+        { .div = 4, .val = 1, .flags = RATE_IN_4430 },
+        { .div = 0 },
+};
+
+static const struct clksel func_64m_fclk_div[] = {
+        { .parent = &dpll_per_m4_ck, .rates = div2_2to4_rates },
+        { .parent = NULL },
+};
+
+static struct clk func_64m_fclk = {
+        .name           = "func_64m_fclk",
+        .parent         = &dpll_per_m4_ck,
+        .clksel         = func_64m_fclk_div,
+        .clksel_reg     = OMAP4430_CM_SCALE_FCLK,
+        .clksel_mask    = OMAP4430_SCALE_FCLK_MASK,
+        .ops            = &clkops_null,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate,
+        .flags          = CLOCK_IN_OMAP4430,
+};
+
+static const struct clksel func_96m_fclk_div[] = {
+        { .parent = &dpll_per_m2x2_ck, .rates = div2_2to4_rates },
+        { .parent = NULL },
+};
+
+static struct clk func_96m_fclk = {
+        .name           = "func_96m_fclk",
+        .parent         = &dpll_per_m2x2_ck,
+        .clksel         = func_96m_fclk_div,
+        .clksel_reg     = OMAP4430_CM_SCALE_FCLK,
+        .clksel_mask    = OMAP4430_SCALE_FCLK_MASK,
+        .ops            = &clkops_null,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate,
+        .flags          = CLOCK_IN_OMAP4430,
+};
+
+static const struct clksel hsmmc6_fclk_sel[] = {
+        { .parent = &func_64m_fclk, .rates = div_1_0_rates },
+        { .parent = &func_96m_fclk, .rates = div_1_1_rates },
+        { .parent = NULL },
+};
+
+static struct clk hsmmc6_fclk = {
+        .name           = "hsmmc6_fclk",
+        .parent         = &func_64m_fclk,
+        .ops            = &clkops_null,
+        .recalc         = &followparent_recalc,
+        .flags          = CLOCK_IN_OMAP4430,
+};
+
+static const struct clksel_rate div2_1to8_rates[] = {
+        { .div = 1, .val = 0, .flags = RATE_IN_4430 },
+        { .div = 8, .val = 1, .flags = RATE_IN_4430 },
+        { .div = 0 },
+};
+
+static const struct clksel init_60m_fclk_div[] = {
+        { .parent = &dpll_usb_m2_ck, .rates = div2_1to8_rates },
+        { .parent = NULL },
+};
+
+static struct clk init_60m_fclk = {
+        .name           = "init_60m_fclk",
+        .parent         = &dpll_usb_m2_ck,
+        .clksel         = init_60m_fclk_div,
+        .clksel_reg     = OMAP4430_CM_CLKSEL_USB_60MHZ,
+        .clksel_mask    = OMAP4430_CLKSEL_0_0_MASK,
+        .ops            = &clkops_null,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate,
+        .flags          = CLOCK_IN_OMAP4430,
+};
+
+static const struct clksel l3_div_div[] = {
+        { .parent = &div_core_ck, .rates = div2_1to2_rates },
+        { .parent = NULL },
+};
+
+static struct clk l3_div_ck = {
+        .name           = "l3_div_ck",
+        .parent         = &div_core_ck,
+        .clksel         = l3_div_div,
+        .clksel_reg     = OMAP4430_CM_CLKSEL_CORE,
+        .clksel_mask    = OMAP4430_CLKSEL_L3_MASK,
+        .ops            = &clkops_null,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate,
+        .flags          = CLOCK_IN_OMAP4430,
+};
+
+static const struct clksel l4_div_div[] = {
+        { .parent = &l3_div_ck, .rates = div2_1to2_rates },
+        { .parent = NULL },
+};
+
+static struct clk l4_div_ck = {
+        .name           = "l4_div_ck",
+        .parent         = &l3_div_ck,
+        .clksel         = l4_div_div,
+        .clksel_reg     = OMAP4430_CM_CLKSEL_CORE,
+        .clksel_mask    = OMAP4430_CLKSEL_L4_MASK,
+        .ops            = &clkops_null,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate,
+        .flags          = CLOCK_IN_OMAP4430,
+};
+
+static struct clk lp_clk_div_ck = {
+        .name           = "lp_clk_div_ck",
+        .parent         = &dpll_abe_m2x2_ck,
+        .ops            = &clkops_null,
+        .recalc         = &followparent_recalc,
+        .flags          = CLOCK_IN_OMAP4430,
+};
+
+static const struct clksel l4_wkup_clk_mux_sel[] = {
+        { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
+        { .parent = &lp_clk_div_ck, .rates = div_1_1_rates },
+        { .parent = NULL },
+};
+
+static struct clk l4_wkup_clk_mux_ck = {
+        .name           = "l4_wkup_clk_mux_ck",
+        .parent         = &sys_clkin_ck,
+        .clksel         = l4_wkup_clk_mux_sel,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP4430_CM_L4_WKUP_CLKSEL,
+        .clksel_mask    = OMAP4430_CLKSEL_0_0_MASK,
+        .ops            = &clkops_null,
+        .recalc         = &omap2_clksel_recalc,
+        .flags          = CLOCK_IN_OMAP4430,
+};
+
+static const struct clksel per_abe_nc_fclk_div[] = {
+        { .parent = &dpll_abe_m2_ck, .rates = div2_1to2_rates },
+        { .parent = NULL },
+};
+
+static struct clk per_abe_nc_fclk = {
+        .name           = "per_abe_nc_fclk",
+        .parent         = &dpll_abe_m2_ck,
+        .clksel         = per_abe_nc_fclk_div,
+        .clksel_reg     = OMAP4430_CM_SCALE_FCLK,
+        .clksel_mask    = OMAP4430_SCALE_FCLK_MASK,
+        .ops            = &clkops_null,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate,
+        .flags          = CLOCK_IN_OMAP4430,
+};
+
+static const struct clksel mcasp2_fclk_sel[] = {
+        { .parent = &func_96m_fclk, .rates = div_1_0_rates },
+        { .parent = &per_abe_nc_fclk, .rates = div_1_1_rates },
+        { .parent = NULL },
+};
+
+static struct clk mcasp2_fclk = {
+        .name           = "mcasp2_fclk",
+        .parent         = &func_96m_fclk,
+        .ops            = &clkops_null,
+        .recalc         = &followparent_recalc,
+        .flags          = CLOCK_IN_OMAP4430,
+};
+
+static struct clk mcasp3_fclk = {
+        .name           = "mcasp3_fclk",
+        .parent         = &func_96m_fclk,
+        .ops            = &clkops_null,
+        .recalc         = &followparent_recalc,
+        .flags          = CLOCK_IN_OMAP4430,
+};
+
+static struct clk ocp_abe_iclk = {
+        .name           = "ocp_abe_iclk",
+        .parent         = &aess_fclk,
+        .ops            = &clkops_null,
+        .recalc         = &followparent_recalc,
+        .flags          = CLOCK_IN_OMAP4430,
+};
+
+static struct clk per_abe_24m_fclk = {
+        .name           = "per_abe_24m_fclk",
+        .parent         = &dpll_abe_m2_ck,
+        .ops            = &clkops_null,
+        .recalc         = &followparent_recalc,
+        .flags          = CLOCK_IN_OMAP4430,
+};
+
+static const struct clksel pmd_stm_clock_mux_sel[] = {
+        { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
+        { .parent = &dpll_core_m6_ck, .rates = div_1_1_rates },
+        { .parent = &dpll_per_m7_ck, .rates = div_1_2_rates },
+        { .parent = NULL },
+};
+
+static struct clk pmd_stm_clock_mux_ck = {
+        .name           = "pmd_stm_clock_mux_ck",
+        .parent         = &sys_clkin_ck,
+        .ops            = &clkops_null,
+        .recalc         = &followparent_recalc,
+        .flags          = CLOCK_IN_OMAP4430,
+};
+
+static struct clk pmd_trace_clk_mux_ck = {
+        .name           = "pmd_trace_clk_mux_ck",
+        .parent         = &sys_clkin_ck,
+        .ops            = &clkops_null,
+        .recalc         = &followparent_recalc,
+        .flags          = CLOCK_IN_OMAP4430,
+};
+
+static struct clk syc_clk_div_ck = {
+        .name           = "syc_clk_div_ck",
+        .parent         = &sys_clkin_ck,
+        .clksel         = dpll_sys_ref_clk_div,
+        .clksel_reg     = OMAP4430_CM_ABE_DSS_SYS_CLKSEL,
+        .clksel_mask    = OMAP4430_CLKSEL_0_0_MASK,
+        .ops            = &clkops_null,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate,
+        .flags          = CLOCK_IN_OMAP4430,
+};
+
+/* Leaf clocks controlled by modules */
+
+static struct clk aes1_ck = {
+        .name           = "aes1_ck",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_L4SEC_AES1_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "l4_secure_clkdm",
+        .parent         = &l3_div_ck,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk aes2_ck = {
+        .name           = "aes2_ck",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_L4SEC_AES2_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "l4_secure_clkdm",
+        .parent         = &l3_div_ck,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk aess_ck = {
+        .name           = "aess_ck",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM1_ABE_AESS_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "abe_clkdm",
+        .parent         = &aess_fclk,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk cust_efuse_ck = {
+        .name           = "cust_efuse_ck",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_CEFUSE_CEFUSE_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "l4_cefuse_clkdm",
+        .parent         = &sys_clkin_ck,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk des3des_ck = {
+        .name           = "des3des_ck",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_L4SEC_DES3DES_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "l4_secure_clkdm",
+        .parent         = &l4_div_ck,
+        .recalc         = &followparent_recalc,
+};
+
+static const struct clksel dmic_sync_mux_sel[] = {
+        { .parent = &abe_24m_fclk, .rates = div_1_0_rates },
+        { .parent = &syc_clk_div_ck, .rates = div_1_1_rates },
+        { .parent = &func_24m_clk, .rates = div_1_2_rates },
+        { .parent = NULL },
+};
+
+static struct clk dmic_sync_mux_ck = {
+        .name           = "dmic_sync_mux_ck",
+        .parent         = &abe_24m_fclk,
+        .clksel         = dmic_sync_mux_sel,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP4430_CM1_ABE_DMIC_CLKCTRL,
+        .clksel_mask    = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK,
+        .ops            = &clkops_null,
+        .recalc         = &omap2_clksel_recalc,
+        .flags          = CLOCK_IN_OMAP4430,
+};
+
+static const struct clksel func_dmic_abe_gfclk_sel[] = {
+        { .parent = &dmic_sync_mux_ck, .rates = div_1_0_rates },
+        { .parent = &pad_clks_ck, .rates = div_1_1_rates },
+        { .parent = &slimbus_clk, .rates = div_1_2_rates },
+        { .parent = NULL },
+};
+
+/* Merged func_dmic_abe_gfclk into dmic_ck */
+static struct clk dmic_ck = {
+        .name           = "dmic_ck",
+        .parent         = &dmic_sync_mux_ck,
+        .clksel         = func_dmic_abe_gfclk_sel,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP4430_CM1_ABE_DMIC_CLKCTRL,
+        .clksel_mask    = OMAP4430_CLKSEL_SOURCE_MASK,
+        .ops            = &clkops_omap2_dflt,
+        .recalc         = &omap2_clksel_recalc,
+        .flags          = CLOCK_IN_OMAP4430,
+        .enable_reg     = OMAP4430_CM1_ABE_DMIC_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "abe_clkdm",
+};
+
+static struct clk dss_ck = {
+        .name           = "dss_ck",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_DSS_DSS_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "l3_dss_clkdm",
+        .parent         = &l3_div_ck,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk ducati_ck = {
+        .name           = "ducati_ck",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_DUCATI_DUCATI_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
+        .clkdm_name     = "ducati_clkdm",
+        .parent         = &ducati_clk_mux_ck,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk emif1_ck = {
+        .name           = "emif1_ck",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_MEMIF_EMIF_1_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
+        .clkdm_name     = "l3_emif_clkdm",
+        .parent         = &ddrphy_ck,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk emif2_ck = {
+        .name           = "emif2_ck",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_MEMIF_EMIF_2_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
+        .clkdm_name     = "l3_emif_clkdm",
+        .parent         = &ddrphy_ck,
+        .recalc         = &followparent_recalc,
+};
+
+static const struct clksel fdif_fclk_div[] = {
+        { .parent = &dpll_per_m4_ck, .rates = div3_1to4_rates },
+        { .parent = NULL },
+};
+
+/* Merged fdif_fclk into fdif_ck */
+static struct clk fdif_ck = {
+        .name           = "fdif_ck",
+        .parent         = &dpll_per_m4_ck,
+        .clksel         = fdif_fclk_div,
+        .clksel_reg     = OMAP4430_CM_CAM_FDIF_CLKCTRL,
+        .clksel_mask    = OMAP4430_CLKSEL_FCLK_MASK,
+        .ops            = &clkops_omap2_dflt,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate,
+        .flags          = CLOCK_IN_OMAP4430,
+        .enable_reg     = OMAP4430_CM_CAM_FDIF_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "iss_clkdm",
+};
+
+static const struct clksel per_sgx_fclk_div[] = {
+        { .parent = &dpll_per_m2x2_ck, .rates = div3_1to4_rates },
+        { .parent = NULL },
+};
+
+static struct clk per_sgx_fclk = {
+        .name           = "per_sgx_fclk",
+        .parent         = &dpll_per_m2x2_ck,
+        .clksel         = per_sgx_fclk_div,
+        .clksel_reg     = OMAP4430_CM_GFX_GFX_CLKCTRL,
+        .clksel_mask    = OMAP4430_CLKSEL_PER_192M_MASK,
+        .ops            = &clkops_null,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate,
+        .flags          = CLOCK_IN_OMAP4430,
+};
+
+static const struct clksel sgx_clk_mux_sel[] = {
+        { .parent = &dpll_core_m7_ck, .rates = div_1_0_rates },
+        { .parent = &per_sgx_fclk, .rates = div_1_1_rates },
+        { .parent = NULL },
+};
+
+/* Merged sgx_clk_mux into gfx_ck */
+static struct clk gfx_ck = {
+        .name           = "gfx_ck",
+        .parent         = &dpll_core_m7_ck,
+        .clksel         = sgx_clk_mux_sel,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP4430_CM_GFX_GFX_CLKCTRL,
+        .clksel_mask    = OMAP4430_CLKSEL_SGX_FCLK_MASK,
+        .ops            = &clkops_omap2_dflt,
+        .recalc         = &omap2_clksel_recalc,
+        .flags          = CLOCK_IN_OMAP4430,
+        .enable_reg     = OMAP4430_CM_GFX_GFX_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "l3_gfx_clkdm",
+};
+
+static struct clk gpio1_ck = {
+        .name           = "gpio1_ck",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_WKUP_GPIO1_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
+        .clkdm_name     = "l4_wkup_clkdm",
+        .parent         = &l4_wkup_clk_mux_ck,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk gpio2_ck = {
+        .name           = "gpio2_ck",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_L4PER_GPIO2_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
+        .clkdm_name     = "l4_per_clkdm",
+        .parent         = &l4_div_ck,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk gpio3_ck = {
+        .name           = "gpio3_ck",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_L4PER_GPIO3_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
+        .clkdm_name     = "l4_per_clkdm",
+        .parent         = &l4_div_ck,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk gpio4_ck = {
+        .name           = "gpio4_ck",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_L4PER_GPIO4_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
+        .clkdm_name     = "l4_per_clkdm",
+        .parent         = &l4_div_ck,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk gpio5_ck = {
+        .name           = "gpio5_ck",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_L4PER_GPIO5_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
+        .clkdm_name     = "l4_per_clkdm",
+        .parent         = &l4_div_ck,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk gpio6_ck = {
+        .name           = "gpio6_ck",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_L4PER_GPIO6_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
+        .clkdm_name     = "l4_per_clkdm",
+        .parent         = &l4_div_ck,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk gpmc_ck = {
+        .name           = "gpmc_ck",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_L3_2_GPMC_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
+        .clkdm_name     = "l3_2_clkdm",
+        .parent         = &l3_div_ck,
+        .recalc         = &followparent_recalc,
+};
+
+static const struct clksel dmt1_clk_mux_sel[] = {
+        { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
+        { .parent = &sys_32k_ck, .rates = div_1_1_rates },
+        { .parent = NULL },
+};
+
+/* Merged dmt1_clk_mux into gptimer1_ck */
+static struct clk gptimer1_ck = {
+        .name           = "gptimer1_ck",
+        .parent         = &sys_clkin_ck,
+        .clksel         = dmt1_clk_mux_sel,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP4430_CM_WKUP_TIMER1_CLKCTRL,
+        .clksel_mask    = OMAP4430_CLKSEL_MASK,
+        .ops            = &clkops_omap2_dflt,
+        .recalc         = &omap2_clksel_recalc,
+        .flags          = CLOCK_IN_OMAP4430,
+        .enable_reg     = OMAP4430_CM_WKUP_TIMER1_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "l4_wkup_clkdm",
+};
+
+/* Merged cm2_dm10_mux into gptimer10_ck */
+static struct clk gptimer10_ck = {
+        .name           = "gptimer10_ck",
+        .parent         = &sys_clkin_ck,
+        .clksel         = dmt1_clk_mux_sel,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL,
+        .clksel_mask    = OMAP4430_CLKSEL_MASK,
+        .ops            = &clkops_omap2_dflt,
+        .recalc         = &omap2_clksel_recalc,
+        .flags          = CLOCK_IN_OMAP4430,
+        .enable_reg     = OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "l4_per_clkdm",
+};
+
+/* Merged cm2_dm11_mux into gptimer11_ck */
+static struct clk gptimer11_ck = {
+        .name           = "gptimer11_ck",
+        .parent         = &sys_clkin_ck,
+        .clksel         = dmt1_clk_mux_sel,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL,
+        .clksel_mask    = OMAP4430_CLKSEL_MASK,
+        .ops            = &clkops_omap2_dflt,
+        .recalc         = &omap2_clksel_recalc,
+        .flags          = CLOCK_IN_OMAP4430,
+        .enable_reg     = OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "l4_per_clkdm",
+};
+
+/* Merged cm2_dm2_mux into gptimer2_ck */
+static struct clk gptimer2_ck = {
+        .name           = "gptimer2_ck",
+        .parent         = &sys_clkin_ck,
+        .clksel         = dmt1_clk_mux_sel,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL,
+        .clksel_mask    = OMAP4430_CLKSEL_MASK,
+        .ops            = &clkops_omap2_dflt,
+        .recalc         = &omap2_clksel_recalc,
+        .flags          = CLOCK_IN_OMAP4430,
+        .enable_reg     = OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "l4_per_clkdm",
+};
+
+/* Merged cm2_dm3_mux into gptimer3_ck */
+static struct clk gptimer3_ck = {
+        .name           = "gptimer3_ck",
+        .parent         = &sys_clkin_ck,
+        .clksel         = dmt1_clk_mux_sel,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL,
+        .clksel_mask    = OMAP4430_CLKSEL_MASK,
+        .ops            = &clkops_omap2_dflt,
+        .recalc         = &omap2_clksel_recalc,
+        .flags          = CLOCK_IN_OMAP4430,
+        .enable_reg     = OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "l4_per_clkdm",
+};
+
+/* Merged cm2_dm4_mux into gptimer4_ck */
+static struct clk gptimer4_ck = {
+        .name           = "gptimer4_ck",
+        .parent         = &sys_clkin_ck,
+        .clksel         = dmt1_clk_mux_sel,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL,
+        .clksel_mask    = OMAP4430_CLKSEL_MASK,
+        .ops            = &clkops_omap2_dflt,
+        .recalc         = &omap2_clksel_recalc,
+        .flags          = CLOCK_IN_OMAP4430,
+        .enable_reg     = OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "l4_per_clkdm",
+};
+
+static const struct clksel timer5_sync_mux_sel[] = {
+        { .parent = &syc_clk_div_ck, .rates = div_1_0_rates },
+        { .parent = &sys_32k_ck, .rates = div_1_1_rates },
+        { .parent = NULL },
+};
+
+/* Merged timer5_sync_mux into gptimer5_ck */
+static struct clk gptimer5_ck = {
+        .name           = "gptimer5_ck",
+        .parent         = &syc_clk_div_ck,
+        .clksel         = timer5_sync_mux_sel,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP4430_CM1_ABE_TIMER5_CLKCTRL,
+        .clksel_mask    = OMAP4430_CLKSEL_MASK,
+        .ops            = &clkops_omap2_dflt,
+        .recalc         = &omap2_clksel_recalc,
+        .flags          = CLOCK_IN_OMAP4430,
+        .enable_reg     = OMAP4430_CM1_ABE_TIMER5_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "abe_clkdm",
+};
+
+/* Merged timer6_sync_mux into gptimer6_ck */
+static struct clk gptimer6_ck = {
+        .name           = "gptimer6_ck",
+        .parent         = &syc_clk_div_ck,
+        .clksel         = timer5_sync_mux_sel,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP4430_CM1_ABE_TIMER6_CLKCTRL,
+        .clksel_mask    = OMAP4430_CLKSEL_MASK,
+        .ops            = &clkops_omap2_dflt,
+        .recalc         = &omap2_clksel_recalc,
+        .flags          = CLOCK_IN_OMAP4430,
+        .enable_reg     = OMAP4430_CM1_ABE_TIMER6_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "abe_clkdm",
+};
+
+/* Merged timer7_sync_mux into gptimer7_ck */
+static struct clk gptimer7_ck = {
+        .name           = "gptimer7_ck",
+        .parent         = &syc_clk_div_ck,
+        .clksel         = timer5_sync_mux_sel,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP4430_CM1_ABE_TIMER7_CLKCTRL,
+        .clksel_mask    = OMAP4430_CLKSEL_MASK,
+        .ops            = &clkops_omap2_dflt,
+        .recalc         = &omap2_clksel_recalc,
+        .flags          = CLOCK_IN_OMAP4430,
+        .enable_reg     = OMAP4430_CM1_ABE_TIMER7_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "abe_clkdm",
+};
+
+/* Merged timer8_sync_mux into gptimer8_ck */
+static struct clk gptimer8_ck = {
+        .name           = "gptimer8_ck",
+        .parent         = &syc_clk_div_ck,
+        .clksel         = timer5_sync_mux_sel,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP4430_CM1_ABE_TIMER8_CLKCTRL,
+        .clksel_mask    = OMAP4430_CLKSEL_MASK,
+        .ops            = &clkops_omap2_dflt,
+        .recalc         = &omap2_clksel_recalc,
+        .flags          = CLOCK_IN_OMAP4430,
+        .enable_reg     = OMAP4430_CM1_ABE_TIMER8_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "abe_clkdm",
+};
+
+/* Merged cm2_dm9_mux into gptimer9_ck */
+static struct clk gptimer9_ck = {
+        .name           = "gptimer9_ck",
+        .parent         = &sys_clkin_ck,
+        .clksel         = dmt1_clk_mux_sel,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL,
+        .clksel_mask    = OMAP4430_CLKSEL_MASK,
+        .ops            = &clkops_omap2_dflt,
+        .recalc         = &omap2_clksel_recalc,
+        .flags          = CLOCK_IN_OMAP4430,
+        .enable_reg     = OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "l4_per_clkdm",
+};
+
+static struct clk hdq1w_ck = {
+        .name           = "hdq1w_ck",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_L4PER_HDQ1W_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "l4_per_clkdm",
+        .parent         = &func_12m_fclk,
+        .recalc         = &followparent_recalc,
+};
+
+/* Merged hsi_fclk into hsi_ck */
+static struct clk hsi_ck = {
+        .name           = "hsi_ck",
+        .parent         = &dpll_per_m2x2_ck,
+        .clksel         = per_sgx_fclk_div,
+        .clksel_reg     = OMAP4430_CM_L3INIT_HSI_CLKCTRL,
+        .clksel_mask    = OMAP4430_CLKSEL_24_25_MASK,
+        .ops            = &clkops_omap2_dflt,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate,
+        .flags          = CLOCK_IN_OMAP4430,
+        .enable_reg     = OMAP4430_CM_L3INIT_HSI_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
+        .clkdm_name     = "l3_init_clkdm",
+};
+
+static struct clk i2c1_ck = {
+        .name           = "i2c1_ck",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_L4PER_I2C1_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "l4_per_clkdm",
+        .parent         = &func_96m_fclk,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk i2c2_ck = {
+        .name           = "i2c2_ck",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_L4PER_I2C2_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "l4_per_clkdm",
+        .parent         = &func_96m_fclk,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk i2c3_ck = {
+        .name           = "i2c3_ck",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_L4PER_I2C3_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "l4_per_clkdm",
+        .parent         = &func_96m_fclk,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk i2c4_ck = {
+        .name           = "i2c4_ck",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_L4PER_I2C4_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "l4_per_clkdm",
+        .parent         = &func_96m_fclk,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk iss_ck = {
+        .name           = "iss_ck",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_CAM_ISS_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "iss_clkdm",
+        .parent         = &ducati_clk_mux_ck,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk ivahd_ck = {
+        .name           = "ivahd_ck",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_IVAHD_IVAHD_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
+        .clkdm_name     = "ivahd_clkdm",
+        .parent         = &dpll_iva_m5_ck,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk keyboard_ck = {
+        .name           = "keyboard_ck",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_WKUP_KEYBOARD_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "l4_wkup_clkdm",
+        .parent         = &sys_32k_ck,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk l3_instr_interconnect_ck = {
+        .name           = "l3_instr_interconnect_ck",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_L3INSTR_L3_INSTR_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
+        .clkdm_name     = "l3_instr_clkdm",
+        .parent         = &l3_div_ck,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk l3_interconnect_3_ck = {
+        .name           = "l3_interconnect_3_ck",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_L3INSTR_L3_3_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
+        .clkdm_name     = "l3_instr_clkdm",
+        .parent         = &l3_div_ck,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mcasp_sync_mux_ck = {
+        .name           = "mcasp_sync_mux_ck",
+        .parent         = &abe_24m_fclk,
+        .clksel         = dmic_sync_mux_sel,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP4430_CM1_ABE_MCASP_CLKCTRL,
+        .clksel_mask    = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK,
+        .ops            = &clkops_null,
+        .recalc         = &omap2_clksel_recalc,
+        .flags          = CLOCK_IN_OMAP4430,
+};
+
+static const struct clksel func_mcasp_abe_gfclk_sel[] = {
+        { .parent = &mcasp_sync_mux_ck, .rates = div_1_0_rates },
+        { .parent = &pad_clks_ck, .rates = div_1_1_rates },
+        { .parent = &slimbus_clk, .rates = div_1_2_rates },
+        { .parent = NULL },
+};
+
+/* Merged func_mcasp_abe_gfclk into mcasp_ck */
+static struct clk mcasp_ck = {
+        .name           = "mcasp_ck",
+        .parent         = &mcasp_sync_mux_ck,
+        .clksel         = func_mcasp_abe_gfclk_sel,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP4430_CM1_ABE_MCASP_CLKCTRL,
+        .clksel_mask    = OMAP4430_CLKSEL_SOURCE_MASK,
+        .ops            = &clkops_omap2_dflt,
+        .recalc         = &omap2_clksel_recalc,
+        .flags          = CLOCK_IN_OMAP4430,
+        .enable_reg     = OMAP4430_CM1_ABE_MCASP_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "abe_clkdm",
+};
+
+static struct clk mcbsp1_sync_mux_ck = {
+        .name           = "mcbsp1_sync_mux_ck",
+        .parent         = &abe_24m_fclk,
+        .clksel         = dmic_sync_mux_sel,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP4430_CM1_ABE_MCBSP1_CLKCTRL,
+        .clksel_mask    = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK,
+        .ops            = &clkops_null,
+        .recalc         = &omap2_clksel_recalc,
+        .flags          = CLOCK_IN_OMAP4430,
+};
+
+static const struct clksel func_mcbsp1_gfclk_sel[] = {
+        { .parent = &mcbsp1_sync_mux_ck, .rates = div_1_0_rates },
+        { .parent = &pad_clks_ck, .rates = div_1_1_rates },
+        { .parent = &slimbus_clk, .rates = div_1_2_rates },
+        { .parent = NULL },
+};
+
+/* Merged func_mcbsp1_gfclk into mcbsp1_ck */
+static struct clk mcbsp1_ck = {
+        .name           = "mcbsp1_ck",
+        .parent         = &mcbsp1_sync_mux_ck,
+        .clksel         = func_mcbsp1_gfclk_sel,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP4430_CM1_ABE_MCBSP1_CLKCTRL,
+        .clksel_mask    = OMAP4430_CLKSEL_SOURCE_MASK,
+        .ops            = &clkops_omap2_dflt,
+        .recalc         = &omap2_clksel_recalc,
+        .flags          = CLOCK_IN_OMAP4430,
+        .enable_reg     = OMAP4430_CM1_ABE_MCBSP1_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "abe_clkdm",
+};
+
+static struct clk mcbsp2_sync_mux_ck = {
+        .name           = "mcbsp2_sync_mux_ck",
+        .parent         = &abe_24m_fclk,
+        .clksel         = dmic_sync_mux_sel,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP4430_CM1_ABE_MCBSP2_CLKCTRL,
+        .clksel_mask    = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK,
+        .ops            = &clkops_null,
+        .recalc         = &omap2_clksel_recalc,
+        .flags          = CLOCK_IN_OMAP4430,
+};
+
+static const struct clksel func_mcbsp2_gfclk_sel[] = {
+        { .parent = &mcbsp2_sync_mux_ck, .rates = div_1_0_rates },
+        { .parent = &pad_clks_ck, .rates = div_1_1_rates },
+        { .parent = &slimbus_clk, .rates = div_1_2_rates },
+        { .parent = NULL },
+};
+
+/* Merged func_mcbsp2_gfclk into mcbsp2_ck */
+static struct clk mcbsp2_ck = {
+        .name           = "mcbsp2_ck",
+        .parent         = &mcbsp2_sync_mux_ck,
+        .clksel         = func_mcbsp2_gfclk_sel,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP4430_CM1_ABE_MCBSP2_CLKCTRL,
+        .clksel_mask    = OMAP4430_CLKSEL_SOURCE_MASK,
+        .ops            = &clkops_omap2_dflt,
+        .recalc         = &omap2_clksel_recalc,
+        .flags          = CLOCK_IN_OMAP4430,
+        .enable_reg     = OMAP4430_CM1_ABE_MCBSP2_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "abe_clkdm",
+};
+
+static struct clk mcbsp3_sync_mux_ck = {
+        .name           = "mcbsp3_sync_mux_ck",
+        .parent         = &abe_24m_fclk,
+        .clksel         = dmic_sync_mux_sel,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP4430_CM1_ABE_MCBSP3_CLKCTRL,
+        .clksel_mask    = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK,
+        .ops            = &clkops_null,
+        .recalc         = &omap2_clksel_recalc,
+        .flags          = CLOCK_IN_OMAP4430,
+};
+
+static const struct clksel func_mcbsp3_gfclk_sel[] = {
+        { .parent = &mcbsp3_sync_mux_ck, .rates = div_1_0_rates },
+        { .parent = &pad_clks_ck, .rates = div_1_1_rates },
+        { .parent = &slimbus_clk, .rates = div_1_2_rates },
+        { .parent = NULL },
+};
+
+/* Merged func_mcbsp3_gfclk into mcbsp3_ck */
+static struct clk mcbsp3_ck = {
+        .name           = "mcbsp3_ck",
+        .parent         = &mcbsp3_sync_mux_ck,
+        .clksel         = func_mcbsp3_gfclk_sel,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP4430_CM1_ABE_MCBSP3_CLKCTRL,
+        .clksel_mask    = OMAP4430_CLKSEL_SOURCE_MASK,
+        .ops            = &clkops_omap2_dflt,
+        .recalc         = &omap2_clksel_recalc,
+        .flags          = CLOCK_IN_OMAP4430,
+        .enable_reg     = OMAP4430_CM1_ABE_MCBSP3_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "abe_clkdm",
+};
+
+static struct clk mcbsp4_sync_mux_ck = {
+        .name           = "mcbsp4_sync_mux_ck",
+        .parent         = &func_96m_fclk,
+        .clksel         = mcasp2_fclk_sel,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP4430_CM_L4PER_MCBSP4_CLKCTRL,
+        .clksel_mask    = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK,
+        .ops            = &clkops_null,
+        .recalc         = &omap2_clksel_recalc,
+        .flags          = CLOCK_IN_OMAP4430,
+};
+
+static const struct clksel per_mcbsp4_gfclk_sel[] = {
+        { .parent = &mcbsp4_sync_mux_ck, .rates = div_1_0_rates },
+        { .parent = &pad_clks_ck, .rates = div_1_1_rates },
+        { .parent = NULL },
+};
+
+/* Merged per_mcbsp4_gfclk into mcbsp4_ck */
+static struct clk mcbsp4_ck = {
+        .name           = "mcbsp4_ck",
+        .parent         = &mcbsp4_sync_mux_ck,
+        .clksel         = per_mcbsp4_gfclk_sel,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP4430_CM_L4PER_MCBSP4_CLKCTRL,
+        .clksel_mask    = OMAP4430_CLKSEL_SOURCE_24_24_MASK,
+        .ops            = &clkops_omap2_dflt,
+        .recalc         = &omap2_clksel_recalc,
+        .flags          = CLOCK_IN_OMAP4430,
+        .enable_reg     = OMAP4430_CM_L4PER_MCBSP4_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "l4_per_clkdm",
+};
+
+static struct clk mcspi1_ck = {
+        .name           = "mcspi1_ck",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_L4PER_MCSPI1_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "l4_per_clkdm",
+        .parent         = &func_48m_fclk,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mcspi2_ck = {
+        .name           = "mcspi2_ck",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_L4PER_MCSPI2_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "l4_per_clkdm",
+        .parent         = &func_48m_fclk,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mcspi3_ck = {
+        .name           = "mcspi3_ck",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_L4PER_MCSPI3_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "l4_per_clkdm",
+        .parent         = &func_48m_fclk,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mcspi4_ck = {
+        .name           = "mcspi4_ck",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_L4PER_MCSPI4_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "l4_per_clkdm",
+        .parent         = &func_48m_fclk,
+        .recalc         = &followparent_recalc,
+};
+
+/* Merged hsmmc1_fclk into mmc1_ck */
+static struct clk mmc1_ck = {
+        .name           = "mmc1_ck",
+        .parent         = &func_64m_fclk,
+        .clksel         = hsmmc6_fclk_sel,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP4430_CM_L3INIT_MMC1_CLKCTRL,
+        .clksel_mask    = OMAP4430_CLKSEL_MASK,
+        .ops            = &clkops_omap2_dflt,
+        .recalc         = &omap2_clksel_recalc,
+        .flags          = CLOCK_IN_OMAP4430,
+        .enable_reg     = OMAP4430_CM_L3INIT_MMC1_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "l3_init_clkdm",
+};
+
+/* Merged hsmmc2_fclk into mmc2_ck */
+static struct clk mmc2_ck = {
+        .name           = "mmc2_ck",
+        .parent         = &func_64m_fclk,
+        .clksel         = hsmmc6_fclk_sel,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP4430_CM_L3INIT_MMC2_CLKCTRL,
+        .clksel_mask    = OMAP4430_CLKSEL_MASK,
+        .ops            = &clkops_omap2_dflt,
+        .recalc         = &omap2_clksel_recalc,
+        .flags          = CLOCK_IN_OMAP4430,
+        .enable_reg     = OMAP4430_CM_L3INIT_MMC2_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "l3_init_clkdm",
+};
+
+static struct clk mmc3_ck = {
+        .name           = "mmc3_ck",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_L4PER_MMCSD3_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "l4_per_clkdm",
+        .parent         = &func_48m_fclk,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mmc4_ck = {
+        .name           = "mmc4_ck",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_L4PER_MMCSD4_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "l4_per_clkdm",
+        .parent         = &func_48m_fclk,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mmc5_ck = {
+        .name           = "mmc5_ck",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_L4PER_MMCSD5_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "l4_per_clkdm",
+        .parent         = &func_48m_fclk,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk ocp_wp1_ck = {
+        .name           = "ocp_wp1_ck",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_L3INSTR_OCP_WP1_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
+        .clkdm_name     = "l3_instr_clkdm",
+        .parent         = &l3_div_ck,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk pdm_ck = {
+        .name           = "pdm_ck",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM1_ABE_PDM_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "abe_clkdm",
+        .parent         = &pad_clks_ck,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk pkaeip29_ck = {
+        .name           = "pkaeip29_ck",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_L4SEC_PKAEIP29_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "l4_secure_clkdm",
+        .parent         = &l4_div_ck,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk rng_ck = {
+        .name           = "rng_ck",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_L4SEC_RNG_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
+        .clkdm_name     = "l4_secure_clkdm",
+        .parent         = &l4_div_ck,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk sha2md51_ck = {
+        .name           = "sha2md51_ck",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_L4SEC_SHA2MD51_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "l4_secure_clkdm",
+        .parent         = &l3_div_ck,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk sl2_ck = {
+        .name           = "sl2_ck",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_IVAHD_SL2_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
+        .clkdm_name     = "ivahd_clkdm",
+        .parent         = &dpll_iva_m5_ck,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk slimbus1_ck = {
+        .name           = "slimbus1_ck",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "abe_clkdm",
+        .parent         = &ocp_abe_iclk,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk slimbus2_ck = {
+        .name           = "slimbus2_ck",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "l4_per_clkdm",
+        .parent         = &l4_div_ck,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk sr_core_ck = {
+        .name           = "sr_core_ck",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_ALWON_SR_CORE_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "l4_ao_clkdm",
+        .parent         = &l4_wkup_clk_mux_ck,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk sr_iva_ck = {
+        .name           = "sr_iva_ck",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_ALWON_SR_IVA_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "l4_ao_clkdm",
+        .parent         = &l4_wkup_clk_mux_ck,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk sr_mpu_ck = {
+        .name           = "sr_mpu_ck",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_ALWON_SR_MPU_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "l4_ao_clkdm",
+        .parent         = &l4_wkup_clk_mux_ck,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk tesla_ck = {
+        .name           = "tesla_ck",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_TESLA_TESLA_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
+        .clkdm_name     = "tesla_clkdm",
+        .parent         = &dpll_iva_m4_ck,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk uart1_ck = {
+        .name           = "uart1_ck",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_L4PER_UART1_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "l4_per_clkdm",
+        .parent         = &func_48m_fclk,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk uart2_ck = {
+        .name           = "uart2_ck",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_L4PER_UART2_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "l4_per_clkdm",
+        .parent         = &func_48m_fclk,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk uart3_ck = {
+        .name           = "uart3_ck",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_L4PER_UART3_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "l4_per_clkdm",
+        .parent         = &func_48m_fclk,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk uart4_ck = {
+        .name           = "uart4_ck",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_L4PER_UART4_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "l4_per_clkdm",
+        .parent         = &func_48m_fclk,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk unipro1_ck = {
+        .name           = "unipro1_ck",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_L3INIT_UNIPRO1_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "l3_init_clkdm",
+        .parent         = &func_96m_fclk,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk usb_host_ck = {
+        .name           = "usb_host_ck",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "l3_init_clkdm",
+        .parent         = &init_60m_fclk,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk usb_host_fs_ck = {
+        .name           = "usb_host_fs_ck",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_L3INIT_USB_HOST_FS_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "l3_init_clkdm",
+        .parent         = &func_48mc_fclk,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk usb_otg_ck = {
+        .name           = "usb_otg_ck",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
+        .clkdm_name     = "l3_init_clkdm",
+        .parent         = &l3_div_ck,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk usb_tll_ck = {
+        .name           = "usb_tll_ck",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
+        .clkdm_name     = "l3_init_clkdm",
+        .parent         = &l4_div_ck,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk usbphyocp2scp_ck = {
+        .name           = "usbphyocp2scp_ck",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
+        .clkdm_name     = "l3_init_clkdm",
+        .parent         = &l4_div_ck,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk usim_ck = {
+        .name           = "usim_ck",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_WKUP_USIM_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "l4_wkup_clkdm",
+        .parent         = &sys_32k_ck,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk wdt2_ck = {
+        .name           = "wdt2_ck",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_WKUP_WDT2_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "l4_wkup_clkdm",
+        .parent         = &sys_32k_ck,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk wdt3_ck = {
+        .name           = "wdt3_ck",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM1_ABE_WDT3_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "abe_clkdm",
+        .parent         = &sys_32k_ck,
+        .recalc         = &followparent_recalc,
+};
+
+/* Remaining optional clocks */
+static const struct clksel otg_60m_gfclk_sel[] = {
+        { .parent = &utmi_phy_clkout_ck, .rates = div_1_0_rates },
+        { .parent = &xclk60motg_ck, .rates = div_1_1_rates },
+        { .parent = NULL },
+};
+
+static struct clk otg_60m_gfclk_ck = {
+        .name           = "otg_60m_gfclk_ck",
+        .parent         = &utmi_phy_clkout_ck,
+        .clksel         = otg_60m_gfclk_sel,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL,
+        .clksel_mask    = OMAP4430_CLKSEL_60M_MASK,
+        .ops            = &clkops_null,
+        .recalc         = &omap2_clksel_recalc,
+        .flags          = CLOCK_IN_OMAP4430,
+};
+
+static const struct clksel stm_clk_div_div[] = {
+        { .parent = &pmd_stm_clock_mux_ck, .rates = div3_1to4_rates },
+        { .parent = NULL },
+};
+
+static struct clk stm_clk_div_ck = {
+        .name           = "stm_clk_div_ck",
+        .parent         = &pmd_stm_clock_mux_ck,
+        .clksel         = stm_clk_div_div,
+        .clksel_reg     = OMAP4430_CM_EMU_DEBUGSS_CLKCTRL,
+        .clksel_mask    = OMAP4430_CLKSEL_PMD_STM_CLK_MASK,
+        .ops            = &clkops_null,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate,
+        .flags          = CLOCK_IN_OMAP4430,
+};
+
+static const struct clksel trace_clk_div_div[] = {
+        { .parent = &pmd_trace_clk_mux_ck, .rates = div3_1to4_rates },
+        { .parent = NULL },
+};
+
+static struct clk trace_clk_div_ck = {
+        .name           = "trace_clk_div_ck",
+        .parent         = &pmd_trace_clk_mux_ck,
+        .clksel         = trace_clk_div_div,
+        .clksel_reg     = OMAP4430_CM_EMU_DEBUGSS_CLKCTRL,
+        .clksel_mask    = OMAP4430_CLKSEL_PMD_TRACE_CLK_MASK,
+        .ops            = &clkops_null,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate,
+        .flags          = CLOCK_IN_OMAP4430,
+};
+
+static const struct clksel_rate div2_14to18_rates[] = {
+        { .div = 14, .val = 0, .flags = RATE_IN_4430 },
+        { .div = 18, .val = 1, .flags = RATE_IN_4430 },
+        { .div = 0 },
+};
+
+static const struct clksel usim_fclk_div[] = {
+        { .parent = &dpll_per_m4_ck, .rates = div2_14to18_rates },
+        { .parent = NULL },
+};
+
+static struct clk usim_fclk = {
+        .name           = "usim_fclk",
+        .parent         = &dpll_per_m4_ck,
+        .clksel         = usim_fclk_div,
+        .clksel_reg     = OMAP4430_CM_WKUP_USIM_CLKCTRL,
+        .clksel_mask    = OMAP4430_CLKSEL_DIV_MASK,
+        .ops            = &clkops_null,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate,
+        .flags          = CLOCK_IN_OMAP4430,
+};
+
+static const struct clksel utmi_p1_gfclk_sel[] = {
+        { .parent = &init_60m_fclk, .rates = div_1_0_rates },
+        { .parent = &xclk60mhsp1_ck, .rates = div_1_1_rates },
+        { .parent = NULL },
+};
+
+static struct clk utmi_p1_gfclk_ck = {
+        .name           = "utmi_p1_gfclk_ck",
+        .parent         = &init_60m_fclk,
+        .clksel         = utmi_p1_gfclk_sel,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
+        .clksel_mask    = OMAP4430_CLKSEL_UTMI_P1_MASK,
+        .ops            = &clkops_null,
+        .recalc         = &omap2_clksel_recalc,
+        .flags          = CLOCK_IN_OMAP4430,
+};
+
+static const struct clksel utmi_p2_gfclk_sel[] = {
+        { .parent = &init_60m_fclk, .rates = div_1_0_rates },
+        { .parent = &xclk60mhsp2_ck, .rates = div_1_1_rates },
+        { .parent = NULL },
+};
+
+static struct clk utmi_p2_gfclk_ck = {
+        .name           = "utmi_p2_gfclk_ck",
+        .parent         = &init_60m_fclk,
+        .clksel         = utmi_p2_gfclk_sel,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
+        .clksel_mask    = OMAP4430_CLKSEL_UTMI_P2_MASK,
+        .ops            = &clkops_null,
+        .recalc         = &omap2_clksel_recalc,
+        .flags          = CLOCK_IN_OMAP4430,
+};
+
+/*
+ * clkdev
+ */
+
+static struct omap_clk omap44xx_clks[] = {
+        CLK(NULL,       "extalt_clkin_ck",              &extalt_clkin_ck,       CK_443X),
+        CLK(NULL,       "pad_clks_ck",                  &pad_clks_ck,   CK_443X),
+        CLK(NULL,       "pad_slimbus_core_clks_ck",     &pad_slimbus_core_clks_ck,      CK_443X),
+        CLK(NULL,       "secure_32k_clk_src_ck",        &secure_32k_clk_src_ck, CK_443X),
+        CLK(NULL,       "slimbus_clk",                  &slimbus_clk,   CK_443X),
+        CLK(NULL,       "sys_32k_ck",                   &sys_32k_ck,    CK_443X),
+        CLK(NULL,       "virt_12000000_ck",             &virt_12000000_ck,      CK_443X),
+        CLK(NULL,       "virt_13000000_ck",             &virt_13000000_ck,      CK_443X),
+        CLK(NULL,       "virt_16800000_ck",             &virt_16800000_ck,      CK_443X),
+        CLK(NULL,       "virt_19200000_ck",             &virt_19200000_ck,      CK_443X),
+        CLK(NULL,       "virt_26000000_ck",             &virt_26000000_ck,      CK_443X),
+        CLK(NULL,       "virt_27000000_ck",             &virt_27000000_ck,      CK_443X),
+        CLK(NULL,       "virt_38400000_ck",             &virt_38400000_ck,      CK_443X),
+        CLK(NULL,       "sys_clkin_ck",                 &sys_clkin_ck,  CK_443X),
+        CLK(NULL,       "utmi_phy_clkout_ck",           &utmi_phy_clkout_ck,    CK_443X),
+        CLK(NULL,       "xclk60mhsp1_ck",               &xclk60mhsp1_ck,        CK_443X),
+        CLK(NULL,       "xclk60mhsp2_ck",               &xclk60mhsp2_ck,        CK_443X),
+        CLK(NULL,       "xclk60motg_ck",                &xclk60motg_ck, CK_443X),
+        CLK(NULL,       "dpll_sys_ref_clk",             &dpll_sys_ref_clk,      CK_443X),
+        CLK(NULL,       "abe_dpll_refclk_mux_ck",       &abe_dpll_refclk_mux_ck,        CK_443X),
+        CLK(NULL,       "dpll_abe_ck",                  &dpll_abe_ck,   CK_443X),
+        CLK(NULL,       "dpll_abe_m2x2_ck",             &dpll_abe_m2x2_ck,      CK_443X),
+        CLK(NULL,       "abe_24m_fclk",                 &abe_24m_fclk,  CK_443X),
+        CLK(NULL,       "abe_clk",                      &abe_clk,       CK_443X),
+        CLK(NULL,       "aess_fclk",                    &aess_fclk,     CK_443X),
+        CLK(NULL,       "dpll_abe_m3_ck",               &dpll_abe_m3_ck,        CK_443X),
+        CLK(NULL,       "core_hsd_byp_clk_mux_ck",      &core_hsd_byp_clk_mux_ck,       CK_443X),
+        CLK(NULL,       "dpll_core_ck",                 &dpll_core_ck,  CK_443X),
+        CLK(NULL,       "dpll_core_m6_ck",              &dpll_core_m6_ck,       CK_443X),
+        CLK(NULL,       "dbgclk_mux_ck",                &dbgclk_mux_ck, CK_443X),
+        CLK(NULL,       "dpll_core_m2_ck",              &dpll_core_m2_ck,       CK_443X),
+        CLK(NULL,       "ddrphy_ck",                    &ddrphy_ck,     CK_443X),
+        CLK(NULL,       "dpll_core_m5_ck",              &dpll_core_m5_ck,       CK_443X),
+        CLK(NULL,       "div_core_ck",                  &div_core_ck,   CK_443X),
+        CLK(NULL,       "div_iva_hs_clk",               &div_iva_hs_clk,        CK_443X),
+        CLK(NULL,       "div_mpu_hs_clk",               &div_mpu_hs_clk,        CK_443X),
+        CLK(NULL,       "dpll_core_m4_ck",              &dpll_core_m4_ck,       CK_443X),
+        CLK(NULL,       "dll_clk_div_ck",               &dll_clk_div_ck,        CK_443X),
+        CLK(NULL,       "dpll_abe_m2_ck",               &dpll_abe_m2_ck,        CK_443X),
+        CLK(NULL,       "dpll_core_m3_ck",              &dpll_core_m3_ck,       CK_443X),
+        CLK(NULL,       "dpll_core_m7_ck",              &dpll_core_m7_ck,       CK_443X),
+        CLK(NULL,       "iva_hsd_byp_clk_mux_ck",       &iva_hsd_byp_clk_mux_ck,        CK_443X),
+        CLK(NULL,       "dpll_iva_ck",                  &dpll_iva_ck,   CK_443X),
+        CLK(NULL,       "dpll_iva_m4_ck",               &dpll_iva_m4_ck,        CK_443X),
+        CLK(NULL,       "dpll_iva_m5_ck",               &dpll_iva_m5_ck,        CK_443X),
+        CLK(NULL,       "dpll_mpu_ck",                  &dpll_mpu_ck,   CK_443X),
+        CLK(NULL,       "dpll_mpu_m2_ck",               &dpll_mpu_m2_ck,        CK_443X),
+        CLK(NULL,       "per_hs_clk_div_ck",            &per_hs_clk_div_ck,     CK_443X),
+        CLK(NULL,       "per_hsd_byp_clk_mux_ck",       &per_hsd_byp_clk_mux_ck,        CK_443X),
+        CLK(NULL,       "dpll_per_ck",                  &dpll_per_ck,   CK_443X),
+        CLK(NULL,       "dpll_per_m2_ck",               &dpll_per_m2_ck,        CK_443X),
+        CLK(NULL,       "dpll_per_m2x2_ck",             &dpll_per_m2x2_ck,      CK_443X),
+        CLK(NULL,       "dpll_per_m3_ck",               &dpll_per_m3_ck,        CK_443X),
+        CLK(NULL,       "dpll_per_m4_ck",               &dpll_per_m4_ck,        CK_443X),
+        CLK(NULL,       "dpll_per_m5_ck",               &dpll_per_m5_ck,        CK_443X),
+        CLK(NULL,       "dpll_per_m6_ck",               &dpll_per_m6_ck,        CK_443X),
+        CLK(NULL,       "dpll_per_m7_ck",               &dpll_per_m7_ck,        CK_443X),
+        CLK(NULL,       "dpll_unipro_ck",               &dpll_unipro_ck,        CK_443X),
+        CLK(NULL,       "dpll_unipro_m2x2_ck",          &dpll_unipro_m2x2_ck,   CK_443X),
+        CLK(NULL,       "usb_hs_clk_div_ck",            &usb_hs_clk_div_ck,     CK_443X),
+        CLK(NULL,       "dpll_usb_ck",                  &dpll_usb_ck,   CK_443X),
+        CLK(NULL,       "dpll_usb_clkdcoldo_ck",        &dpll_usb_clkdcoldo_ck, CK_443X),
+        CLK(NULL,       "dpll_usb_m2_ck",               &dpll_usb_m2_ck,        CK_443X),
+        CLK(NULL,       "ducati_clk_mux_ck",            &ducati_clk_mux_ck,     CK_443X),
+        CLK(NULL,       "func_12m_fclk",                &func_12m_fclk, CK_443X),
+        CLK(NULL,       "func_24m_clk",                 &func_24m_clk,  CK_443X),
+        CLK(NULL,       "func_24mc_fclk",               &func_24mc_fclk,        CK_443X),
+        CLK(NULL,       "func_48m_fclk",                &func_48m_fclk, CK_443X),
+        CLK(NULL,       "func_48mc_fclk",               &func_48mc_fclk,        CK_443X),
+        CLK(NULL,       "func_64m_fclk",                &func_64m_fclk, CK_443X),
+        CLK(NULL,       "func_96m_fclk",                &func_96m_fclk, CK_443X),
+        CLK(NULL,       "hsmmc6_fclk",                  &hsmmc6_fclk,   CK_443X),
+        CLK(NULL,       "init_60m_fclk",                &init_60m_fclk, CK_443X),
+        CLK(NULL,       "l3_div_ck",                    &l3_div_ck,     CK_443X),
+        CLK(NULL,       "l4_div_ck",                    &l4_div_ck,     CK_443X),
+        CLK(NULL,       "lp_clk_div_ck",                &lp_clk_div_ck, CK_443X),
+        CLK(NULL,       "l4_wkup_clk_mux_ck",           &l4_wkup_clk_mux_ck,    CK_443X),
+        CLK(NULL,       "per_abe_nc_fclk",              &per_abe_nc_fclk,       CK_443X),
+        CLK(NULL,       "mcasp2_fclk",                  &mcasp2_fclk,   CK_443X),
+        CLK(NULL,       "mcasp3_fclk",                  &mcasp3_fclk,   CK_443X),
+        CLK(NULL,       "ocp_abe_iclk",                 &ocp_abe_iclk,  CK_443X),
+        CLK(NULL,       "per_abe_24m_fclk",             &per_abe_24m_fclk,      CK_443X),
+        CLK(NULL,       "pmd_stm_clock_mux_ck",         &pmd_stm_clock_mux_ck,  CK_443X),
+        CLK(NULL,       "pmd_trace_clk_mux_ck",         &pmd_trace_clk_mux_ck,  CK_443X),
+        CLK(NULL,       "syc_clk_div_ck",               &syc_clk_div_ck,        CK_443X),
+        CLK(NULL,       "aes1_ck",                      &aes1_ck,       CK_443X),
+        CLK(NULL,       "aes2_ck",                      &aes2_ck,       CK_443X),
+        CLK(NULL,       "aess_ck",                      &aess_ck,       CK_443X),
+        CLK(NULL,       "cust_efuse_ck",                &cust_efuse_ck, CK_443X),
+        CLK(NULL,       "des3des_ck",                   &des3des_ck,    CK_443X),
+        CLK(NULL,       "dmic_sync_mux_ck",             &dmic_sync_mux_ck,      CK_443X),
+        CLK(NULL,       "dmic_ck",                      &dmic_ck,       CK_443X),
+        CLK(NULL,       "dss_ck",                       &dss_ck,        CK_443X),
+        CLK(NULL,       "ducati_ck",                    &ducati_ck,     CK_443X),
+        CLK(NULL,       "emif1_ck",                     &emif1_ck,      CK_443X),
+        CLK(NULL,       "emif2_ck",                     &emif2_ck,      CK_443X),
+        CLK(NULL,       "fdif_ck",                      &fdif_ck,       CK_443X),
+        CLK(NULL,       "per_sgx_fclk",                 &per_sgx_fclk,  CK_443X),
+        CLK(NULL,       "gfx_ck",                       &gfx_ck,        CK_443X),
+        CLK(NULL,       "gpio1_ck",                     &gpio1_ck,      CK_443X),
+        CLK(NULL,       "gpio2_ck",                     &gpio2_ck,      CK_443X),
+        CLK(NULL,       "gpio3_ck",                     &gpio3_ck,      CK_443X),
+        CLK(NULL,       "gpio4_ck",                     &gpio4_ck,      CK_443X),
+        CLK(NULL,       "gpio5_ck",                     &gpio5_ck,      CK_443X),
+        CLK(NULL,       "gpio6_ck",                     &gpio6_ck,      CK_443X),
+        CLK(NULL,       "gpmc_ck",                      &gpmc_ck,       CK_443X),
+        CLK(NULL,       "gptimer1_ck",                  &gptimer1_ck,   CK_443X),
+        CLK(NULL,       "gptimer10_ck",                 &gptimer10_ck,  CK_443X),
+        CLK(NULL,       "gptimer11_ck",                 &gptimer11_ck,  CK_443X),
+        CLK(NULL,       "gptimer2_ck",                  &gptimer2_ck,   CK_443X),
+        CLK(NULL,       "gptimer3_ck",                  &gptimer3_ck,   CK_443X),
+        CLK(NULL,       "gptimer4_ck",                  &gptimer4_ck,   CK_443X),
+        CLK(NULL,       "gptimer5_ck",                  &gptimer5_ck,   CK_443X),
+        CLK(NULL,       "gptimer6_ck",                  &gptimer6_ck,   CK_443X),
+        CLK(NULL,       "gptimer7_ck",                  &gptimer7_ck,   CK_443X),
+        CLK(NULL,       "gptimer8_ck",                  &gptimer8_ck,   CK_443X),
+        CLK(NULL,       "gptimer9_ck",                  &gptimer9_ck,   CK_443X),
+        CLK("omap2_hdq.0",      "ick",                          &hdq1w_ck,      CK_443X),
+        CLK(NULL,       "hsi_ck",                       &hsi_ck,        CK_443X),
+        CLK("i2c_omap.1",       "ick",                          &i2c1_ck,       CK_443X),
+        CLK("i2c_omap.2",       "ick",                          &i2c2_ck,       CK_443X),
+        CLK("i2c_omap.3",       "ick",                          &i2c3_ck,       CK_443X),
+        CLK("i2c_omap.4",       "ick",                          &i2c4_ck,       CK_443X),
+        CLK(NULL,       "iss_ck",                       &iss_ck,        CK_443X),
+        CLK(NULL,       "ivahd_ck",                     &ivahd_ck,      CK_443X),
+        CLK(NULL,       "keyboard_ck",                  &keyboard_ck,   CK_443X),
+        CLK(NULL,       "l3_instr_interconnect_ck",     &l3_instr_interconnect_ck,      CK_443X),
+        CLK(NULL,       "l3_interconnect_3_ck",         &l3_interconnect_3_ck,  CK_443X),
+        CLK(NULL,       "mcasp_sync_mux_ck",            &mcasp_sync_mux_ck,     CK_443X),
+        CLK(NULL,       "mcasp_ck",                     &mcasp_ck,      CK_443X),
+        CLK(NULL,       "mcbsp1_sync_mux_ck",           &mcbsp1_sync_mux_ck,    CK_443X),
+        CLK("omap-mcbsp.1",     "fck",                          &mcbsp1_ck,     CK_443X),
+        CLK(NULL,       "mcbsp2_sync_mux_ck",           &mcbsp2_sync_mux_ck,    CK_443X),
+        CLK("omap-mcbsp.2",     "fck",                          &mcbsp2_ck,     CK_443X),
+        CLK(NULL,       "mcbsp3_sync_mux_ck",           &mcbsp3_sync_mux_ck,    CK_443X),
+        CLK("omap-mcbsp.3",     "fck",                          &mcbsp3_ck,     CK_443X),
+        CLK(NULL,       "mcbsp4_sync_mux_ck",           &mcbsp4_sync_mux_ck,    CK_443X),
+        CLK("omap-mcbsp.4",     "fck",                          &mcbsp4_ck,     CK_443X),
+        CLK("omap2_mcspi.1",    "fck",                          &mcspi1_ck,     CK_443X),
+        CLK("omap2_mcspi.2",    "fck",                          &mcspi2_ck,     CK_443X),
+        CLK("omap2_mcspi.3",    "fck",                          &mcspi3_ck,     CK_443X),
+        CLK("omap2_mcspi.4",    "fck",                          &mcspi4_ck,     CK_443X),
+        CLK("mmci-omap-hs.0",   "fck",                          &mmc1_ck,       CK_443X),
+        CLK("mmci-omap-hs.1",   "fck",                          &mmc2_ck,       CK_443X),
+        CLK("mmci-omap-hs.2",   "fck",                          &mmc3_ck,       CK_443X),
+        CLK("mmci-omap-hs.3",   "fck",                          &mmc4_ck,       CK_443X),
+        CLK("mmci-omap-hs.4",   "fck",                          &mmc5_ck,       CK_443X),
+        CLK(NULL,       "ocp_wp1_ck",                   &ocp_wp1_ck,    CK_443X),
+        CLK(NULL,       "pdm_ck",                       &pdm_ck,        CK_443X),
+        CLK(NULL,       "pkaeip29_ck",                  &pkaeip29_ck,   CK_443X),
+        CLK("omap_rng", "ick",                          &rng_ck,        CK_443X),
+        CLK(NULL,       "sha2md51_ck",                  &sha2md51_ck,   CK_443X),
+        CLK(NULL,       "sl2_ck",                       &sl2_ck,        CK_443X),
+        CLK(NULL,       "slimbus1_ck",                  &slimbus1_ck,   CK_443X),
+        CLK(NULL,       "slimbus2_ck",                  &slimbus2_ck,   CK_443X),
+        CLK(NULL,       "sr_core_ck",                   &sr_core_ck,    CK_443X),
+        CLK(NULL,       "sr_iva_ck",                    &sr_iva_ck,     CK_443X),
+        CLK(NULL,       "sr_mpu_ck",                    &sr_mpu_ck,     CK_443X),
+        CLK(NULL,       "tesla_ck",                     &tesla_ck,      CK_443X),
+        CLK(NULL,       "uart1_ck",                     &uart1_ck,      CK_443X),
+        CLK(NULL,       "uart2_ck",                     &uart2_ck,      CK_443X),
+        CLK(NULL,       "uart3_ck",                     &uart3_ck,      CK_443X),
+        CLK(NULL,       "uart4_ck",                     &uart4_ck,      CK_443X),
+        CLK(NULL,       "unipro1_ck",                   &unipro1_ck,    CK_443X),
+        CLK(NULL,       "usb_host_ck",                  &usb_host_ck,   CK_443X),
+        CLK(NULL,       "usb_host_fs_ck",               &usb_host_fs_ck,        CK_443X),
+        CLK("musb_hdrc",        "ick",                          &usb_otg_ck,    CK_443X),
+        CLK(NULL,       "usb_tll_ck",                   &usb_tll_ck,    CK_443X),
+        CLK(NULL,       "usbphyocp2scp_ck",             &usbphyocp2scp_ck,      CK_443X),
+        CLK(NULL,       "usim_ck",                      &usim_ck,       CK_443X),
+        CLK("omap_wdt", "fck",                          &wdt2_ck,       CK_443X),
+        CLK(NULL,       "wdt3_ck",                      &wdt3_ck,       CK_443X),
+        CLK(NULL,       "otg_60m_gfclk_ck",             &otg_60m_gfclk_ck,      CK_443X),
+        CLK(NULL,       "stm_clk_div_ck",               &stm_clk_div_ck,        CK_443X),
+        CLK(NULL,       "trace_clk_div_ck",             &trace_clk_div_ck,      CK_443X),
+        CLK(NULL,       "usim_fclk",                    &usim_fclk,     CK_443X),
+        CLK(NULL,       "utmi_p1_gfclk_ck",             &utmi_p1_gfclk_ck,      CK_443X),
+        CLK(NULL,       "utmi_p2_gfclk_ck",             &utmi_p2_gfclk_ck,      CK_443X),
+};
+
+int __init omap2_clk_init(void)
+{
+        /* struct prcm_config *prcm; */
+        struct omap_clk *c;
+        /* u32 clkrate; */
+        u32 cpu_clkflg;
+
+        if (cpu_is_omap44xx()) {
+                cpu_mask = RATE_IN_4430;
+                cpu_clkflg = CK_443X;
+        }
+
+        clk_init(&omap2_clk_functions);
+
+        for (c = omap44xx_clks; c < omap44xx_clks + ARRAY_SIZE(omap44xx_clks);
+                                                                          c++)
+                clk_preinit(c->lk.clk);
+
+        for (c = omap44xx_clks; c < omap44xx_clks + ARRAY_SIZE(omap44xx_clks);
+                                                                          c++)
+                if (c->cpu & cpu_clkflg) {
+                        clkdev_add(&c->lk);
+                        clk_register(c->lk.clk);
+                        /* TODO
+                        omap2_init_clk_clkdm(c->lk.clk);
+                        */
+                }
+
+        recalculate_root_clocks();
+
+        /*
+         * Only enable those clocks we will need, let the drivers
+         * enable other clocks as necessary
+         */
+        clk_enable_init_clocks();
+
+        return 0;
+}
diff --git a/arch/arm/mach-omap2/clock_common_data.c b/arch/arm/mach-omap2/clock_common_data.c
new file mode 100644
index 000000000000..f69096b88cdb
--- /dev/null
+++ b/arch/arm/mach-omap2/clock_common_data.c
@@ -0,0 +1,39 @@
+/*
+ *  linux/arch/arm/mach-omap2/clock_common_data.c
+ *
+ *  Copyright (C) 2005-2009 Texas Instruments, Inc.
+ *  Copyright (C) 2004-2009 Nokia Corporation
+ *
+ *  Contacts:
+ *  Richard Woodruff <r-woodruff2@ti.com>
+ *  Paul Walmsley
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This file contains clock data that is common to both the OMAP2xxx and
+ * OMAP3xxx clock definition files.
+ */
+
+#include "clock.h"
+
+/* clksel_rate data common to 24xx/343x */
+const struct clksel_rate gpt_32k_rates[] = {
+         { .div = 1, .val = 0, .flags = RATE_IN_24XX | RATE_IN_343X | DEFAULT_RATE },
+         { .div = 0 }
+};
+
+const struct clksel_rate gpt_sys_rates[] = {
+         { .div = 1, .val = 1, .flags = RATE_IN_24XX | RATE_IN_343X | DEFAULT_RATE },
+         { .div = 0 }
+};
+
+const struct clksel_rate gfx_l3_rates[] = {
+        { .div = 1, .val = 1, .flags = RATE_IN_24XX | RATE_IN_343X },
+        { .div = 2, .val = 2, .flags = RATE_IN_24XX | RATE_IN_343X | DEFAULT_RATE },
+        { .div = 3, .val = 3, .flags = RATE_IN_243X | RATE_IN_343X },
+        { .div = 4, .val = 4, .flags = RATE_IN_243X | RATE_IN_343X },
+        { .div = 0 }
+};
+
diff --git a/arch/arm/mach-omap2/clockdomain.c b/arch/arm/mach-omap2/clockdomain.c
index fcd82320a6a3..1a45ed1e8ba1 100644
--- a/arch/arm/mach-omap2/clockdomain.c
+++ b/arch/arm/mach-omap2/clockdomain.c
@@ -2,7 +2,7 @@
  * OMAP2/3 clockdomain framework functions
  *
  * Copyright (C) 2008 Texas Instruments, Inc.
- * Copyright (C) 2008 Nokia Corporation
+ * Copyright (C) 2008-2009 Nokia Corporation
  *
  * Written by Paul Walmsley and Jouni Högander
  *
@@ -10,9 +10,7 @@
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
  */
-#ifdef CONFIG_OMAP_DEBUG_CLOCKDOMAIN
-#  define DEBUG
-#endif
+#undef DEBUG
 
 #include <linux/module.h>
 #include <linux/kernel.h>
diff --git a/arch/arm/mach-omap2/cm-regbits-44xx.h b/arch/arm/mach-omap2/cm-regbits-44xx.h
new file mode 100644
index 000000000000..0e67f75aa35c
--- /dev/null
+++ b/arch/arm/mach-omap2/cm-regbits-44xx.h
@@ -0,0 +1,1474 @@
+/*
+ * OMAP44xx Clock Management register bits
+ *
+ * Copyright (C) 2009 Texas Instruments, Inc.
+ * Copyright (C) 2009 Nokia Corporation
+ *
+ * Paul Walmsley (paul@pwsan.com)
+ * Rajendra Nayak (rnayak@ti.com)
+ * Benoit Cousson (b-cousson@ti.com)
+ *
+ * This file is automatically generated from the OMAP hardware databases.
+ * We respectfully ask that any modifications to this file be coordinated
+ * with the public linux-omap@vger.kernel.org mailing list and the
+ * authors above to ensure that the autogeneration scripts are kept
+ * up-to-date with the file contents.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ARCH_ARM_MACH_OMAP2_CM_REGBITS_44XX_H
+#define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_44XX_H
+
+#include "cm.h"
+
+
+/* Used by CM_L3_1_DYNAMICDEP, CM_MPU_DYNAMICDEP, CM_TESLA_DYNAMICDEP */
+#define OMAP4430_ABE_DYNDEP_SHIFT                               (1 << 3)
+#define OMAP4430_ABE_DYNDEP_MASK                                BITFIELD(3, 3)
+
+/*
+ * Used by CM_D2D_STATICDEP, CM_DUCATI_STATICDEP, CM_SDMA_STATICDEP,
+ * CM_L3INIT_STATICDEP, CM_SDMA_STATICDEP_RESTORE, CM_MPU_STATICDEP,
+ * CM_TESLA_STATICDEP
+ */
+#define OMAP4430_ABE_STATDEP_SHIFT                              (1 << 3)
+#define OMAP4430_ABE_STATDEP_MASK                               BITFIELD(3, 3)
+
+/* Used by CM_L4CFG_DYNAMICDEP */
+#define OMAP4430_ALWONCORE_DYNDEP_SHIFT                         (1 << 16)
+#define OMAP4430_ALWONCORE_DYNDEP_MASK                          BITFIELD(16, 16)
+
+/* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP, CM_TESLA_STATICDEP */
+#define OMAP4430_ALWONCORE_STATDEP_SHIFT                        (1 << 16)
+#define OMAP4430_ALWONCORE_STATDEP_MASK                         BITFIELD(16, 16)
+
+/*
+ * Used by CM_AUTOIDLE_DPLL_PER, CM_AUTOIDLE_DPLL_UNIPRO, CM_AUTOIDLE_DPLL_USB,
+ * CM_AUTOIDLE_DPLL_CORE_RESTORE, CM_AUTOIDLE_DPLL_ABE, CM_AUTOIDLE_DPLL_CORE,
+ * CM_AUTOIDLE_DPLL_DDRPHY, CM_AUTOIDLE_DPLL_IVA, CM_AUTOIDLE_DPLL_MPU
+ */
+#define OMAP4430_AUTO_DPLL_MODE_SHIFT                           (1 << 0)
+#define OMAP4430_AUTO_DPLL_MODE_MASK                            BITFIELD(0, 2)
+
+/* Used by CM_L4CFG_DYNAMICDEP */
+#define OMAP4430_CEFUSE_DYNDEP_SHIFT                            (1 << 17)
+#define OMAP4430_CEFUSE_DYNDEP_MASK                             BITFIELD(17, 17)
+
+/* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP, CM_TESLA_STATICDEP */
+#define OMAP4430_CEFUSE_STATDEP_SHIFT                           (1 << 17)
+#define OMAP4430_CEFUSE_STATDEP_MASK                            BITFIELD(17, 17)
+
+/* Used by CM1_ABE_CLKSTCTRL */
+#define OMAP4430_CLKACTIVITY_ABE_24M_GFCLK_SHIFT                (1 << 13)
+#define OMAP4430_CLKACTIVITY_ABE_24M_GFCLK_MASK                 BITFIELD(13, 13)
+
+/* Used by CM1_ABE_CLKSTCTRL */
+#define OMAP4430_CLKACTIVITY_ABE_ALWON_32K_CLK_SHIFT            (1 << 12)
+#define OMAP4430_CLKACTIVITY_ABE_ALWON_32K_CLK_MASK             BITFIELD(12, 12)
+
+/* Used by CM_WKUP_CLKSTCTRL */
+#define OMAP4430_CLKACTIVITY_ABE_LP_CLK_SHIFT                   (1 << 9)
+#define OMAP4430_CLKACTIVITY_ABE_LP_CLK_MASK                    BITFIELD(9, 9)
+
+/* Used by CM1_ABE_CLKSTCTRL */
+#define OMAP4430_CLKACTIVITY_ABE_SYSCLK_SHIFT                   (1 << 11)
+#define OMAP4430_CLKACTIVITY_ABE_SYSCLK_MASK                    BITFIELD(11, 11)
+
+/* Used by CM1_ABE_CLKSTCTRL */
+#define OMAP4430_CLKACTIVITY_ABE_X2_CLK_SHIFT                   (1 << 8)
+#define OMAP4430_CLKACTIVITY_ABE_X2_CLK_MASK                    BITFIELD(8, 8)
+
+/* Used by CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE */
+#define OMAP4430_CLKACTIVITY_ASYNC_DLL_CLK_SHIFT                (1 << 11)
+#define OMAP4430_CLKACTIVITY_ASYNC_DLL_CLK_MASK                 BITFIELD(11, 11)
+
+/* Used by CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE */
+#define OMAP4430_CLKACTIVITY_ASYNC_PHY1_CLK_SHIFT               (1 << 12)
+#define OMAP4430_CLKACTIVITY_ASYNC_PHY1_CLK_MASK                BITFIELD(12, 12)
+
+/* Used by CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE */
+#define OMAP4430_CLKACTIVITY_ASYNC_PHY2_CLK_SHIFT               (1 << 13)
+#define OMAP4430_CLKACTIVITY_ASYNC_PHY2_CLK_MASK                BITFIELD(13, 13)
+
+/* Used by CM_CAM_CLKSTCTRL */
+#define OMAP4430_CLKACTIVITY_CAM_PHY_CTRL_GCLK_SHIFT            (1 << 9)
+#define OMAP4430_CLKACTIVITY_CAM_PHY_CTRL_GCLK_MASK             BITFIELD(9, 9)
+
+/* Used by CM_EMU_CLKSTCTRL */
+#define OMAP4430_CLKACTIVITY_CORE_DPLL_EMU_CLK_SHIFT            (1 << 9)
+#define OMAP4430_CLKACTIVITY_CORE_DPLL_EMU_CLK_MASK             BITFIELD(9, 9)
+
+/* Used by CM_CEFUSE_CLKSTCTRL */
+#define OMAP4430_CLKACTIVITY_CUST_EFUSE_SYS_CLK_SHIFT           (1 << 9)
+#define OMAP4430_CLKACTIVITY_CUST_EFUSE_SYS_CLK_MASK            BITFIELD(9, 9)
+
+/* Used by CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE */
+#define OMAP4430_CLKACTIVITY_DLL_CLK_SHIFT                      (1 << 9)
+#define OMAP4430_CLKACTIVITY_DLL_CLK_MASK                       BITFIELD(9, 9)
+
+/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
+#define OMAP4430_CLKACTIVITY_DMT10_GFCLK_SHIFT                  (1 << 9)
+#define OMAP4430_CLKACTIVITY_DMT10_GFCLK_MASK                   BITFIELD(9, 9)
+
+/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
+#define OMAP4430_CLKACTIVITY_DMT11_GFCLK_SHIFT                  (1 << 10)
+#define OMAP4430_CLKACTIVITY_DMT11_GFCLK_MASK                   BITFIELD(10, 10)
+
+/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
+#define OMAP4430_CLKACTIVITY_DMT2_GFCLK_SHIFT                   (1 << 11)
+#define OMAP4430_CLKACTIVITY_DMT2_GFCLK_MASK                    BITFIELD(11, 11)
+
+/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
+#define OMAP4430_CLKACTIVITY_DMT3_GFCLK_SHIFT                   (1 << 12)
+#define OMAP4430_CLKACTIVITY_DMT3_GFCLK_MASK                    BITFIELD(12, 12)
+
+/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
+#define OMAP4430_CLKACTIVITY_DMT4_GFCLK_SHIFT                   (1 << 13)
+#define OMAP4430_CLKACTIVITY_DMT4_GFCLK_MASK                    BITFIELD(13, 13)
+
+/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
+#define OMAP4430_CLKACTIVITY_DMT9_GFCLK_SHIFT                   (1 << 14)
+#define OMAP4430_CLKACTIVITY_DMT9_GFCLK_MASK                    BITFIELD(14, 14)
+
+/* Used by CM_DSS_CLKSTCTRL */
+#define OMAP4430_CLKACTIVITY_DSS_ALWON_SYS_CLK_SHIFT            (1 << 10)
+#define OMAP4430_CLKACTIVITY_DSS_ALWON_SYS_CLK_MASK             BITFIELD(10, 10)
+
+/* Used by CM_DSS_CLKSTCTRL */
+#define OMAP4430_CLKACTIVITY_DSS_FCLK_SHIFT                     (1 << 9)
+#define OMAP4430_CLKACTIVITY_DSS_FCLK_MASK                      BITFIELD(9, 9)
+
+/* Used by CM_DUCATI_CLKSTCTRL */
+#define OMAP4430_CLKACTIVITY_DUCATI_GCLK_SHIFT                  (1 << 8)
+#define OMAP4430_CLKACTIVITY_DUCATI_GCLK_MASK                   BITFIELD(8, 8)
+
+/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
+#define OMAP4430_CLKACTIVITY_EMAC_50MHZ_CLK_SHIFT               (1 << 10)
+#define OMAP4430_CLKACTIVITY_EMAC_50MHZ_CLK_MASK                BITFIELD(10, 10)
+
+/* Used by CM_EMU_CLKSTCTRL */
+#define OMAP4430_CLKACTIVITY_EMU_SYS_CLK_SHIFT                  (1 << 8)
+#define OMAP4430_CLKACTIVITY_EMU_SYS_CLK_MASK                   BITFIELD(8, 8)
+
+/* Used by CM_CAM_CLKSTCTRL */
+#define OMAP4430_CLKACTIVITY_FDIF_GFCLK_SHIFT                   (1 << 10)
+#define OMAP4430_CLKACTIVITY_FDIF_GFCLK_MASK                    BITFIELD(10, 10)
+
+/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
+#define OMAP4430_CLKACTIVITY_FUNC_12M_GFCLK_SHIFT               (1 << 15)
+#define OMAP4430_CLKACTIVITY_FUNC_12M_GFCLK_MASK                BITFIELD(15, 15)
+
+/* Used by CM1_ABE_CLKSTCTRL */
+#define OMAP4430_CLKACTIVITY_FUNC_24M_GFCLK_SHIFT               (1 << 10)
+#define OMAP4430_CLKACTIVITY_FUNC_24M_GFCLK_MASK                BITFIELD(10, 10)
+
+/* Used by CM_DSS_CLKSTCTRL */
+#define OMAP4430_CLKACTIVITY_HDMI_PHY_48MHZ_GFCLK_SHIFT         (1 << 11)
+#define OMAP4430_CLKACTIVITY_HDMI_PHY_48MHZ_GFCLK_MASK          BITFIELD(11, 11)
+
+/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
+#define OMAP4430_CLKACTIVITY_HSIC_P1_480M_GFCLK_SHIFT           (1 << 20)
+#define OMAP4430_CLKACTIVITY_HSIC_P1_480M_GFCLK_MASK            BITFIELD(20, 20)
+
+/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
+#define OMAP4430_CLKACTIVITY_HSIC_P1_GFCLK_SHIFT                (1 << 26)
+#define OMAP4430_CLKACTIVITY_HSIC_P1_GFCLK_MASK                 BITFIELD(26, 26)
+
+/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
+#define OMAP4430_CLKACTIVITY_HSIC_P2_480M_GFCLK_SHIFT           (1 << 21)
+#define OMAP4430_CLKACTIVITY_HSIC_P2_480M_GFCLK_MASK            BITFIELD(21, 21)
+
+/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
+#define OMAP4430_CLKACTIVITY_HSIC_P2_GFCLK_SHIFT                (1 << 27)
+#define OMAP4430_CLKACTIVITY_HSIC_P2_GFCLK_MASK                 BITFIELD(27, 27)
+
+/* Used by CM_L3INIT_CLKSTCTRL */
+#define OMAP4430_CLKACTIVITY_INIT_32K_GFCLK_SHIFT               (1 << 31)
+#define OMAP4430_CLKACTIVITY_INIT_32K_GFCLK_MASK                BITFIELD(31, 31)
+
+/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
+#define OMAP4430_CLKACTIVITY_INIT_48MC_GFCLK_SHIFT              (1 << 13)
+#define OMAP4430_CLKACTIVITY_INIT_48MC_GFCLK_MASK               BITFIELD(13, 13)
+
+/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
+#define OMAP4430_CLKACTIVITY_INIT_48M_GFCLK_SHIFT               (1 << 12)
+#define OMAP4430_CLKACTIVITY_INIT_48M_GFCLK_MASK                BITFIELD(12, 12)
+
+/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
+#define OMAP4430_CLKACTIVITY_INIT_60M_P1_GFCLK_SHIFT            (1 << 28)
+#define OMAP4430_CLKACTIVITY_INIT_60M_P1_GFCLK_MASK             BITFIELD(28, 28)
+
+/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
+#define OMAP4430_CLKACTIVITY_INIT_60M_P2_GFCLK_SHIFT            (1 << 29)
+#define OMAP4430_CLKACTIVITY_INIT_60M_P2_GFCLK_MASK             BITFIELD(29, 29)
+
+/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
+#define OMAP4430_CLKACTIVITY_INIT_96M_GFCLK_SHIFT               (1 << 11)
+#define OMAP4430_CLKACTIVITY_INIT_96M_GFCLK_MASK                BITFIELD(11, 11)
+
+/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
+#define OMAP4430_CLKACTIVITY_INIT_HSI_GFCLK_SHIFT               (1 << 16)
+#define OMAP4430_CLKACTIVITY_INIT_HSI_GFCLK_MASK                BITFIELD(16, 16)
+
+/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
+#define OMAP4430_CLKACTIVITY_INIT_HSMMC1_GFCLK_SHIFT            (1 << 17)
+#define OMAP4430_CLKACTIVITY_INIT_HSMMC1_GFCLK_MASK             BITFIELD(17, 17)
+
+/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
+#define OMAP4430_CLKACTIVITY_INIT_HSMMC2_GFCLK_SHIFT            (1 << 18)
+#define OMAP4430_CLKACTIVITY_INIT_HSMMC2_GFCLK_MASK             BITFIELD(18, 18)
+
+/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
+#define OMAP4430_CLKACTIVITY_INIT_HSMMC6_GFCLK_SHIFT            (1 << 19)
+#define OMAP4430_CLKACTIVITY_INIT_HSMMC6_GFCLK_MASK             BITFIELD(19, 19)
+
+/* Used by CM_CAM_CLKSTCTRL */
+#define OMAP4430_CLKACTIVITY_ISS_GCLK_SHIFT                     (1 << 8)
+#define OMAP4430_CLKACTIVITY_ISS_GCLK_MASK                      BITFIELD(8, 8)
+
+/* Used by CM_IVAHD_CLKSTCTRL */
+#define OMAP4430_CLKACTIVITY_IVAHD_ROOT_CLK_SHIFT               (1 << 8)
+#define OMAP4430_CLKACTIVITY_IVAHD_ROOT_CLK_MASK                BITFIELD(8, 8)
+
+/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
+#define OMAP4430_CLKACTIVITY_L3INIT_DPLL_ALWON_CLK_SHIFT        (1 << 14)
+#define OMAP4430_CLKACTIVITY_L3INIT_DPLL_ALWON_CLK_MASK         BITFIELD(14, 14)
+
+/* Used by CM_L3_1_CLKSTCTRL, CM_L3_1_CLKSTCTRL_RESTORE */
+#define OMAP4430_CLKACTIVITY_L3_1_GICLK_SHIFT                   (1 << 8)
+#define OMAP4430_CLKACTIVITY_L3_1_GICLK_MASK                    BITFIELD(8, 8)
+
+/* Used by CM_L3_2_CLKSTCTRL, CM_L3_2_CLKSTCTRL_RESTORE */
+#define OMAP4430_CLKACTIVITY_L3_2_GICLK_SHIFT                   (1 << 8)
+#define OMAP4430_CLKACTIVITY_L3_2_GICLK_MASK                    BITFIELD(8, 8)
+
+/* Used by CM_D2D_CLKSTCTRL */
+#define OMAP4430_CLKACTIVITY_L3_D2D_GICLK_SHIFT                 (1 << 8)
+#define OMAP4430_CLKACTIVITY_L3_D2D_GICLK_MASK                  BITFIELD(8, 8)
+
+/* Used by CM_SDMA_CLKSTCTRL */
+#define OMAP4430_CLKACTIVITY_L3_DMA_GICLK_SHIFT                 (1 << 8)
+#define OMAP4430_CLKACTIVITY_L3_DMA_GICLK_MASK                  BITFIELD(8, 8)
+
+/* Used by CM_DSS_CLKSTCTRL */
+#define OMAP4430_CLKACTIVITY_L3_DSS_GICLK_SHIFT                 (1 << 8)
+#define OMAP4430_CLKACTIVITY_L3_DSS_GICLK_MASK                  BITFIELD(8, 8)
+
+/* Used by CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE */
+#define OMAP4430_CLKACTIVITY_L3_EMIF_GICLK_SHIFT                (1 << 8)
+#define OMAP4430_CLKACTIVITY_L3_EMIF_GICLK_MASK                 BITFIELD(8, 8)
+
+/* Used by CM_GFX_CLKSTCTRL */
+#define OMAP4430_CLKACTIVITY_L3_GFX_GICLK_SHIFT                 (1 << 8)
+#define OMAP4430_CLKACTIVITY_L3_GFX_GICLK_MASK                  BITFIELD(8, 8)
+
+/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
+#define OMAP4430_CLKACTIVITY_L3_INIT_GICLK_SHIFT                (1 << 8)
+#define OMAP4430_CLKACTIVITY_L3_INIT_GICLK_MASK                 BITFIELD(8, 8)
+
+/* Used by CM_L3INSTR_CLKSTCTRL */
+#define OMAP4430_CLKACTIVITY_L3_INSTR_GICLK_SHIFT               (1 << 8)
+#define OMAP4430_CLKACTIVITY_L3_INSTR_GICLK_MASK                BITFIELD(8, 8)
+
+/* Used by CM_L4SEC_CLKSTCTRL */
+#define OMAP4430_CLKACTIVITY_L3_SECURE_GICLK_SHIFT              (1 << 8)
+#define OMAP4430_CLKACTIVITY_L3_SECURE_GICLK_MASK               BITFIELD(8, 8)
+
+/* Used by CM_ALWON_CLKSTCTRL */
+#define OMAP4430_CLKACTIVITY_L4_AO_ICLK_SHIFT                   (1 << 8)
+#define OMAP4430_CLKACTIVITY_L4_AO_ICLK_MASK                    BITFIELD(8, 8)
+
+/* Used by CM_CEFUSE_CLKSTCTRL */
+#define OMAP4430_CLKACTIVITY_L4_CEFUSE_GICLK_SHIFT              (1 << 8)
+#define OMAP4430_CLKACTIVITY_L4_CEFUSE_GICLK_MASK               BITFIELD(8, 8)
+
+/* Used by CM_L4CFG_CLKSTCTRL, CM_L4CFG_CLKSTCTRL_RESTORE */
+#define OMAP4430_CLKACTIVITY_L4_CFG_GICLK_SHIFT                 (1 << 8)
+#define OMAP4430_CLKACTIVITY_L4_CFG_GICLK_MASK                  BITFIELD(8, 8)
+
+/* Used by CM_D2D_CLKSTCTRL */
+#define OMAP4430_CLKACTIVITY_L4_D2D_GICLK_SHIFT                 (1 << 9)
+#define OMAP4430_CLKACTIVITY_L4_D2D_GICLK_MASK                  BITFIELD(9, 9)
+
+/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
+#define OMAP4430_CLKACTIVITY_L4_INIT_GICLK_SHIFT                (1 << 9)
+#define OMAP4430_CLKACTIVITY_L4_INIT_GICLK_MASK                 BITFIELD(9, 9)
+
+/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
+#define OMAP4430_CLKACTIVITY_L4_PER_GICLK_SHIFT                 (1 << 8)
+#define OMAP4430_CLKACTIVITY_L4_PER_GICLK_MASK                  BITFIELD(8, 8)
+
+/* Used by CM_L4SEC_CLKSTCTRL */
+#define OMAP4430_CLKACTIVITY_L4_SECURE_GICLK_SHIFT              (1 << 9)
+#define OMAP4430_CLKACTIVITY_L4_SECURE_GICLK_MASK               BITFIELD(9, 9)
+
+/* Used by CM_WKUP_CLKSTCTRL */
+#define OMAP4430_CLKACTIVITY_L4_WKUP_GICLK_SHIFT                (1 << 12)
+#define OMAP4430_CLKACTIVITY_L4_WKUP_GICLK_MASK                 BITFIELD(12, 12)
+
+/* Used by CM_MPU_CLKSTCTRL, CM_MPU_CLKSTCTRL_RESTORE */
+#define OMAP4430_CLKACTIVITY_MPU_DPLL_CLK_SHIFT                 (1 << 8)
+#define OMAP4430_CLKACTIVITY_MPU_DPLL_CLK_MASK                  BITFIELD(8, 8)
+
+/* Used by CM1_ABE_CLKSTCTRL */
+#define OMAP4430_CLKACTIVITY_OCP_ABE_GICLK_SHIFT                (1 << 9)
+#define OMAP4430_CLKACTIVITY_OCP_ABE_GICLK_MASK                 BITFIELD(9, 9)
+
+/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
+#define OMAP4430_CLKACTIVITY_PER_24MC_GFCLK_SHIFT               (1 << 16)
+#define OMAP4430_CLKACTIVITY_PER_24MC_GFCLK_MASK                BITFIELD(16, 16)
+
+/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
+#define OMAP4430_CLKACTIVITY_PER_32K_GFCLK_SHIFT                (1 << 17)
+#define OMAP4430_CLKACTIVITY_PER_32K_GFCLK_MASK                 BITFIELD(17, 17)
+
+/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
+#define OMAP4430_CLKACTIVITY_PER_48M_GFCLK_SHIFT                (1 << 18)
+#define OMAP4430_CLKACTIVITY_PER_48M_GFCLK_MASK                 BITFIELD(18, 18)
+
+/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
+#define OMAP4430_CLKACTIVITY_PER_96M_GFCLK_SHIFT                (1 << 19)
+#define OMAP4430_CLKACTIVITY_PER_96M_GFCLK_MASK                 BITFIELD(19, 19)
+
+/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
+#define OMAP4430_CLKACTIVITY_PER_ABE_24M_GFCLK_SHIFT            (1 << 25)
+#define OMAP4430_CLKACTIVITY_PER_ABE_24M_GFCLK_MASK             BITFIELD(25, 25)
+
+/* Used by CM_EMU_CLKSTCTRL */
+#define OMAP4430_CLKACTIVITY_PER_DPLL_EMU_CLK_SHIFT             (1 << 10)
+#define OMAP4430_CLKACTIVITY_PER_DPLL_EMU_CLK_MASK              BITFIELD(10, 10)
+
+/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
+#define OMAP4430_CLKACTIVITY_PER_MCASP2_GFCLK_SHIFT             (1 << 20)
+#define OMAP4430_CLKACTIVITY_PER_MCASP2_GFCLK_MASK              BITFIELD(20, 20)
+
+/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
+#define OMAP4430_CLKACTIVITY_PER_MCASP3_GFCLK_SHIFT             (1 << 21)
+#define OMAP4430_CLKACTIVITY_PER_MCASP3_GFCLK_MASK              BITFIELD(21, 21)
+
+/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
+#define OMAP4430_CLKACTIVITY_PER_MCBSP4_GFCLK_SHIFT             (1 << 22)
+#define OMAP4430_CLKACTIVITY_PER_MCBSP4_GFCLK_MASK              BITFIELD(22, 22)
+
+/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
+#define OMAP4430_CLKACTIVITY_PER_SYS_GFCLK_SHIFT                (1 << 24)
+#define OMAP4430_CLKACTIVITY_PER_SYS_GFCLK_MASK                 BITFIELD(24, 24)
+
+/* Used by CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE */
+#define OMAP4430_CLKACTIVITY_PHY_ROOT_CLK_SHIFT                 (1 << 10)
+#define OMAP4430_CLKACTIVITY_PHY_ROOT_CLK_MASK                  BITFIELD(10, 10)
+
+/* Used by CM_GFX_CLKSTCTRL */
+#define OMAP4430_CLKACTIVITY_SGX_GFCLK_SHIFT                    (1 << 9)
+#define OMAP4430_CLKACTIVITY_SGX_GFCLK_MASK                     BITFIELD(9, 9)
+
+/* Used by CM_ALWON_CLKSTCTRL */
+#define OMAP4430_CLKACTIVITY_SR_CORE_SYSCLK_SHIFT               (1 << 11)
+#define OMAP4430_CLKACTIVITY_SR_CORE_SYSCLK_MASK                BITFIELD(11, 11)
+
+/* Used by CM_ALWON_CLKSTCTRL */
+#define OMAP4430_CLKACTIVITY_SR_IVA_SYSCLK_SHIFT                (1 << 10)
+#define OMAP4430_CLKACTIVITY_SR_IVA_SYSCLK_MASK                 BITFIELD(10, 10)
+
+/* Used by CM_ALWON_CLKSTCTRL */
+#define OMAP4430_CLKACTIVITY_SR_MPU_SYSCLK_SHIFT                (1 << 9)
+#define OMAP4430_CLKACTIVITY_SR_MPU_SYSCLK_MASK                 BITFIELD(9, 9)
+
+/* Used by CM_WKUP_CLKSTCTRL */
+#define OMAP4430_CLKACTIVITY_SYS_CLK_SHIFT                      (1 << 8)
+#define OMAP4430_CLKACTIVITY_SYS_CLK_MASK                       BITFIELD(8, 8)
+
+/* Used by CM_TESLA_CLKSTCTRL */
+#define OMAP4430_CLKACTIVITY_TESLA_ROOT_CLK_SHIFT               (1 << 8)
+#define OMAP4430_CLKACTIVITY_TESLA_ROOT_CLK_MASK                BITFIELD(8, 8)
+
+/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
+#define OMAP4430_CLKACTIVITY_TLL_CH0_GFCLK_SHIFT                (1 << 22)
+#define OMAP4430_CLKACTIVITY_TLL_CH0_GFCLK_MASK                 BITFIELD(22, 22)
+
+/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
+#define OMAP4430_CLKACTIVITY_TLL_CH1_GFCLK_SHIFT                (1 << 23)
+#define OMAP4430_CLKACTIVITY_TLL_CH1_GFCLK_MASK                 BITFIELD(23, 23)
+
+/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
+#define OMAP4430_CLKACTIVITY_TLL_CH2_GFCLK_SHIFT                (1 << 24)
+#define OMAP4430_CLKACTIVITY_TLL_CH2_GFCLK_MASK                 BITFIELD(24, 24)
+
+/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
+#define OMAP4430_CLKACTIVITY_USB_DPLL_HS_CLK_SHIFT              (1 << 15)
+#define OMAP4430_CLKACTIVITY_USB_DPLL_HS_CLK_MASK               BITFIELD(15, 15)
+
+/* Used by CM_WKUP_CLKSTCTRL */
+#define OMAP4430_CLKACTIVITY_USIM_GFCLK_SHIFT                   (1 << 10)
+#define OMAP4430_CLKACTIVITY_USIM_GFCLK_MASK                    BITFIELD(10, 10)
+
+/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
+#define OMAP4430_CLKACTIVITY_UTMI_P3_GFCLK_SHIFT                (1 << 30)
+#define OMAP4430_CLKACTIVITY_UTMI_P3_GFCLK_MASK                 BITFIELD(30, 30)
+
+/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
+#define OMAP4430_CLKACTIVITY_UTMI_ROOT_GFCLK_SHIFT              (1 << 25)
+#define OMAP4430_CLKACTIVITY_UTMI_ROOT_GFCLK_MASK               BITFIELD(25, 25)
+
+/* Used by CM_WKUP_CLKSTCTRL */
+#define OMAP4430_CLKACTIVITY_WKUP_32K_GFCLK_SHIFT               (1 << 11)
+#define OMAP4430_CLKACTIVITY_WKUP_32K_GFCLK_MASK                BITFIELD(11, 11)
+
+/*
+ * Used by CM_WKUP_TIMER1_CLKCTRL, CM_L4PER_DMTIMER10_CLKCTRL,
+ * CM_L4PER_DMTIMER11_CLKCTRL, CM_L4PER_DMTIMER2_CLKCTRL,
+ * CM_L4PER_DMTIMER3_CLKCTRL, CM_L4PER_DMTIMER4_CLKCTRL,
+ * CM_L4PER_DMTIMER9_CLKCTRL, CM_L4PER_MCASP2_CLKCTRL, CM_L4PER_MCASP3_CLKCTRL,
+ * CM_L3INIT_MMC1_CLKCTRL, CM_L3INIT_MMC2_CLKCTRL, CM_L3INIT_MMC6_CLKCTRL,
+ * CM1_ABE_TIMER5_CLKCTRL, CM1_ABE_TIMER6_CLKCTRL, CM1_ABE_TIMER7_CLKCTRL,
+ * CM1_ABE_TIMER8_CLKCTRL
+ */
+#define OMAP4430_CLKSEL_SHIFT                                   (1 << 24)
+#define OMAP4430_CLKSEL_MASK                                    BITFIELD(24, 24)
+
+/*
+ * Renamed from CLKSEL Used by CM_ABE_DSS_SYS_CLKSEL, CM_ABE_PLL_REF_CLKSEL,
+ * CM_DPLL_SYS_REF_CLKSEL, CM_L4_WKUP_CLKSEL, CM_CLKSEL_DUCATI_ISS_ROOT,
+ * CM_CLKSEL_USB_60MHZ
+ */
+#define OMAP4430_CLKSEL_0_0_SHIFT                               (1 << 0)
+#define OMAP4430_CLKSEL_0_0_MASK                                BITFIELD(0, 0)
+
+/* Renamed from CLKSEL Used by CM_BYPCLK_DPLL_IVA, CM_BYPCLK_DPLL_MPU */
+#define OMAP4430_CLKSEL_0_1_SHIFT                               (1 << 0)
+#define OMAP4430_CLKSEL_0_1_MASK                                BITFIELD(0, 1)
+
+/* Renamed from CLKSEL Used by CM_L3INIT_HSI_CLKCTRL */
+#define OMAP4430_CLKSEL_24_25_SHIFT                             (1 << 24)
+#define OMAP4430_CLKSEL_24_25_MASK                              BITFIELD(24, 25)
+
+/* Used by CM_L3INIT_USB_OTG_CLKCTRL */
+#define OMAP4430_CLKSEL_60M_SHIFT                               (1 << 24)
+#define OMAP4430_CLKSEL_60M_MASK                                BITFIELD(24, 24)
+
+/* Used by CM1_ABE_AESS_CLKCTRL */
+#define OMAP4430_CLKSEL_AESS_FCLK_SHIFT                         (1 << 24)
+#define OMAP4430_CLKSEL_AESS_FCLK_MASK                          BITFIELD(24, 24)
+
+/* Used by CM_CLKSEL_CORE_RESTORE, CM_CLKSEL_CORE */
+#define OMAP4430_CLKSEL_CORE_SHIFT                              (1 << 0)
+#define OMAP4430_CLKSEL_CORE_MASK                               BITFIELD(0, 0)
+
+/* Renamed from CLKSEL_CORE Used by CM_SHADOW_FREQ_CONFIG2 */
+#define OMAP4430_CLKSEL_CORE_1_1_SHIFT                          (1 << 1)
+#define OMAP4430_CLKSEL_CORE_1_1_MASK                           BITFIELD(1, 1)
+
+/* Used by CM_WKUP_USIM_CLKCTRL */
+#define OMAP4430_CLKSEL_DIV_SHIFT                               (1 << 24)
+#define OMAP4430_CLKSEL_DIV_MASK                                BITFIELD(24, 24)
+
+/* Used by CM_CAM_FDIF_CLKCTRL */
+#define OMAP4430_CLKSEL_FCLK_SHIFT                              (1 << 24)
+#define OMAP4430_CLKSEL_FCLK_MASK                               BITFIELD(24, 25)
+
+/* Used by CM_L4PER_MCBSP4_CLKCTRL */
+#define OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT                   (1 << 25)
+#define OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK                    BITFIELD(25, 25)
+
+/*
+ * Renamed from CLKSEL_INTERNAL_SOURCE Used by CM1_ABE_DMIC_CLKCTRL,
+ * CM1_ABE_MCASP_CLKCTRL, CM1_ABE_MCBSP1_CLKCTRL, CM1_ABE_MCBSP2_CLKCTRL,
+ * CM1_ABE_MCBSP3_CLKCTRL
+ */
+#define OMAP4430_CLKSEL_INTERNAL_SOURCE_CM1_ABE_DMIC_SHIFT      (1 << 26)
+#define OMAP4430_CLKSEL_INTERNAL_SOURCE_CM1_ABE_DMIC_MASK       BITFIELD(26, 27)
+
+/* Used by CM_CLKSEL_CORE_RESTORE, CM_CLKSEL_CORE */
+#define OMAP4430_CLKSEL_L3_SHIFT                                (1 << 4)
+#define OMAP4430_CLKSEL_L3_MASK                                 BITFIELD(4, 4)
+
+/* Renamed from CLKSEL_L3 Used by CM_SHADOW_FREQ_CONFIG2 */
+#define OMAP4430_CLKSEL_L3_SHADOW_SHIFT                         (1 << 2)
+#define OMAP4430_CLKSEL_L3_SHADOW_MASK                          BITFIELD(2, 2)
+
+/* Used by CM_CLKSEL_CORE_RESTORE, CM_CLKSEL_CORE */
+#define OMAP4430_CLKSEL_L4_SHIFT                                (1 << 8)
+#define OMAP4430_CLKSEL_L4_MASK                                 BITFIELD(8, 8)
+
+/* Used by CM_CLKSEL_ABE */
+#define OMAP4430_CLKSEL_OPP_SHIFT                               (1 << 0)
+#define OMAP4430_CLKSEL_OPP_MASK                                BITFIELD(0, 1)
+
+/* Used by CM_GFX_GFX_CLKCTRL */
+#define OMAP4430_CLKSEL_PER_192M_SHIFT                          (1 << 25)
+#define OMAP4430_CLKSEL_PER_192M_MASK                           BITFIELD(25, 26)
+
+/* Used by CM_EMU_DEBUGSS_CLKCTRL */
+#define OMAP4430_CLKSEL_PMD_STM_CLK_SHIFT                       (1 << 27)
+#define OMAP4430_CLKSEL_PMD_STM_CLK_MASK                        BITFIELD(27, 29)
+
+/* Used by CM_EMU_DEBUGSS_CLKCTRL */
+#define OMAP4430_CLKSEL_PMD_TRACE_CLK_SHIFT                     (1 << 24)
+#define OMAP4430_CLKSEL_PMD_TRACE_CLK_MASK                      BITFIELD(24, 26)
+
+/* Used by CM_GFX_GFX_CLKCTRL */
+#define OMAP4430_CLKSEL_SGX_FCLK_SHIFT                          (1 << 24)
+#define OMAP4430_CLKSEL_SGX_FCLK_MASK                           BITFIELD(24, 24)
+
+/*
+ * Used by CM1_ABE_DMIC_CLKCTRL, CM1_ABE_MCASP_CLKCTRL, CM1_ABE_MCBSP1_CLKCTRL,
+ * CM1_ABE_MCBSP2_CLKCTRL, CM1_ABE_MCBSP3_CLKCTRL
+ */
+#define OMAP4430_CLKSEL_SOURCE_SHIFT                            (1 << 24)
+#define OMAP4430_CLKSEL_SOURCE_MASK                             BITFIELD(24, 25)
+
+/* Renamed from CLKSEL_SOURCE Used by CM_L4PER_MCBSP4_CLKCTRL */
+#define OMAP4430_CLKSEL_SOURCE_24_24_SHIFT                      (1 << 24)
+#define OMAP4430_CLKSEL_SOURCE_24_24_MASK                       BITFIELD(24, 24)
+
+/* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */
+#define OMAP4430_CLKSEL_UTMI_P1_SHIFT                           (1 << 24)
+#define OMAP4430_CLKSEL_UTMI_P1_MASK                            BITFIELD(24, 24)
+
+/* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */
+#define OMAP4430_CLKSEL_UTMI_P2_SHIFT                           (1 << 25)
+#define OMAP4430_CLKSEL_UTMI_P2_MASK                            BITFIELD(25, 25)
+
+/*
+ * Used by CM_WKUP_CLKSTCTRL, CM_EMU_CLKSTCTRL, CM_D2D_CLKSTCTRL,
+ * CM_DUCATI_CLKSTCTRL, CM_L3INSTR_CLKSTCTRL, CM_L3_1_CLKSTCTRL,
+ * CM_L3_2_CLKSTCTRL, CM_L4CFG_CLKSTCTRL, CM_MEMIF_CLKSTCTRL,
+ * CM_SDMA_CLKSTCTRL, CM_GFX_CLKSTCTRL, CM_L4PER_CLKSTCTRL, CM_L4SEC_CLKSTCTRL,
+ * CM_L3INIT_CLKSTCTRL, CM_CAM_CLKSTCTRL, CM_CEFUSE_CLKSTCTRL,
+ * CM_L3INIT_CLKSTCTRL_RESTORE, CM_L3_1_CLKSTCTRL_RESTORE,
+ * CM_L3_2_CLKSTCTRL_RESTORE, CM_L4CFG_CLKSTCTRL_RESTORE,
+ * CM_L4PER_CLKSTCTRL_RESTORE, CM_MEMIF_CLKSTCTRL_RESTORE, CM_ALWON_CLKSTCTRL,
+ * CM_IVAHD_CLKSTCTRL, CM_DSS_CLKSTCTRL, CM_MPU_CLKSTCTRL, CM_TESLA_CLKSTCTRL,
+ * CM1_ABE_CLKSTCTRL, CM_MPU_CLKSTCTRL_RESTORE
+ */
+#define OMAP4430_CLKTRCTRL_SHIFT                                (1 << 0)
+#define OMAP4430_CLKTRCTRL_MASK                                 BITFIELD(0, 1)
+
+/* Used by CM_EMU_OVERRIDE_DPLL_CORE */
+#define OMAP4430_CORE_DPLL_EMU_DIV_SHIFT                        (1 << 0)
+#define OMAP4430_CORE_DPLL_EMU_DIV_MASK                         BITFIELD(0, 6)
+
+/* Used by CM_EMU_OVERRIDE_DPLL_CORE */
+#define OMAP4430_CORE_DPLL_EMU_MULT_SHIFT                       (1 << 8)
+#define OMAP4430_CORE_DPLL_EMU_MULT_MASK                        BITFIELD(8, 18)
+
+/* Used by CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP */
+#define OMAP4430_D2D_DYNDEP_SHIFT                               (1 << 18)
+#define OMAP4430_D2D_DYNDEP_MASK                                BITFIELD(18, 18)
+
+/* Used by CM_MPU_STATICDEP */
+#define OMAP4430_D2D_STATDEP_SHIFT                              (1 << 18)
+#define OMAP4430_D2D_STATDEP_MASK                               BITFIELD(18, 18)
+
+/*
+ * Used by CM_SSC_DELTAMSTEP_DPLL_PER, CM_SSC_DELTAMSTEP_DPLL_UNIPRO,
+ * CM_SSC_DELTAMSTEP_DPLL_USB, CM_SSC_DELTAMSTEP_DPLL_CORE_RESTORE,
+ * CM_SSC_DELTAMSTEP_DPLL_ABE, CM_SSC_DELTAMSTEP_DPLL_CORE,
+ * CM_SSC_DELTAMSTEP_DPLL_DDRPHY, CM_SSC_DELTAMSTEP_DPLL_IVA,
+ * CM_SSC_DELTAMSTEP_DPLL_MPU
+ */
+#define OMAP4430_DELTAMSTEP_SHIFT                               (1 << 0)
+#define OMAP4430_DELTAMSTEP_MASK                                BITFIELD(0, 19)
+
+/* Used by CM_SHADOW_FREQ_CONFIG1_RESTORE, CM_SHADOW_FREQ_CONFIG1 */
+#define OMAP4430_DLL_OVERRIDE_SHIFT                             (1 << 2)
+#define OMAP4430_DLL_OVERRIDE_MASK                              BITFIELD(2, 2)
+
+/* Renamed from DLL_OVERRIDE Used by CM_DLL_CTRL */
+#define OMAP4430_DLL_OVERRIDE_0_0_SHIFT                         (1 << 0)
+#define OMAP4430_DLL_OVERRIDE_0_0_MASK                          BITFIELD(0, 0)
+
+/* Used by CM_SHADOW_FREQ_CONFIG1_RESTORE, CM_SHADOW_FREQ_CONFIG1 */
+#define OMAP4430_DLL_RESET_SHIFT                                (1 << 3)
+#define OMAP4430_DLL_RESET_MASK                                 BITFIELD(3, 3)
+
+/*
+ * Used by CM_CLKSEL_DPLL_PER, CM_CLKSEL_DPLL_UNIPRO, CM_CLKSEL_DPLL_USB,
+ * CM_CLKSEL_DPLL_CORE_RESTORE, CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE,
+ * CM_CLKSEL_DPLL_DDRPHY, CM_CLKSEL_DPLL_IVA, CM_CLKSEL_DPLL_MPU
+ */
+#define OMAP4430_DPLL_BYP_CLKSEL_SHIFT                          (1 << 23)
+#define OMAP4430_DPLL_BYP_CLKSEL_MASK                           BITFIELD(23, 23)
+
+/* Used by CM_CLKDCOLDO_DPLL_USB */
+#define OMAP4430_DPLL_CLKDCOLDO_GATE_CTRL_SHIFT                 (1 << 8)
+#define OMAP4430_DPLL_CLKDCOLDO_GATE_CTRL_MASK                  BITFIELD(8, 8)
+
+/* Used by CM_CLKSEL_DPLL_CORE_RESTORE, CM_CLKSEL_DPLL_CORE */
+#define OMAP4430_DPLL_CLKOUTHIF_CLKSEL_SHIFT                    (1 << 20)
+#define OMAP4430_DPLL_CLKOUTHIF_CLKSEL_MASK                     BITFIELD(20, 20)
+
+/*
+ * Used by CM_DIV_M3_DPLL_PER, CM_DIV_M3_DPLL_CORE_RESTORE, CM_DIV_M3_DPLL_ABE,
+ * CM_DIV_M3_DPLL_CORE
+ */
+#define OMAP4430_DPLL_CLKOUTHIF_DIV_SHIFT                       (1 << 0)
+#define OMAP4430_DPLL_CLKOUTHIF_DIV_MASK                        BITFIELD(0, 4)
+
+/*
+ * Used by CM_DIV_M3_DPLL_PER, CM_DIV_M3_DPLL_CORE_RESTORE, CM_DIV_M3_DPLL_ABE,
+ * CM_DIV_M3_DPLL_CORE
+ */
+#define OMAP4430_DPLL_CLKOUTHIF_DIVCHACK_SHIFT                  (1 << 5)
+#define OMAP4430_DPLL_CLKOUTHIF_DIVCHACK_MASK                   BITFIELD(5, 5)
+
+/*
+ * Used by CM_DIV_M3_DPLL_PER, CM_DIV_M3_DPLL_CORE_RESTORE, CM_DIV_M3_DPLL_ABE,
+ * CM_DIV_M3_DPLL_CORE
+ */
+#define OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT                 (1 << 8)
+#define OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_MASK                  BITFIELD(8, 8)
+
+/* Used by CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO, CM_DIV_M2_DPLL_ABE */
+#define OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_SHIFT                  (1 << 10)
+#define OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK                   BITFIELD(10, 10)
+
+/*
+ * Used by CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO,
+ * CM_DIV_M2_DPLL_CORE_RESTORE, CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE,
+ * CM_DIV_M2_DPLL_DDRPHY, CM_DIV_M2_DPLL_MPU
+ */
+#define OMAP4430_DPLL_CLKOUT_DIV_SHIFT                          (1 << 0)
+#define OMAP4430_DPLL_CLKOUT_DIV_MASK                           BITFIELD(0, 4)
+
+/* Renamed from DPLL_CLKOUT_DIV Used by CM_DIV_M2_DPLL_USB */
+#define OMAP4430_DPLL_CLKOUT_DIV_0_6_SHIFT                      (1 << 0)
+#define OMAP4430_DPLL_CLKOUT_DIV_0_6_MASK                       BITFIELD(0, 6)
+
+/*
+ * Used by CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO,
+ * CM_DIV_M2_DPLL_CORE_RESTORE, CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE,
+ * CM_DIV_M2_DPLL_DDRPHY, CM_DIV_M2_DPLL_MPU
+ */
+#define OMAP4430_DPLL_CLKOUT_DIVCHACK_SHIFT                     (1 << 5)
+#define OMAP4430_DPLL_CLKOUT_DIVCHACK_MASK                      BITFIELD(5, 5)
+
+/* Renamed from DPLL_CLKOUT_DIVCHACK Used by CM_DIV_M2_DPLL_USB */
+#define OMAP4430_DPLL_CLKOUT_DIVCHACK_M2_USB_SHIFT              (1 << 7)
+#define OMAP4430_DPLL_CLKOUT_DIVCHACK_M2_USB_MASK               BITFIELD(7, 7)
+
+/*
+ * Used by CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_USB, CM_DIV_M2_DPLL_CORE_RESTORE,
+ * CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE, CM_DIV_M2_DPLL_DDRPHY,
+ * CM_DIV_M2_DPLL_MPU
+ */
+#define OMAP4430_DPLL_CLKOUT_GATE_CTRL_SHIFT                    (1 << 8)
+#define OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK                     BITFIELD(8, 8)
+
+/* Used by CM_SHADOW_FREQ_CONFIG1_RESTORE, CM_SHADOW_FREQ_CONFIG1 */
+#define OMAP4430_DPLL_CORE_DPLL_EN_SHIFT                        (1 << 8)
+#define OMAP4430_DPLL_CORE_DPLL_EN_MASK                         BITFIELD(8, 10)
+
+/* Used by CM_SHADOW_FREQ_CONFIG1_RESTORE, CM_SHADOW_FREQ_CONFIG1 */
+#define OMAP4430_DPLL_CORE_M2_DIV_SHIFT                         (1 << 11)
+#define OMAP4430_DPLL_CORE_M2_DIV_MASK                          BITFIELD(11, 15)
+
+/* Used by CM_SHADOW_FREQ_CONFIG2 */
+#define OMAP4430_DPLL_CORE_M5_DIV_SHIFT                         (1 << 3)
+#define OMAP4430_DPLL_CORE_M5_DIV_MASK                          BITFIELD(3, 7)
+
+/* Used by CM_SHADOW_FREQ_CONFIG1_RESTORE, CM_SHADOW_FREQ_CONFIG1 */
+#define OMAP4430_DPLL_CORE_SYS_REF_CLKSEL_SHIFT                 (1 << 1)
+#define OMAP4430_DPLL_CORE_SYS_REF_CLKSEL_MASK                  BITFIELD(1, 1)
+
+/*
+ * Used by CM_CLKSEL_DPLL_PER, CM_CLKSEL_DPLL_UNIPRO,
+ * CM_CLKSEL_DPLL_CORE_RESTORE, CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE,
+ * CM_CLKSEL_DPLL_DDRPHY, CM_CLKSEL_DPLL_IVA, CM_CLKSEL_DPLL_MPU
+ */
+#define OMAP4430_DPLL_DIV_SHIFT                                 (1 << 0)
+#define OMAP4430_DPLL_DIV_MASK                                  BITFIELD(0, 6)
+
+/* Renamed from DPLL_DIV Used by CM_CLKSEL_DPLL_USB */
+#define OMAP4430_DPLL_DIV_0_7_SHIFT                             (1 << 0)
+#define OMAP4430_DPLL_DIV_0_7_MASK                              BITFIELD(0, 7)
+
+/*
+ * Used by CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_USB,
+ * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE,
+ * CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU
+ */
+#define OMAP4430_DPLL_DRIFTGUARD_EN_SHIFT                       (1 << 8)
+#define OMAP4430_DPLL_DRIFTGUARD_EN_MASK                        BITFIELD(8, 8)
+
+/* Renamed from DPLL_DRIFTGUARD_EN Used by CM_CLKMODE_DPLL_UNIPRO */
+#define OMAP4430_DPLL_DRIFTGUARD_EN_3_3_SHIFT                   (1 << 3)
+#define OMAP4430_DPLL_DRIFTGUARD_EN_3_3_MASK                    BITFIELD(3, 3)
+
+/*
+ * Used by CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO, CM_CLKMODE_DPLL_USB,
+ * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE,
+ * CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU
+ */
+#define OMAP4430_DPLL_EN_SHIFT                                  (1 << 0)
+#define OMAP4430_DPLL_EN_MASK                                   BITFIELD(0, 2)
+
+/*
+ * Used by CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO,
+ * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE,
+ * CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU
+ */
+#define OMAP4430_DPLL_LPMODE_EN_SHIFT                           (1 << 10)
+#define OMAP4430_DPLL_LPMODE_EN_MASK                            BITFIELD(10, 10)
+
+/*
+ * Used by CM_CLKSEL_DPLL_PER, CM_CLKSEL_DPLL_UNIPRO,
+ * CM_CLKSEL_DPLL_CORE_RESTORE, CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE,
+ * CM_CLKSEL_DPLL_DDRPHY, CM_CLKSEL_DPLL_IVA, CM_CLKSEL_DPLL_MPU
+ */
+#define OMAP4430_DPLL_MULT_SHIFT                                (1 << 8)
+#define OMAP4430_DPLL_MULT_MASK                                 BITFIELD(8, 18)
+
+/* Renamed from DPLL_MULT Used by CM_CLKSEL_DPLL_USB */
+#define OMAP4430_DPLL_MULT_USB_SHIFT                            (1 << 8)
+#define OMAP4430_DPLL_MULT_USB_MASK                             BITFIELD(8, 19)
+
+/*
+ * Used by CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO,
+ * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE,
+ * CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU
+ */
+#define OMAP4430_DPLL_REGM4XEN_SHIFT                            (1 << 11)
+#define OMAP4430_DPLL_REGM4XEN_MASK                             BITFIELD(11, 11)
+
+/* Used by CM_CLKSEL_DPLL_USB */
+#define OMAP4430_DPLL_SD_DIV_SHIFT                              (1 << 24)
+#define OMAP4430_DPLL_SD_DIV_MASK                               BITFIELD(24, 31)
+
+/*
+ * Used by CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO, CM_CLKMODE_DPLL_USB,
+ * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE,
+ * CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU
+ */
+#define OMAP4430_DPLL_SSC_ACK_SHIFT                             (1 << 13)
+#define OMAP4430_DPLL_SSC_ACK_MASK                              BITFIELD(13, 13)
+
+/*
+ * Used by CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO, CM_CLKMODE_DPLL_USB,
+ * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE,
+ * CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU
+ */
+#define OMAP4430_DPLL_SSC_DOWNSPREAD_SHIFT                      (1 << 14)
+#define OMAP4430_DPLL_SSC_DOWNSPREAD_MASK                       BITFIELD(14, 14)
+
+/*
+ * Used by CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO, CM_CLKMODE_DPLL_USB,
+ * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE,
+ * CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU
+ */
+#define OMAP4430_DPLL_SSC_EN_SHIFT                              (1 << 12)
+#define OMAP4430_DPLL_SSC_EN_MASK                               BITFIELD(12, 12)
+
+/* Used by CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP, CM_L4PER_DYNAMICDEP */
+#define OMAP4430_DSS_DYNDEP_SHIFT                               (1 << 8)
+#define OMAP4430_DSS_DYNDEP_MASK                                BITFIELD(8, 8)
+
+/*
+ * Used by CM_DUCATI_STATICDEP, CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE,
+ * CM_MPU_STATICDEP
+ */
+#define OMAP4430_DSS_STATDEP_SHIFT                              (1 << 8)
+#define OMAP4430_DSS_STATDEP_MASK                               BITFIELD(8, 8)
+
+/* Used by CM_L3_2_DYNAMICDEP */
+#define OMAP4430_DUCATI_DYNDEP_SHIFT                            (1 << 0)
+#define OMAP4430_DUCATI_DYNDEP_MASK                             BITFIELD(0, 0)
+
+/* Used by CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE, CM_MPU_STATICDEP */
+#define OMAP4430_DUCATI_STATDEP_SHIFT                           (1 << 0)
+#define OMAP4430_DUCATI_STATDEP_MASK                            BITFIELD(0, 0)
+
+/* Used by CM_SHADOW_FREQ_CONFIG1_RESTORE, CM_SHADOW_FREQ_CONFIG1 */
+#define OMAP4430_FREQ_UPDATE_SHIFT                              (1 << 0)
+#define OMAP4430_FREQ_UPDATE_MASK                               BITFIELD(0, 0)
+
+/* Used by CM_L3_2_DYNAMICDEP */
+#define OMAP4430_GFX_DYNDEP_SHIFT                               (1 << 10)
+#define OMAP4430_GFX_DYNDEP_MASK                                BITFIELD(10, 10)
+
+/* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP */
+#define OMAP4430_GFX_STATDEP_SHIFT                              (1 << 10)
+#define OMAP4430_GFX_STATDEP_MASK                               BITFIELD(10, 10)
+
+/* Used by CM_SHADOW_FREQ_CONFIG2 */
+#define OMAP4430_GPMC_FREQ_UPDATE_SHIFT                         (1 << 0)
+#define OMAP4430_GPMC_FREQ_UPDATE_MASK                          BITFIELD(0, 0)
+
+/*
+ * Used by CM_DIV_M4_DPLL_PER, CM_DIV_M4_DPLL_CORE_RESTORE,
+ * CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA
+ */
+#define OMAP4430_HSDIVIDER_CLKOUT1_DIV_SHIFT                    (1 << 0)
+#define OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK                     BITFIELD(0, 4)
+
+/*
+ * Used by CM_DIV_M4_DPLL_PER, CM_DIV_M4_DPLL_CORE_RESTORE,
+ * CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA
+ */
+#define OMAP4430_HSDIVIDER_CLKOUT1_DIVCHACK_SHIFT               (1 << 5)
+#define OMAP4430_HSDIVIDER_CLKOUT1_DIVCHACK_MASK                BITFIELD(5, 5)
+
+/*
+ * Used by CM_DIV_M4_DPLL_PER, CM_DIV_M4_DPLL_CORE_RESTORE,
+ * CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA
+ */
+#define OMAP4430_HSDIVIDER_CLKOUT1_GATE_CTRL_SHIFT              (1 << 8)
+#define OMAP4430_HSDIVIDER_CLKOUT1_GATE_CTRL_MASK               BITFIELD(8, 8)
+
+/*
+ * Used by CM_DIV_M4_DPLL_PER, CM_DIV_M4_DPLL_CORE_RESTORE,
+ * CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA
+ */
+#define OMAP4430_HSDIVIDER_CLKOUT1_PWDN_SHIFT                   (1 << 12)
+#define OMAP4430_HSDIVIDER_CLKOUT1_PWDN_MASK                    BITFIELD(12, 12)
+
+/*
+ * Used by CM_DIV_M5_DPLL_PER, CM_DIV_M5_DPLL_CORE_RESTORE,
+ * CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA
+ */
+#define OMAP4430_HSDIVIDER_CLKOUT2_DIV_SHIFT                    (1 << 0)
+#define OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK                     BITFIELD(0, 4)
+
+/*
+ * Used by CM_DIV_M5_DPLL_PER, CM_DIV_M5_DPLL_CORE_RESTORE,
+ * CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA
+ */
+#define OMAP4430_HSDIVIDER_CLKOUT2_DIVCHACK_SHIFT               (1 << 5)
+#define OMAP4430_HSDIVIDER_CLKOUT2_DIVCHACK_MASK                BITFIELD(5, 5)
+
+/*
+ * Used by CM_DIV_M5_DPLL_PER, CM_DIV_M5_DPLL_CORE_RESTORE,
+ * CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA
+ */
+#define OMAP4430_HSDIVIDER_CLKOUT2_GATE_CTRL_SHIFT              (1 << 8)
+#define OMAP4430_HSDIVIDER_CLKOUT2_GATE_CTRL_MASK               BITFIELD(8, 8)
+
+/*
+ * Used by CM_DIV_M5_DPLL_PER, CM_DIV_M5_DPLL_CORE_RESTORE,
+ * CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA
+ */
+#define OMAP4430_HSDIVIDER_CLKOUT2_PWDN_SHIFT                   (1 << 12)
+#define OMAP4430_HSDIVIDER_CLKOUT2_PWDN_MASK                    BITFIELD(12, 12)
+
+/*
+ * Used by CM_DIV_M6_DPLL_PER, CM_DIV_M6_DPLL_CORE_RESTORE,
+ * CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY
+ */
+#define OMAP4430_HSDIVIDER_CLKOUT3_DIV_SHIFT                    (1 << 0)
+#define OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK                     BITFIELD(0, 4)
+
+/*
+ * Used by CM_DIV_M6_DPLL_PER, CM_DIV_M6_DPLL_CORE_RESTORE,
+ * CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY
+ */
+#define OMAP4430_HSDIVIDER_CLKOUT3_DIVCHACK_SHIFT               (1 << 5)
+#define OMAP4430_HSDIVIDER_CLKOUT3_DIVCHACK_MASK                BITFIELD(5, 5)
+
+/*
+ * Used by CM_DIV_M6_DPLL_PER, CM_DIV_M6_DPLL_CORE_RESTORE,
+ * CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY
+ */
+#define OMAP4430_HSDIVIDER_CLKOUT3_GATE_CTRL_SHIFT              (1 << 8)
+#define OMAP4430_HSDIVIDER_CLKOUT3_GATE_CTRL_MASK               BITFIELD(8, 8)
+
+/*
+ * Used by CM_DIV_M6_DPLL_PER, CM_DIV_M6_DPLL_CORE_RESTORE,
+ * CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY
+ */
+#define OMAP4430_HSDIVIDER_CLKOUT3_PWDN_SHIFT                   (1 << 12)
+#define OMAP4430_HSDIVIDER_CLKOUT3_PWDN_MASK                    BITFIELD(12, 12)
+
+/*
+ * Used by CM_DIV_M7_DPLL_PER, CM_DIV_M7_DPLL_CORE_RESTORE,
+ * CM_DIV_M7_DPLL_CORE
+ */
+#define OMAP4430_HSDIVIDER_CLKOUT4_DIV_SHIFT                    (1 << 0)
+#define OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK                     BITFIELD(0, 4)
+
+/*
+ * Used by CM_DIV_M7_DPLL_PER, CM_DIV_M7_DPLL_CORE_RESTORE,
+ * CM_DIV_M7_DPLL_CORE
+ */
+#define OMAP4430_HSDIVIDER_CLKOUT4_DIVCHACK_SHIFT               (1 << 5)
+#define OMAP4430_HSDIVIDER_CLKOUT4_DIVCHACK_MASK                BITFIELD(5, 5)
+
+/*
+ * Used by CM_DIV_M7_DPLL_PER, CM_DIV_M7_DPLL_CORE_RESTORE,
+ * CM_DIV_M7_DPLL_CORE
+ */
+#define OMAP4430_HSDIVIDER_CLKOUT4_GATE_CTRL_SHIFT              (1 << 8)
+#define OMAP4430_HSDIVIDER_CLKOUT4_GATE_CTRL_MASK               BITFIELD(8, 8)
+
+/*
+ * Used by CM_DIV_M7_DPLL_PER, CM_DIV_M7_DPLL_CORE_RESTORE,
+ * CM_DIV_M7_DPLL_CORE
+ */
+#define OMAP4430_HSDIVIDER_CLKOUT4_PWDN_SHIFT                   (1 << 12)
+#define OMAP4430_HSDIVIDER_CLKOUT4_PWDN_MASK                    BITFIELD(12, 12)
+
+/*
+ * Used by PRM_PRM_PROFILING_CLKCTRL, CM_WKUP_GPIO1_CLKCTRL,
+ * CM_WKUP_KEYBOARD_CLKCTRL, CM_WKUP_L4WKUP_CLKCTRL, CM_WKUP_RTC_CLKCTRL,
+ * CM_WKUP_SARRAM_CLKCTRL, CM_WKUP_SYNCTIMER_CLKCTRL, CM_WKUP_TIMER12_CLKCTRL,
+ * CM_WKUP_TIMER1_CLKCTRL, CM_WKUP_USIM_CLKCTRL, CM_WKUP_WDT1_CLKCTRL,
+ * CM_WKUP_WDT2_CLKCTRL, CM_EMU_DEBUGSS_CLKCTRL, CM_D2D_MODEM_ICR_CLKCTRL,
+ * CM_D2D_SAD2D_CLKCTRL, CM_D2D_SAD2D_FW_CLKCTRL, CM_DUCATI_DUCATI_CLKCTRL,
+ * CM_L3INSTR_L3_3_CLKCTRL, CM_L3INSTR_L3_INSTR_CLKCTRL,
+ * CM_L3INSTR_OCP_WP1_CLKCTRL, CM_L3_1_L3_1_CLKCTRL, CM_L3_2_GPMC_CLKCTRL,
+ * CM_L3_2_L3_2_CLKCTRL, CM_L3_2_OCMC_RAM_CLKCTRL, CM_L4CFG_HW_SEM_CLKCTRL,
+ * CM_L4CFG_L4_CFG_CLKCTRL, CM_L4CFG_MAILBOX_CLKCTRL, CM_L4CFG_SAR_ROM_CLKCTRL,
+ * CM_MEMIF_DMM_CLKCTRL, CM_MEMIF_EMIF_1_CLKCTRL, CM_MEMIF_EMIF_2_CLKCTRL,
+ * CM_MEMIF_EMIF_FW_CLKCTRL, CM_MEMIF_EMIF_H1_CLKCTRL,
+ * CM_MEMIF_EMIF_H2_CLKCTRL, CM_SDMA_SDMA_CLKCTRL, CM_GFX_GFX_CLKCTRL,
+ * CM_L4PER_ADC_CLKCTRL, CM_L4PER_DMTIMER10_CLKCTRL,
+ * CM_L4PER_DMTIMER11_CLKCTRL, CM_L4PER_DMTIMER2_CLKCTRL,
+ * CM_L4PER_DMTIMER3_CLKCTRL, CM_L4PER_DMTIMER4_CLKCTRL,
+ * CM_L4PER_DMTIMER9_CLKCTRL, CM_L4PER_ELM_CLKCTRL, CM_L4PER_GPIO2_CLKCTRL,
+ * CM_L4PER_GPIO3_CLKCTRL, CM_L4PER_GPIO4_CLKCTRL, CM_L4PER_GPIO5_CLKCTRL,
+ * CM_L4PER_GPIO6_CLKCTRL, CM_L4PER_HDQ1W_CLKCTRL, CM_L4PER_HECC1_CLKCTRL,
+ * CM_L4PER_HECC2_CLKCTRL, CM_L4PER_I2C1_CLKCTRL, CM_L4PER_I2C2_CLKCTRL,
+ * CM_L4PER_I2C3_CLKCTRL, CM_L4PER_I2C4_CLKCTRL, CM_L4PER_I2C5_CLKCTRL,
+ * CM_L4PER_L4PER_CLKCTRL, CM_L4PER_MCASP2_CLKCTRL, CM_L4PER_MCASP3_CLKCTRL,
+ * CM_L4PER_MCBSP4_CLKCTRL, CM_L4PER_MCSPI1_CLKCTRL, CM_L4PER_MCSPI2_CLKCTRL,
+ * CM_L4PER_MCSPI3_CLKCTRL, CM_L4PER_MCSPI4_CLKCTRL, CM_L4PER_MGATE_CLKCTRL,
+ * CM_L4PER_MMCSD3_CLKCTRL, CM_L4PER_MMCSD4_CLKCTRL, CM_L4PER_MMCSD5_CLKCTRL,
+ * CM_L4PER_MSPROHG_CLKCTRL, CM_L4PER_SLIMBUS2_CLKCTRL, CM_L4PER_UART1_CLKCTRL,
+ * CM_L4PER_UART2_CLKCTRL, CM_L4PER_UART3_CLKCTRL, CM_L4PER_UART4_CLKCTRL,
+ * CM_L4SEC_AES1_CLKCTRL, CM_L4SEC_AES2_CLKCTRL, CM_L4SEC_CRYPTODMA_CLKCTRL,
+ * CM_L4SEC_DES3DES_CLKCTRL, CM_L4SEC_PKAEIP29_CLKCTRL, CM_L4SEC_RNG_CLKCTRL,
+ * CM_L4SEC_SHA2MD51_CLKCTRL, CM_L3INIT_CCPTX_CLKCTRL, CM_L3INIT_EMAC_CLKCTRL,
+ * CM_L3INIT_HSI_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL, CM_L3INIT_MMC2_CLKCTRL,
+ * CM_L3INIT_MMC6_CLKCTRL, CM_L3INIT_P1500_CLKCTRL, CM_L3INIT_PCIESS_CLKCTRL,
+ * CM_L3INIT_SATA_CLKCTRL, CM_L3INIT_TPPSS_CLKCTRL, CM_L3INIT_UNIPRO1_CLKCTRL,
+ * CM_L3INIT_USBPHYOCP2SCP_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL,
+ * CM_L3INIT_USB_HOST_FS_CLKCTRL, CM_L3INIT_USB_OTG_CLKCTRL,
+ * CM_L3INIT_USB_TLL_CLKCTRL, CM_L3INIT_XHPI_CLKCTRL, CM_CAM_FDIF_CLKCTRL,
+ * CM_CAM_ISS_CLKCTRL, CM_CEFUSE_CEFUSE_CLKCTRL,
+ * CM_L3INIT_USB_HOST_CLKCTRL_RESTORE, CM_L3INIT_USB_TLL_CLKCTRL_RESTORE,
+ * CM_L3INSTR_L3_3_CLKCTRL_RESTORE, CM_L3INSTR_L3_INSTR_CLKCTRL_RESTORE,
+ * CM_L3INSTR_OCP_WP1_CLKCTRL_RESTORE, CM_L4PER_GPIO2_CLKCTRL_RESTORE,
+ * CM_L4PER_GPIO3_CLKCTRL_RESTORE, CM_L4PER_GPIO4_CLKCTRL_RESTORE,
+ * CM_L4PER_GPIO5_CLKCTRL_RESTORE, CM_L4PER_GPIO6_CLKCTRL_RESTORE,
+ * CM_ALWON_MDMINTC_CLKCTRL, CM_ALWON_SR_CORE_CLKCTRL, CM_ALWON_SR_IVA_CLKCTRL,
+ * CM_ALWON_SR_MPU_CLKCTRL, CM_IVAHD_IVAHD_CLKCTRL, CM_IVAHD_SL2_CLKCTRL,
+ * CM_DSS_DEISS_CLKCTRL, CM_DSS_DSS_CLKCTRL, CM_CM2_PROFILING_CLKCTRL,
+ * CM_MPU_MPU_CLKCTRL, CM_TESLA_TESLA_CLKCTRL, CM1_ABE_AESS_CLKCTRL,
+ * CM1_ABE_DMIC_CLKCTRL, CM1_ABE_L4ABE_CLKCTRL, CM1_ABE_MCASP_CLKCTRL,
+ * CM1_ABE_MCBSP1_CLKCTRL, CM1_ABE_MCBSP2_CLKCTRL, CM1_ABE_MCBSP3_CLKCTRL,
+ * CM1_ABE_PDM_CLKCTRL, CM1_ABE_SLIMBUS_CLKCTRL, CM1_ABE_TIMER5_CLKCTRL,
+ * CM1_ABE_TIMER6_CLKCTRL, CM1_ABE_TIMER7_CLKCTRL, CM1_ABE_TIMER8_CLKCTRL,
+ * CM1_ABE_WDT3_CLKCTRL, CM_CM1_PROFILING_CLKCTRL
+ */
+#define OMAP4430_IDLEST_SHIFT                                   (1 << 16)
+#define OMAP4430_IDLEST_MASK                                    BITFIELD(16, 17)
+
+/* Used by CM_DUCATI_DYNAMICDEP, CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP */
+#define OMAP4430_ISS_DYNDEP_SHIFT                               (1 << 9)
+#define OMAP4430_ISS_DYNDEP_MASK                                BITFIELD(9, 9)
+
+/*
+ * Used by CM_DUCATI_STATICDEP, CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE,
+ * CM_MPU_STATICDEP, CM_TESLA_STATICDEP
+ */
+#define OMAP4430_ISS_STATDEP_SHIFT                              (1 << 9)
+#define OMAP4430_ISS_STATDEP_MASK                               BITFIELD(9, 9)
+
+/* Used by CM_L3_2_DYNAMICDEP, CM_TESLA_DYNAMICDEP */
+#define OMAP4430_IVAHD_DYNDEP_SHIFT                             (1 << 2)
+#define OMAP4430_IVAHD_DYNDEP_MASK                              BITFIELD(2, 2)
+
+/*
+ * Used by CM_D2D_STATICDEP, CM_DUCATI_STATICDEP, CM_SDMA_STATICDEP,
+ * CM_GFX_STATICDEP, CM_L3INIT_STATICDEP, CM_CAM_STATICDEP,
+ * CM_SDMA_STATICDEP_RESTORE, CM_DSS_STATICDEP, CM_MPU_STATICDEP,
+ * CM_TESLA_STATICDEP
+ */
+#define OMAP4430_IVAHD_STATDEP_SHIFT                            (1 << 2)
+#define OMAP4430_IVAHD_STATDEP_MASK                             BITFIELD(2, 2)
+
+/* Used by CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP, CM_L4PER_DYNAMICDEP */
+#define OMAP4430_L3INIT_DYNDEP_SHIFT                            (1 << 7)
+#define OMAP4430_L3INIT_DYNDEP_MASK                             BITFIELD(7, 7)
+
+/*
+ * Used by CM_D2D_STATICDEP, CM_DUCATI_STATICDEP, CM_SDMA_STATICDEP,
+ * CM_SDMA_STATICDEP_RESTORE, CM_MPU_STATICDEP, CM_TESLA_STATICDEP
+ */
+#define OMAP4430_L3INIT_STATDEP_SHIFT                           (1 << 7)
+#define OMAP4430_L3INIT_STATDEP_MASK                            BITFIELD(7, 7)
+
+/*
+ * Used by CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP, CM_L3INIT_DYNAMICDEP,
+ * CM_DSS_DYNAMICDEP, CM_MPU_DYNAMICDEP, CM_TESLA_DYNAMICDEP
+ */
+#define OMAP4430_L3_1_DYNDEP_SHIFT                              (1 << 5)
+#define OMAP4430_L3_1_DYNDEP_MASK                               BITFIELD(5, 5)
+
+/*
+ * Used by CM_D2D_STATICDEP, CM_DUCATI_STATICDEP, CM_SDMA_STATICDEP,
+ * CM_GFX_STATICDEP, CM_L4SEC_STATICDEP, CM_L3INIT_STATICDEP, CM_CAM_STATICDEP,
+ * CM_SDMA_STATICDEP_RESTORE, CM_IVAHD_STATICDEP, CM_DSS_STATICDEP,
+ * CM_MPU_STATICDEP, CM_TESLA_STATICDEP
+ */
+#define OMAP4430_L3_1_STATDEP_SHIFT                             (1 << 5)
+#define OMAP4430_L3_1_STATDEP_MASK                              BITFIELD(5, 5)
+
+/*
+ * Used by CM_EMU_DYNAMICDEP, CM_D2D_DYNAMICDEP, CM_DUCATI_DYNAMICDEP,
+ * CM_L3_1_DYNAMICDEP, CM_L4CFG_DYNAMICDEP, CM_SDMA_DYNAMICDEP,
+ * CM_GFX_DYNAMICDEP, CM_L4SEC_DYNAMICDEP, CM_L3INIT_DYNAMICDEP,
+ * CM_CAM_DYNAMICDEP, CM_IVAHD_DYNAMICDEP
+ */
+#define OMAP4430_L3_2_DYNDEP_SHIFT                              (1 << 6)
+#define OMAP4430_L3_2_DYNDEP_MASK                               BITFIELD(6, 6)
+
+/*
+ * Used by CM_D2D_STATICDEP, CM_DUCATI_STATICDEP, CM_SDMA_STATICDEP,
+ * CM_GFX_STATICDEP, CM_L4SEC_STATICDEP, CM_L3INIT_STATICDEP, CM_CAM_STATICDEP,
+ * CM_SDMA_STATICDEP_RESTORE, CM_IVAHD_STATICDEP, CM_DSS_STATICDEP,
+ * CM_MPU_STATICDEP, CM_TESLA_STATICDEP
+ */
+#define OMAP4430_L3_2_STATDEP_SHIFT                             (1 << 6)
+#define OMAP4430_L3_2_STATDEP_MASK                              BITFIELD(6, 6)
+
+/* Used by CM_L3_1_DYNAMICDEP */
+#define OMAP4430_L4CFG_DYNDEP_SHIFT                             (1 << 12)
+#define OMAP4430_L4CFG_DYNDEP_MASK                              BITFIELD(12, 12)
+
+/*
+ * Used by CM_D2D_STATICDEP, CM_DUCATI_STATICDEP, CM_SDMA_STATICDEP,
+ * CM_L3INIT_STATICDEP, CM_SDMA_STATICDEP_RESTORE, CM_MPU_STATICDEP,
+ * CM_TESLA_STATICDEP
+ */
+#define OMAP4430_L4CFG_STATDEP_SHIFT                            (1 << 12)
+#define OMAP4430_L4CFG_STATDEP_MASK                             BITFIELD(12, 12)
+
+/* Used by CM_L3_2_DYNAMICDEP */
+#define OMAP4430_L4PER_DYNDEP_SHIFT                             (1 << 13)
+#define OMAP4430_L4PER_DYNDEP_MASK                              BITFIELD(13, 13)
+
+/*
+ * Used by CM_D2D_STATICDEP, CM_DUCATI_STATICDEP, CM_SDMA_STATICDEP,
+ * CM_L4SEC_STATICDEP, CM_L3INIT_STATICDEP, CM_SDMA_STATICDEP_RESTORE,
+ * CM_MPU_STATICDEP, CM_TESLA_STATICDEP
+ */
+#define OMAP4430_L4PER_STATDEP_SHIFT                            (1 << 13)
+#define OMAP4430_L4PER_STATDEP_MASK                             BITFIELD(13, 13)
+
+/* Used by CM_L3_2_DYNAMICDEP, CM_L4PER_DYNAMICDEP */
+#define OMAP4430_L4SEC_DYNDEP_SHIFT                             (1 << 14)
+#define OMAP4430_L4SEC_DYNDEP_MASK                              BITFIELD(14, 14)
+
+/*
+ * Used by CM_DUCATI_STATICDEP, CM_SDMA_STATICDEP, CM_L3INIT_STATICDEP,
+ * CM_SDMA_STATICDEP_RESTORE, CM_MPU_STATICDEP
+ */
+#define OMAP4430_L4SEC_STATDEP_SHIFT                            (1 << 14)
+#define OMAP4430_L4SEC_STATDEP_MASK                             BITFIELD(14, 14)
+
+/* Used by CM_L4CFG_DYNAMICDEP */
+#define OMAP4430_L4WKUP_DYNDEP_SHIFT                            (1 << 15)
+#define OMAP4430_L4WKUP_DYNDEP_MASK                             BITFIELD(15, 15)
+
+/*
+ * Used by CM_DUCATI_STATICDEP, CM_SDMA_STATICDEP, CM_L3INIT_STATICDEP,
+ * CM_SDMA_STATICDEP_RESTORE, CM_MPU_STATICDEP, CM_TESLA_STATICDEP
+ */
+#define OMAP4430_L4WKUP_STATDEP_SHIFT                           (1 << 15)
+#define OMAP4430_L4WKUP_STATDEP_MASK                            BITFIELD(15, 15)
+
+/*
+ * Used by CM_D2D_DYNAMICDEP, CM_L3_1_DYNAMICDEP, CM_L4CFG_DYNAMICDEP,
+ * CM_MPU_DYNAMICDEP
+ */
+#define OMAP4430_MEMIF_DYNDEP_SHIFT                             (1 << 4)
+#define OMAP4430_MEMIF_DYNDEP_MASK                              BITFIELD(4, 4)
+
+/*
+ * Used by CM_D2D_STATICDEP, CM_DUCATI_STATICDEP, CM_SDMA_STATICDEP,
+ * CM_GFX_STATICDEP, CM_L4SEC_STATICDEP, CM_L3INIT_STATICDEP, CM_CAM_STATICDEP,
+ * CM_SDMA_STATICDEP_RESTORE, CM_IVAHD_STATICDEP, CM_DSS_STATICDEP,
+ * CM_MPU_STATICDEP, CM_TESLA_STATICDEP
+ */
+#define OMAP4430_MEMIF_STATDEP_SHIFT                            (1 << 4)
+#define OMAP4430_MEMIF_STATDEP_MASK                             BITFIELD(4, 4)
+
+/*
+ * Used by CM_SSC_MODFREQDIV_DPLL_PER, CM_SSC_MODFREQDIV_DPLL_UNIPRO,
+ * CM_SSC_MODFREQDIV_DPLL_USB, CM_SSC_MODFREQDIV_DPLL_CORE_RESTORE,
+ * CM_SSC_MODFREQDIV_DPLL_ABE, CM_SSC_MODFREQDIV_DPLL_CORE,
+ * CM_SSC_MODFREQDIV_DPLL_DDRPHY, CM_SSC_MODFREQDIV_DPLL_IVA,
+ * CM_SSC_MODFREQDIV_DPLL_MPU
+ */
+#define OMAP4430_MODFREQDIV_EXPONENT_SHIFT                      (1 << 8)
+#define OMAP4430_MODFREQDIV_EXPONENT_MASK                       BITFIELD(8, 10)
+
+/*
+ * Used by CM_SSC_MODFREQDIV_DPLL_PER, CM_SSC_MODFREQDIV_DPLL_UNIPRO,
+ * CM_SSC_MODFREQDIV_DPLL_USB, CM_SSC_MODFREQDIV_DPLL_CORE_RESTORE,
+ * CM_SSC_MODFREQDIV_DPLL_ABE, CM_SSC_MODFREQDIV_DPLL_CORE,
+ * CM_SSC_MODFREQDIV_DPLL_DDRPHY, CM_SSC_MODFREQDIV_DPLL_IVA,
+ * CM_SSC_MODFREQDIV_DPLL_MPU
+ */
+#define OMAP4430_MODFREQDIV_MANTISSA_SHIFT                      (1 << 0)
+#define OMAP4430_MODFREQDIV_MANTISSA_MASK                       BITFIELD(0, 6)
+
+/*
+ * Used by PRM_PRM_PROFILING_CLKCTRL, CM_WKUP_GPIO1_CLKCTRL,
+ * CM_WKUP_KEYBOARD_CLKCTRL, CM_WKUP_L4WKUP_CLKCTRL, CM_WKUP_RTC_CLKCTRL,
+ * CM_WKUP_SARRAM_CLKCTRL, CM_WKUP_SYNCTIMER_CLKCTRL, CM_WKUP_TIMER12_CLKCTRL,
+ * CM_WKUP_TIMER1_CLKCTRL, CM_WKUP_USIM_CLKCTRL, CM_WKUP_WDT1_CLKCTRL,
+ * CM_WKUP_WDT2_CLKCTRL, CM_EMU_DEBUGSS_CLKCTRL, CM_D2D_MODEM_ICR_CLKCTRL,
+ * CM_D2D_SAD2D_CLKCTRL, CM_D2D_SAD2D_FW_CLKCTRL, CM_DUCATI_DUCATI_CLKCTRL,
+ * CM_L3INSTR_L3_3_CLKCTRL, CM_L3INSTR_L3_INSTR_CLKCTRL,
+ * CM_L3INSTR_OCP_WP1_CLKCTRL, CM_L3_1_L3_1_CLKCTRL, CM_L3_2_GPMC_CLKCTRL,
+ * CM_L3_2_L3_2_CLKCTRL, CM_L3_2_OCMC_RAM_CLKCTRL, CM_L4CFG_HW_SEM_CLKCTRL,
+ * CM_L4CFG_L4_CFG_CLKCTRL, CM_L4CFG_MAILBOX_CLKCTRL, CM_L4CFG_SAR_ROM_CLKCTRL,
+ * CM_MEMIF_DMM_CLKCTRL, CM_MEMIF_EMIF_1_CLKCTRL, CM_MEMIF_EMIF_2_CLKCTRL,
+ * CM_MEMIF_EMIF_FW_CLKCTRL, CM_MEMIF_EMIF_H1_CLKCTRL,
+ * CM_MEMIF_EMIF_H2_CLKCTRL, CM_SDMA_SDMA_CLKCTRL, CM_GFX_GFX_CLKCTRL,
+ * CM_L4PER_ADC_CLKCTRL, CM_L4PER_DMTIMER10_CLKCTRL,
+ * CM_L4PER_DMTIMER11_CLKCTRL, CM_L4PER_DMTIMER2_CLKCTRL,
+ * CM_L4PER_DMTIMER3_CLKCTRL, CM_L4PER_DMTIMER4_CLKCTRL,
+ * CM_L4PER_DMTIMER9_CLKCTRL, CM_L4PER_ELM_CLKCTRL, CM_L4PER_GPIO2_CLKCTRL,
+ * CM_L4PER_GPIO3_CLKCTRL, CM_L4PER_GPIO4_CLKCTRL, CM_L4PER_GPIO5_CLKCTRL,
+ * CM_L4PER_GPIO6_CLKCTRL, CM_L4PER_HDQ1W_CLKCTRL, CM_L4PER_HECC1_CLKCTRL,
+ * CM_L4PER_HECC2_CLKCTRL, CM_L4PER_I2C1_CLKCTRL, CM_L4PER_I2C2_CLKCTRL,
+ * CM_L4PER_I2C3_CLKCTRL, CM_L4PER_I2C4_CLKCTRL, CM_L4PER_I2C5_CLKCTRL,
+ * CM_L4PER_L4PER_CLKCTRL, CM_L4PER_MCASP2_CLKCTRL, CM_L4PER_MCASP3_CLKCTRL,
+ * CM_L4PER_MCBSP4_CLKCTRL, CM_L4PER_MCSPI1_CLKCTRL, CM_L4PER_MCSPI2_CLKCTRL,
+ * CM_L4PER_MCSPI3_CLKCTRL, CM_L4PER_MCSPI4_CLKCTRL, CM_L4PER_MGATE_CLKCTRL,
+ * CM_L4PER_MMCSD3_CLKCTRL, CM_L4PER_MMCSD4_CLKCTRL, CM_L4PER_MMCSD5_CLKCTRL,
+ * CM_L4PER_MSPROHG_CLKCTRL, CM_L4PER_SLIMBUS2_CLKCTRL, CM_L4PER_UART1_CLKCTRL,
+ * CM_L4PER_UART2_CLKCTRL, CM_L4PER_UART3_CLKCTRL, CM_L4PER_UART4_CLKCTRL,
+ * CM_L4SEC_AES1_CLKCTRL, CM_L4SEC_AES2_CLKCTRL, CM_L4SEC_CRYPTODMA_CLKCTRL,
+ * CM_L4SEC_DES3DES_CLKCTRL, CM_L4SEC_PKAEIP29_CLKCTRL, CM_L4SEC_RNG_CLKCTRL,
+ * CM_L4SEC_SHA2MD51_CLKCTRL, CM_L3INIT_CCPTX_CLKCTRL, CM_L3INIT_EMAC_CLKCTRL,
+ * CM_L3INIT_HSI_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL, CM_L3INIT_MMC2_CLKCTRL,
+ * CM_L3INIT_MMC6_CLKCTRL, CM_L3INIT_P1500_CLKCTRL, CM_L3INIT_PCIESS_CLKCTRL,
+ * CM_L3INIT_SATA_CLKCTRL, CM_L3INIT_TPPSS_CLKCTRL, CM_L3INIT_UNIPRO1_CLKCTRL,
+ * CM_L3INIT_USBPHYOCP2SCP_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL,
+ * CM_L3INIT_USB_HOST_FS_CLKCTRL, CM_L3INIT_USB_OTG_CLKCTRL,
+ * CM_L3INIT_USB_TLL_CLKCTRL, CM_L3INIT_XHPI_CLKCTRL, CM_CAM_FDIF_CLKCTRL,
+ * CM_CAM_ISS_CLKCTRL, CM_CEFUSE_CEFUSE_CLKCTRL,
+ * CM_L3INIT_USB_HOST_CLKCTRL_RESTORE, CM_L3INIT_USB_TLL_CLKCTRL_RESTORE,
+ * CM_L3INSTR_L3_3_CLKCTRL_RESTORE, CM_L3INSTR_L3_INSTR_CLKCTRL_RESTORE,
+ * CM_L3INSTR_OCP_WP1_CLKCTRL_RESTORE, CM_L4PER_GPIO2_CLKCTRL_RESTORE,
+ * CM_L4PER_GPIO3_CLKCTRL_RESTORE, CM_L4PER_GPIO4_CLKCTRL_RESTORE,
+ * CM_L4PER_GPIO5_CLKCTRL_RESTORE, CM_L4PER_GPIO6_CLKCTRL_RESTORE,
+ * CM_ALWON_MDMINTC_CLKCTRL, CM_ALWON_SR_CORE_CLKCTRL, CM_ALWON_SR_IVA_CLKCTRL,
+ * CM_ALWON_SR_MPU_CLKCTRL, CM_IVAHD_IVAHD_CLKCTRL, CM_IVAHD_SL2_CLKCTRL,
+ * CM_DSS_DEISS_CLKCTRL, CM_DSS_DSS_CLKCTRL, CM_CM2_PROFILING_CLKCTRL,
+ * CM_MPU_MPU_CLKCTRL, CM_TESLA_TESLA_CLKCTRL, CM1_ABE_AESS_CLKCTRL,
+ * CM1_ABE_DMIC_CLKCTRL, CM1_ABE_L4ABE_CLKCTRL, CM1_ABE_MCASP_CLKCTRL,
+ * CM1_ABE_MCBSP1_CLKCTRL, CM1_ABE_MCBSP2_CLKCTRL, CM1_ABE_MCBSP3_CLKCTRL,
+ * CM1_ABE_PDM_CLKCTRL, CM1_ABE_SLIMBUS_CLKCTRL, CM1_ABE_TIMER5_CLKCTRL,
+ * CM1_ABE_TIMER6_CLKCTRL, CM1_ABE_TIMER7_CLKCTRL, CM1_ABE_TIMER8_CLKCTRL,
+ * CM1_ABE_WDT3_CLKCTRL, CM_CM1_PROFILING_CLKCTRL
+ */
+#define OMAP4430_MODULEMODE_SHIFT                               (1 << 0)
+#define OMAP4430_MODULEMODE_MASK                                BITFIELD(0, 1)
+
+/* Used by CM_DSS_DSS_CLKCTRL */
+#define OMAP4430_OPTFCLKEN_48MHZ_CLK_SHIFT                      (1 << 9)
+#define OMAP4430_OPTFCLKEN_48MHZ_CLK_MASK                       BITFIELD(9, 9)
+
+/* Used by CM_WKUP_BANDGAP_CLKCTRL */
+#define OMAP4430_OPTFCLKEN_BGAP_32K_SHIFT                       (1 << 8)
+#define OMAP4430_OPTFCLKEN_BGAP_32K_MASK                        BITFIELD(8, 8)
+
+/* Used by CM_L3INIT_USBPHYOCP2SCP_CLKCTRL */
+#define OMAP4430_OPTFCLKEN_CLK32K_SHIFT                         (1 << 9)
+#define OMAP4430_OPTFCLKEN_CLK32K_MASK                          BITFIELD(9, 9)
+
+/* Used by CM_CAM_ISS_CLKCTRL */
+#define OMAP4430_OPTFCLKEN_CTRLCLK_SHIFT                        (1 << 8)
+#define OMAP4430_OPTFCLKEN_CTRLCLK_MASK                         BITFIELD(8, 8)
+
+/*
+ * Used by CM_WKUP_GPIO1_CLKCTRL, CM_L4PER_GPIO2_CLKCTRL,
+ * CM_L4PER_GPIO3_CLKCTRL, CM_L4PER_GPIO4_CLKCTRL, CM_L4PER_GPIO5_CLKCTRL,
+ * CM_L4PER_GPIO6_CLKCTRL, CM_L4PER_GPIO2_CLKCTRL_RESTORE,
+ * CM_L4PER_GPIO3_CLKCTRL_RESTORE, CM_L4PER_GPIO4_CLKCTRL_RESTORE,
+ * CM_L4PER_GPIO5_CLKCTRL_RESTORE, CM_L4PER_GPIO6_CLKCTRL_RESTORE
+ */
+#define OMAP4430_OPTFCLKEN_DBCLK_SHIFT                          (1 << 8)
+#define OMAP4430_OPTFCLKEN_DBCLK_MASK                           BITFIELD(8, 8)
+
+/* Used by CM_MEMIF_DLL_CLKCTRL, CM_MEMIF_DLL_H_CLKCTRL */
+#define OMAP4430_OPTFCLKEN_DLL_CLK_SHIFT                        (1 << 8)
+#define OMAP4430_OPTFCLKEN_DLL_CLK_MASK                         BITFIELD(8, 8)
+
+/* Used by CM_DSS_DSS_CLKCTRL */
+#define OMAP4430_OPTFCLKEN_DSSCLK_SHIFT                         (1 << 8)
+#define OMAP4430_OPTFCLKEN_DSSCLK_MASK                          BITFIELD(8, 8)
+
+/* Used by CM1_ABE_SLIMBUS_CLKCTRL */
+#define OMAP4430_OPTFCLKEN_FCLK0_SHIFT                          (1 << 8)
+#define OMAP4430_OPTFCLKEN_FCLK0_MASK                           BITFIELD(8, 8)
+
+/* Used by CM1_ABE_SLIMBUS_CLKCTRL */
+#define OMAP4430_OPTFCLKEN_FCLK1_SHIFT                          (1 << 9)
+#define OMAP4430_OPTFCLKEN_FCLK1_MASK                           BITFIELD(9, 9)
+
+/* Used by CM1_ABE_SLIMBUS_CLKCTRL */
+#define OMAP4430_OPTFCLKEN_FCLK2_SHIFT                          (1 << 10)
+#define OMAP4430_OPTFCLKEN_FCLK2_MASK                           BITFIELD(10, 10)
+
+/* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */
+#define OMAP4430_OPTFCLKEN_FUNC48MCLK_SHIFT                     (1 << 15)
+#define OMAP4430_OPTFCLKEN_FUNC48MCLK_MASK                      BITFIELD(15, 15)
+
+/* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */
+#define OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_SHIFT                (1 << 13)
+#define OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_MASK                 BITFIELD(13, 13)
+
+/* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */
+#define OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_SHIFT                (1 << 14)
+#define OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_MASK                 BITFIELD(14, 14)
+
+/* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */
+#define OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_SHIFT                 (1 << 11)
+#define OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_MASK                  BITFIELD(11, 11)
+
+/* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */
+#define OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_SHIFT                 (1 << 12)
+#define OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_MASK                  BITFIELD(12, 12)
+
+/* Used by CM_L4PER_SLIMBUS2_CLKCTRL */
+#define OMAP4430_OPTFCLKEN_PER24MC_GFCLK_SHIFT                  (1 << 8)
+#define OMAP4430_OPTFCLKEN_PER24MC_GFCLK_MASK                   BITFIELD(8, 8)
+
+/* Used by CM_L4PER_SLIMBUS2_CLKCTRL */
+#define OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_SHIFT                (1 << 9)
+#define OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_MASK                 BITFIELD(9, 9)
+
+/* Used by CM_L3INIT_USBPHYOCP2SCP_CLKCTRL */
+#define OMAP4430_OPTFCLKEN_PHY_48M_SHIFT                        (1 << 8)
+#define OMAP4430_OPTFCLKEN_PHY_48M_MASK                         BITFIELD(8, 8)
+
+/* Used by CM_L4PER_SLIMBUS2_CLKCTRL */
+#define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_SHIFT                    (1 << 10)
+#define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_MASK                     BITFIELD(10, 10)
+
+/* Renamed from OPTFCLKEN_SLIMBUS_CLK Used by CM1_ABE_SLIMBUS_CLKCTRL */
+#define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_SHIFT              (1 << 11)
+#define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_MASK               BITFIELD(11, 11)
+
+/* Used by CM_DSS_DSS_CLKCTRL */
+#define OMAP4430_OPTFCLKEN_SYS_CLK_SHIFT                        (1 << 10)
+#define OMAP4430_OPTFCLKEN_SYS_CLK_MASK                         BITFIELD(10, 10)
+
+/* Used by CM_DSS_DSS_CLKCTRL */
+#define OMAP4430_OPTFCLKEN_TV_CLK_SHIFT                         (1 << 11)
+#define OMAP4430_OPTFCLKEN_TV_CLK_MASK                          BITFIELD(11, 11)
+
+/* Used by CM_L3INIT_UNIPRO1_CLKCTRL */
+#define OMAP4430_OPTFCLKEN_TXPHYCLK_SHIFT                       (1 << 8)
+#define OMAP4430_OPTFCLKEN_TXPHYCLK_MASK                        BITFIELD(8, 8)
+
+/* Used by CM_L3INIT_USB_TLL_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL_RESTORE */
+#define OMAP4430_OPTFCLKEN_USB_CH0_CLK_SHIFT                    (1 << 8)
+#define OMAP4430_OPTFCLKEN_USB_CH0_CLK_MASK                     BITFIELD(8, 8)
+
+/* Used by CM_L3INIT_USB_TLL_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL_RESTORE */
+#define OMAP4430_OPTFCLKEN_USB_CH1_CLK_SHIFT                    (1 << 9)
+#define OMAP4430_OPTFCLKEN_USB_CH1_CLK_MASK                     BITFIELD(9, 9)
+
+/* Used by CM_L3INIT_USB_TLL_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL_RESTORE */
+#define OMAP4430_OPTFCLKEN_USB_CH2_CLK_SHIFT                    (1 << 10)
+#define OMAP4430_OPTFCLKEN_USB_CH2_CLK_MASK                     BITFIELD(10, 10)
+
+/* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */
+#define OMAP4430_OPTFCLKEN_UTMI_P1_CLK_SHIFT                    (1 << 8)
+#define OMAP4430_OPTFCLKEN_UTMI_P1_CLK_MASK                     BITFIELD(8, 8)
+
+/* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */
+#define OMAP4430_OPTFCLKEN_UTMI_P2_CLK_SHIFT                    (1 << 9)
+#define OMAP4430_OPTFCLKEN_UTMI_P2_CLK_MASK                     BITFIELD(9, 9)
+
+/* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */
+#define OMAP4430_OPTFCLKEN_UTMI_P3_CLK_SHIFT                    (1 << 10)
+#define OMAP4430_OPTFCLKEN_UTMI_P3_CLK_MASK                     BITFIELD(10, 10)
+
+/* Used by CM_L3INIT_USB_OTG_CLKCTRL */
+#define OMAP4430_OPTFCLKEN_XCLK_SHIFT                           (1 << 8)
+#define OMAP4430_OPTFCLKEN_XCLK_MASK                            BITFIELD(8, 8)
+
+/* Used by CM_EMU_OVERRIDE_DPLL_PER, CM_EMU_OVERRIDE_DPLL_CORE */
+#define OMAP4430_OVERRIDE_ENABLE_SHIFT                          (1 << 19)
+#define OMAP4430_OVERRIDE_ENABLE_MASK                           BITFIELD(19, 19)
+
+/* Used by CM_CLKSEL_ABE */
+#define OMAP4430_PAD_CLKS_GATE_SHIFT                            (1 << 8)
+#define OMAP4430_PAD_CLKS_GATE_MASK                             BITFIELD(8, 8)
+
+/* Used by CM_CORE_DVFS_CURRENT, CM_IVA_DVFS_CURRENT */
+#define OMAP4430_PERF_CURRENT_SHIFT                             (1 << 0)
+#define OMAP4430_PERF_CURRENT_MASK                              BITFIELD(0, 7)
+
+/*
+ * Used by CM_CORE_DVFS_PERF1, CM_CORE_DVFS_PERF2, CM_CORE_DVFS_PERF3,
+ * CM_CORE_DVFS_PERF4, CM_IVA_DVFS_PERF_ABE, CM_IVA_DVFS_PERF_IVAHD,
+ * CM_IVA_DVFS_PERF_TESLA
+ */
+#define OMAP4430_PERF_REQ_SHIFT                                 (1 << 0)
+#define OMAP4430_PERF_REQ_MASK                                  BITFIELD(0, 7)
+
+/* Used by CM_EMU_OVERRIDE_DPLL_PER */
+#define OMAP4430_PER_DPLL_EMU_DIV_SHIFT                         (1 << 0)
+#define OMAP4430_PER_DPLL_EMU_DIV_MASK                          BITFIELD(0, 6)
+
+/* Used by CM_EMU_OVERRIDE_DPLL_PER */
+#define OMAP4430_PER_DPLL_EMU_MULT_SHIFT                        (1 << 8)
+#define OMAP4430_PER_DPLL_EMU_MULT_MASK                         BITFIELD(8, 18)
+
+/* Used by CM_RESTORE_ST */
+#define OMAP4430_PHASE1_COMPLETED_SHIFT                         (1 << 0)
+#define OMAP4430_PHASE1_COMPLETED_MASK                          BITFIELD(0, 0)
+
+/* Used by CM_RESTORE_ST */
+#define OMAP4430_PHASE2A_COMPLETED_SHIFT                        (1 << 1)
+#define OMAP4430_PHASE2A_COMPLETED_MASK                         BITFIELD(1, 1)
+
+/* Used by CM_RESTORE_ST */
+#define OMAP4430_PHASE2B_COMPLETED_SHIFT                        (1 << 2)
+#define OMAP4430_PHASE2B_COMPLETED_MASK                         BITFIELD(2, 2)
+
+/* Used by CM_EMU_DEBUGSS_CLKCTRL */
+#define OMAP4430_PMD_STM_MUX_CTRL_SHIFT                         (1 << 20)
+#define OMAP4430_PMD_STM_MUX_CTRL_MASK                          BITFIELD(20, 21)
+
+/* Used by CM_EMU_DEBUGSS_CLKCTRL */
+#define OMAP4430_PMD_TRACE_MUX_CTRL_SHIFT                       (1 << 22)
+#define OMAP4430_PMD_TRACE_MUX_CTRL_MASK                        BITFIELD(22, 23)
+
+/* Used by CM_DYN_DEP_PRESCAL */
+#define OMAP4430_PRESCAL_SHIFT                                  (1 << 0)
+#define OMAP4430_PRESCAL_MASK                                   BITFIELD(0, 5)
+
+/* Used by REVISION_CM2, REVISION_CM1 */
+#define OMAP4430_REV_SHIFT                                      (1 << 0)
+#define OMAP4430_REV_MASK                                       BITFIELD(0, 7)
+
+/*
+ * Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL,
+ * CM_L3INIT_USB_HOST_CLKCTRL_RESTORE, CM_L3INIT_USB_TLL_CLKCTRL_RESTORE
+ */
+#define OMAP4430_SAR_MODE_SHIFT                                 (1 << 4)
+#define OMAP4430_SAR_MODE_MASK                                  BITFIELD(4, 4)
+
+/* Used by CM_SCALE_FCLK */
+#define OMAP4430_SCALE_FCLK_SHIFT                               (1 << 0)
+#define OMAP4430_SCALE_FCLK_MASK                                BITFIELD(0, 0)
+
+/* Used by CM_L4CFG_DYNAMICDEP */
+#define OMAP4430_SDMA_DYNDEP_SHIFT                              (1 << 11)
+#define OMAP4430_SDMA_DYNDEP_MASK                               BITFIELD(11, 11)
+
+/* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP */
+#define OMAP4430_SDMA_STATDEP_SHIFT                             (1 << 11)
+#define OMAP4430_SDMA_STATDEP_MASK                              BITFIELD(11, 11)
+
+/* Used by CM_CLKSEL_ABE */
+#define OMAP4430_SLIMBUS_CLK_GATE_SHIFT                         (1 << 10)
+#define OMAP4430_SLIMBUS_CLK_GATE_MASK                          BITFIELD(10, 10)
+
+/*
+ * Used by CM_EMU_DEBUGSS_CLKCTRL, CM_D2D_SAD2D_CLKCTRL,
+ * CM_DUCATI_DUCATI_CLKCTRL, CM_SDMA_SDMA_CLKCTRL, CM_GFX_GFX_CLKCTRL,
+ * CM_L4SEC_CRYPTODMA_CLKCTRL, CM_L3INIT_CCPTX_CLKCTRL, CM_L3INIT_EMAC_CLKCTRL,
+ * CM_L3INIT_HSI_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL, CM_L3INIT_MMC2_CLKCTRL,
+ * CM_L3INIT_MMC6_CLKCTRL, CM_L3INIT_P1500_CLKCTRL, CM_L3INIT_PCIESS_CLKCTRL,
+ * CM_L3INIT_SATA_CLKCTRL, CM_L3INIT_TPPSS_CLKCTRL, CM_L3INIT_UNIPRO1_CLKCTRL,
+ * CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_FS_CLKCTRL,
+ * CM_L3INIT_USB_OTG_CLKCTRL, CM_L3INIT_XHPI_CLKCTRL, CM_CAM_FDIF_CLKCTRL,
+ * CM_CAM_ISS_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE,
+ * CM_IVAHD_IVAHD_CLKCTRL, CM_DSS_DEISS_CLKCTRL, CM_DSS_DSS_CLKCTRL,
+ * CM_MPU_MPU_CLKCTRL, CM_TESLA_TESLA_CLKCTRL, CM1_ABE_AESS_CLKCTRL
+ */
+#define OMAP4430_STBYST_SHIFT                                   (1 << 18)
+#define OMAP4430_STBYST_MASK                                    BITFIELD(18, 18)
+
+/*
+ * Used by CM_IDLEST_DPLL_PER, CM_IDLEST_DPLL_UNIPRO, CM_IDLEST_DPLL_USB,
+ * CM_IDLEST_DPLL_ABE, CM_IDLEST_DPLL_CORE, CM_IDLEST_DPLL_DDRPHY,
+ * CM_IDLEST_DPLL_IVA, CM_IDLEST_DPLL_MPU
+ */
+#define OMAP4430_ST_DPLL_CLK_SHIFT                              (1 << 0)
+#define OMAP4430_ST_DPLL_CLK_MASK                               BITFIELD(0, 0)
+
+/* Used by CM_CLKDCOLDO_DPLL_USB */
+#define OMAP4430_ST_DPLL_CLKDCOLDO_SHIFT                        (1 << 9)
+#define OMAP4430_ST_DPLL_CLKDCOLDO_MASK                         BITFIELD(9, 9)
+
+/*
+ * Used by CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_USB, CM_DIV_M2_DPLL_CORE_RESTORE,
+ * CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE, CM_DIV_M2_DPLL_DDRPHY,
+ * CM_DIV_M2_DPLL_MPU
+ */
+#define OMAP4430_ST_DPLL_CLKOUT_SHIFT                           (1 << 9)
+#define OMAP4430_ST_DPLL_CLKOUT_MASK                            BITFIELD(9, 9)
+
+/*
+ * Used by CM_DIV_M3_DPLL_PER, CM_DIV_M3_DPLL_CORE_RESTORE, CM_DIV_M3_DPLL_ABE,
+ * CM_DIV_M3_DPLL_CORE
+ */
+#define OMAP4430_ST_DPLL_CLKOUTHIF_SHIFT                        (1 << 9)
+#define OMAP4430_ST_DPLL_CLKOUTHIF_MASK                         BITFIELD(9, 9)
+
+/* Used by CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO, CM_DIV_M2_DPLL_ABE */
+#define OMAP4430_ST_DPLL_CLKOUTX2_SHIFT                         (1 << 11)
+#define OMAP4430_ST_DPLL_CLKOUTX2_MASK                          BITFIELD(11, 11)
+
+/*
+ * Used by CM_DIV_M4_DPLL_PER, CM_DIV_M4_DPLL_CORE_RESTORE,
+ * CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA
+ */
+#define OMAP4430_ST_HSDIVIDER_CLKOUT1_SHIFT                     (1 << 9)
+#define OMAP4430_ST_HSDIVIDER_CLKOUT1_MASK                      BITFIELD(9, 9)
+
+/*
+ * Used by CM_DIV_M5_DPLL_PER, CM_DIV_M5_DPLL_CORE_RESTORE,
+ * CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA
+ */
+#define OMAP4430_ST_HSDIVIDER_CLKOUT2_SHIFT                     (1 << 9)
+#define OMAP4430_ST_HSDIVIDER_CLKOUT2_MASK                      BITFIELD(9, 9)
+
+/*
+ * Used by CM_DIV_M6_DPLL_PER, CM_DIV_M6_DPLL_CORE_RESTORE,
+ * CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY
+ */
+#define OMAP4430_ST_HSDIVIDER_CLKOUT3_SHIFT                     (1 << 9)
+#define OMAP4430_ST_HSDIVIDER_CLKOUT3_MASK                      BITFIELD(9, 9)
+
+/*
+ * Used by CM_DIV_M7_DPLL_PER, CM_DIV_M7_DPLL_CORE_RESTORE,
+ * CM_DIV_M7_DPLL_CORE
+ */
+#define OMAP4430_ST_HSDIVIDER_CLKOUT4_SHIFT                     (1 << 9)
+#define OMAP4430_ST_HSDIVIDER_CLKOUT4_MASK                      BITFIELD(9, 9)
+
+/* Used by CM_SYS_CLKSEL */
+#define OMAP4430_SYS_CLKSEL_SHIFT                               (1 << 0)
+#define OMAP4430_SYS_CLKSEL_MASK                                BITFIELD(0, 2)
+
+/* Used by CM_L4CFG_DYNAMICDEP */
+#define OMAP4430_TESLA_DYNDEP_SHIFT                             (1 << 1)
+#define OMAP4430_TESLA_DYNDEP_MASK                              BITFIELD(1, 1)
+
+/* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP */
+#define OMAP4430_TESLA_STATDEP_SHIFT                            (1 << 1)
+#define OMAP4430_TESLA_STATDEP_MASK                             BITFIELD(1, 1)
+
+/*
+ * Used by CM_EMU_DYNAMICDEP, CM_D2D_DYNAMICDEP, CM_DUCATI_DYNAMICDEP,
+ * CM_L3_1_DYNAMICDEP, CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP,
+ * CM_L4PER_DYNAMICDEP, CM_MPU_DYNAMICDEP, CM_TESLA_DYNAMICDEP
+ */
+#define OMAP4430_WINDOWSIZE_SHIFT                               (1 << 24)
+#define OMAP4430_WINDOWSIZE_MASK                                BITFIELD(24, 27)
+#endif
diff --git a/arch/arm/mach-omap2/cm.c b/arch/arm/mach-omap2/cm.c
index 8eb2dab8c7db..58e4a1c557d8 100644
--- a/arch/arm/mach-omap2/cm.c
+++ b/arch/arm/mach-omap2/cm.c
@@ -21,6 +21,8 @@
 
 #include <asm/atomic.h>
 
+#include <plat/common.h>
+
 #include "cm.h"
 #include "cm-regbits-24xx.h"
 #include "cm-regbits-34xx.h"
@@ -61,9 +63,8 @@ int omap2_cm_wait_module_ready(s16 prcm_mod, u8 idlest_id, u8 idlest_shift)
         mask = 1 << idlest_shift;
 
         /* XXX should be OMAP2 CM */
-        while (((cm_read_mod_reg(prcm_mod, cm_idlest_reg) & mask) != ena) &&
-               (i++ < MAX_MODULE_READY_TIME))
-                udelay(1);
+        omap_test_timeout(((cm_read_mod_reg(prcm_mod, cm_idlest_reg) & mask) == ena),
+                          MAX_MODULE_READY_TIME, i);
 
         return (i < MAX_MODULE_READY_TIME) ? 0 : -EBUSY;
 }
diff --git a/arch/arm/mach-omap2/cm.h b/arch/arm/mach-omap2/cm.h
index a2fcfcc253cc..90a4086fbdf4 100644
--- a/arch/arm/mach-omap2/cm.h
+++ b/arch/arm/mach-omap2/cm.h
@@ -4,8 +4,8 @@
 /*
  * OMAP2/3 Clock Management (CM) register definitions
  *
- * Copyright (C) 2007-2008 Texas Instruments, Inc.
- * Copyright (C) 2007-2008 Nokia Corporation
+ * Copyright (C) 2007-2009 Texas Instruments, Inc.
+ * Copyright (C) 2007-2009 Nokia Corporation
  *
  * Written by Paul Walmsley
  *
@@ -22,6 +22,12 @@
                         OMAP2_L4_IO_ADDRESS(OMAP2430_CM_BASE + (module) + (reg))
 #define OMAP34XX_CM_REGADDR(module, reg)                                \
                         OMAP2_L4_IO_ADDRESS(OMAP3430_CM_BASE + (module) + (reg))
+#define OMAP44XX_CM1_REGADDR(module, reg)                               \
+                        OMAP2_L4_IO_ADDRESS(OMAP4430_CM1_BASE + (module) + (reg))
+#define OMAP44XX_CM2_REGADDR(module, reg)                               \
+                        OMAP2_L4_IO_ADDRESS(OMAP4430_CM2_BASE + (module) + (reg))
+
+#include "cm44xx.h"
 
 /*
  * Architecture-specific global CM registers
@@ -89,6 +95,11 @@
 #define OMAP3430_CM_CLKSEL2_EMU                         0x0050
 #define OMAP3430_CM_CLKSEL3_EMU                         0x0054
 
+/* CM2.CEFUSE_CM2 register offsets */
+
+/* OMAP4 modulemode control */
+#define OMAP4430_MODULEMODE_HWCTRL                      0
+#define OMAP4430_MODULEMODE_SWCTRL                      1
 
 /* Clock management domain register get/set */
 
diff --git a/arch/arm/mach-omap2/cm44xx.h b/arch/arm/mach-omap2/cm44xx.h
new file mode 100644
index 000000000000..c575b9b0c041
--- /dev/null
+++ b/arch/arm/mach-omap2/cm44xx.h
@@ -0,0 +1,358 @@
+/*
+ * OMAP44xx CM1 & CM2 instance offset macros
+ *
+ * Copyright (C) 2009 Texas Instruments, Inc.
+ * Copyright (C) 2009 Nokia Corporation
+ *
+ * Paul Walmsley (paul@pwsan.com)
+ * Rajendra Nayak (rnayak@ti.com)
+ * Benoit Cousson (b-cousson@ti.com)
+ *
+ * This file is automatically generated from the OMAP hardware databases.
+ * We respectfully ask that any modifications to this file be coordinated
+ * with the public linux-omap@vger.kernel.org mailing list and the
+ * authors above to ensure that the autogeneration scripts are kept
+ * up-to-date with the file contents.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ARCH_ARM_MACH_OMAP2_CM44XX_H
+#define __ARCH_ARM_MACH_OMAP2_CM44XX_H
+
+
+/* CM1 */
+
+
+/* CM1.OCP_SOCKET_CM1 register offsets */
+#define OMAP4430_REVISION_CM1                           OMAP44XX_CM1_REGADDR(OMAP4430_CM1_OCP_SOCKET_MOD, 0x0000)
+#define OMAP4430_CM_CM1_PROFILING_CLKCTRL               OMAP44XX_CM1_REGADDR(OMAP4430_CM1_OCP_SOCKET_MOD, 0x0040)
+
+/* CM1.CKGEN_CM1 register offsets */
+#define OMAP4430_CM_CLKSEL_CORE                         OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0000)
+#define OMAP4430_CM_CLKSEL_ABE                          OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0008)
+#define OMAP4430_CM_DLL_CTRL                            OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0010)
+#define OMAP4430_CM_CLKMODE_DPLL_CORE                   OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0020)
+#define OMAP4430_CM_IDLEST_DPLL_CORE                    OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0024)
+#define OMAP4430_CM_AUTOIDLE_DPLL_CORE                  OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0028)
+#define OMAP4430_CM_CLKSEL_DPLL_CORE                    OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x002c)
+#define OMAP4430_CM_DIV_M2_DPLL_CORE                    OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0030)
+#define OMAP4430_CM_DIV_M3_DPLL_CORE                    OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0034)
+#define OMAP4430_CM_DIV_M4_DPLL_CORE                    OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0038)
+#define OMAP4430_CM_DIV_M5_DPLL_CORE                    OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x003c)
+#define OMAP4430_CM_DIV_M6_DPLL_CORE                    OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0040)
+#define OMAP4430_CM_DIV_M7_DPLL_CORE                    OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0044)
+#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_CORE            OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0048)
+#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_CORE            OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x004c)
+#define OMAP4430_CM_EMU_OVERRIDE_DPLL_CORE              OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0050)
+#define OMAP4430_CM_CLKMODE_DPLL_MPU                    OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0060)
+#define OMAP4430_CM_IDLEST_DPLL_MPU                     OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0064)
+#define OMAP4430_CM_AUTOIDLE_DPLL_MPU                   OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0068)
+#define OMAP4430_CM_CLKSEL_DPLL_MPU                     OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x006c)
+#define OMAP4430_CM_DIV_M2_DPLL_MPU                     OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0070)
+#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_MPU             OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0088)
+#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_MPU             OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x008c)
+#define OMAP4430_CM_BYPCLK_DPLL_MPU                     OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x009c)
+#define OMAP4430_CM_CLKMODE_DPLL_IVA                    OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00a0)
+#define OMAP4430_CM_IDLEST_DPLL_IVA                     OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00a4)
+#define OMAP4430_CM_AUTOIDLE_DPLL_IVA                   OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00a8)
+#define OMAP4430_CM_CLKSEL_DPLL_IVA                     OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00ac)
+#define OMAP4430_CM_DIV_M4_DPLL_IVA                     OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00b8)
+#define OMAP4430_CM_DIV_M5_DPLL_IVA                     OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00bc)
+#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_IVA             OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00c8)
+#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_IVA             OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00cc)
+#define OMAP4430_CM_BYPCLK_DPLL_IVA                     OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00dc)
+#define OMAP4430_CM_CLKMODE_DPLL_ABE                    OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00e0)
+#define OMAP4430_CM_IDLEST_DPLL_ABE                     OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00e4)
+#define OMAP4430_CM_AUTOIDLE_DPLL_ABE                   OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00e8)
+#define OMAP4430_CM_CLKSEL_DPLL_ABE                     OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00ec)
+#define OMAP4430_CM_DIV_M2_DPLL_ABE                     OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00f0)
+#define OMAP4430_CM_DIV_M3_DPLL_ABE                     OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00f4)
+#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_ABE             OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0108)
+#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_ABE             OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x010c)
+#define OMAP4430_CM_CLKMODE_DPLL_DDRPHY                 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0120)
+#define OMAP4430_CM_IDLEST_DPLL_DDRPHY                  OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0124)
+#define OMAP4430_CM_AUTOIDLE_DPLL_DDRPHY                OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0128)
+#define OMAP4430_CM_CLKSEL_DPLL_DDRPHY                  OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x012c)
+#define OMAP4430_CM_DIV_M2_DPLL_DDRPHY                  OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0130)
+#define OMAP4430_CM_DIV_M4_DPLL_DDRPHY                  OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0138)
+#define OMAP4430_CM_DIV_M5_DPLL_DDRPHY                  OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x013c)
+#define OMAP4430_CM_DIV_M6_DPLL_DDRPHY                  OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0140)
+#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_DDRPHY          OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0148)
+#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_DDRPHY          OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x014c)
+#define OMAP4430_CM_SHADOW_FREQ_CONFIG1                 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0160)
+#define OMAP4430_CM_SHADOW_FREQ_CONFIG2                 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0164)
+#define OMAP4430_CM_DYN_DEP_PRESCAL                     OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0170)
+#define OMAP4430_CM_RESTORE_ST                          OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0180)
+
+/* CM1.MPU_CM1 register offsets */
+#define OMAP4430_CM_MPU_CLKSTCTRL                       OMAP44XX_CM1_REGADDR(OMAP4430_CM1_MPU_MOD, 0x0000)
+#define OMAP4430_CM_MPU_STATICDEP                       OMAP44XX_CM1_REGADDR(OMAP4430_CM1_MPU_MOD, 0x0004)
+#define OMAP4430_CM_MPU_DYNAMICDEP                      OMAP44XX_CM1_REGADDR(OMAP4430_CM1_MPU_MOD, 0x0008)
+#define OMAP4430_CM_MPU_MPU_CLKCTRL                     OMAP44XX_CM1_REGADDR(OMAP4430_CM1_MPU_MOD, 0x0020)
+
+/* CM1.TESLA_CM1 register offsets */
+#define OMAP4430_CM_TESLA_CLKSTCTRL                     OMAP44XX_CM1_REGADDR(OMAP4430_CM1_TESLA_MOD, 0x0000)
+#define OMAP4430_CM_TESLA_STATICDEP                     OMAP44XX_CM1_REGADDR(OMAP4430_CM1_TESLA_MOD, 0x0004)
+#define OMAP4430_CM_TESLA_DYNAMICDEP                    OMAP44XX_CM1_REGADDR(OMAP4430_CM1_TESLA_MOD, 0x0008)
+#define OMAP4430_CM_TESLA_TESLA_CLKCTRL                 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_TESLA_MOD, 0x0020)
+
+/* CM1.ABE_CM1 register offsets */
+#define OMAP4430_CM1_ABE_CLKSTCTRL                      OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0000)
+#define OMAP4430_CM1_ABE_L4ABE_CLKCTRL                  OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0020)
+#define OMAP4430_CM1_ABE_AESS_CLKCTRL                   OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0028)
+#define OMAP4430_CM1_ABE_PDM_CLKCTRL                    OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0030)
+#define OMAP4430_CM1_ABE_DMIC_CLKCTRL                   OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0038)
+#define OMAP4430_CM1_ABE_MCASP_CLKCTRL                  OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0040)
+#define OMAP4430_CM1_ABE_MCBSP1_CLKCTRL                 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0048)
+#define OMAP4430_CM1_ABE_MCBSP2_CLKCTRL                 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0050)
+#define OMAP4430_CM1_ABE_MCBSP3_CLKCTRL                 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0058)
+#define OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL                OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0060)
+#define OMAP4430_CM1_ABE_TIMER5_CLKCTRL                 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0068)
+#define OMAP4430_CM1_ABE_TIMER6_CLKCTRL                 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0070)
+#define OMAP4430_CM1_ABE_TIMER7_CLKCTRL                 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0078)
+#define OMAP4430_CM1_ABE_TIMER8_CLKCTRL                 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0080)
+#define OMAP4430_CM1_ABE_WDT3_CLKCTRL                   OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0088)
+
+/* CM1.RESTORE_CM1 register offsets */
+#define OMAP4430_CM_CLKSEL_CORE_RESTORE                 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0000)
+#define OMAP4430_CM_DIV_M2_DPLL_CORE_RESTORE            OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0004)
+#define OMAP4430_CM_DIV_M3_DPLL_CORE_RESTORE            OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0008)
+#define OMAP4430_CM_DIV_M4_DPLL_CORE_RESTORE            OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x000c)
+#define OMAP4430_CM_DIV_M5_DPLL_CORE_RESTORE            OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0010)
+#define OMAP4430_CM_DIV_M6_DPLL_CORE_RESTORE            OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0014)
+#define OMAP4430_CM_DIV_M7_DPLL_CORE_RESTORE            OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0018)
+#define OMAP4430_CM_CLKSEL_DPLL_CORE_RESTORE            OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x001c)
+#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_CORE_RESTORE    OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0020)
+#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_CORE_RESTORE    OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0024)
+#define OMAP4430_CM_CLKMODE_DPLL_CORE_RESTORE           OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0028)
+#define OMAP4430_CM_SHADOW_FREQ_CONFIG1_RESTORE         OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x002c)
+#define OMAP4430_CM_AUTOIDLE_DPLL_CORE_RESTORE          OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0030)
+#define OMAP4430_CM_MPU_CLKSTCTRL_RESTORE               OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0034)
+
+/* CM2 */
+
+
+/* CM2.OCP_SOCKET_CM2 register offsets */
+#define OMAP4430_REVISION_CM2                           OMAP44XX_CM2_REGADDR(OMAP4430_CM2_OCP_SOCKET_MOD, 0x0000)
+#define OMAP4430_CM_CM2_PROFILING_CLKCTRL               OMAP44XX_CM2_REGADDR(OMAP4430_CM2_OCP_SOCKET_MOD, 0x0040)
+
+/* CM2.CKGEN_CM2 register offsets */
+#define OMAP4430_CM_CLKSEL_DUCATI_ISS_ROOT              OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0000)
+#define OMAP4430_CM_CLKSEL_USB_60MHZ                    OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0004)
+#define OMAP4430_CM_SCALE_FCLK                          OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0008)
+#define OMAP4430_CM_CORE_DVFS_PERF1                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0010)
+#define OMAP4430_CM_CORE_DVFS_PERF2                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0014)
+#define OMAP4430_CM_CORE_DVFS_PERF3                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0018)
+#define OMAP4430_CM_CORE_DVFS_PERF4                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x001c)
+#define OMAP4430_CM_CORE_DVFS_CURRENT                   OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0024)
+#define OMAP4430_CM_IVA_DVFS_PERF_TESLA                 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0028)
+#define OMAP4430_CM_IVA_DVFS_PERF_IVAHD                 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x002c)
+#define OMAP4430_CM_IVA_DVFS_PERF_ABE                   OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0030)
+#define OMAP4430_CM_IVA_DVFS_CURRENT                    OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0038)
+#define OMAP4430_CM_CLKMODE_DPLL_PER                    OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0040)
+#define OMAP4430_CM_IDLEST_DPLL_PER                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0044)
+#define OMAP4430_CM_AUTOIDLE_DPLL_PER                   OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0048)
+#define OMAP4430_CM_CLKSEL_DPLL_PER                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x004c)
+#define OMAP4430_CM_DIV_M2_DPLL_PER                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0050)
+#define OMAP4430_CM_DIV_M3_DPLL_PER                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0054)
+#define OMAP4430_CM_DIV_M4_DPLL_PER                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0058)
+#define OMAP4430_CM_DIV_M5_DPLL_PER                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x005c)
+#define OMAP4430_CM_DIV_M6_DPLL_PER                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0060)
+#define OMAP4430_CM_DIV_M7_DPLL_PER                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0064)
+#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_PER             OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0068)
+#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_PER             OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x006c)
+#define OMAP4430_CM_EMU_OVERRIDE_DPLL_PER               OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0070)
+#define OMAP4430_CM_CLKMODE_DPLL_USB                    OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0080)
+#define OMAP4430_CM_IDLEST_DPLL_USB                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0084)
+#define OMAP4430_CM_AUTOIDLE_DPLL_USB                   OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0088)
+#define OMAP4430_CM_CLKSEL_DPLL_USB                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x008c)
+#define OMAP4430_CM_DIV_M2_DPLL_USB                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0090)
+#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_USB             OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x00a8)
+#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_USB             OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x00ac)
+#define OMAP4430_CM_CLKDCOLDO_DPLL_USB                  OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x00b4)
+#define OMAP4430_CM_CLKMODE_DPLL_UNIPRO                 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x00c0)
+#define OMAP4430_CM_IDLEST_DPLL_UNIPRO                  OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x00c4)
+#define OMAP4430_CM_AUTOIDLE_DPLL_UNIPRO                OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x00c8)
+#define OMAP4430_CM_CLKSEL_DPLL_UNIPRO                  OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x00cc)
+#define OMAP4430_CM_DIV_M2_DPLL_UNIPRO                  OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x00d0)
+#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_UNIPRO          OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x00e8)
+#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_UNIPRO          OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x00ec)
+
+/* CM2.ALWAYS_ON_CM2 register offsets */
+#define OMAP4430_CM_ALWON_CLKSTCTRL                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_MOD, 0x0000)
+#define OMAP4430_CM_ALWON_MDMINTC_CLKCTRL               OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_MOD, 0x0020)
+#define OMAP4430_CM_ALWON_SR_MPU_CLKCTRL                OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_MOD, 0x0028)
+#define OMAP4430_CM_ALWON_SR_IVA_CLKCTRL                OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_MOD, 0x0030)
+#define OMAP4430_CM_ALWON_SR_CORE_CLKCTRL               OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_MOD, 0x0038)
+
+/* CM2.CORE_CM2 register offsets */
+#define OMAP4430_CM_L3_1_CLKSTCTRL                      OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0000)
+#define OMAP4430_CM_L3_1_DYNAMICDEP                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0008)
+#define OMAP4430_CM_L3_1_L3_1_CLKCTRL                   OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0020)
+#define OMAP4430_CM_L3_2_CLKSTCTRL                      OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0100)
+#define OMAP4430_CM_L3_2_DYNAMICDEP                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0108)
+#define OMAP4430_CM_L3_2_L3_2_CLKCTRL                   OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0120)
+#define OMAP4430_CM_L3_2_GPMC_CLKCTRL                   OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0128)
+#define OMAP4430_CM_L3_2_OCMC_RAM_CLKCTRL               OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0130)
+#define OMAP4430_CM_DUCATI_CLKSTCTRL                    OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0200)
+#define OMAP4430_CM_DUCATI_STATICDEP                    OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0204)
+#define OMAP4430_CM_DUCATI_DYNAMICDEP                   OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0208)
+#define OMAP4430_CM_DUCATI_DUCATI_CLKCTRL               OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0220)
+#define OMAP4430_CM_SDMA_CLKSTCTRL                      OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0300)
+#define OMAP4430_CM_SDMA_STATICDEP                      OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0304)
+#define OMAP4430_CM_SDMA_DYNAMICDEP                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0308)
+#define OMAP4430_CM_SDMA_SDMA_CLKCTRL                   OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0320)
+#define OMAP4430_CM_MEMIF_CLKSTCTRL                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0400)
+#define OMAP4430_CM_MEMIF_DMM_CLKCTRL                   OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0420)
+#define OMAP4430_CM_MEMIF_EMIF_FW_CLKCTRL               OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0428)
+#define OMAP4430_CM_MEMIF_EMIF_1_CLKCTRL                OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0430)
+#define OMAP4430_CM_MEMIF_EMIF_2_CLKCTRL                OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0438)
+#define OMAP4430_CM_MEMIF_DLL_CLKCTRL                   OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0440)
+#define OMAP4430_CM_MEMIF_EMIF_H1_CLKCTRL               OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0450)
+#define OMAP4430_CM_MEMIF_EMIF_H2_CLKCTRL               OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0458)
+#define OMAP4430_CM_MEMIF_DLL_H_CLKCTRL                 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0460)
+#define OMAP4430_CM_D2D_CLKSTCTRL                       OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0500)
+#define OMAP4430_CM_D2D_STATICDEP                       OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0504)
+#define OMAP4430_CM_D2D_DYNAMICDEP                      OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0508)
+#define OMAP4430_CM_D2D_SAD2D_CLKCTRL                   OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0520)
+#define OMAP4430_CM_D2D_MODEM_ICR_CLKCTRL               OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0528)
+#define OMAP4430_CM_D2D_SAD2D_FW_CLKCTRL                OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0530)
+#define OMAP4430_CM_L4CFG_CLKSTCTRL                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0600)
+#define OMAP4430_CM_L4CFG_DYNAMICDEP                    OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0608)
+#define OMAP4430_CM_L4CFG_L4_CFG_CLKCTRL                OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0620)
+#define OMAP4430_CM_L4CFG_HW_SEM_CLKCTRL                OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0628)
+#define OMAP4430_CM_L4CFG_MAILBOX_CLKCTRL               OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0630)
+#define OMAP4430_CM_L4CFG_SAR_ROM_CLKCTRL               OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0638)
+#define OMAP4430_CM_L3INSTR_CLKSTCTRL                   OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0700)
+#define OMAP4430_CM_L3INSTR_L3_3_CLKCTRL                OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0720)
+#define OMAP4430_CM_L3INSTR_L3_INSTR_CLKCTRL            OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0728)
+#define OMAP4430_CM_L3INSTR_OCP_WP1_CLKCTRL             OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0740)
+
+/* CM2.IVAHD_CM2 register offsets */
+#define OMAP4430_CM_IVAHD_CLKSTCTRL                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_IVAHD_MOD, 0x0000)
+#define OMAP4430_CM_IVAHD_STATICDEP                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_IVAHD_MOD, 0x0004)
+#define OMAP4430_CM_IVAHD_DYNAMICDEP                    OMAP44XX_CM2_REGADDR(OMAP4430_CM2_IVAHD_MOD, 0x0008)
+#define OMAP4430_CM_IVAHD_IVAHD_CLKCTRL                 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_IVAHD_MOD, 0x0020)
+#define OMAP4430_CM_IVAHD_SL2_CLKCTRL                   OMAP44XX_CM2_REGADDR(OMAP4430_CM2_IVAHD_MOD, 0x0028)
+
+/* CM2.CAM_CM2 register offsets */
+#define OMAP4430_CM_CAM_CLKSTCTRL                       OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CAM_MOD, 0x0000)
+#define OMAP4430_CM_CAM_STATICDEP                       OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CAM_MOD, 0x0004)
+#define OMAP4430_CM_CAM_DYNAMICDEP                      OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CAM_MOD, 0x0008)
+#define OMAP4430_CM_CAM_ISS_CLKCTRL                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CAM_MOD, 0x0020)
+#define OMAP4430_CM_CAM_FDIF_CLKCTRL                    OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CAM_MOD, 0x0028)
+
+/* CM2.DSS_CM2 register offsets */
+#define OMAP4430_CM_DSS_CLKSTCTRL                       OMAP44XX_CM2_REGADDR(OMAP4430_CM2_DSS_MOD, 0x0000)
+#define OMAP4430_CM_DSS_STATICDEP                       OMAP44XX_CM2_REGADDR(OMAP4430_CM2_DSS_MOD, 0x0004)
+#define OMAP4430_CM_DSS_DYNAMICDEP                      OMAP44XX_CM2_REGADDR(OMAP4430_CM2_DSS_MOD, 0x0008)
+#define OMAP4430_CM_DSS_DSS_CLKCTRL                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_DSS_MOD, 0x0020)
+#define OMAP4430_CM_DSS_DEISS_CLKCTRL                   OMAP44XX_CM2_REGADDR(OMAP4430_CM2_DSS_MOD, 0x0028)
+
+/* CM2.GFX_CM2 register offsets */
+#define OMAP4430_CM_GFX_CLKSTCTRL                       OMAP44XX_CM2_REGADDR(OMAP4430_CM2_GFX_MOD, 0x0000)
+#define OMAP4430_CM_GFX_STATICDEP                       OMAP44XX_CM2_REGADDR(OMAP4430_CM2_GFX_MOD, 0x0004)
+#define OMAP4430_CM_GFX_DYNAMICDEP                      OMAP44XX_CM2_REGADDR(OMAP4430_CM2_GFX_MOD, 0x0008)
+#define OMAP4430_CM_GFX_GFX_CLKCTRL                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_GFX_MOD, 0x0020)
+
+/* CM2.L3INIT_CM2 register offsets */
+#define OMAP4430_CM_L3INIT_CLKSTCTRL                    OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0000)
+#define OMAP4430_CM_L3INIT_STATICDEP                    OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0004)
+#define OMAP4430_CM_L3INIT_DYNAMICDEP                   OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0008)
+#define OMAP4430_CM_L3INIT_MMC1_CLKCTRL                 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0028)
+#define OMAP4430_CM_L3INIT_MMC2_CLKCTRL                 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0030)
+#define OMAP4430_CM_L3INIT_HSI_CLKCTRL                  OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0038)
+#define OMAP4430_CM_L3INIT_UNIPRO1_CLKCTRL              OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0040)
+#define OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL             OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0058)
+#define OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL              OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0060)
+#define OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL              OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0068)
+#define OMAP4430_CM_L3INIT_P1500_CLKCTRL                OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0078)
+#define OMAP4430_CM_L3INIT_EMAC_CLKCTRL                 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0080)
+#define OMAP4430_CM_L3INIT_SATA_CLKCTRL                 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0088)
+#define OMAP4430_CM_L3INIT_TPPSS_CLKCTRL                OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0090)
+#define OMAP4430_CM_L3INIT_PCIESS_CLKCTRL               OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0098)
+#define OMAP4430_CM_L3INIT_CCPTX_CLKCTRL                OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x00a8)
+#define OMAP4430_CM_L3INIT_XHPI_CLKCTRL                 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x00c0)
+#define OMAP4430_CM_L3INIT_MMC6_CLKCTRL                 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x00c8)
+#define OMAP4430_CM_L3INIT_USB_HOST_FS_CLKCTRL          OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x00d0)
+#define OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL        OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x00e0)
+
+/* CM2.L4PER_CM2 register offsets */
+#define OMAP4430_CM_L4PER_CLKSTCTRL                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0000)
+#define OMAP4430_CM_L4PER_DYNAMICDEP                    OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0008)
+#define OMAP4430_CM_L4PER_ADC_CLKCTRL                   OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0020)
+#define OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL             OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0028)
+#define OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL             OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0030)
+#define OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL              OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0038)
+#define OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL              OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0040)
+#define OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL              OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0048)
+#define OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL              OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0050)
+#define OMAP4430_CM_L4PER_ELM_CLKCTRL                   OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0058)
+#define OMAP4430_CM_L4PER_GPIO2_CLKCTRL                 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0060)
+#define OMAP4430_CM_L4PER_GPIO3_CLKCTRL                 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0068)
+#define OMAP4430_CM_L4PER_GPIO4_CLKCTRL                 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0070)
+#define OMAP4430_CM_L4PER_GPIO5_CLKCTRL                 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0078)
+#define OMAP4430_CM_L4PER_GPIO6_CLKCTRL                 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0080)
+#define OMAP4430_CM_L4PER_HDQ1W_CLKCTRL                 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0088)
+#define OMAP4430_CM_L4PER_HECC1_CLKCTRL                 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0090)
+#define OMAP4430_CM_L4PER_HECC2_CLKCTRL                 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0098)
+#define OMAP4430_CM_L4PER_I2C1_CLKCTRL                  OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x00a0)
+#define OMAP4430_CM_L4PER_I2C2_CLKCTRL                  OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x00a8)
+#define OMAP4430_CM_L4PER_I2C3_CLKCTRL                  OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x00b0)
+#define OMAP4430_CM_L4PER_I2C4_CLKCTRL                  OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x00b8)
+#define OMAP4430_CM_L4PER_L4PER_CLKCTRL                 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x00c0)
+#define OMAP4430_CM_L4PER_MCASP2_CLKCTRL                OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x00d0)
+#define OMAP4430_CM_L4PER_MCASP3_CLKCTRL                OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x00d8)
+#define OMAP4430_CM_L4PER_MCBSP4_CLKCTRL                OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x00e0)
+#define OMAP4430_CM_L4PER_MGATE_CLKCTRL                 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x00e8)
+#define OMAP4430_CM_L4PER_MCSPI1_CLKCTRL                OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x00f0)
+#define OMAP4430_CM_L4PER_MCSPI2_CLKCTRL                OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x00f8)
+#define OMAP4430_CM_L4PER_MCSPI3_CLKCTRL                OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0100)
+#define OMAP4430_CM_L4PER_MCSPI4_CLKCTRL                OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0108)
+#define OMAP4430_CM_L4PER_MMCSD3_CLKCTRL                OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0120)
+#define OMAP4430_CM_L4PER_MMCSD4_CLKCTRL                OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0128)
+#define OMAP4430_CM_L4PER_MSPROHG_CLKCTRL               OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0130)
+#define OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL              OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0138)
+#define OMAP4430_CM_L4PER_UART1_CLKCTRL                 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0140)
+#define OMAP4430_CM_L4PER_UART2_CLKCTRL                 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0148)
+#define OMAP4430_CM_L4PER_UART3_CLKCTRL                 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0150)
+#define OMAP4430_CM_L4PER_UART4_CLKCTRL                 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0158)
+#define OMAP4430_CM_L4PER_MMCSD5_CLKCTRL                OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0160)
+#define OMAP4430_CM_L4PER_I2C5_CLKCTRL                  OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0168)
+#define OMAP4430_CM_L4SEC_CLKSTCTRL                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0180)
+#define OMAP4430_CM_L4SEC_STATICDEP                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0184)
+#define OMAP4430_CM_L4SEC_DYNAMICDEP                    OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0188)
+#define OMAP4430_CM_L4SEC_AES1_CLKCTRL                  OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x01a0)
+#define OMAP4430_CM_L4SEC_AES2_CLKCTRL                  OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x01a8)
+#define OMAP4430_CM_L4SEC_DES3DES_CLKCTRL               OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x01b0)
+#define OMAP4430_CM_L4SEC_PKAEIP29_CLKCTRL              OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x01b8)
+#define OMAP4430_CM_L4SEC_RNG_CLKCTRL                   OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x01c0)
+#define OMAP4430_CM_L4SEC_SHA2MD51_CLKCTRL              OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x01c8)
+#define OMAP4430_CM_L4SEC_CRYPTODMA_CLKCTRL             OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x01d8)
+
+/* CM2.CEFUSE_CM2 register offsets */
+#define OMAP4430_CM_CEFUSE_CLKSTCTRL                    OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CEFUSE_MOD, 0x0000)
+#define OMAP4430_CM_CEFUSE_CEFUSE_CLKCTRL               OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CEFUSE_MOD, 0x0020)
+
+/* CM2.RESTORE_CM2 register offsets */
+#define OMAP4430_CM_L3_1_CLKSTCTRL_RESTORE              OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0000)
+#define OMAP4430_CM_L3_2_CLKSTCTRL_RESTORE              OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0004)
+#define OMAP4430_CM_L4CFG_CLKSTCTRL_RESTORE             OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0008)
+#define OMAP4430_CM_MEMIF_CLKSTCTRL_RESTORE             OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x000c)
+#define OMAP4430_CM_L4PER_CLKSTCTRL_RESTORE             OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0010)
+#define OMAP4430_CM_L3INIT_CLKSTCTRL_RESTORE            OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0014)
+#define OMAP4430_CM_L3INSTR_L3_3_CLKCTRL_RESTORE        OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0018)
+#define OMAP4430_CM_L3INSTR_L3_INSTR_CLKCTRL_RESTORE    OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x001c)
+#define OMAP4430_CM_L3INSTR_OCP_WP1_CLKCTRL_RESTORE     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0020)
+#define OMAP4430_CM_L4PER_GPIO2_CLKCTRL_RESTORE         OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0024)
+#define OMAP4430_CM_L4PER_GPIO3_CLKCTRL_RESTORE         OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0028)
+#define OMAP4430_CM_L4PER_GPIO4_CLKCTRL_RESTORE         OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x002c)
+#define OMAP4430_CM_L4PER_GPIO5_CLKCTRL_RESTORE         OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0030)
+#define OMAP4430_CM_L4PER_GPIO6_CLKCTRL_RESTORE         OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0034)
+#define OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL_RESTORE     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0038)
+#define OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL_RESTORE      OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x003c)
+#define OMAP4430_CM_SDMA_STATICDEP_RESTORE              OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0040)
+#endif
diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c
index 733d3dcff98b..18ad93160abb 100644
--- a/arch/arm/mach-omap2/devices.c
+++ b/arch/arm/mach-omap2/devices.c
@@ -27,6 +27,8 @@
 #include <mach/gpio.h>
 #include <plat/mmc.h>
 
+#include "mux.h"
+
 #if defined(CONFIG_VIDEO_OMAP2) || defined(CONFIG_VIDEO_OMAP2_MODULE)
 
 static struct resource cam_resources[] = {
@@ -595,27 +597,40 @@ static inline void omap2_mmc_mux(struct omap_mmc_platform_data *mmc_controller,
 
         if (cpu_is_omap34xx()) {
                 if (controller_nr == 0) {
-                        omap_cfg_reg(N28_3430_MMC1_CLK);
-                        omap_cfg_reg(M27_3430_MMC1_CMD);
-                        omap_cfg_reg(N27_3430_MMC1_DAT0);
+                        omap_mux_init_signal("sdmmc1_clk",
+                                OMAP_PIN_INPUT_PULLUP);
+                        omap_mux_init_signal("sdmmc1_cmd",
+                                OMAP_PIN_INPUT_PULLUP);
+                        omap_mux_init_signal("sdmmc1_dat0",
+                                OMAP_PIN_INPUT_PULLUP);
                         if (mmc_controller->slots[0].wires == 4 ||
                                 mmc_controller->slots[0].wires == 8) {
-                                omap_cfg_reg(N26_3430_MMC1_DAT1);
-                                omap_cfg_reg(N25_3430_MMC1_DAT2);
-                                omap_cfg_reg(P28_3430_MMC1_DAT3);
+                                omap_mux_init_signal("sdmmc1_dat1",
+                                        OMAP_PIN_INPUT_PULLUP);
+                                omap_mux_init_signal("sdmmc1_dat2",
+                                        OMAP_PIN_INPUT_PULLUP);
+                                omap_mux_init_signal("sdmmc1_dat3",
+                                        OMAP_PIN_INPUT_PULLUP);
                         }
                         if (mmc_controller->slots[0].wires == 8) {
-                                omap_cfg_reg(P27_3430_MMC1_DAT4);
-                                omap_cfg_reg(P26_3430_MMC1_DAT5);
-                                omap_cfg_reg(R27_3430_MMC1_DAT6);
-                                omap_cfg_reg(R25_3430_MMC1_DAT7);
+                                omap_mux_init_signal("sdmmc1_dat4",
+                                        OMAP_PIN_INPUT_PULLUP);
+                                omap_mux_init_signal("sdmmc1_dat5",
+                                        OMAP_PIN_INPUT_PULLUP);
+                                omap_mux_init_signal("sdmmc1_dat6",
+                                        OMAP_PIN_INPUT_PULLUP);
+                                omap_mux_init_signal("sdmmc1_dat7",
+                                        OMAP_PIN_INPUT_PULLUP);
                         }
                 }
                 if (controller_nr == 1) {
                         /* MMC2 */
-                        omap_cfg_reg(AE2_3430_MMC2_CLK);
-                        omap_cfg_reg(AG5_3430_MMC2_CMD);
-                        omap_cfg_reg(AH5_3430_MMC2_DAT0);
+                        omap_mux_init_signal("sdmmc2_clk",
+                                OMAP_PIN_INPUT_PULLUP);
+                        omap_mux_init_signal("sdmmc2_cmd",
+                                OMAP_PIN_INPUT_PULLUP);
+                        omap_mux_init_signal("sdmmc2_dat0",
+                                OMAP_PIN_INPUT_PULLUP);
 
                         /*
                          * For 8 wire configurations, Lines DAT4, 5, 6 and 7 need to be muxed
@@ -623,15 +638,22 @@ static inline void omap2_mmc_mux(struct omap_mmc_platform_data *mmc_controller,
                          */
                         if (mmc_controller->slots[0].wires == 4 ||
                                 mmc_controller->slots[0].wires == 8) {
-                                omap_cfg_reg(AH4_3430_MMC2_DAT1);
-                                omap_cfg_reg(AG4_3430_MMC2_DAT2);
-                                omap_cfg_reg(AF4_3430_MMC2_DAT3);
+                                omap_mux_init_signal("sdmmc2_dat1",
+                                        OMAP_PIN_INPUT_PULLUP);
+                                omap_mux_init_signal("sdmmc2_dat2",
+                                        OMAP_PIN_INPUT_PULLUP);
+                                omap_mux_init_signal("sdmmc2_dat3",
+                                        OMAP_PIN_INPUT_PULLUP);
                         }
                         if (mmc_controller->slots[0].wires == 8) {
-                                omap_cfg_reg(AE4_3430_MMC2_DAT4);
-                                omap_cfg_reg(AH3_3430_MMC2_DAT5);
-                                omap_cfg_reg(AF3_3430_MMC2_DAT6);
-                                omap_cfg_reg(AE3_3430_MMC2_DAT7);
+                                omap_mux_init_signal("sdmmc2_dat4.sdmmc2_dat4",
+                                        OMAP_PIN_INPUT_PULLUP);
+                                omap_mux_init_signal("sdmmc2_dat5.sdmmc2_dat5",
+                                        OMAP_PIN_INPUT_PULLUP);
+                                omap_mux_init_signal("sdmmc2_dat6.sdmmc2_dat6",
+                                        OMAP_PIN_INPUT_PULLUP);
+                                omap_mux_init_signal("sdmmc2_dat7.sdmmc2_dat7",
+                                        OMAP_PIN_INPUT_PULLUP);
                         }
                 }
 
diff --git a/arch/arm/mach-omap2/dpll.c b/arch/arm/mach-omap2/dpll.c
new file mode 100644
index 000000000000..f6055b493294
--- /dev/null
+++ b/arch/arm/mach-omap2/dpll.c
@@ -0,0 +1,538 @@
+/*
+ * OMAP3/4 - specific DPLL control functions
+ *
+ * Copyright (C) 2009 Texas Instruments, Inc.
+ * Copyright (C) 2009 Nokia Corporation
+ *
+ * Written by Paul Walmsley
+ * Testing and integration fixes by Jouni Högander
+ *
+ * Parts of this code are based on code written by
+ * Richard Woodruff, Tony Lindgren, Tuukka Tikkanen, Karthik Dasu
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/device.h>
+#include <linux/list.h>
+#include <linux/errno.h>
+#include <linux/delay.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/limits.h>
+#include <linux/bitops.h>
+
+#include <plat/cpu.h>
+#include <plat/clock.h>
+#include <plat/sram.h>
+#include <asm/div64.h>
+#include <asm/clkdev.h>
+
+#include "clock.h"
+#include "prm.h"
+#include "prm-regbits-34xx.h"
+#include "cm.h"
+#include "cm-regbits-34xx.h"
+
+/* CM_AUTOIDLE_PLL*.AUTO_* bit values */
+#define DPLL_AUTOIDLE_DISABLE                   0x0
+#define DPLL_AUTOIDLE_LOW_POWER_STOP            0x1
+
+#define MAX_DPLL_WAIT_TRIES             1000000
+
+
+/**
+ * omap3_dpll_recalc - recalculate DPLL rate
+ * @clk: DPLL struct clk
+ *
+ * Recalculate and propagate the DPLL rate.
+ */
+unsigned long omap3_dpll_recalc(struct clk *clk)
+{
+        return omap2_get_dpll_rate(clk);
+}
+
+/* _omap3_dpll_write_clken - write clken_bits arg to a DPLL's enable bits */
+static void _omap3_dpll_write_clken(struct clk *clk, u8 clken_bits)
+{
+        const struct dpll_data *dd;
+        u32 v;
+
+        dd = clk->dpll_data;
+
+        v = __raw_readl(dd->control_reg);
+        v &= ~dd->enable_mask;
+        v |= clken_bits << __ffs(dd->enable_mask);
+        __raw_writel(v, dd->control_reg);
+}
+
+/* _omap3_wait_dpll_status: wait for a DPLL to enter a specific state */
+static int _omap3_wait_dpll_status(struct clk *clk, u8 state)
+{
+        const struct dpll_data *dd;
+        int i = 0;
+        int ret = -EINVAL;
+
+        dd = clk->dpll_data;
+
+        state <<= __ffs(dd->idlest_mask);
+
+        while (((__raw_readl(dd->idlest_reg) & dd->idlest_mask) != state) &&
+               i < MAX_DPLL_WAIT_TRIES) {
+                i++;
+                udelay(1);
+        }
+
+        if (i == MAX_DPLL_WAIT_TRIES) {
+                printk(KERN_ERR "clock: %s failed transition to '%s'\n",
+                       clk->name, (state) ? "locked" : "bypassed");
+        } else {
+                pr_debug("clock: %s transition to '%s' in %d loops\n",
+                         clk->name, (state) ? "locked" : "bypassed", i);
+
+                ret = 0;
+        }
+
+        return ret;
+}
+
+/* From 3430 TRM ES2 4.7.6.2 */
+static u16 _omap3_dpll_compute_freqsel(struct clk *clk, u8 n)
+{
+        unsigned long fint;
+        u16 f = 0;
+
+        fint = clk->dpll_data->clk_ref->rate / n;
+
+        pr_debug("clock: fint is %lu\n", fint);
+
+        if (fint >= 750000 && fint <= 1000000)
+                f = 0x3;
+        else if (fint > 1000000 && fint <= 1250000)
+                f = 0x4;
+        else if (fint > 1250000 && fint <= 1500000)
+                f = 0x5;
+        else if (fint > 1500000 && fint <= 1750000)
+                f = 0x6;
+        else if (fint > 1750000 && fint <= 2100000)
+                f = 0x7;
+        else if (fint > 7500000 && fint <= 10000000)
+                f = 0xB;
+        else if (fint > 10000000 && fint <= 12500000)
+                f = 0xC;
+        else if (fint > 12500000 && fint <= 15000000)
+                f = 0xD;
+        else if (fint > 15000000 && fint <= 17500000)
+                f = 0xE;
+        else if (fint > 17500000 && fint <= 21000000)
+                f = 0xF;
+        else
+                pr_debug("clock: unknown freqsel setting for %d\n", n);
+
+        return f;
+}
+
+/* Non-CORE DPLL (e.g., DPLLs that do not control SDRC) clock functions */
+
+/*
+ * _omap3_noncore_dpll_lock - instruct a DPLL to lock and wait for readiness
+ * @clk: pointer to a DPLL struct clk
+ *
+ * Instructs a non-CORE DPLL to lock.  Waits for the DPLL to report
+ * readiness before returning.  Will save and restore the DPLL's
+ * autoidle state across the enable, per the CDP code.  If the DPLL
+ * locked successfully, return 0; if the DPLL did not lock in the time
+ * allotted, or DPLL3 was passed in, return -EINVAL.
+ */
+static int _omap3_noncore_dpll_lock(struct clk *clk)
+{
+        u8 ai;
+        int r;
+
+        pr_debug("clock: locking DPLL %s\n", clk->name);
+
+        ai = omap3_dpll_autoidle_read(clk);
+
+        omap3_dpll_deny_idle(clk);
+
+        _omap3_dpll_write_clken(clk, DPLL_LOCKED);
+
+        r = _omap3_wait_dpll_status(clk, 1);
+
+        if (ai)
+                omap3_dpll_allow_idle(clk);
+
+        return r;
+}
+
+/*
+ * _omap3_noncore_dpll_bypass - instruct a DPLL to bypass and wait for readiness
+ * @clk: pointer to a DPLL struct clk
+ *
+ * Instructs a non-CORE DPLL to enter low-power bypass mode.  In
+ * bypass mode, the DPLL's rate is set equal to its parent clock's
+ * rate.  Waits for the DPLL to report readiness before returning.
+ * Will save and restore the DPLL's autoidle state across the enable,
+ * per the CDP code.  If the DPLL entered bypass mode successfully,
+ * return 0; if the DPLL did not enter bypass in the time allotted, or
+ * DPLL3 was passed in, or the DPLL does not support low-power bypass,
+ * return -EINVAL.
+ */
+static int _omap3_noncore_dpll_bypass(struct clk *clk)
+{
+        int r;
+        u8 ai;
+
+        if (!(clk->dpll_data->modes & (1 << DPLL_LOW_POWER_BYPASS)))
+                return -EINVAL;
+
+        pr_debug("clock: configuring DPLL %s for low-power bypass\n",
+                 clk->name);
+
+        ai = omap3_dpll_autoidle_read(clk);
+
+        _omap3_dpll_write_clken(clk, DPLL_LOW_POWER_BYPASS);
+
+        r = _omap3_wait_dpll_status(clk, 0);
+
+        if (ai)
+                omap3_dpll_allow_idle(clk);
+        else
+                omap3_dpll_deny_idle(clk);
+
+        return r;
+}
+
+/*
+ * _omap3_noncore_dpll_stop - instruct a DPLL to stop
+ * @clk: pointer to a DPLL struct clk
+ *
+ * Instructs a non-CORE DPLL to enter low-power stop. Will save and
+ * restore the DPLL's autoidle state across the stop, per the CDP
+ * code.  If DPLL3 was passed in, or the DPLL does not support
+ * low-power stop, return -EINVAL; otherwise, return 0.
+ */
+static int _omap3_noncore_dpll_stop(struct clk *clk)
+{
+        u8 ai;
+
+        if (!(clk->dpll_data->modes & (1 << DPLL_LOW_POWER_STOP)))
+                return -EINVAL;
+
+        pr_debug("clock: stopping DPLL %s\n", clk->name);
+
+        ai = omap3_dpll_autoidle_read(clk);
+
+        _omap3_dpll_write_clken(clk, DPLL_LOW_POWER_STOP);
+
+        if (ai)
+                omap3_dpll_allow_idle(clk);
+        else
+                omap3_dpll_deny_idle(clk);
+
+        return 0;
+}
+
+/**
+ * omap3_noncore_dpll_enable - instruct a DPLL to enter bypass or lock mode
+ * @clk: pointer to a DPLL struct clk
+ *
+ * Instructs a non-CORE DPLL to enable, e.g., to enter bypass or lock.
+ * The choice of modes depends on the DPLL's programmed rate: if it is
+ * the same as the DPLL's parent clock, it will enter bypass;
+ * otherwise, it will enter lock.  This code will wait for the DPLL to
+ * indicate readiness before returning, unless the DPLL takes too long
+ * to enter the target state.  Intended to be used as the struct clk's
+ * enable function.  If DPLL3 was passed in, or the DPLL does not
+ * support low-power stop, or if the DPLL took too long to enter
+ * bypass or lock, return -EINVAL; otherwise, return 0.
+ */
+int omap3_noncore_dpll_enable(struct clk *clk)
+{
+        int r;
+        struct dpll_data *dd;
+
+        dd = clk->dpll_data;
+        if (!dd)
+                return -EINVAL;
+
+        if (clk->rate == dd->clk_bypass->rate) {
+                WARN_ON(clk->parent != dd->clk_bypass);
+                r = _omap3_noncore_dpll_bypass(clk);
+        } else {
+                WARN_ON(clk->parent != dd->clk_ref);
+                r = _omap3_noncore_dpll_lock(clk);
+        }
+        /*
+         *FIXME: this is dubious - if clk->rate has changed, what about
+         * propagating?
+         */
+        if (!r)
+                clk->rate = omap2_get_dpll_rate(clk);
+
+        return r;
+}
+
+/**
+ * omap3_noncore_dpll_disable - instruct a DPLL to enter low-power stop
+ * @clk: pointer to a DPLL struct clk
+ *
+ * Instructs a non-CORE DPLL to enter low-power stop.  This function is
+ * intended for use in struct clkops.  No return value.
+ */
+void omap3_noncore_dpll_disable(struct clk *clk)
+{
+        _omap3_noncore_dpll_stop(clk);
+}
+
+
+/* Non-CORE DPLL rate set code */
+
+/*
+ * omap3_noncore_dpll_program - set non-core DPLL M,N values directly
+ * @clk: struct clk * of DPLL to set
+ * @m: DPLL multiplier to set
+ * @n: DPLL divider to set
+ * @freqsel: FREQSEL value to set
+ *
+ * Program the DPLL with the supplied M, N values, and wait for the DPLL to
+ * lock..  Returns -EINVAL upon error, or 0 upon success.
+ */
+int omap3_noncore_dpll_program(struct clk *clk, u16 m, u8 n, u16 freqsel)
+{
+        struct dpll_data *dd = clk->dpll_data;
+        u32 v;
+
+        /* 3430 ES2 TRM: 4.7.6.9 DPLL Programming Sequence */
+        _omap3_noncore_dpll_bypass(clk);
+
+        /* Set jitter correction */
+        if (!cpu_is_omap44xx()) {
+                v = __raw_readl(dd->control_reg);
+                v &= ~dd->freqsel_mask;
+                v |= freqsel << __ffs(dd->freqsel_mask);
+                __raw_writel(v, dd->control_reg);
+        }
+
+        /* Set DPLL multiplier, divider */
+        v = __raw_readl(dd->mult_div1_reg);
+        v &= ~(dd->mult_mask | dd->div1_mask);
+        v |= m << __ffs(dd->mult_mask);
+        v |= (n - 1) << __ffs(dd->div1_mask);
+        __raw_writel(v, dd->mult_div1_reg);
+
+        /* We let the clock framework set the other output dividers later */
+
+        /* REVISIT: Set ramp-up delay? */
+
+        _omap3_noncore_dpll_lock(clk);
+
+        return 0;
+}
+
+/**
+ * omap3_noncore_dpll_set_rate - set non-core DPLL rate
+ * @clk: struct clk * of DPLL to set
+ * @rate: rounded target rate
+ *
+ * Set the DPLL CLKOUT to the target rate.  If the DPLL can enter
+ * low-power bypass, and the target rate is the bypass source clock
+ * rate, then configure the DPLL for bypass.  Otherwise, round the
+ * target rate if it hasn't been done already, then program and lock
+ * the DPLL.  Returns -EINVAL upon error, or 0 upon success.
+ */
+int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate)
+{
+        struct clk *new_parent = NULL;
+        u16 freqsel = 0;
+        struct dpll_data *dd;
+        int ret;
+
+        if (!clk || !rate)
+                return -EINVAL;
+
+        dd = clk->dpll_data;
+        if (!dd)
+                return -EINVAL;
+
+        if (rate == omap2_get_dpll_rate(clk))
+                return 0;
+
+        /*
+         * Ensure both the bypass and ref clocks are enabled prior to
+         * doing anything; we need the bypass clock running to reprogram
+         * the DPLL.
+         */
+        omap2_clk_enable(dd->clk_bypass);
+        omap2_clk_enable(dd->clk_ref);
+
+        if (dd->clk_bypass->rate == rate &&
+            (clk->dpll_data->modes & (1 << DPLL_LOW_POWER_BYPASS))) {
+                pr_debug("clock: %s: set rate: entering bypass.\n", clk->name);
+
+                ret = _omap3_noncore_dpll_bypass(clk);
+                if (!ret)
+                        new_parent = dd->clk_bypass;
+        } else {
+                if (dd->last_rounded_rate != rate)
+                        omap2_dpll_round_rate(clk, rate);
+
+                if (dd->last_rounded_rate == 0)
+                        return -EINVAL;
+
+                /* No freqsel on OMAP4 */
+                if (!cpu_is_omap44xx()) {
+                        freqsel = _omap3_dpll_compute_freqsel(clk,
+                                                dd->last_rounded_n);
+                        if (!freqsel)
+                                WARN_ON(1);
+                }
+
+                pr_debug("clock: %s: set rate: locking rate to %lu.\n",
+                         clk->name, rate);
+
+                ret = omap3_noncore_dpll_program(clk, dd->last_rounded_m,
+                                                 dd->last_rounded_n, freqsel);
+                if (!ret)
+                        new_parent = dd->clk_ref;
+        }
+        if (!ret) {
+                /*
+                 * Switch the parent clock in the heirarchy, and make sure
+                 * that the new parent's usecount is correct.  Note: we
+                 * enable the new parent before disabling the old to avoid
+                 * any unnecessary hardware disable->enable transitions.
+                 */
+                if (clk->usecount) {
+                        omap2_clk_enable(new_parent);
+                        omap2_clk_disable(clk->parent);
+                }
+                clk_reparent(clk, new_parent);
+                clk->rate = rate;
+        }
+        omap2_clk_disable(dd->clk_ref);
+        omap2_clk_disable(dd->clk_bypass);
+
+        return 0;
+}
+
+/* DPLL autoidle read/set code */
+
+/**
+ * omap3_dpll_autoidle_read - read a DPLL's autoidle bits
+ * @clk: struct clk * of the DPLL to read
+ *
+ * Return the DPLL's autoidle bits, shifted down to bit 0.  Returns
+ * -EINVAL if passed a null pointer or if the struct clk does not
+ * appear to refer to a DPLL.
+ */
+u32 omap3_dpll_autoidle_read(struct clk *clk)
+{
+        const struct dpll_data *dd;
+        u32 v;
+
+        if (!clk || !clk->dpll_data)
+                return -EINVAL;
+
+        dd = clk->dpll_data;
+
+        v = __raw_readl(dd->autoidle_reg);
+        v &= dd->autoidle_mask;
+        v >>= __ffs(dd->autoidle_mask);
+
+        return v;
+}
+
+/**
+ * omap3_dpll_allow_idle - enable DPLL autoidle bits
+ * @clk: struct clk * of the DPLL to operate on
+ *
+ * Enable DPLL automatic idle control.  This automatic idle mode
+ * switching takes effect only when the DPLL is locked, at least on
+ * OMAP3430.  The DPLL will enter low-power stop when its downstream
+ * clocks are gated.  No return value.
+ */
+void omap3_dpll_allow_idle(struct clk *clk)
+{
+        const struct dpll_data *dd;
+        u32 v;
+
+        if (!clk || !clk->dpll_data)
+                return;
+
+        dd = clk->dpll_data;
+
+        /*
+         * REVISIT: CORE DPLL can optionally enter low-power bypass
+         * by writing 0x5 instead of 0x1.  Add some mechanism to
+         * optionally enter this mode.
+         */
+        v = __raw_readl(dd->autoidle_reg);
+        v &= ~dd->autoidle_mask;
+        v |= DPLL_AUTOIDLE_LOW_POWER_STOP << __ffs(dd->autoidle_mask);
+        __raw_writel(v, dd->autoidle_reg);
+}
+
+/**
+ * omap3_dpll_deny_idle - prevent DPLL from automatically idling
+ * @clk: struct clk * of the DPLL to operate on
+ *
+ * Disable DPLL automatic idle control.  No return value.
+ */
+void omap3_dpll_deny_idle(struct clk *clk)
+{
+        const struct dpll_data *dd;
+        u32 v;
+
+        if (!clk || !clk->dpll_data)
+                return;
+
+        dd = clk->dpll_data;
+
+        v = __raw_readl(dd->autoidle_reg);
+        v &= ~dd->autoidle_mask;
+        v |= DPLL_AUTOIDLE_DISABLE << __ffs(dd->autoidle_mask);
+        __raw_writel(v, dd->autoidle_reg);
+
+}
+
+/* Clock control for DPLL outputs */
+
+/**
+ * omap3_clkoutx2_recalc - recalculate DPLL X2 output virtual clock rate
+ * @clk: DPLL output struct clk
+ *
+ * Using parent clock DPLL data, look up DPLL state.  If locked, set our
+ * rate to the dpll_clk * 2; otherwise, just use dpll_clk.
+ */
+unsigned long omap3_clkoutx2_recalc(struct clk *clk)
+{
+        const struct dpll_data *dd;
+        unsigned long rate;
+        u32 v;
+        struct clk *pclk;
+
+        /* Walk up the parents of clk, looking for a DPLL */
+        pclk = clk->parent;
+        while (pclk && !pclk->dpll_data)
+                pclk = pclk->parent;
+
+        /* clk does not have a DPLL as a parent? */
+        WARN_ON(!pclk);
+
+        dd = pclk->dpll_data;
+
+        WARN_ON(!dd->enable_mask);
+
+        v = __raw_readl(dd->control_reg) & dd->enable_mask;
+        v >>= __ffs(dd->enable_mask);
+        if (v != OMAP3XXX_EN_DPLL_LOCKED)
+                rate = clk->parent->rate;
+        else
+                rate = clk->parent->rate * 2;
+        return rate;
+}
diff --git a/arch/arm/mach-omap2/gpmc-smc91x.c b/arch/arm/mach-omap2/gpmc-smc91x.c
index 6083e21b3be6..877c6f5807b7 100644
--- a/arch/arm/mach-omap2/gpmc-smc91x.c
+++ b/arch/arm/mach-omap2/gpmc-smc91x.c
@@ -33,17 +33,19 @@ static struct resource gpmc_smc91x_resources[] = {
 };
 
 static struct smc91x_platdata gpmc_smc91x_info = {
-        .flags  = SMC91X_USE_16BIT | SMC91X_NOWAIT | SMC91X_IO_SHIFT_0,
+        .flags  = SMC91X_USE_16BIT | SMC91X_NOWAIT | SMC91X_IO_SHIFT_0,
+        .leda   = RPC_LED_100_10,
+        .ledb   = RPC_LED_TX_RX,
 };
 
 static struct platform_device gpmc_smc91x_device = {
         .name           = "smc91x",
         .id             = -1,
-        .num_resources  = ARRAY_SIZE(gpmc_smc91x_resources),
-        .resource       = gpmc_smc91x_resources,
         .dev            = {
                 .platform_data = &gpmc_smc91x_info,
         },
+        .num_resources  = ARRAY_SIZE(gpmc_smc91x_resources),
+        .resource       = gpmc_smc91x_resources,
 };
 
 /*
diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c
index e86f5ca180ea..bd8cb5974726 100644
--- a/arch/arm/mach-omap2/gpmc.c
+++ b/arch/arm/mach-omap2/gpmc.c
@@ -517,7 +517,7 @@ void __init gpmc_init(void)
                 ck = "gpmc_fck";
                 l = OMAP34XX_GPMC_BASE;
         } else if (cpu_is_omap44xx()) {
-                ck = "gpmc_fck";
+                ck = "gpmc_ck";
                 l = OMAP44XX_GPMC_BASE;
         }
 
diff --git a/arch/arm/mach-omap2/i2c.c b/arch/arm/mach-omap2/i2c.c
new file mode 100644
index 000000000000..789ca8c02f0c
--- /dev/null
+++ b/arch/arm/mach-omap2/i2c.c
@@ -0,0 +1,56 @@
+/*
+ * Helper module for board specific I2C bus registration
+ *
+ * Copyright (C) 2009 Nokia Corporation.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
+ * 02110-1301 USA
+ *
+ */
+
+#include <plat/cpu.h>
+#include <plat/i2c.h>
+#include <plat/mux.h>
+
+#include "mux.h"
+
+int __init omap_register_i2c_bus(int bus_id, u32 clkrate,
+                          struct i2c_board_info const *info,
+                          unsigned len)
+{
+        if (cpu_is_omap24xx()) {
+                const int omap24xx_pins[][2] = {
+                        { M19_24XX_I2C1_SCL, L15_24XX_I2C1_SDA },
+                        { J15_24XX_I2C2_SCL, H19_24XX_I2C2_SDA },
+                };
+                int scl, sda;
+
+                scl = omap24xx_pins[bus_id - 1][0];
+                sda = omap24xx_pins[bus_id - 1][1];
+                omap_cfg_reg(sda);
+                omap_cfg_reg(scl);
+        }
+
+        /* First I2C bus is not muxable */
+        if (cpu_is_omap34xx() && bus_id > 1) {
+                char mux_name[sizeof("i2c2_scl.i2c2_scl")];
+
+                sprintf(mux_name, "i2c%i_scl.i2c%i_scl", bus_id, bus_id);
+                omap_mux_init_signal(mux_name, OMAP_PIN_INPUT);
+                sprintf(mux_name, "i2c%i_sda.i2c%i_sda", bus_id, bus_id);
+                omap_mux_init_signal(mux_name, OMAP_PIN_INPUT);
+        }
+
+        return omap_plat_register_i2c_bus(bus_id, clkrate, info, len);
+}
diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c
index f48a4b2654dd..a091b53657b9 100644
--- a/arch/arm/mach-omap2/id.c
+++ b/arch/arm/mach-omap2/id.c
@@ -246,6 +246,31 @@ void __init omap3_check_revision(void)
         }
 }
 
+void __init omap4_check_revision(void)
+{
+        u32 idcode;
+        u16 hawkeye;
+        u8 rev;
+        char *rev_name = "ES1.0";
+
+        /*
+         * The IC rev detection is done with hawkeye and rev.
+         * Note that rev does not map directly to defined processor
+         * revision numbers as ES1.0 uses value 0.
+         */
+        idcode = read_tap_reg(OMAP_TAP_IDCODE);
+        hawkeye = (idcode >> 12) & 0xffff;
+        rev = (idcode >> 28) & 0xff;
+
+        if ((hawkeye == 0xb852) && (rev == 0x0)) {
+                omap_revision = OMAP4430_REV_ES1_0;
+                pr_info("OMAP%04x %s\n", omap_rev() >> 16, rev_name);
+                return;
+        }
+
+        pr_err("Unknown OMAP4 CPU id\n");
+}
+
 #define OMAP3_SHOW_FEATURE(feat)                \
         if (omap3_has_ ##feat())                \
                 printk(#feat" ");
@@ -277,10 +302,10 @@ void __init omap3_cpuinfo(void)
         } else if (omap3_has_iva() && omap3_has_sgx()) {
                 /* OMAP3430, OMAP3525, OMAP3515, OMAP3503 devices */
                 strcpy(cpu_name, "OMAP3430/3530");
-        } else if (omap3_has_sgx()) {
+        } else if (omap3_has_iva()) {
                 omap_revision = OMAP3525_REV(rev);
                 strcpy(cpu_name, "OMAP3525");
-        } else if (omap3_has_iva()) {
+        } else if (omap3_has_sgx()) {
                 omap_revision = OMAP3515_REV(rev);
                 strcpy(cpu_name, "OMAP3515");
         } else {
@@ -336,7 +361,7 @@ void __init omap2_check_revision(void)
                 omap3_check_features();
                 omap3_cpuinfo();
         } else if (cpu_is_omap44xx()) {
-                printk(KERN_INFO "FIXME: CPU revision = OMAP4430\n");
+                omap4_check_revision();
                 return;
         } else {
                 pr_err("OMAP revision unknown, please fix!\n");
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index 6a4d8e468703..a8749e8017b9 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -33,9 +33,9 @@
 #include <plat/sdrc.h>
 #include <plat/gpmc.h>
 #include <plat/serial.h>
+#include <plat/mux.h>
 #include <plat/vram.h>
 
-#ifndef CONFIG_ARCH_OMAP4       /* FIXME: Remove this once clkdev is ready */
 #include "clock.h"
 
 #include <plat/omap-pm.h>
@@ -44,7 +44,6 @@
 
 #include <plat/clockdomain.h>
 #include "clockdomains.h"
-#endif
 #include <plat/omap_hwmod.h>
 #include "omap_hwmod_2420.h"
 #include "omap_hwmod_2430.h"
@@ -321,8 +320,8 @@ void __init omap2_init_common_hw(struct omap_sdrc_params *sdrc_cs0,
         omap_pm_if_early_init(mpu_opps, dsp_opps, l3_opps);
         pwrdm_init(powerdomains_omap);
         clkdm_init(clockdomains_omap, clkdm_pwrdm_autodeps);
-        omap2_clk_init();
 #endif
+        omap2_clk_init();
         omap_serial_early_init();
 #ifndef CONFIG_ARCH_OMAP4
         omap_hwmod_late_init();
diff --git a/arch/arm/mach-omap2/mux.c b/arch/arm/mach-omap2/mux.c
index c18a94eca641..e071b3fd1878 100644
--- a/arch/arm/mach-omap2/mux.c
+++ b/arch/arm/mach-omap2/mux.c
@@ -27,19 +27,52 @@
 #include <linux/init.h>
 #include <linux/io.h>
 #include <linux/spinlock.h>
+#include <linux/list.h>
+#include <linux/ctype.h>
+#include <linux/debugfs.h>
+#include <linux/seq_file.h>
+#include <linux/uaccess.h>
 
 #include <asm/system.h>
 
 #include <plat/control.h>
 #include <plat/mux.h>
 
-#ifdef CONFIG_OMAP_MUX
+#include "mux.h"
+
+#define OMAP_MUX_BASE_OFFSET            0x30    /* Offset from CTRL_BASE */
+#define OMAP_MUX_BASE_SZ                0x5ca
+
+struct omap_mux_entry {
+        struct omap_mux         mux;
+        struct list_head        node;
+};
+
+static unsigned long mux_phys;
+static void __iomem *mux_base;
+
+static inline u16 omap_mux_read(u16 reg)
+{
+        if (cpu_is_omap24xx())
+                return __raw_readb(mux_base + reg);
+        else
+                return __raw_readw(mux_base + reg);
+}
+
+static inline void omap_mux_write(u16 val, u16 reg)
+{
+        if (cpu_is_omap24xx())
+                __raw_writeb(val, mux_base + reg);
+        else
+                __raw_writew(val, mux_base + reg);
+}
+
+#if defined(CONFIG_ARCH_OMAP24XX) && defined(CONFIG_OMAP_MUX)
 
 static struct omap_mux_cfg arch_mux_cfg;
 
 /* NOTE: See mux.h for the enumeration */
 
-#ifdef CONFIG_ARCH_OMAP24XX
 static struct pin_config __initdata_or_module omap24xx_pins[] = {
 /*
  *      description                     mux     mux     pull    pull    debug
@@ -249,342 +282,14 @@ MUX_CFG_24XX("AF19_2430_GPIO_85",	0x0113,	3,	0,	0,	1)
 
 #define OMAP24XX_PINS_SZ        ARRAY_SIZE(omap24xx_pins)
 
-#else
-#define omap24xx_pins           NULL
-#define OMAP24XX_PINS_SZ        0
-#endif  /* CONFIG_ARCH_OMAP24XX */
-
-#ifdef CONFIG_ARCH_OMAP34XX
-static struct pin_config __initdata_or_module omap34xx_pins[] = {
-/*
- *              Name, reg-offset,
- *              mux-mode | [active-mode | off-mode]
- */
-
-/* 34xx I2C */
-MUX_CFG_34XX("K21_34XX_I2C1_SCL", 0x1ba,
-                OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
-MUX_CFG_34XX("J21_34XX_I2C1_SDA", 0x1bc,
-                OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
-MUX_CFG_34XX("AF15_34XX_I2C2_SCL", 0x1be,
-                OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
-MUX_CFG_34XX("AE15_34XX_I2C2_SDA", 0x1c0,
-                OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
-MUX_CFG_34XX("AF14_34XX_I2C3_SCL", 0x1c2,
-                OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
-MUX_CFG_34XX("AG14_34XX_I2C3_SDA", 0x1c4,
-                OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
-MUX_CFG_34XX("AD26_34XX_I2C4_SCL", 0xa00,
-                OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
-MUX_CFG_34XX("AE26_34XX_I2C4_SDA", 0xa02,
-                OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
-
-/* PHY - HSUSB: 12-pin ULPI PHY: Port 1*/
-MUX_CFG_34XX("Y8_3430_USB1HS_PHY_CLK", 0x5da,
-                OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_OUTPUT)
-MUX_CFG_34XX("Y9_3430_USB1HS_PHY_STP", 0x5d8,
-                OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_OUTPUT)
-MUX_CFG_34XX("AA14_3430_USB1HS_PHY_DIR", 0x5ec,
-                OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
-MUX_CFG_34XX("AA11_3430_USB1HS_PHY_NXT", 0x5ee,
-                OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
-MUX_CFG_34XX("W13_3430_USB1HS_PHY_D0", 0x5dc,
-                OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
-MUX_CFG_34XX("W12_3430_USB1HS_PHY_D1", 0x5de,
-                OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
-MUX_CFG_34XX("W11_3430_USB1HS_PHY_D2", 0x5e0,
-                OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
-MUX_CFG_34XX("Y11_3430_USB1HS_PHY_D3", 0x5ea,
-                OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
-MUX_CFG_34XX("W9_3430_USB1HS_PHY_D4", 0x5e4,
-                OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
-MUX_CFG_34XX("Y12_3430_USB1HS_PHY_D5", 0x5e6,
-                OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
-MUX_CFG_34XX("W8_3430_USB1HS_PHY_D6", 0x5e8,
-                OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
-MUX_CFG_34XX("Y13_3430_USB1HS_PHY_D7", 0x5e2,
-                OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
-
-/* PHY - HSUSB: 12-pin ULPI PHY: Port 2*/
-MUX_CFG_34XX("AA8_3430_USB2HS_PHY_CLK", 0x5f0,
-                OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_OUTPUT)
-MUX_CFG_34XX("AA10_3430_USB2HS_PHY_STP", 0x5f2,
-                OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_OUTPUT)
-MUX_CFG_34XX("AA9_3430_USB2HS_PHY_DIR", 0x5f4,
-                OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
-MUX_CFG_34XX("AB11_3430_USB2HS_PHY_NXT", 0x5f6,
-                OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
-MUX_CFG_34XX("AB10_3430_USB2HS_PHY_D0", 0x5f8,
-                OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
-MUX_CFG_34XX("AB9_3430_USB2HS_PHY_D1", 0x5fa,
-                OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
-MUX_CFG_34XX("W3_3430_USB2HS_PHY_D2", 0x1d4,
-                OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
-MUX_CFG_34XX("T4_3430_USB2HS_PHY_D3", 0x1de,
-                OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
-MUX_CFG_34XX("T3_3430_USB2HS_PHY_D4", 0x1d8,
-                OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
-MUX_CFG_34XX("R3_3430_USB2HS_PHY_D5", 0x1da,
-                OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
-MUX_CFG_34XX("R4_3430_USB2HS_PHY_D6", 0x1dc,
-                OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
-MUX_CFG_34XX("T2_3430_USB2HS_PHY_D7", 0x1d6,
-                OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
-
-/* TLL - HSUSB: 12-pin TLL Port 1*/
-MUX_CFG_34XX("Y8_3430_USB1HS_TLL_CLK", 0x5da,
-                OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
-MUX_CFG_34XX("Y9_3430_USB1HS_TLL_STP", 0x5d8,
-                OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLUP)
-MUX_CFG_34XX("AA14_3430_USB1HS_TLL_DIR", 0x5ec,
-                OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
-MUX_CFG_34XX("AA11_3430_USB1HS_TLL_NXT", 0x5ee,
-                OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
-MUX_CFG_34XX("W13_3430_USB1HS_TLL_D0", 0x5dc,
-                OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
-MUX_CFG_34XX("W12_3430_USB1HS_TLL_D1", 0x5de,
-                OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
-MUX_CFG_34XX("W11_3430_USB1HS_TLL_D2", 0x5e0,
-                OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
-MUX_CFG_34XX("Y11_3430_USB1HS_TLL_D3", 0x5ea,
-                OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
-MUX_CFG_34XX("W9_3430_USB1HS_TLL_D4", 0x5e4,
-                OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
-MUX_CFG_34XX("Y12_3430_USB1HS_TLL_D5", 0x5e6,
-                OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
-MUX_CFG_34XX("W8_3430_USB1HS_TLL_D6", 0x5e8,
-                OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
-MUX_CFG_34XX("Y13_3430_USB1HS_TLL_D7", 0x5e2,
-                OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
-
-/* TLL - HSUSB: 12-pin TLL Port 2*/
-MUX_CFG_34XX("AA8_3430_USB2HS_TLL_CLK", 0x5f0,
-                OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
-MUX_CFG_34XX("AA10_3430_USB2HS_TLL_STP", 0x5f2,
-                OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLUP)
-MUX_CFG_34XX("AA9_3430_USB2HS_TLL_DIR", 0x5f4,
-                OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
-MUX_CFG_34XX("AB11_3430_USB2HS_TLL_NXT", 0x5f6,
-                OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
-MUX_CFG_34XX("AB10_3430_USB2HS_TLL_D0", 0x5f8,
-                OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
-MUX_CFG_34XX("AB9_3430_USB2HS_TLL_D1", 0x5fa,
-                OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
-MUX_CFG_34XX("W3_3430_USB2HS_TLL_D2", 0x1d4,
-                OMAP34XX_MUX_MODE2 | OMAP34XX_PIN_INPUT_PULLDOWN)
-MUX_CFG_34XX("T4_3430_USB2HS_TLL_D3", 0x1de,
-                OMAP34XX_MUX_MODE2 | OMAP34XX_PIN_INPUT_PULLDOWN)
-MUX_CFG_34XX("T3_3430_USB2HS_TLL_D4", 0x1d8,
-                OMAP34XX_MUX_MODE2 | OMAP34XX_PIN_INPUT_PULLDOWN)
-MUX_CFG_34XX("R3_3430_USB2HS_TLL_D5", 0x1da,
-                OMAP34XX_MUX_MODE2 | OMAP34XX_PIN_INPUT_PULLDOWN)
-MUX_CFG_34XX("R4_3430_USB2HS_TLL_D6", 0x1dc,
-                OMAP34XX_MUX_MODE2 | OMAP34XX_PIN_INPUT_PULLDOWN)
-MUX_CFG_34XX("T2_3430_USB2HS_TLL_D7", 0x1d6,
-                OMAP34XX_MUX_MODE2 | OMAP34XX_PIN_INPUT_PULLDOWN)
-
-/* TLL - HSUSB: 12-pin TLL Port 3*/
-MUX_CFG_34XX("AA6_3430_USB3HS_TLL_CLK", 0x180,
-                OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
-MUX_CFG_34XX("AB3_3430_USB3HS_TLL_STP", 0x166,
-                OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLUP)
-MUX_CFG_34XX("AA3_3430_USB3HS_TLL_DIR", 0x168,
-                OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
-MUX_CFG_34XX("Y3_3430_USB3HS_TLL_NXT", 0x16a,
-                OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
-MUX_CFG_34XX("AA5_3430_USB3HS_TLL_D0", 0x186,
-                OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
-MUX_CFG_34XX("Y4_3430_USB3HS_TLL_D1", 0x184,
-                OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
-MUX_CFG_34XX("Y5_3430_USB3HS_TLL_D2", 0x188,
-                OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
-MUX_CFG_34XX("W5_3430_USB3HS_TLL_D3", 0x18a,
-                OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
-MUX_CFG_34XX("AB12_3430_USB3HS_TLL_D4", 0x16c,
-                OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
-MUX_CFG_34XX("AB13_3430_USB3HS_TLL_D5", 0x16e,
-                OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
-MUX_CFG_34XX("AA13_3430_USB3HS_TLL_D6", 0x170,
-                OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
-MUX_CFG_34XX("AA12_3430_USB3HS_TLL_D7", 0x172,
-                OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
-
-/* PHY FSUSB: FS Serial for Port 1 (multiple PHY modes supported) */
-MUX_CFG_34XX("AF10_3430_USB1FS_PHY_MM1_RXDP", 0x5d8,
-                OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
-MUX_CFG_34XX("AG9_3430_USB1FS_PHY_MM1_RXDM", 0x5ee,
-                OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
-MUX_CFG_34XX("W13_3430_USB1FS_PHY_MM1_RXRCV", 0x5dc,
-                OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
-MUX_CFG_34XX("W12_3430_USB1FS_PHY_MM1_TXSE0", 0x5de,
-                OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
-MUX_CFG_34XX("W11_3430_USB1FS_PHY_MM1_TXDAT", 0x5e0,
-                OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
-MUX_CFG_34XX("Y11_3430_USB1FS_PHY_MM1_TXEN_N", 0x5ea,
-                OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_OUTPUT)
-
-/* PHY FSUSB: FS Serial for Port 2 (multiple PHY modes supported) */
-MUX_CFG_34XX("AF7_3430_USB2FS_PHY_MM2_RXDP", 0x5f2,
-                OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
-MUX_CFG_34XX("AH7_3430_USB2FS_PHY_MM2_RXDM", 0x5f6,
-                OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
-MUX_CFG_34XX("AB10_3430_USB2FS_PHY_MM2_RXRCV", 0x5f8,
-                OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
-MUX_CFG_34XX("AB9_3430_USB2FS_PHY_MM2_TXSE0", 0x5fa,
-                OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
-MUX_CFG_34XX("W3_3430_USB2FS_PHY_MM2_TXDAT", 0x1d4,
-                OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
-MUX_CFG_34XX("T4_3430_USB2FS_PHY_MM2_TXEN_N", 0x1de,
-                OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_OUTPUT)
-
-/* PHY FSUSB: FS Serial for Port 3 (multiple PHY modes supported) */
-MUX_CFG_34XX("AH3_3430_USB3FS_PHY_MM3_RXDP", 0x166,
-                OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
-MUX_CFG_34XX("AE3_3430_USB3FS_PHY_MM3_RXDM", 0x16a,
-                OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
-MUX_CFG_34XX("AD1_3430_USB3FS_PHY_MM3_RXRCV", 0x186,
-                OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
-MUX_CFG_34XX("AE1_3430_USB3FS_PHY_MM3_TXSE0", 0x184,
-                OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
-MUX_CFG_34XX("AD2_3430_USB3FS_PHY_MM3_TXDAT", 0x188,
-                OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
-MUX_CFG_34XX("AC1_3430_USB3FS_PHY_MM3_TXEN_N", 0x18a,
-                OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_OUTPUT)
-
-
-/* 34XX GPIO - bidirectional, unless the name has an "_OUT" suffix.
- * (Always specify PIN_INPUT, except for names suffixed by "_OUT".)
- * No internal pullup/pulldown without "_UP" or "_DOWN" suffix.
- */
-MUX_CFG_34XX("AF26_34XX_GPIO0", 0x1e0,
-                OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_INPUT)
-MUX_CFG_34XX("AF22_34XX_GPIO9", 0xa18,
-                OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_INPUT)
-MUX_CFG_34XX("AG9_34XX_GPIO23", 0x5ee,
-                OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_INPUT)
-MUX_CFG_34XX("AH8_34XX_GPIO29", 0x5fa,
-                OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_INPUT)
-MUX_CFG_34XX("U8_34XX_GPIO54_OUT", 0x0b4,
-                OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_OUTPUT)
-MUX_CFG_34XX("U8_34XX_GPIO54_DOWN", 0x0b4,
-                OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_INPUT_PULLDOWN)
-MUX_CFG_34XX("L8_34XX_GPIO63", 0x0ce,
-                OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_INPUT)
-MUX_CFG_34XX("G25_34XX_GPIO86_OUT", 0x0fc,
-                OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_OUTPUT)
-MUX_CFG_34XX("AG4_34XX_GPIO134_OUT", 0x160,
-                OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_OUTPUT)
-MUX_CFG_34XX("AF4_34XX_GPIO135_OUT", 0x162,
-                OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_OUTPUT)
-MUX_CFG_34XX("AE4_34XX_GPIO136_OUT", 0x164,
-                OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_OUTPUT)
-MUX_CFG_34XX("AF6_34XX_GPIO140_UP", 0x16c,
-                OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_INPUT_PULLUP)
-MUX_CFG_34XX("AE6_34XX_GPIO141", 0x16e,
-                OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_INPUT)
-MUX_CFG_34XX("AF5_34XX_GPIO142", 0x170,
-                OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_INPUT)
-MUX_CFG_34XX("AE5_34XX_GPIO143", 0x172,
-                OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_INPUT)
-MUX_CFG_34XX("H19_34XX_GPIO164_OUT", 0x19c,
-                OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_OUTPUT)
-MUX_CFG_34XX("J25_34XX_GPIO170", 0x1c6,
-                OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_INPUT)
-
-/* OMAP3 SDRC CKE signals to SDR/DDR ram chips */
-MUX_CFG_34XX("H16_34XX_SDRC_CKE0", 0x262,
-                OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_OUTPUT)
-MUX_CFG_34XX("H17_34XX_SDRC_CKE1", 0x264,
-                OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_OUTPUT)
-
-/* MMC1 */
-MUX_CFG_34XX("N28_3430_MMC1_CLK", 0x144,
-                OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
-MUX_CFG_34XX("M27_3430_MMC1_CMD", 0x146,
-                OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
-MUX_CFG_34XX("N27_3430_MMC1_DAT0", 0x148,
-                OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
-MUX_CFG_34XX("N26_3430_MMC1_DAT1", 0x14a,
-                OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
-MUX_CFG_34XX("N25_3430_MMC1_DAT2", 0x14c,
-                OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
-MUX_CFG_34XX("P28_3430_MMC1_DAT3", 0x14e,
-                OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
-MUX_CFG_34XX("P27_3430_MMC1_DAT4", 0x150,
-                OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
-MUX_CFG_34XX("P26_3430_MMC1_DAT5", 0x152,
-                OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
-MUX_CFG_34XX("R27_3430_MMC1_DAT6", 0x154,
-                OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
-MUX_CFG_34XX("R25_3430_MMC1_DAT7", 0x156,
-                OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
-
-/* MMC2 */
-MUX_CFG_34XX("AE2_3430_MMC2_CLK", 0x158,
-                OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
-MUX_CFG_34XX("AG5_3430_MMC2_CMD", 0x15A,
-                OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
-MUX_CFG_34XX("AH5_3430_MMC2_DAT0", 0x15c,
-                OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
-MUX_CFG_34XX("AH4_3430_MMC2_DAT1", 0x15e,
-                OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
-MUX_CFG_34XX("AG4_3430_MMC2_DAT2", 0x160,
-                OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
-MUX_CFG_34XX("AF4_3430_MMC2_DAT3", 0x162,
-                OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
-MUX_CFG_34XX("AE4_3430_MMC2_DAT4", 0x164,
-                OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
-MUX_CFG_34XX("AH3_3430_MMC2_DAT5", 0x166,
-                OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
-MUX_CFG_34XX("AF3_3430_MMC2_DAT6", 0x168,
-                OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
-MUX_CFG_34XX("AE3_3430_MMC2_DAT7", 0x16A,
-                OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
-
-/* MMC3 */
-MUX_CFG_34XX("AF10_3430_MMC3_CLK", 0x5d8,
-                OMAP34XX_MUX_MODE2 | OMAP34XX_PIN_INPUT_PULLUP)
-MUX_CFG_34XX("AC3_3430_MMC3_CMD", 0x1d0,
-                OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLUP)
-MUX_CFG_34XX("AE11_3430_MMC3_DAT0", 0x5e4,
-                OMAP34XX_MUX_MODE2 | OMAP34XX_PIN_INPUT_PULLUP)
-MUX_CFG_34XX("AH9_3430_MMC3_DAT1", 0x5e6,
-                OMAP34XX_MUX_MODE2 | OMAP34XX_PIN_INPUT_PULLUP)
-MUX_CFG_34XX("AF13_3430_MMC3_DAT2", 0x5e8,
-                OMAP34XX_MUX_MODE2 | OMAP34XX_PIN_INPUT_PULLUP)
-MUX_CFG_34XX("AF13_3430_MMC3_DAT3", 0x5e2,
-                OMAP34XX_MUX_MODE2 | OMAP34XX_PIN_INPUT_PULLUP)
-
-/* SYS_NIRQ T2 INT1 */
-MUX_CFG_34XX("AF26_34XX_SYS_NIRQ", 0x1E0,
-                OMAP3_WAKEUP_EN | OMAP34XX_PIN_INPUT_PULLUP |
-                OMAP34XX_MUX_MODE0)
-/* EHCI GPIO's on OMAP3EVM (Rev >= E) */
-MUX_CFG_34XX("AH14_34XX_GPIO21", 0x5ea,
-        OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_INPUT_PULLUP)
-MUX_CFG_34XX("AF9_34XX_GPIO22", 0x5ec,
-        OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_INPUT_PULLUP)
-MUX_CFG_34XX("U3_34XX_GPIO61", 0x0c8,
-        OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_INPUT_PULLUP)
-};
-
-#define OMAP34XX_PINS_SZ        ARRAY_SIZE(omap34xx_pins)
-
-#else
-#define omap34xx_pins           NULL
-#define OMAP34XX_PINS_SZ        0
-#endif  /* CONFIG_ARCH_OMAP34XX */
-
 #if defined(CONFIG_OMAP_MUX_DEBUG) || defined(CONFIG_OMAP_MUX_WARNINGS)
+
 static void __init_or_module omap2_cfg_debug(const struct pin_config *cfg, u16 reg)
 {
         u16 orig;
         u8 warn = 0, debug = 0;
 
-        if (cpu_is_omap24xx())
-                orig = omap_ctrl_readb(cfg->mux_reg);
-        else
-                orig = omap_ctrl_readw(cfg->mux_reg);
+        orig = omap_mux_read(cfg->mux_reg - OMAP_MUX_BASE_OFFSET);
 
 #ifdef  CONFIG_OMAP_MUX_DEBUG
         debug = cfg->debug;
@@ -600,7 +305,6 @@ static void __init_or_module omap2_cfg_debug(const struct pin_config *cfg, u16 r
 #define omap2_cfg_debug(x, y)   do {} while (0)
 #endif
 
-#ifdef CONFIG_ARCH_OMAP24XX
 static int __init_or_module omap24xx_cfg_reg(const struct pin_config *cfg)
 {
         static DEFINE_SPINLOCK(mux_spin_lock);
@@ -614,47 +318,692 @@ static int __init_or_module omap24xx_cfg_reg(const struct pin_config *cfg)
         if (cfg->pu_pd_val)
                 reg |= OMAP2_PULL_UP;
         omap2_cfg_debug(cfg, reg);
-        omap_ctrl_writeb(reg, cfg->mux_reg);
+        omap_mux_write(reg, cfg->mux_reg - OMAP_MUX_BASE_OFFSET);
         spin_unlock_irqrestore(&mux_spin_lock, flags);
 
         return 0;
 }
+
+int __init omap2_mux_init(void)
+{
+        u32 mux_pbase;
+
+        if (cpu_is_omap2420())
+                mux_pbase = OMAP2420_CTRL_BASE + OMAP_MUX_BASE_OFFSET;
+        else if (cpu_is_omap2430())
+                mux_pbase = OMAP243X_CTRL_BASE + OMAP_MUX_BASE_OFFSET;
+        else
+                return -ENODEV;
+
+        mux_base = ioremap(mux_pbase, OMAP_MUX_BASE_SZ);
+        if (!mux_base) {
+                printk(KERN_ERR "mux: Could not ioremap\n");
+                return -ENODEV;
+        }
+
+        if (cpu_is_omap24xx()) {
+                arch_mux_cfg.pins       = omap24xx_pins;
+                arch_mux_cfg.size       = OMAP24XX_PINS_SZ;
+                arch_mux_cfg.cfg_reg    = omap24xx_cfg_reg;
+
+                return omap_mux_register(&arch_mux_cfg);
+        }
+
+        return 0;
+}
+
 #else
-#define omap24xx_cfg_reg        NULL
-#endif
+int __init omap2_mux_init(void)
+{
+        return 0;
+}
+#endif  /* CONFIG_OMAP_MUX */
+
+/*----------------------------------------------------------------------------*/
 
 #ifdef CONFIG_ARCH_OMAP34XX
-static int __init_or_module omap34xx_cfg_reg(const struct pin_config *cfg)
+static LIST_HEAD(muxmodes);
+static DEFINE_MUTEX(muxmode_mutex);
+
+#ifdef CONFIG_OMAP_MUX
+
+static char *omap_mux_options;
+
+int __init omap_mux_init_gpio(int gpio, int val)
 {
-        static DEFINE_SPINLOCK(mux_spin_lock);
-        unsigned long flags;
-        u16 reg = 0;
+        struct omap_mux_entry *e;
+        int found = 0;
+
+        if (!gpio)
+                return -EINVAL;
+
+        list_for_each_entry(e, &muxmodes, node) {
+                struct omap_mux *m = &e->mux;
+                if (gpio == m->gpio) {
+                        u16 old_mode;
+                        u16 mux_mode;
+
+                        old_mode = omap_mux_read(m->reg_offset);
+                        mux_mode = val & ~(OMAP_MUX_NR_MODES - 1);
+                        mux_mode |= OMAP_MUX_MODE4;
+                        printk(KERN_DEBUG "mux: Setting signal "
+                                "%s.gpio%i 0x%04x -> 0x%04x\n",
+                                m->muxnames[0], gpio, old_mode, mux_mode);
+                        omap_mux_write(mux_mode, m->reg_offset);
+                        found++;
+                }
+        }
 
-        spin_lock_irqsave(&mux_spin_lock, flags);
-        reg |= cfg->mux_val;
-        omap2_cfg_debug(cfg, reg);
-        omap_ctrl_writew(reg, cfg->mux_reg);
-        spin_unlock_irqrestore(&mux_spin_lock, flags);
+        if (found == 1)
+                return 0;
+
+        if (found > 1) {
+                printk(KERN_ERR "mux: Multiple gpio paths for gpio%i\n", gpio);
+                return -EINVAL;
+        }
+
+        printk(KERN_ERR "mux: Could not set gpio%i\n", gpio);
+
+        return -ENODEV;
+}
+
+int __init omap_mux_init_signal(char *muxname, int val)
+{
+        struct omap_mux_entry *e;
+        char *m0_name = NULL, *mode_name = NULL;
+        int found = 0;
+
+        mode_name = strchr(muxname, '.');
+        if (mode_name) {
+                *mode_name = '\0';
+                mode_name++;
+                m0_name = muxname;
+        } else {
+                mode_name = muxname;
+        }
+
+        list_for_each_entry(e, &muxmodes, node) {
+                struct omap_mux *m = &e->mux;
+                char *m0_entry = m->muxnames[0];
+                int i;
+
+                if (m0_name && strcmp(m0_name, m0_entry))
+                        continue;
+
+                for (i = 0; i < OMAP_MUX_NR_MODES; i++) {
+                        char *mode_cur = m->muxnames[i];
+
+                        if (!mode_cur)
+                                continue;
+
+                        if (!strcmp(mode_name, mode_cur)) {
+                                u16 old_mode;
+                                u16 mux_mode;
+
+                                old_mode = omap_mux_read(m->reg_offset);
+                                mux_mode = val | i;
+                                printk(KERN_DEBUG "mux: Setting signal "
+                                        "%s.%s 0x%04x -> 0x%04x\n",
+                                        m0_entry, muxname, old_mode, mux_mode);
+                                omap_mux_write(mux_mode, m->reg_offset);
+                                found++;
+                        }
+                }
+        }
+
+        if (found == 1)
+                return 0;
+
+        if (found > 1) {
+                printk(KERN_ERR "mux: Multiple signal paths (%i) for %s\n",
+                                found, muxname);
+                return -EINVAL;
+        }
+
+        printk(KERN_ERR "mux: Could not set signal %s\n", muxname);
+
+        return -ENODEV;
+}
+
+#ifdef CONFIG_DEBUG_FS
+
+#define OMAP_MUX_MAX_NR_FLAGS   10
+#define OMAP_MUX_TEST_FLAG(val, mask)                           \
+        if (((val) & (mask)) == (mask)) {                       \
+                i++;                                            \
+                flags[i] =  #mask;                              \
+        }
+
+/* REVISIT: Add checking for non-optimal mux settings */
+static inline void omap_mux_decode(struct seq_file *s, u16 val)
+{
+        char *flags[OMAP_MUX_MAX_NR_FLAGS];
+        char mode[14];
+        int i = -1;
+
+        sprintf(mode, "OMAP_MUX_MODE%d", val & 0x7);
+        i++;
+        flags[i] = mode;
+
+        OMAP_MUX_TEST_FLAG(val, OMAP_PIN_OFF_WAKEUPENABLE);
+        if (val & OMAP_OFF_EN) {
+                if (!(val & OMAP_OFFOUT_EN)) {
+                        if (!(val & OMAP_OFF_PULL_UP)) {
+                                OMAP_MUX_TEST_FLAG(val,
+                                        OMAP_PIN_OFF_INPUT_PULLDOWN);
+                        } else {
+                                OMAP_MUX_TEST_FLAG(val,
+                                        OMAP_PIN_OFF_INPUT_PULLUP);
+                        }
+                } else {
+                        if (!(val & OMAP_OFFOUT_VAL)) {
+                                OMAP_MUX_TEST_FLAG(val,
+                                        OMAP_PIN_OFF_OUTPUT_LOW);
+                        } else {
+                                OMAP_MUX_TEST_FLAG(val,
+                                        OMAP_PIN_OFF_OUTPUT_HIGH);
+                        }
+                }
+        }
+
+        if (val & OMAP_INPUT_EN) {
+                if (val & OMAP_PULL_ENA) {
+                        if (!(val & OMAP_PULL_UP)) {
+                                OMAP_MUX_TEST_FLAG(val,
+                                        OMAP_PIN_INPUT_PULLDOWN);
+                        } else {
+                                OMAP_MUX_TEST_FLAG(val, OMAP_PIN_INPUT_PULLUP);
+                        }
+                } else {
+                        OMAP_MUX_TEST_FLAG(val, OMAP_PIN_INPUT);
+                }
+        } else {
+                i++;
+                flags[i] = "OMAP_PIN_OUTPUT";
+        }
+
+        do {
+                seq_printf(s, "%s", flags[i]);
+                if (i > 0)
+                        seq_printf(s, " | ");
+        } while (i-- > 0);
+}
+
+#define OMAP_MUX_DEFNAME_LEN    16
+
+static int omap_mux_dbg_board_show(struct seq_file *s, void *unused)
+{
+        struct omap_mux_entry *e;
+
+        list_for_each_entry(e, &muxmodes, node) {
+                struct omap_mux *m = &e->mux;
+                char m0_def[OMAP_MUX_DEFNAME_LEN];
+                char *m0_name = m->muxnames[0];
+                u16 val;
+                int i, mode;
+
+                if (!m0_name)
+                        continue;
+
+                for (i = 0; i < OMAP_MUX_DEFNAME_LEN; i++) {
+                        if (m0_name[i] == '\0') {
+                                m0_def[i] = m0_name[i];
+                                break;
+                        }
+                        m0_def[i] = toupper(m0_name[i]);
+                }
+                val = omap_mux_read(m->reg_offset);
+                mode = val & OMAP_MUX_MODE7;
+
+                seq_printf(s, "OMAP%i_MUX(%s, ",
+                                        cpu_is_omap34xx() ? 3 : 0, m0_def);
+                omap_mux_decode(s, val);
+                seq_printf(s, "),\n");
+        }
+
+        return 0;
+}
+
+static int omap_mux_dbg_board_open(struct inode *inode, struct file *file)
+{
+        return single_open(file, omap_mux_dbg_board_show, &inode->i_private);
+}
+
+static const struct file_operations omap_mux_dbg_board_fops = {
+        .open           = omap_mux_dbg_board_open,
+        .read           = seq_read,
+        .llseek         = seq_lseek,
+        .release        = single_release,
+};
+
+static int omap_mux_dbg_signal_show(struct seq_file *s, void *unused)
+{
+        struct omap_mux *m = s->private;
+        const char *none = "NA";
+        u16 val;
+        int mode;
+
+        val = omap_mux_read(m->reg_offset);
+        mode = val & OMAP_MUX_MODE7;
+
+        seq_printf(s, "name: %s.%s (0x%08lx/0x%03x = 0x%04x), b %s, t %s\n",
+                        m->muxnames[0], m->muxnames[mode],
+                        mux_phys + m->reg_offset, m->reg_offset, val,
+                        m->balls[0] ? m->balls[0] : none,
+                        m->balls[1] ? m->balls[1] : none);
+        seq_printf(s, "mode: ");
+        omap_mux_decode(s, val);
+        seq_printf(s, "\n");
+        seq_printf(s, "signals: %s | %s | %s | %s | %s | %s | %s | %s\n",
+                        m->muxnames[0] ? m->muxnames[0] : none,
+                        m->muxnames[1] ? m->muxnames[1] : none,
+                        m->muxnames[2] ? m->muxnames[2] : none,
+                        m->muxnames[3] ? m->muxnames[3] : none,
+                        m->muxnames[4] ? m->muxnames[4] : none,
+                        m->muxnames[5] ? m->muxnames[5] : none,
+                        m->muxnames[6] ? m->muxnames[6] : none,
+                        m->muxnames[7] ? m->muxnames[7] : none);
 
         return 0;
 }
+
+#define OMAP_MUX_MAX_ARG_CHAR  7
+
+static ssize_t omap_mux_dbg_signal_write(struct file *file,
+                                                const char __user *user_buf,
+                                                size_t count, loff_t *ppos)
+{
+        char buf[OMAP_MUX_MAX_ARG_CHAR];
+        struct seq_file *seqf;
+        struct omap_mux *m;
+        unsigned long val;
+        int buf_size, ret;
+
+        if (count > OMAP_MUX_MAX_ARG_CHAR)
+                return -EINVAL;
+
+        memset(buf, 0, sizeof(buf));
+        buf_size = min(count, sizeof(buf) - 1);
+
+        if (copy_from_user(buf, user_buf, buf_size))
+                return -EFAULT;
+
+        ret = strict_strtoul(buf, 0x10, &val);
+        if (ret < 0)
+                return ret;
+
+        if (val > 0xffff)
+                return -EINVAL;
+
+        seqf = file->private_data;
+        m = seqf->private;
+
+        omap_mux_write((u16)val, m->reg_offset);
+        *ppos += count;
+
+        return count;
+}
+
+static int omap_mux_dbg_signal_open(struct inode *inode, struct file *file)
+{
+        return single_open(file, omap_mux_dbg_signal_show, inode->i_private);
+}
+
+static const struct file_operations omap_mux_dbg_signal_fops = {
+        .open           = omap_mux_dbg_signal_open,
+        .read           = seq_read,
+        .write          = omap_mux_dbg_signal_write,
+        .llseek         = seq_lseek,
+        .release        = single_release,
+};
+
+static struct dentry *mux_dbg_dir;
+
+static void __init omap_mux_dbg_init(void)
+{
+        struct omap_mux_entry *e;
+
+        mux_dbg_dir = debugfs_create_dir("omap_mux", NULL);
+        if (!mux_dbg_dir)
+                return;
+
+        (void)debugfs_create_file("board", S_IRUGO, mux_dbg_dir,
+                                        NULL, &omap_mux_dbg_board_fops);
+
+        list_for_each_entry(e, &muxmodes, node) {
+                struct omap_mux *m = &e->mux;
+
+                (void)debugfs_create_file(m->muxnames[0], S_IWUGO, mux_dbg_dir,
+                                        m, &omap_mux_dbg_signal_fops);
+        }
+}
+
 #else
-#define omap34xx_cfg_reg        NULL
+static inline void omap_mux_dbg_init(void)
+{
+}
+#endif  /* CONFIG_DEBUG_FS */
+
+static void __init omap_mux_free_names(struct omap_mux *m)
+{
+        int i;
+
+        for (i = 0; i < OMAP_MUX_NR_MODES; i++)
+                kfree(m->muxnames[i]);
+
+#ifdef CONFIG_DEBUG_FS
+        for (i = 0; i < OMAP_MUX_NR_SIDES; i++)
+                kfree(m->balls[i]);
 #endif
 
-int __init omap2_mux_init(void)
+}
+
+/* Free all data except for GPIO pins unless CONFIG_DEBUG_FS is set */
+static int __init omap_mux_late_init(void)
 {
-        if (cpu_is_omap24xx()) {
-                arch_mux_cfg.pins       = omap24xx_pins;
-                arch_mux_cfg.size       = OMAP24XX_PINS_SZ;
-                arch_mux_cfg.cfg_reg    = omap24xx_cfg_reg;
-        } else if (cpu_is_omap34xx()) {
-                arch_mux_cfg.pins       = omap34xx_pins;
-                arch_mux_cfg.size       = OMAP34XX_PINS_SZ;
-                arch_mux_cfg.cfg_reg    = omap34xx_cfg_reg;
+        struct omap_mux_entry *e, *tmp;
+
+        list_for_each_entry_safe(e, tmp, &muxmodes, node) {
+                struct omap_mux *m = &e->mux;
+                u16 mode = omap_mux_read(m->reg_offset);
+
+                if (OMAP_MODE_GPIO(mode))
+                        continue;
+
+#ifndef CONFIG_DEBUG_FS
+                mutex_lock(&muxmode_mutex);
+                list_del(&e->node);
+                mutex_unlock(&muxmode_mutex);
+                omap_mux_free_names(m);
+                kfree(m);
+#endif
+
+        }
+
+        omap_mux_dbg_init();
+
+        return 0;
+}
+late_initcall(omap_mux_late_init);
+
+static void __init omap_mux_package_fixup(struct omap_mux *p,
+                                        struct omap_mux *superset)
+{
+        while (p->reg_offset !=  OMAP_MUX_TERMINATOR) {
+                struct omap_mux *s = superset;
+                int found = 0;
+
+                while (s->reg_offset != OMAP_MUX_TERMINATOR) {
+                        if (s->reg_offset == p->reg_offset) {
+                                *s = *p;
+                                found++;
+                                break;
+                        }
+                        s++;
+                }
+                if (!found)
+                        printk(KERN_ERR "mux: Unknown entry offset 0x%x\n",
+                                        p->reg_offset);
+                p++;
+        }
+}
+
+#ifdef CONFIG_DEBUG_FS
+
+static void __init omap_mux_package_init_balls(struct omap_ball *b,
+                                struct omap_mux *superset)
+{
+        while (b->reg_offset != OMAP_MUX_TERMINATOR) {
+                struct omap_mux *s = superset;
+                int found = 0;
+
+                while (s->reg_offset != OMAP_MUX_TERMINATOR) {
+                        if (s->reg_offset == b->reg_offset) {
+                                s->balls[0] = b->balls[0];
+                                s->balls[1] = b->balls[1];
+                                found++;
+                                break;
+                        }
+                        s++;
+                }
+                if (!found)
+                        printk(KERN_ERR "mux: Unknown ball offset 0x%x\n",
+                                        b->reg_offset);
+                b++;
+        }
+}
+
+#else   /* CONFIG_DEBUG_FS */
+
+static inline void omap_mux_package_init_balls(struct omap_ball *b,
+                                        struct omap_mux *superset)
+{
+}
+
+#endif  /* CONFIG_DEBUG_FS */
+
+static int __init omap_mux_setup(char *options)
+{
+        if (!options)
+                return 0;
+
+        omap_mux_options = options;
+
+        return 1;
+}
+__setup("omap_mux=", omap_mux_setup);
+
+/*
+ * Note that the omap_mux=some.signal1=0x1234,some.signal2=0x1234
+ * cmdline options only override the bootloader values.
+ * During development, please enable CONFIG_DEBUG_FS, and use the
+ * signal specific entries under debugfs.
+ */
+static void __init omap_mux_set_cmdline_signals(void)
+{
+        char *options, *next_opt, *token;
+
+        if (!omap_mux_options)
+                return;
+
+        options = kmalloc(strlen(omap_mux_options) + 1, GFP_KERNEL);
+        if (!options)
+                return;
+
+        strcpy(options, omap_mux_options);
+        next_opt = options;
+
+        while ((token = strsep(&next_opt, ",")) != NULL) {
+                char *keyval, *name;
+                unsigned long val;
+
+                keyval = token;
+                name = strsep(&keyval, "=");
+                if (name) {
+                        int res;
+
+                        res = strict_strtoul(keyval, 0x10, &val);
+                        if (res < 0)
+                                continue;
+
+                        omap_mux_init_signal(name, (u16)val);
+                }
+        }
+
+        kfree(options);
+}
+
+static void __init omap_mux_set_board_signals(struct omap_board_mux *board_mux)
+{
+        while (board_mux->reg_offset !=  OMAP_MUX_TERMINATOR) {
+                omap_mux_write(board_mux->value, board_mux->reg_offset);
+                board_mux++;
+        }
+}
+
+static int __init omap_mux_copy_names(struct omap_mux *src,
+                                        struct omap_mux *dst)
+{
+        int i;
+
+        for (i = 0; i < OMAP_MUX_NR_MODES; i++) {
+                if (src->muxnames[i]) {
+                        dst->muxnames[i] =
+                                kmalloc(strlen(src->muxnames[i]) + 1,
+                                        GFP_KERNEL);
+                        if (!dst->muxnames[i])
+                                goto free;
+                        strcpy(dst->muxnames[i], src->muxnames[i]);
+                }
+        }
+
+#ifdef CONFIG_DEBUG_FS
+        for (i = 0; i < OMAP_MUX_NR_SIDES; i++) {
+                if (src->balls[i]) {
+                        dst->balls[i] =
+                                kmalloc(strlen(src->balls[i]) + 1,
+                                        GFP_KERNEL);
+                        if (!dst->balls[i])
+                                goto free;
+                        strcpy(dst->balls[i], src->balls[i]);
+                }
+        }
+#endif
+
+        return 0;
+
+free:
+        omap_mux_free_names(dst);
+        return -ENOMEM;
+
+}
+
+#endif  /* CONFIG_OMAP_MUX */
+
+static u16 omap_mux_get_by_gpio(int gpio)
+{
+        struct omap_mux_entry *e;
+        u16 offset = OMAP_MUX_TERMINATOR;
+
+        list_for_each_entry(e, &muxmodes, node) {
+                struct omap_mux *m = &e->mux;
+                if (m->gpio == gpio) {
+                        offset = m->reg_offset;
+                        break;
+                }
+        }
+
+        return offset;
+}
+
+/* Needed for dynamic muxing of GPIO pins for off-idle */
+u16 omap_mux_get_gpio(int gpio)
+{
+        u16 offset;
+
+        offset = omap_mux_get_by_gpio(gpio);
+        if (offset == OMAP_MUX_TERMINATOR) {
+                printk(KERN_ERR "mux: Could not get gpio%i\n", gpio);
+                return offset;
+        }
+
+        return omap_mux_read(offset);
+}
+
+/* Needed for dynamic muxing of GPIO pins for off-idle */
+void omap_mux_set_gpio(u16 val, int gpio)
+{
+        u16 offset;
+
+        offset = omap_mux_get_by_gpio(gpio);
+        if (offset == OMAP_MUX_TERMINATOR) {
+                printk(KERN_ERR "mux: Could not set gpio%i\n", gpio);
+                return;
+        }
+
+        omap_mux_write(val, offset);
+}
+
+static struct omap_mux * __init omap_mux_list_add(struct omap_mux *src)
+{
+        struct omap_mux_entry *entry;
+        struct omap_mux *m;
+
+        entry = kzalloc(sizeof(struct omap_mux_entry), GFP_KERNEL);
+        if (!entry)
+                return NULL;
+
+        m = &entry->mux;
+        memcpy(m, src, sizeof(struct omap_mux_entry));
+
+#ifdef CONFIG_OMAP_MUX
+        if (omap_mux_copy_names(src, m)) {
+                kfree(entry);
+                return NULL;
         }
+#endif
+
+        mutex_lock(&muxmode_mutex);
+        list_add_tail(&entry->node, &muxmodes);
+        mutex_unlock(&muxmode_mutex);
 
-        return omap_mux_register(&arch_mux_cfg);
+        return m;
 }
 
+/*
+ * Note if CONFIG_OMAP_MUX is not selected, we will only initialize
+ * the GPIO to mux offset mapping that is needed for dynamic muxing
+ * of GPIO pins for off-idle.
+ */
+static void __init omap_mux_init_list(struct omap_mux *superset)
+{
+        while (superset->reg_offset !=  OMAP_MUX_TERMINATOR) {
+                struct omap_mux *entry;
+
+#ifndef CONFIG_OMAP_MUX
+                /* Skip pins that are not muxed as GPIO by bootloader */
+                if (!OMAP_MODE_GPIO(omap_mux_read(superset->reg_offset))) {
+                        superset++;
+                        continue;
+                }
 #endif
+
+                entry = omap_mux_list_add(superset);
+                if (!entry) {
+                        printk(KERN_ERR "mux: Could not add entry\n");
+                        return;
+                }
+                superset++;
+        }
+}
+
+int __init omap_mux_init(u32 mux_pbase, u32 mux_size,
+                                struct omap_mux *superset,
+                                struct omap_mux *package_subset,
+                                struct omap_board_mux *board_mux,
+                                struct omap_ball *package_balls)
+{
+        if (mux_base)
+                return -EBUSY;
+
+        mux_phys = mux_pbase;
+        mux_base = ioremap(mux_pbase, mux_size);
+        if (!mux_base) {
+                printk(KERN_ERR "mux: Could not ioremap\n");
+                return -ENODEV;
+        }
+
+#ifdef CONFIG_OMAP_MUX
+        omap_mux_package_fixup(package_subset, superset);
+        omap_mux_package_init_balls(package_balls, superset);
+        omap_mux_set_cmdline_signals();
+        omap_mux_set_board_signals(board_mux);
+#endif
+
+        omap_mux_init_list(superset);
+
+        return 0;
+}
+
+#endif  /* CONFIG_ARCH_OMAP34XX */
+
diff --git a/arch/arm/mach-omap2/mux.h b/arch/arm/mach-omap2/mux.h
new file mode 100644
index 000000000000..d8b4d5ad2278
--- /dev/null
+++ b/arch/arm/mach-omap2/mux.h
@@ -0,0 +1,163 @@
+/*
+ * Copyright (C) 2009 Nokia
+ * Copyright (C) 2009 Texas Instruments
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include "mux34xx.h"
+
+#define OMAP_MUX_TERMINATOR     0xffff
+
+/* 34xx mux mode options for each pin. See TRM for options */
+#define OMAP_MUX_MODE0      0
+#define OMAP_MUX_MODE1      1
+#define OMAP_MUX_MODE2      2
+#define OMAP_MUX_MODE3      3
+#define OMAP_MUX_MODE4      4
+#define OMAP_MUX_MODE5      5
+#define OMAP_MUX_MODE6      6
+#define OMAP_MUX_MODE7      7
+
+/* 24xx/34xx mux bit defines */
+#define OMAP_PULL_ENA                   (1 << 3)
+#define OMAP_PULL_UP                    (1 << 4)
+#define OMAP_ALTELECTRICALSEL           (1 << 5)
+
+/* 34xx specific mux bit defines */
+#define OMAP_INPUT_EN                   (1 << 8)
+#define OMAP_OFF_EN                     (1 << 9)
+#define OMAP_OFFOUT_EN                  (1 << 10)
+#define OMAP_OFFOUT_VAL                 (1 << 11)
+#define OMAP_OFF_PULL_EN                (1 << 12)
+#define OMAP_OFF_PULL_UP                (1 << 13)
+#define OMAP_WAKEUP_EN                  (1 << 14)
+
+/* Active pin states */
+#define OMAP_PIN_OUTPUT                 0
+#define OMAP_PIN_INPUT                  OMAP_INPUT_EN
+#define OMAP_PIN_INPUT_PULLUP           (OMAP_PULL_ENA | OMAP_INPUT_EN \
+                                                | OMAP_PULL_UP)
+#define OMAP_PIN_INPUT_PULLDOWN         (OMAP_PULL_ENA | OMAP_INPUT_EN)
+
+/* Off mode states */
+#define OMAP_PIN_OFF_NONE               0
+#define OMAP_PIN_OFF_OUTPUT_HIGH        (OMAP_OFF_EN | OMAP_OFFOUT_EN \
+                                                | OMAP_OFFOUT_VAL)
+#define OMAP_PIN_OFF_OUTPUT_LOW         (OMAP_OFF_EN | OMAP_OFFOUT_EN)
+#define OMAP_PIN_OFF_INPUT_PULLUP       (OMAP_OFF_EN | OMAP_OFF_PULL_EN \
+                                                | OMAP_OFF_PULL_UP)
+#define OMAP_PIN_OFF_INPUT_PULLDOWN     (OMAP_OFF_EN | OMAP_OFF_PULL_EN)
+#define OMAP_PIN_OFF_WAKEUPENABLE       OMAP_WAKEUP_EN
+
+#define OMAP_MODE_GPIO(x)       (((x) & OMAP_MUX_MODE7) == OMAP_MUX_MODE4)
+
+/* Flags for omap_mux_init */
+#define OMAP_PACKAGE_MASK               0xffff
+#define OMAP_PACKAGE_CBP                4               /* 515-pin 0.40 0.50 */
+#define OMAP_PACKAGE_CUS                3               /* 423-pin 0.65 */
+#define OMAP_PACKAGE_CBB                2               /* 515-pin 0.40 0.50 */
+#define OMAP_PACKAGE_CBC                1               /* 515-pin 0.50 0.65 */
+
+
+#define OMAP_MUX_NR_MODES       8                       /* Available modes */
+#define OMAP_MUX_NR_SIDES       2                       /* Bottom & top */
+
+/**
+ * struct omap_mux - data for omap mux register offset and it's value
+ * @reg_offset: mux register offset from the mux base
+ * @gpio:       GPIO number
+ * @muxnames:   available signal modes for a ball
+ */
+struct omap_mux {
+        u16     reg_offset;
+        u16     gpio;
+#ifdef CONFIG_OMAP_MUX
+        char    *muxnames[OMAP_MUX_NR_MODES];
+#ifdef CONFIG_DEBUG_FS
+        char    *balls[OMAP_MUX_NR_SIDES];
+#endif
+#endif
+};
+
+/**
+ * struct omap_ball - data for balls on omap package
+ * @reg_offset: mux register offset from the mux base
+ * @balls:      available balls on the package
+ */
+struct omap_ball {
+        u16     reg_offset;
+        char    *balls[OMAP_MUX_NR_SIDES];
+};
+
+/**
+ * struct omap_board_mux - data for initializing mux registers
+ * @reg_offset: mux register offset from the mux base
+ * @mux_value:  desired mux value to set
+ */
+struct omap_board_mux {
+        u16     reg_offset;
+        u16     value;
+};
+
+#if defined(CONFIG_OMAP_MUX) && defined(CONFIG_ARCH_OMAP34XX)
+
+/**
+ * omap_mux_init_gpio - initialize a signal based on the GPIO number
+ * @gpio:               GPIO number
+ * @val:                Options for the mux register value
+ */
+int omap_mux_init_gpio(int gpio, int val);
+
+/**
+ * omap_mux_init_signal - initialize a signal based on the signal name
+ * @muxname:            Mux name in mode0_name.signal_name format
+ * @val:                Options for the mux register value
+ */
+int omap_mux_init_signal(char *muxname, int val);
+
+#else
+
+static inline int omap_mux_init_gpio(int gpio, int val)
+{
+        return 0;
+}
+static inline int omap_mux_init_signal(char *muxname, int val)
+{
+        return 0;
+}
+
+#endif
+
+/**
+ * omap_mux_get_gpio() - get mux register value based on GPIO number
+ * @gpio:               GPIO number
+ *
+ */
+u16 omap_mux_get_gpio(int gpio);
+
+/**
+ * omap_mux_set_gpio() - set mux register value based on GPIO number
+ * @val:                New mux register value
+ * @gpio:               GPIO number
+ *
+ */
+void omap_mux_set_gpio(u16 val, int gpio);
+
+/**
+ * omap3_mux_init() - initialize mux system with board specific set
+ * @board_mux:          Board specific mux table
+ * @flags:              OMAP package type used for the board
+ */
+int omap3_mux_init(struct omap_board_mux *board_mux, int flags);
+
+/**
+ * omap_mux_init - private mux init function, do not call
+ */
+int omap_mux_init(u32 mux_pbase, u32 mux_size,
+                                struct omap_mux *superset,
+                                struct omap_mux *package_subset,
+                                struct omap_board_mux *board_mux,
+                                struct omap_ball *package_balls);
diff --git a/arch/arm/mach-omap2/mux34xx.c b/arch/arm/mach-omap2/mux34xx.c
new file mode 100644
index 000000000000..68e0a595f9a1
--- /dev/null
+++ b/arch/arm/mach-omap2/mux34xx.c
@@ -0,0 +1,2099 @@
+/*
+ * Copyright (C) 2009 Nokia
+ * Copyright (C) 2009 Texas Instruments
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/module.h>
+#include <linux/init.h>
+
+#include "mux.h"
+
+#ifdef CONFIG_OMAP_MUX
+
+#define _OMAP3_MUXENTRY(M0, g, m0, m1, m2, m3, m4, m5, m6, m7)          \
+{                                                                       \
+        .reg_offset     = (OMAP3_CONTROL_PADCONF_##M0##_OFFSET),        \
+        .gpio           = (g),                                          \
+        .muxnames       = { m0, m1, m2, m3, m4, m5, m6, m7 },           \
+}
+
+#else
+
+#define _OMAP3_MUXENTRY(M0, g, m0, m1, m2, m3, m4, m5, m6, m7)          \
+{                                                                       \
+        .reg_offset     = (OMAP3_CONTROL_PADCONF_##M0##_OFFSET),        \
+        .gpio           = (g),                                          \
+}
+
+#endif
+
+#define _OMAP3_BALLENTRY(M0, bb, bt)                                    \
+{                                                                       \
+        .reg_offset     = (OMAP3_CONTROL_PADCONF_##M0##_OFFSET),        \
+        .balls          = { bb, bt },                                   \
+}
+
+/*
+ * Superset of all mux modes for omap3
+ */
+static struct omap_mux __initdata omap3_muxmodes[] = {
+        _OMAP3_MUXENTRY(CAM_D0, 99,
+                "cam_d0", NULL, NULL, NULL,
+                "gpio_99", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(CAM_D1, 100,
+                "cam_d1", NULL, NULL, NULL,
+                "gpio_100", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(CAM_D10, 109,
+                "cam_d10", NULL, NULL, NULL,
+                "gpio_109", "hw_dbg8", NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(CAM_D11, 110,
+                "cam_d11", NULL, NULL, NULL,
+                "gpio_110", "hw_dbg9", NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(CAM_D2, 101,
+                "cam_d2", NULL, NULL, NULL,
+                "gpio_101", "hw_dbg4", NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(CAM_D3, 102,
+                "cam_d3", NULL, NULL, NULL,
+                "gpio_102", "hw_dbg5", NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(CAM_D4, 103,
+                "cam_d4", NULL, NULL, NULL,
+                "gpio_103", "hw_dbg6", NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(CAM_D5, 104,
+                "cam_d5", NULL, NULL, NULL,
+                "gpio_104", "hw_dbg7", NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(CAM_D6, 105,
+                "cam_d6", NULL, NULL, NULL,
+                "gpio_105", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(CAM_D7, 106,
+                "cam_d7", NULL, NULL, NULL,
+                "gpio_106", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(CAM_D8, 107,
+                "cam_d8", NULL, NULL, NULL,
+                "gpio_107", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(CAM_D9, 108,
+                "cam_d9", NULL, NULL, NULL,
+                "gpio_108", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(CAM_FLD, 98,
+                "cam_fld", NULL, "cam_global_reset", NULL,
+                "gpio_98", "hw_dbg3", NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(CAM_HS, 94,
+                "cam_hs", NULL, NULL, NULL,
+                "gpio_94", "hw_dbg0", NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(CAM_PCLK, 97,
+                "cam_pclk", NULL, NULL, NULL,
+                "gpio_97", "hw_dbg2", NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(CAM_STROBE, 126,
+                "cam_strobe", NULL, NULL, NULL,
+                "gpio_126", "hw_dbg11", NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(CAM_VS, 95,
+                "cam_vs", NULL, NULL, NULL,
+                "gpio_95", "hw_dbg1", NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(CAM_WEN, 167,
+                "cam_wen", NULL, "cam_shutter", NULL,
+                "gpio_167", "hw_dbg10", NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(CAM_XCLKA, 96,
+                "cam_xclka", NULL, NULL, NULL,
+                "gpio_96", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(CAM_XCLKB, 111,
+                "cam_xclkb", NULL, NULL, NULL,
+                "gpio_111", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(CSI2_DX0, 112,
+                "csi2_dx0", NULL, NULL, NULL,
+                "gpio_112", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(CSI2_DX1, 114,
+                "csi2_dx1", NULL, NULL, NULL,
+                "gpio_114", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(CSI2_DY0, 113,
+                "csi2_dy0", NULL, NULL, NULL,
+                "gpio_113", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(CSI2_DY1, 115,
+                "csi2_dy1", NULL, NULL, NULL,
+                "gpio_115", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(DSS_ACBIAS, 69,
+                "dss_acbias", NULL, NULL, NULL,
+                "gpio_69", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(DSS_DATA0, 70,
+                "dss_data0", NULL, "uart1_cts", NULL,
+                "gpio_70", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(DSS_DATA1, 71,
+                "dss_data1", NULL, "uart1_rts", NULL,
+                "gpio_71", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(DSS_DATA10, 80,
+                "dss_data10", NULL, NULL, NULL,
+                "gpio_80", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(DSS_DATA11, 81,
+                "dss_data11", NULL, NULL, NULL,
+                "gpio_81", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(DSS_DATA12, 82,
+                "dss_data12", NULL, NULL, NULL,
+                "gpio_82", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(DSS_DATA13, 83,
+                "dss_data13", NULL, NULL, NULL,
+                "gpio_83", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(DSS_DATA14, 84,
+                "dss_data14", NULL, NULL, NULL,
+                "gpio_84", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(DSS_DATA15, 85,
+                "dss_data15", NULL, NULL, NULL,
+                "gpio_85", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(DSS_DATA16, 86,
+                "dss_data16", NULL, NULL, NULL,
+                "gpio_86", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(DSS_DATA17, 87,
+                "dss_data17", NULL, NULL, NULL,
+                "gpio_87", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(DSS_DATA18, 88,
+                "dss_data18", NULL, "mcspi3_clk", "dss_data0",
+                "gpio_88", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(DSS_DATA19, 89,
+                "dss_data19", NULL, "mcspi3_simo", "dss_data1",
+                "gpio_89", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(DSS_DATA20, 90,
+                "dss_data20", NULL, "mcspi3_somi", "dss_data2",
+                "gpio_90", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(DSS_DATA21, 91,
+                "dss_data21", NULL, "mcspi3_cs0", "dss_data3",
+                "gpio_91", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(DSS_DATA22, 92,
+                "dss_data22", NULL, "mcspi3_cs1", "dss_data4",
+                "gpio_92", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(DSS_DATA23, 93,
+                "dss_data23", NULL, NULL, "dss_data5",
+                "gpio_93", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(DSS_DATA2, 72,
+                "dss_data2", NULL, NULL, NULL,
+                "gpio_72", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(DSS_DATA3, 73,
+                "dss_data3", NULL, NULL, NULL,
+                "gpio_73", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(DSS_DATA4, 74,
+                "dss_data4", NULL, "uart3_rx_irrx", NULL,
+                "gpio_74", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(DSS_DATA5, 75,
+                "dss_data5", NULL, "uart3_tx_irtx", NULL,
+                "gpio_75", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(DSS_DATA6, 76,
+                "dss_data6", NULL, "uart1_tx", NULL,
+                "gpio_76", "hw_dbg14", NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(DSS_DATA7, 77,
+                "dss_data7", NULL, "uart1_rx", NULL,
+                "gpio_77", "hw_dbg15", NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(DSS_DATA8, 78,
+                "dss_data8", NULL, NULL, NULL,
+                "gpio_78", "hw_dbg16", NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(DSS_DATA9, 79,
+                "dss_data9", NULL, NULL, NULL,
+                "gpio_79", "hw_dbg17", NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(DSS_HSYNC, 67,
+                "dss_hsync", NULL, NULL, NULL,
+                "gpio_67", "hw_dbg13", NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(DSS_PCLK, 66,
+                "dss_pclk", NULL, NULL, NULL,
+                "gpio_66", "hw_dbg12", NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(DSS_VSYNC, 68,
+                "dss_vsync", NULL, NULL, NULL,
+                "gpio_68", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(ETK_CLK, 12,
+                "etk_clk", "mcbsp5_clkx", "sdmmc3_clk", "hsusb1_stp",
+                "gpio_12", "mm1_rxdp", "hsusb1_tll_stp", "hw_dbg0"),
+        _OMAP3_MUXENTRY(ETK_CTL, 13,
+                "etk_ctl", NULL, "sdmmc3_cmd", "hsusb1_clk",
+                "gpio_13", NULL, "hsusb1_tll_clk", "hw_dbg1"),
+        _OMAP3_MUXENTRY(ETK_D0, 14,
+                "etk_d0", "mcspi3_simo", "sdmmc3_dat4", "hsusb1_data0",
+                "gpio_14", "mm1_rxrcv", "hsusb1_tll_data0", "hw_dbg2"),
+        _OMAP3_MUXENTRY(ETK_D1, 15,
+                "etk_d1", "mcspi3_somi", NULL, "hsusb1_data1",
+                "gpio_15", "mm1_txse0", "hsusb1_tll_data1", "hw_dbg3"),
+        _OMAP3_MUXENTRY(ETK_D10, 24,
+                "etk_d10", NULL, "uart1_rx", "hsusb2_clk",
+                "gpio_24", NULL, "hsusb2_tll_clk", "hw_dbg12"),
+        _OMAP3_MUXENTRY(ETK_D11, 25,
+                "etk_d11", NULL, NULL, "hsusb2_stp",
+                "gpio_25", "mm2_rxdp", "hsusb2_tll_stp", "hw_dbg13"),
+        _OMAP3_MUXENTRY(ETK_D12, 26,
+                "etk_d12", NULL, NULL, "hsusb2_dir",
+                "gpio_26", NULL, "hsusb2_tll_dir", "hw_dbg14"),
+        _OMAP3_MUXENTRY(ETK_D13, 27,
+                "etk_d13", NULL, NULL, "hsusb2_nxt",
+                "gpio_27", "mm2_rxdm", "hsusb2_tll_nxt", "hw_dbg15"),
+        _OMAP3_MUXENTRY(ETK_D14, 28,
+                "etk_d14", NULL, NULL, "hsusb2_data0",
+                "gpio_28", "mm2_rxrcv", "hsusb2_tll_data0", "hw_dbg16"),
+        _OMAP3_MUXENTRY(ETK_D15, 29,
+                "etk_d15", NULL, NULL, "hsusb2_data1",
+                "gpio_29", "mm2_txse0", "hsusb2_tll_data1", "hw_dbg17"),
+        _OMAP3_MUXENTRY(ETK_D2, 16,
+                "etk_d2", "mcspi3_cs0", NULL, "hsusb1_data2",
+                "gpio_16", "mm1_txdat", "hsusb1_tll_data2", "hw_dbg4"),
+        _OMAP3_MUXENTRY(ETK_D3, 17,
+                "etk_d3", "mcspi3_clk", "sdmmc3_dat3", "hsusb1_data7",
+                "gpio_17", NULL, "hsusb1_tll_data7", "hw_dbg5"),
+        _OMAP3_MUXENTRY(ETK_D4, 18,
+                "etk_d4", "mcbsp5_dr", "sdmmc3_dat0", "hsusb1_data4",
+                "gpio_18", NULL, "hsusb1_tll_data4", "hw_dbg6"),
+        _OMAP3_MUXENTRY(ETK_D5, 19,
+                "etk_d5", "mcbsp5_fsx", "sdmmc3_dat1", "hsusb1_data5",
+                "gpio_19", NULL, "hsusb1_tll_data5", "hw_dbg7"),
+        _OMAP3_MUXENTRY(ETK_D6, 20,
+                "etk_d6", "mcbsp5_dx", "sdmmc3_dat2", "hsusb1_data6",
+                "gpio_20", NULL, "hsusb1_tll_data6", "hw_dbg8"),
+        _OMAP3_MUXENTRY(ETK_D7, 21,
+                "etk_d7", "mcspi3_cs1", "sdmmc3_dat7", "hsusb1_data3",
+                "gpio_21", "mm1_txen_n", "hsusb1_tll_data3", "hw_dbg9"),
+        _OMAP3_MUXENTRY(ETK_D8, 22,
+                "etk_d8", "sys_drm_msecure", "sdmmc3_dat6", "hsusb1_dir",
+                "gpio_22", NULL, "hsusb1_tll_dir", "hw_dbg10"),
+        _OMAP3_MUXENTRY(ETK_D9, 23,
+                "etk_d9", "sys_secure_indicator", "sdmmc3_dat5", "hsusb1_nxt",
+                "gpio_23", "mm1_rxdm", "hsusb1_tll_nxt", "hw_dbg11"),
+        _OMAP3_MUXENTRY(GPMC_A1, 34,
+                "gpmc_a1", NULL, NULL, NULL,
+                "gpio_34", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(GPMC_A10, 43,
+                "gpmc_a10", "sys_ndmareq3", NULL, NULL,
+                "gpio_43", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(GPMC_A2, 35,
+                "gpmc_a2", NULL, NULL, NULL,
+                "gpio_35", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(GPMC_A3, 36,
+                "gpmc_a3", NULL, NULL, NULL,
+                "gpio_36", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(GPMC_A4, 37,
+                "gpmc_a4", NULL, NULL, NULL,
+                "gpio_37", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(GPMC_A5, 38,
+                "gpmc_a5", NULL, NULL, NULL,
+                "gpio_38", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(GPMC_A6, 39,
+                "gpmc_a6", NULL, NULL, NULL,
+                "gpio_39", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(GPMC_A7, 40,
+                "gpmc_a7", NULL, NULL, NULL,
+                "gpio_40", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(GPMC_A8, 41,
+                "gpmc_a8", NULL, NULL, NULL,
+                "gpio_41", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(GPMC_A9, 42,
+                "gpmc_a9", "sys_ndmareq2", NULL, NULL,
+                "gpio_42", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(GPMC_CLK, 59,
+                "gpmc_clk", NULL, NULL, NULL,
+                "gpio_59", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(GPMC_D10, 46,
+                "gpmc_d10", NULL, NULL, NULL,
+                "gpio_46", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(GPMC_D11, 47,
+                "gpmc_d11", NULL, NULL, NULL,
+                "gpio_47", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(GPMC_D12, 48,
+                "gpmc_d12", NULL, NULL, NULL,
+                "gpio_48", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(GPMC_D13, 49,
+                "gpmc_d13", NULL, NULL, NULL,
+                "gpio_49", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(GPMC_D14, 50,
+                "gpmc_d14", NULL, NULL, NULL,
+                "gpio_50", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(GPMC_D15, 51,
+                "gpmc_d15", NULL, NULL, NULL,
+                "gpio_51", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(GPMC_D8, 44,
+                "gpmc_d8", NULL, NULL, NULL,
+                "gpio_44", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(GPMC_D9, 45,
+                "gpmc_d9", NULL, NULL, NULL,
+                "gpio_45", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(GPMC_NBE0_CLE, 60,
+                "gpmc_nbe0_cle", NULL, NULL, NULL,
+                "gpio_60", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(GPMC_NBE1, 61,
+                "gpmc_nbe1", NULL, NULL, NULL,
+                "gpio_61", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(GPMC_NCS1, 52,
+                "gpmc_ncs1", NULL, NULL, NULL,
+                "gpio_52", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(GPMC_NCS2, 53,
+                "gpmc_ncs2", NULL, NULL, NULL,
+                "gpio_53", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(GPMC_NCS3, 54,
+                "gpmc_ncs3", "sys_ndmareq0", NULL, NULL,
+                "gpio_54", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(GPMC_NCS4, 55,
+                "gpmc_ncs4", "sys_ndmareq1", "mcbsp4_clkx", "gpt9_pwm_evt",
+                "gpio_55", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(GPMC_NCS5, 56,
+                "gpmc_ncs5", "sys_ndmareq2", "mcbsp4_dr", "gpt10_pwm_evt",
+                "gpio_56", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(GPMC_NCS6, 57,
+                "gpmc_ncs6", "sys_ndmareq3", "mcbsp4_dx", "gpt11_pwm_evt",
+                "gpio_57", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(GPMC_NCS7, 58,
+                "gpmc_ncs7", "gpmc_io_dir", "mcbsp4_fsx", "gpt8_pwm_evt",
+                "gpio_58", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(GPMC_NWP, 62,
+                "gpmc_nwp", NULL, NULL, NULL,
+                "gpio_62", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(GPMC_WAIT1, 63,
+                "gpmc_wait1", NULL, NULL, NULL,
+                "gpio_63", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(GPMC_WAIT2, 64,
+                "gpmc_wait2", NULL, NULL, NULL,
+                "gpio_64", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(GPMC_WAIT3, 65,
+                "gpmc_wait3", "sys_ndmareq1", NULL, NULL,
+                "gpio_65", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(HDQ_SIO, 170,
+                "hdq_sio", "sys_altclk", "i2c2_sccbe", "i2c3_sccbe",
+                "gpio_170", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(HSUSB0_CLK, 120,
+                "hsusb0_clk", NULL, NULL, NULL,
+                "gpio_120", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(HSUSB0_DATA0, 125,
+                "hsusb0_data0", NULL, "uart3_tx_irtx", NULL,
+                "gpio_125", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(HSUSB0_DATA1, 130,
+                "hsusb0_data1", NULL, "uart3_rx_irrx", NULL,
+                "gpio_130", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(HSUSB0_DATA2, 131,
+                "hsusb0_data2", NULL, "uart3_rts_sd", NULL,
+                "gpio_131", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(HSUSB0_DATA3, 169,
+                "hsusb0_data3", NULL, "uart3_cts_rctx", NULL,
+                "gpio_169", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(HSUSB0_DATA4, 188,
+                "hsusb0_data4", NULL, NULL, NULL,
+                "gpio_188", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(HSUSB0_DATA5, 189,
+                "hsusb0_data5", NULL, NULL, NULL,
+                "gpio_189", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(HSUSB0_DATA6, 190,
+                "hsusb0_data6", NULL, NULL, NULL,
+                "gpio_190", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(HSUSB0_DATA7, 191,
+                "hsusb0_data7", NULL, NULL, NULL,
+                "gpio_191", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(HSUSB0_DIR, 122,
+                "hsusb0_dir", NULL, NULL, NULL,
+                "gpio_122", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(HSUSB0_NXT, 124,
+                "hsusb0_nxt", NULL, NULL, NULL,
+                "gpio_124", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(HSUSB0_STP, 121,
+                "hsusb0_stp", NULL, NULL, NULL,
+                "gpio_121", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(I2C2_SCL, 168,
+                "i2c2_scl", NULL, NULL, NULL,
+                "gpio_168", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(I2C2_SDA, 183,
+                "i2c2_sda", NULL, NULL, NULL,
+                "gpio_183", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(I2C3_SCL, 184,
+                "i2c3_scl", NULL, NULL, NULL,
+                "gpio_184", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(I2C3_SDA, 185,
+                "i2c3_sda", NULL, NULL, NULL,
+                "gpio_185", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(I2C4_SCL, 0,
+                "i2c4_scl", "sys_nvmode1", NULL, NULL,
+                NULL, NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(I2C4_SDA, 0,
+                "i2c4_sda", "sys_nvmode2", NULL, NULL,
+                NULL, NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(JTAG_EMU0, 11,
+                "jtag_emu0", NULL, NULL, NULL,
+                "gpio_11", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(JTAG_EMU1, 31,
+                "jtag_emu1", NULL, NULL, NULL,
+                "gpio_31", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(MCBSP1_CLKR, 156,
+                "mcbsp1_clkr", "mcspi4_clk", NULL, NULL,
+                "gpio_156", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(MCBSP1_CLKX, 162,
+                "mcbsp1_clkx", NULL, "mcbsp3_clkx", NULL,
+                "gpio_162", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(MCBSP1_DR, 159,
+                "mcbsp1_dr", "mcspi4_somi", "mcbsp3_dr", NULL,
+                "gpio_159", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(MCBSP1_DX, 158,
+                "mcbsp1_dx", "mcspi4_simo", "mcbsp3_dx", NULL,
+                "gpio_158", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(MCBSP1_FSR, 157,
+                "mcbsp1_fsr", NULL, "cam_global_reset", NULL,
+                "gpio_157", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(MCBSP1_FSX, 161,
+                "mcbsp1_fsx", "mcspi4_cs0", "mcbsp3_fsx", NULL,
+                "gpio_161", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(MCBSP2_CLKX, 117,
+                "mcbsp2_clkx", NULL, NULL, NULL,
+                "gpio_117", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(MCBSP2_DR, 118,
+                "mcbsp2_dr", NULL, NULL, NULL,
+                "gpio_118", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(MCBSP2_DX, 119,
+                "mcbsp2_dx", NULL, NULL, NULL,
+                "gpio_119", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(MCBSP2_FSX, 116,
+                "mcbsp2_fsx", NULL, NULL, NULL,
+                "gpio_116", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(MCBSP3_CLKX, 142,
+                "mcbsp3_clkx", "uart2_tx", NULL, NULL,
+                "gpio_142", "hsusb3_tll_data6", NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(MCBSP3_DR, 141,
+                "mcbsp3_dr", "uart2_rts", NULL, NULL,
+                "gpio_141", "hsusb3_tll_data5", NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(MCBSP3_DX, 140,
+                "mcbsp3_dx", "uart2_cts", NULL, NULL,
+                "gpio_140", "hsusb3_tll_data4", NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(MCBSP3_FSX, 143,
+                "mcbsp3_fsx", "uart2_rx", NULL, NULL,
+                "gpio_143", "hsusb3_tll_data7", NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(MCBSP4_CLKX, 152,
+                "mcbsp4_clkx", NULL, NULL, NULL,
+                "gpio_152", "hsusb3_tll_data1", "mm3_txse0", "safe_mode"),
+        _OMAP3_MUXENTRY(MCBSP4_DR, 153,
+                "mcbsp4_dr", NULL, NULL, NULL,
+                "gpio_153", "hsusb3_tll_data0", "mm3_rxrcv", "safe_mode"),
+        _OMAP3_MUXENTRY(MCBSP4_DX, 154,
+                "mcbsp4_dx", NULL, NULL, NULL,
+                "gpio_154", "hsusb3_tll_data2", "mm3_txdat", "safe_mode"),
+        _OMAP3_MUXENTRY(MCBSP4_FSX, 155,
+                "mcbsp4_fsx", NULL, NULL, NULL,
+                "gpio_155", "hsusb3_tll_data3", "mm3_txen_n", "safe_mode"),
+        _OMAP3_MUXENTRY(MCBSP_CLKS, 160,
+                "mcbsp_clks", NULL, "cam_shutter", NULL,
+                "gpio_160", "uart1_cts", NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(MCSPI1_CLK, 171,
+                "mcspi1_clk", "sdmmc2_dat4", NULL, NULL,
+                "gpio_171", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(MCSPI1_CS0, 174,
+                "mcspi1_cs0", "sdmmc2_dat7", NULL, NULL,
+                "gpio_174", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(MCSPI1_CS1, 175,
+                "mcspi1_cs1", NULL, NULL, "sdmmc3_cmd",
+                "gpio_175", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(MCSPI1_CS2, 176,
+                "mcspi1_cs2", NULL, NULL, "sdmmc3_clk",
+                "gpio_176", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(MCSPI1_CS3, 177,
+                "mcspi1_cs3", NULL, "hsusb2_tll_data2", "hsusb2_data2",
+                "gpio_177", "mm2_txdat", NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(MCSPI1_SIMO, 172,
+                "mcspi1_simo", "sdmmc2_dat5", NULL, NULL,
+                "gpio_172", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(MCSPI1_SOMI, 173,
+                "mcspi1_somi", "sdmmc2_dat6", NULL, NULL,
+                "gpio_173", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(MCSPI2_CLK, 178,
+                "mcspi2_clk", NULL, "hsusb2_tll_data7", "hsusb2_data7",
+                "gpio_178", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(MCSPI2_CS0, 181,
+                "mcspi2_cs0", "gpt11_pwm_evt",
+                "hsusb2_tll_data6", "hsusb2_data6",
+                "gpio_181", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(MCSPI2_CS1, 182,
+                "mcspi2_cs1", "gpt8_pwm_evt",
+                "hsusb2_tll_data3", "hsusb2_data3",
+                "gpio_182", "mm2_txen_n", NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(MCSPI2_SIMO, 179,
+                "mcspi2_simo", "gpt9_pwm_evt",
+                "hsusb2_tll_data4", "hsusb2_data4",
+                "gpio_179", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(MCSPI2_SOMI, 180,
+                "mcspi2_somi", "gpt10_pwm_evt",
+                "hsusb2_tll_data5", "hsusb2_data5",
+                "gpio_180", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(SDMMC1_CLK, 120,
+                "sdmmc1_clk", NULL, NULL, NULL,
+                "gpio_120", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(SDMMC1_CMD, 121,
+                "sdmmc1_cmd", NULL, NULL, NULL,
+                "gpio_121", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(SDMMC1_DAT0, 122,
+                "sdmmc1_dat0", NULL, NULL, NULL,
+                "gpio_122", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(SDMMC1_DAT1, 123,
+                "sdmmc1_dat1", NULL, NULL, NULL,
+                "gpio_123", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(SDMMC1_DAT2, 124,
+                "sdmmc1_dat2", NULL, NULL, NULL,
+                "gpio_124", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(SDMMC1_DAT3, 125,
+                "sdmmc1_dat3", NULL, NULL, NULL,
+                "gpio_125", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(SDMMC1_DAT4, 126,
+                "sdmmc1_dat4", NULL, "sim_io", NULL,
+                "gpio_126", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(SDMMC1_DAT5, 127,
+                "sdmmc1_dat5", NULL, "sim_clk", NULL,
+                "gpio_127", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(SDMMC1_DAT6, 128,
+                "sdmmc1_dat6", NULL, "sim_pwrctrl", NULL,
+                "gpio_128", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(SDMMC1_DAT7, 129,
+                "sdmmc1_dat7", NULL, "sim_rst", NULL,
+                "gpio_129", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(SDMMC2_CLK, 130,
+                "sdmmc2_clk", "mcspi3_clk", NULL, NULL,
+                "gpio_130", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(SDMMC2_CMD, 131,
+                "sdmmc2_cmd", "mcspi3_simo", NULL, NULL,
+                "gpio_131", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(SDMMC2_DAT0, 132,
+                "sdmmc2_dat0", "mcspi3_somi", NULL, NULL,
+                "gpio_132", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(SDMMC2_DAT1, 133,
+                "sdmmc2_dat1", NULL, NULL, NULL,
+                "gpio_133", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(SDMMC2_DAT2, 134,
+                "sdmmc2_dat2", "mcspi3_cs1", NULL, NULL,
+                "gpio_134", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(SDMMC2_DAT3, 135,
+                "sdmmc2_dat3", "mcspi3_cs0", NULL, NULL,
+                "gpio_135", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(SDMMC2_DAT4, 136,
+                "sdmmc2_dat4", "sdmmc2_dir_dat0", NULL, "sdmmc3_dat0",
+                "gpio_136", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(SDMMC2_DAT5, 137,
+                "sdmmc2_dat5", "sdmmc2_dir_dat1",
+                "cam_global_reset", "sdmmc3_dat1",
+                "gpio_137", "hsusb3_tll_stp", "mm3_rxdp", "safe_mode"),
+        _OMAP3_MUXENTRY(SDMMC2_DAT6, 138,
+                "sdmmc2_dat6", "sdmmc2_dir_cmd", "cam_shutter", "sdmmc3_dat2",
+                "gpio_138", "hsusb3_tll_dir", NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(SDMMC2_DAT7, 139,
+                "sdmmc2_dat7", "sdmmc2_clkin", NULL, "sdmmc3_dat3",
+                "gpio_139", "hsusb3_tll_nxt", "mm3_rxdm", "safe_mode"),
+        _OMAP3_MUXENTRY(SDRC_CKE0, 0,
+                "sdrc_cke0", NULL, NULL, NULL,
+                NULL, NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(SDRC_CKE1, 0,
+                "sdrc_cke1", NULL, NULL, NULL,
+                NULL, NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(SYS_BOOT0, 2,
+                "sys_boot0", NULL, NULL, NULL,
+                "gpio_2", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(SYS_BOOT1, 3,
+                "sys_boot1", NULL, NULL, NULL,
+                "gpio_3", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(SYS_BOOT2, 4,
+                "sys_boot2", NULL, NULL, NULL,
+                "gpio_4", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(SYS_BOOT3, 5,
+                "sys_boot3", NULL, NULL, NULL,
+                "gpio_5", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(SYS_BOOT4, 6,
+                "sys_boot4", "sdmmc2_dir_dat2", NULL, NULL,
+                "gpio_6", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(SYS_BOOT5, 7,
+                "sys_boot5", "sdmmc2_dir_dat3", NULL, NULL,
+                "gpio_7", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(SYS_BOOT6, 8,
+                "sys_boot6", NULL, NULL, NULL,
+                "gpio_8", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(SYS_CLKOUT1, 10,
+                "sys_clkout1", NULL, NULL, NULL,
+                "gpio_10", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(SYS_CLKOUT2, 186,
+                "sys_clkout2", NULL, NULL, NULL,
+                "gpio_186", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(SYS_CLKREQ, 1,
+                "sys_clkreq", NULL, NULL, NULL,
+                "gpio_1", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(SYS_NIRQ, 0,
+                "sys_nirq", NULL, NULL, NULL,
+                "gpio_0", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(SYS_NRESWARM, 30,
+                "sys_nreswarm", NULL, NULL, NULL,
+                "gpio_30", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(SYS_OFF_MODE, 9,
+                "sys_off_mode", NULL, NULL, NULL,
+                "gpio_9", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(UART1_CTS, 150,
+                "uart1_cts", NULL, NULL, NULL,
+                "gpio_150", "hsusb3_tll_clk", NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(UART1_RTS, 149,
+                "uart1_rts", NULL, NULL, NULL,
+                "gpio_149", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(UART1_RX, 151,
+                "uart1_rx", NULL, "mcbsp1_clkr", "mcspi4_clk",
+                "gpio_151", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(UART1_TX, 148,
+                "uart1_tx", NULL, NULL, NULL,
+                "gpio_148", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(UART2_CTS, 144,
+                "uart2_cts", "mcbsp3_dx", "gpt9_pwm_evt", NULL,
+                "gpio_144", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(UART2_RTS, 145,
+                "uart2_rts", "mcbsp3_dr", "gpt10_pwm_evt", NULL,
+                "gpio_145", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(UART2_RX, 147,
+                "uart2_rx", "mcbsp3_fsx", "gpt8_pwm_evt", NULL,
+                "gpio_147", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(UART2_TX, 146,
+                "uart2_tx", "mcbsp3_clkx", "gpt11_pwm_evt", NULL,
+                "gpio_146", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(UART3_CTS_RCTX, 163,
+                "uart3_cts_rctx", NULL, NULL, NULL,
+                "gpio_163", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(UART3_RTS_SD, 164,
+                "uart3_rts_sd", NULL, NULL, NULL,
+                "gpio_164", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(UART3_RX_IRRX, 165,
+                "uart3_rx_irrx", NULL, NULL, NULL,
+                "gpio_165", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(UART3_TX_IRTX, 166,
+                "uart3_tx_irtx", NULL, NULL, NULL,
+                "gpio_166", NULL, NULL, "safe_mode"),
+        { .reg_offset = OMAP_MUX_TERMINATOR },
+};
+
+/*
+ * Signals different on CBC package compared to the superset
+ */
+#if defined(CONFIG_OMAP_MUX) && defined(CONFIG_OMAP_PACKAGE_CBC)
+struct omap_mux __initdata omap3_cbc_subset[] = {
+        { .reg_offset = OMAP_MUX_TERMINATOR },
+};
+#else
+#define omap3_cbc_subset        NULL
+#endif
+
+/*
+ * Balls for CBC package
+ * 515-pin s-PBGA Package, 0.65mm Ball Pitch (Top), 0.50mm Ball Pitch (Bottom)
+ *
+ * FIXME: What's up with the outdated TI documentation? See:
+ *
+ * http://wiki.davincidsp.com/index.php/Datasheet_Errata_for_OMAP35x_CBC_Package
+ * http://community.ti.com/forums/t/10982.aspx
+ */
+#if defined(CONFIG_OMAP_MUX) && defined(CONFIG_DEBUG_FS)        \
+                && defined(CONFIG_OMAP_PACKAGE_CBC)
+struct omap_ball __initdata omap3_cbc_ball[] = {
+        _OMAP3_BALLENTRY(CAM_D0, "ae16", NULL),
+        _OMAP3_BALLENTRY(CAM_D1, "ae15", NULL),
+        _OMAP3_BALLENTRY(CAM_D10, "d25", NULL),
+        _OMAP3_BALLENTRY(CAM_D11, "e26", NULL),
+        _OMAP3_BALLENTRY(CAM_D2, "a24", NULL),
+        _OMAP3_BALLENTRY(CAM_D3, "b24", NULL),
+        _OMAP3_BALLENTRY(CAM_D4, "d24", NULL),
+        _OMAP3_BALLENTRY(CAM_D5, "c24", NULL),
+        _OMAP3_BALLENTRY(CAM_D6, "p25", NULL),
+        _OMAP3_BALLENTRY(CAM_D7, "p26", NULL),
+        _OMAP3_BALLENTRY(CAM_D8, "n25", NULL),
+        _OMAP3_BALLENTRY(CAM_D9, "n26", NULL),
+        _OMAP3_BALLENTRY(CAM_FLD, "b23", NULL),
+        _OMAP3_BALLENTRY(CAM_HS, "c23", NULL),
+        _OMAP3_BALLENTRY(CAM_PCLK, "c26", NULL),
+        _OMAP3_BALLENTRY(CAM_STROBE, "d26", NULL),
+        _OMAP3_BALLENTRY(CAM_VS, "d23", NULL),
+        _OMAP3_BALLENTRY(CAM_WEN, "a23", NULL),
+        _OMAP3_BALLENTRY(CAM_XCLKA, "c25", NULL),
+        _OMAP3_BALLENTRY(CAM_XCLKB, "e25", NULL),
+        _OMAP3_BALLENTRY(CSI2_DX0, "ad17", NULL),
+        _OMAP3_BALLENTRY(CSI2_DX1, "ae18", NULL),
+        _OMAP3_BALLENTRY(CSI2_DY0, "ad16", NULL),
+        _OMAP3_BALLENTRY(CSI2_DY1, "ae17", NULL),
+        _OMAP3_BALLENTRY(DSS_ACBIAS, "f26", NULL),
+        _OMAP3_BALLENTRY(DSS_DATA0, "ae21", NULL),
+        _OMAP3_BALLENTRY(DSS_DATA1, "ae22", NULL),
+        _OMAP3_BALLENTRY(DSS_DATA10, "ac26", NULL),
+        _OMAP3_BALLENTRY(DSS_DATA11, "ad26", NULL),
+        _OMAP3_BALLENTRY(DSS_DATA12, "aa25", NULL),
+        _OMAP3_BALLENTRY(DSS_DATA13, "y25", NULL),
+        _OMAP3_BALLENTRY(DSS_DATA14, "aa26", NULL),
+        _OMAP3_BALLENTRY(DSS_DATA15, "ab26", NULL),
+        _OMAP3_BALLENTRY(DSS_DATA16, "l25", NULL),
+        _OMAP3_BALLENTRY(DSS_DATA17, "l26", NULL),
+        _OMAP3_BALLENTRY(DSS_DATA18, "m24", NULL),
+        _OMAP3_BALLENTRY(DSS_DATA19, "m26", NULL),
+        _OMAP3_BALLENTRY(DSS_DATA2, "ae23", NULL),
+        _OMAP3_BALLENTRY(DSS_DATA20, "f25", NULL),
+        _OMAP3_BALLENTRY(DSS_DATA21, "n24", NULL),
+        _OMAP3_BALLENTRY(DSS_DATA22, "ac25", NULL),
+        _OMAP3_BALLENTRY(DSS_DATA23, "ab25", NULL),
+        _OMAP3_BALLENTRY(DSS_DATA3, "ae24", NULL),
+        _OMAP3_BALLENTRY(DSS_DATA4, "ad23", NULL),
+        _OMAP3_BALLENTRY(DSS_DATA5, "ad24", NULL),
+        _OMAP3_BALLENTRY(DSS_DATA6, "g26", NULL),
+        _OMAP3_BALLENTRY(DSS_DATA7, "h25", NULL),
+        _OMAP3_BALLENTRY(DSS_DATA8, "h26", NULL),
+        _OMAP3_BALLENTRY(DSS_DATA9, "j26", NULL),
+        _OMAP3_BALLENTRY(DSS_HSYNC, "k24", NULL),
+        _OMAP3_BALLENTRY(DSS_PCLK, "g25", NULL),
+        _OMAP3_BALLENTRY(DSS_VSYNC, "m25", NULL),
+        _OMAP3_BALLENTRY(ETK_CLK, "ab2", NULL),
+        _OMAP3_BALLENTRY(ETK_CTL, "ab3", NULL),
+        _OMAP3_BALLENTRY(ETK_D0, "ac3", NULL),
+        _OMAP3_BALLENTRY(ETK_D1, "ad4", NULL),
+        _OMAP3_BALLENTRY(ETK_D10, "ae4", NULL),
+        _OMAP3_BALLENTRY(ETK_D11, "af6", NULL),
+        _OMAP3_BALLENTRY(ETK_D12, "ae6", NULL),
+        _OMAP3_BALLENTRY(ETK_D13, "af7", NULL),
+        _OMAP3_BALLENTRY(ETK_D14, "af9", NULL),
+        _OMAP3_BALLENTRY(ETK_D15, "ae9", NULL),
+        _OMAP3_BALLENTRY(ETK_D2, "ad3", NULL),
+        _OMAP3_BALLENTRY(ETK_D3, "aa3", NULL),
+        _OMAP3_BALLENTRY(ETK_D4, "y3", NULL),
+        _OMAP3_BALLENTRY(ETK_D5, "ab1", NULL),
+        _OMAP3_BALLENTRY(ETK_D6, "ae3", NULL),
+        _OMAP3_BALLENTRY(ETK_D7, "ad2", NULL),
+        _OMAP3_BALLENTRY(ETK_D8, "aa4", NULL),
+        _OMAP3_BALLENTRY(ETK_D9, "v2", NULL),
+        _OMAP3_BALLENTRY(GPMC_A1, "j2", NULL),
+        _OMAP3_BALLENTRY(GPMC_A10, "d2", NULL),
+        _OMAP3_BALLENTRY(GPMC_A2, "h1", NULL),
+        _OMAP3_BALLENTRY(GPMC_A3, "h2", NULL),
+        _OMAP3_BALLENTRY(GPMC_A4, "g2", NULL),
+        _OMAP3_BALLENTRY(GPMC_A5, "f1", NULL),
+        _OMAP3_BALLENTRY(GPMC_A6, "f2", NULL),
+        _OMAP3_BALLENTRY(GPMC_A7, "e1", NULL),
+        _OMAP3_BALLENTRY(GPMC_A8, "e2", NULL),
+        _OMAP3_BALLENTRY(GPMC_A9, "d1", NULL),
+        _OMAP3_BALLENTRY(GPMC_CLK, "n1", "l1"),
+        _OMAP3_BALLENTRY(GPMC_D10, "t1", "n1"),
+        _OMAP3_BALLENTRY(GPMC_D11, "u2", "p2"),
+        _OMAP3_BALLENTRY(GPMC_D12, "u1", "p1"),
+        _OMAP3_BALLENTRY(GPMC_D13, "p1", "m1"),
+        _OMAP3_BALLENTRY(GPMC_D14, "l2", "j2"),
+        _OMAP3_BALLENTRY(GPMC_D15, "m2", "k2"),
+        _OMAP3_BALLENTRY(GPMC_D8, "v1", "r1"),
+        _OMAP3_BALLENTRY(GPMC_D9, "y1", "t1"),
+        _OMAP3_BALLENTRY(GPMC_NBE0_CLE, "k2", NULL),
+        _OMAP3_BALLENTRY(GPMC_NBE1, "j1", NULL),
+        _OMAP3_BALLENTRY(GPMC_NCS1, "ad1", "w1"),
+        _OMAP3_BALLENTRY(GPMC_NCS2, "a3", NULL),
+        _OMAP3_BALLENTRY(GPMC_NCS3, "b6", NULL),
+        _OMAP3_BALLENTRY(GPMC_NCS4, "b4", NULL),
+        _OMAP3_BALLENTRY(GPMC_NCS5, "c4", NULL),
+        _OMAP3_BALLENTRY(GPMC_NCS6, "b5", NULL),
+        _OMAP3_BALLENTRY(GPMC_NCS7, "c5", NULL),
+        _OMAP3_BALLENTRY(GPMC_NWP, "ac6", "y5"),
+        _OMAP3_BALLENTRY(GPMC_WAIT1, "ac8", "y8"),
+        _OMAP3_BALLENTRY(GPMC_WAIT2, "b3", NULL),
+        _OMAP3_BALLENTRY(GPMC_WAIT3, "c6", NULL),
+        _OMAP3_BALLENTRY(HDQ_SIO, "j23", NULL),
+        _OMAP3_BALLENTRY(HSUSB0_CLK, "w19", NULL),
+        _OMAP3_BALLENTRY(HSUSB0_DATA0, "v20", NULL),
+        _OMAP3_BALLENTRY(HSUSB0_DATA1, "y20", NULL),
+        _OMAP3_BALLENTRY(HSUSB0_DATA2, "v18", NULL),
+        _OMAP3_BALLENTRY(HSUSB0_DATA3, "w20", NULL),
+        _OMAP3_BALLENTRY(HSUSB0_DATA4, "w17", NULL),
+        _OMAP3_BALLENTRY(HSUSB0_DATA5, "y18", NULL),
+        _OMAP3_BALLENTRY(HSUSB0_DATA6, "y19", NULL),
+        _OMAP3_BALLENTRY(HSUSB0_DATA7, "y17", NULL),
+        _OMAP3_BALLENTRY(HSUSB0_DIR, "v19", NULL),
+        _OMAP3_BALLENTRY(HSUSB0_NXT, "w18", NULL),
+        _OMAP3_BALLENTRY(HSUSB0_STP, "u20", NULL),
+        _OMAP3_BALLENTRY(I2C2_SCL, "c2", NULL),
+        _OMAP3_BALLENTRY(I2C2_SDA, "c1", NULL),
+        _OMAP3_BALLENTRY(I2C3_SCL, "ab4", NULL),
+        _OMAP3_BALLENTRY(I2C3_SDA, "ac4", NULL),
+        _OMAP3_BALLENTRY(I2C4_SCL, "ad15", NULL),
+        _OMAP3_BALLENTRY(I2C4_SDA, "w16", NULL),
+        _OMAP3_BALLENTRY(JTAG_EMU0, "y15", NULL),
+        _OMAP3_BALLENTRY(JTAG_EMU1, "y14", NULL),
+        _OMAP3_BALLENTRY(MCBSP1_CLKR, "u19", NULL),
+        _OMAP3_BALLENTRY(MCBSP1_CLKX, "t17", NULL),
+        _OMAP3_BALLENTRY(MCBSP1_DR, "t20", NULL),
+        _OMAP3_BALLENTRY(MCBSP1_DX, "u17", NULL),
+        _OMAP3_BALLENTRY(MCBSP1_FSR, "v17", NULL),
+        _OMAP3_BALLENTRY(MCBSP1_FSX, "p20", NULL),
+        _OMAP3_BALLENTRY(MCBSP2_CLKX, "r18", NULL),
+        _OMAP3_BALLENTRY(MCBSP2_DR, "t18", NULL),
+        _OMAP3_BALLENTRY(MCBSP2_DX, "r19", NULL),
+        _OMAP3_BALLENTRY(MCBSP2_FSX, "u18", NULL),
+        _OMAP3_BALLENTRY(MCBSP3_CLKX, "u3", NULL),
+        _OMAP3_BALLENTRY(MCBSP3_DR, "n3", NULL),
+        _OMAP3_BALLENTRY(MCBSP3_DX, "p3", NULL),
+        _OMAP3_BALLENTRY(MCBSP3_FSX, "w3", NULL),
+        _OMAP3_BALLENTRY(MCBSP4_CLKX, "v3", NULL),
+        _OMAP3_BALLENTRY(MCBSP4_DR, "u4", NULL),
+        _OMAP3_BALLENTRY(MCBSP4_DX, "r3", NULL),
+        _OMAP3_BALLENTRY(MCBSP4_FSX, "t3", NULL),
+        _OMAP3_BALLENTRY(MCBSP_CLKS, "t19", NULL),
+        _OMAP3_BALLENTRY(MCSPI1_CLK, "p9", NULL),
+        _OMAP3_BALLENTRY(MCSPI1_CS0, "r7", NULL),
+        _OMAP3_BALLENTRY(MCSPI1_CS1, "r8", NULL),
+        _OMAP3_BALLENTRY(MCSPI1_CS2, "r9", NULL),
+        _OMAP3_BALLENTRY(MCSPI1_CS3, "t8", NULL),
+        _OMAP3_BALLENTRY(MCSPI1_SIMO, "p8", NULL),
+        _OMAP3_BALLENTRY(MCSPI1_SOMI, "p7", NULL),
+        _OMAP3_BALLENTRY(MCSPI2_CLK, "w7", NULL),
+        _OMAP3_BALLENTRY(MCSPI2_CS0, "v8", NULL),
+        _OMAP3_BALLENTRY(MCSPI2_CS1, "v9", NULL),
+        _OMAP3_BALLENTRY(MCSPI2_SIMO, "w8", NULL),
+        _OMAP3_BALLENTRY(MCSPI2_SOMI, "u8", NULL),
+        _OMAP3_BALLENTRY(SDMMC1_CLK, "n19", NULL),
+        _OMAP3_BALLENTRY(SDMMC1_CMD, "l18", NULL),
+        _OMAP3_BALLENTRY(SDMMC1_DAT0, "m19", NULL),
+        _OMAP3_BALLENTRY(SDMMC1_DAT1, "m18", NULL),
+        _OMAP3_BALLENTRY(SDMMC1_DAT2, "k18", NULL),
+        _OMAP3_BALLENTRY(SDMMC1_DAT3, "n20", NULL),
+        _OMAP3_BALLENTRY(SDMMC1_DAT4, "m20", NULL),
+        _OMAP3_BALLENTRY(SDMMC1_DAT5, "p17", NULL),
+        _OMAP3_BALLENTRY(SDMMC1_DAT6, "p18", NULL),
+        _OMAP3_BALLENTRY(SDMMC1_DAT7, "p19", NULL),
+        _OMAP3_BALLENTRY(SDMMC2_CLK, "w10", NULL),
+        _OMAP3_BALLENTRY(SDMMC2_CMD, "r10", NULL),
+        _OMAP3_BALLENTRY(SDMMC2_DAT0, "t10", NULL),
+        _OMAP3_BALLENTRY(SDMMC2_DAT1, "t9", NULL),
+        _OMAP3_BALLENTRY(SDMMC2_DAT2, "u10", NULL),
+        _OMAP3_BALLENTRY(SDMMC2_DAT3, "u9", NULL),
+        _OMAP3_BALLENTRY(SDMMC2_DAT4, "v10", NULL),
+        _OMAP3_BALLENTRY(SDMMC2_DAT5, "m3", NULL),
+        _OMAP3_BALLENTRY(SDMMC2_DAT6, "l3", NULL),
+        _OMAP3_BALLENTRY(SDMMC2_DAT7, "k3", NULL),
+        _OMAP3_BALLENTRY(SYS_BOOT0, "f3", NULL),
+        _OMAP3_BALLENTRY(SYS_BOOT1, "d3", NULL),
+        _OMAP3_BALLENTRY(SYS_BOOT2, "c3", NULL),
+        _OMAP3_BALLENTRY(SYS_BOOT3, "e3", NULL),
+        _OMAP3_BALLENTRY(SYS_BOOT4, "e4", NULL),
+        _OMAP3_BALLENTRY(SYS_BOOT5, "g3", NULL),
+        _OMAP3_BALLENTRY(SYS_BOOT6, "d4", NULL),
+        _OMAP3_BALLENTRY(SYS_CLKOUT1, "ae14", NULL),
+        _OMAP3_BALLENTRY(SYS_CLKOUT2, "w11", NULL),
+        _OMAP3_BALLENTRY(SYS_CLKREQ, "w15", NULL),
+        _OMAP3_BALLENTRY(SYS_NIRQ, "v16", NULL),
+        _OMAP3_BALLENTRY(SYS_NRESWARM, "ad7", "aa5"),
+        _OMAP3_BALLENTRY(SYS_OFF_MODE, "v12", NULL),
+        _OMAP3_BALLENTRY(UART1_CTS, "w2", NULL),
+        _OMAP3_BALLENTRY(UART1_RTS, "r2", NULL),
+        _OMAP3_BALLENTRY(UART1_RX, "h3", NULL),
+        _OMAP3_BALLENTRY(UART1_TX, "l4", NULL),
+        _OMAP3_BALLENTRY(UART2_CTS, "y24", NULL),
+        _OMAP3_BALLENTRY(UART2_RTS, "aa24", NULL),
+        _OMAP3_BALLENTRY(UART2_RX, "ad21", NULL),
+        _OMAP3_BALLENTRY(UART2_TX, "ad22", NULL),
+        _OMAP3_BALLENTRY(UART3_CTS_RCTX, "f23", NULL),
+        _OMAP3_BALLENTRY(UART3_RTS_SD, "f24", NULL),
+        _OMAP3_BALLENTRY(UART3_RX_IRRX, "h24", NULL),
+        _OMAP3_BALLENTRY(UART3_TX_IRTX, "g24", NULL),
+        { .reg_offset = OMAP_MUX_TERMINATOR },
+};
+#else
+#define omap3_cbc_ball   NULL
+#endif
+
+/*
+ * Signals different on CUS package compared to superset
+ */
+#if defined(CONFIG_OMAP_MUX) && defined(CONFIG_OMAP_PACKAGE_CUS)
+struct omap_mux __initdata omap3_cus_subset[] = {
+        _OMAP3_MUXENTRY(CAM_D10, 109,
+                "cam_d10", NULL, NULL, NULL,
+                "gpio_109", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(CAM_D11, 110,
+                "cam_d11", NULL, NULL, NULL,
+                "gpio_110", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(CAM_D2, 101,
+                "cam_d2", NULL, NULL, NULL,
+                "gpio_101", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(CAM_D3, 102,
+                "cam_d3", NULL, NULL, NULL,
+                "gpio_102", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(CAM_D4, 103,
+                "cam_d4", NULL, NULL, NULL,
+                "gpio_103", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(CAM_D5, 104,
+                "cam_d5", NULL, NULL, NULL,
+                "gpio_104", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(CAM_FLD, 98,
+                "cam_fld", NULL, "cam_global_reset", NULL,
+                "gpio_98", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(CAM_HS, 94,
+                "cam_hs", NULL, NULL, NULL,
+                "gpio_94", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(CAM_PCLK, 97,
+                "cam_pclk", NULL, NULL, NULL,
+                "gpio_97", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(CAM_STROBE, 126,
+                "cam_strobe", NULL, NULL, NULL,
+                "gpio_126", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(CAM_VS, 95,
+                "cam_vs", NULL, NULL, NULL,
+                "gpio_95", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(CAM_WEN, 167,
+                "cam_wen", NULL, "cam_shutter", NULL,
+                "gpio_167", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(DSS_DATA6, 76,
+                "dss_data6", NULL, "uart1_tx", NULL,
+                "gpio_76", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(DSS_DATA7, 77,
+                "dss_data7", NULL, "uart1_rx", NULL,
+                "gpio_77", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(DSS_DATA8, 78,
+                "dss_data8", NULL, NULL, NULL,
+                "gpio_78", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(DSS_DATA9, 79,
+                "dss_data9", NULL, NULL, NULL,
+                "gpio_79", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(DSS_HSYNC, 67,
+                "dss_hsync", NULL, NULL, NULL,
+                "gpio_67", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(DSS_PCLK, 66,
+                "dss_pclk", NULL, NULL, NULL,
+                "gpio_66", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(ETK_CLK, 12,
+                "etk_clk", "mcbsp5_clkx", "sdmmc3_clk", "hsusb1_stp",
+                "gpio_12", "mm1_rxdp", "hsusb1_tll_stp", NULL),
+        _OMAP3_MUXENTRY(ETK_CTL, 13,
+                "etk_ctl", NULL, "sdmmc3_cmd", "hsusb1_clk",
+                "gpio_13", NULL, "hsusb1_tll_clk", NULL),
+        _OMAP3_MUXENTRY(ETK_D0, 14,
+                "etk_d0", "mcspi3_simo", "sdmmc3_dat4", "hsusb1_data0",
+                "gpio_14", "mm1_rxrcv", "hsusb1_tll_data0", NULL),
+        _OMAP3_MUXENTRY(ETK_D1, 15,
+                "etk_d1", "mcspi3_somi", NULL, "hsusb1_data1",
+                "gpio_15", "mm1_txse0", "hsusb1_tll_data1", NULL),
+        _OMAP3_MUXENTRY(ETK_D10, 24,
+                "etk_d10", NULL, "uart1_rx", "hsusb2_clk",
+                "gpio_24", NULL, "hsusb2_tll_clk", NULL),
+        _OMAP3_MUXENTRY(ETK_D11, 25,
+                "etk_d11", NULL, NULL, "hsusb2_stp",
+                "gpio_25", "mm2_rxdp", "hsusb2_tll_stp", NULL),
+        _OMAP3_MUXENTRY(ETK_D12, 26,
+                "etk_d12", NULL, NULL, "hsusb2_dir",
+                "gpio_26", NULL, "hsusb2_tll_dir", NULL),
+        _OMAP3_MUXENTRY(ETK_D13, 27,
+                "etk_d13", NULL, NULL, "hsusb2_nxt",
+                "gpio_27", "mm2_rxdm", "hsusb2_tll_nxt", NULL),
+        _OMAP3_MUXENTRY(ETK_D14, 28,
+                "etk_d14", NULL, NULL, "hsusb2_data0",
+                "gpio_28", "mm2_rxrcv", "hsusb2_tll_data0", NULL),
+        _OMAP3_MUXENTRY(ETK_D15, 29,
+                "etk_d15", NULL, NULL, "hsusb2_data1",
+                "gpio_29", "mm2_txse0", "hsusb2_tll_data1", NULL),
+        _OMAP3_MUXENTRY(ETK_D2, 16,
+                "etk_d2", "mcspi3_cs0", NULL, "hsusb1_data2",
+                "gpio_16", "mm1_txdat", "hsusb1_tll_data2", NULL),
+        _OMAP3_MUXENTRY(ETK_D3, 17,
+                "etk_d3", "mcspi3_clk", "sdmmc3_dat3", "hsusb1_data7",
+                "gpio_17", NULL, "hsusb1_tll_data7", NULL),
+        _OMAP3_MUXENTRY(ETK_D4, 18,
+                "etk_d4", "mcbsp5_dr", "sdmmc3_dat0", "hsusb1_data4",
+                "gpio_18", NULL, "hsusb1_tll_data4", NULL),
+        _OMAP3_MUXENTRY(ETK_D5, 19,
+                "etk_d5", "mcbsp5_fsx", "sdmmc3_dat1", "hsusb1_data5",
+                "gpio_19", NULL, "hsusb1_tll_data5", NULL),
+        _OMAP3_MUXENTRY(ETK_D6, 20,
+                "etk_d6", "mcbsp5_dx", "sdmmc3_dat2", "hsusb1_data6",
+                "gpio_20", NULL, "hsusb1_tll_data6", NULL),
+        _OMAP3_MUXENTRY(ETK_D7, 21,
+                "etk_d7", "mcspi3_cs1", "sdmmc3_dat7", "hsusb1_data3",
+                "gpio_21", "mm1_txen_n", "hsusb1_tll_data3", NULL),
+        _OMAP3_MUXENTRY(ETK_D8, 22,
+                "etk_d8", "sys_drm_msecure", "sdmmc3_dat6", "hsusb1_dir",
+                "gpio_22", NULL, "hsusb1_tll_dir", NULL),
+        _OMAP3_MUXENTRY(ETK_D9, 23,
+                "etk_d9", "sys_secure_indicator", "sdmmc3_dat5", "hsusb1_nxt",
+                "gpio_23", "mm1_rxdm", "hsusb1_tll_nxt", NULL),
+        _OMAP3_MUXENTRY(MCBSP3_CLKX, 142,
+                "mcbsp3_clkx", "uart2_tx", NULL, NULL,
+                "gpio_142", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(MCBSP3_DR, 141,
+                "mcbsp3_dr", "uart2_rts", NULL, NULL,
+                "gpio_141", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(MCBSP3_DX, 140,
+                "mcbsp3_dx", "uart2_cts", NULL, NULL,
+                "gpio_140", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(MCBSP3_FSX, 143,
+                "mcbsp3_fsx", "uart2_rx", NULL, NULL,
+                "gpio_143", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(SDMMC2_DAT5, 137,
+                "sdmmc2_dat5", "sdmmc2_dir_dat1",
+                "cam_global_reset", "sdmmc3_dat1",
+                "gpio_137", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(SDMMC2_DAT6, 138,
+                "sdmmc2_dat6", "sdmmc2_dir_cmd", "cam_shutter", "sdmmc3_dat2",
+                "gpio_138", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(SDMMC2_DAT7, 139,
+                "sdmmc2_dat7", "sdmmc2_clkin", NULL, "sdmmc3_dat3",
+                "gpio_139", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(UART1_CTS, 150,
+                "uart1_cts", NULL, NULL, NULL,
+                "gpio_150", NULL, NULL, "safe_mode"),
+        { .reg_offset = OMAP_MUX_TERMINATOR },
+};
+#else
+#define omap3_cus_subset        NULL
+#endif
+
+/*
+ * Balls for CUS package
+ * 423-pin s-PBGA Package, 0.65mm Ball Pitch (Bottom)
+ */
+#if defined(CONFIG_OMAP_MUX) && defined(CONFIG_DEBUG_FS)                \
+                && defined(CONFIG_OMAP_PACKAGE_CUS)
+struct omap_ball __initdata omap3_cus_ball[] = {
+        _OMAP3_BALLENTRY(CAM_D0, "ab18", NULL),
+        _OMAP3_BALLENTRY(CAM_D1, "ac18", NULL),
+        _OMAP3_BALLENTRY(CAM_D10, "f21", NULL),
+        _OMAP3_BALLENTRY(CAM_D11, "g21", NULL),
+        _OMAP3_BALLENTRY(CAM_D2, "g19", NULL),
+        _OMAP3_BALLENTRY(CAM_D3, "f19", NULL),
+        _OMAP3_BALLENTRY(CAM_D4, "g20", NULL),
+        _OMAP3_BALLENTRY(CAM_D5, "b21", NULL),
+        _OMAP3_BALLENTRY(CAM_D6, "l24", NULL),
+        _OMAP3_BALLENTRY(CAM_D7, "k24", NULL),
+        _OMAP3_BALLENTRY(CAM_D8, "j23", NULL),
+        _OMAP3_BALLENTRY(CAM_D9, "k23", NULL),
+        _OMAP3_BALLENTRY(CAM_FLD, "h24", NULL),
+        _OMAP3_BALLENTRY(CAM_HS, "a22", NULL),
+        _OMAP3_BALLENTRY(CAM_PCLK, "j19", NULL),
+        _OMAP3_BALLENTRY(CAM_STROBE, "j20", NULL),
+        _OMAP3_BALLENTRY(CAM_VS, "e18", NULL),
+        _OMAP3_BALLENTRY(CAM_WEN, "f18", NULL),
+        _OMAP3_BALLENTRY(CAM_XCLKA, "b22", NULL),
+        _OMAP3_BALLENTRY(CAM_XCLKB, "c22", NULL),
+        _OMAP3_BALLENTRY(DSS_ACBIAS, "j21", NULL),
+        _OMAP3_BALLENTRY(DSS_DATA0, "ac19", NULL),
+        _OMAP3_BALLENTRY(DSS_DATA1, "ab19", NULL),
+        _OMAP3_BALLENTRY(DSS_DATA10, "ac22", NULL),
+        _OMAP3_BALLENTRY(DSS_DATA11, "ac23", NULL),
+        _OMAP3_BALLENTRY(DSS_DATA12, "ab22", NULL),
+        _OMAP3_BALLENTRY(DSS_DATA13, "y22", NULL),
+        _OMAP3_BALLENTRY(DSS_DATA14, "w22", NULL),
+        _OMAP3_BALLENTRY(DSS_DATA15, "v22", NULL),
+        _OMAP3_BALLENTRY(DSS_DATA16, "j22", NULL),
+        _OMAP3_BALLENTRY(DSS_DATA17, "g23", NULL),
+        _OMAP3_BALLENTRY(DSS_DATA18, "g24", NULL),
+        _OMAP3_BALLENTRY(DSS_DATA19, "h23", NULL),
+        _OMAP3_BALLENTRY(DSS_DATA2, "ad20", NULL),
+        _OMAP3_BALLENTRY(DSS_DATA20, "d23", NULL),
+        _OMAP3_BALLENTRY(DSS_DATA21, "k22", NULL),
+        _OMAP3_BALLENTRY(DSS_DATA22, "v21", NULL),
+        _OMAP3_BALLENTRY(DSS_DATA23, "w21", NULL),
+        _OMAP3_BALLENTRY(DSS_DATA3, "ac20", NULL),
+        _OMAP3_BALLENTRY(DSS_DATA4, "ad21", NULL),
+        _OMAP3_BALLENTRY(DSS_DATA5, "ac21", NULL),
+        _OMAP3_BALLENTRY(DSS_DATA6, "d24", NULL),
+        _OMAP3_BALLENTRY(DSS_DATA7, "e23", NULL),
+        _OMAP3_BALLENTRY(DSS_DATA8, "e24", NULL),
+        _OMAP3_BALLENTRY(DSS_DATA9, "f23", NULL),
+        _OMAP3_BALLENTRY(DSS_HSYNC, "e22", NULL),
+        _OMAP3_BALLENTRY(DSS_PCLK, "g22", NULL),
+        _OMAP3_BALLENTRY(DSS_VSYNC, "f22", NULL),
+        _OMAP3_BALLENTRY(ETK_CLK, "ac1", NULL),
+        _OMAP3_BALLENTRY(ETK_CTL, "ad3", NULL),
+        _OMAP3_BALLENTRY(ETK_D0, "ad6", NULL),
+        _OMAP3_BALLENTRY(ETK_D1, "ac6", NULL),
+        _OMAP3_BALLENTRY(ETK_D10, "ac3", NULL),
+        _OMAP3_BALLENTRY(ETK_D11, "ac9", NULL),
+        _OMAP3_BALLENTRY(ETK_D12, "ac10", NULL),
+        _OMAP3_BALLENTRY(ETK_D13, "ad11", NULL),
+        _OMAP3_BALLENTRY(ETK_D14, "ac11", NULL),
+        _OMAP3_BALLENTRY(ETK_D15, "ad12", NULL),
+        _OMAP3_BALLENTRY(ETK_D2, "ac7", NULL),
+        _OMAP3_BALLENTRY(ETK_D3, "ad8", NULL),
+        _OMAP3_BALLENTRY(ETK_D4, "ac5", NULL),
+        _OMAP3_BALLENTRY(ETK_D5, "ad2", NULL),
+        _OMAP3_BALLENTRY(ETK_D6, "ac8", NULL),
+        _OMAP3_BALLENTRY(ETK_D7, "ad9", NULL),
+        _OMAP3_BALLENTRY(ETK_D8, "ac4", NULL),
+        _OMAP3_BALLENTRY(ETK_D9, "ad5", NULL),
+        _OMAP3_BALLENTRY(GPMC_A1, "k4", NULL),
+        _OMAP3_BALLENTRY(GPMC_A10, "g2", NULL),
+        _OMAP3_BALLENTRY(GPMC_A2, "k3", NULL),
+        _OMAP3_BALLENTRY(GPMC_A3, "k2", NULL),
+        _OMAP3_BALLENTRY(GPMC_A4, "j4", NULL),
+        _OMAP3_BALLENTRY(GPMC_A5, "j3", NULL),
+        _OMAP3_BALLENTRY(GPMC_A6, "j2", NULL),
+        _OMAP3_BALLENTRY(GPMC_A7, "j1", NULL),
+        _OMAP3_BALLENTRY(GPMC_A8, "h1", NULL),
+        _OMAP3_BALLENTRY(GPMC_A9, "h2", NULL),
+        _OMAP3_BALLENTRY(GPMC_CLK, "w2", NULL),
+        _OMAP3_BALLENTRY(GPMC_D10, "u1", NULL),
+        _OMAP3_BALLENTRY(GPMC_D11, "r3", NULL),
+        _OMAP3_BALLENTRY(GPMC_D12, "t3", NULL),
+        _OMAP3_BALLENTRY(GPMC_D13, "u2", NULL),
+        _OMAP3_BALLENTRY(GPMC_D14, "v1", NULL),
+        _OMAP3_BALLENTRY(GPMC_D15, "v2", NULL),
+        _OMAP3_BALLENTRY(GPMC_D8, "r2", NULL),
+        _OMAP3_BALLENTRY(GPMC_D9, "t2", NULL),
+        _OMAP3_BALLENTRY(GPMC_NBE0_CLE, "k5", NULL),
+        _OMAP3_BALLENTRY(GPMC_NBE1, "l1", NULL),
+        _OMAP3_BALLENTRY(GPMC_NCS3, "d2", NULL),
+        _OMAP3_BALLENTRY(GPMC_NCS4, "f4", NULL),
+        _OMAP3_BALLENTRY(GPMC_NCS5, "g5", NULL),
+        _OMAP3_BALLENTRY(GPMC_NCS6, "f3", NULL),
+        _OMAP3_BALLENTRY(GPMC_NCS7, "g4", NULL),
+        _OMAP3_BALLENTRY(GPMC_NWP, "e1", NULL),
+        _OMAP3_BALLENTRY(GPMC_WAIT3, "c2", NULL),
+        _OMAP3_BALLENTRY(HDQ_SIO, "a24", NULL),
+        _OMAP3_BALLENTRY(HSUSB0_CLK, "r21", NULL),
+        _OMAP3_BALLENTRY(HSUSB0_DATA0, "t24", NULL),
+        _OMAP3_BALLENTRY(HSUSB0_DATA1, "t23", NULL),
+        _OMAP3_BALLENTRY(HSUSB0_DATA2, "u24", NULL),
+        _OMAP3_BALLENTRY(HSUSB0_DATA3, "u23", NULL),
+        _OMAP3_BALLENTRY(HSUSB0_DATA4, "w24", NULL),
+        _OMAP3_BALLENTRY(HSUSB0_DATA5, "v23", NULL),
+        _OMAP3_BALLENTRY(HSUSB0_DATA6, "w23", NULL),
+        _OMAP3_BALLENTRY(HSUSB0_DATA7, "t22", NULL),
+        _OMAP3_BALLENTRY(HSUSB0_DIR, "p23", NULL),
+        _OMAP3_BALLENTRY(HSUSB0_NXT, "r22", NULL),
+        _OMAP3_BALLENTRY(HSUSB0_STP, "r23", NULL),
+        _OMAP3_BALLENTRY(I2C2_SCL, "ac15", NULL),
+        _OMAP3_BALLENTRY(I2C2_SDA, "ac14", NULL),
+        _OMAP3_BALLENTRY(I2C3_SCL, "ac13", NULL),
+        _OMAP3_BALLENTRY(I2C3_SDA, "ac12", NULL),
+        _OMAP3_BALLENTRY(I2C4_SCL, "y16", NULL),
+        _OMAP3_BALLENTRY(I2C4_SDA, "y15", NULL),
+        _OMAP3_BALLENTRY(JTAG_EMU0, "ac24", NULL),
+        _OMAP3_BALLENTRY(JTAG_EMU1, "ad24", NULL),
+        _OMAP3_BALLENTRY(MCBSP1_CLKR, "w19", NULL),
+        _OMAP3_BALLENTRY(MCBSP1_CLKX, "v18", NULL),
+        _OMAP3_BALLENTRY(MCBSP1_DR, "y18", NULL),
+        _OMAP3_BALLENTRY(MCBSP1_DX, "w18", NULL),
+        _OMAP3_BALLENTRY(MCBSP1_FSR, "ab20", NULL),
+        _OMAP3_BALLENTRY(MCBSP1_FSX, "aa19", NULL),
+        _OMAP3_BALLENTRY(MCBSP2_CLKX, "t21", NULL),
+        _OMAP3_BALLENTRY(MCBSP2_DR, "v19", NULL),
+        _OMAP3_BALLENTRY(MCBSP2_DX, "r20", NULL),
+        _OMAP3_BALLENTRY(MCBSP2_FSX, "v20", NULL),
+        _OMAP3_BALLENTRY(MCBSP3_CLKX, "w4", NULL),
+        _OMAP3_BALLENTRY(MCBSP3_DR, "v5", NULL),
+        _OMAP3_BALLENTRY(MCBSP3_DX, "v6", NULL),
+        _OMAP3_BALLENTRY(MCBSP3_FSX, "v4", NULL),
+        _OMAP3_BALLENTRY(MCBSP_CLKS, "aa18", NULL),
+        _OMAP3_BALLENTRY(MCSPI1_CLK, "t5", NULL),
+        _OMAP3_BALLENTRY(MCSPI1_CS0, "t6", NULL),
+        _OMAP3_BALLENTRY(MCSPI1_CS3, "r5", NULL),
+        _OMAP3_BALLENTRY(MCSPI1_SIMO, "r4", NULL),
+        _OMAP3_BALLENTRY(MCSPI1_SOMI, "t4", NULL),
+        _OMAP3_BALLENTRY(MCSPI2_CLK, "n5", NULL),
+        _OMAP3_BALLENTRY(MCSPI2_CS0, "m5", NULL),
+        _OMAP3_BALLENTRY(MCSPI2_CS1, "m4", NULL),
+        _OMAP3_BALLENTRY(MCSPI2_SIMO, "n4", NULL),
+        _OMAP3_BALLENTRY(MCSPI2_SOMI, "n3", NULL),
+        _OMAP3_BALLENTRY(SDMMC1_CLK, "m23", NULL),
+        _OMAP3_BALLENTRY(SDMMC1_CMD, "l23", NULL),
+        _OMAP3_BALLENTRY(SDMMC1_DAT0, "m22", NULL),
+        _OMAP3_BALLENTRY(SDMMC1_DAT1, "m21", NULL),
+        _OMAP3_BALLENTRY(SDMMC1_DAT2, "m20", NULL),
+        _OMAP3_BALLENTRY(SDMMC1_DAT3, "n23", NULL),
+        _OMAP3_BALLENTRY(SDMMC1_DAT4, "n22", NULL),
+        _OMAP3_BALLENTRY(SDMMC1_DAT5, "n21", NULL),
+        _OMAP3_BALLENTRY(SDMMC1_DAT6, "n20", NULL),
+        _OMAP3_BALLENTRY(SDMMC1_DAT7, "p24", NULL),
+        _OMAP3_BALLENTRY(SDMMC2_CLK, "y1", NULL),
+        _OMAP3_BALLENTRY(SDMMC2_CMD, "ab5", NULL),
+        _OMAP3_BALLENTRY(SDMMC2_DAT0, "ab3", NULL),
+        _OMAP3_BALLENTRY(SDMMC2_DAT1, "y3", NULL),
+        _OMAP3_BALLENTRY(SDMMC2_DAT2, "w3", NULL),
+        _OMAP3_BALLENTRY(SDMMC2_DAT3, "v3", NULL),
+        _OMAP3_BALLENTRY(SDMMC2_DAT4, "ab2", NULL),
+        _OMAP3_BALLENTRY(SDMMC2_DAT5, "aa2", NULL),
+        _OMAP3_BALLENTRY(SDMMC2_DAT6, "y2", NULL),
+        _OMAP3_BALLENTRY(SDMMC2_DAT7, "aa1", NULL),
+        _OMAP3_BALLENTRY(SYS_BOOT0, "ab12", NULL),
+        _OMAP3_BALLENTRY(SYS_BOOT1, "ac16", NULL),
+        _OMAP3_BALLENTRY(SYS_BOOT2, "ad17", NULL),
+        _OMAP3_BALLENTRY(SYS_BOOT3, "ad18", NULL),
+        _OMAP3_BALLENTRY(SYS_BOOT4, "ac17", NULL),
+        _OMAP3_BALLENTRY(SYS_BOOT5, "ab16", NULL),
+        _OMAP3_BALLENTRY(SYS_BOOT6, "aa15", NULL),
+        _OMAP3_BALLENTRY(SYS_CLKOUT1, "y7", NULL),
+        _OMAP3_BALLENTRY(SYS_CLKOUT2, "aa6", NULL),
+        _OMAP3_BALLENTRY(SYS_CLKREQ, "y13", NULL),
+        _OMAP3_BALLENTRY(SYS_NIRQ, "w16", NULL),
+        _OMAP3_BALLENTRY(SYS_NRESWARM, "y10", NULL),
+        _OMAP3_BALLENTRY(SYS_OFF_MODE, "ad23", NULL),
+        _OMAP3_BALLENTRY(UART1_CTS, "ac2", NULL),
+        _OMAP3_BALLENTRY(UART1_RTS, "w6", NULL),
+        _OMAP3_BALLENTRY(UART1_RX, "v7", NULL),
+        _OMAP3_BALLENTRY(UART1_TX, "w7", NULL),
+        _OMAP3_BALLENTRY(UART3_CTS_RCTX, "a23", NULL),
+        _OMAP3_BALLENTRY(UART3_RTS_SD, "b23", NULL),
+        _OMAP3_BALLENTRY(UART3_RX_IRRX, "b24", NULL),
+        _OMAP3_BALLENTRY(UART3_TX_IRTX, "c23", NULL),
+        { .reg_offset = OMAP_MUX_TERMINATOR },
+};
+#else
+#define omap3_cus_ball   NULL
+#endif
+
+/*
+ * Signals different on CBB package comapared to superset
+ */
+#if defined(CONFIG_OMAP_MUX) && defined(CONFIG_OMAP_PACKAGE_CBB)
+struct omap_mux __initdata omap3_cbb_subset[] = {
+        _OMAP3_MUXENTRY(CAM_D10, 109,
+                "cam_d10", NULL, NULL, NULL,
+                "gpio_109", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(CAM_D11, 110,
+                "cam_d11", NULL, NULL, NULL,
+                "gpio_110", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(CAM_D2, 101,
+                "cam_d2", NULL, NULL, NULL,
+                "gpio_101", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(CAM_D3, 102,
+                "cam_d3", NULL, NULL, NULL,
+                "gpio_102", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(CAM_D4, 103,
+                "cam_d4", NULL, NULL, NULL,
+                "gpio_103", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(CAM_D5, 104,
+                "cam_d5", NULL, NULL, NULL,
+                "gpio_104", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(CAM_FLD, 98,
+                "cam_fld", NULL, "cam_global_reset", NULL,
+                "gpio_98", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(CAM_HS, 94,
+                "cam_hs", NULL, NULL, NULL,
+                "gpio_94", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(CAM_PCLK, 97,
+                "cam_pclk", NULL, NULL, NULL,
+                "gpio_97", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(CAM_STROBE, 126,
+                "cam_strobe", NULL, NULL, NULL,
+                "gpio_126", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(CAM_VS, 95,
+                "cam_vs", NULL, NULL, NULL,
+                "gpio_95", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(CAM_WEN, 167,
+                "cam_wen", NULL, "cam_shutter", NULL,
+                "gpio_167", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(DSS_DATA6, 76,
+                "dss_data6", NULL, "uart1_tx", NULL,
+                "gpio_76", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(DSS_DATA7, 77,
+                "dss_data7", NULL, "uart1_rx", NULL,
+                "gpio_77", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(DSS_DATA8, 78,
+                "dss_data8", NULL, NULL, NULL,
+                "gpio_78", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(DSS_DATA9, 79,
+                "dss_data9", NULL, NULL, NULL,
+                "gpio_79", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(DSS_HSYNC, 67,
+                "dss_hsync", NULL, NULL, NULL,
+                "gpio_67", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(DSS_PCLK, 66,
+                "dss_pclk", NULL, NULL, NULL,
+                "gpio_66", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(ETK_CLK, 12,
+                "etk_clk", "mcbsp5_clkx", "sdmmc3_clk", "hsusb1_stp",
+                "gpio_12", "mm1_rxdp", "hsusb1_tll_stp", NULL),
+        _OMAP3_MUXENTRY(ETK_CTL, 13,
+                "etk_ctl", NULL, "sdmmc3_cmd", "hsusb1_clk",
+                "gpio_13", NULL, "hsusb1_tll_clk", NULL),
+        _OMAP3_MUXENTRY(ETK_D0, 14,
+                "etk_d0", "mcspi3_simo", "sdmmc3_dat4", "hsusb1_data0",
+                "gpio_14", "mm1_rxrcv", "hsusb1_tll_data0", NULL),
+        _OMAP3_MUXENTRY(ETK_D1, 15,
+                "etk_d1", "mcspi3_somi", NULL, "hsusb1_data1",
+                "gpio_15", "mm1_txse0", "hsusb1_tll_data1", NULL),
+        _OMAP3_MUXENTRY(ETK_D10, 24,
+                "etk_d10", NULL, "uart1_rx", "hsusb2_clk",
+                "gpio_24", NULL, "hsusb2_tll_clk", NULL),
+        _OMAP3_MUXENTRY(ETK_D11, 25,
+                "etk_d11", NULL, NULL, "hsusb2_stp",
+                "gpio_25", "mm2_rxdp", "hsusb2_tll_stp", NULL),
+        _OMAP3_MUXENTRY(ETK_D12, 26,
+                "etk_d12", NULL, NULL, "hsusb2_dir",
+                "gpio_26", NULL, "hsusb2_tll_dir", NULL),
+        _OMAP3_MUXENTRY(ETK_D13, 27,
+                "etk_d13", NULL, NULL, "hsusb2_nxt",
+                "gpio_27", "mm2_rxdm", "hsusb2_tll_nxt", NULL),
+        _OMAP3_MUXENTRY(ETK_D14, 28,
+                "etk_d14", NULL, NULL, "hsusb2_data0",
+                "gpio_28", "mm2_rxrcv", "hsusb2_tll_data0", NULL),
+        _OMAP3_MUXENTRY(ETK_D15, 29,
+                "etk_d15", NULL, NULL, "hsusb2_data1",
+                "gpio_29", "mm2_txse0", "hsusb2_tll_data1", NULL),
+        _OMAP3_MUXENTRY(ETK_D2, 16,
+                "etk_d2", "mcspi3_cs0", NULL, "hsusb1_data2",
+                "gpio_16", "mm1_txdat", "hsusb1_tll_data2", NULL),
+        _OMAP3_MUXENTRY(ETK_D3, 17,
+                "etk_d3", "mcspi3_clk", "sdmmc3_dat3", "hsusb1_data7",
+                "gpio_17", NULL, "hsusb1_tll_data7", NULL),
+        _OMAP3_MUXENTRY(ETK_D4, 18,
+                "etk_d4", "mcbsp5_dr", "sdmmc3_dat0", "hsusb1_data4",
+                "gpio_18", NULL, "hsusb1_tll_data4", NULL),
+        _OMAP3_MUXENTRY(ETK_D5, 19,
+                "etk_d5", "mcbsp5_fsx", "sdmmc3_dat1", "hsusb1_data5",
+                "gpio_19", NULL, "hsusb1_tll_data5", NULL),
+        _OMAP3_MUXENTRY(ETK_D6, 20,
+                "etk_d6", "mcbsp5_dx", "sdmmc3_dat2", "hsusb1_data6",
+                "gpio_20", NULL, "hsusb1_tll_data6", NULL),
+        _OMAP3_MUXENTRY(ETK_D7, 21,
+                "etk_d7", "mcspi3_cs1", "sdmmc3_dat7", "hsusb1_data3",
+                "gpio_21", "mm1_txen_n", "hsusb1_tll_data3", NULL),
+        _OMAP3_MUXENTRY(ETK_D8, 22,
+                "etk_d8", "sys_drm_msecure", "sdmmc3_dat6", "hsusb1_dir",
+                "gpio_22", NULL, "hsusb1_tll_dir", NULL),
+        _OMAP3_MUXENTRY(ETK_D9, 23,
+                "etk_d9", "sys_secure_indicator", "sdmmc3_dat5", "hsusb1_nxt",
+                "gpio_23", "mm1_rxdm", "hsusb1_tll_nxt", NULL),
+        { .reg_offset = OMAP_MUX_TERMINATOR },
+};
+#else
+#define omap3_cbb_subset        NULL
+#endif
+
+/*
+ * Balls for CBB package
+ * 515-pin s-PBGA Package, 0.50mm Ball Pitch (Top), 0.40mm Ball Pitch (Bottom)
+ */
+#if defined(CONFIG_OMAP_MUX) && defined(CONFIG_DEBUG_FS)                \
+                && defined(CONFIG_OMAP_PACKAGE_CBB)
+struct omap_ball __initdata omap3_cbb_ball[] = {
+        _OMAP3_BALLENTRY(CAM_D0, "ag17", NULL),
+        _OMAP3_BALLENTRY(CAM_D1, "ah17", NULL),
+        _OMAP3_BALLENTRY(CAM_D10, "b25", NULL),
+        _OMAP3_BALLENTRY(CAM_D11, "c26", NULL),
+        _OMAP3_BALLENTRY(CAM_D2, "b24", NULL),
+        _OMAP3_BALLENTRY(CAM_D3, "c24", NULL),
+        _OMAP3_BALLENTRY(CAM_D4, "d24", NULL),
+        _OMAP3_BALLENTRY(CAM_D5, "a25", NULL),
+        _OMAP3_BALLENTRY(CAM_D6, "k28", NULL),
+        _OMAP3_BALLENTRY(CAM_D7, "l28", NULL),
+        _OMAP3_BALLENTRY(CAM_D8, "k27", NULL),
+        _OMAP3_BALLENTRY(CAM_D9, "l27", NULL),
+        _OMAP3_BALLENTRY(CAM_FLD, "c23", NULL),
+        _OMAP3_BALLENTRY(CAM_HS, "a24", NULL),
+        _OMAP3_BALLENTRY(CAM_PCLK, "c27", NULL),
+        _OMAP3_BALLENTRY(CAM_STROBE, "d25", NULL),
+        _OMAP3_BALLENTRY(CAM_VS, "a23", NULL),
+        _OMAP3_BALLENTRY(CAM_WEN, "b23", NULL),
+        _OMAP3_BALLENTRY(CAM_XCLKA, "c25", NULL),
+        _OMAP3_BALLENTRY(CAM_XCLKB, "b26", NULL),
+        _OMAP3_BALLENTRY(CSI2_DX0, "ag19", NULL),
+        _OMAP3_BALLENTRY(CSI2_DX1, "ag18", NULL),
+        _OMAP3_BALLENTRY(CSI2_DY0, "ah19", NULL),
+        _OMAP3_BALLENTRY(CSI2_DY1, "ah18", NULL),
+        _OMAP3_BALLENTRY(DSS_ACBIAS, "e27", NULL),
+        _OMAP3_BALLENTRY(DSS_DATA0, "ag22", NULL),
+        _OMAP3_BALLENTRY(DSS_DATA1, "ah22", NULL),
+        _OMAP3_BALLENTRY(DSS_DATA10, "ad28", NULL),
+        _OMAP3_BALLENTRY(DSS_DATA11, "ad27", NULL),
+        _OMAP3_BALLENTRY(DSS_DATA12, "ab28", NULL),
+        _OMAP3_BALLENTRY(DSS_DATA13, "ab27", NULL),
+        _OMAP3_BALLENTRY(DSS_DATA14, "aa28", NULL),
+        _OMAP3_BALLENTRY(DSS_DATA15, "aa27", NULL),
+        _OMAP3_BALLENTRY(DSS_DATA16, "g25", NULL),
+        _OMAP3_BALLENTRY(DSS_DATA17, "h27", NULL),
+        _OMAP3_BALLENTRY(DSS_DATA18, "h26", NULL),
+        _OMAP3_BALLENTRY(DSS_DATA19, "h25", NULL),
+        _OMAP3_BALLENTRY(DSS_DATA2, "ag23", NULL),
+        _OMAP3_BALLENTRY(DSS_DATA20, "e28", NULL),
+        _OMAP3_BALLENTRY(DSS_DATA21, "j26", NULL),
+        _OMAP3_BALLENTRY(DSS_DATA22, "ac27", NULL),
+        _OMAP3_BALLENTRY(DSS_DATA23, "ac28", NULL),
+        _OMAP3_BALLENTRY(DSS_DATA3, "ah23", NULL),
+        _OMAP3_BALLENTRY(DSS_DATA4, "ag24", NULL),
+        _OMAP3_BALLENTRY(DSS_DATA5, "ah24", NULL),
+        _OMAP3_BALLENTRY(DSS_DATA6, "e26", NULL),
+        _OMAP3_BALLENTRY(DSS_DATA7, "f28", NULL),
+        _OMAP3_BALLENTRY(DSS_DATA8, "f27", NULL),
+        _OMAP3_BALLENTRY(DSS_DATA9, "g26", NULL),
+        _OMAP3_BALLENTRY(DSS_HSYNC, "d26", NULL),
+        _OMAP3_BALLENTRY(DSS_PCLK, "d28", NULL),
+        _OMAP3_BALLENTRY(DSS_VSYNC, "d27", NULL),
+        _OMAP3_BALLENTRY(ETK_CLK, "af10", NULL),
+        _OMAP3_BALLENTRY(ETK_CTL, "ae10", NULL),
+        _OMAP3_BALLENTRY(ETK_D0, "af11", NULL),
+        _OMAP3_BALLENTRY(ETK_D1, "ag12", NULL),
+        _OMAP3_BALLENTRY(ETK_D10, "ae7", NULL),
+        _OMAP3_BALLENTRY(ETK_D11, "af7", NULL),
+        _OMAP3_BALLENTRY(ETK_D12, "ag7", NULL),
+        _OMAP3_BALLENTRY(ETK_D13, "ah7", NULL),
+        _OMAP3_BALLENTRY(ETK_D14, "ag8", NULL),
+        _OMAP3_BALLENTRY(ETK_D15, "ah8", NULL),
+        _OMAP3_BALLENTRY(ETK_D2, "ah12", NULL),
+        _OMAP3_BALLENTRY(ETK_D3, "ae13", NULL),
+        _OMAP3_BALLENTRY(ETK_D4, "ae11", NULL),
+        _OMAP3_BALLENTRY(ETK_D5, "ah9", NULL),
+        _OMAP3_BALLENTRY(ETK_D6, "af13", NULL),
+        _OMAP3_BALLENTRY(ETK_D7, "ah14", NULL),
+        _OMAP3_BALLENTRY(ETK_D8, "af9", NULL),
+        _OMAP3_BALLENTRY(ETK_D9, "ag9", NULL),
+        _OMAP3_BALLENTRY(GPMC_A1, "n4", "ac15"),
+        _OMAP3_BALLENTRY(GPMC_A10, "k3", "ab19"),
+        _OMAP3_BALLENTRY(GPMC_A2, "m4", "ab15"),
+        _OMAP3_BALLENTRY(GPMC_A3, "l4", "ac16"),
+        _OMAP3_BALLENTRY(GPMC_A4, "k4", "ab16"),
+        _OMAP3_BALLENTRY(GPMC_A5, "t3", "ac17"),
+        _OMAP3_BALLENTRY(GPMC_A6, "r3", "ab17"),
+        _OMAP3_BALLENTRY(GPMC_A7, "n3", "ac18"),
+        _OMAP3_BALLENTRY(GPMC_A8, "m3", "ab18"),
+        _OMAP3_BALLENTRY(GPMC_A9, "l3", "ac19"),
+        _OMAP3_BALLENTRY(GPMC_CLK, "t4", "w2"),
+        _OMAP3_BALLENTRY(GPMC_D10, "p1", "ab4"),
+        _OMAP3_BALLENTRY(GPMC_D11, "r1", "ac4"),
+        _OMAP3_BALLENTRY(GPMC_D12, "r2", "ab6"),
+        _OMAP3_BALLENTRY(GPMC_D13, "t2", "ac6"),
+        _OMAP3_BALLENTRY(GPMC_D14, "w1", "ab7"),
+        _OMAP3_BALLENTRY(GPMC_D15, "y1", "ac7"),
+        _OMAP3_BALLENTRY(GPMC_D8, "h2", "ab3"),
+        _OMAP3_BALLENTRY(GPMC_D9, "k2", "ac3"),
+        _OMAP3_BALLENTRY(GPMC_NBE0_CLE, "g3", "ac12"),
+        _OMAP3_BALLENTRY(GPMC_NBE1, "u3", NULL),
+        _OMAP3_BALLENTRY(GPMC_NCS1, "h3", "y1"),
+        _OMAP3_BALLENTRY(GPMC_NCS2, "v8", NULL),
+        _OMAP3_BALLENTRY(GPMC_NCS3, "u8", NULL),
+        _OMAP3_BALLENTRY(GPMC_NCS4, "t8", NULL),
+        _OMAP3_BALLENTRY(GPMC_NCS5, "r8", NULL),
+        _OMAP3_BALLENTRY(GPMC_NCS6, "p8", NULL),
+        _OMAP3_BALLENTRY(GPMC_NCS7, "n8", NULL),
+        _OMAP3_BALLENTRY(GPMC_NWP, "h1", "ab10"),
+        _OMAP3_BALLENTRY(GPMC_WAIT1, "l8", "ac10"),
+        _OMAP3_BALLENTRY(GPMC_WAIT2, "k8", NULL),
+        _OMAP3_BALLENTRY(GPMC_WAIT3, "j8", NULL),
+        _OMAP3_BALLENTRY(HDQ_SIO, "j25", NULL),
+        _OMAP3_BALLENTRY(HSUSB0_CLK, "t28", NULL),
+        _OMAP3_BALLENTRY(HSUSB0_DATA0, "t27", NULL),
+        _OMAP3_BALLENTRY(HSUSB0_DATA1, "u28", NULL),
+        _OMAP3_BALLENTRY(HSUSB0_DATA2, "u27", NULL),
+        _OMAP3_BALLENTRY(HSUSB0_DATA3, "u26", NULL),
+        _OMAP3_BALLENTRY(HSUSB0_DATA4, "u25", NULL),
+        _OMAP3_BALLENTRY(HSUSB0_DATA5, "v28", NULL),
+        _OMAP3_BALLENTRY(HSUSB0_DATA6, "v27", NULL),
+        _OMAP3_BALLENTRY(HSUSB0_DATA7, "v26", NULL),
+        _OMAP3_BALLENTRY(HSUSB0_DIR, "r28", NULL),
+        _OMAP3_BALLENTRY(HSUSB0_NXT, "t26", NULL),
+        _OMAP3_BALLENTRY(HSUSB0_STP, "t25", NULL),
+        _OMAP3_BALLENTRY(I2C2_SCL, "af15", NULL),
+        _OMAP3_BALLENTRY(I2C2_SDA, "ae15", NULL),
+        _OMAP3_BALLENTRY(I2C3_SCL, "af14", NULL),
+        _OMAP3_BALLENTRY(I2C3_SDA, "ag14", NULL),
+        _OMAP3_BALLENTRY(I2C4_SCL, "ad26", NULL),
+        _OMAP3_BALLENTRY(I2C4_SDA, "ae26", NULL),
+        _OMAP3_BALLENTRY(JTAG_EMU0, "aa11", NULL),
+        _OMAP3_BALLENTRY(JTAG_EMU1, "aa10", NULL),
+        _OMAP3_BALLENTRY(MCBSP1_CLKR, "y21", NULL),
+        _OMAP3_BALLENTRY(MCBSP1_CLKX, "w21", NULL),
+        _OMAP3_BALLENTRY(MCBSP1_DR, "u21", NULL),
+        _OMAP3_BALLENTRY(MCBSP1_DX, "v21", NULL),
+        _OMAP3_BALLENTRY(MCBSP1_FSR, "aa21", NULL),
+        _OMAP3_BALLENTRY(MCBSP1_FSX, "k26", NULL),
+        _OMAP3_BALLENTRY(MCBSP2_CLKX, "n21", NULL),
+        _OMAP3_BALLENTRY(MCBSP2_DR, "r21", NULL),
+        _OMAP3_BALLENTRY(MCBSP2_DX, "m21", NULL),
+        _OMAP3_BALLENTRY(MCBSP2_FSX, "p21", NULL),
+        _OMAP3_BALLENTRY(MCBSP3_CLKX, "af5", NULL),
+        _OMAP3_BALLENTRY(MCBSP3_DR, "ae6", NULL),
+        _OMAP3_BALLENTRY(MCBSP3_DX, "af6", NULL),
+        _OMAP3_BALLENTRY(MCBSP3_FSX, "ae5", NULL),
+        _OMAP3_BALLENTRY(MCBSP4_CLKX, "ae1", NULL),
+        _OMAP3_BALLENTRY(MCBSP4_DR, "ad1", NULL),
+        _OMAP3_BALLENTRY(MCBSP4_DX, "ad2", NULL),
+        _OMAP3_BALLENTRY(MCBSP4_FSX, "ac1", NULL),
+        _OMAP3_BALLENTRY(MCBSP_CLKS, "t21", NULL),
+        _OMAP3_BALLENTRY(MCSPI1_CLK, "ab3", NULL),
+        _OMAP3_BALLENTRY(MCSPI1_CS0, "ac2", NULL),
+        _OMAP3_BALLENTRY(MCSPI1_CS1, "ac3", NULL),
+        _OMAP3_BALLENTRY(MCSPI1_CS2, "ab1", NULL),
+        _OMAP3_BALLENTRY(MCSPI1_CS3, "ab2", NULL),
+        _OMAP3_BALLENTRY(MCSPI1_SIMO, "ab4", NULL),
+        _OMAP3_BALLENTRY(MCSPI1_SOMI, "aa4", NULL),
+        _OMAP3_BALLENTRY(MCSPI2_CLK, "aa3", NULL),
+        _OMAP3_BALLENTRY(MCSPI2_CS0, "y4", NULL),
+        _OMAP3_BALLENTRY(MCSPI2_CS1, "v3", NULL),
+        _OMAP3_BALLENTRY(MCSPI2_SIMO, "y2", NULL),
+        _OMAP3_BALLENTRY(MCSPI2_SOMI, "y3", NULL),
+        _OMAP3_BALLENTRY(SDMMC1_CLK, "n28", NULL),
+        _OMAP3_BALLENTRY(SDMMC1_CMD, "m27", NULL),
+        _OMAP3_BALLENTRY(SDMMC1_DAT0, "n27", NULL),
+        _OMAP3_BALLENTRY(SDMMC1_DAT1, "n26", NULL),
+        _OMAP3_BALLENTRY(SDMMC1_DAT2, "n25", NULL),
+        _OMAP3_BALLENTRY(SDMMC1_DAT3, "p28", NULL),
+        _OMAP3_BALLENTRY(SDMMC1_DAT4, "p27", NULL),
+        _OMAP3_BALLENTRY(SDMMC1_DAT5, "p26", NULL),
+        _OMAP3_BALLENTRY(SDMMC1_DAT6, "r27", NULL),
+        _OMAP3_BALLENTRY(SDMMC1_DAT7, "r25", NULL),
+        _OMAP3_BALLENTRY(SDMMC2_CLK, "ae2", NULL),
+        _OMAP3_BALLENTRY(SDMMC2_CMD, "ag5", NULL),
+        _OMAP3_BALLENTRY(SDMMC2_DAT0, "ah5", NULL),
+        _OMAP3_BALLENTRY(SDMMC2_DAT1, "ah4", NULL),
+        _OMAP3_BALLENTRY(SDMMC2_DAT2, "ag4", NULL),
+        _OMAP3_BALLENTRY(SDMMC2_DAT3, "af4", NULL),
+        _OMAP3_BALLENTRY(SDMMC2_DAT4, "ae4", NULL),
+        _OMAP3_BALLENTRY(SDMMC2_DAT5, "ah3", NULL),
+        _OMAP3_BALLENTRY(SDMMC2_DAT6, "af3", NULL),
+        _OMAP3_BALLENTRY(SDMMC2_DAT7, "ae3", NULL),
+        _OMAP3_BALLENTRY(SYS_BOOT0, "ah26", NULL),
+        _OMAP3_BALLENTRY(SYS_BOOT1, "ag26", NULL),
+        _OMAP3_BALLENTRY(SYS_BOOT2, "ae14", NULL),
+        _OMAP3_BALLENTRY(SYS_BOOT3, "af18", NULL),
+        _OMAP3_BALLENTRY(SYS_BOOT4, "af19", NULL),
+        _OMAP3_BALLENTRY(SYS_BOOT5, "ae21", NULL),
+        _OMAP3_BALLENTRY(SYS_BOOT6, "af21", NULL),
+        _OMAP3_BALLENTRY(SYS_CLKOUT1, "ag25", NULL),
+        _OMAP3_BALLENTRY(SYS_CLKOUT2, "ae22", NULL),
+        _OMAP3_BALLENTRY(SYS_CLKREQ, "af25", NULL),
+        _OMAP3_BALLENTRY(SYS_NIRQ, "af26", NULL),
+        _OMAP3_BALLENTRY(SYS_NRESWARM, "af24", NULL),
+        _OMAP3_BALLENTRY(SYS_OFF_MODE, "af22", NULL),
+        _OMAP3_BALLENTRY(UART1_CTS, "w8", NULL),
+        _OMAP3_BALLENTRY(UART1_RTS, "aa9", NULL),
+        _OMAP3_BALLENTRY(UART1_RX, "y8", NULL),
+        _OMAP3_BALLENTRY(UART1_TX, "aa8", NULL),
+        _OMAP3_BALLENTRY(UART2_CTS, "ab26", NULL),
+        _OMAP3_BALLENTRY(UART2_RTS, "ab25", NULL),
+        _OMAP3_BALLENTRY(UART2_RX, "ad25", NULL),
+        _OMAP3_BALLENTRY(UART2_TX, "aa25", NULL),
+        _OMAP3_BALLENTRY(UART3_CTS_RCTX, "h18", NULL),
+        _OMAP3_BALLENTRY(UART3_RTS_SD, "h19", NULL),
+        _OMAP3_BALLENTRY(UART3_RX_IRRX, "h20", NULL),
+        _OMAP3_BALLENTRY(UART3_TX_IRTX, "h21", NULL),
+        { .reg_offset = OMAP_MUX_TERMINATOR },
+};
+#else
+#define omap3_cbb_ball   NULL
+#endif
+
+/*
+ * Signals different on 36XX CBP package comapared to 34XX CBC package
+ */
+#if defined(CONFIG_OMAP_MUX) && defined(CONFIG_OMAP_PACKAGE_CBP)
+struct omap_mux __initdata omap36xx_cbp_subset[] = {
+        _OMAP3_MUXENTRY(CAM_D0, 99,
+                "cam_d0", NULL, "csi2_dx2", NULL,
+                "gpio_99", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(CAM_D1, 100,
+                "cam_d1", NULL, "csi2_dy2", NULL,
+                "gpio_100", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(CAM_D10, 109,
+                "cam_d10", "ssi2_wake", NULL, NULL,
+                "gpio_109", "hw_dbg8", NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(CAM_D2, 101,
+                "cam_d2", "ssi2_rdy_tx", NULL, NULL,
+                "gpio_101", "hw_dbg4", NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(CAM_D3, 102,
+                "cam_d3", "ssi2_dat_rx", NULL, NULL,
+                "gpio_102", "hw_dbg5", NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(CAM_D4, 103,
+                "cam_d4", "ssi2_flag_rx", NULL, NULL,
+                "gpio_103", "hw_dbg6", NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(CAM_D5, 104,
+                "cam_d5", "ssi2_rdy_rx", NULL, NULL,
+                "gpio_104", "hw_dbg7", NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(CAM_HS, 94,
+                "cam_hs", "ssi2_dat_tx", NULL, NULL,
+                "gpio_94", "hw_dbg0", NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(CAM_VS, 95,
+                "cam_vs", "ssi2_flag_tx", NULL, NULL,
+                "gpio_95", "hw_dbg1", NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(DSS_DATA0, 70,
+                "dss_data0", "dsi_dx0", "uart1_cts", NULL,
+                "gpio_70", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(DSS_DATA1, 71,
+                "dss_data1", "dsi_dy0", "uart1_rts", NULL,
+                "gpio_71", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(DSS_DATA2, 72,
+                "dss_data2", "dsi_dx1", NULL, NULL,
+                "gpio_72", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(DSS_DATA3, 73,
+                "dss_data3", "dsi_dy1", NULL, NULL,
+                "gpio_73", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(DSS_DATA4, 74,
+                "dss_data4", "dsi_dx2", "uart3_rx_irrx", NULL,
+                "gpio_74", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(DSS_DATA5, 75,
+                "dss_data5", "dsi_dy2", "uart3_tx_irtx", NULL,
+                "gpio_75", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(DSS_DATA6, 76,
+                "dss_data6", NULL, "uart1_tx", "dssvenc656_data6",
+                "gpio_76", "hw_dbg14", NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(DSS_DATA7, 77,
+                "dss_data7", NULL, "uart1_rx", "dssvenc656_data7",
+                "gpio_77", "hw_dbg15", NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(DSS_DATA8, 78,
+                "dss_data8", NULL, "uart3_rx_irrx", NULL,
+                "gpio_78", "hw_dbg16", NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(DSS_DATA9, 79,
+                "dss_data9", NULL, "uart3_tx_irtx", NULL,
+                "gpio_79", "hw_dbg17", NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(ETK_D12, 26,
+                "etk_d12", "sys_drm_msecure", NULL, "hsusb2_dir",
+                "gpio_26", NULL, "hsusb2_tll_dir", "hw_dbg14"),
+        _OMAP3_MUXENTRY(GPMC_A11, 0,
+                "gpmc_a11", NULL, NULL, NULL,
+                NULL, NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(GPMC_WAIT2, 64,
+                "gpmc_wait2", NULL, "uart4_tx", NULL,
+                "gpio_64", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(GPMC_WAIT3, 65,
+                "gpmc_wait3", "sys_ndmareq1", "uart4_rx", NULL,
+                "gpio_65", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(HSUSB0_DATA0, 125,
+                "hsusb0_data0", NULL, "uart3_tx_irtx", NULL,
+                "gpio_125", "uart2_tx", NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(HSUSB0_DATA1, 130,
+                "hsusb0_data1", NULL, "uart3_rx_irrx", NULL,
+                "gpio_130", "uart2_rx", NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(HSUSB0_DATA2, 131,
+                "hsusb0_data2", NULL, "uart3_rts_sd", NULL,
+                "gpio_131", "uart2_rts", NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(HSUSB0_DATA3, 169,
+                "hsusb0_data3", NULL, "uart3_cts_rctx", NULL,
+                "gpio_169", "uart2_cts", NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(MCBSP1_CLKR, 156,
+                "mcbsp1_clkr", "mcspi4_clk", "sim_cd", NULL,
+                "gpio_156", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(MCBSP1_FSR, 157,
+                "mcbsp1_fsr", "adpllv2d_dithering_en1",
+                "cam_global_reset", NULL,
+                "gpio_157", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(MCBSP4_CLKX, 152,
+                "mcbsp4_clkx", "ssi1_dat_rx", NULL, NULL,
+                "gpio_152", "hsusb3_tll_data1", "mm3_txse0", "safe_mode"),
+        _OMAP3_MUXENTRY(MCBSP4_DR, 153,
+                "mcbsp4_dr", "ssi1_flag_rx", NULL, NULL,
+                "gpio_153", "hsusb3_tll_data0", "mm3_rxrcv", "safe_mode"),
+        _OMAP3_MUXENTRY(MCBSP4_DX, 154,
+                "mcbsp4_dx", "ssi1_rdy_rx", NULL, NULL,
+                "gpio_154", "hsusb3_tll_data2", "mm3_txdat", "safe_mode"),
+        _OMAP3_MUXENTRY(MCBSP4_FSX, 155,
+                "mcbsp4_fsx", "ssi1_wake", NULL, NULL,
+                "gpio_155", "hsusb3_tll_data3", "mm3_txen_n", "safe_mode"),
+        _OMAP3_MUXENTRY(MCSPI1_CS1, 175,
+                "mcspi1_cs1", "adpllv2d_dithering_en2", NULL, "sdmmc3_cmd",
+                "gpio_175", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(SAD2D_MBUSFLAG, 0,
+                "sad2d_mbusflag", "mad2d_sbusflag", NULL, NULL,
+                NULL, NULL, NULL, NULL),
+        _OMAP3_MUXENTRY(SAD2D_MCAD28, 0,
+                "sad2d_mcad28", "mad2d_mcad28", NULL, NULL,
+                NULL, NULL, NULL, NULL),
+        _OMAP3_MUXENTRY(SAD2D_MCAD29, 0,
+                "sad2d_mcad29", "mad2d_mcad29", NULL, NULL,
+                NULL, NULL, NULL, NULL),
+        _OMAP3_MUXENTRY(SAD2D_MCAD32, 0,
+                "sad2d_mcad32", "mad2d_mcad32", NULL, NULL,
+                NULL, NULL, NULL, NULL),
+        _OMAP3_MUXENTRY(SAD2D_MCAD33, 0,
+                "sad2d_mcad33", "mad2d_mcad33", NULL, NULL,
+                NULL, NULL, NULL, NULL),
+        _OMAP3_MUXENTRY(SAD2D_MCAD34, 0,
+                "sad2d_mcad34", "mad2d_mcad34", NULL, NULL,
+                NULL, NULL, NULL, NULL),
+        _OMAP3_MUXENTRY(SAD2D_MCAD35, 0,
+                "sad2d_mcad35", "mad2d_mcad35", NULL, NULL,
+                NULL, NULL, NULL, NULL),
+        _OMAP3_MUXENTRY(SAD2D_MCAD36, 0,
+                "sad2d_mcad36", "mad2d_mcad36", NULL, NULL,
+                NULL, NULL, NULL, NULL),
+        _OMAP3_MUXENTRY(SAD2D_MREAD, 0,
+                "sad2d_mread", "mad2d_sread", NULL, NULL,
+                NULL, NULL, NULL, NULL),
+        _OMAP3_MUXENTRY(SAD2D_MWRITE, 0,
+                "sad2d_mwrite", "mad2d_swrite", NULL, NULL,
+                NULL, NULL, NULL, NULL),
+        _OMAP3_MUXENTRY(SAD2D_SBUSFLAG, 0,
+                "sad2d_sbusflag", "mad2d_mbusflag", NULL, NULL,
+                NULL, NULL, NULL, NULL),
+        _OMAP3_MUXENTRY(SAD2D_SREAD, 0,
+                "sad2d_sread", "mad2d_mread", NULL, NULL,
+                NULL, NULL, NULL, NULL),
+        _OMAP3_MUXENTRY(SAD2D_SWRITE, 0,
+                "sad2d_swrite", "mad2d_mwrite", NULL, NULL,
+                NULL, NULL, NULL, NULL),
+        _OMAP3_MUXENTRY(SDMMC1_CLK, 120,
+                "sdmmc1_clk", "ms_clk", NULL, NULL,
+                "gpio_120", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(SDMMC1_CMD, 121,
+                "sdmmc1_cmd", "ms_bs", NULL, NULL,
+                "gpio_121", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(SDMMC1_DAT0, 122,
+                "sdmmc1_dat0", "ms_dat0", NULL, NULL,
+                "gpio_122", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(SDMMC1_DAT1, 123,
+                "sdmmc1_dat1", "ms_dat1", NULL, NULL,
+                "gpio_123", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(SDMMC1_DAT2, 124,
+                "sdmmc1_dat2", "ms_dat2", NULL, NULL,
+                "gpio_124", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(SDMMC1_DAT3, 125,
+                "sdmmc1_dat3", "ms_dat3", NULL, NULL,
+                "gpio_125", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(SDRC_CKE0, 0,
+                "sdrc_cke0", NULL, NULL, NULL,
+                NULL, NULL, NULL, "safe_mode_out1"),
+        _OMAP3_MUXENTRY(SDRC_CKE1, 0,
+                "sdrc_cke1", NULL, NULL, NULL,
+                NULL, NULL, NULL, "safe_mode_out1"),
+        _OMAP3_MUXENTRY(SIM_IO, 126,
+                "sim_io", "sim_io_low_impedance", NULL, NULL,
+                "gpio_126", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(SIM_CLK, 127,
+                "sim_clk", NULL, NULL, NULL,
+                "gpio_127", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(SIM_PWRCTRL, 128,
+                "sim_pwrctrl", NULL, NULL, NULL,
+                "gpio_128", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(SIM_RST, 129,
+                "sim_rst", NULL, NULL, NULL,
+                "gpio_129", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(SYS_BOOT0, 2,
+                "sys_boot0", NULL, NULL, "dss_data18",
+                "gpio_2", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(SYS_BOOT1, 3,
+                "sys_boot1", NULL, NULL, "dss_data19",
+                "gpio_3", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(SYS_BOOT3, 5,
+                "sys_boot3", NULL, NULL, "dss_data20",
+                "gpio_5", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(SYS_BOOT4, 6,
+                "sys_boot4", "sdmmc2_dir_dat2", NULL, "dss_data21",
+                "gpio_6", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(SYS_BOOT5, 7,
+                "sys_boot5", "sdmmc2_dir_dat3", NULL, "dss_data22",
+                "gpio_7", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(SYS_BOOT6, 8,
+                "sys_boot6", NULL, NULL, "dss_data23",
+                "gpio_8", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(UART1_CTS, 150,
+                "uart1_cts", "ssi1_rdy_tx", NULL, NULL,
+                "gpio_150", "hsusb3_tll_clk", NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(UART1_RTS, 149,
+                "uart1_rts", "ssi1_flag_tx", NULL, NULL,
+                "gpio_149", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(UART1_TX, 148,
+                "uart1_tx", "ssi1_dat_tx", NULL, NULL,
+                "gpio_148", NULL, NULL, "safe_mode"),
+        { .reg_offset = OMAP_MUX_TERMINATOR },
+};
+#else
+#define omap36xx_cbp_subset     NULL
+#endif
+
+/*
+ * Balls for 36XX CBP package
+ * 515-pin s-PBGA Package, 0.50mm Ball Pitch (Top), 0.40mm Ball Pitch (Bottom)
+ */
+#if defined(CONFIG_OMAP_MUX) && defined(CONFIG_DEBUG_FS)                \
+                && defined (CONFIG_OMAP_PACKAGE_CBP)
+struct omap_ball __initdata omap36xx_cbp_ball[] = {
+        _OMAP3_BALLENTRY(CAM_D0, "ag17", NULL),
+        _OMAP3_BALLENTRY(CAM_D1, "ah17", NULL),
+        _OMAP3_BALLENTRY(CAM_D10, "b25", NULL),
+        _OMAP3_BALLENTRY(CAM_D11, "c26", NULL),
+        _OMAP3_BALLENTRY(CAM_D2, "b24", NULL),
+        _OMAP3_BALLENTRY(CAM_D3, "c24", NULL),
+        _OMAP3_BALLENTRY(CAM_D4, "d24", NULL),
+        _OMAP3_BALLENTRY(CAM_D5, "a25", NULL),
+        _OMAP3_BALLENTRY(CAM_D6, "k28", NULL),
+        _OMAP3_BALLENTRY(CAM_D7, "l28", NULL),
+        _OMAP3_BALLENTRY(CAM_D8, "k27", NULL),
+        _OMAP3_BALLENTRY(CAM_D9, "l27", NULL),
+        _OMAP3_BALLENTRY(CAM_FLD, "c23", NULL),
+        _OMAP3_BALLENTRY(CAM_HS, "a24", NULL),
+        _OMAP3_BALLENTRY(CAM_PCLK, "c27", NULL),
+        _OMAP3_BALLENTRY(CAM_STROBE, "d25", NULL),
+        _OMAP3_BALLENTRY(CAM_VS, "a23", NULL),
+        _OMAP3_BALLENTRY(CAM_WEN, "b23", NULL),
+        _OMAP3_BALLENTRY(CAM_XCLKA, "c25", NULL),
+        _OMAP3_BALLENTRY(CAM_XCLKB, "b26", NULL),
+        _OMAP3_BALLENTRY(CSI2_DX0, "ag19", NULL),
+        _OMAP3_BALLENTRY(CSI2_DX1, "ag18", NULL),
+        _OMAP3_BALLENTRY(CSI2_DY0, "ah19", NULL),
+        _OMAP3_BALLENTRY(CSI2_DY1, "ah18", NULL),
+        _OMAP3_BALLENTRY(DSS_ACBIAS, "e27", NULL),
+        _OMAP3_BALLENTRY(DSS_DATA0, "ag22", NULL),
+        _OMAP3_BALLENTRY(DSS_DATA1, "ah22", NULL),
+        _OMAP3_BALLENTRY(DSS_DATA10, "ad28", NULL),
+        _OMAP3_BALLENTRY(DSS_DATA11, "ad27", NULL),
+        _OMAP3_BALLENTRY(DSS_DATA12, "ab28", NULL),
+        _OMAP3_BALLENTRY(DSS_DATA13, "ab27", NULL),
+        _OMAP3_BALLENTRY(DSS_DATA14, "aa28", NULL),
+        _OMAP3_BALLENTRY(DSS_DATA15, "aa27", NULL),
+        _OMAP3_BALLENTRY(DSS_DATA16, "g25", NULL),
+        _OMAP3_BALLENTRY(DSS_DATA17, "h27", NULL),
+        _OMAP3_BALLENTRY(DSS_DATA18, "h26", NULL),
+        _OMAP3_BALLENTRY(DSS_DATA19, "h25", NULL),
+        _OMAP3_BALLENTRY(DSS_DATA2, "ag23", NULL),
+        _OMAP3_BALLENTRY(DSS_DATA20, "e28", NULL),
+        _OMAP3_BALLENTRY(DSS_DATA21, "j26", NULL),
+        _OMAP3_BALLENTRY(DSS_DATA22, "ac27", NULL),
+        _OMAP3_BALLENTRY(DSS_DATA23, "ac28", NULL),
+        _OMAP3_BALLENTRY(DSS_DATA3, "ah23", NULL),
+        _OMAP3_BALLENTRY(DSS_DATA4, "ag24", NULL),
+        _OMAP3_BALLENTRY(DSS_DATA5, "ah24", NULL),
+        _OMAP3_BALLENTRY(DSS_DATA6, "e26", NULL),
+        _OMAP3_BALLENTRY(DSS_DATA7, "f28", NULL),
+        _OMAP3_BALLENTRY(DSS_DATA8, "f27", NULL),
+        _OMAP3_BALLENTRY(DSS_DATA9, "g26", NULL),
+        _OMAP3_BALLENTRY(DSS_HSYNC, "d26", NULL),
+        _OMAP3_BALLENTRY(DSS_PCLK, "d28", NULL),
+        _OMAP3_BALLENTRY(DSS_VSYNC, "d27", NULL),
+        _OMAP3_BALLENTRY(ETK_CLK, "af10", NULL),
+        _OMAP3_BALLENTRY(ETK_CTL, "ae10", NULL),
+        _OMAP3_BALLENTRY(ETK_D0, "af11", NULL),
+        _OMAP3_BALLENTRY(ETK_D1, "ag12", NULL),
+        _OMAP3_BALLENTRY(ETK_D10, "ae7", NULL),
+        _OMAP3_BALLENTRY(ETK_D11, "af7", NULL),
+        _OMAP3_BALLENTRY(ETK_D12, "ag7", NULL),
+        _OMAP3_BALLENTRY(ETK_D13, "ah7", NULL),
+        _OMAP3_BALLENTRY(ETK_D14, "ag8", NULL),
+        _OMAP3_BALLENTRY(ETK_D15, "ah8", NULL),
+        _OMAP3_BALLENTRY(ETK_D2, "ah12", NULL),
+        _OMAP3_BALLENTRY(ETK_D3, "ae13", NULL),
+        _OMAP3_BALLENTRY(ETK_D4, "ae11", NULL),
+        _OMAP3_BALLENTRY(ETK_D5, "ah9", NULL),
+        _OMAP3_BALLENTRY(ETK_D6, "af13", NULL),
+        _OMAP3_BALLENTRY(ETK_D7, "ah14", NULL),
+        _OMAP3_BALLENTRY(ETK_D8, "af9", NULL),
+        _OMAP3_BALLENTRY(ETK_D9, "ag9", NULL),
+        _OMAP3_BALLENTRY(GPMC_A1, "n4", "ac15"),
+        _OMAP3_BALLENTRY(GPMC_A10, "k3", "ab19"),
+        _OMAP3_BALLENTRY(GPMC_A11, NULL, "ac20"),
+        _OMAP3_BALLENTRY(GPMC_A2, "m4", "ab15"),
+        _OMAP3_BALLENTRY(GPMC_A3, "l4", "ac16"),
+        _OMAP3_BALLENTRY(GPMC_A4, "k4", "ab16"),
+        _OMAP3_BALLENTRY(GPMC_A5, "t3", "ac17"),
+        _OMAP3_BALLENTRY(GPMC_A6, "r3", "ab17"),
+        _OMAP3_BALLENTRY(GPMC_A7, "n3", "ac18"),
+        _OMAP3_BALLENTRY(GPMC_A8, "m3", "ab18"),
+        _OMAP3_BALLENTRY(GPMC_A9, "l3", "ac19"),
+        _OMAP3_BALLENTRY(GPMC_CLK, "t4", "w2"),
+        _OMAP3_BALLENTRY(GPMC_D0, "k1", "m2"),
+        _OMAP3_BALLENTRY(GPMC_D1, "l1", "m1"),
+        _OMAP3_BALLENTRY(GPMC_D10, "p1", "ab4"),
+        _OMAP3_BALLENTRY(GPMC_D11, "r1", "ac4"),
+        _OMAP3_BALLENTRY(GPMC_D12, "r2", "ab6"),
+        _OMAP3_BALLENTRY(GPMC_D13, "t2", "ac6"),
+        _OMAP3_BALLENTRY(GPMC_D14, "w1", "ab7"),
+        _OMAP3_BALLENTRY(GPMC_D15, "y1", "ac7"),
+        _OMAP3_BALLENTRY(GPMC_D2, "l2", "n2"),
+        _OMAP3_BALLENTRY(GPMC_D3, "p2", "n1"),
+        _OMAP3_BALLENTRY(GPMC_D4, "t1", "r2"),
+        _OMAP3_BALLENTRY(GPMC_D5, "v1", "r1"),
+        _OMAP3_BALLENTRY(GPMC_D6, "v2", "t2"),
+        _OMAP3_BALLENTRY(GPMC_D7, "w2", "t1"),
+        _OMAP3_BALLENTRY(GPMC_D8, "h2", "ab3"),
+        _OMAP3_BALLENTRY(GPMC_D9, "k2", "ac3"),
+        _OMAP3_BALLENTRY(GPMC_NADV_ALE, "f3", "w1"),
+        _OMAP3_BALLENTRY(GPMC_NBE0_CLE, "g3", "ac12"),
+        _OMAP3_BALLENTRY(GPMC_NBE1, "u3", NULL),
+        _OMAP3_BALLENTRY(GPMC_NCS0, "g4", "y2"),
+        _OMAP3_BALLENTRY(GPMC_NCS1, "h3", "y1"),
+        _OMAP3_BALLENTRY(GPMC_NCS2, "v8", NULL),
+        _OMAP3_BALLENTRY(GPMC_NCS3, "u8", NULL),
+        _OMAP3_BALLENTRY(GPMC_NCS4, "t8", NULL),
+        _OMAP3_BALLENTRY(GPMC_NCS5, "r8", NULL),
+        _OMAP3_BALLENTRY(GPMC_NCS6, "p8", NULL),
+        _OMAP3_BALLENTRY(GPMC_NCS7, "n8", NULL),
+        _OMAP3_BALLENTRY(GPMC_NOE, "g2", "v2"),
+        _OMAP3_BALLENTRY(GPMC_NWE, "f4", "v1"),
+        _OMAP3_BALLENTRY(GPMC_NWP, "h1", "ab10"),
+        _OMAP3_BALLENTRY(GPMC_WAIT0, "m8", "ab12"),
+        _OMAP3_BALLENTRY(GPMC_WAIT1, "l8", "ac10"),
+        _OMAP3_BALLENTRY(GPMC_WAIT2, "k8", NULL),
+        _OMAP3_BALLENTRY(GPMC_WAIT3, "j8", NULL),
+        _OMAP3_BALLENTRY(HDQ_SIO, "j25", NULL),
+        _OMAP3_BALLENTRY(HSUSB0_CLK, "t28", NULL),
+        _OMAP3_BALLENTRY(HSUSB0_DATA0, "t27", NULL),
+        _OMAP3_BALLENTRY(HSUSB0_DATA1, "u28", NULL),
+        _OMAP3_BALLENTRY(HSUSB0_DATA2, "u27", NULL),
+        _OMAP3_BALLENTRY(HSUSB0_DATA3, "u26", NULL),
+        _OMAP3_BALLENTRY(HSUSB0_DATA4, "u25", NULL),
+        _OMAP3_BALLENTRY(HSUSB0_DATA5, "v28", NULL),
+        _OMAP3_BALLENTRY(HSUSB0_DATA6, "v27", NULL),
+        _OMAP3_BALLENTRY(HSUSB0_DATA7, "v26", NULL),
+        _OMAP3_BALLENTRY(HSUSB0_DIR, "r28", NULL),
+        _OMAP3_BALLENTRY(HSUSB0_NXT, "t26", NULL),
+        _OMAP3_BALLENTRY(HSUSB0_STP, "t25", NULL),
+        _OMAP3_BALLENTRY(I2C1_SCL, "k21", NULL),
+        _OMAP3_BALLENTRY(I2C1_SDA, "j21", NULL),
+        _OMAP3_BALLENTRY(I2C2_SCL, "af15", NULL),
+        _OMAP3_BALLENTRY(I2C2_SDA, "ae15", NULL),
+        _OMAP3_BALLENTRY(I2C3_SCL, "af14", NULL),
+        _OMAP3_BALLENTRY(I2C3_SDA, "ag14", NULL),
+        _OMAP3_BALLENTRY(I2C4_SCL, "ad26", NULL),
+        _OMAP3_BALLENTRY(I2C4_SDA, "ae26", NULL),
+        _OMAP3_BALLENTRY(JTAG_EMU0, "aa11", NULL),
+        _OMAP3_BALLENTRY(JTAG_EMU1, "aa10", NULL),
+        _OMAP3_BALLENTRY(JTAG_RTCK, "aa12", NULL),
+        _OMAP3_BALLENTRY(JTAG_TCK, "aa13", NULL),
+        _OMAP3_BALLENTRY(JTAG_TDI, "aa20", NULL),
+        _OMAP3_BALLENTRY(JTAG_TDO, "aa19", NULL),
+        _OMAP3_BALLENTRY(JTAG_TMS_TMSC, "aa18", NULL),
+        _OMAP3_BALLENTRY(MCBSP1_CLKR, "y21", NULL),
+        _OMAP3_BALLENTRY(MCBSP1_CLKX, "w21", NULL),
+        _OMAP3_BALLENTRY(MCBSP1_DR, "u21", NULL),
+        _OMAP3_BALLENTRY(MCBSP1_DX, "v21", NULL),
+        _OMAP3_BALLENTRY(MCBSP1_FSR, "aa21", NULL),
+        _OMAP3_BALLENTRY(MCBSP1_FSX, "k26", NULL),
+        _OMAP3_BALLENTRY(MCBSP2_CLKX, "n21", NULL),
+        _OMAP3_BALLENTRY(MCBSP2_DR, "r21", NULL),
+        _OMAP3_BALLENTRY(MCBSP2_DX, "m21", NULL),
+        _OMAP3_BALLENTRY(MCBSP2_FSX, "p21", NULL),
+        _OMAP3_BALLENTRY(MCBSP3_CLKX, "af5", NULL),
+        _OMAP3_BALLENTRY(MCBSP3_DR, "ae6", NULL),
+        _OMAP3_BALLENTRY(MCBSP3_DX, "af6", NULL),
+        _OMAP3_BALLENTRY(MCBSP3_FSX, "ae5", NULL),
+        _OMAP3_BALLENTRY(MCBSP4_CLKX, "ae1", NULL),
+        _OMAP3_BALLENTRY(MCBSP4_DR, "ad1", NULL),
+        _OMAP3_BALLENTRY(MCBSP4_DX, "ad2", NULL),
+        _OMAP3_BALLENTRY(MCBSP4_FSX, "ac1", NULL),
+        _OMAP3_BALLENTRY(MCBSP_CLKS, "t21", NULL),
+        _OMAP3_BALLENTRY(MCSPI1_CLK, "ab3", NULL),
+        _OMAP3_BALLENTRY(MCSPI1_CS0, "ac2", NULL),
+        _OMAP3_BALLENTRY(MCSPI1_CS1, "ac3", NULL),
+        _OMAP3_BALLENTRY(MCSPI1_CS2, "ab1", NULL),
+        _OMAP3_BALLENTRY(MCSPI1_CS3, "ab2", NULL),
+        _OMAP3_BALLENTRY(MCSPI1_SIMO, "ab4", NULL),
+        _OMAP3_BALLENTRY(MCSPI1_SOMI, "aa4", NULL),
+        _OMAP3_BALLENTRY(MCSPI2_CLK, "aa3", NULL),
+        _OMAP3_BALLENTRY(MCSPI2_CS0, "y4", NULL),
+        _OMAP3_BALLENTRY(MCSPI2_CS1, "v3", NULL),
+        _OMAP3_BALLENTRY(MCSPI2_SIMO, "y2", NULL),
+        _OMAP3_BALLENTRY(MCSPI2_SOMI, "y3", NULL),
+        _OMAP3_BALLENTRY(SDMMC1_CLK, "n28", NULL),
+        _OMAP3_BALLENTRY(SDMMC1_CMD, "m27", NULL),
+        _OMAP3_BALLENTRY(SDMMC1_DAT0, "n27", NULL),
+        _OMAP3_BALLENTRY(SDMMC1_DAT1, "n26", NULL),
+        _OMAP3_BALLENTRY(SDMMC1_DAT2, "n25", NULL),
+        _OMAP3_BALLENTRY(SDMMC1_DAT3, "p28", NULL),
+        _OMAP3_BALLENTRY(SDMMC2_CLK, "ae2", NULL),
+        _OMAP3_BALLENTRY(SDMMC2_CMD, "ag5", NULL),
+        _OMAP3_BALLENTRY(SDMMC2_DAT0, "ah5", NULL),
+        _OMAP3_BALLENTRY(SDMMC2_DAT1, "ah4", NULL),
+        _OMAP3_BALLENTRY(SDMMC2_DAT2, "ag4", NULL),
+        _OMAP3_BALLENTRY(SDMMC2_DAT3, "af4", NULL),
+        _OMAP3_BALLENTRY(SDMMC2_DAT4, "ae4", NULL),
+        _OMAP3_BALLENTRY(SDMMC2_DAT5, "ah3", NULL),
+        _OMAP3_BALLENTRY(SDMMC2_DAT6, "af3", NULL),
+        _OMAP3_BALLENTRY(SDMMC2_DAT7, "ae3", NULL),
+        _OMAP3_BALLENTRY(SDRC_A0, NULL, "n22"),
+        _OMAP3_BALLENTRY(SDRC_A1, NULL, "n23"),
+        _OMAP3_BALLENTRY(SDRC_A10, NULL, "v22"),
+        _OMAP3_BALLENTRY(SDRC_A11, NULL, "v23"),
+        _OMAP3_BALLENTRY(SDRC_A12, NULL, "w22"),
+        _OMAP3_BALLENTRY(SDRC_A13, NULL, "w23"),
+        _OMAP3_BALLENTRY(SDRC_A14, NULL, "y22"),
+        _OMAP3_BALLENTRY(SDRC_A2, NULL, "p22"),
+        _OMAP3_BALLENTRY(SDRC_A3, NULL, "p23"),
+        _OMAP3_BALLENTRY(SDRC_A4, NULL, "r22"),
+        _OMAP3_BALLENTRY(SDRC_A5, NULL, "r23"),
+        _OMAP3_BALLENTRY(SDRC_A6, NULL, "t22"),
+        _OMAP3_BALLENTRY(SDRC_A7, NULL, "t23"),
+        _OMAP3_BALLENTRY(SDRC_A8, NULL, "u22"),
+        _OMAP3_BALLENTRY(SDRC_A9, NULL, "u23"),
+        _OMAP3_BALLENTRY(SDRC_BA0, "h9", "ab21"),
+        _OMAP3_BALLENTRY(SDRC_BA1, "h10", "ac21"),
+        _OMAP3_BALLENTRY(SDRC_CKE0, "h16", "j22"),
+        _OMAP3_BALLENTRY(SDRC_CKE1, "h17", "j23"),
+        _OMAP3_BALLENTRY(SDRC_CLK, "a13", "a11"),
+        _OMAP3_BALLENTRY(SDRC_D0, NULL, "j2"),
+        _OMAP3_BALLENTRY(SDRC_D1, NULL, "j1"),
+        _OMAP3_BALLENTRY(SDRC_D10, "c15", "b14"),
+        _OMAP3_BALLENTRY(SDRC_D11, "b16", "a14"),
+        _OMAP3_BALLENTRY(SDRC_D12, "d17", "b16"),
+        _OMAP3_BALLENTRY(SDRC_D13, "c17", "a16"),
+        _OMAP3_BALLENTRY(SDRC_D14, "b17", "b19"),
+        _OMAP3_BALLENTRY(SDRC_D15, "d18", "a19"),
+        _OMAP3_BALLENTRY(SDRC_D16, NULL, "b3"),
+        _OMAP3_BALLENTRY(SDRC_D17, NULL, "a3"),
+        _OMAP3_BALLENTRY(SDRC_D18, NULL, "b5"),
+        _OMAP3_BALLENTRY(SDRC_D19, NULL, "a5"),
+        _OMAP3_BALLENTRY(SDRC_D2, NULL, "g2"),
+        _OMAP3_BALLENTRY(SDRC_D20, NULL, "b8"),
+        _OMAP3_BALLENTRY(SDRC_D21, NULL, "a8"),
+        _OMAP3_BALLENTRY(SDRC_D22, NULL, "b9"),
+        _OMAP3_BALLENTRY(SDRC_D23, NULL, "a9"),
+        _OMAP3_BALLENTRY(SDRC_D24, NULL, "b21"),
+        _OMAP3_BALLENTRY(SDRC_D25, NULL, "a21"),
+        _OMAP3_BALLENTRY(SDRC_D26, NULL, "d22"),
+        _OMAP3_BALLENTRY(SDRC_D27, NULL, "d23"),
+        _OMAP3_BALLENTRY(SDRC_D28, NULL, "e22"),
+        _OMAP3_BALLENTRY(SDRC_D29, NULL, "e23"),
+        _OMAP3_BALLENTRY(SDRC_D3, NULL, "g1"),
+        _OMAP3_BALLENTRY(SDRC_D30, NULL, "g22"),
+        _OMAP3_BALLENTRY(SDRC_D31, NULL, "g23"),
+        _OMAP3_BALLENTRY(SDRC_D4, NULL, "f2"),
+        _OMAP3_BALLENTRY(SDRC_D5, NULL, "f1"),
+        _OMAP3_BALLENTRY(SDRC_D6, NULL, "d2"),
+        _OMAP3_BALLENTRY(SDRC_D7, NULL, "d1"),
+        _OMAP3_BALLENTRY(SDRC_D8, "c14", "b13"),
+        _OMAP3_BALLENTRY(SDRC_D9, "b14", "a13"),
+        _OMAP3_BALLENTRY(SDRC_DM0, NULL, "c1"),
+        _OMAP3_BALLENTRY(SDRC_DM1, "a16", "a17"),
+        _OMAP3_BALLENTRY(SDRC_DM2, NULL, "a6"),
+        _OMAP3_BALLENTRY(SDRC_DM3, NULL, "a20"),
+        _OMAP3_BALLENTRY(SDRC_DQS0, NULL, "c2"),
+        _OMAP3_BALLENTRY(SDRC_DQS1, "a17", "b17"),
+        _OMAP3_BALLENTRY(SDRC_DQS2, NULL, "b6"),
+        _OMAP3_BALLENTRY(SDRC_DQS3, NULL, "b20"),
+        _OMAP3_BALLENTRY(SDRC_NCAS, "h13", "l22"),
+        _OMAP3_BALLENTRY(SDRC_NCLK, "a14", "b11"),
+        _OMAP3_BALLENTRY(SDRC_NCS0, "h11", "m22"),
+        _OMAP3_BALLENTRY(SDRC_NCS1, "h12", "m23"),
+        _OMAP3_BALLENTRY(SDRC_NRAS, "h14", "l23"),
+        _OMAP3_BALLENTRY(SDRC_NWE, "h15", "k23"),
+        _OMAP3_BALLENTRY(SIM_CLK, "p26", NULL),
+        _OMAP3_BALLENTRY(SIM_IO, "p27", NULL),
+        _OMAP3_BALLENTRY(SIM_PWRCTRL, "r27", NULL),
+        _OMAP3_BALLENTRY(SIM_RST, "r25", NULL),
+        _OMAP3_BALLENTRY(SYS_32K, "ae25", NULL),
+        _OMAP3_BALLENTRY(SYS_BOOT0, "ah26", NULL),
+        _OMAP3_BALLENTRY(SYS_BOOT1, "ag26", NULL),
+        _OMAP3_BALLENTRY(SYS_BOOT2, "ae14", NULL),
+        _OMAP3_BALLENTRY(SYS_BOOT3, "af18", NULL),
+        _OMAP3_BALLENTRY(SYS_BOOT4, "af19", NULL),
+        _OMAP3_BALLENTRY(SYS_BOOT5, "ae21", NULL),
+        _OMAP3_BALLENTRY(SYS_BOOT6, "af21", NULL),
+        _OMAP3_BALLENTRY(SYS_CLKOUT1, "ag25", NULL),
+        _OMAP3_BALLENTRY(SYS_CLKOUT2, "ae22", NULL),
+        _OMAP3_BALLENTRY(SYS_CLKREQ, "af25", NULL),
+        _OMAP3_BALLENTRY(SYS_NIRQ, "af26", NULL),
+        _OMAP3_BALLENTRY(SYS_NRESWARM, "af24", NULL),
+        _OMAP3_BALLENTRY(SYS_OFF_MODE, "af22", NULL),
+        _OMAP3_BALLENTRY(UART1_CTS, "w8", NULL),
+        _OMAP3_BALLENTRY(UART1_RTS, "aa9", NULL),
+        _OMAP3_BALLENTRY(UART1_RX, "y8", NULL),
+        _OMAP3_BALLENTRY(UART1_TX, "aa8", NULL),
+        _OMAP3_BALLENTRY(UART2_CTS, "ab26", NULL),
+        _OMAP3_BALLENTRY(UART2_RTS, "ab25", NULL),
+        _OMAP3_BALLENTRY(UART2_RX, "ad25", NULL),
+        _OMAP3_BALLENTRY(UART2_TX, "aa25", NULL),
+        _OMAP3_BALLENTRY(UART3_CTS_RCTX, "h18", NULL),
+        _OMAP3_BALLENTRY(UART3_RTS_SD, "h19", NULL),
+        _OMAP3_BALLENTRY(UART3_RX_IRRX, "h20", NULL),
+        _OMAP3_BALLENTRY(UART3_TX_IRTX, "h21", NULL),
+        { .reg_offset = OMAP_MUX_TERMINATOR },
+};
+#else
+#define omap36xx_cbp_ball        NULL
+#endif
+
+int __init omap3_mux_init(struct omap_board_mux *board_subset, int flags)
+{
+        struct omap_mux *package_subset;
+        struct omap_ball *package_balls;
+
+        switch (flags & OMAP_PACKAGE_MASK) {
+        case (OMAP_PACKAGE_CBC):
+                package_subset = omap3_cbc_subset;
+                package_balls = omap3_cbc_ball;
+                break;
+        case (OMAP_PACKAGE_CBB):
+                package_subset = omap3_cbb_subset;
+                package_balls = omap3_cbb_ball;
+                break;
+        case (OMAP_PACKAGE_CUS):
+                package_subset = omap3_cus_subset;
+                package_balls = omap3_cus_ball;
+                break;
+        case (OMAP_PACKAGE_CBP):
+                package_subset = omap36xx_cbp_subset;
+                package_balls = omap36xx_cbp_ball;
+                break;
+        default:
+                printk(KERN_ERR "mux: Unknown omap package, mux disabled\n");
+                return -EINVAL;
+        }
+
+        return omap_mux_init(OMAP3_CONTROL_PADCONF_MUX_PBASE,
+                             OMAP3_CONTROL_PADCONF_MUX_SIZE,
+                                omap3_muxmodes, package_subset, board_subset,
+                                package_balls);
+}
diff --git a/arch/arm/mach-omap2/mux34xx.h b/arch/arm/mach-omap2/mux34xx.h
new file mode 100644
index 000000000000..6543ebf8ecfc
--- /dev/null
+++ b/arch/arm/mach-omap2/mux34xx.h
@@ -0,0 +1,398 @@
+/*
+ * Copyright (C) 2009 Nokia
+ * Copyright (C) 2009 Texas Instruments
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#define OMAP3_CONTROL_PADCONF_MUX_PBASE                         0x48002030LU
+
+#define OMAP3_MUX(mode0, mux_value)                                     \
+{                                                                       \
+        .reg_offset     = (OMAP3_CONTROL_PADCONF_##mode0##_OFFSET),     \
+        .value          = (mux_value),                                  \
+}
+
+/*
+ * OMAP3 CONTROL_PADCONF* register offsets for pin-muxing
+ *
+ * Extracted from the TRM.  Add 0x48002030 to these values to get the
+ * absolute addresses.  The name in the macro is the mode-0 name of
+ * the pin.  NOTE: These registers are 16-bits wide.
+ *
+ * Note that 34XX TRM uses MMC instead of SDMMC and SAD2D instead
+ * of CHASSIS for some registers. For the defines, we follow the
+ * 36XX naming, and use SDMMC and CHASSIS.
+ */
+#define OMAP3_CONTROL_PADCONF_SDRC_D0_OFFSET                    0x000
+#define OMAP3_CONTROL_PADCONF_SDRC_D1_OFFSET                    0x002
+#define OMAP3_CONTROL_PADCONF_SDRC_D2_OFFSET                    0x004
+#define OMAP3_CONTROL_PADCONF_SDRC_D3_OFFSET                    0x006
+#define OMAP3_CONTROL_PADCONF_SDRC_D4_OFFSET                    0x008
+#define OMAP3_CONTROL_PADCONF_SDRC_D5_OFFSET                    0x00a
+#define OMAP3_CONTROL_PADCONF_SDRC_D6_OFFSET                    0x00c
+#define OMAP3_CONTROL_PADCONF_SDRC_D7_OFFSET                    0x00e
+#define OMAP3_CONTROL_PADCONF_SDRC_D8_OFFSET                    0x010
+#define OMAP3_CONTROL_PADCONF_SDRC_D9_OFFSET                    0x012
+#define OMAP3_CONTROL_PADCONF_SDRC_D10_OFFSET                   0x014
+#define OMAP3_CONTROL_PADCONF_SDRC_D11_OFFSET                   0x016
+#define OMAP3_CONTROL_PADCONF_SDRC_D12_OFFSET                   0x018
+#define OMAP3_CONTROL_PADCONF_SDRC_D13_OFFSET                   0x01a
+#define OMAP3_CONTROL_PADCONF_SDRC_D14_OFFSET                   0x01c
+#define OMAP3_CONTROL_PADCONF_SDRC_D15_OFFSET                   0x01e
+#define OMAP3_CONTROL_PADCONF_SDRC_D16_OFFSET                   0x020
+#define OMAP3_CONTROL_PADCONF_SDRC_D17_OFFSET                   0x022
+#define OMAP3_CONTROL_PADCONF_SDRC_D18_OFFSET                   0x024
+#define OMAP3_CONTROL_PADCONF_SDRC_D19_OFFSET                   0x026
+#define OMAP3_CONTROL_PADCONF_SDRC_D20_OFFSET                   0x028
+#define OMAP3_CONTROL_PADCONF_SDRC_D21_OFFSET                   0x02a
+#define OMAP3_CONTROL_PADCONF_SDRC_D22_OFFSET                   0x02c
+#define OMAP3_CONTROL_PADCONF_SDRC_D23_OFFSET                   0x02e
+#define OMAP3_CONTROL_PADCONF_SDRC_D24_OFFSET                   0x030
+#define OMAP3_CONTROL_PADCONF_SDRC_D25_OFFSET                   0x032
+#define OMAP3_CONTROL_PADCONF_SDRC_D26_OFFSET                   0x034
+#define OMAP3_CONTROL_PADCONF_SDRC_D27_OFFSET                   0x036
+#define OMAP3_CONTROL_PADCONF_SDRC_D28_OFFSET                   0x038
+#define OMAP3_CONTROL_PADCONF_SDRC_D29_OFFSET                   0x03a
+#define OMAP3_CONTROL_PADCONF_SDRC_D30_OFFSET                   0x03c
+#define OMAP3_CONTROL_PADCONF_SDRC_D31_OFFSET                   0x03e
+#define OMAP3_CONTROL_PADCONF_SDRC_CLK_OFFSET                   0x040
+#define OMAP3_CONTROL_PADCONF_SDRC_DQS0_OFFSET                  0x042
+#define OMAP3_CONTROL_PADCONF_SDRC_DQS1_OFFSET                  0x044
+#define OMAP3_CONTROL_PADCONF_SDRC_DQS2_OFFSET                  0x046
+#define OMAP3_CONTROL_PADCONF_SDRC_DQS3_OFFSET                  0x048
+#define OMAP3_CONTROL_PADCONF_GPMC_A1_OFFSET                    0x04a
+#define OMAP3_CONTROL_PADCONF_GPMC_A2_OFFSET                    0x04c
+#define OMAP3_CONTROL_PADCONF_GPMC_A3_OFFSET                    0x04e
+#define OMAP3_CONTROL_PADCONF_GPMC_A4_OFFSET                    0x050
+#define OMAP3_CONTROL_PADCONF_GPMC_A5_OFFSET                    0x052
+#define OMAP3_CONTROL_PADCONF_GPMC_A6_OFFSET                    0x054
+#define OMAP3_CONTROL_PADCONF_GPMC_A7_OFFSET                    0x056
+#define OMAP3_CONTROL_PADCONF_GPMC_A8_OFFSET                    0x058
+#define OMAP3_CONTROL_PADCONF_GPMC_A9_OFFSET                    0x05a
+#define OMAP3_CONTROL_PADCONF_GPMC_A10_OFFSET                   0x05c
+#define OMAP3_CONTROL_PADCONF_GPMC_D0_OFFSET                    0x05e
+#define OMAP3_CONTROL_PADCONF_GPMC_D1_OFFSET                    0x060
+#define OMAP3_CONTROL_PADCONF_GPMC_D2_OFFSET                    0x062
+#define OMAP3_CONTROL_PADCONF_GPMC_D3_OFFSET                    0x064
+#define OMAP3_CONTROL_PADCONF_GPMC_D4_OFFSET                    0x066
+#define OMAP3_CONTROL_PADCONF_GPMC_D5_OFFSET                    0x068
+#define OMAP3_CONTROL_PADCONF_GPMC_D6_OFFSET                    0x06a
+#define OMAP3_CONTROL_PADCONF_GPMC_D7_OFFSET                    0x06c
+#define OMAP3_CONTROL_PADCONF_GPMC_D8_OFFSET                    0x06e
+#define OMAP3_CONTROL_PADCONF_GPMC_D9_OFFSET                    0x070
+#define OMAP3_CONTROL_PADCONF_GPMC_D10_OFFSET                   0x072
+#define OMAP3_CONTROL_PADCONF_GPMC_D11_OFFSET                   0x074
+#define OMAP3_CONTROL_PADCONF_GPMC_D12_OFFSET                   0x076
+#define OMAP3_CONTROL_PADCONF_GPMC_D13_OFFSET                   0x078
+#define OMAP3_CONTROL_PADCONF_GPMC_D14_OFFSET                   0x07a
+#define OMAP3_CONTROL_PADCONF_GPMC_D15_OFFSET                   0x07c
+#define OMAP3_CONTROL_PADCONF_GPMC_NCS0_OFFSET                  0x07e
+#define OMAP3_CONTROL_PADCONF_GPMC_NCS1_OFFSET                  0x080
+#define OMAP3_CONTROL_PADCONF_GPMC_NCS2_OFFSET                  0x082
+#define OMAP3_CONTROL_PADCONF_GPMC_NCS3_OFFSET                  0x084
+#define OMAP3_CONTROL_PADCONF_GPMC_NCS4_OFFSET                  0x086
+#define OMAP3_CONTROL_PADCONF_GPMC_NCS5_OFFSET                  0x088
+#define OMAP3_CONTROL_PADCONF_GPMC_NCS6_OFFSET                  0x08a
+#define OMAP3_CONTROL_PADCONF_GPMC_NCS7_OFFSET                  0x08c
+#define OMAP3_CONTROL_PADCONF_GPMC_CLK_OFFSET                   0x08e
+#define OMAP3_CONTROL_PADCONF_GPMC_NADV_ALE_OFFSET              0x090
+#define OMAP3_CONTROL_PADCONF_GPMC_NOE_OFFSET                   0x092
+#define OMAP3_CONTROL_PADCONF_GPMC_NWE_OFFSET                   0x094
+#define OMAP3_CONTROL_PADCONF_GPMC_NBE0_CLE_OFFSET              0x096
+#define OMAP3_CONTROL_PADCONF_GPMC_NBE1_OFFSET                  0x098
+#define OMAP3_CONTROL_PADCONF_GPMC_NWP_OFFSET                   0x09a
+#define OMAP3_CONTROL_PADCONF_GPMC_WAIT0_OFFSET                 0x09c
+#define OMAP3_CONTROL_PADCONF_GPMC_WAIT1_OFFSET                 0x09e
+#define OMAP3_CONTROL_PADCONF_GPMC_WAIT2_OFFSET                 0x0a0
+#define OMAP3_CONTROL_PADCONF_GPMC_WAIT3_OFFSET                 0x0a2
+#define OMAP3_CONTROL_PADCONF_DSS_PCLK_OFFSET                   0x0a4
+#define OMAP3_CONTROL_PADCONF_DSS_HSYNC_OFFSET                  0x0a6
+#define OMAP3_CONTROL_PADCONF_DSS_VSYNC_OFFSET                  0x0a8
+#define OMAP3_CONTROL_PADCONF_DSS_ACBIAS_OFFSET                 0x0aa
+#define OMAP3_CONTROL_PADCONF_DSS_DATA0_OFFSET                  0x0ac
+#define OMAP3_CONTROL_PADCONF_DSS_DATA1_OFFSET                  0x0ae
+#define OMAP3_CONTROL_PADCONF_DSS_DATA2_OFFSET                  0x0b0
+#define OMAP3_CONTROL_PADCONF_DSS_DATA3_OFFSET                  0x0b2
+#define OMAP3_CONTROL_PADCONF_DSS_DATA4_OFFSET                  0x0b4
+#define OMAP3_CONTROL_PADCONF_DSS_DATA5_OFFSET                  0x0b6
+#define OMAP3_CONTROL_PADCONF_DSS_DATA6_OFFSET                  0x0b8
+#define OMAP3_CONTROL_PADCONF_DSS_DATA7_OFFSET                  0x0ba
+#define OMAP3_CONTROL_PADCONF_DSS_DATA8_OFFSET                  0x0bc
+#define OMAP3_CONTROL_PADCONF_DSS_DATA9_OFFSET                  0x0be
+#define OMAP3_CONTROL_PADCONF_DSS_DATA10_OFFSET                 0x0c0
+#define OMAP3_CONTROL_PADCONF_DSS_DATA11_OFFSET                 0x0c2
+#define OMAP3_CONTROL_PADCONF_DSS_DATA12_OFFSET                 0x0c4
+#define OMAP3_CONTROL_PADCONF_DSS_DATA13_OFFSET                 0x0c6
+#define OMAP3_CONTROL_PADCONF_DSS_DATA14_OFFSET                 0x0c8
+#define OMAP3_CONTROL_PADCONF_DSS_DATA15_OFFSET                 0x0ca
+#define OMAP3_CONTROL_PADCONF_DSS_DATA16_OFFSET                 0x0cc
+#define OMAP3_CONTROL_PADCONF_DSS_DATA17_OFFSET                 0x0ce
+#define OMAP3_CONTROL_PADCONF_DSS_DATA18_OFFSET                 0x0d0
+#define OMAP3_CONTROL_PADCONF_DSS_DATA19_OFFSET                 0x0d2
+#define OMAP3_CONTROL_PADCONF_DSS_DATA20_OFFSET                 0x0d4
+#define OMAP3_CONTROL_PADCONF_DSS_DATA21_OFFSET                 0x0d6
+#define OMAP3_CONTROL_PADCONF_DSS_DATA22_OFFSET                 0x0d8
+#define OMAP3_CONTROL_PADCONF_DSS_DATA23_OFFSET                 0x0da
+#define OMAP3_CONTROL_PADCONF_CAM_HS_OFFSET                     0x0dc
+#define OMAP3_CONTROL_PADCONF_CAM_VS_OFFSET                     0x0de
+#define OMAP3_CONTROL_PADCONF_CAM_XCLKA_OFFSET                  0x0e0
+#define OMAP3_CONTROL_PADCONF_CAM_PCLK_OFFSET                   0x0e2
+#define OMAP3_CONTROL_PADCONF_CAM_FLD_OFFSET                    0x0e4
+#define OMAP3_CONTROL_PADCONF_CAM_D0_OFFSET                     0x0e6
+#define OMAP3_CONTROL_PADCONF_CAM_D1_OFFSET                     0x0e8
+#define OMAP3_CONTROL_PADCONF_CAM_D2_OFFSET                     0x0ea
+#define OMAP3_CONTROL_PADCONF_CAM_D3_OFFSET                     0x0ec
+#define OMAP3_CONTROL_PADCONF_CAM_D4_OFFSET                     0x0ee
+#define OMAP3_CONTROL_PADCONF_CAM_D5_OFFSET                     0x0f0
+#define OMAP3_CONTROL_PADCONF_CAM_D6_OFFSET                     0x0f2
+#define OMAP3_CONTROL_PADCONF_CAM_D7_OFFSET                     0x0f4
+#define OMAP3_CONTROL_PADCONF_CAM_D8_OFFSET                     0x0f6
+#define OMAP3_CONTROL_PADCONF_CAM_D9_OFFSET                     0x0f8
+#define OMAP3_CONTROL_PADCONF_CAM_D10_OFFSET                    0x0fa
+#define OMAP3_CONTROL_PADCONF_CAM_D11_OFFSET                    0x0fc
+#define OMAP3_CONTROL_PADCONF_CAM_XCLKB_OFFSET                  0x0fe
+#define OMAP3_CONTROL_PADCONF_CAM_WEN_OFFSET                    0x100
+#define OMAP3_CONTROL_PADCONF_CAM_STROBE_OFFSET                 0x102
+#define OMAP3_CONTROL_PADCONF_CSI2_DX0_OFFSET                   0x104
+#define OMAP3_CONTROL_PADCONF_CSI2_DY0_OFFSET                   0x106
+#define OMAP3_CONTROL_PADCONF_CSI2_DX1_OFFSET                   0x108
+#define OMAP3_CONTROL_PADCONF_CSI2_DY1_OFFSET                   0x10a
+#define OMAP3_CONTROL_PADCONF_MCBSP2_FSX_OFFSET                 0x10c
+#define OMAP3_CONTROL_PADCONF_MCBSP2_CLKX_OFFSET                0x10e
+#define OMAP3_CONTROL_PADCONF_MCBSP2_DR_OFFSET                  0x110
+#define OMAP3_CONTROL_PADCONF_MCBSP2_DX_OFFSET                  0x112
+#define OMAP3_CONTROL_PADCONF_SDMMC1_CLK_OFFSET                 0x114
+#define OMAP3_CONTROL_PADCONF_SDMMC1_CMD_OFFSET                 0x116
+#define OMAP3_CONTROL_PADCONF_SDMMC1_DAT0_OFFSET                0x118
+#define OMAP3_CONTROL_PADCONF_SDMMC1_DAT1_OFFSET                0x11a
+#define OMAP3_CONTROL_PADCONF_SDMMC1_DAT2_OFFSET                0x11c
+#define OMAP3_CONTROL_PADCONF_SDMMC1_DAT3_OFFSET                0x11e
+
+/* SDMMC1_DAT4 - DAT7 are SIM_IO SIM_CLK SIM_PWRCTRL and SIM_RST on 36xx */
+#define OMAP3_CONTROL_PADCONF_SDMMC1_DAT4_OFFSET                0x120
+#define OMAP3_CONTROL_PADCONF_SDMMC1_DAT5_OFFSET                0x122
+#define OMAP3_CONTROL_PADCONF_SDMMC1_DAT6_OFFSET                0x124
+#define OMAP3_CONTROL_PADCONF_SDMMC1_DAT7_OFFSET                0x126
+
+#define OMAP3_CONTROL_PADCONF_SDMMC2_CLK_OFFSET                 0x128
+#define OMAP3_CONTROL_PADCONF_SDMMC2_CMD_OFFSET                 0x12a
+#define OMAP3_CONTROL_PADCONF_SDMMC2_DAT0_OFFSET                0x12c
+#define OMAP3_CONTROL_PADCONF_SDMMC2_DAT1_OFFSET                0x12e
+#define OMAP3_CONTROL_PADCONF_SDMMC2_DAT2_OFFSET                0x130
+#define OMAP3_CONTROL_PADCONF_SDMMC2_DAT3_OFFSET                0x132
+#define OMAP3_CONTROL_PADCONF_SDMMC2_DAT4_OFFSET                0x134
+#define OMAP3_CONTROL_PADCONF_SDMMC2_DAT5_OFFSET                0x136
+#define OMAP3_CONTROL_PADCONF_SDMMC2_DAT6_OFFSET                0x138
+#define OMAP3_CONTROL_PADCONF_SDMMC2_DAT7_OFFSET                0x13a
+#define OMAP3_CONTROL_PADCONF_MCBSP3_DX_OFFSET                  0x13c
+#define OMAP3_CONTROL_PADCONF_MCBSP3_DR_OFFSET                  0x13e
+#define OMAP3_CONTROL_PADCONF_MCBSP3_CLKX_OFFSET                0x140
+#define OMAP3_CONTROL_PADCONF_MCBSP3_FSX_OFFSET                 0x142
+#define OMAP3_CONTROL_PADCONF_UART2_CTS_OFFSET                  0x144
+#define OMAP3_CONTROL_PADCONF_UART2_RTS_OFFSET                  0x146
+#define OMAP3_CONTROL_PADCONF_UART2_TX_OFFSET                   0x148
+#define OMAP3_CONTROL_PADCONF_UART2_RX_OFFSET                   0x14a
+#define OMAP3_CONTROL_PADCONF_UART1_TX_OFFSET                   0x14c
+#define OMAP3_CONTROL_PADCONF_UART1_RTS_OFFSET                  0x14e
+#define OMAP3_CONTROL_PADCONF_UART1_CTS_OFFSET                  0x150
+#define OMAP3_CONTROL_PADCONF_UART1_RX_OFFSET                   0x152
+#define OMAP3_CONTROL_PADCONF_MCBSP4_CLKX_OFFSET                0x154
+#define OMAP3_CONTROL_PADCONF_MCBSP4_DR_OFFSET                  0x156
+#define OMAP3_CONTROL_PADCONF_MCBSP4_DX_OFFSET                  0x158
+#define OMAP3_CONTROL_PADCONF_MCBSP4_FSX_OFFSET                 0x15a
+#define OMAP3_CONTROL_PADCONF_MCBSP1_CLKR_OFFSET                0x15c
+#define OMAP3_CONTROL_PADCONF_MCBSP1_FSR_OFFSET                 0x15e
+#define OMAP3_CONTROL_PADCONF_MCBSP1_DX_OFFSET                  0x160
+#define OMAP3_CONTROL_PADCONF_MCBSP1_DR_OFFSET                  0x162
+#define OMAP3_CONTROL_PADCONF_MCBSP_CLKS_OFFSET                 0x164
+#define OMAP3_CONTROL_PADCONF_MCBSP1_FSX_OFFSET                 0x166
+#define OMAP3_CONTROL_PADCONF_MCBSP1_CLKX_OFFSET                0x168
+#define OMAP3_CONTROL_PADCONF_UART3_CTS_RCTX_OFFSET             0x16a
+#define OMAP3_CONTROL_PADCONF_UART3_RTS_SD_OFFSET               0x16c
+#define OMAP3_CONTROL_PADCONF_UART3_RX_IRRX_OFFSET              0x16e
+#define OMAP3_CONTROL_PADCONF_UART3_TX_IRTX_OFFSET              0x170
+#define OMAP3_CONTROL_PADCONF_HSUSB0_CLK_OFFSET                 0x172
+#define OMAP3_CONTROL_PADCONF_HSUSB0_STP_OFFSET                 0x174
+#define OMAP3_CONTROL_PADCONF_HSUSB0_DIR_OFFSET                 0x176
+#define OMAP3_CONTROL_PADCONF_HSUSB0_NXT_OFFSET                 0x178
+#define OMAP3_CONTROL_PADCONF_HSUSB0_DATA0_OFFSET               0x17a
+#define OMAP3_CONTROL_PADCONF_HSUSB0_DATA1_OFFSET               0x17c
+#define OMAP3_CONTROL_PADCONF_HSUSB0_DATA2_OFFSET               0x17e
+#define OMAP3_CONTROL_PADCONF_HSUSB0_DATA3_OFFSET               0x180
+#define OMAP3_CONTROL_PADCONF_HSUSB0_DATA4_OFFSET               0x182
+#define OMAP3_CONTROL_PADCONF_HSUSB0_DATA5_OFFSET               0x184
+#define OMAP3_CONTROL_PADCONF_HSUSB0_DATA6_OFFSET               0x186
+#define OMAP3_CONTROL_PADCONF_HSUSB0_DATA7_OFFSET               0x188
+#define OMAP3_CONTROL_PADCONF_I2C1_SCL_OFFSET                   0x18a
+#define OMAP3_CONTROL_PADCONF_I2C1_SDA_OFFSET                   0x18c
+#define OMAP3_CONTROL_PADCONF_I2C2_SCL_OFFSET                   0x18e
+#define OMAP3_CONTROL_PADCONF_I2C2_SDA_OFFSET                   0x190
+#define OMAP3_CONTROL_PADCONF_I2C3_SCL_OFFSET                   0x192
+#define OMAP3_CONTROL_PADCONF_I2C3_SDA_OFFSET                   0x194
+#define OMAP3_CONTROL_PADCONF_HDQ_SIO_OFFSET                    0x196
+#define OMAP3_CONTROL_PADCONF_MCSPI1_CLK_OFFSET                 0x198
+#define OMAP3_CONTROL_PADCONF_MCSPI1_SIMO_OFFSET                0x19a
+#define OMAP3_CONTROL_PADCONF_MCSPI1_SOMI_OFFSET                0x19c
+#define OMAP3_CONTROL_PADCONF_MCSPI1_CS0_OFFSET                 0x19e
+#define OMAP3_CONTROL_PADCONF_MCSPI1_CS1_OFFSET                 0x1a0
+#define OMAP3_CONTROL_PADCONF_MCSPI1_CS2_OFFSET                 0x1a2
+#define OMAP3_CONTROL_PADCONF_MCSPI1_CS3_OFFSET                 0x1a4
+#define OMAP3_CONTROL_PADCONF_MCSPI2_CLK_OFFSET                 0x1a6
+#define OMAP3_CONTROL_PADCONF_MCSPI2_SIMO_OFFSET                0x1a8
+#define OMAP3_CONTROL_PADCONF_MCSPI2_SOMI_OFFSET                0x1aa
+#define OMAP3_CONTROL_PADCONF_MCSPI2_CS0_OFFSET                 0x1ac
+#define OMAP3_CONTROL_PADCONF_MCSPI2_CS1_OFFSET                 0x1ae
+#define OMAP3_CONTROL_PADCONF_SYS_NIRQ_OFFSET                   0x1b0
+#define OMAP3_CONTROL_PADCONF_SYS_CLKOUT2_OFFSET                0x1b2
+#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD0_OFFSET                0x1b4
+#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD1_OFFSET                0x1b6
+#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD2_OFFSET                0x1b8
+#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD3_OFFSET                0x1ba
+#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD4_OFFSET                0x1bc
+#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD5_OFFSET                0x1be
+#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD6_OFFSET                0x1c0
+#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD7_OFFSET                0x1c2
+#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD8_OFFSET                0x1c4
+#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD9_OFFSET                0x1c6
+#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD10_OFFSET               0x1c8
+#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD11_OFFSET               0x1ca
+#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD12_OFFSET               0x1cc
+#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD13_OFFSET               0x1ce
+#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD14_OFFSET               0x1d0
+#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD15_OFFSET               0x1d2
+#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD16_OFFSET               0x1d4
+#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD17_OFFSET               0x1d6
+#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD18_OFFSET               0x1d8
+#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD19_OFFSET               0x1da
+#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD20_OFFSET               0x1dc
+#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD21_OFFSET               0x1de
+#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD22_OFFSET               0x1e0
+#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD23_OFFSET               0x1e2
+#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD24_OFFSET               0x1e4
+#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD25_OFFSET               0x1e6
+#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD26_OFFSET               0x1e8
+#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD27_OFFSET               0x1ea
+#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD28_OFFSET               0x1ec
+#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD29_OFFSET               0x1ee
+#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD30_OFFSET               0x1f0
+#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD31_OFFSET               0x1f2
+#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD32_OFFSET               0x1f4
+#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD33_OFFSET               0x1f6
+#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD34_OFFSET               0x1f8
+#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD35_OFFSET               0x1fa
+#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD36_OFFSET               0x1fc
+
+/* Note that 34xx TRM has SAD2D instead of CHASSIS for these */
+#define OMAP3_CONTROL_PADCONF_CHASSIS_CLK26MI_OFFSET            0x1fe
+#define OMAP3_CONTROL_PADCONF_CHASSIS_NRESPWRON_OFFSET          0x200
+#define OMAP3_CONTROL_PADCONF_CHASSIS_NRESWARW_OFFSET           0x202
+#define OMAP3_CONTROL_PADCONF_CHASSIS_NIRQ_OFFSET               0x204
+#define OMAP3_CONTROL_PADCONF_CHASSIS_FIQ_OFFSET                0x206
+#define OMAP3_CONTROL_PADCONF_CHASSIS_ARMIRQ_OFFSET             0x208
+#define OMAP3_CONTROL_PADCONF_CHASSIS_IVAIRQ_OFFSET             0x20a
+#define OMAP3_CONTROL_PADCONF_CHASSIS_DMAREQ0_OFFSET            0x20c
+#define OMAP3_CONTROL_PADCONF_CHASSIS_DMAREQ1_OFFSET            0x20e
+#define OMAP3_CONTROL_PADCONF_CHASSIS_DMAREQ2_OFFSET            0x210
+#define OMAP3_CONTROL_PADCONF_CHASSIS_DMAREQ3_OFFSET            0x212
+#define OMAP3_CONTROL_PADCONF_CHASSIS_NTRST_OFFSET              0x214
+#define OMAP3_CONTROL_PADCONF_CHASSIS_TDI_OFFSET                0x216
+#define OMAP3_CONTROL_PADCONF_CHASSIS_TDO_OFFSET                0x218
+#define OMAP3_CONTROL_PADCONF_CHASSIS_TMS_OFFSET                0x21a
+#define OMAP3_CONTROL_PADCONF_CHASSIS_TCK_OFFSET                0x21c
+#define OMAP3_CONTROL_PADCONF_CHASSIS_RTCK_OFFSET               0x21e
+#define OMAP3_CONTROL_PADCONF_CHASSIS_MSTDBY_OFFSET             0x220
+#define OMAP3_CONTROL_PADCONF_CHASSIS_IDLEREQ_OFFSET            0x222
+#define OMAP3_CONTROL_PADCONF_CHASSIS_IDLEACK_OFFSET            0x224
+
+#define OMAP3_CONTROL_PADCONF_SAD2D_MWRITE_OFFSET               0x226
+#define OMAP3_CONTROL_PADCONF_SAD2D_SWRITE_OFFSET               0x228
+#define OMAP3_CONTROL_PADCONF_SAD2D_MREAD_OFFSET                0x22a
+#define OMAP3_CONTROL_PADCONF_SAD2D_SREAD_OFFSET                0x22c
+#define OMAP3_CONTROL_PADCONF_SAD2D_MBUSFLAG_OFFSET             0x22e
+#define OMAP3_CONTROL_PADCONF_SAD2D_SBUSFLAG_OFFSET             0x230
+#define OMAP3_CONTROL_PADCONF_SDRC_CKE0_OFFSET                  0x232
+#define OMAP3_CONTROL_PADCONF_SDRC_CKE1_OFFSET                  0x234
+
+/* 36xx only */
+#define OMAP3_CONTROL_PADCONF_GPMC_A11_OFFSET                   0x236
+#define OMAP3_CONTROL_PADCONF_SDRC_BA0_OFFSET                   0x570
+#define OMAP3_CONTROL_PADCONF_SDRC_BA1_OFFSET                   0x572
+#define OMAP3_CONTROL_PADCONF_SDRC_A0_OFFSET                    0x574
+#define OMAP3_CONTROL_PADCONF_SDRC_A1_OFFSET                    0x576
+#define OMAP3_CONTROL_PADCONF_SDRC_A2_OFFSET                    0x578
+#define OMAP3_CONTROL_PADCONF_SDRC_A3_OFFSET                    0x57a
+#define OMAP3_CONTROL_PADCONF_SDRC_A4_OFFSET                    0x57c
+#define OMAP3_CONTROL_PADCONF_SDRC_A5_OFFSET                    0x57e
+#define OMAP3_CONTROL_PADCONF_SDRC_A6_OFFSET                    0x580
+#define OMAP3_CONTROL_PADCONF_SDRC_A7_OFFSET                    0x582
+#define OMAP3_CONTROL_PADCONF_SDRC_A8_OFFSET                    0x584
+#define OMAP3_CONTROL_PADCONF_SDRC_A9_OFFSET                    0x586
+#define OMAP3_CONTROL_PADCONF_SDRC_A10_OFFSET                   0x588
+#define OMAP3_CONTROL_PADCONF_SDRC_A11_OFFSET                   0x58a
+#define OMAP3_CONTROL_PADCONF_SDRC_A12_OFFSET                   0x58c
+#define OMAP3_CONTROL_PADCONF_SDRC_A13_OFFSET                   0x58e
+#define OMAP3_CONTROL_PADCONF_SDRC_A14_OFFSET                   0x590
+#define OMAP3_CONTROL_PADCONF_SDRC_NCS0_OFFSET                  0x592
+#define OMAP3_CONTROL_PADCONF_SDRC_NCS1_OFFSET                  0x594
+#define OMAP3_CONTROL_PADCONF_SDRC_NCLK_OFFSET                  0x596
+#define OMAP3_CONTROL_PADCONF_SDRC_NRAS_OFFSET                  0x598
+#define OMAP3_CONTROL_PADCONF_SDRC_NCAS_OFFSET                  0x59a
+#define OMAP3_CONTROL_PADCONF_SDRC_NWE_OFFSET                   0x59c
+#define OMAP3_CONTROL_PADCONF_SDRC_DM0_OFFSET                   0x59e
+#define OMAP3_CONTROL_PADCONF_SDRC_DM1_OFFSET                   0x5a0
+#define OMAP3_CONTROL_PADCONF_SDRC_DM2_OFFSET                   0x5a2
+#define OMAP3_CONTROL_PADCONF_SDRC_DM3_OFFSET                   0x5a4
+
+/* 36xx only, these are SDMMC1_DAT4 - DAT7 on 34xx */
+#define OMAP3_CONTROL_PADCONF_SIM_IO_OFFSET                     0x120
+#define OMAP3_CONTROL_PADCONF_SIM_CLK_OFFSET                    0x122
+#define OMAP3_CONTROL_PADCONF_SIM_PWRCTRL_OFFSET                0x124
+#define OMAP3_CONTROL_PADCONF_SIM_RST_OFFSET                    0x126
+
+#define OMAP3_CONTROL_PADCONF_ETK_CLK_OFFSET                    0x5a8
+#define OMAP3_CONTROL_PADCONF_ETK_CTL_OFFSET                    0x5aa
+#define OMAP3_CONTROL_PADCONF_ETK_D0_OFFSET                     0x5ac
+#define OMAP3_CONTROL_PADCONF_ETK_D1_OFFSET                     0x5ae
+#define OMAP3_CONTROL_PADCONF_ETK_D2_OFFSET                     0x5b0
+#define OMAP3_CONTROL_PADCONF_ETK_D3_OFFSET                     0x5b2
+#define OMAP3_CONTROL_PADCONF_ETK_D4_OFFSET                     0x5b4
+#define OMAP3_CONTROL_PADCONF_ETK_D5_OFFSET                     0x5b6
+#define OMAP3_CONTROL_PADCONF_ETK_D6_OFFSET                     0x5b8
+#define OMAP3_CONTROL_PADCONF_ETK_D7_OFFSET                     0x5ba
+#define OMAP3_CONTROL_PADCONF_ETK_D8_OFFSET                     0x5bc
+#define OMAP3_CONTROL_PADCONF_ETK_D9_OFFSET                     0x5be
+#define OMAP3_CONTROL_PADCONF_ETK_D10_OFFSET                    0x5c0
+#define OMAP3_CONTROL_PADCONF_ETK_D11_OFFSET                    0x5c2
+#define OMAP3_CONTROL_PADCONF_ETK_D12_OFFSET                    0x5c4
+#define OMAP3_CONTROL_PADCONF_ETK_D13_OFFSET                    0x5c6
+#define OMAP3_CONTROL_PADCONF_ETK_D14_OFFSET                    0x5c8
+#define OMAP3_CONTROL_PADCONF_ETK_D15_OFFSET                    0x5ca
+#define OMAP3_CONTROL_PADCONF_I2C4_SCL_OFFSET                   0x9d0
+#define OMAP3_CONTROL_PADCONF_I2C4_SDA_OFFSET                   0x9d2
+#define OMAP3_CONTROL_PADCONF_SYS_32K_OFFSET                    0x9d4
+#define OMAP3_CONTROL_PADCONF_SYS_CLKREQ_OFFSET                 0x9d6
+#define OMAP3_CONTROL_PADCONF_SYS_NRESWARM_OFFSET               0x9d8
+#define OMAP3_CONTROL_PADCONF_SYS_BOOT0_OFFSET                  0x9da
+#define OMAP3_CONTROL_PADCONF_SYS_BOOT1_OFFSET                  0x9dc
+#define OMAP3_CONTROL_PADCONF_SYS_BOOT2_OFFSET                  0x9de
+#define OMAP3_CONTROL_PADCONF_SYS_BOOT3_OFFSET                  0x9e0
+#define OMAP3_CONTROL_PADCONF_SYS_BOOT4_OFFSET                  0x9e2
+#define OMAP3_CONTROL_PADCONF_SYS_BOOT5_OFFSET                  0x9e4
+#define OMAP3_CONTROL_PADCONF_SYS_BOOT6_OFFSET                  0x9e6
+#define OMAP3_CONTROL_PADCONF_SYS_OFF_MODE_OFFSET               0x9e8
+#define OMAP3_CONTROL_PADCONF_SYS_CLKOUT1_OFFSET                0x9ea
+#define OMAP3_CONTROL_PADCONF_JTAG_NTRST_OFFSET                 0x9ec
+#define OMAP3_CONTROL_PADCONF_JTAG_TCK_OFFSET                   0x9ee
+#define OMAP3_CONTROL_PADCONF_JTAG_TMS_TMSC_OFFSET              0x9f0
+#define OMAP3_CONTROL_PADCONF_JTAG_TDI_OFFSET                   0x9f2
+#define OMAP3_CONTROL_PADCONF_JTAG_EMU0_OFFSET                  0x9f4
+#define OMAP3_CONTROL_PADCONF_JTAG_EMU1_OFFSET                  0x9f6
+#define OMAP3_CONTROL_PADCONF_SAD2D_SWAKEUP_OFFSET              0xa1c
+#define OMAP3_CONTROL_PADCONF_JTAG_RTCK_OFFSET                  0xa1e
+#define OMAP3_CONTROL_PADCONF_JTAG_TDO_OFFSET                   0xa20
+
+#define OMAP3_CONTROL_PADCONF_MUX_SIZE                          \
+                (OMAP3_CONTROL_PADCONF_JTAG_TDO_OFFSET + 0x2)
diff --git a/arch/arm/mach-omap2/omap-headsmp.S b/arch/arm/mach-omap2/omap-headsmp.S
index 4afadba09477..aa3f65c2ac97 100644
--- a/arch/arm/mach-omap2/omap-headsmp.S
+++ b/arch/arm/mach-omap2/omap-headsmp.S
@@ -27,20 +27,39 @@
  * OMAP4 specific entry point for secondary CPU to jump from ROM
  * code.  This routine also provides a holding flag into which
  * secondary core is held until we're ready for it to initialise.
- * The primary core will update the this flag using a hardware
- * register AuxCoreBoot1.
+ * The primary core will update this flag using a hardware
+ * register AuxCoreBoot0.
  */
 ENTRY(omap_secondary_startup)
-        mrc     p15, 0, r0, c0, c0, 5
-        and     r0, r0, #0x0f
-hold:   ldr     r1, =OMAP4_AUX_CORE_BOOT1_PA    @ read from AuxCoreBoot1
-        ldr     r2, [r1]
-        cmp     r2, r0
+hold:   ldr     r12,=0x103
+        dsb
+        smc                             @ read from AuxCoreBoot0
+        mov     r0, r0, lsr #9
+        mrc     p15, 0, r4, c0, c0, 5
+        and     r4, r4, #0x0f
+        cmp     r0, r4
         bne     hold
 
         /*
-         * we've been released from the cpu_release,secondary_stack
+         * we've been released from the wait loop,secondary_stack
          * should now contain the SVC stack for this core
          */
         b       secondary_startup
+END(omap_secondary_startup)
 
+
+ENTRY(omap_modify_auxcoreboot0)
+        stmfd   sp!, {r1-r12, lr}
+        ldr     r12, =0x104
+        dsb
+        smc
+        ldmfd   sp!, {r1-r12, pc}
+END(omap_modify_auxcoreboot0)
+
+ENTRY(omap_auxcoreboot_addr)
+        stmfd   sp!, {r2-r12, lr}
+        ldr     r12, =0x105
+        dsb
+        smc
+        ldmfd   sp!, {r2-r12, pc}
+END(omap_auxcoreboot_addr)
diff --git a/arch/arm/mach-omap2/omap-smp.c b/arch/arm/mach-omap2/omap-smp.c
index 4890bcf4dadd..38153e5fbca0 100644
--- a/arch/arm/mach-omap2/omap-smp.c
+++ b/arch/arm/mach-omap2/omap-smp.c
@@ -17,19 +17,15 @@
  */
 #include <linux/init.h>
 #include <linux/device.h>
-#include <linux/jiffies.h>
 #include <linux/smp.h>
 #include <linux/io.h>
 
+#include <asm/cacheflush.h>
 #include <asm/localtimer.h>
 #include <asm/smp_scu.h>
 #include <mach/hardware.h>
 #include <plat/common.h>
 
-/* Registers used for communicating startup information */
-static void __iomem *omap4_auxcoreboot_reg0;
-static void __iomem *omap4_auxcoreboot_reg1;
-
 /* SCU base address */
 static void __iomem *scu_base;
 
@@ -65,8 +61,6 @@ void __cpuinit platform_secondary_init(unsigned int cpu)
 
 int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
 {
-        unsigned long timeout;
-
         /*
          * Set synchronisation state between this boot processor
          * and the secondary one
@@ -74,18 +68,15 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
         spin_lock(&boot_lock);
 
         /*
-         * Update the AuxCoreBoot1 with boot state for secondary core.
+         * Update the AuxCoreBoot0 with boot state for secondary core.
          * omap_secondary_startup() routine will hold the secondary core till
          * the AuxCoreBoot1 register is updated with cpu state
          * A barrier is added to ensure that write buffer is drained
          */
-        __raw_writel(cpu, omap4_auxcoreboot_reg1);
+        omap_modify_auxcoreboot0(0x200, 0x0);
+        flush_cache_all();
         smp_wmb();
 
-        timeout = jiffies + (1 * HZ);
-        while (time_before(jiffies, timeout))
-                ;
-
         /*
          * Now the secondary core is starting up let it run its
          * calibrations, then wait for it to finish
@@ -99,17 +90,18 @@ static void __init wakeup_secondary(void)
 {
         /*
          * Write the address of secondary startup routine into the
-         * AuxCoreBoot0 where ROM code will jump and start executing
+         * AuxCoreBoot1 where ROM code will jump and start executing
          * on secondary core once out of WFE
          * A barrier is added to ensure that write buffer is drained
          */
-        __raw_writel(virt_to_phys(omap_secondary_startup),         \
-                                        omap4_auxcoreboot_reg0);
+        omap_auxcoreboot_addr(virt_to_phys(omap_secondary_startup));
         smp_wmb();
 
         /*
          * Send a 'sev' to wake the secondary core from WFE.
+         * Drain the outstanding writes to memory
          */
+        dsb();
         set_event();
         mb();
 }
@@ -136,7 +128,6 @@ void __init smp_prepare_cpus(unsigned int max_cpus)
 {
         unsigned int ncores = get_core_count();
         unsigned int cpu = smp_processor_id();
-        void __iomem *omap4_wkupgen_base;
         int i;
 
         /* sanity check */
@@ -168,12 +159,6 @@ void __init smp_prepare_cpus(unsigned int max_cpus)
         for (i = 0; i < max_cpus; i++)
                 set_cpu_present(i, true);
 
-        /* Never released */
-        omap4_wkupgen_base = ioremap(OMAP44XX_WKUPGEN_BASE, SZ_4K);
-        BUG_ON(!omap4_wkupgen_base);
-        omap4_auxcoreboot_reg0 = omap4_wkupgen_base + 0x800;
-        omap4_auxcoreboot_reg1 = omap4_wkupgen_base + 0x804;
-
         if (max_cpus > 1) {
                 /*
                  * Enable the local timer or broadcast device for the
diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index 633b216a8b26..d8c8545875b1 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -45,6 +45,7 @@
 #include <linux/mutex.h>
 #include <linux/bootmem.h>
 
+#include <plat/common.h>
 #include <plat/cpu.h>
 #include <plat/clockdomain.h>
 #include <plat/powerdomain.h>
@@ -210,6 +211,32 @@ static int _set_softreset(struct omap_hwmod *oh, u32 *v)
 }
 
 /**
+ * _set_module_autoidle: set the OCP_SYSCONFIG AUTOIDLE field in @v
+ * @oh: struct omap_hwmod *
+ * @autoidle: desired AUTOIDLE bitfield value (0 or 1)
+ * @v: pointer to register contents to modify
+ *
+ * Update the module autoidle bit in @v to be @autoidle for the @oh
+ * hwmod.  The autoidle bit controls whether the module can gate
+ * internal clocks automatically when it isn't doing anything; the
+ * exact function of this bit varies on a per-module basis.  This
+ * function does not write to the hardware.  Returns -EINVAL upon
+ * error or 0 upon success.
+ */
+static int _set_module_autoidle(struct omap_hwmod *oh, u8 autoidle,
+                                u32 *v)
+{
+        if (!oh->sysconfig ||
+            !(oh->sysconfig->sysc_flags & SYSC_HAS_AUTOIDLE))
+                return -EINVAL;
+
+        *v &= ~SYSC_AUTOIDLE_MASK;
+        *v |= autoidle << SYSC_AUTOIDLE_SHIFT;
+
+        return 0;
+}
+
+/**
  * _enable_wakeup: set OCP_SYSCONFIG.ENAWAKEUP bit in the hardware
  * @oh: struct omap_hwmod *
  *
@@ -326,6 +353,9 @@ static int _init_main_clk(struct omap_hwmod *oh)
                 ret = -EINVAL;
         oh->_clk = c;
 
+        WARN(!c->clkdm, "omap_hwmod: %s: missing clockdomain for %s.\n",
+             oh->clkdev_con_id, c->name);
+
         return ret;
 }
 
@@ -557,8 +587,19 @@ static void _sysc_enable(struct omap_hwmod *oh)
                 _set_master_standbymode(oh, idlemode, &v);
         }
 
-        /* XXX OCP AUTOIDLE bit? */
+        if (oh->sysconfig->sysc_flags & SYSC_HAS_AUTOIDLE) {
+                idlemode = (oh->flags & HWMOD_NO_OCP_AUTOIDLE) ?
+                        0 : 1;
+                _set_module_autoidle(oh, idlemode, &v);
+        }
+
+        /* XXX OCP ENAWAKEUP bit? */
 
+        /*
+         * XXX The clock framework should handle this, by
+         * calling into this code.  But this must wait until the
+         * clock structures are tagged with omap_hwmod entries
+         */
         if (oh->flags & HWMOD_SET_DEFAULT_CLOCKACT &&
             oh->sysconfig->sysc_flags & SYSC_HAS_CLOCKACTIVITY)
                 _set_clockactivity(oh, oh->sysconfig->clockact, &v);
@@ -622,7 +663,8 @@ static void _sysc_shutdown(struct omap_hwmod *oh)
         if (oh->sysconfig->sysc_flags & SYSC_HAS_MIDLEMODE)
                 _set_master_standbymode(oh, HWMOD_IDLEMODE_FORCE, &v);
 
-        /* XXX clear OCP AUTOIDLE bit? */
+        if (oh->sysconfig->sysc_flags & SYSC_HAS_AUTOIDLE)
+                _set_module_autoidle(oh, 1, &v);
 
         _write_sysconfig(v, oh);
 }
@@ -736,7 +778,7 @@ static int _wait_target_ready(struct omap_hwmod *oh)
 static int _reset(struct omap_hwmod *oh)
 {
         u32 r, v;
-        int c;
+        int c = 0;
 
         if (!oh->sysconfig ||
             !(oh->sysconfig->sysc_flags & SYSC_HAS_SOFTRESET) ||
@@ -758,13 +800,9 @@ static int _reset(struct omap_hwmod *oh)
                 return r;
         _write_sysconfig(v, oh);
 
-        c = 0;
-        while (c < MAX_MODULE_RESET_WAIT &&
-               !(omap_hwmod_readl(oh, oh->sysconfig->syss_offs) &
-                 SYSS_RESETDONE_MASK)) {
-                udelay(1);
-                c++;
-        }
+        omap_test_timeout((omap_hwmod_readl(oh, oh->sysconfig->syss_offs) &
+                           SYSS_RESETDONE_MASK),
+                          MAX_MODULE_RESET_WAIT, c);
 
         if (c == MAX_MODULE_RESET_WAIT)
                 WARN(1, "omap_hwmod: %s: failed to reset in %d usec\n",
@@ -884,33 +922,6 @@ static int _shutdown(struct omap_hwmod *oh)
 }
 
 /**
- * _write_clockact_lock - set the module's clockactivity bits
- * @oh: struct omap_hwmod *
- * @clockact: CLOCKACTIVITY field bits
- *
- * Writes the CLOCKACTIVITY bits @clockact to the hwmod @oh
- * OCP_SYSCONFIG register.  Returns -EINVAL if the hwmod is in the
- * wrong state or returns 0.
- */
-static int _write_clockact_lock(struct omap_hwmod *oh, u8 clockact)
-{
-        u32 v;
-
-        if (!oh->sysconfig ||
-            !(oh->sysconfig->sysc_flags & SYSC_HAS_CLOCKACTIVITY))
-                return -EINVAL;
-
-        mutex_lock(&omap_hwmod_mutex);
-        v = oh->_sysc_cache;
-        _set_clockactivity(oh, clockact, &v);
-        _write_sysconfig(v, oh);
-        mutex_unlock(&omap_hwmod_mutex);
-
-        return 0;
-}
-
-
-/**
  * _setup - do initial configuration of omap_hwmod
  * @oh: struct omap_hwmod *
  *
@@ -948,11 +959,19 @@ static int _setup(struct omap_hwmod *oh)
 
         _enable(oh);
 
-        if (!(oh->flags & HWMOD_INIT_NO_RESET))
-                _reset(oh);
-
-        /* XXX OCP AUTOIDLE bit? */
-        /* XXX OCP ENAWAKEUP bit? */
+        if (!(oh->flags & HWMOD_INIT_NO_RESET)) {
+                /*
+                 * XXX Do the OCP_SYSCONFIG bits need to be
+                 * reprogrammed after a reset?  If not, then this can
+                 * be removed.  If they do, then probably the
+                 * _enable() function should be split to avoid the
+                 * rewrite of the OCP_SYSCONFIG register.
+                 */
+                if (oh->sysconfig) {
+                        _update_sysc_cache(oh);
+                        _sysc_enable(oh);
+                }
+        }
 
         if (!(oh->flags & HWMOD_INIT_NO_IDLE))
                 _idle(oh);
@@ -1348,8 +1367,9 @@ int omap_hwmod_fill_resources(struct omap_hwmod *oh, struct resource *res)
         /* For each IRQ, DMA, memory area, fill in array.*/
 
         for (i = 0; i < oh->mpu_irqs_cnt; i++) {
-                (res + r)->start = *(oh->mpu_irqs + i);
-                (res + r)->end = *(oh->mpu_irqs + i);
+                (res + r)->name = (oh->mpu_irqs + i)->name;
+                (res + r)->start = (oh->mpu_irqs + i)->irq;
+                (res + r)->end = (oh->mpu_irqs + i)->irq;
                 (res + r)->flags = IORESOURCE_IRQ;
                 r++;
         }
@@ -1454,62 +1474,6 @@ int omap_hwmod_del_initiator_dep(struct omap_hwmod *oh,
 }
 
 /**
- * omap_hwmod_set_clockact_none - set clockactivity test to BOTH
- * @oh: struct omap_hwmod *
- *
- * On some modules, this function can affect the wakeup latency vs.
- * power consumption balance.  Intended to be called by the
- * omap_device layer.  Passes along the return value from
- * _write_clockact_lock().
- */
-int omap_hwmod_set_clockact_both(struct omap_hwmod *oh)
-{
-        return _write_clockact_lock(oh, CLOCKACT_TEST_BOTH);
-}
-
-/**
- * omap_hwmod_set_clockact_none - set clockactivity test to MAIN
- * @oh: struct omap_hwmod *
- *
- * On some modules, this function can affect the wakeup latency vs.
- * power consumption balance.  Intended to be called by the
- * omap_device layer.  Passes along the return value from
- * _write_clockact_lock().
- */
-int omap_hwmod_set_clockact_main(struct omap_hwmod *oh)
-{
-        return _write_clockact_lock(oh, CLOCKACT_TEST_MAIN);
-}
-
-/**
- * omap_hwmod_set_clockact_none - set clockactivity test to ICLK
- * @oh: struct omap_hwmod *
- *
- * On some modules, this function can affect the wakeup latency vs.
- * power consumption balance.  Intended to be called by the
- * omap_device layer.  Passes along the return value from
- * _write_clockact_lock().
- */
-int omap_hwmod_set_clockact_iclk(struct omap_hwmod *oh)
-{
-        return _write_clockact_lock(oh, CLOCKACT_TEST_ICLK);
-}
-
-/**
- * omap_hwmod_set_clockact_none - set clockactivity test to NONE
- * @oh: struct omap_hwmod *
- *
- * On some modules, this function can affect the wakeup latency vs.
- * power consumption balance.  Intended to be called by the
- * omap_device layer.  Passes along the return value from
- * _write_clockact_lock().
- */
-int omap_hwmod_set_clockact_none(struct omap_hwmod *oh)
-{
-        return _write_clockact_lock(oh, CLOCKACT_TEST_NONE);
-}
-
-/**
  * omap_hwmod_enable_wakeup - allow device to wake up the system
  * @oh: struct omap_hwmod *
  *
diff --git a/arch/arm/mach-omap2/opp2420_data.c b/arch/arm/mach-omap2/opp2420_data.c
new file mode 100644
index 000000000000..126a9396b3a8
--- /dev/null
+++ b/arch/arm/mach-omap2/opp2420_data.c
@@ -0,0 +1,126 @@
+/*
+ * opp2420_data.c - old-style "OPP" table for OMAP2420
+ *
+ * Copyright (C) 2005-2009 Texas Instruments, Inc.
+ * Copyright (C) 2004-2009 Nokia Corporation
+ *
+ * Richard Woodruff <r-woodruff2@ti.com>
+ *
+ * The OMAP2 processor can be run at several discrete 'PRCM configurations'.
+ * These configurations are characterized by voltage and speed for clocks.
+ * The device is only validated for certain combinations. One way to express
+ * these combinations is via the 'ratio's' which the clocks operate with
+ * respect to each other. These ratio sets are for a given voltage/DPLL
+ * setting. All configurations can be described by a DPLL setting and a ratio
+ * There are 3 ratio sets for the 2430 and X ratio sets for 2420.
+ *
+ * 2430 differs from 2420 in that there are no more phase synchronizers used.
+ * They both have a slightly different clock domain setup. 2420(iva1,dsp) vs
+ * 2430 (iva2.1, NOdsp, mdm)
+ *
+ * XXX Missing voltage data.
+ *
+ * THe format described in this file is deprecated.  Once a reasonable
+ * OPP API exists, the data in this file should be converted to use it.
+ *
+ * This is technically part of the OMAP2xxx clock code.
+ */
+
+#include "opp2xxx.h"
+#include "sdrc.h"
+#include "clock.h"
+
+/*-------------------------------------------------------------------------
+ * Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated.
+ * xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU,
+ * CM_CLKSEL_DSP, CM_CLKSEL_GFX, CM_CLKSEL1_CORE, CM_CLKSEL1_PLL,
+ * CM_CLKSEL2_PLL, CM_CLKSEL_MDM
+ *
+ * Filling in table based on H4 boards and 2430-SDPs variants available.
+ * There are quite a few more rates combinations which could be defined.
+ *
+ * When multiple values are defined the start up will try and choose the
+ * fastest one. If a 'fast' value is defined, then automatically, the /2
+ * one should be included as it can be used.    Generally having more that
+ * one fast set does not make sense, as static timings need to be changed
+ * to change the set.    The exception is the bypass setting which is
+ * availble for low power bypass.
+ *
+ * Note: This table needs to be sorted, fastest to slowest.
+ *-------------------------------------------------------------------------*/
+const struct prcm_config omap2420_rate_table[] = {
+        /* PRCM I - FAST */
+        {S12M, S660M, S330M, RI_CM_CLKSEL_MPU_VAL,              /* 330MHz ARM */
+                RI_CM_CLKSEL_DSP_VAL, RI_CM_CLKSEL_GFX_VAL,
+                RI_CM_CLKSEL1_CORE_VAL, MI_CM_CLKSEL1_PLL_12_VAL,
+                MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_165MHz,
+                RATE_IN_242X},
+
+        /* PRCM II - FAST */
+        {S12M, S600M, S300M, RII_CM_CLKSEL_MPU_VAL,             /* 300MHz ARM */
+                RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
+                RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_12_VAL,
+                MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
+                RATE_IN_242X},
+
+        {S13M, S600M, S300M, RII_CM_CLKSEL_MPU_VAL,             /* 300MHz ARM */
+                RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
+                RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_13_VAL,
+                MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
+                RATE_IN_242X},
+
+        /* PRCM III - FAST */
+        {S12M, S532M, S266M, RIII_CM_CLKSEL_MPU_VAL,            /* 266MHz ARM */
+                RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
+                RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_12_VAL,
+                MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
+                RATE_IN_242X},
+
+        {S13M, S532M, S266M, RIII_CM_CLKSEL_MPU_VAL,            /* 266MHz ARM */
+                RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
+                RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_13_VAL,
+                MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
+                RATE_IN_242X},
+
+        /* PRCM II - SLOW */
+        {S12M, S300M, S150M, RII_CM_CLKSEL_MPU_VAL,             /* 150MHz ARM */
+                RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
+                RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_12_VAL,
+                MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
+                RATE_IN_242X},
+
+        {S13M, S300M, S150M, RII_CM_CLKSEL_MPU_VAL,             /* 150MHz ARM */
+                RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
+                RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_13_VAL,
+                MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
+                RATE_IN_242X},
+
+        /* PRCM III - SLOW */
+        {S12M, S266M, S133M, RIII_CM_CLKSEL_MPU_VAL,            /* 133MHz ARM */
+                RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
+                RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_12_VAL,
+                MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
+                RATE_IN_242X},
+
+        {S13M, S266M, S133M, RIII_CM_CLKSEL_MPU_VAL,            /* 133MHz ARM */
+                RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
+                RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_13_VAL,
+                MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
+                RATE_IN_242X},
+
+        /* PRCM-VII (boot-bypass) */
+        {S12M, S12M, S12M, RVII_CM_CLKSEL_MPU_VAL,              /* 12MHz ARM*/
+                RVII_CM_CLKSEL_DSP_VAL, RVII_CM_CLKSEL_GFX_VAL,
+                RVII_CM_CLKSEL1_CORE_VAL, MVII_CM_CLKSEL1_PLL_12_VAL,
+                MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_BYPASS,
+                RATE_IN_242X},
+
+        /* PRCM-VII (boot-bypass) */
+        {S13M, S13M, S13M, RVII_CM_CLKSEL_MPU_VAL,              /* 13MHz ARM */
+                RVII_CM_CLKSEL_DSP_VAL, RVII_CM_CLKSEL_GFX_VAL,
+                RVII_CM_CLKSEL1_CORE_VAL, MVII_CM_CLKSEL1_PLL_13_VAL,
+                MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_BYPASS,
+                RATE_IN_242X},
+
+        { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
+};
diff --git a/arch/arm/mach-omap2/opp2430_data.c b/arch/arm/mach-omap2/opp2430_data.c
new file mode 100644
index 000000000000..edb81672c844
--- /dev/null
+++ b/arch/arm/mach-omap2/opp2430_data.c
@@ -0,0 +1,133 @@
+/*
+ * opp2420_data.c - old-style "OPP" table for OMAP2420
+ *
+ * Copyright (C) 2005-2009 Texas Instruments, Inc.
+ * Copyright (C) 2004-2009 Nokia Corporation
+ *
+ * Richard Woodruff <r-woodruff2@ti.com>
+ *
+ * The OMAP2 processor can be run at several discrete 'PRCM configurations'.
+ * These configurations are characterized by voltage and speed for clocks.
+ * The device is only validated for certain combinations. One way to express
+ * these combinations is via the 'ratio's' which the clocks operate with
+ * respect to each other. These ratio sets are for a given voltage/DPLL
+ * setting. All configurations can be described by a DPLL setting and a ratio
+ * There are 3 ratio sets for the 2430 and X ratio sets for 2420.
+ *
+ * 2430 differs from 2420 in that there are no more phase synchronizers used.
+ * They both have a slightly different clock domain setup. 2420(iva1,dsp) vs
+ * 2430 (iva2.1, NOdsp, mdm)
+ *
+ * XXX Missing voltage data.
+ *
+ * THe format described in this file is deprecated.  Once a reasonable
+ * OPP API exists, the data in this file should be converted to use it.
+ *
+ * This is technically part of the OMAP2xxx clock code.
+ */
+
+#include "opp2xxx.h"
+#include "sdrc.h"
+#include "clock.h"
+
+/*-------------------------------------------------------------------------
+ * Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated.
+ * xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU,
+ * CM_CLKSEL_DSP, CM_CLKSEL_GFX, CM_CLKSEL1_CORE, CM_CLKSEL1_PLL,
+ * CM_CLKSEL2_PLL, CM_CLKSEL_MDM
+ *
+ * Filling in table based on H4 boards and 2430-SDPs variants available.
+ * There are quite a few more rates combinations which could be defined.
+ *
+ * When multiple values are defined the start up will try and choose the
+ * fastest one. If a 'fast' value is defined, then automatically, the /2
+ * one should be included as it can be used.    Generally having more that
+ * one fast set does not make sense, as static timings need to be changed
+ * to change the set.    The exception is the bypass setting which is
+ * availble for low power bypass.
+ *
+ * Note: This table needs to be sorted, fastest to slowest.
+ *-------------------------------------------------------------------------*/
+const struct prcm_config omap2430_rate_table[] = {
+        /* PRCM #4 - ratio2 (ES2.1) - FAST */
+        {S13M, S798M, S399M, R2_CM_CLKSEL_MPU_VAL,              /* 399MHz ARM */
+                R2_CM_CLKSEL_DSP_VAL, R2_CM_CLKSEL_GFX_VAL,
+                R2_CM_CLKSEL1_CORE_VAL, M4_CM_CLKSEL1_PLL_13_VAL,
+                MX_CLKSEL2_PLL_2x_VAL, R2_CM_CLKSEL_MDM_VAL,
+                SDRC_RFR_CTRL_133MHz,
+                RATE_IN_243X},
+
+        /* PRCM #2 - ratio1 (ES2) - FAST */
+        {S13M, S658M, S329M, R1_CM_CLKSEL_MPU_VAL,              /* 330MHz ARM */
+                R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
+                R1_CM_CLKSEL1_CORE_VAL, M2_CM_CLKSEL1_PLL_13_VAL,
+                MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL,
+                SDRC_RFR_CTRL_165MHz,
+                RATE_IN_243X},
+
+        /* PRCM #5a - ratio1 - FAST */
+        {S13M, S532M, S266M, R1_CM_CLKSEL_MPU_VAL,              /* 266MHz ARM */
+                R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
+                R1_CM_CLKSEL1_CORE_VAL, M5A_CM_CLKSEL1_PLL_13_VAL,
+                MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL,
+                SDRC_RFR_CTRL_133MHz,
+                RATE_IN_243X},
+
+        /* PRCM #5b - ratio1 - FAST */
+        {S13M, S400M, S200M, R1_CM_CLKSEL_MPU_VAL,              /* 200MHz ARM */
+                R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
+                R1_CM_CLKSEL1_CORE_VAL, M5B_CM_CLKSEL1_PLL_13_VAL,
+                MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL,
+                SDRC_RFR_CTRL_100MHz,
+                RATE_IN_243X},
+
+        /* PRCM #4 - ratio1 (ES2.1) - SLOW */
+        {S13M, S399M, S199M, R2_CM_CLKSEL_MPU_VAL,              /* 200MHz ARM */
+                R2_CM_CLKSEL_DSP_VAL, R2_CM_CLKSEL_GFX_VAL,
+                R2_CM_CLKSEL1_CORE_VAL, M4_CM_CLKSEL1_PLL_13_VAL,
+                MX_CLKSEL2_PLL_1x_VAL, R2_CM_CLKSEL_MDM_VAL,
+                SDRC_RFR_CTRL_133MHz,
+                RATE_IN_243X},
+
+        /* PRCM #2 - ratio1 (ES2) - SLOW */
+        {S13M, S329M, S164M, R1_CM_CLKSEL_MPU_VAL,              /* 165MHz ARM */
+                R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
+                R1_CM_CLKSEL1_CORE_VAL, M2_CM_CLKSEL1_PLL_13_VAL,
+                MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL,
+                SDRC_RFR_CTRL_165MHz,
+                RATE_IN_243X},
+
+        /* PRCM #5a - ratio1 - SLOW */
+        {S13M, S266M, S133M, R1_CM_CLKSEL_MPU_VAL,              /* 133MHz ARM */
+                R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
+                R1_CM_CLKSEL1_CORE_VAL, M5A_CM_CLKSEL1_PLL_13_VAL,
+                MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL,
+                SDRC_RFR_CTRL_133MHz,
+                RATE_IN_243X},
+
+        /* PRCM #5b - ratio1 - SLOW*/
+        {S13M, S200M, S100M, R1_CM_CLKSEL_MPU_VAL,              /* 100MHz ARM */
+                R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
+                R1_CM_CLKSEL1_CORE_VAL, M5B_CM_CLKSEL1_PLL_13_VAL,
+                MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL,
+                SDRC_RFR_CTRL_100MHz,
+                RATE_IN_243X},
+
+        /* PRCM-boot/bypass */
+        {S13M, S13M, S13M, RB_CM_CLKSEL_MPU_VAL,                /* 13Mhz */
+                RB_CM_CLKSEL_DSP_VAL, RB_CM_CLKSEL_GFX_VAL,
+                RB_CM_CLKSEL1_CORE_VAL, MB_CM_CLKSEL1_PLL_13_VAL,
+                MX_CLKSEL2_PLL_2x_VAL, RB_CM_CLKSEL_MDM_VAL,
+                SDRC_RFR_CTRL_BYPASS,
+                RATE_IN_243X},
+
+        /* PRCM-boot/bypass */
+        {S12M, S12M, S12M, RB_CM_CLKSEL_MPU_VAL,                /* 12Mhz */
+                RB_CM_CLKSEL_DSP_VAL, RB_CM_CLKSEL_GFX_VAL,
+                RB_CM_CLKSEL1_CORE_VAL, MB_CM_CLKSEL1_PLL_12_VAL,
+                MX_CLKSEL2_PLL_2x_VAL, RB_CM_CLKSEL_MDM_VAL,
+                SDRC_RFR_CTRL_BYPASS,
+                RATE_IN_243X},
+
+        { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
+};
diff --git a/arch/arm/mach-omap2/opp2xxx.h b/arch/arm/mach-omap2/opp2xxx.h
new file mode 100644
index 000000000000..ed6df04e2f29
--- /dev/null
+++ b/arch/arm/mach-omap2/opp2xxx.h
@@ -0,0 +1,424 @@
+/*
+ * opp2xxx.h - macros for old-style OMAP2xxx "OPP" definitions
+ *
+ * Copyright (C) 2005-2009 Texas Instruments, Inc.
+ * Copyright (C) 2004-2009 Nokia Corporation
+ *
+ * Richard Woodruff <r-woodruff2@ti.com>
+ *
+ * The OMAP2 processor can be run at several discrete 'PRCM configurations'.
+ * These configurations are characterized by voltage and speed for clocks.
+ * The device is only validated for certain combinations. One way to express
+ * these combinations is via the 'ratio's' which the clocks operate with
+ * respect to each other. These ratio sets are for a given voltage/DPLL
+ * setting. All configurations can be described by a DPLL setting and a ratio
+ * There are 3 ratio sets for the 2430 and X ratio sets for 2420.
+ *
+ * 2430 differs from 2420 in that there are no more phase synchronizers used.
+ * They both have a slightly different clock domain setup. 2420(iva1,dsp) vs
+ * 2430 (iva2.1, NOdsp, mdm)
+ *
+ * XXX Missing voltage data.
+ *
+ * THe format described in this file is deprecated.  Once a reasonable
+ * OPP API exists, the data in this file should be converted to use it.
+ *
+ * This is technically part of the OMAP2xxx clock code.
+ */
+
+#ifndef __ARCH_ARM_MACH_OMAP2_OPP2XXX_H
+#define __ARCH_ARM_MACH_OMAP2_OPP2XXX_H
+
+/**
+ * struct prcm_config - define clock rates on a per-OPP basis (24xx)
+ *
+ * Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated.
+ * xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU,CM_CLKSEL_DSP
+ * CM_CLKSEL_GFX, CM_CLKSEL1_CORE, CM_CLKSEL1_PLL CM_CLKSEL2_PLL, CM_CLKSEL_MDM
+ *
+ * This is deprecated.  As soon as we have a decent OPP API, we should
+ * move all this stuff to it.
+ */
+struct prcm_config {
+        unsigned long xtal_speed;       /* crystal rate */
+        unsigned long dpll_speed;       /* dpll: out*xtal*M/(N-1)table_recalc */
+        unsigned long mpu_speed;        /* speed of MPU */
+        unsigned long cm_clksel_mpu;    /* mpu divider */
+        unsigned long cm_clksel_dsp;    /* dsp+iva1 div(2420), iva2.1(2430) */
+        unsigned long cm_clksel_gfx;    /* gfx dividers */
+        unsigned long cm_clksel1_core;  /* major subsystem dividers */
+        unsigned long cm_clksel1_pll;   /* m,n */
+        unsigned long cm_clksel2_pll;   /* dpllx1 or x2 out */
+        unsigned long cm_clksel_mdm;    /* modem dividers 2430 only */
+        unsigned long base_sdrc_rfr;    /* base refresh timing for a set */
+        unsigned char flags;
+};
+
+
+/* Core fields for cm_clksel, not ratio governed */
+#define RX_CLKSEL_DSS1                  (0x10 << 8)
+#define RX_CLKSEL_DSS2                  (0x0 << 13)
+#define RX_CLKSEL_SSI                   (0x5 << 20)
+
+/*-------------------------------------------------------------------------
+ * Voltage/DPLL ratios
+ *-------------------------------------------------------------------------*/
+
+/* 2430 Ratio's, 2430-Ratio Config 1 */
+#define R1_CLKSEL_L3                    (4 << 0)
+#define R1_CLKSEL_L4                    (2 << 5)
+#define R1_CLKSEL_USB                   (4 << 25)
+#define R1_CM_CLKSEL1_CORE_VAL          (R1_CLKSEL_USB | RX_CLKSEL_SSI | \
+                                         RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
+                                         R1_CLKSEL_L4 | R1_CLKSEL_L3)
+#define R1_CLKSEL_MPU                   (2 << 0)
+#define R1_CM_CLKSEL_MPU_VAL            R1_CLKSEL_MPU
+#define R1_CLKSEL_DSP                   (2 << 0)
+#define R1_CLKSEL_DSP_IF                (2 << 5)
+#define R1_CM_CLKSEL_DSP_VAL            (R1_CLKSEL_DSP | R1_CLKSEL_DSP_IF)
+#define R1_CLKSEL_GFX                   (2 << 0)
+#define R1_CM_CLKSEL_GFX_VAL            R1_CLKSEL_GFX
+#define R1_CLKSEL_MDM                   (4 << 0)
+#define R1_CM_CLKSEL_MDM_VAL            R1_CLKSEL_MDM
+
+/* 2430-Ratio Config 2 */
+#define R2_CLKSEL_L3                    (6 << 0)
+#define R2_CLKSEL_L4                    (2 << 5)
+#define R2_CLKSEL_USB                   (2 << 25)
+#define R2_CM_CLKSEL1_CORE_VAL          (R2_CLKSEL_USB | RX_CLKSEL_SSI | \
+                                         RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
+                                         R2_CLKSEL_L4 | R2_CLKSEL_L3)
+#define R2_CLKSEL_MPU                   (2 << 0)
+#define R2_CM_CLKSEL_MPU_VAL            R2_CLKSEL_MPU
+#define R2_CLKSEL_DSP                   (2 << 0)
+#define R2_CLKSEL_DSP_IF                (3 << 5)
+#define R2_CM_CLKSEL_DSP_VAL            (R2_CLKSEL_DSP | R2_CLKSEL_DSP_IF)
+#define R2_CLKSEL_GFX                   (2 << 0)
+#define R2_CM_CLKSEL_GFX_VAL            R2_CLKSEL_GFX
+#define R2_CLKSEL_MDM                   (6 << 0)
+#define R2_CM_CLKSEL_MDM_VAL            R2_CLKSEL_MDM
+
+/* 2430-Ratio Bootm (BYPASS) */
+#define RB_CLKSEL_L3                    (1 << 0)
+#define RB_CLKSEL_L4                    (1 << 5)
+#define RB_CLKSEL_USB                   (1 << 25)
+#define RB_CM_CLKSEL1_CORE_VAL          (RB_CLKSEL_USB | RX_CLKSEL_SSI | \
+                                         RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
+                                         RB_CLKSEL_L4 | RB_CLKSEL_L3)
+#define RB_CLKSEL_MPU                   (1 << 0)
+#define RB_CM_CLKSEL_MPU_VAL            RB_CLKSEL_MPU
+#define RB_CLKSEL_DSP                   (1 << 0)
+#define RB_CLKSEL_DSP_IF                (1 << 5)
+#define RB_CM_CLKSEL_DSP_VAL            (RB_CLKSEL_DSP | RB_CLKSEL_DSP_IF)
+#define RB_CLKSEL_GFX                   (1 << 0)
+#define RB_CM_CLKSEL_GFX_VAL            RB_CLKSEL_GFX
+#define RB_CLKSEL_MDM                   (1 << 0)
+#define RB_CM_CLKSEL_MDM_VAL            RB_CLKSEL_MDM
+
+/* 2420 Ratio Equivalents */
+#define RXX_CLKSEL_VLYNQ                (0x12 << 15)
+#define RXX_CLKSEL_SSI                  (0x8 << 20)
+
+/* 2420-PRCM III 532MHz core */
+#define RIII_CLKSEL_L3                  (4 << 0)        /* 133MHz */
+#define RIII_CLKSEL_L4                  (2 << 5)        /* 66.5MHz */
+#define RIII_CLKSEL_USB                 (4 << 25)       /* 33.25MHz */
+#define RIII_CM_CLKSEL1_CORE_VAL        (RIII_CLKSEL_USB | RXX_CLKSEL_SSI | \
+                                         RXX_CLKSEL_VLYNQ | RX_CLKSEL_DSS2 | \
+                                         RX_CLKSEL_DSS1 | RIII_CLKSEL_L4 | \
+                                         RIII_CLKSEL_L3)
+#define RIII_CLKSEL_MPU                 (2 << 0)        /* 266MHz */
+#define RIII_CM_CLKSEL_MPU_VAL          RIII_CLKSEL_MPU
+#define RIII_CLKSEL_DSP                 (3 << 0)        /* c5x - 177.3MHz */
+#define RIII_CLKSEL_DSP_IF              (2 << 5)        /* c5x - 88.67MHz */
+#define RIII_SYNC_DSP                   (1 << 7)        /* Enable sync */
+#define RIII_CLKSEL_IVA                 (6 << 8)        /* iva1 - 88.67MHz */
+#define RIII_SYNC_IVA                   (1 << 13)       /* Enable sync */
+#define RIII_CM_CLKSEL_DSP_VAL          (RIII_SYNC_IVA | RIII_CLKSEL_IVA | \
+                                         RIII_SYNC_DSP | RIII_CLKSEL_DSP_IF | \
+                                         RIII_CLKSEL_DSP)
+#define RIII_CLKSEL_GFX                 (2 << 0)        /* 66.5MHz */
+#define RIII_CM_CLKSEL_GFX_VAL          RIII_CLKSEL_GFX
+
+/* 2420-PRCM II 600MHz core */
+#define RII_CLKSEL_L3                   (6 << 0)        /* 100MHz */
+#define RII_CLKSEL_L4                   (2 << 5)        /* 50MHz */
+#define RII_CLKSEL_USB                  (2 << 25)       /* 50MHz */
+#define RII_CM_CLKSEL1_CORE_VAL         (RII_CLKSEL_USB | RXX_CLKSEL_SSI | \
+                                         RXX_CLKSEL_VLYNQ | RX_CLKSEL_DSS2 | \
+                                         RX_CLKSEL_DSS1 | RII_CLKSEL_L4 | \
+                                         RII_CLKSEL_L3)
+#define RII_CLKSEL_MPU                  (2 << 0)        /* 300MHz */
+#define RII_CM_CLKSEL_MPU_VAL           RII_CLKSEL_MPU
+#define RII_CLKSEL_DSP                  (3 << 0)        /* c5x - 200MHz */
+#define RII_CLKSEL_DSP_IF               (2 << 5)        /* c5x - 100MHz */
+#define RII_SYNC_DSP                    (0 << 7)        /* Bypass sync */
+#define RII_CLKSEL_IVA                  (3 << 8)        /* iva1 - 200MHz */
+#define RII_SYNC_IVA                    (0 << 13)       /* Bypass sync */
+#define RII_CM_CLKSEL_DSP_VAL           (RII_SYNC_IVA | RII_CLKSEL_IVA | \
+                                         RII_SYNC_DSP | RII_CLKSEL_DSP_IF | \
+                                         RII_CLKSEL_DSP)
+#define RII_CLKSEL_GFX                  (2 << 0)        /* 50MHz */
+#define RII_CM_CLKSEL_GFX_VAL           RII_CLKSEL_GFX
+
+/* 2420-PRCM I 660MHz core */
+#define RI_CLKSEL_L3                    (4 << 0)        /* 165MHz */
+#define RI_CLKSEL_L4                    (2 << 5)        /* 82.5MHz */
+#define RI_CLKSEL_USB                   (4 << 25)       /* 41.25MHz */
+#define RI_CM_CLKSEL1_CORE_VAL          (RI_CLKSEL_USB |                \
+                                         RXX_CLKSEL_SSI | RXX_CLKSEL_VLYNQ | \
+                                         RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
+                                         RI_CLKSEL_L4 | RI_CLKSEL_L3)
+#define RI_CLKSEL_MPU                   (2 << 0)        /* 330MHz */
+#define RI_CM_CLKSEL_MPU_VAL            RI_CLKSEL_MPU
+#define RI_CLKSEL_DSP                   (3 << 0)        /* c5x - 220MHz */
+#define RI_CLKSEL_DSP_IF                (2 << 5)        /* c5x - 110MHz */
+#define RI_SYNC_DSP                     (1 << 7)        /* Activate sync */
+#define RI_CLKSEL_IVA                   (4 << 8)        /* iva1 - 165MHz */
+#define RI_SYNC_IVA                     (0 << 13)       /* Bypass sync */
+#define RI_CM_CLKSEL_DSP_VAL            (RI_SYNC_IVA | RI_CLKSEL_IVA |  \
+                                         RI_SYNC_DSP | RI_CLKSEL_DSP_IF | \
+                                         RI_CLKSEL_DSP)
+#define RI_CLKSEL_GFX                   (1 << 0)        /* 165MHz */
+#define RI_CM_CLKSEL_GFX_VAL            RI_CLKSEL_GFX
+
+/* 2420-PRCM VII (boot) */
+#define RVII_CLKSEL_L3                  (1 << 0)
+#define RVII_CLKSEL_L4                  (1 << 5)
+#define RVII_CLKSEL_DSS1                (1 << 8)
+#define RVII_CLKSEL_DSS2                (0 << 13)
+#define RVII_CLKSEL_VLYNQ               (1 << 15)
+#define RVII_CLKSEL_SSI                 (1 << 20)
+#define RVII_CLKSEL_USB                 (1 << 25)
+
+#define RVII_CM_CLKSEL1_CORE_VAL        (RVII_CLKSEL_USB | RVII_CLKSEL_SSI | \
+                                         RVII_CLKSEL_VLYNQ | \
+                                         RVII_CLKSEL_DSS2 | RVII_CLKSEL_DSS1 | \
+                                         RVII_CLKSEL_L4 | RVII_CLKSEL_L3)
+
+#define RVII_CLKSEL_MPU                 (1 << 0) /* all divide by 1 */
+#define RVII_CM_CLKSEL_MPU_VAL          RVII_CLKSEL_MPU
+
+#define RVII_CLKSEL_DSP                 (1 << 0)
+#define RVII_CLKSEL_DSP_IF              (1 << 5)
+#define RVII_SYNC_DSP                   (0 << 7)
+#define RVII_CLKSEL_IVA                 (1 << 8)
+#define RVII_SYNC_IVA                   (0 << 13)
+#define RVII_CM_CLKSEL_DSP_VAL          (RVII_SYNC_IVA | RVII_CLKSEL_IVA | \
+                                         RVII_SYNC_DSP | RVII_CLKSEL_DSP_IF | \
+                                         RVII_CLKSEL_DSP)
+
+#define RVII_CLKSEL_GFX                 (1 << 0)
+#define RVII_CM_CLKSEL_GFX_VAL          RVII_CLKSEL_GFX
+
+/*-------------------------------------------------------------------------
+ * 2430 Target modes: Along with each configuration the CPU has several
+ * modes which goes along with them. Modes mainly are the addition of
+ * describe DPLL combinations to go along with a ratio.
+ *-------------------------------------------------------------------------*/
+
+/* Hardware governed */
+#define MX_48M_SRC                      (0 << 3)
+#define MX_54M_SRC                      (0 << 5)
+#define MX_APLLS_CLIKIN_12              (3 << 23)
+#define MX_APLLS_CLIKIN_13              (2 << 23)
+#define MX_APLLS_CLIKIN_19_2            (0 << 23)
+
+/*
+ * 2430 - standalone, 2*ref*M/(n+1), M/N is for exactness not relock speed
+ * #5a  (ratio1) baseport-target, target DPLL = 266*2 = 532MHz
+ */
+#define M5A_DPLL_MULT_12                (133 << 12)
+#define M5A_DPLL_DIV_12                 (5 << 8)
+#define M5A_CM_CLKSEL1_PLL_12_VAL       (MX_48M_SRC | MX_54M_SRC | \
+                                         M5A_DPLL_DIV_12 | M5A_DPLL_MULT_12 | \
+                                         MX_APLLS_CLIKIN_12)
+#define M5A_DPLL_MULT_13                (61 << 12)
+#define M5A_DPLL_DIV_13                 (2 << 8)
+#define M5A_CM_CLKSEL1_PLL_13_VAL       (MX_48M_SRC | MX_54M_SRC | \
+                                         M5A_DPLL_DIV_13 | M5A_DPLL_MULT_13 | \
+                                         MX_APLLS_CLIKIN_13)
+#define M5A_DPLL_MULT_19                (55 << 12)
+#define M5A_DPLL_DIV_19                 (3 << 8)
+#define M5A_CM_CLKSEL1_PLL_19_VAL       (MX_48M_SRC | MX_54M_SRC | \
+                                         M5A_DPLL_DIV_19 | M5A_DPLL_MULT_19 | \
+                                         MX_APLLS_CLIKIN_19_2)
+/* #5b  (ratio1) target DPLL = 200*2 = 400MHz */
+#define M5B_DPLL_MULT_12                (50 << 12)
+#define M5B_DPLL_DIV_12                 (2 << 8)
+#define M5B_CM_CLKSEL1_PLL_12_VAL       (MX_48M_SRC | MX_54M_SRC | \
+                                         M5B_DPLL_DIV_12 | M5B_DPLL_MULT_12 | \
+                                         MX_APLLS_CLIKIN_12)
+#define M5B_DPLL_MULT_13                (200 << 12)
+#define M5B_DPLL_DIV_13                 (12 << 8)
+
+#define M5B_CM_CLKSEL1_PLL_13_VAL       (MX_48M_SRC | MX_54M_SRC | \
+                                         M5B_DPLL_DIV_13 | M5B_DPLL_MULT_13 | \
+                                         MX_APLLS_CLIKIN_13)
+#define M5B_DPLL_MULT_19                (125 << 12)
+#define M5B_DPLL_DIV_19                 (31 << 8)
+#define M5B_CM_CLKSEL1_PLL_19_VAL       (MX_48M_SRC | MX_54M_SRC | \
+                                         M5B_DPLL_DIV_19 | M5B_DPLL_MULT_19 | \
+                                         MX_APLLS_CLIKIN_19_2)
+/*
+ * #4   (ratio2), DPLL = 399*2 = 798MHz, L3=133MHz
+ */
+#define M4_DPLL_MULT_12                 (133 << 12)
+#define M4_DPLL_DIV_12                  (3 << 8)
+#define M4_CM_CLKSEL1_PLL_12_VAL        (MX_48M_SRC | MX_54M_SRC | \
+                                         M4_DPLL_DIV_12 | M4_DPLL_MULT_12 | \
+                                         MX_APLLS_CLIKIN_12)
+
+#define M4_DPLL_MULT_13                 (399 << 12)
+#define M4_DPLL_DIV_13                  (12 << 8)
+#define M4_CM_CLKSEL1_PLL_13_VAL        (MX_48M_SRC | MX_54M_SRC | \
+                                         M4_DPLL_DIV_13 | M4_DPLL_MULT_13 | \
+                                         MX_APLLS_CLIKIN_13)
+
+#define M4_DPLL_MULT_19                 (145 << 12)
+#define M4_DPLL_DIV_19                  (6 << 8)
+#define M4_CM_CLKSEL1_PLL_19_VAL        (MX_48M_SRC | MX_54M_SRC | \
+                                         M4_DPLL_DIV_19 | M4_DPLL_MULT_19 | \
+                                         MX_APLLS_CLIKIN_19_2)
+
+/*
+ * #3   (ratio2) baseport-target, target DPLL = 330*2 = 660MHz
+ */
+#define M3_DPLL_MULT_12                 (55 << 12)
+#define M3_DPLL_DIV_12                  (1 << 8)
+#define M3_CM_CLKSEL1_PLL_12_VAL        (MX_48M_SRC | MX_54M_SRC | \
+                                         M3_DPLL_DIV_12 | M3_DPLL_MULT_12 | \
+                                         MX_APLLS_CLIKIN_12)
+#define M3_DPLL_MULT_13                 (76 << 12)
+#define M3_DPLL_DIV_13                  (2 << 8)
+#define M3_CM_CLKSEL1_PLL_13_VAL        (MX_48M_SRC | MX_54M_SRC | \
+                                         M3_DPLL_DIV_13 | M3_DPLL_MULT_13 | \
+                                         MX_APLLS_CLIKIN_13)
+#define M3_DPLL_MULT_19                 (17 << 12)
+#define M3_DPLL_DIV_19                  (0 << 8)
+#define M3_CM_CLKSEL1_PLL_19_VAL        (MX_48M_SRC | MX_54M_SRC | \
+                                         M3_DPLL_DIV_19 | M3_DPLL_MULT_19 | \
+                                         MX_APLLS_CLIKIN_19_2)
+
+/*
+ * #2   (ratio1) DPLL = 330*2 = 660MHz, L3=165MHz
+ */
+#define M2_DPLL_MULT_12                 (55 << 12)
+#define M2_DPLL_DIV_12                  (1 << 8)
+#define M2_CM_CLKSEL1_PLL_12_VAL        (MX_48M_SRC | MX_54M_SRC | \
+                                         M2_DPLL_DIV_12 | M2_DPLL_MULT_12 | \
+                                         MX_APLLS_CLIKIN_12)
+
+/* Speed changes - Used 658.7MHz instead of 660MHz for LP-Refresh M=76 N=2,
+ * relock time issue */
+/* Core frequency changed from 330/165 to 329/164 MHz*/
+#define M2_DPLL_MULT_13                 (76 << 12)
+#define M2_DPLL_DIV_13                  (2 << 8)
+#define M2_CM_CLKSEL1_PLL_13_VAL        (MX_48M_SRC | MX_54M_SRC | \
+                                         M2_DPLL_DIV_13 | M2_DPLL_MULT_13 | \
+                                         MX_APLLS_CLIKIN_13)
+
+#define M2_DPLL_MULT_19                 (17 << 12)
+#define M2_DPLL_DIV_19                  (0 << 8)
+#define M2_CM_CLKSEL1_PLL_19_VAL        (MX_48M_SRC | MX_54M_SRC | \
+                                         M2_DPLL_DIV_19 | M2_DPLL_MULT_19 | \
+                                         MX_APLLS_CLIKIN_19_2)
+
+/* boot (boot) */
+#define MB_DPLL_MULT                    (1 << 12)
+#define MB_DPLL_DIV                     (0 << 8)
+#define MB_CM_CLKSEL1_PLL_12_VAL        (MX_48M_SRC | MX_54M_SRC | \
+                                         MB_DPLL_DIV | MB_DPLL_MULT | \
+                                         MX_APLLS_CLIKIN_12)
+
+#define MB_CM_CLKSEL1_PLL_13_VAL        (MX_48M_SRC | MX_54M_SRC | \
+                                         MB_DPLL_DIV | MB_DPLL_MULT | \
+                                         MX_APLLS_CLIKIN_13)
+
+#define MB_CM_CLKSEL1_PLL_19_VAL        (MX_48M_SRC | MX_54M_SRC | \
+                                         MB_DPLL_DIV | MB_DPLL_MULT | \
+                                         MX_APLLS_CLIKIN_19)
+
+/*
+ * 2430 - chassis (sedna)
+ * 165 (ratio1) same as above #2
+ * 150 (ratio1)
+ * 133 (ratio2) same as above #4
+ * 110 (ratio2) same as above #3
+ * 104 (ratio2)
+ * boot (boot)
+ */
+
+/* PRCM I target DPLL = 2*330MHz = 660MHz */
+#define MI_DPLL_MULT_12                 (55 << 12)
+#define MI_DPLL_DIV_12                  (1 << 8)
+#define MI_CM_CLKSEL1_PLL_12_VAL        (MX_48M_SRC | MX_54M_SRC | \
+                                         MI_DPLL_DIV_12 | MI_DPLL_MULT_12 | \
+                                         MX_APLLS_CLIKIN_12)
+
+/*
+ * 2420 Equivalent - mode registers
+ * PRCM II , target DPLL = 2*300MHz = 600MHz
+ */
+#define MII_DPLL_MULT_12                (50 << 12)
+#define MII_DPLL_DIV_12                 (1 << 8)
+#define MII_CM_CLKSEL1_PLL_12_VAL       (MX_48M_SRC | MX_54M_SRC |      \
+                                         MII_DPLL_DIV_12 | MII_DPLL_MULT_12 | \
+                                         MX_APLLS_CLIKIN_12)
+#define MII_DPLL_MULT_13                (300 << 12)
+#define MII_DPLL_DIV_13                 (12 << 8)
+#define MII_CM_CLKSEL1_PLL_13_VAL       (MX_48M_SRC | MX_54M_SRC |      \
+                                         MII_DPLL_DIV_13 | MII_DPLL_MULT_13 | \
+                                         MX_APLLS_CLIKIN_13)
+
+/* PRCM III target DPLL = 2*266 = 532MHz*/
+#define MIII_DPLL_MULT_12               (133 << 12)
+#define MIII_DPLL_DIV_12                (5 << 8)
+#define MIII_CM_CLKSEL1_PLL_12_VAL      (MX_48M_SRC | MX_54M_SRC |      \
+                                         MIII_DPLL_DIV_12 | \
+                                         MIII_DPLL_MULT_12 | MX_APLLS_CLIKIN_12)
+#define MIII_DPLL_MULT_13               (266 << 12)
+#define MIII_DPLL_DIV_13                (12 << 8)
+#define MIII_CM_CLKSEL1_PLL_13_VAL      (MX_48M_SRC | MX_54M_SRC |      \
+                                         MIII_DPLL_DIV_13 | \
+                                         MIII_DPLL_MULT_13 | MX_APLLS_CLIKIN_13)
+
+/* PRCM VII (boot bypass) */
+#define MVII_CM_CLKSEL1_PLL_12_VAL      MB_CM_CLKSEL1_PLL_12_VAL
+#define MVII_CM_CLKSEL1_PLL_13_VAL      MB_CM_CLKSEL1_PLL_13_VAL
+
+/* High and low operation value */
+#define MX_CLKSEL2_PLL_2x_VAL           (2 << 0)
+#define MX_CLKSEL2_PLL_1x_VAL           (1 << 0)
+
+/* MPU speed defines */
+#define S12M    12000000
+#define S13M    13000000
+#define S19M    19200000
+#define S26M    26000000
+#define S100M   100000000
+#define S133M   133000000
+#define S150M   150000000
+#define S164M   164000000
+#define S165M   165000000
+#define S199M   199000000
+#define S200M   200000000
+#define S266M   266000000
+#define S300M   300000000
+#define S329M   329000000
+#define S330M   330000000
+#define S399M   399000000
+#define S400M   400000000
+#define S532M   532000000
+#define S600M   600000000
+#define S658M   658000000
+#define S660M   660000000
+#define S798M   798000000
+
+
+extern const struct prcm_config omap2420_rate_table[];
+extern const struct prcm_config omap2430_rate_table[];
+extern const struct prcm_config *rate_table;
+extern const struct prcm_config *curr_prcm_set;
+
+#endif
diff --git a/arch/arm/mach-omap2/pm-debug.c b/arch/arm/mach-omap2/pm-debug.c
index 8baa30d2acfb..860b755d2220 100644
--- a/arch/arm/mach-omap2/pm-debug.c
+++ b/arch/arm/mach-omap2/pm-debug.c
@@ -326,7 +326,7 @@ int pm_dbg_regset_save(int reg_set)
         return 0;
 }
 
-static const char pwrdm_state_names[][4] = {
+static const char pwrdm_state_names[][PWRDM_MAX_PWRSTS] = {
         "OFF",
         "RET",
         "INA",
@@ -381,7 +381,7 @@ static int pwrdm_dbg_show_counter(struct powerdomain *pwrdm, void *user)
 
         seq_printf(s, "%s (%s)", pwrdm->name,
                         pwrdm_state_names[pwrdm->state]);
-        for (i = 0; i < 4; i++)
+        for (i = 0; i < PWRDM_MAX_PWRSTS; i++)
                 seq_printf(s, ",%s:%d", pwrdm_state_names[i],
                         pwrdm->state_counter[i]);
 
diff --git a/arch/arm/mach-omap2/powerdomain.c b/arch/arm/mach-omap2/powerdomain.c
index b6990e377783..26b3f3ee82a3 100644
--- a/arch/arm/mach-omap2/powerdomain.c
+++ b/arch/arm/mach-omap2/powerdomain.c
@@ -10,9 +10,7 @@
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
  */
-#ifdef CONFIG_OMAP_DEBUG_POWERDOMAIN
-# define DEBUG
-#endif
+#undef DEBUG
 
 #include <linux/kernel.h>
 #include <linux/module.h>
@@ -160,7 +158,7 @@ static __init void _pwrdm_setup(struct powerdomain *pwrdm)
 {
         int i;
 
-        for (i = 0; i < 4; i++)
+        for (i = 0; i < PWRDM_MAX_PWRSTS; i++)
                 pwrdm->state_counter[i] = 0;
 
         pwrdm_wait_transition(pwrdm);
@@ -480,7 +478,7 @@ int pwrdm_add_wkdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2)
         if (IS_ERR(p)) {
                 pr_debug("powerdomain: hardware cannot set/clear wake up of "
                          "%s when %s wakes up\n", pwrdm1->name, pwrdm2->name);
-                return IS_ERR(p);
+                return PTR_ERR(p);
         }
 
         pr_debug("powerdomain: hardware will wake up %s when %s wakes up\n",
@@ -513,7 +511,7 @@ int pwrdm_del_wkdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2)
         if (IS_ERR(p)) {
                 pr_debug("powerdomain: hardware cannot set/clear wake up of "
                          "%s when %s wakes up\n", pwrdm1->name, pwrdm2->name);
-                return IS_ERR(p);
+                return PTR_ERR(p);
         }
 
         pr_debug("powerdomain: hardware will no longer wake up %s after %s "
@@ -550,7 +548,7 @@ int pwrdm_read_wkdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2)
         if (IS_ERR(p)) {
                 pr_debug("powerdomain: hardware cannot set/clear wake up of "
                          "%s when %s wakes up\n", pwrdm1->name, pwrdm2->name);
-                return IS_ERR(p);
+                return PTR_ERR(p);
         }
 
         return prm_read_mod_bits_shift(pwrdm1->prcm_offs, PM_WKDEP,
@@ -573,10 +571,10 @@ int pwrdm_add_sleepdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2)
 {
         struct powerdomain *p;
 
-        if (!pwrdm1)
+        if (!cpu_is_omap34xx())
                 return -EINVAL;
 
-        if (!cpu_is_omap34xx())
+        if (!pwrdm1)
                 return -EINVAL;
 
         p = _pwrdm_deps_lookup(pwrdm2, pwrdm1->sleepdep_srcs);
@@ -584,7 +582,7 @@ int pwrdm_add_sleepdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2)
                 pr_debug("powerdomain: hardware cannot set/clear sleep "
                          "dependency affecting %s from %s\n", pwrdm1->name,
                          pwrdm2->name);
-                return IS_ERR(p);
+                return PTR_ERR(p);
         }
 
         pr_debug("powerdomain: will prevent %s from sleeping if %s is active\n",
@@ -612,10 +610,10 @@ int pwrdm_del_sleepdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2)
 {
         struct powerdomain *p;
 
-        if (!pwrdm1)
+        if (!cpu_is_omap34xx())
                 return -EINVAL;
 
-        if (!cpu_is_omap34xx())
+        if (!pwrdm1)
                 return -EINVAL;
 
         p = _pwrdm_deps_lookup(pwrdm2, pwrdm1->sleepdep_srcs);
@@ -623,7 +621,7 @@ int pwrdm_del_sleepdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2)
                 pr_debug("powerdomain: hardware cannot set/clear sleep "
                          "dependency affecting %s from %s\n", pwrdm1->name,
                          pwrdm2->name);
-                return IS_ERR(p);
+                return PTR_ERR(p);
         }
 
         pr_debug("powerdomain: will no longer prevent %s from sleeping if "
@@ -655,10 +653,10 @@ int pwrdm_read_sleepdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2)
 {
         struct powerdomain *p;
 
-        if (!pwrdm1)
+        if (!cpu_is_omap34xx())
                 return -EINVAL;
 
-        if (!cpu_is_omap34xx())
+        if (!pwrdm1)
                 return -EINVAL;
 
         p = _pwrdm_deps_lookup(pwrdm2, pwrdm1->sleepdep_srcs);
@@ -666,7 +664,7 @@ int pwrdm_read_sleepdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2)
                 pr_debug("powerdomain: hardware cannot set/clear sleep "
                          "dependency affecting %s from %s\n", pwrdm1->name,
                          pwrdm2->name);
-                return IS_ERR(p);
+                return PTR_ERR(p);
         }
 
         return prm_read_mod_bits_shift(pwrdm1->prcm_offs, OMAP3430_CM_SLEEPDEP,
@@ -985,6 +983,9 @@ int pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank)
         if (pwrdm->banks < (bank + 1))
                 return -EEXIST;
 
+        if (pwrdm->flags & PWRDM_HAS_MPU_QUIRK)
+                bank = 1;
+
         /*
          * The register bit names below may not correspond to the
          * actual names of the bits in each powerdomain's register,
@@ -1032,6 +1033,9 @@ int pwrdm_read_prev_mem_pwrst(struct powerdomain *pwrdm, u8 bank)
         if (pwrdm->banks < (bank + 1))
                 return -EEXIST;
 
+        if (pwrdm->flags & PWRDM_HAS_MPU_QUIRK)
+                bank = 1;
+
         /*
          * The register bit names below may not correspond to the
          * actual names of the bits in each powerdomain's register,
diff --git a/arch/arm/mach-omap2/powerdomains34xx.h b/arch/arm/mach-omap2/powerdomains34xx.h
index fd09b0827df0..588f7e07d0ea 100644
--- a/arch/arm/mach-omap2/powerdomains34xx.h
+++ b/arch/arm/mach-omap2/powerdomains34xx.h
@@ -190,6 +190,7 @@ static struct powerdomain mpu_34xx_pwrdm = {
         .wkdep_srcs       = mpu_34xx_wkdeps,
         .pwrsts           = PWRSTS_OFF_RET_ON,
         .pwrsts_logic_ret = PWRSTS_OFF_RET,
+        .flags            = PWRDM_HAS_MPU_QUIRK,
         .banks            = 1,
         .pwrsts_mem_ret   = {
                 [0] = PWRSTS_OFF_RET,
diff --git a/arch/arm/mach-omap2/prcm-common.h b/arch/arm/mach-omap2/prcm-common.h
index cb1ae84e0925..61ac2a418bd0 100644
--- a/arch/arm/mach-omap2/prcm-common.h
+++ b/arch/arm/mach-omap2/prcm-common.h
@@ -4,10 +4,12 @@
 /*
  * OMAP2/3 PRCM base and module definitions
  *
- * Copyright (C) 2007-2008 Texas Instruments, Inc.
- * Copyright (C) 2007-2008 Nokia Corporation
+ * Copyright (C) 2007-2009 Texas Instruments, Inc.
+ * Copyright (C) 2007-2009 Nokia Corporation
  *
  * Written by Paul Walmsley
+ * OMAP4 defines in this file are automatically generated from the OMAP hardware
+ * databases.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -49,6 +51,73 @@
 #define OMAP3430_NEON_MOD                               0xb00
 #define OMAP3430ES2_USBHOST_MOD                         0xc00
 
+#define BITS(n_bit)     \
+        (((1 << n_bit) - 1) | (1 << n_bit))
+
+#define BITFIELD(l_bit, u_bit)  \
+        (BITS(u_bit) & ~((BITS(l_bit)) >> 1))
+
+/* OMAP44XX specific module offsets */
+
+/* CM1 instances */
+
+#define OMAP4430_CM1_OCP_SOCKET_MOD     0x0000
+#define OMAP4430_CM1_CKGEN_MOD          0x0100
+#define OMAP4430_CM1_MPU_MOD            0x0300
+#define OMAP4430_CM1_TESLA_MOD          0x0400
+#define OMAP4430_CM1_ABE_MOD            0x0500
+#define OMAP4430_CM1_RESTORE_MOD        0x0e00
+#define OMAP4430_CM1_INSTR_MOD          0x0f00
+
+/* CM2 instances */
+
+#define OMAP4430_CM2_OCP_SOCKET_MOD     0x0000
+#define OMAP4430_CM2_CKGEN_MOD          0x0100
+#define OMAP4430_CM2_ALWAYS_ON_MOD      0x0600
+#define OMAP4430_CM2_CORE_MOD           0x0700
+#define OMAP4430_CM2_IVAHD_MOD          0x0f00
+#define OMAP4430_CM2_CAM_MOD            0x1000
+#define OMAP4430_CM2_DSS_MOD            0x1100
+#define OMAP4430_CM2_GFX_MOD            0x1200
+#define OMAP4430_CM2_L3INIT_MOD         0x1300
+#define OMAP4430_CM2_L4PER_MOD          0x1400
+#define OMAP4430_CM2_CEFUSE_MOD         0x1600
+#define OMAP4430_CM2_RESTORE_MOD        0x1e00
+#define OMAP4430_CM2_INSTR_MOD          0x1f00
+
+/* PRM instances */
+
+#define OMAP4430_PRM_OCP_SOCKET_MOD     0x0000
+#define OMAP4430_PRM_CKGEN_MOD          0x0100
+#define OMAP4430_PRM_MPU_MOD            0x0300
+#define OMAP4430_PRM_TESLA_MOD          0x0400
+#define OMAP4430_PRM_ABE_MOD            0x0500
+#define OMAP4430_PRM_ALWAYS_ON_MOD      0x0600
+#define OMAP4430_PRM_CORE_MOD           0x0700
+#define OMAP4430_PRM_IVAHD_MOD          0x0f00
+#define OMAP4430_PRM_CAM_MOD            0x1000
+#define OMAP4430_PRM_DSS_MOD            0x1100
+#define OMAP4430_PRM_GFX_MOD            0x1200
+#define OMAP4430_PRM_L3INIT_MOD         0x1300
+#define OMAP4430_PRM_L4PER_MOD          0x1400
+#define OMAP4430_PRM_CEFUSE_MOD         0x1600
+#define OMAP4430_PRM_WKUP_MOD           0x1700
+#define OMAP4430_PRM_WKUP_CM_MOD        0x1800
+#define OMAP4430_PRM_EMU_MOD            0x1900
+#define OMAP4430_PRM_EMU_CM_MOD         0x1a00
+#define OMAP4430_PRM_DEVICE_MOD         0x1b00
+#define OMAP4430_PRM_INSTR_MOD          0x1f00
+
+/* SCRM instances */
+
+#define OMAP4430_SCRM_SCRM_MOD  0x0000
+
+/* CHIRONSS instances */
+
+#define OMAP4430_CHIRONSS_CHIRONSS_OCP_SOCKET_PRCM_MOD  0x0000
+#define OMAP4430_CHIRONSS_CHIRONSS_DEVICE_PRM_MOD       0x0200
+#define OMAP4430_CHIRONSS_CHIRONSS_CPU0_MOD             0x0400
+#define OMAP4430_CHIRONSS_CHIRONSS_CPU1_MOD             0x0800
 
 /* 24XX register bits shared between CM & PRM registers */
 
diff --git a/arch/arm/mach-omap2/prcm.c b/arch/arm/mach-omap2/prcm.c
index 029d376198d4..3ea8177ffb25 100644
--- a/arch/arm/mach-omap2/prcm.c
+++ b/arch/arm/mach-omap2/prcm.c
@@ -34,6 +34,7 @@
 
 static void __iomem *prm_base;
 static void __iomem *cm_base;
+static void __iomem *cm2_base;
 
 #define MAX_MODULE_ENABLE_WAIT          100000
 
@@ -170,14 +171,12 @@ u32 prm_read_mod_reg(s16 module, u16 idx)
 {
         return __omap_prcm_read(prm_base, module, idx);
 }
-EXPORT_SYMBOL(prm_read_mod_reg);
 
 /* Write into a register in a PRM module */
 void prm_write_mod_reg(u32 val, s16 module, u16 idx)
 {
         __omap_prcm_write(val, prm_base, module, idx);
 }
-EXPORT_SYMBOL(prm_write_mod_reg);
 
 /* Read-modify-write a register in a PRM module. Caller must lock */
 u32 prm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx)
@@ -191,21 +190,18 @@ u32 prm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx)
 
         return v;
 }
-EXPORT_SYMBOL(prm_rmw_mod_reg_bits);
 
 /* Read a register in a CM module */
 u32 cm_read_mod_reg(s16 module, u16 idx)
 {
         return __omap_prcm_read(cm_base, module, idx);
 }
-EXPORT_SYMBOL(cm_read_mod_reg);
 
 /* Write into a register in a CM module */
 void cm_write_mod_reg(u32 val, s16 module, u16 idx)
 {
         __omap_prcm_write(val, cm_base, module, idx);
 }
-EXPORT_SYMBOL(cm_write_mod_reg);
 
 /* Read-modify-write a register in a CM module. Caller must lock */
 u32 cm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx)
@@ -219,7 +215,6 @@ u32 cm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx)
 
         return v;
 }
-EXPORT_SYMBOL(cm_rmw_mod_reg_bits);
 
 /**
  * omap2_cm_wait_idlest - wait for IDLEST bit to indicate module readiness
@@ -247,9 +242,8 @@ int omap2_cm_wait_idlest(void __iomem *reg, u32 mask, const char *name)
                 BUG();
 
         /* Wait for lock */
-        while (((__raw_readl(reg) & mask) != ena) &&
-               (i++ < MAX_MODULE_ENABLE_WAIT))
-                udelay(1);
+        omap_test_timeout(((__raw_readl(reg) & mask) == ena),
+                          MAX_MODULE_ENABLE_WAIT, i);
 
         if (i < MAX_MODULE_ENABLE_WAIT)
                 pr_debug("cm: Module associated with clock %s ready after %d "
@@ -265,6 +259,7 @@ void __init omap2_set_globals_prcm(struct omap_globals *omap2_globals)
 {
         prm_base = omap2_globals->prm;
         cm_base = omap2_globals->cm;
+        cm2_base = omap2_globals->cm2;
 }
 
 #ifdef CONFIG_ARCH_OMAP3
diff --git a/arch/arm/mach-omap2/prm-regbits-44xx.h b/arch/arm/mach-omap2/prm-regbits-44xx.h
new file mode 100644
index 000000000000..301c810fb269
--- /dev/null
+++ b/arch/arm/mach-omap2/prm-regbits-44xx.h
@@ -0,0 +1,2205 @@
+/*
+ * OMAP44xx Power Management register bits
+ *
+ * Copyright (C) 2009 Texas Instruments, Inc.
+ * Copyright (C) 2009 Nokia Corporation
+ *
+ * Paul Walmsley (paul@pwsan.com)
+ * Rajendra Nayak (rnayak@ti.com)
+ * Benoit Cousson (b-cousson@ti.com)
+ *
+ * This file is automatically generated from the OMAP hardware databases.
+ * We respectfully ask that any modifications to this file be coordinated
+ * with the public linux-omap@vger.kernel.org mailing list and the
+ * authors above to ensure that the autogeneration scripts are kept
+ * up-to-date with the file contents.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_44XX_H
+#define __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_44XX_H
+
+#include "prm.h"
+
+
+/*
+ * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP,
+ * PRM_LDO_SRAM_MPU_SETUP
+ */
+#define OMAP4430_ABBOFF_ACT_EXPORT_SHIFT                                (1 << 1)
+#define OMAP4430_ABBOFF_ACT_EXPORT_MASK                                 BITFIELD(1, 1)
+
+/*
+ * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP,
+ * PRM_LDO_SRAM_MPU_SETUP
+ */
+#define OMAP4430_ABBOFF_SLEEP_EXPORT_SHIFT                              (1 << 2)
+#define OMAP4430_ABBOFF_SLEEP_EXPORT_MASK                               BITFIELD(2, 2)
+
+/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
+#define OMAP4430_ABB_IVA_DONE_EN_SHIFT                                  (1 << 31)
+#define OMAP4430_ABB_IVA_DONE_EN_MASK                                   BITFIELD(31, 31)
+
+/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
+#define OMAP4430_ABB_IVA_DONE_ST_SHIFT                                  (1 << 31)
+#define OMAP4430_ABB_IVA_DONE_ST_MASK                                   BITFIELD(31, 31)
+
+/* Used by PRM_IRQENABLE_MPU_2 */
+#define OMAP4430_ABB_MPU_DONE_EN_SHIFT                                  (1 << 7)
+#define OMAP4430_ABB_MPU_DONE_EN_MASK                                   BITFIELD(7, 7)
+
+/* Used by PRM_IRQSTATUS_MPU_2 */
+#define OMAP4430_ABB_MPU_DONE_ST_SHIFT                                  (1 << 7)
+#define OMAP4430_ABB_MPU_DONE_ST_MASK                                   BITFIELD(7, 7)
+
+/* Used by PRM_LDO_ABB_IVA_SETUP, PRM_LDO_ABB_MPU_SETUP */
+#define OMAP4430_ACTIVE_FBB_SEL_SHIFT                                   (1 << 2)
+#define OMAP4430_ACTIVE_FBB_SEL_MASK                                    BITFIELD(2, 2)
+
+/* Used by PRM_LDO_ABB_IVA_SETUP, PRM_LDO_ABB_MPU_SETUP */
+#define OMAP4430_ACTIVE_RBB_SEL_SHIFT                                   (1 << 1)
+#define OMAP4430_ACTIVE_RBB_SEL_MASK                                    BITFIELD(1, 1)
+
+/* Used by PM_ABE_PWRSTCTRL */
+#define OMAP4430_AESSMEM_ONSTATE_SHIFT                                  (1 << 16)
+#define OMAP4430_AESSMEM_ONSTATE_MASK                                   BITFIELD(16, 17)
+
+/* Used by PM_ABE_PWRSTCTRL */
+#define OMAP4430_AESSMEM_RETSTATE_SHIFT                                 (1 << 8)
+#define OMAP4430_AESSMEM_RETSTATE_MASK                                  BITFIELD(8, 8)
+
+/* Used by PM_ABE_PWRSTST */
+#define OMAP4430_AESSMEM_STATEST_SHIFT                                  (1 << 4)
+#define OMAP4430_AESSMEM_STATEST_MASK                                   BITFIELD(4, 5)
+
+/*
+ * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP,
+ * PRM_LDO_SRAM_MPU_SETUP
+ */
+#define OMAP4430_AIPOFF_SHIFT                                           (1 << 8)
+#define OMAP4430_AIPOFF_MASK                                            BITFIELD(8, 8)
+
+/* Used by PRM_VOLTCTRL */
+#define OMAP4430_AUTO_CTRL_VDD_CORE_L_SHIFT                             (1 << 0)
+#define OMAP4430_AUTO_CTRL_VDD_CORE_L_MASK                              BITFIELD(0, 1)
+
+/* Used by PRM_VOLTCTRL */
+#define OMAP4430_AUTO_CTRL_VDD_IVA_L_SHIFT                              (1 << 4)
+#define OMAP4430_AUTO_CTRL_VDD_IVA_L_MASK                               BITFIELD(4, 5)
+
+/* Used by PRM_VOLTCTRL */
+#define OMAP4430_AUTO_CTRL_VDD_MPU_L_SHIFT                              (1 << 2)
+#define OMAP4430_AUTO_CTRL_VDD_MPU_L_MASK                               BITFIELD(2, 3)
+
+/* Used by PM_CAM_PWRSTCTRL */
+#define OMAP4430_CAM_MEM_ONSTATE_SHIFT                                  (1 << 16)
+#define OMAP4430_CAM_MEM_ONSTATE_MASK                                   BITFIELD(16, 17)
+
+/* Used by PM_CAM_PWRSTST */
+#define OMAP4430_CAM_MEM_STATEST_SHIFT                                  (1 << 4)
+#define OMAP4430_CAM_MEM_STATEST_MASK                                   BITFIELD(4, 5)
+
+/* Used by PRM_CLKREQCTRL */
+#define OMAP4430_CLKREQ_COND_SHIFT                                      (1 << 0)
+#define OMAP4430_CLKREQ_COND_MASK                                       BITFIELD(0, 2)
+
+/* Used by PRM_VC_VAL_SMPS_RA_CMD */
+#define OMAP4430_CMDRA_VDD_CORE_L_SHIFT                                 (1 << 0)
+#define OMAP4430_CMDRA_VDD_CORE_L_MASK                                  BITFIELD(0, 7)
+
+/* Used by PRM_VC_VAL_SMPS_RA_CMD */
+#define OMAP4430_CMDRA_VDD_IVA_L_SHIFT                                  (1 << 8)
+#define OMAP4430_CMDRA_VDD_IVA_L_MASK                                   BITFIELD(8, 15)
+
+/* Used by PRM_VC_VAL_SMPS_RA_CMD */
+#define OMAP4430_CMDRA_VDD_MPU_L_SHIFT                                  (1 << 16)
+#define OMAP4430_CMDRA_VDD_MPU_L_MASK                                   BITFIELD(16, 23)
+
+/* Used by PRM_VC_CFG_CHANNEL */
+#define OMAP4430_CMD_VDD_CORE_L_SHIFT                                   (1 << 4)
+#define OMAP4430_CMD_VDD_CORE_L_MASK                                    BITFIELD(4, 4)
+
+/* Used by PRM_VC_CFG_CHANNEL */
+#define OMAP4430_CMD_VDD_IVA_L_SHIFT                                    (1 << 12)
+#define OMAP4430_CMD_VDD_IVA_L_MASK                                     BITFIELD(12, 12)
+
+/* Used by PRM_VC_CFG_CHANNEL */
+#define OMAP4430_CMD_VDD_MPU_L_SHIFT                                    (1 << 17)
+#define OMAP4430_CMD_VDD_MPU_L_MASK                                     BITFIELD(17, 17)
+
+/* Used by PM_CORE_PWRSTCTRL */
+#define OMAP4430_CORE_OCMRAM_ONSTATE_SHIFT                              (1 << 18)
+#define OMAP4430_CORE_OCMRAM_ONSTATE_MASK                               BITFIELD(18, 19)
+
+/* Used by PM_CORE_PWRSTCTRL */
+#define OMAP4430_CORE_OCMRAM_RETSTATE_SHIFT                             (1 << 9)
+#define OMAP4430_CORE_OCMRAM_RETSTATE_MASK                              BITFIELD(9, 9)
+
+/* Used by PM_CORE_PWRSTST */
+#define OMAP4430_CORE_OCMRAM_STATEST_SHIFT                              (1 << 6)
+#define OMAP4430_CORE_OCMRAM_STATEST_MASK                               BITFIELD(6, 7)
+
+/* Used by PM_CORE_PWRSTCTRL */
+#define OMAP4430_CORE_OTHER_BANK_ONSTATE_SHIFT                          (1 << 16)
+#define OMAP4430_CORE_OTHER_BANK_ONSTATE_MASK                           BITFIELD(16, 17)
+
+/* Used by PM_CORE_PWRSTCTRL */
+#define OMAP4430_CORE_OTHER_BANK_RETSTATE_SHIFT                         (1 << 8)
+#define OMAP4430_CORE_OTHER_BANK_RETSTATE_MASK                          BITFIELD(8, 8)
+
+/* Used by PM_CORE_PWRSTST */
+#define OMAP4430_CORE_OTHER_BANK_STATEST_SHIFT                          (1 << 4)
+#define OMAP4430_CORE_OTHER_BANK_STATEST_MASK                           BITFIELD(4, 5)
+
+/* Used by PRM_VC_VAL_BYPASS */
+#define OMAP4430_DATA_SHIFT                                             (1 << 16)
+#define OMAP4430_DATA_MASK                                              BITFIELD(16, 23)
+
+/* Used by PRM_DEVICE_OFF_CTRL */
+#define OMAP4430_DEVICE_OFF_ENABLE_SHIFT                                (1 << 0)
+#define OMAP4430_DEVICE_OFF_ENABLE_MASK                                 BITFIELD(0, 0)
+
+/* Used by PRM_VC_CFG_I2C_MODE */
+#define OMAP4430_DFILTEREN_SHIFT                                        (1 << 6)
+#define OMAP4430_DFILTEREN_MASK                                         BITFIELD(6, 6)
+
+/* Used by PRM_IRQENABLE_MPU, PRM_IRQENABLE_TESLA */
+#define OMAP4430_DPLL_ABE_RECAL_EN_SHIFT                                (1 << 4)
+#define OMAP4430_DPLL_ABE_RECAL_EN_MASK                                 BITFIELD(4, 4)
+
+/* Used by PRM_IRQSTATUS_MPU, PRM_IRQSTATUS_TESLA */
+#define OMAP4430_DPLL_ABE_RECAL_ST_SHIFT                                (1 << 4)
+#define OMAP4430_DPLL_ABE_RECAL_ST_MASK                                 BITFIELD(4, 4)
+
+/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
+#define OMAP4430_DPLL_CORE_RECAL_EN_SHIFT                               (1 << 0)
+#define OMAP4430_DPLL_CORE_RECAL_EN_MASK                                BITFIELD(0, 0)
+
+/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
+#define OMAP4430_DPLL_CORE_RECAL_ST_SHIFT                               (1 << 0)
+#define OMAP4430_DPLL_CORE_RECAL_ST_MASK                                BITFIELD(0, 0)
+
+/* Used by PRM_IRQENABLE_MPU */
+#define OMAP4430_DPLL_DDRPHY_RECAL_EN_SHIFT                             (1 << 6)
+#define OMAP4430_DPLL_DDRPHY_RECAL_EN_MASK                              BITFIELD(6, 6)
+
+/* Used by PRM_IRQSTATUS_MPU */
+#define OMAP4430_DPLL_DDRPHY_RECAL_ST_SHIFT                             (1 << 6)
+#define OMAP4430_DPLL_DDRPHY_RECAL_ST_MASK                              BITFIELD(6, 6)
+
+/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU, PRM_IRQENABLE_TESLA */
+#define OMAP4430_DPLL_IVA_RECAL_EN_SHIFT                                (1 << 2)
+#define OMAP4430_DPLL_IVA_RECAL_EN_MASK                                 BITFIELD(2, 2)
+
+/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU, PRM_IRQSTATUS_TESLA */
+#define OMAP4430_DPLL_IVA_RECAL_ST_SHIFT                                (1 << 2)
+#define OMAP4430_DPLL_IVA_RECAL_ST_MASK                                 BITFIELD(2, 2)
+
+/* Used by PRM_IRQENABLE_MPU */
+#define OMAP4430_DPLL_MPU_RECAL_EN_SHIFT                                (1 << 1)
+#define OMAP4430_DPLL_MPU_RECAL_EN_MASK                                 BITFIELD(1, 1)
+
+/* Used by PRM_IRQSTATUS_MPU */
+#define OMAP4430_DPLL_MPU_RECAL_ST_SHIFT                                (1 << 1)
+#define OMAP4430_DPLL_MPU_RECAL_ST_MASK                                 BITFIELD(1, 1)
+
+/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
+#define OMAP4430_DPLL_PER_RECAL_EN_SHIFT                                (1 << 3)
+#define OMAP4430_DPLL_PER_RECAL_EN_MASK                                 BITFIELD(3, 3)
+
+/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
+#define OMAP4430_DPLL_PER_RECAL_ST_SHIFT                                (1 << 3)
+#define OMAP4430_DPLL_PER_RECAL_ST_MASK                                 BITFIELD(3, 3)
+
+/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
+#define OMAP4430_DPLL_UNIPRO_RECAL_EN_SHIFT                             (1 << 7)
+#define OMAP4430_DPLL_UNIPRO_RECAL_EN_MASK                              BITFIELD(7, 7)
+
+/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
+#define OMAP4430_DPLL_UNIPRO_RECAL_ST_SHIFT                             (1 << 7)
+#define OMAP4430_DPLL_UNIPRO_RECAL_ST_MASK                              BITFIELD(7, 7)
+
+/* Used by PRM_IRQENABLE_MPU */
+#define OMAP4430_DPLL_USB_RECAL_EN_SHIFT                                (1 << 5)
+#define OMAP4430_DPLL_USB_RECAL_EN_MASK                                 BITFIELD(5, 5)
+
+/* Used by PRM_IRQSTATUS_MPU */
+#define OMAP4430_DPLL_USB_RECAL_ST_SHIFT                                (1 << 5)
+#define OMAP4430_DPLL_USB_RECAL_ST_MASK                                 BITFIELD(5, 5)
+
+/* Used by PM_DSS_PWRSTCTRL */
+#define OMAP4430_DSS_MEM_ONSTATE_SHIFT                                  (1 << 16)
+#define OMAP4430_DSS_MEM_ONSTATE_MASK                                   BITFIELD(16, 17)
+
+/* Used by PM_DSS_PWRSTCTRL */
+#define OMAP4430_DSS_MEM_RETSTATE_SHIFT                                 (1 << 8)
+#define OMAP4430_DSS_MEM_RETSTATE_MASK                                  BITFIELD(8, 8)
+
+/* Used by PM_DSS_PWRSTST */
+#define OMAP4430_DSS_MEM_STATEST_SHIFT                                  (1 << 4)
+#define OMAP4430_DSS_MEM_STATEST_MASK                                   BITFIELD(4, 5)
+
+/* Used by PM_CORE_PWRSTCTRL */
+#define OMAP4430_DUCATI_L2RAM_ONSTATE_SHIFT                             (1 << 20)
+#define OMAP4430_DUCATI_L2RAM_ONSTATE_MASK                              BITFIELD(20, 21)
+
+/* Used by PM_CORE_PWRSTCTRL */
+#define OMAP4430_DUCATI_L2RAM_RETSTATE_SHIFT                            (1 << 10)
+#define OMAP4430_DUCATI_L2RAM_RETSTATE_MASK                             BITFIELD(10, 10)
+
+/* Used by PM_CORE_PWRSTST */
+#define OMAP4430_DUCATI_L2RAM_STATEST_SHIFT                             (1 << 8)
+#define OMAP4430_DUCATI_L2RAM_STATEST_MASK                              BITFIELD(8, 9)
+
+/* Used by PM_CORE_PWRSTCTRL */
+#define OMAP4430_DUCATI_UNICACHE_ONSTATE_SHIFT                          (1 << 22)
+#define OMAP4430_DUCATI_UNICACHE_ONSTATE_MASK                           BITFIELD(22, 23)
+
+/* Used by PM_CORE_PWRSTCTRL */
+#define OMAP4430_DUCATI_UNICACHE_RETSTATE_SHIFT                         (1 << 11)
+#define OMAP4430_DUCATI_UNICACHE_RETSTATE_MASK                          BITFIELD(11, 11)
+
+/* Used by PM_CORE_PWRSTST */
+#define OMAP4430_DUCATI_UNICACHE_STATEST_SHIFT                          (1 << 10)
+#define OMAP4430_DUCATI_UNICACHE_STATEST_MASK                           BITFIELD(10, 11)
+
+/* Used by RM_MPU_RSTST */
+#define OMAP4430_EMULATION_RST_SHIFT                                    (1 << 0)
+#define OMAP4430_EMULATION_RST_MASK                                     BITFIELD(0, 0)
+
+/* Used by RM_DUCATI_RSTST */
+#define OMAP4430_EMULATION_RST1ST_SHIFT                                 (1 << 3)
+#define OMAP4430_EMULATION_RST1ST_MASK                                  BITFIELD(3, 3)
+
+/* Used by RM_DUCATI_RSTST */
+#define OMAP4430_EMULATION_RST2ST_SHIFT                                 (1 << 4)
+#define OMAP4430_EMULATION_RST2ST_MASK                                  BITFIELD(4, 4)
+
+/* Used by RM_IVAHD_RSTST */
+#define OMAP4430_EMULATION_SEQ1_RST1ST_SHIFT                            (1 << 3)
+#define OMAP4430_EMULATION_SEQ1_RST1ST_MASK                             BITFIELD(3, 3)
+
+/* Used by RM_IVAHD_RSTST */
+#define OMAP4430_EMULATION_SEQ2_RST2ST_SHIFT                            (1 << 4)
+#define OMAP4430_EMULATION_SEQ2_RST2ST_MASK                             BITFIELD(4, 4)
+
+/* Used by PM_EMU_PWRSTCTRL */
+#define OMAP4430_EMU_BANK_ONSTATE_SHIFT                                 (1 << 16)
+#define OMAP4430_EMU_BANK_ONSTATE_MASK                                  BITFIELD(16, 17)
+
+/* Used by PM_EMU_PWRSTST */
+#define OMAP4430_EMU_BANK_STATEST_SHIFT                                 (1 << 4)
+#define OMAP4430_EMU_BANK_STATEST_MASK                                  BITFIELD(4, 5)
+
+/*
+ * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP,
+ * PRM_LDO_SRAM_MPU_SETUP, PRM_SRAM_WKUP_SETUP
+ */
+#define OMAP4430_ENABLE_RTA_EXPORT_SHIFT                                (1 << 0)
+#define OMAP4430_ENABLE_RTA_EXPORT_MASK                                 BITFIELD(0, 0)
+
+/*
+ * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP,
+ * PRM_LDO_SRAM_MPU_SETUP
+ */
+#define OMAP4430_ENFUNC1_SHIFT                                          (1 << 3)
+#define OMAP4430_ENFUNC1_MASK                                           BITFIELD(3, 3)
+
+/*
+ * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP,
+ * PRM_LDO_SRAM_MPU_SETUP
+ */
+#define OMAP4430_ENFUNC3_SHIFT                                          (1 << 5)
+#define OMAP4430_ENFUNC3_MASK                                           BITFIELD(5, 5)
+
+/*
+ * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP,
+ * PRM_LDO_SRAM_MPU_SETUP
+ */
+#define OMAP4430_ENFUNC4_SHIFT                                          (1 << 6)
+#define OMAP4430_ENFUNC4_MASK                                           BITFIELD(6, 6)
+
+/*
+ * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP,
+ * PRM_LDO_SRAM_MPU_SETUP
+ */
+#define OMAP4430_ENFUNC5_SHIFT                                          (1 << 7)
+#define OMAP4430_ENFUNC5_MASK                                           BITFIELD(7, 7)
+
+/* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */
+#define OMAP4430_ERRORGAIN_SHIFT                                        (1 << 16)
+#define OMAP4430_ERRORGAIN_MASK                                         BITFIELD(16, 23)
+
+/* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */
+#define OMAP4430_ERROROFFSET_SHIFT                                      (1 << 24)
+#define OMAP4430_ERROROFFSET_MASK                                       BITFIELD(24, 31)
+
+/* Used by PRM_RSTST */
+#define OMAP4430_EXTERNAL_WARM_RST_SHIFT                                (1 << 5)
+#define OMAP4430_EXTERNAL_WARM_RST_MASK                                 BITFIELD(5, 5)
+
+/* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */
+#define OMAP4430_FORCEUPDATE_SHIFT                                      (1 << 1)
+#define OMAP4430_FORCEUPDATE_MASK                                       BITFIELD(1, 1)
+
+/* Used by PRM_VP_CORE_VOLTAGE, PRM_VP_IVA_VOLTAGE, PRM_VP_MPU_VOLTAGE */
+#define OMAP4430_FORCEUPDATEWAIT_SHIFT                                  (1 << 8)
+#define OMAP4430_FORCEUPDATEWAIT_MASK                                   BITFIELD(8, 31)
+
+/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_TESLA */
+#define OMAP4430_FORCEWKUP_EN_SHIFT                                     (1 << 10)
+#define OMAP4430_FORCEWKUP_EN_MASK                                      BITFIELD(10, 10)
+
+/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_TESLA */
+#define OMAP4430_FORCEWKUP_ST_SHIFT                                     (1 << 10)
+#define OMAP4430_FORCEWKUP_ST_MASK                                      BITFIELD(10, 10)
+
+/* Used by PM_GFX_PWRSTCTRL */
+#define OMAP4430_GFX_MEM_ONSTATE_SHIFT                                  (1 << 16)
+#define OMAP4430_GFX_MEM_ONSTATE_MASK                                   BITFIELD(16, 17)
+
+/* Used by PM_GFX_PWRSTST */
+#define OMAP4430_GFX_MEM_STATEST_SHIFT                                  (1 << 4)
+#define OMAP4430_GFX_MEM_STATEST_MASK                                   BITFIELD(4, 5)
+
+/* Used by PRM_RSTST */
+#define OMAP4430_GLOBAL_COLD_RST_SHIFT                                  (1 << 0)
+#define OMAP4430_GLOBAL_COLD_RST_MASK                                   BITFIELD(0, 0)
+
+/* Used by PRM_RSTST */
+#define OMAP4430_GLOBAL_WARM_SW_RST_SHIFT                               (1 << 1)
+#define OMAP4430_GLOBAL_WARM_SW_RST_MASK                                BITFIELD(1, 1)
+
+/* Used by PRM_IO_PMCTRL */
+#define OMAP4430_GLOBAL_WUEN_SHIFT                                      (1 << 16)
+#define OMAP4430_GLOBAL_WUEN_MASK                                       BITFIELD(16, 16)
+
+/* Used by PRM_VC_CFG_I2C_MODE */
+#define OMAP4430_HSMCODE_SHIFT                                          (1 << 0)
+#define OMAP4430_HSMCODE_MASK                                           BITFIELD(0, 2)
+
+/* Used by PRM_VC_CFG_I2C_MODE */
+#define OMAP4430_HSMODEEN_SHIFT                                         (1 << 3)
+#define OMAP4430_HSMODEEN_MASK                                          BITFIELD(3, 3)
+
+/* Used by PRM_VC_CFG_I2C_CLK */
+#define OMAP4430_HSSCLH_SHIFT                                           (1 << 16)
+#define OMAP4430_HSSCLH_MASK                                            BITFIELD(16, 23)
+
+/* Used by PRM_VC_CFG_I2C_CLK */
+#define OMAP4430_HSSCLL_SHIFT                                           (1 << 24)
+#define OMAP4430_HSSCLL_MASK                                            BITFIELD(24, 31)
+
+/* Used by PM_IVAHD_PWRSTCTRL */
+#define OMAP4430_HWA_MEM_ONSTATE_SHIFT                                  (1 << 16)
+#define OMAP4430_HWA_MEM_ONSTATE_MASK                                   BITFIELD(16, 17)
+
+/* Used by PM_IVAHD_PWRSTCTRL */
+#define OMAP4430_HWA_MEM_RETSTATE_SHIFT                                 (1 << 8)
+#define OMAP4430_HWA_MEM_RETSTATE_MASK                                  BITFIELD(8, 8)
+
+/* Used by PM_IVAHD_PWRSTST */
+#define OMAP4430_HWA_MEM_STATEST_SHIFT                                  (1 << 4)
+#define OMAP4430_HWA_MEM_STATEST_MASK                                   BITFIELD(4, 5)
+
+/* Used by RM_MPU_RSTST */
+#define OMAP4430_ICECRUSHER_MPU_RST_SHIFT                               (1 << 1)
+#define OMAP4430_ICECRUSHER_MPU_RST_MASK                                BITFIELD(1, 1)
+
+/* Used by RM_DUCATI_RSTST */
+#define OMAP4430_ICECRUSHER_RST1ST_SHIFT                                (1 << 5)
+#define OMAP4430_ICECRUSHER_RST1ST_MASK                                 BITFIELD(5, 5)
+
+/* Used by RM_DUCATI_RSTST */
+#define OMAP4430_ICECRUSHER_RST2ST_SHIFT                                (1 << 6)
+#define OMAP4430_ICECRUSHER_RST2ST_MASK                                 BITFIELD(6, 6)
+
+/* Used by RM_IVAHD_RSTST */
+#define OMAP4430_ICECRUSHER_SEQ1_RST1ST_SHIFT                           (1 << 5)
+#define OMAP4430_ICECRUSHER_SEQ1_RST1ST_MASK                            BITFIELD(5, 5)
+
+/* Used by RM_IVAHD_RSTST */
+#define OMAP4430_ICECRUSHER_SEQ2_RST2ST_SHIFT                           (1 << 6)
+#define OMAP4430_ICECRUSHER_SEQ2_RST2ST_MASK                            BITFIELD(6, 6)
+
+/* Used by PRM_RSTST */
+#define OMAP4430_ICEPICK_RST_SHIFT                                      (1 << 9)
+#define OMAP4430_ICEPICK_RST_MASK                                       BITFIELD(9, 9)
+
+/* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */
+#define OMAP4430_INITVDD_SHIFT                                          (1 << 2)
+#define OMAP4430_INITVDD_MASK                                           BITFIELD(2, 2)
+
+/* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */
+#define OMAP4430_INITVOLTAGE_SHIFT                                      (1 << 8)
+#define OMAP4430_INITVOLTAGE_MASK                                       BITFIELD(8, 15)
+
+/*
+ * Used by PM_EMU_PWRSTST, PM_CORE_PWRSTST, PM_CAM_PWRSTST, PM_L3INIT_PWRSTST,
+ * PM_ABE_PWRSTST, PM_GFX_PWRSTST, PM_MPU_PWRSTST, PM_CEFUSE_PWRSTST,
+ * PM_DSS_PWRSTST, PM_L4PER_PWRSTST, PM_TESLA_PWRSTST, PM_IVAHD_PWRSTST
+ */
+#define OMAP4430_INTRANSITION_SHIFT                                     (1 << 20)
+#define OMAP4430_INTRANSITION_MASK                                      BITFIELD(20, 20)
+
+/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
+#define OMAP4430_IO_EN_SHIFT                                            (1 << 9)
+#define OMAP4430_IO_EN_MASK                                             BITFIELD(9, 9)
+
+/* Used by PRM_IO_PMCTRL */
+#define OMAP4430_IO_ON_STATUS_SHIFT                                     (1 << 5)
+#define OMAP4430_IO_ON_STATUS_MASK                                      BITFIELD(5, 5)
+
+/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
+#define OMAP4430_IO_ST_SHIFT                                            (1 << 9)
+#define OMAP4430_IO_ST_MASK                                             BITFIELD(9, 9)
+
+/* Used by PRM_IO_PMCTRL */
+#define OMAP4430_ISOCLK_OVERRIDE_SHIFT                                  (1 << 0)
+#define OMAP4430_ISOCLK_OVERRIDE_MASK                                   BITFIELD(0, 0)
+
+/* Used by PRM_IO_PMCTRL */
+#define OMAP4430_ISOCLK_STATUS_SHIFT                                    (1 << 1)
+#define OMAP4430_ISOCLK_STATUS_MASK                                     BITFIELD(1, 1)
+
+/* Used by PRM_IO_PMCTRL */
+#define OMAP4430_ISOOVR_EXTEND_SHIFT                                    (1 << 4)
+#define OMAP4430_ISOOVR_EXTEND_MASK                                     BITFIELD(4, 4)
+
+/* Used by PRM_IO_COUNT */
+#define OMAP4430_ISO_2_ON_TIME_SHIFT                                    (1 << 0)
+#define OMAP4430_ISO_2_ON_TIME_MASK                                     BITFIELD(0, 7)
+
+/* Used by PM_L3INIT_PWRSTCTRL */
+#define OMAP4430_L3INIT_BANK1_ONSTATE_SHIFT                             (1 << 16)
+#define OMAP4430_L3INIT_BANK1_ONSTATE_MASK                              BITFIELD(16, 17)
+
+/* Used by PM_L3INIT_PWRSTCTRL */
+#define OMAP4430_L3INIT_BANK1_RETSTATE_SHIFT                            (1 << 8)
+#define OMAP4430_L3INIT_BANK1_RETSTATE_MASK                             BITFIELD(8, 8)
+
+/* Used by PM_L3INIT_PWRSTST */
+#define OMAP4430_L3INIT_BANK1_STATEST_SHIFT                             (1 << 4)
+#define OMAP4430_L3INIT_BANK1_STATEST_MASK                              BITFIELD(4, 5)
+
+/*
+ * Used by PM_CORE_PWRSTCTRL, PM_L3INIT_PWRSTCTRL, PM_ABE_PWRSTCTRL,
+ * PM_MPU_PWRSTCTRL, PM_DSS_PWRSTCTRL, PM_L4PER_PWRSTCTRL, PM_TESLA_PWRSTCTRL,
+ * PM_IVAHD_PWRSTCTRL
+ */
+#define OMAP4430_LOGICRETSTATE_SHIFT                                    (1 << 2)
+#define OMAP4430_LOGICRETSTATE_MASK                                     BITFIELD(2, 2)
+
+/*
+ * Used by PM_EMU_PWRSTST, PM_CORE_PWRSTST, PM_CAM_PWRSTST, PM_L3INIT_PWRSTST,
+ * PM_ABE_PWRSTST, PM_GFX_PWRSTST, PM_MPU_PWRSTST, PM_CEFUSE_PWRSTST,
+ * PM_DSS_PWRSTST, PM_L4PER_PWRSTST, PM_TESLA_PWRSTST, PM_IVAHD_PWRSTST
+ */
+#define OMAP4430_LOGICSTATEST_SHIFT                                     (1 << 2)
+#define OMAP4430_LOGICSTATEST_MASK                                      BITFIELD(2, 2)
+
+/*
+ * Used by RM_WKUP_GPIO1_CONTEXT, RM_WKUP_KEYBOARD_CONTEXT,
+ * RM_WKUP_L4WKUP_CONTEXT, RM_WKUP_RTC_CONTEXT, RM_WKUP_SARRAM_CONTEXT,
+ * RM_WKUP_SYNCTIMER_CONTEXT, RM_WKUP_TIMER12_CONTEXT, RM_WKUP_TIMER1_CONTEXT,
+ * RM_WKUP_USIM_CONTEXT, RM_WKUP_WDT1_CONTEXT, RM_WKUP_WDT2_CONTEXT,
+ * RM_EMU_DEBUGSS_CONTEXT, RM_D2D_SAD2D_CONTEXT, RM_D2D_SAD2D_FW_CONTEXT,
+ * RM_DUCATI_DUCATI_CONTEXT, RM_L3INSTR_L3_3_CONTEXT,
+ * RM_L3INSTR_L3_INSTR_CONTEXT, RM_L3INSTR_OCP_WP1_CONTEXT,
+ * RM_L3_1_L3_1_CONTEXT, RM_L3_2_L3_2_CONTEXT, RM_L3_2_OCMC_RAM_CONTEXT,
+ * RM_L4CFG_L4_CFG_CONTEXT, RM_L4CFG_SAR_ROM_CONTEXT, RM_MEMIF_DLL_CONTEXT,
+ * RM_MEMIF_DLL_H_CONTEXT, RM_MEMIF_DMM_CONTEXT, RM_MEMIF_EMIF_FW_CONTEXT,
+ * RM_CAM_FDIF_CONTEXT, RM_CAM_ISS_CONTEXT, RM_L3INIT_CCPTX_CONTEXT,
+ * RM_L3INIT_EMAC_CONTEXT, RM_L3INIT_P1500_CONTEXT, RM_L3INIT_PCIESS_CONTEXT,
+ * RM_L3INIT_SATA_CONTEXT, RM_L3INIT_TPPSS_CONTEXT, RM_L3INIT_UNIPRO1_CONTEXT,
+ * RM_L3INIT_USBPHYOCP2SCP_CONTEXT, RM_L3INIT_XHPI_CONTEXT,
+ * RM_ABE_AESS_CONTEXT, RM_ABE_DMIC_CONTEXT, RM_ABE_MCASP_CONTEXT,
+ * RM_ABE_MCBSP1_CONTEXT, RM_ABE_MCBSP2_CONTEXT, RM_ABE_MCBSP3_CONTEXT,
+ * RM_ABE_PDM_CONTEXT, RM_ABE_SLIMBUS_CONTEXT, RM_ABE_TIMER5_CONTEXT,
+ * RM_ABE_TIMER6_CONTEXT, RM_ABE_TIMER7_CONTEXT, RM_ABE_TIMER8_CONTEXT,
+ * RM_ABE_WDT3_CONTEXT, RM_GFX_GFX_CONTEXT, RM_MPU_MPU_CONTEXT,
+ * RM_CEFUSE_CEFUSE_CONTEXT, RM_ALWON_MDMINTC_CONTEXT,
+ * RM_ALWON_SR_CORE_CONTEXT, RM_ALWON_SR_IVA_CONTEXT, RM_ALWON_SR_MPU_CONTEXT,
+ * RM_DSS_DEISS_CONTEXT, RM_DSS_DSS_CONTEXT, RM_L4PER_ADC_CONTEXT,
+ * RM_L4PER_DMTIMER10_CONTEXT, RM_L4PER_DMTIMER11_CONTEXT,
+ * RM_L4PER_DMTIMER2_CONTEXT, RM_L4PER_DMTIMER3_CONTEXT,
+ * RM_L4PER_DMTIMER4_CONTEXT, RM_L4PER_DMTIMER9_CONTEXT, RM_L4PER_ELM_CONTEXT,
+ * RM_L4PER_HDQ1W_CONTEXT, RM_L4PER_HECC1_CONTEXT, RM_L4PER_HECC2_CONTEXT,
+ * RM_L4PER_I2C2_CONTEXT, RM_L4PER_I2C3_CONTEXT, RM_L4PER_I2C4_CONTEXT,
+ * RM_L4PER_I2C5_CONTEXT, RM_L4PER_L4_PER_CONTEXT, RM_L4PER_MCASP2_CONTEXT,
+ * RM_L4PER_MCASP3_CONTEXT, RM_L4PER_MCBSP4_CONTEXT, RM_L4PER_MCSPI1_CONTEXT,
+ * RM_L4PER_MCSPI2_CONTEXT, RM_L4PER_MCSPI3_CONTEXT, RM_L4PER_MCSPI4_CONTEXT,
+ * RM_L4PER_MGATE_CONTEXT, RM_L4PER_MMCSD3_CONTEXT, RM_L4PER_MMCSD4_CONTEXT,
+ * RM_L4PER_MMCSD5_CONTEXT, RM_L4PER_MSPROHG_CONTEXT,
+ * RM_L4PER_SLIMBUS2_CONTEXT, RM_L4SEC_PKAEIP29_CONTEXT,
+ * RM_TESLA_TESLA_CONTEXT, RM_IVAHD_IVAHD_CONTEXT, RM_IVAHD_SL2_CONTEXT
+ */
+#define OMAP4430_LOSTCONTEXT_DFF_SHIFT                                  (1 << 0)
+#define OMAP4430_LOSTCONTEXT_DFF_MASK                                   BITFIELD(0, 0)
+
+/*
+ * Used by RM_D2D_MODEM_ICR_CONTEXT, RM_D2D_SAD2D_CONTEXT,
+ * RM_D2D_SAD2D_FW_CONTEXT, RM_DUCATI_DUCATI_CONTEXT, RM_L3INSTR_L3_3_CONTEXT,
+ * RM_L3INSTR_OCP_WP1_CONTEXT, RM_L3_1_L3_1_CONTEXT, RM_L3_2_GPMC_CONTEXT,
+ * RM_L3_2_L3_2_CONTEXT, RM_L4CFG_HW_SEM_CONTEXT, RM_L4CFG_L4_CFG_CONTEXT,
+ * RM_L4CFG_MAILBOX_CONTEXT, RM_MEMIF_DMM_CONTEXT, RM_MEMIF_EMIF_1_CONTEXT,
+ * RM_MEMIF_EMIF_2_CONTEXT, RM_MEMIF_EMIF_FW_CONTEXT, RM_MEMIF_EMIF_H1_CONTEXT,
+ * RM_MEMIF_EMIF_H2_CONTEXT, RM_SDMA_SDMA_CONTEXT, RM_L3INIT_HSI_CONTEXT,
+ * RM_L3INIT_MMC1_CONTEXT, RM_L3INIT_MMC2_CONTEXT, RM_L3INIT_MMC6_CONTEXT,
+ * RM_L3INIT_USB_HOST_CONTEXT, RM_L3INIT_USB_HOST_FS_CONTEXT,
+ * RM_L3INIT_USB_OTG_CONTEXT, RM_L3INIT_USB_TLL_CONTEXT, RM_DSS_DSS_CONTEXT,
+ * RM_L4PER_GPIO2_CONTEXT, RM_L4PER_GPIO3_CONTEXT, RM_L4PER_GPIO4_CONTEXT,
+ * RM_L4PER_GPIO5_CONTEXT, RM_L4PER_GPIO6_CONTEXT, RM_L4PER_I2C1_CONTEXT,
+ * RM_L4PER_L4_PER_CONTEXT, RM_L4PER_UART1_CONTEXT, RM_L4PER_UART2_CONTEXT,
+ * RM_L4PER_UART3_CONTEXT, RM_L4PER_UART4_CONTEXT, RM_L4SEC_AES1_CONTEXT,
+ * RM_L4SEC_AES2_CONTEXT, RM_L4SEC_CRYPTODMA_CONTEXT, RM_L4SEC_DES3DES_CONTEXT,
+ * RM_L4SEC_RNG_CONTEXT, RM_L4SEC_SHA2MD51_CONTEXT, RM_TESLA_TESLA_CONTEXT
+ */
+#define OMAP4430_LOSTCONTEXT_RFF_SHIFT                                  (1 << 1)
+#define OMAP4430_LOSTCONTEXT_RFF_MASK                                   BITFIELD(1, 1)
+
+/* Used by RM_ABE_AESS_CONTEXT */
+#define OMAP4430_LOSTMEM_AESSMEM_SHIFT                                  (1 << 8)
+#define OMAP4430_LOSTMEM_AESSMEM_MASK                                   BITFIELD(8, 8)
+
+/* Used by RM_CAM_FDIF_CONTEXT, RM_CAM_ISS_CONTEXT */
+#define OMAP4430_LOSTMEM_CAM_MEM_SHIFT                                  (1 << 8)
+#define OMAP4430_LOSTMEM_CAM_MEM_MASK                                   BITFIELD(8, 8)
+
+/* Used by RM_L3INSTR_OCP_WP1_CONTEXT */
+#define OMAP4430_LOSTMEM_CORE_NRET_BANK_SHIFT                           (1 << 8)
+#define OMAP4430_LOSTMEM_CORE_NRET_BANK_MASK                            BITFIELD(8, 8)
+
+/* Renamed from LOSTMEM_CORE_NRET_BANK Used by RM_MEMIF_DMM_CONTEXT */
+#define OMAP4430_LOSTMEM_CORE_NRET_BANK_9_9_SHIFT                       (1 << 9)
+#define OMAP4430_LOSTMEM_CORE_NRET_BANK_9_9_MASK                        BITFIELD(9, 9)
+
+/* Used by RM_L3_2_OCMC_RAM_CONTEXT */
+#define OMAP4430_LOSTMEM_CORE_OCMRAM_SHIFT                              (1 << 8)
+#define OMAP4430_LOSTMEM_CORE_OCMRAM_MASK                               BITFIELD(8, 8)
+
+/*
+ * Used by RM_D2D_MODEM_ICR_CONTEXT, RM_MEMIF_DMM_CONTEXT,
+ * RM_SDMA_SDMA_CONTEXT
+ */
+#define OMAP4430_LOSTMEM_CORE_OTHER_BANK_SHIFT                          (1 << 8)
+#define OMAP4430_LOSTMEM_CORE_OTHER_BANK_MASK                           BITFIELD(8, 8)
+
+/* Used by RM_DSS_DEISS_CONTEXT, RM_DSS_DSS_CONTEXT */
+#define OMAP4430_LOSTMEM_DSS_MEM_SHIFT                                  (1 << 8)
+#define OMAP4430_LOSTMEM_DSS_MEM_MASK                                   BITFIELD(8, 8)
+
+/* Used by RM_DUCATI_DUCATI_CONTEXT */
+#define OMAP4430_LOSTMEM_DUCATI_L2RAM_SHIFT                             (1 << 9)
+#define OMAP4430_LOSTMEM_DUCATI_L2RAM_MASK                              BITFIELD(9, 9)
+
+/* Used by RM_DUCATI_DUCATI_CONTEXT */
+#define OMAP4430_LOSTMEM_DUCATI_UNICACHE_SHIFT                          (1 << 8)
+#define OMAP4430_LOSTMEM_DUCATI_UNICACHE_MASK                           BITFIELD(8, 8)
+
+/* Used by RM_EMU_DEBUGSS_CONTEXT */
+#define OMAP4430_LOSTMEM_EMU_BANK_SHIFT                                 (1 << 8)
+#define OMAP4430_LOSTMEM_EMU_BANK_MASK                                  BITFIELD(8, 8)
+
+/* Used by RM_GFX_GFX_CONTEXT */
+#define OMAP4430_LOSTMEM_GFX_MEM_SHIFT                                  (1 << 8)
+#define OMAP4430_LOSTMEM_GFX_MEM_MASK                                   BITFIELD(8, 8)
+
+/* Used by RM_IVAHD_IVAHD_CONTEXT */
+#define OMAP4430_LOSTMEM_HWA_MEM_SHIFT                                  (1 << 10)
+#define OMAP4430_LOSTMEM_HWA_MEM_MASK                                   BITFIELD(10, 10)
+
+/*
+ * Used by RM_L3INIT_CCPTX_CONTEXT, RM_L3INIT_EMAC_CONTEXT,
+ * RM_L3INIT_HSI_CONTEXT, RM_L3INIT_MMC1_CONTEXT, RM_L3INIT_MMC2_CONTEXT,
+ * RM_L3INIT_MMC6_CONTEXT, RM_L3INIT_PCIESS_CONTEXT, RM_L3INIT_SATA_CONTEXT,
+ * RM_L3INIT_TPPSS_CONTEXT, RM_L3INIT_UNIPRO1_CONTEXT,
+ * RM_L3INIT_USB_OTG_CONTEXT, RM_L3INIT_XHPI_CONTEXT
+ */
+#define OMAP4430_LOSTMEM_L3INIT_BANK1_SHIFT                             (1 << 8)
+#define OMAP4430_LOSTMEM_L3INIT_BANK1_MASK                              BITFIELD(8, 8)
+
+/* Used by RM_MPU_MPU_CONTEXT */
+#define OMAP4430_LOSTMEM_MPU_L1_SHIFT                                   (1 << 8)
+#define OMAP4430_LOSTMEM_MPU_L1_MASK                                    BITFIELD(8, 8)
+
+/* Used by RM_MPU_MPU_CONTEXT */
+#define OMAP4430_LOSTMEM_MPU_L2_SHIFT                                   (1 << 9)
+#define OMAP4430_LOSTMEM_MPU_L2_MASK                                    BITFIELD(9, 9)
+
+/* Used by RM_MPU_MPU_CONTEXT */
+#define OMAP4430_LOSTMEM_MPU_RAM_SHIFT                                  (1 << 10)
+#define OMAP4430_LOSTMEM_MPU_RAM_MASK                                   BITFIELD(10, 10)
+
+/*
+ * Used by RM_L4PER_HECC1_CONTEXT, RM_L4PER_HECC2_CONTEXT,
+ * RM_L4PER_MCBSP4_CONTEXT, RM_L4PER_MMCSD3_CONTEXT, RM_L4PER_MMCSD4_CONTEXT,
+ * RM_L4PER_MMCSD5_CONTEXT, RM_L4PER_SLIMBUS2_CONTEXT, RM_L4SEC_PKAEIP29_CONTEXT
+ */
+#define OMAP4430_LOSTMEM_NONRETAINED_BANK_SHIFT                         (1 << 8)
+#define OMAP4430_LOSTMEM_NONRETAINED_BANK_MASK                          BITFIELD(8, 8)
+
+/*
+ * Used by RM_ABE_DMIC_CONTEXT, RM_ABE_MCBSP1_CONTEXT, RM_ABE_MCBSP2_CONTEXT,
+ * RM_ABE_MCBSP3_CONTEXT, RM_ABE_PDM_CONTEXT, RM_ABE_SLIMBUS_CONTEXT
+ */
+#define OMAP4430_LOSTMEM_PERIHPMEM_SHIFT                                (1 << 8)
+#define OMAP4430_LOSTMEM_PERIHPMEM_MASK                                 BITFIELD(8, 8)
+
+/*
+ * Used by RM_L4PER_MSPROHG_CONTEXT, RM_L4PER_UART1_CONTEXT,
+ * RM_L4PER_UART2_CONTEXT, RM_L4PER_UART3_CONTEXT, RM_L4PER_UART4_CONTEXT,
+ * RM_L4SEC_CRYPTODMA_CONTEXT
+ */
+#define OMAP4430_LOSTMEM_RETAINED_BANK_SHIFT                            (1 << 8)
+#define OMAP4430_LOSTMEM_RETAINED_BANK_MASK                             BITFIELD(8, 8)
+
+/* Used by RM_IVAHD_SL2_CONTEXT */
+#define OMAP4430_LOSTMEM_SL2_MEM_SHIFT                                  (1 << 8)
+#define OMAP4430_LOSTMEM_SL2_MEM_MASK                                   BITFIELD(8, 8)
+
+/* Used by RM_IVAHD_IVAHD_CONTEXT */
+#define OMAP4430_LOSTMEM_TCM1_MEM_SHIFT                                 (1 << 8)
+#define OMAP4430_LOSTMEM_TCM1_MEM_MASK                                  BITFIELD(8, 8)
+
+/* Used by RM_IVAHD_IVAHD_CONTEXT */
+#define OMAP4430_LOSTMEM_TCM2_MEM_SHIFT                                 (1 << 9)
+#define OMAP4430_LOSTMEM_TCM2_MEM_MASK                                  BITFIELD(9, 9)
+
+/* Used by RM_TESLA_TESLA_CONTEXT */
+#define OMAP4430_LOSTMEM_TESLA_EDMA_SHIFT                               (1 << 10)
+#define OMAP4430_LOSTMEM_TESLA_EDMA_MASK                                BITFIELD(10, 10)
+
+/* Used by RM_TESLA_TESLA_CONTEXT */
+#define OMAP4430_LOSTMEM_TESLA_L1_SHIFT                                 (1 << 8)
+#define OMAP4430_LOSTMEM_TESLA_L1_MASK                                  BITFIELD(8, 8)
+
+/* Used by RM_TESLA_TESLA_CONTEXT */
+#define OMAP4430_LOSTMEM_TESLA_L2_SHIFT                                 (1 << 9)
+#define OMAP4430_LOSTMEM_TESLA_L2_MASK                                  BITFIELD(9, 9)
+
+/* Used by RM_WKUP_SARRAM_CONTEXT */
+#define OMAP4430_LOSTMEM_WKUP_BANK_SHIFT                                (1 << 8)
+#define OMAP4430_LOSTMEM_WKUP_BANK_MASK                                 BITFIELD(8, 8)
+
+/*
+ * Used by PM_CORE_PWRSTCTRL, PM_CAM_PWRSTCTRL, PM_L3INIT_PWRSTCTRL,
+ * PM_ABE_PWRSTCTRL, PM_GFX_PWRSTCTRL, PM_MPU_PWRSTCTRL, PM_CEFUSE_PWRSTCTRL,
+ * PM_DSS_PWRSTCTRL, PM_L4PER_PWRSTCTRL, PM_TESLA_PWRSTCTRL, PM_IVAHD_PWRSTCTRL
+ */
+#define OMAP4430_LOWPOWERSTATECHANGE_SHIFT                              (1 << 4)
+#define OMAP4430_LOWPOWERSTATECHANGE_MASK                               BITFIELD(4, 4)
+
+/* Used by PM_CORE_PWRSTCTRL */
+#define OMAP4430_MEMORYCHANGE_SHIFT                                     (1 << 3)
+#define OMAP4430_MEMORYCHANGE_MASK                                      BITFIELD(3, 3)
+
+/* Used by PRM_MODEM_IF_CTRL */
+#define OMAP4430_MODEM_READY_SHIFT                                      (1 << 1)
+#define OMAP4430_MODEM_READY_MASK                                       BITFIELD(1, 1)
+
+/* Used by PRM_MODEM_IF_CTRL */
+#define OMAP4430_MODEM_SHUTDOWN_IRQ_SHIFT                               (1 << 9)
+#define OMAP4430_MODEM_SHUTDOWN_IRQ_MASK                                BITFIELD(9, 9)
+
+/* Used by PRM_MODEM_IF_CTRL */
+#define OMAP4430_MODEM_SLEEP_ST_SHIFT                                   (1 << 16)
+#define OMAP4430_MODEM_SLEEP_ST_MASK                                    BITFIELD(16, 16)
+
+/* Used by PRM_MODEM_IF_CTRL */
+#define OMAP4430_MODEM_WAKE_IRQ_SHIFT                                   (1 << 8)
+#define OMAP4430_MODEM_WAKE_IRQ_MASK                                    BITFIELD(8, 8)
+
+/* Used by PM_MPU_PWRSTCTRL */
+#define OMAP4430_MPU_L1_ONSTATE_SHIFT                                   (1 << 16)
+#define OMAP4430_MPU_L1_ONSTATE_MASK                                    BITFIELD(16, 17)
+
+/* Used by PM_MPU_PWRSTCTRL */
+#define OMAP4430_MPU_L1_RETSTATE_SHIFT                                  (1 << 8)
+#define OMAP4430_MPU_L1_RETSTATE_MASK                                   BITFIELD(8, 8)
+
+/* Used by PM_MPU_PWRSTST */
+#define OMAP4430_MPU_L1_STATEST_SHIFT                                   (1 << 4)
+#define OMAP4430_MPU_L1_STATEST_MASK                                    BITFIELD(4, 5)
+
+/* Used by PM_MPU_PWRSTCTRL */
+#define OMAP4430_MPU_L2_ONSTATE_SHIFT                                   (1 << 18)
+#define OMAP4430_MPU_L2_ONSTATE_MASK                                    BITFIELD(18, 19)
+
+/* Used by PM_MPU_PWRSTCTRL */
+#define OMAP4430_MPU_L2_RETSTATE_SHIFT                                  (1 << 9)
+#define OMAP4430_MPU_L2_RETSTATE_MASK                                   BITFIELD(9, 9)
+
+/* Used by PM_MPU_PWRSTST */
+#define OMAP4430_MPU_L2_STATEST_SHIFT                                   (1 << 6)
+#define OMAP4430_MPU_L2_STATEST_MASK                                    BITFIELD(6, 7)
+
+/* Used by PM_MPU_PWRSTCTRL */
+#define OMAP4430_MPU_RAM_ONSTATE_SHIFT                                  (1 << 20)
+#define OMAP4430_MPU_RAM_ONSTATE_MASK                                   BITFIELD(20, 21)
+
+/* Used by PM_MPU_PWRSTCTRL */
+#define OMAP4430_MPU_RAM_RETSTATE_SHIFT                                 (1 << 10)
+#define OMAP4430_MPU_RAM_RETSTATE_MASK                                  BITFIELD(10, 10)
+
+/* Used by PM_MPU_PWRSTST */
+#define OMAP4430_MPU_RAM_STATEST_SHIFT                                  (1 << 8)
+#define OMAP4430_MPU_RAM_STATEST_MASK                                   BITFIELD(8, 9)
+
+/* Used by PRM_RSTST */
+#define OMAP4430_MPU_SECURITY_VIOL_RST_SHIFT                            (1 << 2)
+#define OMAP4430_MPU_SECURITY_VIOL_RST_MASK                             BITFIELD(2, 2)
+
+/* Used by PRM_RSTST */
+#define OMAP4430_MPU_WDT_RST_SHIFT                                      (1 << 3)
+#define OMAP4430_MPU_WDT_RST_MASK                                       BITFIELD(3, 3)
+
+/* Used by PM_L4PER_PWRSTCTRL */
+#define OMAP4430_NONRETAINED_BANK_ONSTATE_SHIFT                         (1 << 18)
+#define OMAP4430_NONRETAINED_BANK_ONSTATE_MASK                          BITFIELD(18, 19)
+
+/* Used by PM_L4PER_PWRSTCTRL */
+#define OMAP4430_NONRETAINED_BANK_RETSTATE_SHIFT                        (1 << 9)
+#define OMAP4430_NONRETAINED_BANK_RETSTATE_MASK                         BITFIELD(9, 9)
+
+/* Used by PM_L4PER_PWRSTST */
+#define OMAP4430_NONRETAINED_BANK_STATEST_SHIFT                         (1 << 6)
+#define OMAP4430_NONRETAINED_BANK_STATEST_MASK                          BITFIELD(6, 7)
+
+/* Used by PM_CORE_PWRSTCTRL */
+#define OMAP4430_OCP_NRET_BANK_ONSTATE_SHIFT                            (1 << 24)
+#define OMAP4430_OCP_NRET_BANK_ONSTATE_MASK                             BITFIELD(24, 25)
+
+/* Used by PM_CORE_PWRSTCTRL */
+#define OMAP4430_OCP_NRET_BANK_RETSTATE_SHIFT                           (1 << 12)
+#define OMAP4430_OCP_NRET_BANK_RETSTATE_MASK                            BITFIELD(12, 12)
+
+/* Used by PM_CORE_PWRSTST */
+#define OMAP4430_OCP_NRET_BANK_STATEST_SHIFT                            (1 << 12)
+#define OMAP4430_OCP_NRET_BANK_STATEST_MASK                             BITFIELD(12, 13)
+
+/*
+ * Used by PRM_VC_VAL_CMD_VDD_CORE_L, PRM_VC_VAL_CMD_VDD_IVA_L,
+ * PRM_VC_VAL_CMD_VDD_MPU_L
+ */
+#define OMAP4430_OFF_SHIFT                                              (1 << 0)
+#define OMAP4430_OFF_MASK                                               BITFIELD(0, 7)
+
+/* Used by PRM_LDO_BANDGAP_CTRL */
+#define OMAP4430_OFF_ENABLE_SHIFT                                       (1 << 0)
+#define OMAP4430_OFF_ENABLE_MASK                                        BITFIELD(0, 0)
+
+/*
+ * Used by PRM_VC_VAL_CMD_VDD_CORE_L, PRM_VC_VAL_CMD_VDD_IVA_L,
+ * PRM_VC_VAL_CMD_VDD_MPU_L
+ */
+#define OMAP4430_ON_SHIFT                                               (1 << 24)
+#define OMAP4430_ON_MASK                                                BITFIELD(24, 31)
+
+/*
+ * Used by PRM_VC_VAL_CMD_VDD_CORE_L, PRM_VC_VAL_CMD_VDD_IVA_L,
+ * PRM_VC_VAL_CMD_VDD_MPU_L
+ */
+#define OMAP4430_ONLP_SHIFT                                             (1 << 16)
+#define OMAP4430_ONLP_MASK                                              BITFIELD(16, 23)
+
+/* Used by PRM_LDO_ABB_IVA_CTRL, PRM_LDO_ABB_MPU_CTRL */
+#define OMAP4430_OPP_CHANGE_SHIFT                                       (1 << 2)
+#define OMAP4430_OPP_CHANGE_MASK                                        BITFIELD(2, 2)
+
+/* Used by PRM_LDO_ABB_IVA_CTRL, PRM_LDO_ABB_MPU_CTRL */
+#define OMAP4430_OPP_SEL_SHIFT                                          (1 << 0)
+#define OMAP4430_OPP_SEL_MASK                                           BITFIELD(0, 1)
+
+/* Used by PRM_SRAM_COUNT */
+#define OMAP4430_PCHARGECNT_VALUE_SHIFT                                 (1 << 0)
+#define OMAP4430_PCHARGECNT_VALUE_MASK                                  BITFIELD(0, 5)
+
+/* Used by PRM_PSCON_COUNT */
+#define OMAP4430_PCHARGE_TIME_SHIFT                                     (1 << 0)
+#define OMAP4430_PCHARGE_TIME_MASK                                      BITFIELD(0, 7)
+
+/* Used by PM_ABE_PWRSTCTRL */
+#define OMAP4430_PERIPHMEM_ONSTATE_SHIFT                                (1 << 20)
+#define OMAP4430_PERIPHMEM_ONSTATE_MASK                                 BITFIELD(20, 21)
+
+/* Used by PM_ABE_PWRSTCTRL */
+#define OMAP4430_PERIPHMEM_RETSTATE_SHIFT                               (1 << 10)
+#define OMAP4430_PERIPHMEM_RETSTATE_MASK                                BITFIELD(10, 10)
+
+/* Used by PM_ABE_PWRSTST */
+#define OMAP4430_PERIPHMEM_STATEST_SHIFT                                (1 << 8)
+#define OMAP4430_PERIPHMEM_STATEST_MASK                                 BITFIELD(8, 9)
+
+/* Used by PRM_PHASE1_CNDP */
+#define OMAP4430_PHASE1_CNDP_SHIFT                                      (1 << 0)
+#define OMAP4430_PHASE1_CNDP_MASK                                       BITFIELD(0, 31)
+
+/* Used by PRM_PHASE2A_CNDP */
+#define OMAP4430_PHASE2A_CNDP_SHIFT                                     (1 << 0)
+#define OMAP4430_PHASE2A_CNDP_MASK                                      BITFIELD(0, 31)
+
+/* Used by PRM_PHASE2B_CNDP */
+#define OMAP4430_PHASE2B_CNDP_SHIFT                                     (1 << 0)
+#define OMAP4430_PHASE2B_CNDP_MASK                                      BITFIELD(0, 31)
+
+/* Used by PRM_PSCON_COUNT */
+#define OMAP4430_PONOUT_2_PGOODIN_TIME_SHIFT                            (1 << 8)
+#define OMAP4430_PONOUT_2_PGOODIN_TIME_MASK                             BITFIELD(8, 15)
+
+/*
+ * Used by PM_EMU_PWRSTCTRL, PM_CORE_PWRSTCTRL, PM_CAM_PWRSTCTRL,
+ * PM_L3INIT_PWRSTCTRL, PM_ABE_PWRSTCTRL, PM_GFX_PWRSTCTRL, PM_MPU_PWRSTCTRL,
+ * PM_CEFUSE_PWRSTCTRL, PM_DSS_PWRSTCTRL, PM_L4PER_PWRSTCTRL,
+ * PM_TESLA_PWRSTCTRL, PM_IVAHD_PWRSTCTRL
+ */
+#define OMAP4430_POWERSTATE_SHIFT                                       (1 << 0)
+#define OMAP4430_POWERSTATE_MASK                                        BITFIELD(0, 1)
+
+/*
+ * Used by PM_EMU_PWRSTST, PM_CORE_PWRSTST, PM_CAM_PWRSTST, PM_L3INIT_PWRSTST,
+ * PM_ABE_PWRSTST, PM_GFX_PWRSTST, PM_MPU_PWRSTST, PM_CEFUSE_PWRSTST,
+ * PM_DSS_PWRSTST, PM_L4PER_PWRSTST, PM_TESLA_PWRSTST, PM_IVAHD_PWRSTST
+ */
+#define OMAP4430_POWERSTATEST_SHIFT                                     (1 << 0)
+#define OMAP4430_POWERSTATEST_MASK                                      BITFIELD(0, 1)
+
+/* Used by PRM_PWRREQCTRL */
+#define OMAP4430_PWRREQ_COND_SHIFT                                      (1 << 0)
+#define OMAP4430_PWRREQ_COND_MASK                                       BITFIELD(0, 1)
+
+/* Used by PRM_VC_CFG_CHANNEL */
+#define OMAP4430_RACEN_VDD_CORE_L_SHIFT                                 (1 << 3)
+#define OMAP4430_RACEN_VDD_CORE_L_MASK                                  BITFIELD(3, 3)
+
+/* Used by PRM_VC_CFG_CHANNEL */
+#define OMAP4430_RACEN_VDD_IVA_L_SHIFT                                  (1 << 11)
+#define OMAP4430_RACEN_VDD_IVA_L_MASK                                   BITFIELD(11, 11)
+
+/* Used by PRM_VC_CFG_CHANNEL */
+#define OMAP4430_RACEN_VDD_MPU_L_SHIFT                                  (1 << 20)
+#define OMAP4430_RACEN_VDD_MPU_L_MASK                                   BITFIELD(20, 20)
+
+/* Used by PRM_VC_CFG_CHANNEL */
+#define OMAP4430_RAC_VDD_CORE_L_SHIFT                                   (1 << 2)
+#define OMAP4430_RAC_VDD_CORE_L_MASK                                    BITFIELD(2, 2)
+
+/* Used by PRM_VC_CFG_CHANNEL */
+#define OMAP4430_RAC_VDD_IVA_L_SHIFT                                    (1 << 10)
+#define OMAP4430_RAC_VDD_IVA_L_MASK                                     BITFIELD(10, 10)
+
+/* Used by PRM_VC_CFG_CHANNEL */
+#define OMAP4430_RAC_VDD_MPU_L_SHIFT                                    (1 << 19)
+#define OMAP4430_RAC_VDD_MPU_L_MASK                                     BITFIELD(19, 19)
+
+/*
+ * Used by PRM_VOLTSETUP_CORE_OFF, PRM_VOLTSETUP_CORE_RET_SLEEP,
+ * PRM_VOLTSETUP_IVA_OFF, PRM_VOLTSETUP_IVA_RET_SLEEP, PRM_VOLTSETUP_MPU_OFF,
+ * PRM_VOLTSETUP_MPU_RET_SLEEP
+ */
+#define OMAP4430_RAMP_DOWN_COUNT_SHIFT                                  (1 << 16)
+#define OMAP4430_RAMP_DOWN_COUNT_MASK                                   BITFIELD(16, 21)
+
+/*
+ * Used by PRM_VOLTSETUP_CORE_OFF, PRM_VOLTSETUP_CORE_RET_SLEEP,
+ * PRM_VOLTSETUP_IVA_OFF, PRM_VOLTSETUP_IVA_RET_SLEEP, PRM_VOLTSETUP_MPU_OFF,
+ * PRM_VOLTSETUP_MPU_RET_SLEEP
+ */
+#define OMAP4430_RAMP_DOWN_PRESCAL_SHIFT                                (1 << 24)
+#define OMAP4430_RAMP_DOWN_PRESCAL_MASK                                 BITFIELD(24, 25)
+
+/*
+ * Used by PRM_VOLTSETUP_CORE_OFF, PRM_VOLTSETUP_CORE_RET_SLEEP,
+ * PRM_VOLTSETUP_IVA_OFF, PRM_VOLTSETUP_IVA_RET_SLEEP, PRM_VOLTSETUP_MPU_OFF,
+ * PRM_VOLTSETUP_MPU_RET_SLEEP
+ */
+#define OMAP4430_RAMP_UP_COUNT_SHIFT                                    (1 << 0)
+#define OMAP4430_RAMP_UP_COUNT_MASK                                     BITFIELD(0, 5)
+
+/*
+ * Used by PRM_VOLTSETUP_CORE_OFF, PRM_VOLTSETUP_CORE_RET_SLEEP,
+ * PRM_VOLTSETUP_IVA_OFF, PRM_VOLTSETUP_IVA_RET_SLEEP, PRM_VOLTSETUP_MPU_OFF,
+ * PRM_VOLTSETUP_MPU_RET_SLEEP
+ */
+#define OMAP4430_RAMP_UP_PRESCAL_SHIFT                                  (1 << 8)
+#define OMAP4430_RAMP_UP_PRESCAL_MASK                                   BITFIELD(8, 9)
+
+/* Used by PRM_VC_CFG_CHANNEL */
+#define OMAP4430_RAV_VDD_CORE_L_SHIFT                                   (1 << 1)
+#define OMAP4430_RAV_VDD_CORE_L_MASK                                    BITFIELD(1, 1)
+
+/* Used by PRM_VC_CFG_CHANNEL */
+#define OMAP4430_RAV_VDD_IVA_L_SHIFT                                    (1 << 9)
+#define OMAP4430_RAV_VDD_IVA_L_MASK                                     BITFIELD(9, 9)
+
+/* Used by PRM_VC_CFG_CHANNEL */
+#define OMAP4430_RAV_VDD_MPU_L_SHIFT                                    (1 << 18)
+#define OMAP4430_RAV_VDD_MPU_L_MASK                                     BITFIELD(18, 18)
+
+/* Used by PRM_VC_VAL_BYPASS */
+#define OMAP4430_REGADDR_SHIFT                                          (1 << 8)
+#define OMAP4430_REGADDR_MASK                                           BITFIELD(8, 15)
+
+/*
+ * Used by PRM_VC_VAL_CMD_VDD_CORE_L, PRM_VC_VAL_CMD_VDD_IVA_L,
+ * PRM_VC_VAL_CMD_VDD_MPU_L
+ */
+#define OMAP4430_RET_SHIFT                                              (1 << 8)
+#define OMAP4430_RET_MASK                                               BITFIELD(8, 15)
+
+/* Used by PM_L4PER_PWRSTCTRL */
+#define OMAP4430_RETAINED_BANK_ONSTATE_SHIFT                            (1 << 16)
+#define OMAP4430_RETAINED_BANK_ONSTATE_MASK                             BITFIELD(16, 17)
+
+/* Used by PM_L4PER_PWRSTCTRL */
+#define OMAP4430_RETAINED_BANK_RETSTATE_SHIFT                           (1 << 8)
+#define OMAP4430_RETAINED_BANK_RETSTATE_MASK                            BITFIELD(8, 8)
+
+/* Used by PM_L4PER_PWRSTST */
+#define OMAP4430_RETAINED_BANK_STATEST_SHIFT                            (1 << 4)
+#define OMAP4430_RETAINED_BANK_STATEST_MASK                             BITFIELD(4, 5)
+
+/*
+ * Used by PRM_LDO_SRAM_CORE_CTRL, PRM_LDO_SRAM_IVA_CTRL,
+ * PRM_LDO_SRAM_MPU_CTRL
+ */
+#define OMAP4430_RETMODE_ENABLE_SHIFT                                   (1 << 0)
+#define OMAP4430_RETMODE_ENABLE_MASK                                    BITFIELD(0, 0)
+
+/* Used by REVISION_PRM */
+#define OMAP4430_REV_SHIFT                                              (1 << 0)
+#define OMAP4430_REV_MASK                                               BITFIELD(0, 7)
+
+/* Used by RM_DUCATI_RSTCTRL, RM_TESLA_RSTCTRL, RM_IVAHD_RSTCTRL */
+#define OMAP4430_RST1_SHIFT                                             (1 << 0)
+#define OMAP4430_RST1_MASK                                              BITFIELD(0, 0)
+
+/* Used by RM_DUCATI_RSTST, RM_TESLA_RSTST, RM_IVAHD_RSTST */
+#define OMAP4430_RST1ST_SHIFT                                           (1 << 0)
+#define OMAP4430_RST1ST_MASK                                            BITFIELD(0, 0)
+
+/* Used by RM_DUCATI_RSTCTRL, RM_TESLA_RSTCTRL, RM_IVAHD_RSTCTRL */
+#define OMAP4430_RST2_SHIFT                                             (1 << 1)
+#define OMAP4430_RST2_MASK                                              BITFIELD(1, 1)
+
+/* Used by RM_DUCATI_RSTST, RM_TESLA_RSTST, RM_IVAHD_RSTST */
+#define OMAP4430_RST2ST_SHIFT                                           (1 << 1)
+#define OMAP4430_RST2ST_MASK                                            BITFIELD(1, 1)
+
+/* Used by RM_DUCATI_RSTCTRL, RM_IVAHD_RSTCTRL */
+#define OMAP4430_RST3_SHIFT                                             (1 << 2)
+#define OMAP4430_RST3_MASK                                              BITFIELD(2, 2)
+
+/* Used by RM_DUCATI_RSTST, RM_IVAHD_RSTST */
+#define OMAP4430_RST3ST_SHIFT                                           (1 << 2)
+#define OMAP4430_RST3ST_MASK                                            BITFIELD(2, 2)
+
+/* Used by PRM_RSTTIME */
+#define OMAP4430_RSTTIME1_SHIFT                                         (1 << 0)
+#define OMAP4430_RSTTIME1_MASK                                          BITFIELD(0, 9)
+
+/* Used by PRM_RSTTIME */
+#define OMAP4430_RSTTIME2_SHIFT                                         (1 << 10)
+#define OMAP4430_RSTTIME2_MASK                                          BITFIELD(10, 14)
+
+/* Used by PRM_RSTCTRL */
+#define OMAP4430_RST_GLOBAL_COLD_SW_SHIFT                               (1 << 1)
+#define OMAP4430_RST_GLOBAL_COLD_SW_MASK                                BITFIELD(1, 1)
+
+/* Used by PRM_RSTCTRL */
+#define OMAP4430_RST_GLOBAL_WARM_SW_SHIFT                               (1 << 0)
+#define OMAP4430_RST_GLOBAL_WARM_SW_MASK                                BITFIELD(0, 0)
+
+/* Used by PRM_VC_CFG_CHANNEL */
+#define OMAP4430_SA_VDD_CORE_L_SHIFT                                    (1 << 0)
+#define OMAP4430_SA_VDD_CORE_L_MASK                                     BITFIELD(0, 0)
+
+/* Renamed from SA_VDD_CORE_L Used by PRM_VC_SMPS_SA */
+#define OMAP4430_SA_VDD_CORE_L_0_6_SHIFT                                (1 << 0)
+#define OMAP4430_SA_VDD_CORE_L_0_6_MASK                                 BITFIELD(0, 6)
+
+/* Used by PRM_VC_CFG_CHANNEL */
+#define OMAP4430_SA_VDD_IVA_L_SHIFT                                     (1 << 8)
+#define OMAP4430_SA_VDD_IVA_L_MASK                                      BITFIELD(8, 8)
+
+/* Renamed from SA_VDD_IVA_L Used by PRM_VC_SMPS_SA */
+#define OMAP4430_SA_VDD_IVA_L_PRM_VC_SMPS_SA_SHIFT                      (1 << 8)
+#define OMAP4430_SA_VDD_IVA_L_PRM_VC_SMPS_SA_MASK                       BITFIELD(8, 14)
+
+/* Used by PRM_VC_CFG_CHANNEL */
+#define OMAP4430_SA_VDD_MPU_L_SHIFT                                     (1 << 16)
+#define OMAP4430_SA_VDD_MPU_L_MASK                                      BITFIELD(16, 16)
+
+/* Renamed from SA_VDD_MPU_L Used by PRM_VC_SMPS_SA */
+#define OMAP4430_SA_VDD_MPU_L_PRM_VC_SMPS_SA_SHIFT                      (1 << 16)
+#define OMAP4430_SA_VDD_MPU_L_PRM_VC_SMPS_SA_MASK                       BITFIELD(16, 22)
+
+/* Used by PRM_VC_CFG_I2C_CLK */
+#define OMAP4430_SCLH_SHIFT                                             (1 << 0)
+#define OMAP4430_SCLH_MASK                                              BITFIELD(0, 7)
+
+/* Used by PRM_VC_CFG_I2C_CLK */
+#define OMAP4430_SCLL_SHIFT                                             (1 << 8)
+#define OMAP4430_SCLL_MASK                                              BITFIELD(8, 15)
+
+/* Used by PRM_RSTST */
+#define OMAP4430_SECURE_WDT_RST_SHIFT                                   (1 << 4)
+#define OMAP4430_SECURE_WDT_RST_MASK                                    BITFIELD(4, 4)
+
+/* Used by PM_IVAHD_PWRSTCTRL */
+#define OMAP4430_SL2_MEM_ONSTATE_SHIFT                                  (1 << 18)
+#define OMAP4430_SL2_MEM_ONSTATE_MASK                                   BITFIELD(18, 19)
+
+/* Used by PM_IVAHD_PWRSTCTRL */
+#define OMAP4430_SL2_MEM_RETSTATE_SHIFT                                 (1 << 9)
+#define OMAP4430_SL2_MEM_RETSTATE_MASK                                  BITFIELD(9, 9)
+
+/* Used by PM_IVAHD_PWRSTST */
+#define OMAP4430_SL2_MEM_STATEST_SHIFT                                  (1 << 6)
+#define OMAP4430_SL2_MEM_STATEST_MASK                                   BITFIELD(6, 7)
+
+/* Used by PRM_VC_VAL_BYPASS */
+#define OMAP4430_SLAVEADDR_SHIFT                                        (1 << 0)
+#define OMAP4430_SLAVEADDR_MASK                                         BITFIELD(0, 6)
+
+/* Used by PRM_LDO_ABB_IVA_SETUP, PRM_LDO_ABB_MPU_SETUP */
+#define OMAP4430_SLEEP_RBB_SEL_SHIFT                                    (1 << 3)
+#define OMAP4430_SLEEP_RBB_SEL_MASK                                     BITFIELD(3, 3)
+
+/* Used by PRM_SRAM_COUNT */
+#define OMAP4430_SLPCNT_VALUE_SHIFT                                     (1 << 16)
+#define OMAP4430_SLPCNT_VALUE_MASK                                      BITFIELD(16, 23)
+
+/* Used by PRM_VP_CORE_VSTEPMAX, PRM_VP_IVA_VSTEPMAX, PRM_VP_MPU_VSTEPMAX */
+#define OMAP4430_SMPSWAITTIMEMAX_SHIFT                                  (1 << 8)
+#define OMAP4430_SMPSWAITTIMEMAX_MASK                                   BITFIELD(8, 23)
+
+/* Used by PRM_VP_CORE_VSTEPMIN, PRM_VP_IVA_VSTEPMIN, PRM_VP_MPU_VSTEPMIN */
+#define OMAP4430_SMPSWAITTIMEMIN_SHIFT                                  (1 << 8)
+#define OMAP4430_SMPSWAITTIMEMIN_MASK                                   BITFIELD(8, 23)
+
+/* Used by PRM_LDO_ABB_IVA_SETUP, PRM_LDO_ABB_MPU_SETUP */
+#define OMAP4430_SR2EN_SHIFT                                            (1 << 0)
+#define OMAP4430_SR2EN_MASK                                             BITFIELD(0, 0)
+
+/* Used by PRM_LDO_ABB_IVA_CTRL, PRM_LDO_ABB_MPU_CTRL */
+#define OMAP4430_SR2_IN_TRANSITION_SHIFT                                (1 << 6)
+#define OMAP4430_SR2_IN_TRANSITION_MASK                                 BITFIELD(6, 6)
+
+/* Used by PRM_LDO_ABB_IVA_CTRL, PRM_LDO_ABB_MPU_CTRL */
+#define OMAP4430_SR2_STATUS_SHIFT                                       (1 << 3)
+#define OMAP4430_SR2_STATUS_MASK                                        BITFIELD(3, 4)
+
+/* Used by PRM_LDO_ABB_IVA_SETUP, PRM_LDO_ABB_MPU_SETUP */
+#define OMAP4430_SR2_WTCNT_VALUE_SHIFT                                  (1 << 8)
+#define OMAP4430_SR2_WTCNT_VALUE_MASK                                   BITFIELD(8, 15)
+
+/*
+ * Used by PRM_LDO_SRAM_CORE_CTRL, PRM_LDO_SRAM_IVA_CTRL,
+ * PRM_LDO_SRAM_MPU_CTRL
+ */
+#define OMAP4430_SRAMLDO_STATUS_SHIFT                                   (1 << 8)
+#define OMAP4430_SRAMLDO_STATUS_MASK                                    BITFIELD(8, 8)
+
+/*
+ * Used by PRM_LDO_SRAM_CORE_CTRL, PRM_LDO_SRAM_IVA_CTRL,
+ * PRM_LDO_SRAM_MPU_CTRL
+ */
+#define OMAP4430_SRAM_IN_TRANSITION_SHIFT                               (1 << 9)
+#define OMAP4430_SRAM_IN_TRANSITION_MASK                                BITFIELD(9, 9)
+
+/* Used by PRM_VC_CFG_I2C_MODE */
+#define OMAP4430_SRMODEEN_SHIFT                                         (1 << 4)
+#define OMAP4430_SRMODEEN_MASK                                          BITFIELD(4, 4)
+
+/* Used by PRM_VOLTSETUP_WARMRESET */
+#define OMAP4430_STABLE_COUNT_SHIFT                                     (1 << 0)
+#define OMAP4430_STABLE_COUNT_MASK                                      BITFIELD(0, 5)
+
+/* Used by PRM_VOLTSETUP_WARMRESET */
+#define OMAP4430_STABLE_PRESCAL_SHIFT                                   (1 << 8)
+#define OMAP4430_STABLE_PRESCAL_MASK                                    BITFIELD(8, 9)
+
+/* Used by PM_IVAHD_PWRSTCTRL */
+#define OMAP4430_TCM1_MEM_ONSTATE_SHIFT                                 (1 << 20)
+#define OMAP4430_TCM1_MEM_ONSTATE_MASK                                  BITFIELD(20, 21)
+
+/* Used by PM_IVAHD_PWRSTCTRL */
+#define OMAP4430_TCM1_MEM_RETSTATE_SHIFT                                (1 << 10)
+#define OMAP4430_TCM1_MEM_RETSTATE_MASK                                 BITFIELD(10, 10)
+
+/* Used by PM_IVAHD_PWRSTST */
+#define OMAP4430_TCM1_MEM_STATEST_SHIFT                                 (1 << 8)
+#define OMAP4430_TCM1_MEM_STATEST_MASK                                  BITFIELD(8, 9)
+
+/* Used by PM_IVAHD_PWRSTCTRL */
+#define OMAP4430_TCM2_MEM_ONSTATE_SHIFT                                 (1 << 22)
+#define OMAP4430_TCM2_MEM_ONSTATE_MASK                                  BITFIELD(22, 23)
+
+/* Used by PM_IVAHD_PWRSTCTRL */
+#define OMAP4430_TCM2_MEM_RETSTATE_SHIFT                                (1 << 11)
+#define OMAP4430_TCM2_MEM_RETSTATE_MASK                                 BITFIELD(11, 11)
+
+/* Used by PM_IVAHD_PWRSTST */
+#define OMAP4430_TCM2_MEM_STATEST_SHIFT                                 (1 << 10)
+#define OMAP4430_TCM2_MEM_STATEST_MASK                                  BITFIELD(10, 11)
+
+/* Used by RM_TESLA_RSTST */
+#define OMAP4430_TESLASS_EMU_RSTST_SHIFT                                (1 << 2)
+#define OMAP4430_TESLASS_EMU_RSTST_MASK                                 BITFIELD(2, 2)
+
+/* Used by RM_TESLA_RSTST */
+#define OMAP4430_TESLA_DSP_EMU_REQ_RSTST_SHIFT                          (1 << 3)
+#define OMAP4430_TESLA_DSP_EMU_REQ_RSTST_MASK                           BITFIELD(3, 3)
+
+/* Used by PM_TESLA_PWRSTCTRL */
+#define OMAP4430_TESLA_EDMA_ONSTATE_SHIFT                               (1 << 20)
+#define OMAP4430_TESLA_EDMA_ONSTATE_MASK                                BITFIELD(20, 21)
+
+/* Used by PM_TESLA_PWRSTCTRL */
+#define OMAP4430_TESLA_EDMA_RETSTATE_SHIFT                              (1 << 10)
+#define OMAP4430_TESLA_EDMA_RETSTATE_MASK                               BITFIELD(10, 10)
+
+/* Used by PM_TESLA_PWRSTST */
+#define OMAP4430_TESLA_EDMA_STATEST_SHIFT                               (1 << 8)
+#define OMAP4430_TESLA_EDMA_STATEST_MASK                                BITFIELD(8, 9)
+
+/* Used by PM_TESLA_PWRSTCTRL */
+#define OMAP4430_TESLA_L1_ONSTATE_SHIFT                                 (1 << 16)
+#define OMAP4430_TESLA_L1_ONSTATE_MASK                                  BITFIELD(16, 17)
+
+/* Used by PM_TESLA_PWRSTCTRL */
+#define OMAP4430_TESLA_L1_RETSTATE_SHIFT                                (1 << 8)
+#define OMAP4430_TESLA_L1_RETSTATE_MASK                                 BITFIELD(8, 8)
+
+/* Used by PM_TESLA_PWRSTST */
+#define OMAP4430_TESLA_L1_STATEST_SHIFT                                 (1 << 4)
+#define OMAP4430_TESLA_L1_STATEST_MASK                                  BITFIELD(4, 5)
+
+/* Used by PM_TESLA_PWRSTCTRL */
+#define OMAP4430_TESLA_L2_ONSTATE_SHIFT                                 (1 << 18)
+#define OMAP4430_TESLA_L2_ONSTATE_MASK                                  BITFIELD(18, 19)
+
+/* Used by PM_TESLA_PWRSTCTRL */
+#define OMAP4430_TESLA_L2_RETSTATE_SHIFT                                (1 << 9)
+#define OMAP4430_TESLA_L2_RETSTATE_MASK                                 BITFIELD(9, 9)
+
+/* Used by PM_TESLA_PWRSTST */
+#define OMAP4430_TESLA_L2_STATEST_SHIFT                                 (1 << 6)
+#define OMAP4430_TESLA_L2_STATEST_MASK                                  BITFIELD(6, 7)
+
+/* Used by PRM_VP_CORE_VLIMITTO, PRM_VP_IVA_VLIMITTO, PRM_VP_MPU_VLIMITTO */
+#define OMAP4430_TIMEOUT_SHIFT                                          (1 << 0)
+#define OMAP4430_TIMEOUT_MASK                                           BITFIELD(0, 15)
+
+/* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */
+#define OMAP4430_TIMEOUTEN_SHIFT                                        (1 << 3)
+#define OMAP4430_TIMEOUTEN_MASK                                         BITFIELD(3, 3)
+
+/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
+#define OMAP4430_TRANSITION_EN_SHIFT                                    (1 << 8)
+#define OMAP4430_TRANSITION_EN_MASK                                     BITFIELD(8, 8)
+
+/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
+#define OMAP4430_TRANSITION_ST_SHIFT                                    (1 << 8)
+#define OMAP4430_TRANSITION_ST_MASK                                     BITFIELD(8, 8)
+
+/* Used by PRM_VC_VAL_BYPASS */
+#define OMAP4430_VALID_SHIFT                                            (1 << 24)
+#define OMAP4430_VALID_MASK                                             BITFIELD(24, 24)
+
+/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
+#define OMAP4430_VC_BYPASSACK_EN_SHIFT                                  (1 << 14)
+#define OMAP4430_VC_BYPASSACK_EN_MASK                                   BITFIELD(14, 14)
+
+/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
+#define OMAP4430_VC_BYPASSACK_ST_SHIFT                                  (1 << 14)
+#define OMAP4430_VC_BYPASSACK_ST_MASK                                   BITFIELD(14, 14)
+
+/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
+#define OMAP4430_VC_IVA_VPACK_EN_SHIFT                                  (1 << 30)
+#define OMAP4430_VC_IVA_VPACK_EN_MASK                                   BITFIELD(30, 30)
+
+/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
+#define OMAP4430_VC_IVA_VPACK_ST_SHIFT                                  (1 << 30)
+#define OMAP4430_VC_IVA_VPACK_ST_MASK                                   BITFIELD(30, 30)
+
+/* Used by PRM_IRQENABLE_MPU_2 */
+#define OMAP4430_VC_MPU_VPACK_EN_SHIFT                                  (1 << 6)
+#define OMAP4430_VC_MPU_VPACK_EN_MASK                                   BITFIELD(6, 6)
+
+/* Used by PRM_IRQSTATUS_MPU_2 */
+#define OMAP4430_VC_MPU_VPACK_ST_SHIFT                                  (1 << 6)
+#define OMAP4430_VC_MPU_VPACK_ST_MASK                                   BITFIELD(6, 6)
+
+/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
+#define OMAP4430_VC_RAERR_EN_SHIFT                                      (1 << 12)
+#define OMAP4430_VC_RAERR_EN_MASK                                       BITFIELD(12, 12)
+
+/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
+#define OMAP4430_VC_RAERR_ST_SHIFT                                      (1 << 12)
+#define OMAP4430_VC_RAERR_ST_MASK                                       BITFIELD(12, 12)
+
+/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
+#define OMAP4430_VC_SAERR_EN_SHIFT                                      (1 << 11)
+#define OMAP4430_VC_SAERR_EN_MASK                                       BITFIELD(11, 11)
+
+/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
+#define OMAP4430_VC_SAERR_ST_SHIFT                                      (1 << 11)
+#define OMAP4430_VC_SAERR_ST_MASK                                       BITFIELD(11, 11)
+
+/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
+#define OMAP4430_VC_TOERR_EN_SHIFT                                      (1 << 13)
+#define OMAP4430_VC_TOERR_EN_MASK                                       BITFIELD(13, 13)
+
+/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
+#define OMAP4430_VC_TOERR_ST_SHIFT                                      (1 << 13)
+#define OMAP4430_VC_TOERR_ST_MASK                                       BITFIELD(13, 13)
+
+/* Used by PRM_VP_CORE_VLIMITTO, PRM_VP_IVA_VLIMITTO, PRM_VP_MPU_VLIMITTO */
+#define OMAP4430_VDDMAX_SHIFT                                           (1 << 24)
+#define OMAP4430_VDDMAX_MASK                                            BITFIELD(24, 31)
+
+/* Used by PRM_VP_CORE_VLIMITTO, PRM_VP_IVA_VLIMITTO, PRM_VP_MPU_VLIMITTO */
+#define OMAP4430_VDDMIN_SHIFT                                           (1 << 16)
+#define OMAP4430_VDDMIN_MASK                                            BITFIELD(16, 23)
+
+/* Used by PRM_VOLTCTRL */
+#define OMAP4430_VDD_CORE_I2C_DISABLE_SHIFT                             (1 << 12)
+#define OMAP4430_VDD_CORE_I2C_DISABLE_MASK                              BITFIELD(12, 12)
+
+/* Used by PRM_RSTST */
+#define OMAP4430_VDD_CORE_VOLT_MGR_RST_SHIFT                            (1 << 8)
+#define OMAP4430_VDD_CORE_VOLT_MGR_RST_MASK                             BITFIELD(8, 8)
+
+/* Used by PRM_VOLTCTRL */
+#define OMAP4430_VDD_IVA_I2C_DISABLE_SHIFT                              (1 << 14)
+#define OMAP4430_VDD_IVA_I2C_DISABLE_MASK                               BITFIELD(14, 14)
+
+/* Used by PRM_VOLTCTRL */
+#define OMAP4430_VDD_IVA_PRESENCE_SHIFT                                 (1 << 9)
+#define OMAP4430_VDD_IVA_PRESENCE_MASK                                  BITFIELD(9, 9)
+
+/* Used by PRM_RSTST */
+#define OMAP4430_VDD_IVA_VOLT_MGR_RST_SHIFT                             (1 << 7)
+#define OMAP4430_VDD_IVA_VOLT_MGR_RST_MASK                              BITFIELD(7, 7)
+
+/* Used by PRM_VOLTCTRL */
+#define OMAP4430_VDD_MPU_I2C_DISABLE_SHIFT                              (1 << 13)
+#define OMAP4430_VDD_MPU_I2C_DISABLE_MASK                               BITFIELD(13, 13)
+
+/* Used by PRM_VOLTCTRL */
+#define OMAP4430_VDD_MPU_PRESENCE_SHIFT                                 (1 << 8)
+#define OMAP4430_VDD_MPU_PRESENCE_MASK                                  BITFIELD(8, 8)
+
+/* Used by PRM_RSTST */
+#define OMAP4430_VDD_MPU_VOLT_MGR_RST_SHIFT                             (1 << 6)
+#define OMAP4430_VDD_MPU_VOLT_MGR_RST_MASK                              BITFIELD(6, 6)
+
+/* Used by PRM_VC_VAL_SMPS_RA_VOL */
+#define OMAP4430_VOLRA_VDD_CORE_L_SHIFT                                 (1 << 0)
+#define OMAP4430_VOLRA_VDD_CORE_L_MASK                                  BITFIELD(0, 7)
+
+/* Used by PRM_VC_VAL_SMPS_RA_VOL */
+#define OMAP4430_VOLRA_VDD_IVA_L_SHIFT                                  (1 << 8)
+#define OMAP4430_VOLRA_VDD_IVA_L_MASK                                   BITFIELD(8, 15)
+
+/* Used by PRM_VC_VAL_SMPS_RA_VOL */
+#define OMAP4430_VOLRA_VDD_MPU_L_SHIFT                                  (1 << 16)
+#define OMAP4430_VOLRA_VDD_MPU_L_MASK                                   BITFIELD(16, 23)
+
+/* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */
+#define OMAP4430_VPENABLE_SHIFT                                         (1 << 0)
+#define OMAP4430_VPENABLE_MASK                                          BITFIELD(0, 0)
+
+/* Used by PRM_VP_CORE_STATUS, PRM_VP_IVA_STATUS, PRM_VP_MPU_STATUS */
+#define OMAP4430_VPINIDLE_SHIFT                                         (1 << 0)
+#define OMAP4430_VPINIDLE_MASK                                          BITFIELD(0, 0)
+
+/* Used by PRM_VP_CORE_VOLTAGE, PRM_VP_IVA_VOLTAGE, PRM_VP_MPU_VOLTAGE */
+#define OMAP4430_VPVOLTAGE_SHIFT                                        (1 << 0)
+#define OMAP4430_VPVOLTAGE_MASK                                         BITFIELD(0, 7)
+
+/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
+#define OMAP4430_VP_CORE_EQVALUE_EN_SHIFT                               (1 << 20)
+#define OMAP4430_VP_CORE_EQVALUE_EN_MASK                                BITFIELD(20, 20)
+
+/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
+#define OMAP4430_VP_CORE_EQVALUE_ST_SHIFT                               (1 << 20)
+#define OMAP4430_VP_CORE_EQVALUE_ST_MASK                                BITFIELD(20, 20)
+
+/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
+#define OMAP4430_VP_CORE_MAXVDD_EN_SHIFT                                (1 << 18)
+#define OMAP4430_VP_CORE_MAXVDD_EN_MASK                                 BITFIELD(18, 18)
+
+/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
+#define OMAP4430_VP_CORE_MAXVDD_ST_SHIFT                                (1 << 18)
+#define OMAP4430_VP_CORE_MAXVDD_ST_MASK                                 BITFIELD(18, 18)
+
+/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
+#define OMAP4430_VP_CORE_MINVDD_EN_SHIFT                                (1 << 17)
+#define OMAP4430_VP_CORE_MINVDD_EN_MASK                                 BITFIELD(17, 17)
+
+/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
+#define OMAP4430_VP_CORE_MINVDD_ST_SHIFT                                (1 << 17)
+#define OMAP4430_VP_CORE_MINVDD_ST_MASK                                 BITFIELD(17, 17)
+
+/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
+#define OMAP4430_VP_CORE_NOSMPSACK_EN_SHIFT                             (1 << 19)
+#define OMAP4430_VP_CORE_NOSMPSACK_EN_MASK                              BITFIELD(19, 19)
+
+/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
+#define OMAP4430_VP_CORE_NOSMPSACK_ST_SHIFT                             (1 << 19)
+#define OMAP4430_VP_CORE_NOSMPSACK_ST_MASK                              BITFIELD(19, 19)
+
+/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
+#define OMAP4430_VP_CORE_OPPCHANGEDONE_EN_SHIFT                         (1 << 16)
+#define OMAP4430_VP_CORE_OPPCHANGEDONE_EN_MASK                          BITFIELD(16, 16)
+
+/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
+#define OMAP4430_VP_CORE_OPPCHANGEDONE_ST_SHIFT                         (1 << 16)
+#define OMAP4430_VP_CORE_OPPCHANGEDONE_ST_MASK                          BITFIELD(16, 16)
+
+/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
+#define OMAP4430_VP_CORE_TRANXDONE_EN_SHIFT                             (1 << 21)
+#define OMAP4430_VP_CORE_TRANXDONE_EN_MASK                              BITFIELD(21, 21)
+
+/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
+#define OMAP4430_VP_CORE_TRANXDONE_ST_SHIFT                             (1 << 21)
+#define OMAP4430_VP_CORE_TRANXDONE_ST_MASK                              BITFIELD(21, 21)
+
+/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
+#define OMAP4430_VP_IVA_EQVALUE_EN_SHIFT                                (1 << 28)
+#define OMAP4430_VP_IVA_EQVALUE_EN_MASK                                 BITFIELD(28, 28)
+
+/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
+#define OMAP4430_VP_IVA_EQVALUE_ST_SHIFT                                (1 << 28)
+#define OMAP4430_VP_IVA_EQVALUE_ST_MASK                                 BITFIELD(28, 28)
+
+/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
+#define OMAP4430_VP_IVA_MAXVDD_EN_SHIFT                                 (1 << 26)
+#define OMAP4430_VP_IVA_MAXVDD_EN_MASK                                  BITFIELD(26, 26)
+
+/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
+#define OMAP4430_VP_IVA_MAXVDD_ST_SHIFT                                 (1 << 26)
+#define OMAP4430_VP_IVA_MAXVDD_ST_MASK                                  BITFIELD(26, 26)
+
+/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
+#define OMAP4430_VP_IVA_MINVDD_EN_SHIFT                                 (1 << 25)
+#define OMAP4430_VP_IVA_MINVDD_EN_MASK                                  BITFIELD(25, 25)
+
+/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
+#define OMAP4430_VP_IVA_MINVDD_ST_SHIFT                                 (1 << 25)
+#define OMAP4430_VP_IVA_MINVDD_ST_MASK                                  BITFIELD(25, 25)
+
+/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
+#define OMAP4430_VP_IVA_NOSMPSACK_EN_SHIFT                              (1 << 27)
+#define OMAP4430_VP_IVA_NOSMPSACK_EN_MASK                               BITFIELD(27, 27)
+
+/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
+#define OMAP4430_VP_IVA_NOSMPSACK_ST_SHIFT                              (1 << 27)
+#define OMAP4430_VP_IVA_NOSMPSACK_ST_MASK                               BITFIELD(27, 27)
+
+/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
+#define OMAP4430_VP_IVA_OPPCHANGEDONE_EN_SHIFT                          (1 << 24)
+#define OMAP4430_VP_IVA_OPPCHANGEDONE_EN_MASK                           BITFIELD(24, 24)
+
+/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
+#define OMAP4430_VP_IVA_OPPCHANGEDONE_ST_SHIFT                          (1 << 24)
+#define OMAP4430_VP_IVA_OPPCHANGEDONE_ST_MASK                           BITFIELD(24, 24)
+
+/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
+#define OMAP4430_VP_IVA_TRANXDONE_EN_SHIFT                              (1 << 29)
+#define OMAP4430_VP_IVA_TRANXDONE_EN_MASK                               BITFIELD(29, 29)
+
+/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
+#define OMAP4430_VP_IVA_TRANXDONE_ST_SHIFT                              (1 << 29)
+#define OMAP4430_VP_IVA_TRANXDONE_ST_MASK                               BITFIELD(29, 29)
+
+/* Used by PRM_IRQENABLE_MPU_2 */
+#define OMAP4430_VP_MPU_EQVALUE_EN_SHIFT                                (1 << 4)
+#define OMAP4430_VP_MPU_EQVALUE_EN_MASK                                 BITFIELD(4, 4)
+
+/* Used by PRM_IRQSTATUS_MPU_2 */
+#define OMAP4430_VP_MPU_EQVALUE_ST_SHIFT                                (1 << 4)
+#define OMAP4430_VP_MPU_EQVALUE_ST_MASK                                 BITFIELD(4, 4)
+
+/* Used by PRM_IRQENABLE_MPU_2 */
+#define OMAP4430_VP_MPU_MAXVDD_EN_SHIFT                                 (1 << 2)
+#define OMAP4430_VP_MPU_MAXVDD_EN_MASK                                  BITFIELD(2, 2)
+
+/* Used by PRM_IRQSTATUS_MPU_2 */
+#define OMAP4430_VP_MPU_MAXVDD_ST_SHIFT                                 (1 << 2)
+#define OMAP4430_VP_MPU_MAXVDD_ST_MASK                                  BITFIELD(2, 2)
+
+/* Used by PRM_IRQENABLE_MPU_2 */
+#define OMAP4430_VP_MPU_MINVDD_EN_SHIFT                                 (1 << 1)
+#define OMAP4430_VP_MPU_MINVDD_EN_MASK                                  BITFIELD(1, 1)
+
+/* Used by PRM_IRQSTATUS_MPU_2 */
+#define OMAP4430_VP_MPU_MINVDD_ST_SHIFT                                 (1 << 1)
+#define OMAP4430_VP_MPU_MINVDD_ST_MASK                                  BITFIELD(1, 1)
+
+/* Used by PRM_IRQENABLE_MPU_2 */
+#define OMAP4430_VP_MPU_NOSMPSACK_EN_SHIFT                              (1 << 3)
+#define OMAP4430_VP_MPU_NOSMPSACK_EN_MASK                               BITFIELD(3, 3)
+
+/* Used by PRM_IRQSTATUS_MPU_2 */
+#define OMAP4430_VP_MPU_NOSMPSACK_ST_SHIFT                              (1 << 3)
+#define OMAP4430_VP_MPU_NOSMPSACK_ST_MASK                               BITFIELD(3, 3)
+
+/* Used by PRM_IRQENABLE_MPU_2 */
+#define OMAP4430_VP_MPU_OPPCHANGEDONE_EN_SHIFT                          (1 << 0)
+#define OMAP4430_VP_MPU_OPPCHANGEDONE_EN_MASK                           BITFIELD(0, 0)
+
+/* Used by PRM_IRQSTATUS_MPU_2 */
+#define OMAP4430_VP_MPU_OPPCHANGEDONE_ST_SHIFT                          (1 << 0)
+#define OMAP4430_VP_MPU_OPPCHANGEDONE_ST_MASK                           BITFIELD(0, 0)
+
+/* Used by PRM_IRQENABLE_MPU_2 */
+#define OMAP4430_VP_MPU_TRANXDONE_EN_SHIFT                              (1 << 5)
+#define OMAP4430_VP_MPU_TRANXDONE_EN_MASK                               BITFIELD(5, 5)
+
+/* Used by PRM_IRQSTATUS_MPU_2 */
+#define OMAP4430_VP_MPU_TRANXDONE_ST_SHIFT                              (1 << 5)
+#define OMAP4430_VP_MPU_TRANXDONE_ST_MASK                               BITFIELD(5, 5)
+
+/* Used by PRM_SRAM_COUNT */
+#define OMAP4430_VSETUPCNT_VALUE_SHIFT                                  (1 << 8)
+#define OMAP4430_VSETUPCNT_VALUE_MASK                                   BITFIELD(8, 15)
+
+/* Used by PRM_VP_CORE_VSTEPMAX, PRM_VP_IVA_VSTEPMAX, PRM_VP_MPU_VSTEPMAX */
+#define OMAP4430_VSTEPMAX_SHIFT                                         (1 << 0)
+#define OMAP4430_VSTEPMAX_MASK                                          BITFIELD(0, 7)
+
+/* Used by PRM_VP_CORE_VSTEPMIN, PRM_VP_IVA_VSTEPMIN, PRM_VP_MPU_VSTEPMIN */
+#define OMAP4430_VSTEPMIN_SHIFT                                         (1 << 0)
+#define OMAP4430_VSTEPMIN_MASK                                          BITFIELD(0, 7)
+
+/* Used by PRM_MODEM_IF_CTRL */
+#define OMAP4430_WAKE_MODEM_SHIFT                                       (1 << 0)
+#define OMAP4430_WAKE_MODEM_MASK                                        BITFIELD(0, 0)
+
+/* Used by PM_DSS_DSS_WKDEP */
+#define OMAP4430_WKUPDEP_DISPC_DUCATI_SHIFT                             (1 << 1)
+#define OMAP4430_WKUPDEP_DISPC_DUCATI_MASK                              BITFIELD(1, 1)
+
+/* Used by PM_DSS_DSS_WKDEP */
+#define OMAP4430_WKUPDEP_DISPC_MPU_SHIFT                                (1 << 0)
+#define OMAP4430_WKUPDEP_DISPC_MPU_MASK                                 BITFIELD(0, 0)
+
+/* Used by PM_DSS_DSS_WKDEP */
+#define OMAP4430_WKUPDEP_DISPC_SDMA_SHIFT                               (1 << 3)
+#define OMAP4430_WKUPDEP_DISPC_SDMA_MASK                                BITFIELD(3, 3)
+
+/* Used by PM_DSS_DSS_WKDEP */
+#define OMAP4430_WKUPDEP_DISPC_TESLA_SHIFT                              (1 << 2)
+#define OMAP4430_WKUPDEP_DISPC_TESLA_MASK                               BITFIELD(2, 2)
+
+/* Used by PM_ABE_DMIC_WKDEP */
+#define OMAP4430_WKUPDEP_DMIC_DMA_SDMA_SHIFT                            (1 << 7)
+#define OMAP4430_WKUPDEP_DMIC_DMA_SDMA_MASK                             BITFIELD(7, 7)
+
+/* Used by PM_ABE_DMIC_WKDEP */
+#define OMAP4430_WKUPDEP_DMIC_DMA_TESLA_SHIFT                           (1 << 6)
+#define OMAP4430_WKUPDEP_DMIC_DMA_TESLA_MASK                            BITFIELD(6, 6)
+
+/* Used by PM_ABE_DMIC_WKDEP */
+#define OMAP4430_WKUPDEP_DMIC_IRQ_MPU_SHIFT                             (1 << 0)
+#define OMAP4430_WKUPDEP_DMIC_IRQ_MPU_MASK                              BITFIELD(0, 0)
+
+/* Used by PM_ABE_DMIC_WKDEP */
+#define OMAP4430_WKUPDEP_DMIC_IRQ_TESLA_SHIFT                           (1 << 2)
+#define OMAP4430_WKUPDEP_DMIC_IRQ_TESLA_MASK                            BITFIELD(2, 2)
+
+/* Used by PM_L4PER_DMTIMER10_WKDEP */
+#define OMAP4430_WKUPDEP_DMTIMER10_MPU_SHIFT                            (1 << 0)
+#define OMAP4430_WKUPDEP_DMTIMER10_MPU_MASK                             BITFIELD(0, 0)
+
+/* Used by PM_L4PER_DMTIMER11_WKDEP */
+#define OMAP4430_WKUPDEP_DMTIMER11_DUCATI_SHIFT                         (1 << 1)
+#define OMAP4430_WKUPDEP_DMTIMER11_DUCATI_MASK                          BITFIELD(1, 1)
+
+/* Used by PM_L4PER_DMTIMER11_WKDEP */
+#define OMAP4430_WKUPDEP_DMTIMER11_MPU_SHIFT                            (1 << 0)
+#define OMAP4430_WKUPDEP_DMTIMER11_MPU_MASK                             BITFIELD(0, 0)
+
+/* Used by PM_L4PER_DMTIMER2_WKDEP */
+#define OMAP4430_WKUPDEP_DMTIMER2_MPU_SHIFT                             (1 << 0)
+#define OMAP4430_WKUPDEP_DMTIMER2_MPU_MASK                              BITFIELD(0, 0)
+
+/* Used by PM_L4PER_DMTIMER3_WKDEP */
+#define OMAP4430_WKUPDEP_DMTIMER3_DUCATI_SHIFT                          (1 << 1)
+#define OMAP4430_WKUPDEP_DMTIMER3_DUCATI_MASK                           BITFIELD(1, 1)
+
+/* Used by PM_L4PER_DMTIMER3_WKDEP */
+#define OMAP4430_WKUPDEP_DMTIMER3_MPU_SHIFT                             (1 << 0)
+#define OMAP4430_WKUPDEP_DMTIMER3_MPU_MASK                              BITFIELD(0, 0)
+
+/* Used by PM_L4PER_DMTIMER4_WKDEP */
+#define OMAP4430_WKUPDEP_DMTIMER4_DUCATI_SHIFT                          (1 << 1)
+#define OMAP4430_WKUPDEP_DMTIMER4_DUCATI_MASK                           BITFIELD(1, 1)
+
+/* Used by PM_L4PER_DMTIMER4_WKDEP */
+#define OMAP4430_WKUPDEP_DMTIMER4_MPU_SHIFT                             (1 << 0)
+#define OMAP4430_WKUPDEP_DMTIMER4_MPU_MASK                              BITFIELD(0, 0)
+
+/* Used by PM_L4PER_DMTIMER9_WKDEP */
+#define OMAP4430_WKUPDEP_DMTIMER9_DUCATI_SHIFT                          (1 << 1)
+#define OMAP4430_WKUPDEP_DMTIMER9_DUCATI_MASK                           BITFIELD(1, 1)
+
+/* Used by PM_L4PER_DMTIMER9_WKDEP */
+#define OMAP4430_WKUPDEP_DMTIMER9_MPU_SHIFT                             (1 << 0)
+#define OMAP4430_WKUPDEP_DMTIMER9_MPU_MASK                              BITFIELD(0, 0)
+
+/* Used by PM_DSS_DSS_WKDEP */
+#define OMAP4430_WKUPDEP_DSI1_DUCATI_SHIFT                              (1 << 5)
+#define OMAP4430_WKUPDEP_DSI1_DUCATI_MASK                               BITFIELD(5, 5)
+
+/* Used by PM_DSS_DSS_WKDEP */
+#define OMAP4430_WKUPDEP_DSI1_MPU_SHIFT                                 (1 << 4)
+#define OMAP4430_WKUPDEP_DSI1_MPU_MASK                                  BITFIELD(4, 4)
+
+/* Used by PM_DSS_DSS_WKDEP */
+#define OMAP4430_WKUPDEP_DSI1_SDMA_SHIFT                                (1 << 7)
+#define OMAP4430_WKUPDEP_DSI1_SDMA_MASK                                 BITFIELD(7, 7)
+
+/* Used by PM_DSS_DSS_WKDEP */
+#define OMAP4430_WKUPDEP_DSI1_TESLA_SHIFT                               (1 << 6)
+#define OMAP4430_WKUPDEP_DSI1_TESLA_MASK                                BITFIELD(6, 6)
+
+/* Used by PM_DSS_DSS_WKDEP */
+#define OMAP4430_WKUPDEP_DSI2_DUCATI_SHIFT                              (1 << 9)
+#define OMAP4430_WKUPDEP_DSI2_DUCATI_MASK                               BITFIELD(9, 9)
+
+/* Used by PM_DSS_DSS_WKDEP */
+#define OMAP4430_WKUPDEP_DSI2_MPU_SHIFT                                 (1 << 8)
+#define OMAP4430_WKUPDEP_DSI2_MPU_MASK                                  BITFIELD(8, 8)
+
+/* Used by PM_DSS_DSS_WKDEP */
+#define OMAP4430_WKUPDEP_DSI2_SDMA_SHIFT                                (1 << 11)
+#define OMAP4430_WKUPDEP_DSI2_SDMA_MASK                                 BITFIELD(11, 11)
+
+/* Used by PM_DSS_DSS_WKDEP */
+#define OMAP4430_WKUPDEP_DSI2_TESLA_SHIFT                               (1 << 10)
+#define OMAP4430_WKUPDEP_DSI2_TESLA_MASK                                BITFIELD(10, 10)
+
+/* Used by PM_WKUP_GPIO1_WKDEP */
+#define OMAP4430_WKUPDEP_GPIO1_IRQ1_DUCATI_SHIFT                        (1 << 1)
+#define OMAP4430_WKUPDEP_GPIO1_IRQ1_DUCATI_MASK                         BITFIELD(1, 1)
+
+/* Used by PM_WKUP_GPIO1_WKDEP */
+#define OMAP4430_WKUPDEP_GPIO1_IRQ1_MPU_SHIFT                           (1 << 0)
+#define OMAP4430_WKUPDEP_GPIO1_IRQ1_MPU_MASK                            BITFIELD(0, 0)
+
+/* Used by PM_WKUP_GPIO1_WKDEP */
+#define OMAP4430_WKUPDEP_GPIO1_IRQ2_TESLA_SHIFT                         (1 << 6)
+#define OMAP4430_WKUPDEP_GPIO1_IRQ2_TESLA_MASK                          BITFIELD(6, 6)
+
+/* Used by PM_L4PER_GPIO2_WKDEP */
+#define OMAP4430_WKUPDEP_GPIO2_IRQ1_DUCATI_SHIFT                        (1 << 1)
+#define OMAP4430_WKUPDEP_GPIO2_IRQ1_DUCATI_MASK                         BITFIELD(1, 1)
+
+/* Used by PM_L4PER_GPIO2_WKDEP */
+#define OMAP4430_WKUPDEP_GPIO2_IRQ1_MPU_SHIFT                           (1 << 0)
+#define OMAP4430_WKUPDEP_GPIO2_IRQ1_MPU_MASK                            BITFIELD(0, 0)
+
+/* Used by PM_L4PER_GPIO2_WKDEP */
+#define OMAP4430_WKUPDEP_GPIO2_IRQ2_TESLA_SHIFT                         (1 << 6)
+#define OMAP4430_WKUPDEP_GPIO2_IRQ2_TESLA_MASK                          BITFIELD(6, 6)
+
+/* Used by PM_L4PER_GPIO3_WKDEP */
+#define OMAP4430_WKUPDEP_GPIO3_IRQ1_MPU_SHIFT                           (1 << 0)
+#define OMAP4430_WKUPDEP_GPIO3_IRQ1_MPU_MASK                            BITFIELD(0, 0)
+
+/* Used by PM_L4PER_GPIO3_WKDEP */
+#define OMAP4430_WKUPDEP_GPIO3_IRQ2_TESLA_SHIFT                         (1 << 6)
+#define OMAP4430_WKUPDEP_GPIO3_IRQ2_TESLA_MASK                          BITFIELD(6, 6)
+
+/* Used by PM_L4PER_GPIO4_WKDEP */
+#define OMAP4430_WKUPDEP_GPIO4_IRQ1_MPU_SHIFT                           (1 << 0)
+#define OMAP4430_WKUPDEP_GPIO4_IRQ1_MPU_MASK                            BITFIELD(0, 0)
+
+/* Used by PM_L4PER_GPIO4_WKDEP */
+#define OMAP4430_WKUPDEP_GPIO4_IRQ2_TESLA_SHIFT                         (1 << 6)
+#define OMAP4430_WKUPDEP_GPIO4_IRQ2_TESLA_MASK                          BITFIELD(6, 6)
+
+/* Used by PM_L4PER_GPIO5_WKDEP */
+#define OMAP4430_WKUPDEP_GPIO5_IRQ1_MPU_SHIFT                           (1 << 0)
+#define OMAP4430_WKUPDEP_GPIO5_IRQ1_MPU_MASK                            BITFIELD(0, 0)
+
+/* Used by PM_L4PER_GPIO5_WKDEP */
+#define OMAP4430_WKUPDEP_GPIO5_IRQ2_TESLA_SHIFT                         (1 << 6)
+#define OMAP4430_WKUPDEP_GPIO5_IRQ2_TESLA_MASK                          BITFIELD(6, 6)
+
+/* Used by PM_L4PER_GPIO6_WKDEP */
+#define OMAP4430_WKUPDEP_GPIO6_IRQ1_MPU_SHIFT                           (1 << 0)
+#define OMAP4430_WKUPDEP_GPIO6_IRQ1_MPU_MASK                            BITFIELD(0, 0)
+
+/* Used by PM_L4PER_GPIO6_WKDEP */
+#define OMAP4430_WKUPDEP_GPIO6_IRQ2_TESLA_SHIFT                         (1 << 6)
+#define OMAP4430_WKUPDEP_GPIO6_IRQ2_TESLA_MASK                          BITFIELD(6, 6)
+
+/* Used by PM_DSS_DSS_WKDEP */
+#define OMAP4430_WKUPDEP_HDMIDMA_SDMA_SHIFT                             (1 << 19)
+#define OMAP4430_WKUPDEP_HDMIDMA_SDMA_MASK                              BITFIELD(19, 19)
+
+/* Used by PM_DSS_DSS_WKDEP */
+#define OMAP4430_WKUPDEP_HDMIIRQ_DUCATI_SHIFT                           (1 << 13)
+#define OMAP4430_WKUPDEP_HDMIIRQ_DUCATI_MASK                            BITFIELD(13, 13)
+
+/* Used by PM_DSS_DSS_WKDEP */
+#define OMAP4430_WKUPDEP_HDMIIRQ_MPU_SHIFT                              (1 << 12)
+#define OMAP4430_WKUPDEP_HDMIIRQ_MPU_MASK                               BITFIELD(12, 12)
+
+/* Used by PM_DSS_DSS_WKDEP */
+#define OMAP4430_WKUPDEP_HDMIIRQ_TESLA_SHIFT                            (1 << 14)
+#define OMAP4430_WKUPDEP_HDMIIRQ_TESLA_MASK                             BITFIELD(14, 14)
+
+/* Used by PM_L4PER_HECC1_WKDEP */
+#define OMAP4430_WKUPDEP_HECC1_MPU_SHIFT                                (1 << 0)
+#define OMAP4430_WKUPDEP_HECC1_MPU_MASK                                 BITFIELD(0, 0)
+
+/* Used by PM_L4PER_HECC2_WKDEP */
+#define OMAP4430_WKUPDEP_HECC2_MPU_SHIFT                                (1 << 0)
+#define OMAP4430_WKUPDEP_HECC2_MPU_MASK                                 BITFIELD(0, 0)
+
+/* Used by PM_L3INIT_HSI_WKDEP */
+#define OMAP4430_WKUPDEP_HSI_DSP_TESLA_SHIFT                            (1 << 6)
+#define OMAP4430_WKUPDEP_HSI_DSP_TESLA_MASK                             BITFIELD(6, 6)
+
+/* Used by PM_L3INIT_HSI_WKDEP */
+#define OMAP4430_WKUPDEP_HSI_MCU_DUCATI_SHIFT                           (1 << 1)
+#define OMAP4430_WKUPDEP_HSI_MCU_DUCATI_MASK                            BITFIELD(1, 1)
+
+/* Used by PM_L3INIT_HSI_WKDEP */
+#define OMAP4430_WKUPDEP_HSI_MCU_MPU_SHIFT                              (1 << 0)
+#define OMAP4430_WKUPDEP_HSI_MCU_MPU_MASK                               BITFIELD(0, 0)
+
+/* Used by PM_L4PER_I2C1_WKDEP */
+#define OMAP4430_WKUPDEP_I2C1_DMA_SDMA_SHIFT                            (1 << 7)
+#define OMAP4430_WKUPDEP_I2C1_DMA_SDMA_MASK                             BITFIELD(7, 7)
+
+/* Used by PM_L4PER_I2C1_WKDEP */
+#define OMAP4430_WKUPDEP_I2C1_IRQ_DUCATI_SHIFT                          (1 << 1)
+#define OMAP4430_WKUPDEP_I2C1_IRQ_DUCATI_MASK                           BITFIELD(1, 1)
+
+/* Used by PM_L4PER_I2C1_WKDEP */
+#define OMAP4430_WKUPDEP_I2C1_IRQ_MPU_SHIFT                             (1 << 0)
+#define OMAP4430_WKUPDEP_I2C1_IRQ_MPU_MASK                              BITFIELD(0, 0)
+
+/* Used by PM_L4PER_I2C2_WKDEP */
+#define OMAP4430_WKUPDEP_I2C2_DMA_SDMA_SHIFT                            (1 << 7)
+#define OMAP4430_WKUPDEP_I2C2_DMA_SDMA_MASK                             BITFIELD(7, 7)
+
+/* Used by PM_L4PER_I2C2_WKDEP */
+#define OMAP4430_WKUPDEP_I2C2_IRQ_DUCATI_SHIFT                          (1 << 1)
+#define OMAP4430_WKUPDEP_I2C2_IRQ_DUCATI_MASK                           BITFIELD(1, 1)
+
+/* Used by PM_L4PER_I2C2_WKDEP */
+#define OMAP4430_WKUPDEP_I2C2_IRQ_MPU_SHIFT                             (1 << 0)
+#define OMAP4430_WKUPDEP_I2C2_IRQ_MPU_MASK                              BITFIELD(0, 0)
+
+/* Used by PM_L4PER_I2C3_WKDEP */
+#define OMAP4430_WKUPDEP_I2C3_DMA_SDMA_SHIFT                            (1 << 7)
+#define OMAP4430_WKUPDEP_I2C3_DMA_SDMA_MASK                             BITFIELD(7, 7)
+
+/* Used by PM_L4PER_I2C3_WKDEP */
+#define OMAP4430_WKUPDEP_I2C3_IRQ_DUCATI_SHIFT                          (1 << 1)
+#define OMAP4430_WKUPDEP_I2C3_IRQ_DUCATI_MASK                           BITFIELD(1, 1)
+
+/* Used by PM_L4PER_I2C3_WKDEP */
+#define OMAP4430_WKUPDEP_I2C3_IRQ_MPU_SHIFT                             (1 << 0)
+#define OMAP4430_WKUPDEP_I2C3_IRQ_MPU_MASK                              BITFIELD(0, 0)
+
+/* Used by PM_L4PER_I2C4_WKDEP */
+#define OMAP4430_WKUPDEP_I2C4_DMA_SDMA_SHIFT                            (1 << 7)
+#define OMAP4430_WKUPDEP_I2C4_DMA_SDMA_MASK                             BITFIELD(7, 7)
+
+/* Used by PM_L4PER_I2C4_WKDEP */
+#define OMAP4430_WKUPDEP_I2C4_IRQ_DUCATI_SHIFT                          (1 << 1)
+#define OMAP4430_WKUPDEP_I2C4_IRQ_DUCATI_MASK                           BITFIELD(1, 1)
+
+/* Used by PM_L4PER_I2C4_WKDEP */
+#define OMAP4430_WKUPDEP_I2C4_IRQ_MPU_SHIFT                             (1 << 0)
+#define OMAP4430_WKUPDEP_I2C4_IRQ_MPU_MASK                              BITFIELD(0, 0)
+
+/* Used by PM_L4PER_I2C5_WKDEP */
+#define OMAP4430_WKUPDEP_I2C5_DMA_SDMA_SHIFT                            (1 << 7)
+#define OMAP4430_WKUPDEP_I2C5_DMA_SDMA_MASK                             BITFIELD(7, 7)
+
+/* Used by PM_L4PER_I2C5_WKDEP */
+#define OMAP4430_WKUPDEP_I2C5_IRQ_MPU_SHIFT                             (1 << 0)
+#define OMAP4430_WKUPDEP_I2C5_IRQ_MPU_MASK                              BITFIELD(0, 0)
+
+/* Used by PM_WKUP_KEYBOARD_WKDEP */
+#define OMAP4430_WKUPDEP_KEYBOARD_MPU_SHIFT                             (1 << 0)
+#define OMAP4430_WKUPDEP_KEYBOARD_MPU_MASK                              BITFIELD(0, 0)
+
+/* Used by PM_ABE_MCASP_WKDEP */
+#define OMAP4430_WKUPDEP_MCASP1_DMA_SDMA_SHIFT                          (1 << 7)
+#define OMAP4430_WKUPDEP_MCASP1_DMA_SDMA_MASK                           BITFIELD(7, 7)
+
+/* Used by PM_ABE_MCASP_WKDEP */
+#define OMAP4430_WKUPDEP_MCASP1_DMA_TESLA_SHIFT                         (1 << 6)
+#define OMAP4430_WKUPDEP_MCASP1_DMA_TESLA_MASK                          BITFIELD(6, 6)
+
+/* Used by PM_ABE_MCASP_WKDEP */
+#define OMAP4430_WKUPDEP_MCASP1_IRQ_MPU_SHIFT                           (1 << 0)
+#define OMAP4430_WKUPDEP_MCASP1_IRQ_MPU_MASK                            BITFIELD(0, 0)
+
+/* Used by PM_ABE_MCASP_WKDEP */
+#define OMAP4430_WKUPDEP_MCASP1_IRQ_TESLA_SHIFT                         (1 << 2)
+#define OMAP4430_WKUPDEP_MCASP1_IRQ_TESLA_MASK                          BITFIELD(2, 2)
+
+/* Used by PM_L4PER_MCASP2_WKDEP */
+#define OMAP4430_WKUPDEP_MCASP2_DMA_SDMA_SHIFT                          (1 << 7)
+#define OMAP4430_WKUPDEP_MCASP2_DMA_SDMA_MASK                           BITFIELD(7, 7)
+
+/* Used by PM_L4PER_MCASP2_WKDEP */
+#define OMAP4430_WKUPDEP_MCASP2_DMA_TESLA_SHIFT                         (1 << 6)
+#define OMAP4430_WKUPDEP_MCASP2_DMA_TESLA_MASK                          BITFIELD(6, 6)
+
+/* Used by PM_L4PER_MCASP2_WKDEP */
+#define OMAP4430_WKUPDEP_MCASP2_IRQ_MPU_SHIFT                           (1 << 0)
+#define OMAP4430_WKUPDEP_MCASP2_IRQ_MPU_MASK                            BITFIELD(0, 0)
+
+/* Used by PM_L4PER_MCASP2_WKDEP */
+#define OMAP4430_WKUPDEP_MCASP2_IRQ_TESLA_SHIFT                         (1 << 2)
+#define OMAP4430_WKUPDEP_MCASP2_IRQ_TESLA_MASK                          BITFIELD(2, 2)
+
+/* Used by PM_L4PER_MCASP3_WKDEP */
+#define OMAP4430_WKUPDEP_MCASP3_DMA_SDMA_SHIFT                          (1 << 7)
+#define OMAP4430_WKUPDEP_MCASP3_DMA_SDMA_MASK                           BITFIELD(7, 7)
+
+/* Used by PM_L4PER_MCASP3_WKDEP */
+#define OMAP4430_WKUPDEP_MCASP3_DMA_TESLA_SHIFT                         (1 << 6)
+#define OMAP4430_WKUPDEP_MCASP3_DMA_TESLA_MASK                          BITFIELD(6, 6)
+
+/* Used by PM_L4PER_MCASP3_WKDEP */
+#define OMAP4430_WKUPDEP_MCASP3_IRQ_MPU_SHIFT                           (1 << 0)
+#define OMAP4430_WKUPDEP_MCASP3_IRQ_MPU_MASK                            BITFIELD(0, 0)
+
+/* Used by PM_L4PER_MCASP3_WKDEP */
+#define OMAP4430_WKUPDEP_MCASP3_IRQ_TESLA_SHIFT                         (1 << 2)
+#define OMAP4430_WKUPDEP_MCASP3_IRQ_TESLA_MASK                          BITFIELD(2, 2)
+
+/* Used by PM_ABE_MCBSP1_WKDEP */
+#define OMAP4430_WKUPDEP_MCBSP1_MPU_SHIFT                               (1 << 0)
+#define OMAP4430_WKUPDEP_MCBSP1_MPU_MASK                                BITFIELD(0, 0)
+
+/* Used by PM_ABE_MCBSP1_WKDEP */
+#define OMAP4430_WKUPDEP_MCBSP1_SDMA_SHIFT                              (1 << 3)
+#define OMAP4430_WKUPDEP_MCBSP1_SDMA_MASK                               BITFIELD(3, 3)
+
+/* Used by PM_ABE_MCBSP1_WKDEP */
+#define OMAP4430_WKUPDEP_MCBSP1_TESLA_SHIFT                             (1 << 2)
+#define OMAP4430_WKUPDEP_MCBSP1_TESLA_MASK                              BITFIELD(2, 2)
+
+/* Used by PM_ABE_MCBSP2_WKDEP */
+#define OMAP4430_WKUPDEP_MCBSP2_MPU_SHIFT                               (1 << 0)
+#define OMAP4430_WKUPDEP_MCBSP2_MPU_MASK                                BITFIELD(0, 0)
+
+/* Used by PM_ABE_MCBSP2_WKDEP */
+#define OMAP4430_WKUPDEP_MCBSP2_SDMA_SHIFT                              (1 << 3)
+#define OMAP4430_WKUPDEP_MCBSP2_SDMA_MASK                               BITFIELD(3, 3)
+
+/* Used by PM_ABE_MCBSP2_WKDEP */
+#define OMAP4430_WKUPDEP_MCBSP2_TESLA_SHIFT                             (1 << 2)
+#define OMAP4430_WKUPDEP_MCBSP2_TESLA_MASK                              BITFIELD(2, 2)
+
+/* Used by PM_ABE_MCBSP3_WKDEP */
+#define OMAP4430_WKUPDEP_MCBSP3_MPU_SHIFT                               (1 << 0)
+#define OMAP4430_WKUPDEP_MCBSP3_MPU_MASK                                BITFIELD(0, 0)
+
+/* Used by PM_ABE_MCBSP3_WKDEP */
+#define OMAP4430_WKUPDEP_MCBSP3_SDMA_SHIFT                              (1 << 3)
+#define OMAP4430_WKUPDEP_MCBSP3_SDMA_MASK                               BITFIELD(3, 3)
+
+/* Used by PM_ABE_MCBSP3_WKDEP */
+#define OMAP4430_WKUPDEP_MCBSP3_TESLA_SHIFT                             (1 << 2)
+#define OMAP4430_WKUPDEP_MCBSP3_TESLA_MASK                              BITFIELD(2, 2)
+
+/* Used by PM_L4PER_MCBSP4_WKDEP */
+#define OMAP4430_WKUPDEP_MCBSP4_MPU_SHIFT                               (1 << 0)
+#define OMAP4430_WKUPDEP_MCBSP4_MPU_MASK                                BITFIELD(0, 0)
+
+/* Used by PM_L4PER_MCBSP4_WKDEP */
+#define OMAP4430_WKUPDEP_MCBSP4_SDMA_SHIFT                              (1 << 3)
+#define OMAP4430_WKUPDEP_MCBSP4_SDMA_MASK                               BITFIELD(3, 3)
+
+/* Used by PM_L4PER_MCBSP4_WKDEP */
+#define OMAP4430_WKUPDEP_MCBSP4_TESLA_SHIFT                             (1 << 2)
+#define OMAP4430_WKUPDEP_MCBSP4_TESLA_MASK                              BITFIELD(2, 2)
+
+/* Used by PM_L4PER_MCSPI1_WKDEP */
+#define OMAP4430_WKUPDEP_MCSPI1_DUCATI_SHIFT                            (1 << 1)
+#define OMAP4430_WKUPDEP_MCSPI1_DUCATI_MASK                             BITFIELD(1, 1)
+
+/* Used by PM_L4PER_MCSPI1_WKDEP */
+#define OMAP4430_WKUPDEP_MCSPI1_MPU_SHIFT                               (1 << 0)
+#define OMAP4430_WKUPDEP_MCSPI1_MPU_MASK                                BITFIELD(0, 0)
+
+/* Used by PM_L4PER_MCSPI1_WKDEP */
+#define OMAP4430_WKUPDEP_MCSPI1_SDMA_SHIFT                              (1 << 3)
+#define OMAP4430_WKUPDEP_MCSPI1_SDMA_MASK                               BITFIELD(3, 3)
+
+/* Used by PM_L4PER_MCSPI1_WKDEP */
+#define OMAP4430_WKUPDEP_MCSPI1_TESLA_SHIFT                             (1 << 2)
+#define OMAP4430_WKUPDEP_MCSPI1_TESLA_MASK                              BITFIELD(2, 2)
+
+/* Used by PM_L4PER_MCSPI2_WKDEP */
+#define OMAP4430_WKUPDEP_MCSPI2_DUCATI_SHIFT                            (1 << 1)
+#define OMAP4430_WKUPDEP_MCSPI2_DUCATI_MASK                             BITFIELD(1, 1)
+
+/* Used by PM_L4PER_MCSPI2_WKDEP */
+#define OMAP4430_WKUPDEP_MCSPI2_MPU_SHIFT                               (1 << 0)
+#define OMAP4430_WKUPDEP_MCSPI2_MPU_MASK                                BITFIELD(0, 0)
+
+/* Used by PM_L4PER_MCSPI2_WKDEP */
+#define OMAP4430_WKUPDEP_MCSPI2_SDMA_SHIFT                              (1 << 3)
+#define OMAP4430_WKUPDEP_MCSPI2_SDMA_MASK                               BITFIELD(3, 3)
+
+/* Used by PM_L4PER_MCSPI3_WKDEP */
+#define OMAP4430_WKUPDEP_MCSPI3_MPU_SHIFT                               (1 << 0)
+#define OMAP4430_WKUPDEP_MCSPI3_MPU_MASK                                BITFIELD(0, 0)
+
+/* Used by PM_L4PER_MCSPI3_WKDEP */
+#define OMAP4430_WKUPDEP_MCSPI3_SDMA_SHIFT                              (1 << 3)
+#define OMAP4430_WKUPDEP_MCSPI3_SDMA_MASK                               BITFIELD(3, 3)
+
+/* Used by PM_L4PER_MCSPI4_WKDEP */
+#define OMAP4430_WKUPDEP_MCSPI4_MPU_SHIFT                               (1 << 0)
+#define OMAP4430_WKUPDEP_MCSPI4_MPU_MASK                                BITFIELD(0, 0)
+
+/* Used by PM_L4PER_MCSPI4_WKDEP */
+#define OMAP4430_WKUPDEP_MCSPI4_SDMA_SHIFT                              (1 << 3)
+#define OMAP4430_WKUPDEP_MCSPI4_SDMA_MASK                               BITFIELD(3, 3)
+
+/* Used by PM_L3INIT_MMC1_WKDEP */
+#define OMAP4430_WKUPDEP_MMC1_DUCATI_SHIFT                              (1 << 1)
+#define OMAP4430_WKUPDEP_MMC1_DUCATI_MASK                               BITFIELD(1, 1)
+
+/* Used by PM_L3INIT_MMC1_WKDEP */
+#define OMAP4430_WKUPDEP_MMC1_MPU_SHIFT                                 (1 << 0)
+#define OMAP4430_WKUPDEP_MMC1_MPU_MASK                                  BITFIELD(0, 0)
+
+/* Used by PM_L3INIT_MMC1_WKDEP */
+#define OMAP4430_WKUPDEP_MMC1_SDMA_SHIFT                                (1 << 3)
+#define OMAP4430_WKUPDEP_MMC1_SDMA_MASK                                 BITFIELD(3, 3)
+
+/* Used by PM_L3INIT_MMC1_WKDEP */
+#define OMAP4430_WKUPDEP_MMC1_TESLA_SHIFT                               (1 << 2)
+#define OMAP4430_WKUPDEP_MMC1_TESLA_MASK                                BITFIELD(2, 2)
+
+/* Used by PM_L3INIT_MMC2_WKDEP */
+#define OMAP4430_WKUPDEP_MMC2_DUCATI_SHIFT                              (1 << 1)
+#define OMAP4430_WKUPDEP_MMC2_DUCATI_MASK                               BITFIELD(1, 1)
+
+/* Used by PM_L3INIT_MMC2_WKDEP */
+#define OMAP4430_WKUPDEP_MMC2_MPU_SHIFT                                 (1 << 0)
+#define OMAP4430_WKUPDEP_MMC2_MPU_MASK                                  BITFIELD(0, 0)
+
+/* Used by PM_L3INIT_MMC2_WKDEP */
+#define OMAP4430_WKUPDEP_MMC2_SDMA_SHIFT                                (1 << 3)
+#define OMAP4430_WKUPDEP_MMC2_SDMA_MASK                                 BITFIELD(3, 3)
+
+/* Used by PM_L3INIT_MMC2_WKDEP */
+#define OMAP4430_WKUPDEP_MMC2_TESLA_SHIFT                               (1 << 2)
+#define OMAP4430_WKUPDEP_MMC2_TESLA_MASK                                BITFIELD(2, 2)
+
+/* Used by PM_L3INIT_MMC6_WKDEP */
+#define OMAP4430_WKUPDEP_MMC6_DUCATI_SHIFT                              (1 << 1)
+#define OMAP4430_WKUPDEP_MMC6_DUCATI_MASK                               BITFIELD(1, 1)
+
+/* Used by PM_L3INIT_MMC6_WKDEP */
+#define OMAP4430_WKUPDEP_MMC6_MPU_SHIFT                                 (1 << 0)
+#define OMAP4430_WKUPDEP_MMC6_MPU_MASK                                  BITFIELD(0, 0)
+
+/* Used by PM_L3INIT_MMC6_WKDEP */
+#define OMAP4430_WKUPDEP_MMC6_TESLA_SHIFT                               (1 << 2)
+#define OMAP4430_WKUPDEP_MMC6_TESLA_MASK                                BITFIELD(2, 2)
+
+/* Used by PM_L4PER_MMCSD3_WKDEP */
+#define OMAP4430_WKUPDEP_MMCSD3_DUCATI_SHIFT                            (1 << 1)
+#define OMAP4430_WKUPDEP_MMCSD3_DUCATI_MASK                             BITFIELD(1, 1)
+
+/* Used by PM_L4PER_MMCSD3_WKDEP */
+#define OMAP4430_WKUPDEP_MMCSD3_MPU_SHIFT                               (1 << 0)
+#define OMAP4430_WKUPDEP_MMCSD3_MPU_MASK                                BITFIELD(0, 0)
+
+/* Used by PM_L4PER_MMCSD3_WKDEP */
+#define OMAP4430_WKUPDEP_MMCSD3_SDMA_SHIFT                              (1 << 3)
+#define OMAP4430_WKUPDEP_MMCSD3_SDMA_MASK                               BITFIELD(3, 3)
+
+/* Used by PM_L4PER_MMCSD4_WKDEP */
+#define OMAP4430_WKUPDEP_MMCSD4_DUCATI_SHIFT                            (1 << 1)
+#define OMAP4430_WKUPDEP_MMCSD4_DUCATI_MASK                             BITFIELD(1, 1)
+
+/* Used by PM_L4PER_MMCSD4_WKDEP */
+#define OMAP4430_WKUPDEP_MMCSD4_MPU_SHIFT                               (1 << 0)
+#define OMAP4430_WKUPDEP_MMCSD4_MPU_MASK                                BITFIELD(0, 0)
+
+/* Used by PM_L4PER_MMCSD4_WKDEP */
+#define OMAP4430_WKUPDEP_MMCSD4_SDMA_SHIFT                              (1 << 3)
+#define OMAP4430_WKUPDEP_MMCSD4_SDMA_MASK                               BITFIELD(3, 3)
+
+/* Used by PM_L4PER_MMCSD5_WKDEP */
+#define OMAP4430_WKUPDEP_MMCSD5_DUCATI_SHIFT                            (1 << 1)
+#define OMAP4430_WKUPDEP_MMCSD5_DUCATI_MASK                             BITFIELD(1, 1)
+
+/* Used by PM_L4PER_MMCSD5_WKDEP */
+#define OMAP4430_WKUPDEP_MMCSD5_MPU_SHIFT                               (1 << 0)
+#define OMAP4430_WKUPDEP_MMCSD5_MPU_MASK                                BITFIELD(0, 0)
+
+/* Used by PM_L4PER_MMCSD5_WKDEP */
+#define OMAP4430_WKUPDEP_MMCSD5_SDMA_SHIFT                              (1 << 3)
+#define OMAP4430_WKUPDEP_MMCSD5_SDMA_MASK                               BITFIELD(3, 3)
+
+/* Used by PM_L3INIT_PCIESS_WKDEP */
+#define OMAP4430_WKUPDEP_PCIESS_MPU_SHIFT                               (1 << 0)
+#define OMAP4430_WKUPDEP_PCIESS_MPU_MASK                                BITFIELD(0, 0)
+
+/* Used by PM_L3INIT_PCIESS_WKDEP */
+#define OMAP4430_WKUPDEP_PCIESS_TESLA_SHIFT                             (1 << 2)
+#define OMAP4430_WKUPDEP_PCIESS_TESLA_MASK                              BITFIELD(2, 2)
+
+/* Used by PM_ABE_PDM_WKDEP */
+#define OMAP4430_WKUPDEP_PDM_DMA_SDMA_SHIFT                             (1 << 7)
+#define OMAP4430_WKUPDEP_PDM_DMA_SDMA_MASK                              BITFIELD(7, 7)
+
+/* Used by PM_ABE_PDM_WKDEP */
+#define OMAP4430_WKUPDEP_PDM_DMA_TESLA_SHIFT                            (1 << 6)
+#define OMAP4430_WKUPDEP_PDM_DMA_TESLA_MASK                             BITFIELD(6, 6)
+
+/* Used by PM_ABE_PDM_WKDEP */
+#define OMAP4430_WKUPDEP_PDM_IRQ_MPU_SHIFT                              (1 << 0)
+#define OMAP4430_WKUPDEP_PDM_IRQ_MPU_MASK                               BITFIELD(0, 0)
+
+/* Used by PM_ABE_PDM_WKDEP */
+#define OMAP4430_WKUPDEP_PDM_IRQ_TESLA_SHIFT                            (1 << 2)
+#define OMAP4430_WKUPDEP_PDM_IRQ_TESLA_MASK                             BITFIELD(2, 2)
+
+/* Used by PM_WKUP_RTC_WKDEP */
+#define OMAP4430_WKUPDEP_RTC_MPU_SHIFT                                  (1 << 0)
+#define OMAP4430_WKUPDEP_RTC_MPU_MASK                                   BITFIELD(0, 0)
+
+/* Used by PM_L3INIT_SATA_WKDEP */
+#define OMAP4430_WKUPDEP_SATA_MPU_SHIFT                                 (1 << 0)
+#define OMAP4430_WKUPDEP_SATA_MPU_MASK                                  BITFIELD(0, 0)
+
+/* Used by PM_L3INIT_SATA_WKDEP */
+#define OMAP4430_WKUPDEP_SATA_TESLA_SHIFT                               (1 << 2)
+#define OMAP4430_WKUPDEP_SATA_TESLA_MASK                                BITFIELD(2, 2)
+
+/* Used by PM_ABE_SLIMBUS_WKDEP */
+#define OMAP4430_WKUPDEP_SLIMBUS1_DMA_SDMA_SHIFT                        (1 << 7)
+#define OMAP4430_WKUPDEP_SLIMBUS1_DMA_SDMA_MASK                         BITFIELD(7, 7)
+
+/* Used by PM_ABE_SLIMBUS_WKDEP */
+#define OMAP4430_WKUPDEP_SLIMBUS1_DMA_TESLA_SHIFT                       (1 << 6)
+#define OMAP4430_WKUPDEP_SLIMBUS1_DMA_TESLA_MASK                        BITFIELD(6, 6)
+
+/* Used by PM_ABE_SLIMBUS_WKDEP */
+#define OMAP4430_WKUPDEP_SLIMBUS1_IRQ_MPU_SHIFT                         (1 << 0)
+#define OMAP4430_WKUPDEP_SLIMBUS1_IRQ_MPU_MASK                          BITFIELD(0, 0)
+
+/* Used by PM_ABE_SLIMBUS_WKDEP */
+#define OMAP4430_WKUPDEP_SLIMBUS1_IRQ_TESLA_SHIFT                       (1 << 2)
+#define OMAP4430_WKUPDEP_SLIMBUS1_IRQ_TESLA_MASK                        BITFIELD(2, 2)
+
+/* Used by PM_L4PER_SLIMBUS2_WKDEP */
+#define OMAP4430_WKUPDEP_SLIMBUS2_DMA_SDMA_SHIFT                        (1 << 7)
+#define OMAP4430_WKUPDEP_SLIMBUS2_DMA_SDMA_MASK                         BITFIELD(7, 7)
+
+/* Used by PM_L4PER_SLIMBUS2_WKDEP */
+#define OMAP4430_WKUPDEP_SLIMBUS2_DMA_TESLA_SHIFT                       (1 << 6)
+#define OMAP4430_WKUPDEP_SLIMBUS2_DMA_TESLA_MASK                        BITFIELD(6, 6)
+
+/* Used by PM_L4PER_SLIMBUS2_WKDEP */
+#define OMAP4430_WKUPDEP_SLIMBUS2_IRQ_MPU_SHIFT                         (1 << 0)
+#define OMAP4430_WKUPDEP_SLIMBUS2_IRQ_MPU_MASK                          BITFIELD(0, 0)
+
+/* Used by PM_L4PER_SLIMBUS2_WKDEP */
+#define OMAP4430_WKUPDEP_SLIMBUS2_IRQ_TESLA_SHIFT                       (1 << 2)
+#define OMAP4430_WKUPDEP_SLIMBUS2_IRQ_TESLA_MASK                        BITFIELD(2, 2)
+
+/* Used by PM_ALWON_SR_CORE_WKDEP */
+#define OMAP4430_WKUPDEP_SR_CORE_DUCATI_SHIFT                           (1 << 1)
+#define OMAP4430_WKUPDEP_SR_CORE_DUCATI_MASK                            BITFIELD(1, 1)
+
+/* Used by PM_ALWON_SR_CORE_WKDEP */
+#define OMAP4430_WKUPDEP_SR_CORE_MPU_SHIFT                              (1 << 0)
+#define OMAP4430_WKUPDEP_SR_CORE_MPU_MASK                               BITFIELD(0, 0)
+
+/* Used by PM_ALWON_SR_IVA_WKDEP */
+#define OMAP4430_WKUPDEP_SR_IVA_DUCATI_SHIFT                            (1 << 1)
+#define OMAP4430_WKUPDEP_SR_IVA_DUCATI_MASK                             BITFIELD(1, 1)
+
+/* Used by PM_ALWON_SR_IVA_WKDEP */
+#define OMAP4430_WKUPDEP_SR_IVA_MPU_SHIFT                               (1 << 0)
+#define OMAP4430_WKUPDEP_SR_IVA_MPU_MASK                                BITFIELD(0, 0)
+
+/* Used by PM_ALWON_SR_MPU_WKDEP */
+#define OMAP4430_WKUPDEP_SR_MPU_MPU_SHIFT                               (1 << 0)
+#define OMAP4430_WKUPDEP_SR_MPU_MPU_MASK                                BITFIELD(0, 0)
+
+/* Used by PM_WKUP_TIMER12_WKDEP */
+#define OMAP4430_WKUPDEP_TIMER12_MPU_SHIFT                              (1 << 0)
+#define OMAP4430_WKUPDEP_TIMER12_MPU_MASK                               BITFIELD(0, 0)
+
+/* Used by PM_WKUP_TIMER1_WKDEP */
+#define OMAP4430_WKUPDEP_TIMER1_MPU_SHIFT                               (1 << 0)
+#define OMAP4430_WKUPDEP_TIMER1_MPU_MASK                                BITFIELD(0, 0)
+
+/* Used by PM_ABE_TIMER5_WKDEP */
+#define OMAP4430_WKUPDEP_TIMER5_MPU_SHIFT                               (1 << 0)
+#define OMAP4430_WKUPDEP_TIMER5_MPU_MASK                                BITFIELD(0, 0)
+
+/* Used by PM_ABE_TIMER5_WKDEP */
+#define OMAP4430_WKUPDEP_TIMER5_TESLA_SHIFT                             (1 << 2)
+#define OMAP4430_WKUPDEP_TIMER5_TESLA_MASK                              BITFIELD(2, 2)
+
+/* Used by PM_ABE_TIMER6_WKDEP */
+#define OMAP4430_WKUPDEP_TIMER6_MPU_SHIFT                               (1 << 0)
+#define OMAP4430_WKUPDEP_TIMER6_MPU_MASK                                BITFIELD(0, 0)
+
+/* Used by PM_ABE_TIMER6_WKDEP */
+#define OMAP4430_WKUPDEP_TIMER6_TESLA_SHIFT                             (1 << 2)
+#define OMAP4430_WKUPDEP_TIMER6_TESLA_MASK                              BITFIELD(2, 2)
+
+/* Used by PM_ABE_TIMER7_WKDEP */
+#define OMAP4430_WKUPDEP_TIMER7_MPU_SHIFT                               (1 << 0)
+#define OMAP4430_WKUPDEP_TIMER7_MPU_MASK                                BITFIELD(0, 0)
+
+/* Used by PM_ABE_TIMER7_WKDEP */
+#define OMAP4430_WKUPDEP_TIMER7_TESLA_SHIFT                             (1 << 2)
+#define OMAP4430_WKUPDEP_TIMER7_TESLA_MASK                              BITFIELD(2, 2)
+
+/* Used by PM_ABE_TIMER8_WKDEP */
+#define OMAP4430_WKUPDEP_TIMER8_MPU_SHIFT                               (1 << 0)
+#define OMAP4430_WKUPDEP_TIMER8_MPU_MASK                                BITFIELD(0, 0)
+
+/* Used by PM_ABE_TIMER8_WKDEP */
+#define OMAP4430_WKUPDEP_TIMER8_TESLA_SHIFT                             (1 << 2)
+#define OMAP4430_WKUPDEP_TIMER8_TESLA_MASK                              BITFIELD(2, 2)
+
+/* Used by PM_L4PER_UART1_WKDEP */
+#define OMAP4430_WKUPDEP_UART1_MPU_SHIFT                                (1 << 0)
+#define OMAP4430_WKUPDEP_UART1_MPU_MASK                                 BITFIELD(0, 0)
+
+/* Used by PM_L4PER_UART1_WKDEP */
+#define OMAP4430_WKUPDEP_UART1_SDMA_SHIFT                               (1 << 3)
+#define OMAP4430_WKUPDEP_UART1_SDMA_MASK                                BITFIELD(3, 3)
+
+/* Used by PM_L4PER_UART2_WKDEP */
+#define OMAP4430_WKUPDEP_UART2_MPU_SHIFT                                (1 << 0)
+#define OMAP4430_WKUPDEP_UART2_MPU_MASK                                 BITFIELD(0, 0)
+
+/* Used by PM_L4PER_UART2_WKDEP */
+#define OMAP4430_WKUPDEP_UART2_SDMA_SHIFT                               (1 << 3)
+#define OMAP4430_WKUPDEP_UART2_SDMA_MASK                                BITFIELD(3, 3)
+
+/* Used by PM_L4PER_UART3_WKDEP */
+#define OMAP4430_WKUPDEP_UART3_DUCATI_SHIFT                             (1 << 1)
+#define OMAP4430_WKUPDEP_UART3_DUCATI_MASK                              BITFIELD(1, 1)
+
+/* Used by PM_L4PER_UART3_WKDEP */
+#define OMAP4430_WKUPDEP_UART3_MPU_SHIFT                                (1 << 0)
+#define OMAP4430_WKUPDEP_UART3_MPU_MASK                                 BITFIELD(0, 0)
+
+/* Used by PM_L4PER_UART3_WKDEP */
+#define OMAP4430_WKUPDEP_UART3_SDMA_SHIFT                               (1 << 3)
+#define OMAP4430_WKUPDEP_UART3_SDMA_MASK                                BITFIELD(3, 3)
+
+/* Used by PM_L4PER_UART3_WKDEP */
+#define OMAP4430_WKUPDEP_UART3_TESLA_SHIFT                              (1 << 2)
+#define OMAP4430_WKUPDEP_UART3_TESLA_MASK                               BITFIELD(2, 2)
+
+/* Used by PM_L4PER_UART4_WKDEP */
+#define OMAP4430_WKUPDEP_UART4_MPU_SHIFT                                (1 << 0)
+#define OMAP4430_WKUPDEP_UART4_MPU_MASK                                 BITFIELD(0, 0)
+
+/* Used by PM_L4PER_UART4_WKDEP */
+#define OMAP4430_WKUPDEP_UART4_SDMA_SHIFT                               (1 << 3)
+#define OMAP4430_WKUPDEP_UART4_SDMA_MASK                                BITFIELD(3, 3)
+
+/* Used by PM_L3INIT_UNIPRO1_WKDEP */
+#define OMAP4430_WKUPDEP_UNIPRO1_DUCATI_SHIFT                           (1 << 1)
+#define OMAP4430_WKUPDEP_UNIPRO1_DUCATI_MASK                            BITFIELD(1, 1)
+
+/* Used by PM_L3INIT_UNIPRO1_WKDEP */
+#define OMAP4430_WKUPDEP_UNIPRO1_MPU_SHIFT                              (1 << 0)
+#define OMAP4430_WKUPDEP_UNIPRO1_MPU_MASK                               BITFIELD(0, 0)
+
+/* Used by PM_L3INIT_USB_HOST_WKDEP */
+#define OMAP4430_WKUPDEP_USB_HOST_DUCATI_SHIFT                          (1 << 1)
+#define OMAP4430_WKUPDEP_USB_HOST_DUCATI_MASK                           BITFIELD(1, 1)
+
+/* Used by PM_L3INIT_USB_HOST_FS_WKDEP */
+#define OMAP4430_WKUPDEP_USB_HOST_FS_DUCATI_SHIFT                       (1 << 1)
+#define OMAP4430_WKUPDEP_USB_HOST_FS_DUCATI_MASK                        BITFIELD(1, 1)
+
+/* Used by PM_L3INIT_USB_HOST_FS_WKDEP */
+#define OMAP4430_WKUPDEP_USB_HOST_FS_MPU_SHIFT                          (1 << 0)
+#define OMAP4430_WKUPDEP_USB_HOST_FS_MPU_MASK                           BITFIELD(0, 0)
+
+/* Used by PM_L3INIT_USB_HOST_WKDEP */
+#define OMAP4430_WKUPDEP_USB_HOST_MPU_SHIFT                             (1 << 0)
+#define OMAP4430_WKUPDEP_USB_HOST_MPU_MASK                              BITFIELD(0, 0)
+
+/* Used by PM_L3INIT_USB_OTG_WKDEP */
+#define OMAP4430_WKUPDEP_USB_OTG_DUCATI_SHIFT                           (1 << 1)
+#define OMAP4430_WKUPDEP_USB_OTG_DUCATI_MASK                            BITFIELD(1, 1)
+
+/* Used by PM_L3INIT_USB_OTG_WKDEP */
+#define OMAP4430_WKUPDEP_USB_OTG_MPU_SHIFT                              (1 << 0)
+#define OMAP4430_WKUPDEP_USB_OTG_MPU_MASK                               BITFIELD(0, 0)
+
+/* Used by PM_L3INIT_USB_TLL_WKDEP */
+#define OMAP4430_WKUPDEP_USB_TLL_DUCATI_SHIFT                           (1 << 1)
+#define OMAP4430_WKUPDEP_USB_TLL_DUCATI_MASK                            BITFIELD(1, 1)
+
+/* Used by PM_L3INIT_USB_TLL_WKDEP */
+#define OMAP4430_WKUPDEP_USB_TLL_MPU_SHIFT                              (1 << 0)
+#define OMAP4430_WKUPDEP_USB_TLL_MPU_MASK                               BITFIELD(0, 0)
+
+/* Used by PM_WKUP_USIM_WKDEP */
+#define OMAP4430_WKUPDEP_USIM_MPU_SHIFT                                 (1 << 0)
+#define OMAP4430_WKUPDEP_USIM_MPU_MASK                                  BITFIELD(0, 0)
+
+/* Used by PM_WKUP_USIM_WKDEP */
+#define OMAP4430_WKUPDEP_USIM_SDMA_SHIFT                                (1 << 3)
+#define OMAP4430_WKUPDEP_USIM_SDMA_MASK                                 BITFIELD(3, 3)
+
+/* Used by PM_WKUP_WDT2_WKDEP */
+#define OMAP4430_WKUPDEP_WDT2_DUCATI_SHIFT                              (1 << 1)
+#define OMAP4430_WKUPDEP_WDT2_DUCATI_MASK                               BITFIELD(1, 1)
+
+/* Used by PM_WKUP_WDT2_WKDEP */
+#define OMAP4430_WKUPDEP_WDT2_MPU_SHIFT                                 (1 << 0)
+#define OMAP4430_WKUPDEP_WDT2_MPU_MASK                                  BITFIELD(0, 0)
+
+/* Used by PM_ABE_WDT3_WKDEP */
+#define OMAP4430_WKUPDEP_WDT3_MPU_SHIFT                                 (1 << 0)
+#define OMAP4430_WKUPDEP_WDT3_MPU_MASK                                  BITFIELD(0, 0)
+
+/* Used by PM_L3INIT_HSI_WKDEP */
+#define OMAP4430_WKUPDEP_WGM_HSI_WAKE_MPU_SHIFT                         (1 << 8)
+#define OMAP4430_WKUPDEP_WGM_HSI_WAKE_MPU_MASK                          BITFIELD(8, 8)
+
+/* Used by PM_L3INIT_XHPI_WKDEP */
+#define OMAP4430_WKUPDEP_XHPI_DUCATI_SHIFT                              (1 << 1)
+#define OMAP4430_WKUPDEP_XHPI_DUCATI_MASK                               BITFIELD(1, 1)
+
+/* Used by PRM_IO_PMCTRL */
+#define OMAP4430_WUCLK_CTRL_SHIFT                                       (1 << 8)
+#define OMAP4430_WUCLK_CTRL_MASK                                        BITFIELD(8, 8)
+
+/* Used by PRM_IO_PMCTRL */
+#define OMAP4430_WUCLK_STATUS_SHIFT                                     (1 << 9)
+#define OMAP4430_WUCLK_STATUS_MASK                                      BITFIELD(9, 9)
+#endif
diff --git a/arch/arm/mach-omap2/prm.h b/arch/arm/mach-omap2/prm.h
index a117f853ea39..ea050ce188a7 100644
--- a/arch/arm/mach-omap2/prm.h
+++ b/arch/arm/mach-omap2/prm.h
@@ -4,8 +4,8 @@
 /*
  * OMAP2/3 Power/Reset Management (PRM) register definitions
  *
- * Copyright (C) 2007 Texas Instruments, Inc.
- * Copyright (C) 2007 Nokia Corporation
+ * Copyright (C) 2007-2009 Texas Instruments, Inc.
+ * Copyright (C) 2009 Nokia Corporation
  *
  * Written by Paul Walmsley
  *
@@ -22,6 +22,10 @@
                 OMAP2_L4_IO_ADDRESS(OMAP2430_PRM_BASE + (module) + (reg))
 #define OMAP34XX_PRM_REGADDR(module, reg)                               \
                 OMAP2_L4_IO_ADDRESS(OMAP3430_PRM_BASE + (module) + (reg))
+#define OMAP44XX_PRM_REGADDR(module, reg)                               \
+                OMAP2_L4_IO_ADDRESS(OMAP4430_PRM_BASE + (module) + (reg))
+
+#include "prm44xx.h"
 
 /*
  * Architecture-specific global PRM registers
diff --git a/arch/arm/mach-omap2/prm44xx.h b/arch/arm/mach-omap2/prm44xx.h
new file mode 100644
index 000000000000..89be97f0589d
--- /dev/null
+++ b/arch/arm/mach-omap2/prm44xx.h
@@ -0,0 +1,411 @@
+/*
+ * OMAP44xx PRM instance offset macros
+ *
+ * Copyright (C) 2009 Texas Instruments, Inc.
+ * Copyright (C) 2009 Nokia Corporation
+ *
+ * Paul Walmsley (paul@pwsan.com)
+ * Rajendra Nayak (rnayak@ti.com)
+ * Benoit Cousson (b-cousson@ti.com)
+ *
+ * This file is automatically generated from the OMAP hardware databases.
+ * We respectfully ask that any modifications to this file be coordinated
+ * with the public linux-omap@vger.kernel.org mailing list and the
+ * authors above to ensure that the autogeneration scripts are kept
+ * up-to-date with the file contents.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ARCH_ARM_MACH_OMAP2_PRM44XX_H
+#define __ARCH_ARM_MACH_OMAP2_PRM44XX_H
+
+
+/* PRM */
+
+
+/* PRM.OCP_SOCKET_PRM register offsets */
+#define OMAP4430_REVISION_PRM                           OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x0000)
+#define OMAP4430_PRM_IRQSTATUS_MPU                      OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x0010)
+#define OMAP4430_PRM_IRQSTATUS_MPU_2                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x0014)
+#define OMAP4430_PRM_IRQENABLE_MPU                      OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x0018)
+#define OMAP4430_PRM_IRQENABLE_MPU_2                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x001c)
+#define OMAP4430_PRM_IRQSTATUS_DUCATI                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x0020)
+#define OMAP4430_PRM_IRQENABLE_DUCATI                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x0028)
+#define OMAP4430_PRM_IRQSTATUS_TESLA                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x0030)
+#define OMAP4430_PRM_IRQENABLE_TESLA                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x0038)
+#define OMAP4430_PRM_PRM_PROFILING_CLKCTRL              OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x0040)
+
+/* PRM.CKGEN_PRM register offsets */
+#define OMAP4430_CM_ABE_DSS_SYS_CLKSEL                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CKGEN_MOD, 0x0000)
+#define OMAP4430_CM_DPLL_SYS_REF_CLKSEL                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CKGEN_MOD, 0x0004)
+#define OMAP4430_CM_L4_WKUP_CLKSEL                      OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CKGEN_MOD, 0x0008)
+#define OMAP4430_CM_ABE_PLL_REF_CLKSEL                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CKGEN_MOD, 0x000c)
+#define OMAP4430_CM_SYS_CLKSEL                          OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CKGEN_MOD, 0x0010)
+
+/* PRM.MPU_PRM register offsets */
+#define OMAP4430_PM_MPU_PWRSTCTRL                       OMAP44XX_PRM_REGADDR(OMAP4430_PRM_MPU_MOD, 0x0000)
+#define OMAP4430_PM_MPU_PWRSTST                         OMAP44XX_PRM_REGADDR(OMAP4430_PRM_MPU_MOD, 0x0004)
+#define OMAP4430_RM_MPU_RSTST                           OMAP44XX_PRM_REGADDR(OMAP4430_PRM_MPU_MOD, 0x0014)
+#define OMAP4430_RM_MPU_MPU_CONTEXT                     OMAP44XX_PRM_REGADDR(OMAP4430_PRM_MPU_MOD, 0x0024)
+
+/* PRM.TESLA_PRM register offsets */
+#define OMAP4430_PM_TESLA_PWRSTCTRL                     OMAP44XX_PRM_REGADDR(OMAP4430_PRM_TESLA_MOD, 0x0000)
+#define OMAP4430_PM_TESLA_PWRSTST                       OMAP44XX_PRM_REGADDR(OMAP4430_PRM_TESLA_MOD, 0x0004)
+#define OMAP4430_RM_TESLA_RSTCTRL                       OMAP44XX_PRM_REGADDR(OMAP4430_PRM_TESLA_MOD, 0x0010)
+#define OMAP4430_RM_TESLA_RSTST                         OMAP44XX_PRM_REGADDR(OMAP4430_PRM_TESLA_MOD, 0x0014)
+#define OMAP4430_RM_TESLA_TESLA_CONTEXT                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_TESLA_MOD, 0x0024)
+
+/* PRM.ABE_PRM register offsets */
+#define OMAP4430_PM_ABE_PWRSTCTRL                       OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0000)
+#define OMAP4430_PM_ABE_PWRSTST                         OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0004)
+#define OMAP4430_RM_ABE_AESS_CONTEXT                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x002c)
+#define OMAP4430_PM_ABE_PDM_WKDEP                       OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0030)
+#define OMAP4430_RM_ABE_PDM_CONTEXT                     OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0034)
+#define OMAP4430_PM_ABE_DMIC_WKDEP                      OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0038)
+#define OMAP4430_RM_ABE_DMIC_CONTEXT                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x003c)
+#define OMAP4430_PM_ABE_MCASP_WKDEP                     OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0040)
+#define OMAP4430_RM_ABE_MCASP_CONTEXT                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0044)
+#define OMAP4430_PM_ABE_MCBSP1_WKDEP                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0048)
+#define OMAP4430_RM_ABE_MCBSP1_CONTEXT                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x004c)
+#define OMAP4430_PM_ABE_MCBSP2_WKDEP                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0050)
+#define OMAP4430_RM_ABE_MCBSP2_CONTEXT                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0054)
+#define OMAP4430_PM_ABE_MCBSP3_WKDEP                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0058)
+#define OMAP4430_RM_ABE_MCBSP3_CONTEXT                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x005c)
+#define OMAP4430_PM_ABE_SLIMBUS_WKDEP                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0060)
+#define OMAP4430_RM_ABE_SLIMBUS_CONTEXT                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0064)
+#define OMAP4430_PM_ABE_TIMER5_WKDEP                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0068)
+#define OMAP4430_RM_ABE_TIMER5_CONTEXT                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x006c)
+#define OMAP4430_PM_ABE_TIMER6_WKDEP                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0070)
+#define OMAP4430_RM_ABE_TIMER6_CONTEXT                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0074)
+#define OMAP4430_PM_ABE_TIMER7_WKDEP                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0078)
+#define OMAP4430_RM_ABE_TIMER7_CONTEXT                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x007c)
+#define OMAP4430_PM_ABE_TIMER8_WKDEP                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0080)
+#define OMAP4430_RM_ABE_TIMER8_CONTEXT                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0084)
+#define OMAP4430_PM_ABE_WDT3_WKDEP                      OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0088)
+#define OMAP4430_RM_ABE_WDT3_CONTEXT                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x008c)
+
+/* PRM.ALWAYS_ON_PRM register offsets */
+#define OMAP4430_RM_ALWON_MDMINTC_CONTEXT               OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_MOD, 0x0024)
+#define OMAP4430_PM_ALWON_SR_MPU_WKDEP                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_MOD, 0x0028)
+#define OMAP4430_RM_ALWON_SR_MPU_CONTEXT                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_MOD, 0x002c)
+#define OMAP4430_PM_ALWON_SR_IVA_WKDEP                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_MOD, 0x0030)
+#define OMAP4430_RM_ALWON_SR_IVA_CONTEXT                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_MOD, 0x0034)
+#define OMAP4430_PM_ALWON_SR_CORE_WKDEP                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_MOD, 0x0038)
+#define OMAP4430_RM_ALWON_SR_CORE_CONTEXT               OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_MOD, 0x003c)
+
+/* PRM.CORE_PRM register offsets */
+#define OMAP4430_PM_CORE_PWRSTCTRL                      OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0000)
+#define OMAP4430_PM_CORE_PWRSTST                        OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0004)
+#define OMAP4430_RM_L3_1_L3_1_CONTEXT                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0024)
+#define OMAP4430_RM_L3_2_L3_2_CONTEXT                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0124)
+#define OMAP4430_RM_L3_2_GPMC_CONTEXT                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x012c)
+#define OMAP4430_RM_L3_2_OCMC_RAM_CONTEXT               OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0134)
+#define OMAP4430_RM_DUCATI_RSTCTRL                      OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0210)
+#define OMAP4430_RM_DUCATI_RSTST                        OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0214)
+#define OMAP4430_RM_DUCATI_DUCATI_CONTEXT               OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0224)
+#define OMAP4430_RM_SDMA_SDMA_CONTEXT                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0324)
+#define OMAP4430_RM_MEMIF_DMM_CONTEXT                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0424)
+#define OMAP4430_RM_MEMIF_EMIF_FW_CONTEXT               OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x042c)
+#define OMAP4430_RM_MEMIF_EMIF_1_CONTEXT                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0434)
+#define OMAP4430_RM_MEMIF_EMIF_2_CONTEXT                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x043c)
+#define OMAP4430_RM_MEMIF_DLL_CONTEXT                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0444)
+#define OMAP4430_RM_MEMIF_EMIF_H1_CONTEXT               OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0454)
+#define OMAP4430_RM_MEMIF_EMIF_H2_CONTEXT               OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x045c)
+#define OMAP4430_RM_MEMIF_DLL_H_CONTEXT                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0464)
+#define OMAP4430_RM_D2D_SAD2D_CONTEXT                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0524)
+#define OMAP4430_RM_D2D_MODEM_ICR_CONTEXT               OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x052c)
+#define OMAP4430_RM_D2D_SAD2D_FW_CONTEXT                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0534)
+#define OMAP4430_RM_L4CFG_L4_CFG_CONTEXT                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0624)
+#define OMAP4430_RM_L4CFG_HW_SEM_CONTEXT                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x062c)
+#define OMAP4430_RM_L4CFG_MAILBOX_CONTEXT               OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0634)
+#define OMAP4430_RM_L4CFG_SAR_ROM_CONTEXT               OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x063c)
+#define OMAP4430_RM_L3INSTR_L3_3_CONTEXT                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0724)
+#define OMAP4430_RM_L3INSTR_L3_INSTR_CONTEXT            OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x072c)
+#define OMAP4430_RM_L3INSTR_OCP_WP1_CONTEXT             OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0744)
+
+/* PRM.IVAHD_PRM register offsets */
+#define OMAP4430_PM_IVAHD_PWRSTCTRL                     OMAP44XX_PRM_REGADDR(OMAP4430_PRM_IVAHD_MOD, 0x0000)
+#define OMAP4430_PM_IVAHD_PWRSTST                       OMAP44XX_PRM_REGADDR(OMAP4430_PRM_IVAHD_MOD, 0x0004)
+#define OMAP4430_RM_IVAHD_RSTCTRL                       OMAP44XX_PRM_REGADDR(OMAP4430_PRM_IVAHD_MOD, 0x0010)
+#define OMAP4430_RM_IVAHD_RSTST                         OMAP44XX_PRM_REGADDR(OMAP4430_PRM_IVAHD_MOD, 0x0014)
+#define OMAP4430_RM_IVAHD_IVAHD_CONTEXT                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_IVAHD_MOD, 0x0024)
+#define OMAP4430_RM_IVAHD_SL2_CONTEXT                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_IVAHD_MOD, 0x002c)
+
+/* PRM.CAM_PRM register offsets */
+#define OMAP4430_PM_CAM_PWRSTCTRL                       OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CAM_MOD, 0x0000)
+#define OMAP4430_PM_CAM_PWRSTST                         OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CAM_MOD, 0x0004)
+#define OMAP4430_RM_CAM_ISS_CONTEXT                     OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CAM_MOD, 0x0024)
+#define OMAP4430_RM_CAM_FDIF_CONTEXT                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CAM_MOD, 0x002c)
+
+/* PRM.DSS_PRM register offsets */
+#define OMAP4430_PM_DSS_PWRSTCTRL                       OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DSS_MOD, 0x0000)
+#define OMAP4430_PM_DSS_PWRSTST                         OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DSS_MOD, 0x0004)
+#define OMAP4430_PM_DSS_DSS_WKDEP                       OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DSS_MOD, 0x0020)
+#define OMAP4430_RM_DSS_DSS_CONTEXT                     OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DSS_MOD, 0x0024)
+#define OMAP4430_RM_DSS_DEISS_CONTEXT                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DSS_MOD, 0x002c)
+
+/* PRM.GFX_PRM register offsets */
+#define OMAP4430_PM_GFX_PWRSTCTRL                       OMAP44XX_PRM_REGADDR(OMAP4430_PRM_GFX_MOD, 0x0000)
+#define OMAP4430_PM_GFX_PWRSTST                         OMAP44XX_PRM_REGADDR(OMAP4430_PRM_GFX_MOD, 0x0004)
+#define OMAP4430_RM_GFX_GFX_CONTEXT                     OMAP44XX_PRM_REGADDR(OMAP4430_PRM_GFX_MOD, 0x0024)
+
+/* PRM.L3INIT_PRM register offsets */
+#define OMAP4430_PM_L3INIT_PWRSTCTRL                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0000)
+#define OMAP4430_PM_L3INIT_PWRSTST                      OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0004)
+#define OMAP4430_PM_L3INIT_MMC1_WKDEP                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0028)
+#define OMAP4430_RM_L3INIT_MMC1_CONTEXT                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x002c)
+#define OMAP4430_PM_L3INIT_MMC2_WKDEP                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0030)
+#define OMAP4430_RM_L3INIT_MMC2_CONTEXT                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0034)
+#define OMAP4430_PM_L3INIT_HSI_WKDEP                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0038)
+#define OMAP4430_RM_L3INIT_HSI_CONTEXT                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x003c)
+#define OMAP4430_PM_L3INIT_UNIPRO1_WKDEP                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0040)
+#define OMAP4430_RM_L3INIT_UNIPRO1_CONTEXT              OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0044)
+#define OMAP4430_PM_L3INIT_USB_HOST_WKDEP               OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0058)
+#define OMAP4430_RM_L3INIT_USB_HOST_CONTEXT             OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x005c)
+#define OMAP4430_PM_L3INIT_USB_OTG_WKDEP                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0060)
+#define OMAP4430_RM_L3INIT_USB_OTG_CONTEXT              OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0064)
+#define OMAP4430_PM_L3INIT_USB_TLL_WKDEP                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0068)
+#define OMAP4430_RM_L3INIT_USB_TLL_CONTEXT              OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x006c)
+#define OMAP4430_RM_L3INIT_P1500_CONTEXT                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x007c)
+#define OMAP4430_RM_L3INIT_EMAC_CONTEXT                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0084)
+#define OMAP4430_PM_L3INIT_SATA_WKDEP                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0088)
+#define OMAP4430_RM_L3INIT_SATA_CONTEXT                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x008c)
+#define OMAP4430_RM_L3INIT_TPPSS_CONTEXT                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0094)
+#define OMAP4430_PM_L3INIT_PCIESS_WKDEP                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0098)
+#define OMAP4430_RM_L3INIT_PCIESS_CONTEXT               OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x009c)
+#define OMAP4430_RM_L3INIT_CCPTX_CONTEXT                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x00ac)
+#define OMAP4430_PM_L3INIT_XHPI_WKDEP                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x00c0)
+#define OMAP4430_RM_L3INIT_XHPI_CONTEXT                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x00c4)
+#define OMAP4430_PM_L3INIT_MMC6_WKDEP                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x00c8)
+#define OMAP4430_RM_L3INIT_MMC6_CONTEXT                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x00cc)
+#define OMAP4430_PM_L3INIT_USB_HOST_FS_WKDEP            OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x00d0)
+#define OMAP4430_RM_L3INIT_USB_HOST_FS_CONTEXT          OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x00d4)
+#define OMAP4430_RM_L3INIT_USBPHYOCP2SCP_CONTEXT        OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x00e4)
+
+/* PRM.L4PER_PRM register offsets */
+#define OMAP4430_PM_L4PER_PWRSTCTRL                     OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0000)
+#define OMAP4430_PM_L4PER_PWRSTST                       OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0004)
+#define OMAP4430_RM_L4PER_ADC_CONTEXT                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0024)
+#define OMAP4430_PM_L4PER_DMTIMER10_WKDEP               OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0028)
+#define OMAP4430_RM_L4PER_DMTIMER10_CONTEXT             OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x002c)
+#define OMAP4430_PM_L4PER_DMTIMER11_WKDEP               OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0030)
+#define OMAP4430_RM_L4PER_DMTIMER11_CONTEXT             OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0034)
+#define OMAP4430_PM_L4PER_DMTIMER2_WKDEP                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0038)
+#define OMAP4430_RM_L4PER_DMTIMER2_CONTEXT              OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x003c)
+#define OMAP4430_PM_L4PER_DMTIMER3_WKDEP                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0040)
+#define OMAP4430_RM_L4PER_DMTIMER3_CONTEXT              OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0044)
+#define OMAP4430_PM_L4PER_DMTIMER4_WKDEP                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0048)
+#define OMAP4430_RM_L4PER_DMTIMER4_CONTEXT              OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x004c)
+#define OMAP4430_PM_L4PER_DMTIMER9_WKDEP                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0050)
+#define OMAP4430_RM_L4PER_DMTIMER9_CONTEXT              OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0054)
+#define OMAP4430_RM_L4PER_ELM_CONTEXT                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x005c)
+#define OMAP4430_PM_L4PER_GPIO2_WKDEP                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0060)
+#define OMAP4430_RM_L4PER_GPIO2_CONTEXT                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0064)
+#define OMAP4430_PM_L4PER_GPIO3_WKDEP                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0068)
+#define OMAP4430_RM_L4PER_GPIO3_CONTEXT                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x006c)
+#define OMAP4430_PM_L4PER_GPIO4_WKDEP                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0070)
+#define OMAP4430_RM_L4PER_GPIO4_CONTEXT                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0074)
+#define OMAP4430_PM_L4PER_GPIO5_WKDEP                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0078)
+#define OMAP4430_RM_L4PER_GPIO5_CONTEXT                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x007c)
+#define OMAP4430_PM_L4PER_GPIO6_WKDEP                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0080)
+#define OMAP4430_RM_L4PER_GPIO6_CONTEXT                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0084)
+#define OMAP4430_RM_L4PER_HDQ1W_CONTEXT                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x008c)
+#define OMAP4430_PM_L4PER_HECC1_WKDEP                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0090)
+#define OMAP4430_RM_L4PER_HECC1_CONTEXT                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0094)
+#define OMAP4430_PM_L4PER_HECC2_WKDEP                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0098)
+#define OMAP4430_RM_L4PER_HECC2_CONTEXT                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x009c)
+#define OMAP4430_PM_L4PER_I2C1_WKDEP                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00a0)
+#define OMAP4430_RM_L4PER_I2C1_CONTEXT                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00a4)
+#define OMAP4430_PM_L4PER_I2C2_WKDEP                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00a8)
+#define OMAP4430_RM_L4PER_I2C2_CONTEXT                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00ac)
+#define OMAP4430_PM_L4PER_I2C3_WKDEP                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00b0)
+#define OMAP4430_RM_L4PER_I2C3_CONTEXT                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00b4)
+#define OMAP4430_PM_L4PER_I2C4_WKDEP                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00b8)
+#define OMAP4430_RM_L4PER_I2C4_CONTEXT                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00bc)
+#define OMAP4430_RM_L4PER_L4_PER_CONTEXT                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00c0)
+#define OMAP4430_PM_L4PER_MCASP2_WKDEP                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00d0)
+#define OMAP4430_RM_L4PER_MCASP2_CONTEXT                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00d4)
+#define OMAP4430_PM_L4PER_MCASP3_WKDEP                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00d8)
+#define OMAP4430_RM_L4PER_MCASP3_CONTEXT                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00dc)
+#define OMAP4430_PM_L4PER_MCBSP4_WKDEP                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00e0)
+#define OMAP4430_RM_L4PER_MCBSP4_CONTEXT                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00e4)
+#define OMAP4430_RM_L4PER_MGATE_CONTEXT                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00ec)
+#define OMAP4430_PM_L4PER_MCSPI1_WKDEP                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00f0)
+#define OMAP4430_RM_L4PER_MCSPI1_CONTEXT                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00f4)
+#define OMAP4430_PM_L4PER_MCSPI2_WKDEP                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00f8)
+#define OMAP4430_RM_L4PER_MCSPI2_CONTEXT                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00fc)
+#define OMAP4430_PM_L4PER_MCSPI3_WKDEP                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0100)
+#define OMAP4430_RM_L4PER_MCSPI3_CONTEXT                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0104)
+#define OMAP4430_PM_L4PER_MCSPI4_WKDEP                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0108)
+#define OMAP4430_RM_L4PER_MCSPI4_CONTEXT                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x010c)
+#define OMAP4430_PM_L4PER_MMCSD3_WKDEP                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0120)
+#define OMAP4430_RM_L4PER_MMCSD3_CONTEXT                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0124)
+#define OMAP4430_PM_L4PER_MMCSD4_WKDEP                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0128)
+#define OMAP4430_RM_L4PER_MMCSD4_CONTEXT                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x012c)
+#define OMAP4430_RM_L4PER_MSPROHG_CONTEXT               OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0134)
+#define OMAP4430_PM_L4PER_SLIMBUS2_WKDEP                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0138)
+#define OMAP4430_RM_L4PER_SLIMBUS2_CONTEXT              OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x013c)
+#define OMAP4430_PM_L4PER_UART1_WKDEP                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0140)
+#define OMAP4430_RM_L4PER_UART1_CONTEXT                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0144)
+#define OMAP4430_PM_L4PER_UART2_WKDEP                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0148)
+#define OMAP4430_RM_L4PER_UART2_CONTEXT                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x014c)
+#define OMAP4430_PM_L4PER_UART3_WKDEP                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0150)
+#define OMAP4430_RM_L4PER_UART3_CONTEXT                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0154)
+#define OMAP4430_PM_L4PER_UART4_WKDEP                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0158)
+#define OMAP4430_RM_L4PER_UART4_CONTEXT                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x015c)
+#define OMAP4430_PM_L4PER_MMCSD5_WKDEP                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0160)
+#define OMAP4430_RM_L4PER_MMCSD5_CONTEXT                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0164)
+#define OMAP4430_PM_L4PER_I2C5_WKDEP                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0168)
+#define OMAP4430_RM_L4PER_I2C5_CONTEXT                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x016c)
+#define OMAP4430_RM_L4SEC_AES1_CONTEXT                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x01a4)
+#define OMAP4430_RM_L4SEC_AES2_CONTEXT                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x01ac)
+#define OMAP4430_RM_L4SEC_DES3DES_CONTEXT               OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x01b4)
+#define OMAP4430_RM_L4SEC_PKAEIP29_CONTEXT              OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x01bc)
+#define OMAP4430_RM_L4SEC_RNG_CONTEXT                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x01c4)
+#define OMAP4430_RM_L4SEC_SHA2MD51_CONTEXT              OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x01cc)
+#define OMAP4430_RM_L4SEC_CRYPTODMA_CONTEXT             OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x01dc)
+
+/* PRM.CEFUSE_PRM register offsets */
+#define OMAP4430_PM_CEFUSE_PWRSTCTRL                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CEFUSE_MOD, 0x0000)
+#define OMAP4430_PM_CEFUSE_PWRSTST                      OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CEFUSE_MOD, 0x0004)
+#define OMAP4430_RM_CEFUSE_CEFUSE_CONTEXT               OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CEFUSE_MOD, 0x0024)
+
+/* PRM.WKUP_PRM register offsets */
+#define OMAP4430_RM_WKUP_L4WKUP_CONTEXT                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0024)
+#define OMAP4430_RM_WKUP_WDT1_CONTEXT                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x002c)
+#define OMAP4430_PM_WKUP_WDT2_WKDEP                     OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0030)
+#define OMAP4430_RM_WKUP_WDT2_CONTEXT                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0034)
+#define OMAP4430_PM_WKUP_GPIO1_WKDEP                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0038)
+#define OMAP4430_RM_WKUP_GPIO1_CONTEXT                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x003c)
+#define OMAP4430_PM_WKUP_TIMER1_WKDEP                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0040)
+#define OMAP4430_RM_WKUP_TIMER1_CONTEXT                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0044)
+#define OMAP4430_PM_WKUP_TIMER12_WKDEP                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0048)
+#define OMAP4430_RM_WKUP_TIMER12_CONTEXT                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x004c)
+#define OMAP4430_RM_WKUP_SYNCTIMER_CONTEXT              OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0054)
+#define OMAP4430_PM_WKUP_USIM_WKDEP                     OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0058)
+#define OMAP4430_RM_WKUP_USIM_CONTEXT                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x005c)
+#define OMAP4430_RM_WKUP_SARRAM_CONTEXT                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0064)
+#define OMAP4430_PM_WKUP_KEYBOARD_WKDEP                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0078)
+#define OMAP4430_RM_WKUP_KEYBOARD_CONTEXT               OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x007c)
+#define OMAP4430_PM_WKUP_RTC_WKDEP                      OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0080)
+#define OMAP4430_RM_WKUP_RTC_CONTEXT                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0084)
+
+/* PRM.WKUP_CM register offsets */
+#define OMAP4430_CM_WKUP_CLKSTCTRL                      OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0000)
+#define OMAP4430_CM_WKUP_L4WKUP_CLKCTRL                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0020)
+#define OMAP4430_CM_WKUP_WDT1_CLKCTRL                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0028)
+#define OMAP4430_CM_WKUP_WDT2_CLKCTRL                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0030)
+#define OMAP4430_CM_WKUP_GPIO1_CLKCTRL                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0038)
+#define OMAP4430_CM_WKUP_TIMER1_CLKCTRL                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0040)
+#define OMAP4430_CM_WKUP_TIMER12_CLKCTRL                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0048)
+#define OMAP4430_CM_WKUP_SYNCTIMER_CLKCTRL              OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0050)
+#define OMAP4430_CM_WKUP_USIM_CLKCTRL                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0058)
+#define OMAP4430_CM_WKUP_SARRAM_CLKCTRL                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0060)
+#define OMAP4430_CM_WKUP_KEYBOARD_CLKCTRL               OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0078)
+#define OMAP4430_CM_WKUP_RTC_CLKCTRL                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0080)
+#define OMAP4430_CM_WKUP_BANDGAP_CLKCTRL                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0088)
+
+/* PRM.EMU_PRM register offsets */
+#define OMAP4430_PM_EMU_PWRSTCTRL                       OMAP44XX_PRM_REGADDR(OMAP4430_PRM_EMU_MOD, 0x0000)
+#define OMAP4430_PM_EMU_PWRSTST                         OMAP44XX_PRM_REGADDR(OMAP4430_PRM_EMU_MOD, 0x0004)
+#define OMAP4430_RM_EMU_DEBUGSS_CONTEXT                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_EMU_MOD, 0x0024)
+
+/* PRM.EMU_CM register offsets */
+#define OMAP4430_CM_EMU_CLKSTCTRL                       OMAP44XX_PRM_REGADDR(OMAP4430_PRM_EMU_CM_MOD, 0x0000)
+#define OMAP4430_CM_EMU_DYNAMICDEP                      OMAP44XX_PRM_REGADDR(OMAP4430_PRM_EMU_CM_MOD, 0x0008)
+#define OMAP4430_CM_EMU_DEBUGSS_CLKCTRL                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_EMU_CM_MOD, 0x0020)
+
+/* PRM.DEVICE_PRM register offsets */
+#define OMAP4430_PRM_RSTCTRL                            OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0000)
+#define OMAP4430_PRM_RSTST                              OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0004)
+#define OMAP4430_PRM_RSTTIME                            OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0008)
+#define OMAP4430_PRM_CLKREQCTRL                         OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x000c)
+#define OMAP4430_PRM_VOLTCTRL                           OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0010)
+#define OMAP4430_PRM_PWRREQCTRL                         OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0014)
+#define OMAP4430_PRM_PSCON_COUNT                        OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0018)
+#define OMAP4430_PRM_IO_COUNT                           OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x001c)
+#define OMAP4430_PRM_IO_PMCTRL                          OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0020)
+#define OMAP4430_PRM_VOLTSETUP_WARMRESET                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0024)
+#define OMAP4430_PRM_VOLTSETUP_CORE_OFF                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0028)
+#define OMAP4430_PRM_VOLTSETUP_MPU_OFF                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x002c)
+#define OMAP4430_PRM_VOLTSETUP_IVA_OFF                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0030)
+#define OMAP4430_PRM_VOLTSETUP_CORE_RET_SLEEP           OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0034)
+#define OMAP4430_PRM_VOLTSETUP_MPU_RET_SLEEP            OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0038)
+#define OMAP4430_PRM_VOLTSETUP_IVA_RET_SLEEP            OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x003c)
+#define OMAP4430_PRM_VP_CORE_CONFIG                     OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0040)
+#define OMAP4430_PRM_VP_CORE_STATUS                     OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0044)
+#define OMAP4430_PRM_VP_CORE_VLIMITTO                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0048)
+#define OMAP4430_PRM_VP_CORE_VOLTAGE                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x004c)
+#define OMAP4430_PRM_VP_CORE_VSTEPMAX                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0050)
+#define OMAP4430_PRM_VP_CORE_VSTEPMIN                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0054)
+#define OMAP4430_PRM_VP_MPU_CONFIG                      OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0058)
+#define OMAP4430_PRM_VP_MPU_STATUS                      OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x005c)
+#define OMAP4430_PRM_VP_MPU_VLIMITTO                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0060)
+#define OMAP4430_PRM_VP_MPU_VOLTAGE                     OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0064)
+#define OMAP4430_PRM_VP_MPU_VSTEPMAX                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0068)
+#define OMAP4430_PRM_VP_MPU_VSTEPMIN                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x006c)
+#define OMAP4430_PRM_VP_IVA_CONFIG                      OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0070)
+#define OMAP4430_PRM_VP_IVA_STATUS                      OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0074)
+#define OMAP4430_PRM_VP_IVA_VLIMITTO                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0078)
+#define OMAP4430_PRM_VP_IVA_VOLTAGE                     OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x007c)
+#define OMAP4430_PRM_VP_IVA_VSTEPMAX                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0080)
+#define OMAP4430_PRM_VP_IVA_VSTEPMIN                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0084)
+#define OMAP4430_PRM_VC_SMPS_SA                         OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0088)
+#define OMAP4430_PRM_VC_VAL_SMPS_RA_VOL                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x008c)
+#define OMAP4430_PRM_VC_VAL_SMPS_RA_CMD                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0090)
+#define OMAP4430_PRM_VC_VAL_CMD_VDD_CORE_L              OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0094)
+#define OMAP4430_PRM_VC_VAL_CMD_VDD_MPU_L               OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0098)
+#define OMAP4430_PRM_VC_VAL_CMD_VDD_IVA_L               OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x009c)
+#define OMAP4430_PRM_VC_VAL_BYPASS                      OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00a0)
+#define OMAP4430_PRM_VC_CFG_CHANNEL                     OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00a4)
+#define OMAP4430_PRM_VC_CFG_I2C_MODE                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00a8)
+#define OMAP4430_PRM_VC_CFG_I2C_CLK                     OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00ac)
+#define OMAP4430_PRM_SRAM_COUNT                         OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00b0)
+#define OMAP4430_PRM_SRAM_WKUP_SETUP                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00b4)
+#define OMAP4430_PRM_LDO_SRAM_CORE_SETUP                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00b8)
+#define OMAP4430_PRM_LDO_SRAM_CORE_CTRL                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00bc)
+#define OMAP4430_PRM_LDO_SRAM_MPU_SETUP                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00c0)
+#define OMAP4430_PRM_LDO_SRAM_MPU_CTRL                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00c4)
+#define OMAP4430_PRM_LDO_SRAM_IVA_SETUP                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00c8)
+#define OMAP4430_PRM_LDO_SRAM_IVA_CTRL                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00cc)
+#define OMAP4430_PRM_LDO_ABB_MPU_SETUP                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00d0)
+#define OMAP4430_PRM_LDO_ABB_MPU_CTRL                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00d4)
+#define OMAP4430_PRM_LDO_ABB_IVA_SETUP                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00d8)
+#define OMAP4430_PRM_LDO_ABB_IVA_CTRL                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00dc)
+#define OMAP4430_PRM_LDO_BANDGAP_CTRL                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00e0)
+#define OMAP4430_PRM_DEVICE_OFF_CTRL                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00e4)
+#define OMAP4430_PRM_PHASE1_CNDP                        OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00e8)
+#define OMAP4430_PRM_PHASE2A_CNDP                       OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00ec)
+#define OMAP4430_PRM_PHASE2B_CNDP                       OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00f0)
+#define OMAP4430_PRM_MODEM_IF_CTRL                      OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00f4)
+
+/* CHIRON_PRCM */
+
+
+/* CHIRON_PRCM.CHIRONSS_OCP_SOCKET_PRCM register offsets */
+#define OMAP4430_REVISION_PRCM                          OMAP44XX_PRM_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_OCP_SOCKET_PRCM_MOD, 0x0000)
+
+/* CHIRON_PRCM.CHIRONSS_DEVICE_PRM register offsets */
+#define OMAP4430_CHIRON_PRCM_PRM_RSTST                  OMAP44XX_PRM_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_DEVICE_PRM_MOD, 0x0000)
+
+/* CHIRON_PRCM.CHIRONSS_CPU0 register offsets */
+#define OMAP4430_PM_PDA_CPU0_PWRSTCTRL                  OMAP44XX_PRM_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU0_MOD, 0x0000)
+#define OMAP4430_PM_PDA_CPU0_PWRSTST                    OMAP44XX_PRM_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU0_MOD, 0x0004)
+#define OMAP4430_RM_PDA_CPU0_CPU0_CONTEXT               OMAP44XX_PRM_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU0_MOD, 0x0008)
+#define OMAP4430_RM_PDA_CPU0_CPU0_RSTCTRL               OMAP44XX_PRM_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU0_MOD, 0x000c)
+#define OMAP4430_RM_PDA_CPU0_CPU0_RSTST                 OMAP44XX_PRM_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU0_MOD, 0x0010)
+#define OMAP4430_CM_PDA_CPU0_CPU0_CLKCTRL               OMAP44XX_PRM_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU0_MOD, 0x0014)
+#define OMAP4430_CM_PDA_CPU0_CLKSTCTRL                  OMAP44XX_PRM_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU0_MOD, 0x0018)
+
+/* CHIRON_PRCM.CHIRONSS_CPU1 register offsets */
+#define OMAP4430_PM_PDA_CPU1_PWRSTCTRL                  OMAP44XX_PRM_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU1_MOD, 0x0000)
+#define OMAP4430_PM_PDA_CPU1_PWRSTST                    OMAP44XX_PRM_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU1_MOD, 0x0004)
+#define OMAP4430_RM_PDA_CPU1_CPU1_CONTEXT               OMAP44XX_PRM_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU1_MOD, 0x0008)
+#define OMAP4430_RM_PDA_CPU1_CPU1_RSTCTRL               OMAP44XX_PRM_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU1_MOD, 0x000c)
+#define OMAP4430_RM_PDA_CPU1_CPU1_RSTST                 OMAP44XX_PRM_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU1_MOD, 0x0010)
+#define OMAP4430_CM_PDA_CPU1_CPU1_CLKCTRL               OMAP44XX_PRM_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU1_MOD, 0x0014)
+#define OMAP4430_CM_PDA_CPU1_CLKSTCTRL                  OMAP44XX_PRM_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU1_MOD, 0x0018)
+#endif
diff --git a/arch/arm/mach-omap2/sdrc.h b/arch/arm/mach-omap2/sdrc.h
index 48207b018989..68f57bb67fc5 100644
--- a/arch/arm/mach-omap2/sdrc.h
+++ b/arch/arm/mach-omap2/sdrc.h
@@ -18,6 +18,9 @@
 #include <plat/sdrc.h>
 
 #ifndef __ASSEMBLER__
+
+#include <linux/io.h>
+
 extern void __iomem *omap2_sdrc_base;
 extern void __iomem *omap2_sms_base;
 
@@ -56,4 +59,20 @@ static inline u32 sms_read_reg(u16 reg)
                         OMAP2_L3_IO_ADDRESS(OMAP343X_SDRC_BASE + (reg))
 #endif  /* __ASSEMBLER__ */
 
+/* Minimum frequency that the SDRC DLL can lock at */
+#define MIN_SDRC_DLL_LOCK_FREQ          83000000
+
+/* Scale factor for fixed-point arith in omap3_core_dpll_m2_set_rate() */
+#define SDRC_MPURATE_SCALE              8
+
+/* 2^SDRC_MPURATE_BASE_SHIFT: MPU MHz that SDRC_MPURATE_LOOPS is defined for */
+#define SDRC_MPURATE_BASE_SHIFT         9
+
+/*
+ * SDRC_MPURATE_LOOPS: Number of MPU loops to execute at
+ * 2^MPURATE_BASE_SHIFT MHz for SDRC to stabilize
+ */
+#define SDRC_MPURATE_LOOPS              96
+
+
 #endif
diff --git a/arch/arm/mach-omap2/serial.c b/arch/arm/mach-omap2/serial.c
index 2e17b57f5b23..19805a7de06c 100644
--- a/arch/arm/mach-omap2/serial.c
+++ b/arch/arm/mach-omap2/serial.c
@@ -33,6 +33,7 @@
 #include "pm.h"
 #include "prm-regbits-34xx.h"
 
+#define UART_OMAP_NO_EMPTY_FIFO_READ_IP_REV     0x52
 #define UART_OMAP_WER           0x17    /* Wake-up enable register */
 
 #define DEFAULT_TIMEOUT (5 * HZ)
@@ -572,6 +573,23 @@ static struct omap_uart_state omap_uart[] = {
 #endif
 };
 
+/*
+ * Override the default 8250 read handler: mem_serial_in()
+ * Empty RX fifo read causes an abort on omap3630 and omap4
+ * This function makes sure that an empty rx fifo is not read on these silicons
+ * (OMAP1/2/3430 are not affected)
+ */
+static unsigned int serial_in_override(struct uart_port *up, int offset)
+{
+        if (UART_RX == offset) {
+                unsigned int lsr;
+                lsr = serial_read_reg(omap_uart[up->line].p, UART_LSR);
+                if (!(lsr & UART_LSR_DR))
+                        return -EPERM;
+        }
+        return serial_read_reg(omap_uart[up->line].p, offset);
+}
+
 void __init omap_serial_early_init(void)
 {
         int i;
@@ -622,33 +640,74 @@ void __init omap_serial_early_init(void)
                 uart->num = i;
                 p->private_data = uart;
                 uart->p = p;
-                list_add_tail(&uart->node, &uart_list);
 
                 if (cpu_is_omap44xx())
                         p->irq += 32;
-
-                omap_uart_enable_clocks(uart);
         }
 }
 
-void __init omap_serial_init(void)
+/**
+ * omap_serial_init_port() - initialize single serial port
+ * @port: serial port number (0-3)
+ *
+ * This function initialies serial driver for given @port only.
+ * Platforms can call this function instead of omap_serial_init()
+ * if they don't plan to use all available UARTs as serial ports.
+ *
+ * Don't mix calls to omap_serial_init_port() and omap_serial_init(),
+ * use only one of the two.
+ */
+void __init omap_serial_init_port(int port)
 {
-        int i;
+        struct omap_uart_state *uart;
+        struct platform_device *pdev;
+        struct device *dev;
 
-        for (i = 0; i < ARRAY_SIZE(omap_uart); i++) {
-                struct omap_uart_state *uart = &omap_uart[i];
-                struct platform_device *pdev = &uart->pdev;
-                struct device *dev = &pdev->dev;
+        BUG_ON(port < 0);
+        BUG_ON(port >= ARRAY_SIZE(omap_uart));
 
-                omap_uart_reset(uart);
-                omap_uart_idle_init(uart);
+        uart = &omap_uart[port];
+        pdev = &uart->pdev;
+        dev = &pdev->dev;
 
-                if (WARN_ON(platform_device_register(pdev)))
-                        continue;
-                if ((cpu_is_omap34xx() && uart->padconf) ||
-                    (uart->wk_en && uart->wk_mask)) {
-                        device_init_wakeup(dev, true);
-                        DEV_CREATE_FILE(dev, &dev_attr_sleep_timeout);
-                }
+        omap_uart_enable_clocks(uart);
+
+        omap_uart_reset(uart);
+        omap_uart_idle_init(uart);
+
+        list_add_tail(&uart->node, &uart_list);
+
+        if (WARN_ON(platform_device_register(pdev)))
+                return;
+
+        if ((cpu_is_omap34xx() && uart->padconf) ||
+            (uart->wk_en && uart->wk_mask)) {
+                device_init_wakeup(dev, true);
+                DEV_CREATE_FILE(dev, &dev_attr_sleep_timeout);
         }
+
+                /* omap44xx: Never read empty UART fifo
+                 * omap3xxx: Never read empty UART fifo on UARTs
+                 * with IP rev >=0x52
+                 */
+                if (cpu_is_omap44xx())
+                        uart->p->serial_in = serial_in_override;
+                else if ((serial_read_reg(uart->p, UART_OMAP_MVER) & 0xFF)
+                                >= UART_OMAP_NO_EMPTY_FIFO_READ_IP_REV)
+                        uart->p->serial_in = serial_in_override;
+}
+
+/**
+ * omap_serial_init() - intialize all supported serial ports
+ *
+ * Initializes all available UARTs as serial ports. Platforms
+ * can call this function when they want to have default behaviour
+ * for serial ports (e.g initialize them all as serial ports).
+ */
+void __init omap_serial_init(void)
+{
+        int i;
+
+        for (i = 0; i < ARRAY_SIZE(omap_uart); i++)
+                omap_serial_init_port(i);
 }
diff --git a/arch/arm/mach-omap2/sram34xx.S b/arch/arm/mach-omap2/sram34xx.S
index 82aa4a3d160c..de99ba2a57ab 100644
--- a/arch/arm/mach-omap2/sram34xx.S
+++ b/arch/arm/mach-omap2/sram34xx.S
@@ -91,8 +91,19 @@
  *  new SDRC_ACTIM_CTRL_B_1 register contents
  *  new SDRC_MR_1 register value
  *
- * If the param SDRC_RFR_CTRL_1 is 0, the parameters
- *  are not programmed into the SDRC CS1 registers
+ * If the param SDRC_RFR_CTRL_1 is 0, the parameters are not programmed into
+ * the SDRC CS1 registers
+ *
+ * NOTE: This code no longer attempts to program the SDRC AC timing and MR
+ * registers.  This is because the code currently cannot ensure that all
+ * L3 initiators (e.g., sDMA, IVA, DSS DISPC, etc.) are not accessing the
+ * SDRAM when the registers are written.  If the registers are changed while
+ * an initiator is accessing SDRAM, memory can be corrupted and/or the SDRC
+ * may enter an unpredictable state.  In the future, the intent is to
+ * re-enable this code in cases where we can ensure that no initiators are
+ * touching the SDRAM.  Until that time, users who know that their use case
+ * can satisfy the above requirement can enable the CONFIG_OMAP3_SDRC_AC_TIMING
+ * option.
  */
 ENTRY(omap3_sram_configure_core_dpll)
         stmfd   sp!, {r1-r12, lr}       @ store regs to stack
@@ -219,6 +230,7 @@ configure_sdrc:
         ldr     r12, omap_sdrc_rfr_ctrl_0_val   @ fetch value from SRAM
         ldr     r11, omap3_sdrc_rfr_ctrl_0      @ fetch addr from SRAM
         str     r12, [r11]                      @ store
+#ifdef CONFIG_OMAP3_SDRC_AC_TIMING
         ldr     r12, omap_sdrc_actim_ctrl_a_0_val
         ldr     r11, omap3_sdrc_actim_ctrl_a_0
         str     r12, [r11]
@@ -228,11 +240,13 @@ configure_sdrc:
         ldr     r12, omap_sdrc_mr_0_val
         ldr     r11, omap3_sdrc_mr_0
         str     r12, [r11]
+#endif
         ldr     r12, omap_sdrc_rfr_ctrl_1_val
         cmp     r12, #0                 @ if SDRC_RFR_CTRL_1 is 0,
         beq     skip_cs1_prog           @  do not program cs1 params
         ldr     r11, omap3_sdrc_rfr_ctrl_1
         str     r12, [r11]
+#ifdef CONFIG_OMAP3_SDRC_AC_TIMING
         ldr     r12, omap_sdrc_actim_ctrl_a_1_val
         ldr     r11, omap3_sdrc_actim_ctrl_a_1
         str     r12, [r11]
@@ -242,6 +256,7 @@ configure_sdrc:
         ldr     r12, omap_sdrc_mr_1_val
         ldr     r11, omap3_sdrc_mr_1
         str     r12, [r11]
+#endif
 skip_cs1_prog:
         ldr     r12, [r11]              @ posted-write barrier for SDRC
         bx      lr
diff --git a/arch/arm/mach-omap2/usb-ehci.c b/arch/arm/mach-omap2/usb-ehci.c
index e448abd5ec5d..f1df873d59db 100644
--- a/arch/arm/mach-omap2/usb-ehci.c
+++ b/arch/arm/mach-omap2/usb-ehci.c
@@ -27,6 +27,8 @@
 #include <mach/irqs.h>
 #include <plat/usb.h>
 
+#include "mux.h"
+
 #if defined(CONFIG_USB_EHCI_HCD) || defined(CONFIG_USB_EHCI_HCD_MODULE)
 
 static struct resource ehci_resources[] = {
@@ -72,32 +74,44 @@ static void setup_ehci_io_mux(enum ehci_hcd_omap_mode *port_mode)
 {
         switch (port_mode[0]) {
         case EHCI_HCD_OMAP_MODE_PHY:
-                omap_cfg_reg(Y9_3430_USB1HS_PHY_STP);
-                omap_cfg_reg(Y8_3430_USB1HS_PHY_CLK);
-                omap_cfg_reg(AA14_3430_USB1HS_PHY_DIR);
-                omap_cfg_reg(AA11_3430_USB1HS_PHY_NXT);
-                omap_cfg_reg(W13_3430_USB1HS_PHY_DATA0);
-                omap_cfg_reg(W12_3430_USB1HS_PHY_DATA1);
-                omap_cfg_reg(W11_3430_USB1HS_PHY_DATA2);
-                omap_cfg_reg(Y11_3430_USB1HS_PHY_DATA3);
-                omap_cfg_reg(W9_3430_USB1HS_PHY_DATA4);
-                omap_cfg_reg(Y12_3430_USB1HS_PHY_DATA5);
-                omap_cfg_reg(W8_3430_USB1HS_PHY_DATA6);
-                omap_cfg_reg(Y13_3430_USB1HS_PHY_DATA7);
+                omap_mux_init_signal("hsusb1_stp", OMAP_PIN_OUTPUT);
+                omap_mux_init_signal("hsusb1_clk", OMAP_PIN_OUTPUT);
+                omap_mux_init_signal("hsusb1_dir", OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("hsusb1_nxt", OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("hsusb1_data0", OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("hsusb1_data1", OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("hsusb1_data2", OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("hsusb1_data3", OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("hsusb1_data4", OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("hsusb1_data5", OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("hsusb1_data6", OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("hsusb1_data7", OMAP_PIN_INPUT_PULLDOWN);
                 break;
         case EHCI_HCD_OMAP_MODE_TLL:
-                omap_cfg_reg(Y9_3430_USB1HS_TLL_STP);
-                omap_cfg_reg(Y8_3430_USB1HS_TLL_CLK);
-                omap_cfg_reg(AA14_3430_USB1HS_TLL_DIR);
-                omap_cfg_reg(AA11_3430_USB1HS_TLL_NXT);
-                omap_cfg_reg(W13_3430_USB1HS_TLL_DATA0);
-                omap_cfg_reg(W12_3430_USB1HS_TLL_DATA1);
-                omap_cfg_reg(W11_3430_USB1HS_TLL_DATA2);
-                omap_cfg_reg(Y11_3430_USB1HS_TLL_DATA3);
-                omap_cfg_reg(W9_3430_USB1HS_TLL_DATA4);
-                omap_cfg_reg(Y12_3430_USB1HS_TLL_DATA5);
-                omap_cfg_reg(W8_3430_USB1HS_TLL_DATA6);
-                omap_cfg_reg(Y13_3430_USB1HS_TLL_DATA7);
+                omap_mux_init_signal("hsusb1_tll_stp",
+                        OMAP_PIN_INPUT_PULLUP);
+                omap_mux_init_signal("hsusb1_tll_clk",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("hsusb1_tll_dir",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("hsusb1_tll_nxt",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("hsusb1_tll_data0",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("hsusb1_tll_data1",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("hsusb1_tll_data2",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("hsusb1_tll_data3",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("hsusb1_tll_data4",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("hsusb1_tll_data5",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("hsusb1_tll_data6",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("hsusb1_tll_data7",
+                        OMAP_PIN_INPUT_PULLDOWN);
                 break;
         case EHCI_HCD_OMAP_MODE_UNKNOWN:
                 /* FALLTHROUGH */
@@ -107,32 +121,52 @@ static void setup_ehci_io_mux(enum ehci_hcd_omap_mode *port_mode)
 
         switch (port_mode[1]) {
         case EHCI_HCD_OMAP_MODE_PHY:
-                omap_cfg_reg(AA10_3430_USB2HS_PHY_STP);
-                omap_cfg_reg(AA8_3430_USB2HS_PHY_CLK);
-                omap_cfg_reg(AA9_3430_USB2HS_PHY_DIR);
-                omap_cfg_reg(AB11_3430_USB2HS_PHY_NXT);
-                omap_cfg_reg(AB10_3430_USB2HS_PHY_DATA0);
-                omap_cfg_reg(AB9_3430_USB2HS_PHY_DATA1);
-                omap_cfg_reg(W3_3430_USB2HS_PHY_DATA2);
-                omap_cfg_reg(T4_3430_USB2HS_PHY_DATA3);
-                omap_cfg_reg(T3_3430_USB2HS_PHY_DATA4);
-                omap_cfg_reg(R3_3430_USB2HS_PHY_DATA5);
-                omap_cfg_reg(R4_3430_USB2HS_PHY_DATA6);
-                omap_cfg_reg(T2_3430_USB2HS_PHY_DATA7);
+                omap_mux_init_signal("hsusb2_stp", OMAP_PIN_OUTPUT);
+                omap_mux_init_signal("hsusb2_clk", OMAP_PIN_OUTPUT);
+                omap_mux_init_signal("hsusb2_dir", OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("hsusb2_nxt", OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("hsusb2_data0",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("hsusb2_data1",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("hsusb2_data2",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("hsusb2_data3",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("hsusb2_data4",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("hsusb2_data5",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("hsusb2_data6",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("hsusb2_data7",
+                        OMAP_PIN_INPUT_PULLDOWN);
                 break;
         case EHCI_HCD_OMAP_MODE_TLL:
-                omap_cfg_reg(AA10_3430_USB2HS_TLL_STP);
-                omap_cfg_reg(AA8_3430_USB2HS_TLL_CLK);
-                omap_cfg_reg(AA9_3430_USB2HS_TLL_DIR);
-                omap_cfg_reg(AB11_3430_USB2HS_TLL_NXT);
-                omap_cfg_reg(AB10_3430_USB2HS_TLL_DATA0);
-                omap_cfg_reg(AB9_3430_USB2HS_TLL_DATA1);
-                omap_cfg_reg(W3_3430_USB2HS_TLL_DATA2);
-                omap_cfg_reg(T4_3430_USB2HS_TLL_DATA3);
-                omap_cfg_reg(T3_3430_USB2HS_TLL_DATA4);
-                omap_cfg_reg(R3_3430_USB2HS_TLL_DATA5);
-                omap_cfg_reg(R4_3430_USB2HS_TLL_DATA6);
-                omap_cfg_reg(T2_3430_USB2HS_TLL_DATA7);
+                omap_mux_init_signal("hsusb2_tll_stp",
+                        OMAP_PIN_INPUT_PULLUP);
+                omap_mux_init_signal("hsusb2_tll_clk",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("hsusb2_tll_dir",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("hsusb2_tll_nxt",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("hsusb2_tll_data0",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("hsusb2_tll_data1",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("hsusb2_tll_data2",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("hsusb2_tll_data3",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("hsusb2_tll_data4",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("hsusb2_tll_data5",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("hsusb2_tll_data6",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("hsusb2_tll_data7",
+                        OMAP_PIN_INPUT_PULLDOWN);
                 break;
         case EHCI_HCD_OMAP_MODE_UNKNOWN:
                 /* FALLTHROUGH */
@@ -145,18 +179,30 @@ static void setup_ehci_io_mux(enum ehci_hcd_omap_mode *port_mode)
                 printk(KERN_WARNING "Port3 can't be used in PHY mode\n");
                 break;
         case EHCI_HCD_OMAP_MODE_TLL:
-                omap_cfg_reg(AB3_3430_USB3HS_TLL_STP);
-                omap_cfg_reg(AA6_3430_USB3HS_TLL_CLK);
-                omap_cfg_reg(AA3_3430_USB3HS_TLL_DIR);
-                omap_cfg_reg(Y3_3430_USB3HS_TLL_NXT);
-                omap_cfg_reg(AA5_3430_USB3HS_TLL_DATA0);
-                omap_cfg_reg(Y4_3430_USB3HS_TLL_DATA1);
-                omap_cfg_reg(Y5_3430_USB3HS_TLL_DATA2);
-                omap_cfg_reg(W5_3430_USB3HS_TLL_DATA3);
-                omap_cfg_reg(AB12_3430_USB3HS_TLL_DATA4);
-                omap_cfg_reg(AB13_3430_USB3HS_TLL_DATA5);
-                omap_cfg_reg(AA13_3430_USB3HS_TLL_DATA6);
-                omap_cfg_reg(AA12_3430_USB3HS_TLL_DATA7);
+                omap_mux_init_signal("hsusb3_tll_stp",
+                        OMAP_PIN_INPUT_PULLUP);
+                omap_mux_init_signal("hsusb3_tll_clk",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("hsusb3_tll_dir",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("hsusb3_tll_nxt",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("hsusb3_tll_data0",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("hsusb3_tll_data1",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("hsusb3_tll_data2",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("hsusb3_tll_data3",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("hsusb3_tll_data4",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("hsusb3_tll_data5",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("hsusb3_tll_data6",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("hsusb3_tll_data7",
+                        OMAP_PIN_INPUT_PULLDOWN);
                 break;
         case EHCI_HCD_OMAP_MODE_UNKNOWN:
                 /* FALLTHROUGH */
diff --git a/arch/arm/mach-pxa/Kconfig b/arch/arm/mach-pxa/Kconfig
index d89c6adbe8bc..8a0837ea0294 100644
--- a/arch/arm/mach-pxa/Kconfig
+++ b/arch/arm/mach-pxa/Kconfig
@@ -63,6 +63,15 @@ config ARCH_VIPER
         select HAVE_PWM
         select PXA_HAVE_BOARD_IRQS
         select PXA_HAVE_ISA_IRQS
+        select ARCOM_PCMCIA
+
+config MACH_ARCOM_ZEUS
+        bool "Arcom/Eurotech ZEUS SBC"
+        select PXA27x
+        select ISA
+        select PXA_HAVE_BOARD_IRQS
+        select PXA_HAVE_ISA_IRQS
+        select ARCOM_PCMCIA
 
 config MACH_BALLOON3
         bool "Balloon 3 board"
@@ -101,6 +110,8 @@ config MACH_CM_X300
         bool "CompuLab CM-X300 modules"
         select PXA3xx
         select CPU_PXA300
+        select CPU_PXA310
+        select HAVE_PWM
 
 config ARCH_GUMSTIX
         bool "Gumstix XScale 255 boards"
@@ -179,6 +190,11 @@ config MACH_TRIZEPS_ANY
 
 endchoice
 
+config ARCOM_PCMCIA
+        bool
+        help
+          Generic option for Arcom Viper/Zeus PCMCIA
+
 config TRIZEPS_PCMCIA
         bool
         help
@@ -226,7 +242,6 @@ config MACH_COLIBRI300
         select PXA3xx
         select CPU_PXA300
         select CPU_PXA310
-        select HAVE_PWM
 
 config MACH_COLIBRI320
         bool "Toradex Colibri PXA320"
diff --git a/arch/arm/mach-pxa/Makefile b/arch/arm/mach-pxa/Makefile
index b5d29e60a341..f64afda7e6f6 100644
--- a/arch/arm/mach-pxa/Makefile
+++ b/arch/arm/mach-pxa/Makefile
@@ -38,6 +38,7 @@ obj-$(CONFIG_MACH_SAAR)		+= saar.o
 # 3rd Party Dev Platforms
 obj-$(CONFIG_ARCH_PXA_IDP)      += idp.o
 obj-$(CONFIG_ARCH_VIPER)        += viper.o
+obj-$(CONFIG_MACH_ARCOM_ZEUS)   += zeus.o
 obj-$(CONFIG_MACH_BALLOON3)     += balloon3.o
 obj-$(CONFIG_MACH_CSB726)       += csb726.o
 obj-$(CONFIG_CSB726_CSB701)     += csb701.o
diff --git a/arch/arm/mach-pxa/devices.c b/arch/arm/mach-pxa/devices.c
index 3395463bb5a6..8e10db148f1b 100644
--- a/arch/arm/mach-pxa/devices.c
+++ b/arch/arm/mach-pxa/devices.c
@@ -4,7 +4,6 @@
 #include <linux/platform_device.h>
 #include <linux/dma-mapping.h>
 
-#include <mach/hardware.h>
 #include <mach/udc.h>
 #include <mach/pxafb.h>
 #include <mach/mmc.h>
@@ -14,6 +13,7 @@
 #include <mach/pxa2xx_spi.h>
 #include <mach/camera.h>
 #include <mach/audio.h>
+#include <mach/hardware.h>
 #include <plat/i2c.h>
 #include <plat/pxa3xx_nand.h>
 
diff --git a/arch/arm/mach-pxa/em-x270.c b/arch/arm/mach-pxa/em-x270.c
index 1c0de808b54d..c8a01bc85fde 100644
--- a/arch/arm/mach-pxa/em-x270.c
+++ b/arch/arm/mach-pxa/em-x270.c
@@ -497,16 +497,15 @@ static int em_x270_usb_hub_init(void)
                 goto err_free_vbus_gpio;
 
         /* USB Hub power-on and reset */
-        gpio_direction_output(usb_hub_reset, 0);
+        gpio_direction_output(usb_hub_reset, 1);
+        gpio_direction_output(GPIO9_USB_VBUS_EN, 0);
         regulator_enable(em_x270_usb_ldo);
-        gpio_set_value(usb_hub_reset, 1);
         gpio_set_value(usb_hub_reset, 0);
+        gpio_set_value(usb_hub_reset, 1);
         regulator_disable(em_x270_usb_ldo);
         regulator_enable(em_x270_usb_ldo);
-        gpio_set_value(usb_hub_reset, 1);
-
-        /* enable VBUS */
-        gpio_direction_output(GPIO9_USB_VBUS_EN, 1);
+        gpio_set_value(usb_hub_reset, 0);
+        gpio_set_value(GPIO9_USB_VBUS_EN, 1);
 
         return 0;
 
diff --git a/arch/arm/mach-pxa/include/mach/arcom-pcmcia.h b/arch/arm/mach-pxa/include/mach/arcom-pcmcia.h
new file mode 100644
index 000000000000..d428be4db44c
--- /dev/null
+++ b/arch/arm/mach-pxa/include/mach/arcom-pcmcia.h
@@ -0,0 +1,11 @@
+#ifndef __ARCOM_PCMCIA_H
+#define __ARCOM_PCMCIA_H
+
+struct arcom_pcmcia_pdata {
+        int     cd_gpio;
+        int     rdy_gpio;
+        int     pwr_gpio;
+        void    (*reset)(int state);
+};
+
+#endif
diff --git a/arch/arm/mach-pxa/include/mach/viper.h b/arch/arm/mach-pxa/include/mach/viper.h
index 10988c270ca3..5f5fbf1f6489 100644
--- a/arch/arm/mach-pxa/include/mach/viper.h
+++ b/arch/arm/mach-pxa/include/mach/viper.h
@@ -85,8 +85,6 @@
 /* Interrupt and Configuration Register (VIPER_ICR) */
 /* This is a write only register. Only CF_RST is used under Linux */
 
-extern void viper_cf_rst(int state);
-
 #define VIPER_ICR_RETRIG        (1 << 0)
 #define VIPER_ICR_AUTO_CLR      (1 << 1)
 #define VIPER_ICR_R_DIS         (1 << 2)
diff --git a/arch/arm/mach-pxa/include/mach/zeus.h b/arch/arm/mach-pxa/include/mach/zeus.h
new file mode 100644
index 000000000000..c387046d2f28
--- /dev/null
+++ b/arch/arm/mach-pxa/include/mach/zeus.h
@@ -0,0 +1,82 @@
+/*
+ *  arch/arm/mach-pxa/include/mach/zeus.h
+ *
+ *  Author:     David Vrabel
+ *  Created:    Sept 28, 2005
+ *  Copyright:  Arcom Control Systems Ltd.
+ *
+ *  Maintained by: Marc Zyngier <maz@misterjones.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef _MACH_ZEUS_H
+#define _MACH_ZEUS_H
+
+/* Physical addresses */
+#define ZEUS_FLASH_PHYS         PXA_CS0_PHYS
+#define ZEUS_ETH0_PHYS          PXA_CS1_PHYS
+#define ZEUS_ETH1_PHYS          PXA_CS2_PHYS
+#define ZEUS_CPLD_PHYS          (PXA_CS4_PHYS+0x2000000)
+#define ZEUS_SRAM_PHYS          PXA_CS5_PHYS
+#define ZEUS_PC104IO_PHYS       (0x30000000)
+
+#define ZEUS_CPLD_VERSION_PHYS  (ZEUS_CPLD_PHYS + 0x00000000)
+#define ZEUS_CPLD_ISA_IRQ_PHYS  (ZEUS_CPLD_PHYS + 0x00800000)
+#define ZEUS_CPLD_CONTROL_PHYS  (ZEUS_CPLD_PHYS + 0x01000000)
+#define ZEUS_CPLD_EXTWDOG_PHYS  (ZEUS_CPLD_PHYS + 0x01800000)
+
+/* GPIOs */
+#define ZEUS_AC97_GPIO          0
+#define ZEUS_WAKEUP_GPIO        1
+#define ZEUS_UARTA_GPIO         9
+#define ZEUS_UARTB_GPIO         10
+#define ZEUS_UARTC_GPIO         12
+#define ZEUS_UARTD_GPIO         11
+#define ZEUS_ETH0_GPIO          14
+#define ZEUS_ISA_GPIO           17
+#define ZEUS_BKLEN_GPIO         19
+#define ZEUS_USB2_PWREN_GPIO    22
+#define ZEUS_PTT_GPIO           27
+#define ZEUS_CF_CD_GPIO         35
+#define ZEUS_MMC_WP_GPIO        52
+#define ZEUS_MMC_CD_GPIO        53
+#define ZEUS_EXTGPIO_GPIO       91
+#define ZEUS_CF_PWEN_GPIO       97
+#define ZEUS_CF_RDY_GPIO        99
+#define ZEUS_LCD_EN_GPIO        101
+#define ZEUS_ETH1_GPIO          113
+#define ZEUS_CAN_GPIO           116
+
+#define ZEUS_EXT0_GPIO_BASE     128
+#define ZEUS_EXT1_GPIO_BASE     160
+#define ZEUS_USER_GPIO_BASE     192
+
+#define ZEUS_EXT0_GPIO(x)       (ZEUS_EXT0_GPIO_BASE + (x))
+#define ZEUS_EXT1_GPIO(x)       (ZEUS_EXT1_GPIO_BASE + (x))
+#define ZEUS_USER_GPIO(x)       (ZEUS_USER_GPIO_BASE + (x))
+
+/*
+ * CPLD registers:
+ * Only 4 registers, but spreaded over a 32MB address space.
+ * Be gentle, and remap that over 32kB...
+ */
+
+#define ZEUS_CPLD               (0xf0000000)
+#define ZEUS_CPLD_VERSION       (ZEUS_CPLD + 0x0000)
+#define ZEUS_CPLD_ISA_IRQ       (ZEUS_CPLD + 0x1000)
+#define ZEUS_CPLD_CONTROL       (ZEUS_CPLD + 0x2000)
+#define ZEUS_CPLD_EXTWDOG       (ZEUS_CPLD + 0x3000)
+
+/* CPLD register bits */
+#define ZEUS_CPLD_CONTROL_CF_RST        0x01
+
+#define ZEUS_PC104IO            (0xf1000000)
+
+#define ZEUS_SRAM_SIZE          (256 * 1024)
+
+#endif
+
+
diff --git a/arch/arm/mach-pxa/viper.c b/arch/arm/mach-pxa/viper.c
index cf0d71b7797e..5352b4e5a7dd 100644
--- a/arch/arm/mach-pxa/viper.c
+++ b/arch/arm/mach-pxa/viper.c
@@ -47,6 +47,7 @@
 #include <mach/pxafb.h>
 #include <plat/i2c.h>
 #include <mach/regs-uart.h>
+#include <mach/arcom-pcmcia.h>
 #include <mach/viper.h>
 
 #include <asm/setup.h>
@@ -76,14 +77,28 @@ static void viper_icr_clear_bit(unsigned int bit)
 }
 
 /* This function is used from the pcmcia module to reset the CF */
-void viper_cf_rst(int state)
+static void viper_cf_reset(int state)
 {
         if (state)
                 viper_icr_set_bit(VIPER_ICR_CF_RST);
         else
                 viper_icr_clear_bit(VIPER_ICR_CF_RST);
 }
-EXPORT_SYMBOL(viper_cf_rst);
+
+static struct arcom_pcmcia_pdata viper_pcmcia_info = {
+        .cd_gpio        = VIPER_CF_CD_GPIO,
+        .rdy_gpio       = VIPER_CF_RDY_GPIO,
+        .pwr_gpio       = VIPER_CF_POWER_GPIO,
+        .reset          = viper_cf_reset,
+};
+
+static struct platform_device viper_pcmcia_device = {
+        .name           = "viper-pcmcia",
+        .id             = -1,
+        .dev            = {
+                .platform_data  = &viper_pcmcia_info,
+        },
+};
 
 /*
  * The CPLD version register was not present on VIPER boards prior to
@@ -685,6 +700,7 @@ static struct platform_device *viper_devs[] __initdata = {
         &viper_mtd_devices[0],
         &viper_mtd_devices[1],
         &viper_backlight_device,
+        &viper_pcmcia_device,
 };
 
 static mfp_cfg_t viper_pin_config[] __initdata = {
diff --git a/arch/arm/mach-pxa/zeus.c b/arch/arm/mach-pxa/zeus.c
new file mode 100644
index 000000000000..5b986a8bd9e6
--- /dev/null
+++ b/arch/arm/mach-pxa/zeus.c
@@ -0,0 +1,820 @@
+/*
+ *  Support for the Arcom ZEUS.
+ *
+ *  Copyright (C) 2006 Arcom Control Systems Ltd.
+ *
+ *  Loosely based on Arcom's 2.6.16.28.
+ *  Maintained by Marc Zyngier <maz@misterjones.org>
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ */
+
+#include <linux/cpufreq.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/pm.h>
+#include <linux/gpio.h>
+#include <linux/serial_8250.h>
+#include <linux/dm9000.h>
+#include <linux/mmc/host.h>
+#include <linux/spi/spi.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/partitions.h>
+#include <linux/mtd/physmap.h>
+#include <linux/i2c.h>
+#include <linux/i2c/pca953x.h>
+
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+
+#include <plat/i2c.h>
+
+#include <mach/pxa2xx-regs.h>
+#include <mach/regs-uart.h>
+#include <mach/ohci.h>
+#include <mach/mmc.h>
+#include <mach/pxa27x-udc.h>
+#include <mach/udc.h>
+#include <mach/pxafb.h>
+#include <mach/pxa2xx_spi.h>
+#include <mach/mfp-pxa27x.h>
+#include <mach/pm.h>
+#include <mach/audio.h>
+#include <mach/arcom-pcmcia.h>
+#include <mach/zeus.h>
+
+#include "generic.h"
+
+/*
+ * Interrupt handling
+ */
+
+static unsigned long zeus_irq_enabled_mask;
+static const int zeus_isa_irqs[] = { 3, 4, 5, 6, 7, 10, 11, 12, };
+static const int zeus_isa_irq_map[] = {
+        0,              /* ISA irq #0, invalid */
+        0,              /* ISA irq #1, invalid */
+        0,              /* ISA irq #2, invalid */
+        1 << 0,         /* ISA irq #3 */
+        1 << 1,         /* ISA irq #4 */
+        1 << 2,         /* ISA irq #5 */
+        1 << 3,         /* ISA irq #6 */
+        1 << 4,         /* ISA irq #7 */
+        0,              /* ISA irq #8, invalid */
+        0,              /* ISA irq #9, invalid */
+        1 << 5,         /* ISA irq #10 */
+        1 << 6,         /* ISA irq #11 */
+        1 << 7,         /* ISA irq #12 */
+};
+
+static inline int zeus_irq_to_bitmask(unsigned int irq)
+{
+        return zeus_isa_irq_map[irq - PXA_ISA_IRQ(0)];
+}
+
+static inline int zeus_bit_to_irq(int bit)
+{
+        return zeus_isa_irqs[bit] + PXA_ISA_IRQ(0);
+}
+
+static void zeus_ack_irq(unsigned int irq)
+{
+        __raw_writew(zeus_irq_to_bitmask(irq), ZEUS_CPLD_ISA_IRQ);
+}
+
+static void zeus_mask_irq(unsigned int irq)
+{
+        zeus_irq_enabled_mask &= ~(zeus_irq_to_bitmask(irq));
+}
+
+static void zeus_unmask_irq(unsigned int irq)
+{
+        zeus_irq_enabled_mask |= zeus_irq_to_bitmask(irq);
+}
+
+static inline unsigned long zeus_irq_pending(void)
+{
+        return __raw_readw(ZEUS_CPLD_ISA_IRQ) & zeus_irq_enabled_mask;
+}
+
+static void zeus_irq_handler(unsigned int irq, struct irq_desc *desc)
+{
+        unsigned long pending;
+
+        pending = zeus_irq_pending();
+        do {
+                /* we're in a chained irq handler,
+                 * so ack the interrupt by hand */
+                desc->chip->ack(gpio_to_irq(ZEUS_ISA_GPIO));
+
+                if (likely(pending)) {
+                        irq = zeus_bit_to_irq(__ffs(pending));
+                        generic_handle_irq(irq);
+                }
+                pending = zeus_irq_pending();
+        } while (pending);
+}
+
+static struct irq_chip zeus_irq_chip = {
+        .name   = "ISA",
+        .ack    = zeus_ack_irq,
+        .mask   = zeus_mask_irq,
+        .unmask = zeus_unmask_irq,
+};
+
+static void __init zeus_init_irq(void)
+{
+        int level;
+        int isa_irq;
+
+        pxa27x_init_irq();
+
+        /* Peripheral IRQs. It would be nice to move those inside driver
+           configuration, but it is not supported at the moment. */
+        set_irq_type(gpio_to_irq(ZEUS_AC97_GPIO),       IRQ_TYPE_EDGE_RISING);
+        set_irq_type(gpio_to_irq(ZEUS_WAKEUP_GPIO),     IRQ_TYPE_EDGE_RISING);
+        set_irq_type(gpio_to_irq(ZEUS_PTT_GPIO),        IRQ_TYPE_EDGE_RISING);
+        set_irq_type(gpio_to_irq(ZEUS_EXTGPIO_GPIO),    IRQ_TYPE_EDGE_FALLING);
+        set_irq_type(gpio_to_irq(ZEUS_CAN_GPIO),        IRQ_TYPE_EDGE_FALLING);
+
+        /* Setup ISA IRQs */
+        for (level = 0; level < ARRAY_SIZE(zeus_isa_irqs); level++) {
+                isa_irq = zeus_bit_to_irq(level);
+                set_irq_chip(isa_irq, &zeus_irq_chip);
+                set_irq_handler(isa_irq, handle_edge_irq);
+                set_irq_flags(isa_irq, IRQF_VALID | IRQF_PROBE);
+        }
+
+        set_irq_type(gpio_to_irq(ZEUS_ISA_GPIO), IRQ_TYPE_EDGE_RISING);
+        set_irq_chained_handler(gpio_to_irq(ZEUS_ISA_GPIO), zeus_irq_handler);
+}
+
+
+/*
+ * Platform devices
+ */
+
+/* Flash */
+static struct resource zeus_mtd_resources[] = {
+        [0] = { /* NOR Flash (up to 64MB) */
+                .start  = ZEUS_FLASH_PHYS,
+                .end    = ZEUS_FLASH_PHYS + SZ_64M - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = { /* SRAM */
+                .start  = ZEUS_SRAM_PHYS,
+                .end    = ZEUS_SRAM_PHYS + SZ_512K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+};
+
+static struct physmap_flash_data zeus_flash_data[] = {
+        [0] = {
+                .width          = 2,
+                .parts          = NULL,
+                .nr_parts       = 0,
+        },
+};
+
+static struct platform_device zeus_mtd_devices[] = {
+        [0] = {
+                .name           = "physmap-flash",
+                .id             = 0,
+                .dev            = {
+                        .platform_data = &zeus_flash_data[0],
+                },
+                .resource       = &zeus_mtd_resources[0],
+                .num_resources  = 1,
+        },
+};
+
+/* Serial */
+static struct resource zeus_serial_resources[] = {
+        {
+                .start  = 0x10000000,
+                .end    = 0x1000000f,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .start  = 0x10800000,
+                .end    = 0x1080000f,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .start  = 0x11000000,
+                .end    = 0x1100000f,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .start  = 0x40100000,
+                .end    = 0x4010001f,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .start  = 0x40200000,
+                .end    = 0x4020001f,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .start  = 0x40700000,
+                .end    = 0x4070001f,
+                .flags  = IORESOURCE_MEM,
+        },
+};
+
+static struct plat_serial8250_port serial_platform_data[] = {
+        /* External UARTs */
+        /* FIXME: Shared IRQs on COM1-COM4 will not work properly on v1i1 hardware. */
+        { /* COM1 */
+                .mapbase        = 0x10000000,
+                .irq            = gpio_to_irq(ZEUS_UARTA_GPIO),
+                .irqflags       = IRQF_TRIGGER_RISING,
+                .uartclk        = 14745600,
+                .regshift       = 1,
+                .flags          = UPF_IOREMAP | UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
+                .iotype         = UPIO_MEM,
+        },
+        { /* COM2 */
+                .mapbase        = 0x10800000,
+                .irq            = gpio_to_irq(ZEUS_UARTB_GPIO),
+                .irqflags       = IRQF_TRIGGER_RISING,
+                .uartclk        = 14745600,
+                .regshift       = 1,
+                .flags          = UPF_IOREMAP | UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
+                .iotype         = UPIO_MEM,
+        },
+        { /* COM3 */
+                .mapbase        = 0x11000000,
+                .irq            = gpio_to_irq(ZEUS_UARTC_GPIO),
+                .irqflags       = IRQF_TRIGGER_RISING,
+                .uartclk        = 14745600,
+                .regshift       = 1,
+                .flags          = UPF_IOREMAP | UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
+                .iotype         = UPIO_MEM,
+        },
+        { /* COM4 */
+                .mapbase        = 0x11800000,
+                .irq            = gpio_to_irq(ZEUS_UARTD_GPIO),
+                .irqflags       = IRQF_TRIGGER_RISING,
+                .uartclk        = 14745600,
+                .regshift       = 1,
+                .flags          = UPF_IOREMAP | UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
+                .iotype         = UPIO_MEM,
+        },
+        /* Internal UARTs */
+        { /* FFUART */
+                .membase        = (void *)&FFUART,
+                .mapbase        = __PREG(FFUART),
+                .irq            = IRQ_FFUART,
+                .uartclk        = 921600 * 16,
+                .regshift       = 2,
+                .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
+                .iotype         = UPIO_MEM,
+        },
+        { /* BTUART */
+                .membase        = (void *)&BTUART,
+                .mapbase        = __PREG(BTUART),
+                .irq            = IRQ_BTUART,
+                .uartclk        = 921600 * 16,
+                .regshift       = 2,
+                .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
+                .iotype         = UPIO_MEM,
+        },
+        { /* STUART */
+                .membase        = (void *)&STUART,
+                .mapbase        = __PREG(STUART),
+                .irq            = IRQ_STUART,
+                .uartclk        = 921600 * 16,
+                .regshift       = 2,
+                .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
+                .iotype         = UPIO_MEM,
+        },
+        { },
+};
+
+static struct platform_device zeus_serial_device = {
+        .name = "serial8250",
+        .id   = PLAT8250_DEV_PLATFORM,
+        .dev  = {
+                .platform_data = serial_platform_data,
+        },
+        .num_resources  = ARRAY_SIZE(zeus_serial_resources),
+        .resource       = zeus_serial_resources,
+};
+
+/* Ethernet */
+static struct resource zeus_dm9k0_resource[] = {
+        [0] = {
+                .start = ZEUS_ETH0_PHYS,
+                .end   = ZEUS_ETH0_PHYS + 1,
+                .flags = IORESOURCE_MEM
+        },
+        [1] = {
+                .start = ZEUS_ETH0_PHYS + 2,
+                .end   = ZEUS_ETH0_PHYS + 3,
+                .flags = IORESOURCE_MEM
+        },
+        [2] = {
+                .start = gpio_to_irq(ZEUS_ETH0_GPIO),
+                .end   = gpio_to_irq(ZEUS_ETH0_GPIO),
+                .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
+        },
+};
+
+static struct resource zeus_dm9k1_resource[] = {
+        [0] = {
+                .start = ZEUS_ETH1_PHYS,
+                .end   = ZEUS_ETH1_PHYS + 1,
+                .flags = IORESOURCE_MEM
+        },
+        [1] = {
+                .start = ZEUS_ETH1_PHYS + 2,
+                .end   = ZEUS_ETH1_PHYS + 3,
+                .flags = IORESOURCE_MEM,
+        },
+        [2] = {
+                .start = gpio_to_irq(ZEUS_ETH1_GPIO),
+                .end   = gpio_to_irq(ZEUS_ETH1_GPIO),
+                .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
+        },
+};
+
+static struct dm9000_plat_data zeus_dm9k_platdata = {
+        .flags          = DM9000_PLATF_16BITONLY,
+};
+
+static struct platform_device zeus_dm9k0_device = {
+        .name           = "dm9000",
+        .id             = 0,
+        .num_resources  = ARRAY_SIZE(zeus_dm9k0_resource),
+        .resource       = zeus_dm9k0_resource,
+        .dev            = {
+                .platform_data = &zeus_dm9k_platdata,
+        }
+};
+
+static struct platform_device zeus_dm9k1_device = {
+        .name           = "dm9000",
+        .id             = 1,
+        .num_resources  = ARRAY_SIZE(zeus_dm9k1_resource),
+        .resource       = zeus_dm9k1_resource,
+        .dev            = {
+                .platform_data = &zeus_dm9k_platdata,
+        }
+};
+
+/* External SRAM */
+static struct resource zeus_sram_resource = {
+        .start          = ZEUS_SRAM_PHYS,
+        .end            = ZEUS_SRAM_PHYS + ZEUS_SRAM_SIZE * 2 - 1,
+        .flags          = IORESOURCE_MEM,
+};
+
+static struct platform_device zeus_sram_device = {
+        .name           = "pxa2xx-8bit-sram",
+        .id             = 0,
+        .num_resources  = 1,
+        .resource       = &zeus_sram_resource,
+};
+
+/* SPI interface on SSP3 */
+static struct pxa2xx_spi_master pxa2xx_spi_ssp3_master_info = {
+        .num_chipselect = 1,
+        .enable_dma     = 1,
+};
+
+static struct platform_device pxa2xx_spi_ssp3_device = {
+        .name = "pxa2xx-spi",
+        .id = 3,
+        .dev = {
+                .platform_data = &pxa2xx_spi_ssp3_master_info,
+        },
+};
+
+/* Leds */
+static struct gpio_led zeus_leds[] = {
+        [0] = {
+                .name            = "zeus:yellow:1",
+                .default_trigger = "heartbeat",
+                .gpio            = ZEUS_EXT0_GPIO(3),
+                .active_low      = 1,
+        },
+        [1] = {
+                .name            = "zeus:yellow:2",
+                .default_trigger = "default-on",
+                .gpio            = ZEUS_EXT0_GPIO(4),
+                .active_low      = 1,
+        },
+        [2] = {
+                .name            = "zeus:yellow:3",
+                .default_trigger = "default-on",
+                .gpio            = ZEUS_EXT0_GPIO(5),
+                .active_low      = 1,
+        },
+};
+
+static struct gpio_led_platform_data zeus_leds_info = {
+        .leds           = zeus_leds,
+        .num_leds       = ARRAY_SIZE(zeus_leds),
+};
+
+static struct platform_device zeus_leds_device = {
+        .name           = "leds-gpio",
+        .id             = -1,
+        .dev            = {
+                .platform_data  = &zeus_leds_info,
+        },
+};
+
+static void zeus_cf_reset(int state)
+{
+        u16 cpld_state = __raw_readw(ZEUS_CPLD_CONTROL);
+
+        if (state)
+                cpld_state |= ZEUS_CPLD_CONTROL_CF_RST;
+        else
+                cpld_state &= ~ZEUS_CPLD_CONTROL_CF_RST;
+
+        __raw_writew(cpld_state, ZEUS_CPLD_CONTROL);
+}
+
+static struct arcom_pcmcia_pdata zeus_pcmcia_info = {
+        .cd_gpio        = ZEUS_CF_CD_GPIO,
+        .rdy_gpio       = ZEUS_CF_RDY_GPIO,
+        .pwr_gpio       = ZEUS_CF_PWEN_GPIO,
+        .reset          = zeus_cf_reset,
+};
+
+static struct platform_device zeus_pcmcia_device = {
+        .name           = "zeus-pcmcia",
+        .id             = -1,
+        .dev            = {
+                .platform_data  = &zeus_pcmcia_info,
+        },
+};
+
+static struct platform_device *zeus_devices[] __initdata = {
+        &zeus_serial_device,
+        &zeus_mtd_devices[0],
+        &zeus_dm9k0_device,
+        &zeus_dm9k1_device,
+        &zeus_sram_device,
+        &pxa2xx_spi_ssp3_device,
+        &zeus_leds_device,
+        &zeus_pcmcia_device,
+};
+
+/* AC'97 */
+static pxa2xx_audio_ops_t zeus_ac97_info = {
+        .reset_gpio = 95,
+};
+
+
+/*
+ * USB host
+ */
+
+static int zeus_ohci_init(struct device *dev)
+{
+        int err;
+
+        /* Switch on port 2. */
+        if ((err = gpio_request(ZEUS_USB2_PWREN_GPIO, "USB2_PWREN"))) {
+                dev_err(dev, "Can't request USB2_PWREN\n");
+                return err;
+        }
+
+        if ((err = gpio_direction_output(ZEUS_USB2_PWREN_GPIO, 1))) {
+                gpio_free(ZEUS_USB2_PWREN_GPIO);
+                dev_err(dev, "Can't enable USB2_PWREN\n");
+                return err;
+        }
+
+        /* Port 2 is shared between host and client interface. */
+        UP2OCR = UP2OCR_HXOE | UP2OCR_HXS | UP2OCR_DMPDE | UP2OCR_DPPDE;
+
+        return 0;
+}
+
+static void zeus_ohci_exit(struct device *dev)
+{
+        /* Power-off port 2 */
+        gpio_direction_output(ZEUS_USB2_PWREN_GPIO, 0);
+        gpio_free(ZEUS_USB2_PWREN_GPIO);
+}
+
+static struct pxaohci_platform_data zeus_ohci_platform_data = {
+        .port_mode      = PMM_NPS_MODE,
+        .flags          = ENABLE_PORT_ALL | POWER_CONTROL_LOW | POWER_SENSE_LOW,
+        .init           = zeus_ohci_init,
+        .exit           = zeus_ohci_exit,
+};
+
+/*
+ * Flat Panel
+ */
+
+static void zeus_lcd_power(int on, struct fb_var_screeninfo *si)
+{
+        gpio_set_value(ZEUS_LCD_EN_GPIO, on);
+}
+
+static void zeus_backlight_power(int on)
+{
+        gpio_set_value(ZEUS_BKLEN_GPIO, on);
+}
+
+static int zeus_setup_fb_gpios(void)
+{
+        int err;
+
+        if ((err = gpio_request(ZEUS_LCD_EN_GPIO, "LCD_EN")))
+                goto out_err;
+
+        if ((err = gpio_direction_output(ZEUS_LCD_EN_GPIO, 0)))
+                goto out_err_lcd;
+
+        if ((err = gpio_request(ZEUS_BKLEN_GPIO, "BKLEN")))
+                goto out_err_lcd;
+
+        if ((err = gpio_direction_output(ZEUS_BKLEN_GPIO, 0)))
+                goto out_err_bkl;
+
+        return 0;
+
+out_err_bkl:
+        gpio_free(ZEUS_BKLEN_GPIO);
+out_err_lcd:
+        gpio_free(ZEUS_LCD_EN_GPIO);
+out_err:
+        return err;
+}
+
+static struct pxafb_mode_info zeus_fb_mode_info[] = {
+        {
+                .pixclock       = 39722,
+
+                .xres           = 640,
+                .yres           = 480,
+
+                .bpp            = 16,
+
+                .hsync_len      = 63,
+                .left_margin    = 16,
+                .right_margin   = 81,
+
+                .vsync_len      = 2,
+                .upper_margin   = 12,
+                .lower_margin   = 31,
+
+                .sync           = 0,
+        },
+};
+
+static struct pxafb_mach_info zeus_fb_info = {
+        .modes                  = zeus_fb_mode_info,
+        .num_modes              = 1,
+        .lcd_conn               = LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL,
+        .pxafb_lcd_power        = zeus_lcd_power,
+        .pxafb_backlight_power  = zeus_backlight_power,
+};
+
+/*
+ * MMC/SD Device
+ *
+ * The card detect interrupt isn't debounced so we delay it by 250ms
+ * to give the card a chance to fully insert/eject.
+ */
+
+static struct pxamci_platform_data zeus_mci_platform_data = {
+        .ocr_mask               = MMC_VDD_32_33|MMC_VDD_33_34,
+        .detect_delay           = HZ/4,
+        .gpio_card_detect       = ZEUS_MMC_CD_GPIO,
+        .gpio_card_ro           = ZEUS_MMC_WP_GPIO,
+        .gpio_card_ro_invert    = 1,
+        .gpio_power             = -1
+};
+
+/*
+ * USB Device Controller
+ */
+static void zeus_udc_command(int cmd)
+{
+        switch (cmd) {
+        case PXA2XX_UDC_CMD_DISCONNECT:
+                pr_info("zeus: disconnecting USB client\n");
+                UP2OCR = UP2OCR_HXOE | UP2OCR_HXS | UP2OCR_DMPDE | UP2OCR_DPPDE;
+                break;
+
+        case PXA2XX_UDC_CMD_CONNECT:
+                pr_info("zeus: connecting USB client\n");
+                UP2OCR = UP2OCR_HXOE | UP2OCR_DPPUE;
+                break;
+        }
+}
+
+static struct pxa2xx_udc_mach_info zeus_udc_info = {
+        .udc_command = zeus_udc_command,
+};
+
+static void zeus_power_off(void)
+{
+        local_irq_disable();
+        pxa27x_cpu_suspend(PWRMODE_DEEPSLEEP);
+}
+
+int zeus_get_pcb_info(struct i2c_client *client, unsigned gpio,
+                      unsigned ngpio, void *context)
+{
+        int i;
+        u8 pcb_info = 0;
+
+        for (i = 0; i < 8; i++) {
+                int pcb_bit = gpio + i + 8;
+
+                if (gpio_request(pcb_bit, "pcb info")) {
+                        dev_err(&client->dev, "Can't request pcb info %d\n", i);
+                        continue;
+                }
+
+                if (gpio_direction_input(pcb_bit)) {
+                        dev_err(&client->dev, "Can't read pcb info %d\n", i);
+                        gpio_free(pcb_bit);
+                        continue;
+                }
+
+                pcb_info |= !!gpio_get_value(pcb_bit) << i;
+
+                gpio_free(pcb_bit);
+        }
+
+        dev_info(&client->dev, "Zeus PCB version %d issue %d\n",
+                 pcb_info >> 4, pcb_info & 0xf);
+
+        return 0;
+}
+
+static struct pca953x_platform_data zeus_pca953x_pdata[] = {
+        [0] = { .gpio_base      = ZEUS_EXT0_GPIO_BASE, },
+        [1] = {
+                .gpio_base      = ZEUS_EXT1_GPIO_BASE,
+                .setup          = zeus_get_pcb_info,
+        },
+        [2] = { .gpio_base = ZEUS_USER_GPIO_BASE, },
+};
+
+static struct i2c_board_info __initdata zeus_i2c_devices[] = {
+        {
+                I2C_BOARD_INFO("pca9535",       0x21),
+                .platform_data  = &zeus_pca953x_pdata[0],
+        },
+        {
+                I2C_BOARD_INFO("pca9535",       0x22),
+                .platform_data  = &zeus_pca953x_pdata[1],
+        },
+        {
+                I2C_BOARD_INFO("pca9535",       0x20),
+                .platform_data  = &zeus_pca953x_pdata[2],
+                .irq            = gpio_to_irq(ZEUS_EXTGPIO_GPIO),
+        },
+        { I2C_BOARD_INFO("lm75a",       0x48) },
+        { I2C_BOARD_INFO("24c01",       0x50) },
+        { I2C_BOARD_INFO("isl1208",     0x6f) },
+};
+
+static mfp_cfg_t zeus_pin_config[] __initdata = {
+        GPIO15_nCS_1,
+        GPIO78_nCS_2,
+        GPIO80_nCS_4,
+        GPIO33_nCS_5,
+
+        GPIO22_GPIO,
+        GPIO32_MMC_CLK,
+        GPIO92_MMC_DAT_0,
+        GPIO109_MMC_DAT_1,
+        GPIO110_MMC_DAT_2,
+        GPIO111_MMC_DAT_3,
+        GPIO112_MMC_CMD,
+
+        GPIO88_USBH1_PWR,
+        GPIO89_USBH1_PEN,
+        GPIO119_USBH2_PWR,
+        GPIO120_USBH2_PEN,
+
+        GPIO86_LCD_LDD_16,
+        GPIO87_LCD_LDD_17,
+
+        GPIO102_GPIO,
+        GPIO104_CIF_DD_2,
+        GPIO105_CIF_DD_1,
+
+        GPIO48_nPOE,
+        GPIO49_nPWE,
+        GPIO50_nPIOR,
+        GPIO51_nPIOW,
+        GPIO85_nPCE_1,
+        GPIO54_nPCE_2,
+        GPIO79_PSKTSEL,
+        GPIO55_nPREG,
+        GPIO56_nPWAIT,
+        GPIO57_nIOIS16,
+        GPIO36_GPIO,            /* CF CD */
+        GPIO97_GPIO,            /* CF PWREN */
+        GPIO99_GPIO,            /* CF RDY */
+};
+
+static void __init zeus_init(void)
+{
+        u16 dm9000_msc = 0xe279;
+
+        system_rev = __raw_readw(ZEUS_CPLD_VERSION);
+        pr_info("Zeus CPLD V%dI%d\n", (system_rev & 0xf0) >> 4, (system_rev & 0x0f));
+
+        /* Fix timings for dm9000s (CS1/CS2)*/
+        MSC0 = (MSC0 & 0xffff) | (dm9000_msc << 16);
+        MSC1 = (MSC1 & 0xffff0000) | dm9000_msc;
+
+        pm_power_off = zeus_power_off;
+
+        pxa2xx_mfp_config(ARRAY_AND_SIZE(zeus_pin_config));
+
+        platform_add_devices(zeus_devices, ARRAY_SIZE(zeus_devices));
+
+        pxa_set_ohci_info(&zeus_ohci_platform_data);
+
+        if (zeus_setup_fb_gpios())
+                pr_err("Failed to setup fb gpios\n");
+        else
+                set_pxa_fb_info(&zeus_fb_info);
+
+        pxa_set_mci_info(&zeus_mci_platform_data);
+        pxa_set_udc_info(&zeus_udc_info);
+        pxa_set_ac97_info(&zeus_ac97_info);
+        pxa_set_i2c_info(NULL);
+        i2c_register_board_info(0, ARRAY_AND_SIZE(zeus_i2c_devices));
+}
+
+static struct map_desc zeus_io_desc[] __initdata = {
+        {
+                .virtual = ZEUS_CPLD_VERSION,
+                .pfn     = __phys_to_pfn(ZEUS_CPLD_VERSION_PHYS),
+                .length  = 0x1000,
+                .type    = MT_DEVICE,
+        },
+        {
+                .virtual = ZEUS_CPLD_ISA_IRQ,
+                .pfn     = __phys_to_pfn(ZEUS_CPLD_ISA_IRQ_PHYS),
+                .length  = 0x1000,
+                .type    = MT_DEVICE,
+        },
+        {
+                .virtual = ZEUS_CPLD_CONTROL,
+                .pfn     = __phys_to_pfn(ZEUS_CPLD_CONTROL_PHYS),
+                .length  = 0x1000,
+                .type    = MT_DEVICE,
+        },
+        {
+                .virtual = ZEUS_CPLD_EXTWDOG,
+                .pfn     = __phys_to_pfn(ZEUS_CPLD_EXTWDOG_PHYS),
+                .length  = 0x1000,
+                .type    = MT_DEVICE,
+        },
+        {
+                .virtual = ZEUS_PC104IO,
+                .pfn     = __phys_to_pfn(ZEUS_PC104IO_PHYS),
+                .length  = 0x00800000,
+                .type    = MT_DEVICE,
+        },
+};
+
+static void __init zeus_map_io(void)
+{
+        pxa_map_io();
+
+        iotable_init(zeus_io_desc, ARRAY_SIZE(zeus_io_desc));
+
+        /* Clear PSPR to ensure a full restart on wake-up. */
+        PMCR = PSPR = 0;
+
+        /* enable internal 32.768Khz oscillator (ignore OSCC_OOK) */
+        OSCC |= OSCC_OON;
+
+        /* Some clock cycles later (from OSCC_ON), programme PCFR (OPDE...).
+         * float chip selects and PCMCIA */
+        PCFR = PCFR_OPDE | PCFR_DC_EN | PCFR_FS | PCFR_FP;
+}
+
+MACHINE_START(ARCOM_ZEUS, "Arcom ZEUS")
+        /* Maintainer: Marc Zyngier <maz@misterjones.org> */
+        .phys_io        = 0x40000000,
+        .io_pg_offst    = ((io_p2v(0x40000000) >> 18) & 0xfffc),
+        .boot_params    = 0xa0000100,
+        .map_io         = zeus_map_io,
+        .init_irq       = zeus_init_irq,
+        .timer          = &pxa_timer,
+        .init_machine   = zeus_init,
+MACHINE_END
+
diff --git a/arch/arm/mach-realview/Kconfig b/arch/arm/mach-realview/Kconfig
index c48e1f2c3349..ee5e392430e8 100644
--- a/arch/arm/mach-realview/Kconfig
+++ b/arch/arm/mach-realview/Kconfig
@@ -70,7 +70,7 @@ config MACH_REALVIEW_PBX
         bool "Support RealView/PBX platform"
         select ARM_GIC
         select HAVE_PATA_PLATFORM
-        select ARCH_SPARSEMEM_ENABLE if CPU_V7 && !HIGH_PHYS_OFFSET
+        select ARCH_SPARSEMEM_ENABLE if CPU_V7 && !REALVIEW_HIGH_PHYS_OFFSET
         select ZONE_DMA if SPARSEMEM
         help
           Include support for the ARM(R) RealView PBX platform.
diff --git a/arch/arm/mach-s3c2410/include/mach/spi.h b/arch/arm/mach-s3c2410/include/mach/spi.h
index 193b39d654ed..4d9588373aa5 100644
--- a/arch/arm/mach-s3c2410/include/mach/spi.h
+++ b/arch/arm/mach-s3c2410/include/mach/spi.h
@@ -18,6 +18,8 @@ struct s3c2410_spi_info {
         unsigned int             num_cs;        /* total chipselects */
         int                      bus_num;       /* bus number to use. */
 
+        unsigned int             use_fiq:1;     /* use fiq */
+
         void (*gpio_setup)(struct s3c2410_spi_info *spi, int enable);
         void (*set_cs)(struct s3c2410_spi_info *spi, int cs, int pol);
 };
diff --git a/arch/arm/mach-s3c2442/mach-gta02.c b/arch/arm/mach-s3c2442/mach-gta02.c
index f76d6ff4aeb9..0b4a3a03071f 100644
--- a/arch/arm/mach-s3c2442/mach-gta02.c
+++ b/arch/arm/mach-s3c2442/mach-gta02.c
@@ -268,6 +268,9 @@ struct pcf50633_platform_data gta02_pcf_pdata = {
 
         .batteries = gta02_batteries,
         .num_batteries = ARRAY_SIZE(gta02_batteries),
+
+        .charger_reference_current_ma = 1000,
+
         .reg_init_data = {
                 [PCF50633_REGULATOR_AUTO] = {
                         .constraints = {
diff --git a/arch/arm/mach-s3c24a0/include/mach/memory.h b/arch/arm/mach-s3c24a0/include/mach/memory.h
index 585211ca0187..7d74fd5c8d66 100644
--- a/arch/arm/mach-s3c24a0/include/mach/memory.h
+++ b/arch/arm/mach-s3c24a0/include/mach/memory.h
@@ -15,5 +15,7 @@
 
 #define __virt_to_bus(x) __virt_to_phys(x)
 #define __bus_to_virt(x) __phys_to_virt(x)
+#define __pfn_to_bus(x) __pfn_to_phys(x)
+#define __bus_to_pfn(x) __phys_to_pfn(x)
 
 #endif
diff --git a/arch/arm/mach-sa1100/Kconfig b/arch/arm/mach-sa1100/Kconfig
index 03a7f3857c5e..b17d52f7cc48 100644
--- a/arch/arm/mach-sa1100/Kconfig
+++ b/arch/arm/mach-sa1100/Kconfig
@@ -4,6 +4,7 @@ menu "SA11x0 Implementations"
 
 config SA1100_ASSABET
         bool "Assabet"
+        select CPU_FREQ_SA1110
         help
           Say Y here if you are using the Intel(R) StrongARM(R) SA-1110
           Microprocessor Development Board (also known as the Assabet).
@@ -19,6 +20,7 @@ config ASSABET_NEPONSET
 
 config SA1100_CERF
         bool "CerfBoard"
+        select CPU_FREQ_SA1110
         help
           The Intrinsyc CerfBoard is based on the StrongARM 1110 (Discontinued).
           More information is available at:
@@ -45,6 +47,7 @@ endchoice
 
 config SA1100_COLLIE
         bool "Sharp Zaurus SL5500"
+        # FIXME: select CPU_FREQ_SA11x0
         select SHARP_LOCOMO
         select SHARP_SCOOP
         select SHARP_PARAM
@@ -54,6 +57,7 @@ config SA1100_COLLIE
 config SA1100_H3100
         bool "Compaq iPAQ H3100"
         select HTC_EGPIO
+        select CPU_FREQ_SA1100
         help
           Say Y here if you intend to run this kernel on the Compaq iPAQ
           H3100 handheld computer.  Information about this machine and the
@@ -64,6 +68,7 @@ config SA1100_H3100
 config SA1100_H3600
         bool "Compaq iPAQ H3600/H3700"
         select HTC_EGPIO
+        select CPU_FREQ_SA1100
         help
           Say Y here if you intend to run this kernel on the Compaq iPAQ
           H3600 handheld computer.  Information about this machine and the
@@ -74,6 +79,7 @@ config SA1100_H3600
 config SA1100_BADGE4
         bool "HP Labs BadgePAD 4"
         select SA1111
+        select CPU_FREQ_SA1100
         help
           Say Y here if you want to build a kernel for the HP Laboratories
           BadgePAD 4.
@@ -81,6 +87,7 @@ config SA1100_BADGE4
 config SA1100_JORNADA720
         bool "HP Jornada 720"
         select SA1111
+        # FIXME: select CPU_FREQ_SA11x0
         help
           Say Y here if you want to build a kernel for the HP Jornada 720
           handheld computer.  See <http://www.hp.com/jornada/products/720>
@@ -98,12 +105,14 @@ config SA1100_JORNADA720_SSP
 
 config SA1100_HACKKIT
         bool "HackKit Core CPU Board"
+        select CPU_FREQ_SA1100
         help
           Say Y here to support the HackKit Core CPU Board
           <http://hackkit.eletztrick.de>;
 
 config SA1100_LART
         bool "LART"
+        select CPU_FREQ_SA1100
         help
           Say Y here if you are using the Linux Advanced Radio Terminal
           (also known as the LART).  See <http://www.lartmaker.nl/> for
@@ -111,6 +120,7 @@ config SA1100_LART
 
 config SA1100_PLEB
         bool "PLEB"
+        select CPU_FREQ_SA1100
         help
           Say Y here if you are using version 1 of the Portable Linux
           Embedded Board (also known as PLEB).
@@ -119,6 +129,7 @@ config SA1100_PLEB
 
 config SA1100_SHANNON
         bool "Shannon"
+        select CPU_FREQ_SA1100
         help
           The Shannon (also known as a Tuxscreen, and also as a IS2630) was a
           limited edition webphone produced by Philips. The Shannon is a SA1100
@@ -127,6 +138,7 @@ config SA1100_SHANNON
 
 config SA1100_SIMPAD
         bool "Simpad"
+        select CPU_FREQ_SA1110
         help
           The SIEMENS webpad SIMpad is based on the StrongARM 1110. There
           are two different versions CL4 and SL4. CL4 has 32MB RAM and 16MB
@@ -145,3 +157,4 @@ config SA1100_SSP
 endmenu
 
 endif
+
diff --git a/arch/arm/mach-sa1100/generic.c b/arch/arm/mach-sa1100/generic.c
index 9faea1511c1f..3c1fcd696714 100644
--- a/arch/arm/mach-sa1100/generic.c
+++ b/arch/arm/mach-sa1100/generic.c
@@ -58,7 +58,6 @@ static const unsigned short cclk_frequency_100khz[NR_FREQS] = {
         2802    /* 280.2 MHz */
 };
 
-#if defined(CONFIG_CPU_FREQ_SA1100) || defined(CONFIG_CPU_FREQ_SA1110)
 /* rounds up(!)  */
 unsigned int sa11x0_freq_to_ppcr(unsigned int khz)
 {
@@ -110,17 +109,6 @@ unsigned int sa11x0_getspeed(unsigned int cpu)
         return cclk_frequency_100khz[PPCR & 0xf] * 100;
 }
 
-#else
-/*
- * We still need to provide this so building without cpufreq works.
- */
-unsigned int cpufreq_get(unsigned int cpu)
-{
-        return cclk_frequency_100khz[PPCR & 0xf] * 100;
-}
-EXPORT_SYMBOL(cpufreq_get);
-#endif
-
 /*
  * This is the SA11x0 sched_clock implementation.  This has
  * a resolution of 271ns, and a maximum value of 32025597s (370 days).
diff --git a/arch/arm/mach-u300/include/mach/coh901318.h b/arch/arm/mach-u300/include/mach/coh901318.h
new file mode 100644
index 000000000000..f4cfee9c7d28
--- /dev/null
+++ b/arch/arm/mach-u300/include/mach/coh901318.h
@@ -0,0 +1,281 @@
+/*
+ *
+ * include/linux/coh901318.h
+ *
+ *
+ * Copyright (C) 2007-2009 ST-Ericsson
+ * License terms: GNU General Public License (GPL) version 2
+ * DMA driver for COH 901 318
+ * Author: Per Friden <per.friden@stericsson.com>
+ */
+
+#ifndef COH901318_H
+#define COH901318_H
+
+#include <linux/device.h>
+#include <linux/dmaengine.h>
+
+#define MAX_DMA_PACKET_SIZE_SHIFT 11
+#define MAX_DMA_PACKET_SIZE (1 << MAX_DMA_PACKET_SIZE_SHIFT)
+
+/**
+ * struct coh901318_lli - linked list item for DMAC
+ * @control: control settings for DMAC
+ * @src_addr: transfer source address
+ * @dst_addr: transfer destination address
+ * @link_addr:  physical address to next lli
+ * @virt_link_addr: virtual addres of next lli (only used by pool_free)
+ * @phy_this: physical address of current lli (only used by pool_free)
+ */
+struct coh901318_lli {
+        u32 control;
+        dma_addr_t src_addr;
+        dma_addr_t dst_addr;
+        dma_addr_t link_addr;
+
+        void *virt_link_addr;
+        dma_addr_t phy_this;
+};
+/**
+ * struct coh901318_params - parameters for DMAC configuration
+ * @config: DMA config register
+ * @ctrl_lli_last: DMA control register for the last lli in the list
+ * @ctrl_lli: DMA control register for an lli
+ * @ctrl_lli_chained: DMA control register for a chained lli
+ */
+struct coh901318_params {
+        u32 config;
+        u32 ctrl_lli_last;
+        u32 ctrl_lli;
+        u32 ctrl_lli_chained;
+};
+/**
+ * struct coh_dma_channel - dma channel base
+ * @name: ascii name of dma channel
+ * @number: channel id number
+ * @desc_nbr_max: number of preallocated descriptortors
+ * @priority_high: prio of channel, 0 low otherwise high.
+ * @param: configuration parameters
+ * @dev_addr: physical address of periphal connected to channel
+ */
+struct coh_dma_channel {
+        const char name[32];
+        const int number;
+        const int desc_nbr_max;
+        const int priority_high;
+        const struct coh901318_params param;
+        const dma_addr_t dev_addr;
+};
+
+/**
+ * dma_access_memory_state_t - register dma for memory access
+ *
+ * @dev: The dma device
+ * @active:  1 means dma intends to access memory
+ *           0 means dma wont access memory
+ */
+typedef void (*dma_access_memory_state_t)(struct device *dev,
+                                          bool active);
+
+/**
+ * struct powersave - DMA power save structure
+ * @lock: lock protecting data in this struct
+ * @started_channels: bit mask indicating active dma channels
+ */
+struct powersave {
+        spinlock_t lock;
+        u64 started_channels;
+};
+/**
+ * struct coh901318_platform - platform arch structure
+ * @chans_slave: specifying dma slave channels
+ * @chans_memcpy: specifying dma memcpy channels
+ * @access_memory_state: requesting DMA memeory access (on / off)
+ * @chan_conf: dma channel configurations
+ * @max_channels: max number of dma chanenls
+ */
+struct coh901318_platform {
+        const int *chans_slave;
+        const int *chans_memcpy;
+        const dma_access_memory_state_t access_memory_state;
+        const struct coh_dma_channel *chan_conf;
+        const int max_channels;
+};
+
+/**
+ * coh901318_get_bytes_left() - Get number of bytes left on a current transfer
+ * @chan: dma channel handle
+ * return number of bytes left, or negative on error
+ */
+u32 coh901318_get_bytes_left(struct dma_chan *chan);
+
+/**
+ * coh901318_stop() - Stops dma transfer
+ * @chan: dma channel handle
+ * return 0 on success otherwise negative value
+ */
+void coh901318_stop(struct dma_chan *chan);
+
+/**
+ * coh901318_continue() - Resumes a stopped dma transfer
+ * @chan: dma channel handle
+ * return 0 on success otherwise negative value
+ */
+void coh901318_continue(struct dma_chan *chan);
+
+/**
+ * coh901318_filter_id() - DMA channel filter function
+ * @chan: dma channel handle
+ * @chan_id: id of dma channel to be filter out
+ *
+ * In dma_request_channel() it specifies what channel id to be requested
+ */
+bool coh901318_filter_id(struct dma_chan *chan, void *chan_id);
+
+/*
+ * DMA Controller - this access the static mappings of the coh901318 dma.
+ *
+ */
+
+#define COH901318_MOD32_MASK                                    (0x1F)
+#define COH901318_WORD_MASK                                     (0xFFFFFFFF)
+/* INT_STATUS - Interrupt Status Registers 32bit (R/-) */
+#define COH901318_INT_STATUS1                                   (0x0000)
+#define COH901318_INT_STATUS2                                   (0x0004)
+/* TC_INT_STATUS - Terminal Count Interrupt Status Registers 32bit (R/-) */
+#define COH901318_TC_INT_STATUS1                                (0x0008)
+#define COH901318_TC_INT_STATUS2                                (0x000C)
+/* TC_INT_CLEAR - Terminal Count Interrupt Clear Registers 32bit (-/W) */
+#define COH901318_TC_INT_CLEAR1                                 (0x0010)
+#define COH901318_TC_INT_CLEAR2                                 (0x0014)
+/* RAW_TC_INT_STATUS - Raw Term Count Interrupt Status Registers 32bit (R/-) */
+#define COH901318_RAW_TC_INT_STATUS1                            (0x0018)
+#define COH901318_RAW_TC_INT_STATUS2                            (0x001C)
+/* BE_INT_STATUS - Bus Error Interrupt Status Registers 32bit (R/-) */
+#define COH901318_BE_INT_STATUS1                                (0x0020)
+#define COH901318_BE_INT_STATUS2                                (0x0024)
+/* BE_INT_CLEAR - Bus Error Interrupt Clear Registers 32bit (-/W) */
+#define COH901318_BE_INT_CLEAR1                                 (0x0028)
+#define COH901318_BE_INT_CLEAR2                                 (0x002C)
+/* RAW_BE_INT_STATUS - Raw Term Count Interrupt Status Registers 32bit (R/-) */
+#define COH901318_RAW_BE_INT_STATUS1                            (0x0030)
+#define COH901318_RAW_BE_INT_STATUS2                            (0x0034)
+
+/*
+ * CX_CFG - Channel Configuration Registers 32bit (R/W)
+ */
+#define COH901318_CX_CFG                                        (0x0100)
+#define COH901318_CX_CFG_SPACING                                (0x04)
+/* Channel enable activates tha dma job */
+#define COH901318_CX_CFG_CH_ENABLE                              (0x00000001)
+#define COH901318_CX_CFG_CH_DISABLE                             (0x00000000)
+/* Request Mode */
+#define COH901318_CX_CFG_RM_MASK                                (0x00000006)
+#define COH901318_CX_CFG_RM_MEMORY_TO_MEMORY                    (0x0 << 1)
+#define COH901318_CX_CFG_RM_PRIMARY_TO_MEMORY                   (0x1 << 1)
+#define COH901318_CX_CFG_RM_MEMORY_TO_PRIMARY                   (0x1 << 1)
+#define COH901318_CX_CFG_RM_PRIMARY_TO_SECONDARY                (0x3 << 1)
+#define COH901318_CX_CFG_RM_SECONDARY_TO_PRIMARY                (0x3 << 1)
+/* Linked channel request field. RM must == 11 */
+#define COH901318_CX_CFG_LCRF_SHIFT                             3
+#define COH901318_CX_CFG_LCRF_MASK                              (0x000001F8)
+#define COH901318_CX_CFG_LCR_DISABLE                            (0x00000000)
+/* Terminal Counter Interrupt Request Mask */
+#define COH901318_CX_CFG_TC_IRQ_ENABLE                          (0x00000200)
+#define COH901318_CX_CFG_TC_IRQ_DISABLE                         (0x00000000)
+/* Bus Error interrupt Mask */
+#define COH901318_CX_CFG_BE_IRQ_ENABLE                          (0x00000400)
+#define COH901318_CX_CFG_BE_IRQ_DISABLE                         (0x00000000)
+
+/*
+ * CX_STAT - Channel Status Registers 32bit (R/-)
+ */
+#define COH901318_CX_STAT                                       (0x0200)
+#define COH901318_CX_STAT_SPACING                               (0x04)
+#define COH901318_CX_STAT_RBE_IRQ_IND                           (0x00000008)
+#define COH901318_CX_STAT_RTC_IRQ_IND                           (0x00000004)
+#define COH901318_CX_STAT_ACTIVE                                (0x00000002)
+#define COH901318_CX_STAT_ENABLED                               (0x00000001)
+
+/*
+ * CX_CTRL - Channel Control Registers 32bit (R/W)
+ */
+#define COH901318_CX_CTRL                                       (0x0400)
+#define COH901318_CX_CTRL_SPACING                               (0x10)
+/* Transfer Count Enable */
+#define COH901318_CX_CTRL_TC_ENABLE                             (0x00001000)
+#define COH901318_CX_CTRL_TC_DISABLE                            (0x00000000)
+/* Transfer Count Value 0 - 4095 */
+#define COH901318_CX_CTRL_TC_VALUE_MASK                         (0x00000FFF)
+/* Burst count */
+#define COH901318_CX_CTRL_BURST_COUNT_MASK                      (0x0000E000)
+#define COH901318_CX_CTRL_BURST_COUNT_64_BYTES                  (0x7 << 13)
+#define COH901318_CX_CTRL_BURST_COUNT_48_BYTES                  (0x6 << 13)
+#define COH901318_CX_CTRL_BURST_COUNT_32_BYTES                  (0x5 << 13)
+#define COH901318_CX_CTRL_BURST_COUNT_16_BYTES                  (0x4 << 13)
+#define COH901318_CX_CTRL_BURST_COUNT_8_BYTES                   (0x3 << 13)
+#define COH901318_CX_CTRL_BURST_COUNT_4_BYTES                   (0x2 << 13)
+#define COH901318_CX_CTRL_BURST_COUNT_2_BYTES                   (0x1 << 13)
+#define COH901318_CX_CTRL_BURST_COUNT_1_BYTE                    (0x0 << 13)
+/* Source bus size  */
+#define COH901318_CX_CTRL_SRC_BUS_SIZE_MASK                     (0x00030000)
+#define COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS                  (0x2 << 16)
+#define COH901318_CX_CTRL_SRC_BUS_SIZE_16_BITS                  (0x1 << 16)
+#define COH901318_CX_CTRL_SRC_BUS_SIZE_8_BITS                   (0x0 << 16)
+/* Source address increment */
+#define COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE                   (0x00040000)
+#define COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE                  (0x00000000)
+/* Destination Bus Size */
+#define COH901318_CX_CTRL_DST_BUS_SIZE_MASK                     (0x00180000)
+#define COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS                  (0x2 << 19)
+#define COH901318_CX_CTRL_DST_BUS_SIZE_16_BITS                  (0x1 << 19)
+#define COH901318_CX_CTRL_DST_BUS_SIZE_8_BITS                   (0x0 << 19)
+/* Destination address increment */
+#define COH901318_CX_CTRL_DST_ADDR_INC_ENABLE                   (0x00200000)
+#define COH901318_CX_CTRL_DST_ADDR_INC_DISABLE                  (0x00000000)
+/* Master Mode (Master2 is only connected to MSL) */
+#define COH901318_CX_CTRL_MASTER_MODE_MASK                      (0x00C00000)
+#define COH901318_CX_CTRL_MASTER_MODE_M2R_M1W                   (0x3 << 22)
+#define COH901318_CX_CTRL_MASTER_MODE_M1R_M2W                   (0x2 << 22)
+#define COH901318_CX_CTRL_MASTER_MODE_M2RW                      (0x1 << 22)
+#define COH901318_CX_CTRL_MASTER_MODE_M1RW                      (0x0 << 22)
+/* Terminal Count flag to PER enable */
+#define COH901318_CX_CTRL_TCP_ENABLE                            (0x01000000)
+#define COH901318_CX_CTRL_TCP_DISABLE                           (0x00000000)
+/* Terminal Count flags to CPU enable */
+#define COH901318_CX_CTRL_TC_IRQ_ENABLE                         (0x02000000)
+#define COH901318_CX_CTRL_TC_IRQ_DISABLE                        (0x00000000)
+/* Hand shake to peripheral */
+#define COH901318_CX_CTRL_HSP_ENABLE                            (0x04000000)
+#define COH901318_CX_CTRL_HSP_DISABLE                           (0x00000000)
+#define COH901318_CX_CTRL_HSS_ENABLE                            (0x08000000)
+#define COH901318_CX_CTRL_HSS_DISABLE                           (0x00000000)
+/* DMA mode */
+#define COH901318_CX_CTRL_DDMA_MASK                             (0x30000000)
+#define COH901318_CX_CTRL_DDMA_LEGACY                           (0x0 << 28)
+#define COH901318_CX_CTRL_DDMA_DEMAND_DMA1                      (0x1 << 28)
+#define COH901318_CX_CTRL_DDMA_DEMAND_DMA2                      (0x2 << 28)
+/* Primary Request Data Destination */
+#define COH901318_CX_CTRL_PRDD_MASK                             (0x40000000)
+#define COH901318_CX_CTRL_PRDD_DEST                             (0x1 << 30)
+#define COH901318_CX_CTRL_PRDD_SOURCE                           (0x0 << 30)
+
+/*
+ * CX_SRC_ADDR - Channel Source Address Registers 32bit (R/W)
+ */
+#define COH901318_CX_SRC_ADDR                                   (0x0404)
+#define COH901318_CX_SRC_ADDR_SPACING                           (0x10)
+
+/*
+ * CX_DST_ADDR - Channel Destination Address Registers 32bit R/W
+ */
+#define COH901318_CX_DST_ADDR                                   (0x0408)
+#define COH901318_CX_DST_ADDR_SPACING                           (0x10)
+
+/*
+ * CX_LNK_ADDR - Channel Link Address Registers 32bit (R/W)
+ */
+#define COH901318_CX_LNK_ADDR                                   (0x040C)
+#define COH901318_CX_LNK_ADDR_SPACING                           (0x10)
+#define COH901318_CX_LNK_LINK_IMMEDIATE                         (0x00000001)
+#endif /* COH901318_H */
diff --git a/arch/arm/mach-w90x900/include/mach/nuc900_spi.h b/arch/arm/mach-w90x900/include/mach/nuc900_spi.h
new file mode 100644
index 000000000000..bd94819e314f
--- /dev/null
+++ b/arch/arm/mach-w90x900/include/mach/nuc900_spi.h
@@ -0,0 +1,35 @@
+/*
+ * arch/arm/mach-w90x900/include/mach/nuc900_spi.h
+ *
+ * Copyright (c) 2009 Nuvoton technology corporation.
+ *
+ * Wan ZongShun <mcuos.com@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation;version 2 of the License.
+ *
+ */
+
+#ifndef __ASM_ARCH_SPI_H
+#define __ASM_ARCH_SPI_H
+
+extern void mfp_set_groupg(struct device *dev);
+
+struct nuc900_spi_info {
+        unsigned int num_cs;
+        unsigned int lsb;
+        unsigned int txneg;
+        unsigned int rxneg;
+        unsigned int divider;
+        unsigned int sleep;
+        unsigned int txnum;
+        unsigned int txbitlen;
+        int bus_num;
+};
+
+struct nuc900_spi_chip {
+        unsigned char bits_per_word;
+};
+
+#endif /* __ASM_ARCH_SPI_H */
diff --git a/arch/arm/mm/cache-fa.S b/arch/arm/mm/cache-fa.S
index b63a8f7b95cf..a89444a3c016 100644
--- a/arch/arm/mm/cache-fa.S
+++ b/arch/arm/mm/cache-fa.S
@@ -127,15 +127,16 @@ ENTRY(fa_coherent_user_range)
         mov     pc, lr
 
 /*
- *      flush_kern_dcache_page(kaddr)
+ *      flush_kern_dcache_area(void *addr, size_t size)
  *
  *      Ensure that the data held in the page kaddr is written back
  *      to the page in question.
  *
- *      - kaddr   - kernel address (guaranteed to be page aligned)
+ *      - addr  - kernel address
+ *      - size  - size of region
  */
-ENTRY(fa_flush_kern_dcache_page)
-        add     r1, r0, #PAGE_SZ
+ENTRY(fa_flush_kern_dcache_area)
+        add     r1, r0, r1
 1:      mcr     p15, 0, r0, c7, c14, 1          @ clean & invalidate D line
         add     r0, r0, #CACHE_DLINESIZE
         cmp     r0, r1
@@ -213,7 +214,7 @@ ENTRY(fa_cache_fns)
         .long   fa_flush_user_cache_range
         .long   fa_coherent_kern_range
         .long   fa_coherent_user_range
-        .long   fa_flush_kern_dcache_page
+        .long   fa_flush_kern_dcache_area
         .long   fa_dma_inv_range
         .long   fa_dma_clean_range
         .long   fa_dma_flush_range
diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
index 747f9a9021bb..cb8fc6573b1b 100644
--- a/arch/arm/mm/cache-l2x0.c
+++ b/arch/arm/mm/cache-l2x0.c
@@ -28,69 +28,120 @@
 static void __iomem *l2x0_base;
 static DEFINE_SPINLOCK(l2x0_lock);
 
-static inline void sync_writel(unsigned long val, unsigned long reg,
-                               unsigned long complete_mask)
+static inline void cache_wait(void __iomem *reg, unsigned long mask)
 {
-        unsigned long flags;
-
-        spin_lock_irqsave(&l2x0_lock, flags);
-        writel(val, l2x0_base + reg);
         /* wait for the operation to complete */
-        while (readl(l2x0_base + reg) & complete_mask)
+        while (readl(reg) & mask)
                 ;
-        spin_unlock_irqrestore(&l2x0_lock, flags);
 }
 
 static inline void cache_sync(void)
 {
-        sync_writel(0, L2X0_CACHE_SYNC, 1);
+        void __iomem *base = l2x0_base;
+        writel(0, base + L2X0_CACHE_SYNC);
+        cache_wait(base + L2X0_CACHE_SYNC, 1);
 }
 
 static inline void l2x0_inv_all(void)
 {
+        unsigned long flags;
+
         /* invalidate all ways */
-        sync_writel(0xff, L2X0_INV_WAY, 0xff);
+        spin_lock_irqsave(&l2x0_lock, flags);
+        writel(0xff, l2x0_base + L2X0_INV_WAY);
+        cache_wait(l2x0_base + L2X0_INV_WAY, 0xff);
         cache_sync();
+        spin_unlock_irqrestore(&l2x0_lock, flags);
 }
 
 static void l2x0_inv_range(unsigned long start, unsigned long end)
 {
-        unsigned long addr;
+        void __iomem *base = l2x0_base;
+        unsigned long flags;
 
+        spin_lock_irqsave(&l2x0_lock, flags);
         if (start & (CACHE_LINE_SIZE - 1)) {
                 start &= ~(CACHE_LINE_SIZE - 1);
-                sync_writel(start, L2X0_CLEAN_INV_LINE_PA, 1);
+                cache_wait(base + L2X0_CLEAN_INV_LINE_PA, 1);
+                writel(start, base + L2X0_CLEAN_INV_LINE_PA);
                 start += CACHE_LINE_SIZE;
         }
 
         if (end & (CACHE_LINE_SIZE - 1)) {
                 end &= ~(CACHE_LINE_SIZE - 1);
-                sync_writel(end, L2X0_CLEAN_INV_LINE_PA, 1);
+                cache_wait(base + L2X0_CLEAN_INV_LINE_PA, 1);
+                writel(end, base + L2X0_CLEAN_INV_LINE_PA);
         }
 
-        for (addr = start; addr < end; addr += CACHE_LINE_SIZE)
-                sync_writel(addr, L2X0_INV_LINE_PA, 1);
+        while (start < end) {
+                unsigned long blk_end = start + min(end - start, 4096UL);
+
+                while (start < blk_end) {
+                        cache_wait(base + L2X0_INV_LINE_PA, 1);
+                        writel(start, base + L2X0_INV_LINE_PA);
+                        start += CACHE_LINE_SIZE;
+                }
+
+                if (blk_end < end) {
+                        spin_unlock_irqrestore(&l2x0_lock, flags);
+                        spin_lock_irqsave(&l2x0_lock, flags);
+                }
+        }
+        cache_wait(base + L2X0_INV_LINE_PA, 1);
         cache_sync();
+        spin_unlock_irqrestore(&l2x0_lock, flags);
 }
 
 static void l2x0_clean_range(unsigned long start, unsigned long end)
 {
-        unsigned long addr;
+        void __iomem *base = l2x0_base;
+        unsigned long flags;
 
+        spin_lock_irqsave(&l2x0_lock, flags);
         start &= ~(CACHE_LINE_SIZE - 1);
-        for (addr = start; addr < end; addr += CACHE_LINE_SIZE)
-                sync_writel(addr, L2X0_CLEAN_LINE_PA, 1);
+        while (start < end) {
+                unsigned long blk_end = start + min(end - start, 4096UL);
+
+                while (start < blk_end) {
+                        cache_wait(base + L2X0_CLEAN_LINE_PA, 1);
+                        writel(start, base + L2X0_CLEAN_LINE_PA);
+                        start += CACHE_LINE_SIZE;
+                }
+
+                if (blk_end < end) {
+                        spin_unlock_irqrestore(&l2x0_lock, flags);
+                        spin_lock_irqsave(&l2x0_lock, flags);
+                }
+        }
+        cache_wait(base + L2X0_CLEAN_LINE_PA, 1);
         cache_sync();
+        spin_unlock_irqrestore(&l2x0_lock, flags);
 }
 
 static void l2x0_flush_range(unsigned long start, unsigned long end)
 {
-        unsigned long addr;
+        void __iomem *base = l2x0_base;
+        unsigned long flags;
 
+        spin_lock_irqsave(&l2x0_lock, flags);
         start &= ~(CACHE_LINE_SIZE - 1);
-        for (addr = start; addr < end; addr += CACHE_LINE_SIZE)
-                sync_writel(addr, L2X0_CLEAN_INV_LINE_PA, 1);
+        while (start < end) {
+                unsigned long blk_end = start + min(end - start, 4096UL);
+
+                while (start < blk_end) {
+                        cache_wait(base + L2X0_CLEAN_INV_LINE_PA, 1);
+                        writel(start, base + L2X0_CLEAN_INV_LINE_PA);
+                        start += CACHE_LINE_SIZE;
+                }
+
+                if (blk_end < end) {
+                        spin_unlock_irqrestore(&l2x0_lock, flags);
+                        spin_lock_irqsave(&l2x0_lock, flags);
+                }
+        }
+        cache_wait(base + L2X0_CLEAN_INV_LINE_PA, 1);
         cache_sync();
+        spin_unlock_irqrestore(&l2x0_lock, flags);
 }
 
 void __init l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask)
diff --git a/arch/arm/mm/cache-v3.S b/arch/arm/mm/cache-v3.S
index 8a4abebc478a..2a482731ea36 100644
--- a/arch/arm/mm/cache-v3.S
+++ b/arch/arm/mm/cache-v3.S
@@ -72,14 +72,15 @@ ENTRY(v3_coherent_user_range)
         mov     pc, lr
 
 /*
- *      flush_kern_dcache_page(void *page)
+ *      flush_kern_dcache_area(void *page, size_t size)
  *
  *      Ensure no D cache aliasing occurs, either with itself or
  *      the I cache
  *
- *      - addr  - page aligned address
+ *      - addr  - kernel address
+ *      - size  - region size
  */
-ENTRY(v3_flush_kern_dcache_page)
+ENTRY(v3_flush_kern_dcache_area)
         /* FALLTHROUGH */
 
 /*
@@ -129,7 +130,7 @@ ENTRY(v3_cache_fns)
         .long   v3_flush_user_cache_range
         .long   v3_coherent_kern_range
         .long   v3_coherent_user_range
-        .long   v3_flush_kern_dcache_page
+        .long   v3_flush_kern_dcache_area
         .long   v3_dma_inv_range
         .long   v3_dma_clean_range
         .long   v3_dma_flush_range
diff --git a/arch/arm/mm/cache-v4.S b/arch/arm/mm/cache-v4.S
index 3668611cb400..5c7da3e372e9 100644
--- a/arch/arm/mm/cache-v4.S
+++ b/arch/arm/mm/cache-v4.S
@@ -82,14 +82,15 @@ ENTRY(v4_coherent_user_range)
         mov     pc, lr
 
 /*
- *      flush_kern_dcache_page(void *page)
+ *      flush_kern_dcache_area(void *addr, size_t size)
  *
  *      Ensure no D cache aliasing occurs, either with itself or
  *      the I cache
  *
- *      - addr  - page aligned address
+ *      - addr  - kernel address
+ *      - size  - region size
  */
-ENTRY(v4_flush_kern_dcache_page)
+ENTRY(v4_flush_kern_dcache_area)
         /* FALLTHROUGH */
 
 /*
@@ -141,7 +142,7 @@ ENTRY(v4_cache_fns)
         .long   v4_flush_user_cache_range
         .long   v4_coherent_kern_range
         .long   v4_coherent_user_range
-        .long   v4_flush_kern_dcache_page
+        .long   v4_flush_kern_dcache_area
         .long   v4_dma_inv_range
         .long   v4_dma_clean_range
         .long   v4_dma_flush_range
diff --git a/arch/arm/mm/cache-v4wb.S b/arch/arm/mm/cache-v4wb.S
index 2ebc1b3bf856..3dbedf1ec0e7 100644
--- a/arch/arm/mm/cache-v4wb.S
+++ b/arch/arm/mm/cache-v4wb.S
@@ -114,15 +114,16 @@ ENTRY(v4wb_flush_user_cache_range)
         mov     pc, lr
 
 /*
- *      flush_kern_dcache_page(void *page)
+ *      flush_kern_dcache_area(void *addr, size_t size)
  *
  *      Ensure no D cache aliasing occurs, either with itself or
  *      the I cache
  *
- *      - addr  - page aligned address
+ *      - addr  - kernel address
+ *      - size  - region size
  */
-ENTRY(v4wb_flush_kern_dcache_page)
-        add     r1, r0, #PAGE_SZ
+ENTRY(v4wb_flush_kern_dcache_area)
+        add     r1, r0, r1
         /* fall through */
 
 /*
@@ -224,7 +225,7 @@ ENTRY(v4wb_cache_fns)
         .long   v4wb_flush_user_cache_range
         .long   v4wb_coherent_kern_range
         .long   v4wb_coherent_user_range
-        .long   v4wb_flush_kern_dcache_page
+        .long   v4wb_flush_kern_dcache_area
         .long   v4wb_dma_inv_range
         .long   v4wb_dma_clean_range
         .long   v4wb_dma_flush_range
diff --git a/arch/arm/mm/cache-v4wt.S b/arch/arm/mm/cache-v4wt.S
index c54fa2cc40e6..b3b7410270b4 100644
--- a/arch/arm/mm/cache-v4wt.S
+++ b/arch/arm/mm/cache-v4wt.S
@@ -117,17 +117,18 @@ ENTRY(v4wt_coherent_user_range)
         mov     pc, lr
 
 /*
- *      flush_kern_dcache_page(void *page)
+ *      flush_kern_dcache_area(void *addr, size_t size)
  *
  *      Ensure no D cache aliasing occurs, either with itself or
  *      the I cache
  *
- *      - addr  - page aligned address
+ *      - addr  - kernel address
+ *      - size  - region size
  */
-ENTRY(v4wt_flush_kern_dcache_page)
+ENTRY(v4wt_flush_kern_dcache_area)
         mov     r2, #0
         mcr     p15, 0, r2, c7, c5, 0           @ invalidate I cache
-        add     r1, r0, #PAGE_SZ
+        add     r1, r0, r1
         /* fallthrough */
 
 /*
@@ -180,7 +181,7 @@ ENTRY(v4wt_cache_fns)
         .long   v4wt_flush_user_cache_range
         .long   v4wt_coherent_kern_range
         .long   v4wt_coherent_user_range
-        .long   v4wt_flush_kern_dcache_page
+        .long   v4wt_flush_kern_dcache_area
         .long   v4wt_dma_inv_range
         .long   v4wt_dma_clean_range
         .long   v4wt_dma_flush_range
diff --git a/arch/arm/mm/cache-v6.S b/arch/arm/mm/cache-v6.S
index 295e25dd6381..4ba0a24ce6f5 100644
--- a/arch/arm/mm/cache-v6.S
+++ b/arch/arm/mm/cache-v6.S
@@ -159,15 +159,16 @@ ENDPROC(v6_coherent_user_range)
 ENDPROC(v6_coherent_kern_range)
 
 /*
- *      v6_flush_kern_dcache_page(kaddr)
+ *      v6_flush_kern_dcache_area(void *addr, size_t size)
  *
  *      Ensure that the data held in the page kaddr is written back
  *      to the page in question.
  *
- *      - kaddr   - kernel address (guaranteed to be page aligned)
+ *      - addr  - kernel address
+ *      - size  - region size
  */
-ENTRY(v6_flush_kern_dcache_page)
-        add     r1, r0, #PAGE_SZ
+ENTRY(v6_flush_kern_dcache_area)
+        add     r1, r0, r1
 1:
 #ifdef HARVARD_CACHE
         mcr     p15, 0, r0, c7, c14, 1          @ clean & invalidate D line
@@ -271,7 +272,7 @@ ENTRY(v6_cache_fns)
         .long   v6_flush_user_cache_range
         .long   v6_coherent_kern_range
         .long   v6_coherent_user_range
-        .long   v6_flush_kern_dcache_page
+        .long   v6_flush_kern_dcache_area
         .long   v6_dma_inv_range
         .long   v6_dma_clean_range
         .long   v6_dma_flush_range
diff --git a/arch/arm/mm/cache-v7.S b/arch/arm/mm/cache-v7.S
index e1bd9759617f..9073db849fb4 100644
--- a/arch/arm/mm/cache-v7.S
+++ b/arch/arm/mm/cache-v7.S
@@ -186,16 +186,17 @@ ENDPROC(v7_coherent_kern_range)
 ENDPROC(v7_coherent_user_range)
 
 /*
- *      v7_flush_kern_dcache_page(kaddr)
+ *      v7_flush_kern_dcache_area(void *addr, size_t size)
  *
  *      Ensure that the data held in the page kaddr is written back
  *      to the page in question.
  *
- *      - kaddr   - kernel address (guaranteed to be page aligned)
+ *      - addr  - kernel address
+ *      - size  - region size
  */
-ENTRY(v7_flush_kern_dcache_page)
+ENTRY(v7_flush_kern_dcache_area)
         dcache_line_size r2, r3
-        add     r1, r0, #PAGE_SZ
+        add     r1, r0, r1
 1:
         mcr     p15, 0, r0, c7, c14, 1          @ clean & invalidate D line / unified line
         add     r0, r0, r2
@@ -203,7 +204,7 @@ ENTRY(v7_flush_kern_dcache_page)
         blo     1b
         dsb
         mov     pc, lr
-ENDPROC(v7_flush_kern_dcache_page)
+ENDPROC(v7_flush_kern_dcache_area)
 
 /*
  *      v7_dma_inv_range(start,end)
@@ -279,7 +280,7 @@ ENTRY(v7_cache_fns)
         .long   v7_flush_user_cache_range
         .long   v7_coherent_kern_range
         .long   v7_coherent_user_range
-        .long   v7_flush_kern_dcache_page
+        .long   v7_flush_kern_dcache_area
         .long   v7_dma_inv_range
         .long   v7_dma_clean_range
         .long   v7_dma_flush_range
diff --git a/arch/arm/mm/flush.c b/arch/arm/mm/flush.c
index 329594e760cd..6f3a4b7a3b82 100644
--- a/arch/arm/mm/flush.c
+++ b/arch/arm/mm/flush.c
@@ -131,7 +131,7 @@ void __flush_dcache_page(struct address_space *mapping, struct page *page)
          */
         if (addr)
 #endif
-                __cpuc_flush_dcache_page(addr);
+                __cpuc_flush_dcache_area(addr, PAGE_SIZE);
 
         /*
          * If this is a page cache page, and we have an aliasing VIPT cache,
@@ -258,5 +258,5 @@ void __flush_anon_page(struct vm_area_struct *vma, struct page *page, unsigned l
          * in this mapping of the page.  FIXME: this is overkill
          * since we actually ask for a write-back and invalidate.
          */
-        __cpuc_flush_dcache_page(page_address(page));
+        __cpuc_flush_dcache_area(page_address(page), PAGE_SIZE);
 }
diff --git a/arch/arm/mm/highmem.c b/arch/arm/mm/highmem.c
index 30f82fb5918c..2be1ec7c1b41 100644
--- a/arch/arm/mm/highmem.c
+++ b/arch/arm/mm/highmem.c
@@ -79,7 +79,7 @@ void kunmap_atomic(void *kvaddr, enum km_type type)
         unsigned int idx = type + KM_TYPE_NR * smp_processor_id();
 
         if (kvaddr >= (void *)FIXADDR_START) {
-                __cpuc_flush_dcache_page((void *)vaddr);
+                __cpuc_flush_dcache_area((void *)vaddr, PAGE_SIZE);
 #ifdef CONFIG_DEBUG_HIGHMEM
                 BUG_ON(vaddr != __fix_to_virt(FIX_KMAP_BEGIN + idx));
                 set_pte_ext(TOP_PTE(vaddr), __pte(0), 0);
diff --git a/arch/arm/mm/mmap.c b/arch/arm/mm/mmap.c
index 2b7996401b0f..f5abc51c5a07 100644
--- a/arch/arm/mm/mmap.c
+++ b/arch/arm/mm/mmap.c
@@ -54,7 +54,8 @@ arch_get_unmapped_area(struct file *filp, unsigned long addr,
          * We enforce the MAP_FIXED case.
          */
         if (flags & MAP_FIXED) {
-                if (aliasing && flags & MAP_SHARED && addr & (SHMLBA - 1))
+                if (aliasing && flags & MAP_SHARED &&
+                    (addr - (pgoff << PAGE_SHIFT)) & (SHMLBA - 1))
                         return -EINVAL;
                 return addr;
         }
diff --git a/arch/arm/mm/nommu.c b/arch/arm/mm/nommu.c
index 900811cc9130..374a8311bc84 100644
--- a/arch/arm/mm/nommu.c
+++ b/arch/arm/mm/nommu.c
@@ -61,7 +61,7 @@ void setup_mm_for_reboot(char mode)
 
 void flush_dcache_page(struct page *page)
 {
-        __cpuc_flush_dcache_page(page_address(page));
+        __cpuc_flush_dcache_area(page_address(page), PAGE_SIZE);
 }
 EXPORT_SYMBOL(flush_dcache_page);
 
diff --git a/arch/arm/mm/proc-arm1020.S b/arch/arm/mm/proc-arm1020.S
index d9fb4b98c49f..8012e24282b2 100644
--- a/arch/arm/mm/proc-arm1020.S
+++ b/arch/arm/mm/proc-arm1020.S
@@ -231,17 +231,18 @@ ENTRY(arm1020_coherent_user_range)
         mov     pc, lr
 
 /*
- *      flush_kern_dcache_page(void *page)
+ *      flush_kern_dcache_area(void *addr, size_t size)
  *
  *      Ensure no D cache aliasing occurs, either with itself or
  *      the I cache
  *
- *      - page  - page aligned address
+ *      - addr  - kernel address
+ *      - size  - region size
  */
-ENTRY(arm1020_flush_kern_dcache_page)
+ENTRY(arm1020_flush_kern_dcache_area)
         mov     ip, #0
 #ifndef CONFIG_CPU_DCACHE_DISABLE
-        add     r1, r0, #PAGE_SZ
+        add     r1, r0, r1
 1:      mcr     p15, 0, r0, c7, c14, 1          @ clean+invalidate D entry
         mcr     p15, 0, ip, c7, c10, 4          @ drain WB
         add     r0, r0, #CACHE_DLINESIZE
@@ -335,7 +336,7 @@ ENTRY(arm1020_cache_fns)
         .long   arm1020_flush_user_cache_range
         .long   arm1020_coherent_kern_range
         .long   arm1020_coherent_user_range
-        .long   arm1020_flush_kern_dcache_page
+        .long   arm1020_flush_kern_dcache_area
         .long   arm1020_dma_inv_range
         .long   arm1020_dma_clean_range
         .long   arm1020_dma_flush_range
diff --git a/arch/arm/mm/proc-arm1020e.S b/arch/arm/mm/proc-arm1020e.S
index 7453b75dcea5..41fe25d234f5 100644
--- a/arch/arm/mm/proc-arm1020e.S
+++ b/arch/arm/mm/proc-arm1020e.S
@@ -225,17 +225,18 @@ ENTRY(arm1020e_coherent_user_range)
         mov     pc, lr
 
 /*
- *      flush_kern_dcache_page(void *page)
+ *      flush_kern_dcache_area(void *addr, size_t size)
  *
  *      Ensure no D cache aliasing occurs, either with itself or
  *      the I cache
  *
- *      - page  - page aligned address
+ *      - addr  - kernel address
+ *      - size  - region size
  */
-ENTRY(arm1020e_flush_kern_dcache_page)
+ENTRY(arm1020e_flush_kern_dcache_area)
         mov     ip, #0
 #ifndef CONFIG_CPU_DCACHE_DISABLE
-        add     r1, r0, #PAGE_SZ
+        add     r1, r0, r1
 1:      mcr     p15, 0, r0, c7, c14, 1          @ clean+invalidate D entry
         add     r0, r0, #CACHE_DLINESIZE
         cmp     r0, r1
@@ -321,7 +322,7 @@ ENTRY(arm1020e_cache_fns)
         .long   arm1020e_flush_user_cache_range
         .long   arm1020e_coherent_kern_range
         .long   arm1020e_coherent_user_range
-        .long   arm1020e_flush_kern_dcache_page
+        .long   arm1020e_flush_kern_dcache_area
         .long   arm1020e_dma_inv_range
         .long   arm1020e_dma_clean_range
         .long   arm1020e_dma_flush_range
diff --git a/arch/arm/mm/proc-arm1022.S b/arch/arm/mm/proc-arm1022.S
index 8eb72d75a8b6..20a5b1b31a70 100644
--- a/arch/arm/mm/proc-arm1022.S
+++ b/arch/arm/mm/proc-arm1022.S
@@ -214,17 +214,18 @@ ENTRY(arm1022_coherent_user_range)
         mov     pc, lr
 
 /*
- *      flush_kern_dcache_page(void *page)
+ *      flush_kern_dcache_area(void *addr, size_t size)
  *
  *      Ensure no D cache aliasing occurs, either with itself or
  *      the I cache
  *
- *      - page  - page aligned address
+ *      - addr  - kernel address
+ *      - size  - region size
  */
-ENTRY(arm1022_flush_kern_dcache_page)
+ENTRY(arm1022_flush_kern_dcache_area)
         mov     ip, #0
 #ifndef CONFIG_CPU_DCACHE_DISABLE
-        add     r1, r0, #PAGE_SZ
+        add     r1, r0, r1
 1:      mcr     p15, 0, r0, c7, c14, 1          @ clean+invalidate D entry
         add     r0, r0, #CACHE_DLINESIZE
         cmp     r0, r1
@@ -310,7 +311,7 @@ ENTRY(arm1022_cache_fns)
         .long   arm1022_flush_user_cache_range
         .long   arm1022_coherent_kern_range
         .long   arm1022_coherent_user_range
-        .long   arm1022_flush_kern_dcache_page
+        .long   arm1022_flush_kern_dcache_area
         .long   arm1022_dma_inv_range
         .long   arm1022_dma_clean_range
         .long   arm1022_dma_flush_range
diff --git a/arch/arm/mm/proc-arm1026.S b/arch/arm/mm/proc-arm1026.S
index 3b59f0d67139..96aedb10fcc4 100644
--- a/arch/arm/mm/proc-arm1026.S
+++ b/arch/arm/mm/proc-arm1026.S
@@ -208,17 +208,18 @@ ENTRY(arm1026_coherent_user_range)
         mov     pc, lr
 
 /*
- *      flush_kern_dcache_page(void *page)
+ *      flush_kern_dcache_area(void *addr, size_t size)
  *
  *      Ensure no D cache aliasing occurs, either with itself or
  *      the I cache
  *
- *      - page  - page aligned address
+ *      - addr  - kernel address
+ *      - size  - region size
  */
-ENTRY(arm1026_flush_kern_dcache_page)
+ENTRY(arm1026_flush_kern_dcache_area)
         mov     ip, #0
 #ifndef CONFIG_CPU_DCACHE_DISABLE
-        add     r1, r0, #PAGE_SZ
+        add     r1, r0, r1
 1:      mcr     p15, 0, r0, c7, c14, 1          @ clean+invalidate D entry
         add     r0, r0, #CACHE_DLINESIZE
         cmp     r0, r1
@@ -304,7 +305,7 @@ ENTRY(arm1026_cache_fns)
         .long   arm1026_flush_user_cache_range
         .long   arm1026_coherent_kern_range
         .long   arm1026_coherent_user_range
-        .long   arm1026_flush_kern_dcache_page
+        .long   arm1026_flush_kern_dcache_area
         .long   arm1026_dma_inv_range
         .long   arm1026_dma_clean_range
         .long   arm1026_dma_flush_range
diff --git a/arch/arm/mm/proc-arm920.S b/arch/arm/mm/proc-arm920.S
index 2b7c197cc58d..471669e2d7cb 100644
--- a/arch/arm/mm/proc-arm920.S
+++ b/arch/arm/mm/proc-arm920.S
@@ -207,15 +207,16 @@ ENTRY(arm920_coherent_user_range)
         mov     pc, lr
 
 /*
- *      flush_kern_dcache_page(void *page)
+ *      flush_kern_dcache_area(void *addr, size_t size)
  *
  *      Ensure no D cache aliasing occurs, either with itself or
  *      the I cache
  *
- *      - addr  - page aligned address
+ *      - addr  - kernel address
+ *      - size  - region size
  */
-ENTRY(arm920_flush_kern_dcache_page)
-        add     r1, r0, #PAGE_SZ
+ENTRY(arm920_flush_kern_dcache_area)
+        add     r1, r0, r1
 1:      mcr     p15, 0, r0, c7, c14, 1          @ clean+invalidate D entry
         add     r0, r0, #CACHE_DLINESIZE
         cmp     r0, r1
@@ -293,7 +294,7 @@ ENTRY(arm920_cache_fns)
         .long   arm920_flush_user_cache_range
         .long   arm920_coherent_kern_range
         .long   arm920_coherent_user_range
-        .long   arm920_flush_kern_dcache_page
+        .long   arm920_flush_kern_dcache_area
         .long   arm920_dma_inv_range
         .long   arm920_dma_clean_range
         .long   arm920_dma_flush_range
diff --git a/arch/arm/mm/proc-arm922.S b/arch/arm/mm/proc-arm922.S
index 06a1aa4e3398..ee111b00fa41 100644
--- a/arch/arm/mm/proc-arm922.S
+++ b/arch/arm/mm/proc-arm922.S
@@ -209,15 +209,16 @@ ENTRY(arm922_coherent_user_range)
         mov     pc, lr
 
 /*
- *      flush_kern_dcache_page(void *page)
+ *      flush_kern_dcache_area(void *addr, size_t size)
  *
  *      Ensure no D cache aliasing occurs, either with itself or
  *      the I cache
  *
- *      - addr  - page aligned address
+ *      - addr  - kernel address
+ *      - size  - region size
  */
-ENTRY(arm922_flush_kern_dcache_page)
-        add     r1, r0, #PAGE_SZ
+ENTRY(arm922_flush_kern_dcache_area)
+        add     r1, r0, r1
 1:      mcr     p15, 0, r0, c7, c14, 1          @ clean+invalidate D entry
         add     r0, r0, #CACHE_DLINESIZE
         cmp     r0, r1
@@ -295,7 +296,7 @@ ENTRY(arm922_cache_fns)
         .long   arm922_flush_user_cache_range
         .long   arm922_coherent_kern_range
         .long   arm922_coherent_user_range
-        .long   arm922_flush_kern_dcache_page
+        .long   arm922_flush_kern_dcache_area
         .long   arm922_dma_inv_range
         .long   arm922_dma_clean_range
         .long   arm922_dma_flush_range
diff --git a/arch/arm/mm/proc-arm925.S b/arch/arm/mm/proc-arm925.S
index cb53435a85ae..8deb5bde58e4 100644
--- a/arch/arm/mm/proc-arm925.S
+++ b/arch/arm/mm/proc-arm925.S
@@ -251,15 +251,16 @@ ENTRY(arm925_coherent_user_range)
         mov     pc, lr
 
 /*
- *      flush_kern_dcache_page(void *page)
+ *      flush_kern_dcache_area(void *addr, size_t size)
  *
  *      Ensure no D cache aliasing occurs, either with itself or
  *      the I cache
  *
- *      - addr  - page aligned address
+ *      - addr  - kernel address
+ *      - size  - region size
  */
-ENTRY(arm925_flush_kern_dcache_page)
-        add     r1, r0, #PAGE_SZ
+ENTRY(arm925_flush_kern_dcache_area)
+        add     r1, r0, r1
 1:      mcr     p15, 0, r0, c7, c14, 1          @ clean+invalidate D entry
         add     r0, r0, #CACHE_DLINESIZE
         cmp     r0, r1
@@ -346,7 +347,7 @@ ENTRY(arm925_cache_fns)
         .long   arm925_flush_user_cache_range
         .long   arm925_coherent_kern_range
         .long   arm925_coherent_user_range
-        .long   arm925_flush_kern_dcache_page
+        .long   arm925_flush_kern_dcache_area
         .long   arm925_dma_inv_range
         .long   arm925_dma_clean_range
         .long   arm925_dma_flush_range
diff --git a/arch/arm/mm/proc-arm926.S b/arch/arm/mm/proc-arm926.S
index 1c4848704bb3..64db6e275a44 100644
--- a/arch/arm/mm/proc-arm926.S
+++ b/arch/arm/mm/proc-arm926.S
@@ -214,15 +214,16 @@ ENTRY(arm926_coherent_user_range)
         mov     pc, lr
 
 /*
- *      flush_kern_dcache_page(void *page)
+ *      flush_kern_dcache_area(void *addr, size_t size)
  *
  *      Ensure no D cache aliasing occurs, either with itself or
  *      the I cache
  *
- *      - addr  - page aligned address
+ *      - addr  - kernel address
+ *      - size  - region size
  */
-ENTRY(arm926_flush_kern_dcache_page)
-        add     r1, r0, #PAGE_SZ
+ENTRY(arm926_flush_kern_dcache_area)
+        add     r1, r0, r1
 1:      mcr     p15, 0, r0, c7, c14, 1          @ clean+invalidate D entry
         add     r0, r0, #CACHE_DLINESIZE
         cmp     r0, r1
@@ -309,7 +310,7 @@ ENTRY(arm926_cache_fns)
         .long   arm926_flush_user_cache_range
         .long   arm926_coherent_kern_range
         .long   arm926_coherent_user_range
-        .long   arm926_flush_kern_dcache_page
+        .long   arm926_flush_kern_dcache_area
         .long   arm926_dma_inv_range
         .long   arm926_dma_clean_range
         .long   arm926_dma_flush_range
diff --git a/arch/arm/mm/proc-arm940.S b/arch/arm/mm/proc-arm940.S
index 5b0f8464c8f2..8196b9f401fb 100644
--- a/arch/arm/mm/proc-arm940.S
+++ b/arch/arm/mm/proc-arm940.S
@@ -141,14 +141,15 @@ ENTRY(arm940_coherent_user_range)
         /* FALLTHROUGH */
 
 /*
- *      flush_kern_dcache_page(void *page)
+ *      flush_kern_dcache_area(void *addr, size_t size)
  *
  *      Ensure no D cache aliasing occurs, either with itself or
  *      the I cache
  *
- *      - addr  - page aligned address
+ *      - addr  - kernel address
+ *      - size  - region size
  */
-ENTRY(arm940_flush_kern_dcache_page)
+ENTRY(arm940_flush_kern_dcache_area)
         mov     ip, #0
         mov     r1, #(CACHE_DSEGMENTS - 1) << 4 @ 4 segments
 1:      orr     r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries
@@ -238,7 +239,7 @@ ENTRY(arm940_cache_fns)
         .long   arm940_flush_user_cache_range
         .long   arm940_coherent_kern_range
         .long   arm940_coherent_user_range
-        .long   arm940_flush_kern_dcache_page
+        .long   arm940_flush_kern_dcache_area
         .long   arm940_dma_inv_range
         .long   arm940_dma_clean_range
         .long   arm940_dma_flush_range
diff --git a/arch/arm/mm/proc-arm946.S b/arch/arm/mm/proc-arm946.S
index 40c0449a139b..9a951239c86c 100644
--- a/arch/arm/mm/proc-arm946.S
+++ b/arch/arm/mm/proc-arm946.S
@@ -183,16 +183,17 @@ ENTRY(arm946_coherent_user_range)
         mov     pc, lr
 
 /*
- *      flush_kern_dcache_page(void *page)
+ *      flush_kern_dcache_area(void *addr, size_t size)
  *
  *      Ensure no D cache aliasing occurs, either with itself or
  *      the I cache
  *
- *      - addr  - page aligned address
+ *      - addr  - kernel address
+ *      - size  - region size
  * (same as arm926)
  */
-ENTRY(arm946_flush_kern_dcache_page)
-        add     r1, r0, #PAGE_SZ
+ENTRY(arm946_flush_kern_dcache_area)
+        add     r1, r0, r1
 1:      mcr     p15, 0, r0, c7, c14, 1          @ clean+invalidate D entry
         add     r0, r0, #CACHE_DLINESIZE
         cmp     r0, r1
@@ -280,7 +281,7 @@ ENTRY(arm946_cache_fns)
         .long   arm946_flush_user_cache_range
         .long   arm946_coherent_kern_range
         .long   arm946_coherent_user_range
-        .long   arm946_flush_kern_dcache_page
+        .long   arm946_flush_kern_dcache_area
         .long   arm946_dma_inv_range
         .long   arm946_dma_clean_range
         .long   arm946_dma_flush_range
diff --git a/arch/arm/mm/proc-feroceon.S b/arch/arm/mm/proc-feroceon.S
index d0d7795200fc..dbc39383e66a 100644
--- a/arch/arm/mm/proc-feroceon.S
+++ b/arch/arm/mm/proc-feroceon.S
@@ -226,16 +226,17 @@ ENTRY(feroceon_coherent_user_range)
         mov     pc, lr
 
 /*
- *      flush_kern_dcache_page(void *page)
+ *      flush_kern_dcache_area(void *addr, size_t size)
  *
  *      Ensure no D cache aliasing occurs, either with itself or
  *      the I cache
  *
- *      - addr  - page aligned address
+ *      - addr  - kernel address
+ *      - size  - region size
  */
         .align  5
-ENTRY(feroceon_flush_kern_dcache_page)
-        add     r1, r0, #PAGE_SZ
+ENTRY(feroceon_flush_kern_dcache_area)
+        add     r1, r0, r1
 1:      mcr     p15, 0, r0, c7, c14, 1          @ clean+invalidate D entry
         add     r0, r0, #CACHE_DLINESIZE
         cmp     r0, r1
@@ -246,7 +247,7 @@ ENTRY(feroceon_flush_kern_dcache_page)
         mov     pc, lr
 
         .align  5
-ENTRY(feroceon_range_flush_kern_dcache_page)
+ENTRY(feroceon_range_flush_kern_dcache_area)
         mrs     r2, cpsr
         add     r1, r0, #PAGE_SZ - CACHE_DLINESIZE      @ top addr is inclusive
         orr     r3, r2, #PSR_I_BIT
@@ -372,7 +373,7 @@ ENTRY(feroceon_cache_fns)
         .long   feroceon_flush_user_cache_range
         .long   feroceon_coherent_kern_range
         .long   feroceon_coherent_user_range
-        .long   feroceon_flush_kern_dcache_page
+        .long   feroceon_flush_kern_dcache_area
         .long   feroceon_dma_inv_range
         .long   feroceon_dma_clean_range
         .long   feroceon_dma_flush_range
@@ -383,7 +384,7 @@ ENTRY(feroceon_range_cache_fns)
         .long   feroceon_flush_user_cache_range
         .long   feroceon_coherent_kern_range
         .long   feroceon_coherent_user_range
-        .long   feroceon_range_flush_kern_dcache_page
+        .long   feroceon_range_flush_kern_dcache_area
         .long   feroceon_range_dma_inv_range
         .long   feroceon_range_dma_clean_range
         .long   feroceon_range_dma_flush_range
diff --git a/arch/arm/mm/proc-mohawk.S b/arch/arm/mm/proc-mohawk.S
index 52b5fd74fbb3..9674d36cc97d 100644
--- a/arch/arm/mm/proc-mohawk.S
+++ b/arch/arm/mm/proc-mohawk.S
@@ -186,15 +186,16 @@ ENTRY(mohawk_coherent_user_range)
         mov     pc, lr
 
 /*
- *      flush_kern_dcache_page(void *page)
+ *      flush_kern_dcache_area(void *addr, size_t size)
  *
  *      Ensure no D cache aliasing occurs, either with itself or
  *      the I cache
  *
- *      - addr  - page aligned address
+ *      - addr  - kernel address
+ *      - size  - region size
  */
-ENTRY(mohawk_flush_kern_dcache_page)
-        add     r1, r0, #PAGE_SZ
+ENTRY(mohawk_flush_kern_dcache_area)
+        add     r1, r0, r1
 1:      mcr     p15, 0, r0, c7, c14, 1          @ clean+invalidate D entry
         add     r0, r0, #CACHE_DLINESIZE
         cmp     r0, r1
@@ -273,7 +274,7 @@ ENTRY(mohawk_cache_fns)
         .long   mohawk_flush_user_cache_range
         .long   mohawk_coherent_kern_range
         .long   mohawk_coherent_user_range
-        .long   mohawk_flush_kern_dcache_page
+        .long   mohawk_flush_kern_dcache_area
         .long   mohawk_dma_inv_range
         .long   mohawk_dma_clean_range
         .long   mohawk_dma_flush_range
diff --git a/arch/arm/mm/proc-syms.c b/arch/arm/mm/proc-syms.c
index ac5c80062b70..3e6210b4d6d4 100644
--- a/arch/arm/mm/proc-syms.c
+++ b/arch/arm/mm/proc-syms.c
@@ -27,8 +27,7 @@ EXPORT_SYMBOL(__cpuc_flush_kern_all);
 EXPORT_SYMBOL(__cpuc_flush_user_all);
 EXPORT_SYMBOL(__cpuc_flush_user_range);
 EXPORT_SYMBOL(__cpuc_coherent_kern_range);
-EXPORT_SYMBOL(__cpuc_flush_dcache_page);
-EXPORT_SYMBOL(dmac_inv_range);  /* because of flush_ioremap_region() */
+EXPORT_SYMBOL(__cpuc_flush_dcache_area);
 #else
 EXPORT_SYMBOL(cpu_cache);
 #endif
diff --git a/arch/arm/mm/proc-v6.S b/arch/arm/mm/proc-v6.S
index 5485c821101c..395cc90c6613 100644
--- a/arch/arm/mm/proc-v6.S
+++ b/arch/arm/mm/proc-v6.S
@@ -254,10 +254,9 @@ __pj4_v6_proc_info:
         .long   0x560f5810
         .long   0xff0ffff0
         .long   PMD_TYPE_SECT | \
-                PMD_SECT_BUFFERABLE | \
-                PMD_SECT_CACHEABLE | \
                 PMD_SECT_AP_WRITE | \
-                PMD_SECT_AP_READ
+                PMD_SECT_AP_READ | \
+                PMD_FLAGS
         .long   PMD_TYPE_SECT | \
                 PMD_SECT_XN | \
                 PMD_SECT_AP_WRITE | \
diff --git a/arch/arm/mm/proc-xsc3.S b/arch/arm/mm/proc-xsc3.S
index fab134e29826..96456f548798 100644
--- a/arch/arm/mm/proc-xsc3.S
+++ b/arch/arm/mm/proc-xsc3.S
@@ -226,15 +226,16 @@ ENTRY(xsc3_coherent_user_range)
         mov     pc, lr
 
 /*
- *      flush_kern_dcache_page(void *page)
+ *      flush_kern_dcache_area(void *addr, size_t size)
  *
  *      Ensure no D cache aliasing occurs, either with itself or
  *      the I cache.
  *
- *      - addr  - page aligned address
+ *      - addr  - kernel address
+ *      - size  - region size
  */
-ENTRY(xsc3_flush_kern_dcache_page)
-        add     r1, r0, #PAGE_SZ
+ENTRY(xsc3_flush_kern_dcache_area)
+        add     r1, r0, r1
 1:      mcr     p15, 0, r0, c7, c14, 1          @ clean/invalidate L1 D line
         add     r0, r0, #CACHELINESIZE
         cmp     r0, r1
@@ -309,7 +310,7 @@ ENTRY(xsc3_cache_fns)
         .long   xsc3_flush_user_cache_range
         .long   xsc3_coherent_kern_range
         .long   xsc3_coherent_user_range
-        .long   xsc3_flush_kern_dcache_page
+        .long   xsc3_flush_kern_dcache_area
         .long   xsc3_dma_inv_range
         .long   xsc3_dma_clean_range
         .long   xsc3_dma_flush_range
diff --git a/arch/arm/mm/proc-xscale.S b/arch/arm/mm/proc-xscale.S
index f056c283682d..93df47265f2d 100644
--- a/arch/arm/mm/proc-xscale.S
+++ b/arch/arm/mm/proc-xscale.S
@@ -284,15 +284,16 @@ ENTRY(xscale_coherent_user_range)
         mov     pc, lr
 
 /*
- *      flush_kern_dcache_page(void *page)
+ *      flush_kern_dcache_area(void *addr, size_t size)
  *
  *      Ensure no D cache aliasing occurs, either with itself or
  *      the I cache
  *
- *      - addr  - page aligned address
+ *      - addr  - kernel address
+ *      - size  - region size
  */
-ENTRY(xscale_flush_kern_dcache_page)
-        add     r1, r0, #PAGE_SZ
+ENTRY(xscale_flush_kern_dcache_area)
+        add     r1, r0, r1
 1:      mcr     p15, 0, r0, c7, c10, 1          @ clean D entry
         mcr     p15, 0, r0, c7, c6, 1           @ invalidate D entry
         add     r0, r0, #CACHELINESIZE
@@ -368,7 +369,7 @@ ENTRY(xscale_cache_fns)
         .long   xscale_flush_user_cache_range
         .long   xscale_coherent_kern_range
         .long   xscale_coherent_user_range
-        .long   xscale_flush_kern_dcache_page
+        .long   xscale_flush_kern_dcache_area
         .long   xscale_dma_inv_range
         .long   xscale_dma_clean_range
         .long   xscale_dma_flush_range
@@ -392,7 +393,7 @@ ENTRY(xscale_80200_A0_A1_cache_fns)
         .long   xscale_flush_user_cache_range
         .long   xscale_coherent_kern_range
         .long   xscale_coherent_user_range
-        .long   xscale_flush_kern_dcache_page
+        .long   xscale_flush_kern_dcache_area
         .long   xscale_dma_flush_range
         .long   xscale_dma_clean_range
         .long   xscale_dma_flush_range
diff --git a/arch/arm/plat-mxc/Makefile b/arch/arm/plat-mxc/Makefile
index 4cbca9da1505..996cbac6932c 100644
--- a/arch/arm/plat-mxc/Makefile
+++ b/arch/arm/plat-mxc/Makefile
@@ -9,6 +9,7 @@ obj-$(CONFIG_ARCH_MX1) += iomux-mx1-mx2.o dma-mx1-mx2.o
 obj-$(CONFIG_ARCH_MX2) += iomux-mx1-mx2.o dma-mx1-mx2.o
 obj-$(CONFIG_ARCH_MXC_IOMUX_V3) += iomux-v3.o
 obj-$(CONFIG_MXC_PWM)  += pwm.o
+obj-$(CONFIG_USB_EHCI_MXC) += ehci.o
 obj-$(CONFIG_MXC_ULPI) += ulpi.o
 obj-$(CONFIG_ARCH_MXC_AUDMUX_V1) += audmux-v1.o
 obj-$(CONFIG_ARCH_MXC_AUDMUX_V2) += audmux-v2.o
diff --git a/arch/arm/plat-mxc/ehci.c b/arch/arm/plat-mxc/ehci.c
new file mode 100644
index 000000000000..41599be882e8
--- /dev/null
+++ b/arch/arm/plat-mxc/ehci.c
@@ -0,0 +1,92 @@
+/*
+ * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ * for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software Foundation,
+ * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <linux/platform_device.h>
+#include <linux/io.h>
+
+#include <mach/hardware.h>
+#include <mach/mxc_ehci.h>
+
+#define USBCTRL_OTGBASE_OFFSET  0x600
+
+#define MX31_OTG_SIC_SHIFT      29
+#define MX31_OTG_SIC_MASK       (0xf << MX31_OTG_SIC_SHIFT)
+#define MX31_OTG_PM_BIT         (1 << 24)
+
+#define MX31_H2_SIC_SHIFT       21
+#define MX31_H2_SIC_MASK        (0xf << MX31_H2_SIC_SHIFT)
+#define MX31_H2_PM_BIT          (1 << 16)
+#define MX31_H2_DT_BIT          (1 << 5)
+
+#define MX31_H1_SIC_SHIFT       13
+#define MX31_H1_SIC_MASK        (0xf << MX31_H1_SIC_SHIFT)
+#define MX31_H1_PM_BIT          (1 << 8)
+#define MX31_H1_DT_BIT          (1 << 4)
+
+int mxc_set_usbcontrol(int port, unsigned int flags)
+{
+        unsigned int v;
+
+        if (cpu_is_mx31()) {
+                v = readl(IO_ADDRESS(MX31_OTG_BASE_ADDR +
+                                     USBCTRL_OTGBASE_OFFSET));
+
+                switch (port) {
+                case 0: /* OTG port */
+                        v &= ~(MX31_OTG_SIC_MASK | MX31_OTG_PM_BIT);
+                        v |= (flags & MXC_EHCI_INTERFACE_MASK)
+                                        << MX31_OTG_SIC_SHIFT;
+                        if (flags & MXC_EHCI_POWER_PINS_ENABLED)
+                                v |= MX31_OTG_PM_BIT;
+
+                        break;
+                case 1: /* H1 port */
+                        v &= ~(MX31_H1_SIC_MASK | MX31_H1_PM_BIT);
+                        v |= (flags & MXC_EHCI_INTERFACE_MASK)
+                                                << MX31_H1_SIC_SHIFT;
+                        if (flags & MXC_EHCI_POWER_PINS_ENABLED)
+                                v |= MX31_H1_PM_BIT;
+
+                        if (!(flags & MXC_EHCI_TTL_ENABLED))
+                                v |= MX31_H1_DT_BIT;
+
+                        break;
+                case 2: /* H2 port */
+                        v &= ~(MX31_H2_SIC_MASK | MX31_H2_PM_BIT);
+                        v |= (flags & MXC_EHCI_INTERFACE_MASK)
+                                                << MX31_H2_SIC_SHIFT;
+                        if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
+                                v |= MX31_H2_PM_BIT;
+
+                        if (!(flags & MXC_EHCI_TTL_ENABLED))
+                                v |= MX31_H2_DT_BIT;
+
+                        break;
+                }
+
+                writel(v, IO_ADDRESS(MX31_OTG_BASE_ADDR +
+                                     USBCTRL_OTGBASE_OFFSET));
+                return 0;
+        }
+
+        printk(KERN_WARNING
+                "%s() unable to setup USBCONTROL for this CPU\n", __func__);
+        return -EINVAL;
+}
+EXPORT_SYMBOL(mxc_set_usbcontrol);
+
diff --git a/arch/arm/plat-mxc/include/mach/mxc_ehci.h b/arch/arm/plat-mxc/include/mach/mxc_ehci.h
new file mode 100644
index 000000000000..8f796239393e
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/mxc_ehci.h
@@ -0,0 +1,37 @@
+#ifndef __INCLUDE_ASM_ARCH_MXC_EHCI_H
+#define __INCLUDE_ASM_ARCH_MXC_EHCI_H
+
+/* values for portsc field */
+#define MXC_EHCI_PHY_LOW_POWER_SUSPEND  (1 << 23)
+#define MXC_EHCI_FORCE_FS               (1 << 24)
+#define MXC_EHCI_UTMI_8BIT              (0 << 28)
+#define MXC_EHCI_UTMI_16BIT             (1 << 28)
+#define MXC_EHCI_SERIAL                 (1 << 29)
+#define MXC_EHCI_MODE_UTMI              (0 << 30)
+#define MXC_EHCI_MODE_PHILIPS           (1 << 30)
+#define MXC_EHCI_MODE_ULPI              (2 << 30)
+#define MXC_EHCI_MODE_SERIAL            (3 << 30)
+
+/* values for flags field */
+#define MXC_EHCI_INTERFACE_DIFF_UNI     (0 << 0)
+#define MXC_EHCI_INTERFACE_DIFF_BI      (1 << 0)
+#define MXC_EHCI_INTERFACE_SINGLE_UNI   (2 << 0)
+#define MXC_EHCI_INTERFACE_SINGLE_BI    (3 << 0)
+#define MXC_EHCI_INTERFACE_MASK         (0xf)
+
+#define MXC_EHCI_POWER_PINS_ENABLED     (1 << 5)
+#define MXC_EHCI_TTL_ENABLED            (1 << 6)
+
+struct mxc_usbh_platform_data {
+        int (*init)(struct platform_device *pdev);
+        int (*exit)(struct platform_device *pdev);
+
+        unsigned int             portsc;
+        unsigned int             flags;
+        struct otg_transceiver  *otg;
+};
+
+int mxc_set_usbcontrol(int port, unsigned int flags);
+
+#endif /* __INCLUDE_ASM_ARCH_MXC_EHCI_H */
+
diff --git a/arch/arm/plat-mxc/include/mach/mxc_nand.h b/arch/arm/plat-mxc/include/mach/mxc_nand.h
index 2b972df22d12..5d2d21d414e0 100644
--- a/arch/arm/plat-mxc/include/mach/mxc_nand.h
+++ b/arch/arm/plat-mxc/include/mach/mxc_nand.h
@@ -22,6 +22,7 @@
 
 struct mxc_nand_platform_data {
         int width;      /* data bus width in bytes */
-        int hw_ecc;     /* 0 if supress hardware ECC */
+        int hw_ecc:1;   /* 0 if supress hardware ECC */
+        int flash_bbt:1; /* set to 1 to use a flash based bbt */
 };
 #endif /* __ASM_ARCH_NAND_H */
diff --git a/arch/arm/plat-omap/Kconfig b/arch/arm/plat-omap/Kconfig
index f348ddfb0492..e2ea04a4c8a1 100644
--- a/arch/arm/plat-omap/Kconfig
+++ b/arch/arm/plat-omap/Kconfig
@@ -27,6 +27,7 @@ config ARCH_OMAP4
         bool "TI OMAP4"
         select CPU_V7
         select ARM_GIC
+        select COMMON_CLKDEV
 
 endchoice
 
@@ -42,28 +43,6 @@ config OMAP_DEBUG_LEDS
         depends on OMAP_DEBUG_DEVICES
         default y if LEDS || LEDS_OMAP_DEBUG
 
-config OMAP_DEBUG_POWERDOMAIN
-        bool "Emit debug messages from powerdomain layer"
-        depends on ARCH_OMAP2 || ARCH_OMAP3
-        help
-          Say Y here if you want to compile in powerdomain layer
-          debugging messages for OMAP2/3.   These messages can
-          provide more detail as to why some powerdomain calls
-          may be failing, and will also emit a descriptive message
-          for every powerdomain register write.  However, the
-          extra detail costs some memory.
-
-config OMAP_DEBUG_CLOCKDOMAIN
-        bool "Emit debug messages from clockdomain layer"
-        depends on ARCH_OMAP2 || ARCH_OMAP3
-        help
-          Say Y here if you want to compile in clockdomain layer
-          debugging messages for OMAP2/3.   These messages can
-          provide more detail as to why some clockdomain calls
-          may be failing, and will also emit a descriptive message
-          for every clockdomain register write.  However, the
-          extra detail costs some memory.
-
 config OMAP_RESET_CLOCKS
         bool "Reset unused clocks during boot"
         depends on ARCH_OMAP
@@ -78,28 +57,28 @@ config OMAP_RESET_CLOCKS
 
 config OMAP_MUX
         bool "OMAP multiplexing support"
-        depends on ARCH_OMAP
+        depends on ARCH_OMAP
         default y
-        help
-          Pin multiplexing support for OMAP boards. If your bootloader
-          sets the multiplexing correctly, say N. Otherwise, or if unsure,
-          say Y.
+        help
+          Pin multiplexing support for OMAP boards. If your bootloader
+          sets the multiplexing correctly, say N. Otherwise, or if unsure,
+          say Y.
 
 config OMAP_MUX_DEBUG
         bool "Multiplexing debug output"
-        depends on OMAP_MUX
-        help
-          Makes the multiplexing functions print out a lot of debug info.
-          This is useful if you want to find out the correct values of the
-          multiplexing registers.
+        depends on OMAP_MUX
+        help
+          Makes the multiplexing functions print out a lot of debug info.
+          This is useful if you want to find out the correct values of the
+          multiplexing registers.
 
 config OMAP_MUX_WARNINGS
         bool "Warn about pins the bootloader didn't set up"
-        depends on OMAP_MUX
-        default y
-        help
+        depends on OMAP_MUX
+        default y
+        help
           Choose Y here to warn whenever driver initialization logic needs
-          to change the pin multiplexing setup.  When there are no warnings
+          to change the pin multiplexing setup.  When there are no warnings
           printed, it's safe to deselect OMAP_MUX for your product.
 
 config OMAP_MCBSP
@@ -125,7 +104,7 @@ config OMAP_IOMMU_DEBUG
         tristate
 
 choice
-        prompt "System timer"
+        prompt "System timer"
         default OMAP_MPU_TIMER
 
 config OMAP_MPU_TIMER
@@ -148,11 +127,11 @@ config OMAP_32K_TIMER
 endchoice
 
 config OMAP_32K_TIMER_HZ
-       int "Kernel internal timer frequency for 32KHz timer"
-       range 32 1024
-       depends on OMAP_32K_TIMER
-       default "128"
-       help
+        int "Kernel internal timer frequency for 32KHz timer"
+        range 32 1024
+        depends on OMAP_32K_TIMER
+        default "128"
+        help
           Kernel internal timer frequency should be a divisor of 32768,
           such as 64 or 128.
 
diff --git a/arch/arm/plat-omap/clock.c b/arch/arm/plat-omap/clock.c
index 681bfc37ebb2..89cafc937249 100644
--- a/arch/arm/plat-omap/clock.c
+++ b/arch/arm/plat-omap/clock.c
@@ -40,36 +40,10 @@ static struct clk_functions *arch_clock;
  * clock framework is not up , it is defined here to avoid rework in
  * every driver. Also dummy prcm reset function is added */
 
-/* Dummy hooks only for OMAP4.For rest OMAPs, common clkdev is used */
-#if defined(CONFIG_ARCH_OMAP4)
-struct clk *clk_get(struct device *dev, const char *id)
-{
-        return NULL;
-}
-EXPORT_SYMBOL(clk_get);
-
-void clk_put(struct clk *clk)
-{
-}
-EXPORT_SYMBOL(clk_put);
-
-void omap2_clk_prepare_for_reboot(void)
-{
-}
-EXPORT_SYMBOL(omap2_clk_prepare_for_reboot);
-
-void omap_prcm_arch_reset(char mode)
-{
-}
-EXPORT_SYMBOL(omap_prcm_arch_reset);
-#endif
 int clk_enable(struct clk *clk)
 {
         unsigned long flags;
         int ret = 0;
-        if (cpu_is_omap44xx())
-                /* OMAP4 clk framework not supported yet */
-                return 0;
 
         if (clk == NULL || IS_ERR(clk))
                 return -EINVAL;
diff --git a/arch/arm/plat-omap/common.c b/arch/arm/plat-omap/common.c
index cc050b3313bd..bf1eaf3a27d4 100644
--- a/arch/arm/plat-omap/common.c
+++ b/arch/arm/plat-omap/common.c
@@ -280,16 +280,18 @@ void __init omap2_set_globals_343x(void)
 #if defined(CONFIG_ARCH_OMAP4)
 static struct omap_globals omap4_globals = {
         .class  = OMAP443X_CLASS,
-        .tap    = OMAP2_L4_IO_ADDRESS(0x4830a000),
+        .tap    = OMAP2_L4_IO_ADDRESS(OMAP443X_SCM_BASE),
         .ctrl   = OMAP2_L4_IO_ADDRESS(OMAP443X_CTRL_BASE),
         .prm    = OMAP2_L4_IO_ADDRESS(OMAP4430_PRM_BASE),
         .cm     = OMAP2_L4_IO_ADDRESS(OMAP4430_CM_BASE),
+        .cm2    = OMAP2_L4_IO_ADDRESS(OMAP4430_CM2_BASE),
 };
 
 void __init omap2_set_globals_443x(void)
 {
         omap2_set_globals_tap(&omap4_globals);
         omap2_set_globals_control(&omap4_globals);
+        omap2_set_globals_prcm(&omap4_globals);
 }
 #endif
 
diff --git a/arch/arm/plat-omap/debug-devices.c b/arch/arm/plat-omap/debug-devices.c
index 09c1107637f6..923c9621096b 100644
--- a/arch/arm/plat-omap/debug-devices.c
+++ b/arch/arm/plat-omap/debug-devices.c
@@ -13,6 +13,7 @@
 #include <linux/init.h>
 #include <linux/platform_device.h>
 #include <linux/io.h>
+#include <linux/smc91x.h>
 
 #include <mach/hardware.h>
 
@@ -24,6 +25,12 @@
  * platforms include H2, H3, H4, and Perseus2.
  */
 
+static struct smc91x_platdata smc91x_info = {
+        .flags  = SMC91X_USE_16BIT | SMC91X_NOWAIT,
+        .leda   = RPC_LED_100_10,
+        .ledb   = RPC_LED_TX_RX,
+};
+
 static struct resource smc91x_resources[] = {
         [0] = {
                 .flags  = IORESOURCE_MEM,
@@ -36,6 +43,9 @@ static struct resource smc91x_resources[] = {
 static struct platform_device smc91x_device = {
         .name           = "smc91x",
         .id             = -1,
+        .dev            = {
+                .platform_data = &smc91x_info,
+        },
         .num_resources  = ARRAY_SIZE(smc91x_resources),
         .resource       = smc91x_resources,
 };
diff --git a/arch/arm/plat-omap/debug-leds.c b/arch/arm/plat-omap/debug-leds.c
index 6c768b71ad64..53fcef7c5201 100644
--- a/arch/arm/plat-omap/debug-leds.c
+++ b/arch/arm/plat-omap/debug-leds.c
@@ -293,7 +293,7 @@ static int fpga_resume_noirq(struct device *dev)
         return 0;
 }
 
-static struct dev_pm_ops fpga_dev_pm_ops = {
+static const struct dev_pm_ops fpga_dev_pm_ops = {
         .suspend_noirq = fpga_suspend_noirq,
         .resume_noirq = fpga_resume_noirq,
 };
diff --git a/arch/arm/plat-omap/devices.c b/arch/arm/plat-omap/devices.c
index f86617869b38..30b5db73017a 100644
--- a/arch/arm/plat-omap/devices.c
+++ b/arch/arm/plat-omap/devices.c
@@ -242,6 +242,39 @@ fail:
 
 /*-------------------------------------------------------------------------*/
 
+#if defined(CONFIG_HW_RANDOM_OMAP) || defined(CONFIG_HW_RANDOM_OMAP_MODULE)
+
+#ifdef CONFIG_ARCH_OMAP24XX
+#define OMAP_RNG_BASE           0x480A0000
+#else
+#define OMAP_RNG_BASE           0xfffe5000
+#endif
+
+static struct resource rng_resources[] = {
+        {
+                .start          = OMAP_RNG_BASE,
+                .end            = OMAP_RNG_BASE + 0x4f,
+                .flags          = IORESOURCE_MEM,
+        },
+};
+
+static struct platform_device omap_rng_device = {
+        .name           = "omap_rng",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(rng_resources),
+        .resource       = rng_resources,
+};
+
+static void omap_init_rng(void)
+{
+        (void) platform_device_register(&omap_rng_device);
+}
+#else
+static inline void omap_init_rng(void) {}
+#endif
+
+/*-------------------------------------------------------------------------*/
+
 /* Numbering for the SPI-capable controllers when used for SPI:
  * spi          = 1
  * uwire        = 2
@@ -324,39 +357,6 @@ static void omap_init_wdt(void)
 static inline void omap_init_wdt(void) {}
 #endif
 
-/*-------------------------------------------------------------------------*/
-
-#if defined(CONFIG_HW_RANDOM_OMAP) || defined(CONFIG_HW_RANDOM_OMAP_MODULE)
-
-#ifdef CONFIG_ARCH_OMAP24XX
-#define OMAP_RNG_BASE           0x480A0000
-#else
-#define OMAP_RNG_BASE           0xfffe5000
-#endif
-
-static struct resource rng_resources[] = {
-        {
-                .start          = OMAP_RNG_BASE,
-                .end            = OMAP_RNG_BASE + 0x4f,
-                .flags          = IORESOURCE_MEM,
-        },
-};
-
-static struct platform_device omap_rng_device = {
-        .name      = "omap_rng",
-        .id          = -1,
-        .num_resources  = ARRAY_SIZE(rng_resources),
-        .resource       = rng_resources,
-};
-
-static void omap_init_rng(void)
-{
-        (void) platform_device_register(&omap_rng_device);
-}
-#else
-static inline void omap_init_rng(void) {}
-#endif
-
 /*
  * This gets called after board-specific INIT_MACHINE, and initializes most
  * on-chip peripherals accessible on this board (except for few like USB):
@@ -384,9 +384,9 @@ static int __init omap_init_devices(void)
          */
         omap_init_dsp();
         omap_init_kp();
+        omap_init_rng();
         omap_init_uwire();
         omap_init_wdt();
-        omap_init_rng();
         return 0;
 }
 arch_initcall(omap_init_devices);
diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c
index d17375e06a1e..09d82b3c66ce 100644
--- a/arch/arm/plat-omap/dma.c
+++ b/arch/arm/plat-omap/dma.c
@@ -47,7 +47,6 @@ enum { DMA_CHAIN_STARTED, DMA_CHAIN_NOTSTARTED };
 #endif
 
 #define OMAP_DMA_ACTIVE                 0x01
-#define OMAP_DMA_CCR_EN                 (1 << 7)
 #define OMAP2_DMA_CSR_CLEAR_MASK        0xffe
 
 #define OMAP_FUNC_MUX_ARM_BASE          (0xfffe1000 + 0xec)
@@ -1120,17 +1119,8 @@ int omap_dma_running(void)
 {
         int lch;
 
-        /*
-         * On OMAP1510, internal LCD controller will start the transfer
-         * when it gets enabled, so assume DMA running if LCD enabled.
-         */
-        if (cpu_is_omap1510())
-                if (omap_readw(0xfffec000 + 0x00) & (1 << 0))
-                        return 1;
-
-        /* Check if LCD DMA is running */
-        if (cpu_is_omap16xx())
-                if (omap_readw(OMAP1610_DMA_LCD_CCR) & OMAP_DMA_CCR_EN)
+        if (cpu_class_is_omap1())
+                if (omap_lcd_dma_running())
                         return 1;
 
         for (lch = 0; lch < dma_chan_count; lch++)
@@ -1990,377 +1980,6 @@ static struct irqaction omap24xx_dma_irq;
 
 /*----------------------------------------------------------------------------*/
 
-static struct lcd_dma_info {
-        spinlock_t lock;
-        int reserved;
-        void (*callback)(u16 status, void *data);
-        void *cb_data;
-
-        int active;
-        unsigned long addr, size;
-        int rotate, data_type, xres, yres;
-        int vxres;
-        int mirror;
-        int xscale, yscale;
-        int ext_ctrl;
-        int src_port;
-        int single_transfer;
-} lcd_dma;
-
-void omap_set_lcd_dma_b1(unsigned long addr, u16 fb_xres, u16 fb_yres,
-                         int data_type)
-{
-        lcd_dma.addr = addr;
-        lcd_dma.data_type = data_type;
-        lcd_dma.xres = fb_xres;
-        lcd_dma.yres = fb_yres;
-}
-EXPORT_SYMBOL(omap_set_lcd_dma_b1);
-
-void omap_set_lcd_dma_src_port(int port)
-{
-        lcd_dma.src_port = port;
-}
-
-void omap_set_lcd_dma_ext_controller(int external)
-{
-        lcd_dma.ext_ctrl = external;
-}
-EXPORT_SYMBOL(omap_set_lcd_dma_ext_controller);
-
-void omap_set_lcd_dma_single_transfer(int single)
-{
-        lcd_dma.single_transfer = single;
-}
-EXPORT_SYMBOL(omap_set_lcd_dma_single_transfer);
-
-void omap_set_lcd_dma_b1_rotation(int rotate)
-{
-        if (omap_dma_in_1510_mode()) {
-                printk(KERN_ERR "DMA rotation is not supported in 1510 mode\n");
-                BUG();
-                return;
-        }
-        lcd_dma.rotate = rotate;
-}
-EXPORT_SYMBOL(omap_set_lcd_dma_b1_rotation);
-
-void omap_set_lcd_dma_b1_mirror(int mirror)
-{
-        if (omap_dma_in_1510_mode()) {
-                printk(KERN_ERR "DMA mirror is not supported in 1510 mode\n");
-                BUG();
-        }
-        lcd_dma.mirror = mirror;
-}
-EXPORT_SYMBOL(omap_set_lcd_dma_b1_mirror);
-
-void omap_set_lcd_dma_b1_vxres(unsigned long vxres)
-{
-        if (omap_dma_in_1510_mode()) {
-                printk(KERN_ERR "DMA virtual resulotion is not supported "
-                                "in 1510 mode\n");
-                BUG();
-        }
-        lcd_dma.vxres = vxres;
-}
-EXPORT_SYMBOL(omap_set_lcd_dma_b1_vxres);
-
-void omap_set_lcd_dma_b1_scale(unsigned int xscale, unsigned int yscale)
-{
-        if (omap_dma_in_1510_mode()) {
-                printk(KERN_ERR "DMA scale is not supported in 1510 mode\n");
-                BUG();
-        }
-        lcd_dma.xscale = xscale;
-        lcd_dma.yscale = yscale;
-}
-EXPORT_SYMBOL(omap_set_lcd_dma_b1_scale);
-
-static void set_b1_regs(void)
-{
-        unsigned long top, bottom;
-        int es;
-        u16 w;
-        unsigned long en, fn;
-        long ei, fi;
-        unsigned long vxres;
-        unsigned int xscale, yscale;
-
-        switch (lcd_dma.data_type) {
-        case OMAP_DMA_DATA_TYPE_S8:
-                es = 1;
-                break;
-        case OMAP_DMA_DATA_TYPE_S16:
-                es = 2;
-                break;
-        case OMAP_DMA_DATA_TYPE_S32:
-                es = 4;
-                break;
-        default:
-                BUG();
-                return;
-        }
-
-        vxres = lcd_dma.vxres ? lcd_dma.vxres : lcd_dma.xres;
-        xscale = lcd_dma.xscale ? lcd_dma.xscale : 1;
-        yscale = lcd_dma.yscale ? lcd_dma.yscale : 1;
-        BUG_ON(vxres < lcd_dma.xres);
-
-#define PIXADDR(x, y) (lcd_dma.addr +                                   \
-                ((y) * vxres * yscale + (x) * xscale) * es)
-#define PIXSTEP(sx, sy, dx, dy) (PIXADDR(dx, dy) - PIXADDR(sx, sy) - es + 1)
-
-        switch (lcd_dma.rotate) {
-        case 0:
-                if (!lcd_dma.mirror) {
-                        top = PIXADDR(0, 0);
-                        bottom = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1);
-                        /* 1510 DMA requires the bottom address to be 2 more
-                         * than the actual last memory access location. */
-                        if (omap_dma_in_1510_mode() &&
-                                lcd_dma.data_type == OMAP_DMA_DATA_TYPE_S32)
-                                        bottom += 2;
-                        ei = PIXSTEP(0, 0, 1, 0);
-                        fi = PIXSTEP(lcd_dma.xres - 1, 0, 0, 1);
-                } else {
-                        top = PIXADDR(lcd_dma.xres - 1, 0);
-                        bottom = PIXADDR(0, lcd_dma.yres - 1);
-                        ei = PIXSTEP(1, 0, 0, 0);
-                        fi = PIXSTEP(0, 0, lcd_dma.xres - 1, 1);
-                }
-                en = lcd_dma.xres;
-                fn = lcd_dma.yres;
-                break;
-        case 90:
-                if (!lcd_dma.mirror) {
-                        top = PIXADDR(0, lcd_dma.yres - 1);
-                        bottom = PIXADDR(lcd_dma.xres - 1, 0);
-                        ei = PIXSTEP(0, 1, 0, 0);
-                        fi = PIXSTEP(0, 0, 1, lcd_dma.yres - 1);
-                } else {
-                        top = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1);
-                        bottom = PIXADDR(0, 0);
-                        ei = PIXSTEP(0, 1, 0, 0);
-                        fi = PIXSTEP(1, 0, 0, lcd_dma.yres - 1);
-                }
-                en = lcd_dma.yres;
-                fn = lcd_dma.xres;
-                break;
-        case 180:
-                if (!lcd_dma.mirror) {
-                        top = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1);
-                        bottom = PIXADDR(0, 0);
-                        ei = PIXSTEP(1, 0, 0, 0);
-                        fi = PIXSTEP(0, 1, lcd_dma.xres - 1, 0);
-                } else {
-                        top = PIXADDR(0, lcd_dma.yres - 1);
-                        bottom = PIXADDR(lcd_dma.xres - 1, 0);
-                        ei = PIXSTEP(0, 0, 1, 0);
-                        fi = PIXSTEP(lcd_dma.xres - 1, 1, 0, 0);
-                }
-                en = lcd_dma.xres;
-                fn = lcd_dma.yres;
-                break;
-        case 270:
-                if (!lcd_dma.mirror) {
-                        top = PIXADDR(lcd_dma.xres - 1, 0);
-                        bottom = PIXADDR(0, lcd_dma.yres - 1);
-                        ei = PIXSTEP(0, 0, 0, 1);
-                        fi = PIXSTEP(1, lcd_dma.yres - 1, 0, 0);
-                } else {
-                        top = PIXADDR(0, 0);
-                        bottom = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1);
-                        ei = PIXSTEP(0, 0, 0, 1);
-                        fi = PIXSTEP(0, lcd_dma.yres - 1, 1, 0);
-                }
-                en = lcd_dma.yres;
-                fn = lcd_dma.xres;
-                break;
-        default:
-                BUG();
-                return; /* Suppress warning about uninitialized vars */
-        }
-
-        if (omap_dma_in_1510_mode()) {
-                omap_writew(top >> 16, OMAP1510_DMA_LCD_TOP_F1_U);
-                omap_writew(top, OMAP1510_DMA_LCD_TOP_F1_L);
-                omap_writew(bottom >> 16, OMAP1510_DMA_LCD_BOT_F1_U);
-                omap_writew(bottom, OMAP1510_DMA_LCD_BOT_F1_L);
-
-                return;
-        }
-
-        /* 1610 regs */
-        omap_writew(top >> 16, OMAP1610_DMA_LCD_TOP_B1_U);
-        omap_writew(top, OMAP1610_DMA_LCD_TOP_B1_L);
-        omap_writew(bottom >> 16, OMAP1610_DMA_LCD_BOT_B1_U);
-        omap_writew(bottom, OMAP1610_DMA_LCD_BOT_B1_L);
-
-        omap_writew(en, OMAP1610_DMA_LCD_SRC_EN_B1);
-        omap_writew(fn, OMAP1610_DMA_LCD_SRC_FN_B1);
-
-        w = omap_readw(OMAP1610_DMA_LCD_CSDP);
-        w &= ~0x03;
-        w |= lcd_dma.data_type;
-        omap_writew(w, OMAP1610_DMA_LCD_CSDP);
-
-        w = omap_readw(OMAP1610_DMA_LCD_CTRL);
-        /* Always set the source port as SDRAM for now*/
-        w &= ~(0x03 << 6);
-        if (lcd_dma.callback != NULL)
-                w |= 1 << 1;            /* Block interrupt enable */
-        else
-                w &= ~(1 << 1);
-        omap_writew(w, OMAP1610_DMA_LCD_CTRL);
-
-        if (!(lcd_dma.rotate || lcd_dma.mirror ||
-              lcd_dma.vxres || lcd_dma.xscale || lcd_dma.yscale))
-                return;
-
-        w = omap_readw(OMAP1610_DMA_LCD_CCR);
-        /* Set the double-indexed addressing mode */
-        w |= (0x03 << 12);
-        omap_writew(w, OMAP1610_DMA_LCD_CCR);
-
-        omap_writew(ei, OMAP1610_DMA_LCD_SRC_EI_B1);
-        omap_writew(fi >> 16, OMAP1610_DMA_LCD_SRC_FI_B1_U);
-        omap_writew(fi, OMAP1610_DMA_LCD_SRC_FI_B1_L);
-}
-
-static irqreturn_t lcd_dma_irq_handler(int irq, void *dev_id)
-{
-        u16 w;
-
-        w = omap_readw(OMAP1610_DMA_LCD_CTRL);
-        if (unlikely(!(w & (1 << 3)))) {
-                printk(KERN_WARNING "Spurious LCD DMA IRQ\n");
-                return IRQ_NONE;
-        }
-        /* Ack the IRQ */
-        w |= (1 << 3);
-        omap_writew(w, OMAP1610_DMA_LCD_CTRL);
-        lcd_dma.active = 0;
-        if (lcd_dma.callback != NULL)
-                lcd_dma.callback(w, lcd_dma.cb_data);
-
-        return IRQ_HANDLED;
-}
-
-int omap_request_lcd_dma(void (*callback)(u16 status, void *data),
-                         void *data)
-{
-        spin_lock_irq(&lcd_dma.lock);
-        if (lcd_dma.reserved) {
-                spin_unlock_irq(&lcd_dma.lock);
-                printk(KERN_ERR "LCD DMA channel already reserved\n");
-                BUG();
-                return -EBUSY;
-        }
-        lcd_dma.reserved = 1;
-        spin_unlock_irq(&lcd_dma.lock);
-        lcd_dma.callback = callback;
-        lcd_dma.cb_data = data;
-        lcd_dma.active = 0;
-        lcd_dma.single_transfer = 0;
-        lcd_dma.rotate = 0;
-        lcd_dma.vxres = 0;
-        lcd_dma.mirror = 0;
-        lcd_dma.xscale = 0;
-        lcd_dma.yscale = 0;
-        lcd_dma.ext_ctrl = 0;
-        lcd_dma.src_port = 0;
-
-        return 0;
-}
-EXPORT_SYMBOL(omap_request_lcd_dma);
-
-void omap_free_lcd_dma(void)
-{
-        spin_lock(&lcd_dma.lock);
-        if (!lcd_dma.reserved) {
-                spin_unlock(&lcd_dma.lock);
-                printk(KERN_ERR "LCD DMA is not reserved\n");
-                BUG();
-                return;
-        }
-        if (!enable_1510_mode)
-                omap_writew(omap_readw(OMAP1610_DMA_LCD_CCR) & ~1,
-                            OMAP1610_DMA_LCD_CCR);
-        lcd_dma.reserved = 0;
-        spin_unlock(&lcd_dma.lock);
-}
-EXPORT_SYMBOL(omap_free_lcd_dma);
-
-void omap_enable_lcd_dma(void)
-{
-        u16 w;
-
-        /*
-         * Set the Enable bit only if an external controller is
-         * connected. Otherwise the OMAP internal controller will
-         * start the transfer when it gets enabled.
-         */
-        if (enable_1510_mode || !lcd_dma.ext_ctrl)
-                return;
-
-        w = omap_readw(OMAP1610_DMA_LCD_CTRL);
-        w |= 1 << 8;
-        omap_writew(w, OMAP1610_DMA_LCD_CTRL);
-
-        lcd_dma.active = 1;
-
-        w = omap_readw(OMAP1610_DMA_LCD_CCR);
-        w |= 1 << 7;
-        omap_writew(w, OMAP1610_DMA_LCD_CCR);
-}
-EXPORT_SYMBOL(omap_enable_lcd_dma);
-
-void omap_setup_lcd_dma(void)
-{
-        BUG_ON(lcd_dma.active);
-        if (!enable_1510_mode) {
-                /* Set some reasonable defaults */
-                omap_writew(0x5440, OMAP1610_DMA_LCD_CCR);
-                omap_writew(0x9102, OMAP1610_DMA_LCD_CSDP);
-                omap_writew(0x0004, OMAP1610_DMA_LCD_LCH_CTRL);
-        }
-        set_b1_regs();
-        if (!enable_1510_mode) {
-                u16 w;
-
-                w = omap_readw(OMAP1610_DMA_LCD_CCR);
-                /*
-                 * If DMA was already active set the end_prog bit to have
-                 * the programmed register set loaded into the active
-                 * register set.
-                 */
-                w |= 1 << 11;           /* End_prog */
-                if (!lcd_dma.single_transfer)
-                        w |= (3 << 8);  /* Auto_init, repeat */
-                omap_writew(w, OMAP1610_DMA_LCD_CCR);
-        }
-}
-EXPORT_SYMBOL(omap_setup_lcd_dma);
-
-void omap_stop_lcd_dma(void)
-{
-        u16 w;
-
-        lcd_dma.active = 0;
-        if (enable_1510_mode || !lcd_dma.ext_ctrl)
-                return;
-
-        w = omap_readw(OMAP1610_DMA_LCD_CCR);
-        w &= ~(1 << 7);
-        omap_writew(w, OMAP1610_DMA_LCD_CCR);
-
-        w = omap_readw(OMAP1610_DMA_LCD_CTRL);
-        w &= ~(1 << 8);
-        omap_writew(w, OMAP1610_DMA_LCD_CTRL);
-}
-EXPORT_SYMBOL(omap_stop_lcd_dma);
-
 void omap_dma_global_context_save(void)
 {
         omap_dma_global_context.dma_irqenable_l0 =
@@ -2465,14 +2084,6 @@ static int __init omap_init_dma(void)
                         dma_chan_count = 16;
                 } else
                         dma_chan_count = 9;
-                if (cpu_is_omap16xx()) {
-                        u16 w;
-
-                        /* this would prevent OMAP sleep */
-                        w = omap_readw(OMAP1610_DMA_LCD_CTRL);
-                        w &= ~(1 << 8);
-                        omap_writew(w, OMAP1610_DMA_LCD_CTRL);
-                }
         } else if (cpu_class_is_omap2()) {
                 u8 revision = dma_read(REVISION) & 0xff;
                 printk(KERN_INFO "OMAP DMA hardware revision %d.%d\n",
@@ -2483,7 +2094,6 @@ static int __init omap_init_dma(void)
                 return 0;
         }
 
-        spin_lock_init(&lcd_dma.lock);
         spin_lock_init(&dma_chan_lock);
 
         for (ch = 0; ch < dma_chan_count; ch++) {
@@ -2548,22 +2158,6 @@ static int __init omap_init_dma(void)
                 }
         }
 
-
-        /* FIXME: Update LCD DMA to work on 24xx */
-        if (cpu_class_is_omap1()) {
-                r = request_irq(INT_DMA_LCD, lcd_dma_irq_handler, 0,
-                                "LCD DMA", NULL);
-                if (r != 0) {
-                        int i;
-
-                        printk(KERN_ERR "unable to request IRQ for LCD DMA "
-                               "(error %d)\n", r);
-                        for (i = 0; i < dma_chan_count; i++)
-                                free_irq(omap1_dma_irq[i], (void *) (i + 1));
-                        goto out_free;
-                }
-        }
-
         return 0;
 
 out_free:
diff --git a/arch/arm/plat-omap/gpio.c b/arch/arm/plat-omap/gpio.c
index 055160e0620e..04846811d0aa 100644
--- a/arch/arm/plat-omap/gpio.c
+++ b/arch/arm/plat-omap/gpio.c
@@ -1431,7 +1431,7 @@ static int omap_mpuio_resume_noirq(struct device *dev)
         return 0;
 }
 
-static struct dev_pm_ops omap_mpuio_dev_pm_ops = {
+static const struct dev_pm_ops omap_mpuio_dev_pm_ops = {
         .suspend_noirq = omap_mpuio_suspend_noirq,
         .resume_noirq = omap_mpuio_resume_noirq,
 };
diff --git a/arch/arm/plat-omap/i2c.c b/arch/arm/plat-omap/i2c.c
index c08362dbb8ed..33fff4ef382d 100644
--- a/arch/arm/plat-omap/i2c.c
+++ b/arch/arm/plat-omap/i2c.c
@@ -80,47 +80,8 @@ static struct platform_device omap_i2c_devices[] = {
 #endif
 };
 
-#if defined(CONFIG_ARCH_OMAP24XX)
-static const int omap24xx_pins[][2] = {
-        { M19_24XX_I2C1_SCL, L15_24XX_I2C1_SDA },
-        { J15_24XX_I2C2_SCL, H19_24XX_I2C2_SDA },
-};
-#else
-static const int omap24xx_pins[][2] = {};
-#endif
-#if defined(CONFIG_ARCH_OMAP34XX)
-static const int omap34xx_pins[][2] = {
-        { K21_34XX_I2C1_SCL, J21_34XX_I2C1_SDA},
-        { AF15_34XX_I2C2_SCL, AE15_34XX_I2C2_SDA},
-        { AF14_34XX_I2C3_SCL, AG14_34XX_I2C3_SDA},
-};
-#else
-static const int omap34xx_pins[][2] = {};
-#endif
-
 #define OMAP_I2C_CMDLINE_SETUP  (BIT(31))
 
-static void __init omap_i2c_mux_pins(int bus)
-{
-        int scl, sda;
-
-        if (cpu_class_is_omap1()) {
-                scl = I2C_SCL;
-                sda = I2C_SDA;
-        } else if (cpu_is_omap24xx()) {
-                scl = omap24xx_pins[bus][0];
-                sda = omap24xx_pins[bus][1];
-        } else if (cpu_is_omap34xx()) {
-                scl = omap34xx_pins[bus][0];
-                sda = omap34xx_pins[bus][1];
-        } else {
-                return;
-        }
-
-        omap_cfg_reg(sda);
-        omap_cfg_reg(scl);
-}
-
 static int __init omap_i2c_nr_ports(void)
 {
         int ports = 0;
@@ -156,7 +117,6 @@ static int __init omap_i2c_add_bus(int bus_id)
                 res[1].start = irq;
         }
 
-        omap_i2c_mux_pins(bus_id - 1);
         return platform_device_register(pdev);
 }
 
@@ -209,7 +169,7 @@ out:
 subsys_initcall(omap_register_i2c_bus_cmdline);
 
 /**
- * omap_register_i2c_bus - register I2C bus with device descriptors
+ * omap_plat_register_i2c_bus - register I2C bus with device descriptors
  * @bus_id: bus id counting from number 1
  * @clkrate: clock rate of the bus in kHz
  * @info: pointer into I2C device descriptor table or NULL
@@ -217,7 +177,7 @@ subsys_initcall(omap_register_i2c_bus_cmdline);
  *
  * Returns 0 on success or an error code.
  */
-int __init omap_register_i2c_bus(int bus_id, u32 clkrate,
+int __init omap_plat_register_i2c_bus(int bus_id, u32 clkrate,
                           struct i2c_board_info const *info,
                           unsigned len)
 {
diff --git a/arch/arm/plat-omap/include/plat/board.h b/arch/arm/plat-omap/include/plat/board.h
index abb17b604f82..376ce18216ff 100644
--- a/arch/arm/plat-omap/include/plat/board.h
+++ b/arch/arm/plat-omap/include/plat/board.h
@@ -114,15 +114,6 @@ struct omap_pwm_led_platform_data {
         void (*set_power)(struct omap_pwm_led_platform_data *self, int on_off);
 };
 
-/* See arch/arm/plat-omap/include/mach/gpio-switch.h for definitions */
-struct omap_gpio_switch_config {
-        char name[12];
-        u16 gpio;
-        int flags:4;
-        int type:4;
-        int key_code:24; /* Linux key code */
-};
-
 struct omap_uart_config {
         /* Bit field of UARTs present; bit 0 --> UART1 */
         unsigned int enabled_uarts;
diff --git a/arch/arm/plat-omap/include/plat/clkdev_omap.h b/arch/arm/plat-omap/include/plat/clkdev_omap.h
new file mode 100644
index 000000000000..35b36caf5f91
--- /dev/null
+++ b/arch/arm/plat-omap/include/plat/clkdev_omap.h
@@ -0,0 +1,41 @@
+/*
+ * clkdev <-> OMAP integration
+ *
+ * Russell King <linux@arm.linux.org.uk>
+ *
+ */
+
+#ifndef __ARCH_ARM_PLAT_OMAP_INCLUDE_PLAT_CLKDEV_OMAP_H
+#define __ARCH_ARM_PLAT_OMAP_INCLUDE_PLAT_CLKDEV_OMAP_H
+
+#include <asm/clkdev.h>
+
+struct omap_clk {
+        u16                             cpu;
+        struct clk_lookup               lk;
+};
+
+#define CLK(dev, con, ck, cp)           \
+        {                               \
+                 .cpu = cp,             \
+                .lk = {                 \
+                        .dev_id = dev,  \
+                        .con_id = con,  \
+                        .clk = ck,      \
+                },                      \
+        }
+
+
+#define CK_310          (1 << 0)
+#define CK_7XX          (1 << 1)
+#define CK_1510         (1 << 2)
+#define CK_16XX         (1 << 3)
+#define CK_243X         (1 << 4)
+#define CK_242X         (1 << 5)
+#define CK_343X         (1 << 6)
+#define CK_3430ES1      (1 << 7)
+#define CK_3430ES2      (1 << 8)
+#define CK_443X         (1 << 9)
+
+#endif
+
diff --git a/arch/arm/plat-omap/include/plat/clock.h b/arch/arm/plat-omap/include/plat/clock.h
index 4b8b0d65cbf2..309b6d1dccdb 100644
--- a/arch/arm/plat-omap/include/plat/clock.h
+++ b/arch/arm/plat-omap/include/plat/clock.h
@@ -13,6 +13,8 @@
 #ifndef __ARCH_ARM_OMAP_CLOCK_H
 #define __ARCH_ARM_OMAP_CLOCK_H
 
+#include <linux/list.h>
+
 struct module;
 struct clk;
 struct clockdomain;
@@ -148,6 +150,8 @@ extern const struct clkops clkops_null;
 #define CONFIG_PARTICIPANT      (1 << 10)       /* Fundamental clock */
 #define ENABLE_ON_INIT          (1 << 11)       /* Enable upon framework init */
 #define INVERT_ENABLE           (1 << 12)       /* 0 enables, 1 disables */
+#define CLOCK_IN_OMAP4430       (1 << 13)
+#define ALWAYS_ENABLED          (1 << 14)
 /* bits 13-31 are currently free */
 
 /* Clksel_rate flags */
@@ -156,6 +160,7 @@ extern const struct clkops clkops_null;
 #define RATE_IN_243X            (1 << 2)
 #define RATE_IN_343X            (1 << 3)        /* rates common to all 343X */
 #define RATE_IN_3430ES2         (1 << 4)        /* 3430ES2 rates only */
+#define RATE_IN_4430            (1 << 5)
 
 #define RATE_IN_24XX            (RATE_IN_242X | RATE_IN_243X)
 
diff --git a/arch/arm/plat-omap/include/plat/common.h b/arch/arm/plat-omap/include/plat/common.h
index 064f1730f43b..32c22272425d 100644
--- a/arch/arm/plat-omap/include/plat/common.h
+++ b/arch/arm/plat-omap/include/plat/common.h
@@ -27,7 +27,7 @@
 #ifndef __ARCH_ARM_MACH_OMAP_COMMON_H
 #define __ARCH_ARM_MACH_OMAP_COMMON_H
 
-#include <linux/i2c.h>
+#include <plat/i2c.h>
 
 struct sys_timer;
 
@@ -36,18 +36,6 @@ extern void __iomem *gic_cpu_base_addr;
 
 extern void omap_map_common_io(void);
 extern struct sys_timer omap_timer;
-#if defined(CONFIG_I2C_OMAP) || defined(CONFIG_I2C_OMAP_MODULE)
-extern int omap_register_i2c_bus(int bus_id, u32 clkrate,
-                                 struct i2c_board_info const *info,
-                                 unsigned len);
-#else
-static inline int omap_register_i2c_bus(int bus_id, u32 clkrate,
-                                 struct i2c_board_info const *info,
-                                 unsigned len)
-{
-        return 0;
-}
-#endif
 
 /* IO bases for various OMAP processors */
 struct omap_globals {
@@ -58,6 +46,7 @@ struct omap_globals {
         void __iomem    *ctrl;          /* System Control Module */
         void __iomem    *prm;           /* Power and Reset Management */
         void __iomem    *cm;            /* Clock Management */
+        void __iomem    *cm2;
 };
 
 void omap2_set_globals_242x(void);
@@ -71,4 +60,24 @@ void omap2_set_globals_sdrc(struct omap_globals *);
 void omap2_set_globals_control(struct omap_globals *);
 void omap2_set_globals_prcm(struct omap_globals *);
 
+/**
+ * omap_test_timeout - busy-loop, testing a condition
+ * @cond: condition to test until it evaluates to true
+ * @timeout: maximum number of microseconds in the timeout
+ * @index: loop index (integer)
+ *
+ * Loop waiting for @cond to become true or until at least @timeout
+ * microseconds have passed.  To use, define some integer @index in the
+ * calling code.  After running, if @index == @timeout, then the loop has
+ * timed out.
+ */
+#define omap_test_timeout(cond, timeout, index)                 \
+({                                                              \
+        for (index = 0; index < timeout; index++) {             \
+                if (cond)                                       \
+                        break;                                  \
+                udelay(1);                                      \
+        }                                                       \
+})
+
 #endif /* __ARCH_ARM_MACH_OMAP_COMMON_H */
diff --git a/arch/arm/plat-omap/include/plat/cpu.h b/arch/arm/plat-omap/include/plat/cpu.h
index 2e1789001dfe..9a028bdebb06 100644
--- a/arch/arm/plat-omap/include/plat/cpu.h
+++ b/arch/arm/plat-omap/include/plat/cpu.h
@@ -176,11 +176,13 @@ IS_OMAP_CLASS(15xx, 0x15)
 IS_OMAP_CLASS(16xx, 0x16)
 IS_OMAP_CLASS(24xx, 0x24)
 IS_OMAP_CLASS(34xx, 0x34)
+IS_OMAP_CLASS(44xx, 0x44)
 
 IS_OMAP_SUBCLASS(242x, 0x242)
 IS_OMAP_SUBCLASS(243x, 0x243)
 IS_OMAP_SUBCLASS(343x, 0x343)
 IS_OMAP_SUBCLASS(363x, 0x363)
+IS_OMAP_SUBCLASS(443x, 0x443)
 
 #define cpu_is_omap7xx()                0
 #define cpu_is_omap15xx()               0
@@ -393,11 +395,11 @@ IS_OMAP_TYPE(3517, 0x3517)
                                                 (!omap3_has_iva()) &&   \
                                                 (!omap3_has_sgx()))
 # define cpu_is_omap3515()              (cpu_is_omap3430() &&           \
-                                                (omap3_has_iva()) &&    \
-                                                (!omap3_has_sgx()))
+                                                (!omap3_has_iva()) &&   \
+                                                (omap3_has_sgx()))
 # define cpu_is_omap3525()              (cpu_is_omap3430() &&           \
-                                                (omap3_has_sgx()) &&    \
-                                                (!omap3_has_iva()))
+                                                (!omap3_has_sgx()) &&   \
+                                                (omap3_has_iva()))
 # define cpu_is_omap3530()              (cpu_is_omap3430())
 # define cpu_is_omap3505()              is_omap3505()
 # define cpu_is_omap3517()              is_omap3517()
@@ -408,8 +410,8 @@ IS_OMAP_TYPE(3517, 0x3517)
 # if defined(CONFIG_ARCH_OMAP4)
 # undef cpu_is_omap44xx
 # undef cpu_is_omap443x
-# define cpu_is_omap44xx()              1
-# define cpu_is_omap443x()              1
+# define cpu_is_omap44xx()              is_omap44xx()
+# define cpu_is_omap443x()              is_omap443x()
 # endif
 
 /* Macros to detect if we have OMAP1 or OMAP2 */
@@ -436,14 +438,15 @@ IS_OMAP_TYPE(3517, 0x3517)
 #define OMAP3630_REV_ES1_0      0x36300034
 
 #define OMAP35XX_CLASS          0x35000034
-#define OMAP3503_REV(v)         (OMAP35XX_CLASS | (0x3503 << 16) | (v << 12))
-#define OMAP3515_REV(v)         (OMAP35XX_CLASS | (0x3515 << 16) | (v << 12))
-#define OMAP3525_REV(v)         (OMAP35XX_CLASS | (0x3525 << 16) | (v << 12))
-#define OMAP3530_REV(v)         (OMAP35XX_CLASS | (0x3530 << 16) | (v << 12))
-#define OMAP3505_REV(v)         (OMAP35XX_CLASS | (0x3505 << 16) | (v << 12))
-#define OMAP3517_REV(v)         (OMAP35XX_CLASS | (0x3517 << 16) | (v << 12))
-
-#define OMAP443X_CLASS          0x44300034
+#define OMAP3503_REV(v)         (OMAP35XX_CLASS | (0x3503 << 16) | (v << 8))
+#define OMAP3515_REV(v)         (OMAP35XX_CLASS | (0x3515 << 16) | (v << 8))
+#define OMAP3525_REV(v)         (OMAP35XX_CLASS | (0x3525 << 16) | (v << 8))
+#define OMAP3530_REV(v)         (OMAP35XX_CLASS | (0x3530 << 16) | (v << 8))
+#define OMAP3505_REV(v)         (OMAP35XX_CLASS | (0x3505 << 16) | (v << 8))
+#define OMAP3517_REV(v)         (OMAP35XX_CLASS | (0x3517 << 16) | (v << 8))
+
+#define OMAP443X_CLASS          0x44300044
+#define OMAP4430_REV_ES1_0      0x44300044
 
 /*
  * omap_chip bits
diff --git a/arch/arm/plat-omap/include/plat/dma.h b/arch/arm/plat-omap/include/plat/dma.h
index 1c017b29b7e9..4ede9e17a0be 100644
--- a/arch/arm/plat-omap/include/plat/dma.h
+++ b/arch/arm/plat-omap/include/plat/dma.h
@@ -401,33 +401,6 @@
 
 /*----------------------------------------------------------------------------*/
 
-/* Hardware registers for LCD DMA */
-#define OMAP1510_DMA_LCD_BASE           (0xfffedb00)
-#define OMAP1510_DMA_LCD_CTRL           (OMAP1510_DMA_LCD_BASE + 0x00)
-#define OMAP1510_DMA_LCD_TOP_F1_L       (OMAP1510_DMA_LCD_BASE + 0x02)
-#define OMAP1510_DMA_LCD_TOP_F1_U       (OMAP1510_DMA_LCD_BASE + 0x04)
-#define OMAP1510_DMA_LCD_BOT_F1_L       (OMAP1510_DMA_LCD_BASE + 0x06)
-#define OMAP1510_DMA_LCD_BOT_F1_U       (OMAP1510_DMA_LCD_BASE + 0x08)
-
-#define OMAP1610_DMA_LCD_BASE           (0xfffee300)
-#define OMAP1610_DMA_LCD_CSDP           (OMAP1610_DMA_LCD_BASE + 0xc0)
-#define OMAP1610_DMA_LCD_CCR            (OMAP1610_DMA_LCD_BASE + 0xc2)
-#define OMAP1610_DMA_LCD_CTRL           (OMAP1610_DMA_LCD_BASE + 0xc4)
-#define OMAP1610_DMA_LCD_TOP_B1_L       (OMAP1610_DMA_LCD_BASE + 0xc8)
-#define OMAP1610_DMA_LCD_TOP_B1_U       (OMAP1610_DMA_LCD_BASE + 0xca)
-#define OMAP1610_DMA_LCD_BOT_B1_L       (OMAP1610_DMA_LCD_BASE + 0xcc)
-#define OMAP1610_DMA_LCD_BOT_B1_U       (OMAP1610_DMA_LCD_BASE + 0xce)
-#define OMAP1610_DMA_LCD_TOP_B2_L       (OMAP1610_DMA_LCD_BASE + 0xd0)
-#define OMAP1610_DMA_LCD_TOP_B2_U       (OMAP1610_DMA_LCD_BASE + 0xd2)
-#define OMAP1610_DMA_LCD_BOT_B2_L       (OMAP1610_DMA_LCD_BASE + 0xd4)
-#define OMAP1610_DMA_LCD_BOT_B2_U       (OMAP1610_DMA_LCD_BASE + 0xd6)
-#define OMAP1610_DMA_LCD_SRC_EI_B1      (OMAP1610_DMA_LCD_BASE + 0xd8)
-#define OMAP1610_DMA_LCD_SRC_FI_B1_L    (OMAP1610_DMA_LCD_BASE + 0xda)
-#define OMAP1610_DMA_LCD_SRC_EN_B1      (OMAP1610_DMA_LCD_BASE + 0xe0)
-#define OMAP1610_DMA_LCD_SRC_FN_B1      (OMAP1610_DMA_LCD_BASE + 0xe4)
-#define OMAP1610_DMA_LCD_LCH_CTRL       (OMAP1610_DMA_LCD_BASE + 0xea)
-#define OMAP1610_DMA_LCD_SRC_FI_B1_U    (OMAP1610_DMA_LCD_BASE + 0xf4)
-
 #define OMAP1_DMA_TOUT_IRQ              (1 << 0)
 #define OMAP_DMA_DROP_IRQ               (1 << 1)
 #define OMAP_DMA_HALF_IRQ               (1 << 2)
@@ -441,6 +414,8 @@
 #define OMAP2_DMA_SUPERVISOR_ERR_IRQ    (1 << 10)
 #define OMAP2_DMA_MISALIGNED_ERR_IRQ    (1 << 11)
 
+#define OMAP_DMA_CCR_EN                 (1 << 7)
+
 #define OMAP_DMA_DATA_TYPE_S8           0x00
 #define OMAP_DMA_DATA_TYPE_S16          0x01
 #define OMAP_DMA_DATA_TYPE_S32          0x02
@@ -503,14 +478,6 @@
 #define DMA_CH_PRIO_HIGH                0x1
 #define DMA_CH_PRIO_LOW                 0x0 /* Def */
 
-/* LCD DMA block numbers */
-enum {
-        OMAP_LCD_DMA_B1_TOP,
-        OMAP_LCD_DMA_B1_BOTTOM,
-        OMAP_LCD_DMA_B2_TOP,
-        OMAP_LCD_DMA_B2_BOTTOM
-};
-
 enum omap_dma_burst_mode {
         OMAP_DMA_DATA_BURST_DIS = 0,
         OMAP_DMA_DATA_BURST_4,
@@ -661,20 +628,13 @@ extern int omap_modify_dma_chain_params(int chain_id,
 extern int omap_dma_chain_status(int chain_id);
 #endif
 
-/* LCD DMA functions */
-extern int omap_request_lcd_dma(void (*callback)(u16 status, void *data),
-                                void *data);
-extern void omap_free_lcd_dma(void);
-extern void omap_setup_lcd_dma(void);
-extern void omap_enable_lcd_dma(void);
-extern void omap_stop_lcd_dma(void);
-extern void omap_set_lcd_dma_ext_controller(int external);
-extern void omap_set_lcd_dma_single_transfer(int single);
-extern void omap_set_lcd_dma_b1(unsigned long addr, u16 fb_xres, u16 fb_yres,
-                                int data_type);
-extern void omap_set_lcd_dma_b1_rotation(int rotate);
-extern void omap_set_lcd_dma_b1_vxres(unsigned long vxres);
-extern void omap_set_lcd_dma_b1_mirror(int mirror);
-extern void omap_set_lcd_dma_b1_scale(unsigned int xscale, unsigned int yscale);
+#if defined(CONFIG_ARCH_OMAP1) && defined(CONFIG_FB_OMAP)
+#include <mach/lcd_dma.h>
+#else
+static inline int omap_lcd_dma_running(void)
+{
+        return 0;
+}
+#endif
 
 #endif /* __ASM_ARCH_DMA_H */
diff --git a/arch/arm/plat-omap/include/plat/gpmc.h b/arch/arm/plat-omap/include/plat/gpmc.h
index 696e0ca051b7..e081338e0b23 100644
--- a/arch/arm/plat-omap/include/plat/gpmc.h
+++ b/arch/arm/plat-omap/include/plat/gpmc.h
@@ -45,7 +45,7 @@
 #define GPMC_CONFIG1_DEVICESIZE_16      GPMC_CONFIG1_DEVICESIZE(1)
 #define GPMC_CONFIG1_DEVICETYPE(val)    ((val & 3) << 10)
 #define GPMC_CONFIG1_DEVICETYPE_NOR     GPMC_CONFIG1_DEVICETYPE(0)
-#define GPMC_CONFIG1_DEVICETYPE_NAND    GPMC_CONFIG1_DEVICETYPE(1)
+#define GPMC_CONFIG1_DEVICETYPE_NAND    GPMC_CONFIG1_DEVICETYPE(2)
 #define GPMC_CONFIG1_MUXADDDATA         (1 << 9)
 #define GPMC_CONFIG1_TIME_PARA_GRAN     (1 << 4)
 #define GPMC_CONFIG1_FCLK_DIV(val)      (val & 3)
diff --git a/arch/arm/plat-omap/include/plat/i2c.h b/arch/arm/plat-omap/include/plat/i2c.h
new file mode 100644
index 000000000000..585d9ca68b97
--- /dev/null
+++ b/arch/arm/plat-omap/include/plat/i2c.h
@@ -0,0 +1,39 @@
+/*
+ * Helper module for board specific I2C bus registration
+ *
+ * Copyright (C) 2009 Nokia Corporation.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
+ * 02110-1301 USA
+ *
+ */
+
+#include <linux/i2c.h>
+
+#if defined(CONFIG_I2C_OMAP) || defined(CONFIG_I2C_OMAP_MODULE)
+extern int omap_register_i2c_bus(int bus_id, u32 clkrate,
+                                 struct i2c_board_info const *info,
+                                 unsigned len);
+#else
+static inline int omap_register_i2c_bus(int bus_id, u32 clkrate,
+                                 struct i2c_board_info const *info,
+                                 unsigned len)
+{
+        return 0;
+}
+#endif
+
+int omap_plat_register_i2c_bus(int bus_id, u32 clkrate,
+                                 struct i2c_board_info const *info,
+                                 unsigned len);
diff --git a/arch/arm/plat-omap/include/plat/irqs.h b/arch/arm/plat-omap/include/plat/irqs.h
index ce5dd2d1dc21..97d6c50c3dcb 100644
--- a/arch/arm/plat-omap/include/plat/irqs.h
+++ b/arch/arm/plat-omap/include/plat/irqs.h
@@ -472,8 +472,22 @@
 #endif
 #define TWL4030_GPIO_IRQ_END    (TWL4030_GPIO_IRQ_BASE + TWL4030_GPIO_NR_IRQS)
 
+#define TWL6030_IRQ_BASE        (OMAP_FPGA_IRQ_END)
+#ifdef CONFIG_TWL4030_CORE
+#define TWL6030_BASE_NR_IRQS    20
+#else
+#define TWL6030_BASE_NR_IRQS    0
+#endif
+#define TWL6030_IRQ_END         (TWL6030_IRQ_BASE + TWL6030_BASE_NR_IRQS)
+
 /* Total number of interrupts depends on the enabled blocks above */
-#define NR_IRQS                 TWL4030_GPIO_IRQ_END
+#if (TWL4030_GPIO_IRQ_END > TWL6030_IRQ_END)
+#define TWL_IRQ_END             TWL4030_GPIO_IRQ_END
+#else
+#define TWL_IRQ_END             TWL6030_IRQ_END
+#endif
+
+#define NR_IRQS                 TWL_IRQ_END
 
 #define OMAP_IRQ_BIT(irq)       (1 << ((irq) % 32))
 
diff --git a/arch/arm/plat-omap/include/plat/mux.h b/arch/arm/plat-omap/include/plat/mux.h
index ba77de601501..8f069cc80350 100644
--- a/arch/arm/plat-omap/include/plat/mux.h
+++ b/arch/arm/plat-omap/include/plat/mux.h
@@ -130,58 +130,11 @@
 #define OMAP2_PULL_UP           (1 << 4)
 #define OMAP2_ALTELECTRICALSEL  (1 << 5)
 
-/* 34xx specific mux bit defines */
-#define OMAP3_INPUT_EN          (1 << 8)
-#define OMAP3_OFF_EN            (1 << 9)
-#define OMAP3_OFFOUT_EN         (1 << 10)
-#define OMAP3_OFFOUT_VAL        (1 << 11)
-#define OMAP3_OFF_PULL_EN       (1 << 12)
-#define OMAP3_OFF_PULL_UP       (1 << 13)
-#define OMAP3_WAKEUP_EN         (1 << 14)
-
-/* 34xx mux mode options for each pin. See TRM for options */
-#define OMAP34XX_MUX_MODE0      0
-#define OMAP34XX_MUX_MODE1      1
-#define OMAP34XX_MUX_MODE2      2
-#define OMAP34XX_MUX_MODE3      3
-#define OMAP34XX_MUX_MODE4      4
-#define OMAP34XX_MUX_MODE5      5
-#define OMAP34XX_MUX_MODE6      6
-#define OMAP34XX_MUX_MODE7      7
-
-/* 34xx active pin states */
-#define OMAP34XX_PIN_OUTPUT             0
-#define OMAP34XX_PIN_INPUT              OMAP3_INPUT_EN
-#define OMAP34XX_PIN_INPUT_PULLUP       (OMAP2_PULL_ENA | OMAP3_INPUT_EN \
-                                                | OMAP2_PULL_UP)
-#define OMAP34XX_PIN_INPUT_PULLDOWN     (OMAP2_PULL_ENA | OMAP3_INPUT_EN)
-
-/* 34xx off mode states */
-#define OMAP34XX_PIN_OFF_NONE           0
-#define OMAP34XX_PIN_OFF_OUTPUT_HIGH    (OMAP3_OFF_EN | OMAP3_OFFOUT_EN \
-                                                | OMAP3_OFFOUT_VAL)
-#define OMAP34XX_PIN_OFF_OUTPUT_LOW     (OMAP3_OFF_EN | OMAP3_OFFOUT_EN)
-#define OMAP34XX_PIN_OFF_INPUT_PULLUP   (OMAP3_OFF_EN | OMAP3_OFF_PULL_EN \
-                                                | OMAP3_OFF_PULL_UP)
-#define OMAP34XX_PIN_OFF_INPUT_PULLDOWN (OMAP3_OFF_EN | OMAP3_OFF_PULL_EN)
-#define OMAP34XX_PIN_OFF_WAKEUPENABLE   OMAP3_WAKEUP_EN
-
-#define MUX_CFG_34XX(desc, reg_offset, mux_value) {             \
-        .name           = desc,                                 \
-        .debug          = 0,                                    \
-        .mux_reg        = reg_offset,                           \
-        .mux_val        = mux_value                             \
-},
-
 struct pin_config {
         char                    *name;
         const unsigned int      mux_reg;
         unsigned char           debug;
 
-#if     defined(CONFIG_ARCH_OMAP34XX)
-        u16                     mux_val; /* Wake-up, off mode, pull, mux mode */
-#endif
-
 #if     defined(CONFIG_ARCH_OMAP1) || defined(CONFIG_ARCH_OMAP24XX)
         const unsigned char mask_offset;
         const unsigned char mask;
@@ -219,11 +172,17 @@ enum omap7xx_index {
         AA17_7XX_USB_DM,
         W16_7XX_USB_PU_EN,
         W17_7XX_USB_VBUSI,
+        W18_7XX_USB_DMCK_OUT,
+        W19_7XX_USB_DCRST,
 
         /* MMC */
         MMC_7XX_CMD,
         MMC_7XX_CLK,
         MMC_7XX_DAT0,
+
+        /* I2C */
+        I2C_7XX_SCL,
+        I2C_7XX_SDA,
 };
 
 enum omap1xxx_index {
@@ -681,181 +640,6 @@ enum omap24xx_index {
 
 };
 
-enum omap34xx_index {
-        /* 34xx I2C */
-        K21_34XX_I2C1_SCL,
-        J21_34XX_I2C1_SDA,
-        AF15_34XX_I2C2_SCL,
-        AE15_34XX_I2C2_SDA,
-        AF14_34XX_I2C3_SCL,
-        AG14_34XX_I2C3_SDA,
-        AD26_34XX_I2C4_SCL,
-        AE26_34XX_I2C4_SDA,
-
-        /* PHY - HSUSB: 12-pin ULPI PHY: Port 1*/
-        Y8_3430_USB1HS_PHY_CLK,
-        Y9_3430_USB1HS_PHY_STP,
-        AA14_3430_USB1HS_PHY_DIR,
-        AA11_3430_USB1HS_PHY_NXT,
-        W13_3430_USB1HS_PHY_DATA0,
-        W12_3430_USB1HS_PHY_DATA1,
-        W11_3430_USB1HS_PHY_DATA2,
-        Y11_3430_USB1HS_PHY_DATA3,
-        W9_3430_USB1HS_PHY_DATA4,
-        Y12_3430_USB1HS_PHY_DATA5,
-        W8_3430_USB1HS_PHY_DATA6,
-        Y13_3430_USB1HS_PHY_DATA7,
-
-        /* PHY - HSUSB: 12-pin ULPI PHY: Port 2*/
-        AA8_3430_USB2HS_PHY_CLK,
-        AA10_3430_USB2HS_PHY_STP,
-        AA9_3430_USB2HS_PHY_DIR,
-        AB11_3430_USB2HS_PHY_NXT,
-        AB10_3430_USB2HS_PHY_DATA0,
-        AB9_3430_USB2HS_PHY_DATA1,
-        W3_3430_USB2HS_PHY_DATA2,
-        T4_3430_USB2HS_PHY_DATA3,
-        T3_3430_USB2HS_PHY_DATA4,
-        R3_3430_USB2HS_PHY_DATA5,
-        R4_3430_USB2HS_PHY_DATA6,
-        T2_3430_USB2HS_PHY_DATA7,
-
-
-        /* TLL - HSUSB: 12-pin TLL Port 1*/
-        Y8_3430_USB1HS_TLL_CLK,
-        Y9_3430_USB1HS_TLL_STP,
-        AA14_3430_USB1HS_TLL_DIR,
-        AA11_3430_USB1HS_TLL_NXT,
-        W13_3430_USB1HS_TLL_DATA0,
-        W12_3430_USB1HS_TLL_DATA1,
-        W11_3430_USB1HS_TLL_DATA2,
-        Y11_3430_USB1HS_TLL_DATA3,
-        W9_3430_USB1HS_TLL_DATA4,
-        Y12_3430_USB1HS_TLL_DATA5,
-        W8_3430_USB1HS_TLL_DATA6,
-        Y13_3430_USB1HS_TLL_DATA7,
-
-        /* TLL - HSUSB: 12-pin TLL Port 2*/
-        AA8_3430_USB2HS_TLL_CLK,
-        AA10_3430_USB2HS_TLL_STP,
-        AA9_3430_USB2HS_TLL_DIR,
-        AB11_3430_USB2HS_TLL_NXT,
-        AB10_3430_USB2HS_TLL_DATA0,
-        AB9_3430_USB2HS_TLL_DATA1,
-        W3_3430_USB2HS_TLL_DATA2,
-        T4_3430_USB2HS_TLL_DATA3,
-        T3_3430_USB2HS_TLL_DATA4,
-        R3_3430_USB2HS_TLL_DATA5,
-        R4_3430_USB2HS_TLL_DATA6,
-        T2_3430_USB2HS_TLL_DATA7,
-
-        /* TLL - HSUSB: 12-pin TLL Port 3*/
-        AA6_3430_USB3HS_TLL_CLK,
-        AB3_3430_USB3HS_TLL_STP,
-        AA3_3430_USB3HS_TLL_DIR,
-        Y3_3430_USB3HS_TLL_NXT,
-        AA5_3430_USB3HS_TLL_DATA0,
-        Y4_3430_USB3HS_TLL_DATA1,
-        Y5_3430_USB3HS_TLL_DATA2,
-        W5_3430_USB3HS_TLL_DATA3,
-        AB12_3430_USB3HS_TLL_DATA4,
-        AB13_3430_USB3HS_TLL_DATA5,
-        AA13_3430_USB3HS_TLL_DATA6,
-        AA12_3430_USB3HS_TLL_DATA7,
-
-        /* PHY FSUSB: FS Serial for Port 1 (multiple PHY modes supported) */
-        AF10_3430_USB1FS_PHY_MM1_RXDP,
-        AG9_3430_USB1FS_PHY_MM1_RXDM,
-        W13_3430_USB1FS_PHY_MM1_RXRCV,
-        W12_3430_USB1FS_PHY_MM1_TXSE0,
-        W11_3430_USB1FS_PHY_MM1_TXDAT,
-        Y11_3430_USB1FS_PHY_MM1_TXEN_N,
-
-        /* PHY FSUSB: FS Serial for Port 2 (multiple PHY modes supported) */
-        AF7_3430_USB2FS_PHY_MM2_RXDP,
-        AH7_3430_USB2FS_PHY_MM2_RXDM,
-        AB10_3430_USB2FS_PHY_MM2_RXRCV,
-        AB9_3430_USB2FS_PHY_MM2_TXSE0,
-        W3_3430_USB2FS_PHY_MM2_TXDAT,
-        T4_3430_USB2FS_PHY_MM2_TXEN_N,
-
-        /* PHY FSUSB: FS Serial for Port 3 (multiple PHY modes supported) */
-        AH3_3430_USB3FS_PHY_MM3_RXDP,
-        AE3_3430_USB3FS_PHY_MM3_RXDM,
-        AD1_3430_USB3FS_PHY_MM3_RXRCV,
-        AE1_3430_USB3FS_PHY_MM3_TXSE0,
-        AD2_3430_USB3FS_PHY_MM3_TXDAT,
-        AC1_3430_USB3FS_PHY_MM3_TXEN_N,
-
-        /* 34xx GPIO
-         *  - normally these are bidirectional, no internal pullup/pulldown
-         *  - "_UP" suffix (GPIO3_UP) if internal pullup is configured
-         *  - "_DOWN" suffix (GPIO3_DOWN) with internal pulldown
-         *  - "_OUT" suffix (GPIO3_OUT) for output-only pins (unlike 24xx)
-         */
-        AF26_34XX_GPIO0,
-        AF22_34XX_GPIO9,
-        AG9_34XX_GPIO23,
-        AH8_34XX_GPIO29,
-        U8_34XX_GPIO54_OUT,
-        U8_34XX_GPIO54_DOWN,
-        L8_34XX_GPIO63,
-        G25_34XX_GPIO86_OUT,
-        AG4_34XX_GPIO134_OUT,
-        AF4_34XX_GPIO135_OUT,
-        AE4_34XX_GPIO136_OUT,
-        AF6_34XX_GPIO140_UP,
-        AE6_34XX_GPIO141,
-        AF5_34XX_GPIO142,
-        AE5_34XX_GPIO143,
-        H19_34XX_GPIO164_OUT,
-        J25_34XX_GPIO170,
-
-        /* OMAP3 SDRC CKE signals to SDR/DDR ram chips */
-        H16_34XX_SDRC_CKE0,
-        H17_34XX_SDRC_CKE1,
-
-        /* MMC1 */
-        N28_3430_MMC1_CLK,
-        M27_3430_MMC1_CMD,
-        N27_3430_MMC1_DAT0,
-        N26_3430_MMC1_DAT1,
-        N25_3430_MMC1_DAT2,
-        P28_3430_MMC1_DAT3,
-        P27_3430_MMC1_DAT4,
-        P26_3430_MMC1_DAT5,
-        R27_3430_MMC1_DAT6,
-        R25_3430_MMC1_DAT7,
-
-        /* MMC2 */
-        AE2_3430_MMC2_CLK,
-        AG5_3430_MMC2_CMD,
-        AH5_3430_MMC2_DAT0,
-        AH4_3430_MMC2_DAT1,
-        AG4_3430_MMC2_DAT2,
-        AF4_3430_MMC2_DAT3,
-        AE4_3430_MMC2_DAT4,
-        AH3_3430_MMC2_DAT5,
-        AF3_3430_MMC2_DAT6,
-        AE3_3430_MMC2_DAT7,
-
-        /* MMC3 */
-        AF10_3430_MMC3_CLK,
-        AC3_3430_MMC3_CMD,
-        AE11_3430_MMC3_DAT0,
-        AH9_3430_MMC3_DAT1,
-        AF13_3430_MMC3_DAT2,
-        AF13_3430_MMC3_DAT3,
-
-        /* SYS_NIRQ T2 INT1 */
-        AF26_34XX_SYS_NIRQ,
-
-        /* EHCI GPIO's for OMAP3EVM (Rev >= E) */
-        AH14_34XX_GPIO21,
-        AF9_34XX_GPIO22,
-        U3_34XX_GPIO61,
-};
-
 struct omap_mux_cfg {
         struct pin_config       *pins;
         unsigned long           size;
@@ -865,14 +649,14 @@ struct omap_mux_cfg {
 #ifdef  CONFIG_OMAP_MUX
 /* setup pin muxing in Linux */
 extern int omap1_mux_init(void);
-extern int omap2_mux_init(void);
 extern int omap_mux_register(struct omap_mux_cfg *);
 extern int omap_cfg_reg(unsigned long reg_cfg);
 #else
 /* boot loader does it all (no warnings from CONFIG_OMAP_MUX_WARNINGS) */
 static inline int omap1_mux_init(void) { return 0; }
-static inline int omap2_mux_init(void) { return 0; }
 static inline int omap_cfg_reg(unsigned long reg_cfg) { return 0; }
 #endif
 
+extern int omap2_mux_init(void);
+
 #endif
diff --git a/arch/arm/plat-omap/include/plat/omap44xx.h b/arch/arm/plat-omap/include/plat/omap44xx.h
index e52902a15c1a..ef870de43c29 100644
--- a/arch/arm/plat-omap/include/plat/omap44xx.h
+++ b/arch/arm/plat-omap/include/plat/omap44xx.h
@@ -26,8 +26,10 @@
 #define OMAP44XX_EMIF2_BASE             0x4d000000
 #define OMAP44XX_DMM_BASE               0x4e000000
 #define OMAP4430_32KSYNCT_BASE          0x4a304000
-#define OMAP4430_CM_BASE                0x4a004000
-#define OMAP4430_PRM_BASE               0x48306000
+#define OMAP4430_CM1_BASE               0x4a004000
+#define OMAP4430_CM_BASE                OMAP4430_CM1_BASE
+#define OMAP4430_CM2_BASE               0x4a008000
+#define OMAP4430_PRM_BASE               0x4a306000
 #define OMAP44XX_GPMC_BASE              0x50000000
 #define OMAP443X_SCM_BASE               0x4a002000
 #define OMAP443X_CTRL_BASE              OMAP443X_SCM_BASE
diff --git a/arch/arm/plat-omap/include/plat/omap_device.h b/arch/arm/plat-omap/include/plat/omap_device.h
index 11a9773a4e7f..dc1fac1d805c 100644
--- a/arch/arm/plat-omap/include/plat/omap_device.h
+++ b/arch/arm/plat-omap/include/plat/omap_device.h
@@ -50,8 +50,8 @@
  * @pm_lats: ptr to an omap_device_pm_latency table
  * @pm_lats_cnt: ARRAY_SIZE() of what is passed to @pm_lats
  * @pm_lat_level: array index of the last odpl entry executed - -1 if never
- * @dev_wakeup_lat: dev wakeup latency in microseconds
- * @_dev_wakeup_lat_limit: dev wakeup latency limit in usec - set by OMAP PM
+ * @dev_wakeup_lat: dev wakeup latency in nanoseconds
+ * @_dev_wakeup_lat_limit: dev wakeup latency limit in nsec - set by OMAP PM
  * @_state: one of OMAP_DEVICE_STATE_* (see above)
  * @flags: device flags
  *
@@ -137,5 +137,7 @@ struct omap_device_pm_latency {
 };
 
 
-#endif
+/* Get omap_device pointer from platform_device pointer */
+#define to_omap_device(x) container_of((x), struct omap_device, pdev)
 
+#endif
diff --git a/arch/arm/plat-omap/include/plat/omap_hwmod.h b/arch/arm/plat-omap/include/plat/omap_hwmod.h
index dbdd123eca16..007935a921ea 100644
--- a/arch/arm/plat-omap/include/plat/omap_hwmod.h
+++ b/arch/arm/plat-omap/include/plat/omap_hwmod.h
@@ -50,6 +50,8 @@ struct omap_device;
 #define SYSC_ENAWAKEUP_MASK             (1 << SYSC_ENAWAKEUP_SHIFT)
 #define SYSC_SOFTRESET_SHIFT            1
 #define SYSC_SOFTRESET_MASK             (1 << SYSC_SOFTRESET_SHIFT)
+#define SYSC_AUTOIDLE_SHIFT             0
+#define SYSC_AUTOIDLE_MASK              (1 << SYSC_AUTOIDLE_SHIFT)
 
 /* OCP SYSSTATUS bit shifts/masks */
 #define SYSS_RESETDONE_SHIFT            0
@@ -62,7 +64,21 @@ struct omap_device;
 
 
 /**
- * struct omap_hwmod_dma_info - MPU address space handled by the hwmod
+ * struct omap_hwmod_irq_info - MPU IRQs used by the hwmod
+ * @name: name of the IRQ channel (module local name)
+ * @irq_ch: IRQ channel ID
+ *
+ * @name should be something short, e.g., "tx" or "rx".  It is for use
+ * by platform_get_resource_byname().  It is defined locally to the
+ * hwmod.
+ */
+struct omap_hwmod_irq_info {
+        const char      *name;
+        u16             irq;
+};
+
+/**
+ * struct omap_hwmod_dma_info - DMA channels used by the hwmod
  * @name: name of the DMA channel (module local name)
  * @dma_ch: DMA channel ID
  *
@@ -294,13 +310,17 @@ struct omap_hwmod_omap4_prcm {
  *     SDRAM controller, etc.
  * HWMOD_INIT_NO_IDLE: don't idle this module at boot - important for SDRAM
  *     controller, etc.
+ * HWMOD_NO_AUTOIDLE: disable module autoidle (OCP_SYSCONFIG.AUTOIDLE)
+ *     when module is enabled, rather than the default, which is to
+ *     enable autoidle
  * HWMOD_SET_DEFAULT_CLOCKACT: program CLOCKACTIVITY bits at startup
  */
 #define HWMOD_SWSUP_SIDLE                       (1 << 0)
 #define HWMOD_SWSUP_MSTANDBY                    (1 << 1)
 #define HWMOD_INIT_NO_RESET                     (1 << 2)
 #define HWMOD_INIT_NO_IDLE                      (1 << 3)
-#define HWMOD_SET_DEFAULT_CLOCKACT              (1 << 4)
+#define HWMOD_NO_OCP_AUTOIDLE                   (1 << 4)
+#define HWMOD_SET_DEFAULT_CLOCKACT              (1 << 5)
 
 /*
  * omap_hwmod._int_flags definitions
@@ -373,7 +393,7 @@ struct omap_hwmod_omap4_prcm {
 struct omap_hwmod {
         const char                      *name;
         struct omap_device              *od;
-        u8                              *mpu_irqs;
+        struct omap_hwmod_irq_info      *mpu_irqs;
         struct omap_hwmod_dma_info      *sdma_chs;
         union {
                 struct omap_hwmod_omap2_prcm omap2;
diff --git a/arch/arm/plat-omap/include/plat/powerdomain.h b/arch/arm/plat-omap/include/plat/powerdomain.h
index 3d45ee1d3cf4..0b960051eaed 100644
--- a/arch/arm/plat-omap/include/plat/powerdomain.h
+++ b/arch/arm/plat-omap/include/plat/powerdomain.h
@@ -28,6 +28,8 @@
 #define PWRDM_POWER_INACTIVE    0x2
 #define PWRDM_POWER_ON          0x3
 
+#define PWRDM_MAX_PWRSTS        4
+
 /* Powerdomain allowable state bitfields */
 #define PWRSTS_OFF_ON           ((1 << PWRDM_POWER_OFF) | \
                                  (1 << PWRDM_POWER_ON))
@@ -40,7 +42,10 @@
 
 /* Powerdomain flags */
 #define PWRDM_HAS_HDWR_SAR      (1 << 0) /* hardware save-and-restore support */
-
+#define PWRDM_HAS_MPU_QUIRK     (1 << 1) /* MPU pwr domain has MEM bank 0 bits
+                                          * in MEM bank 1 position. This is
+                                          * true for OMAP3430
+                                          */
 
 /*
  * Number of memory banks that are power-controllable.  On OMAP3430, the
@@ -85,15 +90,15 @@ struct powerdomain {
         /* Used to represent the OMAP chip types containing this pwrdm */
         const struct omap_chip_id omap_chip;
 
-        /* Bit shift of this powerdomain's PM_WKDEP/CM_SLEEPDEP bit */
-        const u8 dep_bit;
-
         /* Powerdomains that can be told to wake this powerdomain up */
         struct pwrdm_dep *wkdep_srcs;
 
         /* Powerdomains that can be told to keep this pwrdm from inactivity */
         struct pwrdm_dep *sleepdep_srcs;
 
+        /* Bit shift of this powerdomain's PM_WKDEP/CM_SLEEPDEP bit */
+        const u8 dep_bit;
+
         /* Possible powerdomain power states */
         const u8 pwrsts;
 
@@ -118,11 +123,11 @@ struct powerdomain {
         struct list_head node;
 
         int state;
-        unsigned state_counter[4];
+        unsigned state_counter[PWRDM_MAX_PWRSTS];
 
 #ifdef CONFIG_PM_DEBUG
         s64 timer;
-        s64 state_timer[4];
+        s64 state_timer[PWRDM_MAX_PWRSTS];
 #endif
 };
 
diff --git a/arch/arm/plat-omap/include/plat/serial.h b/arch/arm/plat-omap/include/plat/serial.h
index 9951345a25d6..f5a4a92393ef 100644
--- a/arch/arm/plat-omap/include/plat/serial.h
+++ b/arch/arm/plat-omap/include/plat/serial.h
@@ -53,6 +53,7 @@
 #ifndef __ASSEMBLER__
 extern void __init omap_serial_early_init(void);
 extern void omap_serial_init(void);
+extern void omap_serial_init_port(int port);
 extern int omap_uart_can_sleep(void);
 extern void omap_uart_check_wakeup(void);
 extern void omap_uart_prepare_suspend(void);
diff --git a/arch/arm/plat-omap/include/plat/smp.h b/arch/arm/plat-omap/include/plat/smp.h
index dcaa8fde7063..8983d54c4fd2 100644
--- a/arch/arm/plat-omap/include/plat/smp.h
+++ b/arch/arm/plat-omap/include/plat/smp.h
@@ -28,6 +28,8 @@
 
 /* Needed for secondary core boot */
 extern void omap_secondary_startup(void);
+extern u32 omap_modify_auxcoreboot0(u32 set_mask, u32 clear_mask);
+extern void omap_auxcoreboot_addr(u32 cpu_addr);
 
 /*
  * We use Soft IRQ1 as the IPI
diff --git a/arch/arm/plat-omap/mux.c b/arch/arm/plat-omap/mux.c
index 05aebcad215b..06703635ace1 100644
--- a/arch/arm/plat-omap/mux.c
+++ b/arch/arm/plat-omap/mux.c
@@ -54,8 +54,12 @@ int __init_or_module omap_cfg_reg(const unsigned long index)
 {
         struct pin_config *reg;
 
-        if (cpu_is_omap44xx())
-                return 0;
+        if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
+                printk(KERN_ERR "mux: Broken omap_cfg_reg(%lu) entry\n",
+                                index);
+                WARN_ON(1);
+                return -EINVAL;
+        }
 
         if (mux_cfg == NULL) {
                 printk(KERN_ERR "Pin mux table not initialized\n");
diff --git a/arch/arm/plat-omap/omap_device.c b/arch/arm/plat-omap/omap_device.c
index bb16e624a557..1e5648d3e3d8 100644
--- a/arch/arm/plat-omap/omap_device.c
+++ b/arch/arm/plat-omap/omap_device.c
@@ -134,18 +134,18 @@ static int _omap_device_activate(struct omap_device *od, u8 ignore_lat)
                     (od->dev_wakeup_lat <= od->_dev_wakeup_lat_limit))
                         break;
 
-                getnstimeofday(&a);
+                read_persistent_clock(&a);
 
                 /* XXX check return code */
                 odpl->activate_func(od);
 
-                getnstimeofday(&b);
+                read_persistent_clock(&b);
 
                 c = timespec_sub(b, a);
-                act_lat = timespec_to_ns(&c) * NSEC_PER_USEC;
+                act_lat = timespec_to_ns(&c);
 
                 pr_debug("omap_device: %s: pm_lat %d: activate: elapsed time "
-                         "%llu usec\n", od->pdev.name, od->pm_lat_level,
+                         "%llu nsec\n", od->pdev.name, od->pm_lat_level,
                          act_lat);
 
                 WARN(act_lat > odpl->activate_lat, "omap_device: %s.%d: "
@@ -190,18 +190,18 @@ static int _omap_device_deactivate(struct omap_device *od, u8 ignore_lat)
                      od->_dev_wakeup_lat_limit))
                         break;
 
-                getnstimeofday(&a);
+                read_persistent_clock(&a);
 
                 /* XXX check return code */
                 odpl->deactivate_func(od);
 
-                getnstimeofday(&b);
+                read_persistent_clock(&b);
 
                 c = timespec_sub(b, a);
-                deact_lat = timespec_to_ns(&c) * NSEC_PER_USEC;
+                deact_lat = timespec_to_ns(&c);
 
                 pr_debug("omap_device: %s: pm_lat %d: deactivate: elapsed time "
-                         "%llu usec\n", od->pdev.name, od->pm_lat_level,
+                         "%llu nsec\n", od->pdev.name, od->pm_lat_level,
                          deact_lat);
 
                 WARN(deact_lat > odpl->deactivate_lat, "omap_device: %s.%d: "
@@ -459,7 +459,7 @@ int omap_device_enable(struct platform_device *pdev)
         ret = _omap_device_activate(od, IGNORE_WAKEUP_LAT);
 
         od->dev_wakeup_lat = 0;
-        od->_dev_wakeup_lat_limit = INT_MAX;
+        od->_dev_wakeup_lat_limit = UINT_MAX;
         od->_state = OMAP_DEVICE_STATE_ENABLED;
 
         return ret;
diff --git a/arch/arm/plat-omap/sram.c b/arch/arm/plat-omap/sram.c
index ad2bf07d30b5..d8d5094b37ed 100644
--- a/arch/arm/plat-omap/sram.c
+++ b/arch/arm/plat-omap/sram.c
@@ -48,8 +48,10 @@
 #define OMAP3_SRAM_VA           0xfe400000
 #define OMAP3_SRAM_PUB_PA       0x40208000
 #define OMAP3_SRAM_PUB_VA       (OMAP3_SRAM_VA + 0x8000)
-#define OMAP4_SRAM_PA           0x40200000              /*0x402f0000*/
-#define OMAP4_SRAM_VA           0xfe400000              /*0xfe4f0000*/
+#define OMAP4_SRAM_PA           0x40300000
+#define OMAP4_SRAM_VA           0xfe400000
+#define OMAP4_SRAM_PUB_PA       (OMAP4_SRAM_PA + 0x4000)
+#define OMAP4_SRAM_PUB_VA       (OMAP4_SRAM_VA + 0x4000)
 
 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
 #define SRAM_BOOTLOADER_SZ      0x00
@@ -140,6 +142,10 @@ void __init omap_detect_sram(void)
                                 } else {
                                         omap_sram_size = 0x8000; /* 32K */
                                 }
+                        } else if (cpu_is_omap44xx()) {
+                                omap_sram_base = OMAP4_SRAM_PUB_VA;
+                                omap_sram_start = OMAP4_SRAM_PUB_PA;
+                                omap_sram_size = 0xa000; /* 40K */
                         } else {
                                 omap_sram_base = OMAP2_SRAM_PUB_VA;
                                 omap_sram_start = OMAP2_SRAM_PUB_PA;
@@ -153,7 +159,7 @@ void __init omap_detect_sram(void)
                         } else if (cpu_is_omap44xx()) {
                                 omap_sram_base = OMAP4_SRAM_VA;
                                 omap_sram_start = OMAP4_SRAM_PA;
-                                omap_sram_size = 0x8000; /* 32K */
+                                omap_sram_size = 0xe000; /* 56K */
                         } else {
                                 omap_sram_base = OMAP2_SRAM_VA;
                                 omap_sram_start = OMAP2_SRAM_PA;
diff --git a/arch/arm/plat-omap/usb.c b/arch/arm/plat-omap/usb.c
index 51033a4503c3..d3bf17cd36f3 100644
--- a/arch/arm/plat-omap/usb.c
+++ b/arch/arm/plat-omap/usb.c
@@ -137,7 +137,13 @@ static u32 __init omap_usb0_init(unsigned nwires, unsigned is_device)
         if (is_device) {
                 if (cpu_is_omap24xx())
                         omap_cfg_reg(J20_24XX_USB0_PUEN);
-                else
+                else if (cpu_is_omap7xx()) {
+                        omap_cfg_reg(AA17_7XX_USB_DM);
+                        omap_cfg_reg(W16_7XX_USB_PU_EN);
+                        omap_cfg_reg(W17_7XX_USB_VBUSI);
+                        omap_cfg_reg(W18_7XX_USB_DMCK_OUT);
+                        omap_cfg_reg(W19_7XX_USB_DCRST);
+                } else
                         omap_cfg_reg(W4_USB_PUEN);
         }
 
diff --git a/arch/arm/plat-s3c/include/plat/nand.h b/arch/arm/plat-s3c/include/plat/nand.h
index 065985978413..226147b7e026 100644
--- a/arch/arm/plat-s3c/include/plat/nand.h
+++ b/arch/arm/plat-s3c/include/plat/nand.h
@@ -17,6 +17,7 @@
  *                      Setting this flag will allow the kernel to
  *                      look for it at boot time and also skip the NAND
  *                      scan.
+ * @options:            Default value to set into 'struct nand_chip' options.
  * @nr_chips:           Number of chips in this set
  * @nr_partitions:      Number of partitions pointed to by @partitions
  * @name:               Name of set (optional)
@@ -31,6 +32,7 @@ struct s3c2410_nand_set {
         unsigned int            disable_ecc:1;
         unsigned int            flash_bbt:1;
 
+        unsigned int            options;
         int                     nr_chips;
         int                     nr_partitions;
         char                    *name;
diff --git a/arch/arm/tools/Makefile b/arch/arm/tools/Makefile
index 1dbaa29ac4d7..635cb1865e4d 100644
--- a/arch/arm/tools/Makefile
+++ b/arch/arm/tools/Makefile
@@ -4,7 +4,7 @@
 # Copyright (C) 2001 Russell King
 #
 
-include/asm-arm/mach-types.h: $(src)/gen-mach-types $(src)/mach-types
+include/generated/mach-types.h: $(src)/gen-mach-types $(src)/mach-types
         @echo '  Generating $@'
         @mkdir -p $(dir $@)
         $(Q)$(AWK) -f $^ > $@ || { rm -f $@; /bin/false; }
diff --git a/arch/arm/tools/gen-mach-types b/arch/arm/tools/gen-mach-types
index ce319ef64bc1..04fef71d7be9 100644
--- a/arch/arm/tools/gen-mach-types
+++ b/arch/arm/tools/gen-mach-types
@@ -1,6 +1,6 @@
 #!/bin/awk
 #
-# Awk script to generate include/asm-arm/mach-types.h
+# Awk script to generate include/generated/mach-types.h
 #
 BEGIN   { nr = 0 }
 /^#/    { next }
diff --git a/arch/arm/tools/mach-types b/arch/arm/tools/mach-types
index 07b976da6174..c3a74ce24ef6 100644
--- a/arch/arm/tools/mach-types
+++ b/arch/arm/tools/mach-types
@@ -12,7 +12,7 @@
 #
 #   http://www.arm.linux.org.uk/developer/machines/?action=new
 #
-# Last update: Wed Nov 25 22:14:58 2009
+# Last update: Wed Dec 16 20:06:34 2009
 #
 # machine_is_xxx        CONFIG_xxxx             MACH_TYPE_xxx           number
 #
@@ -1776,6 +1776,7 @@ cybook3			MACH_CYBOOK3		CYBOOK3			1784
 wdg002                  MACH_WDG002             WDG002                  1785
 sg560adsl               MACH_SG560ADSL          SG560ADSL               1786
 nextio_n2800_ica        MACH_NEXTIO_N2800_ICA   NEXTIO_N2800_ICA        1787
+dove_db                 MACH_DOVE_DB            DOVE_DB                 1788
 marvell_newdb           MACH_MARVELL_NEWDB      MARVELL_NEWDB           1789
 vandihud                MACH_VANDIHUD           VANDIHUD                1790
 magx_e8                 MACH_MAGX_E8            MAGX_E8                 1791
@@ -2536,3 +2537,44 @@ c3ax03			MACH_C3AX03		C3AX03			2549
 mxt_td60                MACH_MXT_TD60           MXT_TD60                2550
 esyx                    MACH_ESYX               ESYX                    2551
 bulldog                 MACH_BULLDOG            BULLDOG                 2553
+derell_me2000           MACH_DERELL_ME2000      DERELL_ME2000           2554
+bcmring_base            MACH_BCMRING_BASE       BCMRING_BASE            2555
+bcmring_evm             MACH_BCMRING_EVM        BCMRING_EVM             2556
+bcmring_evm_jazz        MACH_BCMRING_EVM_JAZZ   BCMRING_EVM_JAZZ        2557
+bcmring_sp              MACH_BCMRING_SP         BCMRING_SP              2558
+bcmring_sv              MACH_BCMRING_SV         BCMRING_SV              2559
+bcmring_sv_jazz         MACH_BCMRING_SV_JAZZ    BCMRING_SV_JAZZ         2560
+bcmring_tablet          MACH_BCMRING_TABLET     BCMRING_TABLET          2561
+bcmring_vp              MACH_BCMRING_VP         BCMRING_VP              2562
+bcmring_evm_seikor      MACH_BCMRING_EVM_SEIKOR BCMRING_EVM_SEIKOR      2563
+bcmring_sp_wqvga        MACH_BCMRING_SP_WQVGA   BCMRING_SP_WQVGA        2564
+bcmring_custom          MACH_BCMRING_CUSTOM     BCMRING_CUSTOM          2565
+acer_s200               MACH_ACER_S200          ACER_S200               2566
+bt270                   MACH_BT270              BT270                   2567
+iseo                    MACH_ISEO               ISEO                    2568
+cezanne                 MACH_CEZANNE            CEZANNE                 2569
+lucca                   MACH_LUCCA              LUCCA                   2570
+supersmart              MACH_SUPERSMART         SUPERSMART              2571
+magnolia2               MACH_MAGNOLIA2          MAGNOLIA2               2573
+emxx                    MACH_EMXX               EMXX                    2574
+outlaw                  MACH_OUTLAW             OUTLAW                  2575
+riot_bei2               MACH_RIOT_BEI2          RIOT_BEI2               2576
+riot_vox                MACH_RIOT_VOX           RIOT_VOX                2577
+riot_x37                MACH_RIOT_X37           RIOT_X37                2578
+mega25mx                MACH_MEGA25MX           MEGA25MX                2579
+benzina2                MACH_BENZINA2           BENZINA2                2580
+ignite                  MACH_IGNITE             IGNITE                  2581
+foggia                  MACH_FOGGIA             FOGGIA                  2582
+arezzo                  MACH_AREZZO             AREZZO                  2583
+leica_skywalker         MACH_LEICA_SKYWALKER    LEICA_SKYWALKER         2584
+jacinto2_jamr           MACH_JACINTO2_JAMR      JACINTO2_JAMR           2585
+gts_nova                MACH_GTS_NOVA           GTS_NOVA                2586
+p3600                   MACH_P3600              P3600                   2587
+dlt2                    MACH_DLT2               DLT2                    2588
+df3120                  MACH_DF3120             DF3120                  2589
+ecucore_9g20            MACH_ECUCORE_9G20       ECUCORE_9G20            2590
+nautel_lpc3240          MACH_NAUTEL_LPC3240     NAUTEL_LPC3240          2591
+glacier                 MACH_GLACIER            GLACIER                 2592
+phrazer_bulldog         MACH_PHRAZER_BULLDOG    PHRAZER_BULLDOG         2593
+omap3_bulldog           MACH_OMAP3_BULLDOG      OMAP3_BULLDOG           2594
+pca101                  MACH_PCA101             PCA101                  2595
diff --git a/arch/arm/vfp/vfpmodule.c b/arch/arm/vfp/vfpmodule.c
index 2d7423af1197..aed05bc3c2ea 100644
--- a/arch/arm/vfp/vfpmodule.c
+++ b/arch/arm/vfp/vfpmodule.c
@@ -38,16 +38,72 @@ union vfp_state *last_VFP_context[NR_CPUS];
  */
 unsigned int VFP_arch;
 
+/*
+ * Per-thread VFP initialization.
+ */
+static void vfp_thread_flush(struct thread_info *thread)
+{
+        union vfp_state *vfp = &thread->vfpstate;
+        unsigned int cpu;
+
+        memset(vfp, 0, sizeof(union vfp_state));
+
+        vfp->hard.fpexc = FPEXC_EN;
+        vfp->hard.fpscr = FPSCR_ROUND_NEAREST;
+
+        /*
+         * Disable VFP to ensure we initialize it first.  We must ensure
+         * that the modification of last_VFP_context[] and hardware disable
+         * are done for the same CPU and without preemption.
+         */
+        cpu = get_cpu();
+        if (last_VFP_context[cpu] == vfp)
+                last_VFP_context[cpu] = NULL;
+        fmxr(FPEXC, fmrx(FPEXC) & ~FPEXC_EN);
+        put_cpu();
+}
+
+static void vfp_thread_release(struct thread_info *thread)
+{
+        /* release case: Per-thread VFP cleanup. */
+        union vfp_state *vfp = &thread->vfpstate;
+        unsigned int cpu = thread->cpu;
+
+        if (last_VFP_context[cpu] == vfp)
+                last_VFP_context[cpu] = NULL;
+}
+
+/*
+ * When this function is called with the following 'cmd's, the following
+ * is true while this function is being run:
+ *  THREAD_NOFTIFY_SWTICH:
+ *   - the previously running thread will not be scheduled onto another CPU.
+ *   - the next thread to be run (v) will not be running on another CPU.
+ *   - thread->cpu is the local CPU number
+ *   - not preemptible as we're called in the middle of a thread switch
+ *  THREAD_NOTIFY_FLUSH:
+ *   - the thread (v) will be running on the local CPU, so
+ *      v === current_thread_info()
+ *   - thread->cpu is the local CPU number at the time it is accessed,
+ *      but may change at any time.
+ *   - we could be preempted if tree preempt rcu is enabled, so
+ *      it is unsafe to use thread->cpu.
+ *  THREAD_NOTIFY_RELEASE:
+ *   - the thread (v) will not be running on any CPU; it is a dead thread.
+ *   - thread->cpu will be the last CPU the thread ran on, which may not
+ *      be the current CPU.
+ *   - we could be preempted if tree preempt rcu is enabled.
+ */
 static int vfp_notifier(struct notifier_block *self, unsigned long cmd, void *v)
 {
         struct thread_info *thread = v;
-        union vfp_state *vfp;
-        __u32 cpu = thread->cpu;
 
         if (likely(cmd == THREAD_NOTIFY_SWITCH)) {
                 u32 fpexc = fmrx(FPEXC);
 
 #ifdef CONFIG_SMP
+                unsigned int cpu = thread->cpu;
+
                 /*
                  * On SMP, if VFP is enabled, save the old state in
                  * case the thread migrates to a different CPU. The
@@ -74,25 +130,10 @@ static int vfp_notifier(struct notifier_block *self, unsigned long cmd, void *v)
                 return NOTIFY_DONE;
         }
 
-        vfp = &thread->vfpstate;
-        if (cmd == THREAD_NOTIFY_FLUSH) {
-                /*
-                 * Per-thread VFP initialisation.
-                 */
-                memset(vfp, 0, sizeof(union vfp_state));
-
-                vfp->hard.fpexc = FPEXC_EN;
-                vfp->hard.fpscr = FPSCR_ROUND_NEAREST;
-
-                /*
-                 * Disable VFP to ensure we initialise it first.
-                 */
-                fmxr(FPEXC, fmrx(FPEXC) & ~FPEXC_EN);
-        }
-
-        /* flush and release case: Per-thread VFP cleanup. */
-        if (last_VFP_context[cpu] == vfp)
-                last_VFP_context[cpu] = NULL;
+        if (cmd == THREAD_NOTIFY_FLUSH)
+                vfp_thread_flush(thread);
+        else
+                vfp_thread_release(thread);
 
         return NOTIFY_DONE;
 }
diff --git a/arch/avr32/Kconfig b/arch/avr32/Kconfig
index d856354f4272..f2b319333184 100644
--- a/arch/avr32/Kconfig
+++ b/arch/avr32/Kconfig
@@ -112,6 +112,11 @@ config CPU_AT32AP7002
         bool
         select CPU_AT32AP700X
 
+# AP700X boards
+config BOARD_ATNGW100_COMMON
+        bool
+        select CPU_AT32AP7000
+
 choice
         prompt "AVR32 board type"
         default BOARD_ATSTK1000
@@ -119,9 +124,13 @@ choice
 config BOARD_ATSTK1000
         bool "ATSTK1000 evaluation board"
 
-config BOARD_ATNGW100
+config BOARD_ATNGW100_MKI
         bool "ATNGW100 Network Gateway"
-        select CPU_AT32AP7000
+        select BOARD_ATNGW100_COMMON
+
+config BOARD_ATNGW100_MKII
+        bool "ATNGW100 mkII Network Gateway"
+        select BOARD_ATNGW100_COMMON
 
 config BOARD_HAMMERHEAD
         bool "Hammerhead board"
diff --git a/arch/avr32/Makefile b/arch/avr32/Makefile
index c21a3290d542..ead8a75203a9 100644
--- a/arch/avr32/Makefile
+++ b/arch/avr32/Makefile
@@ -32,7 +32,7 @@ head-$(CONFIG_LOADER_U_BOOT)		+= arch/avr32/boot/u-boot/head.o
 head-y                                  += arch/avr32/kernel/head.o
 core-y                                  += $(machdirs)
 core-$(CONFIG_BOARD_ATSTK1000)          += arch/avr32/boards/atstk1000/
-core-$(CONFIG_BOARD_ATNGW100)           += arch/avr32/boards/atngw100/
+core-$(CONFIG_BOARD_ATNGW100_COMMON)    += arch/avr32/boards/atngw100/
 core-$(CONFIG_BOARD_HAMMERHEAD)         += arch/avr32/boards/hammerhead/
 core-$(CONFIG_BOARD_FAVR_32)            += arch/avr32/boards/favr-32/
 core-$(CONFIG_BOARD_MERISC)             += arch/avr32/boards/merisc/
diff --git a/arch/avr32/boards/atngw100/Kconfig b/arch/avr32/boards/atngw100/Kconfig
index be27a0218ab4..4e55617ade2d 100644
--- a/arch/avr32/boards/atngw100/Kconfig
+++ b/arch/avr32/boards/atngw100/Kconfig
@@ -1,6 +1,17 @@
 # NGW100 customization
 
-if BOARD_ATNGW100
+if BOARD_ATNGW100_COMMON
+
+config BOARD_ATNGW100_MKII_LCD
+        bool "Enable ATNGW100 mkII LCD interface"
+        depends on BOARD_ATNGW100_MKII
+        help
+          This enables the LCD controller (LCDC) in the AT32AP7000. Since the
+          LCDC is multiplexed with MACB1 (LAN) Ethernet port, only one can be
+          enabled at a time.
+
+          This choice enables the LCDC and disables the MACB1 interface marked
+          LAN on the PCB.
 
 choice
         prompt "Select an NGW100 add-on board to support"
@@ -11,15 +22,11 @@ config BOARD_ATNGW100_ADDON_NONE
 
 config BOARD_ATNGW100_EVKLCD10X
         bool "EVKLCD10X addon board"
+        depends on BOARD_ATNGW100_MKI || BOARD_ATNGW100_MKII_LCD
         help
           This enables support for the EVKLCD100 (QVGA) or EVKLCD101 (VGA)
-          addon board for the NGW100. By enabling this the LCD controller and
-          AC97 controller is added as platform devices.
-
-          This choice disables the detect pin and the write-protect pin for the
-          MCI platform device, since it conflicts with the LCD platform device.
-          The MCI pins can be reenabled by editing the "add device function" but
-          this may break the setup for other displays that use these pins.
+          addon board for the NGW100 and NGW100 mkII. By enabling this the LCD
+          controller and AC97 controller is added as platform devices.
 
 config BOARD_ATNGW100_MRMT
         bool "Mediama RMT1/2 add-on board"
@@ -55,4 +62,4 @@ if BOARD_ATNGW100_MRMT
 source  "arch/avr32/boards/atngw100/Kconfig_mrmt"
 endif
 
-endif   # BOARD_ATNGW100
+endif   # BOARD_ATNGW100_COMMON
diff --git a/arch/avr32/boards/atngw100/evklcd10x.c b/arch/avr32/boards/atngw100/evklcd10x.c
index 00337112c5ac..20388750d564 100644
--- a/arch/avr32/boards/atngw100/evklcd10x.c
+++ b/arch/avr32/boards/atngw100/evklcd10x.c
@@ -164,7 +164,12 @@ static int __init atevklcd10x_init(void)
 
         at32_add_device_lcdc(0, &atevklcd10x_lcdc_data,
                         fbmem_start, fbmem_size,
-                        ATMEL_LCDC_ALT_18BIT | ATMEL_LCDC_PE_DVAL);
+#ifdef CONFIG_BOARD_ATNGW100_MKII
+                        ATMEL_LCDC_PRI_18BIT | ATMEL_LCDC_PC_DVAL
+#else
+                        ATMEL_LCDC_ALT_18BIT | ATMEL_LCDC_PE_DVAL
+#endif
+                        );
 
         at32_add_device_ac97c(0, &ac97c0_data, AC97C_BOTH);
 
diff --git a/arch/avr32/boards/atngw100/mrmt.c b/arch/avr32/boards/atngw100/mrmt.c
index bf78e516a85f..7919be311f4a 100644
--- a/arch/avr32/boards/atngw100/mrmt.c
+++ b/arch/avr32/boards/atngw100/mrmt.c
@@ -302,6 +302,7 @@ static int __init mrmt1_init(void)
         at32_select_periph( GPIO_PIOB_BASE, 1 << (PB_EXTINT_BASE+TS_IRQ),
                         GPIO_PERIPH_A, AT32_GPIOF_DEGLITCH);
         set_irq_type( AT32_EXTINT(TS_IRQ), IRQ_TYPE_EDGE_FALLING );
+        at32_spi_setup_slaves(0,spi01_board_info,ARRAY_SIZE(spi01_board_info));
         spi_register_board_info(spi01_board_info,ARRAY_SIZE(spi01_board_info));
 #endif
 
diff --git a/arch/avr32/boards/atngw100/setup.c b/arch/avr32/boards/atngw100/setup.c
index bc299fbbeb4e..8c6a2440e345 100644
--- a/arch/avr32/boards/atngw100/setup.c
+++ b/arch/avr32/boards/atngw100/setup.c
@@ -20,6 +20,7 @@
 #include <linux/leds.h>
 #include <linux/spi/spi.h>
 #include <linux/atmel-mci.h>
+#include <linux/usb/atmel_usba_udc.h>
 
 #include <asm/io.h>
 #include <asm/setup.h>
@@ -36,6 +37,75 @@ unsigned long at32_board_osc_rates[3] = {
         [2] = 12000000, /* 12 MHz on osc1 */
 };
 
+/*
+ * The ATNGW100 mkII is very similar to the ATNGW100. Both have the AT32AP7000
+ * chip on board; the difference is that the ATNGW100 mkII has 128 MB 32-bit
+ * SDRAM (the ATNGW100 has 32 MB 16-bit SDRAM) and 256 MB 16-bit NAND flash
+ * (the ATNGW100 has none.)
+ *
+ * The RAM difference is handled by the boot loader, so the only difference we
+ * end up handling here is the NAND flash, EBI pin reservation and if LCDC or
+ * MACB1 should be enabled.
+ */
+#ifdef CONFIG_BOARD_ATNGW100_MKII
+#include <linux/mtd/partitions.h>
+#include <mach/smc.h>
+
+static struct smc_timing nand_timing __initdata = {
+        .ncs_read_setup         = 0,
+        .nrd_setup              = 10,
+        .ncs_write_setup        = 0,
+        .nwe_setup              = 10,
+
+        .ncs_read_pulse         = 30,
+        .nrd_pulse              = 15,
+        .ncs_write_pulse        = 30,
+        .nwe_pulse              = 15,
+
+        .read_cycle             = 30,
+        .write_cycle            = 30,
+
+        .ncs_read_recover       = 0,
+        .nrd_recover            = 15,
+        .ncs_write_recover      = 0,
+        /* WE# high -> RE# low min 60 ns */
+        .nwe_recover            = 50,
+};
+
+static struct smc_config nand_config __initdata = {
+        .bus_width              = 2,
+        .nrd_controlled         = 1,
+        .nwe_controlled         = 1,
+        .nwait_mode             = 0,
+        .byte_write             = 0,
+        .tdf_cycles             = 2,
+        .tdf_mode               = 0,
+};
+
+static struct mtd_partition nand_partitions[] = {
+        {
+                .name           = "main",
+                .offset         = 0x00000000,
+                .size           = MTDPART_SIZ_FULL,
+        },
+};
+
+static struct mtd_partition *nand_part_info(int size, int *num_partitions)
+{
+        *num_partitions = ARRAY_SIZE(nand_partitions);
+        return nand_partitions;
+}
+
+static struct atmel_nand_data atngw100mkii_nand_data __initdata = {
+        .cle            = 21,
+        .ale            = 22,
+        .rdy_pin        = GPIO_PIN_PB(28),
+        .enable_pin     = GPIO_PIN_PE(23),
+        .bus_width_16   = true,
+        .partition_info = nand_part_info,
+};
+#endif
+
 /* Initialized by bootloader-specific startup code. */
 struct tag *bootloader_tags __initdata;
 
@@ -56,9 +126,9 @@ static struct spi_board_info spi0_board_info[] __initdata = {
 static struct mci_platform_data __initdata mci0_data = {
         .slot[0] = {
                 .bus_width      = 4,
-#if defined(CONFIG_BOARD_ATNGW100_EVKLCD10X) || defined(CONFIG_BOARD_ATNGW100_MRMT1)
-                .detect_pin     = GPIO_PIN_NONE,
-                .wp_pin         = GPIO_PIN_NONE,
+#if defined(CONFIG_BOARD_ATNGW100_MKII)
+                .detect_pin     = GPIO_PIN_PC(25),
+                .wp_pin         = GPIO_PIN_PE(22),
 #else
                 .detect_pin     = GPIO_PIN_PC(25),
                 .wp_pin         = GPIO_PIN_PE(0),
@@ -66,6 +136,14 @@ static struct mci_platform_data __initdata mci0_data = {
         },
 };
 
+static struct usba_platform_data atngw100_usba_data __initdata = {
+#if defined(CONFIG_BOARD_ATNGW100_MKII)
+        .vbus_pin       = GPIO_PIN_PE(26),
+#else
+        .vbus_pin       = -ENODEV,
+#endif
+};
+
 /*
  * The next two functions should go away as the boot loader is
  * supposed to initialize the macb address registers with a valid
@@ -173,18 +251,27 @@ static int __init atngw100_init(void)
         unsigned        i;
 
         /*
-         * ATNGW100 uses 16-bit SDRAM interface, so we don't need to
-         * reserve any pins for it.
+         * ATNGW100 mkII uses 32-bit SDRAM interface. Reserve the
+         * SDRAM-specific pins so that nobody messes with them.
          */
+#ifdef CONFIG_BOARD_ATNGW100_MKII
+        at32_reserve_pin(GPIO_PIOE_BASE, ATMEL_EBI_PE_DATA_ALL);
+
+        smc_set_timing(&nand_config, &nand_timing);
+        smc_set_configuration(3, &nand_config);
+        at32_add_device_nand(0, &atngw100mkii_nand_data);
+#endif
 
         at32_add_device_usart(0);
 
         set_hw_addr(at32_add_device_eth(0, &eth_data[0]));
+#ifndef CONFIG_BOARD_ATNGW100_MKII_LCD
         set_hw_addr(at32_add_device_eth(1, &eth_data[1]));
+#endif
 
         at32_add_device_spi(0, spi0_board_info, ARRAY_SIZE(spi0_board_info));
         at32_add_device_mci(0, &mci0_data);
-        at32_add_device_usba(0, NULL);
+        at32_add_device_usba(0, &atngw100_usba_data);
 
         for (i = 0; i < ARRAY_SIZE(ngw_leds); i++) {
                 at32_select_gpio(ngw_leds[i].gpio,
@@ -194,10 +281,14 @@ static int __init atngw100_init(void)
 
         /* all these i2c/smbus pins should have external pullups for
          * open-drain sharing among all I2C devices.  SDA and SCL do;
-         * PB28/EXTINT3 doesn't; it should be SMBALERT# (for PMBus),
-         * but it's not available off-board.
+         * PB28/EXTINT3 (ATNGW100) and PE21 (ATNGW100 mkII) doesn't; it should
+         * be SMBALERT# (for PMBus), but it's not available off-board.
          */
+#ifdef CONFIG_BOARD_ATNGW100_MKII
+        at32_select_periph(GPIO_PIOE_BASE, 1 << 21, 0, AT32_GPIOF_PULLUP);
+#else
         at32_select_periph(GPIO_PIOB_BASE, 1 << 28, 0, AT32_GPIOF_PULLUP);
+#endif
         at32_select_gpio(i2c_gpio_data.sda_pin,
                 AT32_GPIOF_MULTIDRV | AT32_GPIOF_OUTPUT | AT32_GPIOF_HIGH);
         at32_select_gpio(i2c_gpio_data.scl_pin,
@@ -211,14 +302,22 @@ postcore_initcall(atngw100_init);
 
 static int __init atngw100_arch_init(void)
 {
-        /* PB30 is the otherwise unused jumper on the mainboard, with an
-         * external pullup; the jumper grounds it.  Use it however you
-         * like, including letting U-Boot or Linux tweak boot sequences.
+        /* PB30 (ATNGW100) and PE30 (ATNGW100 mkII) is the otherwise unused
+         * jumper on the mainboard, with an external pullup; the jumper grounds
+         * it. Use it however you like, including letting U-Boot or Linux tweak
+         * boot sequences.
          */
+#ifdef CONFIG_BOARD_ATNGW100_MKII
+        at32_select_gpio(GPIO_PIN_PE(30), 0);
+        gpio_request(GPIO_PIN_PE(30), "j15");
+        gpio_direction_input(GPIO_PIN_PE(30));
+        gpio_export(GPIO_PIN_PE(30), false);
+#else
         at32_select_gpio(GPIO_PIN_PB(30), 0);
         gpio_request(GPIO_PIN_PB(30), "j15");
         gpio_direction_input(GPIO_PIN_PB(30));
         gpio_export(GPIO_PIN_PB(30), false);
+#endif
 
         /* set_irq_type() after the arch_initcall for EIC has run, and
          * before the I2C subsystem could try using this IRQ.
diff --git a/arch/avr32/configs/atngw100_defconfig b/arch/avr32/configs/atngw100_defconfig
index 574aca975334..32205c9d37d4 100644
--- a/arch/avr32/configs/atngw100_defconfig
+++ b/arch/avr32/configs/atngw100_defconfig
@@ -1,7 +1,7 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.27-rc1
-# Tue Aug  5 16:00:47 2008
+# Linux kernel version: 2.6.32-rc5
+# Thu Oct 29 09:39:22 2009
 #
 CONFIG_AVR32=y
 CONFIG_GENERIC_GPIO=y
@@ -21,6 +21,7 @@ CONFIG_GENERIC_HWEIGHT=y
 CONFIG_GENERIC_CALIBRATE_DELAY=y
 CONFIG_GENERIC_BUG=y
 CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+CONFIG_CONSTRUCTORS=y
 
 #
 # General setup
@@ -34,22 +35,37 @@ CONFIG_SWAP=y
 CONFIG_SYSVIPC=y
 CONFIG_SYSVIPC_SYSCTL=y
 CONFIG_POSIX_MQUEUE=y
+CONFIG_POSIX_MQUEUE_SYSCTL=y
 CONFIG_BSD_PROCESS_ACCT=y
 CONFIG_BSD_PROCESS_ACCT_V3=y
 # CONFIG_TASKSTATS is not set
 # CONFIG_AUDIT is not set
+
+#
+# RCU Subsystem
+#
+CONFIG_TREE_RCU=y
+# CONFIG_TREE_PREEMPT_RCU is not set
+# CONFIG_RCU_TRACE is not set
+CONFIG_RCU_FANOUT=32
+# CONFIG_RCU_FANOUT_EXACT is not set
+# CONFIG_TREE_RCU_TRACE is not set
 # CONFIG_IKCONFIG is not set
 CONFIG_LOG_BUF_SHIFT=14
-# CONFIG_CGROUPS is not set
 # CONFIG_GROUP_SCHED is not set
+# CONFIG_CGROUPS is not set
 CONFIG_SYSFS_DEPRECATED=y
 CONFIG_SYSFS_DEPRECATED_V2=y
 # CONFIG_RELAY is not set
 # CONFIG_NAMESPACES is not set
 CONFIG_BLK_DEV_INITRD=y
 CONFIG_INITRAMFS_SOURCE=""
+CONFIG_RD_GZIP=y
+# CONFIG_RD_BZIP2 is not set
+# CONFIG_RD_LZMA is not set
 CONFIG_CC_OPTIMIZE_FOR_SIZE=y
 CONFIG_SYSCTL=y
+CONFIG_ANON_INODES=y
 CONFIG_EMBEDDED=y
 # CONFIG_SYSCTL_SYSCALL is not set
 CONFIG_KALLSYMS=y
@@ -59,38 +75,40 @@ CONFIG_HOTPLUG=y
 CONFIG_PRINTK=y
 CONFIG_BUG=y
 CONFIG_ELF_CORE=y
-# CONFIG_COMPAT_BRK is not set
 # CONFIG_BASE_FULL is not set
 CONFIG_FUTEX=y
-CONFIG_ANON_INODES=y
 CONFIG_EPOLL=y
 CONFIG_SIGNALFD=y
 CONFIG_TIMERFD=y
 CONFIG_EVENTFD=y
 CONFIG_SHMEM=y
+CONFIG_AIO=y
+
+#
+# Kernel Performance Events And Counters
+#
 CONFIG_VM_EVENT_COUNTERS=y
 CONFIG_SLUB_DEBUG=y
+# CONFIG_COMPAT_BRK is not set
 # CONFIG_SLAB is not set
 CONFIG_SLUB=y
 # CONFIG_SLOB is not set
 CONFIG_PROFILING=y
-# CONFIG_MARKERS is not set
+CONFIG_TRACEPOINTS=y
 CONFIG_OPROFILE=m
 CONFIG_HAVE_OPROFILE=y
 CONFIG_KPROBES=y
-# CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS is not set
-# CONFIG_HAVE_IOREMAP_PROT is not set
 CONFIG_HAVE_KPROBES=y
-# CONFIG_HAVE_KRETPROBES is not set
-# CONFIG_HAVE_ARCH_TRACEHOOK is not set
-# CONFIG_HAVE_DMA_ATTRS is not set
-# CONFIG_USE_GENERIC_SMP_HELPERS is not set
 CONFIG_HAVE_CLK=y
-CONFIG_PROC_PAGE_MONITOR=y
+
+#
+# GCOV-based kernel profiling
+#
+# CONFIG_GCOV_KERNEL is not set
+CONFIG_SLOW_WORK=y
 # CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
 CONFIG_SLABINFO=y
 CONFIG_RT_MUTEXES=y
-# CONFIG_TINY_SHMEM is not set
 CONFIG_BASE_SMALL=1
 CONFIG_MODULES=y
 # CONFIG_MODULE_FORCE_LOAD is not set
@@ -98,11 +116,8 @@ CONFIG_MODULE_UNLOAD=y
 CONFIG_MODULE_FORCE_UNLOAD=y
 # CONFIG_MODVERSIONS is not set
 # CONFIG_MODULE_SRCVERSION_ALL is not set
-CONFIG_KMOD=y
 CONFIG_BLOCK=y
-# CONFIG_LBD is not set
-# CONFIG_BLK_DEV_IO_TRACE is not set
-# CONFIG_LSF is not set
+CONFIG_LBDAF=y
 # CONFIG_BLK_DEV_BSG is not set
 # CONFIG_BLK_DEV_INTEGRITY is not set
 
@@ -118,7 +133,7 @@ CONFIG_IOSCHED_CFQ=y
 CONFIG_DEFAULT_CFQ=y
 # CONFIG_DEFAULT_NOOP is not set
 CONFIG_DEFAULT_IOSCHED="cfq"
-CONFIG_CLASSIC_RCU=y
+CONFIG_FREEZER=y
 
 #
 # System Type and features
@@ -133,8 +148,23 @@ CONFIG_PERFORMANCE_COUNTERS=y
 CONFIG_PLATFORM_AT32AP=y
 CONFIG_CPU_AT32AP700X=y
 CONFIG_CPU_AT32AP7000=y
+CONFIG_BOARD_ATNGW100_COMMON=y
 # CONFIG_BOARD_ATSTK1000 is not set
-CONFIG_BOARD_ATNGW100=y
+CONFIG_BOARD_ATNGW100_MKI=y
+# CONFIG_BOARD_ATNGW100_MKII is not set
+# CONFIG_BOARD_HAMMERHEAD is not set
+# CONFIG_BOARD_FAVR_32 is not set
+# CONFIG_BOARD_MERISC is not set
+# CONFIG_BOARD_MIMC200 is not set
+# CONFIG_BOARD_ATSTK1002 is not set
+# CONFIG_BOARD_ATSTK1003 is not set
+# CONFIG_BOARD_ATSTK1004 is not set
+# CONFIG_BOARD_ATSTK1006 is not set
+# CONFIG_BOARD_ATSTK1000_J2_LED8 is not set
+# CONFIG_BOARD_ATSTK1000_J2_RGB is not set
+CONFIG_BOARD_ATNGW100_ADDON_NONE=y
+# CONFIG_BOARD_ATNGW100_EVKLCD10X is not set
+# CONFIG_BOARD_ATNGW100_MRMT is not set
 CONFIG_LOADER_U_BOOT=y
 
 #
@@ -150,7 +180,7 @@ CONFIG_PREEMPT_NONE=y
 # CONFIG_PREEMPT_VOLUNTARY is not set
 # CONFIG_PREEMPT is not set
 CONFIG_QUICKLIST=y
-# CONFIG_HAVE_ARCH_BOOTMEM_NODE is not set
+# CONFIG_HAVE_ARCH_BOOTMEM is not set
 # CONFIG_ARCH_HAVE_MEMORY_PRESENT is not set
 # CONFIG_NEED_NODE_MEMMAP_SIZE is not set
 CONFIG_ARCH_FLATMEM_ENABLE=y
@@ -162,14 +192,16 @@ CONFIG_FLATMEM_MANUAL=y
 # CONFIG_SPARSEMEM_MANUAL is not set
 CONFIG_FLATMEM=y
 CONFIG_FLAT_NODE_MEM_MAP=y
-# CONFIG_SPARSEMEM_STATIC is not set
-# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
 CONFIG_PAGEFLAGS_EXTENDED=y
 CONFIG_SPLIT_PTLOCK_CPUS=4
-# CONFIG_RESOURCES_64BIT is not set
+# CONFIG_PHYS_ADDR_T_64BIT is not set
 CONFIG_ZONE_DMA_FLAG=0
 CONFIG_NR_QUICK=2
 CONFIG_VIRT_TO_BUS=y
+CONFIG_HAVE_MLOCK=y
+CONFIG_HAVE_MLOCKED_PAGE_BIT=y
+# CONFIG_KSM is not set
+CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
 # CONFIG_OWNERSHIP_TRACE is not set
 CONFIG_NMI_DEBUGGING=y
 # CONFIG_HZ_100 is not set
@@ -177,7 +209,7 @@ CONFIG_HZ_250=y
 # CONFIG_HZ_300 is not set
 # CONFIG_HZ_1000 is not set
 CONFIG_HZ=250
-# CONFIG_SCHED_HRTICK is not set
+CONFIG_SCHED_HRTICK=y
 CONFIG_CMDLINE=""
 
 #
@@ -188,6 +220,7 @@ CONFIG_PM=y
 CONFIG_PM_SLEEP=y
 CONFIG_SUSPEND=y
 CONFIG_SUSPEND_FREEZER=y
+# CONFIG_PM_RUNTIME is not set
 CONFIG_ARCH_SUSPEND_POSSIBLE=y
 
 #
@@ -219,6 +252,8 @@ CONFIG_CPU_FREQ_AT32AP=y
 # Executable file formats
 #
 CONFIG_BINFMT_ELF=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+# CONFIG_HAVE_AOUT is not set
 # CONFIG_BINFMT_MISC is not set
 CONFIG_NET=y
 
@@ -271,7 +306,6 @@ CONFIG_INET_TCP_DIAG=y
 CONFIG_TCP_CONG_CUBIC=y
 CONFIG_DEFAULT_TCP_CONG="cubic"
 # CONFIG_TCP_MD5SIG is not set
-# CONFIG_IP_VS is not set
 CONFIG_IPV6=y
 # CONFIG_IPV6_PRIVACY is not set
 # CONFIG_IPV6_ROUTER_PREF is not set
@@ -314,10 +348,12 @@ CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
 CONFIG_NETFILTER_XT_MATCH_MARK=m
 CONFIG_NETFILTER_XT_MATCH_POLICY=m
 CONFIG_NETFILTER_XT_MATCH_STATE=m
+# CONFIG_IP_VS is not set
 
 #
 # IP: Netfilter Configuration
 #
+CONFIG_NF_DEFRAG_IPV4=m
 CONFIG_NF_CONNTRACK_IPV4=m
 CONFIG_NF_CONNTRACK_PROC_COMPAT=y
 CONFIG_IP_NF_IPTABLES=m
@@ -343,16 +379,18 @@ CONFIG_IP_NF_MANGLE=m
 CONFIG_NF_CONNTRACK_IPV6=m
 CONFIG_IP6_NF_IPTABLES=m
 CONFIG_IP6_NF_MATCH_IPV6HEADER=m
-CONFIG_IP6_NF_FILTER=m
 CONFIG_IP6_NF_TARGET_LOG=m
+CONFIG_IP6_NF_FILTER=m
 CONFIG_IP6_NF_TARGET_REJECT=m
 CONFIG_IP6_NF_MANGLE=m
 # CONFIG_IP_DCCP is not set
 # CONFIG_IP_SCTP is not set
+# CONFIG_RDS is not set
 # CONFIG_TIPC is not set
 # CONFIG_ATM is not set
 CONFIG_STP=m
 CONFIG_BRIDGE=m
+# CONFIG_NET_DSA is not set
 CONFIG_VLAN_8021Q=m
 # CONFIG_VLAN_8021Q_GVRP is not set
 # CONFIG_DECNET is not set
@@ -364,26 +402,33 @@ CONFIG_LLC=m
 # CONFIG_LAPB is not set
 # CONFIG_ECONET is not set
 # CONFIG_WAN_ROUTER is not set
+# CONFIG_PHONET is not set
+# CONFIG_IEEE802154 is not set
 # CONFIG_NET_SCHED is not set
+# CONFIG_DCB is not set
 
 #
 # Network testing
 #
 # CONFIG_NET_PKTGEN is not set
 # CONFIG_NET_TCPPROBE is not set
+# CONFIG_NET_DROP_MONITOR is not set
 # CONFIG_HAMRADIO is not set
 # CONFIG_CAN is not set
 # CONFIG_IRDA is not set
 # CONFIG_BT is not set
 # CONFIG_AF_RXRPC is not set
+CONFIG_WIRELESS=y
+# CONFIG_CFG80211 is not set
+CONFIG_CFG80211_DEFAULT_PS_VALUE=0
+# CONFIG_WIRELESS_OLD_REGULATORY is not set
+# CONFIG_WIRELESS_EXT is not set
+# CONFIG_LIB80211 is not set
 
 #
-# Wireless
+# CFG80211 needs to be enabled for MAC80211
 #
-# CONFIG_CFG80211 is not set
-# CONFIG_WIRELESS_EXT is not set
-# CONFIG_MAC80211 is not set
-# CONFIG_IEEE80211 is not set
+# CONFIG_WIMAX is not set
 # CONFIG_RFKILL is not set
 # CONFIG_NET_9P is not set
 
@@ -395,6 +440,7 @@ CONFIG_LLC=m
 # Generic Driver Options
 #
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+# CONFIG_DEVTMPFS is not set
 CONFIG_STANDALONE=y
 # CONFIG_PREVENT_FIRMWARE_BUILD is not set
 # CONFIG_FW_LOADER is not set
@@ -404,6 +450,7 @@ CONFIG_STANDALONE=y
 # CONFIG_CONNECTOR is not set
 CONFIG_MTD=y
 # CONFIG_MTD_DEBUG is not set
+# CONFIG_MTD_TESTS is not set
 # CONFIG_MTD_CONCAT is not set
 CONFIG_MTD_PARTITIONS=y
 # CONFIG_MTD_REDBOOT_PARTS is not set
@@ -453,16 +500,17 @@ CONFIG_MTD_CFI_UTIL=y
 #
 # CONFIG_MTD_COMPLEX_MAPPINGS is not set
 CONFIG_MTD_PHYSMAP=y
-CONFIG_MTD_PHYSMAP_START=0x80000000
-CONFIG_MTD_PHYSMAP_LEN=0x0
-CONFIG_MTD_PHYSMAP_BANKWIDTH=2
+# CONFIG_MTD_PHYSMAP_COMPAT is not set
 # CONFIG_MTD_PLATRAM is not set
 
 #
 # Self-contained MTD device drivers
 #
 CONFIG_MTD_DATAFLASH=y
+# CONFIG_MTD_DATAFLASH_WRITE_VERIFY is not set
+# CONFIG_MTD_DATAFLASH_OTP is not set
 # CONFIG_MTD_M25P80 is not set
+# CONFIG_MTD_SST25L is not set
 # CONFIG_MTD_SLRAM is not set
 # CONFIG_MTD_PHRAM is not set
 # CONFIG_MTD_MTDRAM is not set
@@ -478,9 +526,22 @@ CONFIG_MTD_DATAFLASH=y
 # CONFIG_MTD_ONENAND is not set
 
 #
+# LPDDR flash memory drivers
+#
+# CONFIG_MTD_LPDDR is not set
+
+#
 # UBI - Unsorted block images
 #
-# CONFIG_MTD_UBI is not set
+CONFIG_MTD_UBI=y
+CONFIG_MTD_UBI_WL_THRESHOLD=4096
+CONFIG_MTD_UBI_BEB_RESERVE=1
+# CONFIG_MTD_UBI_GLUEBI is not set
+
+#
+# UBI debugging options
+#
+# CONFIG_MTD_UBI_DEBUG is not set
 # CONFIG_PARPORT is not set
 CONFIG_BLK_DEV=y
 # CONFIG_BLK_DEV_COW_COMMON is not set
@@ -498,10 +559,20 @@ CONFIG_MISC_DEVICES=y
 CONFIG_ATMEL_TCLIB=y
 CONFIG_ATMEL_TCB_CLKSRC=y
 CONFIG_ATMEL_TCB_CLKSRC_BLOCK=0
-# CONFIG_EEPROM_93CX6 is not set
+# CONFIG_ICS932S401 is not set
 # CONFIG_ATMEL_SSC is not set
 # CONFIG_ENCLOSURE_SERVICES is not set
-# CONFIG_HAVE_IDE is not set
+# CONFIG_ISL29003 is not set
+# CONFIG_C2PORT is not set
+
+#
+# EEPROM support
+#
+CONFIG_EEPROM_AT24=m
+# CONFIG_EEPROM_AT25 is not set
+# CONFIG_EEPROM_LEGACY is not set
+# CONFIG_EEPROM_MAX6875 is not set
+# CONFIG_EEPROM_93CX6 is not set
 
 #
 # SCSI device support
@@ -534,26 +605,37 @@ CONFIG_PHYLIB=y
 # CONFIG_BROADCOM_PHY is not set
 # CONFIG_ICPLUS_PHY is not set
 # CONFIG_REALTEK_PHY is not set
+# CONFIG_NATIONAL_PHY is not set
+# CONFIG_STE10XP is not set
+# CONFIG_LSI_ET1011C_PHY is not set
 # CONFIG_FIXED_PHY is not set
 # CONFIG_MDIO_BITBANG is not set
 CONFIG_NET_ETHERNET=y
 # CONFIG_MII is not set
 CONFIG_MACB=y
 # CONFIG_ENC28J60 is not set
+# CONFIG_ETHOC is not set
+# CONFIG_DNET is not set
 # CONFIG_IBM_NEW_EMAC_ZMII is not set
 # CONFIG_IBM_NEW_EMAC_RGMII is not set
 # CONFIG_IBM_NEW_EMAC_TAH is not set
 # CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
+# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
+# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
 # CONFIG_B44 is not set
+# CONFIG_KS8842 is not set
+# CONFIG_KS8851 is not set
+# CONFIG_KS8851_MLL is not set
 # CONFIG_NETDEV_1000 is not set
 # CONFIG_NETDEV_10000 is not set
+CONFIG_WLAN=y
+# CONFIG_WLAN_PRE80211 is not set
+# CONFIG_WLAN_80211 is not set
 
 #
-# Wireless LAN
+# Enable WiMAX (Networking options) to see the WiMAX drivers
 #
-# CONFIG_WLAN_PRE80211 is not set
-# CONFIG_WLAN_80211 is not set
-# CONFIG_IWLWIFI_LEDS is not set
 # CONFIG_WAN is not set
 CONFIG_PPP=m
 # CONFIG_PPP_MULTILINK is not set
@@ -603,9 +685,11 @@ CONFIG_SERIAL_ATMEL=y
 CONFIG_SERIAL_ATMEL_CONSOLE=y
 CONFIG_SERIAL_ATMEL_PDC=y
 # CONFIG_SERIAL_ATMEL_TTYAT is not set
+# CONFIG_SERIAL_MAX3100 is not set
 CONFIG_SERIAL_CORE=y
 CONFIG_SERIAL_CORE_CONSOLE=y
 CONFIG_UNIX98_PTYS=y
+# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
 # CONFIG_LEGACY_PTYS is not set
 # CONFIG_IPMI_HANDLER is not set
 # CONFIG_HW_RANDOM is not set
@@ -614,7 +698,9 @@ CONFIG_UNIX98_PTYS=y
 # CONFIG_TCG_TPM is not set
 CONFIG_I2C=m
 CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_COMPAT=y
 CONFIG_I2C_CHARDEV=m
+CONFIG_I2C_HELPER_AUTO=y
 CONFIG_I2C_ALGOBIT=m
 
 #
@@ -624,6 +710,7 @@ CONFIG_I2C_ALGOBIT=m
 #
 # I2C system bus drivers (mostly embedded / system-on-chip)
 #
+# CONFIG_I2C_DESIGNWARE is not set
 CONFIG_I2C_GPIO=m
 # CONFIG_I2C_OCORES is not set
 # CONFIG_I2C_SIMTEC is not set
@@ -644,14 +731,6 @@ CONFIG_I2C_GPIO=m
 # Miscellaneous I2C Chip support
 #
 # CONFIG_DS1682 is not set
-CONFIG_EEPROM_AT24=m
-# CONFIG_EEPROM_LEGACY is not set
-# CONFIG_SENSORS_PCF8574 is not set
-# CONFIG_PCF8575 is not set
-# CONFIG_SENSORS_PCA9539 is not set
-# CONFIG_SENSORS_PCF8591 is not set
-# CONFIG_TPS65010 is not set
-# CONFIG_SENSORS_MAX6875 is not set
 # CONFIG_SENSORS_TSL2550 is not set
 # CONFIG_I2C_DEBUG_CORE is not set
 # CONFIG_I2C_DEBUG_ALGO is not set
@@ -666,19 +745,28 @@ CONFIG_SPI_MASTER=y
 #
 CONFIG_SPI_ATMEL=y
 # CONFIG_SPI_BITBANG is not set
+# CONFIG_SPI_GPIO is not set
 
 #
 # SPI Protocol Masters
 #
-# CONFIG_EEPROM_AT25 is not set
 CONFIG_SPI_SPIDEV=m
 # CONFIG_SPI_TLE62X0 is not set
+
+#
+# PPS support
+#
+# CONFIG_PPS is not set
 CONFIG_ARCH_REQUIRE_GPIOLIB=y
 CONFIG_GPIOLIB=y
 # CONFIG_DEBUG_GPIO is not set
 CONFIG_GPIO_SYSFS=y
 
 #
+# Memory mapped GPIO expanders:
+#
+
+#
 # I2C GPIO expanders:
 #
 # CONFIG_GPIO_MAX732X is not set
@@ -694,11 +782,15 @@ CONFIG_GPIO_SYSFS=y
 #
 # CONFIG_GPIO_MAX7301 is not set
 # CONFIG_GPIO_MCP23S08 is not set
+# CONFIG_GPIO_MC33880 is not set
+
+#
+# AC97 GPIO expanders:
+#
 # CONFIG_W1 is not set
 # CONFIG_POWER_SUPPLY is not set
 # CONFIG_HWMON is not set
 # CONFIG_THERMAL is not set
-# CONFIG_THERMAL_HWMON is not set
 CONFIG_WATCHDOG=y
 # CONFIG_WATCHDOG_NOWAYOUT is not set
 
@@ -707,11 +799,11 @@ CONFIG_WATCHDOG=y
 #
 # CONFIG_SOFT_WATCHDOG is not set
 CONFIG_AT32AP700X_WDT=y
+CONFIG_SSB_POSSIBLE=y
 
 #
 # Sonics Silicon Backplane
 #
-CONFIG_SSB_POSSIBLE=y
 # CONFIG_SSB is not set
 
 #
@@ -720,22 +812,17 @@ CONFIG_SSB_POSSIBLE=y
 # CONFIG_MFD_CORE is not set
 # CONFIG_MFD_SM501 is not set
 # CONFIG_HTC_PASIC3 is not set
-
-#
-# Multimedia devices
-#
-
-#
-# Multimedia core support
-#
-# CONFIG_VIDEO_DEV is not set
-# CONFIG_DVB_CORE is not set
-# CONFIG_VIDEO_MEDIA is not set
-
-#
-# Multimedia drivers
-#
-# CONFIG_DAB is not set
+# CONFIG_TPS65010 is not set
+# CONFIG_MFD_TMIO is not set
+# CONFIG_MFD_WM8400 is not set
+# CONFIG_MFD_WM831X is not set
+# CONFIG_MFD_WM8350_I2C is not set
+# CONFIG_MFD_PCF50633 is not set
+# CONFIG_MFD_MC13783 is not set
+# CONFIG_AB3100_CORE is not set
+# CONFIG_EZX_PCAP is not set
+# CONFIG_REGULATOR is not set
+# CONFIG_MEDIA_SUPPORT is not set
 
 #
 # Graphics support
@@ -756,32 +843,43 @@ CONFIG_USB_SUPPORT=y
 # CONFIG_USB_ARCH_HAS_EHCI is not set
 # CONFIG_USB_OTG_WHITELIST is not set
 # CONFIG_USB_OTG_BLACKLIST_HUB is not set
+# CONFIG_USB_GADGET_MUSB_HDRC is not set
 
 #
-# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
+# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
 #
 CONFIG_USB_GADGET=y
 # CONFIG_USB_GADGET_DEBUG is not set
 # CONFIG_USB_GADGET_DEBUG_FILES is not set
+# CONFIG_USB_GADGET_DEBUG_FS is not set
+CONFIG_USB_GADGET_VBUS_DRAW=2
 CONFIG_USB_GADGET_SELECTED=y
-# CONFIG_USB_GADGET_AMD5536UDC is not set
+# CONFIG_USB_GADGET_AT91 is not set
 CONFIG_USB_GADGET_ATMEL_USBA=y
 CONFIG_USB_ATMEL_USBA=y
 # CONFIG_USB_GADGET_FSL_USB2 is not set
-# CONFIG_USB_GADGET_NET2280 is not set
-# CONFIG_USB_GADGET_PXA25X is not set
-# CONFIG_USB_GADGET_M66592 is not set
-# CONFIG_USB_GADGET_PXA27X is not set
-# CONFIG_USB_GADGET_GOKU is not set
 # CONFIG_USB_GADGET_LH7A40X is not set
 # CONFIG_USB_GADGET_OMAP is not set
+# CONFIG_USB_GADGET_PXA25X is not set
+# CONFIG_USB_GADGET_R8A66597 is not set
+# CONFIG_USB_GADGET_PXA27X is not set
+# CONFIG_USB_GADGET_S3C_HSOTG is not set
+# CONFIG_USB_GADGET_IMX is not set
 # CONFIG_USB_GADGET_S3C2410 is not set
-# CONFIG_USB_GADGET_AT91 is not set
+# CONFIG_USB_GADGET_M66592 is not set
+# CONFIG_USB_GADGET_AMD5536UDC is not set
+# CONFIG_USB_GADGET_FSL_QE is not set
+# CONFIG_USB_GADGET_CI13XXX is not set
+# CONFIG_USB_GADGET_NET2280 is not set
+# CONFIG_USB_GADGET_GOKU is not set
+# CONFIG_USB_GADGET_LANGWELL is not set
 # CONFIG_USB_GADGET_DUMMY_HCD is not set
 CONFIG_USB_GADGET_DUALSPEED=y
 CONFIG_USB_ZERO=m
+# CONFIG_USB_AUDIO is not set
 CONFIG_USB_ETH=m
 CONFIG_USB_ETH_RNDIS=y
+# CONFIG_USB_ETH_EEM is not set
 CONFIG_USB_GADGETFS=m
 CONFIG_USB_FILE_STORAGE=m
 # CONFIG_USB_FILE_STORAGE_TEST is not set
@@ -789,12 +887,18 @@ CONFIG_USB_G_SERIAL=m
 # CONFIG_USB_MIDI_GADGET is not set
 # CONFIG_USB_G_PRINTER is not set
 CONFIG_USB_CDC_COMPOSITE=m
+
+#
+# OTG and related infrastructure
+#
+# CONFIG_USB_GPIO_VBUS is not set
+# CONFIG_NOP_USB_XCEIV is not set
 CONFIG_MMC=y
 # CONFIG_MMC_DEBUG is not set
 # CONFIG_MMC_UNSAFE_RESUME is not set
 
 #
-# MMC/SD Card Drivers
+# MMC/SD/SDIO Card Drivers
 #
 CONFIG_MMC_BLOCK=y
 CONFIG_MMC_BLOCK_BOUNCE=y
@@ -802,10 +906,12 @@ CONFIG_MMC_BLOCK_BOUNCE=y
 CONFIG_MMC_TEST=m
 
 #
-# MMC/SD Host Controller Drivers
+# MMC/SD/SDIO Host Controller Drivers
 #
 # CONFIG_MMC_SDHCI is not set
+# CONFIG_MMC_AT91 is not set
 CONFIG_MMC_ATMELMCI=y
+# CONFIG_MMC_ATMELMCI_DMA is not set
 CONFIG_MMC_SPI=m
 # CONFIG_MEMSTICK is not set
 CONFIG_NEW_LEDS=y
@@ -815,7 +921,11 @@ CONFIG_LEDS_CLASS=y
 # LED drivers
 #
 CONFIG_LEDS_GPIO=y
+CONFIG_LEDS_GPIO_PLATFORM=y
+# CONFIG_LEDS_LP3944 is not set
 # CONFIG_LEDS_PCA955X is not set
+# CONFIG_LEDS_DAC124S085 is not set
+# CONFIG_LEDS_BD2802 is not set
 
 #
 # LED Triggers
@@ -823,7 +933,13 @@ CONFIG_LEDS_GPIO=y
 CONFIG_LEDS_TRIGGERS=y
 CONFIG_LEDS_TRIGGER_TIMER=y
 CONFIG_LEDS_TRIGGER_HEARTBEAT=y
+# CONFIG_LEDS_TRIGGER_BACKLIGHT is not set
+# CONFIG_LEDS_TRIGGER_GPIO is not set
 CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
+
+#
+# iptables trigger is under Netfilter config (LED target)
+#
 # CONFIG_ACCESSIBILITY is not set
 CONFIG_RTC_LIB=y
 CONFIG_RTC_CLASS=y
@@ -855,25 +971,33 @@ CONFIG_RTC_INTF_DEV=y
 # CONFIG_RTC_DRV_M41T80 is not set
 # CONFIG_RTC_DRV_S35390A is not set
 # CONFIG_RTC_DRV_FM3130 is not set
+# CONFIG_RTC_DRV_RX8581 is not set
+# CONFIG_RTC_DRV_RX8025 is not set
 
 #
 # SPI RTC drivers
 #
 # CONFIG_RTC_DRV_M41T94 is not set
 # CONFIG_RTC_DRV_DS1305 is not set
+# CONFIG_RTC_DRV_DS1390 is not set
 # CONFIG_RTC_DRV_MAX6902 is not set
 # CONFIG_RTC_DRV_R9701 is not set
 # CONFIG_RTC_DRV_RS5C348 is not set
+# CONFIG_RTC_DRV_DS3234 is not set
+# CONFIG_RTC_DRV_PCF2123 is not set
 
 #
 # Platform RTC drivers
 #
+# CONFIG_RTC_DRV_DS1286 is not set
 # CONFIG_RTC_DRV_DS1511 is not set
 # CONFIG_RTC_DRV_DS1553 is not set
 # CONFIG_RTC_DRV_DS1742 is not set
 # CONFIG_RTC_DRV_STK17TA8 is not set
 # CONFIG_RTC_DRV_M48T86 is not set
+# CONFIG_RTC_DRV_M48T35 is not set
 # CONFIG_RTC_DRV_M48T59 is not set
+# CONFIG_RTC_DRV_BQ4802 is not set
 # CONFIG_RTC_DRV_V3020 is not set
 
 #
@@ -892,24 +1016,38 @@ CONFIG_DMA_ENGINE=y
 # DMA Clients
 #
 # CONFIG_NET_DMA is not set
+# CONFIG_ASYNC_TX_DMA is not set
 # CONFIG_DMATEST is not set
+# CONFIG_AUXDISPLAY is not set
 # CONFIG_UIO is not set
 
 #
+# TI VLYNQ
+#
+# CONFIG_STAGING is not set
+
+#
 # File systems
 #
-CONFIG_EXT2_FS=m
+CONFIG_EXT2_FS=y
 # CONFIG_EXT2_FS_XATTR is not set
 # CONFIG_EXT2_FS_XIP is not set
-CONFIG_EXT3_FS=m
+CONFIG_EXT3_FS=y
+# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
 # CONFIG_EXT3_FS_XATTR is not set
-# CONFIG_EXT4DEV_FS is not set
-CONFIG_JBD=m
+# CONFIG_EXT4_FS is not set
+CONFIG_JBD=y
+# CONFIG_JBD_DEBUG is not set
 # CONFIG_REISERFS_FS is not set
 # CONFIG_JFS_FS is not set
 # CONFIG_FS_POSIX_ACL is not set
 # CONFIG_XFS_FS is not set
+# CONFIG_GFS2_FS is not set
 # CONFIG_OCFS2_FS is not set
+# CONFIG_BTRFS_FS is not set
+# CONFIG_NILFS2_FS is not set
+CONFIG_FILE_LOCKING=y
+CONFIG_FSNOTIFY=y
 # CONFIG_DNOTIFY is not set
 CONFIG_INOTIFY=y
 CONFIG_INOTIFY_USER=y
@@ -917,6 +1055,12 @@ CONFIG_INOTIFY_USER=y
 # CONFIG_AUTOFS_FS is not set
 # CONFIG_AUTOFS4_FS is not set
 CONFIG_FUSE_FS=m
+# CONFIG_CUSE is not set
+
+#
+# Caches
+#
+# CONFIG_FSCACHE is not set
 
 #
 # CD-ROM/DVD Filesystems
@@ -940,15 +1084,13 @@ CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
 CONFIG_PROC_FS=y
 # CONFIG_PROC_KCORE is not set
 CONFIG_PROC_SYSCTL=y
+CONFIG_PROC_PAGE_MONITOR=y
 CONFIG_SYSFS=y
 CONFIG_TMPFS=y
 # CONFIG_TMPFS_POSIX_ACL is not set
 # CONFIG_HUGETLB_PAGE is not set
 CONFIG_CONFIGFS_FS=m
-
-#
-# Miscellaneous filesystems
-#
+CONFIG_MISC_FILESYSTEMS=y
 # CONFIG_ADFS_FS is not set
 # CONFIG_AFFS_FS is not set
 # CONFIG_HFS_FS is not set
@@ -967,7 +1109,9 @@ CONFIG_JFFS2_ZLIB=y
 # CONFIG_JFFS2_LZO is not set
 CONFIG_JFFS2_RTIME=y
 # CONFIG_JFFS2_RUBIN is not set
+# CONFIG_UBIFS_FS is not set
 # CONFIG_CRAMFS is not set
+# CONFIG_SQUASHFS is not set
 # CONFIG_VXFS_FS is not set
 # CONFIG_MINIX_FS is not set
 # CONFIG_OMFS_FS is not set
@@ -975,7 +1119,9 @@ CONFIG_JFFS2_RTIME=y
 # CONFIG_QNX4FS_FS is not set
 # CONFIG_ROMFS_FS is not set
 # CONFIG_SYSV_FS is not set
-# CONFIG_UFS_FS is not set
+CONFIG_UFS_FS=y
+# CONFIG_UFS_FS_WRITE is not set
+# CONFIG_UFS_DEBUG is not set
 CONFIG_NETWORK_FILESYSTEMS=y
 CONFIG_NFS_FS=y
 CONFIG_NFS_V3=y
@@ -1060,14 +1206,18 @@ CONFIG_ENABLE_WARN_DEPRECATED=y
 CONFIG_ENABLE_MUST_CHECK=y
 CONFIG_FRAME_WARN=1024
 CONFIG_MAGIC_SYSRQ=y
+# CONFIG_STRIP_ASM_SYMS is not set
 # CONFIG_UNUSED_SYMBOLS is not set
-# CONFIG_DEBUG_FS is not set
+CONFIG_DEBUG_FS=y
 # CONFIG_HEADERS_CHECK is not set
 CONFIG_DEBUG_KERNEL=y
 # CONFIG_DEBUG_SHIRQ is not set
 CONFIG_DETECT_SOFTLOCKUP=y
 # CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
 CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
+CONFIG_DETECT_HUNG_TASK=y
+# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set
+CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0
 CONFIG_SCHED_DEBUG=y
 # CONFIG_SCHEDSTATS is not set
 # CONFIG_TIMER_STATS is not set
@@ -1083,6 +1233,7 @@ CONFIG_SCHED_DEBUG=y
 # CONFIG_LOCK_STAT is not set
 # CONFIG_DEBUG_SPINLOCK_SLEEP is not set
 # CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+CONFIG_STACKTRACE=y
 # CONFIG_DEBUG_KOBJECT is not set
 CONFIG_DEBUG_BUGVERBOSE=y
 # CONFIG_DEBUG_INFO is not set
@@ -1091,13 +1242,39 @@ CONFIG_DEBUG_BUGVERBOSE=y
 # CONFIG_DEBUG_MEMORY_INIT is not set
 # CONFIG_DEBUG_LIST is not set
 # CONFIG_DEBUG_SG is not set
+# CONFIG_DEBUG_NOTIFIERS is not set
+# CONFIG_DEBUG_CREDENTIALS is not set
 CONFIG_FRAME_POINTER=y
 # CONFIG_BOOT_PRINTK_DELAY is not set
 # CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_RCU_CPU_STALL_DETECTOR is not set
 # CONFIG_KPROBES_SANITY_TEST is not set
 # CONFIG_BACKTRACE_SELF_TEST is not set
+# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
+# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
 # CONFIG_LKDTM is not set
 # CONFIG_FAULT_INJECTION is not set
+# CONFIG_PAGE_POISONING is not set
+CONFIG_NOP_TRACER=y
+CONFIG_RING_BUFFER=y
+CONFIG_EVENT_TRACING=y
+CONFIG_CONTEXT_SWITCH_TRACER=y
+CONFIG_RING_BUFFER_ALLOW_SWAP=y
+CONFIG_TRACING=y
+CONFIG_TRACING_SUPPORT=y
+CONFIG_FTRACE=y
+# CONFIG_IRQSOFF_TRACER is not set
+# CONFIG_SCHED_TRACER is not set
+# CONFIG_ENABLE_DEFAULT_TRACERS is not set
+# CONFIG_BOOT_TRACER is not set
+CONFIG_BRANCH_PROFILE_NONE=y
+# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set
+# CONFIG_PROFILE_ALL_BRANCHES is not set
+# CONFIG_KMEMTRACE is not set
+# CONFIG_WORKQUEUE_TRACER is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_RING_BUFFER_BENCHMARK is not set
+# CONFIG_DYNAMIC_DEBUG is not set
 # CONFIG_SAMPLES is not set
 
 #
@@ -1105,19 +1282,30 @@ CONFIG_FRAME_POINTER=y
 #
 # CONFIG_KEYS is not set
 # CONFIG_SECURITY is not set
+# CONFIG_SECURITYFS is not set
 # CONFIG_SECURITY_FILE_CAPABILITIES is not set
 CONFIG_CRYPTO=y
 
 #
 # Crypto core or helper
 #
+# CONFIG_CRYPTO_FIPS is not set
 CONFIG_CRYPTO_ALGAPI=y
+CONFIG_CRYPTO_ALGAPI2=y
 CONFIG_CRYPTO_AEAD=y
+CONFIG_CRYPTO_AEAD2=y
 CONFIG_CRYPTO_BLKCIPHER=y
+CONFIG_CRYPTO_BLKCIPHER2=y
 CONFIG_CRYPTO_HASH=y
+CONFIG_CRYPTO_HASH2=y
+CONFIG_CRYPTO_RNG=m
+CONFIG_CRYPTO_RNG2=y
+CONFIG_CRYPTO_PCOMP=y
 CONFIG_CRYPTO_MANAGER=y
+CONFIG_CRYPTO_MANAGER2=y
 # CONFIG_CRYPTO_GF128MUL is not set
 # CONFIG_CRYPTO_NULL is not set
+CONFIG_CRYPTO_WORKQUEUE=y
 # CONFIG_CRYPTO_CRYPTD is not set
 CONFIG_CRYPTO_AUTHENC=y
 # CONFIG_CRYPTO_TEST is not set
@@ -1145,11 +1333,13 @@ CONFIG_CRYPTO_PCBC=m
 #
 CONFIG_CRYPTO_HMAC=y
 # CONFIG_CRYPTO_XCBC is not set
+# CONFIG_CRYPTO_VMAC is not set
 
 #
 # Digest
 #
 # CONFIG_CRYPTO_CRC32C is not set
+# CONFIG_CRYPTO_GHASH is not set
 # CONFIG_CRYPTO_MD4 is not set
 CONFIG_CRYPTO_MD5=y
 # CONFIG_CRYPTO_MICHAEL_MIC is not set
@@ -1166,7 +1356,7 @@ CONFIG_CRYPTO_SHA1=y
 #
 # Ciphers
 #
-# CONFIG_CRYPTO_AES is not set
+CONFIG_CRYPTO_AES=m
 # CONFIG_CRYPTO_ANUBIS is not set
 CONFIG_CRYPTO_ARC4=m
 # CONFIG_CRYPTO_BLOWFISH is not set
@@ -1186,15 +1376,21 @@ CONFIG_CRYPTO_DES=y
 # Compression
 #
 CONFIG_CRYPTO_DEFLATE=y
+# CONFIG_CRYPTO_ZLIB is not set
 # CONFIG_CRYPTO_LZO is not set
+
+#
+# Random Number Generation
+#
+CONFIG_CRYPTO_ANSI_CPRNG=m
 CONFIG_CRYPTO_HW=y
+CONFIG_BINARY_PRINTF=y
 
 #
 # Library routines
 #
 CONFIG_BITREVERSE=y
-# CONFIG_GENERIC_FIND_FIRST_BIT is not set
-# CONFIG_GENERIC_FIND_NEXT_BIT is not set
+CONFIG_GENERIC_FIND_LAST_BIT=y
 CONFIG_CRC_CCITT=m
 # CONFIG_CRC16 is not set
 # CONFIG_CRC_T10DIF is not set
@@ -1204,8 +1400,9 @@ CONFIG_CRC7=m
 # CONFIG_LIBCRC32C is not set
 CONFIG_ZLIB_INFLATE=y
 CONFIG_ZLIB_DEFLATE=y
+CONFIG_DECOMPRESS_GZIP=y
 CONFIG_GENERIC_ALLOCATOR=y
-CONFIG_PLIST=y
 CONFIG_HAS_IOMEM=y
 CONFIG_HAS_IOPORT=y
 CONFIG_HAS_DMA=y
+CONFIG_NLATTR=y
diff --git a/arch/avr32/configs/atngw100_evklcd100_defconfig b/arch/avr32/configs/atngw100_evklcd100_defconfig
index 86a45b5c9d0d..c732cc397ad0 100644
--- a/arch/avr32/configs/atngw100_evklcd100_defconfig
+++ b/arch/avr32/configs/atngw100_evklcd100_defconfig
@@ -1,7 +1,7 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.25.6
-# Wed Jun 18 16:06:32 2008
+# Linux kernel version: 2.6.32-rc5
+# Thu Oct 29 09:36:39 2009
 #
 CONFIG_AVR32=y
 CONFIG_GENERIC_GPIO=y
@@ -21,6 +21,7 @@ CONFIG_GENERIC_HWEIGHT=y
 CONFIG_GENERIC_CALIBRATE_DELAY=y
 CONFIG_GENERIC_BUG=y
 CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+CONFIG_CONSTRUCTORS=y
 
 #
 # General setup
@@ -34,22 +35,37 @@ CONFIG_SWAP=y
 CONFIG_SYSVIPC=y
 CONFIG_SYSVIPC_SYSCTL=y
 CONFIG_POSIX_MQUEUE=y
+CONFIG_POSIX_MQUEUE_SYSCTL=y
 CONFIG_BSD_PROCESS_ACCT=y
 CONFIG_BSD_PROCESS_ACCT_V3=y
 # CONFIG_TASKSTATS is not set
 # CONFIG_AUDIT is not set
+
+#
+# RCU Subsystem
+#
+CONFIG_TREE_RCU=y
+# CONFIG_TREE_PREEMPT_RCU is not set
+# CONFIG_RCU_TRACE is not set
+CONFIG_RCU_FANOUT=32
+# CONFIG_RCU_FANOUT_EXACT is not set
+# CONFIG_TREE_RCU_TRACE is not set
 # CONFIG_IKCONFIG is not set
 CONFIG_LOG_BUF_SHIFT=14
-# CONFIG_CGROUPS is not set
 # CONFIG_GROUP_SCHED is not set
+# CONFIG_CGROUPS is not set
 CONFIG_SYSFS_DEPRECATED=y
 CONFIG_SYSFS_DEPRECATED_V2=y
 # CONFIG_RELAY is not set
 # CONFIG_NAMESPACES is not set
 CONFIG_BLK_DEV_INITRD=y
 CONFIG_INITRAMFS_SOURCE=""
+CONFIG_RD_GZIP=y
+# CONFIG_RD_BZIP2 is not set
+# CONFIG_RD_LZMA is not set
 CONFIG_CC_OPTIMIZE_FOR_SIZE=y
 CONFIG_SYSCTL=y
+CONFIG_ANON_INODES=y
 CONFIG_EMBEDDED=y
 # CONFIG_SYSCTL_SYSCALL is not set
 CONFIG_KALLSYMS=y
@@ -59,43 +75,51 @@ CONFIG_HOTPLUG=y
 CONFIG_PRINTK=y
 CONFIG_BUG=y
 CONFIG_ELF_CORE=y
-# CONFIG_COMPAT_BRK is not set
 # CONFIG_BASE_FULL is not set
 CONFIG_FUTEX=y
-CONFIG_ANON_INODES=y
 CONFIG_EPOLL=y
 CONFIG_SIGNALFD=y
 CONFIG_TIMERFD=y
 CONFIG_EVENTFD=y
 CONFIG_SHMEM=y
+CONFIG_AIO=y
+
+#
+# Kernel Performance Events And Counters
+#
 CONFIG_VM_EVENT_COUNTERS=y
 CONFIG_SLUB_DEBUG=y
+# CONFIG_COMPAT_BRK is not set
 # CONFIG_SLAB is not set
 CONFIG_SLUB=y
 # CONFIG_SLOB is not set
 CONFIG_PROFILING=y
-# CONFIG_MARKERS is not set
+CONFIG_TRACEPOINTS=y
 CONFIG_OPROFILE=m
 CONFIG_HAVE_OPROFILE=y
 CONFIG_KPROBES=y
 CONFIG_HAVE_KPROBES=y
-# CONFIG_HAVE_KRETPROBES is not set
-CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_HAVE_CLK=y
+
+#
+# GCOV-based kernel profiling
+#
+# CONFIG_GCOV_KERNEL is not set
+CONFIG_SLOW_WORK=y
+# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
 CONFIG_SLABINFO=y
 CONFIG_RT_MUTEXES=y
-# CONFIG_TINY_SHMEM is not set
 CONFIG_BASE_SMALL=1
 CONFIG_MODULES=y
+# CONFIG_MODULE_FORCE_LOAD is not set
 CONFIG_MODULE_UNLOAD=y
 CONFIG_MODULE_FORCE_UNLOAD=y
 # CONFIG_MODVERSIONS is not set
 # CONFIG_MODULE_SRCVERSION_ALL is not set
-CONFIG_KMOD=y
 CONFIG_BLOCK=y
-# CONFIG_LBD is not set
-# CONFIG_BLK_DEV_IO_TRACE is not set
-# CONFIG_LSF is not set
+CONFIG_LBDAF=y
 # CONFIG_BLK_DEV_BSG is not set
+# CONFIG_BLK_DEV_INTEGRITY is not set
 
 #
 # IO Schedulers
@@ -109,7 +133,7 @@ CONFIG_IOSCHED_CFQ=y
 CONFIG_DEFAULT_CFQ=y
 # CONFIG_DEFAULT_NOOP is not set
 CONFIG_DEFAULT_IOSCHED="cfq"
-CONFIG_CLASSIC_RCU=y
+CONFIG_FREEZER=y
 
 #
 # System Type and features
@@ -124,13 +148,26 @@ CONFIG_PERFORMANCE_COUNTERS=y
 CONFIG_PLATFORM_AT32AP=y
 CONFIG_CPU_AT32AP700X=y
 CONFIG_CPU_AT32AP7000=y
+CONFIG_BOARD_ATNGW100_COMMON=y
 # CONFIG_BOARD_ATSTK1000 is not set
-CONFIG_BOARD_ATNGW100=y
+CONFIG_BOARD_ATNGW100_MKI=y
+# CONFIG_BOARD_ATNGW100_MKII is not set
+# CONFIG_BOARD_HAMMERHEAD is not set
+# CONFIG_BOARD_FAVR_32 is not set
+# CONFIG_BOARD_MERISC is not set
+# CONFIG_BOARD_MIMC200 is not set
+# CONFIG_BOARD_ATSTK1002 is not set
+# CONFIG_BOARD_ATSTK1003 is not set
+# CONFIG_BOARD_ATSTK1004 is not set
+# CONFIG_BOARD_ATSTK1006 is not set
+# CONFIG_BOARD_ATSTK1000_J2_LED8 is not set
+# CONFIG_BOARD_ATSTK1000_J2_RGB is not set
+# CONFIG_BOARD_ATNGW100_ADDON_NONE is not set
 CONFIG_BOARD_ATNGW100_EVKLCD10X=y
+# CONFIG_BOARD_ATNGW100_MRMT is not set
 CONFIG_BOARD_ATNGW100_EVKLCD10X_QVGA=y
 # CONFIG_BOARD_ATNGW100_EVKLCD10X_VGA is not set
 # CONFIG_BOARD_ATNGW100_EVKLCD10X_POW_QVGA is not set
-CONFIG_BOARD_ATNGW100_I2C_GPIO=y
 CONFIG_LOADER_U_BOOT=y
 
 #
@@ -139,14 +176,14 @@ CONFIG_LOADER_U_BOOT=y
 # CONFIG_AP700X_32_BIT_SMC is not set
 CONFIG_AP700X_16_BIT_SMC=y
 # CONFIG_AP700X_8_BIT_SMC is not set
-CONFIG_GPIO_DEV=y
 CONFIG_LOAD_ADDRESS=0x10000000
 CONFIG_ENTRY_ADDRESS=0x90000000
 CONFIG_PHYS_OFFSET=0x10000000
 CONFIG_PREEMPT_NONE=y
 # CONFIG_PREEMPT_VOLUNTARY is not set
 # CONFIG_PREEMPT is not set
-# CONFIG_HAVE_ARCH_BOOTMEM_NODE is not set
+CONFIG_QUICKLIST=y
+# CONFIG_HAVE_ARCH_BOOTMEM is not set
 # CONFIG_ARCH_HAVE_MEMORY_PRESENT is not set
 # CONFIG_NEED_NODE_MEMMAP_SIZE is not set
 CONFIG_ARCH_FLATMEM_ENABLE=y
@@ -158,33 +195,36 @@ CONFIG_FLATMEM_MANUAL=y
 # CONFIG_SPARSEMEM_MANUAL is not set
 CONFIG_FLATMEM=y
 CONFIG_FLAT_NODE_MEM_MAP=y
-# CONFIG_SPARSEMEM_STATIC is not set
-# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
+CONFIG_PAGEFLAGS_EXTENDED=y
 CONFIG_SPLIT_PTLOCK_CPUS=4
-# CONFIG_RESOURCES_64BIT is not set
+# CONFIG_PHYS_ADDR_T_64BIT is not set
 CONFIG_ZONE_DMA_FLAG=0
+CONFIG_NR_QUICK=2
 CONFIG_VIRT_TO_BUS=y
+CONFIG_HAVE_MLOCK=y
+CONFIG_HAVE_MLOCKED_PAGE_BIT=y
+# CONFIG_KSM is not set
+CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
 # CONFIG_OWNERSHIP_TRACE is not set
 CONFIG_NMI_DEBUGGING=y
-CONFIG_DW_DMAC=y
 # CONFIG_HZ_100 is not set
 CONFIG_HZ_250=y
 # CONFIG_HZ_300 is not set
 # CONFIG_HZ_1000 is not set
 CONFIG_HZ=250
-# CONFIG_SCHED_HRTICK is not set
+CONFIG_SCHED_HRTICK=y
 CONFIG_CMDLINE=""
 
 #
 # Power management options
 #
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
 CONFIG_PM=y
-# CONFIG_PM_LEGACY is not set
 # CONFIG_PM_DEBUG is not set
 CONFIG_PM_SLEEP=y
 CONFIG_SUSPEND=y
 CONFIG_SUSPEND_FREEZER=y
+# CONFIG_PM_RUNTIME is not set
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
 
 #
 # CPU Frequency scaling
@@ -194,6 +234,7 @@ CONFIG_CPU_FREQ_TABLE=y
 # CONFIG_CPU_FREQ_DEBUG is not set
 # CONFIG_CPU_FREQ_STAT is not set
 # CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set
 # CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set
 CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
 # CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set
@@ -214,11 +255,9 @@ CONFIG_CPU_FREQ_AT32AP=y
 # Executable file formats
 #
 CONFIG_BINFMT_ELF=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+# CONFIG_HAVE_AOUT is not set
 # CONFIG_BINFMT_MISC is not set
-
-#
-# Networking
-#
 CONFIG_NET=y
 
 #
@@ -232,6 +271,7 @@ CONFIG_XFRM_USER=y
 # CONFIG_XFRM_SUB_POLICY is not set
 # CONFIG_XFRM_MIGRATE is not set
 # CONFIG_XFRM_STATISTICS is not set
+CONFIG_XFRM_IPCOMP=y
 CONFIG_NET_KEY=y
 # CONFIG_NET_KEY_MIGRATE is not set
 CONFIG_INET=y
@@ -269,7 +309,6 @@ CONFIG_INET_TCP_DIAG=y
 CONFIG_TCP_CONG_CUBIC=y
 CONFIG_DEFAULT_TCP_CONG="cubic"
 # CONFIG_TCP_MD5SIG is not set
-# CONFIG_IP_VS is not set
 CONFIG_IPV6=y
 # CONFIG_IPV6_PRIVACY is not set
 # CONFIG_IPV6_ROUTER_PREF is not set
@@ -285,8 +324,10 @@ CONFIG_INET6_XFRM_MODE_TUNNEL=y
 CONFIG_INET6_XFRM_MODE_BEET=y
 # CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set
 CONFIG_IPV6_SIT=y
+CONFIG_IPV6_NDISC_NODETYPE=y
 # CONFIG_IPV6_TUNNEL is not set
 # CONFIG_IPV6_MULTIPLE_TABLES is not set
+# CONFIG_IPV6_MROUTE is not set
 # CONFIG_NETWORK_SECMARK is not set
 CONFIG_NETFILTER=y
 # CONFIG_NETFILTER_DEBUG is not set
@@ -310,10 +351,12 @@ CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
 CONFIG_NETFILTER_XT_MATCH_MARK=m
 CONFIG_NETFILTER_XT_MATCH_POLICY=m
 CONFIG_NETFILTER_XT_MATCH_STATE=m
+# CONFIG_IP_VS is not set
 
 #
 # IP: Netfilter Configuration
 #
+CONFIG_NF_DEFRAG_IPV4=m
 CONFIG_NF_CONNTRACK_IPV4=m
 CONFIG_NF_CONNTRACK_PROC_COMPAT=y
 CONFIG_IP_NF_IPTABLES=m
@@ -339,16 +382,20 @@ CONFIG_IP_NF_MANGLE=m
 CONFIG_NF_CONNTRACK_IPV6=m
 CONFIG_IP6_NF_IPTABLES=m
 CONFIG_IP6_NF_MATCH_IPV6HEADER=m
-CONFIG_IP6_NF_FILTER=m
 CONFIG_IP6_NF_TARGET_LOG=m
+CONFIG_IP6_NF_FILTER=m
 CONFIG_IP6_NF_TARGET_REJECT=m
 CONFIG_IP6_NF_MANGLE=m
 # CONFIG_IP_DCCP is not set
 # CONFIG_IP_SCTP is not set
+# CONFIG_RDS is not set
 # CONFIG_TIPC is not set
 # CONFIG_ATM is not set
+CONFIG_STP=m
 CONFIG_BRIDGE=m
+# CONFIG_NET_DSA is not set
 CONFIG_VLAN_8021Q=m
+# CONFIG_VLAN_8021Q_GVRP is not set
 # CONFIG_DECNET is not set
 CONFIG_LLC=m
 # CONFIG_LLC2 is not set
@@ -358,26 +405,33 @@ CONFIG_LLC=m
 # CONFIG_LAPB is not set
 # CONFIG_ECONET is not set
 # CONFIG_WAN_ROUTER is not set
+# CONFIG_PHONET is not set
+# CONFIG_IEEE802154 is not set
 # CONFIG_NET_SCHED is not set
+# CONFIG_DCB is not set
 
 #
 # Network testing
 #
 # CONFIG_NET_PKTGEN is not set
 # CONFIG_NET_TCPPROBE is not set
+# CONFIG_NET_DROP_MONITOR is not set
 # CONFIG_HAMRADIO is not set
 # CONFIG_CAN is not set
 # CONFIG_IRDA is not set
 # CONFIG_BT is not set
 # CONFIG_AF_RXRPC is not set
+CONFIG_WIRELESS=y
+# CONFIG_CFG80211 is not set
+CONFIG_CFG80211_DEFAULT_PS_VALUE=0
+# CONFIG_WIRELESS_OLD_REGULATORY is not set
+# CONFIG_WIRELESS_EXT is not set
+# CONFIG_LIB80211 is not set
 
 #
-# Wireless
+# CFG80211 needs to be enabled for MAC80211
 #
-# CONFIG_CFG80211 is not set
-# CONFIG_WIRELESS_EXT is not set
-# CONFIG_MAC80211 is not set
-# CONFIG_IEEE80211 is not set
+# CONFIG_WIMAX is not set
 # CONFIG_RFKILL is not set
 # CONFIG_NET_9P is not set
 
@@ -389,6 +443,7 @@ CONFIG_LLC=m
 # Generic Driver Options
 #
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+# CONFIG_DEVTMPFS is not set
 CONFIG_STANDALONE=y
 # CONFIG_PREVENT_FIRMWARE_BUILD is not set
 # CONFIG_FW_LOADER is not set
@@ -398,10 +453,12 @@ CONFIG_STANDALONE=y
 # CONFIG_CONNECTOR is not set
 CONFIG_MTD=y
 # CONFIG_MTD_DEBUG is not set
+# CONFIG_MTD_TESTS is not set
 # CONFIG_MTD_CONCAT is not set
 CONFIG_MTD_PARTITIONS=y
 # CONFIG_MTD_REDBOOT_PARTS is not set
 CONFIG_MTD_CMDLINE_PARTS=y
+# CONFIG_MTD_AR7_PARTS is not set
 
 #
 # User Modules And Translation Layers
@@ -446,16 +503,17 @@ CONFIG_MTD_CFI_UTIL=y
 #
 # CONFIG_MTD_COMPLEX_MAPPINGS is not set
 CONFIG_MTD_PHYSMAP=y
-CONFIG_MTD_PHYSMAP_START=0x80000000
-CONFIG_MTD_PHYSMAP_LEN=0x0
-CONFIG_MTD_PHYSMAP_BANKWIDTH=2
+# CONFIG_MTD_PHYSMAP_COMPAT is not set
 # CONFIG_MTD_PLATRAM is not set
 
 #
 # Self-contained MTD device drivers
 #
 CONFIG_MTD_DATAFLASH=y
+# CONFIG_MTD_DATAFLASH_WRITE_VERIFY is not set
+# CONFIG_MTD_DATAFLASH_OTP is not set
 # CONFIG_MTD_M25P80 is not set
+# CONFIG_MTD_SST25L is not set
 # CONFIG_MTD_SLRAM is not set
 # CONFIG_MTD_PHRAM is not set
 # CONFIG_MTD_MTDRAM is not set
@@ -471,6 +529,11 @@ CONFIG_MTD_DATAFLASH=y
 # CONFIG_MTD_ONENAND is not set
 
 #
+# LPDDR flash memory drivers
+#
+# CONFIG_MTD_LPDDR is not set
+
+#
 # UBI - Unsorted block images
 #
 CONFIG_MTD_UBI=y
@@ -499,10 +562,20 @@ CONFIG_MISC_DEVICES=y
 CONFIG_ATMEL_TCLIB=y
 CONFIG_ATMEL_TCB_CLKSRC=y
 CONFIG_ATMEL_TCB_CLKSRC_BLOCK=0
-# CONFIG_EEPROM_93CX6 is not set
+# CONFIG_ICS932S401 is not set
 # CONFIG_ATMEL_SSC is not set
 # CONFIG_ENCLOSURE_SERVICES is not set
-# CONFIG_HAVE_IDE is not set
+# CONFIG_ISL29003 is not set
+# CONFIG_C2PORT is not set
+
+#
+# EEPROM support
+#
+# CONFIG_EEPROM_AT24 is not set
+# CONFIG_EEPROM_AT25 is not set
+# CONFIG_EEPROM_LEGACY is not set
+# CONFIG_EEPROM_MAX6875 is not set
+# CONFIG_EEPROM_93CX6 is not set
 
 #
 # SCSI device support
@@ -514,7 +587,6 @@ CONFIG_ATMEL_TCB_CLKSRC_BLOCK=0
 # CONFIG_ATA is not set
 # CONFIG_MD is not set
 CONFIG_NETDEVICES=y
-# CONFIG_NETDEVICES_MULTIQUEUE is not set
 # CONFIG_DUMMY is not set
 # CONFIG_BONDING is not set
 # CONFIG_MACVLAN is not set
@@ -536,25 +608,37 @@ CONFIG_PHYLIB=y
 # CONFIG_BROADCOM_PHY is not set
 # CONFIG_ICPLUS_PHY is not set
 # CONFIG_REALTEK_PHY is not set
+# CONFIG_NATIONAL_PHY is not set
+# CONFIG_STE10XP is not set
+# CONFIG_LSI_ET1011C_PHY is not set
 # CONFIG_FIXED_PHY is not set
 # CONFIG_MDIO_BITBANG is not set
 CONFIG_NET_ETHERNET=y
 # CONFIG_MII is not set
 CONFIG_MACB=y
 # CONFIG_ENC28J60 is not set
+# CONFIG_ETHOC is not set
+# CONFIG_DNET is not set
 # CONFIG_IBM_NEW_EMAC_ZMII is not set
 # CONFIG_IBM_NEW_EMAC_RGMII is not set
 # CONFIG_IBM_NEW_EMAC_TAH is not set
 # CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
+# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
+# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
 # CONFIG_B44 is not set
+# CONFIG_KS8842 is not set
+# CONFIG_KS8851 is not set
+# CONFIG_KS8851_MLL is not set
 # CONFIG_NETDEV_1000 is not set
 # CONFIG_NETDEV_10000 is not set
+CONFIG_WLAN=y
+# CONFIG_WLAN_PRE80211 is not set
+# CONFIG_WLAN_80211 is not set
 
 #
-# Wireless LAN
+# Enable WiMAX (Networking options) to see the WiMAX drivers
 #
-# CONFIG_WLAN_PRE80211 is not set
-# CONFIG_WLAN_80211 is not set
 # CONFIG_WAN is not set
 CONFIG_PPP=m
 # CONFIG_PPP_MULTILINK is not set
@@ -598,15 +682,30 @@ CONFIG_INPUT_EVDEV=m
 # CONFIG_INPUT_TABLET is not set
 CONFIG_INPUT_TOUCHSCREEN=y
 # CONFIG_TOUCHSCREEN_ADS7846 is not set
+# CONFIG_TOUCHSCREEN_AD7877 is not set
+# CONFIG_TOUCHSCREEN_AD7879_I2C is not set
+# CONFIG_TOUCHSCREEN_AD7879_SPI is not set
+# CONFIG_TOUCHSCREEN_AD7879 is not set
+# CONFIG_TOUCHSCREEN_EETI is not set
 # CONFIG_TOUCHSCREEN_FUJITSU is not set
 # CONFIG_TOUCHSCREEN_GUNZE is not set
 # CONFIG_TOUCHSCREEN_ELO is not set
+# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set
+# CONFIG_TOUCHSCREEN_MCS5000 is not set
 # CONFIG_TOUCHSCREEN_MTOUCH is not set
+# CONFIG_TOUCHSCREEN_INEXIO is not set
 # CONFIG_TOUCHSCREEN_MK712 is not set
 # CONFIG_TOUCHSCREEN_PENMOUNT is not set
 # CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
 # CONFIG_TOUCHSCREEN_TOUCHWIN is not set
-# CONFIG_TOUCHSCREEN_UCB1400 is not set
+CONFIG_TOUCHSCREEN_WM97XX=m
+CONFIG_TOUCHSCREEN_WM9705=y
+CONFIG_TOUCHSCREEN_WM9712=y
+CONFIG_TOUCHSCREEN_WM9713=y
+# CONFIG_TOUCHSCREEN_WM97XX_ATMEL is not set
+# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set
+# CONFIG_TOUCHSCREEN_TSC2007 is not set
+# CONFIG_TOUCHSCREEN_W90X900 is not set
 # CONFIG_INPUT_MISC is not set
 
 #
@@ -619,9 +718,11 @@ CONFIG_INPUT_TOUCHSCREEN=y
 # Character devices
 #
 CONFIG_VT=y
+CONFIG_CONSOLE_TRANSLATIONS=y
 CONFIG_VT_CONSOLE=y
 CONFIG_HW_CONSOLE=y
 # CONFIG_VT_HW_CONSOLE_BINDING is not set
+CONFIG_DEVKMEM=y
 # CONFIG_SERIAL_NONSTANDARD is not set
 
 #
@@ -636,9 +737,11 @@ CONFIG_SERIAL_ATMEL=y
 CONFIG_SERIAL_ATMEL_CONSOLE=y
 CONFIG_SERIAL_ATMEL_PDC=y
 # CONFIG_SERIAL_ATMEL_TTYAT is not set
+# CONFIG_SERIAL_MAX3100 is not set
 CONFIG_SERIAL_CORE=y
 CONFIG_SERIAL_CORE_CONSOLE=y
 CONFIG_UNIX98_PTYS=y
+# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
 # CONFIG_LEGACY_PTYS is not set
 # CONFIG_IPMI_HANDLER is not set
 # CONFIG_HW_RANDOM is not set
@@ -647,45 +750,44 @@ CONFIG_UNIX98_PTYS=y
 # CONFIG_TCG_TPM is not set
 CONFIG_I2C=m
 CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_COMPAT=y
 CONFIG_I2C_CHARDEV=m
+CONFIG_I2C_HELPER_AUTO=y
+CONFIG_I2C_ALGOBIT=m
 
 #
-# I2C Algorithms
+# I2C Hardware Bus support
 #
-CONFIG_I2C_ALGOBIT=m
-# CONFIG_I2C_ALGOPCF is not set
-# CONFIG_I2C_ALGOPCA is not set
 
 #
-# I2C Hardware Bus support
+# I2C system bus drivers (mostly embedded / system-on-chip)
 #
-CONFIG_I2C_ATMELTWI=m
+# CONFIG_I2C_DESIGNWARE is not set
 CONFIG_I2C_GPIO=m
 # CONFIG_I2C_OCORES is not set
-# CONFIG_I2C_PARPORT_LIGHT is not set
 # CONFIG_I2C_SIMTEC is not set
+
+#
+# External I2C/SMBus adapter drivers
+#
+# CONFIG_I2C_PARPORT_LIGHT is not set
 # CONFIG_I2C_TAOS_EVM is not set
+
+#
+# Other I2C/SMBus bus drivers
+#
+# CONFIG_I2C_PCA_PLATFORM is not set
 # CONFIG_I2C_STUB is not set
 
 #
 # Miscellaneous I2C Chip support
 #
 # CONFIG_DS1682 is not set
-# CONFIG_EEPROM_LEGACY is not set
-# CONFIG_SENSORS_PCF8574 is not set
-# CONFIG_PCF8575 is not set
-# CONFIG_SENSORS_PCF8591 is not set
-# CONFIG_TPS65010 is not set
-# CONFIG_SENSORS_MAX6875 is not set
 # CONFIG_SENSORS_TSL2550 is not set
 # CONFIG_I2C_DEBUG_CORE is not set
 # CONFIG_I2C_DEBUG_ALGO is not set
 # CONFIG_I2C_DEBUG_BUS is not set
 # CONFIG_I2C_DEBUG_CHIP is not set
-
-#
-# SPI support
-#
 CONFIG_SPI=y
 # CONFIG_SPI_DEBUG is not set
 CONFIG_SPI_MASTER=y
@@ -695,30 +797,48 @@ CONFIG_SPI_MASTER=y
 #
 CONFIG_SPI_ATMEL=y
 # CONFIG_SPI_BITBANG is not set
+# CONFIG_SPI_GPIO is not set
 
 #
 # SPI Protocol Masters
 #
-# CONFIG_EEPROM_AT25 is not set
 CONFIG_SPI_SPIDEV=m
 # CONFIG_SPI_TLE62X0 is not set
-CONFIG_HAVE_GPIO_LIB=y
 
 #
-# GPIO Support
+# PPS support
 #
+# CONFIG_PPS is not set
+CONFIG_ARCH_REQUIRE_GPIOLIB=y
+CONFIG_GPIOLIB=y
 # CONFIG_DEBUG_GPIO is not set
+# CONFIG_GPIO_SYSFS is not set
+
+#
+# Memory mapped GPIO expanders:
+#
 
 #
 # I2C GPIO expanders:
 #
+# CONFIG_GPIO_MAX732X is not set
 # CONFIG_GPIO_PCA953X is not set
 # CONFIG_GPIO_PCF857X is not set
 
 #
+# PCI GPIO expanders:
+#
+
+#
 # SPI GPIO expanders:
 #
+# CONFIG_GPIO_MAX7301 is not set
 # CONFIG_GPIO_MCP23S08 is not set
+# CONFIG_GPIO_MC33880 is not set
+
+#
+# AC97 GPIO expanders:
+#
 # CONFIG_W1 is not set
 # CONFIG_POWER_SUPPLY is not set
 # CONFIG_HWMON is not set
@@ -731,24 +851,31 @@ CONFIG_WATCHDOG=y
 #
 # CONFIG_SOFT_WATCHDOG is not set
 CONFIG_AT32AP700X_WDT=y
+CONFIG_SSB_POSSIBLE=y
 
 #
 # Sonics Silicon Backplane
 #
-CONFIG_SSB_POSSIBLE=y
 # CONFIG_SSB is not set
 
 #
 # Multifunction device drivers
 #
+# CONFIG_MFD_CORE is not set
 # CONFIG_MFD_SM501 is not set
-
-#
-# Multimedia devices
-#
-# CONFIG_VIDEO_DEV is not set
-# CONFIG_DVB_CORE is not set
-# CONFIG_DAB is not set
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_UCB1400_CORE is not set
+# CONFIG_TPS65010 is not set
+# CONFIG_MFD_TMIO is not set
+# CONFIG_MFD_WM8400 is not set
+# CONFIG_MFD_WM831X is not set
+# CONFIG_MFD_WM8350_I2C is not set
+# CONFIG_MFD_PCF50633 is not set
+# CONFIG_MFD_MC13783 is not set
+# CONFIG_AB3100_CORE is not set
+# CONFIG_EZX_PCAP is not set
+# CONFIG_REGULATOR is not set
+# CONFIG_MEDIA_SUPPORT is not set
 
 #
 # Graphics support
@@ -758,6 +885,7 @@ CONFIG_SSB_POSSIBLE=y
 CONFIG_FB=y
 # CONFIG_FIRMWARE_EDID is not set
 # CONFIG_FB_DDC is not set
+# CONFIG_FB_BOOT_VESA_SUPPORT is not set
 CONFIG_FB_CFB_FILLRECT=y
 CONFIG_FB_CFB_COPYAREA=y
 CONFIG_FB_CFB_IMAGEBLIT=y
@@ -765,8 +893,8 @@ CONFIG_FB_CFB_IMAGEBLIT=y
 # CONFIG_FB_SYS_FILLRECT is not set
 # CONFIG_FB_SYS_COPYAREA is not set
 # CONFIG_FB_SYS_IMAGEBLIT is not set
+# CONFIG_FB_FOREIGN_ENDIAN is not set
 # CONFIG_FB_SYS_FOPS is not set
-CONFIG_FB_DEFERRED_IO=y
 # CONFIG_FB_SVGALIB is not set
 # CONFIG_FB_MACMODES is not set
 # CONFIG_FB_BACKLIGHT is not set
@@ -779,6 +907,9 @@ CONFIG_FB_DEFERRED_IO=y
 # CONFIG_FB_S1D13XXX is not set
 CONFIG_FB_ATMEL=y
 # CONFIG_FB_VIRTUAL is not set
+# CONFIG_FB_METRONOME is not set
+# CONFIG_FB_MB862XX is not set
+# CONFIG_FB_BROADSHEET is not set
 # CONFIG_BACKLIGHT_LCD_SUPPORT is not set
 
 #
@@ -792,119 +923,124 @@ CONFIG_FB_ATMEL=y
 CONFIG_DUMMY_CONSOLE=y
 # CONFIG_FRAMEBUFFER_CONSOLE is not set
 # CONFIG_LOGO is not set
-
-#
-# Sound
-#
 CONFIG_SOUND=y
-
-#
-# Advanced Linux Sound Architecture
-#
+CONFIG_SOUND_OSS_CORE=y
+CONFIG_SOUND_OSS_CORE_PRECLAIM=y
 CONFIG_SND=y
-CONFIG_SND_TIMER=m
+CONFIG_SND_TIMER=y
 CONFIG_SND_PCM=m
 # CONFIG_SND_SEQUENCER is not set
 CONFIG_SND_OSSEMUL=y
 CONFIG_SND_MIXER_OSS=m
 CONFIG_SND_PCM_OSS=m
 CONFIG_SND_PCM_OSS_PLUGINS=y
+CONFIG_SND_HRTIMER=y
 # CONFIG_SND_DYNAMIC_MINORS is not set
 # CONFIG_SND_SUPPORT_OLD_API is not set
 CONFIG_SND_VERBOSE_PROCFS=y
 # CONFIG_SND_VERBOSE_PRINTK is not set
 # CONFIG_SND_DEBUG is not set
-
-#
-# Generic devices
-#
+CONFIG_SND_VMASTER=y
+# CONFIG_SND_RAWMIDI_SEQ is not set
+# CONFIG_SND_OPL3_LIB_SEQ is not set
+# CONFIG_SND_OPL4_LIB_SEQ is not set
+# CONFIG_SND_SBAWE_SEQ is not set
+# CONFIG_SND_EMU10K1_SEQ is not set
 CONFIG_SND_AC97_CODEC=m
-# CONFIG_SND_DUMMY is not set
-# CONFIG_SND_MTPAV is not set
-# CONFIG_SND_SERIAL_U16550 is not set
-# CONFIG_SND_MPU401 is not set
+# CONFIG_SND_DRIVERS is not set
 
 #
-# AVR32 devices
-#
-CONFIG_SND_ATMEL_AC97=m
-
-#
-# SPI devices
-#
-
-#
-# System on Chip audio support
+# Atmel devices (AVR32 and AT91)
 #
+# CONFIG_SND_ATMEL_ABDAC is not set
+CONFIG_SND_ATMEL_AC97C=m
+# CONFIG_SND_SPI is not set
 # CONFIG_SND_SOC is not set
-
-#
-# SoC Audio support for SuperH
-#
-
-#
-# ALSA SoC audio for Freescale SOCs
-#
-
-#
-# Open Sound System
-#
 # CONFIG_SOUND_PRIME is not set
 CONFIG_AC97_BUS=m
 CONFIG_HID_SUPPORT=y
 CONFIG_HID=y
-# CONFIG_HID_DEBUG is not set
 # CONFIG_HIDRAW is not set
+# CONFIG_HID_PID is not set
+
+#
+# Special HID drivers
+#
 CONFIG_USB_SUPPORT=y
 # CONFIG_USB_ARCH_HAS_HCD is not set
 # CONFIG_USB_ARCH_HAS_OHCI is not set
 # CONFIG_USB_ARCH_HAS_EHCI is not set
+# CONFIG_USB_OTG_WHITELIST is not set
+# CONFIG_USB_OTG_BLACKLIST_HUB is not set
+# CONFIG_USB_GADGET_MUSB_HDRC is not set
 
 #
-# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
+# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
 #
 CONFIG_USB_GADGET=y
 # CONFIG_USB_GADGET_DEBUG is not set
 # CONFIG_USB_GADGET_DEBUG_FILES is not set
+# CONFIG_USB_GADGET_DEBUG_FS is not set
+CONFIG_USB_GADGET_VBUS_DRAW=350
 CONFIG_USB_GADGET_SELECTED=y
-# CONFIG_USB_GADGET_AMD5536UDC is not set
+# CONFIG_USB_GADGET_AT91 is not set
 CONFIG_USB_GADGET_ATMEL_USBA=y
 CONFIG_USB_ATMEL_USBA=y
 # CONFIG_USB_GADGET_FSL_USB2 is not set
-# CONFIG_USB_GADGET_NET2280 is not set
-# CONFIG_USB_GADGET_PXA2XX is not set
-# CONFIG_USB_GADGET_M66592 is not set
-# CONFIG_USB_GADGET_GOKU is not set
 # CONFIG_USB_GADGET_LH7A40X is not set
 # CONFIG_USB_GADGET_OMAP is not set
+# CONFIG_USB_GADGET_PXA25X is not set
+# CONFIG_USB_GADGET_R8A66597 is not set
+# CONFIG_USB_GADGET_PXA27X is not set
+# CONFIG_USB_GADGET_S3C_HSOTG is not set
+# CONFIG_USB_GADGET_IMX is not set
 # CONFIG_USB_GADGET_S3C2410 is not set
-# CONFIG_USB_GADGET_AT91 is not set
+# CONFIG_USB_GADGET_M66592 is not set
+# CONFIG_USB_GADGET_AMD5536UDC is not set
+# CONFIG_USB_GADGET_FSL_QE is not set
+# CONFIG_USB_GADGET_CI13XXX is not set
+# CONFIG_USB_GADGET_NET2280 is not set
+# CONFIG_USB_GADGET_GOKU is not set
+# CONFIG_USB_GADGET_LANGWELL is not set
 # CONFIG_USB_GADGET_DUMMY_HCD is not set
 CONFIG_USB_GADGET_DUALSPEED=y
 CONFIG_USB_ZERO=m
+# CONFIG_USB_AUDIO is not set
 CONFIG_USB_ETH=m
 CONFIG_USB_ETH_RNDIS=y
+# CONFIG_USB_ETH_EEM is not set
 CONFIG_USB_GADGETFS=m
 CONFIG_USB_FILE_STORAGE=m
 # CONFIG_USB_FILE_STORAGE_TEST is not set
 CONFIG_USB_G_SERIAL=m
 # CONFIG_USB_MIDI_GADGET is not set
 # CONFIG_USB_G_PRINTER is not set
+CONFIG_USB_CDC_COMPOSITE=m
+
+#
+# OTG and related infrastructure
+#
+# CONFIG_USB_GPIO_VBUS is not set
+# CONFIG_NOP_USB_XCEIV is not set
 CONFIG_MMC=y
 # CONFIG_MMC_DEBUG is not set
 # CONFIG_MMC_UNSAFE_RESUME is not set
 
 #
-# MMC/SD Card Drivers
+# MMC/SD/SDIO Card Drivers
 #
 CONFIG_MMC_BLOCK=y
 CONFIG_MMC_BLOCK_BOUNCE=y
 # CONFIG_SDIO_UART is not set
+# CONFIG_MMC_TEST is not set
 
 #
-# MMC/SD Host Controller Drivers
+# MMC/SD/SDIO Host Controller Drivers
 #
+# CONFIG_MMC_SDHCI is not set
+# CONFIG_MMC_AT91 is not set
 CONFIG_MMC_ATMELMCI=y
+# CONFIG_MMC_ATMELMCI_DMA is not set
 # CONFIG_MMC_SPI is not set
 # CONFIG_MEMSTICK is not set
 CONFIG_NEW_LEDS=y
@@ -913,7 +1049,13 @@ CONFIG_LEDS_CLASS=y
 #
 # LED drivers
 #
+# CONFIG_LEDS_PCA9532 is not set
 CONFIG_LEDS_GPIO=y
+CONFIG_LEDS_GPIO_PLATFORM=y
+# CONFIG_LEDS_LP3944 is not set
+# CONFIG_LEDS_PCA955X is not set
+# CONFIG_LEDS_DAC124S085 is not set
+# CONFIG_LEDS_BD2802 is not set
 
 #
 # LED Triggers
@@ -921,6 +1063,14 @@ CONFIG_LEDS_GPIO=y
 CONFIG_LEDS_TRIGGERS=y
 CONFIG_LEDS_TRIGGER_TIMER=y
 CONFIG_LEDS_TRIGGER_HEARTBEAT=y
+# CONFIG_LEDS_TRIGGER_BACKLIGHT is not set
+# CONFIG_LEDS_TRIGGER_GPIO is not set
+# CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set
+
+#
+# iptables trigger is under Netfilter config (LED target)
+#
+# CONFIG_ACCESSIBILITY is not set
 CONFIG_RTC_LIB=y
 CONFIG_RTC_CLASS=y
 CONFIG_RTC_HCTOSYS=y
@@ -950,51 +1100,84 @@ CONFIG_RTC_INTF_DEV=y
 # CONFIG_RTC_DRV_PCF8583 is not set
 # CONFIG_RTC_DRV_M41T80 is not set
 # CONFIG_RTC_DRV_S35390A is not set
+# CONFIG_RTC_DRV_FM3130 is not set
+# CONFIG_RTC_DRV_RX8581 is not set
+# CONFIG_RTC_DRV_RX8025 is not set
 
 #
 # SPI RTC drivers
 #
+# CONFIG_RTC_DRV_M41T94 is not set
+# CONFIG_RTC_DRV_DS1305 is not set
+# CONFIG_RTC_DRV_DS1390 is not set
 # CONFIG_RTC_DRV_MAX6902 is not set
 # CONFIG_RTC_DRV_R9701 is not set
 # CONFIG_RTC_DRV_RS5C348 is not set
+# CONFIG_RTC_DRV_DS3234 is not set
+# CONFIG_RTC_DRV_PCF2123 is not set
 
 #
 # Platform RTC drivers
 #
+# CONFIG_RTC_DRV_DS1286 is not set
 # CONFIG_RTC_DRV_DS1511 is not set
 # CONFIG_RTC_DRV_DS1553 is not set
 # CONFIG_RTC_DRV_DS1742 is not set
 # CONFIG_RTC_DRV_STK17TA8 is not set
 # CONFIG_RTC_DRV_M48T86 is not set
+# CONFIG_RTC_DRV_M48T35 is not set
 # CONFIG_RTC_DRV_M48T59 is not set
+# CONFIG_RTC_DRV_BQ4802 is not set
 # CONFIG_RTC_DRV_V3020 is not set
 
 #
 # on-CPU RTC drivers
 #
 CONFIG_RTC_DRV_AT32AP700X=y
+CONFIG_DMADEVICES=y
 
 #
-# Userspace I/O
+# DMA Devices
 #
+CONFIG_DW_DMAC=y
+CONFIG_DMA_ENGINE=y
+
+#
+# DMA Clients
+#
+# CONFIG_NET_DMA is not set
+# CONFIG_ASYNC_TX_DMA is not set
+# CONFIG_DMATEST is not set
+# CONFIG_AUXDISPLAY is not set
 # CONFIG_UIO is not set
 
 #
+# TI VLYNQ
+#
+# CONFIG_STAGING is not set
+
+#
 # File systems
 #
 CONFIG_EXT2_FS=y
 # CONFIG_EXT2_FS_XATTR is not set
 # CONFIG_EXT2_FS_XIP is not set
 CONFIG_EXT3_FS=y
+# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
 # CONFIG_EXT3_FS_XATTR is not set
-# CONFIG_EXT4DEV_FS is not set
+# CONFIG_EXT4_FS is not set
 CONFIG_JBD=y
+# CONFIG_JBD_DEBUG is not set
 # CONFIG_REISERFS_FS is not set
 # CONFIG_JFS_FS is not set
 # CONFIG_FS_POSIX_ACL is not set
 # CONFIG_XFS_FS is not set
 # CONFIG_GFS2_FS is not set
 # CONFIG_OCFS2_FS is not set
+# CONFIG_BTRFS_FS is not set
+# CONFIG_NILFS2_FS is not set
+CONFIG_FILE_LOCKING=y
+CONFIG_FSNOTIFY=y
 # CONFIG_DNOTIFY is not set
 CONFIG_INOTIFY=y
 CONFIG_INOTIFY_USER=y
@@ -1002,6 +1185,12 @@ CONFIG_INOTIFY_USER=y
 # CONFIG_AUTOFS_FS is not set
 # CONFIG_AUTOFS4_FS is not set
 CONFIG_FUSE_FS=m
+# CONFIG_CUSE is not set
+
+#
+# Caches
+#
+# CONFIG_FSCACHE is not set
 
 #
 # CD-ROM/DVD Filesystems
@@ -1025,15 +1214,13 @@ CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
 CONFIG_PROC_FS=y
 # CONFIG_PROC_KCORE is not set
 CONFIG_PROC_SYSCTL=y
+CONFIG_PROC_PAGE_MONITOR=y
 CONFIG_SYSFS=y
 CONFIG_TMPFS=y
 # CONFIG_TMPFS_POSIX_ACL is not set
 # CONFIG_HUGETLB_PAGE is not set
 CONFIG_CONFIGFS_FS=y
-
-#
-# Miscellaneous filesystems
-#
+CONFIG_MISC_FILESYSTEMS=y
 # CONFIG_ADFS_FS is not set
 # CONFIG_AFFS_FS is not set
 # CONFIG_HFS_FS is not set
@@ -1059,8 +1246,10 @@ CONFIG_UBIFS_FS_LZO=y
 CONFIG_UBIFS_FS_ZLIB=y
 # CONFIG_UBIFS_FS_DEBUG is not set
 # CONFIG_CRAMFS is not set
+# CONFIG_SQUASHFS is not set
 # CONFIG_VXFS_FS is not set
 # CONFIG_MINIX_FS is not set
+# CONFIG_OMFS_FS is not set
 # CONFIG_HPFS_FS is not set
 # CONFIG_QNX4FS_FS is not set
 # CONFIG_ROMFS_FS is not set
@@ -1071,19 +1260,16 @@ CONFIG_NFS_FS=y
 CONFIG_NFS_V3=y
 # CONFIG_NFS_V3_ACL is not set
 # CONFIG_NFS_V4 is not set
-# CONFIG_NFS_DIRECTIO is not set
+CONFIG_ROOT_NFS=y
 CONFIG_NFSD=m
 CONFIG_NFSD_V3=y
 # CONFIG_NFSD_V3_ACL is not set
 # CONFIG_NFSD_V4 is not set
-CONFIG_NFSD_TCP=y
-CONFIG_ROOT_NFS=y
 CONFIG_LOCKD=y
 CONFIG_LOCKD_V4=y
 CONFIG_EXPORTFS=m
 CONFIG_NFS_COMMON=y
 CONFIG_SUNRPC=y
-# CONFIG_SUNRPC_BIND34 is not set
 # CONFIG_RPCSEC_GSS_KRB5 is not set
 # CONFIG_RPCSEC_GSS_SPKM3 is not set
 CONFIG_SMB_FS=m
@@ -1151,16 +1337,24 @@ CONFIG_NLS_UTF8=m
 # CONFIG_PRINTK_TIME is not set
 CONFIG_ENABLE_WARN_DEPRECATED=y
 CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_FRAME_WARN=1024
 CONFIG_MAGIC_SYSRQ=y
+# CONFIG_STRIP_ASM_SYMS is not set
 # CONFIG_UNUSED_SYMBOLS is not set
-# CONFIG_DEBUG_FS is not set
+CONFIG_DEBUG_FS=y
 # CONFIG_HEADERS_CHECK is not set
 CONFIG_DEBUG_KERNEL=y
 # CONFIG_DEBUG_SHIRQ is not set
 CONFIG_DETECT_SOFTLOCKUP=y
+# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
+CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
+CONFIG_DETECT_HUNG_TASK=y
+# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set
+CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0
 CONFIG_SCHED_DEBUG=y
 # CONFIG_SCHEDSTATS is not set
 # CONFIG_TIMER_STATS is not set
+# CONFIG_DEBUG_OBJECTS is not set
 # CONFIG_SLUB_DEBUG_ON is not set
 # CONFIG_SLUB_STATS is not set
 # CONFIG_DEBUG_RT_MUTEXES is not set
@@ -1172,19 +1366,48 @@ CONFIG_SCHED_DEBUG=y
 # CONFIG_LOCK_STAT is not set
 # CONFIG_DEBUG_SPINLOCK_SLEEP is not set
 # CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+CONFIG_STACKTRACE=y
 # CONFIG_DEBUG_KOBJECT is not set
 CONFIG_DEBUG_BUGVERBOSE=y
 # CONFIG_DEBUG_INFO is not set
 # CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_WRITECOUNT is not set
+# CONFIG_DEBUG_MEMORY_INIT is not set
 # CONFIG_DEBUG_LIST is not set
 # CONFIG_DEBUG_SG is not set
+# CONFIG_DEBUG_NOTIFIERS is not set
+# CONFIG_DEBUG_CREDENTIALS is not set
 CONFIG_FRAME_POINTER=y
 # CONFIG_BOOT_PRINTK_DELAY is not set
 # CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_RCU_CPU_STALL_DETECTOR is not set
 # CONFIG_KPROBES_SANITY_TEST is not set
 # CONFIG_BACKTRACE_SELF_TEST is not set
+# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
+# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
 # CONFIG_LKDTM is not set
 # CONFIG_FAULT_INJECTION is not set
+# CONFIG_PAGE_POISONING is not set
+CONFIG_NOP_TRACER=y
+CONFIG_RING_BUFFER=y
+CONFIG_EVENT_TRACING=y
+CONFIG_CONTEXT_SWITCH_TRACER=y
+CONFIG_RING_BUFFER_ALLOW_SWAP=y
+CONFIG_TRACING=y
+CONFIG_TRACING_SUPPORT=y
+CONFIG_FTRACE=y
+# CONFIG_IRQSOFF_TRACER is not set
+# CONFIG_SCHED_TRACER is not set
+# CONFIG_ENABLE_DEFAULT_TRACERS is not set
+# CONFIG_BOOT_TRACER is not set
+CONFIG_BRANCH_PROFILE_NONE=y
+# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set
+# CONFIG_PROFILE_ALL_BRANCHES is not set
+# CONFIG_KMEMTRACE is not set
+# CONFIG_WORKQUEUE_TRACER is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_RING_BUFFER_BENCHMARK is not set
+# CONFIG_DYNAMIC_DEBUG is not set
 # CONFIG_SAMPLES is not set
 
 #
@@ -1192,63 +1415,118 @@ CONFIG_FRAME_POINTER=y
 #
 # CONFIG_KEYS is not set
 # CONFIG_SECURITY is not set
+# CONFIG_SECURITYFS is not set
 # CONFIG_SECURITY_FILE_CAPABILITIES is not set
 CONFIG_CRYPTO=y
+
+#
+# Crypto core or helper
+#
+# CONFIG_CRYPTO_FIPS is not set
 CONFIG_CRYPTO_ALGAPI=y
+CONFIG_CRYPTO_ALGAPI2=y
 CONFIG_CRYPTO_AEAD=y
+CONFIG_CRYPTO_AEAD2=y
 CONFIG_CRYPTO_BLKCIPHER=y
-# CONFIG_CRYPTO_SEQIV is not set
+CONFIG_CRYPTO_BLKCIPHER2=y
 CONFIG_CRYPTO_HASH=y
+CONFIG_CRYPTO_HASH2=y
+CONFIG_CRYPTO_RNG=m
+CONFIG_CRYPTO_RNG2=y
+CONFIG_CRYPTO_PCOMP=y
 CONFIG_CRYPTO_MANAGER=y
+CONFIG_CRYPTO_MANAGER2=y
+# CONFIG_CRYPTO_GF128MUL is not set
+# CONFIG_CRYPTO_NULL is not set
+CONFIG_CRYPTO_WORKQUEUE=y
+# CONFIG_CRYPTO_CRYPTD is not set
+CONFIG_CRYPTO_AUTHENC=y
+# CONFIG_CRYPTO_TEST is not set
+
+#
+# Authenticated Encryption with Associated Data
+#
+# CONFIG_CRYPTO_CCM is not set
+# CONFIG_CRYPTO_GCM is not set
+# CONFIG_CRYPTO_SEQIV is not set
+
+#
+# Block modes
+#
+CONFIG_CRYPTO_CBC=y
+# CONFIG_CRYPTO_CTR is not set
+# CONFIG_CRYPTO_CTS is not set
+CONFIG_CRYPTO_ECB=m
+# CONFIG_CRYPTO_LRW is not set
+# CONFIG_CRYPTO_PCBC is not set
+# CONFIG_CRYPTO_XTS is not set
+
+#
+# Hash modes
+#
 CONFIG_CRYPTO_HMAC=y
 # CONFIG_CRYPTO_XCBC is not set
-# CONFIG_CRYPTO_NULL is not set
+# CONFIG_CRYPTO_VMAC is not set
+
+#
+# Digest
+#
+# CONFIG_CRYPTO_CRC32C is not set
+# CONFIG_CRYPTO_GHASH is not set
 # CONFIG_CRYPTO_MD4 is not set
 CONFIG_CRYPTO_MD5=y
+# CONFIG_CRYPTO_MICHAEL_MIC is not set
+# CONFIG_CRYPTO_RMD128 is not set
+# CONFIG_CRYPTO_RMD160 is not set
+# CONFIG_CRYPTO_RMD256 is not set
+# CONFIG_CRYPTO_RMD320 is not set
 CONFIG_CRYPTO_SHA1=y
 # CONFIG_CRYPTO_SHA256 is not set
 # CONFIG_CRYPTO_SHA512 is not set
-# CONFIG_CRYPTO_WP512 is not set
 # CONFIG_CRYPTO_TGR192 is not set
-# CONFIG_CRYPTO_GF128MUL is not set
-CONFIG_CRYPTO_ECB=m
-CONFIG_CRYPTO_CBC=y
-# CONFIG_CRYPTO_PCBC is not set
-# CONFIG_CRYPTO_LRW is not set
-# CONFIG_CRYPTO_XTS is not set
-# CONFIG_CRYPTO_CTR is not set
-# CONFIG_CRYPTO_GCM is not set
-# CONFIG_CRYPTO_CCM is not set
-# CONFIG_CRYPTO_CRYPTD is not set
-CONFIG_CRYPTO_DES=y
-# CONFIG_CRYPTO_FCRYPT is not set
+# CONFIG_CRYPTO_WP512 is not set
+
+#
+# Ciphers
+#
+CONFIG_CRYPTO_AES=m
+# CONFIG_CRYPTO_ANUBIS is not set
+CONFIG_CRYPTO_ARC4=m
 # CONFIG_CRYPTO_BLOWFISH is not set
-# CONFIG_CRYPTO_TWOFISH is not set
-# CONFIG_CRYPTO_SERPENT is not set
-# CONFIG_CRYPTO_AES is not set
+# CONFIG_CRYPTO_CAMELLIA is not set
 # CONFIG_CRYPTO_CAST5 is not set
 # CONFIG_CRYPTO_CAST6 is not set
-# CONFIG_CRYPTO_TEA is not set
-CONFIG_CRYPTO_ARC4=m
+CONFIG_CRYPTO_DES=y
+# CONFIG_CRYPTO_FCRYPT is not set
 # CONFIG_CRYPTO_KHAZAD is not set
-# CONFIG_CRYPTO_ANUBIS is not set
-# CONFIG_CRYPTO_SEED is not set
 # CONFIG_CRYPTO_SALSA20 is not set
+# CONFIG_CRYPTO_SEED is not set
+# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_TEA is not set
+# CONFIG_CRYPTO_TWOFISH is not set
+
+#
+# Compression
+#
 CONFIG_CRYPTO_DEFLATE=y
-# CONFIG_CRYPTO_MICHAEL_MIC is not set
-# CONFIG_CRYPTO_CRC32C is not set
-# CONFIG_CRYPTO_CAMELLIA is not set
-# CONFIG_CRYPTO_TEST is not set
-CONFIG_CRYPTO_AUTHENC=y
+# CONFIG_CRYPTO_ZLIB is not set
 CONFIG_CRYPTO_LZO=y
+
+#
+# Random Number Generation
+#
+CONFIG_CRYPTO_ANSI_CPRNG=m
 CONFIG_CRYPTO_HW=y
+CONFIG_BINARY_PRINTF=y
 
 #
 # Library routines
 #
 CONFIG_BITREVERSE=y
+CONFIG_GENERIC_FIND_LAST_BIT=y
 CONFIG_CRC_CCITT=m
 CONFIG_CRC16=y
+# CONFIG_CRC_T10DIF is not set
 # CONFIG_CRC_ITU_T is not set
 CONFIG_CRC32=y
 # CONFIG_CRC7 is not set
@@ -1257,8 +1535,9 @@ CONFIG_ZLIB_INFLATE=y
 CONFIG_ZLIB_DEFLATE=y
 CONFIG_LZO_COMPRESS=y
 CONFIG_LZO_DECOMPRESS=y
+CONFIG_DECOMPRESS_GZIP=y
 CONFIG_GENERIC_ALLOCATOR=y
-CONFIG_PLIST=y
 CONFIG_HAS_IOMEM=y
 CONFIG_HAS_IOPORT=y
 CONFIG_HAS_DMA=y
+CONFIG_NLATTR=y
diff --git a/arch/avr32/configs/atngw100_evklcd101_defconfig b/arch/avr32/configs/atngw100_evklcd101_defconfig
index a96b68ea5e83..5ef67da343bc 100644
--- a/arch/avr32/configs/atngw100_evklcd101_defconfig
+++ b/arch/avr32/configs/atngw100_evklcd101_defconfig
@@ -1,7 +1,7 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.25.6
-# Wed Jun 18 16:09:32 2008
+# Linux kernel version: 2.6.32-rc5
+# Thu Oct 29 09:37:19 2009
 #
 CONFIG_AVR32=y
 CONFIG_GENERIC_GPIO=y
@@ -21,6 +21,7 @@ CONFIG_GENERIC_HWEIGHT=y
 CONFIG_GENERIC_CALIBRATE_DELAY=y
 CONFIG_GENERIC_BUG=y
 CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+CONFIG_CONSTRUCTORS=y
 
 #
 # General setup
@@ -34,22 +35,37 @@ CONFIG_SWAP=y
 CONFIG_SYSVIPC=y
 CONFIG_SYSVIPC_SYSCTL=y
 CONFIG_POSIX_MQUEUE=y
+CONFIG_POSIX_MQUEUE_SYSCTL=y
 CONFIG_BSD_PROCESS_ACCT=y
 CONFIG_BSD_PROCESS_ACCT_V3=y
 # CONFIG_TASKSTATS is not set
 # CONFIG_AUDIT is not set
+
+#
+# RCU Subsystem
+#
+CONFIG_TREE_RCU=y
+# CONFIG_TREE_PREEMPT_RCU is not set
+# CONFIG_RCU_TRACE is not set
+CONFIG_RCU_FANOUT=32
+# CONFIG_RCU_FANOUT_EXACT is not set
+# CONFIG_TREE_RCU_TRACE is not set
 # CONFIG_IKCONFIG is not set
 CONFIG_LOG_BUF_SHIFT=14
-# CONFIG_CGROUPS is not set
 # CONFIG_GROUP_SCHED is not set
+# CONFIG_CGROUPS is not set
 CONFIG_SYSFS_DEPRECATED=y
 CONFIG_SYSFS_DEPRECATED_V2=y
 # CONFIG_RELAY is not set
 # CONFIG_NAMESPACES is not set
 CONFIG_BLK_DEV_INITRD=y
 CONFIG_INITRAMFS_SOURCE=""
+CONFIG_RD_GZIP=y
+# CONFIG_RD_BZIP2 is not set
+# CONFIG_RD_LZMA is not set
 CONFIG_CC_OPTIMIZE_FOR_SIZE=y
 CONFIG_SYSCTL=y
+CONFIG_ANON_INODES=y
 CONFIG_EMBEDDED=y
 # CONFIG_SYSCTL_SYSCALL is not set
 CONFIG_KALLSYMS=y
@@ -59,43 +75,51 @@ CONFIG_HOTPLUG=y
 CONFIG_PRINTK=y
 CONFIG_BUG=y
 CONFIG_ELF_CORE=y
-# CONFIG_COMPAT_BRK is not set
 # CONFIG_BASE_FULL is not set
 CONFIG_FUTEX=y
-CONFIG_ANON_INODES=y
 CONFIG_EPOLL=y
 CONFIG_SIGNALFD=y
 CONFIG_TIMERFD=y
 CONFIG_EVENTFD=y
 CONFIG_SHMEM=y
+CONFIG_AIO=y
+
+#
+# Kernel Performance Events And Counters
+#
 CONFIG_VM_EVENT_COUNTERS=y
 CONFIG_SLUB_DEBUG=y
+# CONFIG_COMPAT_BRK is not set
 # CONFIG_SLAB is not set
 CONFIG_SLUB=y
 # CONFIG_SLOB is not set
 CONFIG_PROFILING=y
-# CONFIG_MARKERS is not set
+CONFIG_TRACEPOINTS=y
 CONFIG_OPROFILE=m
 CONFIG_HAVE_OPROFILE=y
 CONFIG_KPROBES=y
 CONFIG_HAVE_KPROBES=y
-# CONFIG_HAVE_KRETPROBES is not set
-CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_HAVE_CLK=y
+
+#
+# GCOV-based kernel profiling
+#
+# CONFIG_GCOV_KERNEL is not set
+CONFIG_SLOW_WORK=y
+# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
 CONFIG_SLABINFO=y
 CONFIG_RT_MUTEXES=y
-# CONFIG_TINY_SHMEM is not set
 CONFIG_BASE_SMALL=1
 CONFIG_MODULES=y
+# CONFIG_MODULE_FORCE_LOAD is not set
 CONFIG_MODULE_UNLOAD=y
 CONFIG_MODULE_FORCE_UNLOAD=y
 # CONFIG_MODVERSIONS is not set
 # CONFIG_MODULE_SRCVERSION_ALL is not set
-CONFIG_KMOD=y
 CONFIG_BLOCK=y
-# CONFIG_LBD is not set
-# CONFIG_BLK_DEV_IO_TRACE is not set
-# CONFIG_LSF is not set
+CONFIG_LBDAF=y
 # CONFIG_BLK_DEV_BSG is not set
+# CONFIG_BLK_DEV_INTEGRITY is not set
 
 #
 # IO Schedulers
@@ -109,7 +133,7 @@ CONFIG_IOSCHED_CFQ=y
 CONFIG_DEFAULT_CFQ=y
 # CONFIG_DEFAULT_NOOP is not set
 CONFIG_DEFAULT_IOSCHED="cfq"
-CONFIG_CLASSIC_RCU=y
+CONFIG_FREEZER=y
 
 #
 # System Type and features
@@ -124,13 +148,20 @@ CONFIG_PERFORMANCE_COUNTERS=y
 CONFIG_PLATFORM_AT32AP=y
 CONFIG_CPU_AT32AP700X=y
 CONFIG_CPU_AT32AP7000=y
+CONFIG_BOARD_ATNGW100_COMMON=y
 # CONFIG_BOARD_ATSTK1000 is not set
-CONFIG_BOARD_ATNGW100=y
+CONFIG_BOARD_ATNGW100_MKI=y
+# CONFIG_BOARD_ATNGW100_MKII is not set
+# CONFIG_BOARD_HAMMERHEAD is not set
+# CONFIG_BOARD_FAVR_32 is not set
+# CONFIG_BOARD_MERISC is not set
+# CONFIG_BOARD_MIMC200 is not set
+# CONFIG_BOARD_ATNGW100_ADDON_NONE is not set
 CONFIG_BOARD_ATNGW100_EVKLCD10X=y
+# CONFIG_BOARD_ATNGW100_MRMT is not set
 # CONFIG_BOARD_ATNGW100_EVKLCD10X_QVGA is not set
 CONFIG_BOARD_ATNGW100_EVKLCD10X_VGA=y
 # CONFIG_BOARD_ATNGW100_EVKLCD10X_POW_QVGA is not set
-CONFIG_BOARD_ATNGW100_I2C_GPIO=y
 CONFIG_LOADER_U_BOOT=y
 
 #
@@ -139,14 +170,14 @@ CONFIG_LOADER_U_BOOT=y
 # CONFIG_AP700X_32_BIT_SMC is not set
 CONFIG_AP700X_16_BIT_SMC=y
 # CONFIG_AP700X_8_BIT_SMC is not set
-CONFIG_GPIO_DEV=y
 CONFIG_LOAD_ADDRESS=0x10000000
 CONFIG_ENTRY_ADDRESS=0x90000000
 CONFIG_PHYS_OFFSET=0x10000000
 CONFIG_PREEMPT_NONE=y
 # CONFIG_PREEMPT_VOLUNTARY is not set
 # CONFIG_PREEMPT is not set
-# CONFIG_HAVE_ARCH_BOOTMEM_NODE is not set
+CONFIG_QUICKLIST=y
+# CONFIG_HAVE_ARCH_BOOTMEM is not set
 # CONFIG_ARCH_HAVE_MEMORY_PRESENT is not set
 # CONFIG_NEED_NODE_MEMMAP_SIZE is not set
 CONFIG_ARCH_FLATMEM_ENABLE=y
@@ -158,33 +189,36 @@ CONFIG_FLATMEM_MANUAL=y
 # CONFIG_SPARSEMEM_MANUAL is not set
 CONFIG_FLATMEM=y
 CONFIG_FLAT_NODE_MEM_MAP=y
-# CONFIG_SPARSEMEM_STATIC is not set
-# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
+CONFIG_PAGEFLAGS_EXTENDED=y
 CONFIG_SPLIT_PTLOCK_CPUS=4
-# CONFIG_RESOURCES_64BIT is not set
+# CONFIG_PHYS_ADDR_T_64BIT is not set
 CONFIG_ZONE_DMA_FLAG=0
+CONFIG_NR_QUICK=2
 CONFIG_VIRT_TO_BUS=y
+CONFIG_HAVE_MLOCK=y
+CONFIG_HAVE_MLOCKED_PAGE_BIT=y
+# CONFIG_KSM is not set
+CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
 # CONFIG_OWNERSHIP_TRACE is not set
 CONFIG_NMI_DEBUGGING=y
-CONFIG_DW_DMAC=y
 # CONFIG_HZ_100 is not set
 CONFIG_HZ_250=y
 # CONFIG_HZ_300 is not set
 # CONFIG_HZ_1000 is not set
 CONFIG_HZ=250
-# CONFIG_SCHED_HRTICK is not set
+CONFIG_SCHED_HRTICK=y
 CONFIG_CMDLINE=""
 
 #
 # Power management options
 #
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
 CONFIG_PM=y
-# CONFIG_PM_LEGACY is not set
 # CONFIG_PM_DEBUG is not set
 CONFIG_PM_SLEEP=y
 CONFIG_SUSPEND=y
 CONFIG_SUSPEND_FREEZER=y
+# CONFIG_PM_RUNTIME is not set
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
 
 #
 # CPU Frequency scaling
@@ -194,6 +228,7 @@ CONFIG_CPU_FREQ_TABLE=y
 # CONFIG_CPU_FREQ_DEBUG is not set
 # CONFIG_CPU_FREQ_STAT is not set
 # CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set
 # CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set
 CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
 # CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set
@@ -214,11 +249,9 @@ CONFIG_CPU_FREQ_AT32AP=y
 # Executable file formats
 #
 CONFIG_BINFMT_ELF=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+# CONFIG_HAVE_AOUT is not set
 # CONFIG_BINFMT_MISC is not set
-
-#
-# Networking
-#
 CONFIG_NET=y
 
 #
@@ -232,6 +265,7 @@ CONFIG_XFRM_USER=y
 # CONFIG_XFRM_SUB_POLICY is not set
 # CONFIG_XFRM_MIGRATE is not set
 # CONFIG_XFRM_STATISTICS is not set
+CONFIG_XFRM_IPCOMP=y
 CONFIG_NET_KEY=y
 # CONFIG_NET_KEY_MIGRATE is not set
 CONFIG_INET=y
@@ -269,7 +303,6 @@ CONFIG_INET_TCP_DIAG=y
 CONFIG_TCP_CONG_CUBIC=y
 CONFIG_DEFAULT_TCP_CONG="cubic"
 # CONFIG_TCP_MD5SIG is not set
-# CONFIG_IP_VS is not set
 CONFIG_IPV6=y
 # CONFIG_IPV6_PRIVACY is not set
 # CONFIG_IPV6_ROUTER_PREF is not set
@@ -285,8 +318,10 @@ CONFIG_INET6_XFRM_MODE_TUNNEL=y
 CONFIG_INET6_XFRM_MODE_BEET=y
 # CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set
 CONFIG_IPV6_SIT=y
+CONFIG_IPV6_NDISC_NODETYPE=y
 # CONFIG_IPV6_TUNNEL is not set
 # CONFIG_IPV6_MULTIPLE_TABLES is not set
+# CONFIG_IPV6_MROUTE is not set
 # CONFIG_NETWORK_SECMARK is not set
 CONFIG_NETFILTER=y
 # CONFIG_NETFILTER_DEBUG is not set
@@ -310,10 +345,12 @@ CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
 CONFIG_NETFILTER_XT_MATCH_MARK=m
 CONFIG_NETFILTER_XT_MATCH_POLICY=m
 CONFIG_NETFILTER_XT_MATCH_STATE=m
+# CONFIG_IP_VS is not set
 
 #
 # IP: Netfilter Configuration
 #
+CONFIG_NF_DEFRAG_IPV4=m
 CONFIG_NF_CONNTRACK_IPV4=m
 CONFIG_NF_CONNTRACK_PROC_COMPAT=y
 CONFIG_IP_NF_IPTABLES=m
@@ -339,16 +376,20 @@ CONFIG_IP_NF_MANGLE=m
 CONFIG_NF_CONNTRACK_IPV6=m
 CONFIG_IP6_NF_IPTABLES=m
 CONFIG_IP6_NF_MATCH_IPV6HEADER=m
-CONFIG_IP6_NF_FILTER=m
 CONFIG_IP6_NF_TARGET_LOG=m
+CONFIG_IP6_NF_FILTER=m
 CONFIG_IP6_NF_TARGET_REJECT=m
 CONFIG_IP6_NF_MANGLE=m
 # CONFIG_IP_DCCP is not set
 # CONFIG_IP_SCTP is not set
+# CONFIG_RDS is not set
 # CONFIG_TIPC is not set
 # CONFIG_ATM is not set
+CONFIG_STP=m
 CONFIG_BRIDGE=m
+# CONFIG_NET_DSA is not set
 CONFIG_VLAN_8021Q=m
+# CONFIG_VLAN_8021Q_GVRP is not set
 # CONFIG_DECNET is not set
 CONFIG_LLC=m
 # CONFIG_LLC2 is not set
@@ -358,26 +399,33 @@ CONFIG_LLC=m
 # CONFIG_LAPB is not set
 # CONFIG_ECONET is not set
 # CONFIG_WAN_ROUTER is not set
+# CONFIG_PHONET is not set
+# CONFIG_IEEE802154 is not set
 # CONFIG_NET_SCHED is not set
+# CONFIG_DCB is not set
 
 #
 # Network testing
 #
 # CONFIG_NET_PKTGEN is not set
 # CONFIG_NET_TCPPROBE is not set
+# CONFIG_NET_DROP_MONITOR is not set
 # CONFIG_HAMRADIO is not set
 # CONFIG_CAN is not set
 # CONFIG_IRDA is not set
 # CONFIG_BT is not set
 # CONFIG_AF_RXRPC is not set
+CONFIG_WIRELESS=y
+# CONFIG_CFG80211 is not set
+CONFIG_CFG80211_DEFAULT_PS_VALUE=0
+# CONFIG_WIRELESS_OLD_REGULATORY is not set
+# CONFIG_WIRELESS_EXT is not set
+# CONFIG_LIB80211 is not set
 
 #
-# Wireless
+# CFG80211 needs to be enabled for MAC80211
 #
-# CONFIG_CFG80211 is not set
-# CONFIG_WIRELESS_EXT is not set
-# CONFIG_MAC80211 is not set
-# CONFIG_IEEE80211 is not set
+# CONFIG_WIMAX is not set
 # CONFIG_RFKILL is not set
 # CONFIG_NET_9P is not set
 
@@ -389,6 +437,7 @@ CONFIG_LLC=m
 # Generic Driver Options
 #
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+# CONFIG_DEVTMPFS is not set
 CONFIG_STANDALONE=y
 # CONFIG_PREVENT_FIRMWARE_BUILD is not set
 # CONFIG_FW_LOADER is not set
@@ -398,10 +447,12 @@ CONFIG_STANDALONE=y
 # CONFIG_CONNECTOR is not set
 CONFIG_MTD=y
 # CONFIG_MTD_DEBUG is not set
+# CONFIG_MTD_TESTS is not set
 # CONFIG_MTD_CONCAT is not set
 CONFIG_MTD_PARTITIONS=y
 # CONFIG_MTD_REDBOOT_PARTS is not set
 CONFIG_MTD_CMDLINE_PARTS=y
+# CONFIG_MTD_AR7_PARTS is not set
 
 #
 # User Modules And Translation Layers
@@ -446,16 +497,17 @@ CONFIG_MTD_CFI_UTIL=y
 #
 # CONFIG_MTD_COMPLEX_MAPPINGS is not set
 CONFIG_MTD_PHYSMAP=y
-CONFIG_MTD_PHYSMAP_START=0x80000000
-CONFIG_MTD_PHYSMAP_LEN=0x0
-CONFIG_MTD_PHYSMAP_BANKWIDTH=2
+# CONFIG_MTD_PHYSMAP_COMPAT is not set
 # CONFIG_MTD_PLATRAM is not set
 
 #
 # Self-contained MTD device drivers
 #
 CONFIG_MTD_DATAFLASH=y
+# CONFIG_MTD_DATAFLASH_WRITE_VERIFY is not set
+# CONFIG_MTD_DATAFLASH_OTP is not set
 # CONFIG_MTD_M25P80 is not set
+# CONFIG_MTD_SST25L is not set
 # CONFIG_MTD_SLRAM is not set
 # CONFIG_MTD_PHRAM is not set
 # CONFIG_MTD_MTDRAM is not set
@@ -471,6 +523,11 @@ CONFIG_MTD_DATAFLASH=y
 # CONFIG_MTD_ONENAND is not set
 
 #
+# LPDDR flash memory drivers
+#
+# CONFIG_MTD_LPDDR is not set
+
+#
 # UBI - Unsorted block images
 #
 CONFIG_MTD_UBI=y
@@ -499,10 +556,20 @@ CONFIG_MISC_DEVICES=y
 CONFIG_ATMEL_TCLIB=y
 CONFIG_ATMEL_TCB_CLKSRC=y
 CONFIG_ATMEL_TCB_CLKSRC_BLOCK=0
-# CONFIG_EEPROM_93CX6 is not set
+# CONFIG_ICS932S401 is not set
 # CONFIG_ATMEL_SSC is not set
 # CONFIG_ENCLOSURE_SERVICES is not set
-# CONFIG_HAVE_IDE is not set
+# CONFIG_ISL29003 is not set
+# CONFIG_C2PORT is not set
+
+#
+# EEPROM support
+#
+# CONFIG_EEPROM_AT24 is not set
+# CONFIG_EEPROM_AT25 is not set
+# CONFIG_EEPROM_LEGACY is not set
+# CONFIG_EEPROM_MAX6875 is not set
+# CONFIG_EEPROM_93CX6 is not set
 
 #
 # SCSI device support
@@ -514,7 +581,6 @@ CONFIG_ATMEL_TCB_CLKSRC_BLOCK=0
 # CONFIG_ATA is not set
 # CONFIG_MD is not set
 CONFIG_NETDEVICES=y
-# CONFIG_NETDEVICES_MULTIQUEUE is not set
 # CONFIG_DUMMY is not set
 # CONFIG_BONDING is not set
 # CONFIG_MACVLAN is not set
@@ -536,25 +602,37 @@ CONFIG_PHYLIB=y
 # CONFIG_BROADCOM_PHY is not set
 # CONFIG_ICPLUS_PHY is not set
 # CONFIG_REALTEK_PHY is not set
+# CONFIG_NATIONAL_PHY is not set
+# CONFIG_STE10XP is not set
+# CONFIG_LSI_ET1011C_PHY is not set
 # CONFIG_FIXED_PHY is not set
 # CONFIG_MDIO_BITBANG is not set
 CONFIG_NET_ETHERNET=y
 # CONFIG_MII is not set
 CONFIG_MACB=y
 # CONFIG_ENC28J60 is not set
+# CONFIG_ETHOC is not set
+# CONFIG_DNET is not set
 # CONFIG_IBM_NEW_EMAC_ZMII is not set
 # CONFIG_IBM_NEW_EMAC_RGMII is not set
 # CONFIG_IBM_NEW_EMAC_TAH is not set
 # CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
+# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
+# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
 # CONFIG_B44 is not set
+# CONFIG_KS8842 is not set
+# CONFIG_KS8851 is not set
+# CONFIG_KS8851_MLL is not set
 # CONFIG_NETDEV_1000 is not set
 # CONFIG_NETDEV_10000 is not set
+CONFIG_WLAN=y
+# CONFIG_WLAN_PRE80211 is not set
+# CONFIG_WLAN_80211 is not set
 
 #
-# Wireless LAN
+# Enable WiMAX (Networking options) to see the WiMAX drivers
 #
-# CONFIG_WLAN_PRE80211 is not set
-# CONFIG_WLAN_80211 is not set
 # CONFIG_WAN is not set
 CONFIG_PPP=m
 # CONFIG_PPP_MULTILINK is not set
@@ -598,15 +676,30 @@ CONFIG_INPUT_EVDEV=m
 # CONFIG_INPUT_TABLET is not set
 CONFIG_INPUT_TOUCHSCREEN=y
 # CONFIG_TOUCHSCREEN_ADS7846 is not set
+# CONFIG_TOUCHSCREEN_AD7877 is not set
+# CONFIG_TOUCHSCREEN_AD7879_I2C is not set
+# CONFIG_TOUCHSCREEN_AD7879_SPI is not set
+# CONFIG_TOUCHSCREEN_AD7879 is not set
+# CONFIG_TOUCHSCREEN_EETI is not set
 # CONFIG_TOUCHSCREEN_FUJITSU is not set
 # CONFIG_TOUCHSCREEN_GUNZE is not set
 # CONFIG_TOUCHSCREEN_ELO is not set
+# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set
+# CONFIG_TOUCHSCREEN_MCS5000 is not set
 # CONFIG_TOUCHSCREEN_MTOUCH is not set
+# CONFIG_TOUCHSCREEN_INEXIO is not set
 # CONFIG_TOUCHSCREEN_MK712 is not set
 # CONFIG_TOUCHSCREEN_PENMOUNT is not set
 # CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
 # CONFIG_TOUCHSCREEN_TOUCHWIN is not set
-# CONFIG_TOUCHSCREEN_UCB1400 is not set
+CONFIG_TOUCHSCREEN_WM97XX=m
+CONFIG_TOUCHSCREEN_WM9705=y
+CONFIG_TOUCHSCREEN_WM9712=y
+CONFIG_TOUCHSCREEN_WM9713=y
+# CONFIG_TOUCHSCREEN_WM97XX_ATMEL is not set
+# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set
+# CONFIG_TOUCHSCREEN_TSC2007 is not set
+# CONFIG_TOUCHSCREEN_W90X900 is not set
 # CONFIG_INPUT_MISC is not set
 
 #
@@ -619,9 +712,11 @@ CONFIG_INPUT_TOUCHSCREEN=y
 # Character devices
 #
 CONFIG_VT=y
+CONFIG_CONSOLE_TRANSLATIONS=y
 CONFIG_VT_CONSOLE=y
 CONFIG_HW_CONSOLE=y
 # CONFIG_VT_HW_CONSOLE_BINDING is not set
+CONFIG_DEVKMEM=y
 # CONFIG_SERIAL_NONSTANDARD is not set
 
 #
@@ -636,9 +731,11 @@ CONFIG_SERIAL_ATMEL=y
 CONFIG_SERIAL_ATMEL_CONSOLE=y
 CONFIG_SERIAL_ATMEL_PDC=y
 # CONFIG_SERIAL_ATMEL_TTYAT is not set
+# CONFIG_SERIAL_MAX3100 is not set
 CONFIG_SERIAL_CORE=y
 CONFIG_SERIAL_CORE_CONSOLE=y
 CONFIG_UNIX98_PTYS=y
+# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
 # CONFIG_LEGACY_PTYS is not set
 # CONFIG_IPMI_HANDLER is not set
 # CONFIG_HW_RANDOM is not set
@@ -647,45 +744,44 @@ CONFIG_UNIX98_PTYS=y
 # CONFIG_TCG_TPM is not set
 CONFIG_I2C=m
 CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_COMPAT=y
 CONFIG_I2C_CHARDEV=m
+CONFIG_I2C_HELPER_AUTO=y
+CONFIG_I2C_ALGOBIT=m
 
 #
-# I2C Algorithms
+# I2C Hardware Bus support
 #
-CONFIG_I2C_ALGOBIT=m
-# CONFIG_I2C_ALGOPCF is not set
-# CONFIG_I2C_ALGOPCA is not set
 
 #
-# I2C Hardware Bus support
+# I2C system bus drivers (mostly embedded / system-on-chip)
 #
-CONFIG_I2C_ATMELTWI=m
+# CONFIG_I2C_DESIGNWARE is not set
 CONFIG_I2C_GPIO=m
 # CONFIG_I2C_OCORES is not set
-# CONFIG_I2C_PARPORT_LIGHT is not set
 # CONFIG_I2C_SIMTEC is not set
+
+#
+# External I2C/SMBus adapter drivers
+#
+# CONFIG_I2C_PARPORT_LIGHT is not set
 # CONFIG_I2C_TAOS_EVM is not set
+
+#
+# Other I2C/SMBus bus drivers
+#
+# CONFIG_I2C_PCA_PLATFORM is not set
 # CONFIG_I2C_STUB is not set
 
 #
 # Miscellaneous I2C Chip support
 #
 # CONFIG_DS1682 is not set
-# CONFIG_EEPROM_LEGACY is not set
-# CONFIG_SENSORS_PCF8574 is not set
-# CONFIG_PCF8575 is not set
-# CONFIG_SENSORS_PCF8591 is not set
-# CONFIG_TPS65010 is not set
-# CONFIG_SENSORS_MAX6875 is not set
 # CONFIG_SENSORS_TSL2550 is not set
 # CONFIG_I2C_DEBUG_CORE is not set
 # CONFIG_I2C_DEBUG_ALGO is not set
 # CONFIG_I2C_DEBUG_BUS is not set
 # CONFIG_I2C_DEBUG_CHIP is not set
-
-#
-# SPI support
-#
 CONFIG_SPI=y
 # CONFIG_SPI_DEBUG is not set
 CONFIG_SPI_MASTER=y
@@ -695,30 +791,48 @@ CONFIG_SPI_MASTER=y
 #
 CONFIG_SPI_ATMEL=y
 # CONFIG_SPI_BITBANG is not set
+# CONFIG_SPI_GPIO is not set
 
 #
 # SPI Protocol Masters
 #
-# CONFIG_EEPROM_AT25 is not set
 CONFIG_SPI_SPIDEV=m
 # CONFIG_SPI_TLE62X0 is not set
-CONFIG_HAVE_GPIO_LIB=y
 
 #
-# GPIO Support
+# PPS support
 #
+# CONFIG_PPS is not set
+CONFIG_ARCH_REQUIRE_GPIOLIB=y
+CONFIG_GPIOLIB=y
 # CONFIG_DEBUG_GPIO is not set
+# CONFIG_GPIO_SYSFS is not set
+
+#
+# Memory mapped GPIO expanders:
+#
 
 #
 # I2C GPIO expanders:
 #
+# CONFIG_GPIO_MAX732X is not set
 # CONFIG_GPIO_PCA953X is not set
 # CONFIG_GPIO_PCF857X is not set
 
 #
+# PCI GPIO expanders:
+#
+
+#
 # SPI GPIO expanders:
 #
+# CONFIG_GPIO_MAX7301 is not set
 # CONFIG_GPIO_MCP23S08 is not set
+# CONFIG_GPIO_MC33880 is not set
+
+#
+# AC97 GPIO expanders:
+#
 # CONFIG_W1 is not set
 # CONFIG_POWER_SUPPLY is not set
 # CONFIG_HWMON is not set
@@ -731,24 +845,31 @@ CONFIG_WATCHDOG=y
 #
 # CONFIG_SOFT_WATCHDOG is not set
 CONFIG_AT32AP700X_WDT=y
+CONFIG_SSB_POSSIBLE=y
 
 #
 # Sonics Silicon Backplane
 #
-CONFIG_SSB_POSSIBLE=y
 # CONFIG_SSB is not set
 
 #
 # Multifunction device drivers
 #
+# CONFIG_MFD_CORE is not set
 # CONFIG_MFD_SM501 is not set
-
-#
-# Multimedia devices
-#
-# CONFIG_VIDEO_DEV is not set
-# CONFIG_DVB_CORE is not set
-# CONFIG_DAB is not set
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_UCB1400_CORE is not set
+# CONFIG_TPS65010 is not set
+# CONFIG_MFD_TMIO is not set
+# CONFIG_MFD_WM8400 is not set
+# CONFIG_MFD_WM831X is not set
+# CONFIG_MFD_WM8350_I2C is not set
+# CONFIG_MFD_PCF50633 is not set
+# CONFIG_MFD_MC13783 is not set
+# CONFIG_AB3100_CORE is not set
+# CONFIG_EZX_PCAP is not set
+# CONFIG_REGULATOR is not set
+# CONFIG_MEDIA_SUPPORT is not set
 
 #
 # Graphics support
@@ -758,6 +879,7 @@ CONFIG_SSB_POSSIBLE=y
 CONFIG_FB=y
 # CONFIG_FIRMWARE_EDID is not set
 # CONFIG_FB_DDC is not set
+# CONFIG_FB_BOOT_VESA_SUPPORT is not set
 CONFIG_FB_CFB_FILLRECT=y
 CONFIG_FB_CFB_COPYAREA=y
 CONFIG_FB_CFB_IMAGEBLIT=y
@@ -765,8 +887,8 @@ CONFIG_FB_CFB_IMAGEBLIT=y
 # CONFIG_FB_SYS_FILLRECT is not set
 # CONFIG_FB_SYS_COPYAREA is not set
 # CONFIG_FB_SYS_IMAGEBLIT is not set
+# CONFIG_FB_FOREIGN_ENDIAN is not set
 # CONFIG_FB_SYS_FOPS is not set
-CONFIG_FB_DEFERRED_IO=y
 # CONFIG_FB_SVGALIB is not set
 # CONFIG_FB_MACMODES is not set
 # CONFIG_FB_BACKLIGHT is not set
@@ -779,6 +901,9 @@ CONFIG_FB_DEFERRED_IO=y
 # CONFIG_FB_S1D13XXX is not set
 CONFIG_FB_ATMEL=y
 # CONFIG_FB_VIRTUAL is not set
+# CONFIG_FB_METRONOME is not set
+# CONFIG_FB_MB862XX is not set
+# CONFIG_FB_BROADSHEET is not set
 # CONFIG_BACKLIGHT_LCD_SUPPORT is not set
 
 #
@@ -792,119 +917,124 @@ CONFIG_FB_ATMEL=y
 CONFIG_DUMMY_CONSOLE=y
 # CONFIG_FRAMEBUFFER_CONSOLE is not set
 # CONFIG_LOGO is not set
-
-#
-# Sound
-#
 CONFIG_SOUND=y
-
-#
-# Advanced Linux Sound Architecture
-#
+CONFIG_SOUND_OSS_CORE=y
+CONFIG_SOUND_OSS_CORE_PRECLAIM=y
 CONFIG_SND=y
-CONFIG_SND_TIMER=m
+CONFIG_SND_TIMER=y
 CONFIG_SND_PCM=m
 # CONFIG_SND_SEQUENCER is not set
 CONFIG_SND_OSSEMUL=y
 CONFIG_SND_MIXER_OSS=m
 CONFIG_SND_PCM_OSS=m
 CONFIG_SND_PCM_OSS_PLUGINS=y
+CONFIG_SND_HRTIMER=y
 # CONFIG_SND_DYNAMIC_MINORS is not set
 # CONFIG_SND_SUPPORT_OLD_API is not set
 CONFIG_SND_VERBOSE_PROCFS=y
 # CONFIG_SND_VERBOSE_PRINTK is not set
 # CONFIG_SND_DEBUG is not set
-
-#
-# Generic devices
-#
+CONFIG_SND_VMASTER=y
+# CONFIG_SND_RAWMIDI_SEQ is not set
+# CONFIG_SND_OPL3_LIB_SEQ is not set
+# CONFIG_SND_OPL4_LIB_SEQ is not set
+# CONFIG_SND_SBAWE_SEQ is not set
+# CONFIG_SND_EMU10K1_SEQ is not set
 CONFIG_SND_AC97_CODEC=m
-# CONFIG_SND_DUMMY is not set
-# CONFIG_SND_MTPAV is not set
-# CONFIG_SND_SERIAL_U16550 is not set
-# CONFIG_SND_MPU401 is not set
+# CONFIG_SND_DRIVERS is not set
 
 #
-# AVR32 devices
-#
-CONFIG_SND_ATMEL_AC97=m
-
-#
-# SPI devices
-#
-
-#
-# System on Chip audio support
+# Atmel devices (AVR32 and AT91)
 #
+# CONFIG_SND_ATMEL_ABDAC is not set
+CONFIG_SND_ATMEL_AC97C=m
+# CONFIG_SND_SPI is not set
 # CONFIG_SND_SOC is not set
-
-#
-# SoC Audio support for SuperH
-#
-
-#
-# ALSA SoC audio for Freescale SOCs
-#
-
-#
-# Open Sound System
-#
 # CONFIG_SOUND_PRIME is not set
 CONFIG_AC97_BUS=m
 CONFIG_HID_SUPPORT=y
 CONFIG_HID=y
-# CONFIG_HID_DEBUG is not set
 # CONFIG_HIDRAW is not set
+# CONFIG_HID_PID is not set
+
+#
+# Special HID drivers
+#
 CONFIG_USB_SUPPORT=y
 # CONFIG_USB_ARCH_HAS_HCD is not set
 # CONFIG_USB_ARCH_HAS_OHCI is not set
 # CONFIG_USB_ARCH_HAS_EHCI is not set
+# CONFIG_USB_OTG_WHITELIST is not set
+# CONFIG_USB_OTG_BLACKLIST_HUB is not set
+# CONFIG_USB_GADGET_MUSB_HDRC is not set
 
 #
-# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
+# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
 #
 CONFIG_USB_GADGET=y
 # CONFIG_USB_GADGET_DEBUG is not set
 # CONFIG_USB_GADGET_DEBUG_FILES is not set
+# CONFIG_USB_GADGET_DEBUG_FS is not set
+CONFIG_USB_GADGET_VBUS_DRAW=350
 CONFIG_USB_GADGET_SELECTED=y
-# CONFIG_USB_GADGET_AMD5536UDC is not set
+# CONFIG_USB_GADGET_AT91 is not set
 CONFIG_USB_GADGET_ATMEL_USBA=y
 CONFIG_USB_ATMEL_USBA=y
 # CONFIG_USB_GADGET_FSL_USB2 is not set
-# CONFIG_USB_GADGET_NET2280 is not set
-# CONFIG_USB_GADGET_PXA2XX is not set
-# CONFIG_USB_GADGET_M66592 is not set
-# CONFIG_USB_GADGET_GOKU is not set
 # CONFIG_USB_GADGET_LH7A40X is not set
 # CONFIG_USB_GADGET_OMAP is not set
+# CONFIG_USB_GADGET_PXA25X is not set
+# CONFIG_USB_GADGET_R8A66597 is not set
+# CONFIG_USB_GADGET_PXA27X is not set
+# CONFIG_USB_GADGET_S3C_HSOTG is not set
+# CONFIG_USB_GADGET_IMX is not set
 # CONFIG_USB_GADGET_S3C2410 is not set
-# CONFIG_USB_GADGET_AT91 is not set
+# CONFIG_USB_GADGET_M66592 is not set
+# CONFIG_USB_GADGET_AMD5536UDC is not set
+# CONFIG_USB_GADGET_FSL_QE is not set
+# CONFIG_USB_GADGET_CI13XXX is not set
+# CONFIG_USB_GADGET_NET2280 is not set
+# CONFIG_USB_GADGET_GOKU is not set
+# CONFIG_USB_GADGET_LANGWELL is not set
 # CONFIG_USB_GADGET_DUMMY_HCD is not set
 CONFIG_USB_GADGET_DUALSPEED=y
 CONFIG_USB_ZERO=m
+# CONFIG_USB_AUDIO is not set
 CONFIG_USB_ETH=m
 CONFIG_USB_ETH_RNDIS=y
+# CONFIG_USB_ETH_EEM is not set
 CONFIG_USB_GADGETFS=m
 CONFIG_USB_FILE_STORAGE=m
 # CONFIG_USB_FILE_STORAGE_TEST is not set
 CONFIG_USB_G_SERIAL=m
 # CONFIG_USB_MIDI_GADGET is not set
 # CONFIG_USB_G_PRINTER is not set
+CONFIG_USB_CDC_COMPOSITE=m
+
+#
+# OTG and related infrastructure
+#
+# CONFIG_USB_GPIO_VBUS is not set
+# CONFIG_NOP_USB_XCEIV is not set
 CONFIG_MMC=y
 # CONFIG_MMC_DEBUG is not set
 # CONFIG_MMC_UNSAFE_RESUME is not set
 
 #
-# MMC/SD Card Drivers
+# MMC/SD/SDIO Card Drivers
 #
 CONFIG_MMC_BLOCK=y
 CONFIG_MMC_BLOCK_BOUNCE=y
 # CONFIG_SDIO_UART is not set
+# CONFIG_MMC_TEST is not set
 
 #
-# MMC/SD Host Controller Drivers
+# MMC/SD/SDIO Host Controller Drivers
 #
+# CONFIG_MMC_SDHCI is not set
+# CONFIG_MMC_AT91 is not set
 CONFIG_MMC_ATMELMCI=y
+# CONFIG_MMC_ATMELMCI_DMA is not set
 # CONFIG_MMC_SPI is not set
 # CONFIG_MEMSTICK is not set
 CONFIG_NEW_LEDS=y
@@ -913,7 +1043,13 @@ CONFIG_LEDS_CLASS=y
 #
 # LED drivers
 #
+# CONFIG_LEDS_PCA9532 is not set
 CONFIG_LEDS_GPIO=y
+CONFIG_LEDS_GPIO_PLATFORM=y
+# CONFIG_LEDS_LP3944 is not set
+# CONFIG_LEDS_PCA955X is not set
+# CONFIG_LEDS_DAC124S085 is not set
+# CONFIG_LEDS_BD2802 is not set
 
 #
 # LED Triggers
@@ -921,6 +1057,14 @@ CONFIG_LEDS_GPIO=y
 CONFIG_LEDS_TRIGGERS=y
 CONFIG_LEDS_TRIGGER_TIMER=y
 CONFIG_LEDS_TRIGGER_HEARTBEAT=y
+# CONFIG_LEDS_TRIGGER_BACKLIGHT is not set
+# CONFIG_LEDS_TRIGGER_GPIO is not set
+# CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set
+
+#
+# iptables trigger is under Netfilter config (LED target)
+#
+# CONFIG_ACCESSIBILITY is not set
 CONFIG_RTC_LIB=y
 CONFIG_RTC_CLASS=y
 CONFIG_RTC_HCTOSYS=y
@@ -950,51 +1094,84 @@ CONFIG_RTC_INTF_DEV=y
 # CONFIG_RTC_DRV_PCF8583 is not set
 # CONFIG_RTC_DRV_M41T80 is not set
 # CONFIG_RTC_DRV_S35390A is not set
+# CONFIG_RTC_DRV_FM3130 is not set
+# CONFIG_RTC_DRV_RX8581 is not set
+# CONFIG_RTC_DRV_RX8025 is not set
 
 #
 # SPI RTC drivers
 #
+# CONFIG_RTC_DRV_M41T94 is not set
+# CONFIG_RTC_DRV_DS1305 is not set
+# CONFIG_RTC_DRV_DS1390 is not set
 # CONFIG_RTC_DRV_MAX6902 is not set
 # CONFIG_RTC_DRV_R9701 is not set
 # CONFIG_RTC_DRV_RS5C348 is not set
+# CONFIG_RTC_DRV_DS3234 is not set
+# CONFIG_RTC_DRV_PCF2123 is not set
 
 #
 # Platform RTC drivers
 #
+# CONFIG_RTC_DRV_DS1286 is not set
 # CONFIG_RTC_DRV_DS1511 is not set
 # CONFIG_RTC_DRV_DS1553 is not set
 # CONFIG_RTC_DRV_DS1742 is not set
 # CONFIG_RTC_DRV_STK17TA8 is not set
 # CONFIG_RTC_DRV_M48T86 is not set
+# CONFIG_RTC_DRV_M48T35 is not set
 # CONFIG_RTC_DRV_M48T59 is not set
+# CONFIG_RTC_DRV_BQ4802 is not set
 # CONFIG_RTC_DRV_V3020 is not set
 
 #
 # on-CPU RTC drivers
 #
 CONFIG_RTC_DRV_AT32AP700X=y
+CONFIG_DMADEVICES=y
 
 #
-# Userspace I/O
+# DMA Devices
 #
+CONFIG_DW_DMAC=y
+CONFIG_DMA_ENGINE=y
+
+#
+# DMA Clients
+#
+# CONFIG_NET_DMA is not set
+# CONFIG_ASYNC_TX_DMA is not set
+# CONFIG_DMATEST is not set
+# CONFIG_AUXDISPLAY is not set
 # CONFIG_UIO is not set
 
 #
+# TI VLYNQ
+#
+# CONFIG_STAGING is not set
+
+#
 # File systems
 #
 CONFIG_EXT2_FS=y
 # CONFIG_EXT2_FS_XATTR is not set
 # CONFIG_EXT2_FS_XIP is not set
 CONFIG_EXT3_FS=y
+# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
 # CONFIG_EXT3_FS_XATTR is not set
-# CONFIG_EXT4DEV_FS is not set
+# CONFIG_EXT4_FS is not set
 CONFIG_JBD=y
+# CONFIG_JBD_DEBUG is not set
 # CONFIG_REISERFS_FS is not set
 # CONFIG_JFS_FS is not set
 # CONFIG_FS_POSIX_ACL is not set
 # CONFIG_XFS_FS is not set
 # CONFIG_GFS2_FS is not set
 # CONFIG_OCFS2_FS is not set
+# CONFIG_BTRFS_FS is not set
+# CONFIG_NILFS2_FS is not set
+CONFIG_FILE_LOCKING=y
+CONFIG_FSNOTIFY=y
 # CONFIG_DNOTIFY is not set
 CONFIG_INOTIFY=y
 CONFIG_INOTIFY_USER=y
@@ -1002,6 +1179,12 @@ CONFIG_INOTIFY_USER=y
 # CONFIG_AUTOFS_FS is not set
 # CONFIG_AUTOFS4_FS is not set
 CONFIG_FUSE_FS=m
+# CONFIG_CUSE is not set
+
+#
+# Caches
+#
+# CONFIG_FSCACHE is not set
 
 #
 # CD-ROM/DVD Filesystems
@@ -1025,15 +1208,13 @@ CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
 CONFIG_PROC_FS=y
 # CONFIG_PROC_KCORE is not set
 CONFIG_PROC_SYSCTL=y
+CONFIG_PROC_PAGE_MONITOR=y
 CONFIG_SYSFS=y
 CONFIG_TMPFS=y
 # CONFIG_TMPFS_POSIX_ACL is not set
 # CONFIG_HUGETLB_PAGE is not set
 CONFIG_CONFIGFS_FS=y
-
-#
-# Miscellaneous filesystems
-#
+CONFIG_MISC_FILESYSTEMS=y
 # CONFIG_ADFS_FS is not set
 # CONFIG_AFFS_FS is not set
 # CONFIG_HFS_FS is not set
@@ -1059,8 +1240,10 @@ CONFIG_UBIFS_FS_LZO=y
 CONFIG_UBIFS_FS_ZLIB=y
 # CONFIG_UBIFS_FS_DEBUG is not set
 # CONFIG_CRAMFS is not set
+# CONFIG_SQUASHFS is not set
 # CONFIG_VXFS_FS is not set
 # CONFIG_MINIX_FS is not set
+# CONFIG_OMFS_FS is not set
 # CONFIG_HPFS_FS is not set
 # CONFIG_QNX4FS_FS is not set
 # CONFIG_ROMFS_FS is not set
@@ -1071,19 +1254,16 @@ CONFIG_NFS_FS=y
 CONFIG_NFS_V3=y
 # CONFIG_NFS_V3_ACL is not set
 # CONFIG_NFS_V4 is not set
-# CONFIG_NFS_DIRECTIO is not set
+CONFIG_ROOT_NFS=y
 CONFIG_NFSD=m
 CONFIG_NFSD_V3=y
 # CONFIG_NFSD_V3_ACL is not set
 # CONFIG_NFSD_V4 is not set
-CONFIG_NFSD_TCP=y
-CONFIG_ROOT_NFS=y
 CONFIG_LOCKD=y
 CONFIG_LOCKD_V4=y
 CONFIG_EXPORTFS=m
 CONFIG_NFS_COMMON=y
 CONFIG_SUNRPC=y
-# CONFIG_SUNRPC_BIND34 is not set
 # CONFIG_RPCSEC_GSS_KRB5 is not set
 # CONFIG_RPCSEC_GSS_SPKM3 is not set
 CONFIG_SMB_FS=m
@@ -1151,16 +1331,24 @@ CONFIG_NLS_UTF8=m
 # CONFIG_PRINTK_TIME is not set
 CONFIG_ENABLE_WARN_DEPRECATED=y
 CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_FRAME_WARN=1024
 CONFIG_MAGIC_SYSRQ=y
+# CONFIG_STRIP_ASM_SYMS is not set
 # CONFIG_UNUSED_SYMBOLS is not set
-# CONFIG_DEBUG_FS is not set
+CONFIG_DEBUG_FS=y
 # CONFIG_HEADERS_CHECK is not set
 CONFIG_DEBUG_KERNEL=y
 # CONFIG_DEBUG_SHIRQ is not set
 CONFIG_DETECT_SOFTLOCKUP=y
+# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
+CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
+CONFIG_DETECT_HUNG_TASK=y
+# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set
+CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0
 CONFIG_SCHED_DEBUG=y
 # CONFIG_SCHEDSTATS is not set
 # CONFIG_TIMER_STATS is not set
+# CONFIG_DEBUG_OBJECTS is not set
 # CONFIG_SLUB_DEBUG_ON is not set
 # CONFIG_SLUB_STATS is not set
 # CONFIG_DEBUG_RT_MUTEXES is not set
@@ -1172,19 +1360,48 @@ CONFIG_SCHED_DEBUG=y
 # CONFIG_LOCK_STAT is not set
 # CONFIG_DEBUG_SPINLOCK_SLEEP is not set
 # CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+CONFIG_STACKTRACE=y
 # CONFIG_DEBUG_KOBJECT is not set
 CONFIG_DEBUG_BUGVERBOSE=y
 # CONFIG_DEBUG_INFO is not set
 # CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_WRITECOUNT is not set
+# CONFIG_DEBUG_MEMORY_INIT is not set
 # CONFIG_DEBUG_LIST is not set
 # CONFIG_DEBUG_SG is not set
+# CONFIG_DEBUG_NOTIFIERS is not set
+# CONFIG_DEBUG_CREDENTIALS is not set
 CONFIG_FRAME_POINTER=y
 # CONFIG_BOOT_PRINTK_DELAY is not set
 # CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_RCU_CPU_STALL_DETECTOR is not set
 # CONFIG_KPROBES_SANITY_TEST is not set
 # CONFIG_BACKTRACE_SELF_TEST is not set
+# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
+# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
 # CONFIG_LKDTM is not set
 # CONFIG_FAULT_INJECTION is not set
+# CONFIG_PAGE_POISONING is not set
+CONFIG_NOP_TRACER=y
+CONFIG_RING_BUFFER=y
+CONFIG_EVENT_TRACING=y
+CONFIG_CONTEXT_SWITCH_TRACER=y
+CONFIG_RING_BUFFER_ALLOW_SWAP=y
+CONFIG_TRACING=y
+CONFIG_TRACING_SUPPORT=y
+CONFIG_FTRACE=y
+# CONFIG_IRQSOFF_TRACER is not set
+# CONFIG_SCHED_TRACER is not set
+# CONFIG_ENABLE_DEFAULT_TRACERS is not set
+# CONFIG_BOOT_TRACER is not set
+CONFIG_BRANCH_PROFILE_NONE=y
+# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set
+# CONFIG_PROFILE_ALL_BRANCHES is not set
+# CONFIG_KMEMTRACE is not set
+# CONFIG_WORKQUEUE_TRACER is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_RING_BUFFER_BENCHMARK is not set
+# CONFIG_DYNAMIC_DEBUG is not set
 # CONFIG_SAMPLES is not set
 
 #
@@ -1192,63 +1409,118 @@ CONFIG_FRAME_POINTER=y
 #
 # CONFIG_KEYS is not set
 # CONFIG_SECURITY is not set
+# CONFIG_SECURITYFS is not set
 # CONFIG_SECURITY_FILE_CAPABILITIES is not set
 CONFIG_CRYPTO=y
+
+#
+# Crypto core or helper
+#
+# CONFIG_CRYPTO_FIPS is not set
 CONFIG_CRYPTO_ALGAPI=y
+CONFIG_CRYPTO_ALGAPI2=y
 CONFIG_CRYPTO_AEAD=y
+CONFIG_CRYPTO_AEAD2=y
 CONFIG_CRYPTO_BLKCIPHER=y
-# CONFIG_CRYPTO_SEQIV is not set
+CONFIG_CRYPTO_BLKCIPHER2=y
 CONFIG_CRYPTO_HASH=y
+CONFIG_CRYPTO_HASH2=y
+CONFIG_CRYPTO_RNG=m
+CONFIG_CRYPTO_RNG2=y
+CONFIG_CRYPTO_PCOMP=y
 CONFIG_CRYPTO_MANAGER=y
+CONFIG_CRYPTO_MANAGER2=y
+# CONFIG_CRYPTO_GF128MUL is not set
+# CONFIG_CRYPTO_NULL is not set
+CONFIG_CRYPTO_WORKQUEUE=y
+# CONFIG_CRYPTO_CRYPTD is not set
+CONFIG_CRYPTO_AUTHENC=y
+# CONFIG_CRYPTO_TEST is not set
+
+#
+# Authenticated Encryption with Associated Data
+#
+# CONFIG_CRYPTO_CCM is not set
+# CONFIG_CRYPTO_GCM is not set
+# CONFIG_CRYPTO_SEQIV is not set
+
+#
+# Block modes
+#
+CONFIG_CRYPTO_CBC=y
+# CONFIG_CRYPTO_CTR is not set
+# CONFIG_CRYPTO_CTS is not set
+CONFIG_CRYPTO_ECB=m
+# CONFIG_CRYPTO_LRW is not set
+# CONFIG_CRYPTO_PCBC is not set
+# CONFIG_CRYPTO_XTS is not set
+
+#
+# Hash modes
+#
 CONFIG_CRYPTO_HMAC=y
 # CONFIG_CRYPTO_XCBC is not set
-# CONFIG_CRYPTO_NULL is not set
+# CONFIG_CRYPTO_VMAC is not set
+
+#
+# Digest
+#
+# CONFIG_CRYPTO_CRC32C is not set
+# CONFIG_CRYPTO_GHASH is not set
 # CONFIG_CRYPTO_MD4 is not set
 CONFIG_CRYPTO_MD5=y
+# CONFIG_CRYPTO_MICHAEL_MIC is not set
+# CONFIG_CRYPTO_RMD128 is not set
+# CONFIG_CRYPTO_RMD160 is not set
+# CONFIG_CRYPTO_RMD256 is not set
+# CONFIG_CRYPTO_RMD320 is not set
 CONFIG_CRYPTO_SHA1=y
 # CONFIG_CRYPTO_SHA256 is not set
 # CONFIG_CRYPTO_SHA512 is not set
-# CONFIG_CRYPTO_WP512 is not set
 # CONFIG_CRYPTO_TGR192 is not set
-# CONFIG_CRYPTO_GF128MUL is not set
-CONFIG_CRYPTO_ECB=m
-CONFIG_CRYPTO_CBC=y
-# CONFIG_CRYPTO_PCBC is not set
-# CONFIG_CRYPTO_LRW is not set
-# CONFIG_CRYPTO_XTS is not set
-# CONFIG_CRYPTO_CTR is not set
-# CONFIG_CRYPTO_GCM is not set
-# CONFIG_CRYPTO_CCM is not set
-# CONFIG_CRYPTO_CRYPTD is not set
-CONFIG_CRYPTO_DES=y
-# CONFIG_CRYPTO_FCRYPT is not set
+# CONFIG_CRYPTO_WP512 is not set
+
+#
+# Ciphers
+#
+CONFIG_CRYPTO_AES=m
+# CONFIG_CRYPTO_ANUBIS is not set
+CONFIG_CRYPTO_ARC4=m
 # CONFIG_CRYPTO_BLOWFISH is not set
-# CONFIG_CRYPTO_TWOFISH is not set
-# CONFIG_CRYPTO_SERPENT is not set
-# CONFIG_CRYPTO_AES is not set
+# CONFIG_CRYPTO_CAMELLIA is not set
 # CONFIG_CRYPTO_CAST5 is not set
 # CONFIG_CRYPTO_CAST6 is not set
-# CONFIG_CRYPTO_TEA is not set
-CONFIG_CRYPTO_ARC4=m
+CONFIG_CRYPTO_DES=y
+# CONFIG_CRYPTO_FCRYPT is not set
 # CONFIG_CRYPTO_KHAZAD is not set
-# CONFIG_CRYPTO_ANUBIS is not set
-# CONFIG_CRYPTO_SEED is not set
 # CONFIG_CRYPTO_SALSA20 is not set
+# CONFIG_CRYPTO_SEED is not set
+# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_TEA is not set
+# CONFIG_CRYPTO_TWOFISH is not set
+
+#
+# Compression
+#
 CONFIG_CRYPTO_DEFLATE=y
-# CONFIG_CRYPTO_MICHAEL_MIC is not set
-# CONFIG_CRYPTO_CRC32C is not set
-# CONFIG_CRYPTO_CAMELLIA is not set
-# CONFIG_CRYPTO_TEST is not set
-CONFIG_CRYPTO_AUTHENC=y
+# CONFIG_CRYPTO_ZLIB is not set
 CONFIG_CRYPTO_LZO=y
+
+#
+# Random Number Generation
+#
+CONFIG_CRYPTO_ANSI_CPRNG=m
 CONFIG_CRYPTO_HW=y
+CONFIG_BINARY_PRINTF=y
 
 #
 # Library routines
 #
 CONFIG_BITREVERSE=y
+CONFIG_GENERIC_FIND_LAST_BIT=y
 CONFIG_CRC_CCITT=m
 CONFIG_CRC16=y
+# CONFIG_CRC_T10DIF is not set
 # CONFIG_CRC_ITU_T is not set
 CONFIG_CRC32=y
 # CONFIG_CRC7 is not set
@@ -1257,8 +1529,9 @@ CONFIG_ZLIB_INFLATE=y
 CONFIG_ZLIB_DEFLATE=y
 CONFIG_LZO_COMPRESS=y
 CONFIG_LZO_DECOMPRESS=y
+CONFIG_DECOMPRESS_GZIP=y
 CONFIG_GENERIC_ALLOCATOR=y
-CONFIG_PLIST=y
 CONFIG_HAS_IOMEM=y
 CONFIG_HAS_IOPORT=y
 CONFIG_HAS_DMA=y
+CONFIG_NLATTR=y
diff --git a/arch/avr32/configs/atngw100mkii_defconfig b/arch/avr32/configs/atngw100mkii_defconfig
new file mode 100644
index 000000000000..9b8b5b3b9c71
--- /dev/null
+++ b/arch/avr32/configs/atngw100mkii_defconfig
@@ -0,0 +1,1414 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.32-rc5
+# Thu Nov  5 15:32:26 2009
+#
+CONFIG_AVR32=y
+CONFIG_GENERIC_GPIO=y
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_GENERIC_BUG=y
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+CONFIG_CONSTRUCTORS=y
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION=""
+# CONFIG_LOCALVERSION_AUTO is not set
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_POSIX_MQUEUE_SYSCTL=y
+CONFIG_BSD_PROCESS_ACCT=y
+CONFIG_BSD_PROCESS_ACCT_V3=y
+# CONFIG_TASKSTATS is not set
+# CONFIG_AUDIT is not set
+
+#
+# RCU Subsystem
+#
+CONFIG_TREE_RCU=y
+# CONFIG_TREE_PREEMPT_RCU is not set
+# CONFIG_RCU_TRACE is not set
+CONFIG_RCU_FANOUT=32
+# CONFIG_RCU_FANOUT_EXACT is not set
+# CONFIG_TREE_RCU_TRACE is not set
+# CONFIG_IKCONFIG is not set
+CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_GROUP_SCHED is not set
+# CONFIG_CGROUPS is not set
+CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SYSFS_DEPRECATED_V2=y
+# CONFIG_RELAY is not set
+# CONFIG_NAMESPACES is not set
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_RD_GZIP=y
+# CONFIG_RD_BZIP2 is not set
+# CONFIG_RD_LZMA is not set
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_SYSCTL=y
+CONFIG_ANON_INODES=y
+CONFIG_EMBEDDED=y
+# CONFIG_SYSCTL_SYSCALL is not set
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_ALL is not set
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+# CONFIG_BASE_FULL is not set
+CONFIG_FUTEX=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_AIO=y
+
+#
+# Kernel Performance Events And Counters
+#
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLUB_DEBUG=y
+# CONFIG_COMPAT_BRK is not set
+# CONFIG_SLAB is not set
+CONFIG_SLUB=y
+# CONFIG_SLOB is not set
+CONFIG_PROFILING=y
+CONFIG_TRACEPOINTS=y
+CONFIG_OPROFILE=m
+CONFIG_HAVE_OPROFILE=y
+CONFIG_KPROBES=y
+CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_CLK=y
+
+#
+# GCOV-based kernel profiling
+#
+# CONFIG_GCOV_KERNEL is not set
+CONFIG_SLOW_WORK=y
+# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
+CONFIG_BASE_SMALL=1
+CONFIG_MODULES=y
+# CONFIG_MODULE_FORCE_LOAD is not set
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODULE_FORCE_UNLOAD=y
+# CONFIG_MODVERSIONS is not set
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+CONFIG_BLOCK=y
+CONFIG_LBDAF=y
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_BLK_DEV_INTEGRITY is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+# CONFIG_IOSCHED_AS is not set
+# CONFIG_IOSCHED_DEADLINE is not set
+CONFIG_IOSCHED_CFQ=y
+# CONFIG_DEFAULT_AS is not set
+# CONFIG_DEFAULT_DEADLINE is not set
+CONFIG_DEFAULT_CFQ=y
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="cfq"
+CONFIG_FREEZER=y
+
+#
+# System Type and features
+#
+CONFIG_TICK_ONESHOT=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+CONFIG_SUBARCH_AVR32B=y
+CONFIG_MMU=y
+CONFIG_PERFORMANCE_COUNTERS=y
+CONFIG_PLATFORM_AT32AP=y
+CONFIG_CPU_AT32AP700X=y
+CONFIG_CPU_AT32AP7000=y
+CONFIG_BOARD_ATNGW100_COMMON=y
+# CONFIG_BOARD_ATSTK1000 is not set
+# CONFIG_BOARD_ATNGW100_MKI is not set
+CONFIG_BOARD_ATNGW100_MKII=y
+# CONFIG_BOARD_HAMMERHEAD is not set
+# CONFIG_BOARD_FAVR_32 is not set
+# CONFIG_BOARD_MERISC is not set
+# CONFIG_BOARD_MIMC200 is not set
+# CONFIG_BOARD_ATNGW100_MKII_LCD is not set
+CONFIG_BOARD_ATNGW100_ADDON_NONE=y
+# CONFIG_BOARD_ATNGW100_EVKLCD10X is not set
+# CONFIG_BOARD_ATNGW100_MRMT is not set
+CONFIG_LOADER_U_BOOT=y
+
+#
+# Atmel AVR32 AP options
+#
+# CONFIG_AP700X_32_BIT_SMC is not set
+CONFIG_AP700X_16_BIT_SMC=y
+# CONFIG_AP700X_8_BIT_SMC is not set
+CONFIG_LOAD_ADDRESS=0x10000000
+CONFIG_ENTRY_ADDRESS=0x90000000
+CONFIG_PHYS_OFFSET=0x10000000
+CONFIG_PREEMPT_NONE=y
+# CONFIG_PREEMPT_VOLUNTARY is not set
+# CONFIG_PREEMPT is not set
+CONFIG_QUICKLIST=y
+# CONFIG_HAVE_ARCH_BOOTMEM is not set
+# CONFIG_ARCH_HAVE_MEMORY_PRESENT is not set
+# CONFIG_NEED_NODE_MEMMAP_SIZE is not set
+CONFIG_ARCH_FLATMEM_ENABLE=y
+# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
+# CONFIG_ARCH_SPARSEMEM_ENABLE is not set
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_SPLIT_PTLOCK_CPUS=4
+# CONFIG_PHYS_ADDR_T_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=0
+CONFIG_NR_QUICK=2
+CONFIG_VIRT_TO_BUS=y
+CONFIG_HAVE_MLOCK=y
+CONFIG_HAVE_MLOCKED_PAGE_BIT=y
+# CONFIG_KSM is not set
+CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
+# CONFIG_OWNERSHIP_TRACE is not set
+CONFIG_NMI_DEBUGGING=y
+# CONFIG_HZ_100 is not set
+CONFIG_HZ_250=y
+# CONFIG_HZ_300 is not set
+# CONFIG_HZ_1000 is not set
+CONFIG_HZ=250
+CONFIG_SCHED_HRTICK=y
+CONFIG_CMDLINE=""
+
+#
+# Power management options
+#
+CONFIG_PM=y
+# CONFIG_PM_DEBUG is not set
+CONFIG_PM_SLEEP=y
+CONFIG_SUSPEND=y
+CONFIG_SUSPEND_FREEZER=y
+# CONFIG_PM_RUNTIME is not set
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+
+#
+# CPU Frequency scaling
+#
+CONFIG_CPU_FREQ=y
+CONFIG_CPU_FREQ_TABLE=y
+# CONFIG_CPU_FREQ_DEBUG is not set
+# CONFIG_CPU_FREQ_STAT is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set
+CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
+# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set
+CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
+# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set
+CONFIG_CPU_FREQ_GOV_USERSPACE=y
+CONFIG_CPU_FREQ_GOV_ONDEMAND=y
+# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set
+CONFIG_CPU_FREQ_AT32AP=y
+
+#
+# Bus options
+#
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+# CONFIG_PCCARD is not set
+
+#
+# Executable file formats
+#
+CONFIG_BINFMT_ELF=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+# CONFIG_HAVE_AOUT is not set
+# CONFIG_BINFMT_MISC is not set
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+CONFIG_PACKET_MMAP=y
+CONFIG_UNIX=y
+CONFIG_XFRM=y
+CONFIG_XFRM_USER=y
+# CONFIG_XFRM_SUB_POLICY is not set
+# CONFIG_XFRM_MIGRATE is not set
+# CONFIG_XFRM_STATISTICS is not set
+CONFIG_XFRM_IPCOMP=y
+CONFIG_NET_KEY=y
+# CONFIG_NET_KEY_MIGRATE is not set
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_ADVANCED_ROUTER=y
+CONFIG_ASK_IP_FIB_HASH=y
+# CONFIG_IP_FIB_TRIE is not set
+CONFIG_IP_FIB_HASH=y
+# CONFIG_IP_MULTIPLE_TABLES is not set
+# CONFIG_IP_ROUTE_MULTIPATH is not set
+# CONFIG_IP_ROUTE_VERBOSE is not set
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+# CONFIG_IP_PNP_BOOTP is not set
+# CONFIG_IP_PNP_RARP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+CONFIG_IP_MROUTE=y
+CONFIG_IP_PIMSM_V1=y
+# CONFIG_IP_PIMSM_V2 is not set
+# CONFIG_ARPD is not set
+CONFIG_SYN_COOKIES=y
+CONFIG_INET_AH=y
+CONFIG_INET_ESP=y
+CONFIG_INET_IPCOMP=y
+CONFIG_INET_XFRM_TUNNEL=y
+CONFIG_INET_TUNNEL=y
+CONFIG_INET_XFRM_MODE_TRANSPORT=y
+CONFIG_INET_XFRM_MODE_TUNNEL=y
+CONFIG_INET_XFRM_MODE_BEET=y
+# CONFIG_INET_LRO is not set
+CONFIG_INET_DIAG=y
+CONFIG_INET_TCP_DIAG=y
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+CONFIG_IPV6=y
+# CONFIG_IPV6_PRIVACY is not set
+# CONFIG_IPV6_ROUTER_PREF is not set
+# CONFIG_IPV6_OPTIMISTIC_DAD is not set
+CONFIG_INET6_AH=y
+CONFIG_INET6_ESP=y
+CONFIG_INET6_IPCOMP=y
+# CONFIG_IPV6_MIP6 is not set
+CONFIG_INET6_XFRM_TUNNEL=y
+CONFIG_INET6_TUNNEL=y
+CONFIG_INET6_XFRM_MODE_TRANSPORT=y
+CONFIG_INET6_XFRM_MODE_TUNNEL=y
+CONFIG_INET6_XFRM_MODE_BEET=y
+# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set
+CONFIG_IPV6_SIT=y
+CONFIG_IPV6_NDISC_NODETYPE=y
+# CONFIG_IPV6_TUNNEL is not set
+# CONFIG_IPV6_MULTIPLE_TABLES is not set
+# CONFIG_IPV6_MROUTE is not set
+# CONFIG_NETWORK_SECMARK is not set
+CONFIG_NETFILTER=y
+# CONFIG_NETFILTER_DEBUG is not set
+# CONFIG_NETFILTER_ADVANCED is not set
+
+#
+# Core Netfilter Configuration
+#
+CONFIG_NETFILTER_NETLINK=m
+CONFIG_NETFILTER_NETLINK_LOG=m
+CONFIG_NF_CONNTRACK=m
+CONFIG_NF_CONNTRACK_FTP=m
+CONFIG_NF_CONNTRACK_IRC=m
+CONFIG_NF_CONNTRACK_SIP=m
+CONFIG_NF_CT_NETLINK=m
+CONFIG_NETFILTER_XTABLES=y
+CONFIG_NETFILTER_XT_TARGET_MARK=m
+CONFIG_NETFILTER_XT_TARGET_NFLOG=m
+CONFIG_NETFILTER_XT_TARGET_TCPMSS=m
+CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
+CONFIG_NETFILTER_XT_MATCH_MARK=m
+CONFIG_NETFILTER_XT_MATCH_POLICY=m
+CONFIG_NETFILTER_XT_MATCH_STATE=m
+# CONFIG_IP_VS is not set
+
+#
+# IP: Netfilter Configuration
+#
+CONFIG_NF_DEFRAG_IPV4=m
+CONFIG_NF_CONNTRACK_IPV4=m
+CONFIG_NF_CONNTRACK_PROC_COMPAT=y
+CONFIG_IP_NF_IPTABLES=m
+CONFIG_IP_NF_FILTER=m
+CONFIG_IP_NF_TARGET_REJECT=m
+CONFIG_IP_NF_TARGET_LOG=m
+# CONFIG_IP_NF_TARGET_ULOG is not set
+CONFIG_NF_NAT=m
+CONFIG_NF_NAT_NEEDED=y
+CONFIG_IP_NF_TARGET_MASQUERADE=m
+CONFIG_NF_NAT_FTP=m
+CONFIG_NF_NAT_IRC=m
+# CONFIG_NF_NAT_TFTP is not set
+# CONFIG_NF_NAT_AMANDA is not set
+# CONFIG_NF_NAT_PPTP is not set
+# CONFIG_NF_NAT_H323 is not set
+CONFIG_NF_NAT_SIP=m
+CONFIG_IP_NF_MANGLE=m
+
+#
+# IPv6: Netfilter Configuration
+#
+CONFIG_NF_CONNTRACK_IPV6=m
+CONFIG_IP6_NF_IPTABLES=m
+CONFIG_IP6_NF_MATCH_IPV6HEADER=m
+CONFIG_IP6_NF_TARGET_LOG=m
+CONFIG_IP6_NF_FILTER=m
+CONFIG_IP6_NF_TARGET_REJECT=m
+CONFIG_IP6_NF_MANGLE=m
+# CONFIG_IP_DCCP is not set
+# CONFIG_IP_SCTP is not set
+# CONFIG_RDS is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+CONFIG_STP=m
+CONFIG_BRIDGE=m
+# CONFIG_NET_DSA is not set
+CONFIG_VLAN_8021Q=m
+# CONFIG_VLAN_8021Q_GVRP is not set
+# CONFIG_DECNET is not set
+CONFIG_LLC=m
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_PHONET is not set
+# CONFIG_IEEE802154 is not set
+# CONFIG_NET_SCHED is not set
+# CONFIG_DCB is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_NET_TCPPROBE is not set
+# CONFIG_NET_DROP_MONITOR is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+# CONFIG_AF_RXRPC is not set
+CONFIG_WIRELESS=y
+# CONFIG_CFG80211 is not set
+CONFIG_CFG80211_DEFAULT_PS_VALUE=0
+# CONFIG_WIRELESS_OLD_REGULATORY is not set
+# CONFIG_WIRELESS_EXT is not set
+# CONFIG_LIB80211 is not set
+
+#
+# CFG80211 needs to be enabled for MAC80211
+#
+# CONFIG_WIMAX is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+# CONFIG_DEVTMPFS is not set
+CONFIG_STANDALONE=y
+# CONFIG_PREVENT_FIRMWARE_BUILD is not set
+# CONFIG_FW_LOADER is not set
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
+# CONFIG_SYS_HYPERVISOR is not set
+# CONFIG_CONNECTOR is not set
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+# CONFIG_MTD_TESTS is not set
+# CONFIG_MTD_CONCAT is not set
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_REDBOOT_PARTS is not set
+CONFIG_MTD_CMDLINE_PARTS=y
+# CONFIG_MTD_AR7_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+CONFIG_MTD_CFI=y
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_GEN_PROBE=y
+# CONFIG_MTD_CFI_ADV_OPTIONS is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+CONFIG_MTD_CFI_INTELEXT=y
+# CONFIG_MTD_CFI_AMDSTD is not set
+# CONFIG_MTD_CFI_STAA is not set
+CONFIG_MTD_CFI_UTIL=y
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+CONFIG_MTD_PHYSMAP=y
+# CONFIG_MTD_PHYSMAP_COMPAT is not set
+# CONFIG_MTD_PLATRAM is not set
+
+#
+# Self-contained MTD device drivers
+#
+CONFIG_MTD_DATAFLASH=y
+# CONFIG_MTD_DATAFLASH_WRITE_VERIFY is not set
+# CONFIG_MTD_DATAFLASH_OTP is not set
+# CONFIG_MTD_M25P80 is not set
+# CONFIG_MTD_SST25L is not set
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+CONFIG_MTD_NAND=y
+# CONFIG_MTD_NAND_VERIFY_WRITE is not set
+# CONFIG_MTD_NAND_ECC_SMC is not set
+# CONFIG_MTD_NAND_MUSEUM_IDS is not set
+CONFIG_MTD_NAND_IDS=y
+# CONFIG_MTD_NAND_DISKONCHIP is not set
+CONFIG_MTD_NAND_ATMEL=y
+CONFIG_MTD_NAND_ATMEL_ECC_HW=y
+# CONFIG_MTD_NAND_ATMEL_ECC_SOFT is not set
+# CONFIG_MTD_NAND_ATMEL_ECC_NONE is not set
+# CONFIG_MTD_NAND_NANDSIM is not set
+# CONFIG_MTD_NAND_PLATFORM is not set
+# CONFIG_MTD_ONENAND is not set
+
+#
+# LPDDR flash memory drivers
+#
+# CONFIG_MTD_LPDDR is not set
+
+#
+# UBI - Unsorted block images
+#
+CONFIG_MTD_UBI=y
+CONFIG_MTD_UBI_WL_THRESHOLD=4096
+CONFIG_MTD_UBI_BEB_RESERVE=1
+# CONFIG_MTD_UBI_GLUEBI is not set
+
+#
+# UBI debugging options
+#
+# CONFIG_MTD_UBI_DEBUG is not set
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=m
+# CONFIG_BLK_DEV_CRYPTOLOOP is not set
+CONFIG_BLK_DEV_NBD=m
+CONFIG_BLK_DEV_RAM=m
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=4096
+# CONFIG_BLK_DEV_XIP is not set
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+CONFIG_MISC_DEVICES=y
+# CONFIG_ATMEL_PWM is not set
+CONFIG_ATMEL_TCLIB=y
+CONFIG_ATMEL_TCB_CLKSRC=y
+CONFIG_ATMEL_TCB_CLKSRC_BLOCK=0
+# CONFIG_ICS932S401 is not set
+# CONFIG_ATMEL_SSC is not set
+# CONFIG_ENCLOSURE_SERVICES is not set
+# CONFIG_ISL29003 is not set
+# CONFIG_C2PORT is not set
+
+#
+# EEPROM support
+#
+# CONFIG_EEPROM_AT24 is not set
+# CONFIG_EEPROM_AT25 is not set
+# CONFIG_EEPROM_LEGACY is not set
+# CONFIG_EEPROM_MAX6875 is not set
+# CONFIG_EEPROM_93CX6 is not set
+
+#
+# SCSI device support
+#
+# CONFIG_RAID_ATTRS is not set
+# CONFIG_SCSI is not set
+# CONFIG_SCSI_DMA is not set
+# CONFIG_SCSI_NETLINK is not set
+# CONFIG_ATA is not set
+# CONFIG_MD is not set
+CONFIG_NETDEVICES=y
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
+# CONFIG_EQUALIZER is not set
+CONFIG_TUN=m
+# CONFIG_VETH is not set
+CONFIG_PHYLIB=y
+
+#
+# MII PHY device drivers
+#
+# CONFIG_MARVELL_PHY is not set
+# CONFIG_DAVICOM_PHY is not set
+# CONFIG_QSEMI_PHY is not set
+# CONFIG_LXT_PHY is not set
+# CONFIG_CICADA_PHY is not set
+# CONFIG_VITESSE_PHY is not set
+# CONFIG_SMSC_PHY is not set
+# CONFIG_BROADCOM_PHY is not set
+# CONFIG_ICPLUS_PHY is not set
+# CONFIG_REALTEK_PHY is not set
+# CONFIG_NATIONAL_PHY is not set
+# CONFIG_STE10XP is not set
+# CONFIG_LSI_ET1011C_PHY is not set
+# CONFIG_FIXED_PHY is not set
+# CONFIG_MDIO_BITBANG is not set
+CONFIG_NET_ETHERNET=y
+# CONFIG_MII is not set
+CONFIG_MACB=y
+# CONFIG_ENC28J60 is not set
+# CONFIG_ETHOC is not set
+# CONFIG_DNET is not set
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
+# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
+# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
+# CONFIG_B44 is not set
+# CONFIG_KS8842 is not set
+# CONFIG_KS8851 is not set
+# CONFIG_KS8851_MLL is not set
+# CONFIG_NETDEV_1000 is not set
+# CONFIG_NETDEV_10000 is not set
+CONFIG_WLAN=y
+# CONFIG_WLAN_PRE80211 is not set
+# CONFIG_WLAN_80211 is not set
+
+#
+# Enable WiMAX (Networking options) to see the WiMAX drivers
+#
+# CONFIG_WAN is not set
+CONFIG_PPP=m
+# CONFIG_PPP_MULTILINK is not set
+CONFIG_PPP_FILTER=y
+CONFIG_PPP_ASYNC=m
+# CONFIG_PPP_SYNC_TTY is not set
+CONFIG_PPP_DEFLATE=m
+CONFIG_PPP_BSDCOMP=m
+CONFIG_PPP_MPPE=m
+CONFIG_PPPOE=m
+# CONFIG_PPPOL2TP is not set
+# CONFIG_SLIP is not set
+CONFIG_SLHC=m
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_ISDN is not set
+# CONFIG_PHONE is not set
+
+#
+# Input device support
+#
+# CONFIG_INPUT is not set
+
+#
+# Hardware I/O ports
+#
+# CONFIG_SERIO is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+# CONFIG_VT is not set
+# CONFIG_DEVKMEM is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+# CONFIG_SERIAL_8250 is not set
+
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_ATMEL=y
+CONFIG_SERIAL_ATMEL_CONSOLE=y
+CONFIG_SERIAL_ATMEL_PDC=y
+# CONFIG_SERIAL_ATMEL_TTYAT is not set
+# CONFIG_SERIAL_MAX3100 is not set
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_UNIX98_PTYS=y
+# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
+# CONFIG_LEGACY_PTYS is not set
+# CONFIG_IPMI_HANDLER is not set
+# CONFIG_HW_RANDOM is not set
+# CONFIG_R3964 is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+CONFIG_I2C=m
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_COMPAT=y
+CONFIG_I2C_CHARDEV=m
+CONFIG_I2C_HELPER_AUTO=y
+CONFIG_I2C_ALGOBIT=m
+
+#
+# I2C Hardware Bus support
+#
+
+#
+# I2C system bus drivers (mostly embedded / system-on-chip)
+#
+# CONFIG_I2C_DESIGNWARE is not set
+CONFIG_I2C_GPIO=m
+# CONFIG_I2C_OCORES is not set
+# CONFIG_I2C_SIMTEC is not set
+
+#
+# External I2C/SMBus adapter drivers
+#
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_TAOS_EVM is not set
+
+#
+# Other I2C/SMBus bus drivers
+#
+# CONFIG_I2C_PCA_PLATFORM is not set
+# CONFIG_I2C_STUB is not set
+
+#
+# Miscellaneous I2C Chip support
+#
+# CONFIG_DS1682 is not set
+# CONFIG_SENSORS_TSL2550 is not set
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+# CONFIG_I2C_DEBUG_CHIP is not set
+CONFIG_SPI=y
+# CONFIG_SPI_DEBUG is not set
+CONFIG_SPI_MASTER=y
+
+#
+# SPI Master Controller Drivers
+#
+CONFIG_SPI_ATMEL=y
+# CONFIG_SPI_BITBANG is not set
+# CONFIG_SPI_GPIO is not set
+
+#
+# SPI Protocol Masters
+#
+CONFIG_SPI_SPIDEV=m
+# CONFIG_SPI_TLE62X0 is not set
+
+#
+# PPS support
+#
+# CONFIG_PPS is not set
+CONFIG_ARCH_REQUIRE_GPIOLIB=y
+CONFIG_GPIOLIB=y
+# CONFIG_DEBUG_GPIO is not set
+CONFIG_GPIO_SYSFS=y
+
+#
+# Memory mapped GPIO expanders:
+#
+
+#
+# I2C GPIO expanders:
+#
+# CONFIG_GPIO_MAX732X is not set
+# CONFIG_GPIO_PCA953X is not set
+# CONFIG_GPIO_PCF857X is not set
+
+#
+# PCI GPIO expanders:
+#
+
+#
+# SPI GPIO expanders:
+#
+# CONFIG_GPIO_MAX7301 is not set
+# CONFIG_GPIO_MCP23S08 is not set
+# CONFIG_GPIO_MC33880 is not set
+
+#
+# AC97 GPIO expanders:
+#
+# CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
+# CONFIG_HWMON is not set
+# CONFIG_THERMAL is not set
+CONFIG_WATCHDOG=y
+# CONFIG_WATCHDOG_NOWAYOUT is not set
+
+#
+# Watchdog Device Drivers
+#
+# CONFIG_SOFT_WATCHDOG is not set
+CONFIG_AT32AP700X_WDT=y
+CONFIG_SSB_POSSIBLE=y
+
+#
+# Sonics Silicon Backplane
+#
+# CONFIG_SSB is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_CORE is not set
+# CONFIG_MFD_SM501 is not set
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_TPS65010 is not set
+# CONFIG_MFD_TMIO is not set
+# CONFIG_MFD_WM8400 is not set
+# CONFIG_MFD_WM831X is not set
+# CONFIG_MFD_WM8350_I2C is not set
+# CONFIG_MFD_PCF50633 is not set
+# CONFIG_MFD_MC13783 is not set
+# CONFIG_AB3100_CORE is not set
+# CONFIG_EZX_PCAP is not set
+# CONFIG_REGULATOR is not set
+# CONFIG_MEDIA_SUPPORT is not set
+
+#
+# Graphics support
+#
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+# CONFIG_FB is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+# CONFIG_SOUND is not set
+CONFIG_USB_SUPPORT=y
+# CONFIG_USB_ARCH_HAS_HCD is not set
+# CONFIG_USB_ARCH_HAS_OHCI is not set
+# CONFIG_USB_ARCH_HAS_EHCI is not set
+# CONFIG_USB_OTG_WHITELIST is not set
+# CONFIG_USB_OTG_BLACKLIST_HUB is not set
+# CONFIG_USB_GADGET_MUSB_HDRC is not set
+
+#
+# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
+#
+CONFIG_USB_GADGET=y
+# CONFIG_USB_GADGET_DEBUG is not set
+# CONFIG_USB_GADGET_DEBUG_FILES is not set
+# CONFIG_USB_GADGET_DEBUG_FS is not set
+CONFIG_USB_GADGET_VBUS_DRAW=2
+CONFIG_USB_GADGET_SELECTED=y
+# CONFIG_USB_GADGET_AT91 is not set
+CONFIG_USB_GADGET_ATMEL_USBA=y
+CONFIG_USB_ATMEL_USBA=y
+# CONFIG_USB_GADGET_FSL_USB2 is not set
+# CONFIG_USB_GADGET_LH7A40X is not set
+# CONFIG_USB_GADGET_OMAP is not set
+# CONFIG_USB_GADGET_PXA25X is not set
+# CONFIG_USB_GADGET_R8A66597 is not set
+# CONFIG_USB_GADGET_PXA27X is not set
+# CONFIG_USB_GADGET_S3C_HSOTG is not set
+# CONFIG_USB_GADGET_IMX is not set
+# CONFIG_USB_GADGET_S3C2410 is not set
+# CONFIG_USB_GADGET_M66592 is not set
+# CONFIG_USB_GADGET_AMD5536UDC is not set
+# CONFIG_USB_GADGET_FSL_QE is not set
+# CONFIG_USB_GADGET_CI13XXX is not set
+# CONFIG_USB_GADGET_NET2280 is not set
+# CONFIG_USB_GADGET_GOKU is not set
+# CONFIG_USB_GADGET_LANGWELL is not set
+# CONFIG_USB_GADGET_DUMMY_HCD is not set
+CONFIG_USB_GADGET_DUALSPEED=y
+CONFIG_USB_ZERO=m
+# CONFIG_USB_AUDIO is not set
+CONFIG_USB_ETH=m
+CONFIG_USB_ETH_RNDIS=y
+# CONFIG_USB_ETH_EEM is not set
+CONFIG_USB_GADGETFS=m
+CONFIG_USB_FILE_STORAGE=m
+# CONFIG_USB_FILE_STORAGE_TEST is not set
+CONFIG_USB_G_SERIAL=m
+# CONFIG_USB_MIDI_GADGET is not set
+# CONFIG_USB_G_PRINTER is not set
+CONFIG_USB_CDC_COMPOSITE=m
+
+#
+# OTG and related infrastructure
+#
+# CONFIG_USB_GPIO_VBUS is not set
+# CONFIG_NOP_USB_XCEIV is not set
+CONFIG_MMC=y
+# CONFIG_MMC_DEBUG is not set
+# CONFIG_MMC_UNSAFE_RESUME is not set
+
+#
+# MMC/SD/SDIO Card Drivers
+#
+CONFIG_MMC_BLOCK=y
+CONFIG_MMC_BLOCK_BOUNCE=y
+# CONFIG_SDIO_UART is not set
+CONFIG_MMC_TEST=m
+
+#
+# MMC/SD/SDIO Host Controller Drivers
+#
+# CONFIG_MMC_SDHCI is not set
+# CONFIG_MMC_AT91 is not set
+CONFIG_MMC_ATMELMCI=y
+# CONFIG_MMC_ATMELMCI_DMA is not set
+CONFIG_MMC_SPI=m
+# CONFIG_MEMSTICK is not set
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
+
+#
+# LED drivers
+#
+CONFIG_LEDS_GPIO=y
+CONFIG_LEDS_GPIO_PLATFORM=y
+# CONFIG_LEDS_LP3944 is not set
+# CONFIG_LEDS_PCA955X is not set
+# CONFIG_LEDS_DAC124S085 is not set
+# CONFIG_LEDS_BD2802 is not set
+
+#
+# LED Triggers
+#
+CONFIG_LEDS_TRIGGERS=y
+CONFIG_LEDS_TRIGGER_TIMER=y
+CONFIG_LEDS_TRIGGER_HEARTBEAT=y
+# CONFIG_LEDS_TRIGGER_BACKLIGHT is not set
+# CONFIG_LEDS_TRIGGER_GPIO is not set
+CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
+
+#
+# iptables trigger is under Netfilter config (LED target)
+#
+# CONFIG_ACCESSIBILITY is not set
+CONFIG_RTC_LIB=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_HCTOSYS=y
+CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
+# CONFIG_RTC_DEBUG is not set
+
+#
+# RTC interfaces
+#
+CONFIG_RTC_INTF_SYSFS=y
+CONFIG_RTC_INTF_PROC=y
+CONFIG_RTC_INTF_DEV=y
+# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
+# CONFIG_RTC_DRV_TEST is not set
+
+#
+# I2C RTC drivers
+#
+# CONFIG_RTC_DRV_DS1307 is not set
+# CONFIG_RTC_DRV_DS1374 is not set
+# CONFIG_RTC_DRV_DS1672 is not set
+# CONFIG_RTC_DRV_MAX6900 is not set
+# CONFIG_RTC_DRV_RS5C372 is not set
+# CONFIG_RTC_DRV_ISL1208 is not set
+# CONFIG_RTC_DRV_X1205 is not set
+# CONFIG_RTC_DRV_PCF8563 is not set
+# CONFIG_RTC_DRV_PCF8583 is not set
+# CONFIG_RTC_DRV_M41T80 is not set
+# CONFIG_RTC_DRV_S35390A is not set
+# CONFIG_RTC_DRV_FM3130 is not set
+# CONFIG_RTC_DRV_RX8581 is not set
+# CONFIG_RTC_DRV_RX8025 is not set
+
+#
+# SPI RTC drivers
+#
+# CONFIG_RTC_DRV_M41T94 is not set
+# CONFIG_RTC_DRV_DS1305 is not set
+# CONFIG_RTC_DRV_DS1390 is not set
+# CONFIG_RTC_DRV_MAX6902 is not set
+# CONFIG_RTC_DRV_R9701 is not set
+# CONFIG_RTC_DRV_RS5C348 is not set
+# CONFIG_RTC_DRV_DS3234 is not set
+# CONFIG_RTC_DRV_PCF2123 is not set
+
+#
+# Platform RTC drivers
+#
+# CONFIG_RTC_DRV_DS1286 is not set
+# CONFIG_RTC_DRV_DS1511 is not set
+# CONFIG_RTC_DRV_DS1553 is not set
+# CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_STK17TA8 is not set
+# CONFIG_RTC_DRV_M48T86 is not set
+# CONFIG_RTC_DRV_M48T35 is not set
+# CONFIG_RTC_DRV_M48T59 is not set
+# CONFIG_RTC_DRV_BQ4802 is not set
+# CONFIG_RTC_DRV_V3020 is not set
+
+#
+# on-CPU RTC drivers
+#
+CONFIG_RTC_DRV_AT32AP700X=y
+CONFIG_DMADEVICES=y
+
+#
+# DMA Devices
+#
+CONFIG_DW_DMAC=y
+CONFIG_DMA_ENGINE=y
+
+#
+# DMA Clients
+#
+# CONFIG_NET_DMA is not set
+# CONFIG_ASYNC_TX_DMA is not set
+# CONFIG_DMATEST is not set
+# CONFIG_AUXDISPLAY is not set
+# CONFIG_UIO is not set
+
+#
+# TI VLYNQ
+#
+# CONFIG_STAGING is not set
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+# CONFIG_EXT2_FS_XATTR is not set
+# CONFIG_EXT2_FS_XIP is not set
+CONFIG_EXT3_FS=y
+# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
+# CONFIG_EXT3_FS_XATTR is not set
+# CONFIG_EXT4_FS is not set
+CONFIG_JBD=y
+# CONFIG_JBD_DEBUG is not set
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+# CONFIG_FS_POSIX_ACL is not set
+# CONFIG_XFS_FS is not set
+# CONFIG_GFS2_FS is not set
+# CONFIG_OCFS2_FS is not set
+# CONFIG_BTRFS_FS is not set
+# CONFIG_NILFS2_FS is not set
+CONFIG_FILE_LOCKING=y
+CONFIG_FSNOTIFY=y
+# CONFIG_DNOTIFY is not set
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+CONFIG_FUSE_FS=m
+# CONFIG_CUSE is not set
+
+#
+# Caches
+#
+# CONFIG_FSCACHE is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=m
+CONFIG_MSDOS_FS=m
+CONFIG_VFAT_FS=m
+CONFIG_FAT_DEFAULT_CODEPAGE=850
+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+# CONFIG_PROC_KCORE is not set
+CONFIG_PROC_SYSCTL=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_HUGETLB_PAGE is not set
+CONFIG_CONFIGFS_FS=m
+CONFIG_MISC_FILESYSTEMS=y
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_DEBUG=0
+CONFIG_JFFS2_FS_WRITEBUFFER=y
+# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
+# CONFIG_JFFS2_SUMMARY is not set
+# CONFIG_JFFS2_FS_XATTR is not set
+# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
+CONFIG_JFFS2_ZLIB=y
+# CONFIG_JFFS2_LZO is not set
+CONFIG_JFFS2_RTIME=y
+# CONFIG_JFFS2_RUBIN is not set
+# CONFIG_UBIFS_FS is not set
+# CONFIG_CRAMFS is not set
+# CONFIG_SQUASHFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_OMFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_SYSV_FS is not set
+CONFIG_UFS_FS=y
+# CONFIG_UFS_FS_WRITE is not set
+# CONFIG_UFS_DEBUG is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+# CONFIG_NFS_V3_ACL is not set
+# CONFIG_NFS_V4 is not set
+CONFIG_ROOT_NFS=y
+CONFIG_NFSD=m
+CONFIG_NFSD_V3=y
+# CONFIG_NFSD_V3_ACL is not set
+# CONFIG_NFSD_V4 is not set
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+CONFIG_EXPORTFS=m
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=y
+# CONFIG_RPCSEC_GSS_KRB5 is not set
+# CONFIG_RPCSEC_GSS_SPKM3 is not set
+CONFIG_SMB_FS=m
+# CONFIG_SMB_NLS_DEFAULT is not set
+CONFIG_CIFS=m
+# CONFIG_CIFS_STATS is not set
+# CONFIG_CIFS_WEAK_PW_HASH is not set
+# CONFIG_CIFS_XATTR is not set
+# CONFIG_CIFS_DEBUG2 is not set
+# CONFIG_CIFS_EXPERIMENTAL is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+CONFIG_NLS=m
+CONFIG_NLS_DEFAULT="iso8859-1"
+CONFIG_NLS_CODEPAGE_437=m
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+CONFIG_NLS_CODEPAGE_850=m
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+# CONFIG_NLS_ASCII is not set
+CONFIG_NLS_ISO8859_1=m
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+CONFIG_NLS_UTF8=m
+# CONFIG_DLM is not set
+
+#
+# Kernel hacking
+#
+# CONFIG_PRINTK_TIME is not set
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_FRAME_WARN=1024
+CONFIG_MAGIC_SYSRQ=y
+# CONFIG_STRIP_ASM_SYMS is not set
+# CONFIG_UNUSED_SYMBOLS is not set
+CONFIG_DEBUG_FS=y
+# CONFIG_HEADERS_CHECK is not set
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_SHIRQ is not set
+CONFIG_DETECT_SOFTLOCKUP=y
+# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
+CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
+CONFIG_DETECT_HUNG_TASK=y
+# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set
+CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0
+CONFIG_SCHED_DEBUG=y
+# CONFIG_SCHEDSTATS is not set
+# CONFIG_TIMER_STATS is not set
+# CONFIG_DEBUG_OBJECTS is not set
+# CONFIG_SLUB_DEBUG_ON is not set
+# CONFIG_SLUB_STATS is not set
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_RT_MUTEX_TESTER is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_DEBUG_MUTEXES is not set
+# CONFIG_DEBUG_LOCK_ALLOC is not set
+# CONFIG_PROVE_LOCKING is not set
+# CONFIG_LOCK_STAT is not set
+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+CONFIG_STACKTRACE=y
+# CONFIG_DEBUG_KOBJECT is not set
+CONFIG_DEBUG_BUGVERBOSE=y
+# CONFIG_DEBUG_INFO is not set
+# CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_WRITECOUNT is not set
+# CONFIG_DEBUG_MEMORY_INIT is not set
+# CONFIG_DEBUG_LIST is not set
+# CONFIG_DEBUG_SG is not set
+# CONFIG_DEBUG_NOTIFIERS is not set
+# CONFIG_DEBUG_CREDENTIALS is not set
+CONFIG_FRAME_POINTER=y
+# CONFIG_BOOT_PRINTK_DELAY is not set
+# CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_RCU_CPU_STALL_DETECTOR is not set
+# CONFIG_KPROBES_SANITY_TEST is not set
+# CONFIG_BACKTRACE_SELF_TEST is not set
+# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
+# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
+# CONFIG_LKDTM is not set
+# CONFIG_FAULT_INJECTION is not set
+# CONFIG_PAGE_POISONING is not set
+CONFIG_NOP_TRACER=y
+CONFIG_RING_BUFFER=y
+CONFIG_EVENT_TRACING=y
+CONFIG_CONTEXT_SWITCH_TRACER=y
+CONFIG_RING_BUFFER_ALLOW_SWAP=y
+CONFIG_TRACING=y
+CONFIG_TRACING_SUPPORT=y
+CONFIG_FTRACE=y
+# CONFIG_IRQSOFF_TRACER is not set
+# CONFIG_SCHED_TRACER is not set
+# CONFIG_ENABLE_DEFAULT_TRACERS is not set
+# CONFIG_BOOT_TRACER is not set
+CONFIG_BRANCH_PROFILE_NONE=y
+# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set
+# CONFIG_PROFILE_ALL_BRANCHES is not set
+# CONFIG_KMEMTRACE is not set
+# CONFIG_WORKQUEUE_TRACER is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_RING_BUFFER_BENCHMARK is not set
+# CONFIG_DYNAMIC_DEBUG is not set
+# CONFIG_SAMPLES is not set
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITYFS is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+CONFIG_CRYPTO=y
+
+#
+# Crypto core or helper
+#
+# CONFIG_CRYPTO_FIPS is not set
+CONFIG_CRYPTO_ALGAPI=y
+CONFIG_CRYPTO_ALGAPI2=y
+CONFIG_CRYPTO_AEAD=y
+CONFIG_CRYPTO_AEAD2=y
+CONFIG_CRYPTO_BLKCIPHER=y
+CONFIG_CRYPTO_BLKCIPHER2=y
+CONFIG_CRYPTO_HASH=y
+CONFIG_CRYPTO_HASH2=y
+CONFIG_CRYPTO_RNG=m
+CONFIG_CRYPTO_RNG2=y
+CONFIG_CRYPTO_PCOMP=y
+CONFIG_CRYPTO_MANAGER=y
+CONFIG_CRYPTO_MANAGER2=y
+# CONFIG_CRYPTO_GF128MUL is not set
+# CONFIG_CRYPTO_NULL is not set
+CONFIG_CRYPTO_WORKQUEUE=y
+# CONFIG_CRYPTO_CRYPTD is not set
+CONFIG_CRYPTO_AUTHENC=y
+# CONFIG_CRYPTO_TEST is not set
+
+#
+# Authenticated Encryption with Associated Data
+#
+# CONFIG_CRYPTO_CCM is not set
+# CONFIG_CRYPTO_GCM is not set
+# CONFIG_CRYPTO_SEQIV is not set
+
+#
+# Block modes
+#
+CONFIG_CRYPTO_CBC=y
+# CONFIG_CRYPTO_CTR is not set
+# CONFIG_CRYPTO_CTS is not set
+CONFIG_CRYPTO_ECB=m
+# CONFIG_CRYPTO_LRW is not set
+CONFIG_CRYPTO_PCBC=m
+# CONFIG_CRYPTO_XTS is not set
+
+#
+# Hash modes
+#
+CONFIG_CRYPTO_HMAC=y
+# CONFIG_CRYPTO_XCBC is not set
+# CONFIG_CRYPTO_VMAC is not set
+
+#
+# Digest
+#
+# CONFIG_CRYPTO_CRC32C is not set
+# CONFIG_CRYPTO_GHASH is not set
+# CONFIG_CRYPTO_MD4 is not set
+CONFIG_CRYPTO_MD5=y
+# CONFIG_CRYPTO_MICHAEL_MIC is not set
+# CONFIG_CRYPTO_RMD128 is not set
+# CONFIG_CRYPTO_RMD160 is not set
+# CONFIG_CRYPTO_RMD256 is not set
+# CONFIG_CRYPTO_RMD320 is not set
+CONFIG_CRYPTO_SHA1=y
+# CONFIG_CRYPTO_SHA256 is not set
+# CONFIG_CRYPTO_SHA512 is not set
+# CONFIG_CRYPTO_TGR192 is not set
+# CONFIG_CRYPTO_WP512 is not set
+
+#
+# Ciphers
+#
+CONFIG_CRYPTO_AES=m
+# CONFIG_CRYPTO_ANUBIS is not set
+CONFIG_CRYPTO_ARC4=m
+# CONFIG_CRYPTO_BLOWFISH is not set
+# CONFIG_CRYPTO_CAMELLIA is not set
+# CONFIG_CRYPTO_CAST5 is not set
+# CONFIG_CRYPTO_CAST6 is not set
+CONFIG_CRYPTO_DES=y
+# CONFIG_CRYPTO_FCRYPT is not set
+# CONFIG_CRYPTO_KHAZAD is not set
+# CONFIG_CRYPTO_SALSA20 is not set
+# CONFIG_CRYPTO_SEED is not set
+# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_TEA is not set
+# CONFIG_CRYPTO_TWOFISH is not set
+
+#
+# Compression
+#
+CONFIG_CRYPTO_DEFLATE=y
+# CONFIG_CRYPTO_ZLIB is not set
+# CONFIG_CRYPTO_LZO is not set
+
+#
+# Random Number Generation
+#
+CONFIG_CRYPTO_ANSI_CPRNG=m
+CONFIG_CRYPTO_HW=y
+CONFIG_BINARY_PRINTF=y
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+CONFIG_GENERIC_FIND_LAST_BIT=y
+CONFIG_CRC_CCITT=m
+# CONFIG_CRC16 is not set
+# CONFIG_CRC_T10DIF is not set
+CONFIG_CRC_ITU_T=m
+CONFIG_CRC32=y
+CONFIG_CRC7=m
+# CONFIG_LIBCRC32C is not set
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_DECOMPRESS_GZIP=y
+CONFIG_GENERIC_ALLOCATOR=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
+CONFIG_NLATTR=y
diff --git a/arch/avr32/configs/atngw100mkii_evklcd100_defconfig b/arch/avr32/configs/atngw100mkii_evklcd100_defconfig
new file mode 100644
index 000000000000..01e913d66be4
--- /dev/null
+++ b/arch/avr32/configs/atngw100mkii_evklcd100_defconfig
@@ -0,0 +1,1549 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.32-rc5
+# Thu Nov  5 15:33:09 2009
+#
+CONFIG_AVR32=y
+CONFIG_GENERIC_GPIO=y
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_GENERIC_BUG=y
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+CONFIG_CONSTRUCTORS=y
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION=""
+# CONFIG_LOCALVERSION_AUTO is not set
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_POSIX_MQUEUE_SYSCTL=y
+CONFIG_BSD_PROCESS_ACCT=y
+CONFIG_BSD_PROCESS_ACCT_V3=y
+# CONFIG_TASKSTATS is not set
+# CONFIG_AUDIT is not set
+
+#
+# RCU Subsystem
+#
+CONFIG_TREE_RCU=y
+# CONFIG_TREE_PREEMPT_RCU is not set
+# CONFIG_RCU_TRACE is not set
+CONFIG_RCU_FANOUT=32
+# CONFIG_RCU_FANOUT_EXACT is not set
+# CONFIG_TREE_RCU_TRACE is not set
+# CONFIG_IKCONFIG is not set
+CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_GROUP_SCHED is not set
+# CONFIG_CGROUPS is not set
+CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SYSFS_DEPRECATED_V2=y
+# CONFIG_RELAY is not set
+# CONFIG_NAMESPACES is not set
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_RD_GZIP=y
+# CONFIG_RD_BZIP2 is not set
+# CONFIG_RD_LZMA is not set
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_SYSCTL=y
+CONFIG_ANON_INODES=y
+CONFIG_EMBEDDED=y
+# CONFIG_SYSCTL_SYSCALL is not set
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_ALL is not set
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+# CONFIG_BASE_FULL is not set
+CONFIG_FUTEX=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_AIO=y
+
+#
+# Kernel Performance Events And Counters
+#
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLUB_DEBUG=y
+# CONFIG_COMPAT_BRK is not set
+# CONFIG_SLAB is not set
+CONFIG_SLUB=y
+# CONFIG_SLOB is not set
+CONFIG_PROFILING=y
+CONFIG_TRACEPOINTS=y
+CONFIG_OPROFILE=m
+CONFIG_HAVE_OPROFILE=y
+CONFIG_KPROBES=y
+CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_CLK=y
+
+#
+# GCOV-based kernel profiling
+#
+# CONFIG_GCOV_KERNEL is not set
+CONFIG_SLOW_WORK=y
+# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
+CONFIG_BASE_SMALL=1
+CONFIG_MODULES=y
+# CONFIG_MODULE_FORCE_LOAD is not set
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODULE_FORCE_UNLOAD=y
+# CONFIG_MODVERSIONS is not set
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+CONFIG_BLOCK=y
+CONFIG_LBDAF=y
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_BLK_DEV_INTEGRITY is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+# CONFIG_IOSCHED_AS is not set
+# CONFIG_IOSCHED_DEADLINE is not set
+CONFIG_IOSCHED_CFQ=y
+# CONFIG_DEFAULT_AS is not set
+# CONFIG_DEFAULT_DEADLINE is not set
+CONFIG_DEFAULT_CFQ=y
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="cfq"
+CONFIG_FREEZER=y
+
+#
+# System Type and features
+#
+CONFIG_TICK_ONESHOT=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+CONFIG_SUBARCH_AVR32B=y
+CONFIG_MMU=y
+CONFIG_PERFORMANCE_COUNTERS=y
+CONFIG_PLATFORM_AT32AP=y
+CONFIG_CPU_AT32AP700X=y
+CONFIG_CPU_AT32AP7000=y
+CONFIG_BOARD_ATNGW100_COMMON=y
+# CONFIG_BOARD_ATSTK1000 is not set
+# CONFIG_BOARD_ATNGW100_MKI is not set
+CONFIG_BOARD_ATNGW100_MKII=y
+# CONFIG_BOARD_HAMMERHEAD is not set
+# CONFIG_BOARD_FAVR_32 is not set
+# CONFIG_BOARD_MERISC is not set
+# CONFIG_BOARD_MIMC200 is not set
+CONFIG_BOARD_ATNGW100_MKII_LCD=y
+# CONFIG_BOARD_ATNGW100_ADDON_NONE is not set
+CONFIG_BOARD_ATNGW100_EVKLCD10X=y
+# CONFIG_BOARD_ATNGW100_MRMT is not set
+CONFIG_BOARD_ATNGW100_EVKLCD10X_QVGA=y
+# CONFIG_BOARD_ATNGW100_EVKLCD10X_VGA is not set
+# CONFIG_BOARD_ATNGW100_EVKLCD10X_POW_QVGA is not set
+CONFIG_LOADER_U_BOOT=y
+
+#
+# Atmel AVR32 AP options
+#
+# CONFIG_AP700X_32_BIT_SMC is not set
+CONFIG_AP700X_16_BIT_SMC=y
+# CONFIG_AP700X_8_BIT_SMC is not set
+CONFIG_LOAD_ADDRESS=0x10000000
+CONFIG_ENTRY_ADDRESS=0x90000000
+CONFIG_PHYS_OFFSET=0x10000000
+CONFIG_PREEMPT_NONE=y
+# CONFIG_PREEMPT_VOLUNTARY is not set
+# CONFIG_PREEMPT is not set
+CONFIG_QUICKLIST=y
+# CONFIG_HAVE_ARCH_BOOTMEM is not set
+# CONFIG_ARCH_HAVE_MEMORY_PRESENT is not set
+# CONFIG_NEED_NODE_MEMMAP_SIZE is not set
+CONFIG_ARCH_FLATMEM_ENABLE=y
+# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
+# CONFIG_ARCH_SPARSEMEM_ENABLE is not set
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_SPLIT_PTLOCK_CPUS=4
+# CONFIG_PHYS_ADDR_T_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=0
+CONFIG_NR_QUICK=2
+CONFIG_VIRT_TO_BUS=y
+CONFIG_HAVE_MLOCK=y
+CONFIG_HAVE_MLOCKED_PAGE_BIT=y
+# CONFIG_KSM is not set
+CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
+# CONFIG_OWNERSHIP_TRACE is not set
+CONFIG_NMI_DEBUGGING=y
+# CONFIG_HZ_100 is not set
+CONFIG_HZ_250=y
+# CONFIG_HZ_300 is not set
+# CONFIG_HZ_1000 is not set
+CONFIG_HZ=250
+CONFIG_SCHED_HRTICK=y
+CONFIG_CMDLINE=""
+
+#
+# Power management options
+#
+CONFIG_PM=y
+# CONFIG_PM_DEBUG is not set
+CONFIG_PM_SLEEP=y
+CONFIG_SUSPEND=y
+CONFIG_SUSPEND_FREEZER=y
+# CONFIG_PM_RUNTIME is not set
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+
+#
+# CPU Frequency scaling
+#
+CONFIG_CPU_FREQ=y
+CONFIG_CPU_FREQ_TABLE=y
+# CONFIG_CPU_FREQ_DEBUG is not set
+# CONFIG_CPU_FREQ_STAT is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set
+CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
+# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set
+CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
+# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set
+CONFIG_CPU_FREQ_GOV_USERSPACE=y
+CONFIG_CPU_FREQ_GOV_ONDEMAND=y
+# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set
+CONFIG_CPU_FREQ_AT32AP=y
+
+#
+# Bus options
+#
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+# CONFIG_PCCARD is not set
+
+#
+# Executable file formats
+#
+CONFIG_BINFMT_ELF=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+# CONFIG_HAVE_AOUT is not set
+# CONFIG_BINFMT_MISC is not set
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+CONFIG_PACKET_MMAP=y
+CONFIG_UNIX=y
+CONFIG_XFRM=y
+CONFIG_XFRM_USER=y
+# CONFIG_XFRM_SUB_POLICY is not set
+# CONFIG_XFRM_MIGRATE is not set
+# CONFIG_XFRM_STATISTICS is not set
+CONFIG_XFRM_IPCOMP=y
+CONFIG_NET_KEY=y
+# CONFIG_NET_KEY_MIGRATE is not set
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_ADVANCED_ROUTER=y
+CONFIG_ASK_IP_FIB_HASH=y
+# CONFIG_IP_FIB_TRIE is not set
+CONFIG_IP_FIB_HASH=y
+# CONFIG_IP_MULTIPLE_TABLES is not set
+# CONFIG_IP_ROUTE_MULTIPATH is not set
+# CONFIG_IP_ROUTE_VERBOSE is not set
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+# CONFIG_IP_PNP_BOOTP is not set
+# CONFIG_IP_PNP_RARP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+CONFIG_IP_MROUTE=y
+CONFIG_IP_PIMSM_V1=y
+# CONFIG_IP_PIMSM_V2 is not set
+# CONFIG_ARPD is not set
+CONFIG_SYN_COOKIES=y
+CONFIG_INET_AH=y
+CONFIG_INET_ESP=y
+CONFIG_INET_IPCOMP=y
+CONFIG_INET_XFRM_TUNNEL=y
+CONFIG_INET_TUNNEL=y
+CONFIG_INET_XFRM_MODE_TRANSPORT=y
+CONFIG_INET_XFRM_MODE_TUNNEL=y
+CONFIG_INET_XFRM_MODE_BEET=y
+# CONFIG_INET_LRO is not set
+CONFIG_INET_DIAG=y
+CONFIG_INET_TCP_DIAG=y
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+CONFIG_IPV6=y
+# CONFIG_IPV6_PRIVACY is not set
+# CONFIG_IPV6_ROUTER_PREF is not set
+# CONFIG_IPV6_OPTIMISTIC_DAD is not set
+CONFIG_INET6_AH=y
+CONFIG_INET6_ESP=y
+CONFIG_INET6_IPCOMP=y
+# CONFIG_IPV6_MIP6 is not set
+CONFIG_INET6_XFRM_TUNNEL=y
+CONFIG_INET6_TUNNEL=y
+CONFIG_INET6_XFRM_MODE_TRANSPORT=y
+CONFIG_INET6_XFRM_MODE_TUNNEL=y
+CONFIG_INET6_XFRM_MODE_BEET=y
+# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set
+CONFIG_IPV6_SIT=y
+CONFIG_IPV6_NDISC_NODETYPE=y
+# CONFIG_IPV6_TUNNEL is not set
+# CONFIG_IPV6_MULTIPLE_TABLES is not set
+# CONFIG_IPV6_MROUTE is not set
+# CONFIG_NETWORK_SECMARK is not set
+CONFIG_NETFILTER=y
+# CONFIG_NETFILTER_DEBUG is not set
+# CONFIG_NETFILTER_ADVANCED is not set
+
+#
+# Core Netfilter Configuration
+#
+CONFIG_NETFILTER_NETLINK=m
+CONFIG_NETFILTER_NETLINK_LOG=m
+CONFIG_NF_CONNTRACK=m
+CONFIG_NF_CONNTRACK_FTP=m
+CONFIG_NF_CONNTRACK_IRC=m
+CONFIG_NF_CONNTRACK_SIP=m
+CONFIG_NF_CT_NETLINK=m
+CONFIG_NETFILTER_XTABLES=y
+CONFIG_NETFILTER_XT_TARGET_MARK=m
+CONFIG_NETFILTER_XT_TARGET_NFLOG=m
+CONFIG_NETFILTER_XT_TARGET_TCPMSS=m
+CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
+CONFIG_NETFILTER_XT_MATCH_MARK=m
+CONFIG_NETFILTER_XT_MATCH_POLICY=m
+CONFIG_NETFILTER_XT_MATCH_STATE=m
+# CONFIG_IP_VS is not set
+
+#
+# IP: Netfilter Configuration
+#
+CONFIG_NF_DEFRAG_IPV4=m
+CONFIG_NF_CONNTRACK_IPV4=m
+CONFIG_NF_CONNTRACK_PROC_COMPAT=y
+CONFIG_IP_NF_IPTABLES=m
+CONFIG_IP_NF_FILTER=m
+CONFIG_IP_NF_TARGET_REJECT=m
+CONFIG_IP_NF_TARGET_LOG=m
+# CONFIG_IP_NF_TARGET_ULOG is not set
+CONFIG_NF_NAT=m
+CONFIG_NF_NAT_NEEDED=y
+CONFIG_IP_NF_TARGET_MASQUERADE=m
+CONFIG_NF_NAT_FTP=m
+CONFIG_NF_NAT_IRC=m
+# CONFIG_NF_NAT_TFTP is not set
+# CONFIG_NF_NAT_AMANDA is not set
+# CONFIG_NF_NAT_PPTP is not set
+# CONFIG_NF_NAT_H323 is not set
+CONFIG_NF_NAT_SIP=m
+CONFIG_IP_NF_MANGLE=m
+
+#
+# IPv6: Netfilter Configuration
+#
+CONFIG_NF_CONNTRACK_IPV6=m
+CONFIG_IP6_NF_IPTABLES=m
+CONFIG_IP6_NF_MATCH_IPV6HEADER=m
+CONFIG_IP6_NF_TARGET_LOG=m
+CONFIG_IP6_NF_FILTER=m
+CONFIG_IP6_NF_TARGET_REJECT=m
+CONFIG_IP6_NF_MANGLE=m
+# CONFIG_IP_DCCP is not set
+# CONFIG_IP_SCTP is not set
+# CONFIG_RDS is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+CONFIG_STP=m
+CONFIG_BRIDGE=m
+# CONFIG_NET_DSA is not set
+CONFIG_VLAN_8021Q=m
+# CONFIG_VLAN_8021Q_GVRP is not set
+# CONFIG_DECNET is not set
+CONFIG_LLC=m
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_PHONET is not set
+# CONFIG_IEEE802154 is not set
+# CONFIG_NET_SCHED is not set
+# CONFIG_DCB is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_NET_TCPPROBE is not set
+# CONFIG_NET_DROP_MONITOR is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+# CONFIG_AF_RXRPC is not set
+CONFIG_WIRELESS=y
+# CONFIG_CFG80211 is not set
+CONFIG_CFG80211_DEFAULT_PS_VALUE=0
+# CONFIG_WIRELESS_OLD_REGULATORY is not set
+# CONFIG_WIRELESS_EXT is not set
+# CONFIG_LIB80211 is not set
+
+#
+# CFG80211 needs to be enabled for MAC80211
+#
+# CONFIG_WIMAX is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+# CONFIG_DEVTMPFS is not set
+CONFIG_STANDALONE=y
+# CONFIG_PREVENT_FIRMWARE_BUILD is not set
+# CONFIG_FW_LOADER is not set
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
+# CONFIG_SYS_HYPERVISOR is not set
+# CONFIG_CONNECTOR is not set
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+# CONFIG_MTD_TESTS is not set
+# CONFIG_MTD_CONCAT is not set
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_REDBOOT_PARTS is not set
+CONFIG_MTD_CMDLINE_PARTS=y
+# CONFIG_MTD_AR7_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+CONFIG_MTD_CFI=y
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_GEN_PROBE=y
+# CONFIG_MTD_CFI_ADV_OPTIONS is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+CONFIG_MTD_CFI_INTELEXT=y
+# CONFIG_MTD_CFI_AMDSTD is not set
+# CONFIG_MTD_CFI_STAA is not set
+CONFIG_MTD_CFI_UTIL=y
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+CONFIG_MTD_PHYSMAP=y
+# CONFIG_MTD_PHYSMAP_COMPAT is not set
+# CONFIG_MTD_PLATRAM is not set
+
+#
+# Self-contained MTD device drivers
+#
+CONFIG_MTD_DATAFLASH=y
+# CONFIG_MTD_DATAFLASH_WRITE_VERIFY is not set
+# CONFIG_MTD_DATAFLASH_OTP is not set
+# CONFIG_MTD_M25P80 is not set
+# CONFIG_MTD_SST25L is not set
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+CONFIG_MTD_NAND=y
+# CONFIG_MTD_NAND_VERIFY_WRITE is not set
+# CONFIG_MTD_NAND_ECC_SMC is not set
+# CONFIG_MTD_NAND_MUSEUM_IDS is not set
+CONFIG_MTD_NAND_IDS=y
+# CONFIG_MTD_NAND_DISKONCHIP is not set
+CONFIG_MTD_NAND_ATMEL=y
+CONFIG_MTD_NAND_ATMEL_ECC_HW=y
+# CONFIG_MTD_NAND_ATMEL_ECC_SOFT is not set
+# CONFIG_MTD_NAND_ATMEL_ECC_NONE is not set
+# CONFIG_MTD_NAND_NANDSIM is not set
+# CONFIG_MTD_NAND_PLATFORM is not set
+# CONFIG_MTD_ONENAND is not set
+
+#
+# LPDDR flash memory drivers
+#
+# CONFIG_MTD_LPDDR is not set
+
+#
+# UBI - Unsorted block images
+#
+CONFIG_MTD_UBI=y
+CONFIG_MTD_UBI_WL_THRESHOLD=4096
+CONFIG_MTD_UBI_BEB_RESERVE=1
+# CONFIG_MTD_UBI_GLUEBI is not set
+
+#
+# UBI debugging options
+#
+# CONFIG_MTD_UBI_DEBUG is not set
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=m
+# CONFIG_BLK_DEV_CRYPTOLOOP is not set
+CONFIG_BLK_DEV_NBD=m
+CONFIG_BLK_DEV_RAM=m
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=4096
+# CONFIG_BLK_DEV_XIP is not set
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+CONFIG_MISC_DEVICES=y
+# CONFIG_ATMEL_PWM is not set
+CONFIG_ATMEL_TCLIB=y
+CONFIG_ATMEL_TCB_CLKSRC=y
+CONFIG_ATMEL_TCB_CLKSRC_BLOCK=0
+# CONFIG_ICS932S401 is not set
+# CONFIG_ATMEL_SSC is not set
+# CONFIG_ENCLOSURE_SERVICES is not set
+# CONFIG_ISL29003 is not set
+# CONFIG_C2PORT is not set
+
+#
+# EEPROM support
+#
+# CONFIG_EEPROM_AT24 is not set
+# CONFIG_EEPROM_AT25 is not set
+# CONFIG_EEPROM_LEGACY is not set
+# CONFIG_EEPROM_MAX6875 is not set
+# CONFIG_EEPROM_93CX6 is not set
+
+#
+# SCSI device support
+#
+# CONFIG_RAID_ATTRS is not set
+# CONFIG_SCSI is not set
+# CONFIG_SCSI_DMA is not set
+# CONFIG_SCSI_NETLINK is not set
+# CONFIG_ATA is not set
+# CONFIG_MD is not set
+CONFIG_NETDEVICES=y
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_VETH is not set
+CONFIG_PHYLIB=y
+
+#
+# MII PHY device drivers
+#
+# CONFIG_MARVELL_PHY is not set
+# CONFIG_DAVICOM_PHY is not set
+# CONFIG_QSEMI_PHY is not set
+# CONFIG_LXT_PHY is not set
+# CONFIG_CICADA_PHY is not set
+# CONFIG_VITESSE_PHY is not set
+# CONFIG_SMSC_PHY is not set
+# CONFIG_BROADCOM_PHY is not set
+# CONFIG_ICPLUS_PHY is not set
+# CONFIG_REALTEK_PHY is not set
+# CONFIG_NATIONAL_PHY is not set
+# CONFIG_STE10XP is not set
+# CONFIG_LSI_ET1011C_PHY is not set
+# CONFIG_FIXED_PHY is not set
+# CONFIG_MDIO_BITBANG is not set
+CONFIG_NET_ETHERNET=y
+# CONFIG_MII is not set
+CONFIG_MACB=y
+# CONFIG_ENC28J60 is not set
+# CONFIG_ETHOC is not set
+# CONFIG_DNET is not set
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
+# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
+# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
+# CONFIG_B44 is not set
+# CONFIG_KS8842 is not set
+# CONFIG_KS8851 is not set
+# CONFIG_KS8851_MLL is not set
+# CONFIG_NETDEV_1000 is not set
+# CONFIG_NETDEV_10000 is not set
+CONFIG_WLAN=y
+# CONFIG_WLAN_PRE80211 is not set
+# CONFIG_WLAN_80211 is not set
+
+#
+# Enable WiMAX (Networking options) to see the WiMAX drivers
+#
+# CONFIG_WAN is not set
+CONFIG_PPP=m
+# CONFIG_PPP_MULTILINK is not set
+CONFIG_PPP_FILTER=y
+CONFIG_PPP_ASYNC=m
+# CONFIG_PPP_SYNC_TTY is not set
+CONFIG_PPP_DEFLATE=m
+CONFIG_PPP_BSDCOMP=m
+CONFIG_PPP_MPPE=m
+CONFIG_PPPOE=m
+# CONFIG_PPPOL2TP is not set
+# CONFIG_SLIP is not set
+CONFIG_SLHC=m
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_ISDN is not set
+# CONFIG_PHONE is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
+
+#
+# Userland interfaces
+#
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_JOYDEV is not set
+CONFIG_INPUT_EVDEV=m
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input Device Drivers
+#
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+CONFIG_INPUT_TOUCHSCREEN=y
+# CONFIG_TOUCHSCREEN_ADS7846 is not set
+# CONFIG_TOUCHSCREEN_AD7877 is not set
+# CONFIG_TOUCHSCREEN_AD7879_I2C is not set
+# CONFIG_TOUCHSCREEN_AD7879_SPI is not set
+# CONFIG_TOUCHSCREEN_AD7879 is not set
+# CONFIG_TOUCHSCREEN_EETI is not set
+# CONFIG_TOUCHSCREEN_FUJITSU is not set
+# CONFIG_TOUCHSCREEN_GUNZE is not set
+# CONFIG_TOUCHSCREEN_ELO is not set
+# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set
+# CONFIG_TOUCHSCREEN_MCS5000 is not set
+# CONFIG_TOUCHSCREEN_MTOUCH is not set
+# CONFIG_TOUCHSCREEN_INEXIO is not set
+# CONFIG_TOUCHSCREEN_MK712 is not set
+# CONFIG_TOUCHSCREEN_PENMOUNT is not set
+# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
+# CONFIG_TOUCHSCREEN_TOUCHWIN is not set
+CONFIG_TOUCHSCREEN_WM97XX=m
+CONFIG_TOUCHSCREEN_WM9705=y
+CONFIG_TOUCHSCREEN_WM9712=y
+CONFIG_TOUCHSCREEN_WM9713=y
+# CONFIG_TOUCHSCREEN_WM97XX_ATMEL is not set
+# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set
+# CONFIG_TOUCHSCREEN_TSC2007 is not set
+# CONFIG_TOUCHSCREEN_W90X900 is not set
+# CONFIG_INPUT_MISC is not set
+
+#
+# Hardware I/O ports
+#
+# CONFIG_SERIO is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+# CONFIG_VT_HW_CONSOLE_BINDING is not set
+CONFIG_DEVKMEM=y
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+# CONFIG_SERIAL_8250 is not set
+
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_ATMEL=y
+CONFIG_SERIAL_ATMEL_CONSOLE=y
+CONFIG_SERIAL_ATMEL_PDC=y
+# CONFIG_SERIAL_ATMEL_TTYAT is not set
+# CONFIG_SERIAL_MAX3100 is not set
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_UNIX98_PTYS=y
+# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
+# CONFIG_LEGACY_PTYS is not set
+# CONFIG_IPMI_HANDLER is not set
+# CONFIG_HW_RANDOM is not set
+# CONFIG_R3964 is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+CONFIG_I2C=m
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_COMPAT=y
+CONFIG_I2C_CHARDEV=m
+CONFIG_I2C_HELPER_AUTO=y
+CONFIG_I2C_ALGOBIT=m
+
+#
+# I2C Hardware Bus support
+#
+
+#
+# I2C system bus drivers (mostly embedded / system-on-chip)
+#
+# CONFIG_I2C_DESIGNWARE is not set
+CONFIG_I2C_GPIO=m
+# CONFIG_I2C_OCORES is not set
+# CONFIG_I2C_SIMTEC is not set
+
+#
+# External I2C/SMBus adapter drivers
+#
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_TAOS_EVM is not set
+
+#
+# Other I2C/SMBus bus drivers
+#
+# CONFIG_I2C_PCA_PLATFORM is not set
+# CONFIG_I2C_STUB is not set
+
+#
+# Miscellaneous I2C Chip support
+#
+# CONFIG_DS1682 is not set
+# CONFIG_SENSORS_TSL2550 is not set
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+# CONFIG_I2C_DEBUG_CHIP is not set
+CONFIG_SPI=y
+# CONFIG_SPI_DEBUG is not set
+CONFIG_SPI_MASTER=y
+
+#
+# SPI Master Controller Drivers
+#
+CONFIG_SPI_ATMEL=y
+# CONFIG_SPI_BITBANG is not set
+# CONFIG_SPI_GPIO is not set
+
+#
+# SPI Protocol Masters
+#
+CONFIG_SPI_SPIDEV=m
+# CONFIG_SPI_TLE62X0 is not set
+
+#
+# PPS support
+#
+# CONFIG_PPS is not set
+CONFIG_ARCH_REQUIRE_GPIOLIB=y
+CONFIG_GPIOLIB=y
+# CONFIG_DEBUG_GPIO is not set
+# CONFIG_GPIO_SYSFS is not set
+
+#
+# Memory mapped GPIO expanders:
+#
+
+#
+# I2C GPIO expanders:
+#
+# CONFIG_GPIO_MAX732X is not set
+# CONFIG_GPIO_PCA953X is not set
+# CONFIG_GPIO_PCF857X is not set
+
+#
+# PCI GPIO expanders:
+#
+
+#
+# SPI GPIO expanders:
+#
+# CONFIG_GPIO_MAX7301 is not set
+# CONFIG_GPIO_MCP23S08 is not set
+# CONFIG_GPIO_MC33880 is not set
+
+#
+# AC97 GPIO expanders:
+#
+# CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
+# CONFIG_HWMON is not set
+# CONFIG_THERMAL is not set
+CONFIG_WATCHDOG=y
+# CONFIG_WATCHDOG_NOWAYOUT is not set
+
+#
+# Watchdog Device Drivers
+#
+# CONFIG_SOFT_WATCHDOG is not set
+CONFIG_AT32AP700X_WDT=y
+CONFIG_SSB_POSSIBLE=y
+
+#
+# Sonics Silicon Backplane
+#
+# CONFIG_SSB is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_CORE is not set
+# CONFIG_MFD_SM501 is not set
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_UCB1400_CORE is not set
+# CONFIG_TPS65010 is not set
+# CONFIG_MFD_TMIO is not set
+# CONFIG_MFD_WM8400 is not set
+# CONFIG_MFD_WM831X is not set
+# CONFIG_MFD_WM8350_I2C is not set
+# CONFIG_MFD_PCF50633 is not set
+# CONFIG_MFD_MC13783 is not set
+# CONFIG_AB3100_CORE is not set
+# CONFIG_EZX_PCAP is not set
+# CONFIG_REGULATOR is not set
+# CONFIG_MEDIA_SUPPORT is not set
+
+#
+# Graphics support
+#
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+CONFIG_FB=y
+# CONFIG_FIRMWARE_EDID is not set
+# CONFIG_FB_DDC is not set
+# CONFIG_FB_BOOT_VESA_SUPPORT is not set
+CONFIG_FB_CFB_FILLRECT=y
+CONFIG_FB_CFB_COPYAREA=y
+CONFIG_FB_CFB_IMAGEBLIT=y
+# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
+# CONFIG_FB_SYS_FILLRECT is not set
+# CONFIG_FB_SYS_COPYAREA is not set
+# CONFIG_FB_SYS_IMAGEBLIT is not set
+# CONFIG_FB_FOREIGN_ENDIAN is not set
+# CONFIG_FB_SYS_FOPS is not set
+# CONFIG_FB_SVGALIB is not set
+# CONFIG_FB_MACMODES is not set
+# CONFIG_FB_BACKLIGHT is not set
+# CONFIG_FB_MODE_HELPERS is not set
+# CONFIG_FB_TILEBLITTING is not set
+
+#
+# Frame buffer hardware drivers
+#
+# CONFIG_FB_S1D13XXX is not set
+CONFIG_FB_ATMEL=y
+# CONFIG_FB_VIRTUAL is not set
+# CONFIG_FB_METRONOME is not set
+# CONFIG_FB_MB862XX is not set
+# CONFIG_FB_BROADSHEET is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+
+#
+# Console display driver support
+#
+CONFIG_DUMMY_CONSOLE=y
+# CONFIG_FRAMEBUFFER_CONSOLE is not set
+# CONFIG_LOGO is not set
+CONFIG_SOUND=y
+CONFIG_SOUND_OSS_CORE=y
+CONFIG_SOUND_OSS_CORE_PRECLAIM=y
+CONFIG_SND=y
+CONFIG_SND_TIMER=y
+CONFIG_SND_PCM=m
+# CONFIG_SND_SEQUENCER is not set
+CONFIG_SND_OSSEMUL=y
+CONFIG_SND_MIXER_OSS=m
+CONFIG_SND_PCM_OSS=m
+CONFIG_SND_PCM_OSS_PLUGINS=y
+CONFIG_SND_HRTIMER=y
+# CONFIG_SND_DYNAMIC_MINORS is not set
+# CONFIG_SND_SUPPORT_OLD_API is not set
+CONFIG_SND_VERBOSE_PROCFS=y
+# CONFIG_SND_VERBOSE_PRINTK is not set
+# CONFIG_SND_DEBUG is not set
+CONFIG_SND_VMASTER=y
+# CONFIG_SND_RAWMIDI_SEQ is not set
+# CONFIG_SND_OPL3_LIB_SEQ is not set
+# CONFIG_SND_OPL4_LIB_SEQ is not set
+# CONFIG_SND_SBAWE_SEQ is not set
+# CONFIG_SND_EMU10K1_SEQ is not set
+CONFIG_SND_AC97_CODEC=m
+# CONFIG_SND_DRIVERS is not set
+
+#
+# Atmel devices (AVR32 and AT91)
+#
+# CONFIG_SND_ATMEL_ABDAC is not set
+CONFIG_SND_ATMEL_AC97C=m
+# CONFIG_SND_SPI is not set
+# CONFIG_SND_SOC is not set
+# CONFIG_SOUND_PRIME is not set
+CONFIG_AC97_BUS=m
+CONFIG_HID_SUPPORT=y
+CONFIG_HID=y
+# CONFIG_HIDRAW is not set
+# CONFIG_HID_PID is not set
+
+#
+# Special HID drivers
+#
+CONFIG_USB_SUPPORT=y
+# CONFIG_USB_ARCH_HAS_HCD is not set
+# CONFIG_USB_ARCH_HAS_OHCI is not set
+# CONFIG_USB_ARCH_HAS_EHCI is not set
+# CONFIG_USB_OTG_WHITELIST is not set
+# CONFIG_USB_OTG_BLACKLIST_HUB is not set
+# CONFIG_USB_GADGET_MUSB_HDRC is not set
+
+#
+# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
+#
+CONFIG_USB_GADGET=y
+# CONFIG_USB_GADGET_DEBUG is not set
+# CONFIG_USB_GADGET_DEBUG_FILES is not set
+# CONFIG_USB_GADGET_DEBUG_FS is not set
+CONFIG_USB_GADGET_VBUS_DRAW=350
+CONFIG_USB_GADGET_SELECTED=y
+# CONFIG_USB_GADGET_AT91 is not set
+CONFIG_USB_GADGET_ATMEL_USBA=y
+CONFIG_USB_ATMEL_USBA=y
+# CONFIG_USB_GADGET_FSL_USB2 is not set
+# CONFIG_USB_GADGET_LH7A40X is not set
+# CONFIG_USB_GADGET_OMAP is not set
+# CONFIG_USB_GADGET_PXA25X is not set
+# CONFIG_USB_GADGET_R8A66597 is not set
+# CONFIG_USB_GADGET_PXA27X is not set
+# CONFIG_USB_GADGET_S3C_HSOTG is not set
+# CONFIG_USB_GADGET_IMX is not set
+# CONFIG_USB_GADGET_S3C2410 is not set
+# CONFIG_USB_GADGET_M66592 is not set
+# CONFIG_USB_GADGET_AMD5536UDC is not set
+# CONFIG_USB_GADGET_FSL_QE is not set
+# CONFIG_USB_GADGET_CI13XXX is not set
+# CONFIG_USB_GADGET_NET2280 is not set
+# CONFIG_USB_GADGET_GOKU is not set
+# CONFIG_USB_GADGET_LANGWELL is not set
+# CONFIG_USB_GADGET_DUMMY_HCD is not set
+CONFIG_USB_GADGET_DUALSPEED=y
+CONFIG_USB_ZERO=m
+# CONFIG_USB_AUDIO is not set
+CONFIG_USB_ETH=m
+CONFIG_USB_ETH_RNDIS=y
+# CONFIG_USB_ETH_EEM is not set
+CONFIG_USB_GADGETFS=m
+CONFIG_USB_FILE_STORAGE=m
+# CONFIG_USB_FILE_STORAGE_TEST is not set
+CONFIG_USB_G_SERIAL=m
+# CONFIG_USB_MIDI_GADGET is not set
+# CONFIG_USB_G_PRINTER is not set
+CONFIG_USB_CDC_COMPOSITE=m
+
+#
+# OTG and related infrastructure
+#
+# CONFIG_USB_GPIO_VBUS is not set
+# CONFIG_NOP_USB_XCEIV is not set
+CONFIG_MMC=y
+# CONFIG_MMC_DEBUG is not set
+# CONFIG_MMC_UNSAFE_RESUME is not set
+
+#
+# MMC/SD/SDIO Card Drivers
+#
+CONFIG_MMC_BLOCK=y
+CONFIG_MMC_BLOCK_BOUNCE=y
+# CONFIG_SDIO_UART is not set
+# CONFIG_MMC_TEST is not set
+
+#
+# MMC/SD/SDIO Host Controller Drivers
+#
+# CONFIG_MMC_SDHCI is not set
+# CONFIG_MMC_AT91 is not set
+CONFIG_MMC_ATMELMCI=y
+# CONFIG_MMC_ATMELMCI_DMA is not set
+# CONFIG_MMC_SPI is not set
+# CONFIG_MEMSTICK is not set
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
+
+#
+# LED drivers
+#
+# CONFIG_LEDS_PCA9532 is not set
+CONFIG_LEDS_GPIO=y
+CONFIG_LEDS_GPIO_PLATFORM=y
+# CONFIG_LEDS_LP3944 is not set
+# CONFIG_LEDS_PCA955X is not set
+# CONFIG_LEDS_DAC124S085 is not set
+# CONFIG_LEDS_BD2802 is not set
+
+#
+# LED Triggers
+#
+CONFIG_LEDS_TRIGGERS=y
+CONFIG_LEDS_TRIGGER_TIMER=y
+CONFIG_LEDS_TRIGGER_HEARTBEAT=y
+# CONFIG_LEDS_TRIGGER_BACKLIGHT is not set
+# CONFIG_LEDS_TRIGGER_GPIO is not set
+# CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set
+
+#
+# iptables trigger is under Netfilter config (LED target)
+#
+# CONFIG_ACCESSIBILITY is not set
+CONFIG_RTC_LIB=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_HCTOSYS=y
+CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
+# CONFIG_RTC_DEBUG is not set
+
+#
+# RTC interfaces
+#
+CONFIG_RTC_INTF_SYSFS=y
+CONFIG_RTC_INTF_PROC=y
+CONFIG_RTC_INTF_DEV=y
+# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
+# CONFIG_RTC_DRV_TEST is not set
+
+#
+# I2C RTC drivers
+#
+# CONFIG_RTC_DRV_DS1307 is not set
+# CONFIG_RTC_DRV_DS1374 is not set
+# CONFIG_RTC_DRV_DS1672 is not set
+# CONFIG_RTC_DRV_MAX6900 is not set
+# CONFIG_RTC_DRV_RS5C372 is not set
+# CONFIG_RTC_DRV_ISL1208 is not set
+# CONFIG_RTC_DRV_X1205 is not set
+# CONFIG_RTC_DRV_PCF8563 is not set
+# CONFIG_RTC_DRV_PCF8583 is not set
+# CONFIG_RTC_DRV_M41T80 is not set
+# CONFIG_RTC_DRV_S35390A is not set
+# CONFIG_RTC_DRV_FM3130 is not set
+# CONFIG_RTC_DRV_RX8581 is not set
+# CONFIG_RTC_DRV_RX8025 is not set
+
+#
+# SPI RTC drivers
+#
+# CONFIG_RTC_DRV_M41T94 is not set
+# CONFIG_RTC_DRV_DS1305 is not set
+# CONFIG_RTC_DRV_DS1390 is not set
+# CONFIG_RTC_DRV_MAX6902 is not set
+# CONFIG_RTC_DRV_R9701 is not set
+# CONFIG_RTC_DRV_RS5C348 is not set
+# CONFIG_RTC_DRV_DS3234 is not set
+# CONFIG_RTC_DRV_PCF2123 is not set
+
+#
+# Platform RTC drivers
+#
+# CONFIG_RTC_DRV_DS1286 is not set
+# CONFIG_RTC_DRV_DS1511 is not set
+# CONFIG_RTC_DRV_DS1553 is not set
+# CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_STK17TA8 is not set
+# CONFIG_RTC_DRV_M48T86 is not set
+# CONFIG_RTC_DRV_M48T35 is not set
+# CONFIG_RTC_DRV_M48T59 is not set
+# CONFIG_RTC_DRV_BQ4802 is not set
+# CONFIG_RTC_DRV_V3020 is not set
+
+#
+# on-CPU RTC drivers
+#
+CONFIG_RTC_DRV_AT32AP700X=y
+CONFIG_DMADEVICES=y
+
+#
+# DMA Devices
+#
+CONFIG_DW_DMAC=y
+CONFIG_DMA_ENGINE=y
+
+#
+# DMA Clients
+#
+# CONFIG_NET_DMA is not set
+# CONFIG_ASYNC_TX_DMA is not set
+# CONFIG_DMATEST is not set
+# CONFIG_AUXDISPLAY is not set
+# CONFIG_UIO is not set
+
+#
+# TI VLYNQ
+#
+# CONFIG_STAGING is not set
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+# CONFIG_EXT2_FS_XATTR is not set
+# CONFIG_EXT2_FS_XIP is not set
+CONFIG_EXT3_FS=y
+# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
+# CONFIG_EXT3_FS_XATTR is not set
+# CONFIG_EXT4_FS is not set
+CONFIG_JBD=y
+# CONFIG_JBD_DEBUG is not set
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+# CONFIG_FS_POSIX_ACL is not set
+# CONFIG_XFS_FS is not set
+# CONFIG_GFS2_FS is not set
+# CONFIG_OCFS2_FS is not set
+# CONFIG_BTRFS_FS is not set
+# CONFIG_NILFS2_FS is not set
+CONFIG_FILE_LOCKING=y
+CONFIG_FSNOTIFY=y
+# CONFIG_DNOTIFY is not set
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+CONFIG_FUSE_FS=m
+# CONFIG_CUSE is not set
+
+#
+# Caches
+#
+# CONFIG_FSCACHE is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=m
+CONFIG_MSDOS_FS=m
+CONFIG_VFAT_FS=m
+CONFIG_FAT_DEFAULT_CODEPAGE=850
+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+# CONFIG_PROC_KCORE is not set
+CONFIG_PROC_SYSCTL=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_HUGETLB_PAGE is not set
+CONFIG_CONFIGFS_FS=y
+CONFIG_MISC_FILESYSTEMS=y
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_DEBUG=0
+CONFIG_JFFS2_FS_WRITEBUFFER=y
+# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
+# CONFIG_JFFS2_SUMMARY is not set
+# CONFIG_JFFS2_FS_XATTR is not set
+# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
+CONFIG_JFFS2_ZLIB=y
+# CONFIG_JFFS2_LZO is not set
+CONFIG_JFFS2_RTIME=y
+# CONFIG_JFFS2_RUBIN is not set
+CONFIG_UBIFS_FS=y
+# CONFIG_UBIFS_FS_XATTR is not set
+# CONFIG_UBIFS_FS_ADVANCED_COMPR is not set
+CONFIG_UBIFS_FS_LZO=y
+CONFIG_UBIFS_FS_ZLIB=y
+# CONFIG_UBIFS_FS_DEBUG is not set
+# CONFIG_CRAMFS is not set
+# CONFIG_SQUASHFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_OMFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+# CONFIG_NFS_V3_ACL is not set
+# CONFIG_NFS_V4 is not set
+CONFIG_ROOT_NFS=y
+CONFIG_NFSD=m
+CONFIG_NFSD_V3=y
+# CONFIG_NFSD_V3_ACL is not set
+# CONFIG_NFSD_V4 is not set
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+CONFIG_EXPORTFS=m
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=y
+# CONFIG_RPCSEC_GSS_KRB5 is not set
+# CONFIG_RPCSEC_GSS_SPKM3 is not set
+CONFIG_SMB_FS=m
+# CONFIG_SMB_NLS_DEFAULT is not set
+CONFIG_CIFS=m
+# CONFIG_CIFS_STATS is not set
+# CONFIG_CIFS_WEAK_PW_HASH is not set
+# CONFIG_CIFS_XATTR is not set
+# CONFIG_CIFS_DEBUG2 is not set
+# CONFIG_CIFS_EXPERIMENTAL is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+CONFIG_NLS=m
+CONFIG_NLS_DEFAULT="iso8859-1"
+CONFIG_NLS_CODEPAGE_437=m
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+CONFIG_NLS_CODEPAGE_850=m
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+# CONFIG_NLS_ASCII is not set
+CONFIG_NLS_ISO8859_1=m
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+CONFIG_NLS_UTF8=m
+# CONFIG_DLM is not set
+
+#
+# Kernel hacking
+#
+# CONFIG_PRINTK_TIME is not set
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_FRAME_WARN=1024
+CONFIG_MAGIC_SYSRQ=y
+# CONFIG_STRIP_ASM_SYMS is not set
+# CONFIG_UNUSED_SYMBOLS is not set
+CONFIG_DEBUG_FS=y
+# CONFIG_HEADERS_CHECK is not set
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_SHIRQ is not set
+CONFIG_DETECT_SOFTLOCKUP=y
+# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
+CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
+CONFIG_DETECT_HUNG_TASK=y
+# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set
+CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0
+CONFIG_SCHED_DEBUG=y
+# CONFIG_SCHEDSTATS is not set
+# CONFIG_TIMER_STATS is not set
+# CONFIG_DEBUG_OBJECTS is not set
+# CONFIG_SLUB_DEBUG_ON is not set
+# CONFIG_SLUB_STATS is not set
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_RT_MUTEX_TESTER is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_DEBUG_MUTEXES is not set
+# CONFIG_DEBUG_LOCK_ALLOC is not set
+# CONFIG_PROVE_LOCKING is not set
+# CONFIG_LOCK_STAT is not set
+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+CONFIG_STACKTRACE=y
+# CONFIG_DEBUG_KOBJECT is not set
+CONFIG_DEBUG_BUGVERBOSE=y
+# CONFIG_DEBUG_INFO is not set
+# CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_WRITECOUNT is not set
+# CONFIG_DEBUG_MEMORY_INIT is not set
+# CONFIG_DEBUG_LIST is not set
+# CONFIG_DEBUG_SG is not set
+# CONFIG_DEBUG_NOTIFIERS is not set
+# CONFIG_DEBUG_CREDENTIALS is not set
+CONFIG_FRAME_POINTER=y
+# CONFIG_BOOT_PRINTK_DELAY is not set
+# CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_RCU_CPU_STALL_DETECTOR is not set
+# CONFIG_KPROBES_SANITY_TEST is not set
+# CONFIG_BACKTRACE_SELF_TEST is not set
+# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
+# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
+# CONFIG_LKDTM is not set
+# CONFIG_FAULT_INJECTION is not set
+# CONFIG_PAGE_POISONING is not set
+CONFIG_NOP_TRACER=y
+CONFIG_RING_BUFFER=y
+CONFIG_EVENT_TRACING=y
+CONFIG_CONTEXT_SWITCH_TRACER=y
+CONFIG_RING_BUFFER_ALLOW_SWAP=y
+CONFIG_TRACING=y
+CONFIG_TRACING_SUPPORT=y
+CONFIG_FTRACE=y
+# CONFIG_IRQSOFF_TRACER is not set
+# CONFIG_SCHED_TRACER is not set
+# CONFIG_ENABLE_DEFAULT_TRACERS is not set
+# CONFIG_BOOT_TRACER is not set
+CONFIG_BRANCH_PROFILE_NONE=y
+# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set
+# CONFIG_PROFILE_ALL_BRANCHES is not set
+# CONFIG_KMEMTRACE is not set
+# CONFIG_WORKQUEUE_TRACER is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_RING_BUFFER_BENCHMARK is not set
+# CONFIG_DYNAMIC_DEBUG is not set
+# CONFIG_SAMPLES is not set
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITYFS is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+CONFIG_CRYPTO=y
+
+#
+# Crypto core or helper
+#
+# CONFIG_CRYPTO_FIPS is not set
+CONFIG_CRYPTO_ALGAPI=y
+CONFIG_CRYPTO_ALGAPI2=y
+CONFIG_CRYPTO_AEAD=y
+CONFIG_CRYPTO_AEAD2=y
+CONFIG_CRYPTO_BLKCIPHER=y
+CONFIG_CRYPTO_BLKCIPHER2=y
+CONFIG_CRYPTO_HASH=y
+CONFIG_CRYPTO_HASH2=y
+CONFIG_CRYPTO_RNG=m
+CONFIG_CRYPTO_RNG2=y
+CONFIG_CRYPTO_PCOMP=y
+CONFIG_CRYPTO_MANAGER=y
+CONFIG_CRYPTO_MANAGER2=y
+# CONFIG_CRYPTO_GF128MUL is not set
+# CONFIG_CRYPTO_NULL is not set
+CONFIG_CRYPTO_WORKQUEUE=y
+# CONFIG_CRYPTO_CRYPTD is not set
+CONFIG_CRYPTO_AUTHENC=y
+# CONFIG_CRYPTO_TEST is not set
+
+#
+# Authenticated Encryption with Associated Data
+#
+# CONFIG_CRYPTO_CCM is not set
+# CONFIG_CRYPTO_GCM is not set
+# CONFIG_CRYPTO_SEQIV is not set
+
+#
+# Block modes
+#
+CONFIG_CRYPTO_CBC=y
+# CONFIG_CRYPTO_CTR is not set
+# CONFIG_CRYPTO_CTS is not set
+CONFIG_CRYPTO_ECB=m
+# CONFIG_CRYPTO_LRW is not set
+# CONFIG_CRYPTO_PCBC is not set
+# CONFIG_CRYPTO_XTS is not set
+
+#
+# Hash modes
+#
+CONFIG_CRYPTO_HMAC=y
+# CONFIG_CRYPTO_XCBC is not set
+# CONFIG_CRYPTO_VMAC is not set
+
+#
+# Digest
+#
+# CONFIG_CRYPTO_CRC32C is not set
+# CONFIG_CRYPTO_GHASH is not set
+# CONFIG_CRYPTO_MD4 is not set
+CONFIG_CRYPTO_MD5=y
+# CONFIG_CRYPTO_MICHAEL_MIC is not set
+# CONFIG_CRYPTO_RMD128 is not set
+# CONFIG_CRYPTO_RMD160 is not set
+# CONFIG_CRYPTO_RMD256 is not set
+# CONFIG_CRYPTO_RMD320 is not set
+CONFIG_CRYPTO_SHA1=y
+# CONFIG_CRYPTO_SHA256 is not set
+# CONFIG_CRYPTO_SHA512 is not set
+# CONFIG_CRYPTO_TGR192 is not set
+# CONFIG_CRYPTO_WP512 is not set
+
+#
+# Ciphers
+#
+CONFIG_CRYPTO_AES=m
+# CONFIG_CRYPTO_ANUBIS is not set
+CONFIG_CRYPTO_ARC4=m
+# CONFIG_CRYPTO_BLOWFISH is not set
+# CONFIG_CRYPTO_CAMELLIA is not set
+# CONFIG_CRYPTO_CAST5 is not set
+# CONFIG_CRYPTO_CAST6 is not set
+CONFIG_CRYPTO_DES=y
+# CONFIG_CRYPTO_FCRYPT is not set
+# CONFIG_CRYPTO_KHAZAD is not set
+# CONFIG_CRYPTO_SALSA20 is not set
+# CONFIG_CRYPTO_SEED is not set
+# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_TEA is not set
+# CONFIG_CRYPTO_TWOFISH is not set
+
+#
+# Compression
+#
+CONFIG_CRYPTO_DEFLATE=y
+# CONFIG_CRYPTO_ZLIB is not set
+CONFIG_CRYPTO_LZO=y
+
+#
+# Random Number Generation
+#
+CONFIG_CRYPTO_ANSI_CPRNG=m
+CONFIG_CRYPTO_HW=y
+CONFIG_BINARY_PRINTF=y
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+CONFIG_GENERIC_FIND_LAST_BIT=y
+CONFIG_CRC_CCITT=m
+CONFIG_CRC16=y
+# CONFIG_CRC_T10DIF is not set
+# CONFIG_CRC_ITU_T is not set
+CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
+# CONFIG_LIBCRC32C is not set
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_LZO_COMPRESS=y
+CONFIG_LZO_DECOMPRESS=y
+CONFIG_DECOMPRESS_GZIP=y
+CONFIG_GENERIC_ALLOCATOR=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
+CONFIG_NLATTR=y
diff --git a/arch/avr32/configs/atngw100mkii_evklcd101_defconfig b/arch/avr32/configs/atngw100mkii_evklcd101_defconfig
new file mode 100644
index 000000000000..bbf6bc316ecf
--- /dev/null
+++ b/arch/avr32/configs/atngw100mkii_evklcd101_defconfig
@@ -0,0 +1,1549 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.32-rc5
+# Thu Nov  5 15:33:32 2009
+#
+CONFIG_AVR32=y
+CONFIG_GENERIC_GPIO=y
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_GENERIC_BUG=y
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+CONFIG_CONSTRUCTORS=y
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION=""
+# CONFIG_LOCALVERSION_AUTO is not set
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_POSIX_MQUEUE_SYSCTL=y
+CONFIG_BSD_PROCESS_ACCT=y
+CONFIG_BSD_PROCESS_ACCT_V3=y
+# CONFIG_TASKSTATS is not set
+# CONFIG_AUDIT is not set
+
+#
+# RCU Subsystem
+#
+CONFIG_TREE_RCU=y
+# CONFIG_TREE_PREEMPT_RCU is not set
+# CONFIG_RCU_TRACE is not set
+CONFIG_RCU_FANOUT=32
+# CONFIG_RCU_FANOUT_EXACT is not set
+# CONFIG_TREE_RCU_TRACE is not set
+# CONFIG_IKCONFIG is not set
+CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_GROUP_SCHED is not set
+# CONFIG_CGROUPS is not set
+CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SYSFS_DEPRECATED_V2=y
+# CONFIG_RELAY is not set
+# CONFIG_NAMESPACES is not set
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_RD_GZIP=y
+# CONFIG_RD_BZIP2 is not set
+# CONFIG_RD_LZMA is not set
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_SYSCTL=y
+CONFIG_ANON_INODES=y
+CONFIG_EMBEDDED=y
+# CONFIG_SYSCTL_SYSCALL is not set
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_ALL is not set
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+# CONFIG_BASE_FULL is not set
+CONFIG_FUTEX=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_AIO=y
+
+#
+# Kernel Performance Events And Counters
+#
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLUB_DEBUG=y
+# CONFIG_COMPAT_BRK is not set
+# CONFIG_SLAB is not set
+CONFIG_SLUB=y
+# CONFIG_SLOB is not set
+CONFIG_PROFILING=y
+CONFIG_TRACEPOINTS=y
+CONFIG_OPROFILE=m
+CONFIG_HAVE_OPROFILE=y
+CONFIG_KPROBES=y
+CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_CLK=y
+
+#
+# GCOV-based kernel profiling
+#
+# CONFIG_GCOV_KERNEL is not set
+CONFIG_SLOW_WORK=y
+# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
+CONFIG_BASE_SMALL=1
+CONFIG_MODULES=y
+# CONFIG_MODULE_FORCE_LOAD is not set
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODULE_FORCE_UNLOAD=y
+# CONFIG_MODVERSIONS is not set
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+CONFIG_BLOCK=y
+CONFIG_LBDAF=y
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_BLK_DEV_INTEGRITY is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+# CONFIG_IOSCHED_AS is not set
+# CONFIG_IOSCHED_DEADLINE is not set
+CONFIG_IOSCHED_CFQ=y
+# CONFIG_DEFAULT_AS is not set
+# CONFIG_DEFAULT_DEADLINE is not set
+CONFIG_DEFAULT_CFQ=y
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="cfq"
+CONFIG_FREEZER=y
+
+#
+# System Type and features
+#
+CONFIG_TICK_ONESHOT=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+CONFIG_SUBARCH_AVR32B=y
+CONFIG_MMU=y
+CONFIG_PERFORMANCE_COUNTERS=y
+CONFIG_PLATFORM_AT32AP=y
+CONFIG_CPU_AT32AP700X=y
+CONFIG_CPU_AT32AP7000=y
+CONFIG_BOARD_ATNGW100_COMMON=y
+# CONFIG_BOARD_ATSTK1000 is not set
+# CONFIG_BOARD_ATNGW100_MKI is not set
+CONFIG_BOARD_ATNGW100_MKII=y
+# CONFIG_BOARD_HAMMERHEAD is not set
+# CONFIG_BOARD_FAVR_32 is not set
+# CONFIG_BOARD_MERISC is not set
+# CONFIG_BOARD_MIMC200 is not set
+CONFIG_BOARD_ATNGW100_MKII_LCD=y
+# CONFIG_BOARD_ATNGW100_ADDON_NONE is not set
+CONFIG_BOARD_ATNGW100_EVKLCD10X=y
+# CONFIG_BOARD_ATNGW100_MRMT is not set
+# CONFIG_BOARD_ATNGW100_EVKLCD10X_QVGA is not set
+CONFIG_BOARD_ATNGW100_EVKLCD10X_VGA=y
+# CONFIG_BOARD_ATNGW100_EVKLCD10X_POW_QVGA is not set
+CONFIG_LOADER_U_BOOT=y
+
+#
+# Atmel AVR32 AP options
+#
+# CONFIG_AP700X_32_BIT_SMC is not set
+CONFIG_AP700X_16_BIT_SMC=y
+# CONFIG_AP700X_8_BIT_SMC is not set
+CONFIG_LOAD_ADDRESS=0x10000000
+CONFIG_ENTRY_ADDRESS=0x90000000
+CONFIG_PHYS_OFFSET=0x10000000
+CONFIG_PREEMPT_NONE=y
+# CONFIG_PREEMPT_VOLUNTARY is not set
+# CONFIG_PREEMPT is not set
+CONFIG_QUICKLIST=y
+# CONFIG_HAVE_ARCH_BOOTMEM is not set
+# CONFIG_ARCH_HAVE_MEMORY_PRESENT is not set
+# CONFIG_NEED_NODE_MEMMAP_SIZE is not set
+CONFIG_ARCH_FLATMEM_ENABLE=y
+# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
+# CONFIG_ARCH_SPARSEMEM_ENABLE is not set
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_SPLIT_PTLOCK_CPUS=4
+# CONFIG_PHYS_ADDR_T_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=0
+CONFIG_NR_QUICK=2
+CONFIG_VIRT_TO_BUS=y
+CONFIG_HAVE_MLOCK=y
+CONFIG_HAVE_MLOCKED_PAGE_BIT=y
+# CONFIG_KSM is not set
+CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
+# CONFIG_OWNERSHIP_TRACE is not set
+CONFIG_NMI_DEBUGGING=y
+# CONFIG_HZ_100 is not set
+CONFIG_HZ_250=y
+# CONFIG_HZ_300 is not set
+# CONFIG_HZ_1000 is not set
+CONFIG_HZ=250
+CONFIG_SCHED_HRTICK=y
+CONFIG_CMDLINE=""
+
+#
+# Power management options
+#
+CONFIG_PM=y
+# CONFIG_PM_DEBUG is not set
+CONFIG_PM_SLEEP=y
+CONFIG_SUSPEND=y
+CONFIG_SUSPEND_FREEZER=y
+# CONFIG_PM_RUNTIME is not set
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+
+#
+# CPU Frequency scaling
+#
+CONFIG_CPU_FREQ=y
+CONFIG_CPU_FREQ_TABLE=y
+# CONFIG_CPU_FREQ_DEBUG is not set
+# CONFIG_CPU_FREQ_STAT is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set
+CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
+# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set
+CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
+# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set
+CONFIG_CPU_FREQ_GOV_USERSPACE=y
+CONFIG_CPU_FREQ_GOV_ONDEMAND=y
+# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set
+CONFIG_CPU_FREQ_AT32AP=y
+
+#
+# Bus options
+#
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+# CONFIG_PCCARD is not set
+
+#
+# Executable file formats
+#
+CONFIG_BINFMT_ELF=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+# CONFIG_HAVE_AOUT is not set
+# CONFIG_BINFMT_MISC is not set
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+CONFIG_PACKET_MMAP=y
+CONFIG_UNIX=y
+CONFIG_XFRM=y
+CONFIG_XFRM_USER=y
+# CONFIG_XFRM_SUB_POLICY is not set
+# CONFIG_XFRM_MIGRATE is not set
+# CONFIG_XFRM_STATISTICS is not set
+CONFIG_XFRM_IPCOMP=y
+CONFIG_NET_KEY=y
+# CONFIG_NET_KEY_MIGRATE is not set
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_ADVANCED_ROUTER=y
+CONFIG_ASK_IP_FIB_HASH=y
+# CONFIG_IP_FIB_TRIE is not set
+CONFIG_IP_FIB_HASH=y
+# CONFIG_IP_MULTIPLE_TABLES is not set
+# CONFIG_IP_ROUTE_MULTIPATH is not set
+# CONFIG_IP_ROUTE_VERBOSE is not set
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+# CONFIG_IP_PNP_BOOTP is not set
+# CONFIG_IP_PNP_RARP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+CONFIG_IP_MROUTE=y
+CONFIG_IP_PIMSM_V1=y
+# CONFIG_IP_PIMSM_V2 is not set
+# CONFIG_ARPD is not set
+CONFIG_SYN_COOKIES=y
+CONFIG_INET_AH=y
+CONFIG_INET_ESP=y
+CONFIG_INET_IPCOMP=y
+CONFIG_INET_XFRM_TUNNEL=y
+CONFIG_INET_TUNNEL=y
+CONFIG_INET_XFRM_MODE_TRANSPORT=y
+CONFIG_INET_XFRM_MODE_TUNNEL=y
+CONFIG_INET_XFRM_MODE_BEET=y
+# CONFIG_INET_LRO is not set
+CONFIG_INET_DIAG=y
+CONFIG_INET_TCP_DIAG=y
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+CONFIG_IPV6=y
+# CONFIG_IPV6_PRIVACY is not set
+# CONFIG_IPV6_ROUTER_PREF is not set
+# CONFIG_IPV6_OPTIMISTIC_DAD is not set
+CONFIG_INET6_AH=y
+CONFIG_INET6_ESP=y
+CONFIG_INET6_IPCOMP=y
+# CONFIG_IPV6_MIP6 is not set
+CONFIG_INET6_XFRM_TUNNEL=y
+CONFIG_INET6_TUNNEL=y
+CONFIG_INET6_XFRM_MODE_TRANSPORT=y
+CONFIG_INET6_XFRM_MODE_TUNNEL=y
+CONFIG_INET6_XFRM_MODE_BEET=y
+# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set
+CONFIG_IPV6_SIT=y
+CONFIG_IPV6_NDISC_NODETYPE=y
+# CONFIG_IPV6_TUNNEL is not set
+# CONFIG_IPV6_MULTIPLE_TABLES is not set
+# CONFIG_IPV6_MROUTE is not set
+# CONFIG_NETWORK_SECMARK is not set
+CONFIG_NETFILTER=y
+# CONFIG_NETFILTER_DEBUG is not set
+# CONFIG_NETFILTER_ADVANCED is not set
+
+#
+# Core Netfilter Configuration
+#
+CONFIG_NETFILTER_NETLINK=m
+CONFIG_NETFILTER_NETLINK_LOG=m
+CONFIG_NF_CONNTRACK=m
+CONFIG_NF_CONNTRACK_FTP=m
+CONFIG_NF_CONNTRACK_IRC=m
+CONFIG_NF_CONNTRACK_SIP=m
+CONFIG_NF_CT_NETLINK=m
+CONFIG_NETFILTER_XTABLES=y
+CONFIG_NETFILTER_XT_TARGET_MARK=m
+CONFIG_NETFILTER_XT_TARGET_NFLOG=m
+CONFIG_NETFILTER_XT_TARGET_TCPMSS=m
+CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
+CONFIG_NETFILTER_XT_MATCH_MARK=m
+CONFIG_NETFILTER_XT_MATCH_POLICY=m
+CONFIG_NETFILTER_XT_MATCH_STATE=m
+# CONFIG_IP_VS is not set
+
+#
+# IP: Netfilter Configuration
+#
+CONFIG_NF_DEFRAG_IPV4=m
+CONFIG_NF_CONNTRACK_IPV4=m
+CONFIG_NF_CONNTRACK_PROC_COMPAT=y
+CONFIG_IP_NF_IPTABLES=m
+CONFIG_IP_NF_FILTER=m
+CONFIG_IP_NF_TARGET_REJECT=m
+CONFIG_IP_NF_TARGET_LOG=m
+# CONFIG_IP_NF_TARGET_ULOG is not set
+CONFIG_NF_NAT=m
+CONFIG_NF_NAT_NEEDED=y
+CONFIG_IP_NF_TARGET_MASQUERADE=m
+CONFIG_NF_NAT_FTP=m
+CONFIG_NF_NAT_IRC=m
+# CONFIG_NF_NAT_TFTP is not set
+# CONFIG_NF_NAT_AMANDA is not set
+# CONFIG_NF_NAT_PPTP is not set
+# CONFIG_NF_NAT_H323 is not set
+CONFIG_NF_NAT_SIP=m
+CONFIG_IP_NF_MANGLE=m
+
+#
+# IPv6: Netfilter Configuration
+#
+CONFIG_NF_CONNTRACK_IPV6=m
+CONFIG_IP6_NF_IPTABLES=m
+CONFIG_IP6_NF_MATCH_IPV6HEADER=m
+CONFIG_IP6_NF_TARGET_LOG=m
+CONFIG_IP6_NF_FILTER=m
+CONFIG_IP6_NF_TARGET_REJECT=m
+CONFIG_IP6_NF_MANGLE=m
+# CONFIG_IP_DCCP is not set
+# CONFIG_IP_SCTP is not set
+# CONFIG_RDS is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+CONFIG_STP=m
+CONFIG_BRIDGE=m
+# CONFIG_NET_DSA is not set
+CONFIG_VLAN_8021Q=m
+# CONFIG_VLAN_8021Q_GVRP is not set
+# CONFIG_DECNET is not set
+CONFIG_LLC=m
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_PHONET is not set
+# CONFIG_IEEE802154 is not set
+# CONFIG_NET_SCHED is not set
+# CONFIG_DCB is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_NET_TCPPROBE is not set
+# CONFIG_NET_DROP_MONITOR is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+# CONFIG_AF_RXRPC is not set
+CONFIG_WIRELESS=y
+# CONFIG_CFG80211 is not set
+CONFIG_CFG80211_DEFAULT_PS_VALUE=0
+# CONFIG_WIRELESS_OLD_REGULATORY is not set
+# CONFIG_WIRELESS_EXT is not set
+# CONFIG_LIB80211 is not set
+
+#
+# CFG80211 needs to be enabled for MAC80211
+#
+# CONFIG_WIMAX is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+# CONFIG_DEVTMPFS is not set
+CONFIG_STANDALONE=y
+# CONFIG_PREVENT_FIRMWARE_BUILD is not set
+# CONFIG_FW_LOADER is not set
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
+# CONFIG_SYS_HYPERVISOR is not set
+# CONFIG_CONNECTOR is not set
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+# CONFIG_MTD_TESTS is not set
+# CONFIG_MTD_CONCAT is not set
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_REDBOOT_PARTS is not set
+CONFIG_MTD_CMDLINE_PARTS=y
+# CONFIG_MTD_AR7_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+CONFIG_MTD_CFI=y
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_GEN_PROBE=y
+# CONFIG_MTD_CFI_ADV_OPTIONS is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+CONFIG_MTD_CFI_INTELEXT=y
+# CONFIG_MTD_CFI_AMDSTD is not set
+# CONFIG_MTD_CFI_STAA is not set
+CONFIG_MTD_CFI_UTIL=y
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+CONFIG_MTD_PHYSMAP=y
+# CONFIG_MTD_PHYSMAP_COMPAT is not set
+# CONFIG_MTD_PLATRAM is not set
+
+#
+# Self-contained MTD device drivers
+#
+CONFIG_MTD_DATAFLASH=y
+# CONFIG_MTD_DATAFLASH_WRITE_VERIFY is not set
+# CONFIG_MTD_DATAFLASH_OTP is not set
+# CONFIG_MTD_M25P80 is not set
+# CONFIG_MTD_SST25L is not set
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+CONFIG_MTD_NAND=y
+# CONFIG_MTD_NAND_VERIFY_WRITE is not set
+# CONFIG_MTD_NAND_ECC_SMC is not set
+# CONFIG_MTD_NAND_MUSEUM_IDS is not set
+CONFIG_MTD_NAND_IDS=y
+# CONFIG_MTD_NAND_DISKONCHIP is not set
+CONFIG_MTD_NAND_ATMEL=y
+CONFIG_MTD_NAND_ATMEL_ECC_HW=y
+# CONFIG_MTD_NAND_ATMEL_ECC_SOFT is not set
+# CONFIG_MTD_NAND_ATMEL_ECC_NONE is not set
+# CONFIG_MTD_NAND_NANDSIM is not set
+# CONFIG_MTD_NAND_PLATFORM is not set
+# CONFIG_MTD_ONENAND is not set
+
+#
+# LPDDR flash memory drivers
+#
+# CONFIG_MTD_LPDDR is not set
+
+#
+# UBI - Unsorted block images
+#
+CONFIG_MTD_UBI=y
+CONFIG_MTD_UBI_WL_THRESHOLD=4096
+CONFIG_MTD_UBI_BEB_RESERVE=1
+# CONFIG_MTD_UBI_GLUEBI is not set
+
+#
+# UBI debugging options
+#
+# CONFIG_MTD_UBI_DEBUG is not set
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=m
+# CONFIG_BLK_DEV_CRYPTOLOOP is not set
+CONFIG_BLK_DEV_NBD=m
+CONFIG_BLK_DEV_RAM=m
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=4096
+# CONFIG_BLK_DEV_XIP is not set
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+CONFIG_MISC_DEVICES=y
+# CONFIG_ATMEL_PWM is not set
+CONFIG_ATMEL_TCLIB=y
+CONFIG_ATMEL_TCB_CLKSRC=y
+CONFIG_ATMEL_TCB_CLKSRC_BLOCK=0
+# CONFIG_ICS932S401 is not set
+# CONFIG_ATMEL_SSC is not set
+# CONFIG_ENCLOSURE_SERVICES is not set
+# CONFIG_ISL29003 is not set
+# CONFIG_C2PORT is not set
+
+#
+# EEPROM support
+#
+# CONFIG_EEPROM_AT24 is not set
+# CONFIG_EEPROM_AT25 is not set
+# CONFIG_EEPROM_LEGACY is not set
+# CONFIG_EEPROM_MAX6875 is not set
+# CONFIG_EEPROM_93CX6 is not set
+
+#
+# SCSI device support
+#
+# CONFIG_RAID_ATTRS is not set
+# CONFIG_SCSI is not set
+# CONFIG_SCSI_DMA is not set
+# CONFIG_SCSI_NETLINK is not set
+# CONFIG_ATA is not set
+# CONFIG_MD is not set
+CONFIG_NETDEVICES=y
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_VETH is not set
+CONFIG_PHYLIB=y
+
+#
+# MII PHY device drivers
+#
+# CONFIG_MARVELL_PHY is not set
+# CONFIG_DAVICOM_PHY is not set
+# CONFIG_QSEMI_PHY is not set
+# CONFIG_LXT_PHY is not set
+# CONFIG_CICADA_PHY is not set
+# CONFIG_VITESSE_PHY is not set
+# CONFIG_SMSC_PHY is not set
+# CONFIG_BROADCOM_PHY is not set
+# CONFIG_ICPLUS_PHY is not set
+# CONFIG_REALTEK_PHY is not set
+# CONFIG_NATIONAL_PHY is not set
+# CONFIG_STE10XP is not set
+# CONFIG_LSI_ET1011C_PHY is not set
+# CONFIG_FIXED_PHY is not set
+# CONFIG_MDIO_BITBANG is not set
+CONFIG_NET_ETHERNET=y
+# CONFIG_MII is not set
+CONFIG_MACB=y
+# CONFIG_ENC28J60 is not set
+# CONFIG_ETHOC is not set
+# CONFIG_DNET is not set
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
+# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
+# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
+# CONFIG_B44 is not set
+# CONFIG_KS8842 is not set
+# CONFIG_KS8851 is not set
+# CONFIG_KS8851_MLL is not set
+# CONFIG_NETDEV_1000 is not set
+# CONFIG_NETDEV_10000 is not set
+CONFIG_WLAN=y
+# CONFIG_WLAN_PRE80211 is not set
+# CONFIG_WLAN_80211 is not set
+
+#
+# Enable WiMAX (Networking options) to see the WiMAX drivers
+#
+# CONFIG_WAN is not set
+CONFIG_PPP=m
+# CONFIG_PPP_MULTILINK is not set
+CONFIG_PPP_FILTER=y
+CONFIG_PPP_ASYNC=m
+# CONFIG_PPP_SYNC_TTY is not set
+CONFIG_PPP_DEFLATE=m
+CONFIG_PPP_BSDCOMP=m
+CONFIG_PPP_MPPE=m
+CONFIG_PPPOE=m
+# CONFIG_PPPOL2TP is not set
+# CONFIG_SLIP is not set
+CONFIG_SLHC=m
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_ISDN is not set
+# CONFIG_PHONE is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
+
+#
+# Userland interfaces
+#
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_JOYDEV is not set
+CONFIG_INPUT_EVDEV=m
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input Device Drivers
+#
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+CONFIG_INPUT_TOUCHSCREEN=y
+# CONFIG_TOUCHSCREEN_ADS7846 is not set
+# CONFIG_TOUCHSCREEN_AD7877 is not set
+# CONFIG_TOUCHSCREEN_AD7879_I2C is not set
+# CONFIG_TOUCHSCREEN_AD7879_SPI is not set
+# CONFIG_TOUCHSCREEN_AD7879 is not set
+# CONFIG_TOUCHSCREEN_EETI is not set
+# CONFIG_TOUCHSCREEN_FUJITSU is not set
+# CONFIG_TOUCHSCREEN_GUNZE is not set
+# CONFIG_TOUCHSCREEN_ELO is not set
+# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set
+# CONFIG_TOUCHSCREEN_MCS5000 is not set
+# CONFIG_TOUCHSCREEN_MTOUCH is not set
+# CONFIG_TOUCHSCREEN_INEXIO is not set
+# CONFIG_TOUCHSCREEN_MK712 is not set
+# CONFIG_TOUCHSCREEN_PENMOUNT is not set
+# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
+# CONFIG_TOUCHSCREEN_TOUCHWIN is not set
+CONFIG_TOUCHSCREEN_WM97XX=m
+CONFIG_TOUCHSCREEN_WM9705=y
+CONFIG_TOUCHSCREEN_WM9712=y
+CONFIG_TOUCHSCREEN_WM9713=y
+# CONFIG_TOUCHSCREEN_WM97XX_ATMEL is not set
+# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set
+# CONFIG_TOUCHSCREEN_TSC2007 is not set
+# CONFIG_TOUCHSCREEN_W90X900 is not set
+# CONFIG_INPUT_MISC is not set
+
+#
+# Hardware I/O ports
+#
+# CONFIG_SERIO is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+# CONFIG_VT_HW_CONSOLE_BINDING is not set
+CONFIG_DEVKMEM=y
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+# CONFIG_SERIAL_8250 is not set
+
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_ATMEL=y
+CONFIG_SERIAL_ATMEL_CONSOLE=y
+CONFIG_SERIAL_ATMEL_PDC=y
+# CONFIG_SERIAL_ATMEL_TTYAT is not set
+# CONFIG_SERIAL_MAX3100 is not set
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_UNIX98_PTYS=y
+# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
+# CONFIG_LEGACY_PTYS is not set
+# CONFIG_IPMI_HANDLER is not set
+# CONFIG_HW_RANDOM is not set
+# CONFIG_R3964 is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+CONFIG_I2C=m
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_COMPAT=y
+CONFIG_I2C_CHARDEV=m
+CONFIG_I2C_HELPER_AUTO=y
+CONFIG_I2C_ALGOBIT=m
+
+#
+# I2C Hardware Bus support
+#
+
+#
+# I2C system bus drivers (mostly embedded / system-on-chip)
+#
+# CONFIG_I2C_DESIGNWARE is not set
+CONFIG_I2C_GPIO=m
+# CONFIG_I2C_OCORES is not set
+# CONFIG_I2C_SIMTEC is not set
+
+#
+# External I2C/SMBus adapter drivers
+#
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_TAOS_EVM is not set
+
+#
+# Other I2C/SMBus bus drivers
+#
+# CONFIG_I2C_PCA_PLATFORM is not set
+# CONFIG_I2C_STUB is not set
+
+#
+# Miscellaneous I2C Chip support
+#
+# CONFIG_DS1682 is not set
+# CONFIG_SENSORS_TSL2550 is not set
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+# CONFIG_I2C_DEBUG_CHIP is not set
+CONFIG_SPI=y
+# CONFIG_SPI_DEBUG is not set
+CONFIG_SPI_MASTER=y
+
+#
+# SPI Master Controller Drivers
+#
+CONFIG_SPI_ATMEL=y
+# CONFIG_SPI_BITBANG is not set
+# CONFIG_SPI_GPIO is not set
+
+#
+# SPI Protocol Masters
+#
+CONFIG_SPI_SPIDEV=m
+# CONFIG_SPI_TLE62X0 is not set
+
+#
+# PPS support
+#
+# CONFIG_PPS is not set
+CONFIG_ARCH_REQUIRE_GPIOLIB=y
+CONFIG_GPIOLIB=y
+# CONFIG_DEBUG_GPIO is not set
+# CONFIG_GPIO_SYSFS is not set
+
+#
+# Memory mapped GPIO expanders:
+#
+
+#
+# I2C GPIO expanders:
+#
+# CONFIG_GPIO_MAX732X is not set
+# CONFIG_GPIO_PCA953X is not set
+# CONFIG_GPIO_PCF857X is not set
+
+#
+# PCI GPIO expanders:
+#
+
+#
+# SPI GPIO expanders:
+#
+# CONFIG_GPIO_MAX7301 is not set
+# CONFIG_GPIO_MCP23S08 is not set
+# CONFIG_GPIO_MC33880 is not set
+
+#
+# AC97 GPIO expanders:
+#
+# CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
+# CONFIG_HWMON is not set
+# CONFIG_THERMAL is not set
+CONFIG_WATCHDOG=y
+# CONFIG_WATCHDOG_NOWAYOUT is not set
+
+#
+# Watchdog Device Drivers
+#
+# CONFIG_SOFT_WATCHDOG is not set
+CONFIG_AT32AP700X_WDT=y
+CONFIG_SSB_POSSIBLE=y
+
+#
+# Sonics Silicon Backplane
+#
+# CONFIG_SSB is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_CORE is not set
+# CONFIG_MFD_SM501 is not set
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_UCB1400_CORE is not set
+# CONFIG_TPS65010 is not set
+# CONFIG_MFD_TMIO is not set
+# CONFIG_MFD_WM8400 is not set
+# CONFIG_MFD_WM831X is not set
+# CONFIG_MFD_WM8350_I2C is not set
+# CONFIG_MFD_PCF50633 is not set
+# CONFIG_MFD_MC13783 is not set
+# CONFIG_AB3100_CORE is not set
+# CONFIG_EZX_PCAP is not set
+# CONFIG_REGULATOR is not set
+# CONFIG_MEDIA_SUPPORT is not set
+
+#
+# Graphics support
+#
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+CONFIG_FB=y
+# CONFIG_FIRMWARE_EDID is not set
+# CONFIG_FB_DDC is not set
+# CONFIG_FB_BOOT_VESA_SUPPORT is not set
+CONFIG_FB_CFB_FILLRECT=y
+CONFIG_FB_CFB_COPYAREA=y
+CONFIG_FB_CFB_IMAGEBLIT=y
+# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
+# CONFIG_FB_SYS_FILLRECT is not set
+# CONFIG_FB_SYS_COPYAREA is not set
+# CONFIG_FB_SYS_IMAGEBLIT is not set
+# CONFIG_FB_FOREIGN_ENDIAN is not set
+# CONFIG_FB_SYS_FOPS is not set
+# CONFIG_FB_SVGALIB is not set
+# CONFIG_FB_MACMODES is not set
+# CONFIG_FB_BACKLIGHT is not set
+# CONFIG_FB_MODE_HELPERS is not set
+# CONFIG_FB_TILEBLITTING is not set
+
+#
+# Frame buffer hardware drivers
+#
+# CONFIG_FB_S1D13XXX is not set
+CONFIG_FB_ATMEL=y
+# CONFIG_FB_VIRTUAL is not set
+# CONFIG_FB_METRONOME is not set
+# CONFIG_FB_MB862XX is not set
+# CONFIG_FB_BROADSHEET is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+
+#
+# Console display driver support
+#
+CONFIG_DUMMY_CONSOLE=y
+# CONFIG_FRAMEBUFFER_CONSOLE is not set
+# CONFIG_LOGO is not set
+CONFIG_SOUND=y
+CONFIG_SOUND_OSS_CORE=y
+CONFIG_SOUND_OSS_CORE_PRECLAIM=y
+CONFIG_SND=y
+CONFIG_SND_TIMER=y
+CONFIG_SND_PCM=m
+# CONFIG_SND_SEQUENCER is not set
+CONFIG_SND_OSSEMUL=y
+CONFIG_SND_MIXER_OSS=m
+CONFIG_SND_PCM_OSS=m
+CONFIG_SND_PCM_OSS_PLUGINS=y
+CONFIG_SND_HRTIMER=y
+# CONFIG_SND_DYNAMIC_MINORS is not set
+# CONFIG_SND_SUPPORT_OLD_API is not set
+CONFIG_SND_VERBOSE_PROCFS=y
+# CONFIG_SND_VERBOSE_PRINTK is not set
+# CONFIG_SND_DEBUG is not set
+CONFIG_SND_VMASTER=y
+# CONFIG_SND_RAWMIDI_SEQ is not set
+# CONFIG_SND_OPL3_LIB_SEQ is not set
+# CONFIG_SND_OPL4_LIB_SEQ is not set
+# CONFIG_SND_SBAWE_SEQ is not set
+# CONFIG_SND_EMU10K1_SEQ is not set
+CONFIG_SND_AC97_CODEC=m
+# CONFIG_SND_DRIVERS is not set
+
+#
+# Atmel devices (AVR32 and AT91)
+#
+# CONFIG_SND_ATMEL_ABDAC is not set
+CONFIG_SND_ATMEL_AC97C=m
+# CONFIG_SND_SPI is not set
+# CONFIG_SND_SOC is not set
+# CONFIG_SOUND_PRIME is not set
+CONFIG_AC97_BUS=m
+CONFIG_HID_SUPPORT=y
+CONFIG_HID=y
+# CONFIG_HIDRAW is not set
+# CONFIG_HID_PID is not set
+
+#
+# Special HID drivers
+#
+CONFIG_USB_SUPPORT=y
+# CONFIG_USB_ARCH_HAS_HCD is not set
+# CONFIG_USB_ARCH_HAS_OHCI is not set
+# CONFIG_USB_ARCH_HAS_EHCI is not set
+# CONFIG_USB_OTG_WHITELIST is not set
+# CONFIG_USB_OTG_BLACKLIST_HUB is not set
+# CONFIG_USB_GADGET_MUSB_HDRC is not set
+
+#
+# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
+#
+CONFIG_USB_GADGET=y
+# CONFIG_USB_GADGET_DEBUG is not set
+# CONFIG_USB_GADGET_DEBUG_FILES is not set
+# CONFIG_USB_GADGET_DEBUG_FS is not set
+CONFIG_USB_GADGET_VBUS_DRAW=350
+CONFIG_USB_GADGET_SELECTED=y
+# CONFIG_USB_GADGET_AT91 is not set
+CONFIG_USB_GADGET_ATMEL_USBA=y
+CONFIG_USB_ATMEL_USBA=y
+# CONFIG_USB_GADGET_FSL_USB2 is not set
+# CONFIG_USB_GADGET_LH7A40X is not set
+# CONFIG_USB_GADGET_OMAP is not set
+# CONFIG_USB_GADGET_PXA25X is not set
+# CONFIG_USB_GADGET_R8A66597 is not set
+# CONFIG_USB_GADGET_PXA27X is not set
+# CONFIG_USB_GADGET_S3C_HSOTG is not set
+# CONFIG_USB_GADGET_IMX is not set
+# CONFIG_USB_GADGET_S3C2410 is not set
+# CONFIG_USB_GADGET_M66592 is not set
+# CONFIG_USB_GADGET_AMD5536UDC is not set
+# CONFIG_USB_GADGET_FSL_QE is not set
+# CONFIG_USB_GADGET_CI13XXX is not set
+# CONFIG_USB_GADGET_NET2280 is not set
+# CONFIG_USB_GADGET_GOKU is not set
+# CONFIG_USB_GADGET_LANGWELL is not set
+# CONFIG_USB_GADGET_DUMMY_HCD is not set
+CONFIG_USB_GADGET_DUALSPEED=y
+CONFIG_USB_ZERO=m
+# CONFIG_USB_AUDIO is not set
+CONFIG_USB_ETH=m
+CONFIG_USB_ETH_RNDIS=y
+# CONFIG_USB_ETH_EEM is not set
+CONFIG_USB_GADGETFS=m
+CONFIG_USB_FILE_STORAGE=m
+# CONFIG_USB_FILE_STORAGE_TEST is not set
+CONFIG_USB_G_SERIAL=m
+# CONFIG_USB_MIDI_GADGET is not set
+# CONFIG_USB_G_PRINTER is not set
+CONFIG_USB_CDC_COMPOSITE=m
+
+#
+# OTG and related infrastructure
+#
+# CONFIG_USB_GPIO_VBUS is not set
+# CONFIG_NOP_USB_XCEIV is not set
+CONFIG_MMC=y
+# CONFIG_MMC_DEBUG is not set
+# CONFIG_MMC_UNSAFE_RESUME is not set
+
+#
+# MMC/SD/SDIO Card Drivers
+#
+CONFIG_MMC_BLOCK=y
+CONFIG_MMC_BLOCK_BOUNCE=y
+# CONFIG_SDIO_UART is not set
+# CONFIG_MMC_TEST is not set
+
+#
+# MMC/SD/SDIO Host Controller Drivers
+#
+# CONFIG_MMC_SDHCI is not set
+# CONFIG_MMC_AT91 is not set
+CONFIG_MMC_ATMELMCI=y
+# CONFIG_MMC_ATMELMCI_DMA is not set
+# CONFIG_MMC_SPI is not set
+# CONFIG_MEMSTICK is not set
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
+
+#
+# LED drivers
+#
+# CONFIG_LEDS_PCA9532 is not set
+CONFIG_LEDS_GPIO=y
+CONFIG_LEDS_GPIO_PLATFORM=y
+# CONFIG_LEDS_LP3944 is not set
+# CONFIG_LEDS_PCA955X is not set
+# CONFIG_LEDS_DAC124S085 is not set
+# CONFIG_LEDS_BD2802 is not set
+
+#
+# LED Triggers
+#
+CONFIG_LEDS_TRIGGERS=y
+CONFIG_LEDS_TRIGGER_TIMER=y
+CONFIG_LEDS_TRIGGER_HEARTBEAT=y
+# CONFIG_LEDS_TRIGGER_BACKLIGHT is not set
+# CONFIG_LEDS_TRIGGER_GPIO is not set
+# CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set
+
+#
+# iptables trigger is under Netfilter config (LED target)
+#
+# CONFIG_ACCESSIBILITY is not set
+CONFIG_RTC_LIB=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_HCTOSYS=y
+CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
+# CONFIG_RTC_DEBUG is not set
+
+#
+# RTC interfaces
+#
+CONFIG_RTC_INTF_SYSFS=y
+CONFIG_RTC_INTF_PROC=y
+CONFIG_RTC_INTF_DEV=y
+# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
+# CONFIG_RTC_DRV_TEST is not set
+
+#
+# I2C RTC drivers
+#
+# CONFIG_RTC_DRV_DS1307 is not set
+# CONFIG_RTC_DRV_DS1374 is not set
+# CONFIG_RTC_DRV_DS1672 is not set
+# CONFIG_RTC_DRV_MAX6900 is not set
+# CONFIG_RTC_DRV_RS5C372 is not set
+# CONFIG_RTC_DRV_ISL1208 is not set
+# CONFIG_RTC_DRV_X1205 is not set
+# CONFIG_RTC_DRV_PCF8563 is not set
+# CONFIG_RTC_DRV_PCF8583 is not set
+# CONFIG_RTC_DRV_M41T80 is not set
+# CONFIG_RTC_DRV_S35390A is not set
+# CONFIG_RTC_DRV_FM3130 is not set
+# CONFIG_RTC_DRV_RX8581 is not set
+# CONFIG_RTC_DRV_RX8025 is not set
+
+#
+# SPI RTC drivers
+#
+# CONFIG_RTC_DRV_M41T94 is not set
+# CONFIG_RTC_DRV_DS1305 is not set
+# CONFIG_RTC_DRV_DS1390 is not set
+# CONFIG_RTC_DRV_MAX6902 is not set
+# CONFIG_RTC_DRV_R9701 is not set
+# CONFIG_RTC_DRV_RS5C348 is not set
+# CONFIG_RTC_DRV_DS3234 is not set
+# CONFIG_RTC_DRV_PCF2123 is not set
+
+#
+# Platform RTC drivers
+#
+# CONFIG_RTC_DRV_DS1286 is not set
+# CONFIG_RTC_DRV_DS1511 is not set
+# CONFIG_RTC_DRV_DS1553 is not set
+# CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_STK17TA8 is not set
+# CONFIG_RTC_DRV_M48T86 is not set
+# CONFIG_RTC_DRV_M48T35 is not set
+# CONFIG_RTC_DRV_M48T59 is not set
+# CONFIG_RTC_DRV_BQ4802 is not set
+# CONFIG_RTC_DRV_V3020 is not set
+
+#
+# on-CPU RTC drivers
+#
+CONFIG_RTC_DRV_AT32AP700X=y
+CONFIG_DMADEVICES=y
+
+#
+# DMA Devices
+#
+CONFIG_DW_DMAC=y
+CONFIG_DMA_ENGINE=y
+
+#
+# DMA Clients
+#
+# CONFIG_NET_DMA is not set
+# CONFIG_ASYNC_TX_DMA is not set
+# CONFIG_DMATEST is not set
+# CONFIG_AUXDISPLAY is not set
+# CONFIG_UIO is not set
+
+#
+# TI VLYNQ
+#
+# CONFIG_STAGING is not set
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+# CONFIG_EXT2_FS_XATTR is not set
+# CONFIG_EXT2_FS_XIP is not set
+CONFIG_EXT3_FS=y
+# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
+# CONFIG_EXT3_FS_XATTR is not set
+# CONFIG_EXT4_FS is not set
+CONFIG_JBD=y
+# CONFIG_JBD_DEBUG is not set
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+# CONFIG_FS_POSIX_ACL is not set
+# CONFIG_XFS_FS is not set
+# CONFIG_GFS2_FS is not set
+# CONFIG_OCFS2_FS is not set
+# CONFIG_BTRFS_FS is not set
+# CONFIG_NILFS2_FS is not set
+CONFIG_FILE_LOCKING=y
+CONFIG_FSNOTIFY=y
+# CONFIG_DNOTIFY is not set
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+CONFIG_FUSE_FS=m
+# CONFIG_CUSE is not set
+
+#
+# Caches
+#
+# CONFIG_FSCACHE is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=m
+CONFIG_MSDOS_FS=m
+CONFIG_VFAT_FS=m
+CONFIG_FAT_DEFAULT_CODEPAGE=850
+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+# CONFIG_PROC_KCORE is not set
+CONFIG_PROC_SYSCTL=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_HUGETLB_PAGE is not set
+CONFIG_CONFIGFS_FS=y
+CONFIG_MISC_FILESYSTEMS=y
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_DEBUG=0
+CONFIG_JFFS2_FS_WRITEBUFFER=y
+# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
+# CONFIG_JFFS2_SUMMARY is not set
+# CONFIG_JFFS2_FS_XATTR is not set
+# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
+CONFIG_JFFS2_ZLIB=y
+# CONFIG_JFFS2_LZO is not set
+CONFIG_JFFS2_RTIME=y
+# CONFIG_JFFS2_RUBIN is not set
+CONFIG_UBIFS_FS=y
+# CONFIG_UBIFS_FS_XATTR is not set
+# CONFIG_UBIFS_FS_ADVANCED_COMPR is not set
+CONFIG_UBIFS_FS_LZO=y
+CONFIG_UBIFS_FS_ZLIB=y
+# CONFIG_UBIFS_FS_DEBUG is not set
+# CONFIG_CRAMFS is not set
+# CONFIG_SQUASHFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_OMFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+# CONFIG_NFS_V3_ACL is not set
+# CONFIG_NFS_V4 is not set
+CONFIG_ROOT_NFS=y
+CONFIG_NFSD=m
+CONFIG_NFSD_V3=y
+# CONFIG_NFSD_V3_ACL is not set
+# CONFIG_NFSD_V4 is not set
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+CONFIG_EXPORTFS=m
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=y
+# CONFIG_RPCSEC_GSS_KRB5 is not set
+# CONFIG_RPCSEC_GSS_SPKM3 is not set
+CONFIG_SMB_FS=m
+# CONFIG_SMB_NLS_DEFAULT is not set
+CONFIG_CIFS=m
+# CONFIG_CIFS_STATS is not set
+# CONFIG_CIFS_WEAK_PW_HASH is not set
+# CONFIG_CIFS_XATTR is not set
+# CONFIG_CIFS_DEBUG2 is not set
+# CONFIG_CIFS_EXPERIMENTAL is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+CONFIG_NLS=m
+CONFIG_NLS_DEFAULT="iso8859-1"
+CONFIG_NLS_CODEPAGE_437=m
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+CONFIG_NLS_CODEPAGE_850=m
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+# CONFIG_NLS_ASCII is not set
+CONFIG_NLS_ISO8859_1=m
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+CONFIG_NLS_UTF8=m
+# CONFIG_DLM is not set
+
+#
+# Kernel hacking
+#
+# CONFIG_PRINTK_TIME is not set
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_FRAME_WARN=1024
+CONFIG_MAGIC_SYSRQ=y
+# CONFIG_STRIP_ASM_SYMS is not set
+# CONFIG_UNUSED_SYMBOLS is not set
+CONFIG_DEBUG_FS=y
+# CONFIG_HEADERS_CHECK is not set
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_SHIRQ is not set
+CONFIG_DETECT_SOFTLOCKUP=y
+# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
+CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
+CONFIG_DETECT_HUNG_TASK=y
+# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set
+CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0
+CONFIG_SCHED_DEBUG=y
+# CONFIG_SCHEDSTATS is not set
+# CONFIG_TIMER_STATS is not set
+# CONFIG_DEBUG_OBJECTS is not set
+# CONFIG_SLUB_DEBUG_ON is not set
+# CONFIG_SLUB_STATS is not set
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_RT_MUTEX_TESTER is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_DEBUG_MUTEXES is not set
+# CONFIG_DEBUG_LOCK_ALLOC is not set
+# CONFIG_PROVE_LOCKING is not set
+# CONFIG_LOCK_STAT is not set
+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+CONFIG_STACKTRACE=y
+# CONFIG_DEBUG_KOBJECT is not set
+CONFIG_DEBUG_BUGVERBOSE=y
+# CONFIG_DEBUG_INFO is not set
+# CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_WRITECOUNT is not set
+# CONFIG_DEBUG_MEMORY_INIT is not set
+# CONFIG_DEBUG_LIST is not set
+# CONFIG_DEBUG_SG is not set
+# CONFIG_DEBUG_NOTIFIERS is not set
+# CONFIG_DEBUG_CREDENTIALS is not set
+CONFIG_FRAME_POINTER=y
+# CONFIG_BOOT_PRINTK_DELAY is not set
+# CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_RCU_CPU_STALL_DETECTOR is not set
+# CONFIG_KPROBES_SANITY_TEST is not set
+# CONFIG_BACKTRACE_SELF_TEST is not set
+# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
+# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
+# CONFIG_LKDTM is not set
+# CONFIG_FAULT_INJECTION is not set
+# CONFIG_PAGE_POISONING is not set
+CONFIG_NOP_TRACER=y
+CONFIG_RING_BUFFER=y
+CONFIG_EVENT_TRACING=y
+CONFIG_CONTEXT_SWITCH_TRACER=y
+CONFIG_RING_BUFFER_ALLOW_SWAP=y
+CONFIG_TRACING=y
+CONFIG_TRACING_SUPPORT=y
+CONFIG_FTRACE=y
+# CONFIG_IRQSOFF_TRACER is not set
+# CONFIG_SCHED_TRACER is not set
+# CONFIG_ENABLE_DEFAULT_TRACERS is not set
+# CONFIG_BOOT_TRACER is not set
+CONFIG_BRANCH_PROFILE_NONE=y
+# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set
+# CONFIG_PROFILE_ALL_BRANCHES is not set
+# CONFIG_KMEMTRACE is not set
+# CONFIG_WORKQUEUE_TRACER is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_RING_BUFFER_BENCHMARK is not set
+# CONFIG_DYNAMIC_DEBUG is not set
+# CONFIG_SAMPLES is not set
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITYFS is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+CONFIG_CRYPTO=y
+
+#
+# Crypto core or helper
+#
+# CONFIG_CRYPTO_FIPS is not set
+CONFIG_CRYPTO_ALGAPI=y
+CONFIG_CRYPTO_ALGAPI2=y
+CONFIG_CRYPTO_AEAD=y
+CONFIG_CRYPTO_AEAD2=y
+CONFIG_CRYPTO_BLKCIPHER=y
+CONFIG_CRYPTO_BLKCIPHER2=y
+CONFIG_CRYPTO_HASH=y
+CONFIG_CRYPTO_HASH2=y
+CONFIG_CRYPTO_RNG=m
+CONFIG_CRYPTO_RNG2=y
+CONFIG_CRYPTO_PCOMP=y
+CONFIG_CRYPTO_MANAGER=y
+CONFIG_CRYPTO_MANAGER2=y
+# CONFIG_CRYPTO_GF128MUL is not set
+# CONFIG_CRYPTO_NULL is not set
+CONFIG_CRYPTO_WORKQUEUE=y
+# CONFIG_CRYPTO_CRYPTD is not set
+CONFIG_CRYPTO_AUTHENC=y
+# CONFIG_CRYPTO_TEST is not set
+
+#
+# Authenticated Encryption with Associated Data
+#
+# CONFIG_CRYPTO_CCM is not set
+# CONFIG_CRYPTO_GCM is not set
+# CONFIG_CRYPTO_SEQIV is not set
+
+#
+# Block modes
+#
+CONFIG_CRYPTO_CBC=y
+# CONFIG_CRYPTO_CTR is not set
+# CONFIG_CRYPTO_CTS is not set
+CONFIG_CRYPTO_ECB=m
+# CONFIG_CRYPTO_LRW is not set
+# CONFIG_CRYPTO_PCBC is not set
+# CONFIG_CRYPTO_XTS is not set
+
+#
+# Hash modes
+#
+CONFIG_CRYPTO_HMAC=y
+# CONFIG_CRYPTO_XCBC is not set
+# CONFIG_CRYPTO_VMAC is not set
+
+#
+# Digest
+#
+# CONFIG_CRYPTO_CRC32C is not set
+# CONFIG_CRYPTO_GHASH is not set
+# CONFIG_CRYPTO_MD4 is not set
+CONFIG_CRYPTO_MD5=y
+# CONFIG_CRYPTO_MICHAEL_MIC is not set
+# CONFIG_CRYPTO_RMD128 is not set
+# CONFIG_CRYPTO_RMD160 is not set
+# CONFIG_CRYPTO_RMD256 is not set
+# CONFIG_CRYPTO_RMD320 is not set
+CONFIG_CRYPTO_SHA1=y
+# CONFIG_CRYPTO_SHA256 is not set
+# CONFIG_CRYPTO_SHA512 is not set
+# CONFIG_CRYPTO_TGR192 is not set
+# CONFIG_CRYPTO_WP512 is not set
+
+#
+# Ciphers
+#
+CONFIG_CRYPTO_AES=m
+# CONFIG_CRYPTO_ANUBIS is not set
+CONFIG_CRYPTO_ARC4=m
+# CONFIG_CRYPTO_BLOWFISH is not set
+# CONFIG_CRYPTO_CAMELLIA is not set
+# CONFIG_CRYPTO_CAST5 is not set
+# CONFIG_CRYPTO_CAST6 is not set
+CONFIG_CRYPTO_DES=y
+# CONFIG_CRYPTO_FCRYPT is not set
+# CONFIG_CRYPTO_KHAZAD is not set
+# CONFIG_CRYPTO_SALSA20 is not set
+# CONFIG_CRYPTO_SEED is not set
+# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_TEA is not set
+# CONFIG_CRYPTO_TWOFISH is not set
+
+#
+# Compression
+#
+CONFIG_CRYPTO_DEFLATE=y
+# CONFIG_CRYPTO_ZLIB is not set
+CONFIG_CRYPTO_LZO=y
+
+#
+# Random Number Generation
+#
+CONFIG_CRYPTO_ANSI_CPRNG=m
+CONFIG_CRYPTO_HW=y
+CONFIG_BINARY_PRINTF=y
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+CONFIG_GENERIC_FIND_LAST_BIT=y
+CONFIG_CRC_CCITT=m
+CONFIG_CRC16=y
+# CONFIG_CRC_T10DIF is not set
+# CONFIG_CRC_ITU_T is not set
+CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
+# CONFIG_LIBCRC32C is not set
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_LZO_COMPRESS=y
+CONFIG_LZO_DECOMPRESS=y
+CONFIG_DECOMPRESS_GZIP=y
+CONFIG_GENERIC_ALLOCATOR=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
+CONFIG_NLATTR=y
diff --git a/arch/avr32/configs/atstk1002_defconfig b/arch/avr32/configs/atstk1002_defconfig
index 0abe90adb1a4..42dafce02389 100644
--- a/arch/avr32/configs/atstk1002_defconfig
+++ b/arch/avr32/configs/atstk1002_defconfig
@@ -1,7 +1,7 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.27-rc1
-# Mon Aug  4 16:02:27 2008
+# Linux kernel version: 2.6.32-rc5
+# Thu Oct 29 13:00:55 2009
 #
 CONFIG_AVR32=y
 CONFIG_GENERIC_GPIO=y
@@ -21,6 +21,7 @@ CONFIG_GENERIC_HWEIGHT=y
 CONFIG_GENERIC_CALIBRATE_DELAY=y
 CONFIG_GENERIC_BUG=y
 CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+CONFIG_CONSTRUCTORS=y
 
 #
 # General setup
@@ -34,21 +35,36 @@ CONFIG_SWAP=y
 CONFIG_SYSVIPC=y
 CONFIG_SYSVIPC_SYSCTL=y
 CONFIG_POSIX_MQUEUE=y
+CONFIG_POSIX_MQUEUE_SYSCTL=y
 # CONFIG_BSD_PROCESS_ACCT is not set
 # CONFIG_TASKSTATS is not set
 # CONFIG_AUDIT is not set
+
+#
+# RCU Subsystem
+#
+CONFIG_TREE_RCU=y
+# CONFIG_TREE_PREEMPT_RCU is not set
+# CONFIG_RCU_TRACE is not set
+CONFIG_RCU_FANOUT=32
+# CONFIG_RCU_FANOUT_EXACT is not set
+# CONFIG_TREE_RCU_TRACE is not set
 # CONFIG_IKCONFIG is not set
 CONFIG_LOG_BUF_SHIFT=14
-# CONFIG_CGROUPS is not set
 # CONFIG_GROUP_SCHED is not set
+# CONFIG_CGROUPS is not set
 CONFIG_SYSFS_DEPRECATED=y
 CONFIG_SYSFS_DEPRECATED_V2=y
 CONFIG_RELAY=y
 # CONFIG_NAMESPACES is not set
 CONFIG_BLK_DEV_INITRD=y
 CONFIG_INITRAMFS_SOURCE=""
+CONFIG_RD_GZIP=y
+# CONFIG_RD_BZIP2 is not set
+# CONFIG_RD_LZMA is not set
 CONFIG_CC_OPTIMIZE_FOR_SIZE=y
 CONFIG_SYSCTL=y
+CONFIG_ANON_INODES=y
 CONFIG_EMBEDDED=y
 # CONFIG_SYSCTL_SYSCALL is not set
 CONFIG_KALLSYMS=y
@@ -58,38 +74,40 @@ CONFIG_HOTPLUG=y
 CONFIG_PRINTK=y
 CONFIG_BUG=y
 CONFIG_ELF_CORE=y
-# CONFIG_COMPAT_BRK is not set
 # CONFIG_BASE_FULL is not set
 CONFIG_FUTEX=y
-CONFIG_ANON_INODES=y
 CONFIG_EPOLL=y
 CONFIG_SIGNALFD=y
 CONFIG_TIMERFD=y
 CONFIG_EVENTFD=y
 CONFIG_SHMEM=y
+CONFIG_AIO=y
+
+#
+# Kernel Performance Events And Counters
+#
 CONFIG_VM_EVENT_COUNTERS=y
 CONFIG_SLUB_DEBUG=y
+# CONFIG_COMPAT_BRK is not set
 # CONFIG_SLAB is not set
 CONFIG_SLUB=y
 # CONFIG_SLOB is not set
 CONFIG_PROFILING=y
-# CONFIG_MARKERS is not set
+CONFIG_TRACEPOINTS=y
 CONFIG_OPROFILE=m
 CONFIG_HAVE_OPROFILE=y
 CONFIG_KPROBES=y
-# CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS is not set
-# CONFIG_HAVE_IOREMAP_PROT is not set
 CONFIG_HAVE_KPROBES=y
-# CONFIG_HAVE_KRETPROBES is not set
-# CONFIG_HAVE_ARCH_TRACEHOOK is not set
-# CONFIG_HAVE_DMA_ATTRS is not set
-# CONFIG_USE_GENERIC_SMP_HELPERS is not set
 CONFIG_HAVE_CLK=y
-CONFIG_PROC_PAGE_MONITOR=y
+
+#
+# GCOV-based kernel profiling
+#
+# CONFIG_GCOV_KERNEL is not set
+# CONFIG_SLOW_WORK is not set
 # CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
 CONFIG_SLABINFO=y
 CONFIG_RT_MUTEXES=y
-# CONFIG_TINY_SHMEM is not set
 CONFIG_BASE_SMALL=1
 CONFIG_MODULES=y
 # CONFIG_MODULE_FORCE_LOAD is not set
@@ -97,11 +115,8 @@ CONFIG_MODULE_UNLOAD=y
 # CONFIG_MODULE_FORCE_UNLOAD is not set
 # CONFIG_MODVERSIONS is not set
 # CONFIG_MODULE_SRCVERSION_ALL is not set
-CONFIG_KMOD=y
 CONFIG_BLOCK=y
-# CONFIG_LBD is not set
-# CONFIG_BLK_DEV_IO_TRACE is not set
-# CONFIG_LSF is not set
+CONFIG_LBDAF=y
 # CONFIG_BLK_DEV_BSG is not set
 # CONFIG_BLK_DEV_INTEGRITY is not set
 
@@ -117,7 +132,7 @@ CONFIG_IOSCHED_CFQ=y
 CONFIG_DEFAULT_CFQ=y
 # CONFIG_DEFAULT_NOOP is not set
 CONFIG_DEFAULT_IOSCHED="cfq"
-CONFIG_CLASSIC_RCU=y
+CONFIG_FREEZER=y
 
 #
 # System Type and features
@@ -133,7 +148,12 @@ CONFIG_PLATFORM_AT32AP=y
 CONFIG_CPU_AT32AP700X=y
 CONFIG_CPU_AT32AP7000=y
 CONFIG_BOARD_ATSTK1000=y
-# CONFIG_BOARD_ATNGW100 is not set
+# CONFIG_BOARD_ATNGW100_MKI is not set
+# CONFIG_BOARD_ATNGW100_MKII is not set
+# CONFIG_BOARD_HAMMERHEAD is not set
+# CONFIG_BOARD_FAVR_32 is not set
+# CONFIG_BOARD_MERISC is not set
+# CONFIG_BOARD_MIMC200 is not set
 CONFIG_BOARD_ATSTK1002=y
 # CONFIG_BOARD_ATSTK1003 is not set
 # CONFIG_BOARD_ATSTK1004 is not set
@@ -159,7 +179,7 @@ CONFIG_PREEMPT_NONE=y
 # CONFIG_PREEMPT_VOLUNTARY is not set
 # CONFIG_PREEMPT is not set
 CONFIG_QUICKLIST=y
-# CONFIG_HAVE_ARCH_BOOTMEM_NODE is not set
+# CONFIG_HAVE_ARCH_BOOTMEM is not set
 # CONFIG_ARCH_HAVE_MEMORY_PRESENT is not set
 # CONFIG_NEED_NODE_MEMMAP_SIZE is not set
 CONFIG_ARCH_FLATMEM_ENABLE=y
@@ -171,14 +191,16 @@ CONFIG_FLATMEM_MANUAL=y
 # CONFIG_SPARSEMEM_MANUAL is not set
 CONFIG_FLATMEM=y
 CONFIG_FLAT_NODE_MEM_MAP=y
-# CONFIG_SPARSEMEM_STATIC is not set
-# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
 CONFIG_PAGEFLAGS_EXTENDED=y
 CONFIG_SPLIT_PTLOCK_CPUS=4
-# CONFIG_RESOURCES_64BIT is not set
+# CONFIG_PHYS_ADDR_T_64BIT is not set
 CONFIG_ZONE_DMA_FLAG=0
 CONFIG_NR_QUICK=2
 CONFIG_VIRT_TO_BUS=y
+CONFIG_HAVE_MLOCK=y
+CONFIG_HAVE_MLOCKED_PAGE_BIT=y
+# CONFIG_KSM is not set
+CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
 # CONFIG_OWNERSHIP_TRACE is not set
 CONFIG_NMI_DEBUGGING=y
 # CONFIG_HZ_100 is not set
@@ -186,7 +208,7 @@ CONFIG_HZ_250=y
 # CONFIG_HZ_300 is not set
 # CONFIG_HZ_1000 is not set
 CONFIG_HZ=250
-# CONFIG_SCHED_HRTICK is not set
+CONFIG_SCHED_HRTICK=y
 CONFIG_CMDLINE=""
 
 #
@@ -197,6 +219,7 @@ CONFIG_PM=y
 CONFIG_PM_SLEEP=y
 CONFIG_SUSPEND=y
 CONFIG_SUSPEND_FREEZER=y
+# CONFIG_PM_RUNTIME is not set
 CONFIG_ARCH_SUSPEND_POSSIBLE=y
 
 #
@@ -228,6 +251,8 @@ CONFIG_CPU_FREQ_AT32AP=y
 # Executable file formats
 #
 CONFIG_BINFMT_ELF=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+# CONFIG_HAVE_AOUT is not set
 # CONFIG_BINFMT_MISC is not set
 CONFIG_NET=y
 
@@ -295,10 +320,12 @@ CONFIG_IPV6_TUNNEL=m
 # CONFIG_NETFILTER is not set
 # CONFIG_IP_DCCP is not set
 # CONFIG_IP_SCTP is not set
+# CONFIG_RDS is not set
 # CONFIG_TIPC is not set
 # CONFIG_ATM is not set
 CONFIG_STP=m
 CONFIG_BRIDGE=m
+# CONFIG_NET_DSA is not set
 # CONFIG_VLAN_8021Q is not set
 # CONFIG_DECNET is not set
 CONFIG_LLC=m
@@ -309,26 +336,33 @@ CONFIG_LLC=m
 # CONFIG_LAPB is not set
 # CONFIG_ECONET is not set
 # CONFIG_WAN_ROUTER is not set
+# CONFIG_PHONET is not set
+# CONFIG_IEEE802154 is not set
 # CONFIG_NET_SCHED is not set
+# CONFIG_DCB is not set
 
 #
 # Network testing
 #
 # CONFIG_NET_PKTGEN is not set
 # CONFIG_NET_TCPPROBE is not set
+# CONFIG_NET_DROP_MONITOR is not set
 # CONFIG_HAMRADIO is not set
 # CONFIG_CAN is not set
 # CONFIG_IRDA is not set
 # CONFIG_BT is not set
 # CONFIG_AF_RXRPC is not set
+CONFIG_WIRELESS=y
+# CONFIG_CFG80211 is not set
+CONFIG_CFG80211_DEFAULT_PS_VALUE=0
+# CONFIG_WIRELESS_OLD_REGULATORY is not set
+# CONFIG_WIRELESS_EXT is not set
+# CONFIG_LIB80211 is not set
 
 #
-# Wireless
+# CFG80211 needs to be enabled for MAC80211
 #
-# CONFIG_CFG80211 is not set
-# CONFIG_WIRELESS_EXT is not set
-# CONFIG_MAC80211 is not set
-# CONFIG_IEEE80211 is not set
+# CONFIG_WIMAX is not set
 # CONFIG_RFKILL is not set
 # CONFIG_NET_9P is not set
 
@@ -340,6 +374,7 @@ CONFIG_LLC=m
 # Generic Driver Options
 #
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+# CONFIG_DEVTMPFS is not set
 CONFIG_STANDALONE=y
 # CONFIG_PREVENT_FIRMWARE_BUILD is not set
 # CONFIG_FW_LOADER is not set
@@ -349,6 +384,7 @@ CONFIG_STANDALONE=y
 # CONFIG_CONNECTOR is not set
 CONFIG_MTD=y
 # CONFIG_MTD_DEBUG is not set
+# CONFIG_MTD_TESTS is not set
 # CONFIG_MTD_CONCAT is not set
 CONFIG_MTD_PARTITIONS=y
 # CONFIG_MTD_REDBOOT_PARTS is not set
@@ -398,17 +434,18 @@ CONFIG_MTD_CFI_UTIL=y
 #
 # CONFIG_MTD_COMPLEX_MAPPINGS is not set
 CONFIG_MTD_PHYSMAP=y
-CONFIG_MTD_PHYSMAP_START=0x8000000
-CONFIG_MTD_PHYSMAP_LEN=0x0
-CONFIG_MTD_PHYSMAP_BANKWIDTH=2
+# CONFIG_MTD_PHYSMAP_COMPAT is not set
 # CONFIG_MTD_PLATRAM is not set
 
 #
 # Self-contained MTD device drivers
 #
 CONFIG_MTD_DATAFLASH=m
+# CONFIG_MTD_DATAFLASH_WRITE_VERIFY is not set
+# CONFIG_MTD_DATAFLASH_OTP is not set
 CONFIG_MTD_M25P80=m
 CONFIG_M25PXX_USE_FAST_READ=y
+# CONFIG_MTD_SST25L is not set
 # CONFIG_MTD_SLRAM is not set
 # CONFIG_MTD_PHRAM is not set
 # CONFIG_MTD_MTDRAM is not set
@@ -424,9 +461,22 @@ CONFIG_M25PXX_USE_FAST_READ=y
 # CONFIG_MTD_ONENAND is not set
 
 #
+# LPDDR flash memory drivers
+#
+# CONFIG_MTD_LPDDR is not set
+
+#
 # UBI - Unsorted block images
 #
-# CONFIG_MTD_UBI is not set
+CONFIG_MTD_UBI=y
+CONFIG_MTD_UBI_WL_THRESHOLD=4096
+CONFIG_MTD_UBI_BEB_RESERVE=1
+# CONFIG_MTD_UBI_GLUEBI is not set
+
+#
+# UBI debugging options
+#
+# CONFIG_MTD_UBI_DEBUG is not set
 # CONFIG_PARPORT is not set
 CONFIG_BLK_DEV=y
 # CONFIG_BLK_DEV_COW_COMMON is not set
@@ -444,10 +494,20 @@ CONFIG_ATMEL_PWM=m
 CONFIG_ATMEL_TCLIB=y
 CONFIG_ATMEL_TCB_CLKSRC=y
 CONFIG_ATMEL_TCB_CLKSRC_BLOCK=0
-# CONFIG_EEPROM_93CX6 is not set
+# CONFIG_ICS932S401 is not set
 CONFIG_ATMEL_SSC=m
 # CONFIG_ENCLOSURE_SERVICES is not set
-# CONFIG_HAVE_IDE is not set
+# CONFIG_ISL29003 is not set
+# CONFIG_C2PORT is not set
+
+#
+# EEPROM support
+#
+CONFIG_EEPROM_AT24=m
+# CONFIG_EEPROM_AT25 is not set
+# CONFIG_EEPROM_LEGACY is not set
+# CONFIG_EEPROM_MAX6875 is not set
+# CONFIG_EEPROM_93CX6 is not set
 
 #
 # SCSI device support
@@ -469,10 +529,6 @@ CONFIG_BLK_DEV_SR=m
 # CONFIG_BLK_DEV_SR_VENDOR is not set
 # CONFIG_CHR_DEV_SG is not set
 # CONFIG_CHR_DEV_SCH is not set
-
-#
-# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
-#
 # CONFIG_SCSI_MULTI_LUN is not set
 # CONFIG_SCSI_CONSTANTS is not set
 # CONFIG_SCSI_LOGGING is not set
@@ -489,8 +545,10 @@ CONFIG_SCSI_WAIT_SCAN=m
 # CONFIG_SCSI_SRP_ATTRS is not set
 # CONFIG_SCSI_LOWLEVEL is not set
 # CONFIG_SCSI_DH is not set
+# CONFIG_SCSI_OSD_INITIATOR is not set
 CONFIG_ATA=m
 # CONFIG_ATA_NONSTANDARD is not set
+CONFIG_ATA_VERBOSE_ERROR=y
 # CONFIG_SATA_PMP is not set
 CONFIG_ATA_SFF=y
 # CONFIG_SATA_MV is not set
@@ -519,26 +577,37 @@ CONFIG_PHYLIB=y
 # CONFIG_BROADCOM_PHY is not set
 # CONFIG_ICPLUS_PHY is not set
 # CONFIG_REALTEK_PHY is not set
+# CONFIG_NATIONAL_PHY is not set
+# CONFIG_STE10XP is not set
+# CONFIG_LSI_ET1011C_PHY is not set
 # CONFIG_FIXED_PHY is not set
 # CONFIG_MDIO_BITBANG is not set
 CONFIG_NET_ETHERNET=y
 # CONFIG_MII is not set
 CONFIG_MACB=y
 # CONFIG_ENC28J60 is not set
+# CONFIG_ETHOC is not set
+# CONFIG_DNET is not set
 # CONFIG_IBM_NEW_EMAC_ZMII is not set
 # CONFIG_IBM_NEW_EMAC_RGMII is not set
 # CONFIG_IBM_NEW_EMAC_TAH is not set
 # CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
+# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
+# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
 # CONFIG_B44 is not set
+# CONFIG_KS8842 is not set
+# CONFIG_KS8851 is not set
+# CONFIG_KS8851_MLL is not set
 # CONFIG_NETDEV_1000 is not set
 # CONFIG_NETDEV_10000 is not set
+CONFIG_WLAN=y
+# CONFIG_WLAN_PRE80211 is not set
+# CONFIG_WLAN_80211 is not set
 
 #
-# Wireless LAN
+# Enable WiMAX (Networking options) to see the WiMAX drivers
 #
-# CONFIG_WLAN_PRE80211 is not set
-# CONFIG_WLAN_80211 is not set
-# CONFIG_IWLWIFI_LEDS is not set
 # CONFIG_WAN is not set
 CONFIG_PPP=m
 # CONFIG_PPP_MULTILINK is not set
@@ -580,18 +649,25 @@ CONFIG_INPUT_EVDEV=m
 # Input Device Drivers
 #
 CONFIG_INPUT_KEYBOARD=y
+# CONFIG_KEYBOARD_ADP5588 is not set
 # CONFIG_KEYBOARD_ATKBD is not set
-# CONFIG_KEYBOARD_SUNKBD is not set
+# CONFIG_QT2160 is not set
 # CONFIG_KEYBOARD_LKKBD is not set
-# CONFIG_KEYBOARD_XTKBD is not set
+CONFIG_KEYBOARD_GPIO=m
+# CONFIG_KEYBOARD_MATRIX is not set
+# CONFIG_KEYBOARD_LM8323 is not set
+# CONFIG_KEYBOARD_MAX7359 is not set
 # CONFIG_KEYBOARD_NEWTON is not set
+# CONFIG_KEYBOARD_OPENCORES is not set
 # CONFIG_KEYBOARD_STOWAWAY is not set
-CONFIG_KEYBOARD_GPIO=m
+# CONFIG_KEYBOARD_SUNKBD is not set
+# CONFIG_KEYBOARD_XTKBD is not set
 CONFIG_INPUT_MOUSE=y
 # CONFIG_MOUSE_PS2 is not set
 # CONFIG_MOUSE_SERIAL is not set
 # CONFIG_MOUSE_VSXXXAA is not set
 CONFIG_MOUSE_GPIO=m
+# CONFIG_MOUSE_SYNAPTICS_I2C is not set
 # CONFIG_INPUT_JOYSTICK is not set
 # CONFIG_INPUT_TABLET is not set
 # CONFIG_INPUT_TOUCHSCREEN is not set
@@ -622,9 +698,11 @@ CONFIG_SERIAL_ATMEL=y
 CONFIG_SERIAL_ATMEL_CONSOLE=y
 CONFIG_SERIAL_ATMEL_PDC=y
 # CONFIG_SERIAL_ATMEL_TTYAT is not set
+# CONFIG_SERIAL_MAX3100 is not set
 CONFIG_SERIAL_CORE=y
 CONFIG_SERIAL_CORE_CONSOLE=y
 CONFIG_UNIX98_PTYS=y
+# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
 # CONFIG_LEGACY_PTYS is not set
 # CONFIG_IPMI_HANDLER is not set
 # CONFIG_HW_RANDOM is not set
@@ -633,7 +711,9 @@ CONFIG_UNIX98_PTYS=y
 # CONFIG_TCG_TPM is not set
 CONFIG_I2C=m
 CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_COMPAT=y
 CONFIG_I2C_CHARDEV=m
+CONFIG_I2C_HELPER_AUTO=y
 CONFIG_I2C_ALGOBIT=m
 
 #
@@ -643,6 +723,7 @@ CONFIG_I2C_ALGOBIT=m
 #
 # I2C system bus drivers (mostly embedded / system-on-chip)
 #
+# CONFIG_I2C_DESIGNWARE is not set
 CONFIG_I2C_GPIO=m
 # CONFIG_I2C_OCORES is not set
 # CONFIG_I2C_SIMTEC is not set
@@ -663,14 +744,6 @@ CONFIG_I2C_GPIO=m
 # Miscellaneous I2C Chip support
 #
 # CONFIG_DS1682 is not set
-CONFIG_EEPROM_AT24=m
-# CONFIG_EEPROM_LEGACY is not set
-# CONFIG_SENSORS_PCF8574 is not set
-# CONFIG_PCF8575 is not set
-# CONFIG_SENSORS_PCA9539 is not set
-# CONFIG_SENSORS_PCF8591 is not set
-# CONFIG_TPS65010 is not set
-# CONFIG_SENSORS_MAX6875 is not set
 # CONFIG_SENSORS_TSL2550 is not set
 # CONFIG_I2C_DEBUG_CORE is not set
 # CONFIG_I2C_DEBUG_ALGO is not set
@@ -685,19 +758,28 @@ CONFIG_SPI_MASTER=y
 #
 CONFIG_SPI_ATMEL=y
 # CONFIG_SPI_BITBANG is not set
+# CONFIG_SPI_GPIO is not set
 
 #
 # SPI Protocol Masters
 #
-# CONFIG_EEPROM_AT25 is not set
 CONFIG_SPI_SPIDEV=m
 # CONFIG_SPI_TLE62X0 is not set
+
+#
+# PPS support
+#
+# CONFIG_PPS is not set
 CONFIG_ARCH_REQUIRE_GPIOLIB=y
 CONFIG_GPIOLIB=y
 # CONFIG_DEBUG_GPIO is not set
 CONFIG_GPIO_SYSFS=y
 
 #
+# Memory mapped GPIO expanders:
+#
+
+#
 # I2C GPIO expanders:
 #
 # CONFIG_GPIO_MAX732X is not set
@@ -713,11 +795,15 @@ CONFIG_GPIO_SYSFS=y
 #
 # CONFIG_GPIO_MAX7301 is not set
 # CONFIG_GPIO_MCP23S08 is not set
+# CONFIG_GPIO_MC33880 is not set
+
+#
+# AC97 GPIO expanders:
+#
 # CONFIG_W1 is not set
 # CONFIG_POWER_SUPPLY is not set
 # CONFIG_HWMON is not set
 # CONFIG_THERMAL is not set
-# CONFIG_THERMAL_HWMON is not set
 CONFIG_WATCHDOG=y
 # CONFIG_WATCHDOG_NOWAYOUT is not set
 
@@ -726,11 +812,11 @@ CONFIG_WATCHDOG=y
 #
 # CONFIG_SOFT_WATCHDOG is not set
 CONFIG_AT32AP700X_WDT=y
+CONFIG_SSB_POSSIBLE=y
 
 #
 # Sonics Silicon Backplane
 #
-CONFIG_SSB_POSSIBLE=y
 # CONFIG_SSB is not set
 
 #
@@ -739,22 +825,17 @@ CONFIG_SSB_POSSIBLE=y
 # CONFIG_MFD_CORE is not set
 # CONFIG_MFD_SM501 is not set
 # CONFIG_HTC_PASIC3 is not set
-
-#
-# Multimedia devices
-#
-
-#
-# Multimedia core support
-#
-# CONFIG_VIDEO_DEV is not set
-# CONFIG_DVB_CORE is not set
-# CONFIG_VIDEO_MEDIA is not set
-
-#
-# Multimedia drivers
-#
-# CONFIG_DAB is not set
+# CONFIG_TPS65010 is not set
+# CONFIG_MFD_TMIO is not set
+# CONFIG_MFD_WM8400 is not set
+# CONFIG_MFD_WM831X is not set
+# CONFIG_MFD_WM8350_I2C is not set
+# CONFIG_MFD_PCF50633 is not set
+# CONFIG_MFD_MC13783 is not set
+# CONFIG_AB3100_CORE is not set
+# CONFIG_EZX_PCAP is not set
+# CONFIG_REGULATOR is not set
+# CONFIG_MEDIA_SUPPORT is not set
 
 #
 # Graphics support
@@ -764,6 +845,7 @@ CONFIG_SSB_POSSIBLE=y
 CONFIG_FB=y
 # CONFIG_FIRMWARE_EDID is not set
 # CONFIG_FB_DDC is not set
+# CONFIG_FB_BOOT_VESA_SUPPORT is not set
 CONFIG_FB_CFB_FILLRECT=y
 CONFIG_FB_CFB_COPYAREA=y
 CONFIG_FB_CFB_IMAGEBLIT=y
@@ -785,10 +867,15 @@ CONFIG_FB_CFB_IMAGEBLIT=y
 # CONFIG_FB_S1D13XXX is not set
 CONFIG_FB_ATMEL=y
 # CONFIG_FB_VIRTUAL is not set
+# CONFIG_FB_METRONOME is not set
+# CONFIG_FB_MB862XX is not set
+# CONFIG_FB_BROADSHEET is not set
 CONFIG_BACKLIGHT_LCD_SUPPORT=y
 CONFIG_LCD_CLASS_DEVICE=y
+# CONFIG_LCD_LMS283GF05 is not set
 CONFIG_LCD_LTV350QV=y
 # CONFIG_LCD_ILI9320 is not set
+# CONFIG_LCD_TDO24M is not set
 # CONFIG_LCD_VGG2432A4 is not set
 # CONFIG_LCD_PLATFORM is not set
 # CONFIG_BACKLIGHT_CLASS_DEVICE is not set
@@ -799,6 +886,8 @@ CONFIG_LCD_LTV350QV=y
 # CONFIG_DISPLAY_SUPPORT is not set
 # CONFIG_LOGO is not set
 CONFIG_SOUND=m
+CONFIG_SOUND_OSS_CORE=y
+CONFIG_SOUND_OSS_CORE_PRECLAIM=y
 CONFIG_SND=m
 CONFIG_SND_TIMER=m
 CONFIG_SND_PCM=m
@@ -807,12 +896,24 @@ CONFIG_SND_OSSEMUL=y
 CONFIG_SND_MIXER_OSS=m
 CONFIG_SND_PCM_OSS=m
 CONFIG_SND_PCM_OSS_PLUGINS=y
+# CONFIG_SND_HRTIMER is not set
 # CONFIG_SND_DYNAMIC_MINORS is not set
 # CONFIG_SND_SUPPORT_OLD_API is not set
 # CONFIG_SND_VERBOSE_PROCFS is not set
 # CONFIG_SND_VERBOSE_PRINTK is not set
 # CONFIG_SND_DEBUG is not set
+# CONFIG_SND_RAWMIDI_SEQ is not set
+# CONFIG_SND_OPL3_LIB_SEQ is not set
+# CONFIG_SND_OPL4_LIB_SEQ is not set
+# CONFIG_SND_SBAWE_SEQ is not set
+# CONFIG_SND_EMU10K1_SEQ is not set
 # CONFIG_SND_DRIVERS is not set
+
+#
+# Atmel devices (AVR32 and AT91)
+#
+# CONFIG_SND_ATMEL_ABDAC is not set
+# CONFIG_SND_ATMEL_AC97C is not set
 CONFIG_SND_SPI=y
 CONFIG_SND_AT73C213=m
 CONFIG_SND_AT73C213_TARGET_BITRATE=48000
@@ -825,33 +926,43 @@ CONFIG_USB_SUPPORT=y
 # CONFIG_USB_ARCH_HAS_EHCI is not set
 # CONFIG_USB_OTG_WHITELIST is not set
 # CONFIG_USB_OTG_BLACKLIST_HUB is not set
+# CONFIG_USB_GADGET_MUSB_HDRC is not set
 
 #
-# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
+# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
 #
 CONFIG_USB_GADGET=y
 # CONFIG_USB_GADGET_DEBUG is not set
 # CONFIG_USB_GADGET_DEBUG_FILES is not set
 # CONFIG_USB_GADGET_DEBUG_FS is not set
+CONFIG_USB_GADGET_VBUS_DRAW=2
 CONFIG_USB_GADGET_SELECTED=y
-# CONFIG_USB_GADGET_AMD5536UDC is not set
+# CONFIG_USB_GADGET_AT91 is not set
 CONFIG_USB_GADGET_ATMEL_USBA=y
 CONFIG_USB_ATMEL_USBA=y
 # CONFIG_USB_GADGET_FSL_USB2 is not set
-# CONFIG_USB_GADGET_NET2280 is not set
-# CONFIG_USB_GADGET_PXA25X is not set
-# CONFIG_USB_GADGET_M66592 is not set
-# CONFIG_USB_GADGET_PXA27X is not set
-# CONFIG_USB_GADGET_GOKU is not set
 # CONFIG_USB_GADGET_LH7A40X is not set
 # CONFIG_USB_GADGET_OMAP is not set
+# CONFIG_USB_GADGET_PXA25X is not set
+# CONFIG_USB_GADGET_R8A66597 is not set
+# CONFIG_USB_GADGET_PXA27X is not set
+# CONFIG_USB_GADGET_S3C_HSOTG is not set
+# CONFIG_USB_GADGET_IMX is not set
 # CONFIG_USB_GADGET_S3C2410 is not set
-# CONFIG_USB_GADGET_AT91 is not set
+# CONFIG_USB_GADGET_M66592 is not set
+# CONFIG_USB_GADGET_AMD5536UDC is not set
+# CONFIG_USB_GADGET_FSL_QE is not set
+# CONFIG_USB_GADGET_CI13XXX is not set
+# CONFIG_USB_GADGET_NET2280 is not set
+# CONFIG_USB_GADGET_GOKU is not set
+# CONFIG_USB_GADGET_LANGWELL is not set
 # CONFIG_USB_GADGET_DUMMY_HCD is not set
 CONFIG_USB_GADGET_DUALSPEED=y
 CONFIG_USB_ZERO=m
+# CONFIG_USB_AUDIO is not set
 CONFIG_USB_ETH=m
 CONFIG_USB_ETH_RNDIS=y
+# CONFIG_USB_ETH_EEM is not set
 CONFIG_USB_GADGETFS=m
 CONFIG_USB_FILE_STORAGE=m
 # CONFIG_USB_FILE_STORAGE_TEST is not set
@@ -859,12 +970,18 @@ CONFIG_USB_G_SERIAL=m
 # CONFIG_USB_MIDI_GADGET is not set
 # CONFIG_USB_G_PRINTER is not set
 CONFIG_USB_CDC_COMPOSITE=m
+
+#
+# OTG and related infrastructure
+#
+# CONFIG_USB_GPIO_VBUS is not set
+# CONFIG_NOP_USB_XCEIV is not set
 CONFIG_MMC=y
 # CONFIG_MMC_DEBUG is not set
 # CONFIG_MMC_UNSAFE_RESUME is not set
 
 #
-# MMC/SD Card Drivers
+# MMC/SD/SDIO Card Drivers
 #
 CONFIG_MMC_BLOCK=y
 CONFIG_MMC_BLOCK_BOUNCE=y
@@ -872,10 +989,12 @@ CONFIG_MMC_BLOCK_BOUNCE=y
 # CONFIG_MMC_TEST is not set
 
 #
-# MMC/SD Host Controller Drivers
+# MMC/SD/SDIO Host Controller Drivers
 #
 # CONFIG_MMC_SDHCI is not set
+# CONFIG_MMC_AT91 is not set
 CONFIG_MMC_ATMELMCI=y
+# CONFIG_MMC_ATMELMCI_DMA is not set
 CONFIG_MMC_SPI=m
 # CONFIG_MEMSTICK is not set
 CONFIG_NEW_LEDS=y
@@ -887,7 +1006,11 @@ CONFIG_LEDS_CLASS=m
 CONFIG_LEDS_ATMEL_PWM=m
 # CONFIG_LEDS_PCA9532 is not set
 CONFIG_LEDS_GPIO=m
+CONFIG_LEDS_GPIO_PLATFORM=y
+# CONFIG_LEDS_LP3944 is not set
 # CONFIG_LEDS_PCA955X is not set
+# CONFIG_LEDS_DAC124S085 is not set
+# CONFIG_LEDS_BD2802 is not set
 
 #
 # LED Triggers
@@ -895,7 +1018,13 @@ CONFIG_LEDS_GPIO=m
 CONFIG_LEDS_TRIGGERS=y
 CONFIG_LEDS_TRIGGER_TIMER=m
 CONFIG_LEDS_TRIGGER_HEARTBEAT=m
+# CONFIG_LEDS_TRIGGER_BACKLIGHT is not set
+# CONFIG_LEDS_TRIGGER_GPIO is not set
 CONFIG_LEDS_TRIGGER_DEFAULT_ON=m
+
+#
+# iptables trigger is under Netfilter config (LED target)
+#
 # CONFIG_ACCESSIBILITY is not set
 CONFIG_RTC_LIB=y
 CONFIG_RTC_CLASS=y
@@ -927,25 +1056,33 @@ CONFIG_RTC_INTF_DEV=y
 # CONFIG_RTC_DRV_M41T80 is not set
 # CONFIG_RTC_DRV_S35390A is not set
 # CONFIG_RTC_DRV_FM3130 is not set
+# CONFIG_RTC_DRV_RX8581 is not set
+# CONFIG_RTC_DRV_RX8025 is not set
 
 #
 # SPI RTC drivers
 #
 # CONFIG_RTC_DRV_M41T94 is not set
 # CONFIG_RTC_DRV_DS1305 is not set
+# CONFIG_RTC_DRV_DS1390 is not set
 # CONFIG_RTC_DRV_MAX6902 is not set
 # CONFIG_RTC_DRV_R9701 is not set
 # CONFIG_RTC_DRV_RS5C348 is not set
+# CONFIG_RTC_DRV_DS3234 is not set
+# CONFIG_RTC_DRV_PCF2123 is not set
 
 #
 # Platform RTC drivers
 #
+# CONFIG_RTC_DRV_DS1286 is not set
 # CONFIG_RTC_DRV_DS1511 is not set
 # CONFIG_RTC_DRV_DS1553 is not set
 # CONFIG_RTC_DRV_DS1742 is not set
 # CONFIG_RTC_DRV_STK17TA8 is not set
 # CONFIG_RTC_DRV_M48T86 is not set
+# CONFIG_RTC_DRV_M48T35 is not set
 # CONFIG_RTC_DRV_M48T59 is not set
+# CONFIG_RTC_DRV_BQ4802 is not set
 # CONFIG_RTC_DRV_V3020 is not set
 
 #
@@ -964,25 +1101,45 @@ CONFIG_DMA_ENGINE=y
 # DMA Clients
 #
 # CONFIG_NET_DMA is not set
+# CONFIG_ASYNC_TX_DMA is not set
 # CONFIG_DMATEST is not set
+# CONFIG_AUXDISPLAY is not set
 # CONFIG_UIO is not set
 
 #
+# TI VLYNQ
+#
+# CONFIG_STAGING is not set
+
+#
 # File systems
 #
 CONFIG_EXT2_FS=y
 # CONFIG_EXT2_FS_XATTR is not set
 # CONFIG_EXT2_FS_XIP is not set
 CONFIG_EXT3_FS=y
+# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
 # CONFIG_EXT3_FS_XATTR is not set
-# CONFIG_EXT4DEV_FS is not set
+CONFIG_EXT4_FS=y
+CONFIG_EXT4_FS_XATTR=y
+# CONFIG_EXT4_FS_POSIX_ACL is not set
+# CONFIG_EXT4_FS_SECURITY is not set
+# CONFIG_EXT4_DEBUG is not set
 CONFIG_JBD=y
 # CONFIG_JBD_DEBUG is not set
+CONFIG_JBD2=y
+# CONFIG_JBD2_DEBUG is not set
+CONFIG_FS_MBCACHE=y
 # CONFIG_REISERFS_FS is not set
 # CONFIG_JFS_FS is not set
 # CONFIG_FS_POSIX_ACL is not set
 # CONFIG_XFS_FS is not set
+# CONFIG_GFS2_FS is not set
 # CONFIG_OCFS2_FS is not set
+# CONFIG_BTRFS_FS is not set
+# CONFIG_NILFS2_FS is not set
+CONFIG_FILE_LOCKING=y
+CONFIG_FSNOTIFY=y
 # CONFIG_DNOTIFY is not set
 CONFIG_INOTIFY=y
 CONFIG_INOTIFY_USER=y
@@ -990,6 +1147,12 @@ CONFIG_INOTIFY_USER=y
 # CONFIG_AUTOFS_FS is not set
 # CONFIG_AUTOFS4_FS is not set
 CONFIG_FUSE_FS=m
+# CONFIG_CUSE is not set
+
+#
+# Caches
+#
+# CONFIG_FSCACHE is not set
 
 #
 # CD-ROM/DVD Filesystems
@@ -1013,15 +1176,13 @@ CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
 CONFIG_PROC_FS=y
 CONFIG_PROC_KCORE=y
 CONFIG_PROC_SYSCTL=y
+CONFIG_PROC_PAGE_MONITOR=y
 CONFIG_SYSFS=y
 CONFIG_TMPFS=y
 # CONFIG_TMPFS_POSIX_ACL is not set
 # CONFIG_HUGETLB_PAGE is not set
 # CONFIG_CONFIGFS_FS is not set
-
-#
-# Miscellaneous filesystems
-#
+CONFIG_MISC_FILESYSTEMS=y
 # CONFIG_ADFS_FS is not set
 # CONFIG_AFFS_FS is not set
 # CONFIG_HFS_FS is not set
@@ -1039,7 +1200,14 @@ CONFIG_JFFS2_ZLIB=y
 # CONFIG_JFFS2_LZO is not set
 CONFIG_JFFS2_RTIME=y
 # CONFIG_JFFS2_RUBIN is not set
+CONFIG_UBIFS_FS=y
+# CONFIG_UBIFS_FS_XATTR is not set
+# CONFIG_UBIFS_FS_ADVANCED_COMPR is not set
+CONFIG_UBIFS_FS_LZO=y
+CONFIG_UBIFS_FS_ZLIB=y
+# CONFIG_UBIFS_FS_DEBUG is not set
 # CONFIG_CRAMFS is not set
+# CONFIG_SQUASHFS is not set
 # CONFIG_VXFS_FS is not set
 CONFIG_MINIX_FS=m
 # CONFIG_OMFS_FS is not set
@@ -1122,6 +1290,7 @@ CONFIG_ENABLE_WARN_DEPRECATED=y
 CONFIG_ENABLE_MUST_CHECK=y
 CONFIG_FRAME_WARN=1024
 CONFIG_MAGIC_SYSRQ=y
+# CONFIG_STRIP_ASM_SYMS is not set
 # CONFIG_UNUSED_SYMBOLS is not set
 CONFIG_DEBUG_FS=y
 # CONFIG_HEADERS_CHECK is not set
@@ -1130,6 +1299,9 @@ CONFIG_DEBUG_KERNEL=y
 CONFIG_DETECT_SOFTLOCKUP=y
 # CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
 CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
+CONFIG_DETECT_HUNG_TASK=y
+# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set
+CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0
 CONFIG_SCHED_DEBUG=y
 # CONFIG_SCHEDSTATS is not set
 # CONFIG_TIMER_STATS is not set
@@ -1145,6 +1317,7 @@ CONFIG_SCHED_DEBUG=y
 # CONFIG_LOCK_STAT is not set
 # CONFIG_DEBUG_SPINLOCK_SLEEP is not set
 # CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+CONFIG_STACKTRACE=y
 # CONFIG_DEBUG_KOBJECT is not set
 CONFIG_DEBUG_BUGVERBOSE=y
 # CONFIG_DEBUG_INFO is not set
@@ -1153,13 +1326,39 @@ CONFIG_DEBUG_BUGVERBOSE=y
 # CONFIG_DEBUG_MEMORY_INIT is not set
 # CONFIG_DEBUG_LIST is not set
 # CONFIG_DEBUG_SG is not set
+# CONFIG_DEBUG_NOTIFIERS is not set
+# CONFIG_DEBUG_CREDENTIALS is not set
 CONFIG_FRAME_POINTER=y
 # CONFIG_BOOT_PRINTK_DELAY is not set
 # CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_RCU_CPU_STALL_DETECTOR is not set
 # CONFIG_KPROBES_SANITY_TEST is not set
 # CONFIG_BACKTRACE_SELF_TEST is not set
+# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
+# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
 # CONFIG_LKDTM is not set
 # CONFIG_FAULT_INJECTION is not set
+# CONFIG_PAGE_POISONING is not set
+CONFIG_NOP_TRACER=y
+CONFIG_RING_BUFFER=y
+CONFIG_EVENT_TRACING=y
+CONFIG_CONTEXT_SWITCH_TRACER=y
+CONFIG_RING_BUFFER_ALLOW_SWAP=y
+CONFIG_TRACING=y
+CONFIG_TRACING_SUPPORT=y
+CONFIG_FTRACE=y
+# CONFIG_IRQSOFF_TRACER is not set
+# CONFIG_SCHED_TRACER is not set
+# CONFIG_ENABLE_DEFAULT_TRACERS is not set
+# CONFIG_BOOT_TRACER is not set
+CONFIG_BRANCH_PROFILE_NONE=y
+# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set
+# CONFIG_PROFILE_ALL_BRANCHES is not set
+# CONFIG_KMEMTRACE is not set
+# CONFIG_WORKQUEUE_TRACER is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_RING_BUFFER_BENCHMARK is not set
+# CONFIG_DYNAMIC_DEBUG is not set
 # CONFIG_SAMPLES is not set
 
 #
@@ -1167,19 +1366,30 @@ CONFIG_FRAME_POINTER=y
 #
 # CONFIG_KEYS is not set
 # CONFIG_SECURITY is not set
+# CONFIG_SECURITYFS is not set
 # CONFIG_SECURITY_FILE_CAPABILITIES is not set
 CONFIG_CRYPTO=y
 
 #
 # Crypto core or helper
 #
-CONFIG_CRYPTO_ALGAPI=m
+# CONFIG_CRYPTO_FIPS is not set
+CONFIG_CRYPTO_ALGAPI=y
+CONFIG_CRYPTO_ALGAPI2=y
 CONFIG_CRYPTO_AEAD=m
+CONFIG_CRYPTO_AEAD2=y
 CONFIG_CRYPTO_BLKCIPHER=m
+CONFIG_CRYPTO_BLKCIPHER2=y
 CONFIG_CRYPTO_HASH=m
+CONFIG_CRYPTO_HASH2=y
+CONFIG_CRYPTO_RNG=m
+CONFIG_CRYPTO_RNG2=y
+CONFIG_CRYPTO_PCOMP=y
 CONFIG_CRYPTO_MANAGER=m
+CONFIG_CRYPTO_MANAGER2=y
 # CONFIG_CRYPTO_GF128MUL is not set
 # CONFIG_CRYPTO_NULL is not set
+CONFIG_CRYPTO_WORKQUEUE=y
 # CONFIG_CRYPTO_CRYPTD is not set
 CONFIG_CRYPTO_AUTHENC=m
 # CONFIG_CRYPTO_TEST is not set
@@ -1207,11 +1417,13 @@ CONFIG_CRYPTO_CBC=m
 #
 CONFIG_CRYPTO_HMAC=m
 # CONFIG_CRYPTO_XCBC is not set
+# CONFIG_CRYPTO_VMAC is not set
 
 #
 # Digest
 #
 # CONFIG_CRYPTO_CRC32C is not set
+# CONFIG_CRYPTO_GHASH is not set
 # CONFIG_CRYPTO_MD4 is not set
 CONFIG_CRYPTO_MD5=m
 # CONFIG_CRYPTO_MICHAEL_MIC is not set
@@ -1228,7 +1440,7 @@ CONFIG_CRYPTO_SHA1=m
 #
 # Ciphers
 #
-# CONFIG_CRYPTO_AES is not set
+CONFIG_CRYPTO_AES=m
 # CONFIG_CRYPTO_ANUBIS is not set
 # CONFIG_CRYPTO_ARC4 is not set
 # CONFIG_CRYPTO_BLOWFISH is not set
@@ -1247,18 +1459,24 @@ CONFIG_CRYPTO_DES=m
 #
 # Compression
 #
-CONFIG_CRYPTO_DEFLATE=m
-# CONFIG_CRYPTO_LZO is not set
+CONFIG_CRYPTO_DEFLATE=y
+# CONFIG_CRYPTO_ZLIB is not set
+CONFIG_CRYPTO_LZO=y
+
+#
+# Random Number Generation
+#
+CONFIG_CRYPTO_ANSI_CPRNG=m
 # CONFIG_CRYPTO_HW is not set
+CONFIG_BINARY_PRINTF=y
 
 #
 # Library routines
 #
 CONFIG_BITREVERSE=y
-# CONFIG_GENERIC_FIND_FIRST_BIT is not set
-# CONFIG_GENERIC_FIND_NEXT_BIT is not set
+CONFIG_GENERIC_FIND_LAST_BIT=y
 CONFIG_CRC_CCITT=m
-# CONFIG_CRC16 is not set
+CONFIG_CRC16=y
 CONFIG_CRC_T10DIF=m
 CONFIG_CRC_ITU_T=m
 CONFIG_CRC32=y
@@ -1266,8 +1484,11 @@ CONFIG_CRC7=m
 # CONFIG_LIBCRC32C is not set
 CONFIG_ZLIB_INFLATE=y
 CONFIG_ZLIB_DEFLATE=y
+CONFIG_LZO_COMPRESS=y
+CONFIG_LZO_DECOMPRESS=y
+CONFIG_DECOMPRESS_GZIP=y
 CONFIG_GENERIC_ALLOCATOR=y
-CONFIG_PLIST=y
 CONFIG_HAS_IOMEM=y
 CONFIG_HAS_IOPORT=y
 CONFIG_HAS_DMA=y
+CONFIG_NLATTR=y
diff --git a/arch/avr32/configs/atstk1006_defconfig b/arch/avr32/configs/atstk1006_defconfig
index c1603c4860e0..363e2381f32a 100644
--- a/arch/avr32/configs/atstk1006_defconfig
+++ b/arch/avr32/configs/atstk1006_defconfig
@@ -1,7 +1,7 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.28-rc8
-# Thu Dec 18 11:22:23 2008
+# Linux kernel version: 2.6.32-rc5
+# Thu Oct 29 13:00:25 2009
 #
 CONFIG_AVR32=y
 CONFIG_GENERIC_GPIO=y
@@ -21,6 +21,7 @@ CONFIG_GENERIC_HWEIGHT=y
 CONFIG_GENERIC_CALIBRATE_DELAY=y
 CONFIG_GENERIC_BUG=y
 CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+CONFIG_CONSTRUCTORS=y
 
 #
 # General setup
@@ -34,21 +35,36 @@ CONFIG_SWAP=y
 CONFIG_SYSVIPC=y
 CONFIG_SYSVIPC_SYSCTL=y
 CONFIG_POSIX_MQUEUE=y
+CONFIG_POSIX_MQUEUE_SYSCTL=y
 # CONFIG_BSD_PROCESS_ACCT is not set
 # CONFIG_TASKSTATS is not set
 # CONFIG_AUDIT is not set
+
+#
+# RCU Subsystem
+#
+CONFIG_TREE_RCU=y
+# CONFIG_TREE_PREEMPT_RCU is not set
+# CONFIG_RCU_TRACE is not set
+CONFIG_RCU_FANOUT=32
+# CONFIG_RCU_FANOUT_EXACT is not set
+# CONFIG_TREE_RCU_TRACE is not set
 # CONFIG_IKCONFIG is not set
 CONFIG_LOG_BUF_SHIFT=14
-# CONFIG_CGROUPS is not set
 # CONFIG_GROUP_SCHED is not set
+# CONFIG_CGROUPS is not set
 CONFIG_SYSFS_DEPRECATED=y
 CONFIG_SYSFS_DEPRECATED_V2=y
 CONFIG_RELAY=y
 # CONFIG_NAMESPACES is not set
 CONFIG_BLK_DEV_INITRD=y
 CONFIG_INITRAMFS_SOURCE=""
+CONFIG_RD_GZIP=y
+# CONFIG_RD_BZIP2 is not set
+# CONFIG_RD_LZMA is not set
 CONFIG_CC_OPTIMIZE_FOR_SIZE=y
 CONFIG_SYSCTL=y
+CONFIG_ANON_INODES=y
 CONFIG_EMBEDDED=y
 # CONFIG_SYSCTL_SYSCALL is not set
 CONFIG_KALLSYMS=y
@@ -58,32 +74,40 @@ CONFIG_HOTPLUG=y
 CONFIG_PRINTK=y
 CONFIG_BUG=y
 CONFIG_ELF_CORE=y
-# CONFIG_COMPAT_BRK is not set
 # CONFIG_BASE_FULL is not set
 CONFIG_FUTEX=y
-CONFIG_ANON_INODES=y
 CONFIG_EPOLL=y
 CONFIG_SIGNALFD=y
 CONFIG_TIMERFD=y
 CONFIG_EVENTFD=y
 CONFIG_SHMEM=y
 CONFIG_AIO=y
+
+#
+# Kernel Performance Events And Counters
+#
 CONFIG_VM_EVENT_COUNTERS=y
 CONFIG_SLUB_DEBUG=y
+# CONFIG_COMPAT_BRK is not set
 # CONFIG_SLAB is not set
 CONFIG_SLUB=y
 # CONFIG_SLOB is not set
 CONFIG_PROFILING=y
-# CONFIG_MARKERS is not set
+CONFIG_TRACEPOINTS=y
 CONFIG_OPROFILE=m
 CONFIG_HAVE_OPROFILE=y
 CONFIG_KPROBES=y
 CONFIG_HAVE_KPROBES=y
 CONFIG_HAVE_CLK=y
+
+#
+# GCOV-based kernel profiling
+#
+# CONFIG_GCOV_KERNEL is not set
+# CONFIG_SLOW_WORK is not set
 # CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
 CONFIG_SLABINFO=y
 CONFIG_RT_MUTEXES=y
-# CONFIG_TINY_SHMEM is not set
 CONFIG_BASE_SMALL=1
 CONFIG_MODULES=y
 # CONFIG_MODULE_FORCE_LOAD is not set
@@ -91,11 +115,8 @@ CONFIG_MODULE_UNLOAD=y
 # CONFIG_MODULE_FORCE_UNLOAD is not set
 # CONFIG_MODVERSIONS is not set
 # CONFIG_MODULE_SRCVERSION_ALL is not set
-CONFIG_KMOD=y
 CONFIG_BLOCK=y
-# CONFIG_LBD is not set
-# CONFIG_BLK_DEV_IO_TRACE is not set
-# CONFIG_LSF is not set
+CONFIG_LBDAF=y
 # CONFIG_BLK_DEV_BSG is not set
 # CONFIG_BLK_DEV_INTEGRITY is not set
 
@@ -111,7 +132,6 @@ CONFIG_IOSCHED_CFQ=y
 CONFIG_DEFAULT_CFQ=y
 # CONFIG_DEFAULT_NOOP is not set
 CONFIG_DEFAULT_IOSCHED="cfq"
-CONFIG_CLASSIC_RCU=y
 CONFIG_FREEZER=y
 
 #
@@ -128,8 +148,11 @@ CONFIG_PLATFORM_AT32AP=y
 CONFIG_CPU_AT32AP700X=y
 CONFIG_CPU_AT32AP7000=y
 CONFIG_BOARD_ATSTK1000=y
-# CONFIG_BOARD_ATNGW100 is not set
+# CONFIG_BOARD_ATNGW100_MKI is not set
+# CONFIG_BOARD_ATNGW100_MKII is not set
+# CONFIG_BOARD_HAMMERHEAD is not set
 # CONFIG_BOARD_FAVR_32 is not set
+# CONFIG_BOARD_MERISC is not set
 # CONFIG_BOARD_MIMC200 is not set
 # CONFIG_BOARD_ATSTK1002 is not set
 # CONFIG_BOARD_ATSTK1003 is not set
@@ -156,7 +179,7 @@ CONFIG_PREEMPT_NONE=y
 # CONFIG_PREEMPT_VOLUNTARY is not set
 # CONFIG_PREEMPT is not set
 CONFIG_QUICKLIST=y
-# CONFIG_HAVE_ARCH_BOOTMEM_NODE is not set
+# CONFIG_HAVE_ARCH_BOOTMEM is not set
 # CONFIG_ARCH_HAVE_MEMORY_PRESENT is not set
 # CONFIG_NEED_NODE_MEMMAP_SIZE is not set
 CONFIG_ARCH_FLATMEM_ENABLE=y
@@ -170,12 +193,14 @@ CONFIG_FLATMEM=y
 CONFIG_FLAT_NODE_MEM_MAP=y
 CONFIG_PAGEFLAGS_EXTENDED=y
 CONFIG_SPLIT_PTLOCK_CPUS=4
-# CONFIG_RESOURCES_64BIT is not set
 # CONFIG_PHYS_ADDR_T_64BIT is not set
 CONFIG_ZONE_DMA_FLAG=0
 CONFIG_NR_QUICK=2
 CONFIG_VIRT_TO_BUS=y
-CONFIG_UNEVICTABLE_LRU=y
+CONFIG_HAVE_MLOCK=y
+CONFIG_HAVE_MLOCKED_PAGE_BIT=y
+# CONFIG_KSM is not set
+CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
 # CONFIG_OWNERSHIP_TRACE is not set
 CONFIG_NMI_DEBUGGING=y
 # CONFIG_HZ_100 is not set
@@ -194,6 +219,7 @@ CONFIG_PM=y
 CONFIG_PM_SLEEP=y
 CONFIG_SUSPEND=y
 CONFIG_SUSPEND_FREEZER=y
+# CONFIG_PM_RUNTIME is not set
 CONFIG_ARCH_SUSPEND_POSSIBLE=y
 
 #
@@ -294,6 +320,7 @@ CONFIG_IPV6_TUNNEL=m
 # CONFIG_NETFILTER is not set
 # CONFIG_IP_DCCP is not set
 # CONFIG_IP_SCTP is not set
+# CONFIG_RDS is not set
 # CONFIG_TIPC is not set
 # CONFIG_ATM is not set
 CONFIG_STP=m
@@ -309,20 +336,24 @@ CONFIG_LLC=m
 # CONFIG_LAPB is not set
 # CONFIG_ECONET is not set
 # CONFIG_WAN_ROUTER is not set
+# CONFIG_PHONET is not set
+# CONFIG_IEEE802154 is not set
 # CONFIG_NET_SCHED is not set
+# CONFIG_DCB is not set
 
 #
 # Network testing
 #
 # CONFIG_NET_PKTGEN is not set
 # CONFIG_NET_TCPPROBE is not set
+# CONFIG_NET_DROP_MONITOR is not set
 # CONFIG_HAMRADIO is not set
 # CONFIG_CAN is not set
 # CONFIG_IRDA is not set
 # CONFIG_BT is not set
 # CONFIG_AF_RXRPC is not set
-# CONFIG_PHONET is not set
 # CONFIG_WIRELESS is not set
+# CONFIG_WIMAX is not set
 # CONFIG_RFKILL is not set
 # CONFIG_NET_9P is not set
 
@@ -334,6 +365,7 @@ CONFIG_LLC=m
 # Generic Driver Options
 #
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+# CONFIG_DEVTMPFS is not set
 CONFIG_STANDALONE=y
 # CONFIG_PREVENT_FIRMWARE_BUILD is not set
 # CONFIG_FW_LOADER is not set
@@ -343,6 +375,7 @@ CONFIG_STANDALONE=y
 # CONFIG_CONNECTOR is not set
 CONFIG_MTD=y
 # CONFIG_MTD_DEBUG is not set
+# CONFIG_MTD_TESTS is not set
 # CONFIG_MTD_CONCAT is not set
 CONFIG_MTD_PARTITIONS=y
 # CONFIG_MTD_REDBOOT_PARTS is not set
@@ -393,9 +426,7 @@ CONFIG_MTD_CFI_UTIL=y
 #
 # CONFIG_MTD_COMPLEX_MAPPINGS is not set
 CONFIG_MTD_PHYSMAP=y
-CONFIG_MTD_PHYSMAP_START=0x8000000
-CONFIG_MTD_PHYSMAP_LEN=0x0
-CONFIG_MTD_PHYSMAP_BANKWIDTH=2
+# CONFIG_MTD_PHYSMAP_COMPAT is not set
 # CONFIG_MTD_PLATRAM is not set
 
 #
@@ -406,6 +437,7 @@ CONFIG_MTD_DATAFLASH=m
 CONFIG_MTD_DATAFLASH_OTP=y
 CONFIG_MTD_M25P80=m
 CONFIG_M25PXX_USE_FAST_READ=y
+# CONFIG_MTD_SST25L is not set
 # CONFIG_MTD_SLRAM is not set
 # CONFIG_MTD_PHRAM is not set
 # CONFIG_MTD_MTDRAM is not set
@@ -432,6 +464,11 @@ CONFIG_MTD_NAND_ATMEL_ECC_HW=y
 # CONFIG_MTD_ONENAND is not set
 
 #
+# LPDDR flash memory drivers
+#
+# CONFIG_MTD_LPDDR is not set
+
+#
 # UBI - Unsorted block images
 #
 CONFIG_MTD_UBI=y
@@ -460,13 +497,22 @@ CONFIG_ATMEL_PWM=m
 CONFIG_ATMEL_TCLIB=y
 CONFIG_ATMEL_TCB_CLKSRC=y
 CONFIG_ATMEL_TCB_CLKSRC_BLOCK=0
-# CONFIG_EEPROM_93CX6 is not set
 # CONFIG_ICS932S401 is not set
 CONFIG_ATMEL_SSC=m
 # CONFIG_ENCLOSURE_SERVICES is not set
+# CONFIG_ISL29003 is not set
 # CONFIG_C2PORT is not set
 
 #
+# EEPROM support
+#
+# CONFIG_EEPROM_AT24 is not set
+# CONFIG_EEPROM_AT25 is not set
+# CONFIG_EEPROM_LEGACY is not set
+# CONFIG_EEPROM_MAX6875 is not set
+# CONFIG_EEPROM_93CX6 is not set
+
+#
 # SCSI device support
 #
 # CONFIG_RAID_ATTRS is not set
@@ -486,10 +532,6 @@ CONFIG_BLK_DEV_SR=m
 # CONFIG_BLK_DEV_SR_VENDOR is not set
 # CONFIG_CHR_DEV_SG is not set
 # CONFIG_CHR_DEV_SCH is not set
-
-#
-# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
-#
 # CONFIG_SCSI_MULTI_LUN is not set
 # CONFIG_SCSI_CONSTANTS is not set
 # CONFIG_SCSI_LOGGING is not set
@@ -506,8 +548,10 @@ CONFIG_SCSI_WAIT_SCAN=m
 # CONFIG_SCSI_SRP_ATTRS is not set
 # CONFIG_SCSI_LOWLEVEL is not set
 # CONFIG_SCSI_DH is not set
+# CONFIG_SCSI_OSD_INITIATOR is not set
 CONFIG_ATA=m
 # CONFIG_ATA_NONSTANDARD is not set
+CONFIG_ATA_VERBOSE_ERROR=y
 # CONFIG_SATA_PMP is not set
 CONFIG_ATA_SFF=y
 # CONFIG_SATA_MV is not set
@@ -536,12 +580,17 @@ CONFIG_PHYLIB=y
 # CONFIG_BROADCOM_PHY is not set
 # CONFIG_ICPLUS_PHY is not set
 # CONFIG_REALTEK_PHY is not set
+# CONFIG_NATIONAL_PHY is not set
+# CONFIG_STE10XP is not set
+# CONFIG_LSI_ET1011C_PHY is not set
 # CONFIG_FIXED_PHY is not set
 # CONFIG_MDIO_BITBANG is not set
 CONFIG_NET_ETHERNET=y
 # CONFIG_MII is not set
 CONFIG_MACB=y
 # CONFIG_ENC28J60 is not set
+# CONFIG_ETHOC is not set
+# CONFIG_DNET is not set
 # CONFIG_IBM_NEW_EMAC_ZMII is not set
 # CONFIG_IBM_NEW_EMAC_RGMII is not set
 # CONFIG_IBM_NEW_EMAC_TAH is not set
@@ -550,15 +599,18 @@ CONFIG_MACB=y
 # CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
 # CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
 # CONFIG_B44 is not set
+# CONFIG_KS8842 is not set
+# CONFIG_KS8851 is not set
+# CONFIG_KS8851_MLL is not set
 # CONFIG_NETDEV_1000 is not set
 # CONFIG_NETDEV_10000 is not set
+CONFIG_WLAN=y
+# CONFIG_WLAN_PRE80211 is not set
+# CONFIG_WLAN_80211 is not set
 
 #
-# Wireless LAN
+# Enable WiMAX (Networking options) to see the WiMAX drivers
 #
-# CONFIG_WLAN_PRE80211 is not set
-# CONFIG_WLAN_80211 is not set
-# CONFIG_IWLWIFI_LEDS is not set
 # CONFIG_WAN is not set
 CONFIG_PPP=m
 # CONFIG_PPP_MULTILINK is not set
@@ -600,18 +652,25 @@ CONFIG_INPUT_EVDEV=m
 # Input Device Drivers
 #
 CONFIG_INPUT_KEYBOARD=y
+# CONFIG_KEYBOARD_ADP5588 is not set
 # CONFIG_KEYBOARD_ATKBD is not set
-# CONFIG_KEYBOARD_SUNKBD is not set
+# CONFIG_QT2160 is not set
 # CONFIG_KEYBOARD_LKKBD is not set
-# CONFIG_KEYBOARD_XTKBD is not set
+CONFIG_KEYBOARD_GPIO=m
+# CONFIG_KEYBOARD_MATRIX is not set
+# CONFIG_KEYBOARD_LM8323 is not set
+# CONFIG_KEYBOARD_MAX7359 is not set
 # CONFIG_KEYBOARD_NEWTON is not set
+# CONFIG_KEYBOARD_OPENCORES is not set
 # CONFIG_KEYBOARD_STOWAWAY is not set
-CONFIG_KEYBOARD_GPIO=m
+# CONFIG_KEYBOARD_SUNKBD is not set
+# CONFIG_KEYBOARD_XTKBD is not set
 CONFIG_INPUT_MOUSE=y
 # CONFIG_MOUSE_PS2 is not set
 # CONFIG_MOUSE_SERIAL is not set
 # CONFIG_MOUSE_VSXXXAA is not set
 CONFIG_MOUSE_GPIO=m
+# CONFIG_MOUSE_SYNAPTICS_I2C is not set
 # CONFIG_INPUT_JOYSTICK is not set
 # CONFIG_INPUT_TABLET is not set
 # CONFIG_INPUT_TOUCHSCREEN is not set
@@ -642,9 +701,11 @@ CONFIG_SERIAL_ATMEL=y
 CONFIG_SERIAL_ATMEL_CONSOLE=y
 CONFIG_SERIAL_ATMEL_PDC=y
 # CONFIG_SERIAL_ATMEL_TTYAT is not set
+# CONFIG_SERIAL_MAX3100 is not set
 CONFIG_SERIAL_CORE=y
 CONFIG_SERIAL_CORE_CONSOLE=y
 CONFIG_UNIX98_PTYS=y
+# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
 # CONFIG_LEGACY_PTYS is not set
 # CONFIG_IPMI_HANDLER is not set
 # CONFIG_HW_RANDOM is not set
@@ -653,6 +714,7 @@ CONFIG_UNIX98_PTYS=y
 # CONFIG_TCG_TPM is not set
 CONFIG_I2C=m
 CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_COMPAT=y
 CONFIG_I2C_CHARDEV=m
 CONFIG_I2C_HELPER_AUTO=y
 CONFIG_I2C_ALGOBIT=m
@@ -664,6 +726,7 @@ CONFIG_I2C_ALGOBIT=m
 #
 # I2C system bus drivers (mostly embedded / system-on-chip)
 #
+# CONFIG_I2C_DESIGNWARE is not set
 CONFIG_I2C_GPIO=m
 # CONFIG_I2C_OCORES is not set
 # CONFIG_I2C_SIMTEC is not set
@@ -684,14 +747,6 @@ CONFIG_I2C_GPIO=m
 # Miscellaneous I2C Chip support
 #
 # CONFIG_DS1682 is not set
-# CONFIG_EEPROM_AT24 is not set
-# CONFIG_EEPROM_LEGACY is not set
-# CONFIG_SENSORS_PCF8574 is not set
-# CONFIG_PCF8575 is not set
-# CONFIG_SENSORS_PCA9539 is not set
-# CONFIG_SENSORS_PCF8591 is not set
-# CONFIG_TPS65010 is not set
-# CONFIG_SENSORS_MAX6875 is not set
 # CONFIG_SENSORS_TSL2550 is not set
 # CONFIG_I2C_DEBUG_CORE is not set
 # CONFIG_I2C_DEBUG_ALGO is not set
@@ -706,13 +761,18 @@ CONFIG_SPI_MASTER=y
 #
 CONFIG_SPI_ATMEL=y
 # CONFIG_SPI_BITBANG is not set
+# CONFIG_SPI_GPIO is not set
 
 #
 # SPI Protocol Masters
 #
-# CONFIG_EEPROM_AT25 is not set
 CONFIG_SPI_SPIDEV=m
 # CONFIG_SPI_TLE62X0 is not set
+
+#
+# PPS support
+#
+# CONFIG_PPS is not set
 CONFIG_ARCH_REQUIRE_GPIOLIB=y
 CONFIG_GPIOLIB=y
 # CONFIG_DEBUG_GPIO is not set
@@ -738,11 +798,15 @@ CONFIG_GPIO_SYSFS=y
 #
 # CONFIG_GPIO_MAX7301 is not set
 # CONFIG_GPIO_MCP23S08 is not set
+# CONFIG_GPIO_MC33880 is not set
+
+#
+# AC97 GPIO expanders:
+#
 # CONFIG_W1 is not set
 # CONFIG_POWER_SUPPLY is not set
 # CONFIG_HWMON is not set
 # CONFIG_THERMAL is not set
-# CONFIG_THERMAL_HWMON is not set
 CONFIG_WATCHDOG=y
 # CONFIG_WATCHDOG_NOWAYOUT is not set
 
@@ -764,26 +828,17 @@ CONFIG_SSB_POSSIBLE=y
 # CONFIG_MFD_CORE is not set
 # CONFIG_MFD_SM501 is not set
 # CONFIG_HTC_PASIC3 is not set
+# CONFIG_TPS65010 is not set
 # CONFIG_MFD_TMIO is not set
 # CONFIG_MFD_WM8400 is not set
+# CONFIG_MFD_WM831X is not set
 # CONFIG_MFD_WM8350_I2C is not set
+# CONFIG_MFD_PCF50633 is not set
+# CONFIG_MFD_MC13783 is not set
+# CONFIG_AB3100_CORE is not set
+# CONFIG_EZX_PCAP is not set
 # CONFIG_REGULATOR is not set
-
-#
-# Multimedia devices
-#
-
-#
-# Multimedia core support
-#
-# CONFIG_VIDEO_DEV is not set
-# CONFIG_DVB_CORE is not set
-# CONFIG_VIDEO_MEDIA is not set
-
-#
-# Multimedia drivers
-#
-# CONFIG_DAB is not set
+# CONFIG_MEDIA_SUPPORT is not set
 
 #
 # Graphics support
@@ -817,8 +872,10 @@ CONFIG_FB_ATMEL=y
 # CONFIG_FB_VIRTUAL is not set
 # CONFIG_FB_METRONOME is not set
 # CONFIG_FB_MB862XX is not set
+# CONFIG_FB_BROADSHEET is not set
 CONFIG_BACKLIGHT_LCD_SUPPORT=y
 CONFIG_LCD_CLASS_DEVICE=y
+# CONFIG_LCD_LMS283GF05 is not set
 CONFIG_LCD_LTV350QV=y
 # CONFIG_LCD_ILI9320 is not set
 # CONFIG_LCD_TDO24M is not set
@@ -833,6 +890,7 @@ CONFIG_LCD_LTV350QV=y
 # CONFIG_LOGO is not set
 CONFIG_SOUND=m
 CONFIG_SOUND_OSS_CORE=y
+CONFIG_SOUND_OSS_CORE_PRECLAIM=y
 CONFIG_SND=m
 CONFIG_SND_TIMER=m
 CONFIG_SND_PCM=m
@@ -841,16 +899,28 @@ CONFIG_SND_OSSEMUL=y
 CONFIG_SND_MIXER_OSS=m
 CONFIG_SND_PCM_OSS=m
 CONFIG_SND_PCM_OSS_PLUGINS=y
+# CONFIG_SND_HRTIMER is not set
 # CONFIG_SND_DYNAMIC_MINORS is not set
 # CONFIG_SND_SUPPORT_OLD_API is not set
 # CONFIG_SND_VERBOSE_PROCFS is not set
 # CONFIG_SND_VERBOSE_PRINTK is not set
 # CONFIG_SND_DEBUG is not set
+# CONFIG_SND_RAWMIDI_SEQ is not set
+# CONFIG_SND_OPL3_LIB_SEQ is not set
+# CONFIG_SND_OPL4_LIB_SEQ is not set
+# CONFIG_SND_SBAWE_SEQ is not set
+# CONFIG_SND_EMU10K1_SEQ is not set
 CONFIG_SND_DRIVERS=y
 # CONFIG_SND_DUMMY is not set
 # CONFIG_SND_MTPAV is not set
 # CONFIG_SND_SERIAL_U16550 is not set
 # CONFIG_SND_MPU401 is not set
+
+#
+# Atmel devices (AVR32 and AT91)
+#
+# CONFIG_SND_ATMEL_ABDAC is not set
+# CONFIG_SND_ATMEL_AC97C is not set
 CONFIG_SND_SPI=y
 CONFIG_SND_AT73C213=m
 CONFIG_SND_AT73C213_TARGET_BITRATE=48000
@@ -863,11 +933,10 @@ CONFIG_USB_SUPPORT=y
 # CONFIG_USB_ARCH_HAS_EHCI is not set
 # CONFIG_USB_OTG_WHITELIST is not set
 # CONFIG_USB_OTG_BLACKLIST_HUB is not set
-# CONFIG_USB_MUSB_HDRC is not set
 # CONFIG_USB_GADGET_MUSB_HDRC is not set
 
 #
-# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may also be needed;
+# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
 #
 CONFIG_USB_GADGET=y
 # CONFIG_USB_GADGET_DEBUG is not set
@@ -882,18 +951,25 @@ CONFIG_USB_ATMEL_USBA=y
 # CONFIG_USB_GADGET_LH7A40X is not set
 # CONFIG_USB_GADGET_OMAP is not set
 # CONFIG_USB_GADGET_PXA25X is not set
+# CONFIG_USB_GADGET_R8A66597 is not set
 # CONFIG_USB_GADGET_PXA27X is not set
+# CONFIG_USB_GADGET_S3C_HSOTG is not set
+# CONFIG_USB_GADGET_IMX is not set
 # CONFIG_USB_GADGET_S3C2410 is not set
 # CONFIG_USB_GADGET_M66592 is not set
 # CONFIG_USB_GADGET_AMD5536UDC is not set
 # CONFIG_USB_GADGET_FSL_QE is not set
+# CONFIG_USB_GADGET_CI13XXX is not set
 # CONFIG_USB_GADGET_NET2280 is not set
 # CONFIG_USB_GADGET_GOKU is not set
+# CONFIG_USB_GADGET_LANGWELL is not set
 # CONFIG_USB_GADGET_DUMMY_HCD is not set
 CONFIG_USB_GADGET_DUALSPEED=y
 CONFIG_USB_ZERO=m
+# CONFIG_USB_AUDIO is not set
 CONFIG_USB_ETH=m
 CONFIG_USB_ETH_RNDIS=y
+# CONFIG_USB_ETH_EEM is not set
 CONFIG_USB_GADGETFS=m
 CONFIG_USB_FILE_STORAGE=m
 # CONFIG_USB_FILE_STORAGE_TEST is not set
@@ -901,6 +977,12 @@ CONFIG_USB_G_SERIAL=m
 # CONFIG_USB_MIDI_GADGET is not set
 # CONFIG_USB_G_PRINTER is not set
 # CONFIG_USB_CDC_COMPOSITE is not set
+
+#
+# OTG and related infrastructure
+#
+# CONFIG_USB_GPIO_VBUS is not set
+# CONFIG_NOP_USB_XCEIV is not set
 CONFIG_MMC=y
 # CONFIG_MMC_DEBUG is not set
 # CONFIG_MMC_UNSAFE_RESUME is not set
@@ -917,6 +999,7 @@ CONFIG_MMC_BLOCK_BOUNCE=y
 # MMC/SD/SDIO Host Controller Drivers
 #
 # CONFIG_MMC_SDHCI is not set
+# CONFIG_MMC_AT91 is not set
 CONFIG_MMC_ATMELMCI=y
 # CONFIG_MMC_ATMELMCI_DMA is not set
 CONFIG_MMC_SPI=m
@@ -930,7 +1013,11 @@ CONFIG_LEDS_CLASS=m
 CONFIG_LEDS_ATMEL_PWM=m
 # CONFIG_LEDS_PCA9532 is not set
 CONFIG_LEDS_GPIO=m
+CONFIG_LEDS_GPIO_PLATFORM=y
+# CONFIG_LEDS_LP3944 is not set
 # CONFIG_LEDS_PCA955X is not set
+# CONFIG_LEDS_DAC124S085 is not set
+# CONFIG_LEDS_BD2802 is not set
 
 #
 # LED Triggers
@@ -939,7 +1026,12 @@ CONFIG_LEDS_TRIGGERS=y
 CONFIG_LEDS_TRIGGER_TIMER=m
 CONFIG_LEDS_TRIGGER_HEARTBEAT=m
 # CONFIG_LEDS_TRIGGER_BACKLIGHT is not set
+# CONFIG_LEDS_TRIGGER_GPIO is not set
 CONFIG_LEDS_TRIGGER_DEFAULT_ON=m
+
+#
+# iptables trigger is under Netfilter config (LED target)
+#
 # CONFIG_ACCESSIBILITY is not set
 CONFIG_RTC_LIB=y
 CONFIG_RTC_CLASS=y
@@ -972,6 +1064,7 @@ CONFIG_RTC_INTF_DEV=y
 # CONFIG_RTC_DRV_S35390A is not set
 # CONFIG_RTC_DRV_FM3130 is not set
 # CONFIG_RTC_DRV_RX8581 is not set
+# CONFIG_RTC_DRV_RX8025 is not set
 
 #
 # SPI RTC drivers
@@ -983,6 +1076,7 @@ CONFIG_RTC_INTF_DEV=y
 # CONFIG_RTC_DRV_R9701 is not set
 # CONFIG_RTC_DRV_RS5C348 is not set
 # CONFIG_RTC_DRV_DS3234 is not set
+# CONFIG_RTC_DRV_PCF2123 is not set
 
 #
 # Platform RTC drivers
@@ -1014,32 +1108,42 @@ CONFIG_DMA_ENGINE=y
 # DMA Clients
 #
 # CONFIG_NET_DMA is not set
+# CONFIG_ASYNC_TX_DMA is not set
 # CONFIG_DMATEST is not set
+# CONFIG_AUXDISPLAY is not set
 # CONFIG_UIO is not set
+
+#
+# TI VLYNQ
+#
 # CONFIG_STAGING is not set
-CONFIG_STAGING_EXCLUDE_BUILD=y
 
 #
 # File systems
 #
-CONFIG_EXT2_FS=m
+CONFIG_EXT2_FS=y
 # CONFIG_EXT2_FS_XATTR is not set
 # CONFIG_EXT2_FS_XIP is not set
-CONFIG_EXT3_FS=m
+CONFIG_EXT3_FS=y
+# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
 # CONFIG_EXT3_FS_XATTR is not set
-CONFIG_EXT4_FS=m
-CONFIG_EXT4DEV_COMPAT=y
+CONFIG_EXT4_FS=y
 # CONFIG_EXT4_FS_XATTR is not set
-CONFIG_JBD=m
+# CONFIG_EXT4_DEBUG is not set
+CONFIG_JBD=y
 # CONFIG_JBD_DEBUG is not set
-CONFIG_JBD2=m
+CONFIG_JBD2=y
 # CONFIG_JBD2_DEBUG is not set
 # CONFIG_REISERFS_FS is not set
 # CONFIG_JFS_FS is not set
 # CONFIG_FS_POSIX_ACL is not set
-CONFIG_FILE_LOCKING=y
 # CONFIG_XFS_FS is not set
+# CONFIG_GFS2_FS is not set
 # CONFIG_OCFS2_FS is not set
+# CONFIG_BTRFS_FS is not set
+# CONFIG_NILFS2_FS is not set
+CONFIG_FILE_LOCKING=y
+CONFIG_FSNOTIFY=y
 # CONFIG_DNOTIFY is not set
 CONFIG_INOTIFY=y
 CONFIG_INOTIFY_USER=y
@@ -1047,6 +1151,12 @@ CONFIG_INOTIFY_USER=y
 # CONFIG_AUTOFS_FS is not set
 # CONFIG_AUTOFS4_FS is not set
 CONFIG_FUSE_FS=m
+# CONFIG_CUSE is not set
+
+#
+# Caches
+#
+# CONFIG_FSCACHE is not set
 
 #
 # CD-ROM/DVD Filesystems
@@ -1076,10 +1186,7 @@ CONFIG_TMPFS=y
 # CONFIG_TMPFS_POSIX_ACL is not set
 # CONFIG_HUGETLB_PAGE is not set
 # CONFIG_CONFIGFS_FS is not set
-
-#
-# Miscellaneous filesystems
-#
+CONFIG_MISC_FILESYSTEMS=y
 # CONFIG_ADFS_FS is not set
 # CONFIG_AFFS_FS is not set
 # CONFIG_HFS_FS is not set
@@ -1099,12 +1206,13 @@ CONFIG_JFFS2_ZLIB=y
 CONFIG_JFFS2_RTIME=y
 # CONFIG_JFFS2_RUBIN is not set
 CONFIG_UBIFS_FS=y
-CONFIG_UBIFS_FS_XATTR=y
+# CONFIG_UBIFS_FS_XATTR is not set
 # CONFIG_UBIFS_FS_ADVANCED_COMPR is not set
 CONFIG_UBIFS_FS_LZO=y
 CONFIG_UBIFS_FS_ZLIB=y
 # CONFIG_UBIFS_FS_DEBUG is not set
 # CONFIG_CRAMFS is not set
+# CONFIG_SQUASHFS is not set
 # CONFIG_VXFS_FS is not set
 CONFIG_MINIX_FS=m
 # CONFIG_OMFS_FS is not set
@@ -1124,7 +1232,6 @@ CONFIG_LOCKD=y
 CONFIG_LOCKD_V4=y
 CONFIG_NFS_COMMON=y
 CONFIG_SUNRPC=y
-# CONFIG_SUNRPC_REGISTER_V4 is not set
 # CONFIG_RPCSEC_GSS_KRB5 is not set
 # CONFIG_RPCSEC_GSS_SPKM3 is not set
 # CONFIG_SMB_FS is not set
@@ -1188,6 +1295,7 @@ CONFIG_ENABLE_WARN_DEPRECATED=y
 CONFIG_ENABLE_MUST_CHECK=y
 CONFIG_FRAME_WARN=1024
 CONFIG_MAGIC_SYSRQ=y
+# CONFIG_STRIP_ASM_SYMS is not set
 # CONFIG_UNUSED_SYMBOLS is not set
 CONFIG_DEBUG_FS=y
 # CONFIG_HEADERS_CHECK is not set
@@ -1196,6 +1304,9 @@ CONFIG_DEBUG_KERNEL=y
 CONFIG_DETECT_SOFTLOCKUP=y
 # CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
 CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
+CONFIG_DETECT_HUNG_TASK=y
+# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set
+CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0
 CONFIG_SCHED_DEBUG=y
 # CONFIG_SCHEDSTATS is not set
 # CONFIG_TIMER_STATS is not set
@@ -1211,6 +1322,7 @@ CONFIG_SCHED_DEBUG=y
 # CONFIG_LOCK_STAT is not set
 # CONFIG_DEBUG_SPINLOCK_SLEEP is not set
 # CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+CONFIG_STACKTRACE=y
 # CONFIG_DEBUG_KOBJECT is not set
 CONFIG_DEBUG_BUGVERBOSE=y
 # CONFIG_DEBUG_INFO is not set
@@ -1219,6 +1331,8 @@ CONFIG_DEBUG_BUGVERBOSE=y
 # CONFIG_DEBUG_MEMORY_INIT is not set
 # CONFIG_DEBUG_LIST is not set
 # CONFIG_DEBUG_SG is not set
+# CONFIG_DEBUG_NOTIFIERS is not set
+# CONFIG_DEBUG_CREDENTIALS is not set
 CONFIG_FRAME_POINTER=y
 # CONFIG_BOOT_PRINTK_DELAY is not set
 # CONFIG_RCU_TORTURE_TEST is not set
@@ -1226,17 +1340,30 @@ CONFIG_FRAME_POINTER=y
 # CONFIG_KPROBES_SANITY_TEST is not set
 # CONFIG_BACKTRACE_SELF_TEST is not set
 # CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
+# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
 # CONFIG_LKDTM is not set
 # CONFIG_FAULT_INJECTION is not set
-
-#
-# Tracers
-#
+# CONFIG_PAGE_POISONING is not set
+CONFIG_NOP_TRACER=y
+CONFIG_RING_BUFFER=y
+CONFIG_EVENT_TRACING=y
+CONFIG_CONTEXT_SWITCH_TRACER=y
+CONFIG_RING_BUFFER_ALLOW_SWAP=y
+CONFIG_TRACING=y
+CONFIG_TRACING_SUPPORT=y
+CONFIG_FTRACE=y
 # CONFIG_IRQSOFF_TRACER is not set
 # CONFIG_SCHED_TRACER is not set
-# CONFIG_CONTEXT_SWITCH_TRACER is not set
+# CONFIG_ENABLE_DEFAULT_TRACERS is not set
 # CONFIG_BOOT_TRACER is not set
-# CONFIG_DYNAMIC_PRINTK_DEBUG is not set
+CONFIG_BRANCH_PROFILE_NONE=y
+# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set
+# CONFIG_PROFILE_ALL_BRANCHES is not set
+# CONFIG_KMEMTRACE is not set
+# CONFIG_WORKQUEUE_TRACER is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_RING_BUFFER_BENCHMARK is not set
+# CONFIG_DYNAMIC_DEBUG is not set
 # CONFIG_SAMPLES is not set
 
 #
@@ -1262,10 +1389,12 @@ CONFIG_CRYPTO_HASH=m
 CONFIG_CRYPTO_HASH2=y
 CONFIG_CRYPTO_RNG=m
 CONFIG_CRYPTO_RNG2=y
+CONFIG_CRYPTO_PCOMP=y
 CONFIG_CRYPTO_MANAGER=m
 CONFIG_CRYPTO_MANAGER2=y
 # CONFIG_CRYPTO_GF128MUL is not set
 # CONFIG_CRYPTO_NULL is not set
+CONFIG_CRYPTO_WORKQUEUE=y
 # CONFIG_CRYPTO_CRYPTD is not set
 CONFIG_CRYPTO_AUTHENC=m
 # CONFIG_CRYPTO_TEST is not set
@@ -1293,11 +1422,13 @@ CONFIG_CRYPTO_CBC=m
 #
 CONFIG_CRYPTO_HMAC=m
 # CONFIG_CRYPTO_XCBC is not set
+# CONFIG_CRYPTO_VMAC is not set
 
 #
 # Digest
 #
 # CONFIG_CRYPTO_CRC32C is not set
+# CONFIG_CRYPTO_GHASH is not set
 # CONFIG_CRYPTO_MD4 is not set
 CONFIG_CRYPTO_MD5=m
 # CONFIG_CRYPTO_MICHAEL_MIC is not set
@@ -1334,6 +1465,7 @@ CONFIG_CRYPTO_DES=m
 # Compression
 #
 CONFIG_CRYPTO_DEFLATE=y
+# CONFIG_CRYPTO_ZLIB is not set
 CONFIG_CRYPTO_LZO=y
 
 #
@@ -1341,11 +1473,13 @@ CONFIG_CRYPTO_LZO=y
 #
 CONFIG_CRYPTO_ANSI_CPRNG=m
 # CONFIG_CRYPTO_HW is not set
+CONFIG_BINARY_PRINTF=y
 
 #
 # Library routines
 #
 CONFIG_BITREVERSE=y
+CONFIG_GENERIC_FIND_LAST_BIT=y
 CONFIG_CRC_CCITT=m
 CONFIG_CRC16=y
 CONFIG_CRC_T10DIF=m
@@ -1357,8 +1491,9 @@ CONFIG_ZLIB_INFLATE=y
 CONFIG_ZLIB_DEFLATE=y
 CONFIG_LZO_COMPRESS=y
 CONFIG_LZO_DECOMPRESS=y
+CONFIG_DECOMPRESS_GZIP=y
 CONFIG_GENERIC_ALLOCATOR=y
-CONFIG_PLIST=y
 CONFIG_HAS_IOMEM=y
 CONFIG_HAS_IOPORT=y
 CONFIG_HAS_DMA=y
+CONFIG_NLATTR=y
diff --git a/arch/avr32/include/asm/asm-offsets.h b/arch/avr32/include/asm/asm-offsets.h
new file mode 100644
index 000000000000..d370ee36a182
--- /dev/null
+++ b/arch/avr32/include/asm/asm-offsets.h
@@ -0,0 +1 @@
+#include <generated/asm-offsets.h>
diff --git a/arch/avr32/include/asm/elf.h b/arch/avr32/include/asm/elf.h
index d5d1d41c600a..3b3159b710d4 100644
--- a/arch/avr32/include/asm/elf.h
+++ b/arch/avr32/include/asm/elf.h
@@ -77,7 +77,6 @@ typedef struct user_fpu_struct elf_fpregset_t;
 #endif
 #define ELF_ARCH        EM_AVR32
 
-#define USE_ELF_CORE_DUMP
 #define ELF_EXEC_PAGESIZE       4096
 
 /* This is the location that an ET_DYN program is loaded if exec'ed.  Typical
diff --git a/arch/avr32/include/asm/hardirq.h b/arch/avr32/include/asm/hardirq.h
index 015bc75ea798..9e36e3ff77d2 100644
--- a/arch/avr32/include/asm/hardirq.h
+++ b/arch/avr32/include/asm/hardirq.h
@@ -1,23 +1,6 @@
 #ifndef __ASM_AVR32_HARDIRQ_H
 #define __ASM_AVR32_HARDIRQ_H
-
-#include <linux/threads.h>
-#include <asm/irq.h>
-
 #ifndef __ASSEMBLY__
-
-#include <linux/cache.h>
-
-/* entry.S is sensitive to the offsets of these fields */
-typedef struct {
-        unsigned int __softirq_pending;
-} ____cacheline_aligned irq_cpustat_t;
-
-void ack_bad_irq(unsigned int irq);
-
-/* Standard mappings for irq_cpustat_t above */
-#include <linux/irq_cpustat.h>
-
+#include <asm-generic/hardirq.h>
 #endif /* __ASSEMBLY__ */
-
 #endif /* __ASM_AVR32_HARDIRQ_H */
diff --git a/arch/avr32/include/asm/syscalls.h b/arch/avr32/include/asm/syscalls.h
index 483d666c27c0..66a197266637 100644
--- a/arch/avr32/include/asm/syscalls.h
+++ b/arch/avr32/include/asm/syscalls.h
@@ -29,10 +29,6 @@ asmlinkage int sys_sigaltstack(const stack_t __user *, stack_t __user *,
                                struct pt_regs *);
 asmlinkage int sys_rt_sigreturn(struct pt_regs *);
 
-/* kernel/sys_avr32.c */
-asmlinkage long sys_mmap2(unsigned long, unsigned long, unsigned long,
-                          unsigned long, unsigned long, off_t);
-
 /* mm/cache.c */
 asmlinkage int sys_cacheflush(int, void __user *, size_t);
 
diff --git a/arch/avr32/kernel/irq.c b/arch/avr32/kernel/irq.c
index 9f572229d318..9604f7758f9a 100644
--- a/arch/avr32/kernel/irq.c
+++ b/arch/avr32/kernel/irq.c
@@ -16,15 +16,6 @@
 #include <linux/seq_file.h>
 #include <linux/sysdev.h>
 
-/*
- * 'what should we do if we get a hw irq event on an illegal vector'.
- * each architecture has to answer this themselves.
- */
-void ack_bad_irq(unsigned int irq)
-{
-        printk("unexpected IRQ %u\n", irq);
-}
-
 /* May be overridden by platform code */
 int __weak nmi_enable(void)
 {
@@ -51,7 +42,7 @@ int show_interrupts(struct seq_file *p, void *v)
         }
 
         if (i < NR_IRQS) {
-                spin_lock_irqsave(&irq_desc[i].lock, flags);
+                raw_spin_lock_irqsave(&irq_desc[i].lock, flags);
                 action = irq_desc[i].action;
                 if (!action)
                         goto unlock;
@@ -66,7 +57,7 @@ int show_interrupts(struct seq_file *p, void *v)
 
                 seq_putc(p, '\n');
         unlock:
-                spin_unlock_irqrestore(&irq_desc[i].lock, flags);
+                raw_spin_unlock_irqrestore(&irq_desc[i].lock, flags);
         }
 
         return 0;
diff --git a/arch/avr32/kernel/sys_avr32.c b/arch/avr32/kernel/sys_avr32.c
index 5d2daeaf356f..459349b5ed5a 100644
--- a/arch/avr32/kernel/sys_avr32.c
+++ b/arch/avr32/kernel/sys_avr32.c
@@ -5,39 +5,8 @@
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
  */
-#include <linux/errno.h>
-#include <linux/fs.h>
-#include <linux/file.h>
-#include <linux/mm.h>
 #include <linux/unistd.h>
 
-#include <asm/mman.h>
-#include <asm/uaccess.h>
-#include <asm/syscalls.h>
-
-asmlinkage long sys_mmap2(unsigned long addr, unsigned long len,
-                          unsigned long prot, unsigned long flags,
-                          unsigned long fd, off_t offset)
-{
-        int error = -EBADF;
-        struct file *file = NULL;
-
-        flags &= ~(MAP_EXECUTABLE | MAP_DENYWRITE);
-        if (!(flags & MAP_ANONYMOUS)) {
-                file = fget(fd);
-                if (!file)
-                        return error;
-        }
-
-        down_write(&current->mm->mmap_sem);
-        error = do_mmap_pgoff(file, addr, len, prot, flags, offset);
-        up_write(&current->mm->mmap_sem);
-
-        if (file)
-                fput(file);
-        return error;
-}
-
 int kernel_execve(const char *file, char **argv, char **envp)
 {
         register long scno asm("r8") = __NR_execve;
diff --git a/arch/avr32/kernel/syscall-stubs.S b/arch/avr32/kernel/syscall-stubs.S
index f7244cd02fbb..0447a3e2ba64 100644
--- a/arch/avr32/kernel/syscall-stubs.S
+++ b/arch/avr32/kernel/syscall-stubs.S
@@ -61,7 +61,7 @@ __sys_execve:
 __sys_mmap2:
         pushm   lr
         st.w    --sp, ARG6
-        call    sys_mmap2
+        call    sys_mmap_pgoff
         sub     sp, -4
         popm    pc
 
diff --git a/arch/avr32/kernel/vmlinux.lds.S b/arch/avr32/kernel/vmlinux.lds.S
index c4b56654349a..9cd2bd91d64a 100644
--- a/arch/avr32/kernel/vmlinux.lds.S
+++ b/arch/avr32/kernel/vmlinux.lds.S
@@ -39,30 +39,10 @@ SECTIONS
                 __tagtable_begin = .;
                         *(.taglist.init)
                 __tagtable_end = .;
-                        INIT_DATA
-                . = ALIGN(16);
-                __setup_start = .;
-                        *(.init.setup)
-                __setup_end = .;
-                . = ALIGN(4);
-                __initcall_start = .;
-                        INITCALLS
-                __initcall_end = .;
-                __con_initcall_start = .;
-                        *(.con_initcall.init)
-                __con_initcall_end = .;
-                __security_initcall_start = .;
-                        *(.security_initcall.init)
-                __security_initcall_end = .;
-#ifdef CONFIG_BLK_DEV_INITRD
-                . = ALIGN(32);
-                __initramfs_start = .;
-                        *(.init.ramfs)
-                __initramfs_end = .;
-#endif
-                . = ALIGN(PAGE_SIZE);
-                __init_end = .;
         }
+        INIT_DATA_SECTION(16)
+        . = ALIGN(PAGE_SIZE);
+        __init_end = .;
 
         .text           : AT(ADDR(.text) - LOAD_OFFSET) {
                 _evba = .;
@@ -78,34 +58,16 @@ SECTIONS
                 _etext = .;
         } = 0xd703d703
 
-        . = ALIGN(4);
-        __ex_table      : AT(ADDR(__ex_table) - LOAD_OFFSET) {
-                __start___ex_table = .;
-                *(__ex_table)
-                __stop___ex_table = .;
-        }
-
+        EXCEPTION_TABLE(4)
         RODATA
 
-        . = ALIGN(THREAD_SIZE);
-
         .data           : AT(ADDR(.data) - LOAD_OFFSET) {
                 _data = .;
                 _sdata = .;
-                /*
-                 * First, the init task union, aligned to an 8K boundary.
-                 */
-                *(.data.init_task)
 
-                /* Then, the page-aligned data */
-                . = ALIGN(PAGE_SIZE);
-                *(.data.page_aligned)
-
-                /* Then, the cacheline aligned data */
-                . = ALIGN(L1_CACHE_BYTES);
-                *(.data.cacheline_aligned)
-
-                /* And the rest... */
+                INIT_TASK_DATA(THREAD_SIZE)
+                PAGE_ALIGNED_DATA(PAGE_SIZE);
+                CACHELINE_ALIGNED_DATA(L1_CACHE_BYTES)
                 *(.data.rel*)
                 DATA_DATA
                 CONSTRUCTORS
@@ -113,16 +75,8 @@ SECTIONS
                 _edata = .;
         }
 
-
-        . = ALIGN(8);
-        .bss            : AT(ADDR(.bss) - LOAD_OFFSET) {
-                __bss_start = .;
-                *(.bss)
-                *(COMMON)
-                . = ALIGN(8);
-                __bss_stop = .;
-                _end = .;
-        }
+        BSS_SECTION(0, 8, 8)
+        _end = .;
 
         DWARF_DEBUG
 
diff --git a/arch/avr32/mach-at32ap/at32ap700x.c b/arch/avr32/mach-at32ap/at32ap700x.c
index eb9d4dc2e86d..1aa1ea5e9212 100644
--- a/arch/avr32/mach-at32ap/at32ap700x.c
+++ b/arch/avr32/mach-at32ap/at32ap700x.c
@@ -15,6 +15,8 @@
 #include <linux/gpio.h>
 #include <linux/spi/spi.h>
 #include <linux/usb/atmel_usba_udc.h>
+
+#include <mach/atmel-mci.h>
 #include <linux/atmel-mci.h>
 
 #include <asm/io.h>
@@ -1181,19 +1183,32 @@ static struct resource atmel_spi1_resource[] = {
 DEFINE_DEV(atmel_spi, 1);
 DEV_CLK(spi_clk, atmel_spi1, pba, 1);
 
-static void __init
-at32_spi_setup_slaves(unsigned int bus_num, struct spi_board_info *b,
-                      unsigned int n, const u8 *pins)
+void __init
+at32_spi_setup_slaves(unsigned int bus_num, struct spi_board_info *b, unsigned int n)
 {
+        /*
+         * Manage the chipselects as GPIOs, normally using the same pins
+         * the SPI controller expects; but boards can use other pins.
+         */
+        static u8 __initdata spi_pins[][4] = {
+                { GPIO_PIN_PA(3), GPIO_PIN_PA(4),
+                  GPIO_PIN_PA(5), GPIO_PIN_PA(20) },
+                { GPIO_PIN_PB(2), GPIO_PIN_PB(3),
+                  GPIO_PIN_PB(4), GPIO_PIN_PA(27) },
+        };
         unsigned int pin, mode;
 
+        /* There are only 2 SPI controllers */
+        if (bus_num > 1)
+                return;
+
         for (; n; n--, b++) {
                 b->bus_num = bus_num;
                 if (b->chip_select >= 4)
                         continue;
                 pin = (unsigned)b->controller_data;
                 if (!pin) {
-                        pin = pins[b->chip_select];
+                        pin = spi_pins[bus_num][b->chip_select];
                         b->controller_data = (void *)pin;
                 }
                 mode = AT32_GPIOF_OUTPUT;
@@ -1206,16 +1221,6 @@ at32_spi_setup_slaves(unsigned int bus_num, struct spi_board_info *b,
 struct platform_device *__init
 at32_add_device_spi(unsigned int id, struct spi_board_info *b, unsigned int n)
 {
-        /*
-         * Manage the chipselects as GPIOs, normally using the same pins
-         * the SPI controller expects; but boards can use other pins.
-         */
-        static u8 __initdata spi0_pins[] =
-                { GPIO_PIN_PA(3), GPIO_PIN_PA(4),
-                  GPIO_PIN_PA(5), GPIO_PIN_PA(20), };
-        static u8 __initdata spi1_pins[] =
-                { GPIO_PIN_PB(2), GPIO_PIN_PB(3),
-                  GPIO_PIN_PB(4), GPIO_PIN_PA(27), };
         struct platform_device *pdev;
         u32 pin_mask;
 
@@ -1228,7 +1233,7 @@ at32_add_device_spi(unsigned int id, struct spi_board_info *b, unsigned int n)
                 select_peripheral(PIOA, (1 << 0), PERIPH_A, AT32_GPIOF_PULLUP);
                 select_peripheral(PIOA, pin_mask, PERIPH_A, 0);
 
-                at32_spi_setup_slaves(0, b, n, spi0_pins);
+                at32_spi_setup_slaves(0, b, n);
                 break;
 
         case 1:
@@ -1239,7 +1244,7 @@ at32_add_device_spi(unsigned int id, struct spi_board_info *b, unsigned int n)
                 select_peripheral(PIOB, (1 << 0), PERIPH_B, AT32_GPIOF_PULLUP);
                 select_peripheral(PIOB, pin_mask, PERIPH_B, 0);
 
-                at32_spi_setup_slaves(1, b, n, spi1_pins);
+                at32_spi_setup_slaves(1, b, n);
                 break;
 
         default:
@@ -1320,7 +1325,7 @@ struct platform_device *__init
 at32_add_device_mci(unsigned int id, struct mci_platform_data *data)
 {
         struct platform_device          *pdev;
-        struct dw_dma_slave             *dws = &data->dma_slave;
+        struct mci_dma_slave            *slave;
         u32                             pioa_mask;
         u32                             piob_mask;
 
@@ -1339,13 +1344,17 @@ at32_add_device_mci(unsigned int id, struct mci_platform_data *data)
                                 ARRAY_SIZE(atmel_mci0_resource)))
                 goto fail;
 
-        dws->dma_dev = &dw_dmac0_device.dev;
-        dws->reg_width = DW_DMA_SLAVE_WIDTH_32BIT;
-        dws->cfg_hi = (DWC_CFGH_SRC_PER(0)
+        slave = kzalloc(sizeof(struct mci_dma_slave), GFP_KERNEL);
+
+        slave->sdata.dma_dev = &dw_dmac0_device.dev;
+        slave->sdata.reg_width = DW_DMA_SLAVE_WIDTH_32BIT;
+        slave->sdata.cfg_hi = (DWC_CFGH_SRC_PER(0)
                                 | DWC_CFGH_DST_PER(1));
-        dws->cfg_lo &= ~(DWC_CFGL_HS_DST_POL
+        slave->sdata.cfg_lo &= ~(DWC_CFGL_HS_DST_POL
                                 | DWC_CFGL_HS_SRC_POL);
 
+        data->dma_slave = slave;
+
         if (platform_device_add_data(pdev, data,
                                 sizeof(struct mci_platform_data)))
                 goto fail;
@@ -1411,6 +1420,8 @@ at32_add_device_mci(unsigned int id, struct mci_platform_data *data)
         return pdev;
 
 fail:
+        data->dma_slave = NULL;
+        kfree(slave);
         platform_device_put(pdev);
         return NULL;
 }
diff --git a/arch/avr32/mach-at32ap/include/mach/atmel-mci.h b/arch/avr32/mach-at32ap/include/mach/atmel-mci.h
new file mode 100644
index 000000000000..a9b38967f703
--- /dev/null
+++ b/arch/avr32/mach-at32ap/include/mach/atmel-mci.h
@@ -0,0 +1,24 @@
+#ifndef __MACH_ATMEL_MCI_H
+#define __MACH_ATMEL_MCI_H
+
+#include <linux/dw_dmac.h>
+
+/**
+ * struct mci_dma_data - DMA data for MCI interface
+ */
+struct mci_dma_data {
+        struct dw_dma_slave     sdata;
+};
+
+/* accessor macros */
+#define slave_data_ptr(s)       (&(s)->sdata)
+#define find_slave_dev(s)       ((s)->sdata.dma_dev)
+
+#define setup_dma_addr(s, t, r) do {            \
+        if (s) {                                \
+                (s)->sdata.tx_reg = (t);        \
+                (s)->sdata.rx_reg = (r);        \
+        }                                       \
+} while (0)
+
+#endif /* __MACH_ATMEL_MCI_H */
diff --git a/arch/avr32/mach-at32ap/include/mach/board.h b/arch/avr32/mach-at32ap/include/mach/board.h
index ddedb471f33e..c7f25bb1d068 100644
--- a/arch/avr32/mach-at32ap/include/mach/board.h
+++ b/arch/avr32/mach-at32ap/include/mach/board.h
@@ -49,6 +49,7 @@ at32_add_device_eth(unsigned int id, struct eth_platform_data *data);
 struct spi_board_info;
 struct platform_device *
 at32_add_device_spi(unsigned int id, struct spi_board_info *b, unsigned int n);
+void at32_spi_setup_slaves(unsigned int bus_num, struct spi_board_info *b, unsigned int n);
 
 struct atmel_lcdfb_info;
 struct platform_device *
diff --git a/arch/blackfin/Kconfig b/arch/blackfin/Kconfig
index ae6a60f10120..53c1e1d45c68 100644
--- a/arch/blackfin/Kconfig
+++ b/arch/blackfin/Kconfig
@@ -5,6 +5,10 @@
 
 mainmenu "Blackfin Kernel Configuration"
 
+config SYMBOL_PREFIX
+        string
+        default "_"
+
 config MMU
         def_bool n
 
@@ -28,6 +32,9 @@ config BLACKFIN
         select HAVE_OPROFILE
         select ARCH_WANT_OPTIONAL_GPIOLIB
 
+config GENERIC_CSUM
+        def_bool y
+
 config GENERIC_BUG
         def_bool y
         depends on BUG
@@ -173,7 +180,7 @@ config BF539
         help
           BF539 Processor Support.
 
-config BF542
+config BF542_std
         bool "BF542"
         help
           BF542 Processor Support.
@@ -183,7 +190,7 @@ config BF542M
         help
           BF542 Processor Support.
 
-config BF544
+config BF544_std
         bool "BF544"
         help
           BF544 Processor Support.
@@ -193,7 +200,7 @@ config BF544M
         help
           BF544 Processor Support.
 
-config BF547
+config BF547_std
         bool "BF547"
         help
           BF547 Processor Support.
@@ -203,7 +210,7 @@ config BF547M
         help
           BF547 Processor Support.
 
-config BF548
+config BF548_std
         bool "BF548"
         help
           BF548 Processor Support.
@@ -213,7 +220,7 @@ config BF548M
         help
           BF548 Processor Support.
 
-config BF549
+config BF549_std
         bool "BF549"
         help
           BF549 Processor Support.
@@ -307,31 +314,11 @@ config BF_REV_NONE
 
 endchoice
 
-config BF51x
-        bool
-        depends on (BF512 || BF514 || BF516 || BF518)
-        default y
-
-config BF52x
-        bool
-        depends on (BF522 || BF523 || BF524 || BF525 || BF526 || BF527)
-        default y
-
 config BF53x
         bool
         depends on (BF531 || BF532 || BF533 || BF534 || BF536 || BF537)
         default y
 
-config BF54xM
-        bool
-        depends on (BF542M || BF544M || BF547M || BF548M || BF549M)
-        default y
-
-config BF54x
-        bool
-        depends on (BF542 || BF544 || BF547 || BF548 || BF549 || BF54xM)
-        default y
-
 config MEM_GENERIC_BOARD
         bool
         depends on GENERIC_BOARD
@@ -913,6 +900,12 @@ config DMA_UNCACHED_2M
         bool "Enable 2M DMA region"
 config DMA_UNCACHED_1M
         bool "Enable 1M DMA region"
+config DMA_UNCACHED_512K
+        bool "Enable 512K DMA region"
+config DMA_UNCACHED_256K
+        bool "Enable 256K DMA region"
+config DMA_UNCACHED_128K
+        bool "Enable 128K DMA region"
 config DMA_UNCACHED_NONE
         bool "Disable DMA region"
 endchoice
@@ -1274,6 +1267,8 @@ source "net/Kconfig"
 
 source "drivers/Kconfig"
 
+source "drivers/firmware/Kconfig"
+
 source "fs/Kconfig"
 
 source "arch/blackfin/Kconfig.debug"
diff --git a/arch/blackfin/Makefile b/arch/blackfin/Makefile
index f063b772934b..d4c7177e7656 100644
--- a/arch/blackfin/Makefile
+++ b/arch/blackfin/Makefile
@@ -16,6 +16,7 @@ GZFLAGS          := -9
 KBUILD_CFLAGS           += $(call cc-option,-mno-fdpic)
 KBUILD_AFLAGS           += $(call cc-option,-mno-fdpic)
 CFLAGS_MODULE    += -mlong-calls
+LDFLAGS_MODULE   += -m elf32bfin
 KALLSYMS         += --symbol-prefix=_
 
 KBUILD_DEFCONFIG := BF537-STAMP_defconfig
@@ -137,7 +138,7 @@ archclean:
 
 INSTALL_PATH ?= /tftpboot
 boot := arch/$(ARCH)/boot
-BOOT_TARGETS = vmImage vmImage.bz2 vmImage.gz vmImage.lzma
+BOOT_TARGETS = vmImage vmImage.bin vmImage.bz2 vmImage.gz vmImage.lzma
 PHONY += $(BOOT_TARGETS) install
 KBUILD_IMAGE := $(boot)/vmImage
 
@@ -151,6 +152,7 @@ install:
 
 define archhelp
   echo  '* vmImage         - Alias to selected kernel format (vmImage.gz by default)'
+  echo  '  vmImage.bin     - Uncompressed Kernel-only image for U-Boot (arch/$(ARCH)/boot/vmImage.bin)'
   echo  '  vmImage.bz2     - Kernel-only image for U-Boot (arch/$(ARCH)/boot/vmImage.bz2)'
   echo  '* vmImage.gz      - Kernel-only image for U-Boot (arch/$(ARCH)/boot/vmImage.gz)'
   echo  '  vmImage.lzma    - Kernel-only image for U-Boot (arch/$(ARCH)/boot/vmImage.lzma)'
diff --git a/arch/blackfin/boot/Makefile b/arch/blackfin/boot/Makefile
index fd9ccc5fea10..e9c48c6f8c1f 100644
--- a/arch/blackfin/boot/Makefile
+++ b/arch/blackfin/boot/Makefile
@@ -8,7 +8,7 @@
 
 MKIMAGE := $(srctree)/scripts/mkuboot.sh
 
-targets := vmImage vmImage.bz2 vmImage.gz vmImage.lzma
+targets := vmImage vmImage.bin vmImage.bz2 vmImage.gz vmImage.lzma
 extra-y += vmlinux.bin vmlinux.bin.gz vmlinux.bin.bz2 vmlinux.bin.lzma
 
 quiet_cmd_uimage = UIMAGE  $@
@@ -29,6 +29,9 @@ $(obj)/vmlinux.bin.bz2: $(obj)/vmlinux.bin FORCE
 $(obj)/vmlinux.bin.lzma: $(obj)/vmlinux.bin FORCE
         $(call if_changed,lzma)
 
+$(obj)/vmImage.bin: $(obj)/vmlinux.bin
+        $(call if_changed,uimage,none)
+
 $(obj)/vmImage.bz2: $(obj)/vmlinux.bin.bz2
         $(call if_changed,uimage,bzip2)
 
@@ -38,6 +41,7 @@ $(obj)/vmImage.gz: $(obj)/vmlinux.bin.gz
 $(obj)/vmImage.lzma: $(obj)/vmlinux.bin.lzma
         $(call if_changed,uimage,lzma)
 
+suffix-y                      := bin
 suffix-$(CONFIG_KERNEL_GZIP)  := gz
 suffix-$(CONFIG_KERNEL_BZIP2) := bz2
 suffix-$(CONFIG_KERNEL_LZMA)  := lzma
diff --git a/arch/blackfin/configs/BF518F-EZBRD_defconfig b/arch/blackfin/configs/BF518F-EZBRD_defconfig
index 9905b26009e5..e31559419817 100644
--- a/arch/blackfin/configs/BF518F-EZBRD_defconfig
+++ b/arch/blackfin/configs/BF518F-EZBRD_defconfig
@@ -67,6 +67,7 @@ CONFIG_COMPAT_BRK=y
 CONFIG_SLAB=y
 # CONFIG_SLUB is not set
 # CONFIG_SLOB is not set
+CONFIG_MMAP_ALLOW_UNINITIALIZED=y
 # CONFIG_PROFILING is not set
 # CONFIG_MARKERS is not set
 CONFIG_HAVE_OPROFILE=y
@@ -316,6 +317,7 @@ CONFIG_SPLIT_PTLOCK_CPUS=4
 # CONFIG_PHYS_ADDR_T_64BIT is not set
 CONFIG_ZONE_DMA_FLAG=1
 CONFIG_VIRT_TO_BUS=y
+CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0
 CONFIG_BFIN_GPTIMERS=m
 # CONFIG_DMA_UNCACHED_4M is not set
 # CONFIG_DMA_UNCACHED_2M is not set
@@ -438,17 +440,7 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
 # CONFIG_TIPC is not set
 # CONFIG_ATM is not set
 # CONFIG_BRIDGE is not set
-CONFIG_NET_DSA=y
-# CONFIG_NET_DSA_TAG_DSA is not set
-# CONFIG_NET_DSA_TAG_EDSA is not set
-# CONFIG_NET_DSA_TAG_TRAILER is not set
-CONFIG_NET_DSA_TAG_STPID=y
-# CONFIG_NET_DSA_MV88E6XXX is not set
-# CONFIG_NET_DSA_MV88E6060 is not set
-# CONFIG_NET_DSA_MV88E6XXX_NEED_PPU is not set
-# CONFIG_NET_DSA_MV88E6131 is not set
-# CONFIG_NET_DSA_MV88E6123_61_65 is not set
-CONFIG_NET_DSA_KSZ8893M=y
+# CONFIG_NET_DSA is not set
 # CONFIG_VLAN_8021Q is not set
 # CONFIG_DECNET is not set
 # CONFIG_LLC2 is not set
diff --git a/arch/blackfin/configs/BF526-EZBRD_defconfig b/arch/blackfin/configs/BF526-EZBRD_defconfig
index 9dc682088023..075e0fdcb399 100644
--- a/arch/blackfin/configs/BF526-EZBRD_defconfig
+++ b/arch/blackfin/configs/BF526-EZBRD_defconfig
@@ -67,6 +67,7 @@ CONFIG_COMPAT_BRK=y
 CONFIG_SLAB=y
 # CONFIG_SLUB is not set
 # CONFIG_SLOB is not set
+CONFIG_MMAP_ALLOW_UNINITIALIZED=y
 # CONFIG_PROFILING is not set
 # CONFIG_MARKERS is not set
 CONFIG_HAVE_OPROFILE=y
@@ -321,6 +322,7 @@ CONFIG_SPLIT_PTLOCK_CPUS=4
 # CONFIG_PHYS_ADDR_T_64BIT is not set
 CONFIG_ZONE_DMA_FLAG=1
 CONFIG_VIRT_TO_BUS=y
+CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0
 CONFIG_BFIN_GPTIMERS=m
 # CONFIG_DMA_UNCACHED_4M is not set
 # CONFIG_DMA_UNCACHED_2M is not set
diff --git a/arch/blackfin/configs/BF527-EZKIT_defconfig b/arch/blackfin/configs/BF527-EZKIT_defconfig
index 77e35d4baf53..6d1a623fb149 100644
--- a/arch/blackfin/configs/BF527-EZKIT_defconfig
+++ b/arch/blackfin/configs/BF527-EZKIT_defconfig
@@ -67,6 +67,7 @@ CONFIG_COMPAT_BRK=y
 CONFIG_SLAB=y
 # CONFIG_SLUB is not set
 # CONFIG_SLOB is not set
+CONFIG_MMAP_ALLOW_UNINITIALIZED=y
 # CONFIG_PROFILING is not set
 # CONFIG_MARKERS is not set
 CONFIG_HAVE_OPROFILE=y
@@ -321,6 +322,7 @@ CONFIG_SPLIT_PTLOCK_CPUS=4
 # CONFIG_PHYS_ADDR_T_64BIT is not set
 CONFIG_ZONE_DMA_FLAG=1
 CONFIG_VIRT_TO_BUS=y
+CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0
 CONFIG_BFIN_GPTIMERS=y
 # CONFIG_DMA_UNCACHED_4M is not set
 # CONFIG_DMA_UNCACHED_2M is not set
diff --git a/arch/blackfin/configs/BF533-EZKIT_defconfig b/arch/blackfin/configs/BF533-EZKIT_defconfig
index 4c044805cb5c..50f9a23ccdbd 100644
--- a/arch/blackfin/configs/BF533-EZKIT_defconfig
+++ b/arch/blackfin/configs/BF533-EZKIT_defconfig
@@ -67,6 +67,7 @@ CONFIG_COMPAT_BRK=y
 CONFIG_SLAB=y
 # CONFIG_SLUB is not set
 # CONFIG_SLOB is not set
+CONFIG_MMAP_ALLOW_UNINITIALIZED=y
 # CONFIG_PROFILING is not set
 # CONFIG_MARKERS is not set
 CONFIG_HAVE_OPROFILE=y
@@ -283,6 +284,7 @@ CONFIG_SPLIT_PTLOCK_CPUS=4
 # CONFIG_PHYS_ADDR_T_64BIT is not set
 CONFIG_ZONE_DMA_FLAG=1
 CONFIG_VIRT_TO_BUS=y
+CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0
 CONFIG_BFIN_GPTIMERS=m
 # CONFIG_DMA_UNCACHED_4M is not set
 # CONFIG_DMA_UNCACHED_2M is not set
diff --git a/arch/blackfin/configs/BF533-STAMP_defconfig b/arch/blackfin/configs/BF533-STAMP_defconfig
index c99bbcd09a68..6c60c8286318 100644
--- a/arch/blackfin/configs/BF533-STAMP_defconfig
+++ b/arch/blackfin/configs/BF533-STAMP_defconfig
@@ -67,6 +67,7 @@ CONFIG_COMPAT_BRK=y
 CONFIG_SLAB=y
 # CONFIG_SLUB is not set
 # CONFIG_SLOB is not set
+CONFIG_MMAP_ALLOW_UNINITIALIZED=y
 # CONFIG_PROFILING is not set
 # CONFIG_MARKERS is not set
 CONFIG_HAVE_OPROFILE=y
@@ -283,6 +284,7 @@ CONFIG_SPLIT_PTLOCK_CPUS=4
 # CONFIG_PHYS_ADDR_T_64BIT is not set
 CONFIG_ZONE_DMA_FLAG=1
 CONFIG_VIRT_TO_BUS=y
+CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0
 CONFIG_BFIN_GPTIMERS=m
 # CONFIG_DMA_UNCACHED_4M is not set
 # CONFIG_DMA_UNCACHED_2M is not set
diff --git a/arch/blackfin/configs/BF537-STAMP_defconfig b/arch/blackfin/configs/BF537-STAMP_defconfig
index 092ffda80e68..2908595b67c5 100644
--- a/arch/blackfin/configs/BF537-STAMP_defconfig
+++ b/arch/blackfin/configs/BF537-STAMP_defconfig
@@ -67,6 +67,7 @@ CONFIG_COMPAT_BRK=y
 CONFIG_SLAB=y
 # CONFIG_SLUB is not set
 # CONFIG_SLOB is not set
+CONFIG_MMAP_ALLOW_UNINITIALIZED=y
 # CONFIG_PROFILING is not set
 # CONFIG_MARKERS is not set
 CONFIG_HAVE_OPROFILE=y
@@ -290,6 +291,7 @@ CONFIG_SPLIT_PTLOCK_CPUS=4
 # CONFIG_PHYS_ADDR_T_64BIT is not set
 CONFIG_ZONE_DMA_FLAG=1
 CONFIG_VIRT_TO_BUS=y
+CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0
 CONFIG_BFIN_GPTIMERS=m
 # CONFIG_DMA_UNCACHED_4M is not set
 # CONFIG_DMA_UNCACHED_2M is not set
@@ -704,10 +706,7 @@ CONFIG_CONFIG_INPUT_PCF8574=m
 #
 # Hardware I/O ports
 #
-CONFIG_SERIO=y
-CONFIG_SERIO_SERPORT=y
-CONFIG_SERIO_LIBPS2=y
-# CONFIG_SERIO_RAW is not set
+# CONFIG_SERIO is not set
 # CONFIG_GAMEPORT is not set
 
 #
diff --git a/arch/blackfin/configs/BF538-EZKIT_defconfig b/arch/blackfin/configs/BF538-EZKIT_defconfig
index fa698a89f6fe..09ea2499555e 100644
--- a/arch/blackfin/configs/BF538-EZKIT_defconfig
+++ b/arch/blackfin/configs/BF538-EZKIT_defconfig
@@ -67,6 +67,7 @@ CONFIG_COMPAT_BRK=y
 CONFIG_SLAB=y
 # CONFIG_SLUB is not set
 # CONFIG_SLOB is not set
+CONFIG_MMAP_ALLOW_UNINITIALIZED=y
 # CONFIG_PROFILING is not set
 # CONFIG_MARKERS is not set
 CONFIG_HAVE_OPROFILE=y
@@ -301,6 +302,7 @@ CONFIG_SPLIT_PTLOCK_CPUS=4
 # CONFIG_PHYS_ADDR_T_64BIT is not set
 CONFIG_ZONE_DMA_FLAG=1
 CONFIG_VIRT_TO_BUS=y
+CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0
 CONFIG_BFIN_GPTIMERS=m
 # CONFIG_DMA_UNCACHED_4M is not set
 # CONFIG_DMA_UNCACHED_2M is not set
diff --git a/arch/blackfin/configs/BF548-EZKIT_defconfig b/arch/blackfin/configs/BF548-EZKIT_defconfig
index f773ad1155d4..eb3e98b6f3f0 100644
--- a/arch/blackfin/configs/BF548-EZKIT_defconfig
+++ b/arch/blackfin/configs/BF548-EZKIT_defconfig
@@ -1,22 +1,29 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.28.10
-# Thu May 21 05:50:01 2009
+# Linux kernel version: 2.6.31.5
+# Mon Nov  2 22:02:56 2009
 #
 # CONFIG_MMU is not set
 # CONFIG_FPU is not set
 CONFIG_RWSEM_GENERIC_SPINLOCK=y
 # CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
 CONFIG_BLACKFIN=y
+CONFIG_GENERIC_CSUM=y
+CONFIG_GENERIC_BUG=y
 CONFIG_ZONE_DMA=y
 CONFIG_GENERIC_FIND_NEXT_BIT=y
 CONFIG_GENERIC_HWEIGHT=y
 CONFIG_GENERIC_HARDIRQS=y
 CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
 CONFIG_GENERIC_GPIO=y
 CONFIG_FORCE_MAX_ZONEORDER=14
 CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
 CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+CONFIG_CONSTRUCTORS=y
 
 #
 # General setup
@@ -26,22 +33,40 @@ CONFIG_BROKEN_ON_SMP=y
 CONFIG_INIT_ENV_ARG_LIMIT=32
 CONFIG_LOCALVERSION=""
 CONFIG_LOCALVERSION_AUTO=y
+CONFIG_HAVE_KERNEL_GZIP=y
+CONFIG_HAVE_KERNEL_BZIP2=y
+CONFIG_HAVE_KERNEL_LZMA=y
+CONFIG_KERNEL_GZIP=y
+# CONFIG_KERNEL_BZIP2 is not set
+# CONFIG_KERNEL_LZMA is not set
 CONFIG_SYSVIPC=y
 CONFIG_SYSVIPC_SYSCTL=y
 # CONFIG_POSIX_MQUEUE is not set
 # CONFIG_BSD_PROCESS_ACCT is not set
 # CONFIG_TASKSTATS is not set
 # CONFIG_AUDIT is not set
+
+#
+# RCU Subsystem
+#
+CONFIG_CLASSIC_RCU=y
+# CONFIG_TREE_RCU is not set
+# CONFIG_PREEMPT_RCU is not set
+# CONFIG_TREE_RCU_TRACE is not set
+# CONFIG_PREEMPT_RCU_TRACE is not set
 CONFIG_IKCONFIG=y
 CONFIG_IKCONFIG_PROC=y
 CONFIG_LOG_BUF_SHIFT=14
-# CONFIG_CGROUPS is not set
 # CONFIG_GROUP_SCHED is not set
+# CONFIG_CGROUPS is not set
 # CONFIG_SYSFS_DEPRECATED_V2 is not set
 # CONFIG_RELAY is not set
 # CONFIG_NAMESPACES is not set
 CONFIG_BLK_DEV_INITRD=y
 CONFIG_INITRAMFS_SOURCE=""
+CONFIG_RD_GZIP=y
+# CONFIG_RD_BZIP2 is not set
+# CONFIG_RD_LZMA is not set
 # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
 CONFIG_SYSCTL=y
 CONFIG_ANON_INODES=y
@@ -62,17 +87,28 @@ CONFIG_EPOLL=y
 # CONFIG_TIMERFD is not set
 # CONFIG_EVENTFD is not set
 # CONFIG_AIO is not set
+
+#
+# Performance Counters
+#
 CONFIG_VM_EVENT_COUNTERS=y
+# CONFIG_STRIP_ASM_SYMS is not set
 CONFIG_COMPAT_BRK=y
 CONFIG_SLAB=y
 # CONFIG_SLUB is not set
 # CONFIG_SLOB is not set
+CONFIG_MMAP_ALLOW_UNINITIALIZED=y
 # CONFIG_PROFILING is not set
 # CONFIG_MARKERS is not set
 CONFIG_HAVE_OPROFILE=y
+
+#
+# GCOV-based kernel profiling
+#
+# CONFIG_GCOV_KERNEL is not set
+# CONFIG_SLOW_WORK is not set
 # CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
 CONFIG_SLABINFO=y
-CONFIG_TINY_SHMEM=y
 CONFIG_BASE_SMALL=0
 CONFIG_MODULES=y
 # CONFIG_MODULE_FORCE_LOAD is not set
@@ -80,11 +116,8 @@ CONFIG_MODULE_UNLOAD=y
 # CONFIG_MODULE_FORCE_UNLOAD is not set
 # CONFIG_MODVERSIONS is not set
 # CONFIG_MODULE_SRCVERSION_ALL is not set
-CONFIG_KMOD=y
 CONFIG_BLOCK=y
-# CONFIG_LBD is not set
-# CONFIG_BLK_DEV_IO_TRACE is not set
-# CONFIG_LSF is not set
+# CONFIG_LBDAF is not set
 # CONFIG_BLK_DEV_BSG is not set
 # CONFIG_BLK_DEV_INTEGRITY is not set
 
@@ -94,13 +127,12 @@ CONFIG_BLOCK=y
 CONFIG_IOSCHED_NOOP=y
 CONFIG_IOSCHED_AS=y
 # CONFIG_IOSCHED_DEADLINE is not set
-CONFIG_IOSCHED_CFQ=y
+# CONFIG_IOSCHED_CFQ is not set
 CONFIG_DEFAULT_AS=y
 # CONFIG_DEFAULT_DEADLINE is not set
 # CONFIG_DEFAULT_CFQ is not set
 # CONFIG_DEFAULT_NOOP is not set
 CONFIG_DEFAULT_IOSCHED="anticipatory"
-CONFIG_CLASSIC_RCU=y
 # CONFIG_PREEMPT_NONE is not set
 CONFIG_PREEMPT_VOLUNTARY=y
 # CONFIG_PREEMPT is not set
@@ -137,7 +169,7 @@ CONFIG_PREEMPT_VOLUNTARY=y
 # CONFIG_BF544M is not set
 # CONFIG_BF547 is not set
 # CONFIG_BF547M is not set
-CONFIG_BF548=y
+CONFIG_BF548_std=y
 # CONFIG_BF548M is not set
 # CONFIG_BF549 is not set
 # CONFIG_BF549M is not set
@@ -195,7 +227,7 @@ CONFIG_BFIN548_EZKIT=y
 #
 # BF548 Specific Configuration
 #
-# CONFIG_DEB_DMA_URGENT is not set
+CONFIG_DEB_DMA_URGENT=y
 # CONFIG_BF548_ATAPI_ALTERNATIVE_PORT is not set
 
 #
@@ -352,10 +384,11 @@ CONFIG_FLATMEM=y
 CONFIG_FLAT_NODE_MEM_MAP=y
 CONFIG_PAGEFLAGS_EXTENDED=y
 CONFIG_SPLIT_PTLOCK_CPUS=4
-# CONFIG_RESOURCES_64BIT is not set
 # CONFIG_PHYS_ADDR_T_64BIT is not set
 CONFIG_ZONE_DMA_FLAG=1
 CONFIG_VIRT_TO_BUS=y
+CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
+CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0
 CONFIG_BFIN_GPTIMERS=m
 # CONFIG_DMA_UNCACHED_4M is not set
 CONFIG_DMA_UNCACHED_2M=y
@@ -366,14 +399,13 @@ CONFIG_DMA_UNCACHED_2M=y
 # Cache Support
 #
 CONFIG_BFIN_ICACHE=y
-# CONFIG_BFIN_ICACHE_LOCK is not set
+CONFIG_BFIN_EXTMEM_ICACHEABLE=y
+# CONFIG_BFIN_L2_ICACHEABLE is not set
 CONFIG_BFIN_DCACHE=y
 # CONFIG_BFIN_DCACHE_BANKA is not set
-CONFIG_BFIN_EXTMEM_ICACHEABLE=y
 CONFIG_BFIN_EXTMEM_DCACHEABLE=y
-CONFIG_BFIN_EXTMEM_WRITEBACK=y
-# CONFIG_BFIN_EXTMEM_WRITETHROUGH is not set
-# CONFIG_BFIN_L2_ICACHEABLE is not set
+# CONFIG_BFIN_EXTMEM_WRITEBACK is not set
+CONFIG_BFIN_EXTMEM_WRITETHROUGH=y
 # CONFIG_BFIN_L2_DCACHEABLE is not set
 
 #
@@ -382,7 +414,7 @@ CONFIG_BFIN_EXTMEM_WRITEBACK=y
 # CONFIG_MPU is not set
 
 #
-# Asynchonous Memory Configuration
+# Asynchronous Memory Configuration
 #
 
 #
@@ -441,11 +473,6 @@ CONFIG_NET=y
 CONFIG_PACKET=y
 # CONFIG_PACKET_MMAP is not set
 CONFIG_UNIX=y
-CONFIG_XFRM=y
-# CONFIG_XFRM_USER is not set
-# CONFIG_XFRM_SUB_POLICY is not set
-# CONFIG_XFRM_MIGRATE is not set
-# CONFIG_XFRM_STATISTICS is not set
 # CONFIG_NET_KEY is not set
 CONFIG_INET=y
 # CONFIG_IP_MULTICAST is not set
@@ -469,13 +496,11 @@ CONFIG_IP_PNP=y
 # CONFIG_INET_XFRM_MODE_BEET is not set
 # CONFIG_INET_LRO is not set
 # CONFIG_INET_DIAG is not set
-CONFIG_INET_TCP_DIAG=y
 # CONFIG_TCP_CONG_ADVANCED is not set
 CONFIG_TCP_CONG_CUBIC=y
 CONFIG_DEFAULT_TCP_CONG="cubic"
 # CONFIG_TCP_MD5SIG is not set
 # CONFIG_IPV6 is not set
-# CONFIG_NETLABEL is not set
 # CONFIG_NETWORK_SECMARK is not set
 # CONFIG_NETFILTER is not set
 # CONFIG_IP_DCCP is not set
@@ -493,7 +518,10 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
 # CONFIG_LAPB is not set
 # CONFIG_ECONET is not set
 # CONFIG_WAN_ROUTER is not set
+# CONFIG_PHONET is not set
+# CONFIG_IEEE802154 is not set
 # CONFIG_NET_SCHED is not set
+# CONFIG_DCB is not set
 
 #
 # Network testing
@@ -548,14 +576,10 @@ CONFIG_SIR_BFIN_DMA=y
 # CONFIG_MCS_FIR is not set
 # CONFIG_BT is not set
 # CONFIG_AF_RXRPC is not set
-# CONFIG_PHONET is not set
-CONFIG_WIRELESS=y
-# CONFIG_CFG80211 is not set
-CONFIG_WIRELESS_OLD_REGULATORY=y
+# CONFIG_WIRELESS is not set
 CONFIG_WIRELESS_EXT=y
-CONFIG_WIRELESS_EXT_SYSFS=y
-# CONFIG_MAC80211 is not set
-# CONFIG_IEEE80211 is not set
+CONFIG_LIB80211=m
+# CONFIG_WIMAX is not set
 # CONFIG_RFKILL is not set
 # CONFIG_NET_9P is not set
 
@@ -578,6 +602,7 @@ CONFIG_EXTRA_FIRMWARE=""
 # CONFIG_CONNECTOR is not set
 CONFIG_MTD=y
 # CONFIG_MTD_DEBUG is not set
+# CONFIG_MTD_TESTS is not set
 # CONFIG_MTD_CONCAT is not set
 CONFIG_MTD_PARTITIONS=y
 # CONFIG_MTD_REDBOOT_PARTS is not set
@@ -653,7 +678,6 @@ CONFIG_MTD_NAND=y
 # CONFIG_MTD_NAND_VERIFY_WRITE is not set
 # CONFIG_MTD_NAND_ECC_SMC is not set
 # CONFIG_MTD_NAND_MUSEUM_IDS is not set
-# CONFIG_MTD_NAND_BFIN is not set
 CONFIG_MTD_NAND_IDS=y
 CONFIG_MTD_NAND_BF5XX=y
 CONFIG_MTD_NAND_BF5XX_HWECC=y
@@ -665,6 +689,11 @@ CONFIG_MTD_NAND_BF5XX_HWECC=y
 # CONFIG_MTD_ONENAND is not set
 
 #
+# LPDDR flash memory drivers
+#
+# CONFIG_MTD_LPDDR is not set
+
+#
 # UBI - Unsorted block images
 #
 # CONFIG_MTD_UBI is not set
@@ -682,10 +711,20 @@ CONFIG_BLK_DEV_RAM_SIZE=4096
 # CONFIG_ATA_OVER_ETH is not set
 # CONFIG_BLK_DEV_HD is not set
 CONFIG_MISC_DEVICES=y
-# CONFIG_EEPROM_93CX6 is not set
 # CONFIG_ICS932S401 is not set
 # CONFIG_ENCLOSURE_SERVICES is not set
+# CONFIG_ISL29003 is not set
+# CONFIG_AD525X_DPOT is not set
 # CONFIG_C2PORT is not set
+
+#
+# EEPROM support
+#
+# CONFIG_EEPROM_AT24 is not set
+# CONFIG_EEPROM_AT25 is not set
+# CONFIG_EEPROM_LEGACY is not set
+# CONFIG_EEPROM_MAX6875 is not set
+# CONFIG_EEPROM_93CX6 is not set
 CONFIG_HAVE_IDE=y
 # CONFIG_IDE is not set
 
@@ -709,10 +748,6 @@ CONFIG_BLK_DEV_SR=m
 # CONFIG_BLK_DEV_SR_VENDOR is not set
 # CONFIG_CHR_DEV_SG is not set
 # CONFIG_CHR_DEV_SCH is not set
-
-#
-# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
-#
 # CONFIG_SCSI_MULTI_LUN is not set
 # CONFIG_SCSI_CONSTANTS is not set
 # CONFIG_SCSI_LOGGING is not set
@@ -729,6 +764,7 @@ CONFIG_SCSI_WAIT_SCAN=m
 # CONFIG_SCSI_SRP_ATTRS is not set
 # CONFIG_SCSI_LOWLEVEL is not set
 # CONFIG_SCSI_DH is not set
+# CONFIG_SCSI_OSD_INITIATOR is not set
 CONFIG_ATA=y
 # CONFIG_ATA_NONSTANDARD is not set
 CONFIG_SATA_PMP=y
@@ -744,13 +780,34 @@ CONFIG_NETDEVICES=y
 # CONFIG_EQUALIZER is not set
 # CONFIG_TUN is not set
 # CONFIG_VETH is not set
-# CONFIG_PHYLIB is not set
+CONFIG_PHYLIB=y
+
+#
+# MII PHY device drivers
+#
+# CONFIG_MARVELL_PHY is not set
+# CONFIG_DAVICOM_PHY is not set
+# CONFIG_QSEMI_PHY is not set
+# CONFIG_LXT_PHY is not set
+# CONFIG_CICADA_PHY is not set
+# CONFIG_VITESSE_PHY is not set
+# CONFIG_SMSC_PHY is not set
+# CONFIG_BROADCOM_PHY is not set
+# CONFIG_ICPLUS_PHY is not set
+# CONFIG_REALTEK_PHY is not set
+# CONFIG_NATIONAL_PHY is not set
+# CONFIG_STE10XP is not set
+# CONFIG_LSI_ET1011C_PHY is not set
+# CONFIG_FIXED_PHY is not set
+# CONFIG_MDIO_BITBANG is not set
 CONFIG_NET_ETHERNET=y
 CONFIG_MII=y
 # CONFIG_SMC91X is not set
-CONFIG_SMSC911X=y
 # CONFIG_DM9000 is not set
 # CONFIG_ENC28J60 is not set
+# CONFIG_ETHOC is not set
+CONFIG_SMSC911X=y
+# CONFIG_DNET is not set
 # CONFIG_IBM_NEW_EMAC_ZMII is not set
 # CONFIG_IBM_NEW_EMAC_RGMII is not set
 # CONFIG_IBM_NEW_EMAC_TAH is not set
@@ -759,6 +816,8 @@ CONFIG_SMSC911X=y
 # CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
 # CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
 # CONFIG_B44 is not set
+# CONFIG_KS8842 is not set
+# CONFIG_KS8851 is not set
 # CONFIG_NETDEV_1000 is not set
 # CONFIG_NETDEV_10000 is not set
 
@@ -771,13 +830,16 @@ CONFIG_LIBERTAS=m
 # CONFIG_LIBERTAS_USB is not set
 CONFIG_LIBERTAS_SDIO=m
 CONFIG_POWEROF2_BLOCKSIZE_ONLY=y
+# CONFIG_LIBERTAS_SPI is not set
 # CONFIG_LIBERTAS_DEBUG is not set
 # CONFIG_USB_ZD1201 is not set
-# CONFIG_USB_NET_RNDIS_WLAN is not set
-# CONFIG_IWLWIFI_LEDS is not set
 # CONFIG_HOSTAP is not set
 
 #
+# Enable WiMAX (Networking options) to see the WiMAX drivers
+#
+
+#
 # USB Network Adapters
 #
 # CONFIG_USB_CATC is not set
@@ -813,28 +875,31 @@ CONFIG_INPUT_EVBUG=m
 # Input Device Drivers
 #
 CONFIG_INPUT_KEYBOARD=y
+# CONFIG_KEYBOARD_ADP5588 is not set
 # CONFIG_KEYBOARD_ATKBD is not set
-# CONFIG_KEYBOARD_SUNKBD is not set
+CONFIG_KEYBOARD_BFIN=y
 # CONFIG_KEYBOARD_LKKBD is not set
-# CONFIG_KEYBOARD_XTKBD is not set
-# CONFIG_KEYBOARD_NEWTON is not set
-# CONFIG_KEYBOARD_STOWAWAY is not set
 # CONFIG_KEYBOARD_GPIO is not set
-CONFIG_KEYBOARD_BFIN=y
+# CONFIG_KEYBOARD_MATRIX is not set
+# CONFIG_KEYBOARD_NEWTON is not set
 # CONFIG_KEYBOARD_OPENCORES is not set
-# CONFIG_KEYBOARD_ADP5588 is not set
+# CONFIG_KEYBOARD_STOWAWAY is not set
+# CONFIG_KEYBOARD_SUNKBD is not set
+# CONFIG_KEYBOARD_XTKBD is not set
 # CONFIG_INPUT_MOUSE is not set
 # CONFIG_INPUT_JOYSTICK is not set
 # CONFIG_INPUT_TABLET is not set
 CONFIG_INPUT_TOUCHSCREEN=y
+# CONFIG_TOUCHSCREEN_ADS7846 is not set
 CONFIG_TOUCHSCREEN_AD7877=m
 # CONFIG_TOUCHSCREEN_AD7879_I2C is not set
 # CONFIG_TOUCHSCREEN_AD7879_SPI is not set
 # CONFIG_TOUCHSCREEN_AD7879 is not set
-# CONFIG_TOUCHSCREEN_ADS7846 is not set
+# CONFIG_TOUCHSCREEN_EETI is not set
 # CONFIG_TOUCHSCREEN_FUJITSU is not set
 # CONFIG_TOUCHSCREEN_GUNZE is not set
 # CONFIG_TOUCHSCREEN_ELO is not set
+# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set
 # CONFIG_TOUCHSCREEN_MTOUCH is not set
 # CONFIG_TOUCHSCREEN_INEXIO is not set
 # CONFIG_TOUCHSCREEN_MK712 is not set
@@ -844,6 +909,8 @@ CONFIG_TOUCHSCREEN_AD7877=m
 # CONFIG_TOUCHSCREEN_WM97XX is not set
 # CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set
 # CONFIG_TOUCHSCREEN_TOUCHIT213 is not set
+# CONFIG_TOUCHSCREEN_TSC2007 is not set
+# CONFIG_TOUCHSCREEN_W90X900 is not set
 CONFIG_INPUT_MISC=y
 # CONFIG_INPUT_ATI_REMOTE is not set
 # CONFIG_INPUT_ATI_REMOTE2 is not set
@@ -852,7 +919,11 @@ CONFIG_INPUT_MISC=y
 # CONFIG_INPUT_YEALINK is not set
 # CONFIG_INPUT_CM109 is not set
 # CONFIG_INPUT_UINPUT is not set
-# CONFIG_CONFIG_INPUT_PCF8574 is not set
+# CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set
+# CONFIG_INPUT_BFIN_ROTARY is not set
+# CONFIG_INPUT_AD714X is not set
+# CONFIG_INPUT_ADXL34X is not set
+# CONFIG_INPUT_PCF8574 is not set
 
 #
 # Hardware I/O ports
@@ -863,16 +934,13 @@ CONFIG_INPUT_MISC=y
 #
 # Character devices
 #
-# CONFIG_AD9960 is not set
 CONFIG_BFIN_DMA_INTERFACE=m
 # CONFIG_BFIN_PPI is not set
 # CONFIG_BFIN_PPIFCD is not set
 # CONFIG_BFIN_SIMPLE_TIMER is not set
 # CONFIG_BFIN_SPI_ADC is not set
 CONFIG_BFIN_SPORT=m
-# CONFIG_BFIN_TIMER_LATENCY is not set
 # CONFIG_BFIN_TWI_LCD is not set
-CONFIG_SIMPLE_GPIO=m
 CONFIG_VT=y
 CONFIG_CONSOLE_TRANSLATIONS=y
 CONFIG_VT_CONSOLE=y
@@ -890,6 +958,7 @@ CONFIG_BFIN_JTAG_COMM=m
 #
 # Non-8250 serial port support
 #
+# CONFIG_SERIAL_MAX3100 is not set
 CONFIG_SERIAL_BFIN=y
 CONFIG_SERIAL_BFIN_CONSOLE=y
 CONFIG_SERIAL_BFIN_DMA=y
@@ -903,6 +972,7 @@ CONFIG_SERIAL_CORE=y
 CONFIG_SERIAL_CORE_CONSOLE=y
 # CONFIG_SERIAL_BFIN_SPORT is not set
 CONFIG_UNIX98_PTYS=y
+# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
 # CONFIG_LEGACY_PTYS is not set
 CONFIG_BFIN_OTP=y
 # CONFIG_BFIN_OTP_WRITE_ENABLE is not set
@@ -951,14 +1021,9 @@ CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=100
 # Miscellaneous I2C Chip support
 #
 # CONFIG_DS1682 is not set
-# CONFIG_EEPROM_AT24 is not set
-# CONFIG_SENSORS_AD5252 is not set
-# CONFIG_EEPROM_LEGACY is not set
 # CONFIG_SENSORS_PCF8574 is not set
 # CONFIG_PCF8575 is not set
 # CONFIG_SENSORS_PCA9539 is not set
-# CONFIG_SENSORS_PCF8591 is not set
-# CONFIG_SENSORS_MAX6875 is not set
 # CONFIG_SENSORS_TSL2550 is not set
 # CONFIG_I2C_DEBUG_CORE is not set
 # CONFIG_I2C_DEBUG_ALGO is not set
@@ -975,13 +1040,18 @@ CONFIG_SPI_BFIN=y
 # CONFIG_SPI_BFIN_LOCK is not set
 # CONFIG_SPI_BFIN_SPORT is not set
 # CONFIG_SPI_BITBANG is not set
+# CONFIG_SPI_GPIO is not set
 
 #
 # SPI Protocol Masters
 #
-# CONFIG_EEPROM_AT25 is not set
 # CONFIG_SPI_SPIDEV is not set
 # CONFIG_SPI_TLE62X0 is not set
+
+#
+# PPS support
+#
+# CONFIG_PPS is not set
 CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
 CONFIG_GPIOLIB=y
 # CONFIG_DEBUG_GPIO is not set
@@ -997,6 +1067,7 @@ CONFIG_GPIO_SYSFS=y
 # CONFIG_GPIO_MAX732X is not set
 # CONFIG_GPIO_PCA953X is not set
 # CONFIG_GPIO_PCF857X is not set
+# CONFIG_GPIO_ADP5588 is not set
 
 #
 # PCI GPIO expanders:
@@ -1038,28 +1109,19 @@ CONFIG_SSB_POSSIBLE=y
 # CONFIG_MFD_CORE is not set
 # CONFIG_MFD_SM501 is not set
 # CONFIG_HTC_PASIC3 is not set
+# CONFIG_UCB1400_CORE is not set
+# CONFIG_TPS65010 is not set
+# CONFIG_TWL4030_CORE is not set
 # CONFIG_MFD_TMIO is not set
 # CONFIG_PMIC_DA903X is not set
 # CONFIG_PMIC_ADP5520 is not set
 # CONFIG_MFD_WM8400 is not set
 # CONFIG_MFD_WM8350_I2C is not set
+# CONFIG_MFD_PCF50633 is not set
+# CONFIG_AB3100_CORE is not set
+# CONFIG_EZX_PCAP is not set
 # CONFIG_REGULATOR is not set
-
-#
-# Multimedia devices
-#
-
-#
-# Multimedia core support
-#
-# CONFIG_VIDEO_DEV is not set
-# CONFIG_DVB_CORE is not set
-# CONFIG_VIDEO_MEDIA is not set
-
-#
-# Multimedia drivers
-#
-# CONFIG_DAB is not set
+# CONFIG_MEDIA_SUPPORT is not set
 
 #
 # Graphics support
@@ -1096,6 +1158,7 @@ CONFIG_FB_BF54X_LQ043=y
 # CONFIG_FB_VIRTUAL is not set
 # CONFIG_FB_METRONOME is not set
 # CONFIG_FB_MB862XX is not set
+# CONFIG_FB_BROADSHEET is not set
 # CONFIG_BACKLIGHT_LCD_SUPPORT is not set
 
 #
@@ -1132,6 +1195,7 @@ CONFIG_SOUND_OSS_CORE=y
 CONFIG_SND=y
 CONFIG_SND_TIMER=y
 CONFIG_SND_PCM=y
+CONFIG_SND_JACK=y
 # CONFIG_SND_SEQUENCER is not set
 CONFIG_SND_OSSEMUL=y
 CONFIG_SND_MIXER_OSS=y
@@ -1142,6 +1206,11 @@ CONFIG_SND_SUPPORT_OLD_API=y
 CONFIG_SND_VERBOSE_PROCFS=y
 # CONFIG_SND_VERBOSE_PRINTK is not set
 # CONFIG_SND_DEBUG is not set
+# CONFIG_SND_RAWMIDI_SEQ is not set
+# CONFIG_SND_OPL3_LIB_SEQ is not set
+# CONFIG_SND_OPL4_LIB_SEQ is not set
+# CONFIG_SND_SBAWE_SEQ is not set
+# CONFIG_SND_EMU10K1_SEQ is not set
 CONFIG_SND_DRIVERS=y
 # CONFIG_SND_DUMMY is not set
 # CONFIG_SND_MTPAV is not set
@@ -1152,7 +1221,6 @@ CONFIG_SND_SPI=y
 #
 # ALSA Blackfin devices
 #
-# CONFIG_SND_BLACKFIN_AD1836 is not set
 # CONFIG_SND_BFIN_AD73322 is not set
 CONFIG_SND_USB=y
 # CONFIG_SND_USB_AUDIO is not set
@@ -1160,15 +1228,17 @@ CONFIG_SND_USB=y
 CONFIG_SND_SOC=y
 CONFIG_SND_SOC_AC97_BUS=y
 # CONFIG_SND_BF5XX_I2S is not set
+# CONFIG_SND_BF5XX_TDM is not set
 CONFIG_SND_BF5XX_AC97=y
 CONFIG_SND_BF5XX_MMAP_SUPPORT=y
 # CONFIG_SND_BF5XX_MULTICHAN_SUPPORT is not set
+CONFIG_SND_BF5XX_HAVE_COLD_RESET=y
+CONFIG_SND_BF5XX_RESET_GPIO_NUM=19
+CONFIG_SND_BF5XX_SOC_AD1980=y
 CONFIG_SND_BF5XX_SOC_SPORT=y
 CONFIG_SND_BF5XX_SOC_AC97=y
-CONFIG_SND_BF5XX_SOC_AD1980=y
 CONFIG_SND_BF5XX_SPORT_NUM=0
-CONFIG_SND_BF5XX_HAVE_COLD_RESET=y
-CONFIG_SND_BF5XX_RESET_GPIO_NUM=19
+CONFIG_SND_SOC_I2C_AND_SPI=y
 # CONFIG_SND_SOC_ALL_CODECS is not set
 CONFIG_SND_SOC_AD1980=y
 # CONFIG_SOUND_PRIME is not set
@@ -1188,30 +1258,34 @@ CONFIG_USB_HID=y
 #
 # Special HID drivers
 #
-CONFIG_HID_COMPAT=y
 CONFIG_HID_A4TECH=y
 CONFIG_HID_APPLE=y
 CONFIG_HID_BELKIN=y
-CONFIG_HID_BRIGHT=y
 CONFIG_HID_CHERRY=y
 CONFIG_HID_CHICONY=y
 CONFIG_HID_CYPRESS=y
-CONFIG_HID_DELL=y
+# CONFIG_HID_DRAGONRISE is not set
 CONFIG_HID_EZKEY=y
+# CONFIG_HID_KYE is not set
 CONFIG_HID_GYRATION=y
+# CONFIG_HID_KENSINGTON is not set
 CONFIG_HID_LOGITECH=y
 # CONFIG_LOGITECH_FF is not set
 # CONFIG_LOGIRUMBLEPAD2_FF is not set
 CONFIG_HID_MICROSOFT=y
 CONFIG_HID_MONTEREY=y
+# CONFIG_HID_NTRIG is not set
 CONFIG_HID_PANTHERLORD=y
 # CONFIG_PANTHERLORD_FF is not set
 CONFIG_HID_PETALYNX=y
 CONFIG_HID_SAMSUNG=y
 CONFIG_HID_SONY=y
 CONFIG_HID_SUNPLUS=y
-CONFIG_THRUSTMASTER_FF=m
-CONFIG_ZEROPLUS_FF=m
+# CONFIG_HID_GREENASIA is not set
+# CONFIG_HID_SMARTJOYPLUS is not set
+# CONFIG_HID_TOPSEED is not set
+# CONFIG_HID_THRUSTMASTER is not set
+# CONFIG_HID_ZEROPLUS is not set
 CONFIG_USB_SUPPORT=y
 CONFIG_USB_ARCH_HAS_HCD=y
 # CONFIG_USB_ARCH_HAS_OHCI is not set
@@ -1237,6 +1311,7 @@ CONFIG_USB_MON=y
 # USB Host Controller Drivers
 #
 # CONFIG_USB_C67X00_HCD is not set
+# CONFIG_USB_OXU210HP_HCD is not set
 # CONFIG_USB_ISP116X_HCD is not set
 # CONFIG_USB_ISP1760_HCD is not set
 # CONFIG_USB_ISP1362_HCD is not set
@@ -1267,18 +1342,17 @@ CONFIG_USB_INVENTRA_DMA=y
 # CONFIG_USB_TMC is not set
 
 #
-# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may also be needed;
+# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
 #
 
 #
-# see USB_STORAGE Help for more information
+# also be needed; see USB_STORAGE Help for more info
 #
 CONFIG_USB_STORAGE=y
 # CONFIG_USB_STORAGE_DEBUG is not set
 # CONFIG_USB_STORAGE_DATAFAB is not set
 # CONFIG_USB_STORAGE_FREECOM is not set
 # CONFIG_USB_STORAGE_ISD200 is not set
-# CONFIG_USB_STORAGE_DPCM is not set
 # CONFIG_USB_STORAGE_USBAT is not set
 # CONFIG_USB_STORAGE_SDDR09 is not set
 # CONFIG_USB_STORAGE_SDDR55 is not set
@@ -1314,7 +1388,6 @@ CONFIG_USB_STORAGE=y
 # CONFIG_USB_LED is not set
 # CONFIG_USB_CYPRESS_CY7C63 is not set
 # CONFIG_USB_CYTHERM is not set
-# CONFIG_USB_PHIDGET is not set
 # CONFIG_USB_IDMOUSE is not set
 # CONFIG_USB_FTDI_ELAN is not set
 # CONFIG_USB_APPLEDISPLAY is not set
@@ -1326,6 +1399,13 @@ CONFIG_USB_STORAGE=y
 # CONFIG_USB_ISIGHTFW is not set
 # CONFIG_USB_VST is not set
 # CONFIG_USB_GADGET is not set
+
+#
+# OTG and related infrastructure
+#
+CONFIG_USB_OTG_UTILS=y
+# CONFIG_USB_GPIO_VBUS is not set
+CONFIG_NOP_USB_XCEIV=y
 CONFIG_MMC=y
 # CONFIG_MMC_DEBUG is not set
 # CONFIG_MMC_UNSAFE_RESUME is not set
@@ -1380,6 +1460,7 @@ CONFIG_RTC_INTF_DEV=y
 # CONFIG_RTC_DRV_S35390A is not set
 # CONFIG_RTC_DRV_FM3130 is not set
 # CONFIG_RTC_DRV_RX8581 is not set
+# CONFIG_RTC_DRV_RX8025 is not set
 
 #
 # SPI RTC drivers
@@ -1411,10 +1492,21 @@ CONFIG_RTC_INTF_DEV=y
 #
 CONFIG_RTC_DRV_BFIN=y
 # CONFIG_DMADEVICES is not set
+# CONFIG_AUXDISPLAY is not set
 # CONFIG_UIO is not set
+
+#
+# TI VLYNQ
+#
 # CONFIG_STAGING is not set
 
 #
+# Firmware Drivers
+#
+# CONFIG_FIRMWARE_MEMMAP is not set
+# CONFIG_SIGMA is not set
+
+#
 # File systems
 #
 CONFIG_EXT2_FS=y
@@ -1427,9 +1519,11 @@ CONFIG_FS_MBCACHE=y
 # CONFIG_REISERFS_FS is not set
 # CONFIG_JFS_FS is not set
 # CONFIG_FS_POSIX_ACL is not set
-CONFIG_FILE_LOCKING=y
 # CONFIG_XFS_FS is not set
 # CONFIG_OCFS2_FS is not set
+# CONFIG_BTRFS_FS is not set
+CONFIG_FILE_LOCKING=y
+CONFIG_FSNOTIFY=y
 # CONFIG_DNOTIFY is not set
 CONFIG_INOTIFY=y
 CONFIG_INOTIFY_USER=y
@@ -1439,6 +1533,11 @@ CONFIG_INOTIFY_USER=y
 # CONFIG_FUSE_FS is not set
 
 #
+# Caches
+#
+# CONFIG_FSCACHE is not set
+
+#
 # CD-ROM/DVD Filesystems
 #
 CONFIG_ISO9660_FS=m
@@ -1467,10 +1566,7 @@ CONFIG_SYSFS=y
 # CONFIG_TMPFS is not set
 # CONFIG_HUGETLB_PAGE is not set
 # CONFIG_CONFIGFS_FS is not set
-
-#
-# Miscellaneous filesystems
-#
+CONFIG_MISC_FILESYSTEMS=y
 # CONFIG_ADFS_FS is not set
 # CONFIG_AFFS_FS is not set
 # CONFIG_HFS_FS is not set
@@ -1489,17 +1585,8 @@ CONFIG_JFFS2_ZLIB=y
 # CONFIG_JFFS2_LZO is not set
 CONFIG_JFFS2_RTIME=y
 # CONFIG_JFFS2_RUBIN is not set
-CONFIG_YAFFS_FS=m
-CONFIG_YAFFS_YAFFS1=y
-# CONFIG_YAFFS_9BYTE_TAGS is not set
-# CONFIG_YAFFS_DOES_ECC is not set
-CONFIG_YAFFS_YAFFS2=y
-CONFIG_YAFFS_AUTO_YAFFS2=y
-# CONFIG_YAFFS_DISABLE_LAZY_LOAD is not set
-# CONFIG_YAFFS_DISABLE_WIDE_TNODES is not set
-# CONFIG_YAFFS_ALWAYS_CHECK_CHUNK_ERASED is not set
-CONFIG_YAFFS_SHORT_NAMES_IN_RAM=y
 # CONFIG_CRAMFS is not set
+# CONFIG_SQUASHFS is not set
 # CONFIG_VXFS_FS is not set
 # CONFIG_MINIX_FS is not set
 # CONFIG_OMFS_FS is not set
@@ -1508,6 +1595,7 @@ CONFIG_YAFFS_SHORT_NAMES_IN_RAM=y
 # CONFIG_ROMFS_FS is not set
 # CONFIG_SYSV_FS is not set
 # CONFIG_UFS_FS is not set
+# CONFIG_NILFS2_FS is not set
 CONFIG_NETWORK_FILESYSTEMS=y
 CONFIG_NFS_FS=m
 CONFIG_NFS_V3=y
@@ -1522,7 +1610,6 @@ CONFIG_LOCKD_V4=y
 CONFIG_EXPORTFS=m
 CONFIG_NFS_COMMON=y
 CONFIG_SUNRPC=m
-# CONFIG_SUNRPC_REGISTER_V4 is not set
 # CONFIG_RPCSEC_GSS_KRB5 is not set
 # CONFIG_RPCSEC_GSS_SPKM3 is not set
 CONFIG_SMB_FS=m
@@ -1596,11 +1683,15 @@ CONFIG_FRAME_WARN=1024
 # CONFIG_UNUSED_SYMBOLS is not set
 CONFIG_DEBUG_FS=y
 # CONFIG_HEADERS_CHECK is not set
+CONFIG_DEBUG_SECTION_MISMATCH=y
 CONFIG_DEBUG_KERNEL=y
 CONFIG_DEBUG_SHIRQ=y
 CONFIG_DETECT_SOFTLOCKUP=y
 # CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
 CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
+CONFIG_DETECT_HUNG_TASK=y
+# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set
+CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0
 CONFIG_SCHED_DEBUG=y
 # CONFIG_SCHEDSTATS is not set
 # CONFIG_TIMER_STATS is not set
@@ -1608,16 +1699,21 @@ CONFIG_SCHED_DEBUG=y
 # CONFIG_DEBUG_SLAB is not set
 # CONFIG_DEBUG_SPINLOCK is not set
 # CONFIG_DEBUG_MUTEXES is not set
+# CONFIG_DEBUG_LOCK_ALLOC is not set
+# CONFIG_PROVE_LOCKING is not set
+# CONFIG_LOCK_STAT is not set
 # CONFIG_DEBUG_SPINLOCK_SLEEP is not set
 # CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
 # CONFIG_DEBUG_KOBJECT is not set
 CONFIG_DEBUG_BUGVERBOSE=y
 CONFIG_DEBUG_INFO=y
 # CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_NOMMU_REGIONS is not set
 # CONFIG_DEBUG_WRITECOUNT is not set
 # CONFIG_DEBUG_MEMORY_INIT is not set
 # CONFIG_DEBUG_LIST is not set
 # CONFIG_DEBUG_SG is not set
+# CONFIG_DEBUG_NOTIFIERS is not set
 # CONFIG_FRAME_POINTER is not set
 # CONFIG_BOOT_PRINTK_DELAY is not set
 # CONFIG_RCU_TORTURE_TEST is not set
@@ -1625,17 +1721,16 @@ CONFIG_DEBUG_INFO=y
 # CONFIG_BACKTRACE_SELF_TEST is not set
 # CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
 # CONFIG_FAULT_INJECTION is not set
-
-#
-# Tracers
-#
-# CONFIG_SCHED_TRACER is not set
-# CONFIG_CONTEXT_SWITCH_TRACER is not set
-# CONFIG_BOOT_TRACER is not set
-# CONFIG_DYNAMIC_PRINTK_DEBUG is not set
+# CONFIG_PAGE_POISONING is not set
+CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
+CONFIG_TRACING_SUPPORT=y
+# CONFIG_FTRACE is not set
+# CONFIG_DYNAMIC_DEBUG is not set
 # CONFIG_SAMPLES is not set
 CONFIG_HAVE_ARCH_KGDB=y
 # CONFIG_KGDB is not set
+# CONFIG_KMEMCHECK is not set
 # CONFIG_DEBUG_STACKOVERFLOW is not set
 # CONFIG_DEBUG_STACK_USAGE is not set
 CONFIG_DEBUG_VERBOSE=y
@@ -1657,17 +1752,15 @@ CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE=y
 CONFIG_EARLY_PRINTK=y
 CONFIG_CPLB_INFO=y
 CONFIG_ACCESS_CHECK=y
+# CONFIG_BFIN_ISRAM_SELF_TEST is not set
 
 #
 # Security options
 #
 # CONFIG_KEYS is not set
-CONFIG_SECURITY=y
+# CONFIG_SECURITY is not set
 # CONFIG_SECURITYFS is not set
-# CONFIG_SECURITY_NETWORK is not set
 # CONFIG_SECURITY_FILE_CAPABILITIES is not set
-# CONFIG_SECURITY_ROOTPLUG is not set
-CONFIG_SECURITY_DEFAULT_MMAP_MIN_ADDR=0
 CONFIG_CRYPTO=y
 
 #
@@ -1746,6 +1839,7 @@ CONFIG_CRYPTO=y
 # Compression
 #
 # CONFIG_CRYPTO_DEFLATE is not set
+# CONFIG_CRYPTO_ZLIB is not set
 # CONFIG_CRYPTO_LZO is not set
 
 #
@@ -1753,11 +1847,13 @@ CONFIG_CRYPTO=y
 #
 # CONFIG_CRYPTO_ANSI_CPRNG is not set
 CONFIG_CRYPTO_HW=y
+# CONFIG_BINARY_PRINTF is not set
 
 #
 # Library routines
 #
 CONFIG_BITREVERSE=y
+CONFIG_GENERIC_FIND_LAST_BIT=y
 CONFIG_CRC_CCITT=m
 # CONFIG_CRC16 is not set
 # CONFIG_CRC_T10DIF is not set
@@ -1767,6 +1863,8 @@ CONFIG_CRC32=y
 # CONFIG_LIBCRC32C is not set
 CONFIG_ZLIB_INFLATE=y
 CONFIG_ZLIB_DEFLATE=m
+CONFIG_DECOMPRESS_GZIP=y
 CONFIG_HAS_IOMEM=y
 CONFIG_HAS_IOPORT=y
 CONFIG_HAS_DMA=y
+CONFIG_NLATTR=y
diff --git a/arch/blackfin/configs/BF561-ACVILON_defconfig b/arch/blackfin/configs/BF561-ACVILON_defconfig
new file mode 100644
index 000000000000..b9b0f93d0bd3
--- /dev/null
+++ b/arch/blackfin/configs/BF561-ACVILON_defconfig
@@ -0,0 +1,1643 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.31.4
+# Sat Oct 24 12:15:32 2009
+#
+# CONFIG_MMU is not set
+# CONFIG_FPU is not set
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
+CONFIG_BLACKFIN=y
+CONFIG_GENERIC_CSUM=y
+CONFIG_GENERIC_BUG=y
+CONFIG_ZONE_DMA=y
+CONFIG_GENERIC_FIND_NEXT_BIT=y
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
+CONFIG_GENERIC_GPIO=y
+CONFIG_FORCE_MAX_ZONEORDER=14
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+CONFIG_CONSTRUCTORS=y
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION=""
+CONFIG_LOCALVERSION_AUTO=y
+CONFIG_HAVE_KERNEL_GZIP=y
+CONFIG_HAVE_KERNEL_BZIP2=y
+CONFIG_HAVE_KERNEL_LZMA=y
+CONFIG_KERNEL_GZIP=y
+# CONFIG_KERNEL_BZIP2 is not set
+# CONFIG_KERNEL_LZMA is not set
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+# CONFIG_POSIX_MQUEUE is not set
+# CONFIG_BSD_PROCESS_ACCT is not set
+# CONFIG_TASKSTATS is not set
+# CONFIG_AUDIT is not set
+
+#
+# RCU Subsystem
+#
+CONFIG_CLASSIC_RCU=y
+# CONFIG_TREE_RCU is not set
+# CONFIG_PREEMPT_RCU is not set
+# CONFIG_TREE_RCU_TRACE is not set
+# CONFIG_PREEMPT_RCU_TRACE is not set
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_GROUP_SCHED is not set
+# CONFIG_CGROUPS is not set
+CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SYSFS_DEPRECATED_V2=y
+# CONFIG_RELAY is not set
+# CONFIG_NAMESPACES is not set
+# CONFIG_BLK_DEV_INITRD is not set
+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+CONFIG_SYSCTL=y
+CONFIG_ANON_INODES=y
+CONFIG_EMBEDDED=y
+CONFIG_UID16=y
+# CONFIG_SYSCTL_SYSCALL is not set
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_ALL is not set
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+# CONFIG_ELF_CORE is not set
+CONFIG_BASE_FULL=y
+# CONFIG_FUTEX is not set
+CONFIG_EPOLL=y
+# CONFIG_SIGNALFD is not set
+# CONFIG_TIMERFD is not set
+# CONFIG_EVENTFD is not set
+# CONFIG_AIO is not set
+
+#
+# Performance Counters
+#
+CONFIG_VM_EVENT_COUNTERS=y
+# CONFIG_STRIP_ASM_SYMS is not set
+CONFIG_COMPAT_BRK=y
+CONFIG_SLAB=y
+# CONFIG_SLUB is not set
+# CONFIG_SLOB is not set
+# CONFIG_MMAP_ALLOW_UNINITIALIZED is not set
+# CONFIG_PROFILING is not set
+# CONFIG_MARKERS is not set
+CONFIG_HAVE_OPROFILE=y
+
+#
+# GCOV-based kernel profiling
+#
+# CONFIG_GCOV_KERNEL is not set
+# CONFIG_SLOW_WORK is not set
+# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
+CONFIG_SLABINFO=y
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+# CONFIG_MODULE_FORCE_LOAD is not set
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODULE_FORCE_UNLOAD is not set
+# CONFIG_MODVERSIONS is not set
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+CONFIG_BLOCK=y
+CONFIG_LBDAF=y
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_BLK_DEV_INTEGRITY is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+# CONFIG_IOSCHED_DEADLINE is not set
+CONFIG_IOSCHED_CFQ=y
+CONFIG_DEFAULT_AS=y
+# CONFIG_DEFAULT_DEADLINE is not set
+# CONFIG_DEFAULT_CFQ is not set
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="anticipatory"
+# CONFIG_PREEMPT_NONE is not set
+CONFIG_PREEMPT_VOLUNTARY=y
+# CONFIG_PREEMPT is not set
+# CONFIG_FREEZER is not set
+
+#
+# Blackfin Processor Options
+#
+
+#
+# Processor and Board Settings
+#
+# CONFIG_BF512 is not set
+# CONFIG_BF514 is not set
+# CONFIG_BF516 is not set
+# CONFIG_BF518 is not set
+# CONFIG_BF522 is not set
+# CONFIG_BF523 is not set
+# CONFIG_BF524 is not set
+# CONFIG_BF525 is not set
+# CONFIG_BF526 is not set
+# CONFIG_BF527 is not set
+# CONFIG_BF531 is not set
+# CONFIG_BF532 is not set
+# CONFIG_BF533 is not set
+# CONFIG_BF534 is not set
+# CONFIG_BF536 is not set
+# CONFIG_BF537 is not set
+# CONFIG_BF538 is not set
+# CONFIG_BF539 is not set
+# CONFIG_BF542 is not set
+# CONFIG_BF542M is not set
+# CONFIG_BF544 is not set
+# CONFIG_BF544M is not set
+# CONFIG_BF547 is not set
+# CONFIG_BF547M is not set
+# CONFIG_BF548 is not set
+# CONFIG_BF548M is not set
+# CONFIG_BF549 is not set
+# CONFIG_BF549M is not set
+CONFIG_BF561=y
+# CONFIG_SMP is not set
+CONFIG_BF_REV_MIN=3
+CONFIG_BF_REV_MAX=5
+# CONFIG_BF_REV_0_0 is not set
+# CONFIG_BF_REV_0_1 is not set
+# CONFIG_BF_REV_0_2 is not set
+# CONFIG_BF_REV_0_3 is not set
+# CONFIG_BF_REV_0_4 is not set
+CONFIG_BF_REV_0_5=y
+# CONFIG_BF_REV_0_6 is not set
+# CONFIG_BF_REV_ANY is not set
+# CONFIG_BF_REV_NONE is not set
+CONFIG_IRQ_PLL_WAKEUP=7
+CONFIG_IRQ_SPORT0_ERROR=7
+CONFIG_IRQ_SPORT1_ERROR=7
+CONFIG_IRQ_TIMER0=10
+CONFIG_IRQ_TIMER1=10
+CONFIG_IRQ_TIMER2=10
+CONFIG_IRQ_TIMER3=10
+CONFIG_IRQ_TIMER4=10
+CONFIG_IRQ_TIMER5=10
+CONFIG_IRQ_TIMER6=10
+CONFIG_IRQ_TIMER7=10
+CONFIG_IRQ_SPI_ERROR=7
+# CONFIG_BFIN561_EZKIT is not set
+# CONFIG_BFIN561_TEPLA is not set
+# CONFIG_BFIN561_BLUETECHNIX_CM is not set
+CONFIG_BFIN561_ACVILON=y
+
+#
+# BF561 Specific Configuration
+#
+
+#
+# Core B Support
+#
+# CONFIG_BF561_COREB is not set
+
+#
+# Interrupt Priority Assignment
+#
+
+#
+# Priority
+#
+CONFIG_IRQ_DMA1_ERROR=7
+CONFIG_IRQ_DMA2_ERROR=7
+CONFIG_IRQ_IMDMA_ERROR=7
+CONFIG_IRQ_PPI0_ERROR=7
+CONFIG_IRQ_PPI1_ERROR=7
+CONFIG_IRQ_UART_ERROR=7
+CONFIG_IRQ_RESERVED_ERROR=7
+CONFIG_IRQ_DMA1_0=8
+CONFIG_IRQ_DMA1_1=8
+CONFIG_IRQ_DMA1_2=8
+CONFIG_IRQ_DMA1_3=8
+CONFIG_IRQ_DMA1_4=8
+CONFIG_IRQ_DMA1_5=8
+CONFIG_IRQ_DMA1_6=8
+CONFIG_IRQ_DMA1_7=8
+CONFIG_IRQ_DMA1_8=8
+CONFIG_IRQ_DMA1_9=8
+CONFIG_IRQ_DMA1_10=8
+CONFIG_IRQ_DMA1_11=8
+CONFIG_IRQ_DMA2_0=9
+CONFIG_IRQ_DMA2_1=9
+CONFIG_IRQ_DMA2_2=9
+CONFIG_IRQ_DMA2_3=9
+CONFIG_IRQ_DMA2_4=9
+CONFIG_IRQ_DMA2_5=9
+CONFIG_IRQ_DMA2_6=9
+CONFIG_IRQ_DMA2_7=9
+CONFIG_IRQ_DMA2_8=9
+CONFIG_IRQ_DMA2_9=9
+CONFIG_IRQ_DMA2_10=9
+CONFIG_IRQ_DMA2_11=9
+CONFIG_IRQ_TIMER8=10
+CONFIG_IRQ_TIMER9=10
+CONFIG_IRQ_TIMER10=10
+CONFIG_IRQ_TIMER11=10
+CONFIG_IRQ_PROG0_INTA=11
+CONFIG_IRQ_PROG0_INTB=11
+CONFIG_IRQ_PROG1_INTA=11
+CONFIG_IRQ_PROG1_INTB=11
+CONFIG_IRQ_PROG2_INTA=11
+CONFIG_IRQ_PROG2_INTB=11
+CONFIG_IRQ_DMA1_WRRD0=8
+CONFIG_IRQ_DMA1_WRRD1=8
+CONFIG_IRQ_DMA2_WRRD0=9
+CONFIG_IRQ_DMA2_WRRD1=9
+CONFIG_IRQ_IMDMA_WRRD0=12
+CONFIG_IRQ_IMDMA_WRRD1=12
+CONFIG_IRQ_WDTIMER=13
+
+#
+# Board customizations
+#
+# CONFIG_CMDLINE_BOOL is not set
+CONFIG_BOOT_LOAD=0x1000
+
+#
+# Clock/PLL Setup
+#
+CONFIG_CLKIN_HZ=12000000
+# CONFIG_BFIN_KERNEL_CLOCK is not set
+CONFIG_MAX_VCO_HZ=600000000
+CONFIG_MIN_VCO_HZ=50000000
+CONFIG_MAX_SCLK_HZ=133333333
+CONFIG_MIN_SCLK_HZ=27000000
+
+#
+# Kernel Timer/Scheduler
+#
+# CONFIG_HZ_100 is not set
+CONFIG_HZ_250=y
+# CONFIG_HZ_300 is not set
+# CONFIG_HZ_1000 is not set
+CONFIG_HZ=250
+CONFIG_SCHED_HRTICK=y
+CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+# CONFIG_TICKSOURCE_GPTMR0 is not set
+CONFIG_TICKSOURCE_CORETMR=y
+CONFIG_CYCLES_CLOCKSOURCE=y
+# CONFIG_GPTMR0_CLOCKSOURCE is not set
+CONFIG_TICK_ONESHOT=y
+# CONFIG_NO_HZ is not set
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+
+#
+# Misc
+#
+CONFIG_BFIN_SCRATCH_REG_RETN=y
+# CONFIG_BFIN_SCRATCH_REG_RETE is not set
+# CONFIG_BFIN_SCRATCH_REG_CYCLES is not set
+
+#
+# Blackfin Kernel Optimizations
+#
+
+#
+# Memory Optimizations
+#
+CONFIG_I_ENTRY_L1=y
+CONFIG_EXCPT_IRQ_SYSC_L1=y
+CONFIG_DO_IRQ_L1=y
+CONFIG_CORE_TIMER_IRQ_L1=y
+CONFIG_IDLE_L1=y
+CONFIG_SCHEDULE_L1=y
+CONFIG_ARITHMETIC_OPS_L1=y
+CONFIG_ACCESS_OK_L1=y
+CONFIG_MEMSET_L1=y
+CONFIG_MEMCPY_L1=y
+CONFIG_SYS_BFIN_SPINLOCK_L1=y
+# CONFIG_IP_CHECKSUM_L1 is not set
+CONFIG_CACHELINE_ALIGNED_L1=y
+# CONFIG_SYSCALL_TAB_L1 is not set
+# CONFIG_CPLB_SWITCH_TAB_L1 is not set
+CONFIG_APP_STACK_L1=y
+
+#
+# Speed Optimizations
+#
+CONFIG_BFIN_INS_LOWOVERHEAD=y
+CONFIG_RAMKERNEL=y
+# CONFIG_ROMKERNEL is not set
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_SPLIT_PTLOCK_CPUS=4
+# CONFIG_PHYS_ADDR_T_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=1
+CONFIG_VIRT_TO_BUS=y
+CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
+CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0
+CONFIG_BFIN_GPTIMERS=y
+CONFIG_DMA_UNCACHED_4M=y
+# CONFIG_DMA_UNCACHED_2M is not set
+# CONFIG_DMA_UNCACHED_1M is not set
+# CONFIG_DMA_UNCACHED_NONE is not set
+
+#
+# Cache Support
+#
+CONFIG_BFIN_ICACHE=y
+CONFIG_BFIN_EXTMEM_ICACHEABLE=y
+# CONFIG_BFIN_L2_ICACHEABLE is not set
+CONFIG_BFIN_DCACHE=y
+# CONFIG_BFIN_DCACHE_BANKA is not set
+CONFIG_BFIN_EXTMEM_DCACHEABLE=y
+CONFIG_BFIN_EXTMEM_WRITEBACK=y
+# CONFIG_BFIN_EXTMEM_WRITETHROUGH is not set
+# CONFIG_BFIN_L2_DCACHEABLE is not set
+
+#
+# Memory Protection Unit
+#
+# CONFIG_MPU is not set
+
+#
+# Asynchronous Memory Configuration
+#
+
+#
+# EBIU_AMGCTL Global Control
+#
+CONFIG_C_AMCKEN=y
+CONFIG_C_CDPRIO=y
+CONFIG_C_B0PEN=y
+CONFIG_C_B1PEN=y
+CONFIG_C_B2PEN=y
+# CONFIG_C_B3PEN is not set
+# CONFIG_C_AMBEN is not set
+# CONFIG_C_AMBEN_B0 is not set
+# CONFIG_C_AMBEN_B0_B1 is not set
+# CONFIG_C_AMBEN_B0_B1_B2 is not set
+CONFIG_C_AMBEN_ALL=y
+
+#
+# EBIU_AMBCTL Control
+#
+CONFIG_BANK_0=0x99b2
+CONFIG_BANK_1=0x3350
+CONFIG_BANK_2=0x7BB0
+CONFIG_BANK_3=0xAAC2
+
+#
+# Bus options (PCI, PCMCIA, EISA, MCA, ISA)
+#
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+# CONFIG_PCCARD is not set
+
+#
+# Executable file formats
+#
+CONFIG_BINFMT_ELF_FDPIC=y
+CONFIG_BINFMT_FLAT=y
+CONFIG_BINFMT_ZFLAT=y
+# CONFIG_BINFMT_SHARED_FLAT is not set
+# CONFIG_HAVE_AOUT is not set
+# CONFIG_BINFMT_MISC is not set
+
+#
+# Power management options
+#
+# CONFIG_PM is not set
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+
+#
+# CPU Frequency scaling
+#
+# CONFIG_CPU_FREQ is not set
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+# CONFIG_PACKET_MMAP is not set
+CONFIG_UNIX=y
+CONFIG_XFRM=y
+# CONFIG_XFRM_USER is not set
+# CONFIG_XFRM_SUB_POLICY is not set
+# CONFIG_XFRM_MIGRATE is not set
+# CONFIG_XFRM_STATISTICS is not set
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+# CONFIG_IP_MULTICAST is not set
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
+CONFIG_IP_PNP=y
+# CONFIG_IP_PNP_DHCP is not set
+# CONFIG_IP_PNP_BOOTP is not set
+# CONFIG_IP_PNP_RARP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_ARPD is not set
+CONFIG_SYN_COOKIES=y
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
+# CONFIG_INET_TUNNEL is not set
+CONFIG_INET_XFRM_MODE_TRANSPORT=y
+CONFIG_INET_XFRM_MODE_TUNNEL=y
+CONFIG_INET_XFRM_MODE_BEET=y
+# CONFIG_INET_LRO is not set
+CONFIG_INET_DIAG=y
+CONFIG_INET_TCP_DIAG=y
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+# CONFIG_IPV6 is not set
+# CONFIG_NETLABEL is not set
+# CONFIG_NETWORK_SECMARK is not set
+# CONFIG_NETFILTER is not set
+# CONFIG_IP_DCCP is not set
+# CONFIG_IP_SCTP is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_NET_DSA is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_PHONET is not set
+# CONFIG_IEEE802154 is not set
+# CONFIG_NET_SCHED is not set
+# CONFIG_DCB is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+# CONFIG_AF_RXRPC is not set
+# CONFIG_WIRELESS is not set
+# CONFIG_WIMAX is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+# CONFIG_FW_LOADER is not set
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
+# CONFIG_SYS_HYPERVISOR is not set
+# CONFIG_CONNECTOR is not set
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+# CONFIG_MTD_TESTS is not set
+# CONFIG_MTD_CONCAT is not set
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_REDBOOT_PARTS is not set
+CONFIG_MTD_CMDLINE_PARTS=y
+# CONFIG_MTD_AR7_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+# CONFIG_MTD_CFI is not set
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+CONFIG_MTD_RAM=y
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+# CONFIG_MTD_UCLINUX is not set
+CONFIG_MTD_PLATRAM=y
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_DATAFLASH is not set
+# CONFIG_MTD_M25P80 is not set
+# CONFIG_MTD_SLRAM is not set
+CONFIG_MTD_PHRAM=y
+# CONFIG_MTD_MTDRAM is not set
+CONFIG_MTD_BLOCK2MTD=y
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+CONFIG_MTD_NAND=y
+CONFIG_MTD_NAND_VERIFY_WRITE=y
+# CONFIG_MTD_NAND_ECC_SMC is not set
+# CONFIG_MTD_NAND_MUSEUM_IDS is not set
+CONFIG_MTD_NAND_IDS=y
+# CONFIG_MTD_NAND_DISKONCHIP is not set
+# CONFIG_MTD_NAND_NANDSIM is not set
+CONFIG_MTD_NAND_PLATFORM=y
+# CONFIG_MTD_ALAUDA is not set
+# CONFIG_MTD_ONENAND is not set
+
+#
+# LPDDR flash memory drivers
+#
+# CONFIG_MTD_LPDDR is not set
+
+#
+# UBI - Unsorted block images
+#
+# CONFIG_MTD_UBI is not set
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=y
+# CONFIG_BLK_DEV_CRYPTOLOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_UB is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=2
+CONFIG_BLK_DEV_RAM_SIZE=16384
+# CONFIG_BLK_DEV_XIP is not set
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+# CONFIG_BLK_DEV_HD is not set
+# CONFIG_MISC_DEVICES is not set
+CONFIG_HAVE_IDE=y
+# CONFIG_IDE is not set
+
+#
+# SCSI device support
+#
+# CONFIG_RAID_ATTRS is not set
+CONFIG_SCSI=y
+CONFIG_SCSI_DMA=y
+# CONFIG_SCSI_TGT is not set
+# CONFIG_SCSI_NETLINK is not set
+# CONFIG_SCSI_PROC_FS is not set
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+# CONFIG_BLK_DEV_SR is not set
+# CONFIG_CHR_DEV_SG is not set
+# CONFIG_CHR_DEV_SCH is not set
+# CONFIG_SCSI_MULTI_LUN is not set
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+# CONFIG_SCSI_SCAN_ASYNC is not set
+CONFIG_SCSI_WAIT_SCAN=y
+
+#
+# SCSI Transports
+#
+# CONFIG_SCSI_SPI_ATTRS is not set
+# CONFIG_SCSI_FC_ATTRS is not set
+# CONFIG_SCSI_ISCSI_ATTRS is not set
+# CONFIG_SCSI_SAS_LIBSAS is not set
+# CONFIG_SCSI_SRP_ATTRS is not set
+# CONFIG_SCSI_LOWLEVEL is not set
+# CONFIG_SCSI_DH is not set
+# CONFIG_SCSI_OSD_INITIATOR is not set
+# CONFIG_ATA is not set
+# CONFIG_MD is not set
+CONFIG_NETDEVICES=y
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_VETH is not set
+CONFIG_PHYLIB=y
+
+#
+# MII PHY device drivers
+#
+# CONFIG_MARVELL_PHY is not set
+# CONFIG_DAVICOM_PHY is not set
+# CONFIG_QSEMI_PHY is not set
+# CONFIG_LXT_PHY is not set
+# CONFIG_CICADA_PHY is not set
+# CONFIG_VITESSE_PHY is not set
+# CONFIG_SMSC_PHY is not set
+# CONFIG_BROADCOM_PHY is not set
+# CONFIG_ICPLUS_PHY is not set
+# CONFIG_REALTEK_PHY is not set
+# CONFIG_NATIONAL_PHY is not set
+# CONFIG_STE10XP is not set
+# CONFIG_LSI_ET1011C_PHY is not set
+# CONFIG_FIXED_PHY is not set
+# CONFIG_MDIO_BITBANG is not set
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
+# CONFIG_SMC91X is not set
+# CONFIG_DM9000 is not set
+# CONFIG_ENC28J60 is not set
+# CONFIG_ETHOC is not set
+CONFIG_SMSC911X=y
+# CONFIG_DNET is not set
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
+# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
+# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
+# CONFIG_B44 is not set
+# CONFIG_KS8842 is not set
+# CONFIG_KS8851 is not set
+# CONFIG_NETDEV_1000 is not set
+# CONFIG_NETDEV_10000 is not set
+
+#
+# Wireless LAN
+#
+# CONFIG_WLAN_PRE80211 is not set
+# CONFIG_WLAN_80211 is not set
+
+#
+# Enable WiMAX (Networking options) to see the WiMAX drivers
+#
+
+#
+# USB Network Adapters
+#
+# CONFIG_USB_CATC is not set
+# CONFIG_USB_KAWETH is not set
+# CONFIG_USB_PEGASUS is not set
+# CONFIG_USB_RTL8150 is not set
+# CONFIG_USB_USBNET is not set
+# CONFIG_WAN is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_ISDN is not set
+# CONFIG_PHONE is not set
+
+#
+# Input device support
+#
+# CONFIG_INPUT is not set
+
+#
+# Hardware I/O ports
+#
+# CONFIG_SERIO is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+# CONFIG_BFIN_DMA_INTERFACE is not set
+# CONFIG_BFIN_PPI is not set
+# CONFIG_BFIN_PPIFCD is not set
+CONFIG_BFIN_SIMPLE_TIMER=y
+# CONFIG_BFIN_SPI_ADC is not set
+# CONFIG_BFIN_SPORT is not set
+# CONFIG_BFIN_TWI_LCD is not set
+# CONFIG_VT is not set
+# CONFIG_DEVKMEM is not set
+# CONFIG_BFIN_JTAG_COMM is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+# CONFIG_SERIAL_8250 is not set
+
+#
+# Non-8250 serial port support
+#
+# CONFIG_SERIAL_MAX3100 is not set
+CONFIG_SERIAL_BFIN=y
+CONFIG_SERIAL_BFIN_CONSOLE=y
+# CONFIG_SERIAL_BFIN_DMA is not set
+CONFIG_SERIAL_BFIN_PIO=y
+CONFIG_SERIAL_BFIN_UART0=y
+# CONFIG_BFIN_UART0_CTSRTS is not set
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+# CONFIG_SERIAL_BFIN_SPORT is not set
+CONFIG_UNIX98_PTYS=y
+# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
+CONFIG_LEGACY_PTYS=y
+CONFIG_LEGACY_PTY_COUNT=256
+
+#
+# CAN, the car bus and industrial fieldbus
+#
+# CONFIG_CAN4LINUX is not set
+# CONFIG_IPMI_HANDLER is not set
+# CONFIG_HW_RANDOM is not set
+# CONFIG_R3964 is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_HELPER_AUTO=y
+CONFIG_I2C_ALGOPCA=y
+
+#
+# I2C Hardware Bus support
+#
+
+#
+# I2C system bus drivers (mostly embedded / system-on-chip)
+#
+# CONFIG_I2C_GPIO is not set
+# CONFIG_I2C_OCORES is not set
+# CONFIG_I2C_SIMTEC is not set
+
+#
+# External I2C/SMBus adapter drivers
+#
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_TAOS_EVM is not set
+# CONFIG_I2C_TINY_USB is not set
+
+#
+# Other I2C/SMBus bus drivers
+#
+CONFIG_I2C_PCA_PLATFORM=y
+# CONFIG_I2C_STUB is not set
+
+#
+# Miscellaneous I2C Chip support
+#
+# CONFIG_DS1682 is not set
+# CONFIG_SENSORS_PCA9539 is not set
+# CONFIG_SENSORS_TSL2550 is not set
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+# CONFIG_I2C_DEBUG_CHIP is not set
+CONFIG_SPI=y
+# CONFIG_SPI_DEBUG is not set
+CONFIG_SPI_MASTER=y
+
+#
+# SPI Master Controller Drivers
+#
+CONFIG_SPI_BFIN=y
+# CONFIG_SPI_BFIN_LOCK is not set
+# CONFIG_SPI_BFIN_SPORT is not set
+# CONFIG_SPI_BITBANG is not set
+# CONFIG_SPI_GPIO is not set
+
+#
+# SPI Protocol Masters
+#
+CONFIG_SPI_SPIDEV=y
+# CONFIG_SPI_TLE62X0 is not set
+
+#
+# PPS support
+#
+# CONFIG_PPS is not set
+CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
+CONFIG_GPIOLIB=y
+# CONFIG_DEBUG_GPIO is not set
+CONFIG_GPIO_SYSFS=y
+
+#
+# Memory mapped GPIO expanders:
+#
+
+#
+# I2C GPIO expanders:
+#
+# CONFIG_GPIO_MAX732X is not set
+# CONFIG_GPIO_PCA953X is not set
+CONFIG_GPIO_PCF857X=y
+# CONFIG_GPIO_ADP5588 is not set
+
+#
+# PCI GPIO expanders:
+#
+
+#
+# SPI GPIO expanders:
+#
+# CONFIG_GPIO_MAX7301 is not set
+# CONFIG_GPIO_MCP23S08 is not set
+# CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
+CONFIG_HWMON=y
+# CONFIG_HWMON_VID is not set
+# CONFIG_SENSORS_AD7414 is not set
+# CONFIG_SENSORS_AD7418 is not set
+# CONFIG_SENSORS_ADCXX is not set
+# CONFIG_SENSORS_ADM1021 is not set
+# CONFIG_SENSORS_ADM1025 is not set
+# CONFIG_SENSORS_ADM1026 is not set
+# CONFIG_SENSORS_ADM1029 is not set
+# CONFIG_SENSORS_ADM1031 is not set
+# CONFIG_SENSORS_ADM9240 is not set
+# CONFIG_SENSORS_ADT7462 is not set
+# CONFIG_SENSORS_ADT7470 is not set
+# CONFIG_SENSORS_ADT7473 is not set
+# CONFIG_SENSORS_ADT7475 is not set
+# CONFIG_SENSORS_ATXP1 is not set
+# CONFIG_SENSORS_DS1621 is not set
+# CONFIG_SENSORS_F71805F is not set
+# CONFIG_SENSORS_F71882FG is not set
+# CONFIG_SENSORS_F75375S is not set
+# CONFIG_SENSORS_G760A is not set
+# CONFIG_SENSORS_GL518SM is not set
+# CONFIG_SENSORS_GL520SM is not set
+# CONFIG_SENSORS_IT87 is not set
+# CONFIG_SENSORS_LM63 is not set
+# CONFIG_SENSORS_LM70 is not set
+CONFIG_SENSORS_LM75=y
+# CONFIG_SENSORS_LM77 is not set
+# CONFIG_SENSORS_LM78 is not set
+# CONFIG_SENSORS_LM80 is not set
+# CONFIG_SENSORS_LM83 is not set
+# CONFIG_SENSORS_LM85 is not set
+# CONFIG_SENSORS_LM87 is not set
+# CONFIG_SENSORS_LM90 is not set
+# CONFIG_SENSORS_LM92 is not set
+# CONFIG_SENSORS_LM93 is not set
+# CONFIG_SENSORS_LTC4215 is not set
+# CONFIG_SENSORS_LTC4245 is not set
+# CONFIG_SENSORS_LM95241 is not set
+# CONFIG_SENSORS_MAX1111 is not set
+# CONFIG_SENSORS_MAX1619 is not set
+# CONFIG_SENSORS_MAX6650 is not set
+# CONFIG_SENSORS_PC87360 is not set
+# CONFIG_SENSORS_PC87427 is not set
+# CONFIG_SENSORS_PCF8591 is not set
+# CONFIG_SENSORS_SHT15 is not set
+# CONFIG_SENSORS_DME1737 is not set
+# CONFIG_SENSORS_SMSC47M1 is not set
+# CONFIG_SENSORS_SMSC47M192 is not set
+# CONFIG_SENSORS_SMSC47B397 is not set
+# CONFIG_SENSORS_ADS7828 is not set
+# CONFIG_SENSORS_THMC50 is not set
+# CONFIG_SENSORS_TMP401 is not set
+# CONFIG_SENSORS_VT1211 is not set
+# CONFIG_SENSORS_W83781D is not set
+# CONFIG_SENSORS_W83791D is not set
+# CONFIG_SENSORS_W83792D is not set
+# CONFIG_SENSORS_W83793 is not set
+# CONFIG_SENSORS_W83L785TS is not set
+# CONFIG_SENSORS_W83L786NG is not set
+# CONFIG_SENSORS_W83627HF is not set
+# CONFIG_SENSORS_W83627EHF is not set
+# CONFIG_HWMON_DEBUG_CHIP is not set
+# CONFIG_THERMAL is not set
+# CONFIG_THERMAL_HWMON is not set
+CONFIG_WATCHDOG=y
+# CONFIG_WATCHDOG_NOWAYOUT is not set
+
+#
+# Watchdog Device Drivers
+#
+# CONFIG_SOFT_WATCHDOG is not set
+CONFIG_BFIN_WDT=y
+
+#
+# USB-based Watchdog Cards
+#
+# CONFIG_USBPCWATCHDOG is not set
+CONFIG_SSB_POSSIBLE=y
+
+#
+# Sonics Silicon Backplane
+#
+# CONFIG_SSB is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_CORE is not set
+# CONFIG_MFD_SM501 is not set
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_TPS65010 is not set
+# CONFIG_TWL4030_CORE is not set
+# CONFIG_MFD_TMIO is not set
+# CONFIG_PMIC_DA903X is not set
+# CONFIG_PMIC_ADP5520 is not set
+# CONFIG_MFD_WM8400 is not set
+# CONFIG_MFD_WM8350_I2C is not set
+# CONFIG_MFD_PCF50633 is not set
+# CONFIG_AB3100_CORE is not set
+# CONFIG_EZX_PCAP is not set
+# CONFIG_REGULATOR is not set
+# CONFIG_MEDIA_SUPPORT is not set
+
+#
+# Graphics support
+#
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+# CONFIG_FB is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+CONFIG_SOUND=y
+CONFIG_SOUND_OSS_CORE=y
+CONFIG_SND=y
+CONFIG_SND_TIMER=y
+CONFIG_SND_PCM=y
+# CONFIG_SND_SEQUENCER is not set
+CONFIG_SND_OSSEMUL=y
+CONFIG_SND_MIXER_OSS=y
+CONFIG_SND_PCM_OSS=y
+CONFIG_SND_PCM_OSS_PLUGINS=y
+# CONFIG_SND_HRTIMER is not set
+# CONFIG_SND_DYNAMIC_MINORS is not set
+CONFIG_SND_SUPPORT_OLD_API=y
+CONFIG_SND_VERBOSE_PROCFS=y
+# CONFIG_SND_VERBOSE_PRINTK is not set
+# CONFIG_SND_DEBUG is not set
+# CONFIG_SND_RAWMIDI_SEQ is not set
+# CONFIG_SND_OPL3_LIB_SEQ is not set
+# CONFIG_SND_OPL4_LIB_SEQ is not set
+# CONFIG_SND_SBAWE_SEQ is not set
+# CONFIG_SND_EMU10K1_SEQ is not set
+# CONFIG_SND_DRIVERS is not set
+CONFIG_SND_SPI=y
+
+#
+# ALSA Blackfin devices
+#
+# CONFIG_SND_BFIN_AD73322 is not set
+# CONFIG_SND_USB is not set
+CONFIG_SND_SOC=y
+CONFIG_SND_BF5XX_I2S=y
+# CONFIG_SND_BF5XX_SOC_SSM2602 is not set
+# CONFIG_SND_BF5XX_SOC_AD73311 is not set
+# CONFIG_SND_BF5XX_SOC_ADAU1371 is not set
+# CONFIG_SND_BF5XX_SOC_ADAU1761 is not set
+# CONFIG_SND_BF5XX_TDM is not set
+# CONFIG_SND_BF5XX_AC97 is not set
+CONFIG_SND_BF5XX_SOC_SPORT=y
+CONFIG_SND_BF5XX_SPORT_NUM=1
+CONFIG_SND_SOC_I2C_AND_SPI=y
+# CONFIG_SND_SOC_ALL_CODECS is not set
+# CONFIG_SOUND_PRIME is not set
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_ARCH_HAS_HCD=y
+# CONFIG_USB_ARCH_HAS_OHCI is not set
+# CONFIG_USB_ARCH_HAS_EHCI is not set
+CONFIG_USB=y
+# CONFIG_USB_DEBUG is not set
+CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
+
+#
+# Miscellaneous USB options
+#
+# CONFIG_USB_DEVICEFS is not set
+# CONFIG_USB_DEVICE_CLASS is not set
+# CONFIG_USB_DYNAMIC_MINORS is not set
+# CONFIG_USB_OTG is not set
+# CONFIG_USB_OTG_WHITELIST is not set
+# CONFIG_USB_OTG_BLACKLIST_HUB is not set
+CONFIG_USB_MON=y
+# CONFIG_USB_WUSB is not set
+# CONFIG_USB_WUSB_CBAF is not set
+
+#
+# USB Host Controller Drivers
+#
+# CONFIG_USB_C67X00_HCD is not set
+# CONFIG_USB_OXU210HP_HCD is not set
+# CONFIG_USB_ISP116X_HCD is not set
+# CONFIG_USB_ISP1760_HCD is not set
+# CONFIG_USB_ISP1362_HCD is not set
+# CONFIG_USB_SL811_HCD is not set
+# CONFIG_USB_R8A66597_HCD is not set
+# CONFIG_USB_HWA_HCD is not set
+
+#
+# USB Device Class drivers
+#
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+# CONFIG_USB_WDM is not set
+# CONFIG_USB_TMC is not set
+
+#
+# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
+#
+
+#
+# also be needed; see USB_STORAGE Help for more info
+#
+CONFIG_USB_STORAGE=y
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
+# CONFIG_USB_STORAGE_USBAT is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_SDDR55 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_STORAGE_ALAUDA is not set
+# CONFIG_USB_STORAGE_KARMA is not set
+# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
+# CONFIG_USB_LIBUSUAL is not set
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_MICROTEK is not set
+
+#
+# USB port drivers
+#
+CONFIG_USB_SERIAL=y
+# CONFIG_USB_SERIAL_CONSOLE is not set
+# CONFIG_USB_EZUSB is not set
+# CONFIG_USB_SERIAL_GENERIC is not set
+# CONFIG_USB_SERIAL_AIRCABLE is not set
+# CONFIG_USB_SERIAL_ARK3116 is not set
+# CONFIG_USB_SERIAL_BELKIN is not set
+# CONFIG_USB_SERIAL_CH341 is not set
+# CONFIG_USB_SERIAL_WHITEHEAT is not set
+# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set
+# CONFIG_USB_SERIAL_CP210X is not set
+# CONFIG_USB_SERIAL_CYPRESS_M8 is not set
+# CONFIG_USB_SERIAL_EMPEG is not set
+CONFIG_USB_SERIAL_FTDI_SIO=y
+# CONFIG_USB_SERIAL_FUNSOFT is not set
+# CONFIG_USB_SERIAL_VISOR is not set
+# CONFIG_USB_SERIAL_IPAQ is not set
+# CONFIG_USB_SERIAL_IR is not set
+# CONFIG_USB_SERIAL_EDGEPORT is not set
+# CONFIG_USB_SERIAL_EDGEPORT_TI is not set
+# CONFIG_USB_SERIAL_GARMIN is not set
+# CONFIG_USB_SERIAL_IPW is not set
+# CONFIG_USB_SERIAL_IUU is not set
+# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set
+# CONFIG_USB_SERIAL_KEYSPAN is not set
+# CONFIG_USB_SERIAL_KLSI is not set
+# CONFIG_USB_SERIAL_KOBIL_SCT is not set
+# CONFIG_USB_SERIAL_MCT_U232 is not set
+# CONFIG_USB_SERIAL_MOS7720 is not set
+# CONFIG_USB_SERIAL_MOS7840 is not set
+# CONFIG_USB_SERIAL_MOTOROLA is not set
+# CONFIG_USB_SERIAL_NAVMAN is not set
+CONFIG_USB_SERIAL_PL2303=y
+# CONFIG_USB_SERIAL_OTI6858 is not set
+# CONFIG_USB_SERIAL_QUALCOMM is not set
+# CONFIG_USB_SERIAL_SPCP8X5 is not set
+# CONFIG_USB_SERIAL_HP4X is not set
+# CONFIG_USB_SERIAL_SAFE is not set
+# CONFIG_USB_SERIAL_SIEMENS_MPI is not set
+# CONFIG_USB_SERIAL_SIERRAWIRELESS is not set
+# CONFIG_USB_SERIAL_SYMBOL is not set
+# CONFIG_USB_SERIAL_TI is not set
+# CONFIG_USB_SERIAL_CYBERJACK is not set
+# CONFIG_USB_SERIAL_XIRCOM is not set
+# CONFIG_USB_SERIAL_OPTION is not set
+# CONFIG_USB_SERIAL_OMNINET is not set
+# CONFIG_USB_SERIAL_OPTICON is not set
+# CONFIG_USB_SERIAL_DEBUG is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_EMI62 is not set
+# CONFIG_USB_EMI26 is not set
+# CONFIG_USB_ADUTUX is not set
+# CONFIG_USB_SEVSEG is not set
+# CONFIG_USB_RIO500 is not set
+# CONFIG_USB_LEGOTOWER is not set
+# CONFIG_USB_LCD is not set
+# CONFIG_USB_BERRY_CHARGE is not set
+# CONFIG_USB_LED is not set
+# CONFIG_USB_CYPRESS_CY7C63 is not set
+# CONFIG_USB_CYTHERM is not set
+# CONFIG_USB_IDMOUSE is not set
+# CONFIG_USB_FTDI_ELAN is not set
+# CONFIG_USB_APPLEDISPLAY is not set
+# CONFIG_USB_LD is not set
+# CONFIG_USB_TRANCEVIBRATOR is not set
+# CONFIG_USB_IOWARRIOR is not set
+# CONFIG_USB_TEST is not set
+# CONFIG_USB_ISIGHTFW is not set
+# CONFIG_USB_VST is not set
+# CONFIG_USB_GADGET is not set
+
+#
+# OTG and related infrastructure
+#
+# CONFIG_USB_GPIO_VBUS is not set
+# CONFIG_NOP_USB_XCEIV is not set
+# CONFIG_MMC is not set
+# CONFIG_MEMSTICK is not set
+# CONFIG_NEW_LEDS is not set
+# CONFIG_ACCESSIBILITY is not set
+CONFIG_RTC_LIB=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_HCTOSYS=y
+CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
+# CONFIG_RTC_DEBUG is not set
+
+#
+# RTC interfaces
+#
+CONFIG_RTC_INTF_SYSFS=y
+CONFIG_RTC_INTF_PROC=y
+CONFIG_RTC_INTF_DEV=y
+# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
+# CONFIG_RTC_DRV_TEST is not set
+
+#
+# I2C RTC drivers
+#
+CONFIG_RTC_DRV_DS1307=y
+# CONFIG_RTC_DRV_DS1374 is not set
+# CONFIG_RTC_DRV_DS1672 is not set
+# CONFIG_RTC_DRV_MAX6900 is not set
+# CONFIG_RTC_DRV_RS5C372 is not set
+# CONFIG_RTC_DRV_ISL1208 is not set
+# CONFIG_RTC_DRV_X1205 is not set
+# CONFIG_RTC_DRV_PCF8563 is not set
+# CONFIG_RTC_DRV_PCF8583 is not set
+# CONFIG_RTC_DRV_M41T80 is not set
+# CONFIG_RTC_DRV_S35390A is not set
+# CONFIG_RTC_DRV_FM3130 is not set
+# CONFIG_RTC_DRV_RX8581 is not set
+# CONFIG_RTC_DRV_RX8025 is not set
+
+#
+# SPI RTC drivers
+#
+# CONFIG_RTC_DRV_M41T94 is not set
+# CONFIG_RTC_DRV_DS1305 is not set
+# CONFIG_RTC_DRV_DS1390 is not set
+# CONFIG_RTC_DRV_MAX6902 is not set
+# CONFIG_RTC_DRV_R9701 is not set
+# CONFIG_RTC_DRV_RS5C348 is not set
+# CONFIG_RTC_DRV_DS3234 is not set
+
+#
+# Platform RTC drivers
+#
+# CONFIG_RTC_DRV_DS1286 is not set
+# CONFIG_RTC_DRV_DS1511 is not set
+# CONFIG_RTC_DRV_DS1553 is not set
+# CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_STK17TA8 is not set
+# CONFIG_RTC_DRV_M48T86 is not set
+# CONFIG_RTC_DRV_M48T35 is not set
+# CONFIG_RTC_DRV_M48T59 is not set
+# CONFIG_RTC_DRV_BQ4802 is not set
+# CONFIG_RTC_DRV_V3020 is not set
+
+#
+# on-CPU RTC drivers
+#
+# CONFIG_DMADEVICES is not set
+# CONFIG_AUXDISPLAY is not set
+# CONFIG_UIO is not set
+
+#
+# TI VLYNQ
+#
+# CONFIG_STAGING is not set
+
+#
+# Firmware Drivers
+#
+# CONFIG_FIRMWARE_MEMMAP is not set
+# CONFIG_SIGMA is not set
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+CONFIG_EXT2_FS_XATTR=y
+CONFIG_EXT2_FS_POSIX_ACL=y
+CONFIG_EXT2_FS_SECURITY=y
+# CONFIG_EXT3_FS is not set
+# CONFIG_EXT4_FS is not set
+CONFIG_FS_MBCACHE=y
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+CONFIG_FS_POSIX_ACL=y
+# CONFIG_XFS_FS is not set
+# CONFIG_GFS2_FS is not set
+# CONFIG_OCFS2_FS is not set
+# CONFIG_BTRFS_FS is not set
+CONFIG_FILE_LOCKING=y
+CONFIG_FSNOTIFY=y
+# CONFIG_DNOTIFY is not set
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_FUSE_FS is not set
+
+#
+# Caches
+#
+# CONFIG_FSCACHE is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_FAT_DEFAULT_CODEPAGE=866
+CONFIG_FAT_DEFAULT_IOCHARSET="cp1251"
+CONFIG_NTFS_FS=y
+# CONFIG_NTFS_DEBUG is not set
+# CONFIG_NTFS_RW is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_SYSFS=y
+# CONFIG_TMPFS is not set
+# CONFIG_HUGETLB_PAGE is not set
+CONFIG_CONFIGFS_FS=y
+CONFIG_MISC_FILESYSTEMS=y
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_DEBUG=0
+CONFIG_JFFS2_FS_WRITEBUFFER=y
+# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
+# CONFIG_JFFS2_SUMMARY is not set
+# CONFIG_JFFS2_FS_XATTR is not set
+CONFIG_JFFS2_COMPRESSION_OPTIONS=y
+# CONFIG_JFFS2_ZLIB is not set
+CONFIG_JFFS2_LZO=y
+# CONFIG_JFFS2_RTIME is not set
+# CONFIG_JFFS2_RUBIN is not set
+# CONFIG_JFFS2_CMODE_NONE is not set
+# CONFIG_JFFS2_CMODE_PRIORITY is not set
+# CONFIG_JFFS2_CMODE_SIZE is not set
+CONFIG_JFFS2_CMODE_FAVOURLZO=y
+CONFIG_CRAMFS=y
+# CONFIG_SQUASHFS is not set
+# CONFIG_VXFS_FS is not set
+CONFIG_MINIX_FS=y
+# CONFIG_OMFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+# CONFIG_NILFS2_FS is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+# CONFIG_NFS_V3_ACL is not set
+# CONFIG_NFS_V4 is not set
+CONFIG_ROOT_NFS=y
+# CONFIG_NFSD is not set
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=y
+# CONFIG_RPCSEC_GSS_KRB5 is not set
+# CONFIG_RPCSEC_GSS_SPKM3 is not set
+# CONFIG_SMB_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="cp1251"
+# CONFIG_NLS_CODEPAGE_437 is not set
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+CONFIG_NLS_CODEPAGE_866=y
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+CONFIG_NLS_CODEPAGE_1251=y
+# CONFIG_NLS_ASCII is not set
+# CONFIG_NLS_ISO8859_1 is not set
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+CONFIG_NLS_KOI8_R=y
+# CONFIG_NLS_KOI8_U is not set
+CONFIG_NLS_UTF8=y
+# CONFIG_DLM is not set
+
+#
+# Kernel hacking
+#
+# CONFIG_PRINTK_TIME is not set
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_FRAME_WARN=1024
+# CONFIG_MAGIC_SYSRQ is not set
+# CONFIG_UNUSED_SYMBOLS is not set
+CONFIG_DEBUG_FS=y
+# CONFIG_HEADERS_CHECK is not set
+CONFIG_DEBUG_SECTION_MISMATCH=y
+CONFIG_DEBUG_KERNEL=y
+CONFIG_DEBUG_SHIRQ=y
+CONFIG_DETECT_SOFTLOCKUP=y
+# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
+CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
+CONFIG_DETECT_HUNG_TASK=y
+# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set
+CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0
+CONFIG_SCHED_DEBUG=y
+# CONFIG_SCHEDSTATS is not set
+# CONFIG_TIMER_STATS is not set
+# CONFIG_DEBUG_OBJECTS is not set
+# CONFIG_DEBUG_SLAB is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_DEBUG_MUTEXES is not set
+# CONFIG_DEBUG_LOCK_ALLOC is not set
+# CONFIG_PROVE_LOCKING is not set
+# CONFIG_LOCK_STAT is not set
+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+# CONFIG_DEBUG_KOBJECT is not set
+# CONFIG_DEBUG_BUGVERBOSE is not set
+CONFIG_DEBUG_INFO=y
+# CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_NOMMU_REGIONS is not set
+# CONFIG_DEBUG_WRITECOUNT is not set
+# CONFIG_DEBUG_MEMORY_INIT is not set
+# CONFIG_DEBUG_LIST is not set
+# CONFIG_DEBUG_SG is not set
+# CONFIG_DEBUG_NOTIFIERS is not set
+# CONFIG_FRAME_POINTER is not set
+# CONFIG_BOOT_PRINTK_DELAY is not set
+# CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_RCU_CPU_STALL_DETECTOR is not set
+# CONFIG_BACKTRACE_SELF_TEST is not set
+# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
+# CONFIG_FAULT_INJECTION is not set
+# CONFIG_PAGE_POISONING is not set
+CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
+CONFIG_TRACING_SUPPORT=y
+CONFIG_FTRACE=y
+# CONFIG_FUNCTION_TRACER is not set
+# CONFIG_IRQSOFF_TRACER is not set
+# CONFIG_SCHED_TRACER is not set
+# CONFIG_ENABLE_DEFAULT_TRACERS is not set
+# CONFIG_BOOT_TRACER is not set
+CONFIG_BRANCH_PROFILE_NONE=y
+# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set
+# CONFIG_PROFILE_ALL_BRANCHES is not set
+# CONFIG_STACK_TRACER is not set
+# CONFIG_KMEMTRACE is not set
+# CONFIG_WORKQUEUE_TRACER is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_DYNAMIC_DEBUG is not set
+# CONFIG_SAMPLES is not set
+CONFIG_HAVE_ARCH_KGDB=y
+# CONFIG_KGDB is not set
+# CONFIG_KMEMCHECK is not set
+# CONFIG_DEBUG_STACKOVERFLOW is not set
+# CONFIG_DEBUG_STACK_USAGE is not set
+CONFIG_DEBUG_VERBOSE=y
+CONFIG_DEBUG_MMRS=y
+# CONFIG_DEBUG_HWERR is not set
+# CONFIG_DEBUG_DOUBLEFAULT is not set
+CONFIG_DEBUG_HUNT_FOR_ZERO=y
+CONFIG_DEBUG_BFIN_HWTRACE_ON=y
+CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_OFF=y
+# CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_ONE is not set
+# CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_TWO is not set
+CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION=0
+# CONFIG_DEBUG_BFIN_HWTRACE_EXPAND is not set
+# CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE is not set
+# CONFIG_EARLY_PRINTK is not set
+CONFIG_CPLB_INFO=y
+CONFIG_ACCESS_CHECK=y
+# CONFIG_BFIN_ISRAM_SELF_TEST is not set
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+CONFIG_SECURITY=y
+# CONFIG_SECURITYFS is not set
+# CONFIG_SECURITY_NETWORK is not set
+# CONFIG_SECURITY_PATH is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+# CONFIG_SECURITY_ROOTPLUG is not set
+# CONFIG_SECURITY_TOMOYO is not set
+CONFIG_CRYPTO=y
+
+#
+# Crypto core or helper
+#
+# CONFIG_CRYPTO_FIPS is not set
+# CONFIG_CRYPTO_MANAGER is not set
+# CONFIG_CRYPTO_MANAGER2 is not set
+# CONFIG_CRYPTO_GF128MUL is not set
+# CONFIG_CRYPTO_NULL is not set
+# CONFIG_CRYPTO_CRYPTD is not set
+# CONFIG_CRYPTO_AUTHENC is not set
+# CONFIG_CRYPTO_TEST is not set
+
+#
+# Authenticated Encryption with Associated Data
+#
+# CONFIG_CRYPTO_CCM is not set
+# CONFIG_CRYPTO_GCM is not set
+# CONFIG_CRYPTO_SEQIV is not set
+
+#
+# Block modes
+#
+# CONFIG_CRYPTO_CBC is not set
+# CONFIG_CRYPTO_CTR is not set
+# CONFIG_CRYPTO_CTS is not set
+# CONFIG_CRYPTO_ECB is not set
+# CONFIG_CRYPTO_LRW is not set
+# CONFIG_CRYPTO_PCBC is not set
+# CONFIG_CRYPTO_XTS is not set
+
+#
+# Hash modes
+#
+# CONFIG_CRYPTO_HMAC is not set
+# CONFIG_CRYPTO_XCBC is not set
+
+#
+# Digest
+#
+# CONFIG_CRYPTO_CRC32C is not set
+# CONFIG_CRYPTO_MD4 is not set
+# CONFIG_CRYPTO_MD5 is not set
+# CONFIG_CRYPTO_MICHAEL_MIC is not set
+# CONFIG_CRYPTO_RMD128 is not set
+# CONFIG_CRYPTO_RMD160 is not set
+# CONFIG_CRYPTO_RMD256 is not set
+# CONFIG_CRYPTO_RMD320 is not set
+# CONFIG_CRYPTO_SHA1 is not set
+# CONFIG_CRYPTO_SHA256 is not set
+# CONFIG_CRYPTO_SHA512 is not set
+# CONFIG_CRYPTO_TGR192 is not set
+# CONFIG_CRYPTO_WP512 is not set
+
+#
+# Ciphers
+#
+# CONFIG_CRYPTO_AES is not set
+# CONFIG_CRYPTO_ANUBIS is not set
+# CONFIG_CRYPTO_ARC4 is not set
+# CONFIG_CRYPTO_BLOWFISH is not set
+# CONFIG_CRYPTO_CAMELLIA is not set
+# CONFIG_CRYPTO_CAST5 is not set
+# CONFIG_CRYPTO_CAST6 is not set
+# CONFIG_CRYPTO_DES is not set
+# CONFIG_CRYPTO_FCRYPT is not set
+# CONFIG_CRYPTO_KHAZAD is not set
+# CONFIG_CRYPTO_SALSA20 is not set
+# CONFIG_CRYPTO_SEED is not set
+# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_TEA is not set
+# CONFIG_CRYPTO_TWOFISH is not set
+
+#
+# Compression
+#
+# CONFIG_CRYPTO_DEFLATE is not set
+# CONFIG_CRYPTO_ZLIB is not set
+# CONFIG_CRYPTO_LZO is not set
+
+#
+# Random Number Generation
+#
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
+CONFIG_CRYPTO_HW=y
+# CONFIG_BINARY_PRINTF is not set
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+CONFIG_GENERIC_FIND_LAST_BIT=y
+# CONFIG_CRC_CCITT is not set
+# CONFIG_CRC16 is not set
+# CONFIG_CRC_T10DIF is not set
+# CONFIG_CRC_ITU_T is not set
+CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
+# CONFIG_LIBCRC32C is not set
+CONFIG_ZLIB_INFLATE=y
+CONFIG_LZO_COMPRESS=y
+CONFIG_LZO_DECOMPRESS=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
+CONFIG_NLATTR=y
diff --git a/arch/blackfin/configs/BF561-EZKIT_defconfig b/arch/blackfin/configs/BF561-EZKIT_defconfig
index 0313cd1d9824..e3ecdcc3e76b 100644
--- a/arch/blackfin/configs/BF561-EZKIT_defconfig
+++ b/arch/blackfin/configs/BF561-EZKIT_defconfig
@@ -1,22 +1,29 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.28.10
-# Thu May 21 05:50:01 2009
+# Linux kernel version: 2.6.31.5
+# Mon Nov  2 21:59:31 2009
 #
 # CONFIG_MMU is not set
 # CONFIG_FPU is not set
 CONFIG_RWSEM_GENERIC_SPINLOCK=y
 # CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
 CONFIG_BLACKFIN=y
+CONFIG_GENERIC_CSUM=y
+CONFIG_GENERIC_BUG=y
 CONFIG_ZONE_DMA=y
 CONFIG_GENERIC_FIND_NEXT_BIT=y
 CONFIG_GENERIC_HWEIGHT=y
 CONFIG_GENERIC_HARDIRQS=y
 CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
 CONFIG_GENERIC_GPIO=y
 CONFIG_FORCE_MAX_ZONEORDER=14
 CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
 CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+CONFIG_CONSTRUCTORS=y
 
 #
 # General setup
@@ -26,22 +33,40 @@ CONFIG_BROKEN_ON_SMP=y
 CONFIG_INIT_ENV_ARG_LIMIT=32
 CONFIG_LOCALVERSION=""
 CONFIG_LOCALVERSION_AUTO=y
+CONFIG_HAVE_KERNEL_GZIP=y
+CONFIG_HAVE_KERNEL_BZIP2=y
+CONFIG_HAVE_KERNEL_LZMA=y
+CONFIG_KERNEL_GZIP=y
+# CONFIG_KERNEL_BZIP2 is not set
+# CONFIG_KERNEL_LZMA is not set
 CONFIG_SYSVIPC=y
 CONFIG_SYSVIPC_SYSCTL=y
 # CONFIG_POSIX_MQUEUE is not set
 # CONFIG_BSD_PROCESS_ACCT is not set
 # CONFIG_TASKSTATS is not set
 # CONFIG_AUDIT is not set
+
+#
+# RCU Subsystem
+#
+CONFIG_CLASSIC_RCU=y
+# CONFIG_TREE_RCU is not set
+# CONFIG_PREEMPT_RCU is not set
+# CONFIG_TREE_RCU_TRACE is not set
+# CONFIG_PREEMPT_RCU_TRACE is not set
 CONFIG_IKCONFIG=y
 CONFIG_IKCONFIG_PROC=y
 CONFIG_LOG_BUF_SHIFT=14
-# CONFIG_CGROUPS is not set
 # CONFIG_GROUP_SCHED is not set
+# CONFIG_CGROUPS is not set
 # CONFIG_SYSFS_DEPRECATED_V2 is not set
 # CONFIG_RELAY is not set
 # CONFIG_NAMESPACES is not set
 CONFIG_BLK_DEV_INITRD=y
 CONFIG_INITRAMFS_SOURCE=""
+CONFIG_RD_GZIP=y
+# CONFIG_RD_BZIP2 is not set
+# CONFIG_RD_LZMA is not set
 # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
 CONFIG_SYSCTL=y
 CONFIG_ANON_INODES=y
@@ -62,17 +87,28 @@ CONFIG_EPOLL=y
 # CONFIG_TIMERFD is not set
 # CONFIG_EVENTFD is not set
 # CONFIG_AIO is not set
+
+#
+# Performance Counters
+#
 CONFIG_VM_EVENT_COUNTERS=y
+# CONFIG_STRIP_ASM_SYMS is not set
 CONFIG_COMPAT_BRK=y
 CONFIG_SLAB=y
 # CONFIG_SLUB is not set
 # CONFIG_SLOB is not set
+CONFIG_MMAP_ALLOW_UNINITIALIZED=y
 # CONFIG_PROFILING is not set
 # CONFIG_MARKERS is not set
 CONFIG_HAVE_OPROFILE=y
+
+#
+# GCOV-based kernel profiling
+#
+# CONFIG_GCOV_KERNEL is not set
+# CONFIG_SLOW_WORK is not set
 # CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
 CONFIG_SLABINFO=y
-CONFIG_TINY_SHMEM=y
 CONFIG_BASE_SMALL=0
 CONFIG_MODULES=y
 # CONFIG_MODULE_FORCE_LOAD is not set
@@ -80,11 +116,8 @@ CONFIG_MODULE_UNLOAD=y
 # CONFIG_MODULE_FORCE_UNLOAD is not set
 # CONFIG_MODVERSIONS is not set
 # CONFIG_MODULE_SRCVERSION_ALL is not set
-CONFIG_KMOD=y
 CONFIG_BLOCK=y
-# CONFIG_LBD is not set
-# CONFIG_BLK_DEV_IO_TRACE is not set
-# CONFIG_LSF is not set
+# CONFIG_LBDAF is not set
 # CONFIG_BLK_DEV_BSG is not set
 # CONFIG_BLK_DEV_INTEGRITY is not set
 
@@ -94,13 +127,12 @@ CONFIG_BLOCK=y
 CONFIG_IOSCHED_NOOP=y
 CONFIG_IOSCHED_AS=y
 # CONFIG_IOSCHED_DEADLINE is not set
-CONFIG_IOSCHED_CFQ=y
+# CONFIG_IOSCHED_CFQ is not set
 CONFIG_DEFAULT_AS=y
 # CONFIG_DEFAULT_DEADLINE is not set
 # CONFIG_DEFAULT_CFQ is not set
 # CONFIG_DEFAULT_NOOP is not set
 CONFIG_DEFAULT_IOSCHED="anticipatory"
-CONFIG_CLASSIC_RCU=y
 # CONFIG_PREEMPT_NONE is not set
 CONFIG_PREEMPT_VOLUNTARY=y
 # CONFIG_PREEMPT is not set
@@ -170,6 +202,7 @@ CONFIG_IRQ_SPI_ERROR=7
 CONFIG_BFIN561_EZKIT=y
 # CONFIG_BFIN561_TEPLA is not set
 # CONFIG_BFIN561_BLUETECHNIX_CM is not set
+# CONFIG_BFIN561_ACVILON is not set
 
 #
 # BF561 Specific Configuration
@@ -317,10 +350,11 @@ CONFIG_FLATMEM=y
 CONFIG_FLAT_NODE_MEM_MAP=y
 CONFIG_PAGEFLAGS_EXTENDED=y
 CONFIG_SPLIT_PTLOCK_CPUS=4
-# CONFIG_RESOURCES_64BIT is not set
 # CONFIG_PHYS_ADDR_T_64BIT is not set
 CONFIG_ZONE_DMA_FLAG=1
 CONFIG_VIRT_TO_BUS=y
+CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
+CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0
 CONFIG_BFIN_GPTIMERS=m
 # CONFIG_DMA_UNCACHED_4M is not set
 # CONFIG_DMA_UNCACHED_2M is not set
@@ -331,14 +365,13 @@ CONFIG_DMA_UNCACHED_1M=y
 # Cache Support
 #
 CONFIG_BFIN_ICACHE=y
-# CONFIG_BFIN_ICACHE_LOCK is not set
+CONFIG_BFIN_EXTMEM_ICACHEABLE=y
+# CONFIG_BFIN_L2_ICACHEABLE is not set
 CONFIG_BFIN_DCACHE=y
 # CONFIG_BFIN_DCACHE_BANKA is not set
-CONFIG_BFIN_EXTMEM_ICACHEABLE=y
 CONFIG_BFIN_EXTMEM_DCACHEABLE=y
 CONFIG_BFIN_EXTMEM_WRITEBACK=y
 # CONFIG_BFIN_EXTMEM_WRITETHROUGH is not set
-# CONFIG_BFIN_L2_ICACHEABLE is not set
 # CONFIG_BFIN_L2_DCACHEABLE is not set
 
 #
@@ -347,7 +380,7 @@ CONFIG_BFIN_EXTMEM_WRITEBACK=y
 # CONFIG_MPU is not set
 
 #
-# Asynchonous Memory Configuration
+# Asynchronous Memory Configuration
 #
 
 #
@@ -407,11 +440,6 @@ CONFIG_NET=y
 CONFIG_PACKET=y
 # CONFIG_PACKET_MMAP is not set
 CONFIG_UNIX=y
-CONFIG_XFRM=y
-# CONFIG_XFRM_USER is not set
-# CONFIG_XFRM_SUB_POLICY is not set
-# CONFIG_XFRM_MIGRATE is not set
-# CONFIG_XFRM_STATISTICS is not set
 # CONFIG_NET_KEY is not set
 CONFIG_INET=y
 # CONFIG_IP_MULTICAST is not set
@@ -435,13 +463,11 @@ CONFIG_IP_PNP=y
 # CONFIG_INET_XFRM_MODE_BEET is not set
 # CONFIG_INET_LRO is not set
 # CONFIG_INET_DIAG is not set
-CONFIG_INET_TCP_DIAG=y
 # CONFIG_TCP_CONG_ADVANCED is not set
 CONFIG_TCP_CONG_CUBIC=y
 CONFIG_DEFAULT_TCP_CONG="cubic"
 # CONFIG_TCP_MD5SIG is not set
 # CONFIG_IPV6 is not set
-# CONFIG_NETLABEL is not set
 # CONFIG_NETWORK_SECMARK is not set
 # CONFIG_NETFILTER is not set
 # CONFIG_IP_DCCP is not set
@@ -459,7 +485,10 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
 # CONFIG_LAPB is not set
 # CONFIG_ECONET is not set
 # CONFIG_WAN_ROUTER is not set
+# CONFIG_PHONET is not set
+# CONFIG_IEEE802154 is not set
 # CONFIG_NET_SCHED is not set
+# CONFIG_DCB is not set
 
 #
 # Network testing
@@ -503,13 +532,8 @@ CONFIG_IRTTY_SIR=m
 #
 # CONFIG_BT is not set
 # CONFIG_AF_RXRPC is not set
-# CONFIG_PHONET is not set
-CONFIG_WIRELESS=y
-# CONFIG_CFG80211 is not set
-CONFIG_WIRELESS_OLD_REGULATORY=y
-# CONFIG_WIRELESS_EXT is not set
-# CONFIG_MAC80211 is not set
-# CONFIG_IEEE80211 is not set
+# CONFIG_WIRELESS is not set
+# CONFIG_WIMAX is not set
 # CONFIG_RFKILL is not set
 # CONFIG_NET_9P is not set
 
@@ -530,6 +554,7 @@ CONFIG_PREVENT_FIRMWARE_BUILD=y
 # CONFIG_CONNECTOR is not set
 CONFIG_MTD=y
 # CONFIG_MTD_DEBUG is not set
+# CONFIG_MTD_TESTS is not set
 # CONFIG_MTD_CONCAT is not set
 CONFIG_MTD_PARTITIONS=y
 # CONFIG_MTD_REDBOOT_PARTS is not set
@@ -603,6 +628,11 @@ CONFIG_MTD_PHYSMAP=m
 # CONFIG_MTD_ONENAND is not set
 
 #
+# LPDDR flash memory drivers
+#
+# CONFIG_MTD_LPDDR is not set
+
+#
 # UBI - Unsorted block images
 #
 # CONFIG_MTD_UBI is not set
@@ -619,9 +649,14 @@ CONFIG_BLK_DEV_RAM_SIZE=4096
 # CONFIG_ATA_OVER_ETH is not set
 # CONFIG_BLK_DEV_HD is not set
 CONFIG_MISC_DEVICES=y
-# CONFIG_EEPROM_93CX6 is not set
 # CONFIG_ENCLOSURE_SERVICES is not set
 # CONFIG_C2PORT is not set
+
+#
+# EEPROM support
+#
+# CONFIG_EEPROM_AT25 is not set
+# CONFIG_EEPROM_93CX6 is not set
 CONFIG_HAVE_IDE=y
 # CONFIG_IDE is not set
 
@@ -645,9 +680,11 @@ CONFIG_NETDEVICES=y
 CONFIG_NET_ETHERNET=y
 CONFIG_MII=y
 CONFIG_SMC91X=y
-# CONFIG_SMSC911X is not set
 # CONFIG_DM9000 is not set
 # CONFIG_ENC28J60 is not set
+# CONFIG_ETHOC is not set
+# CONFIG_SMSC911X is not set
+# CONFIG_DNET is not set
 # CONFIG_IBM_NEW_EMAC_ZMII is not set
 # CONFIG_IBM_NEW_EMAC_RGMII is not set
 # CONFIG_IBM_NEW_EMAC_TAH is not set
@@ -656,6 +693,8 @@ CONFIG_SMC91X=y
 # CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
 # CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
 # CONFIG_B44 is not set
+# CONFIG_KS8842 is not set
+# CONFIG_KS8851 is not set
 # CONFIG_NETDEV_1000 is not set
 # CONFIG_NETDEV_10000 is not set
 
@@ -664,7 +703,10 @@ CONFIG_SMC91X=y
 #
 # CONFIG_WLAN_PRE80211 is not set
 # CONFIG_WLAN_80211 is not set
-# CONFIG_IWLWIFI_LEDS is not set
+
+#
+# Enable WiMAX (Networking options) to see the WiMAX drivers
+#
 # CONFIG_WAN is not set
 # CONFIG_PPP is not set
 # CONFIG_SLIP is not set
@@ -708,15 +750,12 @@ CONFIG_INPUT_EVDEV=m
 #
 # Character devices
 #
-# CONFIG_AD9960 is not set
 CONFIG_BFIN_DMA_INTERFACE=m
 # CONFIG_BFIN_PPI is not set
 # CONFIG_BFIN_PPIFCD is not set
 # CONFIG_BFIN_SIMPLE_TIMER is not set
 # CONFIG_BFIN_SPI_ADC is not set
 # CONFIG_BFIN_SPORT is not set
-# CONFIG_BFIN_TIMER_LATENCY is not set
-CONFIG_SIMPLE_GPIO=m
 # CONFIG_VT is not set
 # CONFIG_DEVKMEM is not set
 CONFIG_BFIN_JTAG_COMM=m
@@ -730,6 +769,7 @@ CONFIG_BFIN_JTAG_COMM=m
 #
 # Non-8250 serial port support
 #
+# CONFIG_SERIAL_MAX3100 is not set
 CONFIG_SERIAL_BFIN=y
 CONFIG_SERIAL_BFIN_CONSOLE=y
 CONFIG_SERIAL_BFIN_DMA=y
@@ -740,6 +780,7 @@ CONFIG_SERIAL_CORE=y
 CONFIG_SERIAL_CORE_CONSOLE=y
 # CONFIG_SERIAL_BFIN_SPORT is not set
 CONFIG_UNIX98_PTYS=y
+# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
 # CONFIG_LEGACY_PTYS is not set
 
 #
@@ -763,13 +804,18 @@ CONFIG_SPI_BFIN=y
 # CONFIG_SPI_BFIN_LOCK is not set
 # CONFIG_SPI_BFIN_SPORT is not set
 # CONFIG_SPI_BITBANG is not set
+# CONFIG_SPI_GPIO is not set
 
 #
 # SPI Protocol Masters
 #
-# CONFIG_EEPROM_AT25 is not set
 # CONFIG_SPI_SPIDEV is not set
 # CONFIG_SPI_TLE62X0 is not set
+
+#
+# PPS support
+#
+# CONFIG_PPS is not set
 CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
 CONFIG_GPIOLIB=y
 # CONFIG_DEBUG_GPIO is not set
@@ -782,9 +828,6 @@ CONFIG_GPIO_SYSFS=y
 #
 # I2C GPIO expanders:
 #
-# CONFIG_GPIO_MAX732X is not set
-# CONFIG_GPIO_PCA953X is not set
-# CONFIG_GPIO_PCF857X is not set
 
 #
 # PCI GPIO expanders:
@@ -822,23 +865,9 @@ CONFIG_SSB_POSSIBLE=y
 # CONFIG_MFD_SM501 is not set
 # CONFIG_HTC_PASIC3 is not set
 # CONFIG_MFD_TMIO is not set
+# CONFIG_EZX_PCAP is not set
 # CONFIG_REGULATOR is not set
-
-#
-# Multimedia devices
-#
-
-#
-# Multimedia core support
-#
-# CONFIG_VIDEO_DEV is not set
-# CONFIG_DVB_CORE is not set
-# CONFIG_VIDEO_MEDIA is not set
-
-#
-# Multimedia drivers
-#
-# CONFIG_DAB is not set
+# CONFIG_MEDIA_SUPPORT is not set
 
 #
 # Graphics support
@@ -862,7 +891,6 @@ CONFIG_HID=m
 #
 # Special HID drivers
 #
-CONFIG_HID_COMPAT=y
 # CONFIG_USB_SUPPORT is not set
 # CONFIG_MMC is not set
 # CONFIG_MEMSTICK is not set
@@ -870,10 +898,20 @@ CONFIG_HID_COMPAT=y
 # CONFIG_ACCESSIBILITY is not set
 # CONFIG_RTC_CLASS is not set
 # CONFIG_DMADEVICES is not set
+# CONFIG_AUXDISPLAY is not set
 # CONFIG_UIO is not set
+
+#
+# TI VLYNQ
+#
 # CONFIG_STAGING is not set
 
 #
+# Firmware Drivers
+#
+# CONFIG_FIRMWARE_MEMMAP is not set
+
+#
 # File systems
 #
 # CONFIG_EXT2_FS is not set
@@ -882,9 +920,11 @@ CONFIG_HID_COMPAT=y
 # CONFIG_REISERFS_FS is not set
 # CONFIG_JFS_FS is not set
 # CONFIG_FS_POSIX_ACL is not set
-CONFIG_FILE_LOCKING=y
 # CONFIG_XFS_FS is not set
 # CONFIG_OCFS2_FS is not set
+# CONFIG_BTRFS_FS is not set
+CONFIG_FILE_LOCKING=y
+CONFIG_FSNOTIFY=y
 # CONFIG_DNOTIFY is not set
 CONFIG_INOTIFY=y
 CONFIG_INOTIFY_USER=y
@@ -894,6 +934,11 @@ CONFIG_INOTIFY_USER=y
 # CONFIG_FUSE_FS is not set
 
 #
+# Caches
+#
+# CONFIG_FSCACHE is not set
+
+#
 # CD-ROM/DVD Filesystems
 #
 # CONFIG_ISO9660_FS is not set
@@ -915,10 +960,7 @@ CONFIG_SYSFS=y
 # CONFIG_TMPFS is not set
 # CONFIG_HUGETLB_PAGE is not set
 # CONFIG_CONFIGFS_FS is not set
-
-#
-# Miscellaneous filesystems
-#
+CONFIG_MISC_FILESYSTEMS=y
 # CONFIG_ADFS_FS is not set
 # CONFIG_AFFS_FS is not set
 # CONFIG_HFS_FS is not set
@@ -937,17 +979,8 @@ CONFIG_JFFS2_ZLIB=y
 # CONFIG_JFFS2_LZO is not set
 CONFIG_JFFS2_RTIME=y
 # CONFIG_JFFS2_RUBIN is not set
-CONFIG_YAFFS_FS=m
-CONFIG_YAFFS_YAFFS1=y
-# CONFIG_YAFFS_9BYTE_TAGS is not set
-# CONFIG_YAFFS_DOES_ECC is not set
-CONFIG_YAFFS_YAFFS2=y
-CONFIG_YAFFS_AUTO_YAFFS2=y
-# CONFIG_YAFFS_DISABLE_LAZY_LOAD is not set
-# CONFIG_YAFFS_DISABLE_WIDE_TNODES is not set
-# CONFIG_YAFFS_ALWAYS_CHECK_CHUNK_ERASED is not set
-CONFIG_YAFFS_SHORT_NAMES_IN_RAM=y
 # CONFIG_CRAMFS is not set
+# CONFIG_SQUASHFS is not set
 # CONFIG_VXFS_FS is not set
 # CONFIG_MINIX_FS is not set
 # CONFIG_OMFS_FS is not set
@@ -956,6 +989,7 @@ CONFIG_YAFFS_SHORT_NAMES_IN_RAM=y
 # CONFIG_ROMFS_FS is not set
 # CONFIG_SYSV_FS is not set
 # CONFIG_UFS_FS is not set
+# CONFIG_NILFS2_FS is not set
 CONFIG_NETWORK_FILESYSTEMS=y
 CONFIG_NFS_FS=m
 CONFIG_NFS_V3=y
@@ -966,7 +1000,6 @@ CONFIG_LOCKD=m
 CONFIG_LOCKD_V4=y
 CONFIG_NFS_COMMON=y
 CONFIG_SUNRPC=m
-# CONFIG_SUNRPC_REGISTER_V4 is not set
 # CONFIG_RPCSEC_GSS_KRB5 is not set
 # CONFIG_RPCSEC_GSS_SPKM3 is not set
 CONFIG_SMB_FS=m
@@ -1034,11 +1067,15 @@ CONFIG_FRAME_WARN=1024
 # CONFIG_UNUSED_SYMBOLS is not set
 CONFIG_DEBUG_FS=y
 # CONFIG_HEADERS_CHECK is not set
+CONFIG_DEBUG_SECTION_MISMATCH=y
 CONFIG_DEBUG_KERNEL=y
 CONFIG_DEBUG_SHIRQ=y
 CONFIG_DETECT_SOFTLOCKUP=y
 # CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
 CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
+CONFIG_DETECT_HUNG_TASK=y
+# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set
+CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0
 CONFIG_SCHED_DEBUG=y
 # CONFIG_SCHEDSTATS is not set
 # CONFIG_TIMER_STATS is not set
@@ -1046,16 +1083,21 @@ CONFIG_SCHED_DEBUG=y
 # CONFIG_DEBUG_SLAB is not set
 # CONFIG_DEBUG_SPINLOCK is not set
 # CONFIG_DEBUG_MUTEXES is not set
+# CONFIG_DEBUG_LOCK_ALLOC is not set
+# CONFIG_PROVE_LOCKING is not set
+# CONFIG_LOCK_STAT is not set
 # CONFIG_DEBUG_SPINLOCK_SLEEP is not set
 # CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
 # CONFIG_DEBUG_KOBJECT is not set
 CONFIG_DEBUG_BUGVERBOSE=y
 CONFIG_DEBUG_INFO=y
 # CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_NOMMU_REGIONS is not set
 # CONFIG_DEBUG_WRITECOUNT is not set
 # CONFIG_DEBUG_MEMORY_INIT is not set
 # CONFIG_DEBUG_LIST is not set
 # CONFIG_DEBUG_SG is not set
+# CONFIG_DEBUG_NOTIFIERS is not set
 # CONFIG_FRAME_POINTER is not set
 # CONFIG_BOOT_PRINTK_DELAY is not set
 # CONFIG_RCU_TORTURE_TEST is not set
@@ -1063,17 +1105,19 @@ CONFIG_DEBUG_INFO=y
 # CONFIG_BACKTRACE_SELF_TEST is not set
 # CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
 # CONFIG_FAULT_INJECTION is not set
-
-#
-# Tracers
-#
-# CONFIG_SCHED_TRACER is not set
-# CONFIG_CONTEXT_SWITCH_TRACER is not set
-# CONFIG_BOOT_TRACER is not set
-# CONFIG_DYNAMIC_PRINTK_DEBUG is not set
+# CONFIG_PAGE_POISONING is not set
+CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
+CONFIG_TRACING_SUPPORT=y
+# CONFIG_FTRACE is not set
+# CONFIG_BRANCH_PROFILE_NONE is not set
+# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set
+# CONFIG_PROFILE_ALL_BRANCHES is not set
+# CONFIG_DYNAMIC_DEBUG is not set
 # CONFIG_SAMPLES is not set
 CONFIG_HAVE_ARCH_KGDB=y
 # CONFIG_KGDB is not set
+# CONFIG_KMEMCHECK is not set
 # CONFIG_DEBUG_STACKOVERFLOW is not set
 # CONFIG_DEBUG_STACK_USAGE is not set
 CONFIG_DEBUG_VERBOSE=y
@@ -1095,16 +1139,15 @@ CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE=y
 CONFIG_EARLY_PRINTK=y
 CONFIG_CPLB_INFO=y
 CONFIG_ACCESS_CHECK=y
+# CONFIG_BFIN_ISRAM_SELF_TEST is not set
 
 #
 # Security options
 #
 # CONFIG_KEYS is not set
-CONFIG_SECURITY=y
+# CONFIG_SECURITY is not set
 # CONFIG_SECURITYFS is not set
-# CONFIG_SECURITY_NETWORK is not set
 # CONFIG_SECURITY_FILE_CAPABILITIES is not set
-CONFIG_SECURITY_DEFAULT_MMAP_MIN_ADDR=0
 CONFIG_CRYPTO=y
 
 #
@@ -1183,6 +1226,7 @@ CONFIG_CRYPTO=y
 # Compression
 #
 # CONFIG_CRYPTO_DEFLATE is not set
+# CONFIG_CRYPTO_ZLIB is not set
 # CONFIG_CRYPTO_LZO is not set
 
 #
@@ -1190,11 +1234,13 @@ CONFIG_CRYPTO=y
 #
 # CONFIG_CRYPTO_ANSI_CPRNG is not set
 CONFIG_CRYPTO_HW=y
+# CONFIG_BINARY_PRINTF is not set
 
 #
 # Library routines
 #
 CONFIG_BITREVERSE=y
+CONFIG_GENERIC_FIND_LAST_BIT=y
 CONFIG_CRC_CCITT=m
 # CONFIG_CRC16 is not set
 # CONFIG_CRC_T10DIF is not set
@@ -1204,6 +1250,8 @@ CONFIG_CRC32=y
 # CONFIG_LIBCRC32C is not set
 CONFIG_ZLIB_INFLATE=y
 CONFIG_ZLIB_DEFLATE=m
+CONFIG_DECOMPRESS_GZIP=y
 CONFIG_HAS_IOMEM=y
 CONFIG_HAS_IOPORT=y
 CONFIG_HAS_DMA=y
+CONFIG_NLATTR=y
diff --git a/arch/blackfin/configs/BlackStamp_defconfig b/arch/blackfin/configs/BlackStamp_defconfig
index 5d944ffd4ab0..9e65d885ec0b 100644
--- a/arch/blackfin/configs/BlackStamp_defconfig
+++ b/arch/blackfin/configs/BlackStamp_defconfig
@@ -66,6 +66,7 @@ CONFIG_VM_EVENT_COUNTERS=y
 CONFIG_SLAB=y
 # CONFIG_SLUB is not set
 # CONFIG_SLOB is not set
+CONFIG_MMAP_ALLOW_UNINITIALIZED=y
 # CONFIG_PROFILING is not set
 # CONFIG_MARKERS is not set
 CONFIG_HAVE_OPROFILE=y
@@ -275,6 +276,7 @@ CONFIG_SPLIT_PTLOCK_CPUS=4
 # CONFIG_RESOURCES_64BIT is not set
 CONFIG_ZONE_DMA_FLAG=1
 CONFIG_VIRT_TO_BUS=y
+CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0
 CONFIG_BFIN_GPTIMERS=y
 # CONFIG_DMA_UNCACHED_4M is not set
 # CONFIG_DMA_UNCACHED_2M is not set
diff --git a/arch/blackfin/configs/CM-BF527_defconfig b/arch/blackfin/configs/CM-BF527_defconfig
index 648a31d01bf4..4432150d89e3 100644
--- a/arch/blackfin/configs/CM-BF527_defconfig
+++ b/arch/blackfin/configs/CM-BF527_defconfig
@@ -1,12 +1,13 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.28
+# Linux kernel version: 2.6.30.5
 #
 # CONFIG_MMU is not set
 # CONFIG_FPU is not set
 CONFIG_RWSEM_GENERIC_SPINLOCK=y
 # CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
 CONFIG_BLACKFIN=y
+CONFIG_GENERIC_BUG=y
 CONFIG_ZONE_DMA=y
 CONFIG_GENERIC_FIND_NEXT_BIT=y
 CONFIG_GENERIC_HWEIGHT=y
@@ -15,6 +16,9 @@ CONFIG_GENERIC_IRQ_PROBE=y
 CONFIG_GENERIC_GPIO=y
 CONFIG_FORCE_MAX_ZONEORDER=14
 CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
 CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
 
 #
@@ -25,55 +29,72 @@ CONFIG_BROKEN_ON_SMP=y
 CONFIG_INIT_ENV_ARG_LIMIT=32
 CONFIG_LOCALVERSION=""
 CONFIG_LOCALVERSION_AUTO=y
+CONFIG_HAVE_KERNEL_GZIP=y
+CONFIG_HAVE_KERNEL_BZIP2=y
+CONFIG_HAVE_KERNEL_LZMA=y
+# CONFIG_KERNEL_GZIP is not set
+# CONFIG_KERNEL_BZIP2 is not set
+CONFIG_KERNEL_LZMA=y
 CONFIG_SYSVIPC=y
 CONFIG_SYSVIPC_SYSCTL=y
 # CONFIG_POSIX_MQUEUE is not set
 # CONFIG_BSD_PROCESS_ACCT is not set
 # CONFIG_TASKSTATS is not set
 # CONFIG_AUDIT is not set
+
+#
+# RCU Subsystem
+#
+CONFIG_CLASSIC_RCU=y
+# CONFIG_TREE_RCU is not set
+# CONFIG_PREEMPT_RCU is not set
+# CONFIG_TREE_RCU_TRACE is not set
+# CONFIG_PREEMPT_RCU_TRACE is not set
 CONFIG_IKCONFIG=y
 CONFIG_IKCONFIG_PROC=y
 CONFIG_LOG_BUF_SHIFT=14
-# CONFIG_CGROUPS is not set
 # CONFIG_GROUP_SCHED is not set
-CONFIG_SYSFS_DEPRECATED=y
-CONFIG_SYSFS_DEPRECATED_V2=y
+# CONFIG_CGROUPS is not set
+# CONFIG_SYSFS_DEPRECATED_V2 is not set
 # CONFIG_RELAY is not set
 # CONFIG_NAMESPACES is not set
 CONFIG_BLK_DEV_INITRD=y
 CONFIG_INITRAMFS_SOURCE=""
+# CONFIG_RD_GZIP is not set
+# CONFIG_RD_BZIP2 is not set
+CONFIG_RD_LZMA=y
 # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
-# CONFIG_SYSCTL is not set
+CONFIG_SYSCTL=y
+CONFIG_ANON_INODES=y
 CONFIG_EMBEDDED=y
 CONFIG_UID16=y
 # CONFIG_SYSCTL_SYSCALL is not set
 CONFIG_KALLSYMS=y
-# CONFIG_KALLSYMS_ALL is not set
 # CONFIG_KALLSYMS_EXTRA_PASS is not set
+# CONFIG_STRIP_ASM_SYMS is not set
 CONFIG_HOTPLUG=y
 CONFIG_PRINTK=y
 CONFIG_BUG=y
 # CONFIG_ELF_CORE is not set
-CONFIG_COMPAT_BRK=y
 CONFIG_BASE_FULL=y
 # CONFIG_FUTEX is not set
-CONFIG_ANON_INODES=y
 CONFIG_EPOLL=y
 CONFIG_SIGNALFD=y
 CONFIG_TIMERFD=y
 CONFIG_EVENTFD=y
 # CONFIG_AIO is not set
 CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_COMPAT_BRK=y
 CONFIG_SLAB=y
 # CONFIG_SLUB is not set
 # CONFIG_SLOB is not set
+CONFIG_MMAP_ALLOW_UNINITIALIZED=y
 # CONFIG_PROFILING is not set
 # CONFIG_MARKERS is not set
 CONFIG_HAVE_OPROFILE=y
+# CONFIG_SLOW_WORK is not set
 # CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
 CONFIG_SLABINFO=y
-CONFIG_RT_MUTEXES=y
-CONFIG_TINY_SHMEM=y
 CONFIG_BASE_SMALL=0
 CONFIG_MODULES=y
 # CONFIG_MODULE_FORCE_LOAD is not set
@@ -81,11 +102,8 @@ CONFIG_MODULE_UNLOAD=y
 # CONFIG_MODULE_FORCE_UNLOAD is not set
 # CONFIG_MODVERSIONS is not set
 # CONFIG_MODULE_SRCVERSION_ALL is not set
-CONFIG_KMOD=y
 CONFIG_BLOCK=y
 # CONFIG_LBD is not set
-# CONFIG_BLK_DEV_IO_TRACE is not set
-# CONFIG_LSF is not set
 # CONFIG_BLK_DEV_BSG is not set
 # CONFIG_BLK_DEV_INTEGRITY is not set
 
@@ -101,7 +119,6 @@ CONFIG_IOSCHED_CFQ=y
 CONFIG_DEFAULT_CFQ=y
 # CONFIG_DEFAULT_NOOP is not set
 CONFIG_DEFAULT_IOSCHED="cfq"
-CONFIG_CLASSIC_RCU=y
 # CONFIG_PREEMPT_NONE is not set
 CONFIG_PREEMPT_VOLUNTARY=y
 # CONFIG_PREEMPT is not set
@@ -265,7 +282,10 @@ CONFIG_HZ=250
 # CONFIG_SCHED_HRTICK is not set
 CONFIG_GENERIC_TIME=y
 CONFIG_GENERIC_CLOCKEVENTS=y
+# CONFIG_TICKSOURCE_GPTMR0 is not set
+CONFIG_TICKSOURCE_CORETMR=y
 # CONFIG_CYCLES_CLOCKSOURCE is not set
+# CONFIG_GPTMR0_CLOCKSOURCE is not set
 # CONFIG_NO_HZ is not set
 # CONFIG_HIGH_RES_TIMERS is not set
 CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
@@ -315,10 +335,12 @@ CONFIG_FLATMEM=y
 CONFIG_FLAT_NODE_MEM_MAP=y
 CONFIG_PAGEFLAGS_EXTENDED=y
 CONFIG_SPLIT_PTLOCK_CPUS=4
-# CONFIG_RESOURCES_64BIT is not set
 # CONFIG_PHYS_ADDR_T_64BIT is not set
 CONFIG_ZONE_DMA_FLAG=1
 CONFIG_VIRT_TO_BUS=y
+CONFIG_UNEVICTABLE_LRU=y
+CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
+CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0
 CONFIG_BFIN_GPTIMERS=y
 # CONFIG_DMA_UNCACHED_4M is not set
 # CONFIG_DMA_UNCACHED_2M is not set
@@ -329,10 +351,9 @@ CONFIG_DMA_UNCACHED_1M=y
 # Cache Support
 #
 CONFIG_BFIN_ICACHE=y
-# CONFIG_BFIN_ICACHE_LOCK is not set
+CONFIG_BFIN_EXTMEM_ICACHEABLE=y
 CONFIG_BFIN_DCACHE=y
 # CONFIG_BFIN_DCACHE_BANKA is not set
-CONFIG_BFIN_EXTMEM_ICACHEABLE=y
 CONFIG_BFIN_EXTMEM_DCACHEABLE=y
 CONFIG_BFIN_EXTMEM_WRITEBACK=y
 # CONFIG_BFIN_EXTMEM_WRITETHROUGH is not set
@@ -343,7 +364,7 @@ CONFIG_BFIN_EXTMEM_WRITEBACK=y
 # CONFIG_MPU is not set
 
 #
-# Asynchonous Memory Configuration
+# Asynchronous Memory Configuration
 #
 
 #
@@ -361,7 +382,7 @@ CONFIG_C_AMBEN_ALL=y
 # EBIU_AMBCTL Control
 #
 CONFIG_BANK_0=0x7BB0
-CONFIG_BANK_1=0x5554
+CONFIG_BANK_1=0x7BB0
 CONFIG_BANK_2=0x7BB0
 CONFIG_BANK_3=0xFFC0
 
@@ -386,7 +407,6 @@ CONFIG_BINFMT_ZFLAT=y
 #
 # CONFIG_PM is not set
 CONFIG_ARCH_SUSPEND_POSSIBLE=y
-# CONFIG_PM_WAKEUP_BY_GPIO is not set
 
 #
 # CPU Frequency scaling
@@ -400,11 +420,6 @@ CONFIG_NET=y
 CONFIG_PACKET=y
 # CONFIG_PACKET_MMAP is not set
 CONFIG_UNIX=y
-CONFIG_XFRM=y
-# CONFIG_XFRM_USER is not set
-# CONFIG_XFRM_SUB_POLICY is not set
-# CONFIG_XFRM_MIGRATE is not set
-# CONFIG_XFRM_STATISTICS is not set
 # CONFIG_NET_KEY is not set
 CONFIG_INET=y
 # CONFIG_IP_MULTICAST is not set
@@ -428,7 +443,6 @@ CONFIG_IP_PNP=y
 # CONFIG_INET_XFRM_MODE_BEET is not set
 # CONFIG_INET_LRO is not set
 # CONFIG_INET_DIAG is not set
-CONFIG_INET_TCP_DIAG=y
 # CONFIG_TCP_CONG_ADVANCED is not set
 CONFIG_TCP_CONG_CUBIC=y
 CONFIG_DEFAULT_TCP_CONG="cubic"
@@ -452,7 +466,9 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
 # CONFIG_LAPB is not set
 # CONFIG_ECONET is not set
 # CONFIG_WAN_ROUTER is not set
+# CONFIG_PHONET is not set
 # CONFIG_NET_SCHED is not set
+# CONFIG_DCB is not set
 
 #
 # Network testing
@@ -463,13 +479,8 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
 # CONFIG_IRDA is not set
 # CONFIG_BT is not set
 # CONFIG_AF_RXRPC is not set
-# CONFIG_PHONET is not set
-CONFIG_WIRELESS=y
-# CONFIG_CFG80211 is not set
-CONFIG_WIRELESS_OLD_REGULATORY=y
-# CONFIG_WIRELESS_EXT is not set
-# CONFIG_MAC80211 is not set
-# CONFIG_IEEE80211 is not set
+# CONFIG_WIRELESS is not set
+# CONFIG_WIMAX is not set
 # CONFIG_RFKILL is not set
 # CONFIG_NET_9P is not set
 
@@ -484,22 +495,21 @@ CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 CONFIG_STANDALONE=y
 CONFIG_PREVENT_FIRMWARE_BUILD=y
 # CONFIG_FW_LOADER is not set
-# CONFIG_DEBUG_DRIVER is not set
-# CONFIG_DEBUG_DEVRES is not set
 # CONFIG_SYS_HYPERVISOR is not set
 # CONFIG_CONNECTOR is not set
 CONFIG_MTD=y
 # CONFIG_MTD_DEBUG is not set
+# CONFIG_MTD_TESTS is not set
 # CONFIG_MTD_CONCAT is not set
 CONFIG_MTD_PARTITIONS=y
 # CONFIG_MTD_REDBOOT_PARTS is not set
-# CONFIG_MTD_CMDLINE_PARTS is not set
+CONFIG_MTD_CMDLINE_PARTS=y
 # CONFIG_MTD_AR7_PARTS is not set
 
 #
 # User Modules And Translation Layers
 #
-CONFIG_MTD_CHAR=m
+CONFIG_MTD_CHAR=y
 CONFIG_MTD_BLKDEVS=y
 CONFIG_MTD_BLOCK=y
 # CONFIG_FTL is not set
@@ -512,9 +522,9 @@ CONFIG_MTD_BLOCK=y
 #
 # RAM/ROM/Flash chip drivers
 #
-# CONFIG_MTD_CFI is not set
-CONFIG_MTD_JEDECPROBE=m
-CONFIG_MTD_GEN_PROBE=m
+CONFIG_MTD_CFI=y
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_GEN_PROBE=y
 # CONFIG_MTD_CFI_ADV_OPTIONS is not set
 CONFIG_MTD_MAP_BANK_WIDTH_1=y
 CONFIG_MTD_MAP_BANK_WIDTH_2=y
@@ -526,9 +536,11 @@ CONFIG_MTD_CFI_I1=y
 CONFIG_MTD_CFI_I2=y
 # CONFIG_MTD_CFI_I4 is not set
 # CONFIG_MTD_CFI_I8 is not set
-# CONFIG_MTD_CFI_INTELEXT is not set
+CONFIG_MTD_CFI_INTELEXT=y
 # CONFIG_MTD_CFI_AMDSTD is not set
 # CONFIG_MTD_CFI_STAA is not set
+# CONFIG_MTD_PSD4256G is not set
+CONFIG_MTD_CFI_UTIL=y
 CONFIG_MTD_RAM=y
 CONFIG_MTD_ROM=m
 # CONFIG_MTD_ABSENT is not set
@@ -538,7 +550,7 @@ CONFIG_MTD_ROM=m
 #
 CONFIG_MTD_COMPLEX_MAPPINGS=y
 # CONFIG_MTD_PHYSMAP is not set
-# CONFIG_MTD_GPIO_ADDR is not set
+CONFIG_MTD_GPIO_ADDR=y
 # CONFIG_MTD_UCLINUX is not set
 # CONFIG_MTD_PLATRAM is not set
 
@@ -562,6 +574,11 @@ CONFIG_MTD_COMPLEX_MAPPINGS=y
 # CONFIG_MTD_ONENAND is not set
 
 #
+# LPDDR flash memory drivers
+#
+# CONFIG_MTD_LPDDR is not set
+
+#
 # UBI - Unsorted block images
 #
 # CONFIG_MTD_UBI is not set
@@ -586,12 +603,46 @@ CONFIG_HAVE_IDE=y
 # SCSI device support
 #
 # CONFIG_RAID_ATTRS is not set
-# CONFIG_SCSI is not set
-# CONFIG_SCSI_DMA is not set
+CONFIG_SCSI=y
+CONFIG_SCSI_DMA=y
+# CONFIG_SCSI_TGT is not set
 # CONFIG_SCSI_NETLINK is not set
+CONFIG_SCSI_PROC_FS=y
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+# CONFIG_BLK_DEV_SR is not set
+# CONFIG_CHR_DEV_SG is not set
+# CONFIG_CHR_DEV_SCH is not set
+
+#
+# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
+#
+# CONFIG_SCSI_MULTI_LUN is not set
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+# CONFIG_SCSI_SCAN_ASYNC is not set
+CONFIG_SCSI_WAIT_SCAN=m
+
+#
+# SCSI Transports
+#
+# CONFIG_SCSI_SPI_ATTRS is not set
+# CONFIG_SCSI_FC_ATTRS is not set
+# CONFIG_SCSI_ISCSI_ATTRS is not set
+# CONFIG_SCSI_SAS_LIBSAS is not set
+# CONFIG_SCSI_SRP_ATTRS is not set
+# CONFIG_SCSI_LOWLEVEL is not set
+# CONFIG_SCSI_DH is not set
+# CONFIG_SCSI_OSD_INITIATOR is not set
 # CONFIG_ATA is not set
 # CONFIG_MD is not set
 CONFIG_NETDEVICES=y
+CONFIG_COMPAT_NET_DEV_OPS=y
 # CONFIG_DUMMY is not set
 # CONFIG_BONDING is not set
 # CONFIG_MACVLAN is not set
@@ -613,6 +664,9 @@ CONFIG_PHYLIB=y
 # CONFIG_BROADCOM_PHY is not set
 # CONFIG_ICPLUS_PHY is not set
 # CONFIG_REALTEK_PHY is not set
+# CONFIG_NATIONAL_PHY is not set
+# CONFIG_STE10XP is not set
+# CONFIG_LSI_ET1011C_PHY is not set
 # CONFIG_FIXED_PHY is not set
 # CONFIG_MDIO_BITBANG is not set
 CONFIG_NET_ETHERNET=y
@@ -623,9 +677,11 @@ CONFIG_BFIN_TX_DESC_NUM=10
 CONFIG_BFIN_RX_DESC_NUM=20
 CONFIG_BFIN_MAC_RMII=y
 # CONFIG_SMC91X is not set
-# CONFIG_SMSC911X is not set
 # CONFIG_DM9000 is not set
 # CONFIG_ENC28J60 is not set
+# CONFIG_ETHOC is not set
+# CONFIG_SMSC911X is not set
+# CONFIG_DNET is not set
 # CONFIG_IBM_NEW_EMAC_ZMII is not set
 # CONFIG_IBM_NEW_EMAC_RGMII is not set
 # CONFIG_IBM_NEW_EMAC_TAH is not set
@@ -633,6 +689,7 @@ CONFIG_BFIN_MAC_RMII=y
 # CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
 # CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
 # CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
+# CONFIG_B44 is not set
 # CONFIG_NETDEV_1000 is not set
 # CONFIG_NETDEV_10000 is not set
 
@@ -641,7 +698,10 @@ CONFIG_BFIN_MAC_RMII=y
 #
 # CONFIG_WLAN_PRE80211 is not set
 # CONFIG_WLAN_80211 is not set
-# CONFIG_IWLWIFI_LEDS is not set
+
+#
+# Enable WiMAX (Networking options) to see the WiMAX drivers
+#
 
 #
 # USB Network Adapters
@@ -674,17 +734,13 @@ CONFIG_BFIN_MAC_RMII=y
 #
 # Character devices
 #
-# CONFIG_AD9960 is not set
-# CONFIG_SPI_ADC_BF533 is not set
-# CONFIG_BF5xx_PPIFCD is not set
+CONFIG_BFIN_DMA_INTERFACE=m
+# CONFIG_BFIN_PPI is not set
+# CONFIG_BFIN_PPIFCD is not set
 # CONFIG_BFIN_SIMPLE_TIMER is not set
-# CONFIG_BF5xx_PPI is not set
-# CONFIG_BF5xx_EPPI is not set
+# CONFIG_BFIN_SPI_ADC is not set
 # CONFIG_BFIN_SPORT is not set
-# CONFIG_BFIN_TIMER_LATENCY is not set
-# CONFIG_TWI_LCD is not set
-CONFIG_BFIN_DMA_INTERFACE=m
-CONFIG_SIMPLE_GPIO=m
+# CONFIG_BFIN_TWI_LCD is not set
 # CONFIG_VT is not set
 # CONFIG_DEVKMEM is not set
 # CONFIG_BFIN_JTAG_COMM is not set
@@ -698,6 +754,7 @@ CONFIG_SIMPLE_GPIO=m
 #
 # Non-8250 serial port support
 #
+# CONFIG_SERIAL_MAX3100 is not set
 CONFIG_SERIAL_BFIN=y
 CONFIG_SERIAL_BFIN_CONSOLE=y
 CONFIG_SERIAL_BFIN_DMA=y
@@ -710,6 +767,7 @@ CONFIG_SERIAL_CORE=y
 CONFIG_SERIAL_CORE_CONSOLE=y
 # CONFIG_SERIAL_BFIN_SPORT is not set
 CONFIG_UNIX98_PTYS=y
+# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
 # CONFIG_LEGACY_PTYS is not set
 CONFIG_BFIN_OTP=y
 # CONFIG_BFIN_OTP_WRITE_ENABLE is not set
@@ -758,13 +816,9 @@ CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=100
 # Miscellaneous I2C Chip support
 #
 # CONFIG_DS1682 is not set
-# CONFIG_AT24 is not set
-# CONFIG_SENSORS_AD5252 is not set
-# CONFIG_SENSORS_EEPROM is not set
 # CONFIG_SENSORS_PCF8574 is not set
 # CONFIG_PCF8575 is not set
 # CONFIG_SENSORS_PCA9539 is not set
-# CONFIG_SENSORS_PCF8591 is not set
 # CONFIG_SENSORS_MAX6875 is not set
 # CONFIG_SENSORS_TSL2550 is not set
 # CONFIG_I2C_DEBUG_CORE is not set
@@ -772,7 +826,6 @@ CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=100
 # CONFIG_I2C_DEBUG_BUS is not set
 # CONFIG_I2C_DEBUG_CHIP is not set
 CONFIG_SPI=y
-# CONFIG_SPI_DEBUG is not set
 CONFIG_SPI_MASTER=y
 
 #
@@ -780,17 +833,17 @@ CONFIG_SPI_MASTER=y
 #
 CONFIG_SPI_BFIN=y
 # CONFIG_SPI_BFIN_LOCK is not set
+# CONFIG_SPI_BFIN_SPORT is not set
 # CONFIG_SPI_BITBANG is not set
+# CONFIG_SPI_GPIO is not set
 
 #
 # SPI Protocol Masters
 #
-# CONFIG_SPI_AT25 is not set
 # CONFIG_SPI_SPIDEV is not set
 # CONFIG_SPI_TLE62X0 is not set
 CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
 CONFIG_GPIOLIB=y
-# CONFIG_DEBUG_GPIO is not set
 CONFIG_GPIO_SYSFS=y
 
 #
@@ -803,6 +856,7 @@ CONFIG_GPIO_SYSFS=y
 # CONFIG_GPIO_MAX732X is not set
 # CONFIG_GPIO_PCA953X is not set
 # CONFIG_GPIO_PCF857X is not set
+# CONFIG_GPIO_ADP5588 is not set
 
 #
 # PCI GPIO expanders:
@@ -829,11 +883,13 @@ CONFIG_HWMON=y
 # CONFIG_SENSORS_ADT7462 is not set
 # CONFIG_SENSORS_ADT7470 is not set
 # CONFIG_SENSORS_ADT7473 is not set
+# CONFIG_SENSORS_ADT7475 is not set
 # CONFIG_SENSORS_ATXP1 is not set
 # CONFIG_SENSORS_DS1621 is not set
 # CONFIG_SENSORS_F71805F is not set
 # CONFIG_SENSORS_F71882FG is not set
 # CONFIG_SENSORS_F75375S is not set
+# CONFIG_SENSORS_G760A is not set
 # CONFIG_SENSORS_GL518SM is not set
 # CONFIG_SENSORS_GL520SM is not set
 # CONFIG_SENSORS_IT87 is not set
@@ -849,11 +905,16 @@ CONFIG_HWMON=y
 # CONFIG_SENSORS_LM90 is not set
 # CONFIG_SENSORS_LM92 is not set
 # CONFIG_SENSORS_LM93 is not set
+# CONFIG_SENSORS_LTC4215 is not set
+# CONFIG_SENSORS_LTC4245 is not set
+# CONFIG_SENSORS_LM95241 is not set
 # CONFIG_SENSORS_MAX1111 is not set
 # CONFIG_SENSORS_MAX1619 is not set
 # CONFIG_SENSORS_MAX6650 is not set
 # CONFIG_SENSORS_PC87360 is not set
 # CONFIG_SENSORS_PC87427 is not set
+# CONFIG_SENSORS_PCF8591 is not set
+# CONFIG_SENSORS_SHT15 is not set
 # CONFIG_SENSORS_DME1737 is not set
 # CONFIG_SENSORS_SMSC47M1 is not set
 # CONFIG_SENSORS_SMSC47M192 is not set
@@ -885,6 +946,12 @@ CONFIG_BFIN_WDT=y
 # USB-based Watchdog Cards
 #
 # CONFIG_USBPCWATCHDOG is not set
+CONFIG_SSB_POSSIBLE=y
+
+#
+# Sonics Silicon Backplane
+#
+# CONFIG_SSB is not set
 
 #
 # Multifunction device drivers
@@ -892,10 +959,14 @@ CONFIG_BFIN_WDT=y
 # CONFIG_MFD_CORE is not set
 # CONFIG_MFD_SM501 is not set
 # CONFIG_HTC_PASIC3 is not set
+# CONFIG_TPS65010 is not set
+# CONFIG_TWL4030_CORE is not set
 # CONFIG_MFD_TMIO is not set
 # CONFIG_PMIC_DA903X is not set
+# CONFIG_PMIC_ADP5520 is not set
 # CONFIG_MFD_WM8400 is not set
 # CONFIG_MFD_WM8350_I2C is not set
+# CONFIG_MFD_PCF50633 is not set
 # CONFIG_REGULATOR is not set
 
 #
@@ -931,20 +1002,20 @@ CONFIG_USB_SUPPORT=y
 CONFIG_USB_ARCH_HAS_HCD=y
 # CONFIG_USB_ARCH_HAS_OHCI is not set
 # CONFIG_USB_ARCH_HAS_EHCI is not set
-CONFIG_USB=y
+CONFIG_USB=m
 # CONFIG_USB_DEBUG is not set
-# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
+CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
 
 #
 # Miscellaneous USB options
 #
-# CONFIG_USB_DEVICEFS is not set
-CONFIG_USB_DEVICE_CLASS=y
+CONFIG_USB_DEVICEFS=y
+# CONFIG_USB_DEVICE_CLASS is not set
 # CONFIG_USB_DYNAMIC_MINORS is not set
 # CONFIG_USB_OTG is not set
 # CONFIG_USB_OTG_WHITELIST is not set
 CONFIG_USB_OTG_BLACKLIST_HUB=y
-CONFIG_USB_MON=y
+CONFIG_USB_MON=m
 # CONFIG_USB_WUSB is not set
 # CONFIG_USB_WUSB_CBAF is not set
 
@@ -952,24 +1023,24 @@ CONFIG_USB_MON=y
 # USB Host Controller Drivers
 #
 # CONFIG_USB_C67X00_HCD is not set
+# CONFIG_USB_OXU210HP_HCD is not set
 # CONFIG_USB_ISP116X_HCD is not set
 # CONFIG_USB_ISP1760_HCD is not set
 # CONFIG_USB_ISP1362_HCD is not set
 # CONFIG_USB_SL811_HCD is not set
 # CONFIG_USB_R8A66597_HCD is not set
 # CONFIG_USB_HWA_HCD is not set
-CONFIG_USB_MUSB_HDRC=y
+CONFIG_USB_MUSB_HDRC=m
 CONFIG_USB_MUSB_SOC=y
 
 #
 # Blackfin high speed USB Support
 #
-CONFIG_USB_MUSB_HOST=y
-# CONFIG_USB_MUSB_PERIPHERAL is not set
+# CONFIG_USB_MUSB_HOST is not set
+CONFIG_USB_MUSB_PERIPHERAL=y
 # CONFIG_USB_MUSB_OTG is not set
-CONFIG_USB_MUSB_HDRC_HCD=y
+CONFIG_USB_GADGET_MUSB_HDRC=y
 CONFIG_MUSB_PIO_ONLY=y
-CONFIG_MUSB_DMA_POLL=y
 # CONFIG_USB_MUSB_DEBUG is not set
 
 #
@@ -981,18 +1052,31 @@ CONFIG_MUSB_DMA_POLL=y
 # CONFIG_USB_TMC is not set
 
 #
-# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may also be needed;
+# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
 #
 
 #
-# see USB_STORAGE Help for more information
+# also be needed; see USB_STORAGE Help for more info
 #
+CONFIG_USB_STORAGE=m
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
+# CONFIG_USB_STORAGE_USBAT is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_SDDR55 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_STORAGE_ALAUDA is not set
+# CONFIG_USB_STORAGE_KARMA is not set
+# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
 # CONFIG_USB_LIBUSUAL is not set
 
 #
 # USB Imaging devices
 #
 # CONFIG_USB_MDC800 is not set
+# CONFIG_USB_MICROTEK is not set
 
 #
 # USB port drivers
@@ -1013,7 +1097,6 @@ CONFIG_MUSB_DMA_POLL=y
 # CONFIG_USB_LED is not set
 # CONFIG_USB_CYPRESS_CY7C63 is not set
 # CONFIG_USB_CYTHERM is not set
-# CONFIG_USB_PHIDGET is not set
 # CONFIG_USB_IDMOUSE is not set
 # CONFIG_USB_FTDI_ELAN is not set
 # CONFIG_USB_APPLEDISPLAY is not set
@@ -1021,9 +1104,50 @@ CONFIG_MUSB_DMA_POLL=y
 # CONFIG_USB_LD is not set
 # CONFIG_USB_TRANCEVIBRATOR is not set
 # CONFIG_USB_IOWARRIOR is not set
+# CONFIG_USB_TEST is not set
 # CONFIG_USB_ISIGHTFW is not set
 # CONFIG_USB_VST is not set
-# CONFIG_USB_GADGET is not set
+CONFIG_USB_GADGET=m
+# CONFIG_USB_GADGET_DEBUG_FILES is not set
+# CONFIG_USB_GADGET_DEBUG_FS is not set
+CONFIG_USB_GADGET_VBUS_DRAW=2
+CONFIG_USB_GADGET_SELECTED=y
+# CONFIG_USB_GADGET_AT91 is not set
+# CONFIG_USB_GADGET_ATMEL_USBA is not set
+# CONFIG_USB_GADGET_FSL_USB2 is not set
+# CONFIG_USB_GADGET_LH7A40X is not set
+# CONFIG_USB_GADGET_OMAP is not set
+# CONFIG_USB_GADGET_PXA25X is not set
+# CONFIG_USB_GADGET_PXA27X is not set
+# CONFIG_USB_GADGET_S3C2410 is not set
+# CONFIG_USB_GADGET_IMX is not set
+# CONFIG_USB_GADGET_M66592 is not set
+# CONFIG_USB_GADGET_AMD5536UDC is not set
+# CONFIG_USB_GADGET_FSL_QE is not set
+# CONFIG_USB_GADGET_CI13XXX is not set
+# CONFIG_USB_GADGET_NET2272 is not set
+# CONFIG_USB_GADGET_NET2280 is not set
+# CONFIG_USB_GADGET_GOKU is not set
+# CONFIG_USB_GADGET_DUMMY_HCD is not set
+CONFIG_USB_GADGET_DUALSPEED=y
+# CONFIG_USB_ZERO is not set
+# CONFIG_USB_AUDIO is not set
+CONFIG_USB_ETH=m
+CONFIG_USB_ETH_RNDIS=y
+# CONFIG_USB_GADGETFS is not set
+CONFIG_USB_FILE_STORAGE=m
+# CONFIG_USB_FILE_STORAGE_TEST is not set
+CONFIG_USB_G_SERIAL=m
+# CONFIG_USB_MIDI_GADGET is not set
+CONFIG_USB_G_PRINTER=m
+# CONFIG_USB_CDC_COMPOSITE is not set
+
+#
+# OTG and related infrastructure
+#
+CONFIG_USB_OTG_UTILS=y
+# CONFIG_USB_GPIO_VBUS is not set
+# CONFIG_NOP_USB_XCEIV is not set
 # CONFIG_MMC is not set
 # CONFIG_MEMSTICK is not set
 # CONFIG_NEW_LEDS is not set
@@ -1090,6 +1214,7 @@ CONFIG_RTC_INTF_DEV=y
 #
 CONFIG_RTC_DRV_BFIN=y
 # CONFIG_DMADEVICES is not set
+# CONFIG_AUXDISPLAY is not set
 # CONFIG_UIO is not set
 # CONFIG_STAGING is not set
 
@@ -1102,9 +1227,10 @@ CONFIG_RTC_DRV_BFIN=y
 # CONFIG_REISERFS_FS is not set
 # CONFIG_JFS_FS is not set
 # CONFIG_FS_POSIX_ACL is not set
-CONFIG_FILE_LOCKING=y
 # CONFIG_XFS_FS is not set
 # CONFIG_OCFS2_FS is not set
+# CONFIG_BTRFS_FS is not set
+CONFIG_FILE_LOCKING=y
 # CONFIG_DNOTIFY is not set
 CONFIG_INOTIFY=y
 CONFIG_INOTIFY_USER=y
@@ -1114,6 +1240,11 @@ CONFIG_INOTIFY_USER=y
 # CONFIG_FUSE_FS is not set
 
 #
+# Caches
+#
+# CONFIG_FSCACHE is not set
+
+#
 # CD-ROM/DVD Filesystems
 #
 # CONFIG_ISO9660_FS is not set
@@ -1122,8 +1253,11 @@ CONFIG_INOTIFY_USER=y
 #
 # DOS/FAT/NT Filesystems
 #
-# CONFIG_MSDOS_FS is not set
-# CONFIG_VFAT_FS is not set
+CONFIG_FAT_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
 # CONFIG_NTFS_FS is not set
 
 #
@@ -1135,10 +1269,7 @@ CONFIG_SYSFS=y
 # CONFIG_TMPFS is not set
 # CONFIG_HUGETLB_PAGE is not set
 # CONFIG_CONFIGFS_FS is not set
-
-#
-# Miscellaneous filesystems
-#
+CONFIG_MISC_FILESYSTEMS=y
 # CONFIG_ADFS_FS is not set
 # CONFIG_AFFS_FS is not set
 # CONFIG_HFS_FS is not set
@@ -1146,9 +1277,19 @@ CONFIG_SYSFS=y
 # CONFIG_BEFS_FS is not set
 # CONFIG_BFS_FS is not set
 # CONFIG_EFS_FS is not set
-# CONFIG_YAFFS_FS is not set
-# CONFIG_JFFS2_FS is not set
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_DEBUG=0
+CONFIG_JFFS2_FS_WRITEBUFFER=y
+# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
+# CONFIG_JFFS2_SUMMARY is not set
+# CONFIG_JFFS2_FS_XATTR is not set
+# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
+CONFIG_JFFS2_ZLIB=y
+# CONFIG_JFFS2_LZO is not set
+CONFIG_JFFS2_RTIME=y
+# CONFIG_JFFS2_RUBIN is not set
 # CONFIG_CRAMFS is not set
+# CONFIG_SQUASHFS is not set
 # CONFIG_VXFS_FS is not set
 # CONFIG_MINIX_FS is not set
 # CONFIG_OMFS_FS is not set
@@ -1157,6 +1298,7 @@ CONFIG_SYSFS=y
 # CONFIG_ROMFS_FS is not set
 # CONFIG_SYSV_FS is not set
 # CONFIG_UFS_FS is not set
+# CONFIG_NILFS2_FS is not set
 CONFIG_NETWORK_FILESYSTEMS=y
 CONFIG_NFS_FS=m
 CONFIG_NFS_V3=y
@@ -1167,7 +1309,6 @@ CONFIG_LOCKD=m
 CONFIG_LOCKD_V4=y
 CONFIG_NFS_COMMON=y
 CONFIG_SUNRPC=m
-# CONFIG_SUNRPC_REGISTER_V4 is not set
 # CONFIG_RPCSEC_GSS_KRB5 is not set
 # CONFIG_RPCSEC_GSS_SPKM3 is not set
 CONFIG_SMB_FS=m
@@ -1182,9 +1323,9 @@ CONFIG_SMB_FS=m
 #
 # CONFIG_PARTITION_ADVANCED is not set
 CONFIG_MSDOS_PARTITION=y
-CONFIG_NLS=m
+CONFIG_NLS=y
 CONFIG_NLS_DEFAULT="iso8859-1"
-# CONFIG_NLS_CODEPAGE_437 is not set
+CONFIG_NLS_CODEPAGE_437=y
 # CONFIG_NLS_CODEPAGE_737 is not set
 # CONFIG_NLS_CODEPAGE_775 is not set
 # CONFIG_NLS_CODEPAGE_850 is not set
@@ -1208,7 +1349,7 @@ CONFIG_NLS_DEFAULT="iso8859-1"
 # CONFIG_NLS_CODEPAGE_1250 is not set
 # CONFIG_NLS_CODEPAGE_1251 is not set
 # CONFIG_NLS_ASCII is not set
-# CONFIG_NLS_ISO8859_1 is not set
+CONFIG_NLS_ISO8859_1=y
 # CONFIG_NLS_ISO8859_2 is not set
 # CONFIG_NLS_ISO8859_3 is not set
 # CONFIG_NLS_ISO8859_4 is not set
@@ -1235,55 +1376,34 @@ CONFIG_FRAME_WARN=1024
 # CONFIG_UNUSED_SYMBOLS is not set
 CONFIG_DEBUG_FS=y
 # CONFIG_HEADERS_CHECK is not set
-CONFIG_DEBUG_KERNEL=y
-# CONFIG_DEBUG_SHIRQ is not set
-CONFIG_DETECT_SOFTLOCKUP=y
-# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
-CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
-# CONFIG_SCHED_DEBUG is not set
-# CONFIG_SCHEDSTATS is not set
-# CONFIG_TIMER_STATS is not set
-# CONFIG_DEBUG_OBJECTS is not set
-# CONFIG_DEBUG_SLAB is not set
-# CONFIG_DEBUG_RT_MUTEXES is not set
-# CONFIG_RT_MUTEX_TESTER is not set
-# CONFIG_DEBUG_SPINLOCK is not set
-# CONFIG_DEBUG_MUTEXES is not set
-# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
-# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
-# CONFIG_DEBUG_KOBJECT is not set
-CONFIG_DEBUG_BUGVERBOSE=y
-# CONFIG_DEBUG_INFO is not set
-# CONFIG_DEBUG_VM is not set
-# CONFIG_DEBUG_WRITECOUNT is not set
+CONFIG_DEBUG_SECTION_MISMATCH=y
+# CONFIG_DEBUG_KERNEL is not set
+# CONFIG_DEBUG_BUGVERBOSE is not set
 # CONFIG_DEBUG_MEMORY_INIT is not set
-# CONFIG_DEBUG_LIST is not set
-# CONFIG_DEBUG_SG is not set
-# CONFIG_FRAME_POINTER is not set
-# CONFIG_BOOT_PRINTK_DELAY is not set
-# CONFIG_RCU_TORTURE_TEST is not set
 # CONFIG_RCU_CPU_STALL_DETECTOR is not set
-# CONFIG_BACKTRACE_SELF_TEST is not set
-# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
-# CONFIG_FAULT_INJECTION is not set
-# CONFIG_SYSCTL_SYSCALL_CHECK is not set
+CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
+CONFIG_TRACING_SUPPORT=y
 
 #
 # Tracers
 #
+# CONFIG_FUNCTION_TRACER is not set
+# CONFIG_IRQSOFF_TRACER is not set
 # CONFIG_SCHED_TRACER is not set
 # CONFIG_CONTEXT_SWITCH_TRACER is not set
+# CONFIG_EVENT_TRACER is not set
 # CONFIG_BOOT_TRACER is not set
-# CONFIG_DYNAMIC_PRINTK_DEBUG is not set
+# CONFIG_TRACE_BRANCH_PROFILING is not set
+# CONFIG_STACK_TRACER is not set
+# CONFIG_KMEMTRACE is not set
+# CONFIG_WORKQUEUE_TRACER is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_DYNAMIC_DEBUG is not set
 # CONFIG_SAMPLES is not set
 CONFIG_HAVE_ARCH_KGDB=y
-# CONFIG_KGDB is not set
-# CONFIG_DEBUG_STACKOVERFLOW is not set
-# CONFIG_DEBUG_STACK_USAGE is not set
-# CONFIG_KGDB_TESTCASE is not set
 CONFIG_DEBUG_VERBOSE=y
-CONFIG_DEBUG_MMRS=y
-# CONFIG_DEBUG_HWERR is not set
+# CONFIG_DEBUG_MMRS is not set
 # CONFIG_DEBUG_DOUBLEFAULT is not set
 CONFIG_DEBUG_HUNT_FOR_ZERO=y
 CONFIG_DEBUG_BFIN_HWTRACE_ON=y
@@ -1293,9 +1413,10 @@ CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_OFF=y
 CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION=0
 # CONFIG_DEBUG_BFIN_HWTRACE_EXPAND is not set
 # CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE is not set
-# CONFIG_EARLY_PRINTK is not set
+CONFIG_EARLY_PRINTK=y
 # CONFIG_CPLB_INFO is not set
 CONFIG_ACCESS_CHECK=y
+# CONFIG_BFIN_ISRAM_SELF_TEST is not set
 
 #
 # Security options
@@ -1304,9 +1425,9 @@ CONFIG_ACCESS_CHECK=y
 CONFIG_SECURITY=y
 # CONFIG_SECURITYFS is not set
 # CONFIG_SECURITY_NETWORK is not set
+# CONFIG_SECURITY_PATH is not set
 # CONFIG_SECURITY_FILE_CAPABILITIES is not set
-# CONFIG_SECURITY_ROOTPLUG is not set
-CONFIG_SECURITY_DEFAULT_MMAP_MIN_ADDR=0
+# CONFIG_SECURITY_TOMOYO is not set
 CONFIG_CRYPTO=y
 
 #
@@ -1385,6 +1506,7 @@ CONFIG_CRYPTO=y
 # Compression
 #
 # CONFIG_CRYPTO_DEFLATE is not set
+# CONFIG_CRYPTO_ZLIB is not set
 # CONFIG_CRYPTO_LZO is not set
 
 #
@@ -1392,20 +1514,24 @@ CONFIG_CRYPTO=y
 #
 # CONFIG_CRYPTO_ANSI_CPRNG is not set
 CONFIG_CRYPTO_HW=y
+# CONFIG_BINARY_PRINTF is not set
 
 #
 # Library routines
 #
 CONFIG_BITREVERSE=y
+CONFIG_GENERIC_FIND_LAST_BIT=y
 CONFIG_CRC_CCITT=m
 # CONFIG_CRC16 is not set
 # CONFIG_CRC_T10DIF is not set
-# CONFIG_CRC_ITU_T is not set
+CONFIG_CRC_ITU_T=y
 CONFIG_CRC32=y
-# CONFIG_CRC7 is not set
+CONFIG_CRC7=y
 # CONFIG_LIBCRC32C is not set
 CONFIG_ZLIB_INFLATE=y
-CONFIG_PLIST=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_DECOMPRESS_LZMA=y
 CONFIG_HAS_IOMEM=y
 CONFIG_HAS_IOPORT=y
 CONFIG_HAS_DMA=y
+CONFIG_NLATTR=y
diff --git a/arch/blackfin/configs/CM-BF533_defconfig b/arch/blackfin/configs/CM-BF533_defconfig
index ae665b93b875..df56639ab2f2 100644
--- a/arch/blackfin/configs/CM-BF533_defconfig
+++ b/arch/blackfin/configs/CM-BF533_defconfig
@@ -1,94 +1,110 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.22.16
+# Linux kernel version: 2.6.30.5
 #
 # CONFIG_MMU is not set
 # CONFIG_FPU is not set
 CONFIG_RWSEM_GENERIC_SPINLOCK=y
 # CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
 CONFIG_BLACKFIN=y
+CONFIG_GENERIC_BUG=y
 CONFIG_ZONE_DMA=y
-CONFIG_SEMAPHORE_SLEEPERS=y
 CONFIG_GENERIC_FIND_NEXT_BIT=y
 CONFIG_GENERIC_HWEIGHT=y
 CONFIG_GENERIC_HARDIRQS=y
 CONFIG_GENERIC_IRQ_PROBE=y
-CONFIG_GENERIC_TIME=y
 CONFIG_GENERIC_GPIO=y
 CONFIG_FORCE_MAX_ZONEORDER=14
 CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
 CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
 
 #
-# Code maturity level options
+# General setup
 #
 CONFIG_EXPERIMENTAL=y
 CONFIG_BROKEN_ON_SMP=y
 CONFIG_INIT_ENV_ARG_LIMIT=32
-
-#
-# General setup
-#
 CONFIG_LOCALVERSION=""
 CONFIG_LOCALVERSION_AUTO=y
+CONFIG_HAVE_KERNEL_GZIP=y
+CONFIG_HAVE_KERNEL_BZIP2=y
+CONFIG_HAVE_KERNEL_LZMA=y
+# CONFIG_KERNEL_GZIP is not set
+# CONFIG_KERNEL_BZIP2 is not set
+CONFIG_KERNEL_LZMA=y
 CONFIG_SYSVIPC=y
-# CONFIG_IPC_NS is not set
 CONFIG_SYSVIPC_SYSCTL=y
 # CONFIG_POSIX_MQUEUE is not set
 # CONFIG_BSD_PROCESS_ACCT is not set
 # CONFIG_TASKSTATS is not set
-# CONFIG_UTS_NS is not set
 # CONFIG_AUDIT is not set
+
+#
+# RCU Subsystem
+#
+CONFIG_CLASSIC_RCU=y
+# CONFIG_TREE_RCU is not set
+# CONFIG_PREEMPT_RCU is not set
+# CONFIG_TREE_RCU_TRACE is not set
+# CONFIG_PREEMPT_RCU_TRACE is not set
 CONFIG_IKCONFIG=y
 CONFIG_IKCONFIG_PROC=y
 CONFIG_LOG_BUF_SHIFT=14
-# CONFIG_SYSFS_DEPRECATED is not set
+# CONFIG_GROUP_SCHED is not set
+# CONFIG_CGROUPS is not set
+# CONFIG_SYSFS_DEPRECATED_V2 is not set
 # CONFIG_RELAY is not set
-# CONFIG_BLK_DEV_INITRD is not set
-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
-# CONFIG_SYSCTL is not set
+# CONFIG_NAMESPACES is not set
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+# CONFIG_RD_GZIP is not set
+# CONFIG_RD_BZIP2 is not set
+CONFIG_RD_LZMA=y
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_SYSCTL=y
+CONFIG_ANON_INODES=y
 CONFIG_EMBEDDED=y
 # CONFIG_UID16 is not set
 # CONFIG_SYSCTL_SYSCALL is not set
 CONFIG_KALLSYMS=y
 # CONFIG_KALLSYMS_EXTRA_PASS is not set
-# CONFIG_HOTPLUG is not set
+# CONFIG_STRIP_ASM_SYMS is not set
+CONFIG_HOTPLUG=y
 CONFIG_PRINTK=y
 CONFIG_BUG=y
 # CONFIG_ELF_CORE is not set
 CONFIG_BASE_FULL=y
 # CONFIG_FUTEX is not set
-CONFIG_ANON_INODES=y
 CONFIG_EPOLL=y
 CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
 CONFIG_EVENTFD=y
+CONFIG_AIO=y
 CONFIG_VM_EVENT_COUNTERS=y
-CONFIG_BIG_ORDER_ALLOC_NOFAIL_MAGIC=3
-# CONFIG_NP2 is not set
+CONFIG_COMPAT_BRK=y
 CONFIG_SLAB=y
 # CONFIG_SLUB is not set
 # CONFIG_SLOB is not set
-CONFIG_RT_MUTEXES=y
-CONFIG_TINY_SHMEM=y
+CONFIG_MMAP_ALLOW_UNINITIALIZED=y
+# CONFIG_PROFILING is not set
+# CONFIG_MARKERS is not set
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_SLOW_WORK is not set
+# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
+CONFIG_SLABINFO=y
 CONFIG_BASE_SMALL=0
-
-#
-# Loadable module support
-#
 CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_MODULE_FORCE_UNLOAD is not set
+# CONFIG_MODULE_FORCE_LOAD is not set
+# CONFIG_MODULE_UNLOAD is not set
 # CONFIG_MODVERSIONS is not set
 # CONFIG_MODULE_SRCVERSION_ALL is not set
-CONFIG_KMOD=y
-
-#
-# Block layer
-#
 CONFIG_BLOCK=y
 # CONFIG_LBD is not set
-# CONFIG_BLK_DEV_IO_TRACE is not set
-# CONFIG_LSF is not set
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_BLK_DEV_INTEGRITY is not set
 
 #
 # IO Schedulers
@@ -96,7 +112,7 @@ CONFIG_BLOCK=y
 CONFIG_IOSCHED_NOOP=y
 # CONFIG_IOSCHED_AS is not set
 # CONFIG_IOSCHED_DEADLINE is not set
-CONFIG_IOSCHED_CFQ=y
+# CONFIG_IOSCHED_CFQ is not set
 # CONFIG_DEFAULT_AS is not set
 # CONFIG_DEFAULT_DEADLINE is not set
 # CONFIG_DEFAULT_CFQ is not set
@@ -105,6 +121,7 @@ CONFIG_DEFAULT_IOSCHED="noop"
 CONFIG_PREEMPT_NONE=y
 # CONFIG_PREEMPT_VOLUNTARY is not set
 # CONFIG_PREEMPT is not set
+# CONFIG_FREEZER is not set
 
 #
 # Blackfin Processor Options
@@ -113,6 +130,10 @@ CONFIG_PREEMPT_NONE=y
 #
 # Processor and Board Settings
 #
+# CONFIG_BF512 is not set
+# CONFIG_BF514 is not set
+# CONFIG_BF516 is not set
+# CONFIG_BF518 is not set
 # CONFIG_BF522 is not set
 # CONFIG_BF523 is not set
 # CONFIG_BF524 is not set
@@ -125,28 +146,38 @@ CONFIG_BF533=y
 # CONFIG_BF534 is not set
 # CONFIG_BF536 is not set
 # CONFIG_BF537 is not set
+# CONFIG_BF538 is not set
+# CONFIG_BF539 is not set
 # CONFIG_BF542 is not set
+# CONFIG_BF542M is not set
 # CONFIG_BF544 is not set
+# CONFIG_BF544M is not set
 # CONFIG_BF547 is not set
+# CONFIG_BF547M is not set
 # CONFIG_BF548 is not set
+# CONFIG_BF548M is not set
 # CONFIG_BF549 is not set
+# CONFIG_BF549M is not set
 # CONFIG_BF561 is not set
+CONFIG_BF_REV_MIN=3
+CONFIG_BF_REV_MAX=6
 # CONFIG_BF_REV_0_0 is not set
 # CONFIG_BF_REV_0_1 is not set
 # CONFIG_BF_REV_0_2 is not set
 CONFIG_BF_REV_0_3=y
 # CONFIG_BF_REV_0_4 is not set
 # CONFIG_BF_REV_0_5 is not set
+# CONFIG_BF_REV_0_6 is not set
 # CONFIG_BF_REV_ANY is not set
 # CONFIG_BF_REV_NONE is not set
 CONFIG_BF53x=y
-CONFIG_BFIN_SINGLE_CORE=y
 CONFIG_MEM_MT48LC16M16A2TG_75=y
 # CONFIG_BFIN533_EZKIT is not set
 # CONFIG_BFIN533_STAMP is not set
+# CONFIG_BLACKSTAMP is not set
 CONFIG_BFIN533_BLUETECHNIX_CM=y
 # CONFIG_H8606_HVSISTEMAS is not set
-# CONFIG_GENERIC_BF533_BOARD is not set
+# CONFIG_BFIN532_IP0X is not set
 
 #
 # BF533/2/1 Specific Configuration
@@ -188,6 +219,7 @@ CONFIG_WDTIMER=13
 # Board customizations
 #
 # CONFIG_CMDLINE_BOOL is not set
+CONFIG_BOOT_LOAD=0x1000
 
 #
 # Clock/PLL Setup
@@ -207,13 +239,20 @@ CONFIG_HZ_250=y
 # CONFIG_HZ_300 is not set
 # CONFIG_HZ_1000 is not set
 CONFIG_HZ=250
+# CONFIG_SCHED_HRTICK is not set
+CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+# CONFIG_TICKSOURCE_GPTMR0 is not set
+CONFIG_TICKSOURCE_CORETMR=y
+# CONFIG_CYCLES_CLOCKSOURCE is not set
+# CONFIG_GPTMR0_CLOCKSOURCE is not set
+# CONFIG_NO_HZ is not set
+# CONFIG_HIGH_RES_TIMERS is not set
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
 
 #
-# Memory Setup
+# Misc
 #
-CONFIG_MAX_MEM_SIZE=32
-CONFIG_MEM_ADD_WIDTH=9
-CONFIG_BOOT_LOAD=0x1000
 CONFIG_BFIN_SCRATCH_REG_RETN=y
 # CONFIG_BFIN_SCRATCH_REG_RETE is not set
 # CONFIG_BFIN_SCRATCH_REG_CYCLES is not set
@@ -240,6 +279,12 @@ CONFIG_IP_CHECKSUM_L1=y
 CONFIG_CACHELINE_ALIGNED_L1=y
 CONFIG_SYSCALL_TAB_L1=y
 CONFIG_CPLB_SWITCH_TAB_L1=y
+CONFIG_APP_STACK_L1=y
+
+#
+# Speed Optimizations
+#
+CONFIG_BFIN_INS_LOWOVERHEAD=y
 CONFIG_RAMKERNEL=y
 # CONFIG_ROMKERNEL is not set
 CONFIG_SELECT_MEMORY_MODEL=y
@@ -248,12 +293,16 @@ CONFIG_FLATMEM_MANUAL=y
 # CONFIG_SPARSEMEM_MANUAL is not set
 CONFIG_FLATMEM=y
 CONFIG_FLAT_NODE_MEM_MAP=y
-# CONFIG_SPARSEMEM_STATIC is not set
+CONFIG_PAGEFLAGS_EXTENDED=y
 CONFIG_SPLIT_PTLOCK_CPUS=4
-# CONFIG_RESOURCES_64BIT is not set
+# CONFIG_PHYS_ADDR_T_64BIT is not set
 CONFIG_ZONE_DMA_FLAG=1
-CONFIG_LARGE_ALLOCS=y
+CONFIG_VIRT_TO_BUS=y
+CONFIG_UNEVICTABLE_LRU=y
+CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
+CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0
 # CONFIG_BFIN_GPTIMERS is not set
+# CONFIG_DMA_UNCACHED_4M is not set
 # CONFIG_DMA_UNCACHED_2M is not set
 CONFIG_DMA_UNCACHED_1M=y
 # CONFIG_DMA_UNCACHED_NONE is not set
@@ -262,10 +311,9 @@ CONFIG_DMA_UNCACHED_1M=y
 # Cache Support
 #
 CONFIG_BFIN_ICACHE=y
-# CONFIG_BFIN_ICACHE_LOCK is not set
+CONFIG_BFIN_EXTMEM_ICACHEABLE=y
 CONFIG_BFIN_DCACHE=y
 # CONFIG_BFIN_DCACHE_BANKA is not set
-CONFIG_BFIN_EXTMEM_ICACHEABLE=y
 CONFIG_BFIN_EXTMEM_DCACHEABLE=y
 CONFIG_BFIN_EXTMEM_WRITEBACK=y
 # CONFIG_BFIN_EXTMEM_WRITETHROUGH is not set
@@ -276,7 +324,7 @@ CONFIG_BFIN_EXTMEM_WRITEBACK=y
 # CONFIG_MPU is not set
 
 #
-# Asynchonous Memory Configuration
+# Asynchronous Memory Configuration
 #
 
 #
@@ -301,12 +349,8 @@ CONFIG_BANK_3=0xFFC2
 #
 # Bus options (PCI, PCMCIA, EISA, MCA, ISA)
 #
-# CONFIG_PCI is not set
 # CONFIG_ARCH_SUPPORTS_MSI is not set
-
-#
-# PCCARD (PCMCIA/CardBus) support
-#
+# CONFIG_PCCARD is not set
 
 #
 # Executable file formats
@@ -315,22 +359,19 @@ CONFIG_BINFMT_ELF_FDPIC=y
 CONFIG_BINFMT_FLAT=y
 CONFIG_BINFMT_ZFLAT=y
 CONFIG_BINFMT_SHARED_FLAT=y
+# CONFIG_HAVE_AOUT is not set
 # CONFIG_BINFMT_MISC is not set
 
 #
 # Power management options
 #
 # CONFIG_PM is not set
-# CONFIG_PM_WAKEUP_BY_GPIO is not set
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
 
 #
 # CPU Frequency scaling
 #
 # CONFIG_CPU_FREQ is not set
-
-#
-# Networking
-#
 CONFIG_NET=y
 
 #
@@ -339,45 +380,13 @@ CONFIG_NET=y
 CONFIG_PACKET=y
 # CONFIG_PACKET_MMAP is not set
 CONFIG_UNIX=y
-CONFIG_XFRM=y
-# CONFIG_XFRM_USER is not set
-# CONFIG_XFRM_SUB_POLICY is not set
-# CONFIG_XFRM_MIGRATE is not set
 # CONFIG_NET_KEY is not set
-CONFIG_INET=y
-# CONFIG_IP_MULTICAST is not set
-# CONFIG_IP_ADVANCED_ROUTER is not set
-CONFIG_IP_FIB_HASH=y
-# CONFIG_IP_PNP is not set
-# CONFIG_NET_IPIP is not set
-# CONFIG_NET_IPGRE is not set
-# CONFIG_ARPD is not set
-# CONFIG_SYN_COOKIES is not set
-# CONFIG_INET_AH is not set
-# CONFIG_INET_ESP is not set
-# CONFIG_INET_IPCOMP is not set
-# CONFIG_INET_XFRM_TUNNEL is not set
-# CONFIG_INET_TUNNEL is not set
-# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
-# CONFIG_INET_XFRM_MODE_TUNNEL is not set
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_DIAG is not set
-CONFIG_INET_TCP_DIAG=y
-# CONFIG_TCP_CONG_ADVANCED is not set
-CONFIG_TCP_CONG_CUBIC=y
-CONFIG_DEFAULT_TCP_CONG="cubic"
-# CONFIG_TCP_MD5SIG is not set
-# CONFIG_IPV6 is not set
-# CONFIG_INET6_XFRM_TUNNEL is not set
-# CONFIG_INET6_TUNNEL is not set
-# CONFIG_NETLABEL is not set
+# CONFIG_INET is not set
 # CONFIG_NETWORK_SECMARK is not set
 # CONFIG_NETFILTER is not set
-# CONFIG_IP_DCCP is not set
-# CONFIG_IP_SCTP is not set
-# CONFIG_TIPC is not set
 # CONFIG_ATM is not set
 # CONFIG_BRIDGE is not set
+# CONFIG_NET_DSA is not set
 # CONFIG_VLAN_8021Q is not set
 # CONFIG_DECNET is not set
 # CONFIG_LLC2 is not set
@@ -385,31 +394,23 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
 # CONFIG_ATALK is not set
 # CONFIG_X25 is not set
 # CONFIG_LAPB is not set
-# CONFIG_ECONET is not set
 # CONFIG_WAN_ROUTER is not set
-
-#
-# QoS and/or fair queueing
-#
+# CONFIG_PHONET is not set
 # CONFIG_NET_SCHED is not set
+# CONFIG_DCB is not set
 
 #
 # Network testing
 #
 # CONFIG_NET_PKTGEN is not set
 # CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
 # CONFIG_IRDA is not set
 # CONFIG_BT is not set
-# CONFIG_AF_RXRPC is not set
-
-#
-# Wireless
-#
-# CONFIG_CFG80211 is not set
-# CONFIG_WIRELESS_EXT is not set
-# CONFIG_MAC80211 is not set
-# CONFIG_IEEE80211 is not set
+# CONFIG_WIRELESS is not set
+# CONFIG_WIMAX is not set
 # CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
 
 #
 # Device Drivers
@@ -418,20 +419,22 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
 #
 # Generic Driver Options
 #
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 CONFIG_STANDALONE=y
 CONFIG_PREVENT_FIRMWARE_BUILD=y
+CONFIG_FW_LOADER=y
+CONFIG_FIRMWARE_IN_KERNEL=y
+CONFIG_EXTRA_FIRMWARE=""
 # CONFIG_SYS_HYPERVISOR is not set
-
-#
-# Connector - unified userspace <-> kernelspace linker
-#
 # CONFIG_CONNECTOR is not set
 CONFIG_MTD=y
 # CONFIG_MTD_DEBUG is not set
+# CONFIG_MTD_TESTS is not set
 # CONFIG_MTD_CONCAT is not set
 CONFIG_MTD_PARTITIONS=y
 # CONFIG_MTD_REDBOOT_PARTS is not set
-# CONFIG_MTD_CMDLINE_PARTS is not set
+CONFIG_MTD_CMDLINE_PARTS=y
+# CONFIG_MTD_AR7_PARTS is not set
 
 #
 # User Modules And Translation Layers
@@ -444,12 +447,15 @@ CONFIG_MTD_BLOCK=y
 # CONFIG_INFTL is not set
 # CONFIG_RFD_FTL is not set
 # CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
 
 #
 # RAM/ROM/Flash chip drivers
 #
-# CONFIG_MTD_CFI is not set
+CONFIG_MTD_CFI=y
 # CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_GEN_PROBE=y
+# CONFIG_MTD_CFI_ADV_OPTIONS is not set
 CONFIG_MTD_MAP_BANK_WIDTH_1=y
 CONFIG_MTD_MAP_BANK_WIDTH_2=y
 CONFIG_MTD_MAP_BANK_WIDTH_4=y
@@ -460,6 +466,11 @@ CONFIG_MTD_CFI_I1=y
 CONFIG_MTD_CFI_I2=y
 # CONFIG_MTD_CFI_I4 is not set
 # CONFIG_MTD_CFI_I8 is not set
+CONFIG_MTD_CFI_INTELEXT=y
+# CONFIG_MTD_CFI_AMDSTD is not set
+# CONFIG_MTD_CFI_STAA is not set
+# CONFIG_MTD_PSD4256G is not set
+CONFIG_MTD_CFI_UTIL=y
 CONFIG_MTD_RAM=y
 # CONFIG_MTD_ROM is not set
 # CONFIG_MTD_ABSENT is not set
@@ -468,12 +479,16 @@ CONFIG_MTD_RAM=y
 # Mapping drivers for chip access
 #
 # CONFIG_MTD_COMPLEX_MAPPINGS is not set
-CONFIG_MTD_UCLINUX=y
+CONFIG_MTD_PHYSMAP=y
+# CONFIG_MTD_PHYSMAP_COMPAT is not set
+# CONFIG_MTD_UCLINUX is not set
 # CONFIG_MTD_PLATRAM is not set
 
 #
 # Self-contained MTD device drivers
 #
+# CONFIG_MTD_DATAFLASH is not set
+# CONFIG_MTD_M25P80 is not set
 # CONFIG_MTD_SLRAM is not set
 # CONFIG_MTD_PHRAM is not set
 # CONFIG_MTD_MTDRAM is not set
@@ -489,36 +504,25 @@ CONFIG_MTD_UCLINUX=y
 # CONFIG_MTD_ONENAND is not set
 
 #
-# UBI - Unsorted block images
+# LPDDR flash memory drivers
 #
-# CONFIG_MTD_UBI is not set
+# CONFIG_MTD_LPDDR is not set
 
 #
-# Parallel port support
+# UBI - Unsorted block images
 #
+# CONFIG_MTD_UBI is not set
 # CONFIG_PARPORT is not set
-
-#
-# Plug and Play support
-#
-# CONFIG_PNPACPI is not set
-
-#
-# Block devices
-#
+CONFIG_BLK_DEV=y
 # CONFIG_BLK_DEV_COW_COMMON is not set
 # CONFIG_BLK_DEV_LOOP is not set
 # CONFIG_BLK_DEV_NBD is not set
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_COUNT=16
-CONFIG_BLK_DEV_RAM_SIZE=4096
-CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
+# CONFIG_BLK_DEV_RAM is not set
 # CONFIG_CDROM_PKTCDVD is not set
 # CONFIG_ATA_OVER_ETH is not set
-
-#
-# Misc devices
-#
+# CONFIG_BLK_DEV_HD is not set
+# CONFIG_MISC_DEVICES is not set
+CONFIG_HAVE_IDE=y
 # CONFIG_IDE is not set
 
 #
@@ -526,34 +530,19 @@ CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
 #
 # CONFIG_RAID_ATTRS is not set
 # CONFIG_SCSI is not set
+# CONFIG_SCSI_DMA is not set
 # CONFIG_SCSI_NETLINK is not set
 # CONFIG_ATA is not set
-
-#
-# Multi-device support (RAID and LVM)
-#
 # CONFIG_MD is not set
-
-#
-# Network device support
-#
 CONFIG_NETDEVICES=y
+CONFIG_COMPAT_NET_DEV_OPS=y
 # CONFIG_DUMMY is not set
-# CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
 # CONFIG_EQUALIZER is not set
 # CONFIG_TUN is not set
-# CONFIG_PHYLIB is not set
-
-#
-# Ethernet (10 or 100Mbit)
-#
-CONFIG_NET_ETHERNET=y
-CONFIG_MII=y
-CONFIG_SMC91X=y
-# CONFIG_SMSC911X is not set
-# CONFIG_DM9000 is not set
+# CONFIG_VETH is not set
+# CONFIG_NET_ETHERNET is not set
 # CONFIG_NETDEV_1000 is not set
-# CONFIG_AX88180 is not set
 # CONFIG_NETDEV_10000 is not set
 
 #
@@ -561,22 +550,17 @@ CONFIG_SMC91X=y
 #
 # CONFIG_WLAN_PRE80211 is not set
 # CONFIG_WLAN_80211 is not set
+
+#
+# Enable WiMAX (Networking options) to see the WiMAX drivers
+#
 # CONFIG_WAN is not set
 # CONFIG_PPP is not set
 # CONFIG_SLIP is not set
-# CONFIG_SHAPER is not set
 # CONFIG_NETCONSOLE is not set
 # CONFIG_NETPOLL is not set
 # CONFIG_NET_POLL_CONTROLLER is not set
-
-#
-# ISDN subsystem
-#
 # CONFIG_ISDN is not set
-
-#
-# Telephony Support
-#
 # CONFIG_PHONE is not set
 
 #
@@ -593,16 +577,15 @@ CONFIG_SMC91X=y
 #
 # Character devices
 #
-# CONFIG_AD9960 is not set
-# CONFIG_SPI_ADC_BF533 is not set
-# CONFIG_BF5xx_PFLAGS is not set
-# CONFIG_BF5xx_PPIFCD is not set
+# CONFIG_BFIN_DMA_INTERFACE is not set
+# CONFIG_BFIN_PPI is not set
+# CONFIG_BFIN_PPIFCD is not set
 # CONFIG_BFIN_SIMPLE_TIMER is not set
-# CONFIG_BF5xx_PPI is not set
-CONFIG_BFIN_SPORT=y
-# CONFIG_BFIN_TIMER_LATENCY is not set
+# CONFIG_BFIN_SPI_ADC is not set
+# CONFIG_BFIN_SPORT is not set
 # CONFIG_VT is not set
 # CONFIG_DEVKMEM is not set
+# CONFIG_BFIN_JTAG_COMM is not set
 # CONFIG_SERIAL_NONSTANDARD is not set
 
 #
@@ -613,6 +596,7 @@ CONFIG_BFIN_SPORT=y
 #
 # Non-8250 serial port support
 #
+# CONFIG_SERIAL_MAX3100 is not set
 CONFIG_SERIAL_BFIN=y
 CONFIG_SERIAL_BFIN_CONSOLE=y
 CONFIG_SERIAL_BFIN_DMA=y
@@ -623,176 +607,141 @@ CONFIG_SERIAL_CORE=y
 CONFIG_SERIAL_CORE_CONSOLE=y
 # CONFIG_SERIAL_BFIN_SPORT is not set
 CONFIG_UNIX98_PTYS=y
+# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
 # CONFIG_LEGACY_PTYS is not set
 
 #
 # CAN, the car bus and industrial fieldbus
 #
 # CONFIG_CAN4LINUX is not set
-
-#
-# IPMI
-#
 # CONFIG_IPMI_HANDLER is not set
-# CONFIG_WATCHDOG is not set
 # CONFIG_HW_RANDOM is not set
-# CONFIG_GEN_RTC is not set
 # CONFIG_R3964 is not set
 # CONFIG_RAW_DRIVER is not set
-
-#
-# TPM devices
-#
 # CONFIG_TCG_TPM is not set
 # CONFIG_I2C is not set
-
-CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
-CONFIG_GPIOLIB=y
-CONFIG_GPIO_SYSFS=y
+CONFIG_SPI=y
+CONFIG_SPI_MASTER=y
 
 #
-# SPI support
+# SPI Master Controller Drivers
 #
-# CONFIG_SPI is not set
-# CONFIG_SPI_MASTER is not set
+CONFIG_SPI_BFIN=y
+# CONFIG_SPI_BFIN_LOCK is not set
+# CONFIG_SPI_BFIN_SPORT is not set
+# CONFIG_SPI_BITBANG is not set
+# CONFIG_SPI_GPIO is not set
 
 #
-# Dallas's 1-wire bus
+# SPI Protocol Masters
 #
+# CONFIG_SPI_SPIDEV is not set
+# CONFIG_SPI_TLE62X0 is not set
+CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
+# CONFIG_GPIOLIB is not set
 # CONFIG_W1 is not set
-CONFIG_HWMON=y
-# CONFIG_HWMON_VID is not set
-# CONFIG_SENSORS_ABITUGURU is not set
-# CONFIG_SENSORS_F71805F is not set
-# CONFIG_SENSORS_PC87427 is not set
-# CONFIG_SENSORS_SMSC47M1 is not set
-# CONFIG_SENSORS_SMSC47B397 is not set
-# CONFIG_SENSORS_VT1211 is not set
-# CONFIG_SENSORS_W83627HF is not set
-# CONFIG_HWMON_DEBUG_CHIP is not set
+# CONFIG_POWER_SUPPLY is not set
+# CONFIG_HWMON is not set
+# CONFIG_THERMAL is not set
+# CONFIG_THERMAL_HWMON is not set
+# CONFIG_WATCHDOG is not set
+CONFIG_SSB_POSSIBLE=y
+
+#
+# Sonics Silicon Backplane
+#
+# CONFIG_SSB is not set
 
 #
 # Multifunction device drivers
 #
+# CONFIG_MFD_CORE is not set
 # CONFIG_MFD_SM501 is not set
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_MFD_TMIO is not set
+# CONFIG_REGULATOR is not set
 
 #
 # Multimedia devices
 #
+
+#
+# Multimedia core support
+#
 # CONFIG_VIDEO_DEV is not set
-# CONFIG_DVB_CORE is not set
-# CONFIG_DAB is not set
+# CONFIG_VIDEO_MEDIA is not set
 
 #
-# Graphics support
+# Multimedia drivers
 #
-# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+# CONFIG_DAB is not set
 
 #
-# Display device support
+# Graphics support
 #
-# CONFIG_DISPLAY_SUPPORT is not set
 # CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
 # CONFIG_FB is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
 
 #
-# Sound
+# Display device support
 #
+# CONFIG_DISPLAY_SUPPORT is not set
 # CONFIG_SOUND is not set
+# CONFIG_USB_SUPPORT is not set
+CONFIG_MMC=y
+# CONFIG_MMC_DEBUG is not set
+# CONFIG_MMC_UNSAFE_RESUME is not set
 
 #
-# USB support
+# MMC/SD/SDIO Card Drivers
 #
-CONFIG_USB_ARCH_HAS_HCD=y
-# CONFIG_USB_ARCH_HAS_OHCI is not set
-# CONFIG_USB_ARCH_HAS_EHCI is not set
-# CONFIG_USB is not set
+CONFIG_MMC_BLOCK=y
+# CONFIG_MMC_BLOCK_BOUNCE is not set
+# CONFIG_SDIO_UART is not set
+# CONFIG_MMC_TEST is not set
 
 #
-# Enable Host or Gadget support to see Inventra options
-#
-
-#
-# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
-#
-
-#
-# USB Gadget Support
-#
-# CONFIG_USB_GADGET is not set
-# CONFIG_MMC is not set
-
-#
-# LED devices
+# MMC/SD/SDIO Host Controller Drivers
 #
+# CONFIG_MMC_SDHCI is not set
+CONFIG_MMC_SPI=m
+# CONFIG_MEMSTICK is not set
 # CONFIG_NEW_LEDS is not set
-
-#
-# LED drivers
-#
-
-#
-# LED Triggers
-#
-
-#
-# InfiniBand support
-#
-
-#
-# EDAC - error detection and reporting (RAS) (EXPERIMENTAL)
-#
-
-#
-# Real Time Clock
-#
+# CONFIG_ACCESSIBILITY is not set
 # CONFIG_RTC_CLASS is not set
-
-#
-# DMA Engine support
-#
-# CONFIG_DMA_ENGINE is not set
-
-#
-# DMA Clients
-#
-
-#
-# DMA Devices
-#
-
-#
-# PBX support
-#
-# CONFIG_PBX is not set
+# CONFIG_DMADEVICES is not set
+# CONFIG_AUXDISPLAY is not set
+# CONFIG_UIO is not set
+# CONFIG_STAGING is not set
 
 #
 # File systems
 #
-CONFIG_EXT2_FS=y
-CONFIG_EXT2_FS_XATTR=y
-# CONFIG_EXT2_FS_POSIX_ACL is not set
-# CONFIG_EXT2_FS_SECURITY is not set
+# CONFIG_EXT2_FS is not set
 # CONFIG_EXT3_FS is not set
-# CONFIG_EXT4DEV_FS is not set
-CONFIG_FS_MBCACHE=y
+# CONFIG_EXT4_FS is not set
 # CONFIG_REISERFS_FS is not set
 # CONFIG_JFS_FS is not set
 # CONFIG_FS_POSIX_ACL is not set
 # CONFIG_XFS_FS is not set
-# CONFIG_GFS2_FS is not set
 # CONFIG_OCFS2_FS is not set
-# CONFIG_MINIX_FS is not set
-# CONFIG_ROMFS_FS is not set
-CONFIG_INOTIFY=y
-CONFIG_INOTIFY_USER=y
-# CONFIG_QUOTA is not set
+# CONFIG_BTRFS_FS is not set
+CONFIG_FILE_LOCKING=y
 # CONFIG_DNOTIFY is not set
+# CONFIG_INOTIFY is not set
+# CONFIG_QUOTA is not set
 # CONFIG_AUTOFS_FS is not set
 # CONFIG_AUTOFS4_FS is not set
 # CONFIG_FUSE_FS is not set
 
 #
+# Caches
+#
+# CONFIG_FSCACHE is not set
+
+#
 # CD-ROM/DVD Filesystems
 #
 # CONFIG_ISO9660_FS is not set
@@ -801,8 +750,11 @@ CONFIG_INOTIFY_USER=y
 #
 # DOS/FAT/NT Filesystems
 #
+CONFIG_FAT_FS=y
 # CONFIG_MSDOS_FS is not set
-# CONFIG_VFAT_FS is not set
+CONFIG_VFAT_FS=y
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
 # CONFIG_NTFS_FS is not set
 
 #
@@ -813,12 +765,8 @@ CONFIG_PROC_SYSCTL=y
 CONFIG_SYSFS=y
 # CONFIG_TMPFS is not set
 # CONFIG_HUGETLB_PAGE is not set
-CONFIG_RAMFS=y
 # CONFIG_CONFIGFS_FS is not set
-
-#
-# Miscellaneous filesystems
-#
+CONFIG_MISC_FILESYSTEMS=y
 # CONFIG_ADFS_FS is not set
 # CONFIG_AFFS_FS is not set
 # CONFIG_HFS_FS is not set
@@ -826,60 +774,106 @@ CONFIG_RAMFS=y
 # CONFIG_BEFS_FS is not set
 # CONFIG_BFS_FS is not set
 # CONFIG_EFS_FS is not set
-# CONFIG_YAFFS_FS is not set
 # CONFIG_JFFS2_FS is not set
 # CONFIG_CRAMFS is not set
+# CONFIG_SQUASHFS is not set
 # CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_OMFS_FS is not set
 # CONFIG_HPFS_FS is not set
 # CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
 # CONFIG_SYSV_FS is not set
 # CONFIG_UFS_FS is not set
-
-#
-# Network File Systems
-#
-# CONFIG_NFS_FS is not set
-# CONFIG_NFSD is not set
-# CONFIG_SMB_FS is not set
-# CONFIG_CIFS is not set
-# CONFIG_NCP_FS is not set
-# CONFIG_CODA_FS is not set
-# CONFIG_AFS_FS is not set
-# CONFIG_9P_FS is not set
+# CONFIG_NILFS2_FS is not set
+# CONFIG_NETWORK_FILESYSTEMS is not set
 
 #
 # Partition Types
 #
 # CONFIG_PARTITION_ADVANCED is not set
 CONFIG_MSDOS_PARTITION=y
-
-#
-# Native Language Support
-#
-# CONFIG_NLS is not set
-
-#
-# Distributed Lock Manager
-#
-# CONFIG_DLM is not set
-
-#
-# Profiling support
-#
-# CONFIG_PROFILING is not set
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="iso8859-1"
+CONFIG_NLS_CODEPAGE_437=y
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+# CONFIG_NLS_ASCII is not set
+CONFIG_NLS_ISO8859_1=y
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+# CONFIG_NLS_UTF8 is not set
 
 #
 # Kernel hacking
 #
 # CONFIG_PRINTK_TIME is not set
+CONFIG_ENABLE_WARN_DEPRECATED=y
 CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_FRAME_WARN=1024
 # CONFIG_MAGIC_SYSRQ is not set
 # CONFIG_UNUSED_SYMBOLS is not set
 CONFIG_DEBUG_FS=y
 # CONFIG_HEADERS_CHECK is not set
+CONFIG_DEBUG_SECTION_MISMATCH=y
 # CONFIG_DEBUG_KERNEL is not set
-CONFIG_DEBUG_BUGVERBOSE=y
+# CONFIG_DEBUG_BUGVERBOSE is not set
+# CONFIG_DEBUG_MEMORY_INIT is not set
+# CONFIG_RCU_CPU_STALL_DETECTOR is not set
+CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
+CONFIG_TRACING_SUPPORT=y
+
+#
+# Tracers
+#
+# CONFIG_FUNCTION_TRACER is not set
+# CONFIG_IRQSOFF_TRACER is not set
+# CONFIG_SCHED_TRACER is not set
+# CONFIG_CONTEXT_SWITCH_TRACER is not set
+# CONFIG_EVENT_TRACER is not set
+# CONFIG_BOOT_TRACER is not set
+# CONFIG_TRACE_BRANCH_PROFILING is not set
+# CONFIG_STACK_TRACER is not set
+# CONFIG_KMEMTRACE is not set
+# CONFIG_WORKQUEUE_TRACER is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_DYNAMIC_DEBUG is not set
+# CONFIG_SAMPLES is not set
+CONFIG_HAVE_ARCH_KGDB=y
+CONFIG_DEBUG_VERBOSE=y
 CONFIG_DEBUG_MMRS=y
+# CONFIG_DEBUG_DOUBLEFAULT is not set
 CONFIG_DEBUG_HUNT_FOR_ZERO=y
 CONFIG_DEBUG_BFIN_HWTRACE_ON=y
 CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_OFF=y
@@ -888,34 +882,39 @@ CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_OFF=y
 CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION=0
 # CONFIG_DEBUG_BFIN_HWTRACE_EXPAND is not set
 # CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE is not set
-# CONFIG_EARLY_PRINTK is not set
+CONFIG_EARLY_PRINTK=y
 CONFIG_CPLB_INFO=y
 CONFIG_ACCESS_CHECK=y
+# CONFIG_BFIN_ISRAM_SELF_TEST is not set
 
 #
 # Security options
 #
 # CONFIG_KEYS is not set
 CONFIG_SECURITY=y
+# CONFIG_SECURITYFS is not set
 # CONFIG_SECURITY_NETWORK is not set
-CONFIG_SECURITY_CAPABILITIES=y
-
-#
-# Cryptographic options
-#
+# CONFIG_SECURITY_PATH is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+# CONFIG_SECURITY_TOMOYO is not set
 # CONFIG_CRYPTO is not set
+# CONFIG_BINARY_PRINTF is not set
 
 #
 # Library routines
 #
 CONFIG_BITREVERSE=y
-CONFIG_CRC_CCITT=m
+CONFIG_GENERIC_FIND_LAST_BIT=y
+CONFIG_CRC_CCITT=y
 # CONFIG_CRC16 is not set
-# CONFIG_CRC_ITU_T is not set
+# CONFIG_CRC_T10DIF is not set
+CONFIG_CRC_ITU_T=y
 CONFIG_CRC32=y
+CONFIG_CRC7=y
 # CONFIG_LIBCRC32C is not set
 CONFIG_ZLIB_INFLATE=y
-CONFIG_PLIST=y
+CONFIG_DECOMPRESS_LZMA=y
 CONFIG_HAS_IOMEM=y
 CONFIG_HAS_IOPORT=y
 CONFIG_HAS_DMA=y
+CONFIG_NLATTR=y
diff --git a/arch/blackfin/configs/CM-BF537E_defconfig b/arch/blackfin/configs/CM-BF537E_defconfig
index d74b6f4db35d..22e565c51d66 100644
--- a/arch/blackfin/configs/CM-BF537E_defconfig
+++ b/arch/blackfin/configs/CM-BF537E_defconfig
@@ -1,13 +1,13 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.28.10
-# Wed Jun  3 06:27:41 2009
+# Linux kernel version: 2.6.30.5
 #
 # CONFIG_MMU is not set
 # CONFIG_FPU is not set
 CONFIG_RWSEM_GENERIC_SPINLOCK=y
 # CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
 CONFIG_BLACKFIN=y
+CONFIG_GENERIC_BUG=y
 CONFIG_ZONE_DMA=y
 CONFIG_GENERIC_FIND_NEXT_BIT=y
 CONFIG_GENERIC_HWEIGHT=y
@@ -16,6 +16,9 @@ CONFIG_GENERIC_IRQ_PROBE=y
 CONFIG_GENERIC_GPIO=y
 CONFIG_FORCE_MAX_ZONEORDER=14
 CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
 CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
 
 #
@@ -26,21 +29,40 @@ CONFIG_BROKEN_ON_SMP=y
 CONFIG_INIT_ENV_ARG_LIMIT=32
 CONFIG_LOCALVERSION=""
 CONFIG_LOCALVERSION_AUTO=y
+CONFIG_HAVE_KERNEL_GZIP=y
+CONFIG_HAVE_KERNEL_BZIP2=y
+CONFIG_HAVE_KERNEL_LZMA=y
+# CONFIG_KERNEL_GZIP is not set
+# CONFIG_KERNEL_BZIP2 is not set
+CONFIG_KERNEL_LZMA=y
 CONFIG_SYSVIPC=y
 CONFIG_SYSVIPC_SYSCTL=y
 # CONFIG_POSIX_MQUEUE is not set
 # CONFIG_BSD_PROCESS_ACCT is not set
 # CONFIG_TASKSTATS is not set
 # CONFIG_AUDIT is not set
+
+#
+# RCU Subsystem
+#
+CONFIG_CLASSIC_RCU=y
+# CONFIG_TREE_RCU is not set
+# CONFIG_PREEMPT_RCU is not set
+# CONFIG_TREE_RCU_TRACE is not set
+# CONFIG_PREEMPT_RCU_TRACE is not set
 CONFIG_IKCONFIG=y
 CONFIG_IKCONFIG_PROC=y
 CONFIG_LOG_BUF_SHIFT=14
-# CONFIG_CGROUPS is not set
 # CONFIG_GROUP_SCHED is not set
+# CONFIG_CGROUPS is not set
 # CONFIG_SYSFS_DEPRECATED_V2 is not set
 # CONFIG_RELAY is not set
 # CONFIG_NAMESPACES is not set
-# CONFIG_BLK_DEV_INITRD is not set
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+# CONFIG_RD_GZIP is not set
+# CONFIG_RD_BZIP2 is not set
+CONFIG_RD_LZMA=y
 # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
 CONFIG_SYSCTL=y
 CONFIG_ANON_INODES=y
@@ -49,7 +71,8 @@ CONFIG_EMBEDDED=y
 # CONFIG_SYSCTL_SYSCALL is not set
 CONFIG_KALLSYMS=y
 # CONFIG_KALLSYMS_EXTRA_PASS is not set
-# CONFIG_HOTPLUG is not set
+# CONFIG_STRIP_ASM_SYMS is not set
+CONFIG_HOTPLUG=y
 CONFIG_PRINTK=y
 CONFIG_BUG=y
 # CONFIG_ELF_CORE is not set
@@ -65,12 +88,13 @@ CONFIG_COMPAT_BRK=y
 CONFIG_SLAB=y
 # CONFIG_SLUB is not set
 # CONFIG_SLOB is not set
+CONFIG_MMAP_ALLOW_UNINITIALIZED=y
 # CONFIG_PROFILING is not set
 # CONFIG_MARKERS is not set
 CONFIG_HAVE_OPROFILE=y
+# CONFIG_SLOW_WORK is not set
 # CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
 CONFIG_SLABINFO=y
-CONFIG_TINY_SHMEM=y
 CONFIG_BASE_SMALL=0
 CONFIG_MODULES=y
 # CONFIG_MODULE_FORCE_LOAD is not set
@@ -78,11 +102,8 @@ CONFIG_MODULE_UNLOAD=y
 # CONFIG_MODULE_FORCE_UNLOAD is not set
 # CONFIG_MODVERSIONS is not set
 # CONFIG_MODULE_SRCVERSION_ALL is not set
-CONFIG_KMOD=y
 CONFIG_BLOCK=y
 # CONFIG_LBD is not set
-# CONFIG_BLK_DEV_IO_TRACE is not set
-# CONFIG_LSF is not set
 # CONFIG_BLK_DEV_BSG is not set
 # CONFIG_BLK_DEV_INTEGRITY is not set
 
@@ -98,7 +119,6 @@ CONFIG_IOSCHED_CFQ=y
 # CONFIG_DEFAULT_CFQ is not set
 CONFIG_DEFAULT_NOOP=y
 CONFIG_DEFAULT_IOSCHED="noop"
-CONFIG_CLASSIC_RCU=y
 CONFIG_PREEMPT_NONE=y
 # CONFIG_PREEMPT_VOLUNTARY is not set
 # CONFIG_PREEMPT is not set
@@ -181,7 +201,8 @@ CONFIG_IRQ_MEM_DMA1=13
 CONFIG_IRQ_WATCH=13
 CONFIG_IRQ_SPI=10
 # CONFIG_BFIN537_STAMP is not set
-CONFIG_BFIN537_BLUETECHNIX_CM=y
+CONFIG_BFIN537_BLUETECHNIX_CM_E=y
+# CONFIG_BFIN537_BLUETECHNIX_CM_U is not set
 # CONFIG_BFIN537_BLUETECHNIX_TCM is not set
 # CONFIG_PNAV10 is not set
 # CONFIG_CAMSIG_MINOTAUR is not set
@@ -283,10 +304,12 @@ CONFIG_FLATMEM=y
 CONFIG_FLAT_NODE_MEM_MAP=y
 CONFIG_PAGEFLAGS_EXTENDED=y
 CONFIG_SPLIT_PTLOCK_CPUS=4
-# CONFIG_RESOURCES_64BIT is not set
 # CONFIG_PHYS_ADDR_T_64BIT is not set
 CONFIG_ZONE_DMA_FLAG=1
 CONFIG_VIRT_TO_BUS=y
+CONFIG_UNEVICTABLE_LRU=y
+CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
+CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0
 # CONFIG_BFIN_GPTIMERS is not set
 # CONFIG_DMA_UNCACHED_4M is not set
 # CONFIG_DMA_UNCACHED_2M is not set
@@ -297,10 +320,9 @@ CONFIG_DMA_UNCACHED_1M=y
 # Cache Support
 #
 CONFIG_BFIN_ICACHE=y
-# CONFIG_BFIN_ICACHE_LOCK is not set
+CONFIG_BFIN_EXTMEM_ICACHEABLE=y
 CONFIG_BFIN_DCACHE=y
 # CONFIG_BFIN_DCACHE_BANKA is not set
-CONFIG_BFIN_EXTMEM_ICACHEABLE=y
 CONFIG_BFIN_EXTMEM_DCACHEABLE=y
 CONFIG_BFIN_EXTMEM_WRITEBACK=y
 # CONFIG_BFIN_EXTMEM_WRITETHROUGH is not set
@@ -311,7 +333,7 @@ CONFIG_BFIN_EXTMEM_WRITEBACK=y
 # CONFIG_MPU is not set
 
 #
-# Asynchonous Memory Configuration
+# Asynchronous Memory Configuration
 #
 
 #
@@ -337,6 +359,7 @@ CONFIG_BANK_3=0xFFC2
 # Bus options (PCI, PCMCIA, EISA, MCA, ISA)
 #
 # CONFIG_ARCH_SUPPORTS_MSI is not set
+# CONFIG_PCCARD is not set
 
 #
 # Executable file formats
@@ -366,11 +389,6 @@ CONFIG_NET=y
 CONFIG_PACKET=y
 # CONFIG_PACKET_MMAP is not set
 CONFIG_UNIX=y
-CONFIG_XFRM=y
-# CONFIG_XFRM_USER is not set
-# CONFIG_XFRM_SUB_POLICY is not set
-# CONFIG_XFRM_MIGRATE is not set
-# CONFIG_XFRM_STATISTICS is not set
 # CONFIG_NET_KEY is not set
 CONFIG_INET=y
 # CONFIG_IP_MULTICAST is not set
@@ -394,7 +412,6 @@ CONFIG_IP_PNP=y
 # CONFIG_INET_XFRM_MODE_BEET is not set
 # CONFIG_INET_LRO is not set
 # CONFIG_INET_DIAG is not set
-CONFIG_INET_TCP_DIAG=y
 # CONFIG_TCP_CONG_ADVANCED is not set
 CONFIG_TCP_CONG_CUBIC=y
 CONFIG_DEFAULT_TCP_CONG="cubic"
@@ -418,7 +435,9 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
 # CONFIG_LAPB is not set
 # CONFIG_ECONET is not set
 # CONFIG_WAN_ROUTER is not set
+# CONFIG_PHONET is not set
 # CONFIG_NET_SCHED is not set
+# CONFIG_DCB is not set
 
 #
 # Network testing
@@ -429,8 +448,8 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
 # CONFIG_IRDA is not set
 # CONFIG_BT is not set
 # CONFIG_AF_RXRPC is not set
-# CONFIG_PHONET is not set
 # CONFIG_WIRELESS is not set
+# CONFIG_WIMAX is not set
 # CONFIG_RFKILL is not set
 # CONFIG_NET_9P is not set
 
@@ -441,16 +460,21 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
 #
 # Generic Driver Options
 #
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 CONFIG_STANDALONE=y
 CONFIG_PREVENT_FIRMWARE_BUILD=y
+CONFIG_FW_LOADER=y
+CONFIG_FIRMWARE_IN_KERNEL=y
+CONFIG_EXTRA_FIRMWARE=""
 # CONFIG_SYS_HYPERVISOR is not set
 # CONFIG_CONNECTOR is not set
 CONFIG_MTD=y
 # CONFIG_MTD_DEBUG is not set
+# CONFIG_MTD_TESTS is not set
 # CONFIG_MTD_CONCAT is not set
 CONFIG_MTD_PARTITIONS=y
 # CONFIG_MTD_REDBOOT_PARTS is not set
-# CONFIG_MTD_CMDLINE_PARTS is not set
+CONFIG_MTD_CMDLINE_PARTS=y
 # CONFIG_MTD_AR7_PARTS is not set
 
 #
@@ -486,22 +510,26 @@ CONFIG_MTD_CFI_I2=y
 CONFIG_MTD_CFI_INTELEXT=y
 # CONFIG_MTD_CFI_AMDSTD is not set
 # CONFIG_MTD_CFI_STAA is not set
+# CONFIG_MTD_PSD4256G is not set
 CONFIG_MTD_CFI_UTIL=y
 CONFIG_MTD_RAM=y
-# CONFIG_MTD_ROM is not set
+CONFIG_MTD_ROM=m
 # CONFIG_MTD_ABSENT is not set
 
 #
 # Mapping drivers for chip access
 #
 CONFIG_MTD_COMPLEX_MAPPINGS=y
+# CONFIG_MTD_PHYSMAP is not set
 CONFIG_MTD_GPIO_ADDR=y
-CONFIG_MTD_UCLINUX=y
+# CONFIG_MTD_UCLINUX is not set
 # CONFIG_MTD_PLATRAM is not set
 
 #
 # Self-contained MTD device drivers
 #
+# CONFIG_MTD_DATAFLASH is not set
+# CONFIG_MTD_M25P80 is not set
 # CONFIG_MTD_SLRAM is not set
 # CONFIG_MTD_PHRAM is not set
 # CONFIG_MTD_MTDRAM is not set
@@ -517,6 +545,11 @@ CONFIG_MTD_UCLINUX=y
 # CONFIG_MTD_ONENAND is not set
 
 #
+# LPDDR flash memory drivers
+#
+# CONFIG_MTD_LPDDR is not set
+
+#
 # UBI - Unsorted block images
 #
 # CONFIG_MTD_UBI is not set
@@ -533,9 +566,14 @@ CONFIG_BLK_DEV_RAM_SIZE=4096
 # CONFIG_ATA_OVER_ETH is not set
 # CONFIG_BLK_DEV_HD is not set
 CONFIG_MISC_DEVICES=y
-# CONFIG_EEPROM_93CX6 is not set
 # CONFIG_ENCLOSURE_SERVICES is not set
 # CONFIG_C2PORT is not set
+
+#
+# EEPROM support
+#
+# CONFIG_EEPROM_AT25 is not set
+# CONFIG_EEPROM_93CX6 is not set
 CONFIG_HAVE_IDE=y
 # CONFIG_IDE is not set
 
@@ -549,6 +587,7 @@ CONFIG_HAVE_IDE=y
 # CONFIG_ATA is not set
 # CONFIG_MD is not set
 CONFIG_NETDEVICES=y
+CONFIG_COMPAT_NET_DEV_OPS=y
 # CONFIG_DUMMY is not set
 # CONFIG_BONDING is not set
 # CONFIG_MACVLAN is not set
@@ -570,6 +609,9 @@ CONFIG_PHYLIB=y
 # CONFIG_BROADCOM_PHY is not set
 # CONFIG_ICPLUS_PHY is not set
 # CONFIG_REALTEK_PHY is not set
+# CONFIG_NATIONAL_PHY is not set
+# CONFIG_STE10XP is not set
+# CONFIG_LSI_ET1011C_PHY is not set
 # CONFIG_FIXED_PHY is not set
 # CONFIG_MDIO_BITBANG is not set
 CONFIG_NET_ETHERNET=y
@@ -580,8 +622,11 @@ CONFIG_BFIN_TX_DESC_NUM=10
 CONFIG_BFIN_RX_DESC_NUM=20
 # CONFIG_BFIN_MAC_RMII is not set
 # CONFIG_SMC91X is not set
-# CONFIG_SMSC911X is not set
 # CONFIG_DM9000 is not set
+# CONFIG_ENC28J60 is not set
+# CONFIG_ETHOC is not set
+# CONFIG_SMSC911X is not set
+# CONFIG_DNET is not set
 # CONFIG_IBM_NEW_EMAC_ZMII is not set
 # CONFIG_IBM_NEW_EMAC_RGMII is not set
 # CONFIG_IBM_NEW_EMAC_TAH is not set
@@ -598,7 +643,10 @@ CONFIG_BFIN_RX_DESC_NUM=20
 #
 # CONFIG_WLAN_PRE80211 is not set
 # CONFIG_WLAN_80211 is not set
-# CONFIG_IWLWIFI_LEDS is not set
+
+#
+# Enable WiMAX (Networking options) to see the WiMAX drivers
+#
 # CONFIG_WAN is not set
 # CONFIG_PPP is not set
 # CONFIG_SLIP is not set
@@ -622,15 +670,12 @@ CONFIG_BFIN_RX_DESC_NUM=20
 #
 # Character devices
 #
-# CONFIG_AD9960 is not set
 CONFIG_BFIN_DMA_INTERFACE=m
 # CONFIG_BFIN_PPI is not set
 # CONFIG_BFIN_PPIFCD is not set
 # CONFIG_BFIN_SIMPLE_TIMER is not set
 # CONFIG_BFIN_SPI_ADC is not set
 CONFIG_BFIN_SPORT=y
-# CONFIG_BFIN_TIMER_LATENCY is not set
-# CONFIG_SIMPLE_GPIO is not set
 # CONFIG_VT is not set
 # CONFIG_DEVKMEM is not set
 # CONFIG_BFIN_JTAG_COMM is not set
@@ -644,6 +689,7 @@ CONFIG_BFIN_SPORT=y
 #
 # Non-8250 serial port support
 #
+# CONFIG_SERIAL_MAX3100 is not set
 CONFIG_SERIAL_BFIN=y
 CONFIG_SERIAL_BFIN_CONSOLE=y
 CONFIG_SERIAL_BFIN_DMA=y
@@ -656,6 +702,7 @@ CONFIG_SERIAL_CORE=y
 CONFIG_SERIAL_CORE_CONSOLE=y
 # CONFIG_SERIAL_BFIN_SPORT is not set
 CONFIG_UNIX98_PTYS=y
+# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
 # CONFIG_LEGACY_PTYS is not set
 
 #
@@ -668,7 +715,23 @@ CONFIG_UNIX98_PTYS=y
 # CONFIG_RAW_DRIVER is not set
 # CONFIG_TCG_TPM is not set
 # CONFIG_I2C is not set
-# CONFIG_SPI is not set
+CONFIG_SPI=y
+CONFIG_SPI_MASTER=y
+
+#
+# SPI Master Controller Drivers
+#
+CONFIG_SPI_BFIN=y
+# CONFIG_SPI_BFIN_LOCK is not set
+# CONFIG_SPI_BFIN_SPORT is not set
+# CONFIG_SPI_BITBANG is not set
+# CONFIG_SPI_GPIO is not set
+
+#
+# SPI Protocol Masters
+#
+# CONFIG_SPI_SPIDEV is not set
+# CONFIG_SPI_TLE62X0 is not set
 CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
 CONFIG_GPIOLIB=y
 CONFIG_GPIO_SYSFS=y
@@ -688,15 +751,21 @@ CONFIG_GPIO_SYSFS=y
 #
 # SPI GPIO expanders:
 #
+# CONFIG_GPIO_MAX7301 is not set
+# CONFIG_GPIO_MCP23S08 is not set
 # CONFIG_W1 is not set
 # CONFIG_POWER_SUPPLY is not set
 CONFIG_HWMON=y
 # CONFIG_HWMON_VID is not set
+# CONFIG_SENSORS_ADCXX is not set
 # CONFIG_SENSORS_F71805F is not set
 # CONFIG_SENSORS_F71882FG is not set
 # CONFIG_SENSORS_IT87 is not set
+# CONFIG_SENSORS_LM70 is not set
+# CONFIG_SENSORS_MAX1111 is not set
 # CONFIG_SENSORS_PC87360 is not set
 # CONFIG_SENSORS_PC87427 is not set
+# CONFIG_SENSORS_SHT15 is not set
 # CONFIG_SENSORS_SMSC47M1 is not set
 # CONFIG_SENSORS_SMSC47B397 is not set
 # CONFIG_SENSORS_VT1211 is not set
@@ -758,21 +827,74 @@ CONFIG_USB_ARCH_HAS_HCD=y
 # CONFIG_USB is not set
 # CONFIG_USB_OTG_WHITELIST is not set
 # CONFIG_USB_OTG_BLACKLIST_HUB is not set
-
-#
-# Enable Host or Gadget support to see Inventra options
-#
-
-#
-# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may also be needed;
-#
-# CONFIG_USB_GADGET is not set
-# CONFIG_MMC is not set
+# CONFIG_USB_GADGET_MUSB_HDRC is not set
+
+#
+# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
+#
+CONFIG_USB_GADGET=m
+# CONFIG_USB_GADGET_DEBUG_FILES is not set
+# CONFIG_USB_GADGET_DEBUG_FS is not set
+CONFIG_USB_GADGET_VBUS_DRAW=2
+CONFIG_USB_GADGET_SELECTED=y
+# CONFIG_USB_GADGET_AT91 is not set
+# CONFIG_USB_GADGET_ATMEL_USBA is not set
+# CONFIG_USB_GADGET_FSL_USB2 is not set
+# CONFIG_USB_GADGET_LH7A40X is not set
+# CONFIG_USB_GADGET_OMAP is not set
+# CONFIG_USB_GADGET_PXA25X is not set
+# CONFIG_USB_GADGET_PXA27X is not set
+# CONFIG_USB_GADGET_S3C2410 is not set
+# CONFIG_USB_GADGET_IMX is not set
+# CONFIG_USB_GADGET_M66592 is not set
+# CONFIG_USB_GADGET_AMD5536UDC is not set
+# CONFIG_USB_GADGET_FSL_QE is not set
+# CONFIG_USB_GADGET_CI13XXX is not set
+CONFIG_USB_GADGET_NET2272=y
+CONFIG_USB_NET2272=m
+# CONFIG_USB_GADGET_NET2280 is not set
+# CONFIG_USB_GADGET_GOKU is not set
+# CONFIG_USB_GADGET_DUMMY_HCD is not set
+CONFIG_USB_GADGET_DUALSPEED=y
+# CONFIG_USB_ZERO is not set
+# CONFIG_USB_AUDIO is not set
+CONFIG_USB_ETH=m
+CONFIG_USB_ETH_RNDIS=y
+# CONFIG_USB_GADGETFS is not set
+# CONFIG_USB_FILE_STORAGE is not set
+# CONFIG_USB_G_SERIAL is not set
+# CONFIG_USB_MIDI_GADGET is not set
+# CONFIG_USB_G_PRINTER is not set
+# CONFIG_USB_CDC_COMPOSITE is not set
+
+#
+# OTG and related infrastructure
+#
+# CONFIG_USB_GPIO_VBUS is not set
+# CONFIG_NOP_USB_XCEIV is not set
+CONFIG_MMC=y
+# CONFIG_MMC_DEBUG is not set
+# CONFIG_MMC_UNSAFE_RESUME is not set
+
+#
+# MMC/SD/SDIO Card Drivers
+#
+CONFIG_MMC_BLOCK=y
+# CONFIG_MMC_BLOCK_BOUNCE is not set
+# CONFIG_SDIO_UART is not set
+# CONFIG_MMC_TEST is not set
+
+#
+# MMC/SD/SDIO Host Controller Drivers
+#
+# CONFIG_MMC_SDHCI is not set
+CONFIG_MMC_SPI=m
 # CONFIG_MEMSTICK is not set
 # CONFIG_NEW_LEDS is not set
 # CONFIG_ACCESSIBILITY is not set
 # CONFIG_RTC_CLASS is not set
 # CONFIG_DMADEVICES is not set
+# CONFIG_AUXDISPLAY is not set
 # CONFIG_UIO is not set
 # CONFIG_STAGING is not set
 
@@ -789,9 +911,10 @@ CONFIG_FS_MBCACHE=y
 # CONFIG_REISERFS_FS is not set
 # CONFIG_JFS_FS is not set
 # CONFIG_FS_POSIX_ACL is not set
-CONFIG_FILE_LOCKING=y
 # CONFIG_XFS_FS is not set
 # CONFIG_OCFS2_FS is not set
+# CONFIG_BTRFS_FS is not set
+CONFIG_FILE_LOCKING=y
 # CONFIG_DNOTIFY is not set
 CONFIG_INOTIFY=y
 CONFIG_INOTIFY_USER=y
@@ -801,6 +924,11 @@ CONFIG_INOTIFY_USER=y
 # CONFIG_FUSE_FS is not set
 
 #
+# Caches
+#
+# CONFIG_FSCACHE is not set
+
+#
 # CD-ROM/DVD Filesystems
 #
 # CONFIG_ISO9660_FS is not set
@@ -809,8 +937,11 @@ CONFIG_INOTIFY_USER=y
 #
 # DOS/FAT/NT Filesystems
 #
-# CONFIG_MSDOS_FS is not set
-# CONFIG_VFAT_FS is not set
+CONFIG_FAT_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
 # CONFIG_NTFS_FS is not set
 
 #
@@ -822,10 +953,7 @@ CONFIG_SYSFS=y
 # CONFIG_TMPFS is not set
 # CONFIG_HUGETLB_PAGE is not set
 # CONFIG_CONFIGFS_FS is not set
-
-#
-# Miscellaneous filesystems
-#
+CONFIG_MISC_FILESYSTEMS=y
 # CONFIG_ADFS_FS is not set
 # CONFIG_AFFS_FS is not set
 # CONFIG_HFS_FS is not set
@@ -833,9 +961,19 @@ CONFIG_SYSFS=y
 # CONFIG_BEFS_FS is not set
 # CONFIG_BFS_FS is not set
 # CONFIG_EFS_FS is not set
-# CONFIG_JFFS2_FS is not set
-# CONFIG_YAFFS_FS is not set
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_DEBUG=0
+CONFIG_JFFS2_FS_WRITEBUFFER=y
+# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
+# CONFIG_JFFS2_SUMMARY is not set
+# CONFIG_JFFS2_FS_XATTR is not set
+# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
+CONFIG_JFFS2_ZLIB=y
+# CONFIG_JFFS2_LZO is not set
+CONFIG_JFFS2_RTIME=y
+# CONFIG_JFFS2_RUBIN is not set
 # CONFIG_CRAMFS is not set
+# CONFIG_SQUASHFS is not set
 # CONFIG_VXFS_FS is not set
 # CONFIG_MINIX_FS is not set
 # CONFIG_OMFS_FS is not set
@@ -844,14 +982,70 @@ CONFIG_SYSFS=y
 # CONFIG_ROMFS_FS is not set
 # CONFIG_SYSV_FS is not set
 # CONFIG_UFS_FS is not set
-# CONFIG_NETWORK_FILESYSTEMS is not set
+# CONFIG_NILFS2_FS is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_NFS_FS=m
+CONFIG_NFS_V3=y
+# CONFIG_NFS_V3_ACL is not set
+# CONFIG_NFS_V4 is not set
+# CONFIG_NFSD is not set
+CONFIG_LOCKD=m
+CONFIG_LOCKD_V4=y
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=m
+# CONFIG_RPCSEC_GSS_KRB5 is not set
+# CONFIG_RPCSEC_GSS_SPKM3 is not set
+# CONFIG_SMB_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
 
 #
 # Partition Types
 #
 # CONFIG_PARTITION_ADVANCED is not set
 CONFIG_MSDOS_PARTITION=y
-# CONFIG_NLS is not set
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="iso8859-1"
+CONFIG_NLS_CODEPAGE_437=y
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+# CONFIG_NLS_ASCII is not set
+CONFIG_NLS_ISO8859_1=y
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+# CONFIG_NLS_UTF8 is not set
 # CONFIG_DLM is not set
 
 #
@@ -867,14 +1061,28 @@ CONFIG_DEBUG_FS=y
 # CONFIG_HEADERS_CHECK is not set
 CONFIG_DEBUG_SECTION_MISMATCH=y
 # CONFIG_DEBUG_KERNEL is not set
-CONFIG_DEBUG_BUGVERBOSE=y
+# CONFIG_DEBUG_BUGVERBOSE is not set
 # CONFIG_DEBUG_MEMORY_INIT is not set
 # CONFIG_RCU_CPU_STALL_DETECTOR is not set
+CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
+CONFIG_TRACING_SUPPORT=y
 
 #
 # Tracers
 #
-# CONFIG_DYNAMIC_PRINTK_DEBUG is not set
+# CONFIG_FUNCTION_TRACER is not set
+# CONFIG_IRQSOFF_TRACER is not set
+# CONFIG_SCHED_TRACER is not set
+# CONFIG_CONTEXT_SWITCH_TRACER is not set
+# CONFIG_EVENT_TRACER is not set
+# CONFIG_BOOT_TRACER is not set
+# CONFIG_TRACE_BRANCH_PROFILING is not set
+# CONFIG_STACK_TRACER is not set
+# CONFIG_KMEMTRACE is not set
+# CONFIG_WORKQUEUE_TRACER is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_DYNAMIC_DEBUG is not set
 # CONFIG_SAMPLES is not set
 CONFIG_HAVE_ARCH_KGDB=y
 CONFIG_DEBUG_VERBOSE=y
@@ -888,9 +1096,10 @@ CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_OFF=y
 CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION=0
 # CONFIG_DEBUG_BFIN_HWTRACE_EXPAND is not set
 # CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE is not set
-# CONFIG_EARLY_PRINTK is not set
+CONFIG_EARLY_PRINTK=y
 CONFIG_CPLB_INFO=y
 CONFIG_ACCESS_CHECK=y
+# CONFIG_BFIN_ISRAM_SELF_TEST is not set
 
 #
 # Security options
@@ -899,8 +1108,9 @@ CONFIG_ACCESS_CHECK=y
 CONFIG_SECURITY=y
 # CONFIG_SECURITYFS is not set
 # CONFIG_SECURITY_NETWORK is not set
+# CONFIG_SECURITY_PATH is not set
 # CONFIG_SECURITY_FILE_CAPABILITIES is not set
-CONFIG_SECURITY_DEFAULT_MMAP_MIN_ADDR=0
+# CONFIG_SECURITY_TOMOYO is not set
 CONFIG_CRYPTO=y
 
 #
@@ -979,6 +1189,7 @@ CONFIG_CRYPTO=y
 # Compression
 #
 # CONFIG_CRYPTO_DEFLATE is not set
+# CONFIG_CRYPTO_ZLIB is not set
 # CONFIG_CRYPTO_LZO is not set
 
 #
@@ -986,19 +1197,24 @@ CONFIG_CRYPTO=y
 #
 # CONFIG_CRYPTO_ANSI_CPRNG is not set
 CONFIG_CRYPTO_HW=y
+# CONFIG_BINARY_PRINTF is not set
 
 #
 # Library routines
 #
 CONFIG_BITREVERSE=y
+CONFIG_GENERIC_FIND_LAST_BIT=y
 CONFIG_CRC_CCITT=m
 # CONFIG_CRC16 is not set
 # CONFIG_CRC_T10DIF is not set
-# CONFIG_CRC_ITU_T is not set
+CONFIG_CRC_ITU_T=y
 CONFIG_CRC32=y
-# CONFIG_CRC7 is not set
+CONFIG_CRC7=y
 # CONFIG_LIBCRC32C is not set
 CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_DECOMPRESS_LZMA=y
 CONFIG_HAS_IOMEM=y
 CONFIG_HAS_IOPORT=y
 CONFIG_HAS_DMA=y
+CONFIG_NLATTR=y
diff --git a/arch/blackfin/configs/CM-BF537U_defconfig b/arch/blackfin/configs/CM-BF537U_defconfig
index 7fc8dfa1719f..efcc90d2f345 100644
--- a/arch/blackfin/configs/CM-BF537U_defconfig
+++ b/arch/blackfin/configs/CM-BF537U_defconfig
@@ -1,94 +1,111 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.22.16
+# Linux kernel version: 2.6.30.5
 #
 # CONFIG_MMU is not set
 # CONFIG_FPU is not set
 CONFIG_RWSEM_GENERIC_SPINLOCK=y
 # CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
 CONFIG_BLACKFIN=y
+CONFIG_GENERIC_BUG=y
 CONFIG_ZONE_DMA=y
-CONFIG_SEMAPHORE_SLEEPERS=y
 CONFIG_GENERIC_FIND_NEXT_BIT=y
 CONFIG_GENERIC_HWEIGHT=y
 CONFIG_GENERIC_HARDIRQS=y
 CONFIG_GENERIC_IRQ_PROBE=y
-CONFIG_GENERIC_TIME=y
 CONFIG_GENERIC_GPIO=y
 CONFIG_FORCE_MAX_ZONEORDER=14
 CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
 CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
 
 #
-# Code maturity level options
+# General setup
 #
 CONFIG_EXPERIMENTAL=y
 CONFIG_BROKEN_ON_SMP=y
 CONFIG_INIT_ENV_ARG_LIMIT=32
-
-#
-# General setup
-#
 CONFIG_LOCALVERSION=""
 CONFIG_LOCALVERSION_AUTO=y
+CONFIG_HAVE_KERNEL_GZIP=y
+CONFIG_HAVE_KERNEL_BZIP2=y
+CONFIG_HAVE_KERNEL_LZMA=y
+# CONFIG_KERNEL_GZIP is not set
+# CONFIG_KERNEL_BZIP2 is not set
+CONFIG_KERNEL_LZMA=y
 CONFIG_SYSVIPC=y
-# CONFIG_IPC_NS is not set
 CONFIG_SYSVIPC_SYSCTL=y
 # CONFIG_POSIX_MQUEUE is not set
 # CONFIG_BSD_PROCESS_ACCT is not set
 # CONFIG_TASKSTATS is not set
-# CONFIG_UTS_NS is not set
 # CONFIG_AUDIT is not set
+
+#
+# RCU Subsystem
+#
+CONFIG_CLASSIC_RCU=y
+# CONFIG_TREE_RCU is not set
+# CONFIG_PREEMPT_RCU is not set
+# CONFIG_TREE_RCU_TRACE is not set
+# CONFIG_PREEMPT_RCU_TRACE is not set
 CONFIG_IKCONFIG=y
 CONFIG_IKCONFIG_PROC=y
 CONFIG_LOG_BUF_SHIFT=14
-# CONFIG_SYSFS_DEPRECATED is not set
+# CONFIG_GROUP_SCHED is not set
+# CONFIG_CGROUPS is not set
+# CONFIG_SYSFS_DEPRECATED_V2 is not set
 # CONFIG_RELAY is not set
-# CONFIG_BLK_DEV_INITRD is not set
+# CONFIG_NAMESPACES is not set
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+# CONFIG_RD_GZIP is not set
+# CONFIG_RD_BZIP2 is not set
+CONFIG_RD_LZMA=y
 # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
-# CONFIG_SYSCTL is not set
+CONFIG_SYSCTL=y
+CONFIG_ANON_INODES=y
 CONFIG_EMBEDDED=y
 # CONFIG_UID16 is not set
 # CONFIG_SYSCTL_SYSCALL is not set
 CONFIG_KALLSYMS=y
 # CONFIG_KALLSYMS_EXTRA_PASS is not set
-# CONFIG_HOTPLUG is not set
+# CONFIG_STRIP_ASM_SYMS is not set
+CONFIG_HOTPLUG=y
 CONFIG_PRINTK=y
 CONFIG_BUG=y
 # CONFIG_ELF_CORE is not set
 CONFIG_BASE_FULL=y
 # CONFIG_FUTEX is not set
-CONFIG_ANON_INODES=y
 CONFIG_EPOLL=y
 CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
 CONFIG_EVENTFD=y
+CONFIG_AIO=y
 CONFIG_VM_EVENT_COUNTERS=y
-CONFIG_BIG_ORDER_ALLOC_NOFAIL_MAGIC=3
-# CONFIG_NP2 is not set
+CONFIG_COMPAT_BRK=y
 CONFIG_SLAB=y
 # CONFIG_SLUB is not set
 # CONFIG_SLOB is not set
-CONFIG_RT_MUTEXES=y
-CONFIG_TINY_SHMEM=y
+CONFIG_MMAP_ALLOW_UNINITIALIZED=y
+# CONFIG_PROFILING is not set
+# CONFIG_MARKERS is not set
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_SLOW_WORK is not set
+# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
+CONFIG_SLABINFO=y
 CONFIG_BASE_SMALL=0
-
-#
-# Loadable module support
-#
 CONFIG_MODULES=y
+# CONFIG_MODULE_FORCE_LOAD is not set
 CONFIG_MODULE_UNLOAD=y
 # CONFIG_MODULE_FORCE_UNLOAD is not set
 # CONFIG_MODVERSIONS is not set
 # CONFIG_MODULE_SRCVERSION_ALL is not set
-CONFIG_KMOD=y
-
-#
-# Block layer
-#
 CONFIG_BLOCK=y
 # CONFIG_LBD is not set
-# CONFIG_BLK_DEV_IO_TRACE is not set
-# CONFIG_LSF is not set
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_BLK_DEV_INTEGRITY is not set
 
 #
 # IO Schedulers
@@ -105,6 +122,7 @@ CONFIG_DEFAULT_IOSCHED="noop"
 CONFIG_PREEMPT_NONE=y
 # CONFIG_PREEMPT_VOLUNTARY is not set
 # CONFIG_PREEMPT is not set
+# CONFIG_FREEZER is not set
 
 #
 # Blackfin Processor Options
@@ -113,6 +131,10 @@ CONFIG_PREEMPT_NONE=y
 #
 # Processor and Board Settings
 #
+# CONFIG_BF512 is not set
+# CONFIG_BF514 is not set
+# CONFIG_BF516 is not set
+# CONFIG_BF518 is not set
 # CONFIG_BF522 is not set
 # CONFIG_BF523 is not set
 # CONFIG_BF524 is not set
@@ -125,22 +147,31 @@ CONFIG_PREEMPT_NONE=y
 # CONFIG_BF534 is not set
 # CONFIG_BF536 is not set
 CONFIG_BF537=y
+# CONFIG_BF538 is not set
+# CONFIG_BF539 is not set
 # CONFIG_BF542 is not set
+# CONFIG_BF542M is not set
 # CONFIG_BF544 is not set
+# CONFIG_BF544M is not set
 # CONFIG_BF547 is not set
+# CONFIG_BF547M is not set
 # CONFIG_BF548 is not set
+# CONFIG_BF548M is not set
 # CONFIG_BF549 is not set
+# CONFIG_BF549M is not set
 # CONFIG_BF561 is not set
+CONFIG_BF_REV_MIN=2
+CONFIG_BF_REV_MAX=3
 # CONFIG_BF_REV_0_0 is not set
 # CONFIG_BF_REV_0_1 is not set
 CONFIG_BF_REV_0_2=y
 # CONFIG_BF_REV_0_3 is not set
 # CONFIG_BF_REV_0_4 is not set
 # CONFIG_BF_REV_0_5 is not set
+# CONFIG_BF_REV_0_6 is not set
 # CONFIG_BF_REV_ANY is not set
 # CONFIG_BF_REV_NONE is not set
 CONFIG_BF53x=y
-CONFIG_BFIN_SINGLE_CORE=y
 CONFIG_MEM_MT48LC16M16A2TG_75=y
 CONFIG_IRQ_PLL_WAKEUP=7
 CONFIG_IRQ_RTC=8
@@ -150,7 +181,6 @@ CONFIG_IRQ_SPORT0_TX=9
 CONFIG_IRQ_SPORT1_RX=9
 CONFIG_IRQ_SPORT1_TX=9
 CONFIG_IRQ_TWI=10
-CONFIG_IRQ_SPI=10
 CONFIG_IRQ_UART0_RX=10
 CONFIG_IRQ_UART0_TX=10
 CONFIG_IRQ_UART1_RX=10
@@ -169,11 +199,13 @@ CONFIG_IRQ_PORTG_INTB=12
 CONFIG_IRQ_MEM_DMA0=13
 CONFIG_IRQ_MEM_DMA1=13
 CONFIG_IRQ_WATCH=13
+CONFIG_IRQ_SPI=10
 # CONFIG_BFIN537_STAMP is not set
-CONFIG_BFIN537_BLUETECHNIX_CM=y
+# CONFIG_BFIN537_BLUETECHNIX_CM_E is not set
+CONFIG_BFIN537_BLUETECHNIX_CM_U=y
+# CONFIG_BFIN537_BLUETECHNIX_TCM is not set
 # CONFIG_PNAV10 is not set
 # CONFIG_CAMSIG_MINOTAUR is not set
-# CONFIG_GENERIC_BF537_BOARD is not set
 
 #
 # BF537 Specific Configuration
@@ -196,6 +228,7 @@ CONFIG_IRQ_PROG_INTA=12
 # Board customizations
 #
 # CONFIG_CMDLINE_BOOL is not set
+CONFIG_BOOT_LOAD=0x1000
 
 #
 # Clock/PLL Setup
@@ -215,13 +248,20 @@ CONFIG_HZ_250=y
 # CONFIG_HZ_300 is not set
 # CONFIG_HZ_1000 is not set
 CONFIG_HZ=250
+# CONFIG_SCHED_HRTICK is not set
+CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+# CONFIG_TICKSOURCE_GPTMR0 is not set
+CONFIG_TICKSOURCE_CORETMR=y
+# CONFIG_CYCLES_CLOCKSOURCE is not set
+# CONFIG_GPTMR0_CLOCKSOURCE is not set
+# CONFIG_NO_HZ is not set
+# CONFIG_HIGH_RES_TIMERS is not set
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
 
 #
-# Memory Setup
+# Misc
 #
-CONFIG_MAX_MEM_SIZE=32
-CONFIG_MEM_ADD_WIDTH=9
-CONFIG_BOOT_LOAD=0x1000
 CONFIG_BFIN_SCRATCH_REG_RETN=y
 # CONFIG_BFIN_SCRATCH_REG_RETE is not set
 # CONFIG_BFIN_SCRATCH_REG_CYCLES is not set
@@ -248,6 +288,12 @@ CONFIG_IP_CHECKSUM_L1=y
 CONFIG_CACHELINE_ALIGNED_L1=y
 CONFIG_SYSCALL_TAB_L1=y
 CONFIG_CPLB_SWITCH_TAB_L1=y
+CONFIG_APP_STACK_L1=y
+
+#
+# Speed Optimizations
+#
+CONFIG_BFIN_INS_LOWOVERHEAD=y
 CONFIG_RAMKERNEL=y
 # CONFIG_ROMKERNEL is not set
 CONFIG_SELECT_MEMORY_MODEL=y
@@ -256,12 +302,16 @@ CONFIG_FLATMEM_MANUAL=y
 # CONFIG_SPARSEMEM_MANUAL is not set
 CONFIG_FLATMEM=y
 CONFIG_FLAT_NODE_MEM_MAP=y
-# CONFIG_SPARSEMEM_STATIC is not set
+CONFIG_PAGEFLAGS_EXTENDED=y
 CONFIG_SPLIT_PTLOCK_CPUS=4
-# CONFIG_RESOURCES_64BIT is not set
+# CONFIG_PHYS_ADDR_T_64BIT is not set
 CONFIG_ZONE_DMA_FLAG=1
-CONFIG_LARGE_ALLOCS=y
+CONFIG_VIRT_TO_BUS=y
+CONFIG_UNEVICTABLE_LRU=y
+CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
+CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0
 # CONFIG_BFIN_GPTIMERS is not set
+# CONFIG_DMA_UNCACHED_4M is not set
 # CONFIG_DMA_UNCACHED_2M is not set
 CONFIG_DMA_UNCACHED_1M=y
 # CONFIG_DMA_UNCACHED_NONE is not set
@@ -270,10 +320,9 @@ CONFIG_DMA_UNCACHED_1M=y
 # Cache Support
 #
 CONFIG_BFIN_ICACHE=y
-# CONFIG_BFIN_ICACHE_LOCK is not set
+CONFIG_BFIN_EXTMEM_ICACHEABLE=y
 CONFIG_BFIN_DCACHE=y
 # CONFIG_BFIN_DCACHE_BANKA is not set
-CONFIG_BFIN_EXTMEM_ICACHEABLE=y
 CONFIG_BFIN_EXTMEM_DCACHEABLE=y
 CONFIG_BFIN_EXTMEM_WRITEBACK=y
 # CONFIG_BFIN_EXTMEM_WRITETHROUGH is not set
@@ -284,7 +333,7 @@ CONFIG_BFIN_EXTMEM_WRITEBACK=y
 # CONFIG_MPU is not set
 
 #
-# Asynchonous Memory Configuration
+# Asynchronous Memory Configuration
 #
 
 #
@@ -309,12 +358,8 @@ CONFIG_BANK_3=0xFFC2
 #
 # Bus options (PCI, PCMCIA, EISA, MCA, ISA)
 #
-# CONFIG_PCI is not set
 # CONFIG_ARCH_SUPPORTS_MSI is not set
-
-#
-# PCCARD (PCMCIA/CardBus) support
-#
+# CONFIG_PCCARD is not set
 
 #
 # Executable file formats
@@ -323,22 +368,19 @@ CONFIG_BINFMT_ELF_FDPIC=y
 CONFIG_BINFMT_FLAT=y
 CONFIG_BINFMT_ZFLAT=y
 CONFIG_BINFMT_SHARED_FLAT=y
+# CONFIG_HAVE_AOUT is not set
 # CONFIG_BINFMT_MISC is not set
 
 #
 # Power management options
 #
 # CONFIG_PM is not set
-# CONFIG_PM_WAKEUP_BY_GPIO is not set
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
 
 #
 # CPU Frequency scaling
 #
 # CONFIG_CPU_FREQ is not set
-
-#
-# Networking
-#
 CONFIG_NET=y
 
 #
@@ -347,10 +389,6 @@ CONFIG_NET=y
 CONFIG_PACKET=y
 # CONFIG_PACKET_MMAP is not set
 CONFIG_UNIX=y
-CONFIG_XFRM=y
-# CONFIG_XFRM_USER is not set
-# CONFIG_XFRM_SUB_POLICY is not set
-# CONFIG_XFRM_MIGRATE is not set
 # CONFIG_NET_KEY is not set
 CONFIG_INET=y
 # CONFIG_IP_MULTICAST is not set
@@ -369,15 +407,13 @@ CONFIG_IP_FIB_HASH=y
 # CONFIG_INET_XFRM_MODE_TRANSPORT is not set
 # CONFIG_INET_XFRM_MODE_TUNNEL is not set
 # CONFIG_INET_XFRM_MODE_BEET is not set
+CONFIG_INET_LRO=y
 # CONFIG_INET_DIAG is not set
-CONFIG_INET_TCP_DIAG=y
 # CONFIG_TCP_CONG_ADVANCED is not set
 CONFIG_TCP_CONG_CUBIC=y
 CONFIG_DEFAULT_TCP_CONG="cubic"
 # CONFIG_TCP_MD5SIG is not set
 # CONFIG_IPV6 is not set
-# CONFIG_INET6_XFRM_TUNNEL is not set
-# CONFIG_INET6_TUNNEL is not set
 # CONFIG_NETLABEL is not set
 # CONFIG_NETWORK_SECMARK is not set
 # CONFIG_NETFILTER is not set
@@ -386,6 +422,7 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
 # CONFIG_TIPC is not set
 # CONFIG_ATM is not set
 # CONFIG_BRIDGE is not set
+# CONFIG_NET_DSA is not set
 # CONFIG_VLAN_8021Q is not set
 # CONFIG_DECNET is not set
 # CONFIG_LLC2 is not set
@@ -395,29 +432,23 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
 # CONFIG_LAPB is not set
 # CONFIG_ECONET is not set
 # CONFIG_WAN_ROUTER is not set
-
-#
-# QoS and/or fair queueing
-#
+# CONFIG_PHONET is not set
 # CONFIG_NET_SCHED is not set
+# CONFIG_DCB is not set
 
 #
 # Network testing
 #
 # CONFIG_NET_PKTGEN is not set
 # CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
 # CONFIG_IRDA is not set
 # CONFIG_BT is not set
 # CONFIG_AF_RXRPC is not set
-
-#
-# Wireless
-#
-# CONFIG_CFG80211 is not set
-# CONFIG_WIRELESS_EXT is not set
-# CONFIG_MAC80211 is not set
-# CONFIG_IEEE80211 is not set
+# CONFIG_WIRELESS is not set
+# CONFIG_WIMAX is not set
 # CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
 
 #
 # Device Drivers
@@ -426,20 +457,22 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
 #
 # Generic Driver Options
 #
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 CONFIG_STANDALONE=y
 CONFIG_PREVENT_FIRMWARE_BUILD=y
+CONFIG_FW_LOADER=y
+CONFIG_FIRMWARE_IN_KERNEL=y
+CONFIG_EXTRA_FIRMWARE=""
 # CONFIG_SYS_HYPERVISOR is not set
-
-#
-# Connector - unified userspace <-> kernelspace linker
-#
 # CONFIG_CONNECTOR is not set
 CONFIG_MTD=y
 # CONFIG_MTD_DEBUG is not set
+# CONFIG_MTD_TESTS is not set
 # CONFIG_MTD_CONCAT is not set
 CONFIG_MTD_PARTITIONS=y
 # CONFIG_MTD_REDBOOT_PARTS is not set
-# CONFIG_MTD_CMDLINE_PARTS is not set
+CONFIG_MTD_CMDLINE_PARTS=y
+# CONFIG_MTD_AR7_PARTS is not set
 
 #
 # User Modules And Translation Layers
@@ -452,12 +485,15 @@ CONFIG_MTD_BLOCK=y
 # CONFIG_INFTL is not set
 # CONFIG_RFD_FTL is not set
 # CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
 
 #
 # RAM/ROM/Flash chip drivers
 #
-# CONFIG_MTD_CFI is not set
+CONFIG_MTD_CFI=y
 # CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_GEN_PROBE=y
+# CONFIG_MTD_CFI_ADV_OPTIONS is not set
 CONFIG_MTD_MAP_BANK_WIDTH_1=y
 CONFIG_MTD_MAP_BANK_WIDTH_2=y
 CONFIG_MTD_MAP_BANK_WIDTH_4=y
@@ -468,20 +504,29 @@ CONFIG_MTD_CFI_I1=y
 CONFIG_MTD_CFI_I2=y
 # CONFIG_MTD_CFI_I4 is not set
 # CONFIG_MTD_CFI_I8 is not set
+CONFIG_MTD_CFI_INTELEXT=y
+# CONFIG_MTD_CFI_AMDSTD is not set
+# CONFIG_MTD_CFI_STAA is not set
+# CONFIG_MTD_PSD4256G is not set
+CONFIG_MTD_CFI_UTIL=y
 CONFIG_MTD_RAM=y
-# CONFIG_MTD_ROM is not set
+CONFIG_MTD_ROM=m
 # CONFIG_MTD_ABSENT is not set
 
 #
 # Mapping drivers for chip access
 #
-# CONFIG_MTD_COMPLEX_MAPPINGS is not set
-CONFIG_MTD_UCLINUX=y
+CONFIG_MTD_COMPLEX_MAPPINGS=y
+# CONFIG_MTD_PHYSMAP is not set
+CONFIG_MTD_GPIO_ADDR=y
+# CONFIG_MTD_UCLINUX is not set
 # CONFIG_MTD_PLATRAM is not set
 
 #
 # Self-contained MTD device drivers
 #
+# CONFIG_MTD_DATAFLASH is not set
+# CONFIG_MTD_M25P80 is not set
 # CONFIG_MTD_SLRAM is not set
 # CONFIG_MTD_PHRAM is not set
 # CONFIG_MTD_MTDRAM is not set
@@ -497,36 +542,36 @@ CONFIG_MTD_UCLINUX=y
 # CONFIG_MTD_ONENAND is not set
 
 #
-# UBI - Unsorted block images
+# LPDDR flash memory drivers
 #
-# CONFIG_MTD_UBI is not set
+# CONFIG_MTD_LPDDR is not set
 
 #
-# Parallel port support
+# UBI - Unsorted block images
 #
+# CONFIG_MTD_UBI is not set
 # CONFIG_PARPORT is not set
-
-#
-# Plug and Play support
-#
-# CONFIG_PNPACPI is not set
-
-#
-# Block devices
-#
+CONFIG_BLK_DEV=y
 # CONFIG_BLK_DEV_COW_COMMON is not set
 # CONFIG_BLK_DEV_LOOP is not set
 # CONFIG_BLK_DEV_NBD is not set
 CONFIG_BLK_DEV_RAM=y
 CONFIG_BLK_DEV_RAM_COUNT=16
 CONFIG_BLK_DEV_RAM_SIZE=4096
-CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
+# CONFIG_BLK_DEV_XIP is not set
 # CONFIG_CDROM_PKTCDVD is not set
 # CONFIG_ATA_OVER_ETH is not set
+# CONFIG_BLK_DEV_HD is not set
+CONFIG_MISC_DEVICES=y
+# CONFIG_ENCLOSURE_SERVICES is not set
+# CONFIG_C2PORT is not set
 
 #
-# Misc devices
+# EEPROM support
 #
+# CONFIG_EEPROM_AT25 is not set
+# CONFIG_EEPROM_93CX6 is not set
+CONFIG_HAVE_IDE=y
 # CONFIG_IDE is not set
 
 #
@@ -534,35 +579,20 @@ CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
 #
 # CONFIG_RAID_ATTRS is not set
 # CONFIG_SCSI is not set
+# CONFIG_SCSI_DMA is not set
 # CONFIG_SCSI_NETLINK is not set
 # CONFIG_ATA is not set
-
-#
-# Multi-device support (RAID and LVM)
-#
 # CONFIG_MD is not set
-
-#
-# Network device support
-#
 CONFIG_NETDEVICES=y
+CONFIG_COMPAT_NET_DEV_OPS=y
 # CONFIG_DUMMY is not set
 # CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
 # CONFIG_EQUALIZER is not set
 # CONFIG_TUN is not set
-# CONFIG_PHYLIB is not set
-
-#
-# Ethernet (10 or 100Mbit)
-#
-CONFIG_NET_ETHERNET=y
-CONFIG_MII=y
-CONFIG_SMC91X=y
-# CONFIG_BFIN_MAC is not set
-# CONFIG_SMSC911X is not set
-# CONFIG_DM9000 is not set
+# CONFIG_VETH is not set
+# CONFIG_NET_ETHERNET is not set
 # CONFIG_NETDEV_1000 is not set
-# CONFIG_AX88180 is not set
 # CONFIG_NETDEV_10000 is not set
 
 #
@@ -570,22 +600,17 @@ CONFIG_SMC91X=y
 #
 # CONFIG_WLAN_PRE80211 is not set
 # CONFIG_WLAN_80211 is not set
+
+#
+# Enable WiMAX (Networking options) to see the WiMAX drivers
+#
 # CONFIG_WAN is not set
 # CONFIG_PPP is not set
 # CONFIG_SLIP is not set
-# CONFIG_SHAPER is not set
 # CONFIG_NETCONSOLE is not set
 # CONFIG_NETPOLL is not set
 # CONFIG_NET_POLL_CONTROLLER is not set
-
-#
-# ISDN subsystem
-#
 # CONFIG_ISDN is not set
-
-#
-# Telephony Support
-#
 # CONFIG_PHONE is not set
 
 #
@@ -602,16 +627,15 @@ CONFIG_SMC91X=y
 #
 # Character devices
 #
-# CONFIG_AD9960 is not set
-# CONFIG_SPI_ADC_BF533 is not set
-# CONFIG_BF5xx_PFLAGS is not set
-# CONFIG_BF5xx_PPIFCD is not set
+CONFIG_BFIN_DMA_INTERFACE=m
+# CONFIG_BFIN_PPI is not set
+# CONFIG_BFIN_PPIFCD is not set
 # CONFIG_BFIN_SIMPLE_TIMER is not set
-# CONFIG_BF5xx_PPI is not set
+# CONFIG_BFIN_SPI_ADC is not set
 CONFIG_BFIN_SPORT=y
-# CONFIG_BFIN_TIMER_LATENCY is not set
 # CONFIG_VT is not set
 # CONFIG_DEVKMEM is not set
+# CONFIG_BFIN_JTAG_COMM is not set
 # CONFIG_SERIAL_NONSTANDARD is not set
 
 #
@@ -622,6 +646,7 @@ CONFIG_BFIN_SPORT=y
 #
 # Non-8250 serial port support
 #
+# CONFIG_SERIAL_MAX3100 is not set
 CONFIG_SERIAL_BFIN=y
 CONFIG_SERIAL_BFIN_CONSOLE=y
 CONFIG_SERIAL_BFIN_DMA=y
@@ -634,165 +659,201 @@ CONFIG_SERIAL_CORE=y
 CONFIG_SERIAL_CORE_CONSOLE=y
 # CONFIG_SERIAL_BFIN_SPORT is not set
 CONFIG_UNIX98_PTYS=y
+# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
 # CONFIG_LEGACY_PTYS is not set
 
 #
 # CAN, the car bus and industrial fieldbus
 #
 # CONFIG_CAN4LINUX is not set
-
-#
-# IPMI
-#
 # CONFIG_IPMI_HANDLER is not set
-# CONFIG_WATCHDOG is not set
 # CONFIG_HW_RANDOM is not set
-# CONFIG_GEN_RTC is not set
 # CONFIG_R3964 is not set
 # CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+# CONFIG_I2C is not set
+CONFIG_SPI=y
+CONFIG_SPI_MASTER=y
 
 #
-# TPM devices
+# SPI Master Controller Drivers
 #
-# CONFIG_TCG_TPM is not set
-# CONFIG_I2C is not set
+CONFIG_SPI_BFIN=y
+# CONFIG_SPI_BFIN_LOCK is not set
+# CONFIG_SPI_BFIN_SPORT is not set
+# CONFIG_SPI_BITBANG is not set
+# CONFIG_SPI_GPIO is not set
 
+#
+# SPI Protocol Masters
+#
+# CONFIG_SPI_SPIDEV is not set
+# CONFIG_SPI_TLE62X0 is not set
 CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
 CONFIG_GPIOLIB=y
 CONFIG_GPIO_SYSFS=y
 
 #
-# SPI support
+# Memory mapped GPIO expanders:
+#
+
+#
+# I2C GPIO expanders:
 #
-# CONFIG_SPI is not set
-# CONFIG_SPI_MASTER is not set
 
 #
-# Dallas's 1-wire bus
+# PCI GPIO expanders:
 #
+
+#
+# SPI GPIO expanders:
+#
+# CONFIG_GPIO_MAX7301 is not set
+# CONFIG_GPIO_MCP23S08 is not set
 # CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
 CONFIG_HWMON=y
 # CONFIG_HWMON_VID is not set
-# CONFIG_SENSORS_ABITUGURU is not set
+# CONFIG_SENSORS_ADCXX is not set
 # CONFIG_SENSORS_F71805F is not set
+# CONFIG_SENSORS_F71882FG is not set
+# CONFIG_SENSORS_IT87 is not set
+# CONFIG_SENSORS_LM70 is not set
+# CONFIG_SENSORS_MAX1111 is not set
+# CONFIG_SENSORS_PC87360 is not set
 # CONFIG_SENSORS_PC87427 is not set
+# CONFIG_SENSORS_SHT15 is not set
 # CONFIG_SENSORS_SMSC47M1 is not set
 # CONFIG_SENSORS_SMSC47B397 is not set
 # CONFIG_SENSORS_VT1211 is not set
 # CONFIG_SENSORS_W83627HF is not set
+# CONFIG_SENSORS_W83627EHF is not set
 # CONFIG_HWMON_DEBUG_CHIP is not set
+# CONFIG_THERMAL is not set
+# CONFIG_THERMAL_HWMON is not set
+# CONFIG_WATCHDOG is not set
+CONFIG_SSB_POSSIBLE=y
+
+#
+# Sonics Silicon Backplane
+#
+# CONFIG_SSB is not set
 
 #
 # Multifunction device drivers
 #
+# CONFIG_MFD_CORE is not set
 # CONFIG_MFD_SM501 is not set
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_MFD_TMIO is not set
+# CONFIG_REGULATOR is not set
 
 #
 # Multimedia devices
 #
+
+#
+# Multimedia core support
+#
 # CONFIG_VIDEO_DEV is not set
 # CONFIG_DVB_CORE is not set
-# CONFIG_DAB is not set
+# CONFIG_VIDEO_MEDIA is not set
 
 #
-# Graphics support
+# Multimedia drivers
 #
-# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+# CONFIG_DAB is not set
 
 #
-# Display device support
+# Graphics support
 #
-# CONFIG_DISPLAY_SUPPORT is not set
 # CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
 # CONFIG_FB is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
 
 #
-# Sound
+# Display device support
 #
+# CONFIG_DISPLAY_SUPPORT is not set
 # CONFIG_SOUND is not set
-
-#
-# USB support
-#
+CONFIG_USB_SUPPORT=y
 CONFIG_USB_ARCH_HAS_HCD=y
 # CONFIG_USB_ARCH_HAS_OHCI is not set
 # CONFIG_USB_ARCH_HAS_EHCI is not set
 # CONFIG_USB is not set
-# CONFIG_USB_MUSB_HDRC is not set
+# CONFIG_USB_OTG_WHITELIST is not set
+# CONFIG_USB_OTG_BLACKLIST_HUB is not set
 # CONFIG_USB_GADGET_MUSB_HDRC is not set
 
 #
-# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
-#
-
-#
-# USB Gadget Support
+# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
 #
 CONFIG_USB_GADGET=y
 # CONFIG_USB_GADGET_DEBUG_FILES is not set
+# CONFIG_USB_GADGET_DEBUG_FS is not set
+CONFIG_USB_GADGET_VBUS_DRAW=2
 CONFIG_USB_GADGET_SELECTED=y
+# CONFIG_USB_GADGET_AT91 is not set
+# CONFIG_USB_GADGET_ATMEL_USBA is not set
 # CONFIG_USB_GADGET_FSL_USB2 is not set
+# CONFIG_USB_GADGET_LH7A40X is not set
+# CONFIG_USB_GADGET_OMAP is not set
+# CONFIG_USB_GADGET_PXA25X is not set
+# CONFIG_USB_GADGET_PXA27X is not set
+# CONFIG_USB_GADGET_S3C2410 is not set
+# CONFIG_USB_GADGET_IMX is not set
+# CONFIG_USB_GADGET_M66592 is not set
+# CONFIG_USB_GADGET_AMD5536UDC is not set
+# CONFIG_USB_GADGET_FSL_QE is not set
+# CONFIG_USB_GADGET_CI13XXX is not set
 CONFIG_USB_GADGET_NET2272=y
 CONFIG_USB_NET2272=y
 # CONFIG_USB_GADGET_NET2280 is not set
-# CONFIG_USB_GADGET_PXA2XX is not set
 # CONFIG_USB_GADGET_GOKU is not set
-# CONFIG_USB_GADGET_LH7A40X is not set
-# CONFIG_USB_GADGET_OMAP is not set
-# CONFIG_USB_GADGET_AT91 is not set
 # CONFIG_USB_GADGET_DUMMY_HCD is not set
 CONFIG_USB_GADGET_DUALSPEED=y
 # CONFIG_USB_ZERO is not set
-# CONFIG_USB_ETH is not set
+# CONFIG_USB_AUDIO is not set
+CONFIG_USB_ETH=y
+CONFIG_USB_ETH_RNDIS=y
 # CONFIG_USB_GADGETFS is not set
 # CONFIG_USB_FILE_STORAGE is not set
 # CONFIG_USB_G_SERIAL is not set
 # CONFIG_USB_MIDI_GADGET is not set
-# CONFIG_MMC is not set
-
-#
-# LED devices
-#
-# CONFIG_NEW_LEDS is not set
-
-#
-# LED drivers
-#
-
-#
-# LED Triggers
-#
+# CONFIG_USB_G_PRINTER is not set
+# CONFIG_USB_CDC_COMPOSITE is not set
 
 #
-# InfiniBand support
+# OTG and related infrastructure
 #
+# CONFIG_USB_GPIO_VBUS is not set
+# CONFIG_NOP_USB_XCEIV is not set
+CONFIG_MMC=y
+# CONFIG_MMC_DEBUG is not set
+# CONFIG_MMC_UNSAFE_RESUME is not set
 
 #
-# EDAC - error detection and reporting (RAS) (EXPERIMENTAL)
+# MMC/SD/SDIO Card Drivers
 #
+CONFIG_MMC_BLOCK=y
+CONFIG_MMC_BLOCK_BOUNCE=y
+# CONFIG_SDIO_UART is not set
+# CONFIG_MMC_TEST is not set
 
 #
-# Real Time Clock
+# MMC/SD/SDIO Host Controller Drivers
 #
+# CONFIG_MMC_SDHCI is not set
+CONFIG_MMC_SPI=m
+# CONFIG_MEMSTICK is not set
+# CONFIG_NEW_LEDS is not set
+# CONFIG_ACCESSIBILITY is not set
 # CONFIG_RTC_CLASS is not set
-
-#
-# DMA Engine support
-#
-# CONFIG_DMA_ENGINE is not set
-
-#
-# DMA Clients
-#
-
-#
-# DMA Devices
-#
-
-#
-# PBX support
-#
-# CONFIG_PBX is not set
+# CONFIG_DMADEVICES is not set
+# CONFIG_AUXDISPLAY is not set
+# CONFIG_UIO is not set
+# CONFIG_STAGING is not set
 
 #
 # File systems
@@ -802,25 +863,29 @@ CONFIG_EXT2_FS_XATTR=y
 # CONFIG_EXT2_FS_POSIX_ACL is not set
 # CONFIG_EXT2_FS_SECURITY is not set
 # CONFIG_EXT3_FS is not set
-# CONFIG_EXT4DEV_FS is not set
+# CONFIG_EXT4_FS is not set
 CONFIG_FS_MBCACHE=y
 # CONFIG_REISERFS_FS is not set
 # CONFIG_JFS_FS is not set
 # CONFIG_FS_POSIX_ACL is not set
 # CONFIG_XFS_FS is not set
-# CONFIG_GFS2_FS is not set
 # CONFIG_OCFS2_FS is not set
-# CONFIG_MINIX_FS is not set
-# CONFIG_ROMFS_FS is not set
+# CONFIG_BTRFS_FS is not set
+CONFIG_FILE_LOCKING=y
+# CONFIG_DNOTIFY is not set
 CONFIG_INOTIFY=y
 CONFIG_INOTIFY_USER=y
 # CONFIG_QUOTA is not set
-# CONFIG_DNOTIFY is not set
 # CONFIG_AUTOFS_FS is not set
 # CONFIG_AUTOFS4_FS is not set
 # CONFIG_FUSE_FS is not set
 
 #
+# Caches
+#
+# CONFIG_FSCACHE is not set
+
+#
 # CD-ROM/DVD Filesystems
 #
 # CONFIG_ISO9660_FS is not set
@@ -829,8 +894,11 @@ CONFIG_INOTIFY_USER=y
 #
 # DOS/FAT/NT Filesystems
 #
-# CONFIG_MSDOS_FS is not set
-# CONFIG_VFAT_FS is not set
+CONFIG_FAT_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
 # CONFIG_NTFS_FS is not set
 
 #
@@ -841,12 +909,8 @@ CONFIG_PROC_SYSCTL=y
 CONFIG_SYSFS=y
 # CONFIG_TMPFS is not set
 # CONFIG_HUGETLB_PAGE is not set
-CONFIG_RAMFS=y
 # CONFIG_CONFIGFS_FS is not set
-
-#
-# Miscellaneous filesystems
-#
+CONFIG_MISC_FILESYSTEMS=y
 # CONFIG_ADFS_FS is not set
 # CONFIG_AFFS_FS is not set
 # CONFIG_HFS_FS is not set
@@ -854,18 +918,29 @@ CONFIG_RAMFS=y
 # CONFIG_BEFS_FS is not set
 # CONFIG_BFS_FS is not set
 # CONFIG_EFS_FS is not set
-# CONFIG_YAFFS_FS is not set
-# CONFIG_JFFS2_FS is not set
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_DEBUG=0
+CONFIG_JFFS2_FS_WRITEBUFFER=y
+# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
+# CONFIG_JFFS2_SUMMARY is not set
+# CONFIG_JFFS2_FS_XATTR is not set
+# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
+CONFIG_JFFS2_ZLIB=y
+# CONFIG_JFFS2_LZO is not set
+CONFIG_JFFS2_RTIME=y
+# CONFIG_JFFS2_RUBIN is not set
 # CONFIG_CRAMFS is not set
+# CONFIG_SQUASHFS is not set
 # CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_OMFS_FS is not set
 # CONFIG_HPFS_FS is not set
 # CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
 # CONFIG_SYSV_FS is not set
 # CONFIG_UFS_FS is not set
-
-#
-# Network File Systems
-#
+# CONFIG_NILFS2_FS is not set
+CONFIG_NETWORK_FILESYSTEMS=y
 # CONFIG_NFS_FS is not set
 # CONFIG_NFSD is not set
 # CONFIG_SMB_FS is not set
@@ -873,41 +948,94 @@ CONFIG_RAMFS=y
 # CONFIG_NCP_FS is not set
 # CONFIG_CODA_FS is not set
 # CONFIG_AFS_FS is not set
-# CONFIG_9P_FS is not set
 
 #
 # Partition Types
 #
 # CONFIG_PARTITION_ADVANCED is not set
 CONFIG_MSDOS_PARTITION=y
-
-#
-# Native Language Support
-#
-# CONFIG_NLS is not set
-
-#
-# Distributed Lock Manager
-#
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="iso8859-1"
+CONFIG_NLS_CODEPAGE_437=y
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+# CONFIG_NLS_ASCII is not set
+CONFIG_NLS_ISO8859_1=y
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+# CONFIG_NLS_UTF8 is not set
 # CONFIG_DLM is not set
 
 #
-# Profiling support
-#
-# CONFIG_PROFILING is not set
-
-#
 # Kernel hacking
 #
 # CONFIG_PRINTK_TIME is not set
+CONFIG_ENABLE_WARN_DEPRECATED=y
 CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_FRAME_WARN=1024
 # CONFIG_MAGIC_SYSRQ is not set
 # CONFIG_UNUSED_SYMBOLS is not set
 CONFIG_DEBUG_FS=y
 # CONFIG_HEADERS_CHECK is not set
+CONFIG_DEBUG_SECTION_MISMATCH=y
 # CONFIG_DEBUG_KERNEL is not set
-CONFIG_DEBUG_BUGVERBOSE=y
+# CONFIG_DEBUG_BUGVERBOSE is not set
+# CONFIG_DEBUG_MEMORY_INIT is not set
+# CONFIG_RCU_CPU_STALL_DETECTOR is not set
+CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
+CONFIG_TRACING_SUPPORT=y
+
+#
+# Tracers
+#
+# CONFIG_FUNCTION_TRACER is not set
+# CONFIG_IRQSOFF_TRACER is not set
+# CONFIG_SCHED_TRACER is not set
+# CONFIG_CONTEXT_SWITCH_TRACER is not set
+# CONFIG_EVENT_TRACER is not set
+# CONFIG_BOOT_TRACER is not set
+# CONFIG_TRACE_BRANCH_PROFILING is not set
+# CONFIG_STACK_TRACER is not set
+# CONFIG_KMEMTRACE is not set
+# CONFIG_WORKQUEUE_TRACER is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_DYNAMIC_DEBUG is not set
+# CONFIG_SAMPLES is not set
+CONFIG_HAVE_ARCH_KGDB=y
+CONFIG_DEBUG_VERBOSE=y
 CONFIG_DEBUG_MMRS=y
+# CONFIG_DEBUG_DOUBLEFAULT is not set
 CONFIG_DEBUG_HUNT_FOR_ZERO=y
 CONFIG_DEBUG_BFIN_HWTRACE_ON=y
 CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_OFF=y
@@ -916,34 +1044,40 @@ CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_OFF=y
 CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION=0
 # CONFIG_DEBUG_BFIN_HWTRACE_EXPAND is not set
 # CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE is not set
-# CONFIG_EARLY_PRINTK is not set
+CONFIG_EARLY_PRINTK=y
 CONFIG_CPLB_INFO=y
 CONFIG_ACCESS_CHECK=y
+# CONFIG_BFIN_ISRAM_SELF_TEST is not set
 
 #
 # Security options
 #
 # CONFIG_KEYS is not set
 CONFIG_SECURITY=y
+# CONFIG_SECURITYFS is not set
 # CONFIG_SECURITY_NETWORK is not set
-CONFIG_SECURITY_CAPABILITIES=y
-
-#
-# Cryptographic options
-#
+# CONFIG_SECURITY_PATH is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+# CONFIG_SECURITY_TOMOYO is not set
 # CONFIG_CRYPTO is not set
+# CONFIG_BINARY_PRINTF is not set
 
 #
 # Library routines
 #
 CONFIG_BITREVERSE=y
+CONFIG_GENERIC_FIND_LAST_BIT=y
 CONFIG_CRC_CCITT=m
 # CONFIG_CRC16 is not set
-# CONFIG_CRC_ITU_T is not set
+# CONFIG_CRC_T10DIF is not set
+CONFIG_CRC_ITU_T=y
 CONFIG_CRC32=y
+CONFIG_CRC7=y
 # CONFIG_LIBCRC32C is not set
 CONFIG_ZLIB_INFLATE=y
-CONFIG_PLIST=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_DECOMPRESS_LZMA=y
 CONFIG_HAS_IOMEM=y
 CONFIG_HAS_IOPORT=y
 CONFIG_HAS_DMA=y
+CONFIG_NLATTR=y
diff --git a/arch/blackfin/configs/CM-BF548_defconfig b/arch/blackfin/configs/CM-BF548_defconfig
index acca4e51a45a..7f579cf51127 100644
--- a/arch/blackfin/configs/CM-BF548_defconfig
+++ b/arch/blackfin/configs/CM-BF548_defconfig
@@ -1,14 +1,14 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.24.4
+# Linux kernel version: 2.6.30.5
 #
 # CONFIG_MMU is not set
 # CONFIG_FPU is not set
 CONFIG_RWSEM_GENERIC_SPINLOCK=y
 # CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
 CONFIG_BLACKFIN=y
+CONFIG_GENERIC_BUG=y
 CONFIG_ZONE_DMA=y
-CONFIG_SEMAPHORE_SLEEPERS=y
 CONFIG_GENERIC_FIND_NEXT_BIT=y
 CONFIG_GENERIC_HWEIGHT=y
 CONFIG_GENERIC_HARDIRQS=y
@@ -16,6 +16,9 @@ CONFIG_GENERIC_IRQ_PROBE=y
 CONFIG_GENERIC_GPIO=y
 CONFIG_FORCE_MAX_ZONEORDER=14
 CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
 CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
 
 #
@@ -26,79 +29,100 @@ CONFIG_BROKEN_ON_SMP=y
 CONFIG_INIT_ENV_ARG_LIMIT=32
 CONFIG_LOCALVERSION=""
 CONFIG_LOCALVERSION_AUTO=y
+CONFIG_HAVE_KERNEL_GZIP=y
+CONFIG_HAVE_KERNEL_BZIP2=y
+CONFIG_HAVE_KERNEL_LZMA=y
+# CONFIG_KERNEL_GZIP is not set
+# CONFIG_KERNEL_BZIP2 is not set
+CONFIG_KERNEL_LZMA=y
 CONFIG_SYSVIPC=y
 CONFIG_SYSVIPC_SYSCTL=y
 # CONFIG_POSIX_MQUEUE is not set
 # CONFIG_BSD_PROCESS_ACCT is not set
 # CONFIG_TASKSTATS is not set
-# CONFIG_USER_NS is not set
-# CONFIG_PID_NS is not set
 # CONFIG_AUDIT is not set
+
+#
+# RCU Subsystem
+#
+CONFIG_CLASSIC_RCU=y
+# CONFIG_TREE_RCU is not set
+# CONFIG_PREEMPT_RCU is not set
+# CONFIG_TREE_RCU_TRACE is not set
+# CONFIG_PREEMPT_RCU_TRACE is not set
 CONFIG_IKCONFIG=y
 CONFIG_IKCONFIG_PROC=y
 CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_GROUP_SCHED is not set
 # CONFIG_CGROUPS is not set
-CONFIG_FAIR_GROUP_SCHED=y
-CONFIG_FAIR_USER_SCHED=y
-# CONFIG_FAIR_CGROUP_SCHED is not set
-# CONFIG_SYSFS_DEPRECATED is not set
+# CONFIG_SYSFS_DEPRECATED_V2 is not set
 # CONFIG_RELAY is not set
+# CONFIG_NAMESPACES is not set
 CONFIG_BLK_DEV_INITRD=y
 CONFIG_INITRAMFS_SOURCE=""
+# CONFIG_RD_GZIP is not set
+# CONFIG_RD_BZIP2 is not set
+CONFIG_RD_LZMA=y
 # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
-# CONFIG_SYSCTL is not set
+CONFIG_SYSCTL=y
+CONFIG_ANON_INODES=y
 CONFIG_EMBEDDED=y
-CONFIG_UID16=y
+# CONFIG_UID16 is not set
 # CONFIG_SYSCTL_SYSCALL is not set
 CONFIG_KALLSYMS=y
 # CONFIG_KALLSYMS_EXTRA_PASS is not set
+# CONFIG_STRIP_ASM_SYMS is not set
 CONFIG_HOTPLUG=y
 CONFIG_PRINTK=y
 CONFIG_BUG=y
 # CONFIG_ELF_CORE is not set
 CONFIG_BASE_FULL=y
 # CONFIG_FUTEX is not set
-CONFIG_ANON_INODES=y
 CONFIG_EPOLL=y
 CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
 CONFIG_EVENTFD=y
+CONFIG_AIO=y
 CONFIG_VM_EVENT_COUNTERS=y
-CONFIG_BIG_ORDER_ALLOC_NOFAIL_MAGIC=3
-# CONFIG_NP2 is not set
+CONFIG_COMPAT_BRK=y
 CONFIG_SLAB=y
 # CONFIG_SLUB is not set
 # CONFIG_SLOB is not set
+CONFIG_MMAP_ALLOW_UNINITIALIZED=y
+# CONFIG_PROFILING is not set
+# CONFIG_MARKERS is not set
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_SLOW_WORK is not set
+# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
 CONFIG_SLABINFO=y
-CONFIG_RT_MUTEXES=y
-CONFIG_TINY_SHMEM=y
 CONFIG_BASE_SMALL=0
 CONFIG_MODULES=y
+# CONFIG_MODULE_FORCE_LOAD is not set
 CONFIG_MODULE_UNLOAD=y
 # CONFIG_MODULE_FORCE_UNLOAD is not set
 # CONFIG_MODVERSIONS is not set
 # CONFIG_MODULE_SRCVERSION_ALL is not set
-CONFIG_KMOD=y
 CONFIG_BLOCK=y
 # CONFIG_LBD is not set
-# CONFIG_BLK_DEV_IO_TRACE is not set
-# CONFIG_LSF is not set
 # CONFIG_BLK_DEV_BSG is not set
+# CONFIG_BLK_DEV_INTEGRITY is not set
 
 #
 # IO Schedulers
 #
 CONFIG_IOSCHED_NOOP=y
-CONFIG_IOSCHED_AS=y
+# CONFIG_IOSCHED_AS is not set
 # CONFIG_IOSCHED_DEADLINE is not set
 CONFIG_IOSCHED_CFQ=y
-CONFIG_DEFAULT_AS=y
+# CONFIG_DEFAULT_AS is not set
 # CONFIG_DEFAULT_DEADLINE is not set
 # CONFIG_DEFAULT_CFQ is not set
-# CONFIG_DEFAULT_NOOP is not set
-CONFIG_DEFAULT_IOSCHED="anticipatory"
-# CONFIG_PREEMPT_NONE is not set
-CONFIG_PREEMPT_VOLUNTARY=y
+CONFIG_DEFAULT_NOOP=y
+CONFIG_DEFAULT_IOSCHED="noop"
+CONFIG_PREEMPT_NONE=y
+# CONFIG_PREEMPT_VOLUNTARY is not set
 # CONFIG_PREEMPT is not set
+# CONFIG_FREEZER is not set
 
 #
 # Blackfin Processor Options
@@ -107,6 +131,10 @@ CONFIG_PREEMPT_VOLUNTARY=y
 #
 # Processor and Board Settings
 #
+# CONFIG_BF512 is not set
+# CONFIG_BF514 is not set
+# CONFIG_BF516 is not set
+# CONFIG_BF518 is not set
 # CONFIG_BF522 is not set
 # CONFIG_BF523 is not set
 # CONFIG_BF524 is not set
@@ -119,19 +147,29 @@ CONFIG_PREEMPT_VOLUNTARY=y
 # CONFIG_BF534 is not set
 # CONFIG_BF536 is not set
 # CONFIG_BF537 is not set
+# CONFIG_BF538 is not set
+# CONFIG_BF539 is not set
 # CONFIG_BF542 is not set
+# CONFIG_BF542M is not set
 # CONFIG_BF544 is not set
+# CONFIG_BF544M is not set
 # CONFIG_BF547 is not set
-CONFIG_BF548=y
+# CONFIG_BF547M is not set
+CONFIG_BF548_std=y
+# CONFIG_BF548M is not set
 # CONFIG_BF549 is not set
+# CONFIG_BF549M is not set
 # CONFIG_BF561 is not set
+CONFIG_BF_REV_MIN=0
+CONFIG_BF_REV_MAX=2
 # CONFIG_BF_REV_0_0 is not set
 # CONFIG_BF_REV_0_1 is not set
-CONFIG_BF_REV_0_2=y
+# CONFIG_BF_REV_0_2 is not set
 # CONFIG_BF_REV_0_3 is not set
 # CONFIG_BF_REV_0_4 is not set
 # CONFIG_BF_REV_0_5 is not set
-# CONFIG_BF_REV_ANY is not set
+# CONFIG_BF_REV_0_6 is not set
+CONFIG_BF_REV_ANY=y
 # CONFIG_BF_REV_NONE is not set
 CONFIG_BF54x=y
 CONFIG_IRQ_PLL_WAKEUP=7
@@ -140,15 +178,12 @@ CONFIG_IRQ_SPORT0_RX=9
 CONFIG_IRQ_SPORT0_TX=9
 CONFIG_IRQ_SPORT1_RX=9
 CONFIG_IRQ_SPORT1_TX=9
+CONFIG_IRQ_SPI0=10
 CONFIG_IRQ_UART0_RX=10
 CONFIG_IRQ_UART0_TX=10
 CONFIG_IRQ_UART1_RX=10
 CONFIG_IRQ_UART1_TX=10
 CONFIG_IRQ_CNT=8
-CONFIG_IRQ_USB_INT0=11
-CONFIG_IRQ_USB_INT1=11
-CONFIG_IRQ_USB_INT2=11
-CONFIG_IRQ_USB_DMA=11
 CONFIG_IRQ_TIMER0=11
 CONFIG_IRQ_TIMER1=11
 CONFIG_IRQ_TIMER2=11
@@ -157,9 +192,21 @@ CONFIG_IRQ_TIMER4=11
 CONFIG_IRQ_TIMER5=11
 CONFIG_IRQ_TIMER6=11
 CONFIG_IRQ_TIMER7=11
+CONFIG_IRQ_USB_INT0=11
+CONFIG_IRQ_USB_INT1=11
+CONFIG_IRQ_USB_INT2=11
+CONFIG_IRQ_USB_DMA=11
 CONFIG_IRQ_TIMER8=11
 CONFIG_IRQ_TIMER9=11
 CONFIG_IRQ_TIMER10=11
+CONFIG_IRQ_SPORT2_RX=9
+CONFIG_IRQ_SPORT2_TX=9
+CONFIG_IRQ_SPORT3_RX=9
+CONFIG_IRQ_SPORT3_TX=9
+CONFIG_IRQ_SPI1=10
+CONFIG_IRQ_SPI2=10
+CONFIG_IRQ_TWI0=11
+CONFIG_IRQ_TWI1=11
 # CONFIG_BFIN548_EZKIT is not set
 CONFIG_BFIN548_BLUETECHNIX_CM=y
 
@@ -167,6 +214,7 @@ CONFIG_BFIN548_BLUETECHNIX_CM=y
 # BF548 Specific Configuration
 #
 # CONFIG_DEB_DMA_URGENT is not set
+# CONFIG_BF548_ATAPI_ALTERNATIVE_PORT is not set
 
 #
 # Interrupt Priority Assignment
@@ -182,7 +230,6 @@ CONFIG_IRQ_SPORT1_ERR=7
 CONFIG_IRQ_SPI0_ERR=7
 CONFIG_IRQ_UART0_ERR=7
 CONFIG_IRQ_EPPI0=8
-CONFIG_IRQ_SPI0=10
 CONFIG_IRQ_PINT0=12
 CONFIG_IRQ_PINT1=12
 CONFIG_IRQ_MDMAS0=13
@@ -197,18 +244,10 @@ CONFIG_IRQ_SPI2_ERR=7
 CONFIG_IRQ_UART1_ERR=7
 CONFIG_IRQ_UART2_ERR=7
 CONFIG_IRQ_CAN0_ERR=7
-CONFIG_IRQ_SPORT2_RX=9
-CONFIG_IRQ_SPORT2_TX=9
-CONFIG_IRQ_SPORT3_RX=9
-CONFIG_IRQ_SPORT3_TX=9
 CONFIG_IRQ_EPPI1=9
 CONFIG_IRQ_EPPI2=9
-CONFIG_IRQ_SPI1=10
-CONFIG_IRQ_SPI2=10
 CONFIG_IRQ_ATAPI_RX=10
 CONFIG_IRQ_ATAPI_TX=10
-CONFIG_IRQ_TWI0=11
-CONFIG_IRQ_TWI1=11
 CONFIG_IRQ_CAN0_RX=11
 CONFIG_IRQ_CAN0_TX=11
 CONFIG_IRQ_MDMAS2=13
@@ -255,6 +294,7 @@ CONFIG_PINT3_ASSIGN=0x02020303
 # Board customizations
 #
 # CONFIG_CMDLINE_BOOL is not set
+CONFIG_BOOT_LOAD=0x1000
 
 #
 # Clock/PLL Setup
@@ -274,16 +314,12 @@ CONFIG_HZ_250=y
 # CONFIG_HZ_300 is not set
 # CONFIG_HZ_1000 is not set
 CONFIG_HZ=250
+# CONFIG_SCHED_HRTICK is not set
 # CONFIG_GENERIC_TIME is not set
-# CONFIG_TICK_ONESHOT is not set
 
 #
-# Memory Setup
+# Misc
 #
-CONFIG_MAX_MEM_SIZE=64
-# CONFIG_MEM_MT46V32M16_6T is not set
-CONFIG_MEM_MT46V32M16_5B=y
-CONFIG_BOOT_LOAD=0x1000
 CONFIG_BFIN_SCRATCH_REG_RETN=y
 # CONFIG_BFIN_SCRATCH_REG_RETE is not set
 # CONFIG_BFIN_SCRATCH_REG_CYCLES is not set
@@ -310,6 +346,12 @@ CONFIG_ACCESS_OK_L1=y
 CONFIG_CACHELINE_ALIGNED_L1=y
 # CONFIG_SYSCALL_TAB_L1 is not set
 # CONFIG_CPLB_SWITCH_TAB_L1 is not set
+CONFIG_APP_STACK_L1=y
+
+#
+# Speed Optimizations
+#
+CONFIG_BFIN_INS_LOWOVERHEAD=y
 CONFIG_RAMKERNEL=y
 # CONFIG_ROMKERNEL is not set
 CONFIG_SELECT_MEMORY_MODEL=y
@@ -318,13 +360,16 @@ CONFIG_FLATMEM_MANUAL=y
 # CONFIG_SPARSEMEM_MANUAL is not set
 CONFIG_FLATMEM=y
 CONFIG_FLAT_NODE_MEM_MAP=y
-# CONFIG_SPARSEMEM_STATIC is not set
-# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
+CONFIG_PAGEFLAGS_EXTENDED=y
 CONFIG_SPLIT_PTLOCK_CPUS=4
-# CONFIG_RESOURCES_64BIT is not set
+# CONFIG_PHYS_ADDR_T_64BIT is not set
 CONFIG_ZONE_DMA_FLAG=1
 CONFIG_VIRT_TO_BUS=y
+CONFIG_UNEVICTABLE_LRU=y
+CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
+CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0
 # CONFIG_BFIN_GPTIMERS is not set
+# CONFIG_DMA_UNCACHED_4M is not set
 # CONFIG_DMA_UNCACHED_2M is not set
 CONFIG_DMA_UNCACHED_1M=y
 # CONFIG_DMA_UNCACHED_NONE is not set
@@ -333,14 +378,13 @@ CONFIG_DMA_UNCACHED_1M=y
 # Cache Support
 #
 CONFIG_BFIN_ICACHE=y
-# CONFIG_BFIN_ICACHE_LOCK is not set
+CONFIG_BFIN_EXTMEM_ICACHEABLE=y
+# CONFIG_BFIN_L2_ICACHEABLE is not set
 CONFIG_BFIN_DCACHE=y
 # CONFIG_BFIN_DCACHE_BANKA is not set
-CONFIG_BFIN_EXTMEM_ICACHEABLE=y
 CONFIG_BFIN_EXTMEM_DCACHEABLE=y
-CONFIG_BFIN_EXTMEM_WRITEBACK=y
-# CONFIG_BFIN_EXTMEM_WRITETHROUGH is not set
-# CONFIG_BFIN_L2_ICACHEABLE is not set
+# CONFIG_BFIN_EXTMEM_WRITEBACK
+CONFIG_BFIN_EXTMEM_WRITETHROUGH=y
 # CONFIG_BFIN_L2_DCACHEABLE is not set
 
 #
@@ -349,7 +393,7 @@ CONFIG_BFIN_EXTMEM_WRITEBACK=y
 # CONFIG_MPU is not set
 
 #
-# Asynchonous Memory Configuration
+# Asynchronous Memory Configuration
 #
 
 #
@@ -369,7 +413,7 @@ CONFIG_C_AMBEN_ALL=y
 CONFIG_BANK_0=0x7BB0
 CONFIG_BANK_1=0x5554
 CONFIG_BANK_2=0x7BB0
-CONFIG_BANK_3=0x99B2
+CONFIG_BANK_3=0x99B3
 CONFIG_EBIU_MBSCTLVAL=0x0
 CONFIG_EBIU_MODEVAL=0x1
 CONFIG_EBIU_FCTLVAL=0x6
@@ -377,7 +421,6 @@ CONFIG_EBIU_FCTLVAL=0x6
 #
 # Bus options (PCI, PCMCIA, EISA, MCA, ISA)
 #
-# CONFIG_PCI is not set
 # CONFIG_ARCH_SUPPORTS_MSI is not set
 # CONFIG_PCCARD is not set
 
@@ -388,23 +431,19 @@ CONFIG_BINFMT_ELF_FDPIC=y
 CONFIG_BINFMT_FLAT=y
 CONFIG_BINFMT_ZFLAT=y
 # CONFIG_BINFMT_SHARED_FLAT is not set
+# CONFIG_HAVE_AOUT is not set
 # CONFIG_BINFMT_MISC is not set
 
 #
 # Power management options
 #
 # CONFIG_PM is not set
-CONFIG_SUSPEND_UP_POSSIBLE=y
-# CONFIG_PM_WAKEUP_BY_GPIO is not set
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
 
 #
 # CPU Frequency scaling
 #
 # CONFIG_CPU_FREQ is not set
-
-#
-# Networking
-#
 CONFIG_NET=y
 
 #
@@ -417,6 +456,7 @@ CONFIG_XFRM=y
 # CONFIG_XFRM_USER is not set
 # CONFIG_XFRM_SUB_POLICY is not set
 # CONFIG_XFRM_MIGRATE is not set
+# CONFIG_XFRM_STATISTICS is not set
 # CONFIG_NET_KEY is not set
 CONFIG_INET=y
 # CONFIG_IP_MULTICAST is not set
@@ -435,19 +475,16 @@ CONFIG_IP_PNP=y
 # CONFIG_INET_IPCOMP is not set
 # CONFIG_INET_XFRM_TUNNEL is not set
 # CONFIG_INET_TUNNEL is not set
-# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
-# CONFIG_INET_XFRM_MODE_TUNNEL is not set
-# CONFIG_INET_XFRM_MODE_BEET is not set
+CONFIG_INET_XFRM_MODE_TRANSPORT=m
+CONFIG_INET_XFRM_MODE_TUNNEL=m
+CONFIG_INET_XFRM_MODE_BEET=m
 # CONFIG_INET_LRO is not set
 # CONFIG_INET_DIAG is not set
-CONFIG_INET_TCP_DIAG=y
 # CONFIG_TCP_CONG_ADVANCED is not set
 CONFIG_TCP_CONG_CUBIC=y
 CONFIG_DEFAULT_TCP_CONG="cubic"
 # CONFIG_TCP_MD5SIG is not set
 # CONFIG_IPV6 is not set
-# CONFIG_INET6_XFRM_TUNNEL is not set
-# CONFIG_INET6_TUNNEL is not set
 # CONFIG_NETLABEL is not set
 # CONFIG_NETWORK_SECMARK is not set
 # CONFIG_NETFILTER is not set
@@ -456,6 +493,7 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
 # CONFIG_TIPC is not set
 # CONFIG_ATM is not set
 # CONFIG_BRIDGE is not set
+# CONFIG_NET_DSA is not set
 # CONFIG_VLAN_8021Q is not set
 # CONFIG_DECNET is not set
 # CONFIG_LLC2 is not set
@@ -465,24 +503,21 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
 # CONFIG_LAPB is not set
 # CONFIG_ECONET is not set
 # CONFIG_WAN_ROUTER is not set
+# CONFIG_PHONET is not set
 # CONFIG_NET_SCHED is not set
+# CONFIG_DCB is not set
 
 #
 # Network testing
 #
 # CONFIG_NET_PKTGEN is not set
 # CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
 # CONFIG_IRDA is not set
 # CONFIG_BT is not set
 # CONFIG_AF_RXRPC is not set
-
-#
-# Wireless
-#
-# CONFIG_CFG80211 is not set
-# CONFIG_WIRELESS_EXT is not set
-# CONFIG_MAC80211 is not set
-# CONFIG_IEEE80211 is not set
+# CONFIG_WIRELESS is not set
+# CONFIG_WIMAX is not set
 # CONFIG_RFKILL is not set
 # CONFIG_NET_9P is not set
 
@@ -501,10 +536,12 @@ CONFIG_PREVENT_FIRMWARE_BUILD=y
 # CONFIG_CONNECTOR is not set
 CONFIG_MTD=y
 # CONFIG_MTD_DEBUG is not set
+# CONFIG_MTD_TESTS is not set
 # CONFIG_MTD_CONCAT is not set
 CONFIG_MTD_PARTITIONS=y
 # CONFIG_MTD_REDBOOT_PARTS is not set
 CONFIG_MTD_CMDLINE_PARTS=y
+# CONFIG_MTD_AR7_PARTS is not set
 
 #
 # User Modules And Translation Layers
@@ -539,6 +576,7 @@ CONFIG_MTD_CFI_I2=y
 CONFIG_MTD_CFI_INTELEXT=y
 # CONFIG_MTD_CFI_AMDSTD is not set
 # CONFIG_MTD_CFI_STAA is not set
+# CONFIG_MTD_PSD4256G is not set
 CONFIG_MTD_CFI_UTIL=y
 CONFIG_MTD_RAM=y
 # CONFIG_MTD_ROM is not set
@@ -549,9 +587,8 @@ CONFIG_MTD_RAM=y
 #
 CONFIG_MTD_COMPLEX_MAPPINGS=y
 CONFIG_MTD_PHYSMAP=y
-CONFIG_MTD_PHYSMAP_START=0x20000000
-CONFIG_MTD_PHYSMAP_LEN=0
-CONFIG_MTD_PHYSMAP_BANKWIDTH=2
+# CONFIG_MTD_PHYSMAP_COMPAT is not set
+# CONFIG_MTD_GPIO_ADDR is not set
 # CONFIG_MTD_UCLINUX is not set
 # CONFIG_MTD_PLATRAM is not set
 
@@ -575,6 +612,11 @@ CONFIG_MTD_PHYSMAP_BANKWIDTH=2
 # CONFIG_MTD_ONENAND is not set
 
 #
+# LPDDR flash memory drivers
+#
+# CONFIG_MTD_LPDDR is not set
+
+#
 # UBI - Unsorted block images
 #
 # CONFIG_MTD_UBI is not set
@@ -587,31 +629,31 @@ CONFIG_BLK_DEV=y
 CONFIG_BLK_DEV_RAM=y
 CONFIG_BLK_DEV_RAM_COUNT=16
 CONFIG_BLK_DEV_RAM_SIZE=4096
-CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
+# CONFIG_BLK_DEV_XIP is not set
 # CONFIG_CDROM_PKTCDVD is not set
 # CONFIG_ATA_OVER_ETH is not set
-CONFIG_MISC_DEVICES=y
-# CONFIG_EEPROM_93CX6 is not set
+# CONFIG_BLK_DEV_HD is not set
+# CONFIG_MISC_DEVICES is not set
+CONFIG_HAVE_IDE=y
 # CONFIG_IDE is not set
 
 #
 # SCSI device support
 #
 # CONFIG_RAID_ATTRS is not set
-CONFIG_SCSI=y
+CONFIG_SCSI=m
 CONFIG_SCSI_DMA=y
 # CONFIG_SCSI_TGT is not set
 # CONFIG_SCSI_NETLINK is not set
-# CONFIG_SCSI_PROC_FS is not set
+CONFIG_SCSI_PROC_FS=y
 
 #
 # SCSI support type (disk, tape, CD-ROM)
 #
-CONFIG_BLK_DEV_SD=y
+CONFIG_BLK_DEV_SD=m
 # CONFIG_CHR_DEV_ST is not set
 # CONFIG_CHR_DEV_OSST is not set
-CONFIG_BLK_DEV_SR=y
-# CONFIG_BLK_DEV_SR_VENDOR is not set
+# CONFIG_BLK_DEV_SR is not set
 # CONFIG_CHR_DEV_SG is not set
 # CONFIG_CHR_DEV_SCH is not set
 
@@ -632,29 +674,54 @@ CONFIG_SCSI_WAIT_SCAN=m
 # CONFIG_SCSI_ISCSI_ATTRS is not set
 # CONFIG_SCSI_SAS_LIBSAS is not set
 # CONFIG_SCSI_SRP_ATTRS is not set
-CONFIG_SCSI_LOWLEVEL=y
-# CONFIG_ISCSI_TCP is not set
-# CONFIG_SCSI_DEBUG is not set
+# CONFIG_SCSI_LOWLEVEL is not set
+# CONFIG_SCSI_DH is not set
+# CONFIG_SCSI_OSD_INITIATOR is not set
 # CONFIG_ATA is not set
 # CONFIG_MD is not set
 CONFIG_NETDEVICES=y
-# CONFIG_NETDEVICES_MULTIQUEUE is not set
+CONFIG_COMPAT_NET_DEV_OPS=y
 # CONFIG_DUMMY is not set
 # CONFIG_BONDING is not set
 # CONFIG_MACVLAN is not set
 # CONFIG_EQUALIZER is not set
 # CONFIG_TUN is not set
 # CONFIG_VETH is not set
-# CONFIG_PHYLIB is not set
+CONFIG_PHYLIB=y
+
+#
+# MII PHY device drivers
+#
+# CONFIG_MARVELL_PHY is not set
+# CONFIG_DAVICOM_PHY is not set
+# CONFIG_QSEMI_PHY is not set
+# CONFIG_LXT_PHY is not set
+# CONFIG_CICADA_PHY is not set
+# CONFIG_VITESSE_PHY is not set
+# CONFIG_SMSC_PHY is not set
+# CONFIG_BROADCOM_PHY is not set
+# CONFIG_ICPLUS_PHY is not set
+# CONFIG_REALTEK_PHY is not set
+# CONFIG_NATIONAL_PHY is not set
+# CONFIG_STE10XP is not set
+# CONFIG_LSI_ET1011C_PHY is not set
+# CONFIG_FIXED_PHY is not set
+# CONFIG_MDIO_BITBANG is not set
 CONFIG_NET_ETHERNET=y
 CONFIG_MII=y
 # CONFIG_SMC91X is not set
-CONFIG_SMSC911X=y
 # CONFIG_DM9000 is not set
+# CONFIG_ENC28J60 is not set
+# CONFIG_ETHOC is not set
+CONFIG_SMSC911X=y
+# CONFIG_DNET is not set
 # CONFIG_IBM_NEW_EMAC_ZMII is not set
 # CONFIG_IBM_NEW_EMAC_RGMII is not set
 # CONFIG_IBM_NEW_EMAC_TAH is not set
 # CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
+# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
+# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
 # CONFIG_B44 is not set
 # CONFIG_NETDEV_1000 is not set
 # CONFIG_NETDEV_10000 is not set
@@ -666,6 +733,10 @@ CONFIG_SMSC911X=y
 # CONFIG_WLAN_80211 is not set
 
 #
+# Enable WiMAX (Networking options) to see the WiMAX drivers
+#
+
+#
 # USB Network Adapters
 #
 # CONFIG_USB_CATC is not set
@@ -676,7 +747,6 @@ CONFIG_SMSC911X=y
 # CONFIG_WAN is not set
 # CONFIG_PPP is not set
 # CONFIG_SLIP is not set
-# CONFIG_SHAPER is not set
 # CONFIG_NETCONSOLE is not set
 # CONFIG_NETPOLL is not set
 # CONFIG_NET_POLL_CONTROLLER is not set
@@ -711,6 +781,7 @@ CONFIG_INPUT_KEYBOARD=y
 # CONFIG_KEYBOARD_GPIO is not set
 # CONFIG_KEYBOARD_BFIN is not set
 # CONFIG_KEYBOARD_OPENCORES is not set
+# CONFIG_KEYBOARD_ADP5588 is not set
 # CONFIG_INPUT_MOUSE is not set
 # CONFIG_INPUT_JOYSTICK is not set
 # CONFIG_INPUT_TABLET is not set
@@ -726,19 +797,16 @@ CONFIG_INPUT_KEYBOARD=y
 #
 # Character devices
 #
-# CONFIG_AD9960 is not set
-# CONFIG_SPI_ADC_BF533 is not set
-# CONFIG_BF5xx_PPIFCD is not set
+CONFIG_BFIN_DMA_INTERFACE=m
+# CONFIG_BFIN_PPI is not set
+# CONFIG_BFIN_PPIFCD is not set
 # CONFIG_BFIN_SIMPLE_TIMER is not set
-# CONFIG_BF5xx_PPI is not set
-CONFIG_BFIN_OTP=y
-# CONFIG_BFIN_OTP_WRITE_ENABLE is not set
+# CONFIG_BFIN_SPI_ADC is not set
 # CONFIG_BFIN_SPORT is not set
-# CONFIG_BFIN_TIMER_LATENCY is not set
-# CONFIG_TWI_LCD is not set
-# CONFIG_SIMPLE_GPIO is not set
+# CONFIG_BFIN_TWI_LCD is not set
 # CONFIG_VT is not set
-# CONFIG_DEVKMEM is not set
+CONFIG_DEVKMEM=y
+# CONFIG_BFIN_JTAG_COMM is not set
 # CONFIG_SERIAL_NONSTANDARD is not set
 
 #
@@ -749,10 +817,11 @@ CONFIG_BFIN_OTP=y
 #
 # Non-8250 serial port support
 #
+# CONFIG_SERIAL_MAX3100 is not set
 CONFIG_SERIAL_BFIN=y
 CONFIG_SERIAL_BFIN_CONSOLE=y
-CONFIG_SERIAL_BFIN_DMA=y
-# CONFIG_SERIAL_BFIN_PIO is not set
+# CONFIG_SERIAL_BFIN_DMA is not set
+CONFIG_SERIAL_BFIN_PIO=y
 # CONFIG_SERIAL_BFIN_UART0 is not set
 CONFIG_SERIAL_BFIN_UART1=y
 # CONFIG_BFIN_UART1_CTSRTS is not set
@@ -762,7 +831,10 @@ CONFIG_SERIAL_CORE=y
 CONFIG_SERIAL_CORE_CONSOLE=y
 # CONFIG_SERIAL_BFIN_SPORT is not set
 CONFIG_UNIX98_PTYS=y
+# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
 # CONFIG_LEGACY_PTYS is not set
+CONFIG_BFIN_OTP=y
+# CONFIG_BFIN_OTP_WRITE_ENABLE is not set
 
 #
 # CAN, the car bus and industrial fieldbus
@@ -770,61 +842,53 @@ CONFIG_UNIX98_PTYS=y
 # CONFIG_CAN4LINUX is not set
 # CONFIG_IPMI_HANDLER is not set
 # CONFIG_HW_RANDOM is not set
-# CONFIG_GEN_RTC is not set
 # CONFIG_R3964 is not set
 # CONFIG_RAW_DRIVER is not set
 # CONFIG_TCG_TPM is not set
 CONFIG_I2C=y
 CONFIG_I2C_BOARDINFO=y
 CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_HELPER_AUTO=y
 
 #
-# I2C Algorithms
+# I2C Hardware Bus support
 #
-# CONFIG_I2C_ALGOBIT is not set
-# CONFIG_I2C_ALGOPCF is not set
-# CONFIG_I2C_ALGOPCA is not set
 
 #
-# I2C Hardware Bus support
+# I2C system bus drivers (mostly embedded / system-on-chip)
 #
 CONFIG_I2C_BLACKFIN_TWI=y
-CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=100
+CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=50
 # CONFIG_I2C_GPIO is not set
 # CONFIG_I2C_OCORES is not set
-# CONFIG_I2C_PARPORT_LIGHT is not set
 # CONFIG_I2C_SIMTEC is not set
+
+#
+# External I2C/SMBus adapter drivers
+#
+# CONFIG_I2C_PARPORT_LIGHT is not set
 # CONFIG_I2C_TAOS_EVM is not set
-# CONFIG_I2C_STUB is not set
 # CONFIG_I2C_TINY_USB is not set
 
 #
+# Other I2C/SMBus bus drivers
+#
+# CONFIG_I2C_PCA_PLATFORM is not set
+# CONFIG_I2C_STUB is not set
+
+#
 # Miscellaneous I2C Chip support
 #
-# CONFIG_SENSORS_DS1337 is not set
-# CONFIG_SENSORS_DS1374 is not set
 # CONFIG_DS1682 is not set
-# CONFIG_SENSORS_AD5252 is not set
-# CONFIG_EEPROM_LEGACY is not set
 # CONFIG_SENSORS_PCF8574 is not set
-# CONFIG_SENSORS_PCF8575 is not set
-# CONFIG_SENSORS_PCA9543 is not set
+# CONFIG_PCF8575 is not set
 # CONFIG_SENSORS_PCA9539 is not set
-# CONFIG_SENSORS_PCF8591 is not set
 # CONFIG_SENSORS_MAX6875 is not set
 # CONFIG_SENSORS_TSL2550 is not set
 # CONFIG_I2C_DEBUG_CORE is not set
 # CONFIG_I2C_DEBUG_ALGO is not set
 # CONFIG_I2C_DEBUG_BUS is not set
 # CONFIG_I2C_DEBUG_CHIP is not set
-
-CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
-CONFIG_GPIOLIB=y
-CONFIG_GPIO_SYSFS=y
-
-#
-# SPI support
-#
 CONFIG_SPI=y
 CONFIG_SPI_MASTER=y
 
@@ -832,64 +896,23 @@ CONFIG_SPI_MASTER=y
 # SPI Master Controller Drivers
 #
 CONFIG_SPI_BFIN=y
+# CONFIG_SPI_BFIN_LOCK is not set
+# CONFIG_SPI_BFIN_SPORT is not set
 # CONFIG_SPI_BITBANG is not set
+# CONFIG_SPI_GPIO is not set
 
 #
 # SPI Protocol Masters
 #
-# CONFIG_EEPROM_AT25 is not set
 # CONFIG_SPI_SPIDEV is not set
 # CONFIG_SPI_TLE62X0 is not set
+CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
+# CONFIG_GPIOLIB is not set
 # CONFIG_W1 is not set
 # CONFIG_POWER_SUPPLY is not set
-CONFIG_HWMON=y
-# CONFIG_HWMON_VID is not set
-# CONFIG_SENSORS_AD7418 is not set
-# CONFIG_SENSORS_ADM1021 is not set
-# CONFIG_SENSORS_ADM1025 is not set
-# CONFIG_SENSORS_ADM1026 is not set
-# CONFIG_SENSORS_ADM1029 is not set
-# CONFIG_SENSORS_ADM1031 is not set
-# CONFIG_SENSORS_ADM9240 is not set
-# CONFIG_SENSORS_ADT7470 is not set
-# CONFIG_SENSORS_ATXP1 is not set
-# CONFIG_SENSORS_DS1621 is not set
-# CONFIG_SENSORS_F71805F is not set
-# CONFIG_SENSORS_F71882FG is not set
-# CONFIG_SENSORS_F75375S is not set
-# CONFIG_SENSORS_GL518SM is not set
-# CONFIG_SENSORS_GL520SM is not set
-# CONFIG_SENSORS_IT87 is not set
-# CONFIG_SENSORS_LM63 is not set
-# CONFIG_SENSORS_LM70 is not set
-# CONFIG_SENSORS_LM75 is not set
-# CONFIG_SENSORS_LM77 is not set
-# CONFIG_SENSORS_LM78 is not set
-# CONFIG_SENSORS_LM80 is not set
-# CONFIG_SENSORS_LM83 is not set
-# CONFIG_SENSORS_LM85 is not set
-# CONFIG_SENSORS_LM87 is not set
-# CONFIG_SENSORS_LM90 is not set
-# CONFIG_SENSORS_LM92 is not set
-# CONFIG_SENSORS_LM93 is not set
-# CONFIG_SENSORS_MAX1619 is not set
-# CONFIG_SENSORS_MAX6650 is not set
-# CONFIG_SENSORS_PC87360 is not set
-# CONFIG_SENSORS_PC87427 is not set
-# CONFIG_SENSORS_DME1737 is not set
-# CONFIG_SENSORS_SMSC47M1 is not set
-# CONFIG_SENSORS_SMSC47M192 is not set
-# CONFIG_SENSORS_SMSC47B397 is not set
-# CONFIG_SENSORS_THMC50 is not set
-# CONFIG_SENSORS_VT1211 is not set
-# CONFIG_SENSORS_W83781D is not set
-# CONFIG_SENSORS_W83791D is not set
-# CONFIG_SENSORS_W83792D is not set
-# CONFIG_SENSORS_W83793 is not set
-# CONFIG_SENSORS_W83L785TS is not set
-# CONFIG_SENSORS_W83627HF is not set
-# CONFIG_SENSORS_W83627EHF is not set
-# CONFIG_HWMON_DEBUG_CHIP is not set
+# CONFIG_HWMON is not set
+# CONFIG_THERMAL is not set
+# CONFIG_THERMAL_HWMON is not set
 CONFIG_WATCHDOG=y
 # CONFIG_WATCHDOG_NOWAYOUT is not set
 
@@ -903,25 +926,43 @@ CONFIG_BFIN_WDT=y
 # USB-based Watchdog Cards
 #
 # CONFIG_USBPCWATCHDOG is not set
+CONFIG_SSB_POSSIBLE=y
 
 #
 # Sonics Silicon Backplane
 #
-CONFIG_SSB_POSSIBLE=y
 # CONFIG_SSB is not set
 
 #
 # Multifunction device drivers
 #
+# CONFIG_MFD_CORE is not set
 # CONFIG_MFD_SM501 is not set
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_TWL4030_CORE is not set
+# CONFIG_MFD_TMIO is not set
+# CONFIG_PMIC_DA903X is not set
+# CONFIG_PMIC_ADP5520 is not set
+# CONFIG_MFD_WM8400 is not set
+# CONFIG_MFD_WM8350_I2C is not set
+# CONFIG_MFD_PCF50633 is not set
+# CONFIG_REGULATOR is not set
 
 #
 # Multimedia devices
 #
+
+#
+# Multimedia core support
+#
 # CONFIG_VIDEO_DEV is not set
 # CONFIG_DVB_CORE is not set
+# CONFIG_VIDEO_MEDIA is not set
+
+#
+# Multimedia drivers
+#
 # CONFIG_DAB is not set
-# CONFIG_USB_DABUSB is not set
 
 #
 # Graphics support
@@ -935,80 +976,75 @@ CONFIG_SSB_POSSIBLE=y
 # Display device support
 #
 # CONFIG_DISPLAY_SUPPORT is not set
-
-#
-# Sound
-#
 # CONFIG_SOUND is not set
-CONFIG_HID_SUPPORT=y
-CONFIG_HID=y
-# CONFIG_HID_DEBUG is not set
-# CONFIG_HIDRAW is not set
-
-#
-# USB Input Devices
-#
-CONFIG_USB_HID=y
-# CONFIG_USB_HIDINPUT_POWERBOOK is not set
-# CONFIG_HID_FF is not set
-# CONFIG_USB_HIDDEV is not set
+# CONFIG_HID_SUPPORT is not set
 CONFIG_USB_SUPPORT=y
 CONFIG_USB_ARCH_HAS_HCD=y
 # CONFIG_USB_ARCH_HAS_OHCI is not set
 # CONFIG_USB_ARCH_HAS_EHCI is not set
-CONFIG_USB=y
+CONFIG_USB=m
 # CONFIG_USB_DEBUG is not set
+# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
 
 #
 # Miscellaneous USB options
 #
-# CONFIG_USB_DEVICEFS is not set
-CONFIG_USB_DEVICE_CLASS=y
+CONFIG_USB_DEVICEFS=y
+# CONFIG_USB_DEVICE_CLASS is not set
 # CONFIG_USB_DYNAMIC_MINORS is not set
 # CONFIG_USB_OTG is not set
+# CONFIG_USB_OTG_WHITELIST is not set
+# CONFIG_USB_OTG_BLACKLIST_HUB is not set
+CONFIG_USB_MON=m
+# CONFIG_USB_WUSB is not set
+# CONFIG_USB_WUSB_CBAF is not set
 
 #
 # USB Host Controller Drivers
 #
+# CONFIG_USB_C67X00_HCD is not set
+# CONFIG_USB_OXU210HP_HCD is not set
 # CONFIG_USB_ISP116X_HCD is not set
-# CONFIG_USB_ISP1362_HCD is not set
 # CONFIG_USB_ISP1760_HCD is not set
+# CONFIG_USB_ISP1362_HCD is not set
 # CONFIG_USB_SL811_HCD is not set
 # CONFIG_USB_R8A66597_HCD is not set
-CONFIG_USB_MUSB_HDRC=y
+# CONFIG_USB_HWA_HCD is not set
+CONFIG_USB_MUSB_HDRC=m
 CONFIG_USB_MUSB_SOC=y
 
 #
-# Blackfin BF54x, BF525 and BF527 high speed USB support
+# Blackfin high speed USB Support
 #
-CONFIG_USB_MUSB_HOST=y
-# CONFIG_USB_MUSB_PERIPHERAL is not set
+# CONFIG_USB_MUSB_HOST is not set
+CONFIG_USB_MUSB_PERIPHERAL=y
 # CONFIG_USB_MUSB_OTG is not set
-CONFIG_USB_MUSB_HDRC_HCD=y
+CONFIG_USB_GADGET_MUSB_HDRC=y
 # CONFIG_MUSB_PIO_ONLY is not set
-# CONFIG_USB_INVENTRA_DMA is not set
+CONFIG_USB_INVENTRA_DMA=y
 # CONFIG_USB_TI_CPPI_DMA is not set
-CONFIG_USB_MUSB_LOGLEVEL=0
+# CONFIG_USB_MUSB_DEBUG is not set
 
 #
 # USB Device Class drivers
 #
 # CONFIG_USB_ACM is not set
 # CONFIG_USB_PRINTER is not set
+# CONFIG_USB_WDM is not set
+# CONFIG_USB_TMC is not set
 
 #
-# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
+# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
 #
 
 #
-# may also be needed; see USB_STORAGE Help for more information
+# also be needed; see USB_STORAGE Help for more info
 #
-CONFIG_USB_STORAGE=y
+CONFIG_USB_STORAGE=m
 # CONFIG_USB_STORAGE_DEBUG is not set
 # CONFIG_USB_STORAGE_DATAFAB is not set
 # CONFIG_USB_STORAGE_FREECOM is not set
 # CONFIG_USB_STORAGE_ISD200 is not set
-# CONFIG_USB_STORAGE_DPCM is not set
 # CONFIG_USB_STORAGE_USBAT is not set
 # CONFIG_USB_STORAGE_SDDR09 is not set
 # CONFIG_USB_STORAGE_SDDR55 is not set
@@ -1016,6 +1052,7 @@ CONFIG_USB_STORAGE=y
 # CONFIG_USB_STORAGE_ALAUDA is not set
 # CONFIG_USB_STORAGE_ONETOUCH is not set
 # CONFIG_USB_STORAGE_KARMA is not set
+# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
 # CONFIG_USB_LIBUSUAL is not set
 
 #
@@ -1023,15 +1060,10 @@ CONFIG_USB_STORAGE=y
 #
 # CONFIG_USB_MDC800 is not set
 # CONFIG_USB_MICROTEK is not set
-CONFIG_USB_MON=y
 
 #
 # USB port drivers
 #
-
-#
-# USB Serial Converter support
-#
 # CONFIG_USB_SERIAL is not set
 
 #
@@ -1040,7 +1072,7 @@ CONFIG_USB_MON=y
 # CONFIG_USB_EMI62 is not set
 # CONFIG_USB_EMI26 is not set
 # CONFIG_USB_ADUTUX is not set
-# CONFIG_USB_AUERSWALD is not set
+# CONFIG_USB_SEVSEG is not set
 # CONFIG_USB_RIO500 is not set
 # CONFIG_USB_LEGOTOWER is not set
 # CONFIG_USB_LCD is not set
@@ -1048,7 +1080,6 @@ CONFIG_USB_MON=y
 # CONFIG_USB_LED is not set
 # CONFIG_USB_CYPRESS_CY7C63 is not set
 # CONFIG_USB_CYTHERM is not set
-# CONFIG_USB_PHIDGET is not set
 # CONFIG_USB_IDMOUSE is not set
 # CONFIG_USB_FTDI_ELAN is not set
 # CONFIG_USB_APPLEDISPLAY is not set
@@ -1056,38 +1087,75 @@ CONFIG_USB_MON=y
 # CONFIG_USB_LD is not set
 # CONFIG_USB_TRANCEVIBRATOR is not set
 # CONFIG_USB_IOWARRIOR is not set
-
-#
-# USB DSL modem support
-#
-
-#
-# USB Gadget Support
-#
-# CONFIG_USB_GADGET is not set
-CONFIG_MMC=y
+# CONFIG_USB_TEST is not set
+# CONFIG_USB_ISIGHTFW is not set
+# CONFIG_USB_VST is not set
+CONFIG_USB_GADGET=m
+# CONFIG_USB_GADGET_DEBUG_FILES is not set
+# CONFIG_USB_GADGET_DEBUG_FS is not set
+CONFIG_USB_GADGET_VBUS_DRAW=2
+CONFIG_USB_GADGET_SELECTED=y
+# CONFIG_USB_GADGET_AT91 is not set
+# CONFIG_USB_GADGET_ATMEL_USBA is not set
+# CONFIG_USB_GADGET_FSL_USB2 is not set
+# CONFIG_USB_GADGET_LH7A40X is not set
+# CONFIG_USB_GADGET_OMAP is not set
+# CONFIG_USB_GADGET_PXA25X is not set
+# CONFIG_USB_GADGET_PXA27X is not set
+# CONFIG_USB_GADGET_S3C2410 is not set
+# CONFIG_USB_GADGET_IMX is not set
+# CONFIG_USB_GADGET_M66592 is not set
+# CONFIG_USB_GADGET_AMD5536UDC is not set
+# CONFIG_USB_GADGET_FSL_QE is not set
+# CONFIG_USB_GADGET_CI13XXX is not set
+# CONFIG_USB_GADGET_NET2272 is not set
+# CONFIG_USB_GADGET_NET2280 is not set
+# CONFIG_USB_GADGET_GOKU is not set
+# CONFIG_USB_GADGET_DUMMY_HCD is not set
+CONFIG_USB_GADGET_DUALSPEED=y
+CONFIG_USB_ZERO=m
+# CONFIG_USB_AUDIO is not set
+CONFIG_USB_ETH=m
+# CONFIG_USB_ETH_RNDIS is not set
+CONFIG_USB_GADGETFS=m
+CONFIG_USB_FILE_STORAGE=m
+# CONFIG_USB_FILE_STORAGE_TEST is not set
+CONFIG_USB_G_SERIAL=m
+# CONFIG_USB_MIDI_GADGET is not set
+CONFIG_USB_G_PRINTER=m
+# CONFIG_USB_CDC_COMPOSITE is not set
+
+#
+# OTG and related infrastructure
+#
+CONFIG_USB_OTG_UTILS=y
+# CONFIG_USB_GPIO_VBUS is not set
+# CONFIG_NOP_USB_XCEIV is not set
+CONFIG_MMC=m
 # CONFIG_MMC_DEBUG is not set
 # CONFIG_MMC_UNSAFE_RESUME is not set
 
 #
-# MMC/SD Card Drivers
+# MMC/SD/SDIO Card Drivers
 #
-CONFIG_MMC_BLOCK=y
+CONFIG_MMC_BLOCK=m
 CONFIG_MMC_BLOCK_BOUNCE=y
 # CONFIG_SDIO_UART is not set
+# CONFIG_MMC_TEST is not set
 
 #
-# MMC/SD Host Controller Drivers
+# MMC/SD/SDIO Host Controller Drivers
 #
-CONFIG_SDH_BFIN=y
+# CONFIG_MMC_SDHCI is not set
+CONFIG_SDH_BFIN=m
+# CONFIG_SDH_BFIN_MISSING_CMD_PULLUP_WORKAROUND is not set
+# CONFIG_SDH_BFIN_ENABLE_SDIO_IRQ is not set
 # CONFIG_MMC_SPI is not set
-# CONFIG_SPI_MMC is not set
+# CONFIG_MEMSTICK is not set
 # CONFIG_NEW_LEDS is not set
-CONFIG_RTC_LIB=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_HCTOSYS=y
-CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
-# CONFIG_RTC_DEBUG is not set
+# CONFIG_ACCESSIBILITY is not set
+CONFIG_RTC_LIB=m
+CONFIG_RTC_CLASS=m
 
 #
 # RTC interfaces
@@ -1111,66 +1179,74 @@ CONFIG_RTC_INTF_DEV=y
 # CONFIG_RTC_DRV_PCF8563 is not set
 # CONFIG_RTC_DRV_PCF8583 is not set
 # CONFIG_RTC_DRV_M41T80 is not set
+# CONFIG_RTC_DRV_S35390A is not set
+# CONFIG_RTC_DRV_FM3130 is not set
+# CONFIG_RTC_DRV_RX8581 is not set
 
 #
 # SPI RTC drivers
 #
-# CONFIG_RTC_DRV_RS5C348 is not set
+# CONFIG_RTC_DRV_M41T94 is not set
+# CONFIG_RTC_DRV_DS1305 is not set
+# CONFIG_RTC_DRV_DS1390 is not set
 # CONFIG_RTC_DRV_MAX6902 is not set
+# CONFIG_RTC_DRV_R9701 is not set
+# CONFIG_RTC_DRV_RS5C348 is not set
+# CONFIG_RTC_DRV_DS3234 is not set
 
 #
 # Platform RTC drivers
 #
+# CONFIG_RTC_DRV_DS1286 is not set
+# CONFIG_RTC_DRV_DS1511 is not set
 # CONFIG_RTC_DRV_DS1553 is not set
-# CONFIG_RTC_DRV_STK17TA8 is not set
 # CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_STK17TA8 is not set
 # CONFIG_RTC_DRV_M48T86 is not set
+# CONFIG_RTC_DRV_M48T35 is not set
 # CONFIG_RTC_DRV_M48T59 is not set
+# CONFIG_RTC_DRV_BQ4802 is not set
 # CONFIG_RTC_DRV_V3020 is not set
 
 #
 # on-CPU RTC drivers
 #
-CONFIG_RTC_DRV_BFIN=y
-
-#
-# Userspace I/O
-#
+CONFIG_RTC_DRV_BFIN=m
+# CONFIG_DMADEVICES is not set
+# CONFIG_AUXDISPLAY is not set
 # CONFIG_UIO is not set
-
-#
-# PBX support
-#
-# CONFIG_PBX is not set
+# CONFIG_STAGING is not set
 
 #
 # File systems
 #
-# CONFIG_EXT2_FS is not set
+CONFIG_EXT2_FS=m
+# CONFIG_EXT2_FS_XATTR is not set
 # CONFIG_EXT3_FS is not set
-# CONFIG_EXT4DEV_FS is not set
+# CONFIG_EXT4_FS is not set
 # CONFIG_REISERFS_FS is not set
 # CONFIG_JFS_FS is not set
 # CONFIG_FS_POSIX_ACL is not set
 # CONFIG_XFS_FS is not set
-# CONFIG_GFS2_FS is not set
 # CONFIG_OCFS2_FS is not set
-# CONFIG_MINIX_FS is not set
-# CONFIG_ROMFS_FS is not set
-CONFIG_INOTIFY=y
-CONFIG_INOTIFY_USER=y
-# CONFIG_QUOTA is not set
+# CONFIG_BTRFS_FS is not set
+CONFIG_FILE_LOCKING=y
 # CONFIG_DNOTIFY is not set
+# CONFIG_INOTIFY is not set
+# CONFIG_QUOTA is not set
 # CONFIG_AUTOFS_FS is not set
 # CONFIG_AUTOFS4_FS is not set
 # CONFIG_FUSE_FS is not set
 
 #
+# Caches
+#
+# CONFIG_FSCACHE is not set
+
+#
 # CD-ROM/DVD Filesystems
 #
-CONFIG_ISO9660_FS=m
-CONFIG_JOLIET=y
-CONFIG_ZISOFS=y
+# CONFIG_ISO9660_FS is not set
 # CONFIG_UDF_FS is not set
 
 #
@@ -1194,10 +1270,7 @@ CONFIG_SYSFS=y
 # CONFIG_TMPFS is not set
 # CONFIG_HUGETLB_PAGE is not set
 # CONFIG_CONFIGFS_FS is not set
-
-#
-# Miscellaneous filesystems
-#
+CONFIG_MISC_FILESYSTEMS=y
 # CONFIG_ADFS_FS is not set
 # CONFIG_AFFS_FS is not set
 # CONFIG_HFS_FS is not set
@@ -1205,17 +1278,7 @@ CONFIG_SYSFS=y
 # CONFIG_BEFS_FS is not set
 # CONFIG_BFS_FS is not set
 # CONFIG_EFS_FS is not set
-CONFIG_YAFFS_FS=m
-CONFIG_YAFFS_YAFFS1=y
-# CONFIG_YAFFS_DOES_ECC is not set
-CONFIG_YAFFS_YAFFS2=y
-CONFIG_YAFFS_AUTO_YAFFS2=y
-# CONFIG_YAFFS_DISABLE_LAZY_LOAD is not set
-CONFIG_YAFFS_CHECKPOINT_RESERVED_BLOCKS=10
-# CONFIG_YAFFS_DISABLE_WIDE_TNODES is not set
-# CONFIG_YAFFS_ALWAYS_CHECK_CHUNK_ERASED is not set
-CONFIG_YAFFS_SHORT_NAMES_IN_RAM=y
-CONFIG_JFFS2_FS=m
+CONFIG_JFFS2_FS=y
 CONFIG_JFFS2_FS_DEBUG=0
 CONFIG_JFFS2_FS_WRITEBUFFER=y
 # CONFIG_JFFS2_FS_WBUF_VERIFY is not set
@@ -1227,34 +1290,30 @@ CONFIG_JFFS2_ZLIB=y
 CONFIG_JFFS2_RTIME=y
 # CONFIG_JFFS2_RUBIN is not set
 # CONFIG_CRAMFS is not set
+# CONFIG_SQUASHFS is not set
 # CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_OMFS_FS is not set
 # CONFIG_HPFS_FS is not set
 # CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
 # CONFIG_SYSV_FS is not set
 # CONFIG_UFS_FS is not set
+# CONFIG_NILFS2_FS is not set
 CONFIG_NETWORK_FILESYSTEMS=y
 CONFIG_NFS_FS=m
 CONFIG_NFS_V3=y
 # CONFIG_NFS_V3_ACL is not set
 # CONFIG_NFS_V4 is not set
-# CONFIG_NFS_DIRECTIO is not set
-CONFIG_NFSD=m
-CONFIG_NFSD_V3=y
-# CONFIG_NFSD_V3_ACL is not set
-# CONFIG_NFSD_V4 is not set
-CONFIG_NFSD_TCP=y
+# CONFIG_NFSD is not set
 CONFIG_LOCKD=m
 CONFIG_LOCKD_V4=y
-CONFIG_EXPORTFS=m
 CONFIG_NFS_COMMON=y
 CONFIG_SUNRPC=m
-# CONFIG_SUNRPC_BIND34 is not set
 # CONFIG_RPCSEC_GSS_KRB5 is not set
 # CONFIG_RPCSEC_GSS_SPKM3 is not set
-CONFIG_SMB_FS=m
-CONFIG_SMB_NLS_DEFAULT=y
-CONFIG_SMB_NLS_REMOTE="cp437"
-CONFIG_CIFS=y
+# CONFIG_SMB_FS is not set
+CONFIG_CIFS=m
 # CONFIG_CIFS_STATS is not set
 # CONFIG_CIFS_WEAK_PW_HASH is not set
 # CONFIG_CIFS_XATTR is not set
@@ -1267,24 +1326,8 @@ CONFIG_CIFS=y
 #
 # Partition Types
 #
-CONFIG_PARTITION_ADVANCED=y
-# CONFIG_ACORN_PARTITION is not set
-# CONFIG_OSF_PARTITION is not set
-# CONFIG_AMIGA_PARTITION is not set
-# CONFIG_ATARI_PARTITION is not set
-# CONFIG_MAC_PARTITION is not set
+# CONFIG_PARTITION_ADVANCED is not set
 CONFIG_MSDOS_PARTITION=y
-# CONFIG_BSD_DISKLABEL is not set
-# CONFIG_MINIX_SUBPARTITION is not set
-# CONFIG_SOLARIS_X86_PARTITION is not set
-# CONFIG_UNIXWARE_DISKLABEL is not set
-# CONFIG_LDM_PARTITION is not set
-# CONFIG_SGI_PARTITION is not set
-# CONFIG_ULTRIX_PARTITION is not set
-# CONFIG_SUN_PARTITION is not set
-# CONFIG_KARMA_PARTITION is not set
-# CONFIG_EFI_PARTITION is not set
-# CONFIG_SYSV68_PARTITION is not set
 CONFIG_NLS=y
 CONFIG_NLS_DEFAULT="iso8859-1"
 CONFIG_NLS_CODEPAGE_437=m
@@ -1326,9 +1369,6 @@ CONFIG_NLS_KOI8_R=m
 CONFIG_NLS_KOI8_U=m
 CONFIG_NLS_UTF8=m
 # CONFIG_DLM is not set
-CONFIG_INSTRUMENTATION=y
-# CONFIG_PROFILING is not set
-# CONFIG_MARKERS is not set
 
 #
 # Kernel hacking
@@ -1336,14 +1376,39 @@ CONFIG_INSTRUMENTATION=y
 # CONFIG_PRINTK_TIME is not set
 CONFIG_ENABLE_WARN_DEPRECATED=y
 CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_FRAME_WARN=1024
 # CONFIG_MAGIC_SYSRQ is not set
 # CONFIG_UNUSED_SYMBOLS is not set
 CONFIG_DEBUG_FS=y
 # CONFIG_HEADERS_CHECK is not set
+CONFIG_DEBUG_SECTION_MISMATCH=y
 # CONFIG_DEBUG_KERNEL is not set
-CONFIG_DEBUG_BUGVERBOSE=y
+# CONFIG_DEBUG_BUGVERBOSE is not set
+# CONFIG_DEBUG_MEMORY_INIT is not set
+# CONFIG_RCU_CPU_STALL_DETECTOR is not set
+CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
+CONFIG_TRACING_SUPPORT=y
+
+#
+# Tracers
+#
+# CONFIG_FUNCTION_TRACER is not set
+# CONFIG_SCHED_TRACER is not set
+# CONFIG_CONTEXT_SWITCH_TRACER is not set
+# CONFIG_EVENT_TRACER is not set
+# CONFIG_BOOT_TRACER is not set
+# CONFIG_TRACE_BRANCH_PROFILING is not set
+# CONFIG_STACK_TRACER is not set
+# CONFIG_KMEMTRACE is not set
+# CONFIG_WORKQUEUE_TRACER is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_DYNAMIC_DEBUG is not set
 # CONFIG_SAMPLES is not set
-CONFIG_DEBUG_MMRS=y
+CONFIG_HAVE_ARCH_KGDB=y
+CONFIG_DEBUG_VERBOSE=y
+# CONFIG_DEBUG_MMRS is not set
+# CONFIG_DEBUG_DOUBLEFAULT is not set
 CONFIG_DEBUG_HUNT_FOR_ZERO=y
 CONFIG_DEBUG_BFIN_HWTRACE_ON=y
 CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_OFF=y
@@ -1352,33 +1417,125 @@ CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_OFF=y
 CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION=0
 # CONFIG_DEBUG_BFIN_HWTRACE_EXPAND is not set
 # CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE is not set
-# CONFIG_EARLY_PRINTK is not set
+CONFIG_EARLY_PRINTK=y
 CONFIG_CPLB_INFO=y
 CONFIG_ACCESS_CHECK=y
+# CONFIG_BFIN_ISRAM_SELF_TEST is not set
 
 #
 # Security options
 #
 # CONFIG_KEYS is not set
 CONFIG_SECURITY=y
+# CONFIG_SECURITYFS is not set
 # CONFIG_SECURITY_NETWORK is not set
-# CONFIG_SECURITY_CAPABILITIES is not set
-# CONFIG_SECURITY_ROOTPLUG is not set
-# CONFIG_CRYPTO is not set
+# CONFIG_SECURITY_PATH is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+# CONFIG_SECURITY_TOMOYO is not set
+CONFIG_CRYPTO=y
+
+#
+# Crypto core or helper
+#
+# CONFIG_CRYPTO_FIPS is not set
+# CONFIG_CRYPTO_MANAGER is not set
+# CONFIG_CRYPTO_MANAGER2 is not set
+# CONFIG_CRYPTO_GF128MUL is not set
+# CONFIG_CRYPTO_NULL is not set
+# CONFIG_CRYPTO_CRYPTD is not set
+# CONFIG_CRYPTO_AUTHENC is not set
+# CONFIG_CRYPTO_TEST is not set
+
+#
+# Authenticated Encryption with Associated Data
+#
+# CONFIG_CRYPTO_CCM is not set
+# CONFIG_CRYPTO_GCM is not set
+# CONFIG_CRYPTO_SEQIV is not set
+
+#
+# Block modes
+#
+# CONFIG_CRYPTO_CBC is not set
+# CONFIG_CRYPTO_CTR is not set
+# CONFIG_CRYPTO_CTS is not set
+# CONFIG_CRYPTO_ECB is not set
+# CONFIG_CRYPTO_LRW is not set
+# CONFIG_CRYPTO_PCBC is not set
+# CONFIG_CRYPTO_XTS is not set
+
+#
+# Hash modes
+#
+# CONFIG_CRYPTO_HMAC is not set
+# CONFIG_CRYPTO_XCBC is not set
+
+#
+# Digest
+#
+# CONFIG_CRYPTO_CRC32C is not set
+# CONFIG_CRYPTO_MD4 is not set
+# CONFIG_CRYPTO_MD5 is not set
+# CONFIG_CRYPTO_MICHAEL_MIC is not set
+# CONFIG_CRYPTO_RMD128 is not set
+# CONFIG_CRYPTO_RMD160 is not set
+# CONFIG_CRYPTO_RMD256 is not set
+# CONFIG_CRYPTO_RMD320 is not set
+# CONFIG_CRYPTO_SHA1 is not set
+# CONFIG_CRYPTO_SHA256 is not set
+# CONFIG_CRYPTO_SHA512 is not set
+# CONFIG_CRYPTO_TGR192 is not set
+# CONFIG_CRYPTO_WP512 is not set
+
+#
+# Ciphers
+#
+# CONFIG_CRYPTO_AES is not set
+# CONFIG_CRYPTO_ANUBIS is not set
+# CONFIG_CRYPTO_ARC4 is not set
+# CONFIG_CRYPTO_BLOWFISH is not set
+# CONFIG_CRYPTO_CAMELLIA is not set
+# CONFIG_CRYPTO_CAST5 is not set
+# CONFIG_CRYPTO_CAST6 is not set
+# CONFIG_CRYPTO_DES is not set
+# CONFIG_CRYPTO_FCRYPT is not set
+# CONFIG_CRYPTO_KHAZAD is not set
+# CONFIG_CRYPTO_SALSA20 is not set
+# CONFIG_CRYPTO_SEED is not set
+# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_TEA is not set
+# CONFIG_CRYPTO_TWOFISH is not set
+
+#
+# Compression
+#
+# CONFIG_CRYPTO_DEFLATE is not set
+# CONFIG_CRYPTO_ZLIB is not set
+# CONFIG_CRYPTO_LZO is not set
+
+#
+# Random Number Generation
+#
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
+# CONFIG_CRYPTO_HW is not set
+# CONFIG_BINARY_PRINTF is not set
 
 #
 # Library routines
 #
 CONFIG_BITREVERSE=y
+CONFIG_GENERIC_FIND_LAST_BIT=y
 CONFIG_CRC_CCITT=m
 # CONFIG_CRC16 is not set
+# CONFIG_CRC_T10DIF is not set
 # CONFIG_CRC_ITU_T is not set
 CONFIG_CRC32=y
 # CONFIG_CRC7 is not set
 # CONFIG_LIBCRC32C is not set
 CONFIG_ZLIB_INFLATE=y
-CONFIG_ZLIB_DEFLATE=m
-CONFIG_PLIST=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_DECOMPRESS_LZMA=y
 CONFIG_HAS_IOMEM=y
 CONFIG_HAS_IOPORT=y
 CONFIG_HAS_DMA=y
+CONFIG_NLATTR=y
diff --git a/arch/blackfin/configs/CM-BF561_defconfig b/arch/blackfin/configs/CM-BF561_defconfig
index bae4ee6e68bb..a6df01dac98a 100644
--- a/arch/blackfin/configs/CM-BF561_defconfig
+++ b/arch/blackfin/configs/CM-BF561_defconfig
@@ -1,15 +1,14 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.24.4
-# Tue Apr  1 10:50:11 2008
+# Linux kernel version: 2.6.30.5
 #
 # CONFIG_MMU is not set
 # CONFIG_FPU is not set
 CONFIG_RWSEM_GENERIC_SPINLOCK=y
 # CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
 CONFIG_BLACKFIN=y
+CONFIG_GENERIC_BUG=y
 CONFIG_ZONE_DMA=y
-CONFIG_SEMAPHORE_SLEEPERS=y
 CONFIG_GENERIC_FIND_NEXT_BIT=y
 CONFIG_GENERIC_HWEIGHT=y
 CONFIG_GENERIC_HARDIRQS=y
@@ -17,6 +16,9 @@ CONFIG_GENERIC_IRQ_PROBE=y
 CONFIG_GENERIC_GPIO=y
 CONFIG_FORCE_MAX_ZONEORDER=14
 CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
 CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
 
 #
@@ -27,62 +29,83 @@ CONFIG_BROKEN_ON_SMP=y
 CONFIG_INIT_ENV_ARG_LIMIT=32
 CONFIG_LOCALVERSION=""
 CONFIG_LOCALVERSION_AUTO=y
+CONFIG_HAVE_KERNEL_GZIP=y
+CONFIG_HAVE_KERNEL_BZIP2=y
+CONFIG_HAVE_KERNEL_LZMA=y
+# CONFIG_KERNEL_GZIP is not set
+# CONFIG_KERNEL_BZIP2 is not set
+CONFIG_KERNEL_LZMA=y
 CONFIG_SYSVIPC=y
 CONFIG_SYSVIPC_SYSCTL=y
 # CONFIG_POSIX_MQUEUE is not set
 # CONFIG_BSD_PROCESS_ACCT is not set
 # CONFIG_TASKSTATS is not set
-# CONFIG_USER_NS is not set
-# CONFIG_PID_NS is not set
 # CONFIG_AUDIT is not set
+
+#
+# RCU Subsystem
+#
+CONFIG_CLASSIC_RCU=y
+# CONFIG_TREE_RCU is not set
+# CONFIG_PREEMPT_RCU is not set
+# CONFIG_TREE_RCU_TRACE is not set
+# CONFIG_PREEMPT_RCU_TRACE is not set
 CONFIG_IKCONFIG=y
 CONFIG_IKCONFIG_PROC=y
 CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_GROUP_SCHED is not set
 # CONFIG_CGROUPS is not set
-CONFIG_FAIR_GROUP_SCHED=y
-CONFIG_FAIR_USER_SCHED=y
-# CONFIG_FAIR_CGROUP_SCHED is not set
-# CONFIG_SYSFS_DEPRECATED is not set
+# CONFIG_SYSFS_DEPRECATED_V2 is not set
 # CONFIG_RELAY is not set
-# CONFIG_BLK_DEV_INITRD is not set
+# CONFIG_NAMESPACES is not set
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+# CONFIG_RD_GZIP is not set
+# CONFIG_RD_BZIP2 is not set
+CONFIG_RD_LZMA=y
 # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
-# CONFIG_SYSCTL is not set
+CONFIG_SYSCTL=y
+CONFIG_ANON_INODES=y
 CONFIG_EMBEDDED=y
 # CONFIG_UID16 is not set
 # CONFIG_SYSCTL_SYSCALL is not set
 CONFIG_KALLSYMS=y
 # CONFIG_KALLSYMS_EXTRA_PASS is not set
-# CONFIG_HOTPLUG is not set
+# CONFIG_STRIP_ASM_SYMS is not set
+CONFIG_HOTPLUG=y
 CONFIG_PRINTK=y
 CONFIG_BUG=y
 # CONFIG_ELF_CORE is not set
 CONFIG_BASE_FULL=y
 # CONFIG_FUTEX is not set
-CONFIG_ANON_INODES=y
 CONFIG_EPOLL=y
-CONFIG_SIGNALFD=y
-CONFIG_EVENTFD=y
+# CONFIG_SIGNALFD is not set
+# CONFIG_TIMERFD is not set
+# CONFIG_EVENTFD is not set
+# CONFIG_AIO is not set
 CONFIG_VM_EVENT_COUNTERS=y
-CONFIG_BIG_ORDER_ALLOC_NOFAIL_MAGIC=3
-# CONFIG_NP2 is not set
+CONFIG_COMPAT_BRK=y
 CONFIG_SLAB=y
 # CONFIG_SLUB is not set
 # CONFIG_SLOB is not set
+CONFIG_MMAP_ALLOW_UNINITIALIZED=y
+# CONFIG_PROFILING is not set
+# CONFIG_MARKERS is not set
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_SLOW_WORK is not set
+# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
 CONFIG_SLABINFO=y
-CONFIG_RT_MUTEXES=y
-CONFIG_TINY_SHMEM=y
 CONFIG_BASE_SMALL=0
 CONFIG_MODULES=y
+# CONFIG_MODULE_FORCE_LOAD is not set
 CONFIG_MODULE_UNLOAD=y
 # CONFIG_MODULE_FORCE_UNLOAD is not set
 # CONFIG_MODVERSIONS is not set
 # CONFIG_MODULE_SRCVERSION_ALL is not set
-CONFIG_KMOD=y
 CONFIG_BLOCK=y
 # CONFIG_LBD is not set
-# CONFIG_BLK_DEV_IO_TRACE is not set
-# CONFIG_LSF is not set
 # CONFIG_BLK_DEV_BSG is not set
+# CONFIG_BLK_DEV_INTEGRITY is not set
 
 #
 # IO Schedulers
@@ -99,6 +122,7 @@ CONFIG_DEFAULT_IOSCHED="noop"
 CONFIG_PREEMPT_NONE=y
 # CONFIG_PREEMPT_VOLUNTARY is not set
 # CONFIG_PREEMPT is not set
+# CONFIG_FREEZER is not set
 
 #
 # Blackfin Processor Options
@@ -107,6 +131,10 @@ CONFIG_PREEMPT_NONE=y
 #
 # Processor and Board Settings
 #
+# CONFIG_BF512 is not set
+# CONFIG_BF514 is not set
+# CONFIG_BF516 is not set
+# CONFIG_BF518 is not set
 # CONFIG_BF522 is not set
 # CONFIG_BF523 is not set
 # CONFIG_BF524 is not set
@@ -119,30 +147,47 @@ CONFIG_PREEMPT_NONE=y
 # CONFIG_BF534 is not set
 # CONFIG_BF536 is not set
 # CONFIG_BF537 is not set
+# CONFIG_BF538 is not set
+# CONFIG_BF539 is not set
 # CONFIG_BF542 is not set
+# CONFIG_BF542M is not set
 # CONFIG_BF544 is not set
+# CONFIG_BF544M is not set
 # CONFIG_BF547 is not set
+# CONFIG_BF547M is not set
 # CONFIG_BF548 is not set
+# CONFIG_BF548M is not set
 # CONFIG_BF549 is not set
+# CONFIG_BF549M is not set
 CONFIG_BF561=y
+# CONFIG_SMP is not set
+CONFIG_BF_REV_MIN=3
+CONFIG_BF_REV_MAX=5
 # CONFIG_BF_REV_0_0 is not set
 # CONFIG_BF_REV_0_1 is not set
 # CONFIG_BF_REV_0_2 is not set
 CONFIG_BF_REV_0_3=y
 # CONFIG_BF_REV_0_4 is not set
 # CONFIG_BF_REV_0_5 is not set
+# CONFIG_BF_REV_0_6 is not set
 # CONFIG_BF_REV_ANY is not set
 # CONFIG_BF_REV_NONE is not set
-CONFIG_BFIN_DUAL_CORE=y
 CONFIG_MEM_MT48LC8M32B2B5_7=y
 CONFIG_IRQ_PLL_WAKEUP=7
 CONFIG_IRQ_SPORT0_ERROR=7
 CONFIG_IRQ_SPORT1_ERROR=7
+CONFIG_IRQ_TIMER0=10
+CONFIG_IRQ_TIMER1=10
+CONFIG_IRQ_TIMER2=10
+CONFIG_IRQ_TIMER3=10
+CONFIG_IRQ_TIMER4=10
+CONFIG_IRQ_TIMER5=10
+CONFIG_IRQ_TIMER6=10
+CONFIG_IRQ_TIMER7=10
 CONFIG_IRQ_SPI_ERROR=7
 # CONFIG_BFIN561_EZKIT is not set
 # CONFIG_BFIN561_TEPLA is not set
 CONFIG_BFIN561_BLUETECHNIX_CM=y
-# CONFIG_GENERIC_BF561_BOARD is not set
 
 #
 # BF561 Specific Configuration
@@ -151,12 +196,7 @@ CONFIG_BFIN561_BLUETECHNIX_CM=y
 #
 # Core B Support
 #
-
-#
-# Core B Support
-#
 CONFIG_BF561_COREB=y
-# CONFIG_BF561_COREB_RESET is not set
 
 #
 # Interrupt Priority Assignment
@@ -196,14 +236,6 @@ CONFIG_IRQ_DMA2_8=9
 CONFIG_IRQ_DMA2_9=9
 CONFIG_IRQ_DMA2_10=9
 CONFIG_IRQ_DMA2_11=9
-CONFIG_IRQ_TIMER0=10
-CONFIG_IRQ_TIMER1=10
-CONFIG_IRQ_TIMER2=10
-CONFIG_IRQ_TIMER3=10
-CONFIG_IRQ_TIMER4=10
-CONFIG_IRQ_TIMER5=10
-CONFIG_IRQ_TIMER6=10
-CONFIG_IRQ_TIMER7=10
 CONFIG_IRQ_TIMER8=10
 CONFIG_IRQ_TIMER9=10
 CONFIG_IRQ_TIMER10=10
@@ -226,6 +258,7 @@ CONFIG_IRQ_WDTIMER=13
 # Board customizations
 #
 # CONFIG_CMDLINE_BOOL is not set
+CONFIG_BOOT_LOAD=0x1000
 
 #
 # Clock/PLL Setup
@@ -245,19 +278,20 @@ CONFIG_HZ_250=y
 # CONFIG_HZ_300 is not set
 # CONFIG_HZ_1000 is not set
 CONFIG_HZ=250
+# CONFIG_SCHED_HRTICK is not set
 CONFIG_GENERIC_TIME=y
 CONFIG_GENERIC_CLOCKEVENTS=y
+# CONFIG_TICKSOURCE_GPTMR0 is not set
+CONFIG_TICKSOURCE_CORETMR=y
 # CONFIG_CYCLES_CLOCKSOURCE is not set
-# CONFIG_TICK_ONESHOT is not set
+# CONFIG_GPTMR0_CLOCKSOURCE is not set
 # CONFIG_NO_HZ is not set
 # CONFIG_HIGH_RES_TIMERS is not set
 CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
 
 #
-# Memory Setup
+# Misc
 #
-CONFIG_MAX_MEM_SIZE=32
-CONFIG_BOOT_LOAD=0x1000
 CONFIG_BFIN_SCRATCH_REG_RETN=y
 # CONFIG_BFIN_SCRATCH_REG_RETE is not set
 # CONFIG_BFIN_SCRATCH_REG_CYCLES is not set
@@ -284,6 +318,12 @@ CONFIG_IP_CHECKSUM_L1=y
 CONFIG_CACHELINE_ALIGNED_L1=y
 CONFIG_SYSCALL_TAB_L1=y
 CONFIG_CPLB_SWITCH_TAB_L1=y
+CONFIG_APP_STACK_L1=y
+
+#
+# Speed Optimizations
+#
+CONFIG_BFIN_INS_LOWOVERHEAD=y
 CONFIG_RAMKERNEL=y
 # CONFIG_ROMKERNEL is not set
 CONFIG_SELECT_MEMORY_MODEL=y
@@ -292,14 +332,16 @@ CONFIG_FLATMEM_MANUAL=y
 # CONFIG_SPARSEMEM_MANUAL is not set
 CONFIG_FLATMEM=y
 CONFIG_FLAT_NODE_MEM_MAP=y
-# CONFIG_SPARSEMEM_STATIC is not set
-# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
+CONFIG_PAGEFLAGS_EXTENDED=y
 CONFIG_SPLIT_PTLOCK_CPUS=4
-# CONFIG_RESOURCES_64BIT is not set
+# CONFIG_PHYS_ADDR_T_64BIT is not set
 CONFIG_ZONE_DMA_FLAG=1
 CONFIG_VIRT_TO_BUS=y
-CONFIG_LARGE_ALLOCS=y
+CONFIG_UNEVICTABLE_LRU=y
+CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
+CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0
 # CONFIG_BFIN_GPTIMERS is not set
+# CONFIG_DMA_UNCACHED_4M is not set
 # CONFIG_DMA_UNCACHED_2M is not set
 CONFIG_DMA_UNCACHED_1M=y
 # CONFIG_DMA_UNCACHED_NONE is not set
@@ -308,15 +350,16 @@ CONFIG_DMA_UNCACHED_1M=y
 # Cache Support
 #
 CONFIG_BFIN_ICACHE=y
-# CONFIG_BFIN_ICACHE_LOCK is not set
+CONFIG_BFIN_EXTMEM_ICACHEABLE=y
+# CONFIG_BFIN_L2_ICACHEABLE is not set
 CONFIG_BFIN_DCACHE=y
 # CONFIG_BFIN_DCACHE_BANKA is not set
-CONFIG_BFIN_EXTMEM_ICACHEABLE=y
 CONFIG_BFIN_EXTMEM_DCACHEABLE=y
-CONFIG_BFIN_EXTMEM_WRITEBACK=y
-# CONFIG_BFIN_EXTMEM_WRITETHROUGH is not set
-# CONFIG_BFIN_L2_ICACHEABLE is not set
+# CONFIG_BFIN_EXTMEM_WRITEBACK is not set
+CONFIG_BFIN_EXTMEM_WRITETHROUGH=y
 # CONFIG_BFIN_L2_DCACHEABLE is not set
+# CONFIG_BFIN_L2_WRITEBACK is not set
+# CONFIG_BFIN_L2_WRITETHROUGH is not set
 
 #
 # Memory Protection Unit
@@ -324,7 +367,7 @@ CONFIG_BFIN_EXTMEM_WRITEBACK=y
 # CONFIG_MPU is not set
 
 #
-# Asynchonous Memory Configuration
+# Asynchronous Memory Configuration
 #
 
 #
@@ -353,8 +396,8 @@ CONFIG_BANK_3=0xFFC2
 #
 # Bus options (PCI, PCMCIA, EISA, MCA, ISA)
 #
-# CONFIG_PCI is not set
 # CONFIG_ARCH_SUPPORTS_MSI is not set
+# CONFIG_PCCARD is not set
 
 #
 # Executable file formats
@@ -363,18 +406,19 @@ CONFIG_BINFMT_ELF_FDPIC=y
 CONFIG_BINFMT_FLAT=y
 CONFIG_BINFMT_ZFLAT=y
 CONFIG_BINFMT_SHARED_FLAT=y
+# CONFIG_HAVE_AOUT is not set
 # CONFIG_BINFMT_MISC is not set
 
 #
 # Power management options
 #
 # CONFIG_PM is not set
-CONFIG_SUSPEND_UP_POSSIBLE=y
-# CONFIG_PM_WAKEUP_BY_GPIO is not set
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
 
 #
-# Networking
+# CPU Frequency scaling
 #
+# CONFIG_CPU_FREQ is not set
 CONFIG_NET=y
 
 #
@@ -383,10 +427,6 @@ CONFIG_NET=y
 CONFIG_PACKET=y
 # CONFIG_PACKET_MMAP is not set
 CONFIG_UNIX=y
-CONFIG_XFRM=y
-# CONFIG_XFRM_USER is not set
-# CONFIG_XFRM_SUB_POLICY is not set
-# CONFIG_XFRM_MIGRATE is not set
 # CONFIG_NET_KEY is not set
 CONFIG_INET=y
 # CONFIG_IP_MULTICAST is not set
@@ -407,14 +447,11 @@ CONFIG_IP_FIB_HASH=y
 # CONFIG_INET_XFRM_MODE_BEET is not set
 # CONFIG_INET_LRO is not set
 # CONFIG_INET_DIAG is not set
-CONFIG_INET_TCP_DIAG=y
 # CONFIG_TCP_CONG_ADVANCED is not set
 CONFIG_TCP_CONG_CUBIC=y
 CONFIG_DEFAULT_TCP_CONG="cubic"
 # CONFIG_TCP_MD5SIG is not set
 # CONFIG_IPV6 is not set
-# CONFIG_INET6_XFRM_TUNNEL is not set
-# CONFIG_INET6_TUNNEL is not set
 # CONFIG_NETLABEL is not set
 # CONFIG_NETWORK_SECMARK is not set
 # CONFIG_NETFILTER is not set
@@ -423,6 +460,7 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
 # CONFIG_TIPC is not set
 # CONFIG_ATM is not set
 # CONFIG_BRIDGE is not set
+# CONFIG_NET_DSA is not set
 # CONFIG_VLAN_8021Q is not set
 # CONFIG_DECNET is not set
 # CONFIG_LLC2 is not set
@@ -432,24 +470,21 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
 # CONFIG_LAPB is not set
 # CONFIG_ECONET is not set
 # CONFIG_WAN_ROUTER is not set
+# CONFIG_PHONET is not set
 # CONFIG_NET_SCHED is not set
+# CONFIG_DCB is not set
 
 #
 # Network testing
 #
 # CONFIG_NET_PKTGEN is not set
 # CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
 # CONFIG_IRDA is not set
 # CONFIG_BT is not set
 # CONFIG_AF_RXRPC is not set
-
-#
-# Wireless
-#
-# CONFIG_CFG80211 is not set
-# CONFIG_WIRELESS_EXT is not set
-# CONFIG_MAC80211 is not set
-# CONFIG_IEEE80211 is not set
+# CONFIG_WIRELESS is not set
+# CONFIG_WIMAX is not set
 # CONFIG_RFKILL is not set
 # CONFIG_NET_9P is not set
 
@@ -460,16 +495,22 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
 #
 # Generic Driver Options
 #
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 CONFIG_STANDALONE=y
 CONFIG_PREVENT_FIRMWARE_BUILD=y
+CONFIG_FW_LOADER=y
+CONFIG_FIRMWARE_IN_KERNEL=y
+CONFIG_EXTRA_FIRMWARE=""
 # CONFIG_SYS_HYPERVISOR is not set
 # CONFIG_CONNECTOR is not set
 CONFIG_MTD=y
 # CONFIG_MTD_DEBUG is not set
+# CONFIG_MTD_TESTS is not set
 # CONFIG_MTD_CONCAT is not set
 CONFIG_MTD_PARTITIONS=y
 # CONFIG_MTD_REDBOOT_PARTS is not set
-# CONFIG_MTD_CMDLINE_PARTS is not set
+CONFIG_MTD_CMDLINE_PARTS=y
+# CONFIG_MTD_AR7_PARTS is not set
 
 #
 # User Modules And Translation Layers
@@ -487,8 +528,10 @@ CONFIG_MTD_BLOCK=y
 #
 # RAM/ROM/Flash chip drivers
 #
-# CONFIG_MTD_CFI is not set
+CONFIG_MTD_CFI=y
 # CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_GEN_PROBE=y
+# CONFIG_MTD_CFI_ADV_OPTIONS is not set
 CONFIG_MTD_MAP_BANK_WIDTH_1=y
 CONFIG_MTD_MAP_BANK_WIDTH_2=y
 CONFIG_MTD_MAP_BANK_WIDTH_4=y
@@ -499,20 +542,29 @@ CONFIG_MTD_CFI_I1=y
 CONFIG_MTD_CFI_I2=y
 # CONFIG_MTD_CFI_I4 is not set
 # CONFIG_MTD_CFI_I8 is not set
+CONFIG_MTD_CFI_INTELEXT=y
+# CONFIG_MTD_CFI_AMDSTD is not set
+# CONFIG_MTD_CFI_STAA is not set
+# CONFIG_MTD_PSD4256G is not set
+CONFIG_MTD_CFI_UTIL=y
 CONFIG_MTD_RAM=y
-# CONFIG_MTD_ROM is not set
+CONFIG_MTD_ROM=m
 # CONFIG_MTD_ABSENT is not set
 
 #
 # Mapping drivers for chip access
 #
 # CONFIG_MTD_COMPLEX_MAPPINGS is not set
-CONFIG_MTD_UCLINUX=y
+CONFIG_MTD_PHYSMAP=y
+# CONFIG_MTD_PHYSMAP_COMPAT is not set
+# CONFIG_MTD_UCLINUX is not set
 # CONFIG_MTD_PLATRAM is not set
 
 #
 # Self-contained MTD device drivers
 #
+# CONFIG_MTD_DATAFLASH is not set
+# CONFIG_MTD_M25P80 is not set
 # CONFIG_MTD_SLRAM is not set
 # CONFIG_MTD_PHRAM is not set
 # CONFIG_MTD_MTDRAM is not set
@@ -528,6 +580,11 @@ CONFIG_MTD_UCLINUX=y
 # CONFIG_MTD_ONENAND is not set
 
 #
+# LPDDR flash memory drivers
+#
+# CONFIG_MTD_LPDDR is not set
+
+#
 # UBI - Unsorted block images
 #
 # CONFIG_MTD_UBI is not set
@@ -539,14 +596,21 @@ CONFIG_BLK_DEV=y
 CONFIG_BLK_DEV_RAM=y
 CONFIG_BLK_DEV_RAM_COUNT=16
 CONFIG_BLK_DEV_RAM_SIZE=4096
-CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
+# CONFIG_BLK_DEV_XIP is not set
 # CONFIG_CDROM_PKTCDVD is not set
 # CONFIG_ATA_OVER_ETH is not set
+# CONFIG_BLK_DEV_HD is not set
 CONFIG_MISC_DEVICES=y
+# CONFIG_ENCLOSURE_SERVICES is not set
+# CONFIG_C2PORT is not set
+
+#
+# EEPROM support
+#
+# CONFIG_EEPROM_AT25 is not set
 # CONFIG_EEPROM_93CX6 is not set
+CONFIG_HAVE_IDE=y
 # CONFIG_IDE is not set
-# CONFIG_BFIN_IDE_ADDRESS_MAPPING_MODE0 is not set
-# CONFIG_BFIN_IDE_ADDRESS_MAPPING_MODE1 is not set
 
 #
 # SCSI device support
@@ -558,26 +622,50 @@ CONFIG_MISC_DEVICES=y
 # CONFIG_ATA is not set
 # CONFIG_MD is not set
 CONFIG_NETDEVICES=y
-# CONFIG_NETDEVICES_MULTIQUEUE is not set
+CONFIG_COMPAT_NET_DEV_OPS=y
 # CONFIG_DUMMY is not set
 # CONFIG_BONDING is not set
 # CONFIG_MACVLAN is not set
 # CONFIG_EQUALIZER is not set
 # CONFIG_TUN is not set
 # CONFIG_VETH is not set
-# CONFIG_PHYLIB is not set
+CONFIG_PHYLIB=y
+
+#
+# MII PHY device drivers
+#
+# CONFIG_MARVELL_PHY is not set
+# CONFIG_DAVICOM_PHY is not set
+# CONFIG_QSEMI_PHY is not set
+# CONFIG_LXT_PHY is not set
+# CONFIG_CICADA_PHY is not set
+# CONFIG_VITESSE_PHY is not set
+# CONFIG_SMSC_PHY is not set
+# CONFIG_BROADCOM_PHY is not set
+# CONFIG_ICPLUS_PHY is not set
+# CONFIG_REALTEK_PHY is not set
+# CONFIG_NATIONAL_PHY is not set
+# CONFIG_STE10XP is not set
+# CONFIG_LSI_ET1011C_PHY is not set
+# CONFIG_FIXED_PHY is not set
+# CONFIG_MDIO_BITBANG is not set
 CONFIG_NET_ETHERNET=y
 CONFIG_MII=y
-CONFIG_SMC91X=y
-# CONFIG_SMSC911X is not set
+# CONFIG_SMC91X is not set
 # CONFIG_DM9000 is not set
+# CONFIG_ENC28J60 is not set
+# CONFIG_ETHOC is not set
+CONFIG_SMSC911X=m
+# CONFIG_DNET is not set
 # CONFIG_IBM_NEW_EMAC_ZMII is not set
 # CONFIG_IBM_NEW_EMAC_RGMII is not set
 # CONFIG_IBM_NEW_EMAC_TAH is not set
 # CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
+# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
+# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
 # CONFIG_B44 is not set
 # CONFIG_NETDEV_1000 is not set
-# CONFIG_AX88180 is not set
 # CONFIG_NETDEV_10000 is not set
 
 #
@@ -585,10 +673,13 @@ CONFIG_SMC91X=y
 #
 # CONFIG_WLAN_PRE80211 is not set
 # CONFIG_WLAN_80211 is not set
+
+#
+# Enable WiMAX (Networking options) to see the WiMAX drivers
+#
 # CONFIG_WAN is not set
 # CONFIG_PPP is not set
 # CONFIG_SLIP is not set
-# CONFIG_SHAPER is not set
 # CONFIG_NETCONSOLE is not set
 # CONFIG_NETPOLL is not set
 # CONFIG_NET_POLL_CONTROLLER is not set
@@ -609,16 +700,15 @@ CONFIG_SMC91X=y
 #
 # Character devices
 #
-# CONFIG_AD9960 is not set
-# CONFIG_SPI_ADC_BF533 is not set
-# CONFIG_BF5xx_PPIFCD is not set
+CONFIG_BFIN_DMA_INTERFACE=m
+# CONFIG_BFIN_PPI is not set
+# CONFIG_BFIN_PPIFCD is not set
 # CONFIG_BFIN_SIMPLE_TIMER is not set
-# CONFIG_BF5xx_PPI is not set
+# CONFIG_BFIN_SPI_ADC is not set
 # CONFIG_BFIN_SPORT is not set
-# CONFIG_BFIN_TIMER_LATENCY is not set
-# CONFIG_SIMPLE_GPIO is not set
 # CONFIG_VT is not set
 # CONFIG_DEVKMEM is not set
+# CONFIG_BFIN_JTAG_COMM is not set
 # CONFIG_SERIAL_NONSTANDARD is not set
 
 #
@@ -629,6 +719,7 @@ CONFIG_SMC91X=y
 #
 # Non-8250 serial port support
 #
+# CONFIG_SERIAL_MAX3100 is not set
 CONFIG_SERIAL_BFIN=y
 CONFIG_SERIAL_BFIN_CONSOLE=y
 CONFIG_SERIAL_BFIN_DMA=y
@@ -639,6 +730,7 @@ CONFIG_SERIAL_CORE=y
 CONFIG_SERIAL_CORE_CONSOLE=y
 # CONFIG_SERIAL_BFIN_SPORT is not set
 CONFIG_UNIX98_PTYS=y
+# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
 # CONFIG_LEGACY_PTYS is not set
 
 #
@@ -647,54 +739,100 @@ CONFIG_UNIX98_PTYS=y
 # CONFIG_CAN4LINUX is not set
 # CONFIG_IPMI_HANDLER is not set
 # CONFIG_HW_RANDOM is not set
-# CONFIG_GEN_RTC is not set
 # CONFIG_R3964 is not set
 # CONFIG_RAW_DRIVER is not set
 # CONFIG_TCG_TPM is not set
 # CONFIG_I2C is not set
+CONFIG_SPI=y
+CONFIG_SPI_MASTER=y
+
+#
+# SPI Master Controller Drivers
+#
+CONFIG_SPI_BFIN=y
+# CONFIG_SPI_BFIN_LOCK is not set
+# CONFIG_SPI_BFIN_SPORT is not set
+# CONFIG_SPI_BITBANG is not set
+# CONFIG_SPI_GPIO is not set
 
+#
+# SPI Protocol Masters
+#
+# CONFIG_SPI_SPIDEV is not set
+# CONFIG_SPI_TLE62X0 is not set
 CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
 CONFIG_GPIOLIB=y
 CONFIG_GPIO_SYSFS=y
 
 #
-# SPI support
+# Memory mapped GPIO expanders:
+#
+
+#
+# I2C GPIO expanders:
+#
+
 #
-# CONFIG_SPI is not set
-# CONFIG_SPI_MASTER is not set
+# PCI GPIO expanders:
+#
+
+#
+# SPI GPIO expanders:
+#
+# CONFIG_GPIO_MAX7301 is not set
+# CONFIG_GPIO_MCP23S08 is not set
 # CONFIG_W1 is not set
 # CONFIG_POWER_SUPPLY is not set
 CONFIG_HWMON=y
 # CONFIG_HWMON_VID is not set
+# CONFIG_SENSORS_ADCXX is not set
 # CONFIG_SENSORS_F71805F is not set
 # CONFIG_SENSORS_F71882FG is not set
 # CONFIG_SENSORS_IT87 is not set
+# CONFIG_SENSORS_LM70 is not set
+# CONFIG_SENSORS_MAX1111 is not set
 # CONFIG_SENSORS_PC87360 is not set
 # CONFIG_SENSORS_PC87427 is not set
+# CONFIG_SENSORS_SHT15 is not set
 # CONFIG_SENSORS_SMSC47M1 is not set
 # CONFIG_SENSORS_SMSC47B397 is not set
 # CONFIG_SENSORS_VT1211 is not set
 # CONFIG_SENSORS_W83627HF is not set
 # CONFIG_SENSORS_W83627EHF is not set
 # CONFIG_HWMON_DEBUG_CHIP is not set
+# CONFIG_THERMAL is not set
+# CONFIG_THERMAL_HWMON is not set
 # CONFIG_WATCHDOG is not set
+CONFIG_SSB_POSSIBLE=y
 
 #
 # Sonics Silicon Backplane
 #
-CONFIG_SSB_POSSIBLE=y
 # CONFIG_SSB is not set
 
 #
 # Multifunction device drivers
 #
+# CONFIG_MFD_CORE is not set
 # CONFIG_MFD_SM501 is not set
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_MFD_TMIO is not set
+# CONFIG_REGULATOR is not set
 
 #
 # Multimedia devices
 #
+
+#
+# Multimedia core support
+#
 # CONFIG_VIDEO_DEV is not set
 # CONFIG_DVB_CORE is not set
+# CONFIG_VIDEO_MEDIA is not set
+
+#
+# Multimedia drivers
+#
 # CONFIG_DAB is not set
 
 #
@@ -709,42 +847,85 @@ CONFIG_SSB_POSSIBLE=y
 # Display device support
 #
 # CONFIG_DISPLAY_SUPPORT is not set
-
-#
-# Sound
-#
 # CONFIG_SOUND is not set
 CONFIG_USB_SUPPORT=y
 CONFIG_USB_ARCH_HAS_HCD=y
 # CONFIG_USB_ARCH_HAS_OHCI is not set
 # CONFIG_USB_ARCH_HAS_EHCI is not set
 # CONFIG_USB is not set
-
-#
-# Enable Host or Gadget support to see Inventra options
-#
-
-#
-# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
-#
-
-#
-# USB Gadget Support
-#
-# CONFIG_USB_GADGET is not set
-# CONFIG_MMC is not set
+# CONFIG_USB_OTG_WHITELIST is not set
+# CONFIG_USB_OTG_BLACKLIST_HUB is not set
+# CONFIG_USB_GADGET_MUSB_HDRC is not set
+
+#
+# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
+#
+CONFIG_USB_GADGET=m
+# CONFIG_USB_GADGET_DEBUG_FILES is not set
+# CONFIG_USB_GADGET_DEBUG_FS is not set
+CONFIG_USB_GADGET_VBUS_DRAW=2
+CONFIG_USB_GADGET_SELECTED=y
+# CONFIG_USB_GADGET_AT91 is not set
+# CONFIG_USB_GADGET_ATMEL_USBA is not set
+# CONFIG_USB_GADGET_FSL_USB2 is not set
+# CONFIG_USB_GADGET_LH7A40X is not set
+# CONFIG_USB_GADGET_OMAP is not set
+# CONFIG_USB_GADGET_PXA25X is not set
+# CONFIG_USB_GADGET_PXA27X is not set
+# CONFIG_USB_GADGET_S3C2410 is not set
+# CONFIG_USB_GADGET_IMX is not set
+# CONFIG_USB_GADGET_M66592 is not set
+# CONFIG_USB_GADGET_AMD5536UDC is not set
+# CONFIG_USB_GADGET_FSL_QE is not set
+# CONFIG_USB_GADGET_CI13XXX is not set
+CONFIG_USB_GADGET_NET2272=y
+CONFIG_USB_NET2272=m
+# CONFIG_USB_GADGET_NET2280 is not set
+# CONFIG_USB_GADGET_GOKU is not set
+# CONFIG_USB_GADGET_DUMMY_HCD is not set
+CONFIG_USB_GADGET_DUALSPEED=y
+# CONFIG_USB_ZERO is not set
+# CONFIG_USB_AUDIO is not set
+CONFIG_USB_ETH=m
+CONFIG_USB_ETH_RNDIS=y
+# CONFIG_USB_GADGETFS is not set
+CONFIG_USB_FILE_STORAGE=m
+# CONFIG_USB_FILE_STORAGE_TEST is not set
+CONFIG_USB_G_SERIAL=m
+# CONFIG_USB_MIDI_GADGET is not set
+CONFIG_USB_G_PRINTER=m
+# CONFIG_USB_CDC_COMPOSITE is not set
+
+#
+# OTG and related infrastructure
+#
+# CONFIG_USB_GPIO_VBUS is not set
+# CONFIG_NOP_USB_XCEIV is not set
+CONFIG_MMC=y
+# CONFIG_MMC_DEBUG is not set
+# CONFIG_MMC_UNSAFE_RESUME is not set
+
+#
+# MMC/SD/SDIO Card Drivers
+#
+CONFIG_MMC_BLOCK=y
+CONFIG_MMC_BLOCK_BOUNCE=y
+# CONFIG_SDIO_UART is not set
+# CONFIG_MMC_TEST is not set
+
+#
+# MMC/SD/SDIO Host Controller Drivers
+#
+# CONFIG_MMC_SDHCI is not set
+CONFIG_MMC_SPI=m
+# CONFIG_MEMSTICK is not set
 # CONFIG_NEW_LEDS is not set
+# CONFIG_ACCESSIBILITY is not set
 # CONFIG_RTC_CLASS is not set
-
-#
-# Userspace I/O
-#
+# CONFIG_DMADEVICES is not set
+# CONFIG_AUXDISPLAY is not set
 # CONFIG_UIO is not set
-
-#
-# PBX support
-#
-# CONFIG_PBX is not set
+# CONFIG_STAGING is not set
 
 #
 # File systems
@@ -754,25 +935,29 @@ CONFIG_EXT2_FS_XATTR=y
 # CONFIG_EXT2_FS_POSIX_ACL is not set
 # CONFIG_EXT2_FS_SECURITY is not set
 # CONFIG_EXT3_FS is not set
-# CONFIG_EXT4DEV_FS is not set
+# CONFIG_EXT4_FS is not set
 CONFIG_FS_MBCACHE=y
 # CONFIG_REISERFS_FS is not set
 # CONFIG_JFS_FS is not set
 # CONFIG_FS_POSIX_ACL is not set
 # CONFIG_XFS_FS is not set
-# CONFIG_GFS2_FS is not set
 # CONFIG_OCFS2_FS is not set
-# CONFIG_MINIX_FS is not set
-# CONFIG_ROMFS_FS is not set
+# CONFIG_BTRFS_FS is not set
+CONFIG_FILE_LOCKING=y
+# CONFIG_DNOTIFY is not set
 CONFIG_INOTIFY=y
 CONFIG_INOTIFY_USER=y
 # CONFIG_QUOTA is not set
-# CONFIG_DNOTIFY is not set
 # CONFIG_AUTOFS_FS is not set
 # CONFIG_AUTOFS4_FS is not set
 # CONFIG_FUSE_FS is not set
 
 #
+# Caches
+#
+# CONFIG_FSCACHE is not set
+
+#
 # CD-ROM/DVD Filesystems
 #
 # CONFIG_ISO9660_FS is not set
@@ -781,8 +966,11 @@ CONFIG_INOTIFY_USER=y
 #
 # DOS/FAT/NT Filesystems
 #
-# CONFIG_MSDOS_FS is not set
-# CONFIG_VFAT_FS is not set
+CONFIG_FAT_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
 # CONFIG_NTFS_FS is not set
 
 #
@@ -794,10 +982,7 @@ CONFIG_SYSFS=y
 # CONFIG_TMPFS is not set
 # CONFIG_HUGETLB_PAGE is not set
 # CONFIG_CONFIGFS_FS is not set
-
-#
-# Miscellaneous filesystems
-#
+CONFIG_MISC_FILESYSTEMS=y
 # CONFIG_ADFS_FS is not set
 # CONFIG_AFFS_FS is not set
 # CONFIG_HFS_FS is not set
@@ -805,14 +990,28 @@ CONFIG_SYSFS=y
 # CONFIG_BEFS_FS is not set
 # CONFIG_BFS_FS is not set
 # CONFIG_EFS_FS is not set
-# CONFIG_YAFFS_FS is not set
-# CONFIG_JFFS2_FS is not set
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_DEBUG=0
+CONFIG_JFFS2_FS_WRITEBUFFER=y
+# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
+# CONFIG_JFFS2_SUMMARY is not set
+# CONFIG_JFFS2_FS_XATTR is not set
+# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
+CONFIG_JFFS2_ZLIB=y
+# CONFIG_JFFS2_LZO is not set
+CONFIG_JFFS2_RTIME=y
+# CONFIG_JFFS2_RUBIN is not set
 # CONFIG_CRAMFS is not set
+# CONFIG_SQUASHFS is not set
 # CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_OMFS_FS is not set
 # CONFIG_HPFS_FS is not set
 # CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
 # CONFIG_SYSV_FS is not set
 # CONFIG_UFS_FS is not set
+# CONFIG_NILFS2_FS is not set
 CONFIG_NETWORK_FILESYSTEMS=y
 # CONFIG_NFS_FS is not set
 # CONFIG_NFSD is not set
@@ -827,11 +1026,47 @@ CONFIG_NETWORK_FILESYSTEMS=y
 #
 # CONFIG_PARTITION_ADVANCED is not set
 CONFIG_MSDOS_PARTITION=y
-# CONFIG_NLS is not set
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="iso8859-1"
+CONFIG_NLS_CODEPAGE_437=y
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+# CONFIG_NLS_ASCII is not set
+CONFIG_NLS_ISO8859_1=y
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+# CONFIG_NLS_UTF8 is not set
 # CONFIG_DLM is not set
-CONFIG_INSTRUMENTATION=y
-# CONFIG_PROFILING is not set
-# CONFIG_MARKERS is not set
 
 #
 # Kernel hacking
@@ -839,14 +1074,40 @@ CONFIG_INSTRUMENTATION=y
 # CONFIG_PRINTK_TIME is not set
 CONFIG_ENABLE_WARN_DEPRECATED=y
 CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_FRAME_WARN=1024
 # CONFIG_MAGIC_SYSRQ is not set
 # CONFIG_UNUSED_SYMBOLS is not set
 CONFIG_DEBUG_FS=y
 # CONFIG_HEADERS_CHECK is not set
+CONFIG_DEBUG_SECTION_MISMATCH=y
 # CONFIG_DEBUG_KERNEL is not set
-CONFIG_DEBUG_BUGVERBOSE=y
+# CONFIG_DEBUG_BUGVERBOSE is not set
+# CONFIG_DEBUG_MEMORY_INIT is not set
+# CONFIG_RCU_CPU_STALL_DETECTOR is not set
+CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
+CONFIG_TRACING_SUPPORT=y
+
+#
+# Tracers
+#
+# CONFIG_FUNCTION_TRACER is not set
+# CONFIG_IRQSOFF_TRACER is not set
+# CONFIG_SCHED_TRACER is not set
+# CONFIG_CONTEXT_SWITCH_TRACER is not set
+# CONFIG_EVENT_TRACER is not set
+# CONFIG_BOOT_TRACER is not set
+# CONFIG_TRACE_BRANCH_PROFILING is not set
+# CONFIG_STACK_TRACER is not set
+# CONFIG_KMEMTRACE is not set
+# CONFIG_WORKQUEUE_TRACER is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_DYNAMIC_DEBUG is not set
 # CONFIG_SAMPLES is not set
+CONFIG_HAVE_ARCH_KGDB=y
+CONFIG_DEBUG_VERBOSE=y
 CONFIG_DEBUG_MMRS=y
+# CONFIG_DEBUG_DOUBLEFAULT is not set
 CONFIG_DEBUG_HUNT_FOR_ZERO=y
 CONFIG_DEBUG_BFIN_HWTRACE_ON=y
 CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_OFF=y
@@ -855,33 +1116,40 @@ CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_OFF=y
 CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION=0
 # CONFIG_DEBUG_BFIN_HWTRACE_EXPAND is not set
 # CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE is not set
-# CONFIG_EARLY_PRINTK is not set
-# CONFIG_DUAL_CORE_TEST_MODULE is not set
+CONFIG_EARLY_PRINTK=y
 CONFIG_CPLB_INFO=y
 CONFIG_ACCESS_CHECK=y
+# CONFIG_BFIN_ISRAM_SELF_TEST is not set
 
 #
 # Security options
 #
 # CONFIG_KEYS is not set
 CONFIG_SECURITY=y
+# CONFIG_SECURITYFS is not set
 # CONFIG_SECURITY_NETWORK is not set
-CONFIG_SECURITY_CAPABILITIES=y
+# CONFIG_SECURITY_PATH is not set
 # CONFIG_SECURITY_FILE_CAPABILITIES is not set
+# CONFIG_SECURITY_TOMOYO is not set
 # CONFIG_CRYPTO is not set
+# CONFIG_BINARY_PRINTF is not set
 
 #
 # Library routines
 #
 CONFIG_BITREVERSE=y
+CONFIG_GENERIC_FIND_LAST_BIT=y
 CONFIG_CRC_CCITT=m
 # CONFIG_CRC16 is not set
-# CONFIG_CRC_ITU_T is not set
+# CONFIG_CRC_T10DIF is not set
+CONFIG_CRC_ITU_T=y
 CONFIG_CRC32=y
-# CONFIG_CRC7 is not set
+CONFIG_CRC7=y
 # CONFIG_LIBCRC32C is not set
 CONFIG_ZLIB_INFLATE=y
-CONFIG_PLIST=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_DECOMPRESS_LZMA=y
 CONFIG_HAS_IOMEM=y
 CONFIG_HAS_IOPORT=y
 CONFIG_HAS_DMA=y
+CONFIG_NLATTR=y
diff --git a/arch/blackfin/configs/H8606_defconfig b/arch/blackfin/configs/H8606_defconfig
index a6a7c8ede705..bc7fae3d8b83 100644
--- a/arch/blackfin/configs/H8606_defconfig
+++ b/arch/blackfin/configs/H8606_defconfig
@@ -67,6 +67,7 @@ CONFIG_BIG_ORDER_ALLOC_NOFAIL_MAGIC=3
 CONFIG_SLAB=y
 # CONFIG_SLUB is not set
 # CONFIG_SLOB is not set
+CONFIG_MMAP_ALLOW_UNINITIALIZED=y
 CONFIG_RT_MUTEXES=y
 CONFIG_TINY_SHMEM=y
 CONFIG_BASE_SMALL=0
@@ -249,6 +250,7 @@ CONFIG_SPLIT_PTLOCK_CPUS=4
 # CONFIG_RESOURCES_64BIT is not set
 CONFIG_ZONE_DMA_FLAG=1
 CONFIG_LARGE_ALLOCS=y
+CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0
 CONFIG_BFIN_GPTIMERS=y
 # CONFIG_DMA_UNCACHED_2M is not set
 CONFIG_DMA_UNCACHED_1M=y
diff --git a/arch/blackfin/configs/IP0X_defconfig b/arch/blackfin/configs/IP0X_defconfig
index 1ec9ae2e964b..a7e49d631229 100644
--- a/arch/blackfin/configs/IP0X_defconfig
+++ b/arch/blackfin/configs/IP0X_defconfig
@@ -68,6 +68,7 @@ CONFIG_BIG_ORDER_ALLOC_NOFAIL_MAGIC=3
 CONFIG_SLAB=y
 # CONFIG_SLUB is not set
 # CONFIG_SLOB is not set
+CONFIG_MMAP_ALLOW_UNINITIALIZED=y
 CONFIG_RT_MUTEXES=y
 CONFIG_TINY_SHMEM=y
 CONFIG_BASE_SMALL=0
@@ -261,6 +262,7 @@ CONFIG_SPLIT_PTLOCK_CPUS=4
 # CONFIG_RESOURCES_64BIT is not set
 CONFIG_ZONE_DMA_FLAG=1
 CONFIG_LARGE_ALLOCS=y
+CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0
 # CONFIG_BFIN_GPTIMERS is not set
 # CONFIG_DMA_UNCACHED_2M is not set
 CONFIG_DMA_UNCACHED_1M=y
diff --git a/arch/blackfin/configs/PNAV-10_defconfig b/arch/blackfin/configs/PNAV-10_defconfig
index ff377fae061b..67d12768602a 100644
--- a/arch/blackfin/configs/PNAV-10_defconfig
+++ b/arch/blackfin/configs/PNAV-10_defconfig
@@ -63,6 +63,7 @@ CONFIG_COMPAT_BRK=y
 CONFIG_SLAB=y
 # CONFIG_SLUB is not set
 # CONFIG_SLOB is not set
+CONFIG_MMAP_ALLOW_UNINITIALIZED=y
 # CONFIG_PROFILING is not set
 # CONFIG_MARKERS is not set
 CONFIG_HAVE_OPROFILE=y
@@ -285,6 +286,7 @@ CONFIG_SPLIT_PTLOCK_CPUS=4
 # CONFIG_PHYS_ADDR_T_64BIT is not set
 CONFIG_ZONE_DMA_FLAG=1
 CONFIG_VIRT_TO_BUS=y
+CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0
 CONFIG_BFIN_GPTIMERS=y
 # CONFIG_DMA_UNCACHED_4M is not set
 # CONFIG_DMA_UNCACHED_2M is not set
diff --git a/arch/blackfin/configs/SRV1_defconfig b/arch/blackfin/configs/SRV1_defconfig
index 814f9cacf407..52bfa6bf18da 100644
--- a/arch/blackfin/configs/SRV1_defconfig
+++ b/arch/blackfin/configs/SRV1_defconfig
@@ -72,6 +72,7 @@ CONFIG_BIG_ORDER_ALLOC_NOFAIL_MAGIC=3
 CONFIG_SLAB=y
 # CONFIG_SLUB is not set
 # CONFIG_SLOB is not set
+CONFIG_MMAP_ALLOW_UNINITIALIZED=y
 CONFIG_RT_MUTEXES=y
 CONFIG_TINY_SHMEM=y
 CONFIG_BASE_SMALL=0
@@ -271,6 +272,7 @@ CONFIG_SPLIT_PTLOCK_CPUS=4
 # CONFIG_RESOURCES_64BIT is not set
 CONFIG_ZONE_DMA_FLAG=1
 CONFIG_LARGE_ALLOCS=y
+CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0
 CONFIG_DMA_UNCACHED_2M=y
 # CONFIG_DMA_UNCACHED_1M is not set
 # CONFIG_DMA_UNCACHED_NONE is not set
@@ -700,7 +702,7 @@ CONFIG_INPUT_MISC=y
 # CONFIG_INPUT_YEALINK is not set
 CONFIG_INPUT_UINPUT=y
 # CONFIG_BF53X_PFBUTTONS is not set
-# CONFIG_TWI_KEYPAD is not set
+# CONFIG_INPUT_PCF8574 is not set
 
 #
 # Hardware I/O ports
diff --git a/arch/blackfin/configs/TCM-BF537_defconfig b/arch/blackfin/configs/TCM-BF537_defconfig
index 375e75a27abc..60adfad54db9 100644
--- a/arch/blackfin/configs/TCM-BF537_defconfig
+++ b/arch/blackfin/configs/TCM-BF537_defconfig
@@ -1,13 +1,13 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.28-rc2
-# Tue Jan  6 09:22:17 2009
+# Linux kernel version: 2.6.30.5
 #
 # CONFIG_MMU is not set
 # CONFIG_FPU is not set
 CONFIG_RWSEM_GENERIC_SPINLOCK=y
 # CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
 CONFIG_BLACKFIN=y
+CONFIG_GENERIC_BUG=y
 CONFIG_ZONE_DMA=y
 CONFIG_GENERIC_FIND_NEXT_BIT=y
 CONFIG_GENERIC_HWEIGHT=y
@@ -16,6 +16,9 @@ CONFIG_GENERIC_IRQ_PROBE=y
 CONFIG_GENERIC_GPIO=y
 CONFIG_FORCE_MAX_ZONEORDER=14
 CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
 CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
 
 #
@@ -26,49 +29,72 @@ CONFIG_BROKEN_ON_SMP=y
 CONFIG_INIT_ENV_ARG_LIMIT=32
 CONFIG_LOCALVERSION=""
 CONFIG_LOCALVERSION_AUTO=y
+CONFIG_HAVE_KERNEL_GZIP=y
+CONFIG_HAVE_KERNEL_BZIP2=y
+CONFIG_HAVE_KERNEL_LZMA=y
+# CONFIG_KERNEL_GZIP is not set
+# CONFIG_KERNEL_BZIP2 is not set
+CONFIG_KERNEL_LZMA=y
 CONFIG_SYSVIPC=y
 CONFIG_SYSVIPC_SYSCTL=y
+# CONFIG_POSIX_MQUEUE is not set
 # CONFIG_BSD_PROCESS_ACCT is not set
+# CONFIG_TASKSTATS is not set
+# CONFIG_AUDIT is not set
+
+#
+# RCU Subsystem
+#
+CONFIG_CLASSIC_RCU=y
+# CONFIG_TREE_RCU is not set
+# CONFIG_PREEMPT_RCU is not set
+# CONFIG_TREE_RCU_TRACE is not set
+# CONFIG_PREEMPT_RCU_TRACE is not set
 CONFIG_IKCONFIG=y
 CONFIG_IKCONFIG_PROC=y
 CONFIG_LOG_BUF_SHIFT=14
-# CONFIG_CGROUPS is not set
 # CONFIG_GROUP_SCHED is not set
+# CONFIG_CGROUPS is not set
 # CONFIG_SYSFS_DEPRECATED_V2 is not set
 # CONFIG_RELAY is not set
 # CONFIG_NAMESPACES is not set
-# CONFIG_BLK_DEV_INITRD is not set
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+# CONFIG_RD_GZIP is not set
+# CONFIG_RD_BZIP2 is not set
+CONFIG_RD_LZMA=y
 # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
-# CONFIG_SYSCTL is not set
+CONFIG_SYSCTL=y
+CONFIG_ANON_INODES=y
 CONFIG_EMBEDDED=y
 # CONFIG_UID16 is not set
 # CONFIG_SYSCTL_SYSCALL is not set
 CONFIG_KALLSYMS=y
 # CONFIG_KALLSYMS_EXTRA_PASS is not set
-# CONFIG_HOTPLUG is not set
+# CONFIG_STRIP_ASM_SYMS is not set
+CONFIG_HOTPLUG=y
 CONFIG_PRINTK=y
 CONFIG_BUG=y
 # CONFIG_ELF_CORE is not set
-CONFIG_COMPAT_BRK=y
 CONFIG_BASE_FULL=y
 # CONFIG_FUTEX is not set
-CONFIG_ANON_INODES=y
 CONFIG_EPOLL=y
 CONFIG_SIGNALFD=y
 CONFIG_TIMERFD=y
 CONFIG_EVENTFD=y
 # CONFIG_AIO is not set
 CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_COMPAT_BRK=y
 CONFIG_SLAB=y
 # CONFIG_SLUB is not set
 # CONFIG_SLOB is not set
+CONFIG_MMAP_ALLOW_UNINITIALIZED=y
 # CONFIG_PROFILING is not set
 # CONFIG_MARKERS is not set
 CONFIG_HAVE_OPROFILE=y
+# CONFIG_SLOW_WORK is not set
 # CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
 CONFIG_SLABINFO=y
-CONFIG_RT_MUTEXES=y
-CONFIG_TINY_SHMEM=y
 CONFIG_BASE_SMALL=0
 CONFIG_MODULES=y
 # CONFIG_MODULE_FORCE_LOAD is not set
@@ -76,11 +102,8 @@ CONFIG_MODULE_UNLOAD=y
 # CONFIG_MODULE_FORCE_UNLOAD is not set
 # CONFIG_MODVERSIONS is not set
 # CONFIG_MODULE_SRCVERSION_ALL is not set
-CONFIG_KMOD=y
 CONFIG_BLOCK=y
 # CONFIG_LBD is not set
-# CONFIG_BLK_DEV_IO_TRACE is not set
-# CONFIG_LSF is not set
 # CONFIG_BLK_DEV_BSG is not set
 # CONFIG_BLK_DEV_INTEGRITY is not set
 
@@ -96,7 +119,6 @@ CONFIG_IOSCHED_CFQ=y
 # CONFIG_DEFAULT_CFQ is not set
 CONFIG_DEFAULT_NOOP=y
 CONFIG_DEFAULT_IOSCHED="noop"
-CONFIG_CLASSIC_RCU=y
 CONFIG_PREEMPT_NONE=y
 # CONFIG_PREEMPT_VOLUNTARY is not set
 # CONFIG_PREEMPT is not set
@@ -128,10 +150,15 @@ CONFIG_BF537=y
 # CONFIG_BF538 is not set
 # CONFIG_BF539 is not set
 # CONFIG_BF542 is not set
+# CONFIG_BF542M is not set
 # CONFIG_BF544 is not set
+# CONFIG_BF544M is not set
 # CONFIG_BF547 is not set
+# CONFIG_BF547M is not set
 # CONFIG_BF548 is not set
+# CONFIG_BF548M is not set
 # CONFIG_BF549 is not set
+# CONFIG_BF549M is not set
 # CONFIG_BF561 is not set
 CONFIG_BF_REV_MIN=2
 CONFIG_BF_REV_MAX=3
@@ -173,11 +200,11 @@ CONFIG_IRQ_MEM_DMA1=13
 CONFIG_IRQ_WATCH=13
 CONFIG_IRQ_SPI=10
 # CONFIG_BFIN537_STAMP is not set
-# CONFIG_BFIN537_BLUETECHNIX_CM is not set
+# CONFIG_BFIN537_BLUETECHNIX_CM_E is not set
+# CONFIG_BFIN537_BLUETECHNIX_CM_U is not set
 CONFIG_BFIN537_BLUETECHNIX_TCM=y
 # CONFIG_PNAV10 is not set
 # CONFIG_CAMSIG_MINOTAUR is not set
-# CONFIG_GENERIC_BF537_BOARD is not set
 
 #
 # BF537 Specific Configuration
@@ -223,7 +250,10 @@ CONFIG_HZ=250
 # CONFIG_SCHED_HRTICK is not set
 CONFIG_GENERIC_TIME=y
 CONFIG_GENERIC_CLOCKEVENTS=y
+# CONFIG_TICKSOURCE_GPTMR0 is not set
+CONFIG_TICKSOURCE_CORETMR=y
 # CONFIG_CYCLES_CLOCKSOURCE is not set
+# CONFIG_GPTMR0_CLOCKSOURCE is not set
 # CONFIG_NO_HZ is not set
 # CONFIG_HIGH_RES_TIMERS is not set
 CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
@@ -273,10 +303,12 @@ CONFIG_FLATMEM=y
 CONFIG_FLAT_NODE_MEM_MAP=y
 CONFIG_PAGEFLAGS_EXTENDED=y
 CONFIG_SPLIT_PTLOCK_CPUS=4
-# CONFIG_RESOURCES_64BIT is not set
 # CONFIG_PHYS_ADDR_T_64BIT is not set
 CONFIG_ZONE_DMA_FLAG=1
 CONFIG_VIRT_TO_BUS=y
+CONFIG_UNEVICTABLE_LRU=y
+CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
+CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0
 # CONFIG_BFIN_GPTIMERS is not set
 # CONFIG_DMA_UNCACHED_4M is not set
 # CONFIG_DMA_UNCACHED_2M is not set
@@ -287,10 +319,9 @@ CONFIG_DMA_UNCACHED_1M=y
 # Cache Support
 #
 CONFIG_BFIN_ICACHE=y
-# CONFIG_BFIN_ICACHE_LOCK is not set
+CONFIG_BFIN_EXTMEM_ICACHEABLE=y
 CONFIG_BFIN_DCACHE=y
 # CONFIG_BFIN_DCACHE_BANKA is not set
-CONFIG_BFIN_EXTMEM_ICACHEABLE=y
 CONFIG_BFIN_EXTMEM_DCACHEABLE=y
 CONFIG_BFIN_EXTMEM_WRITEBACK=y
 # CONFIG_BFIN_EXTMEM_WRITETHROUGH is not set
@@ -301,7 +332,7 @@ CONFIG_BFIN_EXTMEM_WRITEBACK=y
 # CONFIG_MPU is not set
 
 #
-# Asynchonous Memory Configuration
+# Asynchronous Memory Configuration
 #
 
 #
@@ -327,6 +358,7 @@ CONFIG_BANK_3=0xFFC2
 # Bus options (PCI, PCMCIA, EISA, MCA, ISA)
 #
 # CONFIG_ARCH_SUPPORTS_MSI is not set
+# CONFIG_PCCARD is not set
 
 #
 # Executable file formats
@@ -343,13 +375,83 @@ CONFIG_BINFMT_SHARED_FLAT=y
 #
 # CONFIG_PM is not set
 CONFIG_ARCH_SUSPEND_POSSIBLE=y
-# CONFIG_PM_WAKEUP_BY_GPIO is not set
 
 #
 # CPU Frequency scaling
 #
 # CONFIG_CPU_FREQ is not set
-# CONFIG_NET is not set
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+# CONFIG_PACKET_MMAP is not set
+CONFIG_UNIX=y
+CONFIG_XFRM=y
+# CONFIG_XFRM_USER is not set
+# CONFIG_XFRM_SUB_POLICY is not set
+# CONFIG_XFRM_MIGRATE is not set
+# CONFIG_XFRM_STATISTICS is not set
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+# CONFIG_IP_MULTICAST is not set
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
+# CONFIG_IP_PNP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
+# CONFIG_INET_TUNNEL is not set
+CONFIG_INET_XFRM_MODE_TRANSPORT=y
+CONFIG_INET_XFRM_MODE_TUNNEL=y
+CONFIG_INET_XFRM_MODE_BEET=y
+CONFIG_INET_LRO=y
+# CONFIG_INET_DIAG is not set
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+# CONFIG_IPV6 is not set
+# CONFIG_NETWORK_SECMARK is not set
+# CONFIG_NETFILTER is not set
+# CONFIG_IP_DCCP is not set
+# CONFIG_IP_SCTP is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_NET_DSA is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_PHONET is not set
+# CONFIG_NET_SCHED is not set
+# CONFIG_DCB is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+# CONFIG_AF_RXRPC is not set
+# CONFIG_WIRELESS is not set
+# CONFIG_WIMAX is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
 
 #
 # Device Drivers
@@ -358,15 +460,21 @@ CONFIG_ARCH_SUSPEND_POSSIBLE=y
 #
 # Generic Driver Options
 #
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 CONFIG_STANDALONE=y
 CONFIG_PREVENT_FIRMWARE_BUILD=y
+CONFIG_FW_LOADER=y
+CONFIG_FIRMWARE_IN_KERNEL=y
+CONFIG_EXTRA_FIRMWARE=""
 # CONFIG_SYS_HYPERVISOR is not set
+# CONFIG_CONNECTOR is not set
 CONFIG_MTD=y
 # CONFIG_MTD_DEBUG is not set
+# CONFIG_MTD_TESTS is not set
 # CONFIG_MTD_CONCAT is not set
 CONFIG_MTD_PARTITIONS=y
 # CONFIG_MTD_REDBOOT_PARTS is not set
-# CONFIG_MTD_CMDLINE_PARTS is not set
+CONFIG_MTD_CMDLINE_PARTS=y
 # CONFIG_MTD_AR7_PARTS is not set
 
 #
@@ -402,9 +510,10 @@ CONFIG_MTD_CFI_I2=y
 CONFIG_MTD_CFI_INTELEXT=y
 # CONFIG_MTD_CFI_AMDSTD is not set
 # CONFIG_MTD_CFI_STAA is not set
+# CONFIG_MTD_PSD4256G is not set
 CONFIG_MTD_CFI_UTIL=y
 CONFIG_MTD_RAM=y
-# CONFIG_MTD_ROM is not set
+CONFIG_MTD_ROM=m
 # CONFIG_MTD_ABSENT is not set
 
 #
@@ -413,7 +522,7 @@ CONFIG_MTD_RAM=y
 CONFIG_MTD_COMPLEX_MAPPINGS=y
 # CONFIG_MTD_PHYSMAP is not set
 CONFIG_MTD_GPIO_ADDR=y
-CONFIG_MTD_UCLINUX=y
+# CONFIG_MTD_UCLINUX is not set
 # CONFIG_MTD_PLATRAM is not set
 
 #
@@ -436,6 +545,11 @@ CONFIG_MTD_UCLINUX=y
 # CONFIG_MTD_ONENAND is not set
 
 #
+# LPDDR flash memory drivers
+#
+# CONFIG_MTD_LPDDR is not set
+
+#
 # UBI - Unsorted block images
 #
 # CONFIG_MTD_UBI is not set
@@ -443,15 +557,23 @@ CONFIG_MTD_UCLINUX=y
 CONFIG_BLK_DEV=y
 # CONFIG_BLK_DEV_COW_COMMON is not set
 # CONFIG_BLK_DEV_LOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
 CONFIG_BLK_DEV_RAM=y
 CONFIG_BLK_DEV_RAM_COUNT=16
 CONFIG_BLK_DEV_RAM_SIZE=4096
 # CONFIG_BLK_DEV_XIP is not set
 # CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
 # CONFIG_BLK_DEV_HD is not set
 CONFIG_MISC_DEVICES=y
-# CONFIG_EEPROM_93CX6 is not set
 # CONFIG_ENCLOSURE_SERVICES is not set
+# CONFIG_C2PORT is not set
+
+#
+# EEPROM support
+#
+# CONFIG_EEPROM_AT25 is not set
+# CONFIG_EEPROM_93CX6 is not set
 CONFIG_HAVE_IDE=y
 # CONFIG_IDE is not set
 
@@ -464,6 +586,74 @@ CONFIG_HAVE_IDE=y
 # CONFIG_SCSI_NETLINK is not set
 # CONFIG_ATA is not set
 # CONFIG_MD is not set
+CONFIG_NETDEVICES=y
+CONFIG_COMPAT_NET_DEV_OPS=y
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_VETH is not set
+CONFIG_PHYLIB=y
+
+#
+# MII PHY device drivers
+#
+# CONFIG_MARVELL_PHY is not set
+# CONFIG_DAVICOM_PHY is not set
+# CONFIG_QSEMI_PHY is not set
+# CONFIG_LXT_PHY is not set
+# CONFIG_CICADA_PHY is not set
+# CONFIG_VITESSE_PHY is not set
+# CONFIG_SMSC_PHY is not set
+# CONFIG_BROADCOM_PHY is not set
+# CONFIG_ICPLUS_PHY is not set
+# CONFIG_REALTEK_PHY is not set
+# CONFIG_NATIONAL_PHY is not set
+# CONFIG_STE10XP is not set
+# CONFIG_LSI_ET1011C_PHY is not set
+# CONFIG_FIXED_PHY is not set
+# CONFIG_MDIO_BITBANG is not set
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
+CONFIG_BFIN_MAC=y
+CONFIG_BFIN_MAC_USE_L1=y
+CONFIG_BFIN_TX_DESC_NUM=10
+CONFIG_BFIN_RX_DESC_NUM=20
+# CONFIG_BFIN_MAC_RMII is not set
+# CONFIG_SMC91X is not set
+# CONFIG_DM9000 is not set
+# CONFIG_ENC28J60 is not set
+# CONFIG_ETHOC is not set
+# CONFIG_SMSC911X is not set
+# CONFIG_DNET is not set
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
+# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
+# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
+# CONFIG_B44 is not set
+# CONFIG_NETDEV_1000 is not set
+# CONFIG_NETDEV_10000 is not set
+
+#
+# Wireless LAN
+#
+# CONFIG_WLAN_PRE80211 is not set
+# CONFIG_WLAN_80211 is not set
+
+#
+# Enable WiMAX (Networking options) to see the WiMAX drivers
+#
+# CONFIG_WAN is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_ISDN is not set
 # CONFIG_PHONE is not set
 
 #
@@ -480,15 +670,12 @@ CONFIG_HAVE_IDE=y
 #
 # Character devices
 #
-# CONFIG_AD9960 is not set
-# CONFIG_SPI_ADC_BF533 is not set
-# CONFIG_BF5xx_PPIFCD is not set
+CONFIG_BFIN_DMA_INTERFACE=m
+# CONFIG_BFIN_PPI is not set
+# CONFIG_BFIN_PPIFCD is not set
 # CONFIG_BFIN_SIMPLE_TIMER is not set
-# CONFIG_BF5xx_PPI is not set
+# CONFIG_BFIN_SPI_ADC is not set
 CONFIG_BFIN_SPORT=y
-# CONFIG_BFIN_TIMER_LATENCY is not set
-CONFIG_BFIN_DMA_INTERFACE=m
-# CONFIG_SIMPLE_GPIO is not set
 # CONFIG_VT is not set
 # CONFIG_DEVKMEM is not set
 # CONFIG_BFIN_JTAG_COMM is not set
@@ -502,6 +689,7 @@ CONFIG_BFIN_DMA_INTERFACE=m
 #
 # Non-8250 serial port support
 #
+# CONFIG_SERIAL_MAX3100 is not set
 CONFIG_SERIAL_BFIN=y
 CONFIG_SERIAL_BFIN_CONSOLE=y
 CONFIG_SERIAL_BFIN_DMA=y
@@ -514,6 +702,7 @@ CONFIG_SERIAL_CORE=y
 CONFIG_SERIAL_CORE_CONSOLE=y
 # CONFIG_SERIAL_BFIN_SPORT is not set
 CONFIG_UNIX98_PTYS=y
+# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
 # CONFIG_LEGACY_PTYS is not set
 
 #
@@ -534,39 +723,17 @@ CONFIG_SPI_MASTER=y
 #
 CONFIG_SPI_BFIN=y
 # CONFIG_SPI_BFIN_LOCK is not set
+# CONFIG_SPI_BFIN_SPORT is not set
 # CONFIG_SPI_BITBANG is not set
+# CONFIG_SPI_GPIO is not set
 
 #
 # SPI Protocol Masters
 #
-# CONFIG_EEPROM_AT25 is not set
 # CONFIG_SPI_SPIDEV is not set
 # CONFIG_SPI_TLE62X0 is not set
 CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
-CONFIG_GPIOLIB=y
-# CONFIG_DEBUG_GPIO is not set
-CONFIG_GPIO_SYSFS=y
-
-#
-# Memory mapped GPIO expanders:
-#
-
-#
-# I2C GPIO expanders:
-#
-# CONFIG_GPIO_MAX732X is not set
-# CONFIG_GPIO_PCA953X is not set
-# CONFIG_GPIO_PCF857X is not set
-
-#
-# PCI GPIO expanders:
-#
-
-#
-# SPI GPIO expanders:
-#
-# CONFIG_GPIO_MAX7301 is not set
-# CONFIG_GPIO_MCP23S08 is not set
+# CONFIG_GPIOLIB is not set
 # CONFIG_W1 is not set
 # CONFIG_POWER_SUPPLY is not set
 # CONFIG_HWMON is not set
@@ -580,6 +747,12 @@ CONFIG_WATCHDOG=y
 #
 # CONFIG_SOFT_WATCHDOG is not set
 CONFIG_BFIN_WDT=y
+CONFIG_SSB_POSSIBLE=y
+
+#
+# Sonics Silicon Backplane
+#
+# CONFIG_SSB is not set
 
 #
 # Multifunction device drivers
@@ -588,7 +761,7 @@ CONFIG_BFIN_WDT=y
 # CONFIG_MFD_SM501 is not set
 # CONFIG_HTC_PASIC3 is not set
 # CONFIG_MFD_TMIO is not set
-# CONFIG_MFD_WM8400 is not set
+# CONFIG_REGULATOR is not set
 
 #
 # Multimedia devices
@@ -598,6 +771,7 @@ CONFIG_BFIN_WDT=y
 # Multimedia core support
 #
 # CONFIG_VIDEO_DEV is not set
+# CONFIG_DVB_CORE is not set
 # CONFIG_VIDEO_MEDIA is not set
 
 #
@@ -618,13 +792,81 @@ CONFIG_BFIN_WDT=y
 #
 # CONFIG_DISPLAY_SUPPORT is not set
 # CONFIG_SOUND is not set
-# CONFIG_USB_SUPPORT is not set
-# CONFIG_MMC is not set
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_ARCH_HAS_HCD=y
+# CONFIG_USB_ARCH_HAS_OHCI is not set
+# CONFIG_USB_ARCH_HAS_EHCI is not set
+# CONFIG_USB is not set
+# CONFIG_USB_OTG_WHITELIST is not set
+# CONFIG_USB_OTG_BLACKLIST_HUB is not set
+# CONFIG_USB_GADGET_MUSB_HDRC is not set
+
+#
+# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
+#
+CONFIG_USB_GADGET=y
+# CONFIG_USB_GADGET_DEBUG_FILES is not set
+# CONFIG_USB_GADGET_DEBUG_FS is not set
+CONFIG_USB_GADGET_VBUS_DRAW=2
+CONFIG_USB_GADGET_SELECTED=y
+# CONFIG_USB_GADGET_AT91 is not set
+# CONFIG_USB_GADGET_ATMEL_USBA is not set
+# CONFIG_USB_GADGET_FSL_USB2 is not set
+# CONFIG_USB_GADGET_LH7A40X is not set
+# CONFIG_USB_GADGET_OMAP is not set
+# CONFIG_USB_GADGET_PXA25X is not set
+# CONFIG_USB_GADGET_PXA27X is not set
+# CONFIG_USB_GADGET_S3C2410 is not set
+# CONFIG_USB_GADGET_IMX is not set
+# CONFIG_USB_GADGET_M66592 is not set
+# CONFIG_USB_GADGET_AMD5536UDC is not set
+# CONFIG_USB_GADGET_FSL_QE is not set
+# CONFIG_USB_GADGET_CI13XXX is not set
+CONFIG_USB_GADGET_NET2272=y
+CONFIG_USB_NET2272=y
+# CONFIG_USB_GADGET_NET2280 is not set
+# CONFIG_USB_GADGET_GOKU is not set
+# CONFIG_USB_GADGET_DUMMY_HCD is not set
+CONFIG_USB_GADGET_DUALSPEED=y
+# CONFIG_USB_ZERO is not set
+# CONFIG_USB_AUDIO is not set
+CONFIG_USB_ETH=y
+CONFIG_USB_ETH_RNDIS=y
+# CONFIG_USB_GADGETFS is not set
+# CONFIG_USB_FILE_STORAGE is not set
+# CONFIG_USB_G_SERIAL is not set
+# CONFIG_USB_MIDI_GADGET is not set
+# CONFIG_USB_G_PRINTER is not set
+# CONFIG_USB_CDC_COMPOSITE is not set
+
+#
+# OTG and related infrastructure
+#
+# CONFIG_USB_GPIO_VBUS is not set
+# CONFIG_NOP_USB_XCEIV is not set
+CONFIG_MMC=y
+# CONFIG_MMC_DEBUG is not set
+# CONFIG_MMC_UNSAFE_RESUME is not set
+
+#
+# MMC/SD/SDIO Card Drivers
+#
+CONFIG_MMC_BLOCK=y
+CONFIG_MMC_BLOCK_BOUNCE=y
+# CONFIG_SDIO_UART is not set
+# CONFIG_MMC_TEST is not set
+
+#
+# MMC/SD/SDIO Host Controller Drivers
+#
+# CONFIG_MMC_SDHCI is not set
+CONFIG_MMC_SPI=m
 # CONFIG_MEMSTICK is not set
 # CONFIG_NEW_LEDS is not set
 # CONFIG_ACCESSIBILITY is not set
 # CONFIG_RTC_CLASS is not set
 # CONFIG_DMADEVICES is not set
+# CONFIG_AUXDISPLAY is not set
 # CONFIG_UIO is not set
 # CONFIG_STAGING is not set
 
@@ -641,8 +883,10 @@ CONFIG_FS_MBCACHE=y
 # CONFIG_REISERFS_FS is not set
 # CONFIG_JFS_FS is not set
 # CONFIG_FS_POSIX_ACL is not set
-CONFIG_FILE_LOCKING=y
 # CONFIG_XFS_FS is not set
+# CONFIG_OCFS2_FS is not set
+# CONFIG_BTRFS_FS is not set
+CONFIG_FILE_LOCKING=y
 # CONFIG_DNOTIFY is not set
 CONFIG_INOTIFY=y
 CONFIG_INOTIFY_USER=y
@@ -652,6 +896,11 @@ CONFIG_INOTIFY_USER=y
 # CONFIG_FUSE_FS is not set
 
 #
+# Caches
+#
+# CONFIG_FSCACHE is not set
+
+#
 # CD-ROM/DVD Filesystems
 #
 # CONFIG_ISO9660_FS is not set
@@ -660,8 +909,11 @@ CONFIG_INOTIFY_USER=y
 #
 # DOS/FAT/NT Filesystems
 #
-# CONFIG_MSDOS_FS is not set
-# CONFIG_VFAT_FS is not set
+CONFIG_FAT_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
 # CONFIG_NTFS_FS is not set
 
 #
@@ -673,10 +925,7 @@ CONFIG_SYSFS=y
 # CONFIG_TMPFS is not set
 # CONFIG_HUGETLB_PAGE is not set
 # CONFIG_CONFIGFS_FS is not set
-
-#
-# Miscellaneous filesystems
-#
+CONFIG_MISC_FILESYSTEMS=y
 # CONFIG_ADFS_FS is not set
 # CONFIG_AFFS_FS is not set
 # CONFIG_HFS_FS is not set
@@ -684,9 +933,19 @@ CONFIG_SYSFS=y
 # CONFIG_BEFS_FS is not set
 # CONFIG_BFS_FS is not set
 # CONFIG_EFS_FS is not set
-# CONFIG_YAFFS_FS is not set
-# CONFIG_JFFS2_FS is not set
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_DEBUG=0
+CONFIG_JFFS2_FS_WRITEBUFFER=y
+# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
+# CONFIG_JFFS2_SUMMARY is not set
+# CONFIG_JFFS2_FS_XATTR is not set
+# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
+CONFIG_JFFS2_ZLIB=y
+# CONFIG_JFFS2_LZO is not set
+CONFIG_JFFS2_RTIME=y
+# CONFIG_JFFS2_RUBIN is not set
 # CONFIG_CRAMFS is not set
+# CONFIG_SQUASHFS is not set
 # CONFIG_VXFS_FS is not set
 # CONFIG_MINIX_FS is not set
 # CONFIG_OMFS_FS is not set
@@ -695,13 +954,62 @@ CONFIG_SYSFS=y
 # CONFIG_ROMFS_FS is not set
 # CONFIG_SYSV_FS is not set
 # CONFIG_UFS_FS is not set
+# CONFIG_NILFS2_FS is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+# CONFIG_NFS_FS is not set
+# CONFIG_NFSD is not set
+# CONFIG_SMB_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
 
 #
 # Partition Types
 #
 # CONFIG_PARTITION_ADVANCED is not set
 CONFIG_MSDOS_PARTITION=y
-# CONFIG_NLS is not set
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="iso8859-1"
+CONFIG_NLS_CODEPAGE_437=y
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+# CONFIG_NLS_ASCII is not set
+CONFIG_NLS_ISO8859_1=y
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+# CONFIG_NLS_UTF8 is not set
+# CONFIG_DLM is not set
 
 #
 # Kernel hacking
@@ -714,12 +1022,30 @@ CONFIG_FRAME_WARN=1024
 # CONFIG_UNUSED_SYMBOLS is not set
 CONFIG_DEBUG_FS=y
 # CONFIG_HEADERS_CHECK is not set
+CONFIG_DEBUG_SECTION_MISMATCH=y
 # CONFIG_DEBUG_KERNEL is not set
-CONFIG_DEBUG_BUGVERBOSE=y
+# CONFIG_DEBUG_BUGVERBOSE is not set
 # CONFIG_DEBUG_MEMORY_INIT is not set
 # CONFIG_RCU_CPU_STALL_DETECTOR is not set
-# CONFIG_SYSCTL_SYSCALL_CHECK is not set
-# CONFIG_DYNAMIC_PRINTK_DEBUG is not set
+CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
+CONFIG_TRACING_SUPPORT=y
+
+#
+# Tracers
+#
+# CONFIG_FUNCTION_TRACER is not set
+# CONFIG_IRQSOFF_TRACER is not set
+# CONFIG_SCHED_TRACER is not set
+# CONFIG_CONTEXT_SWITCH_TRACER is not set
+# CONFIG_EVENT_TRACER is not set
+# CONFIG_BOOT_TRACER is not set
+# CONFIG_TRACE_BRANCH_PROFILING is not set
+# CONFIG_STACK_TRACER is not set
+# CONFIG_KMEMTRACE is not set
+# CONFIG_WORKQUEUE_TRACER is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_DYNAMIC_DEBUG is not set
 # CONFIG_SAMPLES is not set
 CONFIG_HAVE_ARCH_KGDB=y
 CONFIG_DEBUG_VERBOSE=y
@@ -733,9 +1059,10 @@ CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_OFF=y
 CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION=0
 # CONFIG_DEBUG_BFIN_HWTRACE_EXPAND is not set
 # CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE is not set
-# CONFIG_EARLY_PRINTK is not set
+CONFIG_EARLY_PRINTK=y
 CONFIG_CPLB_INFO=y
 CONFIG_ACCESS_CHECK=y
+# CONFIG_BFIN_ISRAM_SELF_TEST is not set
 
 #
 # Security options
@@ -744,20 +1071,110 @@ CONFIG_ACCESS_CHECK=y
 # CONFIG_SECURITY is not set
 # CONFIG_SECURITYFS is not set
 # CONFIG_SECURITY_FILE_CAPABILITIES is not set
-# CONFIG_CRYPTO is not set
+CONFIG_CRYPTO=y
+
+#
+# Crypto core or helper
+#
+# CONFIG_CRYPTO_FIPS is not set
+# CONFIG_CRYPTO_MANAGER is not set
+# CONFIG_CRYPTO_MANAGER2 is not set
+# CONFIG_CRYPTO_GF128MUL is not set
+# CONFIG_CRYPTO_NULL is not set
+# CONFIG_CRYPTO_CRYPTD is not set
+# CONFIG_CRYPTO_AUTHENC is not set
+# CONFIG_CRYPTO_TEST is not set
+
+#
+# Authenticated Encryption with Associated Data
+#
+# CONFIG_CRYPTO_CCM is not set
+# CONFIG_CRYPTO_GCM is not set
+# CONFIG_CRYPTO_SEQIV is not set
+
+#
+# Block modes
+#
+# CONFIG_CRYPTO_CBC is not set
+# CONFIG_CRYPTO_CTR is not set
+# CONFIG_CRYPTO_CTS is not set
+# CONFIG_CRYPTO_ECB is not set
+# CONFIG_CRYPTO_LRW is not set
+# CONFIG_CRYPTO_PCBC is not set
+# CONFIG_CRYPTO_XTS is not set
+
+#
+# Hash modes
+#
+# CONFIG_CRYPTO_HMAC is not set
+# CONFIG_CRYPTO_XCBC is not set
+
+#
+# Digest
+#
+# CONFIG_CRYPTO_CRC32C is not set
+# CONFIG_CRYPTO_MD4 is not set
+# CONFIG_CRYPTO_MD5 is not set
+# CONFIG_CRYPTO_MICHAEL_MIC is not set
+# CONFIG_CRYPTO_RMD128 is not set
+# CONFIG_CRYPTO_RMD160 is not set
+# CONFIG_CRYPTO_RMD256 is not set
+# CONFIG_CRYPTO_RMD320 is not set
+# CONFIG_CRYPTO_SHA1 is not set
+# CONFIG_CRYPTO_SHA256 is not set
+# CONFIG_CRYPTO_SHA512 is not set
+# CONFIG_CRYPTO_TGR192 is not set
+# CONFIG_CRYPTO_WP512 is not set
+
+#
+# Ciphers
+#
+# CONFIG_CRYPTO_AES is not set
+# CONFIG_CRYPTO_ANUBIS is not set
+# CONFIG_CRYPTO_ARC4 is not set
+# CONFIG_CRYPTO_BLOWFISH is not set
+# CONFIG_CRYPTO_CAMELLIA is not set
+# CONFIG_CRYPTO_CAST5 is not set
+# CONFIG_CRYPTO_CAST6 is not set
+# CONFIG_CRYPTO_DES is not set
+# CONFIG_CRYPTO_FCRYPT is not set
+# CONFIG_CRYPTO_KHAZAD is not set
+# CONFIG_CRYPTO_SALSA20 is not set
+# CONFIG_CRYPTO_SEED is not set
+# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_TEA is not set
+# CONFIG_CRYPTO_TWOFISH is not set
+
+#
+# Compression
+#
+# CONFIG_CRYPTO_DEFLATE is not set
+# CONFIG_CRYPTO_ZLIB is not set
+# CONFIG_CRYPTO_LZO is not set
+
+#
+# Random Number Generation
+#
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
+CONFIG_CRYPTO_HW=y
+# CONFIG_BINARY_PRINTF is not set
 
 #
 # Library routines
 #
+CONFIG_BITREVERSE=y
+CONFIG_GENERIC_FIND_LAST_BIT=y
 # CONFIG_CRC_CCITT is not set
 # CONFIG_CRC16 is not set
 # CONFIG_CRC_T10DIF is not set
-# CONFIG_CRC_ITU_T is not set
-# CONFIG_CRC32 is not set
-# CONFIG_CRC7 is not set
+CONFIG_CRC_ITU_T=y
+CONFIG_CRC32=y
+CONFIG_CRC7=y
 # CONFIG_LIBCRC32C is not set
 CONFIG_ZLIB_INFLATE=y
-CONFIG_PLIST=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_DECOMPRESS_LZMA=y
 CONFIG_HAS_IOMEM=y
 CONFIG_HAS_IOPORT=y
 CONFIG_HAS_DMA=y
+CONFIG_NLATTR=y
diff --git a/arch/blackfin/include/asm/asm-offsets.h b/arch/blackfin/include/asm/asm-offsets.h
new file mode 100644
index 000000000000..d370ee36a182
--- /dev/null
+++ b/arch/blackfin/include/asm/asm-offsets.h
@@ -0,0 +1 @@
+#include <generated/asm-offsets.h>
diff --git a/arch/blackfin/include/asm/bfin-global.h b/arch/blackfin/include/asm/bfin-global.h
index 10064f902d20..e6485c305ea6 100644
--- a/arch/blackfin/include/asm/bfin-global.h
+++ b/arch/blackfin/include/asm/bfin-global.h
@@ -11,9 +11,6 @@
 
 #ifndef __ASSEMBLY__
 
-#include <asm/sections.h>
-#include <asm/ptrace.h>
-#include <asm/user.h>
 #include <linux/linkage.h>
 #include <linux/types.h>
 
@@ -23,6 +20,12 @@
 # define DMA_UNCACHED_REGION (2 * 1024 * 1024)
 #elif defined(CONFIG_DMA_UNCACHED_1M)
 # define DMA_UNCACHED_REGION (1024 * 1024)
+#elif defined(CONFIG_DMA_UNCACHED_512K)
+# define DMA_UNCACHED_REGION (512 * 1024)
+#elif defined(CONFIG_DMA_UNCACHED_256K)
+# define DMA_UNCACHED_REGION (256 * 1024)
+#elif defined(CONFIG_DMA_UNCACHED_128K)
+# define DMA_UNCACHED_REGION (128 * 1024)
 #else
 # define DMA_UNCACHED_REGION (0)
 #endif
@@ -35,6 +38,7 @@ extern unsigned long get_sclk(void);
 extern unsigned long sclk_to_usecs(unsigned long sclk);
 extern unsigned long usecs_to_sclk(unsigned long usecs);
 
+struct pt_regs;
 extern void dump_bfin_process(struct pt_regs *regs);
 extern void dump_bfin_mem(struct pt_regs *regs);
 extern void dump_bfin_trace_buffer(void);
diff --git a/arch/blackfin/include/asm/bfin-lq035q1.h b/arch/blackfin/include/asm/bfin-lq035q1.h
new file mode 100644
index 000000000000..57bc21ac2296
--- /dev/null
+++ b/arch/blackfin/include/asm/bfin-lq035q1.h
@@ -0,0 +1,28 @@
+/*
+ * Blackfin LCD Framebuffer driver SHARP LQ035Q1DH02
+ *
+ * Copyright 2008-2009 Analog Devices Inc.
+ * Licensed under the GPL-2 or later.
+ */
+
+#ifndef BFIN_LQ035Q1_H
+#define BFIN_LQ035Q1_H
+
+#define LQ035_RL        (0 << 8)        /* Right -> Left Scan */
+#define LQ035_LR        (1 << 8)        /* Left -> Right Scan */
+#define LQ035_TB        (1 << 9)        /* Top -> Botton Scan */
+#define LQ035_BT        (0 << 9)        /* Botton -> Top Scan */
+#define LQ035_BGR       (1 << 11)       /* Use BGR format */
+#define LQ035_RGB       (0 << 11)       /* Use RGB format */
+#define LQ035_NORM      (1 << 13)       /* Reversal */
+#define LQ035_REV       (0 << 13)       /* Reversal */
+
+struct bfin_lq035q1fb_disp_info {
+
+        unsigned        mode;
+        /* GPIOs */
+        int             use_bl;
+        unsigned        gpio_bl;
+};
+
+#endif /* BFIN_LQ035Q1_H */
diff --git a/arch/blackfin/include/asm/bug.h b/arch/blackfin/include/asm/bug.h
index 6f4548a13555..75f6dc336d46 100644
--- a/arch/blackfin/include/asm/bug.h
+++ b/arch/blackfin/include/asm/bug.h
@@ -47,7 +47,7 @@
 #define BUG()                                                           \
         do {                                                            \
                 _BUG_OR_WARN(0);                                        \
-                for (;;);                                               \
+                unreachable();                                          \
         } while (0)
 
 #define WARN_ON(condition)                                                      \
diff --git a/arch/blackfin/include/asm/cacheflush.h b/arch/blackfin/include/asm/cacheflush.h
index 417eaac7fe99..2666ff8ea952 100644
--- a/arch/blackfin/include/asm/cacheflush.h
+++ b/arch/blackfin/include/asm/cacheflush.h
@@ -10,6 +10,7 @@
 #define _BLACKFIN_CACHEFLUSH_H
 
 #include <asm/blackfin.h>       /* for SSYNC() */
+#include <asm/sections.h>       /* for _ramend */
 
 extern void blackfin_icache_flush_range(unsigned long start_address, unsigned long end_address);
 extern void blackfin_dcache_flush_range(unsigned long start_address, unsigned long end_address);
diff --git a/arch/blackfin/include/asm/checksum.h b/arch/blackfin/include/asm/checksum.h
index a23415be0de1..623cc7fb00bc 100644
--- a/arch/blackfin/include/asm/checksum.h
+++ b/arch/blackfin/include/asm/checksum.h
@@ -9,63 +9,12 @@
 #define _BFIN_CHECKSUM_H
 
 /*
- * computes the checksum of a memory block at buff, length len,
- * and adds in "sum" (32-bit)
- *
- * returns a 32-bit number suitable for feeding into itself
- * or csum_tcpudp_magic
- *
- * this function must be called with even lengths, except
- * for the last fragment, which may be odd
- *
- * it's best to have buff aligned on a 32-bit boundary
- */
-__wsum csum_partial(const void *buff, int len, __wsum sum);
-
-/*
- * the same as csum_partial, but copies from src while it
- * checksums
- *
- * here even more important to align src and dst on a 32-bit (or even
- * better 64-bit) boundary
- */
-
-__wsum csum_partial_copy(const void *src, void *dst,
-                               int len, __wsum sum);
-
-/*
- * the same as csum_partial_copy, but copies from user space.
- *
- * here even more important to align src and dst on a 32-bit (or even
- * better 64-bit) boundary
- */
-
-extern __wsum csum_partial_copy_from_user(const void __user *src, void *dst,
-                                          int len, __wsum sum, int *csum_err);
-
-#define csum_partial_copy_nocheck(src, dst, len, sum)   \
-        csum_partial_copy((src), (dst), (len), (sum))
-
-__sum16 ip_fast_csum(unsigned char *iph, unsigned int ihl);
-
-/*
- *      Fold a partial checksum
- */
-
-static inline __sum16 csum_fold(__wsum sum)
-{
-        while (sum >> 16)
-                sum = (sum & 0xffff) + (sum >> 16);
-        return ((~(sum << 16)) >> 16);
-}
-
-/*
  * computes the checksum of the TCP/UDP pseudo-header
  * returns a 16-bit checksum, already complemented
  */
 
 static inline __wsum
-csum_tcpudp_nofold(__be32 saddr, __be32 daddr, unsigned short len,
+__csum_tcpudp_nofold(__be32 saddr, __be32 daddr, unsigned short len,
                    unsigned short proto, __wsum sum)
 {
         unsigned int carry;
@@ -88,19 +37,8 @@ csum_tcpudp_nofold(__be32 saddr, __be32 daddr, unsigned short len,
 
         return (sum);
 }
+#define csum_tcpudp_nofold __csum_tcpudp_nofold
 
-static inline __sum16
-csum_tcpudp_magic(__be32 saddr, __be32 daddr, unsigned short len,
-                  unsigned short proto, __wsum sum)
-{
-        return csum_fold(csum_tcpudp_nofold(saddr, daddr, len, proto, sum));
-}
-
-/*
- * this routine is used for miscellaneous IP-like checksums, mainly
- * in icmp.c
- */
-
-extern __sum16 ip_compute_csum(const void *buff, int len);
+#include <asm-generic/checksum.h>
 
-#endif                          /* _BFIN_CHECKSUM_H */
+#endif
diff --git a/arch/blackfin/include/asm/clocks.h b/arch/blackfin/include/asm/clocks.h
index f80dad5ff257..6f0b61852f58 100644
--- a/arch/blackfin/include/asm/clocks.h
+++ b/arch/blackfin/include/asm/clocks.h
@@ -9,6 +9,8 @@
 #ifndef _BFIN_CLOCKS_H
 #define _BFIN_CLOCKS_H
 
+#include <asm/dpmc.h>
+
 #ifdef CONFIG_CCLK_DIV_1
 # define CONFIG_CCLK_ACT_DIV   CCLK_DIV1
 # define CONFIG_CCLK_DIV 1
diff --git a/arch/blackfin/include/asm/dma-mapping.h b/arch/blackfin/include/asm/dma-mapping.h
index 7a23d824ac96..f9172ff30e5c 100644
--- a/arch/blackfin/include/asm/dma-mapping.h
+++ b/arch/blackfin/include/asm/dma-mapping.h
@@ -7,9 +7,9 @@
 #ifndef _BLACKFIN_DMA_MAPPING_H
 #define _BLACKFIN_DMA_MAPPING_H
 
-#include <asm/scatterlist.h>
+#include <asm/cacheflush.h>
+struct scatterlist;
 
-void dma_alloc_init(unsigned long start, unsigned long end);
 void *dma_alloc_coherent(struct device *dev, size_t size,
                          dma_addr_t *dma_handle, gfp_t gfp);
 void dma_free_coherent(struct device *dev, size_t size, void *vaddr,
@@ -20,13 +20,51 @@ void dma_free_coherent(struct device *dev, size_t size, void *vaddr,
  */
 #define dma_alloc_noncoherent(d, s, h, f) dma_alloc_coherent(d, s, h, f)
 #define dma_free_noncoherent(d, s, v, h) dma_free_coherent(d, s, v, h)
+#define dma_supported(d, m)         (1)
+#define dma_get_cache_alignment()   (32)
+#define dma_is_consistent(d, h)     (1)
 
-static inline
-int dma_mapping_error(struct device *dev, dma_addr_t dma_addr)
+static inline int
+dma_set_mask(struct device *dev, u64 dma_mask)
 {
+        if (!dev->dma_mask || !dma_supported(dev, dma_mask))
+                return -EIO;
+
+        *dev->dma_mask = dma_mask;
+
         return 0;
 }
 
+static inline int
+dma_mapping_error(struct device *dev, dma_addr_t dma_addr)
+{
+        return 0;
+}
+
+extern void
+__dma_sync(dma_addr_t addr, size_t size, enum dma_data_direction dir);
+static inline void
+_dma_sync(dma_addr_t addr, size_t size, enum dma_data_direction dir)
+{
+        if (!__builtin_constant_p(dir)) {
+                __dma_sync(addr, size, dir);
+                return;
+        }
+
+        switch (dir) {
+        case DMA_NONE:
+                BUG();
+        case DMA_TO_DEVICE:             /* writeback only */
+                flush_dcache_range(addr, addr + size);
+                break;
+        case DMA_FROM_DEVICE: /* invalidate only */
+        case DMA_BIDIRECTIONAL: /* flush and invalidate */
+                /* Blackfin has no dedicated invalidate (it includes a flush) */
+                invalidate_dcache_range(addr, addr + size);
+                break;
+        }
+}
+
 /*
  * Map a single buffer of the indicated size for DMA in streaming mode.
  * The 32-bit bus address to use is returned.
@@ -34,8 +72,13 @@ int dma_mapping_error(struct device *dev, dma_addr_t dma_addr)
  * Once the device is given the dma address, the device owns this memory
  * until either pci_unmap_single or pci_dma_sync_single is performed.
  */
-extern dma_addr_t dma_map_single(struct device *dev, void *ptr, size_t size,
-                                 enum dma_data_direction direction);
+static inline dma_addr_t
+dma_map_single(struct device *dev, void *ptr, size_t size,
+               enum dma_data_direction dir)
+{
+        _dma_sync((dma_addr_t)ptr, size, dir);
+        return (dma_addr_t) ptr;
+}
 
 static inline dma_addr_t
 dma_map_page(struct device *dev, struct page *page,
@@ -53,8 +96,12 @@ dma_map_page(struct device *dev, struct page *page,
  * After this call, reads by the cpu to the buffer are guarenteed to see
  * whatever the device wrote there.
  */
-extern void dma_unmap_single(struct device *dev, dma_addr_t dma_addr, size_t size,
-                          enum dma_data_direction direction);
+static inline void
+dma_unmap_single(struct device *dev, dma_addr_t dma_addr, size_t size,
+                 enum dma_data_direction dir)
+{
+        BUG_ON(!valid_dma_direction(dir));
+}
 
 static inline void
 dma_unmap_page(struct device *dev, dma_addr_t dma_addr, size_t size,
@@ -80,38 +127,66 @@ dma_unmap_page(struct device *dev, dma_addr_t dma_addr, size_t size,
  * the same here.
  */
 extern int dma_map_sg(struct device *dev, struct scatterlist *sg, int nents,
-                      enum dma_data_direction direction);
+                      enum dma_data_direction dir);
 
 /*
  * Unmap a set of streaming mode DMA translations.
  * Again, cpu read rules concerning calls here are the same as for
  * pci_unmap_single() above.
  */
-extern void dma_unmap_sg(struct device *dev, struct scatterlist *sg,
-                      int nhwentries, enum dma_data_direction direction);
+static inline void
+dma_unmap_sg(struct device *dev, struct scatterlist *sg,
+             int nhwentries, enum dma_data_direction dir)
+{
+        BUG_ON(!valid_dma_direction(dir));
+}
 
-static inline void dma_sync_single_for_cpu(struct device *dev,
-                                        dma_addr_t handle, size_t size,
-                                        enum dma_data_direction dir)
+static inline void
+dma_sync_single_range_for_cpu(struct device *dev, dma_addr_t handle,
+                              unsigned long offset, size_t size,
+                              enum dma_data_direction dir)
 {
+        BUG_ON(!valid_dma_direction(dir));
 }
 
-static inline void dma_sync_single_for_device(struct device *dev,
-                                        dma_addr_t handle, size_t size,
-                                        enum dma_data_direction dir)
+static inline void
+dma_sync_single_range_for_device(struct device *dev, dma_addr_t handle,
+                                 unsigned long offset, size_t size,
+                                 enum dma_data_direction dir)
 {
+        _dma_sync(handle + offset, size, dir);
 }
 
-static inline void dma_sync_sg_for_cpu(struct device *dev,
-                                        struct scatterlist *sg,
-                                        int nents, enum dma_data_direction dir)
+static inline void
+dma_sync_single_for_cpu(struct device *dev, dma_addr_t handle, size_t size,
+                        enum dma_data_direction dir)
 {
+        dma_sync_single_range_for_cpu(dev, handle, 0, size, dir);
 }
 
-static inline void dma_sync_sg_for_device(struct device *dev,
-                                        struct scatterlist *sg,
-                                        int nents, enum dma_data_direction dir)
+static inline void
+dma_sync_single_for_device(struct device *dev, dma_addr_t handle, size_t size,
+                           enum dma_data_direction dir)
+{
+        dma_sync_single_range_for_device(dev, handle, 0, size, dir);
+}
+
+static inline void
+dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg, int nents,
+                    enum dma_data_direction dir)
+{
+        BUG_ON(!valid_dma_direction(dir));
+}
+
+extern void
+dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg,
+                       int nents, enum dma_data_direction dir);
+
+static inline void
+dma_cache_sync(struct device *dev, void *vaddr, size_t size,
+               enum dma_data_direction dir)
 {
+        _dma_sync((dma_addr_t)vaddr, size, dir);
 }
 
 #endif                          /* _BLACKFIN_DMA_MAPPING_H */
diff --git a/arch/blackfin/include/asm/dma.h b/arch/blackfin/include/asm/dma.h
index c9a59622e23f..bd2e62243abe 100644
--- a/arch/blackfin/include/asm/dma.h
+++ b/arch/blackfin/include/asm/dma.h
@@ -10,46 +10,70 @@
 
 #include <linux/interrupt.h>
 #include <mach/dma.h>
+#include <asm/atomic.h>
 #include <asm/blackfin.h>
 #include <asm/page.h>
-
-#define MAX_DMA_ADDRESS PAGE_OFFSET
-
-/*****************************************************************************
-*        Generic DMA  Declarations
-*
-****************************************************************************/
-enum dma_chan_status {
-        DMA_CHANNEL_FREE,
-        DMA_CHANNEL_REQUESTED,
-        DMA_CHANNEL_ENABLED,
-};
+#include <asm-generic/dma.h>
+
+/* DMA_CONFIG Masks */
+#define DMAEN                   0x0001  /* DMA Channel Enable */
+#define WNR                             0x0002  /* Channel Direction (W/R*) */
+#define WDSIZE_8                0x0000  /* Transfer Word Size = 8 */
+#define WDSIZE_16               0x0004  /* Transfer Word Size = 16 */
+#define WDSIZE_32               0x0008  /* Transfer Word Size = 32 */
+#define DMA2D                   0x0010  /* DMA Mode (2D/1D*) */
+#define RESTART                 0x0020  /* DMA Buffer Clear */
+#define DI_SEL                  0x0040  /* Data Interrupt Timing Select */
+#define DI_EN                   0x0080  /* Data Interrupt Enable */
+#define NDSIZE_0                0x0000  /* Next Descriptor Size = 0 (Stop/Autobuffer) */
+#define NDSIZE_1                0x0100  /* Next Descriptor Size = 1 */
+#define NDSIZE_2                0x0200  /* Next Descriptor Size = 2 */
+#define NDSIZE_3                0x0300  /* Next Descriptor Size = 3 */
+#define NDSIZE_4                0x0400  /* Next Descriptor Size = 4 */
+#define NDSIZE_5                0x0500  /* Next Descriptor Size = 5 */
+#define NDSIZE_6                0x0600  /* Next Descriptor Size = 6 */
+#define NDSIZE_7                0x0700  /* Next Descriptor Size = 7 */
+#define NDSIZE_8                0x0800  /* Next Descriptor Size = 8 */
+#define NDSIZE_9                0x0900  /* Next Descriptor Size = 9 */
+#define NDSIZE                  0x0f00  /* Next Descriptor Size */
+#define DMAFLOW                 0x7000  /* Flow Control */
+#define DMAFLOW_STOP    0x0000  /* Stop Mode */
+#define DMAFLOW_AUTO    0x1000  /* Autobuffer Mode */
+#define DMAFLOW_ARRAY   0x4000  /* Descriptor Array Mode */
+#define DMAFLOW_SMALL   0x6000  /* Small Model Descriptor List Mode */
+#define DMAFLOW_LARGE   0x7000  /* Large Model Descriptor List Mode */
+
+/* DMA_IRQ_STATUS Masks */
+#define DMA_DONE                0x0001  /* DMA Completion Interrupt Status */
+#define DMA_ERR                 0x0002  /* DMA Error Interrupt Status */
+#define DFETCH                  0x0004  /* DMA Descriptor Fetch Indicator */
+#define DMA_RUN                 0x0008  /* DMA Channel Running Indicator */
 
 /*-------------------------
  * config reg bits value
  *-------------------------*/
-#define DATA_SIZE_8             0
-#define DATA_SIZE_16            1
-#define DATA_SIZE_32            2
+#define DATA_SIZE_8                     0
+#define DATA_SIZE_16            1
+#define DATA_SIZE_32            2
 
-#define DMA_FLOW_STOP           0
-#define DMA_FLOW_AUTO           1
-#define DMA_FLOW_ARRAY          4
-#define DMA_FLOW_SMALL          6
-#define DMA_FLOW_LARGE          7
+#define DMA_FLOW_STOP           0
+#define DMA_FLOW_AUTO           1
+#define DMA_FLOW_ARRAY          4
+#define DMA_FLOW_SMALL          6
+#define DMA_FLOW_LARGE          7
 
-#define DIMENSION_LINEAR    0
-#define DIMENSION_2D           1
+#define DIMENSION_LINEAR        0
+#define DIMENSION_2D            1
 
-#define DIR_READ     0
-#define DIR_WRITE    1
+#define DIR_READ                        0
+#define DIR_WRITE                       1
 
-#define INTR_DISABLE   0
-#define INTR_ON_BUF    2
-#define INTR_ON_ROW    3
+#define INTR_DISABLE            0
+#define INTR_ON_BUF                     2
+#define INTR_ON_ROW                     3
 
 #define DMA_NOSYNC_KEEP_DMA_BUF 0
-#define DMA_SYNC_RESTART        1
+#define DMA_SYNC_RESTART                1
 
 struct dmasg {
         void *next_desc_addr;
@@ -104,11 +128,9 @@ struct dma_register {
 
 };
 
-struct mutex;
 struct dma_channel {
-        struct mutex dmalock;
         const char *device_id;
-        enum dma_chan_status chan_status;
+        atomic_t chan_status;
         volatile struct dma_register *regs;
         struct dmasg *sg;               /* large mode descriptor */
         unsigned int irq;
@@ -220,27 +242,20 @@ static inline void set_dma_sg(unsigned int channel, struct dmasg *sg, int ndsize
 
 static inline int dma_channel_active(unsigned int channel)
 {
-        if (dma_ch[channel].chan_status == DMA_CHANNEL_FREE)
-                return 0;
-        else
-                return 1;
+        return atomic_read(&dma_ch[channel].chan_status);
 }
 
 static inline void disable_dma(unsigned int channel)
 {
         dma_ch[channel].regs->cfg &= ~DMAEN;
         SSYNC();
-        dma_ch[channel].chan_status = DMA_CHANNEL_REQUESTED;
 }
 static inline void enable_dma(unsigned int channel)
 {
         dma_ch[channel].regs->curr_x_count = 0;
         dma_ch[channel].regs->curr_y_count = 0;
         dma_ch[channel].regs->cfg |= DMAEN;
-        dma_ch[channel].chan_status = DMA_CHANNEL_ENABLED;
 }
-void free_dma(unsigned int channel);
-int request_dma(unsigned int channel, const char *device_id);
 int set_dma_callback(unsigned int channel, irq_handler_t callback, void *data);
 
 static inline void dma_disable_irq(unsigned int channel)
diff --git a/arch/blackfin/include/asm/dpmc.h b/arch/blackfin/include/asm/dpmc.h
index 925e66cb2d49..1597ae5041ee 100644
--- a/arch/blackfin/include/asm/dpmc.h
+++ b/arch/blackfin/include/asm/dpmc.h
@@ -1,7 +1,7 @@
 /*
  * Miscellaneous IOCTL commands for Dynamic Power Management Controller Driver
  *
- * Copyright (C) 2004-2008 Analog Device Inc.
+ * Copyright (C) 2004-2009 Analog Device Inc.
  *
  * Licensed under the GPL-2
  */
@@ -9,7 +9,109 @@
 #ifndef _BLACKFIN_DPMC_H_
 #define _BLACKFIN_DPMC_H_
 
-#ifdef __KERNEL__
+/* PLL_CTL Masks */
+#define DF                      0x0001  /* 0: PLL = CLKIN, 1: PLL = CLKIN/2 */
+#define PLL_OFF                 0x0002  /* PLL Not Powered */
+#define STOPCK                  0x0008  /* Core Clock Off */
+#define PDWN                    0x0020  /* Enter Deep Sleep Mode */
+#ifdef __ADSPBF539__
+# define IN_DELAY               0x0014  /* Add 200ps Delay To EBIU Input Latches */
+# define OUT_DELAY              0x00C0  /* Add 200ps Delay To EBIU Output Signals */
+#else
+# define IN_DELAY               0x0040  /* Add 200ps Delay To EBIU Input Latches */
+# define OUT_DELAY              0x0080  /* Add 200ps Delay To EBIU Output Signals */
+#endif
+#define BYPASS                  0x0100  /* Bypass the PLL */
+#define MSEL                    0x7E00  /* Multiplier Select For CCLK/VCO Factors */
+#define SPORT_HYST              0x8000  /* Enable Additional Hysteresis on SPORT Input Pins */
+#define SET_MSEL(x)             (((x)&0x3F) << 0x9)     /* Set MSEL = 0-63 --> VCO = CLKIN*MSEL */
+
+/* PLL_DIV Masks */
+#define SSEL                    0x000F  /* System Select */
+#define CSEL                    0x0030  /* Core Select */
+#define CSEL_DIV1               0x0000  /* CCLK = VCO / 1 */
+#define CSEL_DIV2               0x0010  /* CCLK = VCO / 2 */
+#define CSEL_DIV4               0x0020  /* CCLK = VCO / 4 */
+#define CSEL_DIV8               0x0030  /* CCLK = VCO / 8 */
+
+#define CCLK_DIV1 CSEL_DIV1
+#define CCLK_DIV2 CSEL_DIV2
+#define CCLK_DIV4 CSEL_DIV4
+#define CCLK_DIV8 CSEL_DIV8
+
+#define SET_SSEL(x)     ((x) & 0xF)     /* Set SSEL = 0-15 --> SCLK = VCO/SSEL */
+#define SCLK_DIV(x)     (x)             /* SCLK = VCO / x */
+
+/* PLL_STAT Masks */
+#define ACTIVE_PLLENABLED       0x0001  /* Processor In Active Mode With PLL Enabled */
+#define FULL_ON                 0x0002  /* Processor In Full On Mode */
+#define ACTIVE_PLLDISABLED      0x0004  /* Processor In Active Mode With PLL Disabled */
+#define PLL_LOCKED              0x0020  /* PLL_LOCKCNT Has Been Reached */
+
+#define RTCWS                   0x0400  /* RTC/Reset Wake-Up Status */
+#define CANWS                   0x0800  /* CAN Wake-Up Status */
+#define USBWS                   0x2000  /* USB Wake-Up Status */
+#define KPADWS                  0x4000  /* Keypad Wake-Up Status */
+#define ROTWS                   0x8000  /* Rotary Wake-Up Status */
+#define GPWS                    0x1000  /* General-Purpose Wake-Up Status */
+
+/* VR_CTL Masks */
+#if defined(__ADSPBF52x__) || defined(__ADSPBF51x__)
+#define FREQ                    0x3000  /* Switching Oscillator Frequency For Regulator */
+#define FREQ_1000               0x3000  /* Switching Frequency Is 1 MHz */
+#else
+#define FREQ                    0x0003  /* Switching Oscillator Frequency For Regulator */
+#define FREQ_333                0x0001  /* Switching Frequency Is 333 kHz */
+#define FREQ_667                0x0002  /* Switching Frequency Is 667 kHz */
+#define FREQ_1000               0x0003  /* Switching Frequency Is 1 MHz */
+#endif
+#define HIBERNATE               0x0000  /* Powerdown/Bypass On-Board Regulation */
+
+#define GAIN                    0x000C  /* Voltage Level Gain */
+#define GAIN_5                  0x0000  /* GAIN = 5 */
+#define GAIN_10                 0x0004  /* GAIN = 1 */
+#define GAIN_20                 0x0008  /* GAIN = 2 */
+#define GAIN_50                 0x000C  /* GAIN = 5 */
+
+#define VLEV                    0x00F0  /* Internal Voltage Level */
+#ifdef __ADSPBF52x__
+#define VLEV_085                0x0040  /* VLEV = 0.85 V (-5% - +10% Accuracy) */
+#define VLEV_090                0x0050  /* VLEV = 0.90 V (-5% - +10% Accuracy) */
+#define VLEV_095                0x0060  /* VLEV = 0.95 V (-5% - +10% Accuracy) */
+#define VLEV_100                0x0070  /* VLEV = 1.00 V (-5% - +10% Accuracy) */
+#define VLEV_105                0x0080  /* VLEV = 1.05 V (-5% - +10% Accuracy) */
+#define VLEV_110                0x0090  /* VLEV = 1.10 V (-5% - +10% Accuracy) */
+#define VLEV_115                0x00A0  /* VLEV = 1.15 V (-5% - +10% Accuracy) */
+#define VLEV_120                0x00B0  /* VLEV = 1.20 V (-5% - +10% Accuracy) */
+#else
+#define VLEV_085                0x0060  /* VLEV = 0.85 V (-5% - +10% Accuracy) */
+#define VLEV_090                0x0070  /* VLEV = 0.90 V (-5% - +10% Accuracy) */
+#define VLEV_095                0x0080  /* VLEV = 0.95 V (-5% - +10% Accuracy) */
+#define VLEV_100                0x0090  /* VLEV = 1.00 V (-5% - +10% Accuracy) */
+#define VLEV_105                0x00A0  /* VLEV = 1.05 V (-5% - +10% Accuracy) */
+#define VLEV_110                0x00B0  /* VLEV = 1.10 V (-5% - +10% Accuracy) */
+#define VLEV_115                0x00C0  /* VLEV = 1.15 V (-5% - +10% Accuracy) */
+#define VLEV_120                0x00D0  /* VLEV = 1.20 V (-5% - +10% Accuracy) */
+#define VLEV_125                0x00E0  /* VLEV = 1.25 V (-5% - +10% Accuracy) */
+#define VLEV_130                0x00F0  /* VLEV = 1.30 V (-5% - +10% Accuracy) */
+#endif
+
+#define WAKE                    0x0100  /* Enable RTC/Reset Wakeup From Hibernate */
+#define CANWE                   0x0200  /* Enable CAN Wakeup From Hibernate */
+#define PHYWE                   0x0400  /* Enable PHY Wakeup From Hibernate */
+#define GPWE                    0x0400  /* General-Purpose Wake-Up Enable */
+#define MXVRWE                  0x0400  /* Enable MXVR Wakeup From Hibernate */
+#define KPADWE                  0x1000  /* Keypad Wake-Up Enable */
+#define ROTWE                   0x2000  /* Rotary Wake-Up Enable */
+#define CLKBUFOE                0x4000  /* CLKIN Buffer Output Enable */
+#define SCKELOW                 0x8000  /* Do Not Drive SCKE High During Reset After Hibernate */
+
+#if defined(__ADSPBF52x__) || defined(__ADSPBF51x__)
+#define USBWE                   0x0200  /* Enable USB Wakeup From Hibernate */
+#else
+#define USBWE                   0x0800  /* Enable USB Wakeup From Hibernate */
+#endif
+
 #ifndef __ASSEMBLY__
 
 void sleep_mode(u32 sic_iwr0, u32 sic_iwr1, u32 sic_iwr2);
@@ -54,6 +156,5 @@ struct bfin_dpmc_platform_data {
         w[P0 + (x - PLL_CTL)] = R0;\
 
 #endif
-#endif  /* __KERNEL__ */
 
 #endif  /*_BLACKFIN_DPMC_H_*/
diff --git a/arch/blackfin/include/asm/elf.h b/arch/blackfin/include/asm/elf.h
index 8e0764c81eaf..5b50f0ecacf8 100644
--- a/arch/blackfin/include/asm/elf.h
+++ b/arch/blackfin/include/asm/elf.h
@@ -55,7 +55,6 @@ do {											\
         _regs->p2       = _dynamic_addr;                                \
 } while(0)
 
-#define USE_ELF_CORE_DUMP
 #define ELF_FDPIC_CORE_EFLAGS   EF_BFIN_FDPIC
 #define ELF_EXEC_PAGESIZE       4096
 
diff --git a/arch/blackfin/include/asm/fcntl.h b/arch/blackfin/include/asm/fcntl.h
index 8727b2b382f1..251c911d59c1 100644
--- a/arch/blackfin/include/asm/fcntl.h
+++ b/arch/blackfin/include/asm/fcntl.h
@@ -7,8 +7,6 @@
 #ifndef _BFIN_FCNTL_H
 #define _BFIN_FCNTL_H
 
-/* open/fcntl - O_SYNC is only implemented on blocks devices and on files
-   located on an ext2 file system */
 #define O_DIRECTORY      040000 /* must be a directory */
 #define O_NOFOLLOW      0100000 /* don't follow links */
 #define O_DIRECT        0200000 /* direct disk access hint - currently ignored */
diff --git a/arch/blackfin/include/asm/gpio.h b/arch/blackfin/include/asm/gpio.h
index 5b44d05ca53e..539468a05057 100644
--- a/arch/blackfin/include/asm/gpio.h
+++ b/arch/blackfin/include/asm/gpio.h
@@ -159,6 +159,11 @@ struct gpio_port_t {
 };
 #endif
 
+#ifdef BFIN_SPECIAL_GPIO_BANKS
+void bfin_special_gpio_free(unsigned gpio);
+int bfin_special_gpio_request(unsigned gpio, const char *label);
+#endif
+
 #ifdef CONFIG_PM
 
 unsigned int bfin_pm_standby_setup(void);
diff --git a/arch/blackfin/include/asm/gptimers.h b/arch/blackfin/include/asm/gptimers.h
index 89f08decb8e0..c722acdda0d3 100644
--- a/arch/blackfin/include/asm/gptimers.h
+++ b/arch/blackfin/include/asm/gptimers.h
@@ -172,25 +172,25 @@
 
 /* The actual gptimer API */
 
-void     set_gptimer_pwidth(int timer_id, uint32_t width);
-uint32_t get_gptimer_pwidth(int timer_id);
-void     set_gptimer_period(int timer_id, uint32_t period);
-uint32_t get_gptimer_period(int timer_id);
-uint32_t get_gptimer_count(int timer_id);
-int      get_gptimer_intr(int timer_id);
-void     clear_gptimer_intr(int timer_id);
-int      get_gptimer_over(int timer_id);
-void     clear_gptimer_over(int timer_id);
-void     set_gptimer_config(int timer_id, uint16_t config);
-uint16_t get_gptimer_config(int timer_id);
-int      get_gptimer_run(int timer_id);
-void     set_gptimer_pulse_hi(int timer_id);
-void     clear_gptimer_pulse_hi(int timer_id);
+void     set_gptimer_pwidth(unsigned int timer_id, uint32_t width);
+uint32_t get_gptimer_pwidth(unsigned int timer_id);
+void     set_gptimer_period(unsigned int timer_id, uint32_t period);
+uint32_t get_gptimer_period(unsigned int timer_id);
+uint32_t get_gptimer_count(unsigned int timer_id);
+int      get_gptimer_intr(unsigned int timer_id);
+void     clear_gptimer_intr(unsigned int timer_id);
+int      get_gptimer_over(unsigned int timer_id);
+void     clear_gptimer_over(unsigned int timer_id);
+void     set_gptimer_config(unsigned int timer_id, uint16_t config);
+uint16_t get_gptimer_config(unsigned int timer_id);
+int      get_gptimer_run(unsigned int timer_id);
+void     set_gptimer_pulse_hi(unsigned int timer_id);
+void     clear_gptimer_pulse_hi(unsigned int timer_id);
 void     enable_gptimers(uint16_t mask);
 void     disable_gptimers(uint16_t mask);
 void     disable_gptimers_sync(uint16_t mask);
 uint16_t get_enabled_gptimers(void);
-uint32_t get_gptimer_status(int group);
-void     set_gptimer_status(int group, uint32_t value);
+uint32_t get_gptimer_status(unsigned int group);
+void     set_gptimer_status(unsigned int group, uint32_t value);
 
 #endif
diff --git a/arch/blackfin/include/asm/io.h b/arch/blackfin/include/asm/io.h
index d1f5029189a7..29e55b9d88bc 100644
--- a/arch/blackfin/include/asm/io.h
+++ b/arch/blackfin/include/asm/io.h
@@ -31,12 +31,14 @@ static inline unsigned char readb(const volatile void __iomem *addr)
         unsigned int val;
         int tmp;
 
-        __asm__ __volatile__ ("cli %1;\n\t"
-                        "NOP; NOP; SSYNC;\n\t"
-                        "%0 = b [%2] (z);\n\t"
-                        "sti %1;\n\t"
-                        : "=d"(val), "=d"(tmp): "a"(addr)
-                        );
+        __asm__ __volatile__ (
+                "cli %1;"
+                "NOP; NOP; SSYNC;"
+                "%0 = b [%2] (z);"
+                "sti %1;"
+                : "=d"(val), "=d"(tmp)
+                : "a"(addr)
+        );
 
         return (unsigned char) val;
 }
@@ -46,12 +48,14 @@ static inline unsigned short readw(const volatile void __iomem *addr)
         unsigned int val;
         int tmp;
 
-        __asm__ __volatile__ ("cli %1;\n\t"
-                        "NOP; NOP; SSYNC;\n\t"
-                        "%0 = w [%2] (z);\n\t"
-                        "sti %1;\n\t"
-                        : "=d"(val), "=d"(tmp): "a"(addr)
-                        );
+        __asm__ __volatile__ (
+                "cli %1;"
+                "NOP; NOP; SSYNC;"
+                "%0 = w [%2] (z);"
+                "sti %1;"
+                : "=d"(val), "=d"(tmp)
+                : "a"(addr)
+        );
 
         return (unsigned short) val;
 }
@@ -61,20 +65,23 @@ static inline unsigned int readl(const volatile void __iomem *addr)
         unsigned int val;
         int tmp;
 
-        __asm__ __volatile__ ("cli %1;\n\t"
-                        "NOP; NOP; SSYNC;\n\t"
-                        "%0 = [%2];\n\t"
-                        "sti %1;\n\t"
-                        : "=d"(val), "=d"(tmp): "a"(addr)
-                        );
+        __asm__ __volatile__ (
+                "cli %1;"
+                "NOP; NOP; SSYNC;"
+                "%0 = [%2];"
+                "sti %1;"
+                : "=d"(val), "=d"(tmp)
+                : "a"(addr)
+        );
+
         return val;
 }
 
 #endif /*  __ASSEMBLY__ */
 
-#define writeb(b,addr) (void)((*(volatile unsigned char *) (addr)) = (b))
-#define writew(b,addr) (void)((*(volatile unsigned short *) (addr)) = (b))
-#define writel(b,addr) (void)((*(volatile unsigned int *) (addr)) = (b))
+#define writeb(b, addr) (void)((*(volatile unsigned char *) (addr)) = (b))
+#define writew(b, addr) (void)((*(volatile unsigned short *) (addr)) = (b))
+#define writel(b, addr) (void)((*(volatile unsigned int *) (addr)) = (b))
 
 #define __raw_readb readb
 #define __raw_readw readw
@@ -82,9 +89,9 @@ static inline unsigned int readl(const volatile void __iomem *addr)
 #define __raw_writeb writeb
 #define __raw_writew writew
 #define __raw_writel writel
-#define memset_io(a,b,c)        memset((void *)(a),(b),(c))
-#define memcpy_fromio(a,b,c)    memcpy((a),(void *)(b),(c))
-#define memcpy_toio(a,b,c)      memcpy((void *)(a),(b),(c))
+#define memset_io(a, b, c)      memset((void *)(a), (b), (c))
+#define memcpy_fromio(a, b, c)  memcpy((a), (void *)(b), (c))
+#define memcpy_toio(a, b, c)    memcpy((void *)(a), (b), (c))
 
 /* Convert "I/O port addresses" to actual addresses.  i.e. ugly casts. */
 #define __io(port) ((void *)(unsigned long)(port))
@@ -92,30 +99,30 @@ static inline unsigned int readl(const volatile void __iomem *addr)
 #define inb(port)    readb(__io(port))
 #define inw(port)    readw(__io(port))
 #define inl(port)    readl(__io(port))
-#define outb(x,port) writeb(x,__io(port))
-#define outw(x,port) writew(x,__io(port))
-#define outl(x,port) writel(x,__io(port))
+#define outb(x, port) writeb(x, __io(port))
+#define outw(x, port) writew(x, __io(port))
+#define outl(x, port) writel(x, __io(port))
 
 #define inb_p(port)    inb(__io(port))
 #define inw_p(port)    inw(__io(port))
 #define inl_p(port)    inl(__io(port))
-#define outb_p(x,port) outb(x,__io(port))
-#define outw_p(x,port) outw(x,__io(port))
-#define outl_p(x,port) outl(x,__io(port))
-
-#define ioread8_rep(a,d,c)      readsb(a,d,c)
-#define ioread16_rep(a,d,c)     readsw(a,d,c)
-#define ioread32_rep(a,d,c)     readsl(a,d,c)
-#define iowrite8_rep(a,s,c)     writesb(a,s,c)
-#define iowrite16_rep(a,s,c)    writesw(a,s,c)
-#define iowrite32_rep(a,s,c)    writesl(a,s,c)
-
-#define ioread8(X)                      readb(X)
-#define ioread16(X)                     readw(X)
-#define ioread32(X)                     readl(X)
-#define iowrite8(val,X)                 writeb(val,X)
-#define iowrite16(val,X)                writew(val,X)
-#define iowrite32(val,X)                writel(val,X)
+#define outb_p(x, port) outb(x, __io(port))
+#define outw_p(x, port) outw(x, __io(port))
+#define outl_p(x, port) outl(x, __io(port))
+
+#define ioread8_rep(a, d, c)    readsb(a, d, c)
+#define ioread16_rep(a, d, c)   readsw(a, d, c)
+#define ioread32_rep(a, d, c)   readsl(a, d, c)
+#define iowrite8_rep(a, s, c)   writesb(a, s, c)
+#define iowrite16_rep(a, s, c)  writesw(a, s, c)
+#define iowrite32_rep(a, s, c)  writesl(a, s, c)
+
+#define ioread8(x)                      readb(x)
+#define ioread16(x)                     readw(x)
+#define ioread32(x)                     readl(x)
+#define iowrite8(val, x)                writeb(val, x)
+#define iowrite16(val, x)               writew(val, x)
+#define iowrite32(val, x)               writel(val, x)
 
 #define mmiowb() wmb()
 
diff --git a/arch/blackfin/include/asm/ipipe.h b/arch/blackfin/include/asm/ipipe.h
index 4617ba66278f..d3b40449ca0e 100644
--- a/arch/blackfin/include/asm/ipipe.h
+++ b/arch/blackfin/include/asm/ipipe.h
@@ -35,9 +35,9 @@
 #include <asm/atomic.h>
 #include <asm/traps.h>
 
-#define IPIPE_ARCH_STRING     "1.11-00"
+#define IPIPE_ARCH_STRING     "1.12-00"
 #define IPIPE_MAJOR_NUMBER    1
-#define IPIPE_MINOR_NUMBER    11
+#define IPIPE_MINOR_NUMBER    12
 #define IPIPE_PATCH_NUMBER    0
 
 #ifdef CONFIG_SMP
@@ -124,16 +124,6 @@ static inline int __ipipe_check_tickdev(const char *devname)
         return 1;
 }
 
-static inline void __ipipe_lock_root(void)
-{
-        set_bit(IPIPE_SYNCDEFER_FLAG, &ipipe_root_cpudom_var(status));
-}
-
-static inline void __ipipe_unlock_root(void)
-{
-        clear_bit(IPIPE_SYNCDEFER_FLAG, &ipipe_root_cpudom_var(status));
-}
-
 void __ipipe_enable_pipeline(void);
 
 #define __ipipe_hook_critical_ipi(ipd) do { } while (0)
diff --git a/arch/blackfin/include/asm/ipipe_base.h b/arch/blackfin/include/asm/ipipe_base.h
index 490098f532a7..00409201d9ed 100644
--- a/arch/blackfin/include/asm/ipipe_base.h
+++ b/arch/blackfin/include/asm/ipipe_base.h
@@ -51,23 +51,15 @@
 
 extern unsigned long __ipipe_root_status; /* Alias to ipipe_root_cpudom_var(status) */
 
-#define __ipipe_stall_root()                                            \
-        do {                                                            \
-                volatile unsigned long *p = &__ipipe_root_status;       \
-                set_bit(0, p);                                          \
-        } while (0)
-
-#define __ipipe_test_and_stall_root()                                   \
-        ({                                                              \
-                volatile unsigned long *p = &__ipipe_root_status;       \
-                test_and_set_bit(0, p);                                 \
-        })
-
-#define __ipipe_test_root()                                     \
-        ({                                                      \
-                const unsigned long *p = &__ipipe_root_status;  \
-                test_bit(0, p);                                 \
-        })
+void __ipipe_stall_root(void);
+
+unsigned long __ipipe_test_and_stall_root(void);
+
+unsigned long __ipipe_test_root(void);
+
+void __ipipe_lock_root(void);
+
+void __ipipe_unlock_root(void);
 
 #endif /* !__ASSEMBLY__ */
 
diff --git a/arch/blackfin/include/asm/irqflags.h b/arch/blackfin/include/asm/irqflags.h
index 9b19a19d9ae9..813a1af3e865 100644
--- a/arch/blackfin/include/asm/irqflags.h
+++ b/arch/blackfin/include/asm/irqflags.h
@@ -33,6 +33,7 @@ static inline unsigned long bfin_cli(void)
 
 #ifdef CONFIG_IPIPE
 
+#include <linux/compiler.h>
 #include <linux/ipipe_base.h>
 #include <linux/ipipe_trace.h>
 
@@ -49,12 +50,12 @@ static inline unsigned long bfin_cli(void)
                 barrier();                              \
         } while (0)
 
-static inline void raw_local_irq_enable(void)
-{
-        barrier();
-        ipipe_check_context(ipipe_root_domain);
-        __ipipe_unstall_root();
-}
+#define raw_local_irq_enable()                          \
+        do {                                            \
+                barrier();                              \
+                ipipe_check_context(ipipe_root_domain); \
+                __ipipe_unstall_root();                 \
+        } while (0)
 
 #define raw_local_save_flags_ptr(x)                                     \
         do {                                                            \
diff --git a/arch/blackfin/include/asm/kgdb.h b/arch/blackfin/include/asm/kgdb.h
index c8b256d2ea30..8651afe12990 100644
--- a/arch/blackfin/include/asm/kgdb.h
+++ b/arch/blackfin/include/asm/kgdb.h
@@ -10,9 +10,6 @@
 
 #include <linux/ptrace.h>
 
-/* gdb locks */
-#define KGDB_MAX_NO_CPUS 8
-
 /*
  * BUFMAX defines the maximum number of characters in inbound/outbound buffers.
  * At least NUMREGBYTES*2 are needed for register packets.
diff --git a/arch/blackfin/include/asm/mem_init.h b/arch/blackfin/include/asm/mem_init.h
index 4179e329b9c9..7c8fe834ff22 100644
--- a/arch/blackfin/include/asm/mem_init.h
+++ b/arch/blackfin/include/asm/mem_init.h
@@ -295,156 +295,3 @@
 #else
 #define PLL_BYPASS       0
 #endif
-
-/***************************************Currently Not Being Used *********************************/
-
-#if defined(CONFIG_FLASH_SPEED_BWAT) && \
-defined(CONFIG_FLASH_SPEED_BRAT) && \
-defined(CONFIG_FLASH_SPEED_BHT) && \
-defined(CONFIG_FLASH_SPEED_BST) && \
-defined(CONFIG_FLASH_SPEED_BTT)
-
-#define flash_EBIU_AMBCTL_WAT  ((CONFIG_FLASH_SPEED_BWAT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
-#define flash_EBIU_AMBCTL_RAT  ((CONFIG_FLASH_SPEED_BRAT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
-#define flash_EBIU_AMBCTL_HT   ((CONFIG_FLASH_SPEED_BHT  * 4) / (4000000000 / CONFIG_SCLK_HZ))
-#define flash_EBIU_AMBCTL_ST   ((CONFIG_FLASH_SPEED_BST  * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
-#define flash_EBIU_AMBCTL_TT   ((CONFIG_FLASH_SPEED_BTT  * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
-
-#if (flash_EBIU_AMBCTL_TT > 3)
-#define flash_EBIU_AMBCTL0_TT   B0TT_4
-#endif
-#if (flash_EBIU_AMBCTL_TT == 3)
-#define flash_EBIU_AMBCTL0_TT   B0TT_3
-#endif
-#if (flash_EBIU_AMBCTL_TT == 2)
-#define flash_EBIU_AMBCTL0_TT   B0TT_2
-#endif
-#if (flash_EBIU_AMBCTL_TT < 2)
-#define flash_EBIU_AMBCTL0_TT   B0TT_1
-#endif
-
-#if (flash_EBIU_AMBCTL_ST > 3)
-#define flash_EBIU_AMBCTL0_ST   B0ST_4
-#endif
-#if (flash_EBIU_AMBCTL_ST == 3)
-#define flash_EBIU_AMBCTL0_ST   B0ST_3
-#endif
-#if (flash_EBIU_AMBCTL_ST == 2)
-#define flash_EBIU_AMBCTL0_ST   B0ST_2
-#endif
-#if (flash_EBIU_AMBCTL_ST < 2)
-#define flash_EBIU_AMBCTL0_ST   B0ST_1
-#endif
-
-#if (flash_EBIU_AMBCTL_HT > 2)
-#define flash_EBIU_AMBCTL0_HT   B0HT_3
-#endif
-#if (flash_EBIU_AMBCTL_HT == 2)
-#define flash_EBIU_AMBCTL0_HT   B0HT_2
-#endif
-#if (flash_EBIU_AMBCTL_HT == 1)
-#define flash_EBIU_AMBCTL0_HT   B0HT_1
-#endif
-#if (flash_EBIU_AMBCTL_HT == 0 && CONFIG_FLASH_SPEED_BHT == 0)
-#define flash_EBIU_AMBCTL0_HT   B0HT_0
-#endif
-#if (flash_EBIU_AMBCTL_HT == 0 && CONFIG_FLASH_SPEED_BHT != 0)
-#define flash_EBIU_AMBCTL0_HT   B0HT_1
-#endif
-
-#if (flash_EBIU_AMBCTL_WAT > 14)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_15
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 14)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_14
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 13)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_13
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 12)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_12
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 11)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_11
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 10)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_10
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 9)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_9
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 8)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_8
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 7)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_7
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 6)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_6
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 5)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_5
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 4)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_4
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 3)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_3
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 2)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_2
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 1)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_1
-#endif
-
-#if (flash_EBIU_AMBCTL_RAT > 14)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_15
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 14)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_14
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 13)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_13
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 12)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_12
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 11)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_11
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 10)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_10
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 9)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_9
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 8)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_8
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 7)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_7
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 6)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_6
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 5)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_5
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 4)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_4
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 3)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_3
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 2)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_2
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 1)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_1
-#endif
-
-#define flash_EBIU_AMBCTL0  \
-        (flash_EBIU_AMBCTL0_WAT | flash_EBIU_AMBCTL0_RAT | flash_EBIU_AMBCTL0_HT | \
-         flash_EBIU_AMBCTL0_ST | flash_EBIU_AMBCTL0_TT | CONFIG_FLASH_SPEED_RDYEN)
-#endif
diff --git a/arch/blackfin/include/asm/mmu_context.h b/arch/blackfin/include/asm/mmu_context.h
index 4a3be376ad5b..ae8ef4ffd806 100644
--- a/arch/blackfin/include/asm/mmu_context.h
+++ b/arch/blackfin/include/asm/mmu_context.h
@@ -66,8 +66,8 @@ activate_l1stack(struct mm_struct *mm, unsigned long sp_base)
 
 #define activate_mm(prev, next) switch_mm(prev, next, NULL)
 
-static inline void switch_mm(struct mm_struct *prev_mm, struct mm_struct *next_mm,
-                             struct task_struct *tsk)
+static inline void __switch_mm(struct mm_struct *prev_mm, struct mm_struct *next_mm,
+                               struct task_struct *tsk)
 {
 #ifdef CONFIG_MPU
         unsigned int cpu = smp_processor_id();
@@ -95,7 +95,24 @@ static inline void switch_mm(struct mm_struct *prev_mm, struct mm_struct *next_m
 #endif
 }
 
+#ifdef CONFIG_IPIPE
+#define lock_mm_switch(flags)   local_irq_save_hw_cond(flags)
+#define unlock_mm_switch(flags) local_irq_restore_hw_cond(flags)
+#else
+#define lock_mm_switch(flags)   do { (void)(flags); } while (0)
+#define unlock_mm_switch(flags) do { (void)(flags); } while (0)
+#endif /* CONFIG_IPIPE */
+
 #ifdef CONFIG_MPU
+static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next,
+                             struct task_struct *tsk)
+{
+        unsigned long flags;
+        lock_mm_switch(flags);
+        __switch_mm(prev, next, tsk);
+        unlock_mm_switch(flags);
+}
+
 static inline void protect_page(struct mm_struct *mm, unsigned long addr,
                                 unsigned long flags)
 {
@@ -128,6 +145,12 @@ static inline void update_protections(struct mm_struct *mm)
                 set_mask_dcplbs(mm->context.page_rwx_mask, cpu);
         }
 }
+#else /* !CONFIG_MPU */
+static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next,
+                             struct task_struct *tsk)
+{
+        __switch_mm(prev, next, tsk);
+}
 #endif
 
 static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk)
@@ -173,4 +196,10 @@ static inline void destroy_context(struct mm_struct *mm)
 #endif
 }
 
+#define ipipe_mm_switch_protect(flags)          \
+        local_irq_save_hw_cond(flags)
+
+#define ipipe_mm_switch_unprotect(flags)        \
+        local_irq_restore_hw_cond(flags)
+
 #endif
diff --git a/arch/blackfin/include/asm/module.h b/arch/blackfin/include/asm/module.h
index 9c1cfffddd9b..4282b169ead9 100644
--- a/arch/blackfin/include/asm/module.h
+++ b/arch/blackfin/include/asm/module.h
@@ -7,8 +7,6 @@
 #ifndef _ASM_BFIN_MODULE_H
 #define _ASM_BFIN_MODULE_H
 
-#define MODULE_SYMBOL_PREFIX "_"
-
 #define Elf_Shdr        Elf32_Shdr
 #define Elf_Sym         Elf32_Sym
 #define Elf_Ehdr        Elf32_Ehdr
diff --git a/arch/blackfin/include/asm/pci.h b/arch/blackfin/include/asm/pci.h
index 61277358c865..99cae2e3bac7 100644
--- a/arch/blackfin/include/asm/pci.h
+++ b/arch/blackfin/include/asm/pci.h
@@ -4,145 +4,19 @@
 #define _ASM_BFIN_PCI_H
 
 #include <asm/scatterlist.h>
+#include <asm-generic/pci-dma-compat.h>
+#include <asm-generic/pci.h>
 
-/*
- *
- * Written by Wout Klaren.
- */
-
-/* Added by Chang Junxiao */
 #define PCIBIOS_MIN_IO 0x00001000
 #define PCIBIOS_MIN_MEM 0x10000000
 
-#define PCI_DMA_BUS_IS_PHYS       (1)
-struct pci_ops;
-
-/*
- * Structure with hardware dependent information and functions of the
- * PCI bus.
- */
-struct pci_bus_info {
-
-        /*
-         * Resources of the PCI bus.
-         */
-        struct resource mem_space;
-        struct resource io_space;
-
-        /*
-         * System dependent functions.
-         */
-        struct pci_ops *bfin_pci_ops;
-        void (*fixup) (int pci_modify);
-        void (*conf_device) (unsigned char bus, unsigned char device_fn);
-};
-
-#define pcibios_assign_all_busses()     0
 static inline void pcibios_set_master(struct pci_dev *dev)
 {
-
         /* No special bus mastering setup handling */
 }
 static inline void pcibios_penalize_isa_irq(int irq)
 {
-
         /* We don't do dynamic PCI IRQ allocation */
 }
-static inline dma_addr_t pci_map_single(struct pci_dev *hwdev, void *ptr,
-                                        size_t size, int direction)
-{
-        if (direction == PCI_DMA_NONE)
-                BUG();
-
-         /* return virt_to_bus(ptr); */
-        return (dma_addr_t) ptr;
-}
-
-/* Unmap a single streaming mode DMA translation.  The dma_addr and size
- * must match what was provided for in a previous pci_map_single call.  All
- * other usages are undefined.
- *
- * After this call, reads by the cpu to the buffer are guarenteed to see
- * whatever the device wrote there.
- */
-static inline void pci_unmap_single(struct pci_dev *hwdev, dma_addr_t dma_addr,
-                                    size_t size, int direction)
-{
-        if (direction == PCI_DMA_NONE)
-                BUG();
-
-        /* Nothing to do */
-}
-
-/* Map a set of buffers described by scatterlist in streaming
- * mode for DMA.  This is the scather-gather version of the
- * above pci_map_single interface.  Here the scatter gather list
- * elements are each tagged with the appropriate dma address
- * and length.  They are obtained via sg_dma_{address,length}(SG).
- *
- * NOTE: An implementation may be able to use a smaller number of
- *       DMA address/length pairs than there are SG table elements.
- *       (for example via virtual mapping capabilities)
- *       The routine returns the number of addr/length pairs actually
- *       used, at most nents.
- *
- * Device ownership issues as mentioned above for pci_map_single are
- * the same here.
- */
-static inline int pci_map_sg(struct pci_dev *hwdev, struct scatterlist *sg,
-                             int nents, int direction)
-{
-        if (direction == PCI_DMA_NONE)
-                BUG();
-        return nents;
-}
-
-/* Unmap a set of streaming mode DMA translations.
- * Again, cpu read rules concerning calls here are the same as for
- * pci_unmap_single() above.
- */
-static inline void pci_unmap_sg(struct pci_dev *hwdev, struct scatterlist *sg,
-                                int nents, int direction)
-{
-        if (direction == PCI_DMA_NONE)
-                BUG();
-
-        /* Nothing to do */
-}
-
-/* Make physical memory consistent for a single
- * streaming mode DMA translation after a transfer.
- *
- * If you perform a pci_map_single() but wish to interrogate the
- * buffer using the cpu, yet do not wish to teardown the PCI dma
- * mapping, you must call this function before doing so.  At the
- * next point you give the PCI dma address back to the card, the
- * device again owns the buffer.
- */
-static inline void pci_dma_sync_single(struct pci_dev *hwdev,
-                                       dma_addr_t dma_handle, size_t size,
-                                       int direction)
-{
-        if (direction == PCI_DMA_NONE)
-                BUG();
-
-        /* Nothing to do */
-}
-
-/* Make physical memory consistent for a set of streaming
- * mode DMA translations after a transfer.
- *
- * The same as pci_dma_sync_single but for a scatter-gather list,
- * same rules and usage.
- */
-static inline void pci_dma_sync_sg(struct pci_dev *hwdev,
-                                   struct scatterlist *sg, int nelems,
-                                   int direction)
-{
-        if (direction == PCI_DMA_NONE)
-                BUG();
-
-        /* Nothing to do */
-}
 
 #endif                          /* _ASM_BFIN_PCI_H */
diff --git a/arch/blackfin/include/asm/ptrace.h b/arch/blackfin/include/asm/ptrace.h
index 27290c955a7a..b33a4488f498 100644
--- a/arch/blackfin/include/asm/ptrace.h
+++ b/arch/blackfin/include/asm/ptrace.h
@@ -89,9 +89,9 @@ struct pt_regs {
 #define PTRACE_GETREGS            12
 #define PTRACE_SETREGS            13    /* ptrace signal  */
 
-#define PTRACE_GETFDPIC           31
-#define PTRACE_GETFDPIC_EXEC      0
-#define PTRACE_GETFDPIC_INTERP    1
+#define PTRACE_GETFDPIC           31    /* get the ELF fdpic loadmap address */
+#define PTRACE_GETFDPIC_EXEC       0    /* [addr] request the executable loadmap */
+#define PTRACE_GETFDPIC_INTERP     1    /* [addr] request the interpreter loadmap */
 
 #define PS_S  (0x0002)
 
diff --git a/arch/blackfin/include/asm/sections.h b/arch/blackfin/include/asm/sections.h
index 1f5381fbb4a7..42f6c53c59c6 100644
--- a/arch/blackfin/include/asm/sections.h
+++ b/arch/blackfin/include/asm/sections.h
@@ -13,10 +13,18 @@ extern unsigned long memory_mtd_start, memory_mtd_end, mtd_size;
 extern unsigned long _ramstart, _ramend, _rambase;
 extern unsigned long memory_start, memory_end, physical_mem_end;
 
-extern char _stext_l1[], _etext_l1[], _sdata_l1[], _edata_l1[], _sbss_l1[],
-        _ebss_l1[], _l1_lma_start[], _sdata_b_l1[], _sbss_b_l1[], _ebss_b_l1[],
-        _stext_l2[], _etext_l2[], _sdata_l2[], _edata_l2[], _sbss_l2[],
-        _ebss_l2[], _l2_lma_start[];
+/*
+ * The weak markings on the lengths might seem weird, but this is required
+ * in order to make gcc accept the fact that these may actually have a value
+ * of 0 (since they aren't actually addresses, but sizes of sections).
+ */
+extern char _stext_l1[], _etext_l1[], _text_l1_lma[], __weak _text_l1_len[];
+extern char _sdata_l1[], _edata_l1[], _sbss_l1[], _ebss_l1[],
+        _data_l1_lma[], __weak _data_l1_len[];
+extern char _sdata_b_l1[], _edata_b_l1[], _sbss_b_l1[], _ebss_b_l1[],
+        _data_b_l1_lma[], __weak _data_b_l1_len[];
+extern char _stext_l2[], _etext_l2[], _sdata_l2[], _edata_l2[],
+        _sbss_l2[], _ebss_l2[], _l2_lma[], __weak _l2_len[];
 
 #include <asm/mem_map.h>
 
diff --git a/arch/blackfin/include/asm/spinlock.h b/arch/blackfin/include/asm/spinlock.h
index b0c7f0ee4b03..1942ccfedbe0 100644
--- a/arch/blackfin/include/asm/spinlock.h
+++ b/arch/blackfin/include/asm/spinlock.h
@@ -17,84 +17,84 @@ asmlinkage int __raw_spin_is_locked_asm(volatile int *ptr);
 asmlinkage void __raw_spin_lock_asm(volatile int *ptr);
 asmlinkage int __raw_spin_trylock_asm(volatile int *ptr);
 asmlinkage void __raw_spin_unlock_asm(volatile int *ptr);
-asmlinkage void __raw_read_lock_asm(volatile int *ptr);
-asmlinkage int __raw_read_trylock_asm(volatile int *ptr);
-asmlinkage void __raw_read_unlock_asm(volatile int *ptr);
-asmlinkage void __raw_write_lock_asm(volatile int *ptr);
-asmlinkage int __raw_write_trylock_asm(volatile int *ptr);
-asmlinkage void __raw_write_unlock_asm(volatile int *ptr);
-
-static inline int __raw_spin_is_locked(raw_spinlock_t *lock)
+asmlinkage void arch_read_lock_asm(volatile int *ptr);
+asmlinkage int arch_read_trylock_asm(volatile int *ptr);
+asmlinkage void arch_read_unlock_asm(volatile int *ptr);
+asmlinkage void arch_write_lock_asm(volatile int *ptr);
+asmlinkage int arch_write_trylock_asm(volatile int *ptr);
+asmlinkage void arch_write_unlock_asm(volatile int *ptr);
+
+static inline int arch_spin_is_locked(arch_spinlock_t *lock)
 {
         return __raw_spin_is_locked_asm(&lock->lock);
 }
 
-static inline void __raw_spin_lock(raw_spinlock_t *lock)
+static inline void arch_spin_lock(arch_spinlock_t *lock)
 {
         __raw_spin_lock_asm(&lock->lock);
 }
 
-#define __raw_spin_lock_flags(lock, flags) __raw_spin_lock(lock)
+#define arch_spin_lock_flags(lock, flags) arch_spin_lock(lock)
 
-static inline int __raw_spin_trylock(raw_spinlock_t *lock)
+static inline int arch_spin_trylock(arch_spinlock_t *lock)
 {
         return __raw_spin_trylock_asm(&lock->lock);
 }
 
-static inline void __raw_spin_unlock(raw_spinlock_t *lock)
+static inline void arch_spin_unlock(arch_spinlock_t *lock)
 {
         __raw_spin_unlock_asm(&lock->lock);
 }
 
-static inline void __raw_spin_unlock_wait(raw_spinlock_t *lock)
+static inline void arch_spin_unlock_wait(arch_spinlock_t *lock)
 {
-        while (__raw_spin_is_locked(lock))
+        while (arch_spin_is_locked(lock))
                 cpu_relax();
 }
 
-static inline int __raw_read_can_lock(raw_rwlock_t *rw)
+static inline int arch_read_can_lock(arch_rwlock_t *rw)
 {
         return __raw_uncached_fetch_asm(&rw->lock) > 0;
 }
 
-static inline int __raw_write_can_lock(raw_rwlock_t *rw)
+static inline int arch_write_can_lock(arch_rwlock_t *rw)
 {
         return __raw_uncached_fetch_asm(&rw->lock) == RW_LOCK_BIAS;
 }
 
-static inline void __raw_read_lock(raw_rwlock_t *rw)
+static inline void arch_read_lock(arch_rwlock_t *rw)
 {
-        __raw_read_lock_asm(&rw->lock);
+        arch_read_lock_asm(&rw->lock);
 }
 
-static inline int __raw_read_trylock(raw_rwlock_t *rw)
+static inline int arch_read_trylock(arch_rwlock_t *rw)
 {
-        return __raw_read_trylock_asm(&rw->lock);
+        return arch_read_trylock_asm(&rw->lock);
 }
 
-static inline void __raw_read_unlock(raw_rwlock_t *rw)
+static inline void arch_read_unlock(arch_rwlock_t *rw)
 {
-        __raw_read_unlock_asm(&rw->lock);
+        arch_read_unlock_asm(&rw->lock);
 }
 
-static inline void __raw_write_lock(raw_rwlock_t *rw)
+static inline void arch_write_lock(arch_rwlock_t *rw)
 {
-        __raw_write_lock_asm(&rw->lock);
+        arch_write_lock_asm(&rw->lock);
 }
 
-static inline int __raw_write_trylock(raw_rwlock_t *rw)
+static inline int arch_write_trylock(arch_rwlock_t *rw)
 {
-        return __raw_write_trylock_asm(&rw->lock);
+        return arch_write_trylock_asm(&rw->lock);
 }
 
-static inline void __raw_write_unlock(raw_rwlock_t *rw)
+static inline void arch_write_unlock(arch_rwlock_t *rw)
 {
-        __raw_write_unlock_asm(&rw->lock);
+        arch_write_unlock_asm(&rw->lock);
 }
 
-#define _raw_spin_relax(lock)   cpu_relax()
-#define _raw_read_relax(lock)   cpu_relax()
-#define _raw_write_relax(lock)  cpu_relax()
+#define arch_spin_relax(lock)   cpu_relax()
+#define arch_read_relax(lock)   cpu_relax()
+#define arch_write_relax(lock)  cpu_relax()
 
 #endif
 
diff --git a/arch/blackfin/include/asm/spinlock_types.h b/arch/blackfin/include/asm/spinlock_types.h
index be75762c0610..1a33608c958b 100644
--- a/arch/blackfin/include/asm/spinlock_types.h
+++ b/arch/blackfin/include/asm/spinlock_types.h
@@ -15,14 +15,14 @@
 
 typedef struct {
         volatile unsigned int lock;
-} raw_spinlock_t;
+} arch_spinlock_t;
 
-#define __RAW_SPIN_LOCK_UNLOCKED        { 0 }
+#define __ARCH_SPIN_LOCK_UNLOCKED       { 0 }
 
 typedef struct {
         volatile unsigned int lock;
-} raw_rwlock_t;
+} arch_rwlock_t;
 
-#define __RAW_RW_LOCK_UNLOCKED          { RW_LOCK_BIAS }
+#define __ARCH_RW_LOCK_UNLOCKED         { RW_LOCK_BIAS }
 
 #endif
diff --git a/arch/blackfin/include/asm/thread_info.h b/arch/blackfin/include/asm/thread_info.h
index afb3a8626380..a40d9368c38a 100644
--- a/arch/blackfin/include/asm/thread_info.h
+++ b/arch/blackfin/include/asm/thread_info.h
@@ -103,11 +103,13 @@ static inline struct thread_info *current_thread_info(void)
 #define TIF_RESTORE_SIGMASK     5       /* restore signal mask in do_signal() */
 #define TIF_FREEZE              6       /* is freezing for suspend */
 #define TIF_IRQ_SYNC            7       /* sync pipeline stage */
+#define TIF_NOTIFY_RESUME       8       /* callback before returning to user */
 
 /* as above, but as bit values */
 #define _TIF_SYSCALL_TRACE      (1<<TIF_SYSCALL_TRACE)
 #define _TIF_SIGPENDING         (1<<TIF_SIGPENDING)
 #define _TIF_NEED_RESCHED       (1<<TIF_NEED_RESCHED)
+#define _TIF_NOTIFY_RESUME      (1<<TIF_NOTIFY_RESUME)
 #define _TIF_POLLING_NRFLAG     (1<<TIF_POLLING_NRFLAG)
 #define _TIF_RESTORE_SIGMASK    (1<<TIF_RESTORE_SIGMASK)
 #define _TIF_FREEZE             (1<<TIF_FREEZE)
diff --git a/arch/blackfin/include/asm/trace.h b/arch/blackfin/include/asm/trace.h
index 609ad3c84189..dc0aa55ae773 100644
--- a/arch/blackfin/include/asm/trace.h
+++ b/arch/blackfin/include/asm/trace.h
@@ -28,6 +28,8 @@ extern unsigned long software_trace_buff[];
 
 #ifdef CONFIG_DEBUG_BFIN_HWTRACE_ON
 
+#define trace_buffer_init() bfin_write_TBUFCTL(BFIN_TRACE_INIT)
+
 #define trace_buffer_save(x) \
         do { \
                 (x) = bfin_read_TBUFCTL(); \
diff --git a/arch/blackfin/include/asm/uaccess.h b/arch/blackfin/include/asm/uaccess.h
index c03b8532aad3..1c0d190adaef 100644
--- a/arch/blackfin/include/asm/uaccess.h
+++ b/arch/blackfin/include/asm/uaccess.h
@@ -17,9 +17,7 @@
 #include <linux/string.h>
 
 #include <asm/segment.h>
-#ifdef CONFIG_ACCESS_CHECK
-# include <asm/bfin-global.h>
-#endif
+#include <asm/sections.h>
 
 #define get_ds()        (KERNEL_DS)
 #define get_fs()        (current_thread_info()->addr_limit)
diff --git a/arch/blackfin/include/asm/unistd.h b/arch/blackfin/include/asm/unistd.h
index 779be02a910a..22886cbdae7a 100644
--- a/arch/blackfin/include/asm/unistd.h
+++ b/arch/blackfin/include/asm/unistd.h
@@ -388,8 +388,9 @@
 #define __NR_pwritev            367
 #define __NR_rt_tgsigqueueinfo  368
 #define __NR_perf_event_open    369
+#define __NR_recvmmsg           370
 
-#define __NR_syscall            370
+#define __NR_syscall            371
 #define NR_syscalls             __NR_syscall
 
 /* Old optional stuff no one actually uses */
diff --git a/arch/blackfin/kernel/bfin_dma_5xx.c b/arch/blackfin/kernel/bfin_dma_5xx.c
index 3946aff4f414..924c00286bab 100644
--- a/arch/blackfin/kernel/bfin_dma_5xx.c
+++ b/arch/blackfin/kernel/bfin_dma_5xx.c
@@ -37,9 +37,8 @@ static int __init blackfin_dma_init(void)
         printk(KERN_INFO "Blackfin DMA Controller\n");
 
         for (i = 0; i < MAX_DMA_CHANNELS; i++) {
-                dma_ch[i].chan_status = DMA_CHANNEL_FREE;
+                atomic_set(&dma_ch[i].chan_status, 0);
                 dma_ch[i].regs = dma_io_base_addr[i];
-                mutex_init(&(dma_ch[i].dmalock));
         }
         /* Mark MEMDMA Channel 0 as requested since we're using it internally */
         request_dma(CH_MEM_STREAM0_DEST, "Blackfin dma_memcpy");
@@ -60,7 +59,7 @@ static int proc_dma_show(struct seq_file *m, void *v)
         int i;
 
         for (i = 0; i < MAX_DMA_CHANNELS; ++i)
-                if (dma_ch[i].chan_status != DMA_CHANNEL_FREE)
+                if (dma_channel_active(i))
                         seq_printf(m, "%2d: %s\n", i, dma_ch[i].device_id);
 
         return 0;
@@ -107,20 +106,11 @@ int request_dma(unsigned int channel, const char *device_id)
         }
 #endif
 
-        mutex_lock(&(dma_ch[channel].dmalock));
-
-        if ((dma_ch[channel].chan_status == DMA_CHANNEL_REQUESTED)
-            || (dma_ch[channel].chan_status == DMA_CHANNEL_ENABLED)) {
-                mutex_unlock(&(dma_ch[channel].dmalock));
+        if (atomic_cmpxchg(&dma_ch[channel].chan_status, 0, 1)) {
                 pr_debug("DMA CHANNEL IN USE  \n");
                 return -EBUSY;
-        } else {
-                dma_ch[channel].chan_status = DMA_CHANNEL_REQUESTED;
-                pr_debug("DMA CHANNEL IS ALLOCATED  \n");
         }
 
-        mutex_unlock(&(dma_ch[channel].dmalock));
-
 #ifdef CONFIG_BF54x
         if (channel >= CH_UART2_RX && channel <= CH_UART3_TX) {
                 unsigned int per_map;
@@ -148,21 +138,20 @@ EXPORT_SYMBOL(request_dma);
 
 int set_dma_callback(unsigned int channel, irq_handler_t callback, void *data)
 {
-        BUG_ON(channel >= MAX_DMA_CHANNELS ||
-                        dma_ch[channel].chan_status == DMA_CHANNEL_FREE);
+        int ret;
+        unsigned int irq;
 
-        if (callback != NULL) {
-                int ret;
-                unsigned int irq = channel2irq(channel);
+        BUG_ON(channel >= MAX_DMA_CHANNELS || !callback ||
+                        !atomic_read(&dma_ch[channel].chan_status));
 
-                ret = request_irq(irq, callback, IRQF_DISABLED,
-                        dma_ch[channel].device_id, data);
-                if (ret)
-                        return ret;
+        irq = channel2irq(channel);
+        ret = request_irq(irq, callback, 0, dma_ch[channel].device_id, data);
+        if (ret)
+                return ret;
+
+        dma_ch[channel].irq = irq;
+        dma_ch[channel].data = data;
 
-                dma_ch[channel].irq = irq;
-                dma_ch[channel].data = data;
-        }
         return 0;
 }
 EXPORT_SYMBOL(set_dma_callback);
@@ -184,7 +173,7 @@ void free_dma(unsigned int channel)
 {
         pr_debug("freedma() : BEGIN \n");
         BUG_ON(channel >= MAX_DMA_CHANNELS ||
-                        dma_ch[channel].chan_status == DMA_CHANNEL_FREE);
+                        !atomic_read(&dma_ch[channel].chan_status));
 
         /* Halt the DMA */
         disable_dma(channel);
@@ -194,9 +183,7 @@ void free_dma(unsigned int channel)
                 free_irq(dma_ch[channel].irq, dma_ch[channel].data);
 
         /* Clear the DMA Variable in the Channel */
-        mutex_lock(&(dma_ch[channel].dmalock));
-        dma_ch[channel].chan_status = DMA_CHANNEL_FREE;
-        mutex_unlock(&(dma_ch[channel].dmalock));
+        atomic_set(&dma_ch[channel].chan_status, 0);
 
         pr_debug("freedma() : END \n");
 }
@@ -210,13 +197,14 @@ int blackfin_dma_suspend(void)
 {
         int i;
 
-        for (i = 0; i < MAX_DMA_SUSPEND_CHANNELS; ++i) {
-                if (dma_ch[i].chan_status == DMA_CHANNEL_ENABLED) {
+        for (i = 0; i < MAX_DMA_CHANNELS; ++i) {
+                if (dma_ch[i].regs->cfg & DMAEN) {
                         printk(KERN_ERR "DMA Channel %d failed to suspend\n", i);
                         return -EBUSY;
                 }
 
-                dma_ch[i].saved_peripheral_map = dma_ch[i].regs->peripheral_map;
+                if (i < MAX_DMA_SUSPEND_CHANNELS)
+                        dma_ch[i].saved_peripheral_map = dma_ch[i].regs->peripheral_map;
         }
 
         return 0;
diff --git a/arch/blackfin/kernel/bfin_gpio.c b/arch/blackfin/kernel/bfin_gpio.c
index 22705eeff34f..a174596cc009 100644
--- a/arch/blackfin/kernel/bfin_gpio.c
+++ b/arch/blackfin/kernel/bfin_gpio.c
@@ -100,6 +100,12 @@ u8 pmux_offset[][16] = {
 };
 # endif
 
+#elif defined(BF538_FAMILY)
+static unsigned short * const port_fer[] = {
+        (unsigned short *) PORTCIO_FER,
+        (unsigned short *) PORTDIO_FER,
+        (unsigned short *) PORTEIO_FER,
+};
 #endif
 
 static unsigned short reserved_gpio_map[GPIO_BANK_NUM];
@@ -163,6 +169,27 @@ static int cmp_label(unsigned short ident, const char *label)
 
 static void port_setup(unsigned gpio, unsigned short usage)
 {
+#if defined(BF538_FAMILY)
+        /*
+         * BF538/9 Port C,D and E are special.
+         * Inverted PORT_FER polarity on CDE and no PORF_FER on F
+         * Regular PORT F GPIOs are handled here, CDE are exclusively
+         * managed by GPIOLIB
+         */
+
+        if (gpio < MAX_BLACKFIN_GPIOS || gpio >= MAX_RESOURCES)
+                return;
+
+        gpio -= MAX_BLACKFIN_GPIOS;
+
+        if (usage == GPIO_USAGE)
+                *port_fer[gpio_bank(gpio)] |= gpio_bit(gpio);
+        else
+                *port_fer[gpio_bank(gpio)] &= ~gpio_bit(gpio);
+        SSYNC();
+        return;
+#endif
+
         if (check_gpio(gpio))
                 return;
 
@@ -762,6 +789,8 @@ int peripheral_request(unsigned short per, const char *label)
         if (!(per & P_DEFINED))
                 return -ENODEV;
 
+        BUG_ON(ident >= MAX_RESOURCES);
+
         local_irq_save_hw(flags);
 
         /* If a pin can be muxed as either GPIO or peripheral, make
@@ -979,6 +1008,76 @@ void bfin_gpio_free(unsigned gpio)
 }
 EXPORT_SYMBOL(bfin_gpio_free);
 
+#ifdef BFIN_SPECIAL_GPIO_BANKS
+static unsigned short reserved_special_gpio_map[gpio_bank(MAX_RESOURCES)];
+
+int bfin_special_gpio_request(unsigned gpio, const char *label)
+{
+        unsigned long flags;
+
+        local_irq_save_hw(flags);
+
+        /*
+         * Allow that the identical GPIO can
+         * be requested from the same driver twice
+         * Do nothing and return -
+         */
+
+        if (cmp_label(gpio, label) == 0) {
+                local_irq_restore_hw(flags);
+                return 0;
+        }
+
+        if (unlikely(reserved_special_gpio_map[gpio_bank(gpio)] & gpio_bit(gpio))) {
+                local_irq_restore_hw(flags);
+                printk(KERN_ERR "bfin-gpio: GPIO %d is already reserved by %s !\n",
+                       gpio, get_label(gpio));
+
+                return -EBUSY;
+        }
+        if (unlikely(reserved_peri_map[gpio_bank(gpio)] & gpio_bit(gpio))) {
+                local_irq_restore_hw(flags);
+                printk(KERN_ERR
+                       "bfin-gpio: GPIO %d is already reserved as Peripheral by %s !\n",
+                       gpio, get_label(gpio));
+
+                return -EBUSY;
+        }
+
+        reserved_special_gpio_map[gpio_bank(gpio)] |= gpio_bit(gpio);
+        reserved_peri_map[gpio_bank(gpio)] |= gpio_bit(gpio);
+
+        set_label(gpio, label);
+        local_irq_restore_hw(flags);
+        port_setup(gpio, GPIO_USAGE);
+
+        return 0;
+}
+EXPORT_SYMBOL(bfin_special_gpio_request);
+
+void bfin_special_gpio_free(unsigned gpio)
+{
+        unsigned long flags;
+
+        might_sleep();
+
+        local_irq_save_hw(flags);
+
+        if (unlikely(!(reserved_special_gpio_map[gpio_bank(gpio)] & gpio_bit(gpio)))) {
+                gpio_error(gpio);
+                local_irq_restore_hw(flags);
+                return;
+        }
+
+        reserved_special_gpio_map[gpio_bank(gpio)] &= ~gpio_bit(gpio);
+        reserved_peri_map[gpio_bank(gpio)] &= ~gpio_bit(gpio);
+        set_label(gpio, "free");
+        local_irq_restore_hw(flags);
+}
+EXPORT_SYMBOL(bfin_special_gpio_free);
+#endif
+
+
 int bfin_gpio_irq_request(unsigned gpio, const char *label)
 {
         unsigned long flags;
diff --git a/arch/blackfin/kernel/cplb-mpu/cplbinit.c b/arch/blackfin/kernel/cplb-mpu/cplbinit.c
index b52c1f8c4bc0..8d42b9e50dfa 100644
--- a/arch/blackfin/kernel/cplb-mpu/cplbinit.c
+++ b/arch/blackfin/kernel/cplb-mpu/cplbinit.c
@@ -92,6 +92,6 @@ void __init generate_cplb_tables_cpu(unsigned int cpu)
                 icplb_tbl[cpu][i_i++].data = 0;
 }
 
-void generate_cplb_tables_all(void)
+void __init generate_cplb_tables_all(void)
 {
 }
diff --git a/arch/blackfin/kernel/cplb-mpu/cplbmgr.c b/arch/blackfin/kernel/cplb-mpu/cplbmgr.c
index 69e0e530d70f..930c01c06813 100644
--- a/arch/blackfin/kernel/cplb-mpu/cplbmgr.c
+++ b/arch/blackfin/kernel/cplb-mpu/cplbmgr.c
@@ -113,11 +113,11 @@ static noinline int dcplb_miss(unsigned int cpu)
                 addr = L2_START;
                 d_data = L2_DMEMORY;
         } else if (addr >= physical_mem_end) {
-                if (addr >= ASYNC_BANK0_BASE && addr < ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE
-                    && (status & FAULT_USERSUPV)) {
-                        addr &= ~0x3fffff;
+                if (addr >= ASYNC_BANK0_BASE && addr < ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE) {
+                        addr &= ~(4 * 1024 * 1024 - 1);
                         d_data &= ~PAGE_SIZE_4KB;
                         d_data |= PAGE_SIZE_4MB;
+                        d_data |= CPLB_USER_RD | CPLB_USER_WR;
                 } else if (addr >= BOOT_ROM_START && addr < BOOT_ROM_START + BOOT_ROM_LENGTH
                     && (status & (FAULT_RW | FAULT_USERSUPV)) == FAULT_USERSUPV) {
                         addr &= ~(1 * 1024 * 1024 - 1);
@@ -203,7 +203,12 @@ static noinline int icplb_miss(unsigned int cpu)
                 addr = L2_START;
                 i_data = L2_IMEMORY;
         } else if (addr >= physical_mem_end) {
-                if (addr >= BOOT_ROM_START && addr < BOOT_ROM_START + BOOT_ROM_LENGTH
+                if (addr >= ASYNC_BANK0_BASE && addr < ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE) {
+                        addr &= ~(4 * 1024 * 1024 - 1);
+                        i_data &= ~PAGE_SIZE_4KB;
+                        i_data |= PAGE_SIZE_4MB;
+                        i_data |= CPLB_USER_RD;
+                } else if (addr >= BOOT_ROM_START && addr < BOOT_ROM_START + BOOT_ROM_LENGTH
                     && (status & FAULT_USERSUPV)) {
                         addr &= ~(1 * 1024 * 1024 - 1);
                         i_data &= ~PAGE_SIZE_4KB;
diff --git a/arch/blackfin/kernel/cplb-nompu/cplbinit.c b/arch/blackfin/kernel/cplb-nompu/cplbinit.c
index fd9a2f31e686..282a7919821b 100644
--- a/arch/blackfin/kernel/cplb-nompu/cplbinit.c
+++ b/arch/blackfin/kernel/cplb-nompu/cplbinit.c
@@ -89,15 +89,25 @@ void __init generate_cplb_tables_cpu(unsigned int cpu)
 
 void __init generate_cplb_tables_all(void)
 {
+        unsigned long uncached_end;
         int i_d, i_i;
 
         i_d = 0;
         /* Normal RAM, including MTD FS.  */
 #ifdef CONFIG_MTD_UCLINUX
-        dcplb_bounds[i_d].eaddr = memory_mtd_start + mtd_size;
+        uncached_end = memory_mtd_start + mtd_size;
 #else
-        dcplb_bounds[i_d].eaddr = memory_end;
+        uncached_end = memory_end;
 #endif
+        /*
+         * if DMA uncached is less than 1MB, mark the 1MB chunk as uncached
+         * so that we don't have to use 4kB pages and cause CPLB thrashing
+         */
+        if ((DMA_UNCACHED_REGION >= 1 * 1024 * 1024) || !DMA_UNCACHED_REGION ||
+            ((_ramend - uncached_end) >= 1 * 1024 * 1024))
+                dcplb_bounds[i_d].eaddr = uncached_end;
+        else
+                dcplb_bounds[i_d].eaddr = uncached_end & ~(1 * 1024 * 1024);
         dcplb_bounds[i_d++].data = SDRAM_DGENERIC;
         /* DMA uncached region.  */
         if (DMA_UNCACHED_REGION) {
@@ -135,18 +145,15 @@ void __init generate_cplb_tables_all(void)
 
         i_i = 0;
         /* Normal RAM, including MTD FS.  */
-#ifdef CONFIG_MTD_UCLINUX
-        icplb_bounds[i_i].eaddr = memory_mtd_start + mtd_size;
-#else
-        icplb_bounds[i_i].eaddr = memory_end;
-#endif
+        icplb_bounds[i_i].eaddr = uncached_end;
         icplb_bounds[i_i++].data = SDRAM_IGENERIC;
-        /* DMA uncached region.  */
-        if (DMA_UNCACHED_REGION) {
-                icplb_bounds[i_i].eaddr = _ramend;
-                icplb_bounds[i_i++].data = 0;
-        }
         if (_ramend != physical_mem_end) {
+                /* DMA uncached region.  */
+                if (DMA_UNCACHED_REGION) {
+                        /* Normally this hole is caught by the async below.  */
+                        icplb_bounds[i_i].eaddr = _ramend;
+                        icplb_bounds[i_i++].data = 0;
+                }
                 /* Reserved memory.  */
                 icplb_bounds[i_i].eaddr = physical_mem_end;
                 icplb_bounds[i_i++].data = (reserved_mem_icache_on ?
diff --git a/arch/blackfin/kernel/dma-mapping.c b/arch/blackfin/kernel/dma-mapping.c
index e74e74d7733f..e937f323d82c 100644
--- a/arch/blackfin/kernel/dma-mapping.c
+++ b/arch/blackfin/kernel/dma-mapping.c
@@ -7,30 +7,25 @@
  */
 
 #include <linux/types.h>
-#include <linux/mm.h>
+#include <linux/gfp.h>
 #include <linux/string.h>
-#include <linux/bootmem.h>
 #include <linux/spinlock.h>
-#include <linux/device.h>
 #include <linux/dma-mapping.h>
-#include <linux/io.h>
 #include <linux/scatterlist.h>
-#include <asm/cacheflush.h>
-#include <asm/bfin-global.h>
 
 static spinlock_t dma_page_lock;
-static unsigned int *dma_page;
+static unsigned long *dma_page;
 static unsigned int dma_pages;
 static unsigned long dma_base;
 static unsigned long dma_size;
 static unsigned int dma_initialized;
 
-void dma_alloc_init(unsigned long start, unsigned long end)
+static void dma_alloc_init(unsigned long start, unsigned long end)
 {
         spin_lock_init(&dma_page_lock);
         dma_initialized = 0;
 
-        dma_page = (unsigned int *)__get_free_page(GFP_KERNEL);
+        dma_page = (unsigned long *)__get_free_page(GFP_KERNEL);
         memset(dma_page, 0, PAGE_SIZE);
         dma_base = PAGE_ALIGN(start);
         dma_size = PAGE_ALIGN(end) - PAGE_ALIGN(start);
@@ -58,10 +53,11 @@ static unsigned long __alloc_dma_pages(unsigned int pages)
         spin_lock_irqsave(&dma_page_lock, flags);
 
         for (i = 0; i < dma_pages;) {
-                if (dma_page[i++] == 0) {
+                if (test_bit(i++, dma_page) == 0) {
                         if (++count == pages) {
                                 while (count--)
-                                        dma_page[--i] = 1;
+                                        __set_bit(--i, dma_page);
+
                                 ret = dma_base + (i << PAGE_SHIFT);
                                 break;
                         }
@@ -84,14 +80,14 @@ static void __free_dma_pages(unsigned long addr, unsigned int pages)
         }
 
         spin_lock_irqsave(&dma_page_lock, flags);
-        for (i = page; i < page + pages; i++) {
-                dma_page[i] = 0;
-        }
+        for (i = page; i < page + pages; i++)
+                __clear_bit(i, dma_page);
+
         spin_unlock_irqrestore(&dma_page_lock, flags);
 }
 
 void *dma_alloc_coherent(struct device *dev, size_t size,
-                         dma_addr_t * dma_handle, gfp_t gfp)
+                         dma_addr_t *dma_handle, gfp_t gfp)
 {
         void *ret;
 
@@ -115,21 +111,14 @@ dma_free_coherent(struct device *dev, size_t size, void *vaddr,
 EXPORT_SYMBOL(dma_free_coherent);
 
 /*
- * Dummy functions defined for some existing drivers
+ * Streaming DMA mappings
  */
-
-dma_addr_t
-dma_map_single(struct device *dev, void *ptr, size_t size,
-               enum dma_data_direction direction)
+void __dma_sync(dma_addr_t addr, size_t size,
+                enum dma_data_direction dir)
 {
-        BUG_ON(direction == DMA_NONE);
-
-        invalidate_dcache_range((unsigned long)ptr,
-                        (unsigned long)ptr + size);
-
-        return (dma_addr_t) ptr;
+        _dma_sync(addr, size, dir);
 }
-EXPORT_SYMBOL(dma_map_single);
+EXPORT_SYMBOL(__dma_sync);
 
 int
 dma_map_sg(struct device *dev, struct scatterlist *sg, int nents,
@@ -137,30 +126,23 @@ dma_map_sg(struct device *dev, struct scatterlist *sg, int nents,
 {
         int i;
 
-        BUG_ON(direction == DMA_NONE);
-
         for (i = 0; i < nents; i++, sg++) {
                 sg->dma_address = (dma_addr_t) sg_virt(sg);
-
-                invalidate_dcache_range(sg_dma_address(sg),
-                                        sg_dma_address(sg) +
-                                        sg_dma_len(sg));
+                __dma_sync(sg_dma_address(sg), sg_dma_len(sg), direction);
         }
 
         return nents;
 }
 EXPORT_SYMBOL(dma_map_sg);
 
-void dma_unmap_single(struct device *dev, dma_addr_t dma_addr, size_t size,
-                enum dma_data_direction direction)
+void dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg,
+                            int nelems, enum dma_data_direction direction)
 {
-        BUG_ON(direction == DMA_NONE);
-}
-EXPORT_SYMBOL(dma_unmap_single);
+        int i;
 
-void dma_unmap_sg(struct device *dev, struct scatterlist *sg,
-                int nhwentries, enum dma_data_direction direction)
-{
-        BUG_ON(direction == DMA_NONE);
+        for (i = 0; i < nelems; i++, sg++) {
+                sg->dma_address = (dma_addr_t) sg_virt(sg);
+                __dma_sync(sg_dma_address(sg), sg_dma_len(sg), direction);
+        }
 }
-EXPORT_SYMBOL(dma_unmap_sg);
+EXPORT_SYMBOL(dma_sync_sg_for_device);
diff --git a/arch/blackfin/kernel/gptimers.c b/arch/blackfin/kernel/gptimers.c
index 7281a91d26b5..cdbe075de1dc 100644
--- a/arch/blackfin/kernel/gptimers.c
+++ b/arch/blackfin/kernel/gptimers.c
@@ -137,7 +137,7 @@ static uint32_t const timil_mask[MAX_BLACKFIN_GPTIMERS] =
 #endif
 };
 
-void set_gptimer_pwidth(int timer_id, uint32_t value)
+void set_gptimer_pwidth(unsigned int timer_id, uint32_t value)
 {
         tassert(timer_id < MAX_BLACKFIN_GPTIMERS);
         timer_regs[timer_id]->width = value;
@@ -145,14 +145,14 @@ void set_gptimer_pwidth(int timer_id, uint32_t value)
 }
 EXPORT_SYMBOL(set_gptimer_pwidth);
 
-uint32_t get_gptimer_pwidth(int timer_id)
+uint32_t get_gptimer_pwidth(unsigned int timer_id)
 {
         tassert(timer_id < MAX_BLACKFIN_GPTIMERS);
         return timer_regs[timer_id]->width;
 }
 EXPORT_SYMBOL(get_gptimer_pwidth);
 
-void set_gptimer_period(int timer_id, uint32_t period)
+void set_gptimer_period(unsigned int timer_id, uint32_t period)
 {
         tassert(timer_id < MAX_BLACKFIN_GPTIMERS);
         timer_regs[timer_id]->period = period;
@@ -160,28 +160,28 @@ void set_gptimer_period(int timer_id, uint32_t period)
 }
 EXPORT_SYMBOL(set_gptimer_period);
 
-uint32_t get_gptimer_period(int timer_id)
+uint32_t get_gptimer_period(unsigned int timer_id)
 {
         tassert(timer_id < MAX_BLACKFIN_GPTIMERS);
         return timer_regs[timer_id]->period;
 }
 EXPORT_SYMBOL(get_gptimer_period);
 
-uint32_t get_gptimer_count(int timer_id)
+uint32_t get_gptimer_count(unsigned int timer_id)
 {
         tassert(timer_id < MAX_BLACKFIN_GPTIMERS);
         return timer_regs[timer_id]->counter;
 }
 EXPORT_SYMBOL(get_gptimer_count);
 
-uint32_t get_gptimer_status(int group)
+uint32_t get_gptimer_status(unsigned int group)
 {
         tassert(group < BFIN_TIMER_NUM_GROUP);
         return group_regs[group]->status;
 }
 EXPORT_SYMBOL(get_gptimer_status);
 
-void set_gptimer_status(int group, uint32_t value)
+void set_gptimer_status(unsigned int group, uint32_t value)
 {
         tassert(group < BFIN_TIMER_NUM_GROUP);
         group_regs[group]->status = value;
@@ -189,42 +189,42 @@ void set_gptimer_status(int group, uint32_t value)
 }
 EXPORT_SYMBOL(set_gptimer_status);
 
-int get_gptimer_intr(int timer_id)
+int get_gptimer_intr(unsigned int timer_id)
 {
         tassert(timer_id < MAX_BLACKFIN_GPTIMERS);
         return !!(group_regs[BFIN_TIMER_OCTET(timer_id)]->status & timil_mask[timer_id]);
 }
 EXPORT_SYMBOL(get_gptimer_intr);
 
-void clear_gptimer_intr(int timer_id)
+void clear_gptimer_intr(unsigned int timer_id)
 {
         tassert(timer_id < MAX_BLACKFIN_GPTIMERS);
         group_regs[BFIN_TIMER_OCTET(timer_id)]->status = timil_mask[timer_id];
 }
 EXPORT_SYMBOL(clear_gptimer_intr);
 
-int get_gptimer_over(int timer_id)
+int get_gptimer_over(unsigned int timer_id)
 {
         tassert(timer_id < MAX_BLACKFIN_GPTIMERS);
         return !!(group_regs[BFIN_TIMER_OCTET(timer_id)]->status & tovf_mask[timer_id]);
 }
 EXPORT_SYMBOL(get_gptimer_over);
 
-void clear_gptimer_over(int timer_id)
+void clear_gptimer_over(unsigned int timer_id)
 {
         tassert(timer_id < MAX_BLACKFIN_GPTIMERS);
         group_regs[BFIN_TIMER_OCTET(timer_id)]->status = tovf_mask[timer_id];
 }
 EXPORT_SYMBOL(clear_gptimer_over);
 
-int get_gptimer_run(int timer_id)
+int get_gptimer_run(unsigned int timer_id)
 {
         tassert(timer_id < MAX_BLACKFIN_GPTIMERS);
         return !!(group_regs[BFIN_TIMER_OCTET(timer_id)]->status & trun_mask[timer_id]);
 }
 EXPORT_SYMBOL(get_gptimer_run);
 
-void set_gptimer_config(int timer_id, uint16_t config)
+void set_gptimer_config(unsigned int timer_id, uint16_t config)
 {
         tassert(timer_id < MAX_BLACKFIN_GPTIMERS);
         timer_regs[timer_id]->config = config;
@@ -232,7 +232,7 @@ void set_gptimer_config(int timer_id, uint16_t config)
 }
 EXPORT_SYMBOL(set_gptimer_config);
 
-uint16_t get_gptimer_config(int timer_id)
+uint16_t get_gptimer_config(unsigned int timer_id)
 {
         tassert(timer_id < MAX_BLACKFIN_GPTIMERS);
         return timer_regs[timer_id]->config;
@@ -280,7 +280,7 @@ void disable_gptimers_sync(uint16_t mask)
 }
 EXPORT_SYMBOL(disable_gptimers_sync);
 
-void set_gptimer_pulse_hi(int timer_id)
+void set_gptimer_pulse_hi(unsigned int timer_id)
 {
         tassert(timer_id < MAX_BLACKFIN_GPTIMERS);
         timer_regs[timer_id]->config |= TIMER_PULSE_HI;
@@ -288,7 +288,7 @@ void set_gptimer_pulse_hi(int timer_id)
 }
 EXPORT_SYMBOL(set_gptimer_pulse_hi);
 
-void clear_gptimer_pulse_hi(int timer_id)
+void clear_gptimer_pulse_hi(unsigned int timer_id)
 {
         tassert(timer_id < MAX_BLACKFIN_GPTIMERS);
         timer_regs[timer_id]->config &= ~TIMER_PULSE_HI;
diff --git a/arch/blackfin/kernel/ipipe.c b/arch/blackfin/kernel/ipipe.c
index 5d7382396dc0..a77307a4473b 100644
--- a/arch/blackfin/kernel/ipipe.c
+++ b/arch/blackfin/kernel/ipipe.c
@@ -335,3 +335,70 @@ void __ipipe_enable_root_irqs_hw(void)
         __clear_bit(IPIPE_STALL_FLAG, &ipipe_root_cpudom_var(status));
         bfin_sti(bfin_irq_flags);
 }
+
+/*
+ * We could use standard atomic bitops in the following root status
+ * manipulation routines, but let's prepare for SMP support in the
+ * same move, preventing CPU migration as required.
+ */
+void __ipipe_stall_root(void)
+{
+        unsigned long *p, flags;
+
+        local_irq_save_hw(flags);
+        p = &__ipipe_root_status;
+        __set_bit(IPIPE_STALL_FLAG, p);
+        local_irq_restore_hw(flags);
+}
+EXPORT_SYMBOL(__ipipe_stall_root);
+
+unsigned long __ipipe_test_and_stall_root(void)
+{
+        unsigned long *p, flags;
+        int x;
+
+        local_irq_save_hw(flags);
+        p = &__ipipe_root_status;
+        x = __test_and_set_bit(IPIPE_STALL_FLAG, p);
+        local_irq_restore_hw(flags);
+
+        return x;
+}
+EXPORT_SYMBOL(__ipipe_test_and_stall_root);
+
+unsigned long __ipipe_test_root(void)
+{
+        const unsigned long *p;
+        unsigned long flags;
+        int x;
+
+        local_irq_save_hw_smp(flags);
+        p = &__ipipe_root_status;
+        x = test_bit(IPIPE_STALL_FLAG, p);
+        local_irq_restore_hw_smp(flags);
+
+        return x;
+}
+EXPORT_SYMBOL(__ipipe_test_root);
+
+void __ipipe_lock_root(void)
+{
+        unsigned long *p, flags;
+
+        local_irq_save_hw(flags);
+        p = &__ipipe_root_status;
+        __set_bit(IPIPE_SYNCDEFER_FLAG, p);
+        local_irq_restore_hw(flags);
+}
+EXPORT_SYMBOL(__ipipe_lock_root);
+
+void __ipipe_unlock_root(void)
+{
+        unsigned long *p, flags;
+
+        local_irq_save_hw(flags);
+        p = &__ipipe_root_status;
+        __clear_bit(IPIPE_SYNCDEFER_FLAG, p);
+        local_irq_restore_hw(flags);
+}
+EXPORT_SYMBOL(__ipipe_unlock_root);
diff --git a/arch/blackfin/kernel/irqchip.c b/arch/blackfin/kernel/irqchip.c
index db9f9c91f11f..64cff54a8a58 100644
--- a/arch/blackfin/kernel/irqchip.c
+++ b/arch/blackfin/kernel/irqchip.c
@@ -23,7 +23,7 @@ void ack_bad_irq(unsigned int irq)
 
 static struct irq_desc bad_irq_desc = {
         .handle_irq = handle_bad_irq,
-        .lock = __SPIN_LOCK_UNLOCKED(irq_desc->lock),
+        .lock = __RAW_SPIN_LOCK_UNLOCKED(bad_irq_desc.lock),
 };
 
 #ifdef CONFIG_CPUMASK_OFFSTACK
@@ -39,7 +39,7 @@ int show_interrupts(struct seq_file *p, void *v)
         unsigned long flags;
 
         if (i < NR_IRQS) {
-                spin_lock_irqsave(&irq_desc[i].lock, flags);
+                raw_spin_lock_irqsave(&irq_desc[i].lock, flags);
                 action = irq_desc[i].action;
                 if (!action)
                         goto skip;
@@ -53,7 +53,7 @@ int show_interrupts(struct seq_file *p, void *v)
 
                 seq_putc(p, '\n');
  skip:
-                spin_unlock_irqrestore(&irq_desc[i].lock, flags);
+                raw_spin_unlock_irqrestore(&irq_desc[i].lock, flags);
         } else if (i == NR_IRQS) {
                 seq_printf(p, "NMI: ");
                 for_each_online_cpu(j)
diff --git a/arch/blackfin/kernel/kgdb.c b/arch/blackfin/kernel/kgdb.c
index cce79d05b90b..f1036b6b9293 100644
--- a/arch/blackfin/kernel/kgdb.c
+++ b/arch/blackfin/kernel/kgdb.c
@@ -24,16 +24,6 @@
 #include <asm/blackfin.h>
 #include <asm/dma.h>
 
-/* Put the error code here just in case the user cares.  */
-int gdb_bfin_errcode;
-/* Likewise, the vector number here (since GDB only gets the signal
-   number through the usual means, and that's not very specific).  */
-int gdb_bfin_vector = -1;
-
-#if KGDB_MAX_NO_CPUS != 8
-#error change the definition of slavecpulocks
-#endif
-
 void pt_regs_to_gdb_regs(unsigned long *gdb_regs, struct pt_regs *regs)
 {
         gdb_regs[BFIN_R0] = regs->r0;
@@ -369,13 +359,6 @@ void kgdb_roundup_cpu(int cpu, unsigned long flags)
 }
 #endif
 
-void kgdb_post_primary_code(struct pt_regs *regs, int eVector, int err_code)
-{
-        /* Master processor is completely in the debugger */
-        gdb_bfin_vector = eVector;
-        gdb_bfin_errcode = err_code;
-}
-
 int kgdb_arch_handle_exception(int vector, int signo,
                                int err_code, char *remcom_in_buffer,
                                char *remcom_out_buffer,
diff --git a/arch/blackfin/kernel/kgdb_test.c b/arch/blackfin/kernel/kgdb_test.c
index 59fc42dc5d6a..9a4b07594389 100644
--- a/arch/blackfin/kernel/kgdb_test.c
+++ b/arch/blackfin/kernel/kgdb_test.c
@@ -17,8 +17,9 @@
 
 #include <asm/blackfin.h>
 
+/* Symbols are here for kgdb test to poke directly */
 static char cmdline[256];
-static unsigned long len;
+static size_t len;
 
 #ifndef CONFIG_SMP
 static int num1 __attribute__((l1_data));
@@ -27,11 +28,10 @@ void kgdb_l1_test(void) __attribute__((l1_text));
 
 void kgdb_l1_test(void)
 {
-        printk(KERN_ALERT "L1(before change) : data variable addr = 0x%p, data value is %d\n", &num1, num1);
-        printk(KERN_ALERT "L1 : code function addr = 0x%p\n", kgdb_l1_test);
-        num1 = num1 + 10 ;
-        printk(KERN_ALERT "L1(after change) : data variable addr = 0x%p, data value is %d\n", &num1, num1);
-        return ;
+        pr_alert("L1(before change) : data variable addr = 0x%p, data value is %d\n", &num1, num1);
+        pr_alert("L1 : code function addr = 0x%p\n", kgdb_l1_test);
+        num1 = num1 + 10;
+        pr_alert("L1(after change) : data variable addr = 0x%p, data value is %d\n", &num1, num1);
 }
 #endif
 
@@ -42,11 +42,10 @@ void kgdb_l2_test(void) __attribute__((l2));
 
 void kgdb_l2_test(void)
 {
-        printk(KERN_ALERT "L2(before change) : data variable addr = 0x%p, data value is %d\n", &num2, num2);
-        printk(KERN_ALERT "L2 : code function addr = 0x%p\n", kgdb_l2_test);
-        num2 = num2 + 20 ;
-        printk(KERN_ALERT "L2(after change) : data variable addr = 0x%p, data value is %d\n", &num2, num2);
-        return ;
+        pr_alert("L2(before change) : data variable addr = 0x%p, data value is %d\n", &num2, num2);
+        pr_alert("L2 : code function addr = 0x%p\n", kgdb_l2_test);
+        num2 = num2 + 20;
+        pr_alert("L2(after change) : data variable addr = 0x%p, data value is %d\n", &num2, num2);
 }
 
 #endif
@@ -54,12 +53,14 @@ void kgdb_l2_test(void)
 
 int kgdb_test(char *name, int len, int count, int z)
 {
-        printk(KERN_ALERT "kgdb name(%d): %s, %d, %d\n", len, name, count, z);
+        pr_alert("kgdb name(%d): %s, %d, %d\n", len, name, count, z);
         count = z;
         return count;
 }
 
-static int test_proc_output(char *buf)
+static ssize_t
+kgdb_test_proc_read(struct file *file, char __user *buf,
+                    size_t count, loff_t *ppos)
 {
         kgdb_test("hello world!", 12, 0x55, 0x10);
 #ifndef CONFIG_SMP
@@ -72,49 +73,31 @@ static int test_proc_output(char *buf)
         return 0;
 }
 
-static int test_read_proc(char *page, char **start, off_t off,
-                                 int count, int *eof, void *data)
+static ssize_t
+kgdb_test_proc_write(struct file *file, const char __user *buffer,
+                     size_t count, loff_t *pos)
 {
-        int len;
-
-        len = test_proc_output(page);
-        if (len <= off+count)
-                *eof = 1;
-        *start = page + off;
-        len -= off;
-        if (len > count)
-                len = count;
-        if (len < 0)
-                len = 0;
-        return len;
-}
-
-static int test_write_proc(struct file *file, const char *buffer,
-                                 unsigned long count, void *data)
-{
-        if (count >= 256)
-                len = 255;
-        else
-                len = count;
-
+        len = min_t(size_t, 255, count);
         memcpy(cmdline, buffer, count);
         cmdline[len] = 0;
 
         return len;
 }
 
+static const struct file_operations kgdb_test_proc_fops = {
+        .owner = THIS_MODULE,
+        .read  = kgdb_test_proc_read,
+        .write = kgdb_test_proc_write,
+};
+
 static int __init kgdbtest_init(void)
 {
         struct proc_dir_entry *entry;
 
-        entry = create_proc_entry("kgdbtest", 0, NULL);
+        entry = proc_create("kgdbtest", 0, NULL, &kgdb_test_proc_fops);
         if (entry == NULL)
                 return -ENOMEM;
 
-        entry->read_proc = test_read_proc;
-        entry->write_proc = test_write_proc;
-        entry->data = NULL;
-
         return 0;
 }
 
diff --git a/arch/blackfin/kernel/process.c b/arch/blackfin/kernel/process.c
index 45876427eb2d..b56b0e485e0b 100644
--- a/arch/blackfin/kernel/process.c
+++ b/arch/blackfin/kernel/process.c
@@ -258,9 +258,12 @@ void finish_atomic_sections (struct pt_regs *regs)
         int __user *up0 = (int __user *)regs->p0;
 
         switch (regs->pc) {
+        default:
+                /* not in middle of an atomic step, so resume like normal */
+                return;
+
         case ATOMIC_XCHG32 + 2:
                 put_user(regs->r1, up0);
-                regs->pc = ATOMIC_XCHG32 + 4;
                 break;
 
         case ATOMIC_CAS32 + 2:
@@ -268,7 +271,6 @@ void finish_atomic_sections (struct pt_regs *regs)
                 if (regs->r0 == regs->r1)
         case ATOMIC_CAS32 + 6:
                         put_user(regs->r2, up0);
-                regs->pc = ATOMIC_CAS32 + 8;
                 break;
 
         case ATOMIC_ADD32 + 2:
@@ -276,7 +278,6 @@ void finish_atomic_sections (struct pt_regs *regs)
                 /* fall through */
         case ATOMIC_ADD32 + 4:
                 put_user(regs->r0, up0);
-                regs->pc = ATOMIC_ADD32 + 6;
                 break;
 
         case ATOMIC_SUB32 + 2:
@@ -284,7 +285,6 @@ void finish_atomic_sections (struct pt_regs *regs)
                 /* fall through */
         case ATOMIC_SUB32 + 4:
                 put_user(regs->r0, up0);
-                regs->pc = ATOMIC_SUB32 + 6;
                 break;
 
         case ATOMIC_IOR32 + 2:
@@ -292,7 +292,6 @@ void finish_atomic_sections (struct pt_regs *regs)
                 /* fall through */
         case ATOMIC_IOR32 + 4:
                 put_user(regs->r0, up0);
-                regs->pc = ATOMIC_IOR32 + 6;
                 break;
 
         case ATOMIC_AND32 + 2:
@@ -300,7 +299,6 @@ void finish_atomic_sections (struct pt_regs *regs)
                 /* fall through */
         case ATOMIC_AND32 + 4:
                 put_user(regs->r0, up0);
-                regs->pc = ATOMIC_AND32 + 6;
                 break;
 
         case ATOMIC_XOR32 + 2:
@@ -308,9 +306,15 @@ void finish_atomic_sections (struct pt_regs *regs)
                 /* fall through */
         case ATOMIC_XOR32 + 4:
                 put_user(regs->r0, up0);
-                regs->pc = ATOMIC_XOR32 + 6;
                 break;
         }
+
+        /*
+         * We've finished the atomic section, and the only thing left for
+         * userspace is to do a RTS, so we might as well handle that too
+         * since we need to update the PC anyways.
+         */
+        regs->pc = regs->rets;
 }
 
 static inline
@@ -332,12 +336,58 @@ int in_mem_const(unsigned long addr, unsigned long size,
 {
         return in_mem_const_off(addr, size, 0, const_addr, const_size);
 }
-#define IN_ASYNC(bnum, bctlnum) \
+#define ASYNC_ENABLED(bnum, bctlnum) \
 ({ \
-        (bfin_read_EBIU_AMGCTL() & 0xe) < ((bnum + 1) << 1) ? -EFAULT : \
-        bfin_read_EBIU_AMBCTL##bctlnum() & B##bnum##RDYEN ? -EFAULT : \
-        BFIN_MEM_ACCESS_CORE; \
+        (bfin_read_EBIU_AMGCTL() & 0xe) < ((bnum + 1) << 1) ? 0 : \
+        bfin_read_EBIU_AMBCTL##bctlnum() & B##bnum##RDYEN ? 0 : \
+        1; \
 })
+/*
+ * We can't read EBIU banks that aren't enabled or we end up hanging
+ * on the access to the async space.  Make sure we validate accesses
+ * that cross async banks too.
+ *      0 - found, but unusable
+ *      1 - found & usable
+ *      2 - not found
+ */
+static
+int in_async(unsigned long addr, unsigned long size)
+{
+        if (addr >= ASYNC_BANK0_BASE && addr < ASYNC_BANK0_BASE + ASYNC_BANK0_SIZE) {
+                if (!ASYNC_ENABLED(0, 0))
+                        return 0;
+                if (addr + size <= ASYNC_BANK0_BASE + ASYNC_BANK0_SIZE)
+                        return 1;
+                size -= ASYNC_BANK0_BASE + ASYNC_BANK0_SIZE - addr;
+                addr = ASYNC_BANK0_BASE + ASYNC_BANK0_SIZE;
+        }
+        if (addr >= ASYNC_BANK1_BASE && addr < ASYNC_BANK1_BASE + ASYNC_BANK1_SIZE) {
+                if (!ASYNC_ENABLED(1, 0))
+                        return 0;
+                if (addr + size <= ASYNC_BANK1_BASE + ASYNC_BANK1_SIZE)
+                        return 1;
+                size -= ASYNC_BANK1_BASE + ASYNC_BANK1_SIZE - addr;
+                addr = ASYNC_BANK1_BASE + ASYNC_BANK1_SIZE;
+        }
+        if (addr >= ASYNC_BANK2_BASE && addr < ASYNC_BANK2_BASE + ASYNC_BANK2_SIZE) {
+                if (!ASYNC_ENABLED(2, 1))
+                        return 0;
+                if (addr + size <= ASYNC_BANK2_BASE + ASYNC_BANK2_SIZE)
+                        return 1;
+                size -= ASYNC_BANK2_BASE + ASYNC_BANK2_SIZE - addr;
+                addr = ASYNC_BANK2_BASE + ASYNC_BANK2_SIZE;
+        }
+        if (addr >= ASYNC_BANK3_BASE && addr < ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE) {
+                if (ASYNC_ENABLED(3, 1))
+                        return 0;
+                if (addr + size <= ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE)
+                        return 1;
+                return 0;
+        }
+
+        /* not within async bounds */
+        return 2;
+}
 
 int bfin_mem_access_type(unsigned long addr, unsigned long size)
 {
@@ -374,17 +424,11 @@ int bfin_mem_access_type(unsigned long addr, unsigned long size)
         if (addr >= SYSMMR_BASE)
                 return BFIN_MEM_ACCESS_CORE_ONLY;
 
-        /* We can't read EBIU banks that aren't enabled or we end up hanging
-         * on the access to the async space.
-         */
-        if (in_mem_const(addr, size, ASYNC_BANK0_BASE, ASYNC_BANK0_SIZE))
-                return IN_ASYNC(0, 0);
-        if (in_mem_const(addr, size, ASYNC_BANK1_BASE, ASYNC_BANK1_SIZE))
-                return IN_ASYNC(1, 0);
-        if (in_mem_const(addr, size, ASYNC_BANK2_BASE, ASYNC_BANK2_SIZE))
-                return IN_ASYNC(2, 1);
-        if (in_mem_const(addr, size, ASYNC_BANK3_BASE, ASYNC_BANK3_SIZE))
-                return IN_ASYNC(3, 1);
+        switch (in_async(addr, size)) {
+        case 0: return -EFAULT;
+        case 1: return BFIN_MEM_ACCESS_CORE;
+        case 2: /* fall through */;
+        }
 
         if (in_mem_const(addr, size, BOOT_ROM_START, BOOT_ROM_LENGTH))
                 return BFIN_MEM_ACCESS_CORE;
@@ -401,6 +445,8 @@ __attribute__((l1_text))
 /* Return 1 if access to memory range is OK, 0 otherwise */
 int _access_ok(unsigned long addr, unsigned long size)
 {
+        int aret;
+
         if (size == 0)
                 return 1;
         /* Check that things do not wrap around */
@@ -450,6 +496,11 @@ int _access_ok(unsigned long addr, unsigned long size)
         if (in_mem_const(addr, size, COREB_L1_DATA_B_START, COREB_L1_DATA_B_LENGTH))
                 return 1;
 #endif
+
+        aret = in_async(addr, size);
+        if (aret < 2)
+                return aret;
+
         if (in_mem_const_off(addr, size, _ebss_l2 - _stext_l2, L2_START, L2_LENGTH))
                 return 1;
 
diff --git a/arch/blackfin/kernel/ptrace.c b/arch/blackfin/kernel/ptrace.c
index 56b0ba12175f..65567dc4b9f5 100644
--- a/arch/blackfin/kernel/ptrace.c
+++ b/arch/blackfin/kernel/ptrace.c
@@ -316,19 +316,6 @@ long arch_ptrace(struct task_struct *child, long request, long addr, long data)
                         case BFIN_MEM_ACCESS_CORE_ONLY:
                                 copied = access_process_vm(child, addr, &data,
                                                            to_copy, 1);
-                                if (copied)
-                                        break;
-
-                                /* hrm, why didn't that work ... maybe no mapping */
-                                if (addr >= FIXED_CODE_START &&
-                                    addr + to_copy <= FIXED_CODE_END) {
-                                        copy_to_user_page(0, 0, 0, paddr, &data, to_copy);
-                                        copied = to_copy;
-                                } else if (addr >= BOOT_ROM_START) {
-                                        memcpy(paddr, &data, to_copy);
-                                        copied = to_copy;
-                                }
-
                                 break;
                         case BFIN_MEM_ACCESS_DMA:
                                 if (safe_dma_memcpy(paddr, &data, to_copy))
diff --git a/arch/blackfin/kernel/setup.c b/arch/blackfin/kernel/setup.c
index c202a44d1416..95448ae9c43a 100644
--- a/arch/blackfin/kernel/setup.c
+++ b/arch/blackfin/kernel/setup.c
@@ -178,10 +178,10 @@ void __init bfin_cache_init(void)
 
 void __init bfin_relocate_l1_mem(void)
 {
-        unsigned long l1_code_length;
-        unsigned long l1_data_a_length;
-        unsigned long l1_data_b_length;
-        unsigned long l2_length;
+        unsigned long text_l1_len = (unsigned long)_text_l1_len;
+        unsigned long data_l1_len = (unsigned long)_data_l1_len;
+        unsigned long data_b_l1_len = (unsigned long)_data_b_l1_len;
+        unsigned long l2_len = (unsigned long)_l2_len;
 
         early_shadow_stamp();
 
@@ -201,30 +201,23 @@ void __init bfin_relocate_l1_mem(void)
 
         blackfin_dma_early_init();
 
-        /* if necessary, copy _stext_l1 to _etext_l1 to L1 instruction SRAM */
-        l1_code_length = _etext_l1 - _stext_l1;
-        if (l1_code_length)
-                early_dma_memcpy(_stext_l1, _l1_lma_start, l1_code_length);
+        /* if necessary, copy L1 text to L1 instruction SRAM */
+        if (L1_CODE_LENGTH && text_l1_len)
+                early_dma_memcpy(_stext_l1, _text_l1_lma, text_l1_len);
 
-        /* if necessary, copy _sdata_l1 to _sbss_l1 to L1 data bank A SRAM */
-        l1_data_a_length = _sbss_l1 - _sdata_l1;
-        if (l1_data_a_length)
-                early_dma_memcpy(_sdata_l1, _l1_lma_start + l1_code_length, l1_data_a_length);
+        /* if necessary, copy L1 data to L1 data bank A SRAM */
+        if (L1_DATA_A_LENGTH && data_l1_len)
+                early_dma_memcpy(_sdata_l1, _data_l1_lma, data_l1_len);
 
-        /* if necessary, copy _sdata_b_l1 to _sbss_b_l1 to L1 data bank B SRAM */
-        l1_data_b_length = _sbss_b_l1 - _sdata_b_l1;
-        if (l1_data_b_length)
-                early_dma_memcpy(_sdata_b_l1, _l1_lma_start + l1_code_length +
-                        l1_data_a_length, l1_data_b_length);
+        /* if necessary, copy L1 data B to L1 data bank B SRAM */
+        if (L1_DATA_B_LENGTH && data_b_l1_len)
+                early_dma_memcpy(_sdata_b_l1, _data_b_l1_lma, data_b_l1_len);
 
         early_dma_memcpy_done();
 
-        /* if necessary, copy _stext_l2 to _edata_l2 to L2 SRAM */
-        if (L2_LENGTH != 0) {
-                l2_length = _sbss_l2 - _stext_l2;
-                if (l2_length)
-                        memcpy(_stext_l2, _l2_lma_start, l2_length);
-        }
+        /* if necessary, copy L2 text/data to L2 SRAM */
+        if (L2_LENGTH && l2_len)
+                memcpy(_stext_l2, _l2_lma, l2_len);
 }
 
 /* add_memory_region to memmap */
@@ -608,11 +601,6 @@ static __init void memory_setup(void)
         page_mask_order = get_order(3 * page_mask_nelts * sizeof(long));
 #endif
 
-#if !defined(CONFIG_MTD_UCLINUX)
-        /*In case there is no valid CPLB behind memory_end make sure we don't get to close*/
-        memory_end -= SIZE_4K;
-#endif
-
         init_mm.start_code = (unsigned long)_stext;
         init_mm.end_code = (unsigned long)_etext;
         init_mm.end_data = (unsigned long)_edata;
@@ -917,7 +905,7 @@ void __init setup_arch(char **cmdline_p)
 
         printk(KERN_INFO "Blackfin support (C) 2004-2009 Analog Devices, Inc.\n");
         if (bfin_compiled_revid() == 0xffff)
-                printk(KERN_INFO "Compiled for ADSP-%s Rev any\n", CPU);
+                printk(KERN_INFO "Compiled for ADSP-%s Rev any, running on 0.%d\n", CPU, bfin_revid());
         else if (bfin_compiled_revid() == -1)
                 printk(KERN_INFO "Compiled for ADSP-%s Rev none\n", CPU);
         else
diff --git a/arch/blackfin/kernel/signal.c b/arch/blackfin/kernel/signal.c
index 9d90c18fab23..e0fd63e9e38a 100644
--- a/arch/blackfin/kernel/signal.c
+++ b/arch/blackfin/kernel/signal.c
@@ -12,6 +12,7 @@
 #include <linux/binfmts.h>
 #include <linux/freezer.h>
 #include <linux/uaccess.h>
+#include <linux/tracehook.h>
 
 #include <asm/cacheflush.h>
 #include <asm/ucontext.h>
@@ -332,3 +333,20 @@ asmlinkage void do_signal(struct pt_regs *regs)
                 sigprocmask(SIG_SETMASK, &current->saved_sigmask, NULL);
         }
 }
+
+/*
+ * notification of userspace execution resumption
+ */
+asmlinkage void do_notify_resume(struct pt_regs *regs)
+{
+        if (test_thread_flag(TIF_SIGPENDING) || test_thread_flag(TIF_RESTORE_SIGMASK))
+                do_signal(regs);
+
+        if (test_thread_flag(TIF_NOTIFY_RESUME)) {
+                clear_thread_flag(TIF_NOTIFY_RESUME);
+                tracehook_notify_resume(regs);
+                if (current->replacement_session_keyring)
+                        key_replace_session_keyring();
+        }
+}
+
diff --git a/arch/blackfin/kernel/sys_bfin.c b/arch/blackfin/kernel/sys_bfin.c
index afcef129d4e8..2e7f8e10bf87 100644
--- a/arch/blackfin/kernel/sys_bfin.c
+++ b/arch/blackfin/kernel/sys_bfin.c
@@ -22,39 +22,6 @@
 #include <asm/cacheflush.h>
 #include <asm/dma.h>
 
-/* common code for old and new mmaps */
-static inline long
-do_mmap2(unsigned long addr, unsigned long len,
-         unsigned long prot, unsigned long flags,
-         unsigned long fd, unsigned long pgoff)
-{
-        int error = -EBADF;
-        struct file *file = NULL;
-
-        flags &= ~(MAP_EXECUTABLE | MAP_DENYWRITE);
-        if (!(flags & MAP_ANONYMOUS)) {
-                file = fget(fd);
-                if (!file)
-                        goto out;
-        }
-
-        down_write(&current->mm->mmap_sem);
-        error = do_mmap_pgoff(file, addr, len, prot, flags, pgoff);
-        up_write(&current->mm->mmap_sem);
-
-        if (file)
-                fput(file);
- out:
-        return error;
-}
-
-asmlinkage long sys_mmap2(unsigned long addr, unsigned long len,
-                          unsigned long prot, unsigned long flags,
-                          unsigned long fd, unsigned long pgoff)
-{
-        return do_mmap2(addr, len, prot, flags, fd, pgoff);
-}
-
 asmlinkage void *sys_sram_alloc(size_t size, unsigned long flags)
 {
         return sram_alloc_with_lsl(size, flags);
diff --git a/arch/blackfin/kernel/time-ts.c b/arch/blackfin/kernel/time-ts.c
index 359cfb1815ca..17c38c5b5b22 100644
--- a/arch/blackfin/kernel/time-ts.c
+++ b/arch/blackfin/kernel/time-ts.c
@@ -22,8 +22,6 @@
 #include <asm/time.h>
 #include <asm/gptimers.h>
 
-#if defined(CONFIG_CYCLES_CLOCKSOURCE)
-
 /* Accelerators for sched_clock()
  * convert from cycles(64bits) => nanoseconds (64bits)
  *  basic equation:
@@ -46,20 +44,11 @@
  *                      -johnstul@us.ibm.com "math is hard, lets go shopping!"
  */
 
-static unsigned long cyc2ns_scale;
 #define CYC2NS_SCALE_FACTOR 10 /* 2^10, carefully chosen */
 
-static inline void set_cyc2ns_scale(unsigned long cpu_khz)
-{
-        cyc2ns_scale = (1000000 << CYC2NS_SCALE_FACTOR) / cpu_khz;
-}
-
-static inline unsigned long long cycles_2_ns(cycle_t cyc)
-{
-        return (cyc * cyc2ns_scale) >> CYC2NS_SCALE_FACTOR;
-}
+#if defined(CONFIG_CYCLES_CLOCKSOURCE)
 
-static cycle_t bfin_read_cycles(struct clocksource *cs)
+static notrace cycle_t bfin_read_cycles(struct clocksource *cs)
 {
         return __bfin_cycles_off + (get_cycles() << __bfin_cycles_mod);
 }
@@ -69,19 +58,18 @@ static struct clocksource bfin_cs_cycles = {
         .rating         = 400,
         .read           = bfin_read_cycles,
         .mask           = CLOCKSOURCE_MASK(64),
-        .shift          = 22,
+        .shift          = CYC2NS_SCALE_FACTOR,
         .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
 };
 
-unsigned long long sched_clock(void)
+static inline unsigned long long bfin_cs_cycles_sched_clock(void)
 {
-        return cycles_2_ns(bfin_read_cycles(&bfin_cs_cycles));
+        return clocksource_cyc2ns(bfin_read_cycles(&bfin_cs_cycles),
+                bfin_cs_cycles.mult, bfin_cs_cycles.shift);
 }
 
 static int __init bfin_cs_cycles_init(void)
 {
-        set_cyc2ns_scale(get_cclk() / 1000);
-
         bfin_cs_cycles.mult = \
                 clocksource_hz2mult(get_cclk(), bfin_cs_cycles.shift);
 
@@ -108,7 +96,7 @@ void __init setup_gptimer0(void)
         enable_gptimers(TIMER0bit);
 }
 
-static cycle_t bfin_read_gptimer0(void)
+static cycle_t bfin_read_gptimer0(struct clocksource *cs)
 {
         return bfin_read_TIMER0_COUNTER();
 }
@@ -118,10 +106,16 @@ static struct clocksource bfin_cs_gptimer0 = {
         .rating         = 350,
         .read           = bfin_read_gptimer0,
         .mask           = CLOCKSOURCE_MASK(32),
-        .shift          = 22,
+        .shift          = CYC2NS_SCALE_FACTOR,
         .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
 };
 
+static inline unsigned long long bfin_cs_gptimer0_sched_clock(void)
+{
+        return clocksource_cyc2ns(bfin_read_TIMER0_COUNTER(),
+                bfin_cs_gptimer0.mult, bfin_cs_gptimer0.shift);
+}
+
 static int __init bfin_cs_gptimer0_init(void)
 {
         setup_gptimer0();
@@ -138,6 +132,19 @@ static int __init bfin_cs_gptimer0_init(void)
 # define bfin_cs_gptimer0_init()
 #endif
 
+
+#if defined(CONFIG_GPTMR0_CLOCKSOURCE) || defined(CONFIG_CYCLES_CLOCKSOURCE)
+/* prefer to use cycles since it has higher rating */
+notrace unsigned long long sched_clock(void)
+{
+#if defined(CONFIG_CYCLES_CLOCKSOURCE)
+        return bfin_cs_cycles_sched_clock();
+#else
+        return bfin_cs_gptimer0_sched_clock();
+#endif
+}
+#endif
+
 #ifdef CONFIG_CORE_TIMER_IRQ_L1
 __attribute__((l1_text))
 #endif
diff --git a/arch/blackfin/kernel/time.c b/arch/blackfin/kernel/time.c
index bd3b53da295e..13c1ee3e6408 100644
--- a/arch/blackfin/kernel/time.c
+++ b/arch/blackfin/kernel/time.c
@@ -184,11 +184,3 @@ void __init time_init(void)
 
         time_sched_init(timer_interrupt);
 }
-
-/*
- * Scheduler clock - returns current time in nanosec units.
- */
-unsigned long long sched_clock(void)
-{
-        return (unsigned long long)jiffies *(NSEC_PER_SEC / HZ);
-}
diff --git a/arch/blackfin/kernel/traps.c b/arch/blackfin/kernel/traps.c
index 78cb3d38f899..d3cbcd6bd985 100644
--- a/arch/blackfin/kernel/traps.c
+++ b/arch/blackfin/kernel/traps.c
@@ -119,6 +119,15 @@ static void decode_address(char *buf, unsigned long address)
                 return;
         }
 
+        /*
+         * Don't walk any of the vmas if we are oopsing, it has been known
+         * to cause problems - corrupt vmas (kernel crashes) cause double faults
+         */
+        if (oops_in_progress) {
+                strcat(buf, "/* kernel dynamic memory (maybe user-space) */");
+                return;
+        }
+
         /* looks like we're off in user-land, so let's walk all the
          * mappings of all our processes and see if we can't be a whee
          * bit more specific
@@ -515,6 +524,36 @@ asmlinkage notrace void trap_c(struct pt_regs *fp)
                         break;
                 /* External Memory Addressing Error */
                 case (SEQSTAT_HWERRCAUSE_EXTERN_ADDR):
+                        if (ANOMALY_05000310) {
+                                static unsigned long anomaly_rets;
+
+                                if ((fp->pc >= (L1_CODE_START + L1_CODE_LENGTH - 512)) &&
+                                    (fp->pc < (L1_CODE_START + L1_CODE_LENGTH))) {
+                                        /*
+                                         * A false hardware error will happen while fetching at
+                                         * the L1 instruction SRAM boundary.  Ignore it.
+                                         */
+                                        anomaly_rets = fp->rets;
+                                        goto traps_done;
+                                } else if (fp->rets == anomaly_rets) {
+                                        /*
+                                         * While boundary code returns to a function, at the ret
+                                         * point, a new false hardware error might occur too based
+                                         * on tests.  Ignore it too.
+                                         */
+                                        goto traps_done;
+                                } else if ((fp->rets >= (L1_CODE_START + L1_CODE_LENGTH - 512)) &&
+                                           (fp->rets < (L1_CODE_START + L1_CODE_LENGTH))) {
+                                        /*
+                                         * If boundary code calls a function, at the entry point,
+                                         * a new false hardware error maybe happen based on tests.
+                                         * Ignore it too.
+                                         */
+                                        goto traps_done;
+                                } else
+                                        anomaly_rets = 0;
+                        }
+
                         info.si_code = BUS_ADRERR;
                         sig = SIGBUS;
                         strerror = KERN_NOTICE HWC_x3(KERN_NOTICE);
@@ -976,12 +1015,12 @@ void dump_bfin_process(struct pt_regs *fp)
             !((unsigned long)current & 0x3) && current->pid) {
                 verbose_printk(KERN_NOTICE "CURRENT PROCESS:\n");
                 if (current->comm >= (char *)FIXED_CODE_START)
-                        verbose_printk(KERN_NOTICE "COMM=%s PID=%d\n",
+                        verbose_printk(KERN_NOTICE "COMM=%s PID=%d",
                                 current->comm, current->pid);
                 else
-                        verbose_printk(KERN_NOTICE "COMM= invalid\n");
+                        verbose_printk(KERN_NOTICE "COMM= invalid");
 
-                printk(KERN_NOTICE "CPU = %d\n", current_thread_info()->cpu);
+                printk(KERN_CONT " CPU=%d\n", current_thread_info()->cpu);
                 if (!((unsigned long)current->mm & 0x3) && (unsigned long)current->mm >= FIXED_CODE_START)
                         verbose_printk(KERN_NOTICE
                                 "TEXT = 0x%p-0x%p        DATA = 0x%p-0x%p\n"
@@ -1140,7 +1179,7 @@ void show_regs(struct pt_regs *fp)
         if (fp->ipend & ~0x3F) {
                 for (i = 0; i < (NR_IRQS - 1); i++) {
                         if (!in_atomic)
-                                spin_lock_irqsave(&irq_desc[i].lock, flags);
+                                raw_spin_lock_irqsave(&irq_desc[i].lock, flags);
 
                         action = irq_desc[i].action;
                         if (!action)
@@ -1155,7 +1194,7 @@ void show_regs(struct pt_regs *fp)
                         verbose_printk("\n");
 unlock:
                         if (!in_atomic)
-                                spin_unlock_irqrestore(&irq_desc[i].lock, flags);
+                                raw_spin_unlock_irqrestore(&irq_desc[i].lock, flags);
                 }
         }
 
diff --git a/arch/blackfin/kernel/vmlinux.lds.S b/arch/blackfin/kernel/vmlinux.lds.S
index 10e12539000e..66799e763dc9 100644
--- a/arch/blackfin/kernel/vmlinux.lds.S
+++ b/arch/blackfin/kernel/vmlinux.lds.S
@@ -4,8 +4,6 @@
  * Licensed under the GPL-2 or later
  */
 
-#define VMLINUX_SYMBOL(_sym_) _##_sym_
-
 #include <asm-generic/vmlinux.lds.h>
 #include <asm/mem_map.h>
 #include <asm/page.h>
@@ -123,8 +121,6 @@ SECTIONS
                 EXIT_DATA
         }
 
-        __l1_lma_start = .;
-
         .text_l1 L1_CODE_START : AT(LOADADDR(.exit.data) + SIZEOF(.exit.data))
         {
                 . = ALIGN(4);
@@ -136,9 +132,11 @@ SECTIONS
                 . = ALIGN(4);
                 __etext_l1 = .;
         }
-        ASSERT (SIZEOF(.text_l1) <= L1_CODE_LENGTH, "L1 text overflow!")
+        __text_l1_lma = LOADADDR(.text_l1);
+        __text_l1_len = SIZEOF(.text_l1);
+        ASSERT (__text_l1_len <= L1_CODE_LENGTH, "L1 text overflow!")
 
-        .data_l1 L1_DATA_A_START : AT(LOADADDR(.text_l1) + SIZEOF(.text_l1))
+        .data_l1 L1_DATA_A_START : AT(__text_l1_lma + __text_l1_len)
         {
                 . = ALIGN(4);
                 __sdata_l1 = .;
@@ -154,9 +152,11 @@ SECTIONS
                 . = ALIGN(4);
                 __ebss_l1 = .;
         }
-        ASSERT (SIZEOF(.data_l1) <= L1_DATA_A_LENGTH, "L1 data A overflow!")
+        __data_l1_lma = LOADADDR(.data_l1);
+        __data_l1_len = SIZEOF(.data_l1);
+        ASSERT (__data_l1_len <= L1_DATA_A_LENGTH, "L1 data A overflow!")
 
-        .data_b_l1 L1_DATA_B_START : AT(LOADADDR(.data_l1) + SIZEOF(.data_l1))
+        .data_b_l1 L1_DATA_B_START : AT(__data_l1_lma + __data_l1_len)
         {
                 . = ALIGN(4);
                 __sdata_b_l1 = .;
@@ -169,11 +169,11 @@ SECTIONS
                 . = ALIGN(4);
                 __ebss_b_l1 = .;
         }
-        ASSERT (SIZEOF(.data_b_l1) <= L1_DATA_B_LENGTH, "L1 data B overflow!")
-
-        __l2_lma_start = LOADADDR(.data_b_l1) + SIZEOF(.data_b_l1);
+        __data_b_l1_lma = LOADADDR(.data_b_l1);
+        __data_b_l1_len = SIZEOF(.data_b_l1);
+        ASSERT (__data_b_l1_len <= L1_DATA_B_LENGTH, "L1 data B overflow!")
 
-        .text_data_l2 L2_START : AT(LOADADDR(.data_b_l1) + SIZEOF(.data_b_l1))
+        .text_data_l2 L2_START : AT(__data_b_l1_lma + __data_b_l1_len)
         {
                 . = ALIGN(4);
                 __stext_l2 = .;
@@ -195,12 +195,14 @@ SECTIONS
                 . = ALIGN(4);
                 __ebss_l2 = .;
         }
-        ASSERT (SIZEOF(.text_data_l2) <= L2_LENGTH, "L2 overflow!")
+        __l2_lma = LOADADDR(.text_data_l2);
+        __l2_len = SIZEOF(.text_data_l2);
+        ASSERT (__l2_len <= L2_LENGTH, "L2 overflow!")
 
         /* Force trailing alignment of our init section so that when we
          * free our init memory, we don't leave behind a partial page.
          */
-        . = LOADADDR(.text_data_l2) + SIZEOF(.text_data_l2);
+        . = __l2_lma + __l2_len;
         . = ALIGN(PAGE_SIZE);
         ___init_end = .;
 
diff --git a/arch/blackfin/lib/Makefile b/arch/blackfin/lib/Makefile
index 635288fc5f54..42c47dc9e12f 100644
--- a/arch/blackfin/lib/Makefile
+++ b/arch/blackfin/lib/Makefile
@@ -5,7 +5,7 @@
 lib-y := \
         ashldi3.o ashrdi3.o lshrdi3.o \
         muldi3.o divsi3.o udivsi3.o modsi3.o umodsi3.o \
-        checksum.o memcpy.o memset.o memcmp.o memchr.o memmove.o \
+        memcpy.o memset.o memcmp.o memchr.o memmove.o \
         strcmp.o strcpy.o strncmp.o strncpy.o \
         umulsi3_highpart.o smulsi3_highpart.o \
         ins.o outs.o
diff --git a/arch/blackfin/lib/checksum.c b/arch/blackfin/lib/checksum.c
deleted file mode 100644
index c62969dc1bbb..000000000000
--- a/arch/blackfin/lib/checksum.c
+++ /dev/null
@@ -1,125 +0,0 @@
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- *
- * An implementation of the TCP/IP protocol suite for the LINUX operating
- * system. INET is implemented using the BSD Socket interface as the
- * means of communication with the user level.
- *
- */
-
-#include <linux/module.h>
-#include <net/checksum.h>
-#include <asm/checksum.h>
-
-#ifdef CONFIG_IP_CHECKSUM_L1
-static unsigned short do_csum(const unsigned char *buff, int len)__attribute__((l1_text));
-#endif
-
-static unsigned short do_csum(const unsigned char *buff, int len)
-{
-        register unsigned long sum = 0;
-        int swappem = 0;
-
-        if (1 & (unsigned long)buff) {
-                sum = *buff << 8;
-                buff++;
-                len--;
-                ++swappem;
-        }
-
-        while (len > 1) {
-                sum += *(unsigned short *)buff;
-                buff += 2;
-                len -= 2;
-        }
-
-        if (len > 0)
-                sum += *buff;
-
-        /*  Fold 32-bit sum to 16 bits */
-        while (sum >> 16)
-                sum = (sum & 0xffff) + (sum >> 16);
-
-        if (swappem)
-                sum = ((sum & 0xff00) >> 8) + ((sum & 0x00ff) << 8);
-
-        return sum;
-
-}
-
-/*
- *      This is a version of ip_compute_csum() optimized for IP headers,
- *      which always checksum on 4 octet boundaries.
- */
-__sum16 ip_fast_csum(unsigned char *iph, unsigned int ihl)
-{
-        return (__force __sum16)~do_csum(iph, ihl * 4);
-}
-EXPORT_SYMBOL(ip_fast_csum);
-
-/*
- * computes the checksum of a memory block at buff, length len,
- * and adds in "sum" (32-bit)
- *
- * returns a 32-bit number suitable for feeding into itself
- * or csum_tcpudp_magic
- *
- * this function must be called with even lengths, except
- * for the last fragment, which may be odd
- *
- * it's best to have buff aligned on a 32-bit boundary
- */
-__wsum csum_partial(const void *buff, int len, __wsum sum)
-{
-        /*
-         * Just in case we get nasty checksum data...
-         * Like 0xffff6ec3 in the case of our IPv6 multicast header.
-         * We fold to begin with, as well as at the end.
-         */
-        sum = (sum & 0xffff) + (sum >> 16);
-
-        sum += do_csum(buff, len);
-
-        sum = (sum & 0xffff) + (sum >> 16);
-
-        return sum;
-}
-EXPORT_SYMBOL(csum_partial);
-
-/*
- * this routine is used for miscellaneous IP-like checksums, mainly
- * in icmp.c
- */
-__sum16 ip_compute_csum(const void *buff, int len)
-{
-        return (__force __sum16)~do_csum(buff, len);
-}
-EXPORT_SYMBOL(ip_compute_csum);
-
-/*
- * copy from fs while checksumming, otherwise like csum_partial
- */
-
-__wsum
-csum_partial_copy_from_user(const void __user *src, void *dst,
-                            int len, __wsum sum, int *csum_err)
-{
-        if (csum_err)
-                *csum_err = 0;
-        memcpy(dst, (__force void *)src, len);
-        return csum_partial(dst, len, sum);
-}
-EXPORT_SYMBOL(csum_partial_copy_from_user);
-
-/*
- * copy from ds while checksumming, otherwise like csum_partial
- */
-
-__wsum csum_partial_copy(const void *src, void *dst, int len, __wsum sum)
-{
-        memcpy(dst, src, len);
-        return csum_partial(dst, len, sum);
-}
-EXPORT_SYMBOL(csum_partial_copy);
diff --git a/arch/blackfin/mach-bf518/Kconfig b/arch/blackfin/mach-bf518/Kconfig
index 4c76fefb7a3b..4ab2d166c832 100644
--- a/arch/blackfin/mach-bf518/Kconfig
+++ b/arch/blackfin/mach-bf518/Kconfig
@@ -1,3 +1,7 @@
+config BF51x
+        def_bool y
+        depends on (BF512 || BF514 || BF516 || BF518)
+
 if (BF51x)
 
 source "arch/blackfin/mach-bf518/boards/Kconfig"
diff --git a/arch/blackfin/mach-bf518/include/mach/blackfin.h b/arch/blackfin/mach-bf518/include/mach/blackfin.h
index 6cfb246aebec..9053462be4b1 100644
--- a/arch/blackfin/mach-bf518/include/mach/blackfin.h
+++ b/arch/blackfin/mach-bf518/include/mach/blackfin.h
@@ -58,10 +58,4 @@
 #define OFFSET_SCR              0x1C    /* SCR Scratch Register                 */
 #define OFFSET_GCTL             0x24    /* Global Control Register              */
 
-/* PLL_DIV Masks                                                                                                        */
-#define CCLK_DIV1 CSEL_DIV1     /*          CCLK = VCO / 1                                  */
-#define CCLK_DIV2 CSEL_DIV2     /*          CCLK = VCO / 2                                  */
-#define CCLK_DIV4 CSEL_DIV4     /*          CCLK = VCO / 4                                  */
-#define CCLK_DIV8 CSEL_DIV8     /*          CCLK = VCO / 8                                  */
-
 #endif
diff --git a/arch/blackfin/mach-bf518/include/mach/cdefBF514.h b/arch/blackfin/mach-bf518/include/mach/cdefBF514.h
index e1d99911025d..108fa4bde277 100644
--- a/arch/blackfin/mach-bf518/include/mach/cdefBF514.h
+++ b/arch/blackfin/mach-bf518/include/mach/cdefBF514.h
@@ -1,7 +1,7 @@
 /*
  * Copyright 2008-2009 Analog Devices Inc.
  *
- * Licensed under the GPL-2 or later
+ * Licensed under the ADI BSD license or the GPL-2 (or later)
  */
 
 #ifndef _CDEF_BF514_H
@@ -10,15 +10,8 @@
 /* include all Core registers and bit definitions */
 #include "defBF514.h"
 
-/* include core specific register pointer definitions */
-#include <asm/cdef_LPBlackfin.h>
-
-/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF514 */
-
-/* include cdefBF51x_base.h for the set of #defines that are common to all ADSP-BF51x processors */
-#include "cdefBF51x_base.h"
-
-/* The following are the #defines needed by ADSP-BF514 that are not in the common header */
+/* BF514 is BF512 + RSI */
+#include "cdefBF512.h"
 
 /* Removable Storage Interface Registers */
 
diff --git a/arch/blackfin/mach-bf518/include/mach/cdefBF516.h b/arch/blackfin/mach-bf518/include/mach/cdefBF516.h
index 6b364eda4947..2751592ef1c1 100644
--- a/arch/blackfin/mach-bf518/include/mach/cdefBF516.h
+++ b/arch/blackfin/mach-bf518/include/mach/cdefBF516.h
@@ -1,7 +1,7 @@
 /*
  * Copyright 2008-2009 Analog Devices Inc.
  *
- * Licensed under the GPL-2 or later
+ * Licensed under the ADI BSD license or the GPL-2 (or later)
  */
 
 #ifndef _CDEF_BF516_H
@@ -10,15 +10,8 @@
 /* include all Core registers and bit definitions */
 #include "defBF516.h"
 
-/* include core specific register pointer definitions */
-#include <asm/cdef_LPBlackfin.h>
-
-/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF516 */
-
-/* include cdefBF51x_base.h for the set of #defines that are common to all ADSP-BF51x processors */
-#include "cdefBF51x_base.h"
-
-/* The following are the #defines needed by ADSP-BF516 that are not in the common header */
+/* BF516 is BF514 + EMAC */
+#include "cdefBF514.h"
 
 /* 10/100 Ethernet Controller   (0xFFC03000 - 0xFFC031FF) */
 
@@ -185,71 +178,4 @@
 #define bfin_read_EMAC_TXC_ABORT()              bfin_read32(EMAC_TXC_ABORT)
 #define bfin_write_EMAC_TXC_ABORT(val)          bfin_write32(EMAC_TXC_ABORT, val)
 
-/* Removable Storage Interface Registers */
-
-#define bfin_read_RSI_PWR_CTL()        bfin_read16(RSI_PWR_CONTROL)
-#define bfin_write_RSI_PWR_CTL(val)    bfin_write16(RSI_PWR_CONTROL, val)
-#define bfin_read_RSI_CLK_CTL()        bfin_read16(RSI_CLK_CONTROL)
-#define bfin_write_RSI_CLK_CTL(val)    bfin_write16(RSI_CLK_CONTROL, val)
-#define bfin_read_RSI_ARGUMENT()       bfin_read32(RSI_ARGUMENT)
-#define bfin_write_RSI_ARGUMENT(val)   bfin_write32(RSI_ARGUMENT, val)
-#define bfin_read_RSI_COMMAND()        bfin_read16(RSI_COMMAND)
-#define bfin_write_RSI_COMMAND(val)    bfin_write16(RSI_COMMAND, val)
-#define bfin_read_RSI_RESP_CMD()       bfin_read16(RSI_RESP_CMD)
-#define bfin_write_RSI_RESP_CMD(val)   bfin_write16(RSI_RESP_CMD, val)
-#define bfin_read_RSI_RESPONSE0()      bfin_read32(RSI_RESPONSE0)
-#define bfin_write_RSI_RESPONSE0(val)  bfin_write32(RSI_RESPONSE0, val)
-#define bfin_read_RSI_RESPONSE1()      bfin_read32(RSI_RESPONSE1)
-#define bfin_write_RSI_RESPONSE1(val)  bfin_write32(RSI_RESPONSE1, val)
-#define bfin_read_RSI_RESPONSE2()      bfin_read32(RSI_RESPONSE2)
-#define bfin_write_RSI_RESPONSE2(val)  bfin_write32(RSI_RESPONSE2, val)
-#define bfin_read_RSI_RESPONSE3()      bfin_read32(RSI_RESPONSE3)
-#define bfin_write_RSI_RESPONSE3(val)  bfin_write32(RSI_RESPONSE3, val)
-#define bfin_read_RSI_DATA_TIMER()     bfin_read32(RSI_DATA_TIMER)
-#define bfin_write_RSI_DATA_TIMER(val) bfin_write32(RSI_DATA_TIMER, val)
-#define bfin_read_RSI_DATA_LGTH()      bfin_read16(RSI_DATA_LGTH)
-#define bfin_write_RSI_DATA_LGTH(val)  bfin_write16(RSI_DATA_LGTH, val)
-#define bfin_read_RSI_DATA_CTL()       bfin_read16(RSI_DATA_CONTROL)
-#define bfin_write_RSI_DATA_CTL(val)   bfin_write16(RSI_DATA_CONTROL, val)
-#define bfin_read_RSI_DATA_CNT()       bfin_read16(RSI_DATA_CNT)
-#define bfin_write_RSI_DATA_CNT(val)   bfin_write16(RSI_DATA_CNT, val)
-#define bfin_read_RSI_STATUS()         bfin_read32(RSI_STATUS)
-#define bfin_write_RSI_STATUS(val)     bfin_write32(RSI_STATUS, val)
-#define bfin_read_RSI_STATUS_CLR()     bfin_read16(RSI_STATUSCL)
-#define bfin_write_RSI_STATUS_CLR(val) bfin_write16(RSI_STATUSCL, val)
-#define bfin_read_RSI_MASK0()          bfin_read32(RSI_MASK0)
-#define bfin_write_RSI_MASK0(val)      bfin_write32(RSI_MASK0, val)
-#define bfin_read_RSI_MASK1()          bfin_read32(RSI_MASK1)
-#define bfin_write_RSI_MASK1(val)      bfin_write32(RSI_MASK1, val)
-#define bfin_read_RSI_FIFO_CNT()       bfin_read16(RSI_FIFO_CNT)
-#define bfin_write_RSI_FIFO_CNT(val)   bfin_write16(RSI_FIFO_CNT, val)
-#define bfin_read_RSI_CEATA_CTL()      bfin_read16(RSI_CEATA_CONTROL)
-#define bfin_write_RSI_CEATA_CTL(val)  bfin_write16(RSI_CEATA_CONTROL, val)
-#define bfin_read_RSI_FIFO()           bfin_read32(RSI_FIFO)
-#define bfin_write_RSI_FIFO(val)       bfin_write32(RSI_FIFO, val)
-#define bfin_read_RSI_E_STATUS()       bfin_read16(RSI_ESTAT)
-#define bfin_write_RSI_E_STATUS(val)   bfin_write16(RSI_ESTAT, val)
-#define bfin_read_RSI_E_MASK()         bfin_read16(RSI_EMASK)
-#define bfin_write_RSI_E_MASK(val)     bfin_write16(RSI_EMASK, val)
-#define bfin_read_RSI_CFG()            bfin_read16(RSI_CONFIG)
-#define bfin_write_RSI_CFG(val)        bfin_write16(RSI_CONFIG, val)
-#define bfin_read_RSI_RD_WAIT_EN()     bfin_read16(RSI_RD_WAIT_EN)
-#define bfin_write_RSI_RD_WAIT_EN(val) bfin_write16(RSI_RD_WAIT_EN, val)
-#define bfin_read_RSI_PID0()           bfin_read16(RSI_PID0)
-#define bfin_write_RSI_PID0(val)       bfin_write16(RSI_PID0, val)
-#define bfin_read_RSI_PID1()           bfin_read16(RSI_PID1)
-#define bfin_write_RSI_PID1(val)       bfin_write16(RSI_PID1, val)
-#define bfin_read_RSI_PID2()           bfin_read16(RSI_PID2)
-#define bfin_write_RSI_PID2(val)       bfin_write16(RSI_PID2, val)
-#define bfin_read_RSI_PID3()           bfin_read16(RSI_PID3)
-#define bfin_write_RSI_PID3(val)       bfin_write16(RSI_PID3, val)
-#define bfin_read_RSI_PID4()           bfin_read16(RSI_PID4)
-#define bfin_write_RSI_PID4(val)       bfin_write16(RSI_PID4, val)
-#define bfin_read_RSI_PID5()           bfin_read16(RSI_PID5)
-#define bfin_write_RSI_PID5(val)       bfin_write16(RSI_PID5, val)
-#define bfin_read_RSI_PID6()           bfin_read16(RSI_PID6)
-#define bfin_write_RSI_PID6(val)       bfin_write16(RSI_PID6, val)
-#define bfin_read_RSI_PID7()           bfin_read16(RSI_PID7)
-#define bfin_write_RSI_PID7(val)       bfin_write16(RSI_PID7, val)
-
 #endif /* _CDEF_BF516_H */
diff --git a/arch/blackfin/mach-bf518/include/mach/cdefBF518.h b/arch/blackfin/mach-bf518/include/mach/cdefBF518.h
index 929b90650bd4..7fb7f0eab990 100644
--- a/arch/blackfin/mach-bf518/include/mach/cdefBF518.h
+++ b/arch/blackfin/mach-bf518/include/mach/cdefBF518.h
@@ -1,7 +1,7 @@
 /*
  * Copyright 2008-2009 Analog Devices Inc.
  *
- * Licensed under the GPL-2 or later
+ * Licensed under the ADI BSD license or the GPL-2 (or later)
  */
 
 #ifndef _CDEF_BF518_H
@@ -10,181 +10,10 @@
 /* include all Core registers and bit definitions */
 #include "defBF518.h"
 
-/* include core specific register pointer definitions */
-#include <asm/cdef_LPBlackfin.h>
+/* BF518 is BF516 + IEEE-1588 */
+#include "cdefBF516.h"
 
-/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF518 */
-
-/* include cdefBF51x_base.h for the set of #defines that are common to all ADSP-BF51x processors */
-#include "cdefBF51x_base.h"
-
-/* The following are the #defines needed by ADSP-BF518 that are not in the common header */
-
-
-/* 10/100 Ethernet Controller   (0xFFC03000 - 0xFFC031FF) */
-
-#define bfin_read_EMAC_OPMODE()                 bfin_read32(EMAC_OPMODE)
-#define bfin_write_EMAC_OPMODE(val)             bfin_write32(EMAC_OPMODE, val)
-#define bfin_read_EMAC_ADDRLO()                 bfin_read32(EMAC_ADDRLO)
-#define bfin_write_EMAC_ADDRLO(val)             bfin_write32(EMAC_ADDRLO, val)
-#define bfin_read_EMAC_ADDRHI()                 bfin_read32(EMAC_ADDRHI)
-#define bfin_write_EMAC_ADDRHI(val)             bfin_write32(EMAC_ADDRHI, val)
-#define bfin_read_EMAC_HASHLO()                 bfin_read32(EMAC_HASHLO)
-#define bfin_write_EMAC_HASHLO(val)             bfin_write32(EMAC_HASHLO, val)
-#define bfin_read_EMAC_HASHHI()                 bfin_read32(EMAC_HASHHI)
-#define bfin_write_EMAC_HASHHI(val)             bfin_write32(EMAC_HASHHI, val)
-#define bfin_read_EMAC_STAADD()                 bfin_read32(EMAC_STAADD)
-#define bfin_write_EMAC_STAADD(val)             bfin_write32(EMAC_STAADD, val)
-#define bfin_read_EMAC_STADAT()                 bfin_read32(EMAC_STADAT)
-#define bfin_write_EMAC_STADAT(val)             bfin_write32(EMAC_STADAT, val)
-#define bfin_read_EMAC_FLC()                    bfin_read32(EMAC_FLC)
-#define bfin_write_EMAC_FLC(val)                bfin_write32(EMAC_FLC, val)
-#define bfin_read_EMAC_VLAN1()                  bfin_read32(EMAC_VLAN1)
-#define bfin_write_EMAC_VLAN1(val)              bfin_write32(EMAC_VLAN1, val)
-#define bfin_read_EMAC_VLAN2()                  bfin_read32(EMAC_VLAN2)
-#define bfin_write_EMAC_VLAN2(val)              bfin_write32(EMAC_VLAN2, val)
-#define bfin_read_EMAC_WKUP_CTL()               bfin_read32(EMAC_WKUP_CTL)
-#define bfin_write_EMAC_WKUP_CTL(val)           bfin_write32(EMAC_WKUP_CTL, val)
-#define bfin_read_EMAC_WKUP_FFMSK0()            bfin_read32(EMAC_WKUP_FFMSK0)
-#define bfin_write_EMAC_WKUP_FFMSK0(val)        bfin_write32(EMAC_WKUP_FFMSK0, val)
-#define bfin_read_EMAC_WKUP_FFMSK1()            bfin_read32(EMAC_WKUP_FFMSK1)
-#define bfin_write_EMAC_WKUP_FFMSK1(val)        bfin_write32(EMAC_WKUP_FFMSK1, val)
-#define bfin_read_EMAC_WKUP_FFMSK2()            bfin_read32(EMAC_WKUP_FFMSK2)
-#define bfin_write_EMAC_WKUP_FFMSK2(val)        bfin_write32(EMAC_WKUP_FFMSK2, val)
-#define bfin_read_EMAC_WKUP_FFMSK3()            bfin_read32(EMAC_WKUP_FFMSK3)
-#define bfin_write_EMAC_WKUP_FFMSK3(val)        bfin_write32(EMAC_WKUP_FFMSK3, val)
-#define bfin_read_EMAC_WKUP_FFCMD()             bfin_read32(EMAC_WKUP_FFCMD)
-#define bfin_write_EMAC_WKUP_FFCMD(val)         bfin_write32(EMAC_WKUP_FFCMD, val)
-#define bfin_read_EMAC_WKUP_FFOFF()             bfin_read32(EMAC_WKUP_FFOFF)
-#define bfin_write_EMAC_WKUP_FFOFF(val)         bfin_write32(EMAC_WKUP_FFOFF, val)
-#define bfin_read_EMAC_WKUP_FFCRC0()            bfin_read32(EMAC_WKUP_FFCRC0)
-#define bfin_write_EMAC_WKUP_FFCRC0(val)        bfin_write32(EMAC_WKUP_FFCRC0, val)
-#define bfin_read_EMAC_WKUP_FFCRC1()            bfin_read32(EMAC_WKUP_FFCRC1)
-#define bfin_write_EMAC_WKUP_FFCRC1(val)        bfin_write32(EMAC_WKUP_FFCRC1, val)
-
-#define bfin_read_EMAC_SYSCTL()                 bfin_read32(EMAC_SYSCTL)
-#define bfin_write_EMAC_SYSCTL(val)             bfin_write32(EMAC_SYSCTL, val)
-#define bfin_read_EMAC_SYSTAT()                 bfin_read32(EMAC_SYSTAT)
-#define bfin_write_EMAC_SYSTAT(val)             bfin_write32(EMAC_SYSTAT, val)
-#define bfin_read_EMAC_RX_STAT()                bfin_read32(EMAC_RX_STAT)
-#define bfin_write_EMAC_RX_STAT(val)            bfin_write32(EMAC_RX_STAT, val)
-#define bfin_read_EMAC_RX_STKY()                bfin_read32(EMAC_RX_STKY)
-#define bfin_write_EMAC_RX_STKY(val)            bfin_write32(EMAC_RX_STKY, val)
-#define bfin_read_EMAC_RX_IRQE()                bfin_read32(EMAC_RX_IRQE)
-#define bfin_write_EMAC_RX_IRQE(val)            bfin_write32(EMAC_RX_IRQE, val)
-#define bfin_read_EMAC_TX_STAT()                bfin_read32(EMAC_TX_STAT)
-#define bfin_write_EMAC_TX_STAT(val)            bfin_write32(EMAC_TX_STAT, val)
-#define bfin_read_EMAC_TX_STKY()                bfin_read32(EMAC_TX_STKY)
-#define bfin_write_EMAC_TX_STKY(val)            bfin_write32(EMAC_TX_STKY, val)
-#define bfin_read_EMAC_TX_IRQE()                bfin_read32(EMAC_TX_IRQE)
-#define bfin_write_EMAC_TX_IRQE(val)            bfin_write32(EMAC_TX_IRQE, val)
-
-#define bfin_read_EMAC_MMC_CTL()                bfin_read32(EMAC_MMC_CTL)
-#define bfin_write_EMAC_MMC_CTL(val)            bfin_write32(EMAC_MMC_CTL, val)
-#define bfin_read_EMAC_MMC_RIRQS()              bfin_read32(EMAC_MMC_RIRQS)
-#define bfin_write_EMAC_MMC_RIRQS(val)          bfin_write32(EMAC_MMC_RIRQS, val)
-#define bfin_read_EMAC_MMC_RIRQE()              bfin_read32(EMAC_MMC_RIRQE)
-#define bfin_write_EMAC_MMC_RIRQE(val)          bfin_write32(EMAC_MMC_RIRQE, val)
-#define bfin_read_EMAC_MMC_TIRQS()              bfin_read32(EMAC_MMC_TIRQS)
-#define bfin_write_EMAC_MMC_TIRQS(val)          bfin_write32(EMAC_MMC_TIRQS, val)
-#define bfin_read_EMAC_MMC_TIRQE()              bfin_read32(EMAC_MMC_TIRQE)
-#define bfin_write_EMAC_MMC_TIRQE(val)          bfin_write32(EMAC_MMC_TIRQE, val)
-
-#define bfin_read_EMAC_RXC_OK()                 bfin_read32(EMAC_RXC_OK)
-#define bfin_write_EMAC_RXC_OK(val)             bfin_write32(EMAC_RXC_OK, val)
-#define bfin_read_EMAC_RXC_FCS()                bfin_read32(EMAC_RXC_FCS)
-#define bfin_write_EMAC_RXC_FCS(val)            bfin_write32(EMAC_RXC_FCS, val)
-#define bfin_read_EMAC_RXC_ALIGN()              bfin_read32(EMAC_RXC_ALIGN)
-#define bfin_write_EMAC_RXC_ALIGN(val)          bfin_write32(EMAC_RXC_ALIGN, val)
-#define bfin_read_EMAC_RXC_OCTET()              bfin_read32(EMAC_RXC_OCTET)
-#define bfin_write_EMAC_RXC_OCTET(val)          bfin_write32(EMAC_RXC_OCTET, val)
-#define bfin_read_EMAC_RXC_DMAOVF()             bfin_read32(EMAC_RXC_DMAOVF)
-#define bfin_write_EMAC_RXC_DMAOVF(val)         bfin_write32(EMAC_RXC_DMAOVF, val)
-#define bfin_read_EMAC_RXC_UNICST()             bfin_read32(EMAC_RXC_UNICST)
-#define bfin_write_EMAC_RXC_UNICST(val)         bfin_write32(EMAC_RXC_UNICST, val)
-#define bfin_read_EMAC_RXC_MULTI()              bfin_read32(EMAC_RXC_MULTI)
-#define bfin_write_EMAC_RXC_MULTI(val)          bfin_write32(EMAC_RXC_MULTI, val)
-#define bfin_read_EMAC_RXC_BROAD()              bfin_read32(EMAC_RXC_BROAD)
-#define bfin_write_EMAC_RXC_BROAD(val)          bfin_write32(EMAC_RXC_BROAD, val)
-#define bfin_read_EMAC_RXC_LNERRI()             bfin_read32(EMAC_RXC_LNERRI)
-#define bfin_write_EMAC_RXC_LNERRI(val)         bfin_write32(EMAC_RXC_LNERRI, val)
-#define bfin_read_EMAC_RXC_LNERRO()             bfin_read32(EMAC_RXC_LNERRO)
-#define bfin_write_EMAC_RXC_LNERRO(val)         bfin_write32(EMAC_RXC_LNERRO, val)
-#define bfin_read_EMAC_RXC_LONG()               bfin_read32(EMAC_RXC_LONG)
-#define bfin_write_EMAC_RXC_LONG(val)           bfin_write32(EMAC_RXC_LONG, val)
-#define bfin_read_EMAC_RXC_MACCTL()             bfin_read32(EMAC_RXC_MACCTL)
-#define bfin_write_EMAC_RXC_MACCTL(val)         bfin_write32(EMAC_RXC_MACCTL, val)
-#define bfin_read_EMAC_RXC_OPCODE()             bfin_read32(EMAC_RXC_OPCODE)
-#define bfin_write_EMAC_RXC_OPCODE(val)         bfin_write32(EMAC_RXC_OPCODE, val)
-#define bfin_read_EMAC_RXC_PAUSE()              bfin_read32(EMAC_RXC_PAUSE)
-#define bfin_write_EMAC_RXC_PAUSE(val)          bfin_write32(EMAC_RXC_PAUSE, val)
-#define bfin_read_EMAC_RXC_ALLFRM()             bfin_read32(EMAC_RXC_ALLFRM)
-#define bfin_write_EMAC_RXC_ALLFRM(val)         bfin_write32(EMAC_RXC_ALLFRM, val)
-#define bfin_read_EMAC_RXC_ALLOCT()             bfin_read32(EMAC_RXC_ALLOCT)
-#define bfin_write_EMAC_RXC_ALLOCT(val)         bfin_write32(EMAC_RXC_ALLOCT, val)
-#define bfin_read_EMAC_RXC_TYPED()              bfin_read32(EMAC_RXC_TYPED)
-#define bfin_write_EMAC_RXC_TYPED(val)          bfin_write32(EMAC_RXC_TYPED, val)
-#define bfin_read_EMAC_RXC_SHORT()              bfin_read32(EMAC_RXC_SHORT)
-#define bfin_write_EMAC_RXC_SHORT(val)          bfin_write32(EMAC_RXC_SHORT, val)
-#define bfin_read_EMAC_RXC_EQ64()               bfin_read32(EMAC_RXC_EQ64)
-#define bfin_write_EMAC_RXC_EQ64(val)           bfin_write32(EMAC_RXC_EQ64, val)
-#define bfin_read_EMAC_RXC_LT128()              bfin_read32(EMAC_RXC_LT128)
-#define bfin_write_EMAC_RXC_LT128(val)          bfin_write32(EMAC_RXC_LT128, val)
-#define bfin_read_EMAC_RXC_LT256()              bfin_read32(EMAC_RXC_LT256)
-#define bfin_write_EMAC_RXC_LT256(val)          bfin_write32(EMAC_RXC_LT256, val)
-#define bfin_read_EMAC_RXC_LT512()              bfin_read32(EMAC_RXC_LT512)
-#define bfin_write_EMAC_RXC_LT512(val)          bfin_write32(EMAC_RXC_LT512, val)
-#define bfin_read_EMAC_RXC_LT1024()             bfin_read32(EMAC_RXC_LT1024)
-#define bfin_write_EMAC_RXC_LT1024(val)         bfin_write32(EMAC_RXC_LT1024, val)
-#define bfin_read_EMAC_RXC_GE1024()             bfin_read32(EMAC_RXC_GE1024)
-#define bfin_write_EMAC_RXC_GE1024(val)         bfin_write32(EMAC_RXC_GE1024, val)
-
-#define bfin_read_EMAC_TXC_OK()                 bfin_read32(EMAC_TXC_OK)
-#define bfin_write_EMAC_TXC_OK(val)             bfin_write32(EMAC_TXC_OK, val)
-#define bfin_read_EMAC_TXC_1COL()               bfin_read32(EMAC_TXC_1COL)
-#define bfin_write_EMAC_TXC_1COL(val)           bfin_write32(EMAC_TXC_1COL, val)
-#define bfin_read_EMAC_TXC_GT1COL()             bfin_read32(EMAC_TXC_GT1COL)
-#define bfin_write_EMAC_TXC_GT1COL(val)         bfin_write32(EMAC_TXC_GT1COL, val)
-#define bfin_read_EMAC_TXC_OCTET()              bfin_read32(EMAC_TXC_OCTET)
-#define bfin_write_EMAC_TXC_OCTET(val)          bfin_write32(EMAC_TXC_OCTET, val)
-#define bfin_read_EMAC_TXC_DEFER()              bfin_read32(EMAC_TXC_DEFER)
-#define bfin_write_EMAC_TXC_DEFER(val)          bfin_write32(EMAC_TXC_DEFER, val)
-#define bfin_read_EMAC_TXC_LATECL()             bfin_read32(EMAC_TXC_LATECL)
-#define bfin_write_EMAC_TXC_LATECL(val)         bfin_write32(EMAC_TXC_LATECL, val)
-#define bfin_read_EMAC_TXC_XS_COL()             bfin_read32(EMAC_TXC_XS_COL)
-#define bfin_write_EMAC_TXC_XS_COL(val)         bfin_write32(EMAC_TXC_XS_COL, val)
-#define bfin_read_EMAC_TXC_DMAUND()             bfin_read32(EMAC_TXC_DMAUND)
-#define bfin_write_EMAC_TXC_DMAUND(val)         bfin_write32(EMAC_TXC_DMAUND, val)
-#define bfin_read_EMAC_TXC_CRSERR()             bfin_read32(EMAC_TXC_CRSERR)
-#define bfin_write_EMAC_TXC_CRSERR(val)         bfin_write32(EMAC_TXC_CRSERR, val)
-#define bfin_read_EMAC_TXC_UNICST()             bfin_read32(EMAC_TXC_UNICST)
-#define bfin_write_EMAC_TXC_UNICST(val)         bfin_write32(EMAC_TXC_UNICST, val)
-#define bfin_read_EMAC_TXC_MULTI()              bfin_read32(EMAC_TXC_MULTI)
-#define bfin_write_EMAC_TXC_MULTI(val)          bfin_write32(EMAC_TXC_MULTI, val)
-#define bfin_read_EMAC_TXC_BROAD()              bfin_read32(EMAC_TXC_BROAD)
-#define bfin_write_EMAC_TXC_BROAD(val)          bfin_write32(EMAC_TXC_BROAD, val)
-#define bfin_read_EMAC_TXC_XS_DFR()             bfin_read32(EMAC_TXC_XS_DFR)
-#define bfin_write_EMAC_TXC_XS_DFR(val)         bfin_write32(EMAC_TXC_XS_DFR, val)
-#define bfin_read_EMAC_TXC_MACCTL()             bfin_read32(EMAC_TXC_MACCTL)
-#define bfin_write_EMAC_TXC_MACCTL(val)         bfin_write32(EMAC_TXC_MACCTL, val)
-#define bfin_read_EMAC_TXC_ALLFRM()             bfin_read32(EMAC_TXC_ALLFRM)
-#define bfin_write_EMAC_TXC_ALLFRM(val)         bfin_write32(EMAC_TXC_ALLFRM, val)
-#define bfin_read_EMAC_TXC_ALLOCT()             bfin_read32(EMAC_TXC_ALLOCT)
-#define bfin_write_EMAC_TXC_ALLOCT(val)         bfin_write32(EMAC_TXC_ALLOCT, val)
-#define bfin_read_EMAC_TXC_EQ64()               bfin_read32(EMAC_TXC_EQ64)
-#define bfin_write_EMAC_TXC_EQ64(val)           bfin_write32(EMAC_TXC_EQ64, val)
-#define bfin_read_EMAC_TXC_LT128()              bfin_read32(EMAC_TXC_LT128)
-#define bfin_write_EMAC_TXC_LT128(val)          bfin_write32(EMAC_TXC_LT128, val)
-#define bfin_read_EMAC_TXC_LT256()              bfin_read32(EMAC_TXC_LT256)
-#define bfin_write_EMAC_TXC_LT256(val)          bfin_write32(EMAC_TXC_LT256, val)
-#define bfin_read_EMAC_TXC_LT512()              bfin_read32(EMAC_TXC_LT512)
-#define bfin_write_EMAC_TXC_LT512(val)          bfin_write32(EMAC_TXC_LT512, val)
-#define bfin_read_EMAC_TXC_LT1024()             bfin_read32(EMAC_TXC_LT1024)
-#define bfin_write_EMAC_TXC_LT1024(val)         bfin_write32(EMAC_TXC_LT1024, val)
-#define bfin_read_EMAC_TXC_GE1024()             bfin_read32(EMAC_TXC_GE1024)
-#define bfin_write_EMAC_TXC_GE1024(val)         bfin_write32(EMAC_TXC_GE1024, val)
-#define bfin_read_EMAC_TXC_ABORT()              bfin_read32(EMAC_TXC_ABORT)
-#define bfin_write_EMAC_TXC_ABORT(val)          bfin_write32(EMAC_TXC_ABORT, val)
+/* PTP TSYNC Registers */
 
 #define bfin_read_EMAC_PTP_CTL()                bfin_read16(EMAC_PTP_CTL)
 #define bfin_write_EMAC_PTP_CTL(val)            bfin_write16(EMAC_PTP_CTL, val)
@@ -227,72 +56,4 @@
 #define bfin_read_EMAC_PTP_PPS_PERIOD()         bfin_read32(EMAC_PTP_PPS_PERIOD)
 #define bfin_write_EMAC_PTP_PPS_PERIOD(val)     bfin_write32(EMAC_PTP_PPS_PERIOD, val)
 
-/* Removable Storage Interface Registers */
-
-#define bfin_read_RSI_PWR_CTL()        bfin_read16(RSI_PWR_CONTROL)
-#define bfin_write_RSI_PWR_CTL(val)    bfin_write16(RSI_PWR_CONTROL, val)
-#define bfin_read_RSI_CLK_CTL()        bfin_read16(RSI_CLK_CONTROL)
-#define bfin_write_RSI_CLK_CTL(val)    bfin_write16(RSI_CLK_CONTROL, val)
-#define bfin_read_RSI_ARGUMENT()       bfin_read32(RSI_ARGUMENT)
-#define bfin_write_RSI_ARGUMENT(val)   bfin_write32(RSI_ARGUMENT, val)
-#define bfin_read_RSI_COMMAND()        bfin_read16(RSI_COMMAND)
-#define bfin_write_RSI_COMMAND(val)    bfin_write16(RSI_COMMAND, val)
-#define bfin_read_RSI_RESP_CMD()       bfin_read16(RSI_RESP_CMD)
-#define bfin_write_RSI_RESP_CMD(val)   bfin_write16(RSI_RESP_CMD, val)
-#define bfin_read_RSI_RESPONSE0()      bfin_read32(RSI_RESPONSE0)
-#define bfin_write_RSI_RESPONSE0(val)  bfin_write32(RSI_RESPONSE0, val)
-#define bfin_read_RSI_RESPONSE1()      bfin_read32(RSI_RESPONSE1)
-#define bfin_write_RSI_RESPONSE1(val)  bfin_write32(RSI_RESPONSE1, val)
-#define bfin_read_RSI_RESPONSE2()      bfin_read32(RSI_RESPONSE2)
-#define bfin_write_RSI_RESPONSE2(val)  bfin_write32(RSI_RESPONSE2, val)
-#define bfin_read_RSI_RESPONSE3()      bfin_read32(RSI_RESPONSE3)
-#define bfin_write_RSI_RESPONSE3(val)  bfin_write32(RSI_RESPONSE3, val)
-#define bfin_read_RSI_DATA_TIMER()     bfin_read32(RSI_DATA_TIMER)
-#define bfin_write_RSI_DATA_TIMER(val) bfin_write32(RSI_DATA_TIMER, val)
-#define bfin_read_RSI_DATA_LGTH()      bfin_read16(RSI_DATA_LGTH)
-#define bfin_write_RSI_DATA_LGTH(val)  bfin_write16(RSI_DATA_LGTH, val)
-#define bfin_read_RSI_DATA_CTL()       bfin_read16(RSI_DATA_CONTROL)
-#define bfin_write_RSI_DATA_CTL(val)   bfin_write16(RSI_DATA_CONTROL, val)
-#define bfin_read_RSI_DATA_CNT()       bfin_read16(RSI_DATA_CNT)
-#define bfin_write_RSI_DATA_CNT(val)   bfin_write16(RSI_DATA_CNT, val)
-#define bfin_read_RSI_STATUS()         bfin_read32(RSI_STATUS)
-#define bfin_write_RSI_STATUS(val)     bfin_write32(RSI_STATUS, val)
-#define bfin_read_RSI_STATUS_CLR()     bfin_read16(RSI_STATUSCL)
-#define bfin_write_RSI_STATUS_CLR(val) bfin_write16(RSI_STATUSCL, val)
-#define bfin_read_RSI_MASK0()          bfin_read32(RSI_MASK0)
-#define bfin_write_RSI_MASK0(val)      bfin_write32(RSI_MASK0, val)
-#define bfin_read_RSI_MASK1()          bfin_read32(RSI_MASK1)
-#define bfin_write_RSI_MASK1(val)      bfin_write32(RSI_MASK1, val)
-#define bfin_read_RSI_FIFO_CNT()       bfin_read16(RSI_FIFO_CNT)
-#define bfin_write_RSI_FIFO_CNT(val)   bfin_write16(RSI_FIFO_CNT, val)
-#define bfin_read_RSI_CEATA_CTL()      bfin_read16(RSI_CEATA_CONTROL)
-#define bfin_write_RSI_CEATA_CTL(val)  bfin_write16(RSI_CEATA_CONTROL, val)
-#define bfin_read_RSI_FIFO()           bfin_read32(RSI_FIFO)
-#define bfin_write_RSI_FIFO(val)       bfin_write32(RSI_FIFO, val)
-#define bfin_read_RSI_E_STATUS()       bfin_read16(RSI_ESTAT)
-#define bfin_write_RSI_E_STATUS(val)   bfin_write16(RSI_ESTAT, val)
-#define bfin_read_RSI_E_MASK()         bfin_read16(RSI_EMASK)
-#define bfin_write_RSI_E_MASK(val)     bfin_write16(RSI_EMASK, val)
-#define bfin_read_RSI_CFG()            bfin_read16(RSI_CONFIG)
-#define bfin_write_RSI_CFG(val)        bfin_write16(RSI_CONFIG, val)
-#define bfin_read_RSI_RD_WAIT_EN()     bfin_read16(RSI_RD_WAIT_EN)
-#define bfin_write_RSI_RD_WAIT_EN(val) bfin_write16(RSI_RD_WAIT_EN, val)
-#define bfin_read_RSI_PID0()           bfin_read16(RSI_PID0)
-#define bfin_write_RSI_PID0(val)       bfin_write16(RSI_PID0, val)
-#define bfin_read_RSI_PID1()           bfin_read16(RSI_PID1)
-#define bfin_write_RSI_PID1(val)       bfin_write16(RSI_PID1, val)
-#define bfin_read_RSI_PID2()           bfin_read16(RSI_PID2)
-#define bfin_write_RSI_PID2(val)       bfin_write16(RSI_PID2, val)
-#define bfin_read_RSI_PID3()           bfin_read16(RSI_PID3)
-#define bfin_write_RSI_PID3(val)       bfin_write16(RSI_PID3, val)
-#define bfin_read_RSI_PID4()           bfin_read16(RSI_PID4)
-#define bfin_write_RSI_PID4(val)       bfin_write16(RSI_PID4, val)
-#define bfin_read_RSI_PID5()           bfin_read16(RSI_PID5)
-#define bfin_write_RSI_PID5(val)       bfin_write16(RSI_PID5, val)
-#define bfin_read_RSI_PID6()           bfin_read16(RSI_PID6)
-#define bfin_write_RSI_PID6(val)       bfin_write16(RSI_PID6, val)
-#define bfin_read_RSI_PID7()           bfin_read16(RSI_PID7)
-#define bfin_write_RSI_PID7(val)       bfin_write16(RSI_PID7, val)
-
-
 #endif /* _CDEF_BF518_H */
diff --git a/arch/blackfin/mach-bf518/include/mach/cdefBF51x_base.h b/arch/blackfin/mach-bf518/include/mach/cdefBF51x_base.h
index 1d970df7aee9..e548e9d1d6fa 100644
--- a/arch/blackfin/mach-bf518/include/mach/cdefBF51x_base.h
+++ b/arch/blackfin/mach-bf518/include/mach/cdefBF51x_base.h
@@ -131,23 +131,6 @@
 #define bfin_write_UART0_GCTL(val)              bfin_write16(UART0_GCTL, val)
 
 
-/* SPI Controller               (0xFFC00500 - 0xFFC005FF)                                                                       */
-#define bfin_read_SPI_CTL()                     bfin_read16(SPI_CTL)
-#define bfin_write_SPI_CTL(val)                 bfin_write16(SPI_CTL, val)
-#define bfin_read_SPI_FLG()                     bfin_read16(SPI_FLG)
-#define bfin_write_SPI_FLG(val)                 bfin_write16(SPI_FLG, val)
-#define bfin_read_SPI_STAT()                    bfin_read16(SPI_STAT)
-#define bfin_write_SPI_STAT(val)                bfin_write16(SPI_STAT, val)
-#define bfin_read_SPI_TDBR()                    bfin_read16(SPI_TDBR)
-#define bfin_write_SPI_TDBR(val)                bfin_write16(SPI_TDBR, val)
-#define bfin_read_SPI_RDBR()                    bfin_read16(SPI_RDBR)
-#define bfin_write_SPI_RDBR(val)                bfin_write16(SPI_RDBR, val)
-#define bfin_read_SPI_BAUD()                    bfin_read16(SPI_BAUD)
-#define bfin_write_SPI_BAUD(val)                bfin_write16(SPI_BAUD, val)
-#define bfin_read_SPI_SHADOW()                  bfin_read16(SPI_SHADOW)
-#define bfin_write_SPI_SHADOW(val)              bfin_write16(SPI_SHADOW, val)
-
-
 /* TIMER0-7 Registers           (0xFFC00600 - 0xFFC006FF)                                                               */
 #define bfin_read_TIMER0_CONFIG()               bfin_read16(TIMER0_CONFIG)
 #define bfin_write_TIMER0_CONFIG(val)           bfin_write16(TIMER0_CONFIG, val)
@@ -844,6 +827,7 @@
 #define bfin_write_PPI_CONTROL(val)             bfin_write16(PPI_CONTROL, val)
 #define bfin_read_PPI_STATUS()                  bfin_read16(PPI_STATUS)
 #define bfin_write_PPI_STATUS(val)              bfin_write16(PPI_STATUS, val)
+#define bfin_clear_PPI_STATUS()                 bfin_write_PPI_STATUS(0xFFFF)
 #define bfin_read_PPI_DELAY()                   bfin_read16(PPI_DELAY)
 #define bfin_write_PPI_DELAY(val)               bfin_write16(PPI_DELAY, val)
 #define bfin_read_PPI_COUNT()                   bfin_read16(PPI_COUNT)
@@ -1062,17 +1046,6 @@
 #define bfin_read_CNT_MIN()                     bfin_read32(CNT_MIN)
 #define bfin_write_CNT_MIN(val)                 bfin_write32(CNT_MIN, val)
 
-/* OTP/FUSE Registers */
-
-#define bfin_read_OTP_CONTROL()                 bfin_read16(OTP_CONTROL)
-#define bfin_write_OTP_CONTROL(val)             bfin_write16(OTP_CONTROL, val)
-#define bfin_read_OTP_BEN()                     bfin_read16(OTP_BEN)
-#define bfin_write_OTP_BEN(val)                 bfin_write16(OTP_BEN, val)
-#define bfin_read_OTP_STATUS()                  bfin_read16(OTP_STATUS)
-#define bfin_write_OTP_STATUS(val)              bfin_write16(OTP_STATUS, val)
-#define bfin_read_OTP_TIMING()                  bfin_read32(OTP_TIMING)
-#define bfin_write_OTP_TIMING(val)              bfin_write32(OTP_TIMING, val)
-
 /* Security Registers */
 
 #define bfin_read_SECURE_SYSSWT()               bfin_read32(SECURE_SYSSWT)
@@ -1082,52 +1055,6 @@
 #define bfin_read_SECURE_STATUS()               bfin_read16(SECURE_STATUS)
 #define bfin_write_SECURE_STATUS(val)           bfin_write16(SECURE_STATUS, val)
 
-/* OTP Read/Write Data Buffer Registers */
-
-#define bfin_read_OTP_DATA0()                   bfin_read32(OTP_DATA0)
-#define bfin_write_OTP_DATA0(val)               bfin_write32(OTP_DATA0, val)
-#define bfin_read_OTP_DATA1()                   bfin_read32(OTP_DATA1)
-#define bfin_write_OTP_DATA1(val)               bfin_write32(OTP_DATA1, val)
-#define bfin_read_OTP_DATA2()                   bfin_read32(OTP_DATA2)
-#define bfin_write_OTP_DATA2(val)               bfin_write32(OTP_DATA2, val)
-#define bfin_read_OTP_DATA3()                   bfin_read32(OTP_DATA3)
-#define bfin_write_OTP_DATA3(val)               bfin_write32(OTP_DATA3, val)
-
-/* NFC Registers */
-
-#define bfin_read_NFC_CTL()                     bfin_read16(NFC_CTL)
-#define bfin_write_NFC_CTL(val)                 bfin_write16(NFC_CTL, val)
-#define bfin_read_NFC_STAT()                    bfin_read16(NFC_STAT)
-#define bfin_write_NFC_STAT(val)                bfin_write16(NFC_STAT, val)
-#define bfin_read_NFC_IRQSTAT()                 bfin_read16(NFC_IRQSTAT)
-#define bfin_write_NFC_IRQSTAT(val)             bfin_write16(NFC_IRQSTAT, val)
-#define bfin_read_NFC_IRQMASK()                 bfin_read16(NFC_IRQMASK)
-#define bfin_write_NFC_IRQMASK(val)             bfin_write16(NFC_IRQMASK, val)
-#define bfin_read_NFC_ECC0()                    bfin_read16(NFC_ECC0)
-#define bfin_write_NFC_ECC0(val)                bfin_write16(NFC_ECC0, val)
-#define bfin_read_NFC_ECC1()                    bfin_read16(NFC_ECC1)
-#define bfin_write_NFC_ECC1(val)                bfin_write16(NFC_ECC1, val)
-#define bfin_read_NFC_ECC2()                    bfin_read16(NFC_ECC2)
-#define bfin_write_NFC_ECC2(val)                bfin_write16(NFC_ECC2, val)
-#define bfin_read_NFC_ECC3()                    bfin_read16(NFC_ECC3)
-#define bfin_write_NFC_ECC3(val)                bfin_write16(NFC_ECC3, val)
-#define bfin_read_NFC_COUNT()                   bfin_read16(NFC_COUNT)
-#define bfin_write_NFC_COUNT(val)               bfin_write16(NFC_COUNT, val)
-#define bfin_read_NFC_RST()                     bfin_read16(NFC_RST)
-#define bfin_write_NFC_RST(val)                 bfin_write16(NFC_RST, val)
-#define bfin_read_NFC_PGCTL()                   bfin_read16(NFC_PGCTL)
-#define bfin_write_NFC_PGCTL(val)               bfin_write16(NFC_PGCTL, val)
-#define bfin_read_NFC_READ()                    bfin_read16(NFC_READ)
-#define bfin_write_NFC_READ(val)                bfin_write16(NFC_READ, val)
-#define bfin_read_NFC_ADDR()                    bfin_read16(NFC_ADDR)
-#define bfin_write_NFC_ADDR(val)                bfin_write16(NFC_ADDR, val)
-#define bfin_read_NFC_CMD()                     bfin_read16(NFC_CMD)
-#define bfin_write_NFC_CMD(val)                 bfin_write16(NFC_CMD, val)
-#define bfin_read_NFC_DATA_WR()                 bfin_read16(NFC_DATA_WR)
-#define bfin_write_NFC_DATA_WR(val)             bfin_write16(NFC_DATA_WR, val)
-#define bfin_read_NFC_DATA_RD()                 bfin_read16(NFC_DATA_RD)
-#define bfin_write_NFC_DATA_RD(val)             bfin_write16(NFC_DATA_RD, val)
-
 /* These need to be last due to the cdef/linux inter-dependencies */
 #include <asm/irq.h>
 
diff --git a/arch/blackfin/mach-bf518/include/mach/defBF514.h b/arch/blackfin/mach-bf518/include/mach/defBF514.h
index b5adca23a788..92e950d6e996 100644
--- a/arch/blackfin/mach-bf518/include/mach/defBF514.h
+++ b/arch/blackfin/mach-bf518/include/mach/defBF514.h
@@ -7,49 +7,8 @@
 #ifndef _DEF_BF514_H
 #define _DEF_BF514_H
 
-/* Include all Core registers and bit definitions */
-#include <asm/def_LPBlackfin.h>
-
-/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF514 */
-
-/* Include defBF51x_base.h for the set of #defines that are common to all ADSP-BF51x processors */
-#include "defBF51x_base.h"
-
-/* The following are the #defines needed by ADSP-BF514 that are not in the common header */
-
-/* SDH Registers */
-
-#define SDH_PWR_CTL                    0xFFC03900 /* SDH Power Control */
-#define SDH_CLK_CTL                    0xFFC03904 /* SDH Clock Control */
-#define SDH_ARGUMENT                   0xFFC03908 /* SDH Argument */
-#define SDH_COMMAND                    0xFFC0390C /* SDH Command */
-#define SDH_RESP_CMD                   0xFFC03910 /* SDH Response Command */
-#define SDH_RESPONSE0                  0xFFC03914 /* SDH Response0 */
-#define SDH_RESPONSE1                  0xFFC03918 /* SDH Response1 */
-#define SDH_RESPONSE2                  0xFFC0391C /* SDH Response2 */
-#define SDH_RESPONSE3                  0xFFC03920 /* SDH Response3 */
-#define SDH_DATA_TIMER                 0xFFC03924 /* SDH Data Timer */
-#define SDH_DATA_LGTH                  0xFFC03928 /* SDH Data Length */
-#define SDH_DATA_CTL                   0xFFC0392C /* SDH Data Control */
-#define SDH_DATA_CNT                   0xFFC03930 /* SDH Data Counter */
-#define SDH_STATUS                     0xFFC03934 /* SDH Status */
-#define SDH_STATUS_CLR                 0xFFC03938 /* SDH Status Clear */
-#define SDH_MASK0                      0xFFC0393C /* SDH Interrupt0 Mask */
-#define SDH_MASK1                      0xFFC03940 /* SDH Interrupt1 Mask */
-#define SDH_FIFO_CNT                   0xFFC03948 /* SDH FIFO Counter */
-#define SDH_FIFO                       0xFFC03980 /* SDH Data FIFO */
-#define SDH_E_STATUS                   0xFFC039C0 /* SDH Exception Status */
-#define SDH_E_MASK                     0xFFC039C4 /* SDH Exception Mask */
-#define SDH_CFG                        0xFFC039C8 /* SDH Configuration */
-#define SDH_RD_WAIT_EN                 0xFFC039CC /* SDH Read Wait Enable */
-#define SDH_PID0                       0xFFC039D0 /* SDH Peripheral Identification0 */
-#define SDH_PID1                       0xFFC039D4 /* SDH Peripheral Identification1 */
-#define SDH_PID2                       0xFFC039D8 /* SDH Peripheral Identification2 */
-#define SDH_PID3                       0xFFC039DC /* SDH Peripheral Identification3 */
-#define SDH_PID4                       0xFFC039E0 /* SDH Peripheral Identification4 */
-#define SDH_PID5                       0xFFC039E4 /* SDH Peripheral Identification5 */
-#define SDH_PID6                       0xFFC039E8 /* SDH Peripheral Identification6 */
-#define SDH_PID7                       0xFFC039EC /* SDH Peripheral Identification7 */
+/* BF514 is BF512 + RSI */
+#include "defBF512.h"
 
 /* Removable Storage Interface Registers */
 
diff --git a/arch/blackfin/mach-bf518/include/mach/defBF516.h b/arch/blackfin/mach-bf518/include/mach/defBF516.h
index 7eb18774d727..22a3aa0d2629 100644
--- a/arch/blackfin/mach-bf518/include/mach/defBF516.h
+++ b/arch/blackfin/mach-bf518/include/mach/defBF516.h
@@ -7,13 +7,8 @@
 #ifndef _DEF_BF516_H
 #define _DEF_BF516_H
 
-/* Include all Core registers and bit definitions */
-#include <asm/def_LPBlackfin.h>
-
-/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF516 */
-
-/* Include defBF51x_base.h for the set of #defines that are common to all ADSP-BF51x processors */
-#include "defBF51x_base.h"
+/* BF516 is BF514 + EMAC */
+#include "defBF514.h"
 
 /* The following are the #defines needed by ADSP-BF516 that are not in the common header */
 /* 10/100 Ethernet Controller   (0xFFC03000 - 0xFFC031FF) */
@@ -394,208 +389,4 @@
 #define TX_GE1024_CNT     0x00200000    /* 1024-Max-Byte TX Frames Sent                           */
 #define TX_ABORT_CNT      0x00400000    /* TX Frames Aborted                                      */
 
-/* SDH Registers */
-
-#define SDH_PWR_CTL                    0xFFC03900 /* SDH Power Control */
-#define SDH_CLK_CTL                    0xFFC03904 /* SDH Clock Control */
-#define SDH_ARGUMENT                   0xFFC03908 /* SDH Argument */
-#define SDH_COMMAND                    0xFFC0390C /* SDH Command */
-#define SDH_RESP_CMD                   0xFFC03910 /* SDH Response Command */
-#define SDH_RESPONSE0                  0xFFC03914 /* SDH Response0 */
-#define SDH_RESPONSE1                  0xFFC03918 /* SDH Response1 */
-#define SDH_RESPONSE2                  0xFFC0391C /* SDH Response2 */
-#define SDH_RESPONSE3                  0xFFC03920 /* SDH Response3 */
-#define SDH_DATA_TIMER                 0xFFC03924 /* SDH Data Timer */
-#define SDH_DATA_LGTH                  0xFFC03928 /* SDH Data Length */
-#define SDH_DATA_CTL                   0xFFC0392C /* SDH Data Control */
-#define SDH_DATA_CNT                   0xFFC03930 /* SDH Data Counter */
-#define SDH_STATUS                     0xFFC03934 /* SDH Status */
-#define SDH_STATUS_CLR                 0xFFC03938 /* SDH Status Clear */
-#define SDH_MASK0                      0xFFC0393C /* SDH Interrupt0 Mask */
-#define SDH_MASK1                      0xFFC03940 /* SDH Interrupt1 Mask */
-#define SDH_FIFO_CNT                   0xFFC03948 /* SDH FIFO Counter */
-#define SDH_FIFO                       0xFFC03980 /* SDH Data FIFO */
-#define SDH_E_STATUS                   0xFFC039C0 /* SDH Exception Status */
-#define SDH_E_MASK                     0xFFC039C4 /* SDH Exception Mask */
-#define SDH_CFG                        0xFFC039C8 /* SDH Configuration */
-#define SDH_RD_WAIT_EN                 0xFFC039CC /* SDH Read Wait Enable */
-#define SDH_PID0                       0xFFC039D0 /* SDH Peripheral Identification0 */
-#define SDH_PID1                       0xFFC039D4 /* SDH Peripheral Identification1 */
-#define SDH_PID2                       0xFFC039D8 /* SDH Peripheral Identification2 */
-#define SDH_PID3                       0xFFC039DC /* SDH Peripheral Identification3 */
-#define SDH_PID4                       0xFFC039E0 /* SDH Peripheral Identification4 */
-#define SDH_PID5                       0xFFC039E4 /* SDH Peripheral Identification5 */
-#define SDH_PID6                       0xFFC039E8 /* SDH Peripheral Identification6 */
-#define SDH_PID7                       0xFFC039EC /* SDH Peripheral Identification7 */
-
-/* Removable Storage Interface Registers */
-
-#define RSI_PWR_CONTROL                0xFFC03800 /* RSI Power Control Register */
-#define RSI_CLK_CONTROL                0xFFC03804 /* RSI Clock Control Register */
-#define RSI_ARGUMENT                   0xFFC03808 /* RSI Argument Register */
-#define RSI_COMMAND                    0xFFC0380C /* RSI Command Register */
-#define RSI_RESP_CMD                   0xFFC03810 /* RSI Response Command Register */
-#define RSI_RESPONSE0                  0xFFC03814 /* RSI Response Register */
-#define RSI_RESPONSE1                  0xFFC03818 /* RSI Response Register */
-#define RSI_RESPONSE2                  0xFFC0381C /* RSI Response Register */
-#define RSI_RESPONSE3                  0xFFC03820 /* RSI Response Register */
-#define RSI_DATA_TIMER                 0xFFC03824 /* RSI Data Timer Register */
-#define RSI_DATA_LGTH                  0xFFC03828 /* RSI Data Length Register */
-#define RSI_DATA_CONTROL               0xFFC0382C /* RSI Data Control Register */
-#define RSI_DATA_CNT                   0xFFC03830 /* RSI Data Counter Register */
-#define RSI_STATUS                     0xFFC03834 /* RSI Status Register */
-#define RSI_STATUSCL                   0xFFC03838 /* RSI Status Clear Register */
-#define RSI_MASK0                      0xFFC0383C /* RSI Interrupt 0 Mask Register */
-#define RSI_MASK1                      0xFFC03840 /* RSI Interrupt 1 Mask Register */
-#define RSI_FIFO_CNT                   0xFFC03848 /* RSI FIFO Counter Register */
-#define RSI_CEATA_CONTROL              0xFFC0384C /* RSI CEATA Register */
-#define RSI_FIFO                       0xFFC03880 /* RSI Data FIFO Register */
-#define RSI_ESTAT                      0xFFC038C0 /* RSI Exception Status Register */
-#define RSI_EMASK                      0xFFC038C4 /* RSI Exception Mask Register */
-#define RSI_CONFIG                     0xFFC038C8 /* RSI Configuration Register */
-#define RSI_RD_WAIT_EN                 0xFFC038CC /* RSI Read Wait Enable Register */
-#define RSI_PID0                       0xFFC03FE0 /* RSI Peripheral ID Register 0 */
-#define RSI_PID1                       0xFFC03FE4 /* RSI Peripheral ID Register 1 */
-#define RSI_PID2                       0xFFC03FE8 /* RSI Peripheral ID Register 2 */
-#define RSI_PID3                       0xFFC03FEC /* RSI Peripheral ID Register 3 */
-#define RSI_PID4                       0xFFC03FF0 /* RSI Peripheral ID Register 4 */
-#define RSI_PID5                       0xFFC03FF4 /* RSI Peripheral ID Register 5 */
-#define RSI_PID6                       0xFFC03FF8 /* RSI Peripheral ID Register 6 */
-#define RSI_PID7                       0xFFC03FFC /* RSI Peripheral ID Register 7 */
-
-/* ********************************************************** */
-/*     SINGLE BIT MACRO PAIRS (bit mask and negated one)      */
-/*     and MULTI BIT READ MACROS                              */
-/* ********************************************************** */
-
-/* Bit masks for SDH_COMMAND */
-
-#define                   CMD_IDX  0x3f       /* Command Index */
-#define                   CMD_RSP  0x40       /* Response */
-#define                 CMD_L_RSP  0x80       /* Long Response */
-#define                 CMD_INT_E  0x100      /* Command Interrupt */
-#define                CMD_PEND_E  0x200      /* Command Pending */
-#define                     CMD_E  0x400      /* Command Enable */
-
-/* Bit masks for SDH_PWR_CTL */
-
-#define                    PWR_ON  0x3        /* Power On */
-#if 0
-#define                       TBD  0x3c       /* TBD */
-#endif
-#define                 SD_CMD_OD  0x40       /* Open Drain Output */
-#define                   ROD_CTL  0x80       /* Rod Control */
-
-/* Bit masks for SDH_CLK_CTL */
-
-#define                    CLKDIV  0xff       /* MC_CLK Divisor */
-#define                     CLK_E  0x100      /* MC_CLK Bus Clock Enable */
-#define                  PWR_SV_E  0x200      /* Power Save Enable */
-#define             CLKDIV_BYPASS  0x400      /* Bypass Divisor */
-#define                  WIDE_BUS  0x800      /* Wide Bus Mode Enable */
-
-/* Bit masks for SDH_RESP_CMD */
-
-#define                  RESP_CMD  0x3f       /* Response Command */
-
-/* Bit masks for SDH_DATA_CTL */
-
-#define                     DTX_E  0x1        /* Data Transfer Enable */
-#define                   DTX_DIR  0x2        /* Data Transfer Direction */
-#define                  DTX_MODE  0x4        /* Data Transfer Mode */
-#define                 DTX_DMA_E  0x8        /* Data Transfer DMA Enable */
-#define              DTX_BLK_LGTH  0xf0       /* Data Transfer Block Length */
-
-/* Bit masks for SDH_STATUS */
-
-#define              CMD_CRC_FAIL  0x1        /* CMD CRC Fail */
-#define              DAT_CRC_FAIL  0x2        /* Data CRC Fail */
-#define               CMD_TIME_OUT  0x4        /* CMD Time Out */
-#define               DAT_TIME_OUT  0x8        /* Data Time Out */
-#define               TX_UNDERRUN  0x10       /* Transmit Underrun */
-#define                RX_OVERRUN  0x20       /* Receive Overrun */
-#define              CMD_RESP_END  0x40       /* CMD Response End */
-#define                  CMD_SENT  0x80       /* CMD Sent */
-#define                   DAT_END  0x100      /* Data End */
-#define             START_BIT_ERR  0x200      /* Start Bit Error */
-#define               DAT_BLK_END  0x400      /* Data Block End */
-#define                   CMD_ACT  0x800      /* CMD Active */
-#define                    TX_ACT  0x1000     /* Transmit Active */
-#define                    RX_ACT  0x2000     /* Receive Active */
-#define              TX_FIFO_STAT  0x4000     /* Transmit FIFO Status */
-#define              RX_FIFO_STAT  0x8000     /* Receive FIFO Status */
-#define              TX_FIFO_FULL  0x10000    /* Transmit FIFO Full */
-#define              RX_FIFO_FULL  0x20000    /* Receive FIFO Full */
-#define              TX_FIFO_ZERO  0x40000    /* Transmit FIFO Empty */
-#define               RX_DAT_ZERO  0x80000    /* Receive FIFO Empty */
-#define                TX_DAT_RDY  0x100000   /* Transmit Data Available */
-#define               RX_FIFO_RDY  0x200000   /* Receive Data Available */
-
-/* Bit masks for SDH_STATUS_CLR */
-
-#define         CMD_CRC_FAIL_STAT  0x1        /* CMD CRC Fail Status */
-#define         DAT_CRC_FAIL_STAT  0x2        /* Data CRC Fail Status */
-#define          CMD_TIMEOUT_STAT  0x4        /* CMD Time Out Status */
-#define          DAT_TIMEOUT_STAT  0x8        /* Data Time Out status */
-#define          TX_UNDERRUN_STAT  0x10       /* Transmit Underrun Status */
-#define           RX_OVERRUN_STAT  0x20       /* Receive Overrun Status */
-#define         CMD_RESP_END_STAT  0x40       /* CMD Response End Status */
-#define             CMD_SENT_STAT  0x80       /* CMD Sent Status */
-#define              DAT_END_STAT  0x100      /* Data End Status */
-#define        START_BIT_ERR_STAT  0x200      /* Start Bit Error Status */
-#define          DAT_BLK_END_STAT  0x400      /* Data Block End Status */
-
-/* Bit masks for SDH_MASK0 */
-
-#define         CMD_CRC_FAIL_MASK  0x1        /* CMD CRC Fail Mask */
-#define         DAT_CRC_FAIL_MASK  0x2        /* Data CRC Fail Mask */
-#define          CMD_TIMEOUT_MASK  0x4        /* CMD Time Out Mask */
-#define          DAT_TIMEOUT_MASK  0x8        /* Data Time Out Mask */
-#define          TX_UNDERRUN_MASK  0x10       /* Transmit Underrun Mask */
-#define           RX_OVERRUN_MASK  0x20       /* Receive Overrun Mask */
-#define         CMD_RESP_END_MASK  0x40       /* CMD Response End Mask */
-#define             CMD_SENT_MASK  0x80       /* CMD Sent Mask */
-#define              DAT_END_MASK  0x100      /* Data End Mask */
-#define        START_BIT_ERR_MASK  0x200      /* Start Bit Error Mask */
-#define          DAT_BLK_END_MASK  0x400      /* Data Block End Mask */
-#define              CMD_ACT_MASK  0x800      /* CMD Active Mask */
-#define               TX_ACT_MASK  0x1000     /* Transmit Active Mask */
-#define               RX_ACT_MASK  0x2000     /* Receive Active Mask */
-#define         TX_FIFO_STAT_MASK  0x4000     /* Transmit FIFO Status Mask */
-#define         RX_FIFO_STAT_MASK  0x8000     /* Receive FIFO Status Mask */
-#define         TX_FIFO_FULL_MASK  0x10000    /* Transmit FIFO Full Mask */
-#define         RX_FIFO_FULL_MASK  0x20000    /* Receive FIFO Full Mask */
-#define         TX_FIFO_ZERO_MASK  0x40000    /* Transmit FIFO Empty Mask */
-#define          RX_DAT_ZERO_MASK  0x80000    /* Receive FIFO Empty Mask */
-#define           TX_DAT_RDY_MASK  0x100000   /* Transmit Data Available Mask */
-#define          RX_FIFO_RDY_MASK  0x200000   /* Receive Data Available Mask */
-
-/* Bit masks for SDH_FIFO_CNT */
-
-#define                FIFO_COUNT  0x7fff     /* FIFO Count */
-
-/* Bit masks for SDH_E_STATUS */
-
-#define              SDIO_INT_DET  0x2        /* SDIO Int Detected */
-#define               SD_CARD_DET  0x10       /* SD Card Detect */
-
-/* Bit masks for SDH_E_MASK */
-
-#define                  SDIO_MSK  0x2        /* Mask SDIO Int Detected */
-#define                   SCD_MSK  0x40       /* Mask Card Detect */
-
-/* Bit masks for SDH_CFG */
-
-#define                   CLKS_EN  0x1        /* Clocks Enable */
-#define                      SD4E  0x4        /* SDIO 4-Bit Enable */
-#define                       MWE  0x8        /* Moving Window Enable */
-#define                    SD_RST  0x10       /* SDMMC Reset */
-#define                 PUP_SDDAT  0x20       /* Pull-up SD_DAT */
-#define                PUP_SDDAT3  0x40       /* Pull-up SD_DAT3 */
-#define                 PD_SDDAT3  0x80       /* Pull-down SD_DAT3 */
-
-/* Bit masks for SDH_RD_WAIT_EN */
-
-#define                       RWR  0x1        /* Read Wait Request */
-
 #endif /* _DEF_BF516_H */
diff --git a/arch/blackfin/mach-bf518/include/mach/defBF518.h b/arch/blackfin/mach-bf518/include/mach/defBF518.h
index 794cf06eb5ba..cb18270e55c2 100644
--- a/arch/blackfin/mach-bf518/include/mach/defBF518.h
+++ b/arch/blackfin/mach-bf518/include/mach/defBF518.h
@@ -7,461 +7,8 @@
 #ifndef _DEF_BF518_H
 #define _DEF_BF518_H
 
-/* Include all Core registers and bit definitions */
-#include <asm/def_LPBlackfin.h>
-
-/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF518 */
-
-/* Include defBF51x_base.h for the set of #defines that are common to all ADSP-BF51x processors */
-#include "defBF51x_base.h"
-
-/* The following are the #defines needed by ADSP-BF518 that are not in the common header */
-/* 10/100 Ethernet Controller   (0xFFC03000 - 0xFFC031FF) */
-
-#define EMAC_OPMODE             0xFFC03000       /* Operating Mode Register                              */
-#define EMAC_ADDRLO             0xFFC03004       /* Address Low (32 LSBs) Register                       */
-#define EMAC_ADDRHI             0xFFC03008       /* Address High (16 MSBs) Register                      */
-#define EMAC_HASHLO             0xFFC0300C       /* Multicast Hash Table Low (Bins 31-0) Register        */
-#define EMAC_HASHHI             0xFFC03010       /* Multicast Hash Table High (Bins 63-32) Register      */
-#define EMAC_STAADD             0xFFC03014       /* Station Management Address Register                  */
-#define EMAC_STADAT             0xFFC03018       /* Station Management Data Register                     */
-#define EMAC_FLC                0xFFC0301C       /* Flow Control Register                                */
-#define EMAC_VLAN1              0xFFC03020       /* VLAN1 Tag Register                                   */
-#define EMAC_VLAN2              0xFFC03024       /* VLAN2 Tag Register                                   */
-#define EMAC_WKUP_CTL           0xFFC0302C       /* Wake-Up Control/Status Register                      */
-#define EMAC_WKUP_FFMSK0        0xFFC03030       /* Wake-Up Frame Filter 0 Byte Mask Register            */
-#define EMAC_WKUP_FFMSK1        0xFFC03034       /* Wake-Up Frame Filter 1 Byte Mask Register            */
-#define EMAC_WKUP_FFMSK2        0xFFC03038       /* Wake-Up Frame Filter 2 Byte Mask Register            */
-#define EMAC_WKUP_FFMSK3        0xFFC0303C       /* Wake-Up Frame Filter 3 Byte Mask Register            */
-#define EMAC_WKUP_FFCMD         0xFFC03040       /* Wake-Up Frame Filter Commands Register               */
-#define EMAC_WKUP_FFOFF         0xFFC03044       /* Wake-Up Frame Filter Offsets Register                */
-#define EMAC_WKUP_FFCRC0        0xFFC03048       /* Wake-Up Frame Filter 0,1 CRC-16 Register             */
-#define EMAC_WKUP_FFCRC1        0xFFC0304C       /* Wake-Up Frame Filter 2,3 CRC-16 Register             */
-
-#define EMAC_SYSCTL             0xFFC03060       /* EMAC System Control Register                         */
-#define EMAC_SYSTAT             0xFFC03064       /* EMAC System Status Register                          */
-#define EMAC_RX_STAT            0xFFC03068       /* RX Current Frame Status Register                     */
-#define EMAC_RX_STKY            0xFFC0306C       /* RX Sticky Frame Status Register                      */
-#define EMAC_RX_IRQE            0xFFC03070       /* RX Frame Status Interrupt Enables Register           */
-#define EMAC_TX_STAT            0xFFC03074       /* TX Current Frame Status Register                     */
-#define EMAC_TX_STKY            0xFFC03078       /* TX Sticky Frame Status Register                      */
-#define EMAC_TX_IRQE            0xFFC0307C       /* TX Frame Status Interrupt Enables Register           */
-
-#define EMAC_MMC_CTL            0xFFC03080       /* MMC Counter Control Register                         */
-#define EMAC_MMC_RIRQS          0xFFC03084       /* MMC RX Interrupt Status Register                     */
-#define EMAC_MMC_RIRQE          0xFFC03088       /* MMC RX Interrupt Enables Register                    */
-#define EMAC_MMC_TIRQS          0xFFC0308C       /* MMC TX Interrupt Status Register                     */
-#define EMAC_MMC_TIRQE          0xFFC03090       /* MMC TX Interrupt Enables Register                    */
-
-#define EMAC_RXC_OK             0xFFC03100       /* RX Frame Successful Count                            */
-#define EMAC_RXC_FCS            0xFFC03104       /* RX Frame FCS Failure Count                           */
-#define EMAC_RXC_ALIGN          0xFFC03108       /* RX Alignment Error Count                             */
-#define EMAC_RXC_OCTET          0xFFC0310C       /* RX Octets Successfully Received Count                */
-#define EMAC_RXC_DMAOVF         0xFFC03110       /* Internal MAC Sublayer Error RX Frame Count           */
-#define EMAC_RXC_UNICST         0xFFC03114       /* Unicast RX Frame Count                               */
-#define EMAC_RXC_MULTI          0xFFC03118       /* Multicast RX Frame Count                             */
-#define EMAC_RXC_BROAD          0xFFC0311C       /* Broadcast RX Frame Count                             */
-#define EMAC_RXC_LNERRI         0xFFC03120       /* RX Frame In Range Error Count                        */
-#define EMAC_RXC_LNERRO         0xFFC03124       /* RX Frame Out Of Range Error Count                    */
-#define EMAC_RXC_LONG           0xFFC03128       /* RX Frame Too Long Count                              */
-#define EMAC_RXC_MACCTL         0xFFC0312C       /* MAC Control RX Frame Count                           */
-#define EMAC_RXC_OPCODE         0xFFC03130       /* Unsupported Op-Code RX Frame Count                   */
-#define EMAC_RXC_PAUSE          0xFFC03134       /* MAC Control Pause RX Frame Count                     */
-#define EMAC_RXC_ALLFRM         0xFFC03138       /* Overall RX Frame Count                               */
-#define EMAC_RXC_ALLOCT         0xFFC0313C       /* Overall RX Octet Count                               */
-#define EMAC_RXC_TYPED          0xFFC03140       /* Type/Length Consistent RX Frame Count                */
-#define EMAC_RXC_SHORT          0xFFC03144       /* RX Frame Fragment Count - Byte Count x < 64          */
-#define EMAC_RXC_EQ64           0xFFC03148       /* Good RX Frame Count - Byte Count x = 64              */
-#define EMAC_RXC_LT128          0xFFC0314C       /* Good RX Frame Count - Byte Count  64 < x < 128       */
-#define EMAC_RXC_LT256          0xFFC03150       /* Good RX Frame Count - Byte Count 128 <= x < 256      */
-#define EMAC_RXC_LT512          0xFFC03154       /* Good RX Frame Count - Byte Count 256 <= x < 512      */
-#define EMAC_RXC_LT1024         0xFFC03158       /* Good RX Frame Count - Byte Count 512 <= x < 1024     */
-#define EMAC_RXC_GE1024         0xFFC0315C       /* Good RX Frame Count - Byte Count x >= 1024           */
-
-#define EMAC_TXC_OK             0xFFC03180       /* TX Frame Successful Count                             */
-#define EMAC_TXC_1COL           0xFFC03184       /* TX Frames Successful After Single Collision Count     */
-#define EMAC_TXC_GT1COL         0xFFC03188       /* TX Frames Successful After Multiple Collisions Count  */
-#define EMAC_TXC_OCTET          0xFFC0318C       /* TX Octets Successfully Received Count                 */
-#define EMAC_TXC_DEFER          0xFFC03190       /* TX Frame Delayed Due To Busy Count                    */
-#define EMAC_TXC_LATECL         0xFFC03194       /* Late TX Collisions Count                              */
-#define EMAC_TXC_XS_COL         0xFFC03198       /* TX Frame Failed Due To Excessive Collisions Count     */
-#define EMAC_TXC_DMAUND         0xFFC0319C       /* Internal MAC Sublayer Error TX Frame Count            */
-#define EMAC_TXC_CRSERR         0xFFC031A0       /* Carrier Sense Deasserted During TX Frame Count        */
-#define EMAC_TXC_UNICST         0xFFC031A4       /* Unicast TX Frame Count                                */
-#define EMAC_TXC_MULTI          0xFFC031A8       /* Multicast TX Frame Count                              */
-#define EMAC_TXC_BROAD          0xFFC031AC       /* Broadcast TX Frame Count                              */
-#define EMAC_TXC_XS_DFR         0xFFC031B0       /* TX Frames With Excessive Deferral Count               */
-#define EMAC_TXC_MACCTL         0xFFC031B4       /* MAC Control TX Frame Count                            */
-#define EMAC_TXC_ALLFRM         0xFFC031B8       /* Overall TX Frame Count                                */
-#define EMAC_TXC_ALLOCT         0xFFC031BC       /* Overall TX Octet Count                                */
-#define EMAC_TXC_EQ64           0xFFC031C0       /* Good TX Frame Count - Byte Count x = 64               */
-#define EMAC_TXC_LT128          0xFFC031C4       /* Good TX Frame Count - Byte Count  64 < x < 128        */
-#define EMAC_TXC_LT256          0xFFC031C8       /* Good TX Frame Count - Byte Count 128 <= x < 256       */
-#define EMAC_TXC_LT512          0xFFC031CC       /* Good TX Frame Count - Byte Count 256 <= x < 512       */
-#define EMAC_TXC_LT1024         0xFFC031D0       /* Good TX Frame Count - Byte Count 512 <= x < 1024      */
-#define EMAC_TXC_GE1024         0xFFC031D4       /* Good TX Frame Count - Byte Count x >= 1024            */
-#define EMAC_TXC_ABORT          0xFFC031D8       /* Total TX Frames Aborted Count                         */
-
-/* Listing for IEEE-Supported Count Registers */
-
-#define FramesReceivedOK                EMAC_RXC_OK        /* RX Frame Successful Count                            */
-#define FrameCheckSequenceErrors        EMAC_RXC_FCS       /* RX Frame FCS Failure Count                           */
-#define AlignmentErrors                 EMAC_RXC_ALIGN     /* RX Alignment Error Count                             */
-#define OctetsReceivedOK                EMAC_RXC_OCTET     /* RX Octets Successfully Received Count                */
-#define FramesLostDueToIntMACRcvError   EMAC_RXC_DMAOVF    /* Internal MAC Sublayer Error RX Frame Count           */
-#define UnicastFramesReceivedOK         EMAC_RXC_UNICST    /* Unicast RX Frame Count                               */
-#define MulticastFramesReceivedOK       EMAC_RXC_MULTI     /* Multicast RX Frame Count                             */
-#define BroadcastFramesReceivedOK       EMAC_RXC_BROAD     /* Broadcast RX Frame Count                             */
-#define InRangeLengthErrors             EMAC_RXC_LNERRI    /* RX Frame In Range Error Count                        */
-#define OutOfRangeLengthField           EMAC_RXC_LNERRO    /* RX Frame Out Of Range Error Count                    */
-#define FrameTooLongErrors              EMAC_RXC_LONG      /* RX Frame Too Long Count                              */
-#define MACControlFramesReceived        EMAC_RXC_MACCTL    /* MAC Control RX Frame Count                           */
-#define UnsupportedOpcodesReceived      EMAC_RXC_OPCODE    /* Unsupported Op-Code RX Frame Count                   */
-#define PAUSEMACCtrlFramesReceived      EMAC_RXC_PAUSE     /* MAC Control Pause RX Frame Count                     */
-#define FramesReceivedAll               EMAC_RXC_ALLFRM    /* Overall RX Frame Count                               */
-#define OctetsReceivedAll               EMAC_RXC_ALLOCT    /* Overall RX Octet Count                               */
-#define TypedFramesReceived             EMAC_RXC_TYPED     /* Type/Length Consistent RX Frame Count                */
-#define FramesLenLt64Received           EMAC_RXC_SHORT     /* RX Frame Fragment Count - Byte Count x < 64          */
-#define FramesLenEq64Received           EMAC_RXC_EQ64      /* Good RX Frame Count - Byte Count x = 64              */
-#define FramesLen65_127Received         EMAC_RXC_LT128     /* Good RX Frame Count - Byte Count  64 < x < 128       */
-#define FramesLen128_255Received        EMAC_RXC_LT256     /* Good RX Frame Count - Byte Count 128 <= x < 256      */
-#define FramesLen256_511Received        EMAC_RXC_LT512     /* Good RX Frame Count - Byte Count 256 <= x < 512      */
-#define FramesLen512_1023Received       EMAC_RXC_LT1024    /* Good RX Frame Count - Byte Count 512 <= x < 1024     */
-#define FramesLen1024_MaxReceived       EMAC_RXC_GE1024    /* Good RX Frame Count - Byte Count x >= 1024           */
-
-#define FramesTransmittedOK             EMAC_TXC_OK        /* TX Frame Successful Count                            */
-#define SingleCollisionFrames           EMAC_TXC_1COL      /* TX Frames Successful After Single Collision Count    */
-#define MultipleCollisionFrames         EMAC_TXC_GT1COL    /* TX Frames Successful After Multiple Collisions Count */
-#define OctetsTransmittedOK             EMAC_TXC_OCTET     /* TX Octets Successfully Received Count                */
-#define FramesWithDeferredXmissions     EMAC_TXC_DEFER     /* TX Frame Delayed Due To Busy Count                   */
-#define LateCollisions                  EMAC_TXC_LATECL    /* Late TX Collisions Count                             */
-#define FramesAbortedDueToXSColls       EMAC_TXC_XS_COL    /* TX Frame Failed Due To Excessive Collisions Count    */
-#define FramesLostDueToIntMacXmitError  EMAC_TXC_DMAUND    /* Internal MAC Sublayer Error TX Frame Count           */
-#define CarrierSenseErrors              EMAC_TXC_CRSERR    /* Carrier Sense Deasserted During TX Frame Count       */
-#define UnicastFramesXmittedOK          EMAC_TXC_UNICST    /* Unicast TX Frame Count                               */
-#define MulticastFramesXmittedOK        EMAC_TXC_MULTI     /* Multicast TX Frame Count                             */
-#define BroadcastFramesXmittedOK        EMAC_TXC_BROAD     /* Broadcast TX Frame Count                             */
-#define FramesWithExcessiveDeferral     EMAC_TXC_XS_DFR    /* TX Frames With Excessive Deferral Count              */
-#define MACControlFramesTransmitted     EMAC_TXC_MACCTL    /* MAC Control TX Frame Count                           */
-#define FramesTransmittedAll            EMAC_TXC_ALLFRM    /* Overall TX Frame Count                               */
-#define OctetsTransmittedAll            EMAC_TXC_ALLOCT    /* Overall TX Octet Count                               */
-#define FramesLenEq64Transmitted        EMAC_TXC_EQ64      /* Good TX Frame Count - Byte Count x = 64              */
-#define FramesLen65_127Transmitted      EMAC_TXC_LT128     /* Good TX Frame Count - Byte Count  64 < x < 128       */
-#define FramesLen128_255Transmitted     EMAC_TXC_LT256     /* Good TX Frame Count - Byte Count 128 <= x < 256      */
-#define FramesLen256_511Transmitted     EMAC_TXC_LT512     /* Good TX Frame Count - Byte Count 256 <= x < 512      */
-#define FramesLen512_1023Transmitted    EMAC_TXC_LT1024    /* Good TX Frame Count - Byte Count 512 <= x < 1024     */
-#define FramesLen1024_MaxTransmitted    EMAC_TXC_GE1024    /* Good TX Frame Count - Byte Count x >= 1024           */
-#define TxAbortedFrames                 EMAC_TXC_ABORT     /* Total TX Frames Aborted Count                        */
-
-/***********************************************************************************
-** System MMR Register Bits And Macros
-**
-** Disclaimer:  All macros are intended to make C and Assembly code more readable.
-**                              Use these macros carefully, as any that do left shifts for field
-**                              depositing will result in the lower order bits being destroyed.  Any
-**                              macro that shifts left to properly position the bit-field should be
-**                              used as part of an OR to initialize a register and NOT as a dynamic
-**                              modifier UNLESS the lower order bits are saved and ORed back in when
-**                              the macro is used.
-*************************************************************************************/
-
-/************************  ETHERNET 10/100 CONTROLLER MASKS  ************************/
-
-/* EMAC_OPMODE Masks */
-
-#define RE                 0x00000001     /* Receiver Enable                                    */
-#define ASTP               0x00000002     /* Enable Automatic Pad Stripping On RX Frames        */
-#define HU                 0x00000010     /* Hash Filter Unicast Address                        */
-#define HM                 0x00000020     /* Hash Filter Multicast Address                      */
-#define PAM                0x00000040     /* Pass-All-Multicast Mode Enable                     */
-#define PR                 0x00000080     /* Promiscuous Mode Enable                            */
-#define IFE                0x00000100     /* Inverse Filtering Enable                           */
-#define DBF                0x00000200     /* Disable Broadcast Frame Reception                  */
-#define PBF                0x00000400     /* Pass Bad Frames Enable                             */
-#define PSF                0x00000800     /* Pass Short Frames Enable                           */
-#define RAF                0x00001000     /* Receive-All Mode                                   */
-#define TE                 0x00010000     /* Transmitter Enable                                 */
-#define DTXPAD             0x00020000     /* Disable Automatic TX Padding                       */
-#define DTXCRC             0x00040000     /* Disable Automatic TX CRC Generation                */
-#define DC                 0x00080000     /* Deferral Check                                     */
-#define BOLMT              0x00300000     /* Back-Off Limit                                     */
-#define BOLMT_10           0x00000000     /*            10-bit range                            */
-#define BOLMT_8            0x00100000     /*            8-bit range                             */
-#define BOLMT_4            0x00200000     /*            4-bit range                             */
-#define BOLMT_1            0x00300000     /*            1-bit range                             */
-#define DRTY               0x00400000     /* Disable TX Retry On Collision                      */
-#define LCTRE              0x00800000     /* Enable TX Retry On Late Collision                  */
-#define RMII               0x01000000     /* RMII/MII* Mode                                     */
-#define RMII_10            0x02000000     /* Speed Select for RMII Port (10MBit/100MBit*)       */
-#define FDMODE             0x04000000     /* Duplex Mode Enable (Full/Half*)                    */
-#define LB                 0x08000000     /* Internal Loopback Enable                           */
-#define DRO                0x10000000     /* Disable Receive Own Frames (Half-Duplex Mode)      */
-
-/* EMAC_STAADD Masks */
-
-#define STABUSY            0x00000001     /* Initiate Station Mgt Reg Access / STA Busy Stat    */
-#define STAOP              0x00000002     /* Station Management Operation Code (Write/Read*)    */
-#define STADISPRE          0x00000004     /* Disable Preamble Generation                        */
-#define STAIE              0x00000008     /* Station Mgt. Transfer Done Interrupt Enable        */
-#define REGAD              0x000007C0     /* STA Register Address                               */
-#define PHYAD              0x0000F800     /* PHY Device Address                                 */
-
-#define SET_REGAD(x) (((x)&0x1F)<<  6 )   /* Set STA Register Address                           */
-#define SET_PHYAD(x) (((x)&0x1F)<< 11 )   /* Set PHY Device Address                             */
-
-/* EMAC_STADAT Mask */
-
-#define STADATA            0x0000FFFF     /* Station Management Data                            */
-
-/* EMAC_FLC Masks */
-
-#define FLCBUSY            0x00000001     /* Send Flow Ctrl Frame / Flow Ctrl Busy Status       */
-#define FLCE               0x00000002     /* Flow Control Enable                                */
-#define PCF                0x00000004     /* Pass Control Frames                                */
-#define BKPRSEN            0x00000008     /* Enable Backpressure                                */
-#define FLCPAUSE           0xFFFF0000     /* Pause Time                                         */
-
-#define SET_FLCPAUSE(x) (((x)&0xFFFF)<< 16) /* Set Pause Time                                   */
-
-/* EMAC_WKUP_CTL Masks */
-
-#define CAPWKFRM           0x00000001    /* Capture Wake-Up Frames                              */
-#define MPKE               0x00000002    /* Magic Packet Enable                                 */
-#define RWKE               0x00000004    /* Remote Wake-Up Frame Enable                         */
-#define GUWKE              0x00000008    /* Global Unicast Wake Enable                          */
-#define MPKS               0x00000020    /* Magic Packet Received Status                        */
-#define RWKS               0x00000F00    /* Wake-Up Frame Received Status, Filters 3:0          */
-
-/* EMAC_WKUP_FFCMD Masks */
-
-#define WF0_E              0x00000001    /* Enable Wake-Up Filter 0                              */
-#define WF0_T              0x00000008    /* Wake-Up Filter 0 Addr Type (Multicast/Unicast*)      */
-#define WF1_E              0x00000100    /* Enable Wake-Up Filter 1                              */
-#define WF1_T              0x00000800    /* Wake-Up Filter 1 Addr Type (Multicast/Unicast*)      */
-#define WF2_E              0x00010000    /* Enable Wake-Up Filter 2                              */
-#define WF2_T              0x00080000    /* Wake-Up Filter 2 Addr Type (Multicast/Unicast*)      */
-#define WF3_E              0x01000000    /* Enable Wake-Up Filter 3                              */
-#define WF3_T              0x08000000    /* Wake-Up Filter 3 Addr Type (Multicast/Unicast*)      */
-
-/* EMAC_WKUP_FFOFF Masks */
-
-#define WF0_OFF            0x000000FF    /* Wake-Up Filter 0 Pattern Offset                      */
-#define WF1_OFF            0x0000FF00    /* Wake-Up Filter 1 Pattern Offset                      */
-#define WF2_OFF            0x00FF0000    /* Wake-Up Filter 2 Pattern Offset                      */
-#define WF3_OFF            0xFF000000    /* Wake-Up Filter 3 Pattern Offset                      */
-
-#define SET_WF0_OFF(x) (((x)&0xFF)<<  0 ) /* Set Wake-Up Filter 0 Byte Offset                    */
-#define SET_WF1_OFF(x) (((x)&0xFF)<<  8 ) /* Set Wake-Up Filter 1 Byte Offset                    */
-#define SET_WF2_OFF(x) (((x)&0xFF)<< 16 ) /* Set Wake-Up Filter 2 Byte Offset                    */
-#define SET_WF3_OFF(x) (((x)&0xFF)<< 24 ) /* Set Wake-Up Filter 3 Byte Offset                    */
-/* Set ALL Offsets */
-#define SET_WF_OFFS(x0,x1,x2,x3) (SET_WF0_OFF((x0))|SET_WF1_OFF((x1))|SET_WF2_OFF((x2))|SET_WF3_OFF((x3)))
-
-/* EMAC_WKUP_FFCRC0 Masks */
-
-#define WF0_CRC           0x0000FFFF    /* Wake-Up Filter 0 Pattern CRC                           */
-#define WF1_CRC           0xFFFF0000    /* Wake-Up Filter 1 Pattern CRC                           */
-
-#define SET_WF0_CRC(x) (((x)&0xFFFF)<<   0 ) /* Set Wake-Up Filter 0 Target CRC                   */
-#define SET_WF1_CRC(x) (((x)&0xFFFF)<<  16 ) /* Set Wake-Up Filter 1 Target CRC                   */
-
-/* EMAC_WKUP_FFCRC1 Masks */
-
-#define WF2_CRC           0x0000FFFF    /* Wake-Up Filter 2 Pattern CRC                           */
-#define WF3_CRC           0xFFFF0000    /* Wake-Up Filter 3 Pattern CRC                           */
-
-#define SET_WF2_CRC(x) (((x)&0xFFFF)<<   0 ) /* Set Wake-Up Filter 2 Target CRC                   */
-#define SET_WF3_CRC(x) (((x)&0xFFFF)<<  16 ) /* Set Wake-Up Filter 3 Target CRC                   */
-
-/* EMAC_SYSCTL Masks */
-
-#define PHYIE             0x00000001    /* PHY_INT Interrupt Enable                               */
-#define RXDWA             0x00000002    /* Receive Frame DMA Word Alignment (Odd/Even*)           */
-#define RXCKS             0x00000004    /* Enable RX Frame TCP/UDP Checksum Computation           */
-#define TXDWA             0x00000010    /* Transmit Frame DMA Word Alignment (Odd/Even*)          */
-#define MDCDIV            0x00003F00    /* SCLK:MDC Clock Divisor [MDC=SCLK/(2*(N+1))]            */
-
-#define SET_MDCDIV(x) (((x)&0x3F)<< 8)   /* Set MDC Clock Divisor                                 */
-
-/* EMAC_SYSTAT Masks */
-
-#define PHYINT            0x00000001    /* PHY_INT Interrupt Status                               */
-#define MMCINT            0x00000002    /* MMC Counter Interrupt Status                           */
-#define RXFSINT           0x00000004    /* RX Frame-Status Interrupt Status                       */
-#define TXFSINT           0x00000008    /* TX Frame-Status Interrupt Status                       */
-#define WAKEDET           0x00000010    /* Wake-Up Detected Status                                */
-#define RXDMAERR          0x00000020    /* RX DMA Direction Error Status                          */
-#define TXDMAERR          0x00000040    /* TX DMA Direction Error Status                          */
-#define STMDONE           0x00000080    /* Station Mgt. Transfer Done Interrupt Status            */
-
-/* EMAC_RX_STAT, EMAC_RX_STKY, and EMAC_RX_IRQE Masks */
-
-#define RX_FRLEN          0x000007FF    /* Frame Length In Bytes                                  */
-#define RX_COMP           0x00001000    /* RX Frame Complete                                      */
-#define RX_OK             0x00002000    /* RX Frame Received With No Errors                       */
-#define RX_LONG           0x00004000    /* RX Frame Too Long Error                                */
-#define RX_ALIGN          0x00008000    /* RX Frame Alignment Error                               */
-#define RX_CRC            0x00010000    /* RX Frame CRC Error                                     */
-#define RX_LEN            0x00020000    /* RX Frame Length Error                                  */
-#define RX_FRAG           0x00040000    /* RX Frame Fragment Error                                */
-#define RX_ADDR           0x00080000    /* RX Frame Address Filter Failed Error                   */
-#define RX_DMAO           0x00100000    /* RX Frame DMA Overrun Error                             */
-#define RX_PHY            0x00200000    /* RX Frame PHY Error                                     */
-#define RX_LATE           0x00400000    /* RX Frame Late Collision Error                          */
-#define RX_RANGE          0x00800000    /* RX Frame Length Field Out of Range Error               */
-#define RX_MULTI          0x01000000    /* RX Multicast Frame Indicator                           */
-#define RX_BROAD          0x02000000    /* RX Broadcast Frame Indicator                           */
-#define RX_CTL            0x04000000    /* RX Control Frame Indicator                             */
-#define RX_UCTL           0x08000000    /* Unsupported RX Control Frame Indicator                 */
-#define RX_TYPE           0x10000000    /* RX Typed Frame Indicator                               */
-#define RX_VLAN1          0x20000000    /* RX VLAN1 Frame Indicator                               */
-#define RX_VLAN2          0x40000000    /* RX VLAN2 Frame Indicator                               */
-#define RX_ACCEPT         0x80000000    /* RX Frame Accepted Indicator                            */
-
-/*  EMAC_TX_STAT, EMAC_TX_STKY, and EMAC_TX_IRQE Masks  */
-
-#define TX_COMP           0x00000001    /* TX Frame Complete                                      */
-#define TX_OK             0x00000002    /* TX Frame Sent With No Errors                           */
-#define TX_ECOLL          0x00000004    /* TX Frame Excessive Collision Error                     */
-#define TX_LATE           0x00000008    /* TX Frame Late Collision Error                          */
-#define TX_DMAU           0x00000010    /* TX Frame DMA Underrun Error (STAT)                     */
-#define TX_MACE           0x00000010    /* Internal MAC Error Detected (STKY and IRQE)            */
-#define TX_EDEFER         0x00000020    /* TX Frame Excessive Deferral Error                      */
-#define TX_BROAD          0x00000040    /* TX Broadcast Frame Indicator                           */
-#define TX_MULTI          0x00000080    /* TX Multicast Frame Indicator                           */
-#define TX_CCNT           0x00000F00    /* TX Frame Collision Count                               */
-#define TX_DEFER          0x00001000    /* TX Frame Deferred Indicator                            */
-#define TX_CRS            0x00002000    /* TX Frame Carrier Sense Not Asserted Error              */
-#define TX_LOSS           0x00004000    /* TX Frame Carrier Lost During TX Error                  */
-#define TX_RETRY          0x00008000    /* TX Frame Successful After Retry                        */
-#define TX_FRLEN          0x07FF0000    /* TX Frame Length (Bytes)                                */
-
-/* EMAC_MMC_CTL Masks */
-#define RSTC              0x00000001    /* Reset All Counters                                     */
-#define CROLL             0x00000002    /* Counter Roll-Over Enable                               */
-#define CCOR              0x00000004    /* Counter Clear-On-Read Mode Enable                      */
-#define MMCE              0x00000008    /* Enable MMC Counter Operation                           */
-
-/* EMAC_MMC_RIRQS and EMAC_MMC_RIRQE Masks */
-#define RX_OK_CNT         0x00000001    /* RX Frames Received With No Errors                      */
-#define RX_FCS_CNT        0x00000002    /* RX Frames W/Frame Check Sequence Errors                */
-#define RX_ALIGN_CNT      0x00000004    /* RX Frames With Alignment Errors                        */
-#define RX_OCTET_CNT      0x00000008    /* RX Octets Received OK                                  */
-#define RX_LOST_CNT       0x00000010    /* RX Frames Lost Due To Internal MAC RX Error            */
-#define RX_UNI_CNT        0x00000020    /* Unicast RX Frames Received OK                          */
-#define RX_MULTI_CNT      0x00000040    /* Multicast RX Frames Received OK                        */
-#define RX_BROAD_CNT      0x00000080    /* Broadcast RX Frames Received OK                        */
-#define RX_IRL_CNT        0x00000100    /* RX Frames With In-Range Length Errors                  */
-#define RX_ORL_CNT        0x00000200    /* RX Frames With Out-Of-Range Length Errors              */
-#define RX_LONG_CNT       0x00000400    /* RX Frames With Frame Too Long Errors                   */
-#define RX_MACCTL_CNT     0x00000800    /* MAC Control RX Frames Received                         */
-#define RX_OPCODE_CTL     0x00001000    /* Unsupported Op-Code RX Frames Received                 */
-#define RX_PAUSE_CNT      0x00002000    /* PAUSEMAC Control RX Frames Received                    */
-#define RX_ALLF_CNT       0x00004000    /* All RX Frames Received                                 */
-#define RX_ALLO_CNT       0x00008000    /* All RX Octets Received                                 */
-#define RX_TYPED_CNT      0x00010000    /* Typed RX Frames Received                               */
-#define RX_SHORT_CNT      0x00020000    /* RX Frame Fragments (< 64 Bytes) Received               */
-#define RX_EQ64_CNT       0x00040000    /* 64-Byte RX Frames Received                             */
-#define RX_LT128_CNT      0x00080000    /* 65-127-Byte RX Frames Received                         */
-#define RX_LT256_CNT      0x00100000    /* 128-255-Byte RX Frames Received                        */
-#define RX_LT512_CNT      0x00200000    /* 256-511-Byte RX Frames Received                        */
-#define RX_LT1024_CNT     0x00400000    /* 512-1023-Byte RX Frames Received                       */
-#define RX_GE1024_CNT     0x00800000    /* 1024-Max-Byte RX Frames Received                       */
-
-/* EMAC_MMC_TIRQS and EMAC_MMC_TIRQE Masks  */
-
-#define TX_OK_CNT         0x00000001    /* TX Frames Sent OK                                      */
-#define TX_SCOLL_CNT      0x00000002    /* TX Frames With Single Collisions                       */
-#define TX_MCOLL_CNT      0x00000004    /* TX Frames With Multiple Collisions                     */
-#define TX_OCTET_CNT      0x00000008    /* TX Octets Sent OK                                      */
-#define TX_DEFER_CNT      0x00000010    /* TX Frames With Deferred Transmission                   */
-#define TX_LATE_CNT       0x00000020    /* TX Frames With Late Collisions                         */
-#define TX_ABORTC_CNT     0x00000040    /* TX Frames Aborted Due To Excess Collisions             */
-#define TX_LOST_CNT       0x00000080    /* TX Frames Lost Due To Internal MAC TX Error            */
-#define TX_CRS_CNT        0x00000100    /* TX Frames With Carrier Sense Errors                    */
-#define TX_UNI_CNT        0x00000200    /* Unicast TX Frames Sent                                 */
-#define TX_MULTI_CNT      0x00000400    /* Multicast TX Frames Sent                               */
-#define TX_BROAD_CNT      0x00000800    /* Broadcast TX Frames Sent                               */
-#define TX_EXDEF_CTL      0x00001000    /* TX Frames With Excessive Deferral                      */
-#define TX_MACCTL_CNT     0x00002000    /* MAC Control TX Frames Sent                             */
-#define TX_ALLF_CNT       0x00004000    /* All TX Frames Sent                                     */
-#define TX_ALLO_CNT       0x00008000    /* All TX Octets Sent                                     */
-#define TX_EQ64_CNT       0x00010000    /* 64-Byte TX Frames Sent                                 */
-#define TX_LT128_CNT      0x00020000    /* 65-127-Byte TX Frames Sent                             */
-#define TX_LT256_CNT      0x00040000    /* 128-255-Byte TX Frames Sent                            */
-#define TX_LT512_CNT      0x00080000    /* 256-511-Byte TX Frames Sent                            */
-#define TX_LT1024_CNT     0x00100000    /* 512-1023-Byte TX Frames Sent                           */
-#define TX_GE1024_CNT     0x00200000    /* 1024-Max-Byte TX Frames Sent                           */
-#define TX_ABORT_CNT      0x00400000    /* TX Frames Aborted                                      */
-
-/* SDH Registers */
-
-#define SDH_PWR_CTL                    0xFFC03900 /* SDH Power Control */
-#define SDH_CLK_CTL                    0xFFC03904 /* SDH Clock Control */
-#define SDH_ARGUMENT                   0xFFC03908 /* SDH Argument */
-#define SDH_COMMAND                    0xFFC0390C /* SDH Command */
-#define SDH_RESP_CMD                   0xFFC03910 /* SDH Response Command */
-#define SDH_RESPONSE0                  0xFFC03914 /* SDH Response0 */
-#define SDH_RESPONSE1                  0xFFC03918 /* SDH Response1 */
-#define SDH_RESPONSE2                  0xFFC0391C /* SDH Response2 */
-#define SDH_RESPONSE3                  0xFFC03920 /* SDH Response3 */
-#define SDH_DATA_TIMER                 0xFFC03924 /* SDH Data Timer */
-#define SDH_DATA_LGTH                  0xFFC03928 /* SDH Data Length */
-#define SDH_DATA_CTL                   0xFFC0392C /* SDH Data Control */
-#define SDH_DATA_CNT                   0xFFC03930 /* SDH Data Counter */
-#define SDH_STATUS                     0xFFC03934 /* SDH Status */
-#define SDH_STATUS_CLR                 0xFFC03938 /* SDH Status Clear */
-#define SDH_MASK0                      0xFFC0393C /* SDH Interrupt0 Mask */
-#define SDH_MASK1                      0xFFC03940 /* SDH Interrupt1 Mask */
-#define SDH_FIFO_CNT                   0xFFC03948 /* SDH FIFO Counter */
-#define SDH_FIFO                       0xFFC03980 /* SDH Data FIFO */
-#define SDH_E_STATUS                   0xFFC039C0 /* SDH Exception Status */
-#define SDH_E_MASK                     0xFFC039C4 /* SDH Exception Mask */
-#define SDH_CFG                        0xFFC039C8 /* SDH Configuration */
-#define SDH_RD_WAIT_EN                 0xFFC039CC /* SDH Read Wait Enable */
-#define SDH_PID0                       0xFFC039D0 /* SDH Peripheral Identification0 */
-#define SDH_PID1                       0xFFC039D4 /* SDH Peripheral Identification1 */
-#define SDH_PID2                       0xFFC039D8 /* SDH Peripheral Identification2 */
-#define SDH_PID3                       0xFFC039DC /* SDH Peripheral Identification3 */
-#define SDH_PID4                       0xFFC039E0 /* SDH Peripheral Identification4 */
-#define SDH_PID5                       0xFFC039E4 /* SDH Peripheral Identification5 */
-#define SDH_PID6                       0xFFC039E8 /* SDH Peripheral Identification6 */
-#define SDH_PID7                       0xFFC039EC /* SDH Peripheral Identification7 */
-
-/* Removable Storage Interface Registers */
-
-#define RSI_PWR_CONTROL                0xFFC03800 /* RSI Power Control Register */
-#define RSI_CLK_CONTROL                0xFFC03804 /* RSI Clock Control Register */
-#define RSI_ARGUMENT                   0xFFC03808 /* RSI Argument Register */
-#define RSI_COMMAND                    0xFFC0380C /* RSI Command Register */
-#define RSI_RESP_CMD                   0xFFC03810 /* RSI Response Command Register */
-#define RSI_RESPONSE0                  0xFFC03814 /* RSI Response Register */
-#define RSI_RESPONSE1                  0xFFC03818 /* RSI Response Register */
-#define RSI_RESPONSE2                  0xFFC0381C /* RSI Response Register */
-#define RSI_RESPONSE3                  0xFFC03820 /* RSI Response Register */
-#define RSI_DATA_TIMER                 0xFFC03824 /* RSI Data Timer Register */
-#define RSI_DATA_LGTH                  0xFFC03828 /* RSI Data Length Register */
-#define RSI_DATA_CONTROL               0xFFC0382C /* RSI Data Control Register */
-#define RSI_DATA_CNT                   0xFFC03830 /* RSI Data Counter Register */
-#define RSI_STATUS                     0xFFC03834 /* RSI Status Register */
-#define RSI_STATUSCL                   0xFFC03838 /* RSI Status Clear Register */
-#define RSI_MASK0                      0xFFC0383C /* RSI Interrupt 0 Mask Register */
-#define RSI_MASK1                      0xFFC03840 /* RSI Interrupt 1 Mask Register */
-#define RSI_FIFO_CNT                   0xFFC03848 /* RSI FIFO Counter Register */
-#define RSI_CEATA_CONTROL              0xFFC0384C /* RSI CEATA Register */
-#define RSI_FIFO                       0xFFC03880 /* RSI Data FIFO Register */
-#define RSI_ESTAT                      0xFFC038C0 /* RSI Exception Status Register */
-#define RSI_EMASK                      0xFFC038C4 /* RSI Exception Mask Register */
-#define RSI_CONFIG                     0xFFC038C8 /* RSI Configuration Register */
-#define RSI_RD_WAIT_EN                 0xFFC038CC /* RSI Read Wait Enable Register */
-#define RSI_PID0                       0xFFC03FE0 /* RSI Peripheral ID Register 0 */
-#define RSI_PID1                       0xFFC03FE4 /* RSI Peripheral ID Register 1 */
-#define RSI_PID2                       0xFFC03FE8 /* RSI Peripheral ID Register 2 */
-#define RSI_PID3                       0xFFC03FEC /* RSI Peripheral ID Register 3 */
-#define RSI_PID4                       0xFFC03FF0 /* RSI Peripheral ID Register 4 */
-#define RSI_PID5                       0xFFC03FF4 /* RSI Peripheral ID Register 5 */
-#define RSI_PID6                       0xFFC03FF8 /* RSI Peripheral ID Register 6 */
-#define RSI_PID7                       0xFFC03FFC /* RSI Peripheral ID Register 7 */
+/* BF518 is BF516 + IEEE-1588 */
+#include "defBF516.h"
 
 /* PTP TSYNC Registers */
 
@@ -489,141 +36,6 @@
 #define EMAC_PTP_PPS_STARTHI           0xFFC030F4 /* PPS Start Time High */
 #define EMAC_PTP_PPS_PERIOD            0xFFC030F8 /* PPS Count Register */
 
-/* ********************************************************** */
-/*     SINGLE BIT MACRO PAIRS (bit mask and negated one)      */
-/*     and MULTI BIT READ MACROS                              */
-/* ********************************************************** */
-
-/* Bit masks for SDH_COMMAND */
-
-#define                   CMD_IDX  0x3f       /* Command Index */
-#define                   CMD_RSP  0x40       /* Response */
-#define                 CMD_L_RSP  0x80       /* Long Response */
-#define                 CMD_INT_E  0x100      /* Command Interrupt */
-#define                CMD_PEND_E  0x200      /* Command Pending */
-#define                     CMD_E  0x400      /* Command Enable */
-
-/* Bit masks for SDH_PWR_CTL */
-
-#define                    PWR_ON  0x3        /* Power On */
-#if 0
-#define                       TBD  0x3c       /* TBD */
-#endif
-#define                 SD_CMD_OD  0x40       /* Open Drain Output */
-#define                   ROD_CTL  0x80       /* Rod Control */
-
-/* Bit masks for SDH_CLK_CTL */
-
-#define                    CLKDIV  0xff       /* MC_CLK Divisor */
-#define                     CLK_E  0x100      /* MC_CLK Bus Clock Enable */
-#define                  PWR_SV_E  0x200      /* Power Save Enable */
-#define             CLKDIV_BYPASS  0x400      /* Bypass Divisor */
-#define                  WIDE_BUS  0x800      /* Wide Bus Mode Enable */
-
-/* Bit masks for SDH_RESP_CMD */
-
-#define                  RESP_CMD  0x3f       /* Response Command */
-
-/* Bit masks for SDH_DATA_CTL */
-
-#define                     DTX_E  0x1        /* Data Transfer Enable */
-#define                   DTX_DIR  0x2        /* Data Transfer Direction */
-#define                  DTX_MODE  0x4        /* Data Transfer Mode */
-#define                 DTX_DMA_E  0x8        /* Data Transfer DMA Enable */
-#define              DTX_BLK_LGTH  0xf0       /* Data Transfer Block Length */
-
-/* Bit masks for SDH_STATUS */
-
-#define              CMD_CRC_FAIL  0x1        /* CMD CRC Fail */
-#define              DAT_CRC_FAIL  0x2        /* Data CRC Fail */
-#define               CMD_TIME_OUT  0x4        /* CMD Time Out */
-#define               DAT_TIME_OUT  0x8        /* Data Time Out */
-#define               TX_UNDERRUN  0x10       /* Transmit Underrun */
-#define                RX_OVERRUN  0x20       /* Receive Overrun */
-#define              CMD_RESP_END  0x40       /* CMD Response End */
-#define                  CMD_SENT  0x80       /* CMD Sent */
-#define                   DAT_END  0x100      /* Data End */
-#define             START_BIT_ERR  0x200      /* Start Bit Error */
-#define               DAT_BLK_END  0x400      /* Data Block End */
-#define                   CMD_ACT  0x800      /* CMD Active */
-#define                    TX_ACT  0x1000     /* Transmit Active */
-#define                    RX_ACT  0x2000     /* Receive Active */
-#define              TX_FIFO_STAT  0x4000     /* Transmit FIFO Status */
-#define              RX_FIFO_STAT  0x8000     /* Receive FIFO Status */
-#define              TX_FIFO_FULL  0x10000    /* Transmit FIFO Full */
-#define              RX_FIFO_FULL  0x20000    /* Receive FIFO Full */
-#define              TX_FIFO_ZERO  0x40000    /* Transmit FIFO Empty */
-#define               RX_DAT_ZERO  0x80000    /* Receive FIFO Empty */
-#define                TX_DAT_RDY  0x100000   /* Transmit Data Available */
-#define               RX_FIFO_RDY  0x200000   /* Receive Data Available */
-
-/* Bit masks for SDH_STATUS_CLR */
-
-#define         CMD_CRC_FAIL_STAT  0x1        /* CMD CRC Fail Status */
-#define         DAT_CRC_FAIL_STAT  0x2        /* Data CRC Fail Status */
-#define          CMD_TIMEOUT_STAT  0x4        /* CMD Time Out Status */
-#define          DAT_TIMEOUT_STAT  0x8        /* Data Time Out status */
-#define          TX_UNDERRUN_STAT  0x10       /* Transmit Underrun Status */
-#define           RX_OVERRUN_STAT  0x20       /* Receive Overrun Status */
-#define         CMD_RESP_END_STAT  0x40       /* CMD Response End Status */
-#define             CMD_SENT_STAT  0x80       /* CMD Sent Status */
-#define              DAT_END_STAT  0x100      /* Data End Status */
-#define        START_BIT_ERR_STAT  0x200      /* Start Bit Error Status */
-#define          DAT_BLK_END_STAT  0x400      /* Data Block End Status */
-
-/* Bit masks for SDH_MASK0 */
-
-#define         CMD_CRC_FAIL_MASK  0x1        /* CMD CRC Fail Mask */
-#define         DAT_CRC_FAIL_MASK  0x2        /* Data CRC Fail Mask */
-#define          CMD_TIMEOUT_MASK  0x4        /* CMD Time Out Mask */
-#define          DAT_TIMEOUT_MASK  0x8        /* Data Time Out Mask */
-#define          TX_UNDERRUN_MASK  0x10       /* Transmit Underrun Mask */
-#define           RX_OVERRUN_MASK  0x20       /* Receive Overrun Mask */
-#define         CMD_RESP_END_MASK  0x40       /* CMD Response End Mask */
-#define             CMD_SENT_MASK  0x80       /* CMD Sent Mask */
-#define              DAT_END_MASK  0x100      /* Data End Mask */
-#define        START_BIT_ERR_MASK  0x200      /* Start Bit Error Mask */
-#define          DAT_BLK_END_MASK  0x400      /* Data Block End Mask */
-#define              CMD_ACT_MASK  0x800      /* CMD Active Mask */
-#define               TX_ACT_MASK  0x1000     /* Transmit Active Mask */
-#define               RX_ACT_MASK  0x2000     /* Receive Active Mask */
-#define         TX_FIFO_STAT_MASK  0x4000     /* Transmit FIFO Status Mask */
-#define         RX_FIFO_STAT_MASK  0x8000     /* Receive FIFO Status Mask */
-#define         TX_FIFO_FULL_MASK  0x10000    /* Transmit FIFO Full Mask */
-#define         RX_FIFO_FULL_MASK  0x20000    /* Receive FIFO Full Mask */
-#define         TX_FIFO_ZERO_MASK  0x40000    /* Transmit FIFO Empty Mask */
-#define          RX_DAT_ZERO_MASK  0x80000    /* Receive FIFO Empty Mask */
-#define           TX_DAT_RDY_MASK  0x100000   /* Transmit Data Available Mask */
-#define          RX_FIFO_RDY_MASK  0x200000   /* Receive Data Available Mask */
-
-/* Bit masks for SDH_FIFO_CNT */
-
-#define                FIFO_COUNT  0x7fff     /* FIFO Count */
-
-/* Bit masks for SDH_E_STATUS */
-
-#define              SDIO_INT_DET  0x2        /* SDIO Int Detected */
-#define               SD_CARD_DET  0x10       /* SD Card Detect */
-
-/* Bit masks for SDH_E_MASK */
-
-#define                  SDIO_MSK  0x2        /* Mask SDIO Int Detected */
-#define                   SCD_MSK  0x40       /* Mask Card Detect */
-
-/* Bit masks for SDH_CFG */
-
-#define                   CLKS_EN  0x1        /* Clocks Enable */
-#define                      SD4E  0x4        /* SDIO 4-Bit Enable */
-#define                       MWE  0x8        /* Moving Window Enable */
-#define                    SD_RST  0x10       /* SDMMC Reset */
-#define                 PUP_SDDAT  0x20       /* Pull-up SD_DAT */
-#define                PUP_SDDAT3  0x40       /* Pull-up SD_DAT3 */
-#define                 PD_SDDAT3  0x80       /* Pull-down SD_DAT3 */
-
-/* Bit masks for SDH_RD_WAIT_EN */
-
-#define                       RWR  0x1        /* Read Wait Request */
-
 /* Bit masks for EMAC_PTP_CTL */
 
 #define                    PTP_EN  0x1        /* Enable the PTP_TSYNC module */
diff --git a/arch/blackfin/mach-bf518/include/mach/defBF51x_base.h b/arch/blackfin/mach-bf518/include/mach/defBF51x_base.h
index f9fd2b2a2956..9241205fb992 100644
--- a/arch/blackfin/mach-bf518/include/mach/defBF51x_base.h
+++ b/arch/blackfin/mach-bf518/include/mach/defBF51x_base.h
@@ -585,58 +585,6 @@
 **                              modifier UNLESS the lower order bits are saved and ORed back in when
 **                              the macro is used.
 *************************************************************************************/
-/*
-** ********************* PLL AND RESET MASKS ****************************************/
-/* PLL_CTL Masks                                                                                                                                        */
-#define DF                              0x0001  /* 0: PLL = CLKIN, 1: PLL = CLKIN/2                                     */
-#define PLL_OFF                 0x0002  /* PLL Not Powered                                                                      */
-#define STOPCK                  0x0008  /* Core Clock Off                                                                       */
-#define PDWN                    0x0020  /* Enter Deep Sleep Mode                                                        */
-#define IN_DELAY                0x0040  /* Add 200ps Delay To EBIU Input Latches                        */
-#define OUT_DELAY               0x0080  /* Add 200ps Delay To EBIU Output Signals                       */
-#define BYPASS                  0x0100  /* Bypass the PLL                                                                       */
-#define MSEL                    0x7E00  /* Multiplier Select For CCLK/VCO Factors                       */
-/* PLL_CTL Macros (Only Use With Logic OR While Setting Lower Order Bits)                       */
-#define SET_MSEL(x)             (((x)&0x3F) << 0x9)     /* Set MSEL = 0-63 --> VCO = CLKIN*MSEL         */
-
-/* PLL_DIV Masks                                                                                                                */
-#define SSEL                    0x000F  /* System Select                                                */
-#define CSEL                    0x0030  /* Core Select                                                  */
-#define CSEL_DIV1               0x0000  /*              CCLK = VCO / 1                                  */
-#define CSEL_DIV2               0x0010  /*              CCLK = VCO / 2                                  */
-#define CSEL_DIV4               0x0020  /*              CCLK = VCO / 4                                  */
-#define CSEL_DIV8               0x0030  /*              CCLK = VCO / 8                                  */
-/* PLL_DIV Macros                                                                                                               */
-#define SET_SSEL(x)             ((x)&0xF)               /* Set SSEL = 0-15 --> SCLK = VCO/SSEL  */
-
-/* VR_CTL Masks */
-#define FREQ                    0x3000  /* Switching Oscillator Frequency For Regulator */
-#define HIBERNATE               0x0000  /*              Powerdown/Bypass On-Board Regulation    */
-
-#define VLEV                    0x00F0  /* Internal Voltage Level                                       */
-#define VLEV_085                0x0060  /*              VLEV = 0.85 V (-5% - +10% Accuracy)     */
-#define VLEV_090                0x0070  /*              VLEV = 0.90 V (-5% - +10% Accuracy)     */
-#define VLEV_095                0x0080  /*              VLEV = 0.95 V (-5% - +10% Accuracy)     */
-#define VLEV_100                0x0090  /*              VLEV = 1.00 V (-5% - +10% Accuracy)     */
-#define VLEV_105                0x00A0  /*              VLEV = 1.05 V (-5% - +10% Accuracy)     */
-#define VLEV_110                0x00B0  /*              VLEV = 1.10 V (-5% - +10% Accuracy)     */
-#define VLEV_115                0x00C0  /*              VLEV = 1.15 V (-5% - +10% Accuracy)     */
-#define VLEV_120                0x00D0  /*              VLEV = 1.20 V (-5% - +10% Accuracy)     */
-#define VLEV_125                0x00E0  /*              VLEV = 1.25 V (-5% - +10% Accuracy)     */
-#define VLEV_130                0x00F0  /*              VLEV = 1.30 V (-5% - +10% Accuracy)     */
-
-#define WAKE                    0x0100  /* Enable RTC/Reset Wakeup From Hibernate       */
-#define USBWE                   0x0200  /* Enable USB Wakeup From Hibernate                     */
-#define PHYWE                   0x0400  /* Enable PHY Wakeup From Hibernate                     */
-#define CLKBUFOE                0x4000  /* CLKIN Buffer Output Enable */
-#define PHYCLKOE                CLKBUFOE        /* Alternative legacy name for the above */
-#define SCKELOW         0x8000  /* Enable Drive CKE Low During Reset            */
-
-/* PLL_STAT Masks                                                                                                                                       */
-#define ACTIVE_PLLENABLED       0x0001  /* Processor In Active Mode With PLL Enabled    */
-#define FULL_ON                         0x0002  /* Processor In Full On Mode                                    */
-#define ACTIVE_PLLDISABLED      0x0004  /* Processor In Active Mode With PLL Disabled   */
-#define PLL_LOCKED                      0x0020  /* PLL_LOCKCNT Has Been Reached                                 */
 
 /* CHIPID Masks */
 #define CHIPID_VERSION         0xF0000000
@@ -756,66 +704,6 @@
 #define IWR_DISABLE(x)  (0xFFFFFFFF ^ (1 << ((x)&0x1F)))        /* Wakeup Disable Peripheral #x         */
 
 
-/* ********* WATCHDOG TIMER MASKS ******************** */
-
-/* Watchdog Timer WDOG_CTL Register Masks */
-
-#define WDEV(x) (((x)<<1) & 0x0006) /* event generated on roll over */
-#define WDEV_RESET 0x0000 /* generate reset event on roll over */
-#define WDEV_NMI 0x0002 /* generate NMI event on roll over */
-#define WDEV_GPI 0x0004 /* generate GP IRQ on roll over */
-#define WDEV_NONE 0x0006 /* no event on roll over */
-#define WDEN 0x0FF0 /* enable watchdog */
-#define WDDIS 0x0AD0 /* disable watchdog */
-#define WDRO 0x8000 /* watchdog rolled over latch */
-
-/* depreciated WDOG_CTL Register Masks for legacy code */
-
-
-#define ICTL WDEV
-#define ENABLE_RESET WDEV_RESET
-#define WDOG_RESET WDEV_RESET
-#define ENABLE_NMI WDEV_NMI
-#define WDOG_NMI WDEV_NMI
-#define ENABLE_GPI WDEV_GPI
-#define WDOG_GPI WDEV_GPI
-#define DISABLE_EVT WDEV_NONE
-#define WDOG_NONE WDEV_NONE
-
-#define TMR_EN WDEN
-#define TMR_DIS WDDIS
-#define TRO WDRO
-#define ICTL_P0 0x01
- #define ICTL_P1 0x02
-#define TRO_P 0x0F
-
-
-
-/* ***************  REAL TIME CLOCK MASKS  **************************/
-/* RTC_STAT and RTC_ALARM Masks                                                                         */
-#define RTC_SEC                         0x0000003F      /* Real-Time Clock Seconds      */
-#define RTC_MIN                         0x00000FC0      /* Real-Time Clock Minutes      */
-#define RTC_HR                          0x0001F000      /* Real-Time Clock Hours        */
-#define RTC_DAY                         0xFFFE0000      /* Real-Time Clock Days         */
-
-/* RTC_ALARM Macro                      z=day           y=hr    x=min   w=sec           */
-#define SET_ALARM(z,y,x,w)      ((((z)&0x7FFF)<<0x11)|(((y)&0x1F)<<0xC)|(((x)&0x3F)<<0x6)|((w)&0x3F))
-
-/* RTC_ICTL and RTC_ISTAT Masks                                                                                                                                         */
-#define STOPWATCH                       0x0001          /* Stopwatch Interrupt Enable                                                           */
-#define ALARM                           0x0002          /* Alarm Interrupt Enable                                                                       */
-#define SECOND                          0x0004          /* Seconds (1 Hz) Interrupt Enable                                                      */
-#define MINUTE                          0x0008          /* Minutes Interrupt Enable                                                                     */
-#define HOUR                            0x0010          /* Hours Interrupt Enable                                                                       */
-#define DAY                                     0x0020          /* 24 Hours (Days) Interrupt Enable                                                     */
-#define DAY_ALARM                       0x0040          /* Day Alarm (Day, Hour, Minute, Second) Interrupt Enable       */
-#define WRITE_PENDING           0x4000          /* Write Pending Status                                                                         */
-#define WRITE_COMPLETE          0x8000          /* Write Complete Interrupt Enable                                                      */
-
-/* RTC_FAST / RTC_PREN Mask                                                                                             */
-#define PREN                            0x0001  /* Enable Prescaler, RTC Runs @1 Hz     */
-
-
 /* ************** UART CONTROLLER MASKS *************************/
 /* UARTx_LCR Masks                                                                                              */
 #define WLS(x)          (((x)-5) & 0x03)        /* Word Length Select */
@@ -1372,33 +1260,6 @@
 
 
 /* **************************  DMA CONTROLLER MASKS  ********************************/
-/* DMAx_CONFIG, MDMA_yy_CONFIG Masks                                                                                            */
-#define DMAEN                   0x0001          /* DMA Channel Enable                                                   */
-#define WNR                             0x0002          /* Channel Direction (W/R*)                                             */
-#define WDSIZE_8                0x0000          /* Transfer Word Size = 8                                               */
-#define WDSIZE_16               0x0004          /* Transfer Word Size = 16                                              */
-#define WDSIZE_32               0x0008          /* Transfer Word Size = 32                                              */
-#define DMA2D                   0x0010          /* DMA Mode (2D/1D*)                                                    */
-#define RESTART                 0x0020          /* DMA Buffer Clear                                                             */
-#define DI_SEL                  0x0040          /* Data Interrupt Timing Select                                 */
-#define DI_EN                   0x0080          /* Data Interrupt Enable                                                */
-#define NDSIZE_0                0x0000          /* Next Descriptor Size = 0 (Stop/Autobuffer)   */
-#define NDSIZE_1                0x0100          /* Next Descriptor Size = 1                                             */
-#define NDSIZE_2                0x0200          /* Next Descriptor Size = 2                                             */
-#define NDSIZE_3                0x0300          /* Next Descriptor Size = 3                                             */
-#define NDSIZE_4                0x0400          /* Next Descriptor Size = 4                                             */
-#define NDSIZE_5                0x0500          /* Next Descriptor Size = 5                                             */
-#define NDSIZE_6                0x0600          /* Next Descriptor Size = 6                                             */
-#define NDSIZE_7                0x0700          /* Next Descriptor Size = 7                                             */
-#define NDSIZE_8                0x0800          /* Next Descriptor Size = 8                                             */
-#define NDSIZE_9                0x0900          /* Next Descriptor Size = 9                                             */
-#define NDSIZE                  0x0900  /* Next Descriptor Size */
-#define DMAFLOW                 0x7000  /* Flow Control */
-#define DMAFLOW_STOP            0x0000          /* Stop Mode                                                                    */
-#define DMAFLOW_AUTO            0x1000          /* Autobuffer Mode                                                              */
-#define DMAFLOW_ARRAY           0x4000          /* Descriptor Array Mode                                                */
-#define DMAFLOW_SMALL           0x6000          /* Small Model Descriptor List Mode                             */
-#define DMAFLOW_LARGE           0x7000          /* Large Model Descriptor List Mode                             */
 
 /* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP Masks                                                            */
 #define CTYPE                   0x0040  /* DMA Channel Type Indicator (Memory/Peripheral*)      */
@@ -1416,13 +1277,6 @@
 #define PMAP_UART1RX    0xA000  /*              UART1 Port Receive DMA                                          */
 #define PMAP_UART1TX    0xB000  /*              UART1 Port Transmit DMA                                         */
 
-/* DMAx_IRQ_STATUS, MDMA_yy_IRQ_STATUS Masks                                            */
-#define DMA_DONE                0x0001  /* DMA Completion Interrupt Status      */
-#define DMA_ERR                 0x0002  /* DMA Error Interrupt Status           */
-#define DFETCH                  0x0004  /* DMA Descriptor Fetch Indicator       */
-#define DMA_RUN                 0x0008  /* DMA Channel Running Indicator        */
-
-
 /*  ************  PARALLEL PERIPHERAL INTERFACE (PPI) MASKS *************/
 /*  PPI_CONTROL Masks                                                                                                   */
 #define PORT_EN                 0x0001          /* PPI Port Enable                                      */
@@ -1830,46 +1684,6 @@
 #define BNDMODE_CAPT     0x2000  /* boundary capture mode */
 #define BNDMODE_AEXT     0x3000  /* boundary auto-extend mode */
 
-/* Bit masks for OTP_CONTROL */
-
-#define                FUSE_FADDR  0x1ff      /* OTP/Fuse Address */
-#define                      FIEN  0x800      /* OTP/Fuse Interrupt Enable */
-#define                     nFIEN  0x0
-#define                  FTESTDEC  0x1000     /* OTP/Fuse Test Decoder */
-#define                 nFTESTDEC  0x0
-#define                   FWRTEST  0x2000     /* OTP/Fuse Write Test */
-#define                  nFWRTEST  0x0
-#define                     FRDEN  0x4000     /* OTP/Fuse Read Enable */
-#define                    nFRDEN  0x0
-#define                     FWREN  0x8000     /* OTP/Fuse Write Enable */
-#define                    nFWREN  0x0
-
-/* Bit masks for OTP_BEN */
-
-#define                      FBEN  0xffff     /* OTP/Fuse Byte Enable */
-
-/* Bit masks for OTP_STATUS */
-
-#define                     FCOMP  0x1        /* OTP/Fuse Access Complete */
-#define                    nFCOMP  0x0
-#define                    FERROR  0x2        /* OTP/Fuse Access Error */
-#define                   nFERROR  0x0
-#define                  MMRGLOAD  0x10       /* Memory Mapped Register Gasket Load */
-#define                 nMMRGLOAD  0x0
-#define                  MMRGLOCK  0x20       /* Memory Mapped Register Gasket Lock */
-#define                 nMMRGLOCK  0x0
-#define                    FPGMEN  0x40       /* OTP/Fuse Program Enable */
-#define                   nFPGMEN  0x0
-
-/* Bit masks for OTP_TIMING */
-
-#define                   USECDIV  0xff       /* Micro Second Divider */
-#define                   READACC  0x7f00     /* Read Access Time */
-#define                   CPUMPRL  0x38000    /* Charge Pump Release Time */
-#define                   CPUMPSU  0xc0000    /* Charge Pump Setup Time */
-#define                   CPUMPHD  0xf00000   /* Charge Pump Hold Time */
-#define                   PGMTIME  0xff000000 /* Program Time */
-
 /* Bit masks for SECURE_SYSSWT */
 
 #define                   EMUDABL  0x1        /* Emulation Disable. */
diff --git a/arch/blackfin/mach-bf527/Kconfig b/arch/blackfin/mach-bf527/Kconfig
index 848ac6f86823..1f8cbe9d6b9a 100644
--- a/arch/blackfin/mach-bf527/Kconfig
+++ b/arch/blackfin/mach-bf527/Kconfig
@@ -1,3 +1,7 @@
+config BF52x
+        def_bool y
+        depends on (BF522 || BF523 || BF524 || BF525 || BF526 || BF527)
+
 if (BF52x)
 
 source "arch/blackfin/mach-bf527/boards/Kconfig"
diff --git a/arch/blackfin/mach-bf527/boards/cm_bf527.c b/arch/blackfin/mach-bf527/boards/cm_bf527.c
index f1996b13a3da..7ab0800e2914 100644
--- a/arch/blackfin/mach-bf527/boards/cm_bf527.c
+++ b/arch/blackfin/mach-bf527/boards/cm_bf527.c
@@ -15,9 +15,6 @@
 #include <linux/spi/spi.h>
 #include <linux/spi/flash.h>
 #include <linux/etherdevice.h>
-#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
-#include <linux/usb/isp1362.h>
-#endif
 #include <linux/i2c.h>
 #include <linux/irq.h>
 #include <linux/interrupt.h>
@@ -65,7 +62,7 @@ static struct isp1760_platform_data isp1760_priv = {
 };
 
 static struct platform_device bfin_isp1760_device = {
-        .name           = "isp1760-hcd",
+        .name           = "isp1760",
         .id             = 0,
         .dev = {
                 .platform_data = &isp1760_priv,
@@ -317,45 +314,6 @@ static struct platform_device sl811_hcd_device = {
 };
 #endif
 
-#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
-static struct resource isp1362_hcd_resources[] = {
-        {
-                .start = 0x20360000,
-                .end = 0x20360000,
-                .flags = IORESOURCE_MEM,
-        }, {
-                .start = 0x20360004,
-                .end = 0x20360004,
-                .flags = IORESOURCE_MEM,
-        }, {
-                .start = CONFIG_USB_ISP1362_BFIN_GPIO_IRQ,
-                .end = CONFIG_USB_ISP1362_BFIN_GPIO_IRQ,
-                .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
-        },
-};
-
-static struct isp1362_platform_data isp1362_priv = {
-        .sel15Kres = 1,
-        .clknotstop = 0,
-        .oc_enable = 0,
-        .int_act_high = 0,
-        .int_edge_triggered = 0,
-        .remote_wakeup_connected = 0,
-        .no_power_switching = 1,
-        .power_switching_mode = 0,
-};
-
-static struct platform_device isp1362_hcd_device = {
-        .name = "isp1362-hcd",
-        .id = 0,
-        .dev = {
-                .platform_data = &isp1362_priv,
-        },
-        .num_resources = ARRAY_SIZE(isp1362_hcd_resources),
-        .resource = isp1362_hcd_resources,
-};
-#endif
-
 #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
 static struct platform_device bfin_mii_bus = {
         .name = "bfin_mii_bus",
@@ -841,10 +799,6 @@ static struct platform_device *cmbf527_devices[] __initdata = {
         &sl811_hcd_device,
 #endif
 
-#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
-        &isp1362_hcd_device,
-#endif
-
 #if defined(CONFIG_USB_ISP1760_HCD) || defined(CONFIG_USB_ISP1760_HCD_MODULE)
         &bfin_isp1760_device,
 #endif
diff --git a/arch/blackfin/mach-bf527/boards/ezkit.c b/arch/blackfin/mach-bf527/boards/ezkit.c
index f09665f74ba0..5294fdd20732 100644
--- a/arch/blackfin/mach-bf527/boards/ezkit.c
+++ b/arch/blackfin/mach-bf527/boards/ezkit.c
@@ -13,9 +13,6 @@
 #include <linux/mtd/physmap.h>
 #include <linux/spi/spi.h>
 #include <linux/spi/flash.h>
-#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
-#include <linux/usb/isp1362.h>
-#endif
 #include <linux/i2c.h>
 #include <linux/irq.h>
 #include <linux/interrupt.h>
@@ -63,7 +60,7 @@ static struct isp1760_platform_data isp1760_priv = {
 };
 
 static struct platform_device bfin_isp1760_device = {
-        .name           = "isp1760-hcd",
+        .name           = "isp1760",
         .id             = 0,
         .dev = {
                 .platform_data = &isp1760_priv,
@@ -373,45 +370,6 @@ static struct platform_device sl811_hcd_device = {
 };
 #endif
 
-#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
-static struct resource isp1362_hcd_resources[] = {
-        {
-                .start = 0x20360000,
-                .end = 0x20360000,
-                .flags = IORESOURCE_MEM,
-        }, {
-                .start = 0x20360004,
-                .end = 0x20360004,
-                .flags = IORESOURCE_MEM,
-        }, {
-                .start = CONFIG_USB_ISP1362_BFIN_GPIO_IRQ,
-                .end = CONFIG_USB_ISP1362_BFIN_GPIO_IRQ,
-                .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
-        },
-};
-
-static struct isp1362_platform_data isp1362_priv = {
-        .sel15Kres = 1,
-        .clknotstop = 0,
-        .oc_enable = 0,
-        .int_act_high = 0,
-        .int_edge_triggered = 0,
-        .remote_wakeup_connected = 0,
-        .no_power_switching = 1,
-        .power_switching_mode = 0,
-};
-
-static struct platform_device isp1362_hcd_device = {
-        .name = "isp1362-hcd",
-        .id = 0,
-        .dev = {
-                .platform_data = &isp1362_priv,
-        },
-        .num_resources = ARRAY_SIZE(isp1362_hcd_resources),
-        .resource = isp1362_hcd_resources,
-};
-#endif
-
 #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
 static struct platform_device bfin_mii_bus = {
         .name = "bfin_mii_bus",
@@ -688,12 +646,6 @@ static struct platform_device bfin_spi0_device = {
 };
 #endif  /* spi master and devices */
 
-#if defined(CONFIG_FB_BF537_LQ035) || defined(CONFIG_FB_BF537_LQ035_MODULE)
-static struct platform_device bfin_fb_device = {
-        .name = "bf537-lq035",
-};
-#endif
-
 #if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
 static struct resource bfin_uart_resources[] = {
 #ifdef CONFIG_SERIAL_BFIN_UART0
@@ -850,7 +802,7 @@ static struct platform_device bfin_device_gpiokeys = {
 };
 #endif
 
-#if defined(CONFIG_JOYSTICK_BFIN_ROTARY) || defined(CONFIG_JOYSTICK_BFIN_ROTARY_MODULE)
+#if defined(CONFIG_INPUT_BFIN_ROTARY) || defined(CONFIG_INPUT_BFIN_ROTARY_MODULE)
 #include <linux/input.h>
 #include <asm/bfin_rotary.h>
 
@@ -924,10 +876,6 @@ static struct platform_device *stamp_devices[] __initdata = {
         &sl811_hcd_device,
 #endif
 
-#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
-        &isp1362_hcd_device,
-#endif
-
 #if defined(CONFIG_USB_ISP1760_HCD) || defined(CONFIG_USB_ISP1760_HCD_MODULE)
         &bfin_isp1760_device,
 #endif
@@ -957,10 +905,6 @@ static struct platform_device *stamp_devices[] __initdata = {
         &bfin_spi0_device,
 #endif
 
-#if defined(CONFIG_FB_BF537_LQ035) || defined(CONFIG_FB_BF537_LQ035_MODULE)
-        &bfin_fb_device,
-#endif
-
 #if defined(CONFIG_FB_BFIN_T350MCQB) || defined(CONFIG_FB_BFIN_T350MCQB_MODULE)
         &bf52x_t350mcqb_device,
 #endif
@@ -991,7 +935,7 @@ static struct platform_device *stamp_devices[] __initdata = {
         &bfin_device_gpiokeys,
 #endif
 
-#if defined(CONFIG_JOYSTICK_BFIN_ROTARY) || defined(CONFIG_JOYSTICK_BFIN_ROTARY_MODULE)
+#if defined(CONFIG_INPUT_BFIN_ROTARY) || defined(CONFIG_INPUT_BFIN_ROTARY_MODULE)
         &bfin_rotary_device,
 #endif
 
diff --git a/arch/blackfin/mach-bf527/include/mach/blackfin.h b/arch/blackfin/mach-bf527/include/mach/blackfin.h
index e7d6034f268f..f714c5de3073 100644
--- a/arch/blackfin/mach-bf527/include/mach/blackfin.h
+++ b/arch/blackfin/mach-bf527/include/mach/blackfin.h
@@ -46,10 +46,4 @@
 #define OFFSET_SCR              0x1C    /* SCR Scratch Register                 */
 #define OFFSET_GCTL             0x24    /* Global Control Register              */
 
-/* PLL_DIV Masks                                                                                                        */
-#define CCLK_DIV1 CSEL_DIV1     /*          CCLK = VCO / 1                                  */
-#define CCLK_DIV2 CSEL_DIV2     /*          CCLK = VCO / 2                                  */
-#define CCLK_DIV4 CSEL_DIV4     /*          CCLK = VCO / 4                                  */
-#define CCLK_DIV8 CSEL_DIV8     /*          CCLK = VCO / 8                                  */
-
 #endif
diff --git a/arch/blackfin/mach-bf527/include/mach/cdefBF525.h b/arch/blackfin/mach-bf527/include/mach/cdefBF525.h
index dc3119e9f663..d7e2751c6bcc 100644
--- a/arch/blackfin/mach-bf527/include/mach/cdefBF525.h
+++ b/arch/blackfin/mach-bf527/include/mach/cdefBF525.h
@@ -10,15 +10,8 @@
 /* include all Core registers and bit definitions */
 #include "defBF525.h"
 
-/* include core specific register pointer definitions */
-#include <asm/cdef_LPBlackfin.h>
-
-/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF525 */
-
-/* include cdefBF52x_base.h for the set of #defines that are common to all ADSP-BF52x processors */
-#include "cdefBF52x_base.h"
-
-/* The following are the #defines needed by ADSP-BF525 that are not in the common header */
+/* BF525 is BF522 + USB */
+#include "cdefBF522.h"
 
 /* USB Control Registers */
 
diff --git a/arch/blackfin/mach-bf527/include/mach/cdefBF527.h b/arch/blackfin/mach-bf527/include/mach/cdefBF527.h
index d6579449ee46..c7ba544d50b6 100644
--- a/arch/blackfin/mach-bf527/include/mach/cdefBF527.h
+++ b/arch/blackfin/mach-bf527/include/mach/cdefBF527.h
@@ -10,15 +10,8 @@
 /* include all Core registers and bit definitions */
 #include "defBF527.h"
 
-/* include core specific register pointer definitions */
-#include <asm/cdef_LPBlackfin.h>
-
-/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF527 */
-
-/* include cdefBF52x_base.h for the set of #defines that are common to all ADSP-BF52x processors */
-#include "cdefBF52x_base.h"
-
-/* The following are the #defines needed by ADSP-BF527 that are not in the common header */
+/* BF527 is BF525 + EMAC */
+#include "cdefBF525.h"
 
 /* 10/100 Ethernet Controller   (0xFFC03000 - 0xFFC031FF) */
 
@@ -185,417 +178,4 @@
 #define bfin_read_EMAC_TXC_ABORT()              bfin_read32(EMAC_TXC_ABORT)
 #define bfin_write_EMAC_TXC_ABORT(val)          bfin_write32(EMAC_TXC_ABORT, val)
 
-/* USB Control Registers */
-
-#define bfin_read_USB_FADDR()                   bfin_read16(USB_FADDR)
-#define bfin_write_USB_FADDR(val)               bfin_write16(USB_FADDR, val)
-#define bfin_read_USB_POWER()                   bfin_read16(USB_POWER)
-#define bfin_write_USB_POWER(val)               bfin_write16(USB_POWER, val)
-#define bfin_read_USB_INTRTX()                  bfin_read16(USB_INTRTX)
-#define bfin_write_USB_INTRTX(val)              bfin_write16(USB_INTRTX, val)
-#define bfin_read_USB_INTRRX()                  bfin_read16(USB_INTRRX)
-#define bfin_write_USB_INTRRX(val)              bfin_write16(USB_INTRRX, val)
-#define bfin_read_USB_INTRTXE()                 bfin_read16(USB_INTRTXE)
-#define bfin_write_USB_INTRTXE(val)             bfin_write16(USB_INTRTXE, val)
-#define bfin_read_USB_INTRRXE()                 bfin_read16(USB_INTRRXE)
-#define bfin_write_USB_INTRRXE(val)             bfin_write16(USB_INTRRXE, val)
-#define bfin_read_USB_INTRUSB()                 bfin_read16(USB_INTRUSB)
-#define bfin_write_USB_INTRUSB(val)             bfin_write16(USB_INTRUSB, val)
-#define bfin_read_USB_INTRUSBE()                bfin_read16(USB_INTRUSBE)
-#define bfin_write_USB_INTRUSBE(val)            bfin_write16(USB_INTRUSBE, val)
-#define bfin_read_USB_FRAME()                   bfin_read16(USB_FRAME)
-#define bfin_write_USB_FRAME(val)               bfin_write16(USB_FRAME, val)
-#define bfin_read_USB_INDEX()                   bfin_read16(USB_INDEX)
-#define bfin_write_USB_INDEX(val)               bfin_write16(USB_INDEX, val)
-#define bfin_read_USB_TESTMODE()                bfin_read16(USB_TESTMODE)
-#define bfin_write_USB_TESTMODE(val)            bfin_write16(USB_TESTMODE, val)
-#define bfin_read_USB_GLOBINTR()                bfin_read16(USB_GLOBINTR)
-#define bfin_write_USB_GLOBINTR(val)            bfin_write16(USB_GLOBINTR, val)
-#define bfin_read_USB_GLOBAL_CTL()              bfin_read16(USB_GLOBAL_CTL)
-#define bfin_write_USB_GLOBAL_CTL(val)          bfin_write16(USB_GLOBAL_CTL, val)
-
-/* USB Packet Control Registers */
-
-#define bfin_read_USB_TX_MAX_PACKET()           bfin_read16(USB_TX_MAX_PACKET)
-#define bfin_write_USB_TX_MAX_PACKET(val)       bfin_write16(USB_TX_MAX_PACKET, val)
-#define bfin_read_USB_CSR0()                    bfin_read16(USB_CSR0)
-#define bfin_write_USB_CSR0(val)                bfin_write16(USB_CSR0, val)
-#define bfin_read_USB_TXCSR()                   bfin_read16(USB_TXCSR)
-#define bfin_write_USB_TXCSR(val)               bfin_write16(USB_TXCSR, val)
-#define bfin_read_USB_RX_MAX_PACKET()           bfin_read16(USB_RX_MAX_PACKET)
-#define bfin_write_USB_RX_MAX_PACKET(val)       bfin_write16(USB_RX_MAX_PACKET, val)
-#define bfin_read_USB_RXCSR()                   bfin_read16(USB_RXCSR)
-#define bfin_write_USB_RXCSR(val)               bfin_write16(USB_RXCSR, val)
-#define bfin_read_USB_COUNT0()                  bfin_read16(USB_COUNT0)
-#define bfin_write_USB_COUNT0(val)              bfin_write16(USB_COUNT0, val)
-#define bfin_read_USB_RXCOUNT()                 bfin_read16(USB_RXCOUNT)
-#define bfin_write_USB_RXCOUNT(val)             bfin_write16(USB_RXCOUNT, val)
-#define bfin_read_USB_TXTYPE()                  bfin_read16(USB_TXTYPE)
-#define bfin_write_USB_TXTYPE(val)              bfin_write16(USB_TXTYPE, val)
-#define bfin_read_USB_NAKLIMIT0()               bfin_read16(USB_NAKLIMIT0)
-#define bfin_write_USB_NAKLIMIT0(val)           bfin_write16(USB_NAKLIMIT0, val)
-#define bfin_read_USB_TXINTERVAL()              bfin_read16(USB_TXINTERVAL)
-#define bfin_write_USB_TXINTERVAL(val)          bfin_write16(USB_TXINTERVAL, val)
-#define bfin_read_USB_RXTYPE()                  bfin_read16(USB_RXTYPE)
-#define bfin_write_USB_RXTYPE(val)              bfin_write16(USB_RXTYPE, val)
-#define bfin_read_USB_RXINTERVAL()              bfin_read16(USB_RXINTERVAL)
-#define bfin_write_USB_RXINTERVAL(val)          bfin_write16(USB_RXINTERVAL, val)
-#define bfin_read_USB_TXCOUNT()                 bfin_read16(USB_TXCOUNT)
-#define bfin_write_USB_TXCOUNT(val)             bfin_write16(USB_TXCOUNT, val)
-
-/* USB Endpoint FIFO Registers */
-
-#define bfin_read_USB_EP0_FIFO()                bfin_read16(USB_EP0_FIFO)
-#define bfin_write_USB_EP0_FIFO(val)            bfin_write16(USB_EP0_FIFO, val)
-#define bfin_read_USB_EP1_FIFO()                bfin_read16(USB_EP1_FIFO)
-#define bfin_write_USB_EP1_FIFO(val)            bfin_write16(USB_EP1_FIFO, val)
-#define bfin_read_USB_EP2_FIFO()                bfin_read16(USB_EP2_FIFO)
-#define bfin_write_USB_EP2_FIFO(val)            bfin_write16(USB_EP2_FIFO, val)
-#define bfin_read_USB_EP3_FIFO()                bfin_read16(USB_EP3_FIFO)
-#define bfin_write_USB_EP3_FIFO(val)            bfin_write16(USB_EP3_FIFO, val)
-#define bfin_read_USB_EP4_FIFO()                bfin_read16(USB_EP4_FIFO)
-#define bfin_write_USB_EP4_FIFO(val)            bfin_write16(USB_EP4_FIFO, val)
-#define bfin_read_USB_EP5_FIFO()                bfin_read16(USB_EP5_FIFO)
-#define bfin_write_USB_EP5_FIFO(val)            bfin_write16(USB_EP5_FIFO, val)
-#define bfin_read_USB_EP6_FIFO()                bfin_read16(USB_EP6_FIFO)
-#define bfin_write_USB_EP6_FIFO(val)            bfin_write16(USB_EP6_FIFO, val)
-#define bfin_read_USB_EP7_FIFO()                bfin_read16(USB_EP7_FIFO)
-#define bfin_write_USB_EP7_FIFO(val)            bfin_write16(USB_EP7_FIFO, val)
-
-/* USB OTG Control Registers */
-
-#define bfin_read_USB_OTG_DEV_CTL()             bfin_read16(USB_OTG_DEV_CTL)
-#define bfin_write_USB_OTG_DEV_CTL(val)         bfin_write16(USB_OTG_DEV_CTL, val)
-#define bfin_read_USB_OTG_VBUS_IRQ()            bfin_read16(USB_OTG_VBUS_IRQ)
-#define bfin_write_USB_OTG_VBUS_IRQ(val)        bfin_write16(USB_OTG_VBUS_IRQ, val)
-#define bfin_read_USB_OTG_VBUS_MASK()           bfin_read16(USB_OTG_VBUS_MASK)
-#define bfin_write_USB_OTG_VBUS_MASK(val)       bfin_write16(USB_OTG_VBUS_MASK, val)
-
-/* USB Phy Control Registers */
-
-#define bfin_read_USB_LINKINFO()                bfin_read16(USB_LINKINFO)
-#define bfin_write_USB_LINKINFO(val)            bfin_write16(USB_LINKINFO, val)
-#define bfin_read_USB_VPLEN()                   bfin_read16(USB_VPLEN)
-#define bfin_write_USB_VPLEN(val)               bfin_write16(USB_VPLEN, val)
-#define bfin_read_USB_HS_EOF1()                 bfin_read16(USB_HS_EOF1)
-#define bfin_write_USB_HS_EOF1(val)             bfin_write16(USB_HS_EOF1, val)
-#define bfin_read_USB_FS_EOF1()                 bfin_read16(USB_FS_EOF1)
-#define bfin_write_USB_FS_EOF1(val)             bfin_write16(USB_FS_EOF1, val)
-#define bfin_read_USB_LS_EOF1()                 bfin_read16(USB_LS_EOF1)
-#define bfin_write_USB_LS_EOF1(val)             bfin_write16(USB_LS_EOF1, val)
-
-/* (APHY_CNTRL is for ADI usage only) */
-
-#define bfin_read_USB_APHY_CNTRL()              bfin_read16(USB_APHY_CNTRL)
-#define bfin_write_USB_APHY_CNTRL(val)          bfin_write16(USB_APHY_CNTRL, val)
-
-/* (APHY_CALIB is for ADI usage only) */
-
-#define bfin_read_USB_APHY_CALIB()              bfin_read16(USB_APHY_CALIB)
-#define bfin_write_USB_APHY_CALIB(val)          bfin_write16(USB_APHY_CALIB, val)
-
-#define bfin_read_USB_APHY_CNTRL2()             bfin_read16(USB_APHY_CNTRL2)
-#define bfin_write_USB_APHY_CNTRL2(val)         bfin_write16(USB_APHY_CNTRL2, val)
-
-/* (PHY_TEST is for ADI usage only) */
-
-#define bfin_read_USB_PHY_TEST()                bfin_read16(USB_PHY_TEST)
-#define bfin_write_USB_PHY_TEST(val)            bfin_write16(USB_PHY_TEST, val)
-
-#define bfin_read_USB_PLLOSC_CTRL()             bfin_read16(USB_PLLOSC_CTRL)
-#define bfin_write_USB_PLLOSC_CTRL(val)         bfin_write16(USB_PLLOSC_CTRL, val)
-#define bfin_read_USB_SRP_CLKDIV()              bfin_read16(USB_SRP_CLKDIV)
-#define bfin_write_USB_SRP_CLKDIV(val)          bfin_write16(USB_SRP_CLKDIV, val)
-
-/* USB Endpoint 0 Control Registers */
-
-#define bfin_read_USB_EP_NI0_TXMAXP()           bfin_read16(USB_EP_NI0_TXMAXP)
-#define bfin_write_USB_EP_NI0_TXMAXP(val)       bfin_write16(USB_EP_NI0_TXMAXP, val)
-#define bfin_read_USB_EP_NI0_TXCSR()            bfin_read16(USB_EP_NI0_TXCSR)
-#define bfin_write_USB_EP_NI0_TXCSR(val)        bfin_write16(USB_EP_NI0_TXCSR, val)
-#define bfin_read_USB_EP_NI0_RXMAXP()           bfin_read16(USB_EP_NI0_RXMAXP)
-#define bfin_write_USB_EP_NI0_RXMAXP(val)       bfin_write16(USB_EP_NI0_RXMAXP, val)
-#define bfin_read_USB_EP_NI0_RXCSR()            bfin_read16(USB_EP_NI0_RXCSR)
-#define bfin_write_USB_EP_NI0_RXCSR(val)        bfin_write16(USB_EP_NI0_RXCSR, val)
-#define bfin_read_USB_EP_NI0_RXCOUNT()          bfin_read16(USB_EP_NI0_RXCOUNT)
-#define bfin_write_USB_EP_NI0_RXCOUNT(val)      bfin_write16(USB_EP_NI0_RXCOUNT, val)
-#define bfin_read_USB_EP_NI0_TXTYPE()           bfin_read16(USB_EP_NI0_TXTYPE)
-#define bfin_write_USB_EP_NI0_TXTYPE(val)       bfin_write16(USB_EP_NI0_TXTYPE, val)
-#define bfin_read_USB_EP_NI0_TXINTERVAL()       bfin_read16(USB_EP_NI0_TXINTERVAL)
-#define bfin_write_USB_EP_NI0_TXINTERVAL(val)   bfin_write16(USB_EP_NI0_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI0_RXTYPE()           bfin_read16(USB_EP_NI0_RXTYPE)
-#define bfin_write_USB_EP_NI0_RXTYPE(val)       bfin_write16(USB_EP_NI0_RXTYPE, val)
-#define bfin_read_USB_EP_NI0_RXINTERVAL()       bfin_read16(USB_EP_NI0_RXINTERVAL)
-#define bfin_write_USB_EP_NI0_RXINTERVAL(val)   bfin_write16(USB_EP_NI0_RXINTERVAL, val)
-#define bfin_read_USB_EP_NI0_TXCOUNT()          bfin_read16(USB_EP_NI0_TXCOUNT)
-#define bfin_write_USB_EP_NI0_TXCOUNT(val)      bfin_write16(USB_EP_NI0_TXCOUNT, val)
-
-/* USB Endpoint 1 Control Registers */
-
-#define bfin_read_USB_EP_NI1_TXMAXP()           bfin_read16(USB_EP_NI1_TXMAXP)
-#define bfin_write_USB_EP_NI1_TXMAXP(val)       bfin_write16(USB_EP_NI1_TXMAXP, val)
-#define bfin_read_USB_EP_NI1_TXCSR()            bfin_read16(USB_EP_NI1_TXCSR)
-#define bfin_write_USB_EP_NI1_TXCSR(val)        bfin_write16(USB_EP_NI1_TXCSR, val)
-#define bfin_read_USB_EP_NI1_RXMAXP()           bfin_read16(USB_EP_NI1_RXMAXP)
-#define bfin_write_USB_EP_NI1_RXMAXP(val)       bfin_write16(USB_EP_NI1_RXMAXP, val)
-#define bfin_read_USB_EP_NI1_RXCSR()            bfin_read16(USB_EP_NI1_RXCSR)
-#define bfin_write_USB_EP_NI1_RXCSR(val)        bfin_write16(USB_EP_NI1_RXCSR, val)
-#define bfin_read_USB_EP_NI1_RXCOUNT()          bfin_read16(USB_EP_NI1_RXCOUNT)
-#define bfin_write_USB_EP_NI1_RXCOUNT(val)      bfin_write16(USB_EP_NI1_RXCOUNT, val)
-#define bfin_read_USB_EP_NI1_TXTYPE()           bfin_read16(USB_EP_NI1_TXTYPE)
-#define bfin_write_USB_EP_NI1_TXTYPE(val)       bfin_write16(USB_EP_NI1_TXTYPE, val)
-#define bfin_read_USB_EP_NI1_TXINTERVAL()       bfin_read16(USB_EP_NI1_TXINTERVAL)
-#define bfin_write_USB_EP_NI1_TXINTERVAL(val)   bfin_write16(USB_EP_NI1_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI1_RXTYPE()           bfin_read16(USB_EP_NI1_RXTYPE)
-#define bfin_write_USB_EP_NI1_RXTYPE(val)       bfin_write16(USB_EP_NI1_RXTYPE, val)
-#define bfin_read_USB_EP_NI1_RXINTERVAL()       bfin_read16(USB_EP_NI1_RXINTERVAL)
-#define bfin_write_USB_EP_NI1_RXINTERVAL(val)   bfin_write16(USB_EP_NI1_RXINTERVAL, val)
-#define bfin_read_USB_EP_NI1_TXCOUNT()          bfin_read16(USB_EP_NI1_TXCOUNT)
-#define bfin_write_USB_EP_NI1_TXCOUNT(val)      bfin_write16(USB_EP_NI1_TXCOUNT, val)
-
-/* USB Endpoint 2 Control Registers */
-
-#define bfin_read_USB_EP_NI2_TXMAXP()           bfin_read16(USB_EP_NI2_TXMAXP)
-#define bfin_write_USB_EP_NI2_TXMAXP(val)       bfin_write16(USB_EP_NI2_TXMAXP, val)
-#define bfin_read_USB_EP_NI2_TXCSR()            bfin_read16(USB_EP_NI2_TXCSR)
-#define bfin_write_USB_EP_NI2_TXCSR(val)        bfin_write16(USB_EP_NI2_TXCSR, val)
-#define bfin_read_USB_EP_NI2_RXMAXP()           bfin_read16(USB_EP_NI2_RXMAXP)
-#define bfin_write_USB_EP_NI2_RXMAXP(val)       bfin_write16(USB_EP_NI2_RXMAXP, val)
-#define bfin_read_USB_EP_NI2_RXCSR()            bfin_read16(USB_EP_NI2_RXCSR)
-#define bfin_write_USB_EP_NI2_RXCSR(val)        bfin_write16(USB_EP_NI2_RXCSR, val)
-#define bfin_read_USB_EP_NI2_RXCOUNT()          bfin_read16(USB_EP_NI2_RXCOUNT)
-#define bfin_write_USB_EP_NI2_RXCOUNT(val)      bfin_write16(USB_EP_NI2_RXCOUNT, val)
-#define bfin_read_USB_EP_NI2_TXTYPE()           bfin_read16(USB_EP_NI2_TXTYPE)
-#define bfin_write_USB_EP_NI2_TXTYPE(val)       bfin_write16(USB_EP_NI2_TXTYPE, val)
-#define bfin_read_USB_EP_NI2_TXINTERVAL()       bfin_read16(USB_EP_NI2_TXINTERVAL)
-#define bfin_write_USB_EP_NI2_TXINTERVAL(val)   bfin_write16(USB_EP_NI2_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI2_RXTYPE()           bfin_read16(USB_EP_NI2_RXTYPE)
-#define bfin_write_USB_EP_NI2_RXTYPE(val)       bfin_write16(USB_EP_NI2_RXTYPE, val)
-#define bfin_read_USB_EP_NI2_RXINTERVAL()       bfin_read16(USB_EP_NI2_RXINTERVAL)
-#define bfin_write_USB_EP_NI2_RXINTERVAL(val)   bfin_write16(USB_EP_NI2_RXINTERVAL, val)
-#define bfin_read_USB_EP_NI2_TXCOUNT()          bfin_read16(USB_EP_NI2_TXCOUNT)
-#define bfin_write_USB_EP_NI2_TXCOUNT(val)      bfin_write16(USB_EP_NI2_TXCOUNT, val)
-
-/* USB Endpoint 3 Control Registers */
-
-#define bfin_read_USB_EP_NI3_TXMAXP()           bfin_read16(USB_EP_NI3_TXMAXP)
-#define bfin_write_USB_EP_NI3_TXMAXP(val)       bfin_write16(USB_EP_NI3_TXMAXP, val)
-#define bfin_read_USB_EP_NI3_TXCSR()            bfin_read16(USB_EP_NI3_TXCSR)
-#define bfin_write_USB_EP_NI3_TXCSR(val)        bfin_write16(USB_EP_NI3_TXCSR, val)
-#define bfin_read_USB_EP_NI3_RXMAXP()           bfin_read16(USB_EP_NI3_RXMAXP)
-#define bfin_write_USB_EP_NI3_RXMAXP(val)       bfin_write16(USB_EP_NI3_RXMAXP, val)
-#define bfin_read_USB_EP_NI3_RXCSR()            bfin_read16(USB_EP_NI3_RXCSR)
-#define bfin_write_USB_EP_NI3_RXCSR(val)        bfin_write16(USB_EP_NI3_RXCSR, val)
-#define bfin_read_USB_EP_NI3_RXCOUNT()          bfin_read16(USB_EP_NI3_RXCOUNT)
-#define bfin_write_USB_EP_NI3_RXCOUNT(val)      bfin_write16(USB_EP_NI3_RXCOUNT, val)
-#define bfin_read_USB_EP_NI3_TXTYPE()           bfin_read16(USB_EP_NI3_TXTYPE)
-#define bfin_write_USB_EP_NI3_TXTYPE(val)       bfin_write16(USB_EP_NI3_TXTYPE, val)
-#define bfin_read_USB_EP_NI3_TXINTERVAL()       bfin_read16(USB_EP_NI3_TXINTERVAL)
-#define bfin_write_USB_EP_NI3_TXINTERVAL(val)   bfin_write16(USB_EP_NI3_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI3_RXTYPE()           bfin_read16(USB_EP_NI3_RXTYPE)
-#define bfin_write_USB_EP_NI3_RXTYPE(val)       bfin_write16(USB_EP_NI3_RXTYPE, val)
-#define bfin_read_USB_EP_NI3_RXINTERVAL()       bfin_read16(USB_EP_NI3_RXINTERVAL)
-#define bfin_write_USB_EP_NI3_RXINTERVAL(val)   bfin_write16(USB_EP_NI3_RXINTERVAL, val)
-#define bfin_read_USB_EP_NI3_TXCOUNT()          bfin_read16(USB_EP_NI3_TXCOUNT)
-#define bfin_write_USB_EP_NI3_TXCOUNT(val)      bfin_write16(USB_EP_NI3_TXCOUNT, val)
-
-/* USB Endpoint 4 Control Registers */
-
-#define bfin_read_USB_EP_NI4_TXMAXP()           bfin_read16(USB_EP_NI4_TXMAXP)
-#define bfin_write_USB_EP_NI4_TXMAXP(val)       bfin_write16(USB_EP_NI4_TXMAXP, val)
-#define bfin_read_USB_EP_NI4_TXCSR()            bfin_read16(USB_EP_NI4_TXCSR)
-#define bfin_write_USB_EP_NI4_TXCSR(val)        bfin_write16(USB_EP_NI4_TXCSR, val)
-#define bfin_read_USB_EP_NI4_RXMAXP()           bfin_read16(USB_EP_NI4_RXMAXP)
-#define bfin_write_USB_EP_NI4_RXMAXP(val)       bfin_write16(USB_EP_NI4_RXMAXP, val)
-#define bfin_read_USB_EP_NI4_RXCSR()            bfin_read16(USB_EP_NI4_RXCSR)
-#define bfin_write_USB_EP_NI4_RXCSR(val)        bfin_write16(USB_EP_NI4_RXCSR, val)
-#define bfin_read_USB_EP_NI4_RXCOUNT()          bfin_read16(USB_EP_NI4_RXCOUNT)
-#define bfin_write_USB_EP_NI4_RXCOUNT(val)      bfin_write16(USB_EP_NI4_RXCOUNT, val)
-#define bfin_read_USB_EP_NI4_TXTYPE()           bfin_read16(USB_EP_NI4_TXTYPE)
-#define bfin_write_USB_EP_NI4_TXTYPE(val)       bfin_write16(USB_EP_NI4_TXTYPE, val)
-#define bfin_read_USB_EP_NI4_TXINTERVAL()       bfin_read16(USB_EP_NI4_TXINTERVAL)
-#define bfin_write_USB_EP_NI4_TXINTERVAL(val)   bfin_write16(USB_EP_NI4_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI4_RXTYPE()           bfin_read16(USB_EP_NI4_RXTYPE)
-#define bfin_write_USB_EP_NI4_RXTYPE(val)       bfin_write16(USB_EP_NI4_RXTYPE, val)
-#define bfin_read_USB_EP_NI4_RXINTERVAL()       bfin_read16(USB_EP_NI4_RXINTERVAL)
-#define bfin_write_USB_EP_NI4_RXINTERVAL(val)   bfin_write16(USB_EP_NI4_RXINTERVAL, val)
-#define bfin_read_USB_EP_NI4_TXCOUNT()          bfin_read16(USB_EP_NI4_TXCOUNT)
-#define bfin_write_USB_EP_NI4_TXCOUNT(val)      bfin_write16(USB_EP_NI4_TXCOUNT, val)
-
-/* USB Endpoint 5 Control Registers */
-
-#define bfin_read_USB_EP_NI5_TXMAXP()           bfin_read16(USB_EP_NI5_TXMAXP)
-#define bfin_write_USB_EP_NI5_TXMAXP(val)       bfin_write16(USB_EP_NI5_TXMAXP, val)
-#define bfin_read_USB_EP_NI5_TXCSR()            bfin_read16(USB_EP_NI5_TXCSR)
-#define bfin_write_USB_EP_NI5_TXCSR(val)        bfin_write16(USB_EP_NI5_TXCSR, val)
-#define bfin_read_USB_EP_NI5_RXMAXP()           bfin_read16(USB_EP_NI5_RXMAXP)
-#define bfin_write_USB_EP_NI5_RXMAXP(val)       bfin_write16(USB_EP_NI5_RXMAXP, val)
-#define bfin_read_USB_EP_NI5_RXCSR()            bfin_read16(USB_EP_NI5_RXCSR)
-#define bfin_write_USB_EP_NI5_RXCSR(val)        bfin_write16(USB_EP_NI5_RXCSR, val)
-#define bfin_read_USB_EP_NI5_RXCOUNT()          bfin_read16(USB_EP_NI5_RXCOUNT)
-#define bfin_write_USB_EP_NI5_RXCOUNT(val)      bfin_write16(USB_EP_NI5_RXCOUNT, val)
-#define bfin_read_USB_EP_NI5_TXTYPE()           bfin_read16(USB_EP_NI5_TXTYPE)
-#define bfin_write_USB_EP_NI5_TXTYPE(val)       bfin_write16(USB_EP_NI5_TXTYPE, val)
-#define bfin_read_USB_EP_NI5_TXINTERVAL()       bfin_read16(USB_EP_NI5_TXINTERVAL)
-#define bfin_write_USB_EP_NI5_TXINTERVAL(val)   bfin_write16(USB_EP_NI5_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI5_RXTYPE()           bfin_read16(USB_EP_NI5_RXTYPE)
-#define bfin_write_USB_EP_NI5_RXTYPE(val)       bfin_write16(USB_EP_NI5_RXTYPE, val)
-#define bfin_read_USB_EP_NI5_RXINTERVAL()       bfin_read16(USB_EP_NI5_RXINTERVAL)
-#define bfin_write_USB_EP_NI5_RXINTERVAL(val)   bfin_write16(USB_EP_NI5_RXINTERVAL, val)
-#define bfin_read_USB_EP_NI5_TXCOUNT()          bfin_read16(USB_EP_NI5_TXCOUNT)
-#define bfin_write_USB_EP_NI5_TXCOUNT(val)      bfin_write16(USB_EP_NI5_TXCOUNT, val)
-
-/* USB Endpoint 6 Control Registers */
-
-#define bfin_read_USB_EP_NI6_TXMAXP()           bfin_read16(USB_EP_NI6_TXMAXP)
-#define bfin_write_USB_EP_NI6_TXMAXP(val)       bfin_write16(USB_EP_NI6_TXMAXP, val)
-#define bfin_read_USB_EP_NI6_TXCSR()            bfin_read16(USB_EP_NI6_TXCSR)
-#define bfin_write_USB_EP_NI6_TXCSR(val)        bfin_write16(USB_EP_NI6_TXCSR, val)
-#define bfin_read_USB_EP_NI6_RXMAXP()           bfin_read16(USB_EP_NI6_RXMAXP)
-#define bfin_write_USB_EP_NI6_RXMAXP(val)       bfin_write16(USB_EP_NI6_RXMAXP, val)
-#define bfin_read_USB_EP_NI6_RXCSR()            bfin_read16(USB_EP_NI6_RXCSR)
-#define bfin_write_USB_EP_NI6_RXCSR(val)        bfin_write16(USB_EP_NI6_RXCSR, val)
-#define bfin_read_USB_EP_NI6_RXCOUNT()          bfin_read16(USB_EP_NI6_RXCOUNT)
-#define bfin_write_USB_EP_NI6_RXCOUNT(val)      bfin_write16(USB_EP_NI6_RXCOUNT, val)
-#define bfin_read_USB_EP_NI6_TXTYPE()           bfin_read16(USB_EP_NI6_TXTYPE)
-#define bfin_write_USB_EP_NI6_TXTYPE(val)       bfin_write16(USB_EP_NI6_TXTYPE, val)
-#define bfin_read_USB_EP_NI6_TXINTERVAL()       bfin_read16(USB_EP_NI6_TXINTERVAL)
-#define bfin_write_USB_EP_NI6_TXINTERVAL(val)   bfin_write16(USB_EP_NI6_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI6_RXTYPE()           bfin_read16(USB_EP_NI6_RXTYPE)
-#define bfin_write_USB_EP_NI6_RXTYPE(val)       bfin_write16(USB_EP_NI6_RXTYPE, val)
-#define bfin_read_USB_EP_NI6_RXINTERVAL()       bfin_read16(USB_EP_NI6_RXINTERVAL)
-#define bfin_write_USB_EP_NI6_RXINTERVAL(val)   bfin_write16(USB_EP_NI6_RXINTERVAL, val)
-#define bfin_read_USB_EP_NI6_TXCOUNT()          bfin_read16(USB_EP_NI6_TXCOUNT)
-#define bfin_write_USB_EP_NI6_TXCOUNT(val)      bfin_write16(USB_EP_NI6_TXCOUNT, val)
-
-/* USB Endpoint 7 Control Registers */
-
-#define bfin_read_USB_EP_NI7_TXMAXP()           bfin_read16(USB_EP_NI7_TXMAXP)
-#define bfin_write_USB_EP_NI7_TXMAXP(val)       bfin_write16(USB_EP_NI7_TXMAXP, val)
-#define bfin_read_USB_EP_NI7_TXCSR()            bfin_read16(USB_EP_NI7_TXCSR)
-#define bfin_write_USB_EP_NI7_TXCSR(val)        bfin_write16(USB_EP_NI7_TXCSR, val)
-#define bfin_read_USB_EP_NI7_RXMAXP()           bfin_read16(USB_EP_NI7_RXMAXP)
-#define bfin_write_USB_EP_NI7_RXMAXP(val)       bfin_write16(USB_EP_NI7_RXMAXP, val)
-#define bfin_read_USB_EP_NI7_RXCSR()            bfin_read16(USB_EP_NI7_RXCSR)
-#define bfin_write_USB_EP_NI7_RXCSR(val)        bfin_write16(USB_EP_NI7_RXCSR, val)
-#define bfin_read_USB_EP_NI7_RXCOUNT()          bfin_read16(USB_EP_NI7_RXCOUNT)
-#define bfin_write_USB_EP_NI7_RXCOUNT(val)      bfin_write16(USB_EP_NI7_RXCOUNT, val)
-#define bfin_read_USB_EP_NI7_TXTYPE()           bfin_read16(USB_EP_NI7_TXTYPE)
-#define bfin_write_USB_EP_NI7_TXTYPE(val)       bfin_write16(USB_EP_NI7_TXTYPE, val)
-#define bfin_read_USB_EP_NI7_TXINTERVAL()       bfin_read16(USB_EP_NI7_TXINTERVAL)
-#define bfin_write_USB_EP_NI7_TXINTERVAL(val)   bfin_write16(USB_EP_NI7_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI7_RXTYPE()           bfin_read16(USB_EP_NI7_RXTYPE)
-#define bfin_write_USB_EP_NI7_RXTYPE(val)       bfin_write16(USB_EP_NI7_RXTYPE, val)
-#define bfin_read_USB_EP_NI7_RXINTERVAL()       bfin_read16(USB_EP_NI7_RXINTERVAL)
-#define bfin_write_USB_EP_NI7_RXINTERVAL(val)   bfin_write16(USB_EP_NI7_RXINTERVAL, val)
-#define bfin_read_USB_EP_NI7_TXCOUNT()          bfin_read16(USB_EP_NI7_TXCOUNT)
-#define bfin_write_USB_EP_NI7_TXCOUNT(val)      bfin_write16(USB_EP_NI7_TXCOUNT, val)
-
-#define bfin_read_USB_DMA_INTERRUPT()           bfin_read16(USB_DMA_INTERRUPT)
-#define bfin_write_USB_DMA_INTERRUPT(val)       bfin_write16(USB_DMA_INTERRUPT, val)
-
-/* USB Channel 0 Config Registers */
-
-#define bfin_read_USB_DMA0CONTROL()             bfin_read16(USB_DMA0CONTROL)
-#define bfin_write_USB_DMA0CONTROL(val)         bfin_write16(USB_DMA0CONTROL, val)
-#define bfin_read_USB_DMA0ADDRLOW()             bfin_read16(USB_DMA0ADDRLOW)
-#define bfin_write_USB_DMA0ADDRLOW(val)         bfin_write16(USB_DMA0ADDRLOW, val)
-#define bfin_read_USB_DMA0ADDRHIGH()            bfin_read16(USB_DMA0ADDRHIGH)
-#define bfin_write_USB_DMA0ADDRHIGH(val)        bfin_write16(USB_DMA0ADDRHIGH, val)
-#define bfin_read_USB_DMA0COUNTLOW()            bfin_read16(USB_DMA0COUNTLOW)
-#define bfin_write_USB_DMA0COUNTLOW(val)        bfin_write16(USB_DMA0COUNTLOW, val)
-#define bfin_read_USB_DMA0COUNTHIGH()           bfin_read16(USB_DMA0COUNTHIGH)
-#define bfin_write_USB_DMA0COUNTHIGH(val)       bfin_write16(USB_DMA0COUNTHIGH, val)
-
-/* USB Channel 1 Config Registers */
-
-#define bfin_read_USB_DMA1CONTROL()             bfin_read16(USB_DMA1CONTROL)
-#define bfin_write_USB_DMA1CONTROL(val)         bfin_write16(USB_DMA1CONTROL, val)
-#define bfin_read_USB_DMA1ADDRLOW()             bfin_read16(USB_DMA1ADDRLOW)
-#define bfin_write_USB_DMA1ADDRLOW(val)         bfin_write16(USB_DMA1ADDRLOW, val)
-#define bfin_read_USB_DMA1ADDRHIGH()            bfin_read16(USB_DMA1ADDRHIGH)
-#define bfin_write_USB_DMA1ADDRHIGH(val)        bfin_write16(USB_DMA1ADDRHIGH, val)
-#define bfin_read_USB_DMA1COUNTLOW()            bfin_read16(USB_DMA1COUNTLOW)
-#define bfin_write_USB_DMA1COUNTLOW(val)        bfin_write16(USB_DMA1COUNTLOW, val)
-#define bfin_read_USB_DMA1COUNTHIGH()           bfin_read16(USB_DMA1COUNTHIGH)
-#define bfin_write_USB_DMA1COUNTHIGH(val)       bfin_write16(USB_DMA1COUNTHIGH, val)
-
-/* USB Channel 2 Config Registers */
-
-#define bfin_read_USB_DMA2CONTROL()             bfin_read16(USB_DMA2CONTROL)
-#define bfin_write_USB_DMA2CONTROL(val)         bfin_write16(USB_DMA2CONTROL, val)
-#define bfin_read_USB_DMA2ADDRLOW()             bfin_read16(USB_DMA2ADDRLOW)
-#define bfin_write_USB_DMA2ADDRLOW(val)         bfin_write16(USB_DMA2ADDRLOW, val)
-#define bfin_read_USB_DMA2ADDRHIGH()            bfin_read16(USB_DMA2ADDRHIGH)
-#define bfin_write_USB_DMA2ADDRHIGH(val)        bfin_write16(USB_DMA2ADDRHIGH, val)
-#define bfin_read_USB_DMA2COUNTLOW()            bfin_read16(USB_DMA2COUNTLOW)
-#define bfin_write_USB_DMA2COUNTLOW(val)        bfin_write16(USB_DMA2COUNTLOW, val)
-#define bfin_read_USB_DMA2COUNTHIGH()           bfin_read16(USB_DMA2COUNTHIGH)
-#define bfin_write_USB_DMA2COUNTHIGH(val)       bfin_write16(USB_DMA2COUNTHIGH, val)
-
-/* USB Channel 3 Config Registers */
-
-#define bfin_read_USB_DMA3CONTROL()             bfin_read16(USB_DMA3CONTROL)
-#define bfin_write_USB_DMA3CONTROL(val)         bfin_write16(USB_DMA3CONTROL, val)
-#define bfin_read_USB_DMA3ADDRLOW()             bfin_read16(USB_DMA3ADDRLOW)
-#define bfin_write_USB_DMA3ADDRLOW(val)         bfin_write16(USB_DMA3ADDRLOW, val)
-#define bfin_read_USB_DMA3ADDRHIGH()            bfin_read16(USB_DMA3ADDRHIGH)
-#define bfin_write_USB_DMA3ADDRHIGH(val)        bfin_write16(USB_DMA3ADDRHIGH, val)
-#define bfin_read_USB_DMA3COUNTLOW()            bfin_read16(USB_DMA3COUNTLOW)
-#define bfin_write_USB_DMA3COUNTLOW(val)        bfin_write16(USB_DMA3COUNTLOW, val)
-#define bfin_read_USB_DMA3COUNTHIGH()           bfin_read16(USB_DMA3COUNTHIGH)
-#define bfin_write_USB_DMA3COUNTHIGH(val)       bfin_write16(USB_DMA3COUNTHIGH, val)
-
-/* USB Channel 4 Config Registers */
-
-#define bfin_read_USB_DMA4CONTROL()             bfin_read16(USB_DMA4CONTROL)
-#define bfin_write_USB_DMA4CONTROL(val)         bfin_write16(USB_DMA4CONTROL, val)
-#define bfin_read_USB_DMA4ADDRLOW()             bfin_read16(USB_DMA4ADDRLOW)
-#define bfin_write_USB_DMA4ADDRLOW(val)         bfin_write16(USB_DMA4ADDRLOW, val)
-#define bfin_read_USB_DMA4ADDRHIGH()            bfin_read16(USB_DMA4ADDRHIGH)
-#define bfin_write_USB_DMA4ADDRHIGH(val)        bfin_write16(USB_DMA4ADDRHIGH, val)
-#define bfin_read_USB_DMA4COUNTLOW()            bfin_read16(USB_DMA4COUNTLOW)
-#define bfin_write_USB_DMA4COUNTLOW(val)        bfin_write16(USB_DMA4COUNTLOW, val)
-#define bfin_read_USB_DMA4COUNTHIGH()           bfin_read16(USB_DMA4COUNTHIGH)
-#define bfin_write_USB_DMA4COUNTHIGH(val)       bfin_write16(USB_DMA4COUNTHIGH, val)
-
-/* USB Channel 5 Config Registers */
-
-#define bfin_read_USB_DMA5CONTROL()             bfin_read16(USB_DMA5CONTROL)
-#define bfin_write_USB_DMA5CONTROL(val)         bfin_write16(USB_DMA5CONTROL, val)
-#define bfin_read_USB_DMA5ADDRLOW()             bfin_read16(USB_DMA5ADDRLOW)
-#define bfin_write_USB_DMA5ADDRLOW(val)         bfin_write16(USB_DMA5ADDRLOW, val)
-#define bfin_read_USB_DMA5ADDRHIGH()            bfin_read16(USB_DMA5ADDRHIGH)
-#define bfin_write_USB_DMA5ADDRHIGH(val)        bfin_write16(USB_DMA5ADDRHIGH, val)
-#define bfin_read_USB_DMA5COUNTLOW()            bfin_read16(USB_DMA5COUNTLOW)
-#define bfin_write_USB_DMA5COUNTLOW(val)        bfin_write16(USB_DMA5COUNTLOW, val)
-#define bfin_read_USB_DMA5COUNTHIGH()           bfin_read16(USB_DMA5COUNTHIGH)
-#define bfin_write_USB_DMA5COUNTHIGH(val)       bfin_write16(USB_DMA5COUNTHIGH, val)
-
-/* USB Channel 6 Config Registers */
-
-#define bfin_read_USB_DMA6CONTROL()             bfin_read16(USB_DMA6CONTROL)
-#define bfin_write_USB_DMA6CONTROL(val)         bfin_write16(USB_DMA6CONTROL, val)
-#define bfin_read_USB_DMA6ADDRLOW()             bfin_read16(USB_DMA6ADDRLOW)
-#define bfin_write_USB_DMA6ADDRLOW(val)         bfin_write16(USB_DMA6ADDRLOW, val)
-#define bfin_read_USB_DMA6ADDRHIGH()            bfin_read16(USB_DMA6ADDRHIGH)
-#define bfin_write_USB_DMA6ADDRHIGH(val)        bfin_write16(USB_DMA6ADDRHIGH, val)
-#define bfin_read_USB_DMA6COUNTLOW()            bfin_read16(USB_DMA6COUNTLOW)
-#define bfin_write_USB_DMA6COUNTLOW(val)        bfin_write16(USB_DMA6COUNTLOW, val)
-#define bfin_read_USB_DMA6COUNTHIGH()           bfin_read16(USB_DMA6COUNTHIGH)
-#define bfin_write_USB_DMA6COUNTHIGH(val)       bfin_write16(USB_DMA6COUNTHIGH, val)
-
-/* USB Channel 7 Config Registers */
-
-#define bfin_read_USB_DMA7CONTROL()             bfin_read16(USB_DMA7CONTROL)
-#define bfin_write_USB_DMA7CONTROL(val)         bfin_write16(USB_DMA7CONTROL, val)
-#define bfin_read_USB_DMA7ADDRLOW()             bfin_read16(USB_DMA7ADDRLOW)
-#define bfin_write_USB_DMA7ADDRLOW(val)         bfin_write16(USB_DMA7ADDRLOW, val)
-#define bfin_read_USB_DMA7ADDRHIGH()            bfin_read16(USB_DMA7ADDRHIGH)
-#define bfin_write_USB_DMA7ADDRHIGH(val)        bfin_write16(USB_DMA7ADDRHIGH, val)
-#define bfin_read_USB_DMA7COUNTLOW()            bfin_read16(USB_DMA7COUNTLOW)
-#define bfin_write_USB_DMA7COUNTLOW(val)        bfin_write16(USB_DMA7COUNTLOW, val)
-#define bfin_read_USB_DMA7COUNTHIGH()           bfin_read16(USB_DMA7COUNTHIGH)
-#define bfin_write_USB_DMA7COUNTHIGH(val)       bfin_write16(USB_DMA7COUNTHIGH, val)
-
 #endif /* _CDEF_BF527_H */
diff --git a/arch/blackfin/mach-bf527/include/mach/cdefBF52x_base.h b/arch/blackfin/mach-bf527/include/mach/cdefBF52x_base.h
index 7014dde10dd6..12f2ad45314e 100644
--- a/arch/blackfin/mach-bf527/include/mach/cdefBF52x_base.h
+++ b/arch/blackfin/mach-bf527/include/mach/cdefBF52x_base.h
@@ -844,6 +844,7 @@
 #define bfin_write_PPI_CONTROL(val)             bfin_write16(PPI_CONTROL, val)
 #define bfin_read_PPI_STATUS()                  bfin_read16(PPI_STATUS)
 #define bfin_write_PPI_STATUS(val)              bfin_write16(PPI_STATUS, val)
+#define bfin_clear_PPI_STATUS()                 bfin_write_PPI_STATUS(0xFFFF)
 #define bfin_read_PPI_DELAY()                   bfin_read16(PPI_DELAY)
 #define bfin_write_PPI_DELAY(val)               bfin_write16(PPI_DELAY, val)
 #define bfin_read_PPI_COUNT()                   bfin_read16(PPI_COUNT)
@@ -1062,17 +1063,6 @@
 #define bfin_read_CNT_MIN()                     bfin_read32(CNT_MIN)
 #define bfin_write_CNT_MIN(val)                 bfin_write32(CNT_MIN, val)
 
-/* OTP/FUSE Registers */
-
-#define bfin_read_OTP_CONTROL()                 bfin_read16(OTP_CONTROL)
-#define bfin_write_OTP_CONTROL(val)             bfin_write16(OTP_CONTROL, val)
-#define bfin_read_OTP_BEN()                     bfin_read16(OTP_BEN)
-#define bfin_write_OTP_BEN(val)                 bfin_write16(OTP_BEN, val)
-#define bfin_read_OTP_STATUS()                  bfin_read16(OTP_STATUS)
-#define bfin_write_OTP_STATUS(val)              bfin_write16(OTP_STATUS, val)
-#define bfin_read_OTP_TIMING()                  bfin_read32(OTP_TIMING)
-#define bfin_write_OTP_TIMING(val)              bfin_write32(OTP_TIMING, val)
-
 /* Security Registers */
 
 #define bfin_read_SECURE_SYSSWT()               bfin_read32(SECURE_SYSSWT)
@@ -1082,17 +1072,6 @@
 #define bfin_read_SECURE_STATUS()               bfin_read16(SECURE_STATUS)
 #define bfin_write_SECURE_STATUS(val)           bfin_write16(SECURE_STATUS, val)
 
-/* OTP Read/Write Data Buffer Registers */
-
-#define bfin_read_OTP_DATA0()                   bfin_read32(OTP_DATA0)
-#define bfin_write_OTP_DATA0(val)               bfin_write32(OTP_DATA0, val)
-#define bfin_read_OTP_DATA1()                   bfin_read32(OTP_DATA1)
-#define bfin_write_OTP_DATA1(val)               bfin_write32(OTP_DATA1, val)
-#define bfin_read_OTP_DATA2()                   bfin_read32(OTP_DATA2)
-#define bfin_write_OTP_DATA2(val)               bfin_write32(OTP_DATA2, val)
-#define bfin_read_OTP_DATA3()                   bfin_read32(OTP_DATA3)
-#define bfin_write_OTP_DATA3(val)               bfin_write32(OTP_DATA3, val)
-
 /* NFC Registers */
 
 #define bfin_read_NFC_CTL()                     bfin_read16(NFC_CTL)
diff --git a/arch/blackfin/mach-bf527/include/mach/defBF525.h b/arch/blackfin/mach-bf527/include/mach/defBF525.h
index 82abefc1ef6c..c136f7032962 100644
--- a/arch/blackfin/mach-bf527/include/mach/defBF525.h
+++ b/arch/blackfin/mach-bf527/include/mach/defBF525.h
@@ -7,15 +7,8 @@
 #ifndef _DEF_BF525_H
 #define _DEF_BF525_H
 
-/* Include all Core registers and bit definitions */
-#include <asm/def_LPBlackfin.h>
-
-/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF525 */
-
-/* Include defBF52x_base.h for the set of #defines that are common to all ADSP-BF52x processors */
-#include "defBF52x_base.h"
-
-/* The following are the #defines needed by ADSP-BF525 that are not in the common header */
+/* BF525 is BF522 + USB */
+#include "defBF522.h"
 
 /* USB Control Registers */
 
diff --git a/arch/blackfin/mach-bf527/include/mach/defBF527.h b/arch/blackfin/mach-bf527/include/mach/defBF527.h
index 570a125df025..4dd58fb33156 100644
--- a/arch/blackfin/mach-bf527/include/mach/defBF527.h
+++ b/arch/blackfin/mach-bf527/include/mach/defBF527.h
@@ -7,15 +7,9 @@
 #ifndef _DEF_BF527_H
 #define _DEF_BF527_H
 
-/* Include all Core registers and bit definitions */
-#include <asm/def_LPBlackfin.h>
+/* BF527 is BF525 + EMAC */
+#include "defBF525.h"
 
-/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF527 */
-
-/* Include defBF52x_base.h for the set of #defines that are common to all ADSP-BF52x processors */
-#include "defBF52x_base.h"
-
-/* The following are the #defines needed by ADSP-BF527 that are not in the common header */
 /* 10/100 Ethernet Controller   (0xFFC03000 - 0xFFC031FF) */
 
 #define EMAC_OPMODE             0xFFC03000       /* Operating Mode Register                              */
@@ -394,673 +388,4 @@
 #define TX_GE1024_CNT     0x00200000    /* 1024-Max-Byte TX Frames Sent                           */
 #define TX_ABORT_CNT      0x00400000    /* TX Frames Aborted                                      */
 
-/* USB Control Registers */
-
-#define                        USB_FADDR  0xffc03800   /* Function address register */
-#define                        USB_POWER  0xffc03804   /* Power management register */
-#define                       USB_INTRTX  0xffc03808   /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */
-#define                       USB_INTRRX  0xffc0380c   /* Interrupt register for Rx endpoints 1 to 7 */
-#define                      USB_INTRTXE  0xffc03810   /* Interrupt enable register for IntrTx */
-#define                      USB_INTRRXE  0xffc03814   /* Interrupt enable register for IntrRx */
-#define                      USB_INTRUSB  0xffc03818   /* Interrupt register for common USB interrupts */
-#define                     USB_INTRUSBE  0xffc0381c   /* Interrupt enable register for IntrUSB */
-#define                        USB_FRAME  0xffc03820   /* USB frame number */
-#define                        USB_INDEX  0xffc03824   /* Index register for selecting the indexed endpoint registers */
-#define                     USB_TESTMODE  0xffc03828   /* Enabled USB 20 test modes */
-#define                     USB_GLOBINTR  0xffc0382c   /* Global Interrupt Mask register and Wakeup Exception Interrupt */
-#define                   USB_GLOBAL_CTL  0xffc03830   /* Global Clock Control for the core */
-
-/* USB Packet Control Registers */
-
-#define                USB_TX_MAX_PACKET  0xffc03840   /* Maximum packet size for Host Tx endpoint */
-#define                         USB_CSR0  0xffc03844   /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
-#define                        USB_TXCSR  0xffc03844   /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
-#define                USB_RX_MAX_PACKET  0xffc03848   /* Maximum packet size for Host Rx endpoint */
-#define                        USB_RXCSR  0xffc0384c   /* Control Status register for Host Rx endpoint */
-#define                       USB_COUNT0  0xffc03850   /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
-#define                      USB_RXCOUNT  0xffc03850   /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
-#define                       USB_TXTYPE  0xffc03854   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */
-#define                    USB_NAKLIMIT0  0xffc03858   /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
-#define                   USB_TXINTERVAL  0xffc03858   /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
-#define                       USB_RXTYPE  0xffc0385c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */
-#define                   USB_RXINTERVAL  0xffc03860   /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */
-#define                      USB_TXCOUNT  0xffc03868   /* Number of bytes to be written to the selected endpoint Tx FIFO */
-
-/* USB Endpoint FIFO Registers */
-
-#define                     USB_EP0_FIFO  0xffc03880   /* Endpoint 0 FIFO */
-#define                     USB_EP1_FIFO  0xffc03888   /* Endpoint 1 FIFO */
-#define                     USB_EP2_FIFO  0xffc03890   /* Endpoint 2 FIFO */
-#define                     USB_EP3_FIFO  0xffc03898   /* Endpoint 3 FIFO */
-#define                     USB_EP4_FIFO  0xffc038a0   /* Endpoint 4 FIFO */
-#define                     USB_EP5_FIFO  0xffc038a8   /* Endpoint 5 FIFO */
-#define                     USB_EP6_FIFO  0xffc038b0   /* Endpoint 6 FIFO */
-#define                     USB_EP7_FIFO  0xffc038b8   /* Endpoint 7 FIFO */
-
-/* USB OTG Control Registers */
-
-#define                  USB_OTG_DEV_CTL  0xffc03900   /* OTG Device Control Register */
-#define                 USB_OTG_VBUS_IRQ  0xffc03904   /* OTG VBUS Control Interrupts */
-#define                USB_OTG_VBUS_MASK  0xffc03908   /* VBUS Control Interrupt Enable */
-
-/* USB Phy Control Registers */
-
-#define                     USB_LINKINFO  0xffc03948   /* Enables programming of some PHY-side delays */
-#define                        USB_VPLEN  0xffc0394c   /* Determines duration of VBUS pulse for VBUS charging */
-#define                      USB_HS_EOF1  0xffc03950   /* Time buffer for High-Speed transactions */
-#define                      USB_FS_EOF1  0xffc03954   /* Time buffer for Full-Speed transactions */
-#define                      USB_LS_EOF1  0xffc03958   /* Time buffer for Low-Speed transactions */
-
-/* (APHY_CNTRL is for ADI usage only) */
-
-#define                   USB_APHY_CNTRL  0xffc039e0   /* Register that increases visibility of Analog PHY */
-
-/* (APHY_CALIB is for ADI usage only) */
-
-#define                   USB_APHY_CALIB  0xffc039e4   /* Register used to set some calibration values */
-
-#define                  USB_APHY_CNTRL2  0xffc039e8   /* Register used to prevent re-enumeration once Moab goes into hibernate mode */
-
-/* (PHY_TEST is for ADI usage only) */
-
-#define                     USB_PHY_TEST  0xffc039ec   /* Used for reducing simulation time and simplifies FIFO testability */
-
-#define                  USB_PLLOSC_CTRL  0xffc039f0   /* Used to program different parameters for USB PLL and Oscillator */
-#define                   USB_SRP_CLKDIV  0xffc039f4   /* Used to program clock divide value for the clock fed to the SRP detection logic */
-
-/* USB Endpoint 0 Control Registers */
-
-#define                USB_EP_NI0_TXMAXP  0xffc03a00   /* Maximum packet size for Host Tx endpoint0 */
-#define                 USB_EP_NI0_TXCSR  0xffc03a04   /* Control Status register for endpoint 0 */
-#define                USB_EP_NI0_RXMAXP  0xffc03a08   /* Maximum packet size for Host Rx endpoint0 */
-#define                 USB_EP_NI0_RXCSR  0xffc03a0c   /* Control Status register for Host Rx endpoint0 */
-#define               USB_EP_NI0_RXCOUNT  0xffc03a10   /* Number of bytes received in endpoint 0 FIFO */
-#define                USB_EP_NI0_TXTYPE  0xffc03a14   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */
-#define            USB_EP_NI0_TXINTERVAL  0xffc03a18   /* Sets the NAK response timeout on Endpoint 0 */
-#define                USB_EP_NI0_RXTYPE  0xffc03a1c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */
-#define            USB_EP_NI0_RXINTERVAL  0xffc03a20   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */
-#define               USB_EP_NI0_TXCOUNT  0xffc03a28   /* Number of bytes to be written to the endpoint0 Tx FIFO */
-
-/* USB Endpoint 1 Control Registers */
-
-#define                USB_EP_NI1_TXMAXP  0xffc03a40   /* Maximum packet size for Host Tx endpoint1 */
-#define                 USB_EP_NI1_TXCSR  0xffc03a44   /* Control Status register for endpoint1 */
-#define                USB_EP_NI1_RXMAXP  0xffc03a48   /* Maximum packet size for Host Rx endpoint1 */
-#define                 USB_EP_NI1_RXCSR  0xffc03a4c   /* Control Status register for Host Rx endpoint1 */
-#define               USB_EP_NI1_RXCOUNT  0xffc03a50   /* Number of bytes received in endpoint1 FIFO */
-#define                USB_EP_NI1_TXTYPE  0xffc03a54   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */
-#define            USB_EP_NI1_TXINTERVAL  0xffc03a58   /* Sets the NAK response timeout on Endpoint1 */
-#define                USB_EP_NI1_RXTYPE  0xffc03a5c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */
-#define            USB_EP_NI1_RXINTERVAL  0xffc03a60   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */
-#define               USB_EP_NI1_TXCOUNT  0xffc03a68   /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */
-
-/* USB Endpoint 2 Control Registers */
-
-#define                USB_EP_NI2_TXMAXP  0xffc03a80   /* Maximum packet size for Host Tx endpoint2 */
-#define                 USB_EP_NI2_TXCSR  0xffc03a84   /* Control Status register for endpoint2 */
-#define                USB_EP_NI2_RXMAXP  0xffc03a88   /* Maximum packet size for Host Rx endpoint2 */
-#define                 USB_EP_NI2_RXCSR  0xffc03a8c   /* Control Status register for Host Rx endpoint2 */
-#define               USB_EP_NI2_RXCOUNT  0xffc03a90   /* Number of bytes received in endpoint2 FIFO */
-#define                USB_EP_NI2_TXTYPE  0xffc03a94   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */
-#define            USB_EP_NI2_TXINTERVAL  0xffc03a98   /* Sets the NAK response timeout on Endpoint2 */
-#define                USB_EP_NI2_RXTYPE  0xffc03a9c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */
-#define            USB_EP_NI2_RXINTERVAL  0xffc03aa0   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */
-#define               USB_EP_NI2_TXCOUNT  0xffc03aa8   /* Number of bytes to be written to the endpoint2 Tx FIFO */
-
-/* USB Endpoint 3 Control Registers */
-
-#define                USB_EP_NI3_TXMAXP  0xffc03ac0   /* Maximum packet size for Host Tx endpoint3 */
-#define                 USB_EP_NI3_TXCSR  0xffc03ac4   /* Control Status register for endpoint3 */
-#define                USB_EP_NI3_RXMAXP  0xffc03ac8   /* Maximum packet size for Host Rx endpoint3 */
-#define                 USB_EP_NI3_RXCSR  0xffc03acc   /* Control Status register for Host Rx endpoint3 */
-#define               USB_EP_NI3_RXCOUNT  0xffc03ad0   /* Number of bytes received in endpoint3 FIFO */
-#define                USB_EP_NI3_TXTYPE  0xffc03ad4   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */
-#define            USB_EP_NI3_TXINTERVAL  0xffc03ad8   /* Sets the NAK response timeout on Endpoint3 */
-#define                USB_EP_NI3_RXTYPE  0xffc03adc   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */
-#define            USB_EP_NI3_RXINTERVAL  0xffc03ae0   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */
-#define               USB_EP_NI3_TXCOUNT  0xffc03ae8   /* Number of bytes to be written to the H124endpoint3 Tx FIFO */
-
-/* USB Endpoint 4 Control Registers */
-
-#define                USB_EP_NI4_TXMAXP  0xffc03b00   /* Maximum packet size for Host Tx endpoint4 */
-#define                 USB_EP_NI4_TXCSR  0xffc03b04   /* Control Status register for endpoint4 */
-#define                USB_EP_NI4_RXMAXP  0xffc03b08   /* Maximum packet size for Host Rx endpoint4 */
-#define                 USB_EP_NI4_RXCSR  0xffc03b0c   /* Control Status register for Host Rx endpoint4 */
-#define               USB_EP_NI4_RXCOUNT  0xffc03b10   /* Number of bytes received in endpoint4 FIFO */
-#define                USB_EP_NI4_TXTYPE  0xffc03b14   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */
-#define            USB_EP_NI4_TXINTERVAL  0xffc03b18   /* Sets the NAK response timeout on Endpoint4 */
-#define                USB_EP_NI4_RXTYPE  0xffc03b1c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */
-#define            USB_EP_NI4_RXINTERVAL  0xffc03b20   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */
-#define               USB_EP_NI4_TXCOUNT  0xffc03b28   /* Number of bytes to be written to the endpoint4 Tx FIFO */
-
-/* USB Endpoint 5 Control Registers */
-
-#define                USB_EP_NI5_TXMAXP  0xffc03b40   /* Maximum packet size for Host Tx endpoint5 */
-#define                 USB_EP_NI5_TXCSR  0xffc03b44   /* Control Status register for endpoint5 */
-#define                USB_EP_NI5_RXMAXP  0xffc03b48   /* Maximum packet size for Host Rx endpoint5 */
-#define                 USB_EP_NI5_RXCSR  0xffc03b4c   /* Control Status register for Host Rx endpoint5 */
-#define               USB_EP_NI5_RXCOUNT  0xffc03b50   /* Number of bytes received in endpoint5 FIFO */
-#define                USB_EP_NI5_TXTYPE  0xffc03b54   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */
-#define            USB_EP_NI5_TXINTERVAL  0xffc03b58   /* Sets the NAK response timeout on Endpoint5 */
-#define                USB_EP_NI5_RXTYPE  0xffc03b5c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */
-#define            USB_EP_NI5_RXINTERVAL  0xffc03b60   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */
-#define               USB_EP_NI5_TXCOUNT  0xffc03b68   /* Number of bytes to be written to the endpoint5 Tx FIFO */
-
-/* USB Endpoint 6 Control Registers */
-
-#define                USB_EP_NI6_TXMAXP  0xffc03b80   /* Maximum packet size for Host Tx endpoint6 */
-#define                 USB_EP_NI6_TXCSR  0xffc03b84   /* Control Status register for endpoint6 */
-#define                USB_EP_NI6_RXMAXP  0xffc03b88   /* Maximum packet size for Host Rx endpoint6 */
-#define                 USB_EP_NI6_RXCSR  0xffc03b8c   /* Control Status register for Host Rx endpoint6 */
-#define               USB_EP_NI6_RXCOUNT  0xffc03b90   /* Number of bytes received in endpoint6 FIFO */
-#define                USB_EP_NI6_TXTYPE  0xffc03b94   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */
-#define            USB_EP_NI6_TXINTERVAL  0xffc03b98   /* Sets the NAK response timeout on Endpoint6 */
-#define                USB_EP_NI6_RXTYPE  0xffc03b9c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */
-#define            USB_EP_NI6_RXINTERVAL  0xffc03ba0   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */
-#define               USB_EP_NI6_TXCOUNT  0xffc03ba8   /* Number of bytes to be written to the endpoint6 Tx FIFO */
-
-/* USB Endpoint 7 Control Registers */
-
-#define                USB_EP_NI7_TXMAXP  0xffc03bc0   /* Maximum packet size for Host Tx endpoint7 */
-#define                 USB_EP_NI7_TXCSR  0xffc03bc4   /* Control Status register for endpoint7 */
-#define                USB_EP_NI7_RXMAXP  0xffc03bc8   /* Maximum packet size for Host Rx endpoint7 */
-#define                 USB_EP_NI7_RXCSR  0xffc03bcc   /* Control Status register for Host Rx endpoint7 */
-#define               USB_EP_NI7_RXCOUNT  0xffc03bd0   /* Number of bytes received in endpoint7 FIFO */
-#define                USB_EP_NI7_TXTYPE  0xffc03bd4   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */
-#define            USB_EP_NI7_TXINTERVAL  0xffc03bd8   /* Sets the NAK response timeout on Endpoint7 */
-#define                USB_EP_NI7_RXTYPE  0xffc03bdc   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */
-#define            USB_EP_NI7_RXINTERVAL  0xffc03bf0   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */
-#define               USB_EP_NI7_TXCOUNT  0xffc03bf8   /* Number of bytes to be written to the endpoint7 Tx FIFO */
-
-#define                USB_DMA_INTERRUPT  0xffc03c00   /* Indicates pending interrupts for the DMA channels */
-
-/* USB Channel 0 Config Registers */
-
-#define                  USB_DMA0CONTROL  0xffc03c04   /* DMA master channel 0 configuration */
-#define                  USB_DMA0ADDRLOW  0xffc03c08   /* Lower 16-bits of memory source/destination address for DMA master channel 0 */
-#define                 USB_DMA0ADDRHIGH  0xffc03c0c   /* Upper 16-bits of memory source/destination address for DMA master channel 0 */
-#define                 USB_DMA0COUNTLOW  0xffc03c10   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */
-#define                USB_DMA0COUNTHIGH  0xffc03c14   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */
-
-/* USB Channel 1 Config Registers */
-
-#define                  USB_DMA1CONTROL  0xffc03c24   /* DMA master channel 1 configuration */
-#define                  USB_DMA1ADDRLOW  0xffc03c28   /* Lower 16-bits of memory source/destination address for DMA master channel 1 */
-#define                 USB_DMA1ADDRHIGH  0xffc03c2c   /* Upper 16-bits of memory source/destination address for DMA master channel 1 */
-#define                 USB_DMA1COUNTLOW  0xffc03c30   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */
-#define                USB_DMA1COUNTHIGH  0xffc03c34   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */
-
-/* USB Channel 2 Config Registers */
-
-#define                  USB_DMA2CONTROL  0xffc03c44   /* DMA master channel 2 configuration */
-#define                  USB_DMA2ADDRLOW  0xffc03c48   /* Lower 16-bits of memory source/destination address for DMA master channel 2 */
-#define                 USB_DMA2ADDRHIGH  0xffc03c4c   /* Upper 16-bits of memory source/destination address for DMA master channel 2 */
-#define                 USB_DMA2COUNTLOW  0xffc03c50   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */
-#define                USB_DMA2COUNTHIGH  0xffc03c54   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */
-
-/* USB Channel 3 Config Registers */
-
-#define                  USB_DMA3CONTROL  0xffc03c64   /* DMA master channel 3 configuration */
-#define                  USB_DMA3ADDRLOW  0xffc03c68   /* Lower 16-bits of memory source/destination address for DMA master channel 3 */
-#define                 USB_DMA3ADDRHIGH  0xffc03c6c   /* Upper 16-bits of memory source/destination address for DMA master channel 3 */
-#define                 USB_DMA3COUNTLOW  0xffc03c70   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */
-#define                USB_DMA3COUNTHIGH  0xffc03c74   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */
-
-/* USB Channel 4 Config Registers */
-
-#define                  USB_DMA4CONTROL  0xffc03c84   /* DMA master channel 4 configuration */
-#define                  USB_DMA4ADDRLOW  0xffc03c88   /* Lower 16-bits of memory source/destination address for DMA master channel 4 */
-#define                 USB_DMA4ADDRHIGH  0xffc03c8c   /* Upper 16-bits of memory source/destination address for DMA master channel 4 */
-#define                 USB_DMA4COUNTLOW  0xffc03c90   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */
-#define                USB_DMA4COUNTHIGH  0xffc03c94   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */
-
-/* USB Channel 5 Config Registers */
-
-#define                  USB_DMA5CONTROL  0xffc03ca4   /* DMA master channel 5 configuration */
-#define                  USB_DMA5ADDRLOW  0xffc03ca8   /* Lower 16-bits of memory source/destination address for DMA master channel 5 */
-#define                 USB_DMA5ADDRHIGH  0xffc03cac   /* Upper 16-bits of memory source/destination address for DMA master channel 5 */
-#define                 USB_DMA5COUNTLOW  0xffc03cb0   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */
-#define                USB_DMA5COUNTHIGH  0xffc03cb4   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */
-
-/* USB Channel 6 Config Registers */
-
-#define                  USB_DMA6CONTROL  0xffc03cc4   /* DMA master channel 6 configuration */
-#define                  USB_DMA6ADDRLOW  0xffc03cc8   /* Lower 16-bits of memory source/destination address for DMA master channel 6 */
-#define                 USB_DMA6ADDRHIGH  0xffc03ccc   /* Upper 16-bits of memory source/destination address for DMA master channel 6 */
-#define                 USB_DMA6COUNTLOW  0xffc03cd0   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */
-#define                USB_DMA6COUNTHIGH  0xffc03cd4   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */
-
-/* USB Channel 7 Config Registers */
-
-#define                  USB_DMA7CONTROL  0xffc03ce4   /* DMA master channel 7 configuration */
-#define                  USB_DMA7ADDRLOW  0xffc03ce8   /* Lower 16-bits of memory source/destination address for DMA master channel 7 */
-#define                 USB_DMA7ADDRHIGH  0xffc03cec   /* Upper 16-bits of memory source/destination address for DMA master channel 7 */
-#define                 USB_DMA7COUNTLOW  0xffc03cf0   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */
-#define                USB_DMA7COUNTHIGH  0xffc03cf4   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */
-
-/* Bit masks for USB_FADDR */
-
-#define          FUNCTION_ADDRESS  0x7f       /* Function address */
-
-/* Bit masks for USB_POWER */
-
-#define           ENABLE_SUSPENDM  0x1        /* enable SuspendM output */
-#define          nENABLE_SUSPENDM  0x0       
-#define              SUSPEND_MODE  0x2        /* Suspend Mode indicator */
-#define             nSUSPEND_MODE  0x0       
-#define               RESUME_MODE  0x4        /* DMA Mode */
-#define              nRESUME_MODE  0x0       
-#define                     RESET  0x8        /* Reset indicator */
-#define                    nRESET  0x0       
-#define                   HS_MODE  0x10       /* High Speed mode indicator */
-#define                  nHS_MODE  0x0       
-#define                 HS_ENABLE  0x20       /* high Speed Enable */
-#define                nHS_ENABLE  0x0       
-#define                 SOFT_CONN  0x40       /* Soft connect */
-#define                nSOFT_CONN  0x0       
-#define                ISO_UPDATE  0x80       /* Isochronous update */
-#define               nISO_UPDATE  0x0       
-
-/* Bit masks for USB_INTRTX */
-
-#define                    EP0_TX  0x1        /* Tx Endpoint 0 interrupt */
-#define                   nEP0_TX  0x0       
-#define                    EP1_TX  0x2        /* Tx Endpoint 1 interrupt */
-#define                   nEP1_TX  0x0       
-#define                    EP2_TX  0x4        /* Tx Endpoint 2 interrupt */
-#define                   nEP2_TX  0x0       
-#define                    EP3_TX  0x8        /* Tx Endpoint 3 interrupt */
-#define                   nEP3_TX  0x0       
-#define                    EP4_TX  0x10       /* Tx Endpoint 4 interrupt */
-#define                   nEP4_TX  0x0       
-#define                    EP5_TX  0x20       /* Tx Endpoint 5 interrupt */
-#define                   nEP5_TX  0x0       
-#define                    EP6_TX  0x40       /* Tx Endpoint 6 interrupt */
-#define                   nEP6_TX  0x0       
-#define                    EP7_TX  0x80       /* Tx Endpoint 7 interrupt */
-#define                   nEP7_TX  0x0       
-
-/* Bit masks for USB_INTRRX */
-
-#define                    EP1_RX  0x2        /* Rx Endpoint 1 interrupt */
-#define                   nEP1_RX  0x0       
-#define                    EP2_RX  0x4        /* Rx Endpoint 2 interrupt */
-#define                   nEP2_RX  0x0       
-#define                    EP3_RX  0x8        /* Rx Endpoint 3 interrupt */
-#define                   nEP3_RX  0x0       
-#define                    EP4_RX  0x10       /* Rx Endpoint 4 interrupt */
-#define                   nEP4_RX  0x0       
-#define                    EP5_RX  0x20       /* Rx Endpoint 5 interrupt */
-#define                   nEP5_RX  0x0       
-#define                    EP6_RX  0x40       /* Rx Endpoint 6 interrupt */
-#define                   nEP6_RX  0x0       
-#define                    EP7_RX  0x80       /* Rx Endpoint 7 interrupt */
-#define                   nEP7_RX  0x0       
-
-/* Bit masks for USB_INTRTXE */
-
-#define                  EP0_TX_E  0x1        /* Endpoint 0 interrupt Enable */
-#define                 nEP0_TX_E  0x0       
-#define                  EP1_TX_E  0x2        /* Tx Endpoint 1 interrupt  Enable */
-#define                 nEP1_TX_E  0x0       
-#define                  EP2_TX_E  0x4        /* Tx Endpoint 2 interrupt  Enable */
-#define                 nEP2_TX_E  0x0       
-#define                  EP3_TX_E  0x8        /* Tx Endpoint 3 interrupt  Enable */
-#define                 nEP3_TX_E  0x0       
-#define                  EP4_TX_E  0x10       /* Tx Endpoint 4 interrupt  Enable */
-#define                 nEP4_TX_E  0x0       
-#define                  EP5_TX_E  0x20       /* Tx Endpoint 5 interrupt  Enable */
-#define                 nEP5_TX_E  0x0       
-#define                  EP6_TX_E  0x40       /* Tx Endpoint 6 interrupt  Enable */
-#define                 nEP6_TX_E  0x0       
-#define                  EP7_TX_E  0x80       /* Tx Endpoint 7 interrupt  Enable */
-#define                 nEP7_TX_E  0x0       
-
-/* Bit masks for USB_INTRRXE */
-
-#define                  EP1_RX_E  0x2        /* Rx Endpoint 1 interrupt  Enable */
-#define                 nEP1_RX_E  0x0       
-#define                  EP2_RX_E  0x4        /* Rx Endpoint 2 interrupt  Enable */
-#define                 nEP2_RX_E  0x0       
-#define                  EP3_RX_E  0x8        /* Rx Endpoint 3 interrupt  Enable */
-#define                 nEP3_RX_E  0x0       
-#define                  EP4_RX_E  0x10       /* Rx Endpoint 4 interrupt  Enable */
-#define                 nEP4_RX_E  0x0       
-#define                  EP5_RX_E  0x20       /* Rx Endpoint 5 interrupt  Enable */
-#define                 nEP5_RX_E  0x0       
-#define                  EP6_RX_E  0x40       /* Rx Endpoint 6 interrupt  Enable */
-#define                 nEP6_RX_E  0x0       
-#define                  EP7_RX_E  0x80       /* Rx Endpoint 7 interrupt  Enable */
-#define                 nEP7_RX_E  0x0       
-
-/* Bit masks for USB_INTRUSB */
-
-#define                 SUSPEND_B  0x1        /* Suspend indicator */
-#define                nSUSPEND_B  0x0       
-#define                  RESUME_B  0x2        /* Resume indicator */
-#define                 nRESUME_B  0x0       
-#define          RESET_OR_BABLE_B  0x4        /* Reset/babble indicator */
-#define         nRESET_OR_BABLE_B  0x0       
-#define                     SOF_B  0x8        /* Start of frame */
-#define                    nSOF_B  0x0       
-#define                    CONN_B  0x10       /* Connection indicator */
-#define                   nCONN_B  0x0       
-#define                  DISCON_B  0x20       /* Disconnect indicator */
-#define                 nDISCON_B  0x0       
-#define             SESSION_REQ_B  0x40       /* Session Request */
-#define            nSESSION_REQ_B  0x0       
-#define              VBUS_ERROR_B  0x80       /* Vbus threshold indicator */
-#define             nVBUS_ERROR_B  0x0       
-
-/* Bit masks for USB_INTRUSBE */
-
-#define                SUSPEND_BE  0x1        /* Suspend indicator int enable */
-#define               nSUSPEND_BE  0x0       
-#define                 RESUME_BE  0x2        /* Resume indicator int enable */
-#define                nRESUME_BE  0x0       
-#define         RESET_OR_BABLE_BE  0x4        /* Reset/babble indicator int enable */
-#define        nRESET_OR_BABLE_BE  0x0       
-#define                    SOF_BE  0x8        /* Start of frame int enable */
-#define                   nSOF_BE  0x0       
-#define                   CONN_BE  0x10       /* Connection indicator int enable */
-#define                  nCONN_BE  0x0       
-#define                 DISCON_BE  0x20       /* Disconnect indicator int enable */
-#define                nDISCON_BE  0x0       
-#define            SESSION_REQ_BE  0x40       /* Session Request int enable */
-#define           nSESSION_REQ_BE  0x0       
-#define             VBUS_ERROR_BE  0x80       /* Vbus threshold indicator int enable */
-#define            nVBUS_ERROR_BE  0x0       
-
-/* Bit masks for USB_FRAME */
-
-#define              FRAME_NUMBER  0x7ff      /* Frame number */
-
-/* Bit masks for USB_INDEX */
-
-#define         SELECTED_ENDPOINT  0xf        /* selected endpoint */
-
-/* Bit masks for USB_GLOBAL_CTL */
-
-#define                GLOBAL_ENA  0x1        /* enables USB module */
-#define               nGLOBAL_ENA  0x0       
-#define                EP1_TX_ENA  0x2        /* Transmit endpoint 1 enable */
-#define               nEP1_TX_ENA  0x0       
-#define                EP2_TX_ENA  0x4        /* Transmit endpoint 2 enable */
-#define               nEP2_TX_ENA  0x0       
-#define                EP3_TX_ENA  0x8        /* Transmit endpoint 3 enable */
-#define               nEP3_TX_ENA  0x0       
-#define                EP4_TX_ENA  0x10       /* Transmit endpoint 4 enable */
-#define               nEP4_TX_ENA  0x0       
-#define                EP5_TX_ENA  0x20       /* Transmit endpoint 5 enable */
-#define               nEP5_TX_ENA  0x0       
-#define                EP6_TX_ENA  0x40       /* Transmit endpoint 6 enable */
-#define               nEP6_TX_ENA  0x0       
-#define                EP7_TX_ENA  0x80       /* Transmit endpoint 7 enable */
-#define               nEP7_TX_ENA  0x0       
-#define                EP1_RX_ENA  0x100      /* Receive endpoint 1 enable */
-#define               nEP1_RX_ENA  0x0       
-#define                EP2_RX_ENA  0x200      /* Receive endpoint 2 enable */
-#define               nEP2_RX_ENA  0x0       
-#define                EP3_RX_ENA  0x400      /* Receive endpoint 3 enable */
-#define               nEP3_RX_ENA  0x0       
-#define                EP4_RX_ENA  0x800      /* Receive endpoint 4 enable */
-#define               nEP4_RX_ENA  0x0       
-#define                EP5_RX_ENA  0x1000     /* Receive endpoint 5 enable */
-#define               nEP5_RX_ENA  0x0       
-#define                EP6_RX_ENA  0x2000     /* Receive endpoint 6 enable */
-#define               nEP6_RX_ENA  0x0       
-#define                EP7_RX_ENA  0x4000     /* Receive endpoint 7 enable */
-#define               nEP7_RX_ENA  0x0       
-
-/* Bit masks for USB_OTG_DEV_CTL */
-
-#define                   SESSION  0x1        /* session indicator */
-#define                  nSESSION  0x0       
-#define                  HOST_REQ  0x2        /* Host negotiation request */
-#define                 nHOST_REQ  0x0       
-#define                 HOST_MODE  0x4        /* indicates USBDRC is a host */
-#define                nHOST_MODE  0x0       
-#define                     VBUS0  0x8        /* Vbus level indicator[0] */
-#define                    nVBUS0  0x0       
-#define                     VBUS1  0x10       /* Vbus level indicator[1] */
-#define                    nVBUS1  0x0       
-#define                     LSDEV  0x20       /* Low-speed indicator */
-#define                    nLSDEV  0x0       
-#define                     FSDEV  0x40       /* Full or High-speed indicator */
-#define                    nFSDEV  0x0       
-#define                  B_DEVICE  0x80       /* A' or 'B' device indicator */
-#define                 nB_DEVICE  0x0       
-
-/* Bit masks for USB_OTG_VBUS_IRQ */
-
-#define             DRIVE_VBUS_ON  0x1        /* indicator to drive VBUS control circuit */
-#define            nDRIVE_VBUS_ON  0x0       
-#define            DRIVE_VBUS_OFF  0x2        /* indicator to shut off charge pump */
-#define           nDRIVE_VBUS_OFF  0x0       
-#define           CHRG_VBUS_START  0x4        /* indicator for external circuit to start charging VBUS */
-#define          nCHRG_VBUS_START  0x0       
-#define             CHRG_VBUS_END  0x8        /* indicator for external circuit to end charging VBUS */
-#define            nCHRG_VBUS_END  0x0       
-#define        DISCHRG_VBUS_START  0x10       /* indicator to start discharging VBUS */
-#define       nDISCHRG_VBUS_START  0x0       
-#define          DISCHRG_VBUS_END  0x20       /* indicator to stop discharging VBUS */
-#define         nDISCHRG_VBUS_END  0x0       
-
-/* Bit masks for USB_OTG_VBUS_MASK */
-
-#define         DRIVE_VBUS_ON_ENA  0x1        /* enable DRIVE_VBUS_ON interrupt */
-#define        nDRIVE_VBUS_ON_ENA  0x0       
-#define        DRIVE_VBUS_OFF_ENA  0x2        /* enable DRIVE_VBUS_OFF interrupt */
-#define       nDRIVE_VBUS_OFF_ENA  0x0       
-#define       CHRG_VBUS_START_ENA  0x4        /* enable CHRG_VBUS_START interrupt */
-#define      nCHRG_VBUS_START_ENA  0x0       
-#define         CHRG_VBUS_END_ENA  0x8        /* enable CHRG_VBUS_END interrupt */
-#define        nCHRG_VBUS_END_ENA  0x0       
-#define    DISCHRG_VBUS_START_ENA  0x10       /* enable DISCHRG_VBUS_START interrupt */
-#define   nDISCHRG_VBUS_START_ENA  0x0       
-#define      DISCHRG_VBUS_END_ENA  0x20       /* enable DISCHRG_VBUS_END interrupt */
-#define     nDISCHRG_VBUS_END_ENA  0x0       
-
-/* Bit masks for USB_CSR0 */
-
-#define                  RXPKTRDY  0x1        /* data packet receive indicator */
-#define                 nRXPKTRDY  0x0       
-#define                  TXPKTRDY  0x2        /* data packet in FIFO indicator */
-#define                 nTXPKTRDY  0x0       
-#define                STALL_SENT  0x4        /* STALL handshake sent */
-#define               nSTALL_SENT  0x0       
-#define                   DATAEND  0x8        /* Data end indicator */
-#define                  nDATAEND  0x0       
-#define                  SETUPEND  0x10       /* Setup end */
-#define                 nSETUPEND  0x0       
-#define                 SENDSTALL  0x20       /* Send STALL handshake */
-#define                nSENDSTALL  0x0       
-#define         SERVICED_RXPKTRDY  0x40       /* used to clear the RxPktRdy bit */
-#define        nSERVICED_RXPKTRDY  0x0       
-#define         SERVICED_SETUPEND  0x80       /* used to clear the SetupEnd bit */
-#define        nSERVICED_SETUPEND  0x0       
-#define                 FLUSHFIFO  0x100      /* flush endpoint FIFO */
-#define                nFLUSHFIFO  0x0       
-#define          STALL_RECEIVED_H  0x4        /* STALL handshake received host mode */
-#define         nSTALL_RECEIVED_H  0x0       
-#define                SETUPPKT_H  0x8        /* send Setup token host mode */
-#define               nSETUPPKT_H  0x0       
-#define                   ERROR_H  0x10       /* timeout error indicator host mode */
-#define                  nERROR_H  0x0       
-#define                  REQPKT_H  0x20       /* Request an IN transaction host mode */
-#define                 nREQPKT_H  0x0       
-#define               STATUSPKT_H  0x40       /* Status stage transaction host mode */
-#define              nSTATUSPKT_H  0x0       
-#define             NAK_TIMEOUT_H  0x80       /* EP0 halted after a NAK host mode */
-#define            nNAK_TIMEOUT_H  0x0       
-
-/* Bit masks for USB_COUNT0 */
-
-#define              EP0_RX_COUNT  0x7f       /* number of received bytes in EP0 FIFO */
-
-/* Bit masks for USB_NAKLIMIT0 */
-
-#define             EP0_NAK_LIMIT  0x1f       /* number of frames/micro frames after which EP0 timeouts */
-
-/* Bit masks for USB_TX_MAX_PACKET */
-
-#define         MAX_PACKET_SIZE_T  0x7ff      /* maximum data pay load in a frame */
-
-/* Bit masks for USB_RX_MAX_PACKET */
-
-#define         MAX_PACKET_SIZE_R  0x7ff      /* maximum data pay load in a frame */
-
-/* Bit masks for USB_TXCSR */
-
-#define                TXPKTRDY_T  0x1        /* data packet in FIFO indicator */
-#define               nTXPKTRDY_T  0x0       
-#define          FIFO_NOT_EMPTY_T  0x2        /* FIFO not empty */
-#define         nFIFO_NOT_EMPTY_T  0x0       
-#define                UNDERRUN_T  0x4        /* TxPktRdy not set  for an IN token */
-#define               nUNDERRUN_T  0x0       
-#define               FLUSHFIFO_T  0x8        /* flush endpoint FIFO */
-#define              nFLUSHFIFO_T  0x0       
-#define              STALL_SEND_T  0x10       /* issue a Stall handshake */
-#define             nSTALL_SEND_T  0x0       
-#define              STALL_SENT_T  0x20       /* Stall handshake transmitted */
-#define             nSTALL_SENT_T  0x0       
-#define        CLEAR_DATATOGGLE_T  0x40       /* clear endpoint data toggle */
-#define       nCLEAR_DATATOGGLE_T  0x0       
-#define                INCOMPTX_T  0x80       /* indicates that a large packet is split */
-#define               nINCOMPTX_T  0x0       
-#define              DMAREQMODE_T  0x400      /* DMA mode (0 or 1) selection */
-#define             nDMAREQMODE_T  0x0       
-#define        FORCE_DATATOGGLE_T  0x800      /* Force data toggle */
-#define       nFORCE_DATATOGGLE_T  0x0       
-#define              DMAREQ_ENA_T  0x1000     /* Enable DMA request for Tx EP */
-#define             nDMAREQ_ENA_T  0x0       
-#define                     ISO_T  0x4000     /* enable Isochronous transfers */
-#define                    nISO_T  0x0       
-#define                 AUTOSET_T  0x8000     /* allows TxPktRdy to be set automatically */
-#define                nAUTOSET_T  0x0       
-#define                  ERROR_TH  0x4        /* error condition host mode */
-#define                 nERROR_TH  0x0       
-#define         STALL_RECEIVED_TH  0x20       /* Stall handshake received host mode */
-#define        nSTALL_RECEIVED_TH  0x0       
-#define            NAK_TIMEOUT_TH  0x80       /* NAK timeout host mode */
-#define           nNAK_TIMEOUT_TH  0x0       
-
-/* Bit masks for USB_TXCOUNT */
-
-#define                  TX_COUNT  0x1fff     /* Number of bytes to be written to the selected endpoint Tx FIFO */
-
-/* Bit masks for USB_RXCSR */
-
-#define                RXPKTRDY_R  0x1        /* data packet in FIFO indicator */
-#define               nRXPKTRDY_R  0x0       
-#define               FIFO_FULL_R  0x2        /* FIFO not empty */
-#define              nFIFO_FULL_R  0x0       
-#define                 OVERRUN_R  0x4        /* TxPktRdy not set  for an IN token */
-#define                nOVERRUN_R  0x0       
-#define               DATAERROR_R  0x8        /* Out packet cannot be loaded into Rx  FIFO */
-#define              nDATAERROR_R  0x0       
-#define               FLUSHFIFO_R  0x10       /* flush endpoint FIFO */
-#define              nFLUSHFIFO_R  0x0       
-#define              STALL_SEND_R  0x20       /* issue a Stall handshake */
-#define             nSTALL_SEND_R  0x0       
-#define              STALL_SENT_R  0x40       /* Stall handshake transmitted */
-#define             nSTALL_SENT_R  0x0       
-#define        CLEAR_DATATOGGLE_R  0x80       /* clear endpoint data toggle */
-#define       nCLEAR_DATATOGGLE_R  0x0       
-#define                INCOMPRX_R  0x100      /* indicates that a large packet is split */
-#define               nINCOMPRX_R  0x0       
-#define              DMAREQMODE_R  0x800      /* DMA mode (0 or 1) selection */
-#define             nDMAREQMODE_R  0x0       
-#define                 DISNYET_R  0x1000     /* disable Nyet handshakes */
-#define                nDISNYET_R  0x0       
-#define              DMAREQ_ENA_R  0x2000     /* Enable DMA request for Tx EP */
-#define             nDMAREQ_ENA_R  0x0       
-#define                     ISO_R  0x4000     /* enable Isochronous transfers */
-#define                    nISO_R  0x0       
-#define               AUTOCLEAR_R  0x8000     /* allows TxPktRdy to be set automatically */
-#define              nAUTOCLEAR_R  0x0       
-#define                  ERROR_RH  0x4        /* TxPktRdy not set  for an IN token host mode */
-#define                 nERROR_RH  0x0       
-#define                 REQPKT_RH  0x20       /* request an IN transaction host mode */
-#define                nREQPKT_RH  0x0       
-#define         STALL_RECEIVED_RH  0x40       /* Stall handshake received host mode */
-#define        nSTALL_RECEIVED_RH  0x0       
-#define               INCOMPRX_RH  0x100      /* indicates that a large packet is split host mode */
-#define              nINCOMPRX_RH  0x0       
-#define             DMAREQMODE_RH  0x800      /* DMA mode (0 or 1) selection host mode */
-#define            nDMAREQMODE_RH  0x0       
-#define                AUTOREQ_RH  0x4000     /* sets ReqPkt automatically host mode */
-#define               nAUTOREQ_RH  0x0       
-
-/* Bit masks for USB_RXCOUNT */
-
-#define                  RX_COUNT  0x1fff     /* Number of received bytes in the packet in the Rx FIFO */
-
-/* Bit masks for USB_TXTYPE */
-
-#define            TARGET_EP_NO_T  0xf        /* EP number */
-#define                PROTOCOL_T  0xc        /* transfer type */
-
-/* Bit masks for USB_TXINTERVAL */
-
-#define          TX_POLL_INTERVAL  0xff       /* polling interval for selected Tx EP */
-
-/* Bit masks for USB_RXTYPE */
-
-#define            TARGET_EP_NO_R  0xf        /* EP number */
-#define                PROTOCOL_R  0xc        /* transfer type */
-
-/* Bit masks for USB_RXINTERVAL */
-
-#define          RX_POLL_INTERVAL  0xff       /* polling interval for selected Rx EP */
-
-/* Bit masks for USB_DMA_INTERRUPT */
-
-#define                  DMA0_INT  0x1        /* DMA0 pending interrupt */
-#define                 nDMA0_INT  0x0       
-#define                  DMA1_INT  0x2        /* DMA1 pending interrupt */
-#define                 nDMA1_INT  0x0       
-#define                  DMA2_INT  0x4        /* DMA2 pending interrupt */
-#define                 nDMA2_INT  0x0       
-#define                  DMA3_INT  0x8        /* DMA3 pending interrupt */
-#define                 nDMA3_INT  0x0       
-#define                  DMA4_INT  0x10       /* DMA4 pending interrupt */
-#define                 nDMA4_INT  0x0       
-#define                  DMA5_INT  0x20       /* DMA5 pending interrupt */
-#define                 nDMA5_INT  0x0       
-#define                  DMA6_INT  0x40       /* DMA6 pending interrupt */
-#define                 nDMA6_INT  0x0       
-#define                  DMA7_INT  0x80       /* DMA7 pending interrupt */
-#define                 nDMA7_INT  0x0       
-
-/* Bit masks for USB_DMAxCONTROL */
-
-#define                   DMA_ENA  0x1        /* DMA enable */
-#define                  nDMA_ENA  0x0       
-#define                 DIRECTION  0x2        /* direction of DMA transfer */
-#define                nDIRECTION  0x0       
-#define                      MODE  0x4        /* DMA Bus error */
-#define                     nMODE  0x0       
-#define                   INT_ENA  0x8        /* Interrupt enable */
-#define                  nINT_ENA  0x0       
-#define                     EPNUM  0xf0       /* EP number */
-#define                  BUSERROR  0x100      /* DMA Bus error */
-#define                 nBUSERROR  0x0       
-
-/* Bit masks for USB_DMAxADDRHIGH */
-
-#define             DMA_ADDR_HIGH  0xffff     /* Upper 16-bits of memory source/destination address for the DMA master channel */
-
-/* Bit masks for USB_DMAxADDRLOW */
-
-#define              DMA_ADDR_LOW  0xffff     /* Lower 16-bits of memory source/destination address for the DMA master channel */
-
-/* Bit masks for USB_DMAxCOUNTHIGH */
-
-#define            DMA_COUNT_HIGH  0xffff     /* Upper 16-bits of byte count of DMA transfer for DMA master channel */
-
-/* Bit masks for USB_DMAxCOUNTLOW */
-
-#define             DMA_COUNT_LOW  0xffff     /* Lower 16-bits of byte count of DMA transfer for DMA master channel */
-
 #endif /* _DEF_BF527_H */
diff --git a/arch/blackfin/mach-bf527/include/mach/defBF52x_base.h b/arch/blackfin/mach-bf527/include/mach/defBF52x_base.h
index b9dbb73d7ef0..8b18b5359210 100644
--- a/arch/blackfin/mach-bf527/include/mach/defBF52x_base.h
+++ b/arch/blackfin/mach-bf527/include/mach/defBF52x_base.h
@@ -586,58 +586,6 @@
 **                              modifier UNLESS the lower order bits are saved and ORed back in when
 **                              the macro is used.
 *************************************************************************************/
-/*
-** ********************* PLL AND RESET MASKS ****************************************/
-/* PLL_CTL Masks                                                                                                                                        */
-#define DF                              0x0001  /* 0: PLL = CLKIN, 1: PLL = CLKIN/2                                     */
-#define PLL_OFF                 0x0002  /* PLL Not Powered                                                                      */
-#define STOPCK                  0x0008  /* Core Clock Off                                                                       */
-#define PDWN                    0x0020  /* Enter Deep Sleep Mode                                                        */
-#define IN_DELAY                0x0040  /* Add 200ps Delay To EBIU Input Latches                        */
-#define OUT_DELAY               0x0080  /* Add 200ps Delay To EBIU Output Signals                       */
-#define BYPASS                  0x0100  /* Bypass the PLL                                                                       */
-#define MSEL                    0x7E00  /* Multiplier Select For CCLK/VCO Factors                       */
-/* PLL_CTL Macros (Only Use With Logic OR While Setting Lower Order Bits)                       */
-#define SET_MSEL(x)             (((x)&0x3F) << 0x9)     /* Set MSEL = 0-63 --> VCO = CLKIN*MSEL         */
-
-/* PLL_DIV Masks                                                                                                                */
-#define SSEL                    0x000F  /* System Select                                                */
-#define CSEL                    0x0030  /* Core Select                                                  */
-#define CSEL_DIV1               0x0000  /*              CCLK = VCO / 1                                  */
-#define CSEL_DIV2               0x0010  /*              CCLK = VCO / 2                                  */
-#define CSEL_DIV4               0x0020  /*              CCLK = VCO / 4                                  */
-#define CSEL_DIV8               0x0030  /*              CCLK = VCO / 8                                  */
-/* PLL_DIV Macros                                                                                                               */
-#define SET_SSEL(x)             ((x)&0xF)               /* Set SSEL = 0-15 --> SCLK = VCO/SSEL  */
-
-/* VR_CTL Masks */
-#define FREQ                    0x3000  /* Switching Oscillator Frequency For Regulator */
-#define HIBERNATE               0x0000  /*              Powerdown/Bypass On-Board Regulation    */
-
-#define VLEV                    0x00F0  /* Internal Voltage Level                                       */
-#define VLEV_085                0x0060  /*              VLEV = 0.85 V (-5% - +10% Accuracy)     */
-#define VLEV_090                0x0070  /*              VLEV = 0.90 V (-5% - +10% Accuracy)     */
-#define VLEV_095                0x0080  /*              VLEV = 0.95 V (-5% - +10% Accuracy)     */
-#define VLEV_100                0x0090  /*              VLEV = 1.00 V (-5% - +10% Accuracy)     */
-#define VLEV_105                0x00A0  /*              VLEV = 1.05 V (-5% - +10% Accuracy)     */
-#define VLEV_110                0x00B0  /*              VLEV = 1.10 V (-5% - +10% Accuracy)     */
-#define VLEV_115                0x00C0  /*              VLEV = 1.15 V (-5% - +10% Accuracy)     */
-#define VLEV_120                0x00D0  /*              VLEV = 1.20 V (-5% - +10% Accuracy)     */
-#define VLEV_125                0x00E0  /*              VLEV = 1.25 V (-5% - +10% Accuracy)     */
-#define VLEV_130                0x00F0  /*              VLEV = 1.30 V (-5% - +10% Accuracy)     */
-
-#define WAKE                    0x0100  /* Enable RTC/Reset Wakeup From Hibernate       */
-#define USBWE                   0x0200  /* Enable USB Wakeup From Hibernate                     */
-#define PHYWE                   0x0400  /* Enable PHY Wakeup From Hibernate                     */
-#define CLKBUFOE                0x4000  /* CLKIN Buffer Output Enable */
-#define PHYCLKOE                CLKBUFOE        /* Alternative legacy name for the above */
-#define SCKELOW         0x8000  /* Enable Drive CKE Low During Reset            */
-
-/* PLL_STAT Masks                                                                                                                                       */
-#define ACTIVE_PLLENABLED       0x0001  /* Processor In Active Mode With PLL Enabled    */
-#define FULL_ON                         0x0002  /* Processor In Full On Mode                                    */
-#define ACTIVE_PLLDISABLED      0x0004  /* Processor In Active Mode With PLL Disabled   */
-#define PLL_LOCKED                      0x0020  /* PLL_LOCKCNT Has Been Reached                                 */
 
 /* CHIPID Masks */
 #define CHIPID_VERSION         0xF0000000
@@ -757,66 +705,6 @@
 #define IWR_DISABLE(x)  (0xFFFFFFFF ^ (1 << ((x)&0x1F)))        /* Wakeup Disable Peripheral #x         */
 
 
-/* ********* WATCHDOG TIMER MASKS ******************** */
-
-/* Watchdog Timer WDOG_CTL Register Masks */
-
-#define WDEV(x) (((x)<<1) & 0x0006) /* event generated on roll over */
-#define WDEV_RESET 0x0000 /* generate reset event on roll over */
-#define WDEV_NMI 0x0002 /* generate NMI event on roll over */
-#define WDEV_GPI 0x0004 /* generate GP IRQ on roll over */
-#define WDEV_NONE 0x0006 /* no event on roll over */
-#define WDEN 0x0FF0 /* enable watchdog */
-#define WDDIS 0x0AD0 /* disable watchdog */
-#define WDRO 0x8000 /* watchdog rolled over latch */
-
-/* depreciated WDOG_CTL Register Masks for legacy code */
-
-
-#define ICTL WDEV
-#define ENABLE_RESET WDEV_RESET
-#define WDOG_RESET WDEV_RESET
-#define ENABLE_NMI WDEV_NMI
-#define WDOG_NMI WDEV_NMI
-#define ENABLE_GPI WDEV_GPI
-#define WDOG_GPI WDEV_GPI
-#define DISABLE_EVT WDEV_NONE
-#define WDOG_NONE WDEV_NONE
-
-#define TMR_EN WDEN
-#define TMR_DIS WDDIS
-#define TRO WDRO
-#define ICTL_P0 0x01
- #define ICTL_P1 0x02
-#define TRO_P 0x0F
-
-
-
-/* ***************  REAL TIME CLOCK MASKS  **************************/
-/* RTC_STAT and RTC_ALARM Masks                                                                         */
-#define RTC_SEC                         0x0000003F      /* Real-Time Clock Seconds      */
-#define RTC_MIN                         0x00000FC0      /* Real-Time Clock Minutes      */
-#define RTC_HR                          0x0001F000      /* Real-Time Clock Hours        */
-#define RTC_DAY                         0xFFFE0000      /* Real-Time Clock Days         */
-
-/* RTC_ALARM Macro                      z=day           y=hr    x=min   w=sec           */
-#define SET_ALARM(z,y,x,w)      ((((z)&0x7FFF)<<0x11)|(((y)&0x1F)<<0xC)|(((x)&0x3F)<<0x6)|((w)&0x3F))
-
-/* RTC_ICTL and RTC_ISTAT Masks                                                                                                                                         */
-#define STOPWATCH                       0x0001          /* Stopwatch Interrupt Enable                                                           */
-#define ALARM                           0x0002          /* Alarm Interrupt Enable                                                                       */
-#define SECOND                          0x0004          /* Seconds (1 Hz) Interrupt Enable                                                      */
-#define MINUTE                          0x0008          /* Minutes Interrupt Enable                                                                     */
-#define HOUR                            0x0010          /* Hours Interrupt Enable                                                                       */
-#define DAY                                     0x0020          /* 24 Hours (Days) Interrupt Enable                                                     */
-#define DAY_ALARM                       0x0040          /* Day Alarm (Day, Hour, Minute, Second) Interrupt Enable       */
-#define WRITE_PENDING           0x4000          /* Write Pending Status                                                                         */
-#define WRITE_COMPLETE          0x8000          /* Write Complete Interrupt Enable                                                      */
-
-/* RTC_FAST / RTC_PREN Mask                                                                                             */
-#define PREN                            0x0001  /* Enable Prescaler, RTC Runs @1 Hz     */
-
-
 /* ************** UART CONTROLLER MASKS *************************/
 /* UARTx_LCR Masks                                                                                              */
 #define WLS(x)          (((x)-5) & 0x03)        /* Word Length Select */
@@ -1381,33 +1269,6 @@
 
 
 /* **************************  DMA CONTROLLER MASKS  ********************************/
-/* DMAx_CONFIG, MDMA_yy_CONFIG Masks                                                                                            */
-#define DMAEN                   0x0001          /* DMA Channel Enable                                                   */
-#define WNR                             0x0002          /* Channel Direction (W/R*)                                             */
-#define WDSIZE_8                0x0000          /* Transfer Word Size = 8                                               */
-#define WDSIZE_16               0x0004          /* Transfer Word Size = 16                                              */
-#define WDSIZE_32               0x0008          /* Transfer Word Size = 32                                              */
-#define DMA2D                   0x0010          /* DMA Mode (2D/1D*)                                                    */
-#define RESTART                 0x0020          /* DMA Buffer Clear                                                             */
-#define DI_SEL                  0x0040          /* Data Interrupt Timing Select                                 */
-#define DI_EN                   0x0080          /* Data Interrupt Enable                                                */
-#define NDSIZE_0                0x0000          /* Next Descriptor Size = 0 (Stop/Autobuffer)   */
-#define NDSIZE_1                0x0100          /* Next Descriptor Size = 1                                             */
-#define NDSIZE_2                0x0200          /* Next Descriptor Size = 2                                             */
-#define NDSIZE_3                0x0300          /* Next Descriptor Size = 3                                             */
-#define NDSIZE_4                0x0400          /* Next Descriptor Size = 4                                             */
-#define NDSIZE_5                0x0500          /* Next Descriptor Size = 5                                             */
-#define NDSIZE_6                0x0600          /* Next Descriptor Size = 6                                             */
-#define NDSIZE_7                0x0700          /* Next Descriptor Size = 7                                             */
-#define NDSIZE_8                0x0800          /* Next Descriptor Size = 8                                             */
-#define NDSIZE_9                0x0900          /* Next Descriptor Size = 9                                             */
-#define NDSIZE                  0x0900  /* Next Descriptor Size */
-#define DMAFLOW                 0x7000  /* Flow Control */
-#define DMAFLOW_STOP            0x0000          /* Stop Mode                                                                    */
-#define DMAFLOW_AUTO            0x1000          /* Autobuffer Mode                                                              */
-#define DMAFLOW_ARRAY           0x4000          /* Descriptor Array Mode                                                */
-#define DMAFLOW_SMALL           0x6000          /* Small Model Descriptor List Mode                             */
-#define DMAFLOW_LARGE           0x7000          /* Large Model Descriptor List Mode                             */
 
 /* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP Masks                                                            */
 #define CTYPE                   0x0040  /* DMA Channel Type Indicator (Memory/Peripheral*)      */
@@ -1425,13 +1286,6 @@
 #define PMAP_UART1RX    0xA000  /*              UART1 Port Receive DMA                                          */
 #define PMAP_UART1TX    0xB000  /*              UART1 Port Transmit DMA                                         */
 
-/* DMAx_IRQ_STATUS, MDMA_yy_IRQ_STATUS Masks                                            */
-#define DMA_DONE                0x0001  /* DMA Completion Interrupt Status      */
-#define DMA_ERR                 0x0002  /* DMA Error Interrupt Status           */
-#define DFETCH                  0x0004  /* DMA Descriptor Fetch Indicator       */
-#define DMA_RUN                 0x0008  /* DMA Channel Running Indicator        */
-
-
 /*  ************  PARALLEL PERIPHERAL INTERFACE (PPI) MASKS *************/
 /*  PPI_CONTROL Masks                                                                                                   */
 #define PORT_EN                 0x0001          /* PPI Port Enable                                      */
@@ -1843,46 +1697,6 @@
 #define BNDMODE_CAPT     0x2000  /* boundary capture mode */
 #define BNDMODE_AEXT     0x3000  /* boundary auto-extend mode */
 
-/* Bit masks for OTP_CONTROL */
-
-#define                FUSE_FADDR  0x1ff      /* OTP/Fuse Address */
-#define                      FIEN  0x800      /* OTP/Fuse Interrupt Enable */
-#define                     nFIEN  0x0
-#define                  FTESTDEC  0x1000     /* OTP/Fuse Test Decoder */
-#define                 nFTESTDEC  0x0
-#define                   FWRTEST  0x2000     /* OTP/Fuse Write Test */
-#define                  nFWRTEST  0x0
-#define                     FRDEN  0x4000     /* OTP/Fuse Read Enable */
-#define                    nFRDEN  0x0
-#define                     FWREN  0x8000     /* OTP/Fuse Write Enable */
-#define                    nFWREN  0x0
-
-/* Bit masks for OTP_BEN */
-
-#define                      FBEN  0xffff     /* OTP/Fuse Byte Enable */
-
-/* Bit masks for OTP_STATUS */
-
-#define                     FCOMP  0x1        /* OTP/Fuse Access Complete */
-#define                    nFCOMP  0x0
-#define                    FERROR  0x2        /* OTP/Fuse Access Error */
-#define                   nFERROR  0x0
-#define                  MMRGLOAD  0x10       /* Memory Mapped Register Gasket Load */
-#define                 nMMRGLOAD  0x0
-#define                  MMRGLOCK  0x20       /* Memory Mapped Register Gasket Lock */
-#define                 nMMRGLOCK  0x0
-#define                    FPGMEN  0x40       /* OTP/Fuse Program Enable */
-#define                   nFPGMEN  0x0
-
-/* Bit masks for OTP_TIMING */
-
-#define                   USECDIV  0xff       /* Micro Second Divider */
-#define                   READACC  0x7f00     /* Read Access Time */
-#define                   CPUMPRL  0x38000    /* Charge Pump Release Time */
-#define                   CPUMPSU  0xc0000    /* Charge Pump Setup Time */
-#define                   CPUMPHD  0xf00000   /* Charge Pump Hold Time */
-#define                   PGMTIME  0xff000000 /* Program Time */
-
 /* Bit masks for SECURE_SYSSWT */
 
 #define                   EMUDABL  0x1        /* Emulation Disable. */
diff --git a/arch/blackfin/mach-bf533/boards/H8606.c b/arch/blackfin/mach-bf533/boards/H8606.c
index 43f43a095a99..4adceb0bdb6d 100644
--- a/arch/blackfin/mach-bf533/boards/H8606.c
+++ b/arch/blackfin/mach-bf533/boards/H8606.c
@@ -166,7 +166,6 @@ static struct bfin5xx_spi_chip spi_flash_chip_info = {
 #if defined(CONFIG_BFIN_SPI_ADC) || defined(CONFIG_BFIN_SPI_ADC_MODULE)
 /* SPI ADC chip */
 static struct bfin5xx_spi_chip spi_adc_chip_info = {
-        .ctl_reg = 0x1000,
         .enable_dma = 1,         /* use dma transfer with this chip*/
         .bits_per_word = 16,
 };
@@ -174,7 +173,6 @@ static struct bfin5xx_spi_chip spi_adc_chip_info = {
 
 #if defined(CONFIG_SND_BLACKFIN_AD1836) || defined(CONFIG_SND_BLACKFIN_AD1836_MODULE)
 static struct bfin5xx_spi_chip ad1836_spi_chip_info = {
-        .ctl_reg = 0x1000,
         .enable_dma = 0,
         .bits_per_word = 16,
 };
@@ -258,12 +256,6 @@ static struct platform_device bfin_spi0_device = {
 };
 #endif  /* spi master and devices */
 
-#if defined(CONFIG_FB_BF537_LQ035) || defined(CONFIG_FB_BF537_LQ035_MODULE)
-static struct platform_device bfin_fb_device = {
-        .name = "bf537-fb",
-};
-#endif
-
 #if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
 static struct resource bfin_uart_resources[] = {
         {
diff --git a/arch/blackfin/mach-bf533/boards/ip0x.c b/arch/blackfin/mach-bf533/boards/ip0x.c
index 644be5e5ab6f..8ec42ba35b9e 100644
--- a/arch/blackfin/mach-bf533/boards/ip0x.c
+++ b/arch/blackfin/mach-bf533/boards/ip0x.c
@@ -20,6 +20,7 @@
 #endif
 #include <asm/irq.h>
 #include <asm/bfin5xx_spi.h>
+#include <asm/portmux.h>
 
 /*
  * Name the Board for the /proc/cpuinfo
@@ -107,20 +108,6 @@ static struct platform_device dm9000_device2 = {
 
 #if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
 static struct bfin5xx_spi_chip mmc_spi_chip_info = {
-/*
- * CPOL (Clock Polarity)
- *  0 - Active high SCK
- *  1 - Active low SCK
- *  CPHA (Clock Phase) Selects transfer format and operation mode
- *  0 - SCLK toggles from middle of the first data bit, slave select
- *      pins controlled by hardware.
- *  1 - SCLK toggles from beginning of first data bit, slave select
- *      pins controller by user software.
- *      .ctl_reg = 0x1c00,               *  CPOL=1,CPHA=1,Sandisk 1G work
- * NO NO        .ctl_reg = 0x1800,               *  CPOL=1,CPHA=0
- * NO NO        .ctl_reg = 0x1400,               *  CPOL=0,CPHA=1
- */
-        .ctl_reg = 0x1000,              /* CPOL=0,CPHA=0,Sandisk 1G work */
         .enable_dma = 0,                /* if 1 - block!!! */
         .bits_per_word = 8,
 };
diff --git a/arch/blackfin/mach-bf533/boards/stamp.c b/arch/blackfin/mach-bf533/boards/stamp.c
index 82f70efd66e7..6d68dcfa2da2 100644
--- a/arch/blackfin/mach-bf533/boards/stamp.c
+++ b/arch/blackfin/mach-bf533/boards/stamp.c
@@ -321,12 +321,6 @@ static struct platform_device bfin_spi0_device = {
 };
 #endif  /* spi master and devices */
 
-#if defined(CONFIG_FB_BF537_LQ035) || defined(CONFIG_FB_BF537_LQ035_MODULE)
-static struct platform_device bfin_fb_device = {
-        .name = "bf537-fb",
-};
-#endif
-
 #if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
 static struct resource bfin_uart_resources[] = {
         {
diff --git a/arch/blackfin/mach-bf533/include/mach/defBF532.h b/arch/blackfin/mach-bf533/include/mach/defBF532.h
index 02b328eb0e07..e9ff491c0953 100644
--- a/arch/blackfin/mach-bf533/include/mach/defBF532.h
+++ b/arch/blackfin/mach-bf533/include/mach/defBF532.h
@@ -370,72 +370,6 @@
 /* System MMR Register Bits */
 /******************************************************************************* */
 
-/* ********************* PLL AND RESET MASKS ************************ */
-
-/* PLL_CTL Masks */
-#define PLL_CLKIN                       0x0000  /* Pass CLKIN to PLL */
-#define PLL_CLKIN_DIV2                  0x0001  /* Pass CLKIN/2 to PLL */
-#define DF                              0x0001  /* 0: PLL = CLKIN, 1: PLL = CLKIN/2                                     */
-#define PLL_OFF                         0x0002  /* Shut off PLL clocks */
-#define STOPCK_OFF                      0x0008  /* Core clock off */
-#define STOPCK                          0x0008  /* Core Clock Off                                                                       */
-#define PDWN                            0x0020  /* Put the PLL in a Deep Sleep state */
-#if !defined(__ADSPBF538__)
-/* this file is included in defBF538.h but IN_DELAY/OUT_DELAY are different */
-# define IN_DELAY        0x0040  /* Add 200ps Delay To EBIU Input Latches */
-# define OUT_DELAY       0x0080  /* Add 200ps Delay To EBIU Output Signals */
-#endif
-#define BYPASS                          0x0100  /* Bypass the PLL */
-/* PLL_CTL Macros (Only Use With Logic OR While Setting Lower Order Bits)                       */
-#define SET_MSEL(x)             (((x)&0x3F) << 0x9)     /* Set MSEL = 0-63 --> VCO = CLKIN*MSEL         */
-
-/* PLL_DIV Masks */
-#define SSEL                            0x000F  /* System Select                                                */
-#define CSEL                            0x0030  /* Core Select                                                  */
-
-#define SCLK_DIV(x)  (x)        /* SCLK = VCO / x */
-
-#define CCLK_DIV1              0x00000000       /* CCLK = VCO / 1 */
-#define CCLK_DIV2              0x00000010       /* CCLK = VCO / 2 */
-#define CCLK_DIV4              0x00000020       /* CCLK = VCO / 4 */
-#define CCLK_DIV8              0x00000030       /* CCLK = VCO / 8 */
-/* PLL_DIV Macros                                                                                                               */
-#define SET_SSEL(x)                     ((x)&0xF)       /* Set SSEL = 0-15 --> SCLK = VCO/SSEL  */
-
-/* PLL_STAT Masks                                                                                                                                       */
-#define ACTIVE_PLLENABLED       0x0001  /* Processor In Active Mode With PLL Enabled    */
-#define FULL_ON                         0x0002  /* Processor In Full On Mode                                    */
-#define ACTIVE_PLLDISABLED      0x0004  /* Processor In Active Mode With PLL Disabled   */
-#define PLL_LOCKED                      0x0020  /* PLL_LOCKCNT Has Been Reached                                 */
-
-/* VR_CTL Masks                                                                                                                                 */
-#define FREQ                    0x0003  /* Switching Oscillator Frequency For Regulator */
-#define HIBERNATE               0x0000  /*              Powerdown/Bypass On-Board Regulation    */
-#define FREQ_333                0x0001  /*              Switching Frequency Is 333 kHz                  */
-#define FREQ_667                0x0002  /*              Switching Frequency Is 667 kHz                  */
-#define FREQ_1000               0x0003  /*              Switching Frequency Is 1 MHz                    */
-
-#define GAIN                    0x000C  /* Voltage Level Gain   */
-#define GAIN_5                  0x0000  /*              GAIN = 5                */
-#define GAIN_10                 0x0004  /*              GAIN = 10               */
-#define GAIN_20                 0x0008  /*              GAIN = 20               */
-#define GAIN_50                 0x000C  /*              GAIN = 50               */
-
-#define VLEV                    0x00F0  /* Internal Voltage Level                                       */
-#define VLEV_085                0x0060  /*              VLEV = 0.85 V (-5% - +10% Accuracy)     */
-#define VLEV_090                0x0070  /*              VLEV = 0.90 V (-5% - +10% Accuracy)     */
-#define VLEV_095                0x0080  /*              VLEV = 0.95 V (-5% - +10% Accuracy)     */
-#define VLEV_100                0x0090  /*              VLEV = 1.00 V (-5% - +10% Accuracy)     */
-#define VLEV_105                0x00A0  /*              VLEV = 1.05 V (-5% - +10% Accuracy)     */
-#define VLEV_110                0x00B0  /*              VLEV = 1.10 V (-5% - +10% Accuracy)     */
-#define VLEV_115                0x00C0  /*              VLEV = 1.15 V (-5% - +10% Accuracy)     */
-#define VLEV_120                0x00D0  /*              VLEV = 1.20 V (-5% - +10% Accuracy)     */
-#define VLEV_125                0x00E0  /*              VLEV = 1.25 V (-5% - +10% Accuracy)     */
-#define VLEV_130                0x00F0  /*              VLEV = 1.30 V (-5% - +10% Accuracy)     */
-
-#define WAKE                    0x0100  /* Enable RTC/Reset Wakeup From Hibernate       */
-#define SCKELOW                 0x8000  /* Do Not Drive SCKE High During Reset After Hibernate */
-
 /* CHIPID Masks */
 #define CHIPID_VERSION         0xF0000000
 #define CHIPID_FAMILY          0x0FFFF000
@@ -703,54 +637,7 @@
 
 /* **********  DMA CONTROLLER MASKS  *********************8 */
 
-/*DMAx_CONFIG, MDMA_yy_CONFIG Masks */
-#define DMAEN           0x00000001      /* Channel Enable */
-#define WNR             0x00000002      /* Channel Direction (W/R*) */
-#define WDSIZE_8        0x00000000      /* Word Size 8 bits */
-#define WDSIZE_16       0x00000004      /* Word Size 16 bits */
-#define WDSIZE_32       0x00000008      /* Word Size 32 bits */
-#define DMA2D           0x00000010      /* 2D/1D* Mode */
-#define RESTART         0x00000020      /* Restart */
-#define DI_SEL          0x00000040      /* Data Interrupt Select */
-#define DI_EN           0x00000080      /* Data Interrupt Enable */
-#define NDSIZE_0                0x0000  /* Next Descriptor Size = 0 (Stop/Autobuffer)   */
-#define NDSIZE_1                0x0100  /* Next Descriptor Size = 1                                             */
-#define NDSIZE_2                0x0200  /* Next Descriptor Size = 2                                             */
-#define NDSIZE_3                0x0300  /* Next Descriptor Size = 3                                             */
-#define NDSIZE_4                0x0400  /* Next Descriptor Size = 4                                             */
-#define NDSIZE_5                0x0500  /* Next Descriptor Size = 5                                             */
-#define NDSIZE_6                0x0600  /* Next Descriptor Size = 6                                             */
-#define NDSIZE_7                0x0700  /* Next Descriptor Size = 7                                             */
-#define NDSIZE_8                0x0800  /* Next Descriptor Size = 8                                             */
-#define NDSIZE_9                0x0900  /* Next Descriptor Size = 9                                             */
-#define NDSIZE          0x00000900      /* Next Descriptor Size */
-#define DMAFLOW         0x00007000      /* Flow Control */
-#define DMAFLOW_STOP            0x0000  /* Stop Mode */
-#define DMAFLOW_AUTO            0x1000  /* Autobuffer Mode */
-#define DMAFLOW_ARRAY           0x4000  /* Descriptor Array Mode */
-#define DMAFLOW_SMALL           0x6000  /* Small Model Descriptor List Mode */
-#define DMAFLOW_LARGE           0x7000  /* Large Model Descriptor List Mode */
-
-#define DMAEN_P                 0       /* Channel Enable */
-#define WNR_P                   1       /* Channel Direction (W/R*) */
-#define DMA2D_P                 4       /* 2D/1D* Mode */
-#define RESTART_P               5       /* Restart */
-#define DI_SEL_P                6       /* Data Interrupt Select */
-#define DI_EN_P                 7       /* Data Interrupt Enable */
-
-/*DMAx_IRQ_STATUS, MDMA_yy_IRQ_STATUS Masks */
-
-#define DMA_DONE                0x00000001      /* DMA Done Indicator */
-#define DMA_ERR                 0x00000002      /* DMA Error Indicator */
-#define DFETCH                  0x00000004      /* Descriptor Fetch Indicator */
-#define DMA_RUN                 0x00000008      /* DMA Running Indicator */
-
-#define DMA_DONE_P              0       /* DMA Done Indicator */
-#define DMA_ERR_P               1       /* DMA Error Indicator */
-#define DFETCH_P                2       /* Descriptor Fetch Indicator */
-#define DMA_RUN_P               3       /* DMA Running Indicator */
-
-/*DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP Masks */
+/* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP Masks */
 
 #define CTYPE               0x00000040  /* DMA Channel Type Indicator */
 #define CTYPE_P             6   /* DMA Channel Type Indicator BIT POSITION */
diff --git a/arch/blackfin/mach-bf537/boards/pnav10.c b/arch/blackfin/mach-bf537/boards/pnav10.c
index 9ba290466b56..4e0afda472ab 100644
--- a/arch/blackfin/mach-bf537/boards/pnav10.c
+++ b/arch/blackfin/mach-bf537/boards/pnav10.c
@@ -13,9 +13,6 @@
 #include <linux/mtd/partitions.h>
 #include <linux/spi/spi.h>
 #include <linux/spi/flash.h>
-#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
-#include <linux/usb/isp1362.h>
-#endif
 #include <linux/irq.h>
 #include <asm/dma.h>
 #include <asm/bfin5xx_spi.h>
@@ -147,45 +144,6 @@ static struct platform_device sl811_hcd_device = {
 };
 #endif
 
-#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
-static struct resource isp1362_hcd_resources[] = {
-        {
-                .start = 0x20360000,
-                .end = 0x20360000,
-                .flags = IORESOURCE_MEM,
-        }, {
-                .start = 0x20360004,
-                .end = 0x20360004,
-                .flags = IORESOURCE_MEM,
-        }, {
-                .start = CONFIG_USB_ISP1362_BFIN_GPIO_IRQ,
-                .end = CONFIG_USB_ISP1362_BFIN_GPIO_IRQ,
-                .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
-        },
-};
-
-static struct isp1362_platform_data isp1362_priv = {
-        .sel15Kres = 1,
-        .clknotstop = 0,
-        .oc_enable = 0,
-        .int_act_high = 0,
-        .int_edge_triggered = 0,
-        .remote_wakeup_connected = 0,
-        .no_power_switching = 1,
-        .power_switching_mode = 0,
-};
-
-static struct platform_device isp1362_hcd_device = {
-        .name = "isp1362-hcd",
-        .id = 0,
-        .dev = {
-                .platform_data = &isp1362_priv,
-        },
-        .num_resources = ARRAY_SIZE(isp1362_hcd_resources),
-        .resource = isp1362_hcd_resources,
-};
-#endif
-
 #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
 static struct platform_device bfin_mii_bus = {
         .name = "bfin_mii_bus",
@@ -492,10 +450,6 @@ static struct platform_device *stamp_devices[] __initdata = {
         &sl811_hcd_device,
 #endif
 
-#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
-        &isp1362_hcd_device,
-#endif
-
 #if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
         &smc91x_device,
 #endif
diff --git a/arch/blackfin/mach-bf537/boards/stamp.c b/arch/blackfin/mach-bf537/boards/stamp.c
index c46baa5e6d9b..ac9b52e0087c 100644
--- a/arch/blackfin/mach-bf537/boards/stamp.c
+++ b/arch/blackfin/mach-bf537/boards/stamp.c
@@ -9,6 +9,7 @@
 #include <linux/device.h>
 #include <linux/kernel.h>
 #include <linux/platform_device.h>
+#include <linux/io.h>
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/nand.h>
 #include <linux/mtd/partitions.h>
@@ -25,6 +26,8 @@
 #include <linux/i2c.h>
 #include <linux/usb/sl811.h>
 #include <linux/spi/mmc_spi.h>
+#include <linux/leds.h>
+#include <linux/input.h>
 #include <asm/dma.h>
 #include <asm/bfin5xx_spi.h>
 #include <asm/reboot.h>
@@ -65,7 +68,7 @@ static struct isp1760_platform_data isp1760_priv = {
 };
 
 static struct platform_device bfin_isp1760_device = {
-        .name           = "isp1760-hcd",
+        .name           = "isp1760",
         .id             = 0,
         .dev = {
                 .platform_data = &isp1760_priv,
@@ -76,7 +79,6 @@ static struct platform_device bfin_isp1760_device = {
 #endif
 
 #if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
-#include <linux/input.h>
 #include <linux/gpio_keys.h>
 
 static struct gpio_keys_button bfin_gpio_keys_table[] = {
@@ -195,28 +197,6 @@ static struct platform_device dm9000_device = {
 };
 #endif
 
-#if defined(CONFIG_AX88180) || defined(CONFIG_AX88180_MODULE)
-static struct resource ax88180_resources[] = {
-        [0] = {
-                .start  = 0x20300000,
-                .end    = 0x20300000 + 0x8000,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = IRQ_PF7,
-                .end    = IRQ_PF7,
-                .flags  = (IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL),
-        },
-};
-
-static struct platform_device ax88180_device = {
-        .name           = "ax88180",
-        .id             = -1,
-        .num_resources  = ARRAY_SIZE(ax88180_resources),
-        .resource       = ax88180_resources,
-};
-#endif
-
 #if defined(CONFIG_USB_SL811_HCD) || defined(CONFIG_USB_SL811_HCD_MODULE)
 static struct resource sl811_hcd_resources[] = {
         {
@@ -272,8 +252,8 @@ static struct resource isp1362_hcd_resources[] = {
                 .end = 0x20360004,
                 .flags = IORESOURCE_MEM,
         }, {
-                .start = CONFIG_USB_ISP1362_BFIN_GPIO_IRQ,
-                .end = CONFIG_USB_ISP1362_BFIN_GPIO_IRQ,
+                .start = IRQ_PF3,
+                .end = IRQ_PF3,
                 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
         },
 };
@@ -300,6 +280,44 @@ static struct platform_device isp1362_hcd_device = {
 };
 #endif
 
+#if defined(CONFIG_CAN_BFIN) || defined(CONFIG_CAN_BFIN_MODULE)
+unsigned short bfin_can_peripherals[] = {
+        P_CAN0_RX, P_CAN0_TX, 0
+};
+
+static struct resource bfin_can_resources[] = {
+        {
+                .start = 0xFFC02A00,
+                .end = 0xFFC02FFF,
+                .flags = IORESOURCE_MEM,
+        },
+        {
+                .start = IRQ_CAN_RX,
+                .end = IRQ_CAN_RX,
+                .flags = IORESOURCE_IRQ,
+        },
+        {
+                .start = IRQ_CAN_TX,
+                .end = IRQ_CAN_TX,
+                .flags = IORESOURCE_IRQ,
+        },
+        {
+                .start = IRQ_CAN_ERROR,
+                .end = IRQ_CAN_ERROR,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device bfin_can_device = {
+        .name = "bfin_can",
+        .num_resources = ARRAY_SIZE(bfin_can_resources),
+        .resource = bfin_can_resources,
+        .dev = {
+                .platform_data = &bfin_can_peripherals, /* Passed to driver */
+        },
+};
+#endif
+
 #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
 static struct platform_device bfin_mii_bus = {
         .name = "bfin_mii_bus",
@@ -514,15 +532,14 @@ static struct bfin5xx_spi_chip ad1938_spi_chip_info = {
 };
 #endif
 
-#if defined(CONFIG_INPUT_EVAL_AD7147EBZ)
-#include <linux/input.h>
+#if defined(CONFIG_INPUT_AD714X_SPI) || defined(CONFIG_INPUT_AD714X_SPI_MODULE)
 #include <linux/input/ad714x.h>
 static struct bfin5xx_spi_chip ad7147_spi_chip_info = {
         .enable_dma = 0,
         .bits_per_word = 16,
 };
 
-static struct ad714x_slider_plat slider_plat[] = {
+static struct ad714x_slider_plat ad7147_spi_slider_plat[] = {
         {
                 .start_stage = 0,
                 .end_stage = 7,
@@ -530,7 +547,7 @@ static struct ad714x_slider_plat slider_plat[] = {
         },
 };
 
-static struct ad714x_button_plat button_plat[] = {
+static struct ad714x_button_plat ad7147_spi_button_plat[] = {
         {
                 .keycode = BTN_FORWARD,
                 .l_mask = 0,
@@ -557,11 +574,11 @@ static struct ad714x_button_plat button_plat[] = {
                 .h_mask = 0x400,
         },
 };
-static struct ad714x_platform_data ad7147_platfrom_data = {
+static struct ad714x_platform_data ad7147_spi_platform_data = {
         .slider_num = 1,
         .button_num = 5,
-        .slider = slider_plat,
-        .button = button_plat,
+        .slider = ad7147_spi_slider_plat,
+        .button = ad7147_spi_button_plat,
         .stage_cfg_reg =  {
                 {0xFBFF, 0x1FFF, 0, 0x2626, 1600, 1600, 1600, 1600},
                 {0xEFFF, 0x1FFF, 0, 0x2626, 1650, 1650, 1650, 1650},
@@ -580,10 +597,9 @@ static struct ad714x_platform_data ad7147_platfrom_data = {
 };
 #endif
 
-#if defined(CONFIG_INPUT_EVAL_AD7142EB)
-#include <linux/input.h>
+#if defined(CONFIG_INPUT_AD714X_I2C) || defined(CONFIG_INPUT_AD714X_I2C_MODULE)
 #include <linux/input/ad714x.h>
-static struct ad714x_button_plat button_plat[] = {
+static struct ad714x_button_plat ad7142_i2c_button_plat[] = {
         {
                 .keycode = BTN_1,
                 .l_mask = 0,
@@ -605,9 +621,9 @@ static struct ad714x_button_plat button_plat[] = {
                 .h_mask = 0x8,
         },
 };
-static struct ad714x_platform_data ad7142_platfrom_data = {
+static struct ad714x_platform_data ad7142_i2c_platform_data = {
         .button_num = 4,
-        .button = button_plat,
+        .button = ad7142_i2c_button_plat,
         .stage_cfg_reg =  {
                 /* fixme: figure out right setting for all comoponent according
                  * to hardware feature of EVAL-AD7142EB board */
@@ -696,8 +712,7 @@ static const struct ad7879_platform_data bfin_ad7879_ts_info = {
 #endif
 
 #if defined(CONFIG_INPUT_ADXL34X) || defined(CONFIG_INPUT_ADXL34X_MODULE)
-#include <linux/input.h>
-#include <linux/spi/adxl34x.h>
+#include <linux/input/adxl34x.h>
 static const struct adxl34x_platform_data adxl34x_info = {
         .x_axis_offset = 0,
         .y_axis_offset = 0,
@@ -721,9 +736,7 @@ static const struct adxl34x_platform_data adxl34x_info = {
         .ev_code_y = ABS_Y,             /* EV_REL */
         .ev_code_z = ABS_Z,             /* EV_REL */
 
-        .ev_code_tap_x = BTN_TOUCH,             /* EV_KEY */
-        .ev_code_tap_y = BTN_TOUCH,             /* EV_KEY */
-        .ev_code_tap_z = BTN_TOUCH,             /* EV_KEY */
+        .ev_code_tap = {BTN_TOUCH, BTN_TOUCH, BTN_TOUCH}, /* EV_KEY x,y,z */
 
 /*      .ev_code_ff = KEY_F,*/          /* EV_KEY */
 /*      .ev_code_act_inactivity = KEY_A,*/      /* EV_KEY */
@@ -761,6 +774,47 @@ static struct bfin5xx_spi_chip enc28j60_spi_chip_info = {
 };
 #endif
 
+#if defined(CONFIG_ADF702X) || defined(CONFIG_ADF702X_MODULE)
+static struct bfin5xx_spi_chip adf7021_spi_chip_info = {
+        .bits_per_word = 16,
+        .cs_gpio = GPIO_PF10,
+};
+
+#include <linux/spi/adf702x.h>
+#define TXREG 0x0160A470
+static const u32 adf7021_regs[] = {
+        0x09608FA0,
+        0x00575011,
+        0x00A7F092,
+        0x2B141563,
+        0x81F29E94,
+        0x00003155,
+        0x050A4F66,
+        0x00000007,
+        0x00000008,
+        0x000231E9,
+        0x3296354A,
+        0x891A2B3B,
+        0x00000D9C,
+        0x0000000D,
+        0x0000000E,
+        0x0000000F,
+};
+
+static struct adf702x_platform_data adf7021_platform_data = {
+        .regs_base = (void *)SPORT1_TCR1,
+        .dma_ch_rx = CH_SPORT1_RX,
+        .dma_ch_tx = CH_SPORT1_TX,
+        .irq_sport_err = IRQ_SPORT1_ERROR,
+        .gpio_int_rfs = GPIO_PF8,
+        .pin_req = {P_SPORT1_DTPRI, P_SPORT1_RFS, P_SPORT1_DRPRI,
+                        P_SPORT1_RSCLK, P_SPORT1_TSCLK, 0},
+        .adf702x_model = MODEL_ADF7021,
+        .adf702x_regs = adf7021_regs,
+        .tx_reg = TXREG,
+};
+#endif
+
 #if defined(CONFIG_MTD_DATAFLASH) \
         || defined(CONFIG_MTD_DATAFLASH_MODULE)
 
@@ -794,6 +848,13 @@ static struct bfin5xx_spi_chip data_flash_chip_info = {
 };
 #endif
 
+#if defined(CONFIG_INPUT_ADXL34X_SPI) || defined(CONFIG_INPUT_ADXL34X_SPI_MODULE)
+static struct bfin5xx_spi_chip spi_adxl34x_chip_info = {
+        .enable_dma = 0,         /* use dma transfer with this chip*/
+        .bits_per_word = 8,
+};
+#endif
+
 static struct spi_board_info bfin_spi_board_info[] __initdata = {
 #if defined(CONFIG_MTD_M25P80) \
         || defined(CONFIG_MTD_M25P80_MODULE)
@@ -855,7 +916,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
         },
 #endif
 
-#if defined(CONFIG_INPUT_EVAL_AD7147EBZ)
+#if defined(CONFIG_INPUT_AD714X_SPI) || defined(CONFIG_INPUT_AD714X_SPI_MODULE)
         {
                 .modalias = "ad714x_captouch",
                 .max_speed_hz = 1000000,     /* max spi clock (SCK) speed in HZ */
@@ -863,7 +924,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
                 .bus_num = 0,
                 .chip_select = 5,
                 .mode = SPI_MODE_3,
-                .platform_data = &ad7147_platfrom_data,
+                .platform_data = &ad7147_spi_platform_data,
                 .controller_data = &ad7147_spi_chip_info,
         },
 #endif
@@ -932,6 +993,30 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
                 .mode = SPI_MODE_0,
         },
 #endif
+#if defined(CONFIG_INPUT_ADXL34X_SPI) || defined(CONFIG_INPUT_ADXL34X_SPI_MODULE)
+        {
+                .modalias       = "adxl34x",
+                .platform_data  = &adxl34x_info,
+                .irq            = IRQ_PF6,
+                .max_speed_hz   = 5000000,    /* max spi clock (SCK) speed in HZ */
+                .bus_num        = 0,
+                .chip_select    = 2,
+                .controller_data = &spi_adxl34x_chip_info,
+                .mode = SPI_MODE_3,
+        },
+#endif
+#if defined(CONFIG_ADF702X) || defined(CONFIG_ADF702X_MODULE)
+        {
+                .modalias = "adf702x",
+                .max_speed_hz = 16000000,     /* max spi clock (SCK) speed in HZ */
+                .bus_num = 0,
+                .chip_select = 0,       /* GPIO controlled SSEL */
+                .controller_data = &adf7021_spi_chip_info,
+                .platform_data = &adf7021_platform_data,
+                .mode = SPI_MODE_0,
+        },
+#endif
+
 };
 
 #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
@@ -1175,7 +1260,6 @@ static struct platform_device i2c_bfin_twi_device = {
 #endif
 
 #if defined(CONFIG_KEYBOARD_ADP5588) || defined(CONFIG_KEYBOARD_ADP5588_MODULE)
-#include <linux/input.h>
 #include <linux/i2c/adp5588.h>
 static const unsigned short adp5588_keymap[ADP5588_KEYMAPSIZE] = {
         [0]      = KEY_GRAVE,
@@ -1268,35 +1352,33 @@ static struct adp5588_kpad_platform_data adp5588_kpad_data = {
          *  ADP5520/5501 Backlight Data
          */
 
-static struct adp5520_backlight_platfrom_data adp5520_backlight_data = {
-        .fade_in                = FADE_T_1200ms,
-        .fade_out               = FADE_T_1200ms,
-        .fade_led_law           = BL_LAW_LINEAR,
-        .en_ambl_sens           = 1,
-        .abml_filt              = BL_AMBL_FILT_640ms,
-        .l1_daylight_max        = BL_CUR_mA(15),
-        .l1_daylight_dim        = BL_CUR_mA(0),
-        .l2_office_max          = BL_CUR_mA(7),
-        .l2_office_dim          = BL_CUR_mA(0),
-        .l3_dark_max            = BL_CUR_mA(3),
-        .l3_dark_dim            = BL_CUR_mA(0),
-        .l2_trip                = L2_COMP_CURR_uA(700),
-        .l2_hyst                = L2_COMP_CURR_uA(50),
-        .l3_trip                = L3_COMP_CURR_uA(80),
-        .l3_hyst                = L3_COMP_CURR_uA(20),
+static struct adp5520_backlight_platform_data adp5520_backlight_data = {
+        .fade_in                = ADP5520_FADE_T_1200ms,
+        .fade_out               = ADP5520_FADE_T_1200ms,
+        .fade_led_law           = ADP5520_BL_LAW_LINEAR,
+        .en_ambl_sens           = 1,
+        .abml_filt              = ADP5520_BL_AMBL_FILT_640ms,
+        .l1_daylight_max        = ADP5520_BL_CUR_mA(15),
+        .l1_daylight_dim        = ADP5520_BL_CUR_mA(0),
+        .l2_office_max          = ADP5520_BL_CUR_mA(7),
+        .l2_office_dim          = ADP5520_BL_CUR_mA(0),
+        .l3_dark_max            = ADP5520_BL_CUR_mA(3),
+        .l3_dark_dim            = ADP5520_BL_CUR_mA(0),
+        .l2_trip                = ADP5520_L2_COMP_CURR_uA(700),
+        .l2_hyst                = ADP5520_L2_COMP_CURR_uA(50),
+        .l3_trip                = ADP5520_L3_COMP_CURR_uA(80),
+        .l3_hyst                = ADP5520_L3_COMP_CURR_uA(20),
 };
 
         /*
          *  ADP5520/5501 LEDs Data
          */
 
-#include <linux/leds.h>
-
 static struct led_info adp5520_leds[] = {
         {
                 .name = "adp5520-led1",
                 .default_trigger = "none",
-                .flags = FLAG_ID_ADP5520_LED1_ADP5501_LED0 | LED_OFFT_600ms,
+                .flags = FLAG_ID_ADP5520_LED1_ADP5501_LED0 | ADP5520_LED_OFFT_600ms,
         },
 #ifdef ADP5520_EN_ALL_LEDS
         {
@@ -1312,51 +1394,50 @@ static struct led_info adp5520_leds[] = {
 #endif
 };
 
-static struct adp5520_leds_platfrom_data adp5520_leds_data = {
+static struct adp5520_leds_platform_data adp5520_leds_data = {
         .num_leds = ARRAY_SIZE(adp5520_leds),
         .leds = adp5520_leds,
-        .fade_in = FADE_T_600ms,
-        .fade_out = FADE_T_600ms,
-        .led_on_time = LED_ONT_600ms,
+        .fade_in = ADP5520_FADE_T_600ms,
+        .fade_out = ADP5520_FADE_T_600ms,
+        .led_on_time = ADP5520_LED_ONT_600ms,
 };
 
         /*
          *  ADP5520 GPIO Data
          */
 
-static struct adp5520_gpio_platfrom_data adp5520_gpio_data = {
+static struct adp5520_gpio_platform_data adp5520_gpio_data = {
         .gpio_start = 50,
-        .gpio_en_mask = GPIO_C1 | GPIO_C2 | GPIO_R2,
-        .gpio_pullup_mask = GPIO_C1 | GPIO_C2 | GPIO_R2,
+        .gpio_en_mask = ADP5520_GPIO_C1 | ADP5520_GPIO_C2 | ADP5520_GPIO_R2,
+        .gpio_pullup_mask = ADP5520_GPIO_C1 | ADP5520_GPIO_C2 | ADP5520_GPIO_R2,
 };
 
         /*
          *  ADP5520 Keypad Data
          */
 
-#include <linux/input.h>
 static const unsigned short adp5520_keymap[ADP5520_KEYMAPSIZE] = {
-        [KEY(0, 0)]     = KEY_GRAVE,
-        [KEY(0, 1)]     = KEY_1,
-        [KEY(0, 2)]     = KEY_2,
-        [KEY(0, 3)]     = KEY_3,
-        [KEY(1, 0)]     = KEY_4,
-        [KEY(1, 1)]     = KEY_5,
-        [KEY(1, 2)]     = KEY_6,
-        [KEY(1, 3)]     = KEY_7,
-        [KEY(2, 0)]     = KEY_8,
-        [KEY(2, 1)]     = KEY_9,
-        [KEY(2, 2)]     = KEY_0,
-        [KEY(2, 3)]     = KEY_MINUS,
-        [KEY(3, 0)]     = KEY_EQUAL,
-        [KEY(3, 1)]     = KEY_BACKSLASH,
-        [KEY(3, 2)]     = KEY_BACKSPACE,
-        [KEY(3, 3)]     = KEY_ENTER,
-};
-
-static struct adp5520_keys_platfrom_data adp5520_keys_data = {
-        .rows_en_mask   = ROW_R3 | ROW_R2 | ROW_R1 | ROW_R0,
-        .cols_en_mask   = COL_C3 | COL_C2 | COL_C1 | COL_C0,
+        [ADP5520_KEY(0, 0)]     = KEY_GRAVE,
+        [ADP5520_KEY(0, 1)]     = KEY_1,
+        [ADP5520_KEY(0, 2)]     = KEY_2,
+        [ADP5520_KEY(0, 3)]     = KEY_3,
+        [ADP5520_KEY(1, 0)]     = KEY_4,
+        [ADP5520_KEY(1, 1)]     = KEY_5,
+        [ADP5520_KEY(1, 2)]     = KEY_6,
+        [ADP5520_KEY(1, 3)]     = KEY_7,
+        [ADP5520_KEY(2, 0)]     = KEY_8,
+        [ADP5520_KEY(2, 1)]     = KEY_9,
+        [ADP5520_KEY(2, 2)]     = KEY_0,
+        [ADP5520_KEY(2, 3)]     = KEY_MINUS,
+        [ADP5520_KEY(3, 0)]     = KEY_EQUAL,
+        [ADP5520_KEY(3, 1)]     = KEY_BACKSLASH,
+        [ADP5520_KEY(3, 2)]     = KEY_BACKSPACE,
+        [ADP5520_KEY(3, 3)]     = KEY_ENTER,
+};
+
+static struct adp5520_keys_platform_data adp5520_keys_data = {
+        .rows_en_mask   = ADP5520_ROW_R3 | ADP5520_ROW_R2 | ADP5520_ROW_R1 | ADP5520_ROW_R0,
+        .cols_en_mask   = ADP5520_COL_C3 | ADP5520_COL_C2 | ADP5520_COL_C1 | ADP5520_COL_C0,
         .keymap         = adp5520_keymap,
         .keymapsize     = ARRAY_SIZE(adp5520_keymap),
         .repeat         = 0,
@@ -1366,50 +1447,81 @@ static struct adp5520_keys_platfrom_data adp5520_keys_data = {
          *  ADP5520/5501 Multifuction Device Init Data
          */
 
-static struct adp5520_subdev_info adp5520_subdevs[] = {
-        {
-                .name = "adp5520-backlight",
-                .id = ID_ADP5520,
-                .platform_data = &adp5520_backlight_data,
-        },
-        {
-                .name = "adp5520-led",
-                .id = ID_ADP5520,
-                .platform_data = &adp5520_leds_data,
-        },
-        {
-                .name = "adp5520-gpio",
-                .id = ID_ADP5520,
-                .platform_data = &adp5520_gpio_data,
-        },
-        {
-                .name = "adp5520-keys",
-                .id = ID_ADP5520,
-                .platform_data = &adp5520_keys_data,
-        },
-};
-
 static struct adp5520_platform_data adp5520_pdev_data = {
-        .num_subdevs = ARRAY_SIZE(adp5520_subdevs),
-        .subdevs = adp5520_subdevs,
+        .backlight = &adp5520_backlight_data,
+        .leds = &adp5520_leds_data,
+        .gpio = &adp5520_gpio_data,
+        .keys = &adp5520_keys_data,
 };
 
 #endif
 
 #if defined(CONFIG_GPIO_ADP5588) || defined(CONFIG_GPIO_ADP5588_MODULE)
 #include <linux/i2c/adp5588.h>
-static struct adp5588_gpio_platfrom_data adp5588_gpio_data = {
+static struct adp5588_gpio_platform_data adp5588_gpio_data = {
         .gpio_start = 50,
         .pullup_dis_mask = 0,
 };
 #endif
 
+#if defined(CONFIG_BACKLIGHT_ADP8870) || defined(CONFIG_BACKLIGHT_ADP8870_MODULE)
+#include <linux/i2c/adp8870.h>
+static struct led_info adp8870_leds[] = {
+        {
+                .name = "adp8870-led7",
+                .default_trigger = "none",
+                .flags = ADP8870_LED_D7 | ADP8870_LED_OFFT_600ms,
+        },
+};
+
+
+static struct adp8870_backlight_platform_data adp8870_pdata = {
+        .bl_led_assign = ADP8870_BL_D1 | ADP8870_BL_D2 | ADP8870_BL_D3 |
+                         ADP8870_BL_D4 | ADP8870_BL_D5 | ADP8870_BL_D6, /* 1 = Backlight 0 = Individual LED */
+        .pwm_assign = 0,                                /* 1 = Enables PWM mode */
+
+        .bl_fade_in = ADP8870_FADE_T_1200ms,            /* Backlight Fade-In Timer */
+        .bl_fade_out = ADP8870_FADE_T_1200ms,           /* Backlight Fade-Out Timer */
+        .bl_fade_law = ADP8870_FADE_LAW_CUBIC1,         /* fade-on/fade-off transfer characteristic */
+
+        .en_ambl_sens = 1,                              /* 1 = enable ambient light sensor */
+        .abml_filt = ADP8870_BL_AMBL_FILT_320ms,        /* Light sensor filter time */
+
+        .l1_daylight_max = ADP8870_BL_CUR_mA(20),       /* use BL_CUR_mA(I) 0 <= I <= 30 mA */
+        .l1_daylight_dim = ADP8870_BL_CUR_mA(0),        /* typ = 0, use BL_CUR_mA(I) 0 <= I <= 30 mA */
+        .l2_bright_max = ADP8870_BL_CUR_mA(14),         /* use BL_CUR_mA(I) 0 <= I <= 30 mA */
+        .l2_bright_dim = ADP8870_BL_CUR_mA(0),          /* typ = 0, use BL_CUR_mA(I) 0 <= I <= 30 mA */
+        .l3_office_max = ADP8870_BL_CUR_mA(6),          /* use BL_CUR_mA(I) 0 <= I <= 30 mA */
+        .l3_office_dim = ADP8870_BL_CUR_mA(0),          /* typ = 0, use BL_CUR_mA(I) 0 <= I <= 30 mA */
+        .l4_indoor_max = ADP8870_BL_CUR_mA(3),          /* use BL_CUR_mA(I) 0 <= I <= 30 mA */
+        .l4_indor_dim = ADP8870_BL_CUR_mA(0),           /* typ = 0, use BL_CUR_mA(I) 0 <= I <= 30 mA */
+        .l5_dark_max = ADP8870_BL_CUR_mA(2),            /* use BL_CUR_mA(I) 0 <= I <= 30 mA */
+        .l5_dark_dim = ADP8870_BL_CUR_mA(0),            /* typ = 0, use BL_CUR_mA(I) 0 <= I <= 30 mA */
+
+        .l2_trip = ADP8870_L2_COMP_CURR_uA(710),        /* use L2_COMP_CURR_uA(I) 0 <= I <= 1106 uA */
+        .l2_hyst = ADP8870_L2_COMP_CURR_uA(73),         /* use L2_COMP_CURR_uA(I) 0 <= I <= 1106 uA */
+        .l3_trip = ADP8870_L3_COMP_CURR_uA(389),        /* use L3_COMP_CURR_uA(I) 0 <= I <= 551 uA */
+        .l3_hyst = ADP8870_L3_COMP_CURR_uA(54),         /* use L3_COMP_CURR_uA(I) 0 <= I <= 551 uA */
+        .l4_trip = ADP8870_L4_COMP_CURR_uA(167),        /* use L4_COMP_CURR_uA(I) 0 <= I <= 275 uA */
+        .l4_hyst = ADP8870_L4_COMP_CURR_uA(16),         /* use L4_COMP_CURR_uA(I) 0 <= I <= 275 uA */
+        .l5_trip = ADP8870_L5_COMP_CURR_uA(43),         /* use L5_COMP_CURR_uA(I) 0 <= I <= 138 uA */
+        .l5_hyst = ADP8870_L5_COMP_CURR_uA(11),         /* use L6_COMP_CURR_uA(I) 0 <= I <= 138 uA */
+
+        .leds = adp8870_leds,
+        .num_leds = ARRAY_SIZE(adp8870_leds),
+        .led_fade_law = ADP8870_FADE_LAW_SQUARE,        /* fade-on/fade-off transfer characteristic */
+        .led_fade_in = ADP8870_FADE_T_600ms,
+        .led_fade_out = ADP8870_FADE_T_600ms,
+        .led_on_time = ADP8870_LED_ONT_200ms,
+};
+#endif
+
 static struct i2c_board_info __initdata bfin_i2c_board_info[] = {
-#if defined(CONFIG_INPUT_EVAL_AD7142EB)
+#if defined(CONFIG_INPUT_AD714X_I2C) || defined(CONFIG_INPUT_AD714X_I2C_MODULE)
         {
                 I2C_BOARD_INFO("ad7142_captouch", 0x2C),
                 .irq = IRQ_PG5,
-                .platform_data = (void *)&ad7142_platfrom_data,
+                .platform_data = (void *)&ad7142_i2c_platform_data,
         },
 #endif
 #if defined(CONFIG_BFIN_TWI_LCD) || defined(CONFIG_BFIN_TWI_LCD_MODULE)
@@ -1462,6 +1574,32 @@ static struct i2c_board_info __initdata bfin_i2c_board_info[] = {
                 I2C_BOARD_INFO("bfin-adv7393", 0x2B),
         },
 #endif
+#if defined(CONFIG_FB_BF537_LQ035) || defined(CONFIG_FB_BF537_LQ035_MODULE)
+        {
+                I2C_BOARD_INFO("bf537-lq035-ad5280", 0x2C),
+        },
+#endif
+#if defined(CONFIG_BACKLIGHT_ADP8870) || defined(CONFIG_BACKLIGHT_ADP8870_MODULE)
+        {
+                I2C_BOARD_INFO("adp8870", 0x2B),
+                .platform_data = (void *)&adp8870_pdata,
+        },
+#endif
+#if defined(CONFIG_SND_SOC_ADAU1371) || defined(CONFIG_SND_SOC_ADAU1371_MODULE)
+        {
+                I2C_BOARD_INFO("adau1371", 0x1A),
+        },
+#endif
+#if defined(CONFIG_SND_SOC_ADAU1761) || defined(CONFIG_SND_SOC_ADAU1761_MODULE)
+        {
+                I2C_BOARD_INFO("adau1761", 0x38),
+        },
+#endif
+#if defined(CONFIG_AD525X_DPOT) || defined(CONFIG_AD525X_DPOT_MODULE)
+        {
+                I2C_BOARD_INFO("ad5258", 0x18),
+        },
+#endif
 };
 
 #if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
@@ -1602,8 +1740,8 @@ static struct platform_device *stamp_devices[] __initdata = {
         &dm9000_device,
 #endif
 
-#if defined(CONFIG_AX88180) || defined(CONFIG_AX88180_MODULE)
-        &ax88180_device,
+#if defined(CONFIG_CAN_BFIN) || defined(CONFIG_CAN_BFIN_MODULE)
+        &bfin_can_device,
 #endif
 
 #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
diff --git a/arch/blackfin/mach-bf537/include/mach/bf537.h b/arch/blackfin/mach-bf537/include/mach/bf537.h
index 17fab4474669..8b291418ca32 100644
--- a/arch/blackfin/mach-bf537/include/mach/bf537.h
+++ b/arch/blackfin/mach-bf537/include/mach/bf537.h
@@ -9,16 +9,6 @@
 #ifndef __MACH_BF537_H__
 #define __MACH_BF537_H__
 
-/* Masks for generic ERROR IRQ demultiplexing used in int-priority-sc.c */
-
-#define SPI_ERR_MASK (TXCOL | RBSY | MODF | TXE)        /* SPI_STAT */
-#define SPORT_ERR_MASK (ROVF | RUVF | TOVF | TUVF)      /* SPORTx_STAT */
-#define PPI_ERR_MASK (0xFFFF & ~FLD)    /* PPI_STATUS */
-#define EMAC_ERR_MASK (PHYINT | MMCINT | RXFSINT | TXFSINT | WAKEDET | RXDMAERR | TXDMAERR | STMDONE)   /* EMAC_SYSTAT */
-#define UART_ERR_MASK_STAT1 (0x4)       /* UARTx_IIR */
-#define UART_ERR_MASK_STAT0 (0x2)       /* UARTx_IIR */
-#define CAN_ERR_MASK  (EWTIF | EWRIF | EPIF | BOIF | WUIF | UIAIF | AAIF | RMLIF | UCEIF | EXTIF | ADIF)        /* CAN_GIF */
-
 #define OFFSET_(x) ((x) & 0x0000FFFF)
 
 /*some misc defines*/
diff --git a/arch/blackfin/mach-bf537/include/mach/blackfin.h b/arch/blackfin/mach-bf537/include/mach/blackfin.h
index eab006d260c5..a12d4b6a221d 100644
--- a/arch/blackfin/mach-bf537/include/mach/blackfin.h
+++ b/arch/blackfin/mach-bf537/include/mach/blackfin.h
@@ -40,10 +40,4 @@
 #define OFFSET_SCR              0x1C    /* SCR Scratch Register                 */
 #define OFFSET_GCTL             0x24    /* Global Control Register              */
 
-/* PLL_DIV Masks                                                                                                        */
-#define CCLK_DIV1 CSEL_DIV1     /*          CCLK = VCO / 1                                  */
-#define CCLK_DIV2 CSEL_DIV2     /*          CCLK = VCO / 2                                  */
-#define CCLK_DIV4 CSEL_DIV4     /*          CCLK = VCO / 4                                  */
-#define CCLK_DIV8 CSEL_DIV8     /*          CCLK = VCO / 8                                  */
-
 #endif
diff --git a/arch/blackfin/mach-bf537/include/mach/defBF534.h b/arch/blackfin/mach-bf537/include/mach/defBF534.h
index a6d20ca57683..066d5c261f47 100644
--- a/arch/blackfin/mach-bf537/include/mach/defBF534.h
+++ b/arch/blackfin/mach-bf537/include/mach/defBF534.h
@@ -958,67 +958,6 @@
 **                              modifier UNLESS the lower order bits are saved and ORed back in when
 **                              the macro is used.
 *************************************************************************************/
-/*
-** ********************* PLL AND RESET MASKS ****************************************/
-/* PLL_CTL Masks                                                                                                                                        */
-#define DF                              0x0001  /* 0: PLL = CLKIN, 1: PLL = CLKIN/2                                     */
-#define PLL_OFF                 0x0002  /* PLL Not Powered                                                                      */
-#define STOPCK                  0x0008  /* Core Clock Off                                                                       */
-#define PDWN                    0x0020  /* Enter Deep Sleep Mode                                                        */
-#define IN_DELAY                0x0040  /* Add 200ps Delay To EBIU Input Latches                        */
-#define OUT_DELAY               0x0080  /* Add 200ps Delay To EBIU Output Signals                       */
-#define BYPASS                  0x0100  /* Bypass the PLL                                                                       */
-#define MSEL                    0x7E00  /* Multiplier Select For CCLK/VCO Factors                       */
-/* PLL_CTL Macros (Only Use With Logic OR While Setting Lower Order Bits)                       */
-#define SET_MSEL(x)             (((x)&0x3F) << 0x9)     /* Set MSEL = 0-63 --> VCO = CLKIN*MSEL         */
-
-/* PLL_DIV Masks                                                                                                                */
-#define SSEL                    0x000F  /* System Select                                                */
-#define CSEL                    0x0030  /* Core Select                                                  */
-#define CSEL_DIV1               0x0000  /*              CCLK = VCO / 1                                  */
-#define CSEL_DIV2               0x0010  /*              CCLK = VCO / 2                                  */
-#define CSEL_DIV4               0x0020  /*              CCLK = VCO / 4                                  */
-#define CSEL_DIV8               0x0030  /*              CCLK = VCO / 8                                  */
-/* PLL_DIV Macros                                                                                                               */
-#define SET_SSEL(x)             ((x)&0xF)       /* Set SSEL = 0-15 --> SCLK = VCO/SSEL  */
-
-/* VR_CTL Masks                                                                                                                                 */
-#define FREQ                    0x0003  /* Switching Oscillator Frequency For Regulator */
-#define HIBERNATE               0x0000  /*              Powerdown/Bypass On-Board Regulation    */
-#define FREQ_333                0x0001  /*              Switching Frequency Is 333 kHz                  */
-#define FREQ_667                0x0002  /*              Switching Frequency Is 667 kHz                  */
-#define FREQ_1000               0x0003  /*              Switching Frequency Is 1 MHz                    */
-
-#define GAIN                    0x000C  /* Voltage Level Gain   */
-#define GAIN_5                  0x0000  /*              GAIN = 5                */
-#define GAIN_10                 0x0004  /*              GAIN = 10               */
-#define GAIN_20                 0x0008  /*              GAIN = 20               */
-#define GAIN_50                 0x000C  /*              GAIN = 50               */
-
-#define VLEV                    0x00F0  /* Internal Voltage Level                                       */
-#define VLEV_085                0x0060  /*              VLEV = 0.85 V (-5% - +10% Accuracy)     */
-#define VLEV_090                0x0070  /*              VLEV = 0.90 V (-5% - +10% Accuracy)     */
-#define VLEV_095                0x0080  /*              VLEV = 0.95 V (-5% - +10% Accuracy)     */
-#define VLEV_100                0x0090  /*              VLEV = 1.00 V (-5% - +10% Accuracy)     */
-#define VLEV_105                0x00A0  /*              VLEV = 1.05 V (-5% - +10% Accuracy)     */
-#define VLEV_110                0x00B0  /*              VLEV = 1.10 V (-5% - +10% Accuracy)     */
-#define VLEV_115                0x00C0  /*              VLEV = 1.15 V (-5% - +10% Accuracy)     */
-#define VLEV_120                0x00D0  /*              VLEV = 1.20 V (-5% - +10% Accuracy)     */
-#define VLEV_125                0x00E0  /*              VLEV = 1.25 V (-5% - +10% Accuracy)     */
-#define VLEV_130                0x00F0  /*              VLEV = 1.30 V (-5% - +10% Accuracy)     */
-
-#define WAKE                    0x0100  /* Enable RTC/Reset Wakeup From Hibernate       */
-#define CANWE                   0x0200  /* Enable CAN Wakeup From Hibernate                     */
-#define PHYWE                   0x0400  /* Enable PHY Wakeup From Hibernate                     */
-#define CLKBUFOE                0x4000  /* CLKIN Buffer Output Enable */
-#define PHYCLKOE                CLKBUFOE        /* Alternative legacy name for the above */
-#define SCKELOW         0x8000  /* Enable Drive CKE Low During Reset            */
-
-/* PLL_STAT Masks                                                                                                                                       */
-#define ACTIVE_PLLENABLED       0x0001  /* Processor In Active Mode With PLL Enabled    */
-#define FULL_ON                         0x0002  /* Processor In Full On Mode                                    */
-#define ACTIVE_PLLDISABLED      0x0004  /* Processor In Active Mode With PLL Disabled   */
-#define PLL_LOCKED                      0x0020  /* PLL_LOCKCNT Has Been Reached                                 */
 
 /* CHIPID Masks */
 #define CHIPID_VERSION         0xF0000000
@@ -1645,34 +1584,6 @@
 #define BGSTAT                  0x0020  /* Bus Grant Status                                             */
 
 /* **************************  DMA CONTROLLER MASKS  ********************************/
-/* DMAx_CONFIG, MDMA_yy_CONFIG Masks                                                                                            */
-#define DMAEN                   0x0001  /* DMA Channel Enable                                                   */
-#define WNR                             0x0002  /* Channel Direction (W/R*)                                             */
-#define WDSIZE_8                0x0000  /* Transfer Word Size = 8                                               */
-#define WDSIZE_16               0x0004  /* Transfer Word Size = 16                                              */
-#define WDSIZE_32               0x0008  /* Transfer Word Size = 32                                              */
-#define DMA2D                   0x0010  /* DMA Mode (2D/1D*)                                                    */
-#define RESTART                 0x0020  /* DMA Buffer Clear                                                             */
-#define DI_SEL                  0x0040  /* Data Interrupt Timing Select                                 */
-#define DI_EN                   0x0080  /* Data Interrupt Enable                                                */
-#define NDSIZE_0                0x0000  /* Next Descriptor Size = 0 (Stop/Autobuffer)   */
-#define NDSIZE_1                0x0100  /* Next Descriptor Size = 1                                             */
-#define NDSIZE_2                0x0200  /* Next Descriptor Size = 2                                             */
-#define NDSIZE_3                0x0300  /* Next Descriptor Size = 3                                             */
-#define NDSIZE_4                0x0400  /* Next Descriptor Size = 4                                             */
-#define NDSIZE_5                0x0500  /* Next Descriptor Size = 5                                             */
-#define NDSIZE_6                0x0600  /* Next Descriptor Size = 6                                             */
-#define NDSIZE_7                0x0700  /* Next Descriptor Size = 7                                             */
-#define NDSIZE_8                0x0800  /* Next Descriptor Size = 8                                             */
-#define NDSIZE_9                0x0900  /* Next Descriptor Size = 9                                             */
-#define NDSIZE                  0x0900  /* Next Descriptor Size */
-
-#define DMAFLOW                 0x7000  /* Flow Control */
-#define DMAFLOW_STOP            0x0000  /* Stop Mode */
-#define DMAFLOW_AUTO            0x1000  /* Autobuffer Mode */
-#define DMAFLOW_ARRAY           0x4000  /* Descriptor Array Mode */
-#define DMAFLOW_SMALL           0x6000  /* Small Model Descriptor List Mode */
-#define DMAFLOW_LARGE           0x7000  /* Large Model Descriptor List Mode */
 
 /* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP Masks                                                            */
 #define CTYPE                   0x0040  /* DMA Channel Type Indicator (Memory/Peripheral*)      */
@@ -1690,12 +1601,6 @@
 #define PMAP_UART1RX    0xA000  /*              UART1 Port Receive DMA                                          */
 #define PMAP_UART1TX    0xB000  /*              UART1 Port Transmit DMA                                         */
 
-/* DMAx_IRQ_STATUS, MDMA_yy_IRQ_STATUS Masks                                            */
-#define DMA_DONE                0x0001  /* DMA Completion Interrupt Status      */
-#define DMA_ERR                 0x0002  /* DMA Error Interrupt Status           */
-#define DFETCH                  0x0004  /* DMA Descriptor Fetch Indicator       */
-#define DMA_RUN                 0x0008  /* DMA Channel Running Indicator        */
-
 /*  ************  PARALLEL PERIPHERAL INTERFACE (PPI) MASKS *************/
 /*  PPI_CONTROL Masks                                                                                                   */
 #define PORT_EN                 0x0001  /* PPI Port Enable                                      */
diff --git a/arch/blackfin/mach-bf538/Makefile b/arch/blackfin/mach-bf538/Makefile
index 8cd2719684db..c0be54f2cd2b 100644
--- a/arch/blackfin/mach-bf538/Makefile
+++ b/arch/blackfin/mach-bf538/Makefile
@@ -3,3 +3,4 @@
 #
 
 obj-y := ints-priority.o dma.o
+obj-$(CONFIG_GPIOLIB)   += ext-gpio.o
diff --git a/arch/blackfin/mach-bf538/boards/ezkit.c b/arch/blackfin/mach-bf538/boards/ezkit.c
index 14af5c2088d4..c296bb1ed503 100644
--- a/arch/blackfin/mach-bf538/boards/ezkit.c
+++ b/arch/blackfin/mach-bf538/boards/ezkit.c
@@ -151,6 +151,44 @@ static struct platform_device bfin_sir2_device = {
 #endif
 #endif
 
+#if defined(CONFIG_CAN_BFIN) || defined(CONFIG_CAN_BFIN_MODULE)
+unsigned short bfin_can_peripherals[] = {
+        P_CAN0_RX, P_CAN0_TX, 0
+};
+
+static struct resource bfin_can_resources[] = {
+        {
+                .start = 0xFFC02A00,
+                .end = 0xFFC02FFF,
+                .flags = IORESOURCE_MEM,
+        },
+        {
+                .start = IRQ_CAN_RX,
+                .end = IRQ_CAN_RX,
+                .flags = IORESOURCE_IRQ,
+        },
+        {
+                .start = IRQ_CAN_TX,
+                .end = IRQ_CAN_TX,
+                .flags = IORESOURCE_IRQ,
+        },
+        {
+                .start = IRQ_CAN_ERROR,
+                .end = IRQ_CAN_ERROR,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device bfin_can_device = {
+        .name = "bfin_can",
+        .num_resources = ARRAY_SIZE(bfin_can_resources),
+        .resource = bfin_can_resources,
+        .dev = {
+                .platform_data = &bfin_can_peripherals, /* Passed to driver */
+        },
+};
+#endif
+
 /*
  *  USB-LAN EzExtender board
  *  Driver needs to know address, irq and flag pin.
@@ -610,6 +648,10 @@ static struct platform_device *cm_bf538_devices[] __initdata = {
 #endif
 #endif
 
+#if defined(CONFIG_CAN_BFIN) || defined(CONFIG_CAN_BFIN_MODULE)
+        &bfin_can_device,
+#endif
+
 #if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
         &smc91x_device,
 #endif
diff --git a/arch/blackfin/mach-bf538/ext-gpio.c b/arch/blackfin/mach-bf538/ext-gpio.c
new file mode 100644
index 000000000000..180b1252679f
--- /dev/null
+++ b/arch/blackfin/mach-bf538/ext-gpio.c
@@ -0,0 +1,123 @@
+/*
+ * GPIOLIB interface for BF538/9 PORT C, D, and E GPIOs
+ *
+ * Copyright 2009 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <linux/module.h>
+#include <linux/err.h>
+#include <asm/blackfin.h>
+#include <asm/gpio.h>
+#include <asm/portmux.h>
+
+#define DEFINE_REG(reg, off) \
+static inline u16 read_##reg(void __iomem *port) \
+        { return bfin_read16(port + off); } \
+static inline void write_##reg(void __iomem *port, u16 v) \
+        { bfin_write16(port + off, v); }
+
+DEFINE_REG(PORTIO, 0x00)
+DEFINE_REG(PORTIO_CLEAR, 0x10)
+DEFINE_REG(PORTIO_SET, 0x20)
+DEFINE_REG(PORTIO_DIR, 0x40)
+DEFINE_REG(PORTIO_INEN, 0x50)
+
+static void __iomem *gpio_chip_to_mmr(struct gpio_chip *chip)
+{
+        switch (chip->base) {
+        default: /* not really needed, but keeps gcc happy */
+        case GPIO_PC0: return (void __iomem *)PORTCIO;
+        case GPIO_PD0: return (void __iomem *)PORTDIO;
+        case GPIO_PE0: return (void __iomem *)PORTEIO;
+        }
+}
+
+static int bf538_gpio_get_value(struct gpio_chip *chip, unsigned gpio)
+{
+        void __iomem *port = gpio_chip_to_mmr(chip);
+        return !!(read_PORTIO(port) & (1u << gpio));
+}
+
+static void bf538_gpio_set_value(struct gpio_chip *chip, unsigned gpio, int value)
+{
+        void __iomem *port = gpio_chip_to_mmr(chip);
+        if (value)
+                write_PORTIO_SET(port, (1u << gpio));
+        else
+                write_PORTIO_CLEAR(port, (1u << gpio));
+}
+
+static int bf538_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
+{
+        void __iomem *port = gpio_chip_to_mmr(chip);
+        write_PORTIO_DIR(port, read_PORTIO_DIR(port) & ~(1u << gpio));
+        write_PORTIO_INEN(port, read_PORTIO_INEN(port) | (1u << gpio));
+        return 0;
+}
+
+static int bf538_gpio_direction_output(struct gpio_chip *chip, unsigned gpio, int value)
+{
+        void __iomem *port = gpio_chip_to_mmr(chip);
+        write_PORTIO_INEN(port, read_PORTIO_INEN(port) & ~(1u << gpio));
+        bf538_gpio_set_value(port, gpio, value);
+        write_PORTIO_DIR(port, read_PORTIO_DIR(port) | (1u << gpio));
+        return 0;
+}
+
+static int bf538_gpio_request(struct gpio_chip *chip, unsigned gpio)
+{
+        return bfin_special_gpio_request(chip->base + gpio, chip->label);
+}
+
+static void bf538_gpio_free(struct gpio_chip *chip, unsigned gpio)
+{
+        return bfin_special_gpio_free(chip->base + gpio);
+}
+
+/* We don't set the irq fields as these banks cannot generate interrupts */
+
+static struct gpio_chip bf538_portc_chip = {
+        .label = "GPIO-PC",
+        .direction_input = bf538_gpio_direction_input,
+        .get = bf538_gpio_get_value,
+        .direction_output = bf538_gpio_direction_output,
+        .set = bf538_gpio_set_value,
+        .request = bf538_gpio_request,
+        .free = bf538_gpio_free,
+        .base = GPIO_PC0,
+        .ngpio = GPIO_PC9 - GPIO_PC0 + 1,
+};
+
+static struct gpio_chip bf538_portd_chip = {
+        .label = "GPIO-PD",
+        .direction_input = bf538_gpio_direction_input,
+        .get = bf538_gpio_get_value,
+        .direction_output = bf538_gpio_direction_output,
+        .set = bf538_gpio_set_value,
+        .request = bf538_gpio_request,
+        .free = bf538_gpio_free,
+        .base = GPIO_PD0,
+        .ngpio = GPIO_PD13 - GPIO_PD0 + 1,
+};
+
+static struct gpio_chip bf538_porte_chip = {
+        .label = "GPIO-PE",
+        .direction_input = bf538_gpio_direction_input,
+        .get = bf538_gpio_get_value,
+        .direction_output = bf538_gpio_direction_output,
+        .set = bf538_gpio_set_value,
+        .request = bf538_gpio_request,
+        .free = bf538_gpio_free,
+        .base = GPIO_PE0,
+        .ngpio = GPIO_PE15 - GPIO_PE0 + 1,
+};
+
+static int __init bf538_extgpio_setup(void)
+{
+        return gpiochip_add(&bf538_portc_chip) |
+                gpiochip_add(&bf538_portd_chip) |
+                gpiochip_add(&bf538_porte_chip);
+}
+arch_initcall(bf538_extgpio_setup);
diff --git a/arch/blackfin/mach-bf538/include/mach/blackfin.h b/arch/blackfin/mach-bf538/include/mach/blackfin.h
index 278e8942eef2..08b5eabb1ed5 100644
--- a/arch/blackfin/mach-bf538/include/mach/blackfin.h
+++ b/arch/blackfin/mach-bf538/include/mach/blackfin.h
@@ -37,10 +37,4 @@
 #define OFFSET_SCR              0x1C    /* SCR Scratch Register                 */
 #define OFFSET_GCTL             0x24    /* Global Control Register              */
 
-/* PLL_DIV Masks                                                                                                        */
-#define CCLK_DIV1 CSEL_DIV1     /*          CCLK = VCO / 1                                  */
-#define CCLK_DIV2 CSEL_DIV2     /*          CCLK = VCO / 2                                  */
-#define CCLK_DIV4 CSEL_DIV4     /*          CCLK = VCO / 4                                  */
-#define CCLK_DIV8 CSEL_DIV8     /*          CCLK = VCO / 8                                  */
-
 #endif
diff --git a/arch/blackfin/mach-bf538/include/mach/defBF539.h b/arch/blackfin/mach-bf538/include/mach/defBF539.h
index 5f6c34dfd08e..fac563e6f62f 100644
--- a/arch/blackfin/mach-bf538/include/mach/defBF539.h
+++ b/arch/blackfin/mach-bf538/include/mach/defBF539.h
@@ -468,31 +468,31 @@
 /* General-Purpose Ports  (0xFFC01500 - 0xFFC015FF)      */
 
 /* GPIO Port C Register Names */
-#define GPIO_C_CNFG                     0xFFC01500      /* GPIO Pin Port C Configuration Register */
-#define GPIO_C_D                        0xFFC01510      /* GPIO Pin Port C Data Register */
-#define GPIO_C_C                        0xFFC01520      /* Clear GPIO Pin Port C Register */
-#define GPIO_C_S                        0xFFC01530      /* Set GPIO Pin Port C Register */
-#define GPIO_C_T                        0xFFC01540      /* Toggle GPIO Pin Port C Register */
-#define GPIO_C_DIR                      0xFFC01550      /* GPIO Pin Port C Direction Register */
-#define GPIO_C_INEN                     0xFFC01560      /* GPIO Pin Port C Input Enable Register */
+#define PORTCIO_FER                     0xFFC01500      /* GPIO Pin Port C Configuration Register */
+#define PORTCIO                         0xFFC01510      /* GPIO Pin Port C Data Register */
+#define PORTCIO_CLEAR                   0xFFC01520      /* Clear GPIO Pin Port C Register */
+#define PORTCIO_SET                     0xFFC01530      /* Set GPIO Pin Port C Register */
+#define PORTCIO_TOGGLE                  0xFFC01540      /* Toggle GPIO Pin Port C Register */
+#define PORTCIO_DIR                     0xFFC01550      /* GPIO Pin Port C Direction Register */
+#define PORTCIO_INEN                    0xFFC01560      /* GPIO Pin Port C Input Enable Register */
 
 /* GPIO Port D Register Names */
-#define GPIO_D_CNFG                     0xFFC01504      /* GPIO Pin Port D Configuration Register */
-#define GPIO_D_D                        0xFFC01514      /* GPIO Pin Port D Data Register */
-#define GPIO_D_C                        0xFFC01524      /* Clear GPIO Pin Port D Register */
-#define GPIO_D_S                        0xFFC01534      /* Set GPIO Pin Port D Register */
-#define GPIO_D_T                        0xFFC01544      /* Toggle GPIO Pin Port D Register */
-#define GPIO_D_DIR                      0xFFC01554      /* GPIO Pin Port D Direction Register */
-#define GPIO_D_INEN                     0xFFC01564      /* GPIO Pin Port D Input Enable Register */
+#define PORTDIO_FER                     0xFFC01504      /* GPIO Pin Port D Configuration Register */
+#define PORTDIO                         0xFFC01514      /* GPIO Pin Port D Data Register */
+#define PORTDIO_CLEAR                   0xFFC01524      /* Clear GPIO Pin Port D Register */
+#define PORTDIO_SET                     0xFFC01534      /* Set GPIO Pin Port D Register */
+#define PORTDIO_TOGGLE                  0xFFC01544      /* Toggle GPIO Pin Port D Register */
+#define PORTDIO_DIR                     0xFFC01554      /* GPIO Pin Port D Direction Register */
+#define PORTDIO_INEN                    0xFFC01564      /* GPIO Pin Port D Input Enable Register */
 
 /* GPIO Port E Register Names */
-#define GPIO_E_CNFG                     0xFFC01508      /* GPIO Pin Port E Configuration Register */
-#define GPIO_E_D                        0xFFC01518      /* GPIO Pin Port E Data Register */
-#define GPIO_E_C                        0xFFC01528      /* Clear GPIO Pin Port E Register */
-#define GPIO_E_S                        0xFFC01538      /* Set GPIO Pin Port E Register */
-#define GPIO_E_T                        0xFFC01548      /* Toggle GPIO Pin Port E Register */
-#define GPIO_E_DIR                      0xFFC01558      /* GPIO Pin Port E Direction Register */
-#define GPIO_E_INEN                     0xFFC01568      /* GPIO Pin Port E Input Enable Register */
+#define PORTEIO_FER                     0xFFC01508      /* GPIO Pin Port E Configuration Register */
+#define PORTEIO                         0xFFC01518      /* GPIO Pin Port E Data Register */
+#define PORTEIO_CLEAR                   0xFFC01528      /* Clear GPIO Pin Port E Register */
+#define PORTEIO_SET                     0xFFC01538      /* Set GPIO Pin Port E Register */
+#define PORTEIO_TOGGLE                  0xFFC01548      /* Toggle GPIO Pin Port E Register */
+#define PORTEIO_DIR                     0xFFC01558      /* GPIO Pin Port E Direction Register */
+#define PORTEIO_INEN                    0xFFC01568      /* GPIO Pin Port E Input Enable Register */
 
 /* DMA Controller 1 Traffic Control Registers (0xFFC01B00 - 0xFFC01BFF) */
 
@@ -1422,81 +1422,6 @@
 /* System MMR Register Bits and Macros */
 /******************************************************************************* */
 
-/* ********************* PLL AND RESET MASKS ************************ */
-/* PLL_CTL Masks */
-#define PLL_CLKIN                       0x0000  /* Pass CLKIN to PLL */
-#define PLL_CLKIN_DIV2          0x0001  /* Pass CLKIN/2 to PLL */
-#define DF                                      0x0001   /* 0: PLL = CLKIN, 1: PLL = CLKIN/2 */
-#define PLL_OFF                         0x0002  /* Shut off PLL clocks */
-
-#define STOPCK                          0x0008  /* Core Clock Off                */
-#define PDWN                            0x0020  /* Put the PLL in a Deep Sleep state */
-#define IN_DELAY                        0x0014  /* EBIU Input Delay Select */
-#define OUT_DELAY                       0x00C0  /* EBIU Output Delay Select */
-#define BYPASS                          0x0100  /* Bypass the PLL */
-#define MSEL                    0x7E00  /* Multiplier Select For CCLK/VCO Factors */
-
-/* PLL_CTL Macros                                */
-#ifdef _MISRA_RULES
-#define SET_MSEL(x)             (((x)&0x3Fu) << 0x9)    /* Set MSEL = 0-63 --> VCO = CLKIN*MSEL */
-#define SET_OUT_DELAY(x)        (((x)&0x03u) << 0x6)
-#define SET_IN_DELAY(x)         ((((x)&0x02u) << 0x3) | (((x)&0x01u) << 0x2))
-#else
-#define SET_MSEL(x)             (((x)&0x3F) << 0x9)     /* Set MSEL = 0-63 --> VCO = CLKIN*MSEL */
-#define SET_OUT_DELAY(x)        (((x)&0x03) << 0x6)
-#define SET_IN_DELAY(x)         ((((x)&0x02) << 0x3) | (((x)&0x01) << 0x2))
-#endif /* _MISRA_RULES */
-
-/* PLL_DIV Masks */
-#define SSEL                            0x000F  /* System Select */
-#define CSEL                            0x0030  /* Core Select */
-#define CSEL_DIV1               0x0000  /*              CCLK = VCO / 1 */
-#define CSEL_DIV2               0x0010  /*              CCLK = VCO / 2 */
-#define CSEL_DIV4               0x0020  /*              CCLK = VCO / 4 */
-#define CSEL_DIV8               0x0030  /*              CCLK = VCO / 8 */
-
-#define SCLK_DIV(x)                     (x)             /* SCLK = VCO / x */
-
-/* PLL_DIV Macros                                                        */
-#ifdef _MISRA_RULES
-#define SET_SSEL(x)                     ((x)&0xFu)      /* Set SSEL = 0-15 --> SCLK = VCO/SSEL */
-#else
-#define SET_SSEL(x)                     ((x)&0xF)       /* Set SSEL = 0-15 --> SCLK = VCO/SSEL */
-#endif /* _MISRA_RULES */
-
-/* PLL_STAT Masks                                                                                */
-#define ACTIVE_PLLENABLED       0x0001  /* Processor In Active Mode With PLL Enabled */
-#define FULL_ON                         0x0002  /* Processor In Full On Mode */
-#define ACTIVE_PLLDISABLED      0x0004  /* Processor In Active Mode With PLL Disabled */
-#define PLL_LOCKED                      0x0020  /* PLL_LOCKCNT Has Been Reached */
-
-/* VR_CTL Masks                                                                          */
-#define FREQ                    0x0003  /* Switching Oscillator Frequency For Regulator */
-#define HIBERNATE               0x0000  /*              Powerdown/Bypass On-Board Regulation */
-#define FREQ_333                0x0001  /*              Switching Frequency Is 333 kHz */
-#define FREQ_667                0x0002  /*              Switching Frequency Is 667 kHz */
-#define FREQ_1000               0x0003  /*              Switching Frequency Is 1 MHz */
-
-#define GAIN                    0x000C  /* Voltage Level Gain */
-#define GAIN_5                  0x0000  /*              GAIN = 5 */
-#define GAIN_10                 0x0004  /*              GAIN = 10 */
-#define GAIN_20                 0x0008  /*              GAIN = 20 */
-#define GAIN_50                 0x000C  /*              GAIN = 50 */
-
-#define VLEV                    0x00F0  /* Internal Voltage Level - Only Program Values Within Specifications */
-#define VLEV_100                0x0090  /*      VLEV = 1.00 V (See Datasheet for Regulator Tolerance) */
-#define VLEV_105                0x00A0  /*      VLEV = 1.05 V (See Datasheet for Regulator Tolerance) */
-#define VLEV_110                0x00B0  /*      VLEV = 1.10 V (See Datasheet for Regulator Tolerance) */
-#define VLEV_115                0x00C0  /*      VLEV = 1.15 V (See Datasheet for Regulator Tolerance) */
-#define VLEV_120                0x00D0  /*      VLEV = 1.20 V (See Datasheet for Regulator Tolerance) */
-#define VLEV_125                0x00E0  /*      VLEV = 1.25 V (See Datasheet for Regulator Tolerance) */
-#define VLEV_130                0x00F0  /*      VLEV = 1.30 V (See Datasheet for Regulator Tolerance) */
-
-#define WAKE                    0x0100  /* Enable RTC/Reset Wakeup From Hibernate */
-#define CANWE                   0x0200  /* Enable CAN Wakeup From Hibernate */
-#define MXVRWE                  0x0400  /* Enable MXVR Wakeup From Hibernate */
-#define SCKELOW                 0x8000  /* Do Not Drive SCKE High During Reset After Hibernate */
-
 /* SWRST Mask */
 #define SYSTEM_RESET    0x0007  /* Initiates A System Software Reset */
 #define DOUBLE_FAULT    0x0008  /* Core Double Fault Causes Reset */
@@ -1609,91 +1534,6 @@
 #endif /* _MISRA_RULES */
 
 
-/* ********* WATCHDOG TIMER MASKS ******************** */
-/* Watchdog Timer WDOG_CTL Register Masks */
-#ifdef _MISRA_RULES
-#define WDEV(x)                 (((x)<<1) & 0x0006u)    /* event generated on roll over */
-#else
-#define WDEV(x)                 (((x)<<1) & 0x0006)     /* event generated on roll over */
-#endif /* _MISRA_RULES */
-#define WDEV_RESET              0x0000                          /* generate reset event on roll over */
-#define WDEV_NMI                0x0002                          /* generate NMI event on roll over */
-#define WDEV_GPI                0x0004                          /* generate GP IRQ on roll over */
-#define WDEV_NONE               0x0006                          /* no event on roll over */
-#define WDEN                    0x0FF0                          /* enable watchdog */
-#define WDDIS                   0x0AD0                          /* disable watchdog */
-#define WDRO                    0x8000                          /* watchdog rolled over latch */
-
-/* deprecated WDOG_CTL Register Masks for legacy code */
-#define ICTL WDEV
-#define ENABLE_RESET    WDEV_RESET
-#define WDOG_RESET              WDEV_RESET
-#define ENABLE_NMI              WDEV_NMI
-#define WDOG_NMI                WDEV_NMI
-#define ENABLE_GPI              WDEV_GPI
-#define WDOG_GPI                WDEV_GPI
-#define DISABLE_EVT     WDEV_NONE
-#define WDOG_NONE               WDEV_NONE
-
-#define TMR_EN                  WDEN
-#define WDOG_DISABLE            WDDIS
-#define TRO                     WDRO
-
-#define ICTL_P0                 0x01
-#define ICTL_P1                 0x02
-#define TRO_P                   0x0F
-
-
-/* ***************  REAL TIME CLOCK MASKS  **************************/
-/* RTC_STAT and RTC_ALARM register */
-#define RTSEC           0x0000003F      /* Real-Time Clock Seconds */
-#define RTMIN           0x00000FC0      /* Real-Time Clock Minutes */
-#define RTHR            0x0001F000      /* Real-Time Clock Hours */
-#define RTDAY           0xFFFE0000      /* Real-Time Clock Days */
-
-/* RTC_ICTL register */
-#define SWIE            0x0001          /* Stopwatch Interrupt Enable */
-#define AIE                     0x0002          /* Alarm Interrupt Enable */
-#define SIE                     0x0004          /* Seconds (1 Hz) Interrupt Enable */
-#define MIE                     0x0008          /* Minutes Interrupt Enable */
-#define HIE                     0x0010          /* Hours Interrupt Enable */
-#define DIE                     0x0020          /* 24 Hours (Days) Interrupt Enable */
-#define DAIE            0x0040          /* Day Alarm (Day, Hour, Minute, Second) Interrupt Enable */
-#define WCIE            0x8000          /* Write Complete Interrupt Enable */
-
-/* RTC_ISTAT register */
-#define SWEF            0x0001          /* Stopwatch Event Flag */
-#define AEF                     0x0002          /* Alarm Event Flag */
-#define SEF                     0x0004          /* Seconds (1 Hz) Event Flag */
-#define MEF                     0x0008          /* Minutes Event Flag */
-#define HEF                     0x0010          /* Hours Event Flag */
-#define DEF                     0x0020          /* 24 Hours (Days) Event Flag */
-#define DAEF            0x0040          /* Day Alarm (Day, Hour, Minute, Second) Event Flag */
-#define WPS                     0x4000          /* Write Pending Status (RO) */
-#define WCOM            0x8000          /* Write Complete */
-
-/* RTC_FAST Mask (RTC_PREN Mask) */
-#define ENABLE_PRESCALE      0x00000001  /* Enable prescaler so RTC runs at 1 Hz */
-#define PREN                 0x00000001
-                /* ** Must be set after power-up for proper operation of RTC */
-
-/* Deprecated RTC_STAT and RTC_ALARM Masks                       */
-#define RTC_SEC                 RTSEC   /* Real-Time Clock Seconds */
-#define RTC_MIN                 RTMIN   /* Real-Time Clock Minutes */
-#define RTC_HR                  RTHR    /* Real-Time Clock Hours */
-#define RTC_DAY                 RTDAY   /* Real-Time Clock Days */
-
-/* Deprecated RTC_ICTL/RTC_ISTAT Masks                                                                                   */
-#define STOPWATCH               SWIE            /* Stopwatch Interrupt Enable    */
-#define ALARM                   AIE             /* Alarm Interrupt Enable                */
-#define SECOND                  SIE             /* Seconds (1 Hz) Interrupt Enable */
-#define MINUTE                  MIE             /* Minutes Interrupt Enable              */
-#define HOUR                    HIE             /* Hours Interrupt Enable                */
-#define DAY                             DIE             /* 24 Hours (Days) Interrupt Enable */
-#define DAY_ALARM               DAIE            /* Day Alarm (Day, Hour, Minute, Second) Interrupt Enable */
-#define WRITE_COMPLETE  WCIE            /* Write Complete Interrupt Enable */
-
-
 /* ***************************** UART CONTROLLER MASKS ********************** */
 /* UARTx_LCR Register */
 #ifdef _MISRA_RULES
@@ -1917,52 +1757,6 @@
 
 
 /* **********  DMA CONTROLLER MASKS  ***********************/
-/* DMAx_CONFIG, MDMA_yy_CONFIG Masks */
-#define DMAEN           0x0001  /* Channel Enable */
-#define WNR                     0x0002  /* Channel Direction (W/R*) */
-#define WDSIZE_8        0x0000  /* Word Size 8 bits */
-#define WDSIZE_16       0x0004  /* Word Size 16 bits */
-#define WDSIZE_32       0x0008  /* Word Size 32 bits */
-#define DMA2D           0x0010  /* 2D/1D* Mode */
-#define RESTART         0x0020  /* Restart */
-#define DI_SEL          0x0040  /* Data Interrupt Select */
-#define DI_EN           0x0080  /* Data Interrupt Enable */
-#define NDSIZE          0x0900  /* Next Descriptor Size */
-#define NDSIZE_0        0x0000  /* Next Descriptor Size = 0 (Stop/Autobuffer) */
-#define NDSIZE_1        0x0100  /* Next Descriptor Size = 1 */
-#define NDSIZE_2        0x0200  /* Next Descriptor Size = 2 */
-#define NDSIZE_3        0x0300  /* Next Descriptor Size = 3 */
-#define NDSIZE_4        0x0400  /* Next Descriptor Size = 4 */
-#define NDSIZE_5        0x0500  /* Next Descriptor Size = 5 */
-#define NDSIZE_6        0x0600  /* Next Descriptor Size = 6 */
-#define NDSIZE_7        0x0700  /* Next Descriptor Size = 7 */
-#define NDSIZE_8        0x0800  /* Next Descriptor Size = 8 */
-#define NDSIZE_9        0x0900  /* Next Descriptor Size = 9 */
-
-#define DMAFLOW                 0x7000  /* Flow Control */
-#define DMAFLOW_STOP            0x0000  /* Stop Mode */
-#define DMAFLOW_AUTO            0x1000  /* Autobuffer Mode */
-#define DMAFLOW_ARRAY           0x4000  /* Descriptor Array Mode */
-#define DMAFLOW_SMALL           0x6000  /* Small Model Descriptor List Mode */
-#define DMAFLOW_LARGE           0x7000  /* Large Model Descriptor List Mode */
-
-#define DMAEN_P         0x0             /* Channel Enable */
-#define WNR_P           0x1             /* Channel Direction (W/R*) */
-#define DMA2D_P         0x4             /* 2D/1D* Mode */
-#define RESTART_P       0x5             /* Restart */
-#define DI_SEL_P        0x6             /* Data Interrupt Select */
-#define DI_EN_P         0x7             /* Data Interrupt Enable */
-
-/* DMAx_IRQ_STATUS, MDMA_yy_IRQ_STATUS Masks */
-#define DMA_DONE        0x0001  /* DMA Done Indicator */
-#define DMA_ERR         0x0002  /* DMA Error Indicator */
-#define DFETCH          0x0004  /* Descriptor Fetch Indicator */
-#define DMA_RUN         0x0008  /* DMA Running Indicator */
-
-#define DMA_DONE_P      0x0             /* DMA Done Indicator */
-#define DMA_ERR_P       0x1             /* DMA Error Indicator */
-#define DFETCH_P        0x2             /* Descriptor Fetch Indicator */
-#define DMA_RUN_P       0x3             /* DMA Running Indicator */
 
 /* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP Masks */
 
@@ -2625,1019 +2419,6 @@
 #define RCV_FULL        0x000C          /*              Receive FIFO Full (2 Bytes To Read) */
 
 
-/********************************* MXVR MASKS ****************************************/
-
-/* MXVR_CONFIG Masks */
-
-#define MXVREN    0x00000001lu
-#define MMSM      0x00000002lu
-#define ACTIVE    0x00000004lu
-#define SDELAY    0x00000008lu
-#define NCMRXEN   0x00000010lu
-#define RWRRXEN   0x00000020lu
-#define MTXEN     0x00000040lu
-#define MTXON     0x00000080lu /*legacy*/
-#define MTXONB    0x00000080lu
-#define EPARITY   0x00000100lu
-#define MSB       0x00001E00lu
-#define APRXEN    0x00002000lu
-#define WAKEUP    0x00004000lu
-#define LMECH     0x00008000lu
-
-#ifdef _MISRA_RULES
-#define SET_MSB(x)     (((x)&0xFu) << 0x9)
-#else
-#define SET_MSB(x)     (((x)&0xF) << 0x9)
-#endif /* _MISRA_RULES */
-
-
-/* MXVR_PLL_CTL_0 Masks */
-
-#define MXTALCEN  0x00000001lu
-#define MXTALFEN  0x00000002lu
-#define MPLLMS    0x00000008lu
-#define MXTALMUL  0x00000030lu
-#define MPLLEN    0x00000040lu
-#define MPLLEN0   0x00000040lu /* legacy */
-#define MPLLEN1   0x00000080lu /* legacy */
-#define MMCLKEN   0x00000100lu
-#define MMCLKMUL  0x00001E00lu
-#define MPLLRSTB  0x00002000lu
-#define MPLLRSTB0 0x00002000lu /* legacy */
-#define MPLLRSTB1 0x00004000lu /* legacy */
-#define MBCLKEN   0x00010000lu
-#define MBCLKDIV  0x001E0000lu
-#define MPLLCDR   0x00200000lu
-#define MPLLCDR0  0x00200000lu /* legacy */
-#define MPLLCDR1  0x00400000lu /* legacy */
-#define INVRX     0x00800000lu
-#define MFSEN     0x01000000lu
-#define MFSDIV    0x1E000000lu
-#define MFSSEL    0x60000000lu
-#define MFSSYNC   0x80000000lu
-
-#define MXTALMUL_256FS   0x00000000lu /* legacy */
-#define MXTALMUL_384FS   0x00000010lu /* legacy */
-#define MXTALMUL_512FS   0x00000020lu /* legacy */
-#define MXTALMUL_1024FS  0x00000030lu
-
-#define MMCLKMUL_1024FS  0x00000000lu
-#define MMCLKMUL_512FS   0x00000200lu
-#define MMCLKMUL_256FS   0x00000400lu
-#define MMCLKMUL_128FS   0x00000600lu
-#define MMCLKMUL_64FS    0x00000800lu
-#define MMCLKMUL_32FS    0x00000A00lu
-#define MMCLKMUL_16FS    0x00000C00lu
-#define MMCLKMUL_8FS     0x00000E00lu
-#define MMCLKMUL_4FS     0x00001000lu
-#define MMCLKMUL_2FS     0x00001200lu
-#define MMCLKMUL_1FS     0x00001400lu
-#define MMCLKMUL_1536FS  0x00001A00lu
-#define MMCLKMUL_768FS   0x00001C00lu
-#define MMCLKMUL_384FS   0x00001E00lu
-
-#define MBCLKDIV_DIV2    0x00020000lu
-#define MBCLKDIV_DIV4    0x00040000lu
-#define MBCLKDIV_DIV8    0x00060000lu
-#define MBCLKDIV_DIV16   0x00080000lu
-#define MBCLKDIV_DIV32   0x000A0000lu
-#define MBCLKDIV_DIV64   0x000C0000lu
-#define MBCLKDIV_DIV128  0x000E0000lu
-#define MBCLKDIV_DIV256  0x00100000lu
-#define MBCLKDIV_DIV512  0x00120000lu
-#define MBCLKDIV_DIV1024 0x00140000lu
-
-#define MFSDIV_DIV2      0x02000000lu
-#define MFSDIV_DIV4      0x04000000lu
-#define MFSDIV_DIV8      0x06000000lu
-#define MFSDIV_DIV16     0x08000000lu
-#define MFSDIV_DIV32     0x0A000000lu
-#define MFSDIV_DIV64     0x0C000000lu
-#define MFSDIV_DIV128    0x0E000000lu
-#define MFSDIV_DIV256    0x10000000lu
-#define MFSDIV_DIV512    0x12000000lu
-#define MFSDIV_DIV1024   0x14000000lu
-
-#define MFSSEL_CLOCK     0x00000000lu
-#define MFSSEL_PULSE_HI  0x20000000lu
-#define MFSSEL_PULSE_LO  0x40000000lu
-
-
-/* MXVR_PLL_CTL_1 Masks */
-
-#define MSTO       0x00000001lu
-#define MSTO0      0x00000001lu /* legacy */
-#define MHOGGD     0x00000004lu
-#define MHOGGD0    0x00000004lu /* legacy */
-#define MHOGGD1    0x00000008lu /* legacy */
-#define MSHAPEREN  0x00000010lu
-#define MSHAPEREN0 0x00000010lu /* legacy */
-#define MSHAPEREN1 0x00000020lu /* legacy */
-#define MPLLCNTEN  0x00008000lu
-#define MPLLCNT    0xFFFF0000lu
-
-#ifdef _MISRA_RULES
-#define SET_MPLLCNT(x)     (((x)&0xFFFFu) << 0x10)
-#else
-#define SET_MPLLCNT(x)     (((x)&0xFFFF) << 0x10)
-#endif /* _MISRA_RULES */
-
-
-/* MXVR_PLL_CTL_2 Masks */
-
-#define MSHAPERSEL 0x00000007lu
-#define MCPSEL     0x000000E0lu
-
-/* MXVR_INT_STAT_0 Masks */
-
-#define NI2A  0x00000001lu
-#define NA2I  0x00000002lu
-#define SBU2L 0x00000004lu
-#define SBL2U 0x00000008lu
-#define PRU   0x00000010lu
-#define MPRU  0x00000020lu
-#define DRU   0x00000040lu
-#define MDRU  0x00000080lu
-#define SBU   0x00000100lu
-#define ATU   0x00000200lu
-#define FCZ0  0x00000400lu
-#define FCZ1  0x00000800lu
-#define PERR  0x00001000lu
-#define MH2L  0x00002000lu
-#define ML2H  0x00004000lu
-#define WUP   0x00008000lu
-#define FU2L  0x00010000lu
-#define FL2U  0x00020000lu
-#define BU2L  0x00040000lu
-#define BL2U  0x00080000lu
-#define PCZ   0x00400000lu
-#define FERR  0x00800000lu
-#define CMR   0x01000000lu
-#define CMROF 0x02000000lu
-#define CMTS  0x04000000lu
-#define CMTC  0x08000000lu
-#define RWRC  0x10000000lu
-#define BCZ   0x20000000lu
-#define BMERR 0x40000000lu
-#define DERR  0x80000000lu
-
-
-/* MXVR_INT_EN_0 Masks */
-
-#define NI2AEN  NI2A
-#define NA2IEN  NA2I
-#define SBU2LEN SBU2L
-#define SBL2UEN SBL2U
-#define PRUEN   PRU
-#define MPRUEN  MPRU
-#define DRUEN   DRU
-#define MDRUEN  MDRU
-#define SBUEN   SBU
-#define ATUEN   ATU
-#define FCZ0EN  FCZ0
-#define FCZ1EN  FCZ1
-#define PERREN  PERR
-#define MH2LEN  MH2L
-#define ML2HEN  ML2H
-#define WUPEN   WUP
-#define FU2LEN  FU2L
-#define FL2UEN  FL2U
-#define BU2LEN  BU2L
-#define BL2UEN  BL2U
-#define PCZEN   PCZ
-#define FERREN  FERR
-#define CMREN   CMR
-#define CMROFEN CMROF
-#define CMTSEN  CMTS
-#define CMTCEN  CMTC
-#define RWRCEN  RWRC
-#define BCZEN   BCZ
-#define BMERREN BMERR
-#define DERREN  DERR
-
-
-/* MXVR_INT_STAT_1 Masks */
-
-#define APR   0x00000004lu
-#define APROF 0x00000008lu
-#define APTS  0x00000040lu
-#define APTC  0x00000080lu
-#define APRCE 0x00000400lu
-#define APRPE 0x00000800lu
-
-#define HDONE0 0x00000001lu
-#define DONE0  0x00000002lu
-#define HDONE1 0x00000010lu
-#define DONE1  0x00000020lu
-#define HDONE2 0x00000100lu
-#define DONE2  0x00000200lu
-#define HDONE3 0x00001000lu
-#define DONE3  0x00002000lu
-#define HDONE4 0x00010000lu
-#define DONE4  0x00020000lu
-#define HDONE5 0x00100000lu
-#define DONE5  0x00200000lu
-#define HDONE6 0x01000000lu
-#define DONE6  0x02000000lu
-#define HDONE7 0x10000000lu
-#define DONE7  0x20000000lu
-
-#define DONEX(x) (0x00000002 << (4 * (x)))
-#define HDONEX(x) (0x00000001 << (4 * (x)))
-
-
-/* MXVR_INT_EN_1 Masks */
-
-#define APREN   APR
-#define APROFEN APROF
-#define APTSEN  APTS
-#define APTCEN  APTC
-#define APRCEEN APRCE
-#define APRPEEN APRPE
-
-#define HDONEEN0 HDONE0
-#define DONEEN0  DONE0
-#define HDONEEN1 HDONE1
-#define DONEEN1  DONE1
-#define HDONEEN2 HDONE2
-#define DONEEN2  DONE2
-#define HDONEEN3 HDONE3
-#define DONEEN3  DONE3
-#define HDONEEN4 HDONE4
-#define DONEEN4  DONE4
-#define HDONEEN5 HDONE5
-#define DONEEN5  DONE5
-#define HDONEEN6 HDONE6
-#define DONEEN6  DONE6
-#define HDONEEN7 HDONE7
-#define DONEEN7  DONE7
-
-#define DONEENX(x) (0x00000002 << (4 * (x)))
-#define HDONEENX(x) (0x00000001 << (4 * (x)))
-
-
-/* MXVR_STATE_0 Masks */
-
-#define NACT     0x00000001lu
-#define SBLOCK   0x00000002lu
-#define PFDLOCK  0x00000004lu
-#define PFDLOCK0 0x00000004lu /* legacy */
-#define PDD      0x00000008lu
-#define PDD0     0x00000008lu /* legacy */
-#define PVCO     0x00000010lu
-#define PVCO0    0x00000010lu /* legacy */
-#define PFDLOCK1 0x00000020lu /* legacy */
-#define PDD1     0x00000040lu /* legacy */
-#define PVCO1    0x00000080lu /* legacy */
-#define APBSY    0x00000100lu
-#define APARB    0x00000200lu
-#define APTX     0x00000400lu
-#define APRX     0x00000800lu
-#define CMBSY    0x00001000lu
-#define CMARB    0x00002000lu
-#define CMTX     0x00004000lu
-#define CMRX     0x00008000lu
-#define MRXONB   0x00010000lu
-#define RGSIP    0x00020000lu
-#define DALIP    0x00040000lu
-#define ALIP     0x00080000lu
-#define RRDIP    0x00100000lu
-#define RWRIP    0x00200000lu
-#define FLOCK    0x00400000lu
-#define BLOCK    0x00800000lu
-#define RSB      0x0F000000lu
-#define DERRNUM  0xF0000000lu
-
-
-/* MXVR_STATE_1 Masks */
-
-#define STXNUMB     0x0000000Flu
-#define SRXNUMB     0x000000F0lu
-#define APCONT      0x00000100lu
-#define DMAACTIVEX  0x00FF0000lu
-#define DMAACTIVE0  0x00010000lu
-#define DMAACTIVE1  0x00020000lu
-#define DMAACTIVE2  0x00040000lu
-#define DMAACTIVE3  0x00080000lu
-#define DMAACTIVE4  0x00100000lu
-#define DMAACTIVE5  0x00200000lu
-#define DMAACTIVE6  0x00400000lu
-#define DMAACTIVE7  0x00800000lu
-#define DMAPMENX    0xFF000000lu
-#define DMAPMEN0    0x01000000lu
-#define DMAPMEN1    0x02000000lu
-#define DMAPMEN2    0x04000000lu
-#define DMAPMEN3    0x08000000lu
-#define DMAPMEN4    0x10000000lu
-#define DMAPMEN5    0x20000000lu
-#define DMAPMEN6    0x40000000lu
-#define DMAPMEN7    0x80000000lu
-
-
-/* MXVR_POSITION Masks */
-
-#define PVALID       0x8000
-#define POSITION     0x003F
-
-
-/* MXVR_MAX_POSITION Masks */
-
-#define MPVALID      0x8000
-#define MPOSITION    0x003F
-
-
-/* MXVR_DELAY Masks */
-
-#define DVALID       0x8000
-#define DELAY        0x003F
-
-
-/* MXVR_MAX_DELAY Masks */
-
-#define MDVALID      0x8000
-#define MDELAY       0x003F
-
-
-/* MXVR_LADDR Masks */
-
-#define LVALID       0x80000000lu
-#define LADDR        0x0000FFFFlu
-
-
-/* MXVR_GADDR Masks */
-
-#define GVALID       0x8000
-#define GADDRL       0x00FF
-
-
-/* MXVR_AADDR Masks */
-
-#define AVALID       0x80000000lu
-#define AADDR        0x0000FFFFlu
-
-
-/* MXVR_ALLOC_0 Masks */
-
-#define CIU0         0x00000080lu
-#define CIU1         0x00008000lu
-#define CIU2         0x00800000lu
-#define CIU3         0x80000000lu
-
-#define CL0          0x0000007Flu
-#define CL1          0x00007F00lu
-#define CL2          0x007F0000lu
-#define CL3          0x7F000000lu
-
-
-/* MXVR_ALLOC_1 Masks */
-
-#define CIU4         0x00000080lu
-#define CIU5         0x00008000lu
-#define CIU6         0x00800000lu
-#define CIU7         0x80000000lu
-
-#define CL4          0x0000007Flu
-#define CL5          0x00007F00lu
-#define CL6          0x007F0000lu
-#define CL7          0x7F000000lu
-
-
-/* MXVR_ALLOC_2 Masks */
-
-#define CIU8         0x00000080lu
-#define CIU9         0x00008000lu
-#define CIU10        0x00800000lu
-#define CIU11        0x80000000lu
-
-#define CL8          0x0000007Flu
-#define CL9          0x00007F00lu
-#define CL10         0x007F0000lu
-#define CL11         0x7F000000lu
-
-
-/* MXVR_ALLOC_3 Masks */
-
-#define CIU12        0x00000080lu
-#define CIU13        0x00008000lu
-#define CIU14        0x00800000lu
-#define CIU15        0x80000000lu
-
-#define CL12         0x0000007Flu
-#define CL13         0x00007F00lu
-#define CL14         0x007F0000lu
-#define CL15         0x7F000000lu
-
-
-/* MXVR_ALLOC_4 Masks */
-
-#define CIU16        0x00000080lu
-#define CIU17        0x00008000lu
-#define CIU18        0x00800000lu
-#define CIU19        0x80000000lu
-
-#define CL16         0x0000007Flu
-#define CL17         0x00007F00lu
-#define CL18         0x007F0000lu
-#define CL19         0x7F000000lu
-
-
-/* MXVR_ALLOC_5 Masks */
-
-#define CIU20        0x00000080lu
-#define CIU21        0x00008000lu
-#define CIU22        0x00800000lu
-#define CIU23        0x80000000lu
-
-#define CL20         0x0000007Flu
-#define CL21         0x00007F00lu
-#define CL22         0x007F0000lu
-#define CL23         0x7F000000lu
-
-
-/* MXVR_ALLOC_6 Masks */
-
-#define CIU24        0x00000080lu
-#define CIU25        0x00008000lu
-#define CIU26        0x00800000lu
-#define CIU27        0x80000000lu
-
-#define CL24         0x0000007Flu
-#define CL25         0x00007F00lu
-#define CL26         0x007F0000lu
-#define CL27         0x7F000000lu
-
-
-/* MXVR_ALLOC_7 Masks */
-
-#define CIU28        0x00000080lu
-#define CIU29        0x00008000lu
-#define CIU30        0x00800000lu
-#define CIU31        0x80000000lu
-
-#define CL28         0x0000007Flu
-#define CL29         0x00007F00lu
-#define CL30         0x007F0000lu
-#define CL31         0x7F000000lu
-
-
-/* MXVR_ALLOC_8 Masks */
-
-#define CIU32        0x00000080lu
-#define CIU33        0x00008000lu
-#define CIU34        0x00800000lu
-#define CIU35        0x80000000lu
-
-#define CL32         0x0000007Flu
-#define CL33         0x00007F00lu
-#define CL34         0x007F0000lu
-#define CL35         0x7F000000lu
-
-
-/* MXVR_ALLOC_9 Masks */
-
-#define CIU36        0x00000080lu
-#define CIU37        0x00008000lu
-#define CIU38        0x00800000lu
-#define CIU39        0x80000000lu
-
-#define CL36         0x0000007Flu
-#define CL37         0x00007F00lu
-#define CL38         0x007F0000lu
-#define CL39         0x7F000000lu
-
-
-/* MXVR_ALLOC_10 Masks */
-
-#define CIU40        0x00000080lu
-#define CIU41        0x00008000lu
-#define CIU42        0x00800000lu
-#define CIU43        0x80000000lu
-
-#define CL40         0x0000007Flu
-#define CL41         0x00007F00lu
-#define CL42         0x007F0000lu
-#define CL43         0x7F000000lu
-
-
-/* MXVR_ALLOC_11 Masks */
-
-#define CIU44        0x00000080lu
-#define CIU45        0x00008000lu
-#define CIU46        0x00800000lu
-#define CIU47        0x80000000lu
-
-#define CL44         0x0000007Flu
-#define CL45         0x00007F00lu
-#define CL46         0x007F0000lu
-#define CL47         0x7F000000lu
-
-
-/* MXVR_ALLOC_12 Masks */
-
-#define CIU48        0x00000080lu
-#define CIU49        0x00008000lu
-#define CIU50        0x00800000lu
-#define CIU51        0x80000000lu
-
-#define CL48         0x0000007Flu
-#define CL49         0x00007F00lu
-#define CL50         0x007F0000lu
-#define CL51         0x7F000000lu
-
-
-/* MXVR_ALLOC_13 Masks */
-
-#define CIU52        0x00000080lu
-#define CIU53        0x00008000lu
-#define CIU54        0x00800000lu
-#define CIU55        0x80000000lu
-
-#define CL52         0x0000007Flu
-#define CL53         0x00007F00lu
-#define CL54         0x007F0000lu
-#define CL55         0x7F000000lu
-
-
-/* MXVR_ALLOC_14 Masks */
-
-#define CIU56        0x00000080lu
-#define CIU57        0x00008000lu
-#define CIU58        0x00800000lu
-#define CIU59        0x80000000lu
-
-#define CL56         0x0000007Flu
-#define CL57         0x00007F00lu
-#define CL58         0x007F0000lu
-#define CL59         0x7F000000lu
-
-
-/* MXVR_SYNC_LCHAN_0 Masks */
-
-#define LCHANPC0     0x0000000Flu
-#define LCHANPC1     0x000000F0lu
-#define LCHANPC2     0x00000F00lu
-#define LCHANPC3     0x0000F000lu
-#define LCHANPC4     0x000F0000lu
-#define LCHANPC5     0x00F00000lu
-#define LCHANPC6     0x0F000000lu
-#define LCHANPC7     0xF0000000lu
-
-
-/* MXVR_SYNC_LCHAN_1 Masks */
-
-#define LCHANPC8     0x0000000Flu
-#define LCHANPC9     0x000000F0lu
-#define LCHANPC10    0x00000F00lu
-#define LCHANPC11    0x0000F000lu
-#define LCHANPC12    0x000F0000lu
-#define LCHANPC13    0x00F00000lu
-#define LCHANPC14    0x0F000000lu
-#define LCHANPC15    0xF0000000lu
-
-
-/* MXVR_SYNC_LCHAN_2 Masks */
-
-#define LCHANPC16    0x0000000Flu
-#define LCHANPC17    0x000000F0lu
-#define LCHANPC18    0x00000F00lu
-#define LCHANPC19    0x0000F000lu
-#define LCHANPC20    0x000F0000lu
-#define LCHANPC21    0x00F00000lu
-#define LCHANPC22    0x0F000000lu
-#define LCHANPC23    0xF0000000lu
-
-
-/* MXVR_SYNC_LCHAN_3 Masks */
-
-#define LCHANPC24    0x0000000Flu
-#define LCHANPC25    0x000000F0lu
-#define LCHANPC26    0x00000F00lu
-#define LCHANPC27    0x0000F000lu
-#define LCHANPC28    0x000F0000lu
-#define LCHANPC29    0x00F00000lu
-#define LCHANPC30    0x0F000000lu
-#define LCHANPC31    0xF0000000lu
-
-
-/* MXVR_SYNC_LCHAN_4 Masks */
-
-#define LCHANPC32    0x0000000Flu
-#define LCHANPC33    0x000000F0lu
-#define LCHANPC34    0x00000F00lu
-#define LCHANPC35    0x0000F000lu
-#define LCHANPC36    0x000F0000lu
-#define LCHANPC37    0x00F00000lu
-#define LCHANPC38    0x0F000000lu
-#define LCHANPC39    0xF0000000lu
-
-
-/* MXVR_SYNC_LCHAN_5 Masks */
-
-#define LCHANPC40    0x0000000Flu
-#define LCHANPC41    0x000000F0lu
-#define LCHANPC42    0x00000F00lu
-#define LCHANPC43    0x0000F000lu
-#define LCHANPC44    0x000F0000lu
-#define LCHANPC45    0x00F00000lu
-#define LCHANPC46    0x0F000000lu
-#define LCHANPC47    0xF0000000lu
-
-
-/* MXVR_SYNC_LCHAN_6 Masks */
-
-#define LCHANPC48    0x0000000Flu
-#define LCHANPC49    0x000000F0lu
-#define LCHANPC50    0x00000F00lu
-#define LCHANPC51    0x0000F000lu
-#define LCHANPC52    0x000F0000lu
-#define LCHANPC53    0x00F00000lu
-#define LCHANPC54    0x0F000000lu
-#define LCHANPC55    0xF0000000lu
-
-
-/* MXVR_SYNC_LCHAN_7 Masks */
-
-#define LCHANPC56    0x0000000Flu
-#define LCHANPC57    0x000000F0lu
-#define LCHANPC58    0x00000F00lu
-#define LCHANPC59    0x0000F000lu
-
-
-/* MXVR_DMAx_CONFIG Masks */
-
-#define MDMAEN      0x00000001lu
-#define DD          0x00000002lu
-#define LCHAN       0x000003C0lu
-#define BITSWAPEN   0x00000400lu
-#define BYSWAPEN    0x00000800lu
-#define MFLOW       0x00007000lu
-#define FIXEDPM     0x00080000lu
-#define STARTPAT    0x00300000lu
-#define STOPPAT     0x00C00000lu
-#define COUNTPOS    0x1C000000lu
-
-#define DD_TX       0x00000000lu
-#define DD_RX       0x00000002lu
-
-#define LCHAN_0     0x00000000lu
-#define LCHAN_1     0x00000040lu
-#define LCHAN_2     0x00000080lu
-#define LCHAN_3     0x000000C0lu
-#define LCHAN_4     0x00000100lu
-#define LCHAN_5     0x00000140lu
-#define LCHAN_6     0x00000180lu
-#define LCHAN_7     0x000001C0lu
-
-#define MFLOW_STOP  0x00000000lu
-#define MFLOW_AUTO  0x00001000lu
-#define MFLOW_PVC   0x00002000lu
-#define MFLOW_PSS   0x00003000lu
-#define MFLOW_PFC   0x00004000lu
-
-#define STARTPAT_0  0x00000000lu
-#define STARTPAT_1  0x00100000lu
-
-#define STOPPAT_0   0x00000000lu
-#define STOPPAT_1   0x00400000lu
-
-#define COUNTPOS_0  0x00000000lu
-#define COUNTPOS_1  0x04000000lu
-#define COUNTPOS_2  0x08000000lu
-#define COUNTPOS_3  0x0C000000lu
-#define COUNTPOS_4  0x10000000lu
-#define COUNTPOS_5  0x14000000lu
-#define COUNTPOS_6  0x18000000lu
-#define COUNTPOS_7  0x1C000000lu
-
-
-/* MXVR_AP_CTL Masks */
-
-#define STARTAP    0x00000001lu
-#define CANCELAP   0x00000002lu
-#define RESETAP    0x00000004lu
-#define APRBE0     0x00004000lu
-#define APRBE1     0x00008000lu
-#define APRBEX     0x0000C000lu
-
-
-/* MXVR_CM_CTL Masks */
-
-#define STARTCM    0x00000001lu
-#define CANCELCM   0x00000002lu
-#define CMRBEX     0xFFFF0000lu
-#define CMRBE0     0x00010000lu
-#define CMRBE1     0x00020000lu
-#define CMRBE2     0x00040000lu
-#define CMRBE3     0x00080000lu
-#define CMRBE4     0x00100000lu
-#define CMRBE5     0x00200000lu
-#define CMRBE6     0x00400000lu
-#define CMRBE7     0x00800000lu
-#define CMRBE8     0x01000000lu
-#define CMRBE9     0x02000000lu
-#define CMRBE10    0x04000000lu
-#define CMRBE11    0x08000000lu
-#define CMRBE12    0x10000000lu
-#define CMRBE13    0x20000000lu
-#define CMRBE14    0x40000000lu
-#define CMRBE15    0x80000000lu
-
-
-/* MXVR_PAT_DATA_x Masks */
-
-#define MATCH_DATA_0 0x000000FFlu
-#define MATCH_DATA_1 0x0000FF00lu
-#define MATCH_DATA_2 0x00FF0000lu
-#define MATCH_DATA_3 0xFF000000lu
-
-
-
-/* MXVR_PAT_EN_x Masks */
-
-#define MATCH_EN_0_0 0x00000001lu
-#define MATCH_EN_0_1 0x00000002lu
-#define MATCH_EN_0_2 0x00000004lu
-#define MATCH_EN_0_3 0x00000008lu
-#define MATCH_EN_0_4 0x00000010lu
-#define MATCH_EN_0_5 0x00000020lu
-#define MATCH_EN_0_6 0x00000040lu
-#define MATCH_EN_0_7 0x00000080lu
-
-#define MATCH_EN_1_0 0x00000100lu
-#define MATCH_EN_1_1 0x00000200lu
-#define MATCH_EN_1_2 0x00000400lu
-#define MATCH_EN_1_3 0x00000800lu
-#define MATCH_EN_1_4 0x00001000lu
-#define MATCH_EN_1_5 0x00002000lu
-#define MATCH_EN_1_6 0x00004000lu
-#define MATCH_EN_1_7 0x00008000lu
-
-#define MATCH_EN_2_0 0x00010000lu
-#define MATCH_EN_2_1 0x00020000lu
-#define MATCH_EN_2_2 0x00040000lu
-#define MATCH_EN_2_3 0x00080000lu
-#define MATCH_EN_2_4 0x00100000lu
-#define MATCH_EN_2_5 0x00200000lu
-#define MATCH_EN_2_6 0x00400000lu
-#define MATCH_EN_2_7 0x00800000lu
-
-#define MATCH_EN_3_0 0x01000000lu
-#define MATCH_EN_3_1 0x02000000lu
-#define MATCH_EN_3_2 0x04000000lu
-#define MATCH_EN_3_3 0x08000000lu
-#define MATCH_EN_3_4 0x10000000lu
-#define MATCH_EN_3_5 0x20000000lu
-#define MATCH_EN_3_6 0x40000000lu
-#define MATCH_EN_3_7 0x80000000lu
-
-
-/* MXVR_ROUTING_0 Masks */
-
-#define MUTE_CH0        0x00000080lu
-#define MUTE_CH1        0x00008000lu
-#define MUTE_CH2        0x00800000lu
-#define MUTE_CH3        0x80000000lu
-
-#define TX_CH0          0x0000007Flu
-#define TX_CH1          0x00007F00lu
-#define TX_CH2          0x007F0000lu
-#define TX_CH3          0x7F000000lu
-
-
-/* MXVR_ROUTING_1 Masks */
-
-#define MUTE_CH4        0x00000080lu
-#define MUTE_CH5        0x00008000lu
-#define MUTE_CH6        0x00800000lu
-#define MUTE_CH7        0x80000000lu
-
-#define TX_CH4          0x0000007Flu
-#define TX_CH5          0x00007F00lu
-#define TX_CH6          0x007F0000lu
-#define TX_CH7          0x7F000000lu
-
-
-/* MXVR_ROUTING_2 Masks */
-
-#define MUTE_CH8        0x00000080lu
-#define MUTE_CH9        0x00008000lu
-#define MUTE_CH10       0x00800000lu
-#define MUTE_CH11       0x80000000lu
-
-#define TX_CH8          0x0000007Flu
-#define TX_CH9          0x00007F00lu
-#define TX_CH10         0x007F0000lu
-#define TX_CH11         0x7F000000lu
-
-/* MXVR_ROUTING_3 Masks */
-
-#define MUTE_CH12       0x00000080lu
-#define MUTE_CH13       0x00008000lu
-#define MUTE_CH14       0x00800000lu
-#define MUTE_CH15       0x80000000lu
-
-#define TX_CH12         0x0000007Flu
-#define TX_CH13         0x00007F00lu
-#define TX_CH14         0x007F0000lu
-#define TX_CH15         0x7F000000lu
-
-
-/* MXVR_ROUTING_4 Masks */
-
-#define MUTE_CH16       0x00000080lu
-#define MUTE_CH17       0x00008000lu
-#define MUTE_CH18       0x00800000lu
-#define MUTE_CH19       0x80000000lu
-
-#define TX_CH16         0x0000007Flu
-#define TX_CH17         0x00007F00lu
-#define TX_CH18         0x007F0000lu
-#define TX_CH19         0x7F000000lu
-
-
-/* MXVR_ROUTING_5 Masks */
-
-#define MUTE_CH20       0x00000080lu
-#define MUTE_CH21       0x00008000lu
-#define MUTE_CH22       0x00800000lu
-#define MUTE_CH23       0x80000000lu
-
-#define TX_CH20         0x0000007Flu
-#define TX_CH21         0x00007F00lu
-#define TX_CH22         0x007F0000lu
-#define TX_CH23         0x7F000000lu
-
-
-/* MXVR_ROUTING_6 Masks */
-
-#define MUTE_CH24       0x00000080lu
-#define MUTE_CH25       0x00008000lu
-#define MUTE_CH26       0x00800000lu
-#define MUTE_CH27       0x80000000lu
-
-#define TX_CH24         0x0000007Flu
-#define TX_CH25         0x00007F00lu
-#define TX_CH26         0x007F0000lu
-#define TX_CH27         0x7F000000lu
-
-
-/* MXVR_ROUTING_7 Masks */
-
-#define MUTE_CH28       0x00000080lu
-#define MUTE_CH29       0x00008000lu
-#define MUTE_CH30       0x00800000lu
-#define MUTE_CH31       0x80000000lu
-
-#define TX_CH28         0x0000007Flu
-#define TX_CH29         0x00007F00lu
-#define TX_CH30         0x007F0000lu
-#define TX_CH31         0x7F000000lu
-
-
-/* MXVR_ROUTING_8 Masks */
-
-#define MUTE_CH32       0x00000080lu
-#define MUTE_CH33       0x00008000lu
-#define MUTE_CH34       0x00800000lu
-#define MUTE_CH35       0x80000000lu
-
-#define TX_CH32         0x0000007Flu
-#define TX_CH33         0x00007F00lu
-#define TX_CH34         0x007F0000lu
-#define TX_CH35         0x7F000000lu
-
-
-/* MXVR_ROUTING_9 Masks */
-
-#define MUTE_CH36       0x00000080lu
-#define MUTE_CH37       0x00008000lu
-#define MUTE_CH38       0x00800000lu
-#define MUTE_CH39       0x80000000lu
-
-#define TX_CH36         0x0000007Flu
-#define TX_CH37         0x00007F00lu
-#define TX_CH38         0x007F0000lu
-#define TX_CH39         0x7F000000lu
-
-
-/* MXVR_ROUTING_10 Masks */
-
-#define MUTE_CH40       0x00000080lu
-#define MUTE_CH41       0x00008000lu
-#define MUTE_CH42       0x00800000lu
-#define MUTE_CH43       0x80000000lu
-
-#define TX_CH40         0x0000007Flu
-#define TX_CH41         0x00007F00lu
-#define TX_CH42         0x007F0000lu
-#define TX_CH43         0x7F000000lu
-
-
-/* MXVR_ROUTING_11 Masks */
-
-#define MUTE_CH44       0x00000080lu
-#define MUTE_CH45       0x00008000lu
-#define MUTE_CH46       0x00800000lu
-#define MUTE_CH47       0x80000000lu
-
-#define TX_CH44         0x0000007Flu
-#define TX_CH45         0x00007F00lu
-#define TX_CH46         0x007F0000lu
-#define TX_CH47         0x7F000000lu
-
-
-/* MXVR_ROUTING_12 Masks */
-
-#define MUTE_CH48       0x00000080lu
-#define MUTE_CH49       0x00008000lu
-#define MUTE_CH50       0x00800000lu
-#define MUTE_CH51       0x80000000lu
-
-#define TX_CH48         0x0000007Flu
-#define TX_CH49         0x00007F00lu
-#define TX_CH50         0x007F0000lu
-#define TX_CH51         0x7F000000lu
-
-
-/* MXVR_ROUTING_13 Masks */
-
-#define MUTE_CH52       0x00000080lu
-#define MUTE_CH53       0x00008000lu
-#define MUTE_CH54       0x00800000lu
-#define MUTE_CH55       0x80000000lu
-
-#define TX_CH52         0x0000007Flu
-#define TX_CH53         0x00007F00lu
-#define TX_CH54         0x007F0000lu
-#define TX_CH55         0x7F000000lu
-
-
-/* MXVR_ROUTING_14 Masks */
-
-#define MUTE_CH56       0x00000080lu
-#define MUTE_CH57       0x00008000lu
-#define MUTE_CH58       0x00800000lu
-#define MUTE_CH59       0x80000000lu
-
-#define TX_CH56         0x0000007Flu
-#define TX_CH57         0x00007F00lu
-#define TX_CH58         0x007F0000lu
-#define TX_CH59         0x7F000000lu
-
-
-/* Control Message Receive Buffer (CMRB) Address Offsets */
-
-#define CMRB_STRIDE       0x00000016lu
-
-#define CMRB_DST_OFFSET   0x00000000lu
-#define CMRB_SRC_OFFSET   0x00000002lu
-#define CMRB_DATA_OFFSET  0x00000005lu
-
-
-/* Control Message Transmit Buffer (CMTB) Address Offsets */
-
-#define CMTB_PRIO_OFFSET    0x00000000lu
-#define CMTB_DST_OFFSET     0x00000002lu
-#define CMTB_SRC_OFFSET     0x00000004lu
-#define CMTB_TYPE_OFFSET    0x00000006lu
-#define CMTB_DATA_OFFSET    0x00000007lu
-
-#define CMTB_ANSWER_OFFSET  0x0000000Alu
-
-#define CMTB_STAT_N_OFFSET  0x00000018lu
-#define CMTB_STAT_A_OFFSET  0x00000016lu
-#define CMTB_STAT_D_OFFSET  0x0000000Elu
-#define CMTB_STAT_R_OFFSET  0x00000014lu
-#define CMTB_STAT_W_OFFSET  0x00000014lu
-#define CMTB_STAT_G_OFFSET  0x00000014lu
-
-
-/* Asynchronous Packet Receive Buffer (APRB) Address Offsets */
-
-#define APRB_STRIDE       0x00000400lu
-
-#define APRB_DST_OFFSET   0x00000000lu
-#define APRB_LEN_OFFSET   0x00000002lu
-#define APRB_SRC_OFFSET   0x00000004lu
-#define APRB_DATA_OFFSET  0x00000006lu
-
-
-/* Asynchronous Packet Transmit Buffer (APTB) Address Offsets */
-
-#define APTB_PRIO_OFFSET  0x00000000lu
-#define APTB_DST_OFFSET   0x00000002lu
-#define APTB_LEN_OFFSET   0x00000004lu
-#define APTB_SRC_OFFSET   0x00000006lu
-#define APTB_DATA_OFFSET  0x00000008lu
-
-
-/* Remote Read Buffer (RRDB) Address Offsets */
-
-#define RRDB_WADDR_OFFSET 0x00000100lu
-#define RRDB_WLEN_OFFSET  0x00000101lu
-
-
-
 /* ************  CONTROLLER AREA NETWORK (CAN) MASKS  ***************/
 /* CAN_CONTROL Masks                                     */
 #define SRS                     0x0001  /* Software Reset */
diff --git a/arch/blackfin/mach-bf538/include/mach/gpio.h b/arch/blackfin/mach-bf538/include/mach/gpio.h
index 295c78a465c2..0c346fba9619 100644
--- a/arch/blackfin/mach-bf538/include/mach/gpio.h
+++ b/arch/blackfin/mach-bf538/include/mach/gpio.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2008 Analog Devices Inc.
+ * Copyright (C) 2008-2009 Analog Devices Inc.
  * Licensed under the GPL-2 or later.
  */
 
@@ -7,11 +7,8 @@
 #ifndef _MACH_GPIO_H_
 #define _MACH_GPIO_H_
 
-        /* FIXME:
-         * For now only support PORTF GPIOs.
-         * PORT C,D and E are for peripheral usage only
-         */
 #define MAX_BLACKFIN_GPIOS 16
+#define BFIN_SPECIAL_GPIO_BANKS 3
 
 #define GPIO_PF0        0       /* PF */
 #define GPIO_PF1        1
diff --git a/arch/blackfin/mach-bf538/include/mach/portmux.h b/arch/blackfin/mach-bf538/include/mach/portmux.h
index 6121cf8b5872..0083ba13ee9e 100644
--- a/arch/blackfin/mach-bf538/include/mach/portmux.h
+++ b/arch/blackfin/mach-bf538/include/mach/portmux.h
@@ -7,7 +7,7 @@
 #ifndef _MACH_PORTMUX_H_
 #define _MACH_PORTMUX_H_
 
-#define MAX_RESOURCES   MAX_BLACKFIN_GPIOS
+#define MAX_RESOURCES   64
 
 #define P_TMR2          (P_DONTCARE)
 #define P_TMR1          (P_DONTCARE)
diff --git a/arch/blackfin/mach-bf548/Kconfig b/arch/blackfin/mach-bf548/Kconfig
index a09623dfd550..70189a0d1a19 100644
--- a/arch/blackfin/mach-bf548/Kconfig
+++ b/arch/blackfin/mach-bf548/Kconfig
@@ -1,3 +1,27 @@
+config BF542
+        def_bool y
+        depends on BF542_std || BF542M
+config BF544
+        def_bool y
+        depends on BF544_std || BF544M
+config BF547
+        def_bool y
+        depends on BF547_std || BF547M
+config BF548
+        def_bool y
+        depends on BF548_std || BF548M
+config BF549
+        def_bool y
+        depends on BF549_std || BF549M
+
+config BF54xM
+        def_bool y
+        depends on (BF542M || BF544M || BF547M || BF548M || BF549M)
+
+config BF54x
+        def_bool y
+        depends on (BF542 || BF544 || BF547 || BF548 || BF549)
+
 if (BF54x)
 
 source "arch/blackfin/mach-bf548/boards/Kconfig"
diff --git a/arch/blackfin/mach-bf548/boards/ezkit.c b/arch/blackfin/mach-bf548/boards/ezkit.c
index 1a5286bbb3fa..60193f72777c 100644
--- a/arch/blackfin/mach-bf548/boards/ezkit.c
+++ b/arch/blackfin/mach-bf548/boards/ezkit.c
@@ -62,7 +62,7 @@ static struct isp1760_platform_data isp1760_priv = {
 };
 
 static struct platform_device bfin_isp1760_device = {
-        .name           = "isp1760-hcd",
+        .name           = "isp1760",
         .id             = 0,
         .dev = {
                 .platform_data = &isp1760_priv,
@@ -154,7 +154,7 @@ static struct platform_device bf54x_kpad_device = {
 };
 #endif
 
-#if defined(CONFIG_JOYSTICK_BFIN_ROTARY) || defined(CONFIG_JOYSTICK_BFIN_ROTARY_MODULE)
+#if defined(CONFIG_INPUT_BFIN_ROTARY) || defined(CONFIG_INPUT_BFIN_ROTARY_MODULE)
 #include <asm/bfin_rotary.h>
 
 static struct bfin_rotary_platform_data bfin_rotary_data = {
@@ -186,7 +186,7 @@ static struct platform_device bfin_rotary_device = {
 #endif
 
 #if defined(CONFIG_INPUT_ADXL34X) || defined(CONFIG_INPUT_ADXL34X_MODULE)
-#include <linux/spi/adxl34x.h>
+#include <linux/input/adxl34x.h>
 static const struct adxl34x_platform_data adxl34x_info = {
         .x_axis_offset = 0,
         .y_axis_offset = 0,
@@ -210,14 +210,17 @@ static const struct adxl34x_platform_data adxl34x_info = {
         .ev_code_y = ABS_Y,             /* EV_REL */
         .ev_code_z = ABS_Z,             /* EV_REL */
 
-        .ev_code_tap_x = BTN_TOUCH,             /* EV_KEY */
-        .ev_code_tap_y = BTN_TOUCH,             /* EV_KEY */
-        .ev_code_tap_z = BTN_TOUCH,             /* EV_KEY */
+        .ev_code_tap = {BTN_TOUCH, BTN_TOUCH, BTN_TOUCH}, /* EV_KEY x,y,z */
 
 /*      .ev_code_ff = KEY_F,*/          /* EV_KEY */
 /*      .ev_code_act_inactivity = KEY_A,*/      /* EV_KEY */
         .power_mode = ADXL_AUTO_SLEEP | ADXL_LINK,
         .fifo_mode = ADXL_FIFO_STREAM,
+        .orientation_enable = ADXL_EN_ORIENTATION_3D,
+        .deadzone_angle = ADXL_DEADZONE_ANGLE_10p8,
+        .divisor_length = ADXL_LP_FILTER_DIVISOR_16,
+        /* EV_KEY {+Z, +Y, +X, -X, -Y, -Z} */
+        .ev_codes_orient_3d = {BTN_Z, BTN_Y, BTN_X, BTN_A, BTN_B, BTN_C},
 };
 #endif
 
@@ -461,6 +464,44 @@ static struct platform_device musb_device = {
 };
 #endif
 
+#if defined(CONFIG_CAN_BFIN) || defined(CONFIG_CAN_BFIN_MODULE)
+unsigned short bfin_can_peripherals[] = {
+        P_CAN0_RX, P_CAN0_TX, 0
+};
+
+static struct resource bfin_can_resources[] = {
+        {
+                .start = 0xFFC02A00,
+                .end = 0xFFC02FFF,
+                .flags = IORESOURCE_MEM,
+        },
+        {
+                .start = IRQ_CAN0_RX,
+                .end = IRQ_CAN0_RX,
+                .flags = IORESOURCE_IRQ,
+        },
+        {
+                .start = IRQ_CAN0_TX,
+                .end = IRQ_CAN0_TX,
+                .flags = IORESOURCE_IRQ,
+        },
+        {
+                .start = IRQ_CAN0_ERROR,
+                .end = IRQ_CAN0_ERROR,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device bfin_can_device = {
+        .name = "bfin_can",
+        .num_resources = ARRAY_SIZE(bfin_can_resources),
+        .resource = bfin_can_resources,
+        .dev = {
+                .platform_data = &bfin_can_peripherals, /* Passed to driver */
+        },
+};
+#endif
+
 #if defined(CONFIG_PATA_BF54X) || defined(CONFIG_PATA_BF54X_MODULE)
 static struct resource bfin_atapi_resources[] = {
         {
@@ -953,6 +994,10 @@ static struct platform_device *ezkit_devices[] __initdata = {
         &bfin_isp1760_device,
 #endif
 
+#if defined(CONFIG_CAN_BFIN) || defined(CONFIG_CAN_BFIN_MODULE)
+        &bfin_can_device,
+#endif
+
 #if defined(CONFIG_PATA_BF54X) || defined(CONFIG_PATA_BF54X_MODULE)
         &bfin_atapi_device,
 #endif
@@ -974,7 +1019,7 @@ static struct platform_device *ezkit_devices[] __initdata = {
         &bf54x_kpad_device,
 #endif
 
-#if defined(CONFIG_JOYSTICK_BFIN_ROTARY) || defined(CONFIG_JOYSTICK_BFIN_ROTARY_MODULE)
+#if defined(CONFIG_INPUT_BFIN_ROTARY) || defined(CONFIG_INPUT_BFIN_ROTARY_MODULE)
         &bfin_rotary_device,
 #endif
 
diff --git a/arch/blackfin/mach-bf548/include/mach/bf548.h b/arch/blackfin/mach-bf548/include/mach/bf548.h
index 7bead5ce0f3b..751e5e11ecf8 100644
--- a/arch/blackfin/mach-bf548/include/mach/bf548.h
+++ b/arch/blackfin/mach-bf548/include/mach/bf548.h
@@ -81,18 +81,6 @@
 
 #define AMGCTLVAL       (V_AMBEN | V_AMCKEN)
 
-#if defined(CONFIG_BF542M)
-# define CONFIG_BF542
-#elif defined(CONFIG_BF544M)
-# define CONFIG_BF544
-#elif defined(CONFIG_BF547M)
-# define CONFIG_BF547
-#elif defined(CONFIG_BF548M)
-# define CONFIG_BF548
-#elif defined(CONFIG_BF549M)
-# define CONFIG_BF549
-#endif
-
 #if defined(CONFIG_BF542)
 # define CPU   "BF542"
 # define CPUID 0x27de
diff --git a/arch/blackfin/mach-bf548/include/mach/blackfin.h b/arch/blackfin/mach-bf548/include/mach/blackfin.h
index 13302b67857a..5684030ccc21 100644
--- a/arch/blackfin/mach-bf548/include/mach/blackfin.h
+++ b/arch/blackfin/mach-bf548/include/mach/blackfin.h
@@ -64,10 +64,4 @@
 #define OFFSET_THR              0x28    /* Transmit Holding register            */
 #define OFFSET_RBR              0x2C    /* Receive Buffer register              */
 
-/* PLL_DIV Masks */
-#define CCLK_DIV1 CSEL_DIV1     /* CCLK = VCO / 1 */
-#define CCLK_DIV2 CSEL_DIV2     /* CCLK = VCO / 2 */
-#define CCLK_DIV4 CSEL_DIV4     /* CCLK = VCO / 4 */
-#define CCLK_DIV8 CSEL_DIV8     /* CCLK = VCO / 8 */
-
 #endif
diff --git a/arch/blackfin/mach-bf548/include/mach/cdefBF547.h b/arch/blackfin/mach-bf548/include/mach/cdefBF547.h
index 423421515134..bc650e6ea482 100644
--- a/arch/blackfin/mach-bf548/include/mach/cdefBF547.h
+++ b/arch/blackfin/mach-bf548/include/mach/cdefBF547.h
@@ -4,21 +4,21 @@
  * Licensed under the GPL-2 or later.
  */
 
-#ifndef _CDEF_BF548_H
-#define _CDEF_BF548_H
+#ifndef _CDEF_BF547_H
+#define _CDEF_BF547_H
 
 /* include all Core registers and bit definitions */
-#include "defBF548.h"
+#include "defBF547.h"
 
 /* include core sbfin_read_()ecific register pointer definitions */
 #include <asm/cdef_LPBlackfin.h>
 
-/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF548 */
+/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF547 */
 
 /* include cdefBF54x_base.h for the set of #defines that are common to all ADSP-BF54x bfin_read_()rocessors */
 #include "cdefBF54x_base.h"
 
-/* The following are the #defines needed by ADSP-BF548 that are not in the common header */
+/* The following are the #defines needed by ADSP-BF547 that are not in the common header */
 
 /* Timer Registers */
 
@@ -805,4 +805,4 @@
 #define bfin_read_HMDMA1_BCOUNT()               bfin_read16(HMDMA1_BCOUNT)
 #define bfin_write_HMDMA1_BCOUNT(val)           bfin_write16(HMDMA1_BCOUNT, val)
 
-#endif /* _CDEF_BF548_H */
+#endif /* _CDEF_BF547_H */
diff --git a/arch/blackfin/mach-bf548/include/mach/cdefBF548.h b/arch/blackfin/mach-bf548/include/mach/cdefBF548.h
index df84180410c4..3523e08f7968 100644
--- a/arch/blackfin/mach-bf548/include/mach/cdefBF548.h
+++ b/arch/blackfin/mach-bf548/include/mach/cdefBF548.h
@@ -18,165 +18,8 @@
 /* include cdefBF54x_base.h for the set of #defines that are common to all ADSP-BF54x bfin_read_()rocessors */
 #include "cdefBF54x_base.h"
 
-/* The following are the #defines needed by ADSP-BF548 that are not in the common header */
-
-/* Timer Registers */
-
-#define bfin_read_TIMER8_CONFIG()       bfin_read16(TIMER8_CONFIG)
-#define bfin_write_TIMER8_CONFIG(val)   bfin_write16(TIMER8_CONFIG, val)
-#define bfin_read_TIMER8_COUNTER()      bfin_read32(TIMER8_COUNTER)
-#define bfin_write_TIMER8_COUNTER(val)  bfin_write32(TIMER8_COUNTER, val)
-#define bfin_read_TIMER8_PERIOD()       bfin_read32(TIMER8_PERIOD)
-#define bfin_write_TIMER8_PERIOD(val)   bfin_write32(TIMER8_PERIOD, val)
-#define bfin_read_TIMER8_WIDTH()        bfin_read32(TIMER8_WIDTH)
-#define bfin_write_TIMER8_WIDTH(val)    bfin_write32(TIMER8_WIDTH, val)
-#define bfin_read_TIMER9_CONFIG()       bfin_read16(TIMER9_CONFIG)
-#define bfin_write_TIMER9_CONFIG(val)   bfin_write16(TIMER9_CONFIG, val)
-#define bfin_read_TIMER9_COUNTER()      bfin_read32(TIMER9_COUNTER)
-#define bfin_write_TIMER9_COUNTER(val)  bfin_write32(TIMER9_COUNTER, val)
-#define bfin_read_TIMER9_PERIOD()       bfin_read32(TIMER9_PERIOD)
-#define bfin_write_TIMER9_PERIOD(val)   bfin_write32(TIMER9_PERIOD, val)
-#define bfin_read_TIMER9_WIDTH()        bfin_read32(TIMER9_WIDTH)
-#define bfin_write_TIMER9_WIDTH(val)    bfin_write32(TIMER9_WIDTH, val)
-#define bfin_read_TIMER10_CONFIG()      bfin_read16(TIMER10_CONFIG)
-#define bfin_write_TIMER10_CONFIG(val)  bfin_write16(TIMER10_CONFIG, val)
-#define bfin_read_TIMER10_COUNTER()     bfin_read32(TIMER10_COUNTER)
-#define bfin_write_TIMER10_COUNTER(val) bfin_write32(TIMER10_COUNTER, val)
-#define bfin_read_TIMER10_PERIOD()      bfin_read32(TIMER10_PERIOD)
-#define bfin_write_TIMER10_PERIOD(val)  bfin_write32(TIMER10_PERIOD, val)
-#define bfin_read_TIMER10_WIDTH()       bfin_read32(TIMER10_WIDTH)
-#define bfin_write_TIMER10_WIDTH(val)   bfin_write32(TIMER10_WIDTH, val)
-
-/* Timer Groubfin_read_() of 3 */
-
-#define bfin_read_TIMER_ENABLE1()       bfin_read16(TIMER_ENABLE1)
-#define bfin_write_TIMER_ENABLE1(val)   bfin_write16(TIMER_ENABLE1, val)
-#define bfin_read_TIMER_DISABLE1()      bfin_read16(TIMER_DISABLE1)
-#define bfin_write_TIMER_DISABLE1(val)  bfin_write16(TIMER_DISABLE1, val)
-#define bfin_read_TIMER_STATUS1()       bfin_read32(TIMER_STATUS1)
-#define bfin_write_TIMER_STATUS1(val)   bfin_write32(TIMER_STATUS1, val)
-
-/* SPORT0 Registers */
-
-#define bfin_read_SPORT0_TCR1()         bfin_read16(SPORT0_TCR1)
-#define bfin_write_SPORT0_TCR1(val)     bfin_write16(SPORT0_TCR1, val)
-#define bfin_read_SPORT0_TCR2()         bfin_read16(SPORT0_TCR2)
-#define bfin_write_SPORT0_TCR2(val)     bfin_write16(SPORT0_TCR2, val)
-#define bfin_read_SPORT0_TCLKDIV()      bfin_read16(SPORT0_TCLKDIV)
-#define bfin_write_SPORT0_TCLKDIV(val)  bfin_write16(SPORT0_TCLKDIV, val)
-#define bfin_read_SPORT0_TFSDIV()       bfin_read16(SPORT0_TFSDIV)
-#define bfin_write_SPORT0_TFSDIV(val)   bfin_write16(SPORT0_TFSDIV, val)
-#define bfin_read_SPORT0_TX()           bfin_read32(SPORT0_TX)
-#define bfin_write_SPORT0_TX(val)       bfin_write32(SPORT0_TX, val)
-#define bfin_read_SPORT0_RX()           bfin_read32(SPORT0_RX)
-#define bfin_write_SPORT0_RX(val)       bfin_write32(SPORT0_RX, val)
-#define bfin_read_SPORT0_RCR1()         bfin_read16(SPORT0_RCR1)
-#define bfin_write_SPORT0_RCR1(val)     bfin_write16(SPORT0_RCR1, val)
-#define bfin_read_SPORT0_RCR2()         bfin_read16(SPORT0_RCR2)
-#define bfin_write_SPORT0_RCR2(val)     bfin_write16(SPORT0_RCR2, val)
-#define bfin_read_SPORT0_RCLKDIV()      bfin_read16(SPORT0_RCLKDIV)
-#define bfin_write_SPORT0_RCLKDIV(val)  bfin_write16(SPORT0_RCLKDIV, val)
-#define bfin_read_SPORT0_RFSDIV()       bfin_read16(SPORT0_RFSDIV)
-#define bfin_write_SPORT0_RFSDIV(val)   bfin_write16(SPORT0_RFSDIV, val)
-#define bfin_read_SPORT0_STAT()         bfin_read16(SPORT0_STAT)
-#define bfin_write_SPORT0_STAT(val)     bfin_write16(SPORT0_STAT, val)
-#define bfin_read_SPORT0_CHNL()         bfin_read16(SPORT0_CHNL)
-#define bfin_write_SPORT0_CHNL(val)     bfin_write16(SPORT0_CHNL, val)
-#define bfin_read_SPORT0_MCMC1()        bfin_read16(SPORT0_MCMC1)
-#define bfin_write_SPORT0_MCMC1(val)    bfin_write16(SPORT0_MCMC1, val)
-#define bfin_read_SPORT0_MCMC2()        bfin_read16(SPORT0_MCMC2)
-#define bfin_write_SPORT0_MCMC2(val)    bfin_write16(SPORT0_MCMC2, val)
-#define bfin_read_SPORT0_MTCS0()        bfin_read32(SPORT0_MTCS0)
-#define bfin_write_SPORT0_MTCS0(val)    bfin_write32(SPORT0_MTCS0, val)
-#define bfin_read_SPORT0_MTCS1()        bfin_read32(SPORT0_MTCS1)
-#define bfin_write_SPORT0_MTCS1(val)    bfin_write32(SPORT0_MTCS1, val)
-#define bfin_read_SPORT0_MTCS2()        bfin_read32(SPORT0_MTCS2)
-#define bfin_write_SPORT0_MTCS2(val)    bfin_write32(SPORT0_MTCS2, val)
-#define bfin_read_SPORT0_MTCS3()        bfin_read32(SPORT0_MTCS3)
-#define bfin_write_SPORT0_MTCS3(val)    bfin_write32(SPORT0_MTCS3, val)
-#define bfin_read_SPORT0_MRCS0()        bfin_read32(SPORT0_MRCS0)
-#define bfin_write_SPORT0_MRCS0(val)    bfin_write32(SPORT0_MRCS0, val)
-#define bfin_read_SPORT0_MRCS1()        bfin_read32(SPORT0_MRCS1)
-#define bfin_write_SPORT0_MRCS1(val)    bfin_write32(SPORT0_MRCS1, val)
-#define bfin_read_SPORT0_MRCS2()        bfin_read32(SPORT0_MRCS2)
-#define bfin_write_SPORT0_MRCS2(val)    bfin_write32(SPORT0_MRCS2, val)
-#define bfin_read_SPORT0_MRCS3()        bfin_read32(SPORT0_MRCS3)
-#define bfin_write_SPORT0_MRCS3(val)    bfin_write32(SPORT0_MRCS3, val)
-
-/* EPPI0 Registers */
-
-#define bfin_read_EPPI0_STATUS()        bfin_read16(EPPI0_STATUS)
-#define bfin_write_EPPI0_STATUS(val)    bfin_write16(EPPI0_STATUS, val)
-#define bfin_read_EPPI0_HCOUNT()        bfin_read16(EPPI0_HCOUNT)
-#define bfin_write_EPPI0_HCOUNT(val)    bfin_write16(EPPI0_HCOUNT, val)
-#define bfin_read_EPPI0_HDELAY()        bfin_read16(EPPI0_HDELAY)
-#define bfin_write_EPPI0_HDELAY(val)    bfin_write16(EPPI0_HDELAY, val)
-#define bfin_read_EPPI0_VCOUNT()        bfin_read16(EPPI0_VCOUNT)
-#define bfin_write_EPPI0_VCOUNT(val)    bfin_write16(EPPI0_VCOUNT, val)
-#define bfin_read_EPPI0_VDELAY()        bfin_read16(EPPI0_VDELAY)
-#define bfin_write_EPPI0_VDELAY(val)    bfin_write16(EPPI0_VDELAY, val)
-#define bfin_read_EPPI0_FRAME()         bfin_read16(EPPI0_FRAME)
-#define bfin_write_EPPI0_FRAME(val)     bfin_write16(EPPI0_FRAME, val)
-#define bfin_read_EPPI0_LINE()          bfin_read16(EPPI0_LINE)
-#define bfin_write_EPPI0_LINE(val)      bfin_write16(EPPI0_LINE, val)
-#define bfin_read_EPPI0_CLKDIV()        bfin_read16(EPPI0_CLKDIV)
-#define bfin_write_EPPI0_CLKDIV(val)    bfin_write16(EPPI0_CLKDIV, val)
-#define bfin_read_EPPI0_CONTROL()       bfin_read32(EPPI0_CONTROL)
-#define bfin_write_EPPI0_CONTROL(val)   bfin_write32(EPPI0_CONTROL, val)
-#define bfin_read_EPPI0_FS1W_HBL()      bfin_read32(EPPI0_FS1W_HBL)
-#define bfin_write_EPPI0_FS1W_HBL(val)  bfin_write32(EPPI0_FS1W_HBL, val)
-#define bfin_read_EPPI0_FS1P_AVPL()     bfin_read32(EPPI0_FS1P_AVPL)
-#define bfin_write_EPPI0_FS1P_AVPL(val) bfin_write32(EPPI0_FS1P_AVPL, val)
-#define bfin_read_EPPI0_FS2W_LVB()      bfin_read32(EPPI0_FS2W_LVB)
-#define bfin_write_EPPI0_FS2W_LVB(val)  bfin_write32(EPPI0_FS2W_LVB, val)
-#define bfin_read_EPPI0_FS2P_LAVF()     bfin_read32(EPPI0_FS2P_LAVF)
-#define bfin_write_EPPI0_FS2P_LAVF(val) bfin_write32(EPPI0_FS2P_LAVF, val)
-#define bfin_read_EPPI0_CLIP()          bfin_read32(EPPI0_CLIP)
-#define bfin_write_EPPI0_CLIP(val)      bfin_write32(EPPI0_CLIP, val)
-
-/* UART2 Registers */
-
-#define bfin_read_UART2_DLL()           bfin_read16(UART2_DLL)
-#define bfin_write_UART2_DLL(val)       bfin_write16(UART2_DLL, val)
-#define bfin_read_UART2_DLH()           bfin_read16(UART2_DLH)
-#define bfin_write_UART2_DLH(val)       bfin_write16(UART2_DLH, val)
-#define bfin_read_UART2_GCTL()          bfin_read16(UART2_GCTL)
-#define bfin_write_UART2_GCTL(val)      bfin_write16(UART2_GCTL, val)
-#define bfin_read_UART2_LCR()           bfin_read16(UART2_LCR)
-#define bfin_write_UART2_LCR(val)       bfin_write16(UART2_LCR, val)
-#define bfin_read_UART2_MCR()           bfin_read16(UART2_MCR)
-#define bfin_write_UART2_MCR(val)       bfin_write16(UART2_MCR, val)
-#define bfin_read_UART2_LSR()           bfin_read16(UART2_LSR)
-#define bfin_write_UART2_LSR(val)       bfin_write16(UART2_LSR, val)
-#define bfin_read_UART2_MSR()           bfin_read16(UART2_MSR)
-#define bfin_write_UART2_MSR(val)       bfin_write16(UART2_MSR, val)
-#define bfin_read_UART2_SCR()           bfin_read16(UART2_SCR)
-#define bfin_write_UART2_SCR(val)       bfin_write16(UART2_SCR, val)
-#define bfin_read_UART2_IER_SET()       bfin_read16(UART2_IER_SET)
-#define bfin_write_UART2_IER_SET(val)   bfin_write16(UART2_IER_SET, val)
-#define bfin_read_UART2_IER_CLEAR()     bfin_read16(UART2_IER_CLEAR)
-#define bfin_write_UART2_IER_CLEAR(val) bfin_write16(UART2_IER_CLEAR, val)
-#define bfin_read_UART2_RBR()           bfin_read16(UART2_RBR)
-#define bfin_write_UART2_RBR(val)       bfin_write16(UART2_RBR, val)
-
-/* Two Wire Interface Registers (TWI1) */
-
-/* SPI2  Registers */
-
-#define bfin_read_SPI2_CTL()            bfin_read16(SPI2_CTL)
-#define bfin_write_SPI2_CTL(val)        bfin_write16(SPI2_CTL, val)
-#define bfin_read_SPI2_FLG()            bfin_read16(SPI2_FLG)
-#define bfin_write_SPI2_FLG(val)        bfin_write16(SPI2_FLG, val)
-#define bfin_read_SPI2_STAT()           bfin_read16(SPI2_STAT)
-#define bfin_write_SPI2_STAT(val)       bfin_write16(SPI2_STAT, val)
-#define bfin_read_SPI2_TDBR()           bfin_read16(SPI2_TDBR)
-#define bfin_write_SPI2_TDBR(val)       bfin_write16(SPI2_TDBR, val)
-#define bfin_read_SPI2_RDBR()           bfin_read16(SPI2_RDBR)
-#define bfin_write_SPI2_RDBR(val)       bfin_write16(SPI2_RDBR, val)
-#define bfin_read_SPI2_BAUD()           bfin_read16(SPI2_BAUD)
-#define bfin_write_SPI2_BAUD(val)       bfin_write16(SPI2_BAUD, val)
-#define bfin_read_SPI2_SHADOW()         bfin_read16(SPI2_SHADOW)
-#define bfin_write_SPI2_SHADOW(val)     bfin_write16(SPI2_SHADOW, val)
+/* The BF548 is like the BF547, but has additional CANs */
+#include "cdefBF547.h"
 
 /* CAN Controller 1 Config 1 Registers */
 
@@ -923,631 +766,4 @@
 #define bfin_read_CAN1_MB31_ID1()               bfin_read16(CAN1_MB31_ID1)
 #define bfin_write_CAN1_MB31_ID1(val)           bfin_write16(CAN1_MB31_ID1, val)
 
-/* ATAPI Registers */
-
-#define bfin_read_ATAPI_CONTROL()               bfin_read16(ATAPI_CONTROL)
-#define bfin_write_ATAPI_CONTROL(val)           bfin_write16(ATAPI_CONTROL, val)
-#define bfin_read_ATAPI_STATUS()                bfin_read16(ATAPI_STATUS)
-#define bfin_write_ATAPI_STATUS(val)            bfin_write16(ATAPI_STATUS, val)
-#define bfin_read_ATAPI_DEV_ADDR()              bfin_read16(ATAPI_DEV_ADDR)
-#define bfin_write_ATAPI_DEV_ADDR(val)          bfin_write16(ATAPI_DEV_ADDR, val)
-#define bfin_read_ATAPI_DEV_TXBUF()             bfin_read16(ATAPI_DEV_TXBUF)
-#define bfin_write_ATAPI_DEV_TXBUF(val)         bfin_write16(ATAPI_DEV_TXBUF, val)
-#define bfin_read_ATAPI_DEV_RXBUF()             bfin_read16(ATAPI_DEV_RXBUF)
-#define bfin_write_ATAPI_DEV_RXBUF(val)         bfin_write16(ATAPI_DEV_RXBUF, val)
-#define bfin_read_ATAPI_INT_MASK()              bfin_read16(ATAPI_INT_MASK)
-#define bfin_write_ATAPI_INT_MASK(val)          bfin_write16(ATAPI_INT_MASK, val)
-#define bfin_read_ATAPI_INT_STATUS()            bfin_read16(ATAPI_INT_STATUS)
-#define bfin_write_ATAPI_INT_STATUS(val)        bfin_write16(ATAPI_INT_STATUS, val)
-#define bfin_read_ATAPI_XFER_LEN()              bfin_read16(ATAPI_XFER_LEN)
-#define bfin_write_ATAPI_XFER_LEN(val)          bfin_write16(ATAPI_XFER_LEN, val)
-#define bfin_read_ATAPI_LINE_STATUS()           bfin_read16(ATAPI_LINE_STATUS)
-#define bfin_write_ATAPI_LINE_STATUS(val)       bfin_write16(ATAPI_LINE_STATUS, val)
-#define bfin_read_ATAPI_SM_STATE()              bfin_read16(ATAPI_SM_STATE)
-#define bfin_write_ATAPI_SM_STATE(val)          bfin_write16(ATAPI_SM_STATE, val)
-#define bfin_read_ATAPI_TERMINATE()             bfin_read16(ATAPI_TERMINATE)
-#define bfin_write_ATAPI_TERMINATE(val)         bfin_write16(ATAPI_TERMINATE, val)
-#define bfin_read_ATAPI_PIO_TFRCNT()            bfin_read16(ATAPI_PIO_TFRCNT)
-#define bfin_write_ATAPI_PIO_TFRCNT(val)        bfin_write16(ATAPI_PIO_TFRCNT, val)
-#define bfin_read_ATAPI_DMA_TFRCNT()            bfin_read16(ATAPI_DMA_TFRCNT)
-#define bfin_write_ATAPI_DMA_TFRCNT(val)        bfin_write16(ATAPI_DMA_TFRCNT, val)
-#define bfin_read_ATAPI_UMAIN_TFRCNT()          bfin_read16(ATAPI_UMAIN_TFRCNT)
-#define bfin_write_ATAPI_UMAIN_TFRCNT(val)      bfin_write16(ATAPI_UMAIN_TFRCNT, val)
-#define bfin_read_ATAPI_UDMAOUT_TFRCNT()        bfin_read16(ATAPI_UDMAOUT_TFRCNT)
-#define bfin_write_ATAPI_UDMAOUT_TFRCNT(val)    bfin_write16(ATAPI_UDMAOUT_TFRCNT, val)
-#define bfin_read_ATAPI_REG_TIM_0()             bfin_read16(ATAPI_REG_TIM_0)
-#define bfin_write_ATAPI_REG_TIM_0(val)         bfin_write16(ATAPI_REG_TIM_0, val)
-#define bfin_read_ATAPI_PIO_TIM_0()             bfin_read16(ATAPI_PIO_TIM_0)
-#define bfin_write_ATAPI_PIO_TIM_0(val)         bfin_write16(ATAPI_PIO_TIM_0, val)
-#define bfin_read_ATAPI_PIO_TIM_1()             bfin_read16(ATAPI_PIO_TIM_1)
-#define bfin_write_ATAPI_PIO_TIM_1(val)         bfin_write16(ATAPI_PIO_TIM_1, val)
-#define bfin_read_ATAPI_MULTI_TIM_0()           bfin_read16(ATAPI_MULTI_TIM_0)
-#define bfin_write_ATAPI_MULTI_TIM_0(val)       bfin_write16(ATAPI_MULTI_TIM_0, val)
-#define bfin_read_ATAPI_MULTI_TIM_1()           bfin_read16(ATAPI_MULTI_TIM_1)
-#define bfin_write_ATAPI_MULTI_TIM_1(val)       bfin_write16(ATAPI_MULTI_TIM_1, val)
-#define bfin_read_ATAPI_MULTI_TIM_2()           bfin_read16(ATAPI_MULTI_TIM_2)
-#define bfin_write_ATAPI_MULTI_TIM_2(val)       bfin_write16(ATAPI_MULTI_TIM_2, val)
-#define bfin_read_ATAPI_ULTRA_TIM_0()           bfin_read16(ATAPI_ULTRA_TIM_0)
-#define bfin_write_ATAPI_ULTRA_TIM_0(val)       bfin_write16(ATAPI_ULTRA_TIM_0, val)
-#define bfin_read_ATAPI_ULTRA_TIM_1()           bfin_read16(ATAPI_ULTRA_TIM_1)
-#define bfin_write_ATAPI_ULTRA_TIM_1(val)       bfin_write16(ATAPI_ULTRA_TIM_1, val)
-#define bfin_read_ATAPI_ULTRA_TIM_2()           bfin_read16(ATAPI_ULTRA_TIM_2)
-#define bfin_write_ATAPI_ULTRA_TIM_2(val)       bfin_write16(ATAPI_ULTRA_TIM_2, val)
-#define bfin_read_ATAPI_ULTRA_TIM_3()           bfin_read16(ATAPI_ULTRA_TIM_3)
-#define bfin_write_ATAPI_ULTRA_TIM_3(val)       bfin_write16(ATAPI_ULTRA_TIM_3, val)
-
-/* SDH Registers */
-
-#define bfin_read_SDH_PWR_CTL()         bfin_read16(SDH_PWR_CTL)
-#define bfin_write_SDH_PWR_CTL(val)     bfin_write16(SDH_PWR_CTL, val)
-#define bfin_read_SDH_CLK_CTL()         bfin_read16(SDH_CLK_CTL)
-#define bfin_write_SDH_CLK_CTL(val)     bfin_write16(SDH_CLK_CTL, val)
-#define bfin_read_SDH_ARGUMENT()        bfin_read32(SDH_ARGUMENT)
-#define bfin_write_SDH_ARGUMENT(val)    bfin_write32(SDH_ARGUMENT, val)
-#define bfin_read_SDH_COMMAND()         bfin_read16(SDH_COMMAND)
-#define bfin_write_SDH_COMMAND(val)     bfin_write16(SDH_COMMAND, val)
-#define bfin_read_SDH_RESP_CMD()        bfin_read16(SDH_RESP_CMD)
-#define bfin_write_SDH_RESP_CMD(val)    bfin_write16(SDH_RESP_CMD, val)
-#define bfin_read_SDH_RESPONSE0()       bfin_read32(SDH_RESPONSE0)
-#define bfin_write_SDH_RESPONSE0(val)   bfin_write32(SDH_RESPONSE0, val)
-#define bfin_read_SDH_RESPONSE1()       bfin_read32(SDH_RESPONSE1)
-#define bfin_write_SDH_RESPONSE1(val)   bfin_write32(SDH_RESPONSE1, val)
-#define bfin_read_SDH_RESPONSE2()       bfin_read32(SDH_RESPONSE2)
-#define bfin_write_SDH_RESPONSE2(val)   bfin_write32(SDH_RESPONSE2, val)
-#define bfin_read_SDH_RESPONSE3()       bfin_read32(SDH_RESPONSE3)
-#define bfin_write_SDH_RESPONSE3(val)   bfin_write32(SDH_RESPONSE3, val)
-#define bfin_read_SDH_DATA_TIMER()      bfin_read32(SDH_DATA_TIMER)
-#define bfin_write_SDH_DATA_TIMER(val)  bfin_write32(SDH_DATA_TIMER, val)
-#define bfin_read_SDH_DATA_LGTH()       bfin_read16(SDH_DATA_LGTH)
-#define bfin_write_SDH_DATA_LGTH(val)   bfin_write16(SDH_DATA_LGTH, val)
-#define bfin_read_SDH_DATA_CTL()        bfin_read16(SDH_DATA_CTL)
-#define bfin_write_SDH_DATA_CTL(val)    bfin_write16(SDH_DATA_CTL, val)
-#define bfin_read_SDH_DATA_CNT()        bfin_read16(SDH_DATA_CNT)
-#define bfin_write_SDH_DATA_CNT(val)    bfin_write16(SDH_DATA_CNT, val)
-#define bfin_read_SDH_STATUS()          bfin_read32(SDH_STATUS)
-#define bfin_write_SDH_STATUS(val)      bfin_write32(SDH_STATUS, val)
-#define bfin_read_SDH_STATUS_CLR()      bfin_read16(SDH_STATUS_CLR)
-#define bfin_write_SDH_STATUS_CLR(val)  bfin_write16(SDH_STATUS_CLR, val)
-#define bfin_read_SDH_MASK0()           bfin_read32(SDH_MASK0)
-#define bfin_write_SDH_MASK0(val)       bfin_write32(SDH_MASK0, val)
-#define bfin_read_SDH_MASK1()           bfin_read32(SDH_MASK1)
-#define bfin_write_SDH_MASK1(val)       bfin_write32(SDH_MASK1, val)
-#define bfin_read_SDH_FIFO_CNT()        bfin_read16(SDH_FIFO_CNT)
-#define bfin_write_SDH_FIFO_CNT(val)    bfin_write16(SDH_FIFO_CNT, val)
-#define bfin_read_SDH_FIFO()            bfin_read32(SDH_FIFO)
-#define bfin_write_SDH_FIFO(val)        bfin_write32(SDH_FIFO, val)
-#define bfin_read_SDH_E_STATUS()        bfin_read16(SDH_E_STATUS)
-#define bfin_write_SDH_E_STATUS(val)    bfin_write16(SDH_E_STATUS, val)
-#define bfin_read_SDH_E_MASK()          bfin_read16(SDH_E_MASK)
-#define bfin_write_SDH_E_MASK(val)      bfin_write16(SDH_E_MASK, val)
-#define bfin_read_SDH_CFG()             bfin_read16(SDH_CFG)
-#define bfin_write_SDH_CFG(val)         bfin_write16(SDH_CFG, val)
-#define bfin_read_SDH_RD_WAIT_EN()      bfin_read16(SDH_RD_WAIT_EN)
-#define bfin_write_SDH_RD_WAIT_EN(val)  bfin_write16(SDH_RD_WAIT_EN, val)
-#define bfin_read_SDH_PID0()            bfin_read16(SDH_PID0)
-#define bfin_write_SDH_PID0(val)        bfin_write16(SDH_PID0, val)
-#define bfin_read_SDH_PID1()            bfin_read16(SDH_PID1)
-#define bfin_write_SDH_PID1(val)        bfin_write16(SDH_PID1, val)
-#define bfin_read_SDH_PID2()            bfin_read16(SDH_PID2)
-#define bfin_write_SDH_PID2(val)        bfin_write16(SDH_PID2, val)
-#define bfin_read_SDH_PID3()            bfin_read16(SDH_PID3)
-#define bfin_write_SDH_PID3(val)        bfin_write16(SDH_PID3, val)
-#define bfin_read_SDH_PID4()            bfin_read16(SDH_PID4)
-#define bfin_write_SDH_PID4(val)        bfin_write16(SDH_PID4, val)
-#define bfin_read_SDH_PID5()            bfin_read16(SDH_PID5)
-#define bfin_write_SDH_PID5(val)        bfin_write16(SDH_PID5, val)
-#define bfin_read_SDH_PID6()            bfin_read16(SDH_PID6)
-#define bfin_write_SDH_PID6(val)        bfin_write16(SDH_PID6, val)
-#define bfin_read_SDH_PID7()            bfin_read16(SDH_PID7)
-#define bfin_write_SDH_PID7(val)        bfin_write16(SDH_PID7, val)
-
-/* HOST Port Registers */
-
-#define bfin_read_HOST_CONTROL()        bfin_read16(HOST_CONTROL)
-#define bfin_write_HOST_CONTROL(val)    bfin_write16(HOST_CONTROL, val)
-#define bfin_read_HOST_STATUS()         bfin_read16(HOST_STATUS)
-#define bfin_write_HOST_STATUS(val)     bfin_write16(HOST_STATUS, val)
-#define bfin_read_HOST_TIMEOUT()        bfin_read16(HOST_TIMEOUT)
-#define bfin_write_HOST_TIMEOUT(val)    bfin_write16(HOST_TIMEOUT, val)
-
-/* USB Control Registers */
-
-#define bfin_read_USB_FADDR()           bfin_read16(USB_FADDR)
-#define bfin_write_USB_FADDR(val)       bfin_write16(USB_FADDR, val)
-#define bfin_read_USB_POWER()           bfin_read16(USB_POWER)
-#define bfin_write_USB_POWER(val)       bfin_write16(USB_POWER, val)
-#define bfin_read_USB_INTRTX()          bfin_read16(USB_INTRTX)
-#define bfin_write_USB_INTRTX(val)      bfin_write16(USB_INTRTX, val)
-#define bfin_read_USB_INTRRX()          bfin_read16(USB_INTRRX)
-#define bfin_write_USB_INTRRX(val)      bfin_write16(USB_INTRRX, val)
-#define bfin_read_USB_INTRTXE()         bfin_read16(USB_INTRTXE)
-#define bfin_write_USB_INTRTXE(val)     bfin_write16(USB_INTRTXE, val)
-#define bfin_read_USB_INTRRXE()         bfin_read16(USB_INTRRXE)
-#define bfin_write_USB_INTRRXE(val)     bfin_write16(USB_INTRRXE, val)
-#define bfin_read_USB_INTRUSB()         bfin_read16(USB_INTRUSB)
-#define bfin_write_USB_INTRUSB(val)     bfin_write16(USB_INTRUSB, val)
-#define bfin_read_USB_INTRUSBE()        bfin_read16(USB_INTRUSBE)
-#define bfin_write_USB_INTRUSBE(val)    bfin_write16(USB_INTRUSBE, val)
-#define bfin_read_USB_FRAME()           bfin_read16(USB_FRAME)
-#define bfin_write_USB_FRAME(val)       bfin_write16(USB_FRAME, val)
-#define bfin_read_USB_INDEX()           bfin_read16(USB_INDEX)
-#define bfin_write_USB_INDEX(val)       bfin_write16(USB_INDEX, val)
-#define bfin_read_USB_TESTMODE()        bfin_read16(USB_TESTMODE)
-#define bfin_write_USB_TESTMODE(val)    bfin_write16(USB_TESTMODE, val)
-#define bfin_read_USB_GLOBINTR()        bfin_read16(USB_GLOBINTR)
-#define bfin_write_USB_GLOBINTR(val)    bfin_write16(USB_GLOBINTR, val)
-#define bfin_read_USB_GLOBAL_CTL()      bfin_read16(USB_GLOBAL_CTL)
-#define bfin_write_USB_GLOBAL_CTL(val)          bfin_write16(USB_GLOBAL_CTL, val)
-
-/* USB Packet Control Registers */
-
-#define bfin_read_USB_TX_MAX_PACKET()           bfin_read16(USB_TX_MAX_PACKET)
-#define bfin_write_USB_TX_MAX_PACKET(val)       bfin_write16(USB_TX_MAX_PACKET, val)
-#define bfin_read_USB_CSR0()            bfin_read16(USB_CSR0)
-#define bfin_write_USB_CSR0(val)        bfin_write16(USB_CSR0, val)
-#define bfin_read_USB_TXCSR()           bfin_read16(USB_TXCSR)
-#define bfin_write_USB_TXCSR(val)       bfin_write16(USB_TXCSR, val)
-#define bfin_read_USB_RX_MAX_PACKET()           bfin_read16(USB_RX_MAX_PACKET)
-#define bfin_write_USB_RX_MAX_PACKET(val)       bfin_write16(USB_RX_MAX_PACKET, val)
-#define bfin_read_USB_RXCSR()           bfin_read16(USB_RXCSR)
-#define bfin_write_USB_RXCSR(val)       bfin_write16(USB_RXCSR, val)
-#define bfin_read_USB_COUNT0()          bfin_read16(USB_COUNT0)
-#define bfin_write_USB_COUNT0(val)      bfin_write16(USB_COUNT0, val)
-#define bfin_read_USB_RXCOUNT()         bfin_read16(USB_RXCOUNT)
-#define bfin_write_USB_RXCOUNT(val)     bfin_write16(USB_RXCOUNT, val)
-#define bfin_read_USB_TXTYPE()          bfin_read16(USB_TXTYPE)
-#define bfin_write_USB_TXTYPE(val)      bfin_write16(USB_TXTYPE, val)
-#define bfin_read_USB_NAKLIMIT0()       bfin_read16(USB_NAKLIMIT0)
-#define bfin_write_USB_NAKLIMIT0(val)   bfin_write16(USB_NAKLIMIT0, val)
-#define bfin_read_USB_TXINTERVAL()      bfin_read16(USB_TXINTERVAL)
-#define bfin_write_USB_TXINTERVAL(val)  bfin_write16(USB_TXINTERVAL, val)
-#define bfin_read_USB_RXTYPE()          bfin_read16(USB_RXTYPE)
-#define bfin_write_USB_RXTYPE(val)      bfin_write16(USB_RXTYPE, val)
-#define bfin_read_USB_RXINTERVAL()      bfin_read16(USB_RXINTERVAL)
-#define bfin_write_USB_RXINTERVAL(val)  bfin_write16(USB_RXINTERVAL, val)
-#define bfin_read_USB_TXCOUNT()         bfin_read16(USB_TXCOUNT)
-#define bfin_write_USB_TXCOUNT(val)     bfin_write16(USB_TXCOUNT, val)
-
-/* USB Endbfin_read_()oint FIFO Registers */
-
-#define bfin_read_USB_EP0_FIFO()        bfin_read16(USB_EP0_FIFO)
-#define bfin_write_USB_EP0_FIFO(val)    bfin_write16(USB_EP0_FIFO, val)
-#define bfin_read_USB_EP1_FIFO()        bfin_read16(USB_EP1_FIFO)
-#define bfin_write_USB_EP1_FIFO(val)    bfin_write16(USB_EP1_FIFO, val)
-#define bfin_read_USB_EP2_FIFO()        bfin_read16(USB_EP2_FIFO)
-#define bfin_write_USB_EP2_FIFO(val)    bfin_write16(USB_EP2_FIFO, val)
-#define bfin_read_USB_EP3_FIFO()        bfin_read16(USB_EP3_FIFO)
-#define bfin_write_USB_EP3_FIFO(val)    bfin_write16(USB_EP3_FIFO, val)
-#define bfin_read_USB_EP4_FIFO()        bfin_read16(USB_EP4_FIFO)
-#define bfin_write_USB_EP4_FIFO(val)    bfin_write16(USB_EP4_FIFO, val)
-#define bfin_read_USB_EP5_FIFO()        bfin_read16(USB_EP5_FIFO)
-#define bfin_write_USB_EP5_FIFO(val)    bfin_write16(USB_EP5_FIFO, val)
-#define bfin_read_USB_EP6_FIFO()        bfin_read16(USB_EP6_FIFO)
-#define bfin_write_USB_EP6_FIFO(val)    bfin_write16(USB_EP6_FIFO, val)
-#define bfin_read_USB_EP7_FIFO()        bfin_read16(USB_EP7_FIFO)
-#define bfin_write_USB_EP7_FIFO(val)    bfin_write16(USB_EP7_FIFO, val)
-
-/* USB OTG Control Registers */
-
-#define bfin_read_USB_OTG_DEV_CTL()             bfin_read16(USB_OTG_DEV_CTL)
-#define bfin_write_USB_OTG_DEV_CTL(val)         bfin_write16(USB_OTG_DEV_CTL, val)
-#define bfin_read_USB_OTG_VBUS_IRQ()            bfin_read16(USB_OTG_VBUS_IRQ)
-#define bfin_write_USB_OTG_VBUS_IRQ(val)        bfin_write16(USB_OTG_VBUS_IRQ, val)
-#define bfin_read_USB_OTG_VBUS_MASK()           bfin_read16(USB_OTG_VBUS_MASK)
-#define bfin_write_USB_OTG_VBUS_MASK(val)       bfin_write16(USB_OTG_VBUS_MASK, val)
-
-/* USB Phy Control Registers */
-
-#define bfin_read_USB_LINKINFO()        bfin_read16(USB_LINKINFO)
-#define bfin_write_USB_LINKINFO(val)    bfin_write16(USB_LINKINFO, val)
-#define bfin_read_USB_VPLEN()           bfin_read16(USB_VPLEN)
-#define bfin_write_USB_VPLEN(val)       bfin_write16(USB_VPLEN, val)
-#define bfin_read_USB_HS_EOF1()         bfin_read16(USB_HS_EOF1)
-#define bfin_write_USB_HS_EOF1(val)     bfin_write16(USB_HS_EOF1, val)
-#define bfin_read_USB_FS_EOF1()         bfin_read16(USB_FS_EOF1)
-#define bfin_write_USB_FS_EOF1(val)     bfin_write16(USB_FS_EOF1, val)
-#define bfin_read_USB_LS_EOF1()         bfin_read16(USB_LS_EOF1)
-#define bfin_write_USB_LS_EOF1(val)     bfin_write16(USB_LS_EOF1, val)
-
-/* (APHY_CNTRL is for ADI usage only) */
-
-#define bfin_read_USB_APHY_CNTRL()              bfin_read16(USB_APHY_CNTRL)
-#define bfin_write_USB_APHY_CNTRL(val)          bfin_write16(USB_APHY_CNTRL, val)
-
-/* (APHY_CALIB is for ADI usage only) */
-
-#define bfin_read_USB_APHY_CALIB()              bfin_read16(USB_APHY_CALIB)
-#define bfin_write_USB_APHY_CALIB(val)          bfin_write16(USB_APHY_CALIB, val)
-#define bfin_read_USB_APHY_CNTRL2()             bfin_read16(USB_APHY_CNTRL2)
-#define bfin_write_USB_APHY_CNTRL2(val)         bfin_write16(USB_APHY_CNTRL2, val)
-
-/* (PHY_TEST is for ADI usage only) */
-
-#define bfin_read_USB_PHY_TEST()                bfin_read16(USB_PHY_TEST)
-#define bfin_write_USB_PHY_TEST(val)            bfin_write16(USB_PHY_TEST, val)
-#define bfin_read_USB_PLLOSC_CTRL()             bfin_read16(USB_PLLOSC_CTRL)
-#define bfin_write_USB_PLLOSC_CTRL(val)         bfin_write16(USB_PLLOSC_CTRL, val)
-#define bfin_read_USB_SRP_CLKDIV()              bfin_read16(USB_SRP_CLKDIV)
-#define bfin_write_USB_SRP_CLKDIV(val)          bfin_write16(USB_SRP_CLKDIV, val)
-
-/* USB Endbfin_read_()oint 0 Control Registers */
-
-#define bfin_read_USB_EP_NI0_TXMAXP()           bfin_read16(USB_EP_NI0_TXMAXP)
-#define bfin_write_USB_EP_NI0_TXMAXP(val)       bfin_write16(USB_EP_NI0_TXMAXP, val)
-#define bfin_read_USB_EP_NI0_TXCSR()            bfin_read16(USB_EP_NI0_TXCSR)
-#define bfin_write_USB_EP_NI0_TXCSR(val)        bfin_write16(USB_EP_NI0_TXCSR, val)
-#define bfin_read_USB_EP_NI0_RXMAXP()           bfin_read16(USB_EP_NI0_RXMAXP)
-#define bfin_write_USB_EP_NI0_RXMAXP(val)       bfin_write16(USB_EP_NI0_RXMAXP, val)
-#define bfin_read_USB_EP_NI0_RXCSR()            bfin_read16(USB_EP_NI0_RXCSR)
-#define bfin_write_USB_EP_NI0_RXCSR(val)        bfin_write16(USB_EP_NI0_RXCSR, val)
-#define bfin_read_USB_EP_NI0_RXCOUNT()          bfin_read16(USB_EP_NI0_RXCOUNT)
-#define bfin_write_USB_EP_NI0_RXCOUNT(val)      bfin_write16(USB_EP_NI0_RXCOUNT, val)
-#define bfin_read_USB_EP_NI0_TXTYPE()           bfin_read16(USB_EP_NI0_TXTYPE)
-#define bfin_write_USB_EP_NI0_TXTYPE(val)       bfin_write16(USB_EP_NI0_TXTYPE, val)
-#define bfin_read_USB_EP_NI0_TXINTERVAL()       bfin_read16(USB_EP_NI0_TXINTERVAL)
-#define bfin_write_USB_EP_NI0_TXINTERVAL(val)   bfin_write16(USB_EP_NI0_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI0_RXTYPE()           bfin_read16(USB_EP_NI0_RXTYPE)
-#define bfin_write_USB_EP_NI0_RXTYPE(val)       bfin_write16(USB_EP_NI0_RXTYPE, val)
-#define bfin_read_USB_EP_NI0_RXINTERVAL()       bfin_read16(USB_EP_NI0_RXINTERVAL)
-#define bfin_write_USB_EP_NI0_RXINTERVAL(val)   bfin_write16(USB_EP_NI0_RXINTERVAL, val)
-
-/* USB Endbfin_read_()oint 1 Control Registers */
-
-#define bfin_read_USB_EP_NI0_TXCOUNT()          bfin_read16(USB_EP_NI0_TXCOUNT)
-#define bfin_write_USB_EP_NI0_TXCOUNT(val)      bfin_write16(USB_EP_NI0_TXCOUNT, val)
-#define bfin_read_USB_EP_NI1_TXMAXP()           bfin_read16(USB_EP_NI1_TXMAXP)
-#define bfin_write_USB_EP_NI1_TXMAXP(val)       bfin_write16(USB_EP_NI1_TXMAXP, val)
-#define bfin_read_USB_EP_NI1_TXCSR()            bfin_read16(USB_EP_NI1_TXCSR)
-#define bfin_write_USB_EP_NI1_TXCSR(val)        bfin_write16(USB_EP_NI1_TXCSR, val)
-#define bfin_read_USB_EP_NI1_RXMAXP()           bfin_read16(USB_EP_NI1_RXMAXP)
-#define bfin_write_USB_EP_NI1_RXMAXP(val)       bfin_write16(USB_EP_NI1_RXMAXP, val)
-#define bfin_read_USB_EP_NI1_RXCSR()            bfin_read16(USB_EP_NI1_RXCSR)
-#define bfin_write_USB_EP_NI1_RXCSR(val)        bfin_write16(USB_EP_NI1_RXCSR, val)
-#define bfin_read_USB_EP_NI1_RXCOUNT()          bfin_read16(USB_EP_NI1_RXCOUNT)
-#define bfin_write_USB_EP_NI1_RXCOUNT(val)      bfin_write16(USB_EP_NI1_RXCOUNT, val)
-#define bfin_read_USB_EP_NI1_TXTYPE()           bfin_read16(USB_EP_NI1_TXTYPE)
-#define bfin_write_USB_EP_NI1_TXTYPE(val)       bfin_write16(USB_EP_NI1_TXTYPE, val)
-#define bfin_read_USB_EP_NI1_TXINTERVAL()       bfin_read16(USB_EP_NI1_TXINTERVAL)
-#define bfin_write_USB_EP_NI1_TXINTERVAL(val)   bfin_write16(USB_EP_NI1_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI1_RXTYPE()           bfin_read16(USB_EP_NI1_RXTYPE)
-#define bfin_write_USB_EP_NI1_RXTYPE(val)       bfin_write16(USB_EP_NI1_RXTYPE, val)
-#define bfin_read_USB_EP_NI1_RXINTERVAL()       bfin_read16(USB_EP_NI1_RXINTERVAL)
-#define bfin_write_USB_EP_NI1_RXINTERVAL(val)   bfin_write16(USB_EP_NI1_RXINTERVAL, val)
-
-/* USB Endbfin_read_()oint 2 Control Registers */
-
-#define bfin_read_USB_EP_NI1_TXCOUNT()          bfin_read16(USB_EP_NI1_TXCOUNT)
-#define bfin_write_USB_EP_NI1_TXCOUNT(val)      bfin_write16(USB_EP_NI1_TXCOUNT, val)
-#define bfin_read_USB_EP_NI2_TXMAXP()           bfin_read16(USB_EP_NI2_TXMAXP)
-#define bfin_write_USB_EP_NI2_TXMAXP(val)       bfin_write16(USB_EP_NI2_TXMAXP, val)
-#define bfin_read_USB_EP_NI2_TXCSR()            bfin_read16(USB_EP_NI2_TXCSR)
-#define bfin_write_USB_EP_NI2_TXCSR(val)        bfin_write16(USB_EP_NI2_TXCSR, val)
-#define bfin_read_USB_EP_NI2_RXMAXP()           bfin_read16(USB_EP_NI2_RXMAXP)
-#define bfin_write_USB_EP_NI2_RXMAXP(val)       bfin_write16(USB_EP_NI2_RXMAXP, val)
-#define bfin_read_USB_EP_NI2_RXCSR()            bfin_read16(USB_EP_NI2_RXCSR)
-#define bfin_write_USB_EP_NI2_RXCSR(val)        bfin_write16(USB_EP_NI2_RXCSR, val)
-#define bfin_read_USB_EP_NI2_RXCOUNT()          bfin_read16(USB_EP_NI2_RXCOUNT)
-#define bfin_write_USB_EP_NI2_RXCOUNT(val)      bfin_write16(USB_EP_NI2_RXCOUNT, val)
-#define bfin_read_USB_EP_NI2_TXTYPE()           bfin_read16(USB_EP_NI2_TXTYPE)
-#define bfin_write_USB_EP_NI2_TXTYPE(val)       bfin_write16(USB_EP_NI2_TXTYPE, val)
-#define bfin_read_USB_EP_NI2_TXINTERVAL()       bfin_read16(USB_EP_NI2_TXINTERVAL)
-#define bfin_write_USB_EP_NI2_TXINTERVAL(val)   bfin_write16(USB_EP_NI2_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI2_RXTYPE()           bfin_read16(USB_EP_NI2_RXTYPE)
-#define bfin_write_USB_EP_NI2_RXTYPE(val)       bfin_write16(USB_EP_NI2_RXTYPE, val)
-#define bfin_read_USB_EP_NI2_RXINTERVAL()       bfin_read16(USB_EP_NI2_RXINTERVAL)
-#define bfin_write_USB_EP_NI2_RXINTERVAL(val)   bfin_write16(USB_EP_NI2_RXINTERVAL, val)
-
-/* USB Endbfin_read_()oint 3 Control Registers */
-
-#define bfin_read_USB_EP_NI2_TXCOUNT()          bfin_read16(USB_EP_NI2_TXCOUNT)
-#define bfin_write_USB_EP_NI2_TXCOUNT(val)      bfin_write16(USB_EP_NI2_TXCOUNT, val)
-#define bfin_read_USB_EP_NI3_TXMAXP()           bfin_read16(USB_EP_NI3_TXMAXP)
-#define bfin_write_USB_EP_NI3_TXMAXP(val)       bfin_write16(USB_EP_NI3_TXMAXP, val)
-#define bfin_read_USB_EP_NI3_TXCSR()            bfin_read16(USB_EP_NI3_TXCSR)
-#define bfin_write_USB_EP_NI3_TXCSR(val)        bfin_write16(USB_EP_NI3_TXCSR, val)
-#define bfin_read_USB_EP_NI3_RXMAXP()           bfin_read16(USB_EP_NI3_RXMAXP)
-#define bfin_write_USB_EP_NI3_RXMAXP(val)       bfin_write16(USB_EP_NI3_RXMAXP, val)
-#define bfin_read_USB_EP_NI3_RXCSR()            bfin_read16(USB_EP_NI3_RXCSR)
-#define bfin_write_USB_EP_NI3_RXCSR(val)        bfin_write16(USB_EP_NI3_RXCSR, val)
-#define bfin_read_USB_EP_NI3_RXCOUNT()          bfin_read16(USB_EP_NI3_RXCOUNT)
-#define bfin_write_USB_EP_NI3_RXCOUNT(val)      bfin_write16(USB_EP_NI3_RXCOUNT, val)
-#define bfin_read_USB_EP_NI3_TXTYPE()           bfin_read16(USB_EP_NI3_TXTYPE)
-#define bfin_write_USB_EP_NI3_TXTYPE(val)       bfin_write16(USB_EP_NI3_TXTYPE, val)
-#define bfin_read_USB_EP_NI3_TXINTERVAL()       bfin_read16(USB_EP_NI3_TXINTERVAL)
-#define bfin_write_USB_EP_NI3_TXINTERVAL(val)   bfin_write16(USB_EP_NI3_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI3_RXTYPE()           bfin_read16(USB_EP_NI3_RXTYPE)
-#define bfin_write_USB_EP_NI3_RXTYPE(val)       bfin_write16(USB_EP_NI3_RXTYPE, val)
-#define bfin_read_USB_EP_NI3_RXINTERVAL()       bfin_read16(USB_EP_NI3_RXINTERVAL)
-#define bfin_write_USB_EP_NI3_RXINTERVAL(val)   bfin_write16(USB_EP_NI3_RXINTERVAL, val)
-
-/* USB Endbfin_read_()oint 4 Control Registers */
-
-#define bfin_read_USB_EP_NI3_TXCOUNT()          bfin_read16(USB_EP_NI3_TXCOUNT)
-#define bfin_write_USB_EP_NI3_TXCOUNT(val)      bfin_write16(USB_EP_NI3_TXCOUNT, val)
-#define bfin_read_USB_EP_NI4_TXMAXP()           bfin_read16(USB_EP_NI4_TXMAXP)
-#define bfin_write_USB_EP_NI4_TXMAXP(val)       bfin_write16(USB_EP_NI4_TXMAXP, val)
-#define bfin_read_USB_EP_NI4_TXCSR()            bfin_read16(USB_EP_NI4_TXCSR)
-#define bfin_write_USB_EP_NI4_TXCSR(val)        bfin_write16(USB_EP_NI4_TXCSR, val)
-#define bfin_read_USB_EP_NI4_RXMAXP()           bfin_read16(USB_EP_NI4_RXMAXP)
-#define bfin_write_USB_EP_NI4_RXMAXP(val)       bfin_write16(USB_EP_NI4_RXMAXP, val)
-#define bfin_read_USB_EP_NI4_RXCSR()            bfin_read16(USB_EP_NI4_RXCSR)
-#define bfin_write_USB_EP_NI4_RXCSR(val)        bfin_write16(USB_EP_NI4_RXCSR, val)
-#define bfin_read_USB_EP_NI4_RXCOUNT()          bfin_read16(USB_EP_NI4_RXCOUNT)
-#define bfin_write_USB_EP_NI4_RXCOUNT(val)      bfin_write16(USB_EP_NI4_RXCOUNT, val)
-#define bfin_read_USB_EP_NI4_TXTYPE()           bfin_read16(USB_EP_NI4_TXTYPE)
-#define bfin_write_USB_EP_NI4_TXTYPE(val)       bfin_write16(USB_EP_NI4_TXTYPE, val)
-#define bfin_read_USB_EP_NI4_TXINTERVAL()       bfin_read16(USB_EP_NI4_TXINTERVAL)
-#define bfin_write_USB_EP_NI4_TXINTERVAL(val)   bfin_write16(USB_EP_NI4_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI4_RXTYPE()           bfin_read16(USB_EP_NI4_RXTYPE)
-#define bfin_write_USB_EP_NI4_RXTYPE(val)       bfin_write16(USB_EP_NI4_RXTYPE, val)
-#define bfin_read_USB_EP_NI4_RXINTERVAL()       bfin_read16(USB_EP_NI4_RXINTERVAL)
-#define bfin_write_USB_EP_NI4_RXINTERVAL(val)   bfin_write16(USB_EP_NI4_RXINTERVAL, val)
-
-/* USB Endbfin_read_()oint 5 Control Registers */
-
-#define bfin_read_USB_EP_NI4_TXCOUNT()          bfin_read16(USB_EP_NI4_TXCOUNT)
-#define bfin_write_USB_EP_NI4_TXCOUNT(val)      bfin_write16(USB_EP_NI4_TXCOUNT, val)
-#define bfin_read_USB_EP_NI5_TXMAXP()           bfin_read16(USB_EP_NI5_TXMAXP)
-#define bfin_write_USB_EP_NI5_TXMAXP(val)       bfin_write16(USB_EP_NI5_TXMAXP, val)
-#define bfin_read_USB_EP_NI5_TXCSR()            bfin_read16(USB_EP_NI5_TXCSR)
-#define bfin_write_USB_EP_NI5_TXCSR(val)        bfin_write16(USB_EP_NI5_TXCSR, val)
-#define bfin_read_USB_EP_NI5_RXMAXP()           bfin_read16(USB_EP_NI5_RXMAXP)
-#define bfin_write_USB_EP_NI5_RXMAXP(val)       bfin_write16(USB_EP_NI5_RXMAXP, val)
-#define bfin_read_USB_EP_NI5_RXCSR()            bfin_read16(USB_EP_NI5_RXCSR)
-#define bfin_write_USB_EP_NI5_RXCSR(val)        bfin_write16(USB_EP_NI5_RXCSR, val)
-#define bfin_read_USB_EP_NI5_RXCOUNT()          bfin_read16(USB_EP_NI5_RXCOUNT)
-#define bfin_write_USB_EP_NI5_RXCOUNT(val)      bfin_write16(USB_EP_NI5_RXCOUNT, val)
-#define bfin_read_USB_EP_NI5_TXTYPE()           bfin_read16(USB_EP_NI5_TXTYPE)
-#define bfin_write_USB_EP_NI5_TXTYPE(val)       bfin_write16(USB_EP_NI5_TXTYPE, val)
-#define bfin_read_USB_EP_NI5_TXINTERVAL()       bfin_read16(USB_EP_NI5_TXINTERVAL)
-#define bfin_write_USB_EP_NI5_TXINTERVAL(val)   bfin_write16(USB_EP_NI5_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI5_RXTYPE()           bfin_read16(USB_EP_NI5_RXTYPE)
-#define bfin_write_USB_EP_NI5_RXTYPE(val)       bfin_write16(USB_EP_NI5_RXTYPE, val)
-#define bfin_read_USB_EP_NI5_RXINTERVAL()       bfin_read16(USB_EP_NI5_RXINTERVAL)
-#define bfin_write_USB_EP_NI5_RXINTERVAL(val)   bfin_write16(USB_EP_NI5_RXINTERVAL, val)
-
-/* USB Endbfin_read_()oint 6 Control Registers */
-
-#define bfin_read_USB_EP_NI5_TXCOUNT()          bfin_read16(USB_EP_NI5_TXCOUNT)
-#define bfin_write_USB_EP_NI5_TXCOUNT(val)      bfin_write16(USB_EP_NI5_TXCOUNT, val)
-#define bfin_read_USB_EP_NI6_TXMAXP()           bfin_read16(USB_EP_NI6_TXMAXP)
-#define bfin_write_USB_EP_NI6_TXMAXP(val)       bfin_write16(USB_EP_NI6_TXMAXP, val)
-#define bfin_read_USB_EP_NI6_TXCSR()            bfin_read16(USB_EP_NI6_TXCSR)
-#define bfin_write_USB_EP_NI6_TXCSR(val)        bfin_write16(USB_EP_NI6_TXCSR, val)
-#define bfin_read_USB_EP_NI6_RXMAXP()           bfin_read16(USB_EP_NI6_RXMAXP)
-#define bfin_write_USB_EP_NI6_RXMAXP(val)       bfin_write16(USB_EP_NI6_RXMAXP, val)
-#define bfin_read_USB_EP_NI6_RXCSR()            bfin_read16(USB_EP_NI6_RXCSR)
-#define bfin_write_USB_EP_NI6_RXCSR(val)        bfin_write16(USB_EP_NI6_RXCSR, val)
-#define bfin_read_USB_EP_NI6_RXCOUNT()          bfin_read16(USB_EP_NI6_RXCOUNT)
-#define bfin_write_USB_EP_NI6_RXCOUNT(val)      bfin_write16(USB_EP_NI6_RXCOUNT, val)
-#define bfin_read_USB_EP_NI6_TXTYPE()           bfin_read16(USB_EP_NI6_TXTYPE)
-#define bfin_write_USB_EP_NI6_TXTYPE(val)       bfin_write16(USB_EP_NI6_TXTYPE, val)
-#define bfin_read_USB_EP_NI6_TXINTERVAL()       bfin_read16(USB_EP_NI6_TXINTERVAL)
-#define bfin_write_USB_EP_NI6_TXINTERVAL(val)   bfin_write16(USB_EP_NI6_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI6_RXTYPE()           bfin_read16(USB_EP_NI6_RXTYPE)
-#define bfin_write_USB_EP_NI6_RXTYPE(val)       bfin_write16(USB_EP_NI6_RXTYPE, val)
-#define bfin_read_USB_EP_NI6_RXINTERVAL()       bfin_read16(USB_EP_NI6_RXINTERVAL)
-#define bfin_write_USB_EP_NI6_RXINTERVAL(val)   bfin_write16(USB_EP_NI6_RXINTERVAL, val)
-
-/* USB Endbfin_read_()oint 7 Control Registers */
-
-#define bfin_read_USB_EP_NI6_TXCOUNT()          bfin_read16(USB_EP_NI6_TXCOUNT)
-#define bfin_write_USB_EP_NI6_TXCOUNT(val)      bfin_write16(USB_EP_NI6_TXCOUNT, val)
-#define bfin_read_USB_EP_NI7_TXMAXP()           bfin_read16(USB_EP_NI7_TXMAXP)
-#define bfin_write_USB_EP_NI7_TXMAXP(val)       bfin_write16(USB_EP_NI7_TXMAXP, val)
-#define bfin_read_USB_EP_NI7_TXCSR()            bfin_read16(USB_EP_NI7_TXCSR)
-#define bfin_write_USB_EP_NI7_TXCSR(val)        bfin_write16(USB_EP_NI7_TXCSR, val)
-#define bfin_read_USB_EP_NI7_RXMAXP()           bfin_read16(USB_EP_NI7_RXMAXP)
-#define bfin_write_USB_EP_NI7_RXMAXP(val)       bfin_write16(USB_EP_NI7_RXMAXP, val)
-#define bfin_read_USB_EP_NI7_RXCSR()            bfin_read16(USB_EP_NI7_RXCSR)
-#define bfin_write_USB_EP_NI7_RXCSR(val)        bfin_write16(USB_EP_NI7_RXCSR, val)
-#define bfin_read_USB_EP_NI7_RXCOUNT()          bfin_read16(USB_EP_NI7_RXCOUNT)
-#define bfin_write_USB_EP_NI7_RXCOUNT(val)      bfin_write16(USB_EP_NI7_RXCOUNT, val)
-#define bfin_read_USB_EP_NI7_TXTYPE()           bfin_read16(USB_EP_NI7_TXTYPE)
-#define bfin_write_USB_EP_NI7_TXTYPE(val)       bfin_write16(USB_EP_NI7_TXTYPE, val)
-#define bfin_read_USB_EP_NI7_TXINTERVAL()       bfin_read16(USB_EP_NI7_TXINTERVAL)
-#define bfin_write_USB_EP_NI7_TXINTERVAL(val)   bfin_write16(USB_EP_NI7_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI7_RXTYPE()           bfin_read16(USB_EP_NI7_RXTYPE)
-#define bfin_write_USB_EP_NI7_RXTYPE(val)       bfin_write16(USB_EP_NI7_RXTYPE, val)
-#define bfin_read_USB_EP_NI7_RXINTERVAL()       bfin_read16(USB_EP_NI7_RXINTERVAL)
-#define bfin_write_USB_EP_NI7_RXINTERVAL(val)   bfin_write16(USB_EP_NI7_RXINTERVAL, val)
-#define bfin_read_USB_EP_NI7_TXCOUNT()          bfin_read16(USB_EP_NI7_TXCOUNT)
-#define bfin_write_USB_EP_NI7_TXCOUNT(val)      bfin_write16(USB_EP_NI7_TXCOUNT, val)
-#define bfin_read_USB_DMA_INTERRUPT()           bfin_read16(USB_DMA_INTERRUPT)
-#define bfin_write_USB_DMA_INTERRUPT(val)       bfin_write16(USB_DMA_INTERRUPT, val)
-
-/* USB Channel 0 Config Registers */
-
-#define bfin_read_USB_DMA0CONTROL()             bfin_read16(USB_DMA0CONTROL)
-#define bfin_write_USB_DMA0CONTROL(val)         bfin_write16(USB_DMA0CONTROL, val)
-#define bfin_read_USB_DMA0ADDRLOW()             bfin_read16(USB_DMA0ADDRLOW)
-#define bfin_write_USB_DMA0ADDRLOW(val)         bfin_write16(USB_DMA0ADDRLOW, val)
-#define bfin_read_USB_DMA0ADDRHIGH()            bfin_read16(USB_DMA0ADDRHIGH)
-#define bfin_write_USB_DMA0ADDRHIGH(val)        bfin_write16(USB_DMA0ADDRHIGH, val)
-#define bfin_read_USB_DMA0COUNTLOW()            bfin_read16(USB_DMA0COUNTLOW)
-#define bfin_write_USB_DMA0COUNTLOW(val)        bfin_write16(USB_DMA0COUNTLOW, val)
-#define bfin_read_USB_DMA0COUNTHIGH()           bfin_read16(USB_DMA0COUNTHIGH)
-#define bfin_write_USB_DMA0COUNTHIGH(val)       bfin_write16(USB_DMA0COUNTHIGH, val)
-
-/* USB Channel 1 Config Registers */
-
-#define bfin_read_USB_DMA1CONTROL()             bfin_read16(USB_DMA1CONTROL)
-#define bfin_write_USB_DMA1CONTROL(val)         bfin_write16(USB_DMA1CONTROL, val)
-#define bfin_read_USB_DMA1ADDRLOW()             bfin_read16(USB_DMA1ADDRLOW)
-#define bfin_write_USB_DMA1ADDRLOW(val)         bfin_write16(USB_DMA1ADDRLOW, val)
-#define bfin_read_USB_DMA1ADDRHIGH()            bfin_read16(USB_DMA1ADDRHIGH)
-#define bfin_write_USB_DMA1ADDRHIGH(val)        bfin_write16(USB_DMA1ADDRHIGH, val)
-#define bfin_read_USB_DMA1COUNTLOW()            bfin_read16(USB_DMA1COUNTLOW)
-#define bfin_write_USB_DMA1COUNTLOW(val)        bfin_write16(USB_DMA1COUNTLOW, val)
-#define bfin_read_USB_DMA1COUNTHIGH()           bfin_read16(USB_DMA1COUNTHIGH)
-#define bfin_write_USB_DMA1COUNTHIGH(val)       bfin_write16(USB_DMA1COUNTHIGH, val)
-
-/* USB Channel 2 Config Registers */
-
-#define bfin_read_USB_DMA2CONTROL()             bfin_read16(USB_DMA2CONTROL)
-#define bfin_write_USB_DMA2CONTROL(val)         bfin_write16(USB_DMA2CONTROL, val)
-#define bfin_read_USB_DMA2ADDRLOW()             bfin_read16(USB_DMA2ADDRLOW)
-#define bfin_write_USB_DMA2ADDRLOW(val)         bfin_write16(USB_DMA2ADDRLOW, val)
-#define bfin_read_USB_DMA2ADDRHIGH()            bfin_read16(USB_DMA2ADDRHIGH)
-#define bfin_write_USB_DMA2ADDRHIGH(val)        bfin_write16(USB_DMA2ADDRHIGH, val)
-#define bfin_read_USB_DMA2COUNTLOW()            bfin_read16(USB_DMA2COUNTLOW)
-#define bfin_write_USB_DMA2COUNTLOW(val)        bfin_write16(USB_DMA2COUNTLOW, val)
-#define bfin_read_USB_DMA2COUNTHIGH()           bfin_read16(USB_DMA2COUNTHIGH)
-#define bfin_write_USB_DMA2COUNTHIGH(val)       bfin_write16(USB_DMA2COUNTHIGH, val)
-
-/* USB Channel 3 Config Registers */
-
-#define bfin_read_USB_DMA3CONTROL()             bfin_read16(USB_DMA3CONTROL)
-#define bfin_write_USB_DMA3CONTROL(val)         bfin_write16(USB_DMA3CONTROL, val)
-#define bfin_read_USB_DMA3ADDRLOW()             bfin_read16(USB_DMA3ADDRLOW)
-#define bfin_write_USB_DMA3ADDRLOW(val)         bfin_write16(USB_DMA3ADDRLOW, val)
-#define bfin_read_USB_DMA3ADDRHIGH()            bfin_read16(USB_DMA3ADDRHIGH)
-#define bfin_write_USB_DMA3ADDRHIGH(val)        bfin_write16(USB_DMA3ADDRHIGH, val)
-#define bfin_read_USB_DMA3COUNTLOW()            bfin_read16(USB_DMA3COUNTLOW)
-#define bfin_write_USB_DMA3COUNTLOW(val)        bfin_write16(USB_DMA3COUNTLOW, val)
-#define bfin_read_USB_DMA3COUNTHIGH()           bfin_read16(USB_DMA3COUNTHIGH)
-#define bfin_write_USB_DMA3COUNTHIGH(val)       bfin_write16(USB_DMA3COUNTHIGH, val)
-
-/* USB Channel 4 Config Registers */
-
-#define bfin_read_USB_DMA4CONTROL()             bfin_read16(USB_DMA4CONTROL)
-#define bfin_write_USB_DMA4CONTROL(val)         bfin_write16(USB_DMA4CONTROL, val)
-#define bfin_read_USB_DMA4ADDRLOW()             bfin_read16(USB_DMA4ADDRLOW)
-#define bfin_write_USB_DMA4ADDRLOW(val)         bfin_write16(USB_DMA4ADDRLOW, val)
-#define bfin_read_USB_DMA4ADDRHIGH()            bfin_read16(USB_DMA4ADDRHIGH)
-#define bfin_write_USB_DMA4ADDRHIGH(val)        bfin_write16(USB_DMA4ADDRHIGH, val)
-#define bfin_read_USB_DMA4COUNTLOW()            bfin_read16(USB_DMA4COUNTLOW)
-#define bfin_write_USB_DMA4COUNTLOW(val)        bfin_write16(USB_DMA4COUNTLOW, val)
-#define bfin_read_USB_DMA4COUNTHIGH()           bfin_read16(USB_DMA4COUNTHIGH)
-#define bfin_write_USB_DMA4COUNTHIGH(val)       bfin_write16(USB_DMA4COUNTHIGH, val)
-
-/* USB Channel 5 Config Registers */
-
-#define bfin_read_USB_DMA5CONTROL()             bfin_read16(USB_DMA5CONTROL)
-#define bfin_write_USB_DMA5CONTROL(val)         bfin_write16(USB_DMA5CONTROL, val)
-#define bfin_read_USB_DMA5ADDRLOW()             bfin_read16(USB_DMA5ADDRLOW)
-#define bfin_write_USB_DMA5ADDRLOW(val)         bfin_write16(USB_DMA5ADDRLOW, val)
-#define bfin_read_USB_DMA5ADDRHIGH()            bfin_read16(USB_DMA5ADDRHIGH)
-#define bfin_write_USB_DMA5ADDRHIGH(val)        bfin_write16(USB_DMA5ADDRHIGH, val)
-#define bfin_read_USB_DMA5COUNTLOW()            bfin_read16(USB_DMA5COUNTLOW)
-#define bfin_write_USB_DMA5COUNTLOW(val)        bfin_write16(USB_DMA5COUNTLOW, val)
-#define bfin_read_USB_DMA5COUNTHIGH()           bfin_read16(USB_DMA5COUNTHIGH)
-#define bfin_write_USB_DMA5COUNTHIGH(val)       bfin_write16(USB_DMA5COUNTHIGH, val)
-
-/* USB Channel 6 Config Registers */
-
-#define bfin_read_USB_DMA6CONTROL()             bfin_read16(USB_DMA6CONTROL)
-#define bfin_write_USB_DMA6CONTROL(val)         bfin_write16(USB_DMA6CONTROL, val)
-#define bfin_read_USB_DMA6ADDRLOW()             bfin_read16(USB_DMA6ADDRLOW)
-#define bfin_write_USB_DMA6ADDRLOW(val)         bfin_write16(USB_DMA6ADDRLOW, val)
-#define bfin_read_USB_DMA6ADDRHIGH()            bfin_read16(USB_DMA6ADDRHIGH)
-#define bfin_write_USB_DMA6ADDRHIGH(val)        bfin_write16(USB_DMA6ADDRHIGH, val)
-#define bfin_read_USB_DMA6COUNTLOW()            bfin_read16(USB_DMA6COUNTLOW)
-#define bfin_write_USB_DMA6COUNTLOW(val)        bfin_write16(USB_DMA6COUNTLOW, val)
-#define bfin_read_USB_DMA6COUNTHIGH()           bfin_read16(USB_DMA6COUNTHIGH)
-#define bfin_write_USB_DMA6COUNTHIGH(val)       bfin_write16(USB_DMA6COUNTHIGH, val)
-
-/* USB Channel 7 Config Registers */
-
-#define bfin_read_USB_DMA7CONTROL()             bfin_read16(USB_DMA7CONTROL)
-#define bfin_write_USB_DMA7CONTROL(val)         bfin_write16(USB_DMA7CONTROL, val)
-#define bfin_read_USB_DMA7ADDRLOW()             bfin_read16(USB_DMA7ADDRLOW)
-#define bfin_write_USB_DMA7ADDRLOW(val)         bfin_write16(USB_DMA7ADDRLOW, val)
-#define bfin_read_USB_DMA7ADDRHIGH()            bfin_read16(USB_DMA7ADDRHIGH)
-#define bfin_write_USB_DMA7ADDRHIGH(val)        bfin_write16(USB_DMA7ADDRHIGH, val)
-#define bfin_read_USB_DMA7COUNTLOW()            bfin_read16(USB_DMA7COUNTLOW)
-#define bfin_write_USB_DMA7COUNTLOW(val)        bfin_write16(USB_DMA7COUNTLOW, val)
-#define bfin_read_USB_DMA7COUNTHIGH()           bfin_read16(USB_DMA7COUNTHIGH)
-#define bfin_write_USB_DMA7COUNTHIGH(val)       bfin_write16(USB_DMA7COUNTHIGH, val)
-
-/* Keybfin_read_()ad Registers */
-
-#define bfin_read_KPAD_CTL()            bfin_read16(KPAD_CTL)
-#define bfin_write_KPAD_CTL(val)        bfin_write16(KPAD_CTL, val)
-#define bfin_read_KPAD_PRESCALE()       bfin_read16(KPAD_PRESCALE)
-#define bfin_write_KPAD_PRESCALE(val)   bfin_write16(KPAD_PRESCALE, val)
-#define bfin_read_KPAD_MSEL()           bfin_read16(KPAD_MSEL)
-#define bfin_write_KPAD_MSEL(val)       bfin_write16(KPAD_MSEL, val)
-#define bfin_read_KPAD_ROWCOL()         bfin_read16(KPAD_ROWCOL)
-#define bfin_write_KPAD_ROWCOL(val)     bfin_write16(KPAD_ROWCOL, val)
-#define bfin_read_KPAD_STAT()           bfin_read16(KPAD_STAT)
-#define bfin_write_KPAD_STAT(val)       bfin_write16(KPAD_STAT, val)
-#define bfin_read_KPAD_SOFTEVAL()       bfin_read16(KPAD_SOFTEVAL)
-#define bfin_write_KPAD_SOFTEVAL(val)   bfin_write16(KPAD_SOFTEVAL, val)
-
-/* Pixel Combfin_read_()ositor (PIXC) Registers */
-
-#define bfin_read_PIXC_CTL()            bfin_read16(PIXC_CTL)
-#define bfin_write_PIXC_CTL(val)        bfin_write16(PIXC_CTL, val)
-#define bfin_read_PIXC_PPL()            bfin_read16(PIXC_PPL)
-#define bfin_write_PIXC_PPL(val)        bfin_write16(PIXC_PPL, val)
-#define bfin_read_PIXC_LPF()            bfin_read16(PIXC_LPF)
-#define bfin_write_PIXC_LPF(val)        bfin_write16(PIXC_LPF, val)
-#define bfin_read_PIXC_AHSTART()        bfin_read16(PIXC_AHSTART)
-#define bfin_write_PIXC_AHSTART(val)    bfin_write16(PIXC_AHSTART, val)
-#define bfin_read_PIXC_AHEND()          bfin_read16(PIXC_AHEND)
-#define bfin_write_PIXC_AHEND(val)      bfin_write16(PIXC_AHEND, val)
-#define bfin_read_PIXC_AVSTART()        bfin_read16(PIXC_AVSTART)
-#define bfin_write_PIXC_AVSTART(val)    bfin_write16(PIXC_AVSTART, val)
-#define bfin_read_PIXC_AVEND()          bfin_read16(PIXC_AVEND)
-#define bfin_write_PIXC_AVEND(val)      bfin_write16(PIXC_AVEND, val)
-#define bfin_read_PIXC_ATRANSP()        bfin_read16(PIXC_ATRANSP)
-#define bfin_write_PIXC_ATRANSP(val)    bfin_write16(PIXC_ATRANSP, val)
-#define bfin_read_PIXC_BHSTART()        bfin_read16(PIXC_BHSTART)
-#define bfin_write_PIXC_BHSTART(val)    bfin_write16(PIXC_BHSTART, val)
-#define bfin_read_PIXC_BHEND()          bfin_read16(PIXC_BHEND)
-#define bfin_write_PIXC_BHEND(val)      bfin_write16(PIXC_BHEND, val)
-#define bfin_read_PIXC_BVSTART()        bfin_read16(PIXC_BVSTART)
-#define bfin_write_PIXC_BVSTART(val)    bfin_write16(PIXC_BVSTART, val)
-#define bfin_read_PIXC_BVEND()          bfin_read16(PIXC_BVEND)
-#define bfin_write_PIXC_BVEND(val)      bfin_write16(PIXC_BVEND, val)
-#define bfin_read_PIXC_BTRANSP()        bfin_read16(PIXC_BTRANSP)
-#define bfin_write_PIXC_BTRANSP(val)    bfin_write16(PIXC_BTRANSP, val)
-#define bfin_read_PIXC_INTRSTAT()       bfin_read16(PIXC_INTRSTAT)
-#define bfin_write_PIXC_INTRSTAT(val)   bfin_write16(PIXC_INTRSTAT, val)
-#define bfin_read_PIXC_RYCON()          bfin_read32(PIXC_RYCON)
-#define bfin_write_PIXC_RYCON(val)      bfin_write32(PIXC_RYCON, val)
-#define bfin_read_PIXC_GUCON()          bfin_read32(PIXC_GUCON)
-#define bfin_write_PIXC_GUCON(val)      bfin_write32(PIXC_GUCON, val)
-#define bfin_read_PIXC_BVCON()          bfin_read32(PIXC_BVCON)
-#define bfin_write_PIXC_BVCON(val)      bfin_write32(PIXC_BVCON, val)
-#define bfin_read_PIXC_CCBIAS()         bfin_read32(PIXC_CCBIAS)
-#define bfin_write_PIXC_CCBIAS(val)     bfin_write32(PIXC_CCBIAS, val)
-#define bfin_read_PIXC_TC()             bfin_read32(PIXC_TC)
-#define bfin_write_PIXC_TC(val)         bfin_write32(PIXC_TC, val)
-
-/* Handshake MDMA 0 Registers */
-
-#define bfin_read_HMDMA0_CONTROL()              bfin_read16(HMDMA0_CONTROL)
-#define bfin_write_HMDMA0_CONTROL(val)          bfin_write16(HMDMA0_CONTROL, val)
-#define bfin_read_HMDMA0_ECINIT()               bfin_read16(HMDMA0_ECINIT)
-#define bfin_write_HMDMA0_ECINIT(val)           bfin_write16(HMDMA0_ECINIT, val)
-#define bfin_read_HMDMA0_BCINIT()               bfin_read16(HMDMA0_BCINIT)
-#define bfin_write_HMDMA0_BCINIT(val)           bfin_write16(HMDMA0_BCINIT, val)
-#define bfin_read_HMDMA0_ECURGENT()             bfin_read16(HMDMA0_ECURGENT)
-#define bfin_write_HMDMA0_ECURGENT(val)         bfin_write16(HMDMA0_ECURGENT, val)
-#define bfin_read_HMDMA0_ECOVERFLOW()           bfin_read16(HMDMA0_ECOVERFLOW)
-#define bfin_write_HMDMA0_ECOVERFLOW(val)       bfin_write16(HMDMA0_ECOVERFLOW, val)
-#define bfin_read_HMDMA0_ECOUNT()               bfin_read16(HMDMA0_ECOUNT)
-#define bfin_write_HMDMA0_ECOUNT(val)           bfin_write16(HMDMA0_ECOUNT, val)
-#define bfin_read_HMDMA0_BCOUNT()               bfin_read16(HMDMA0_BCOUNT)
-#define bfin_write_HMDMA0_BCOUNT(val)           bfin_write16(HMDMA0_BCOUNT, val)
-
-/* Handshake MDMA 1 Registers */
-
-#define bfin_read_HMDMA1_CONTROL()              bfin_read16(HMDMA1_CONTROL)
-#define bfin_write_HMDMA1_CONTROL(val)          bfin_write16(HMDMA1_CONTROL, val)
-#define bfin_read_HMDMA1_ECINIT()               bfin_read16(HMDMA1_ECINIT)
-#define bfin_write_HMDMA1_ECINIT(val)           bfin_write16(HMDMA1_ECINIT, val)
-#define bfin_read_HMDMA1_BCINIT()               bfin_read16(HMDMA1_BCINIT)
-#define bfin_write_HMDMA1_BCINIT(val)           bfin_write16(HMDMA1_BCINIT, val)
-#define bfin_read_HMDMA1_ECURGENT()             bfin_read16(HMDMA1_ECURGENT)
-#define bfin_write_HMDMA1_ECURGENT(val)         bfin_write16(HMDMA1_ECURGENT, val)
-#define bfin_read_HMDMA1_ECOVERFLOW()           bfin_read16(HMDMA1_ECOVERFLOW)
-#define bfin_write_HMDMA1_ECOVERFLOW(val)       bfin_write16(HMDMA1_ECOVERFLOW, val)
-#define bfin_read_HMDMA1_ECOUNT()               bfin_read16(HMDMA1_ECOUNT)
-#define bfin_write_HMDMA1_ECOUNT(val)           bfin_write16(HMDMA1_ECOUNT, val)
-#define bfin_read_HMDMA1_BCOUNT()               bfin_read16(HMDMA1_BCOUNT)
-#define bfin_write_HMDMA1_BCOUNT(val)           bfin_write16(HMDMA1_BCOUNT, val)
-
 #endif /* _CDEF_BF548_H */
diff --git a/arch/blackfin/mach-bf548/include/mach/cdefBF549.h b/arch/blackfin/mach-bf548/include/mach/cdefBF549.h
index 34c84c7fb256..80201ed41f80 100644
--- a/arch/blackfin/mach-bf548/include/mach/cdefBF549.h
+++ b/arch/blackfin/mach-bf548/include/mach/cdefBF549.h
@@ -18,165 +18,8 @@
 /* include cdefBF54x_base.h for the set of #defines that are common to all ADSP-BF54x bfin_read_()rocessors */
 #include "cdefBF54x_base.h"
 
-/* The following are the #defines needed by ADSP-BF549 that are not in the common header */
-
-/* Timer Registers */
-
-#define bfin_read_TIMER8_CONFIG()               bfin_read16(TIMER8_CONFIG)
-#define bfin_write_TIMER8_CONFIG(val)           bfin_write16(TIMER8_CONFIG, val)
-#define bfin_read_TIMER8_COUNTER()              bfin_read32(TIMER8_COUNTER)
-#define bfin_write_TIMER8_COUNTER(val)          bfin_write32(TIMER8_COUNTER, val)
-#define bfin_read_TIMER8_PERIOD()               bfin_read32(TIMER8_PERIOD)
-#define bfin_write_TIMER8_PERIOD(val)           bfin_write32(TIMER8_PERIOD, val)
-#define bfin_read_TIMER8_WIDTH()                bfin_read32(TIMER8_WIDTH)
-#define bfin_write_TIMER8_WIDTH(val)            bfin_write32(TIMER8_WIDTH, val)
-#define bfin_read_TIMER9_CONFIG()               bfin_read16(TIMER9_CONFIG)
-#define bfin_write_TIMER9_CONFIG(val)           bfin_write16(TIMER9_CONFIG, val)
-#define bfin_read_TIMER9_COUNTER()              bfin_read32(TIMER9_COUNTER)
-#define bfin_write_TIMER9_COUNTER(val)          bfin_write32(TIMER9_COUNTER, val)
-#define bfin_read_TIMER9_PERIOD()               bfin_read32(TIMER9_PERIOD)
-#define bfin_write_TIMER9_PERIOD(val)           bfin_write32(TIMER9_PERIOD, val)
-#define bfin_read_TIMER9_WIDTH()                bfin_read32(TIMER9_WIDTH)
-#define bfin_write_TIMER9_WIDTH(val)            bfin_write32(TIMER9_WIDTH, val)
-#define bfin_read_TIMER10_CONFIG()              bfin_read16(TIMER10_CONFIG)
-#define bfin_write_TIMER10_CONFIG(val)          bfin_write16(TIMER10_CONFIG, val)
-#define bfin_read_TIMER10_COUNTER()             bfin_read32(TIMER10_COUNTER)
-#define bfin_write_TIMER10_COUNTER(val)         bfin_write32(TIMER10_COUNTER, val)
-#define bfin_read_TIMER10_PERIOD()              bfin_read32(TIMER10_PERIOD)
-#define bfin_write_TIMER10_PERIOD(val)          bfin_write32(TIMER10_PERIOD, val)
-#define bfin_read_TIMER10_WIDTH()               bfin_read32(TIMER10_WIDTH)
-#define bfin_write_TIMER10_WIDTH(val)           bfin_write32(TIMER10_WIDTH, val)
-
-/* Timer Groubfin_read_() of 3 */
-
-#define bfin_read_TIMER_ENABLE1()               bfin_read16(TIMER_ENABLE1)
-#define bfin_write_TIMER_ENABLE1(val)           bfin_write16(TIMER_ENABLE1, val)
-#define bfin_read_TIMER_DISABLE1()              bfin_read16(TIMER_DISABLE1)
-#define bfin_write_TIMER_DISABLE1(val)          bfin_write16(TIMER_DISABLE1, val)
-#define bfin_read_TIMER_STATUS1()               bfin_read32(TIMER_STATUS1)
-#define bfin_write_TIMER_STATUS1(val)           bfin_write32(TIMER_STATUS1, val)
-
-/* SPORT0 Registers */
-
-#define bfin_read_SPORT0_TCR1()                 bfin_read16(SPORT0_TCR1)
-#define bfin_write_SPORT0_TCR1(val)             bfin_write16(SPORT0_TCR1, val)
-#define bfin_read_SPORT0_TCR2()                 bfin_read16(SPORT0_TCR2)
-#define bfin_write_SPORT0_TCR2(val)             bfin_write16(SPORT0_TCR2, val)
-#define bfin_read_SPORT0_TCLKDIV()              bfin_read16(SPORT0_TCLKDIV)
-#define bfin_write_SPORT0_TCLKDIV(val)          bfin_write16(SPORT0_TCLKDIV, val)
-#define bfin_read_SPORT0_TFSDIV()               bfin_read16(SPORT0_TFSDIV)
-#define bfin_write_SPORT0_TFSDIV(val)           bfin_write16(SPORT0_TFSDIV, val)
-#define bfin_read_SPORT0_TX()                   bfin_read32(SPORT0_TX)
-#define bfin_write_SPORT0_TX(val)               bfin_write32(SPORT0_TX, val)
-#define bfin_read_SPORT0_RX()                   bfin_read32(SPORT0_RX)
-#define bfin_write_SPORT0_RX(val)               bfin_write32(SPORT0_RX, val)
-#define bfin_read_SPORT0_RCR1()                 bfin_read16(SPORT0_RCR1)
-#define bfin_write_SPORT0_RCR1(val)             bfin_write16(SPORT0_RCR1, val)
-#define bfin_read_SPORT0_RCR2()                 bfin_read16(SPORT0_RCR2)
-#define bfin_write_SPORT0_RCR2(val)             bfin_write16(SPORT0_RCR2, val)
-#define bfin_read_SPORT0_RCLKDIV()              bfin_read16(SPORT0_RCLKDIV)
-#define bfin_write_SPORT0_RCLKDIV(val)          bfin_write16(SPORT0_RCLKDIV, val)
-#define bfin_read_SPORT0_RFSDIV()               bfin_read16(SPORT0_RFSDIV)
-#define bfin_write_SPORT0_RFSDIV(val)           bfin_write16(SPORT0_RFSDIV, val)
-#define bfin_read_SPORT0_STAT()                 bfin_read16(SPORT0_STAT)
-#define bfin_write_SPORT0_STAT(val)             bfin_write16(SPORT0_STAT, val)
-#define bfin_read_SPORT0_CHNL()                 bfin_read16(SPORT0_CHNL)
-#define bfin_write_SPORT0_CHNL(val)             bfin_write16(SPORT0_CHNL, val)
-#define bfin_read_SPORT0_MCMC1()                bfin_read16(SPORT0_MCMC1)
-#define bfin_write_SPORT0_MCMC1(val)            bfin_write16(SPORT0_MCMC1, val)
-#define bfin_read_SPORT0_MCMC2()                bfin_read16(SPORT0_MCMC2)
-#define bfin_write_SPORT0_MCMC2(val)            bfin_write16(SPORT0_MCMC2, val)
-#define bfin_read_SPORT0_MTCS0()                bfin_read32(SPORT0_MTCS0)
-#define bfin_write_SPORT0_MTCS0(val)            bfin_write32(SPORT0_MTCS0, val)
-#define bfin_read_SPORT0_MTCS1()                bfin_read32(SPORT0_MTCS1)
-#define bfin_write_SPORT0_MTCS1(val)            bfin_write32(SPORT0_MTCS1, val)
-#define bfin_read_SPORT0_MTCS2()                bfin_read32(SPORT0_MTCS2)
-#define bfin_write_SPORT0_MTCS2(val)            bfin_write32(SPORT0_MTCS2, val)
-#define bfin_read_SPORT0_MTCS3()                bfin_read32(SPORT0_MTCS3)
-#define bfin_write_SPORT0_MTCS3(val)            bfin_write32(SPORT0_MTCS3, val)
-#define bfin_read_SPORT0_MRCS0()                bfin_read32(SPORT0_MRCS0)
-#define bfin_write_SPORT0_MRCS0(val)            bfin_write32(SPORT0_MRCS0, val)
-#define bfin_read_SPORT0_MRCS1()                bfin_read32(SPORT0_MRCS1)
-#define bfin_write_SPORT0_MRCS1(val)            bfin_write32(SPORT0_MRCS1, val)
-#define bfin_read_SPORT0_MRCS2()                bfin_read32(SPORT0_MRCS2)
-#define bfin_write_SPORT0_MRCS2(val)            bfin_write32(SPORT0_MRCS2, val)
-#define bfin_read_SPORT0_MRCS3()                bfin_read32(SPORT0_MRCS3)
-#define bfin_write_SPORT0_MRCS3(val)            bfin_write32(SPORT0_MRCS3, val)
-
-/* EPPI0 Registers */
-
-#define bfin_read_EPPI0_STATUS()                bfin_read16(EPPI0_STATUS)
-#define bfin_write_EPPI0_STATUS(val)            bfin_write16(EPPI0_STATUS, val)
-#define bfin_read_EPPI0_HCOUNT()                bfin_read16(EPPI0_HCOUNT)
-#define bfin_write_EPPI0_HCOUNT(val)            bfin_write16(EPPI0_HCOUNT, val)
-#define bfin_read_EPPI0_HDELAY()                bfin_read16(EPPI0_HDELAY)
-#define bfin_write_EPPI0_HDELAY(val)            bfin_write16(EPPI0_HDELAY, val)
-#define bfin_read_EPPI0_VCOUNT()                bfin_read16(EPPI0_VCOUNT)
-#define bfin_write_EPPI0_VCOUNT(val)            bfin_write16(EPPI0_VCOUNT, val)
-#define bfin_read_EPPI0_VDELAY()                bfin_read16(EPPI0_VDELAY)
-#define bfin_write_EPPI0_VDELAY(val)            bfin_write16(EPPI0_VDELAY, val)
-#define bfin_read_EPPI0_FRAME()                 bfin_read16(EPPI0_FRAME)
-#define bfin_write_EPPI0_FRAME(val)             bfin_write16(EPPI0_FRAME, val)
-#define bfin_read_EPPI0_LINE()                  bfin_read16(EPPI0_LINE)
-#define bfin_write_EPPI0_LINE(val)              bfin_write16(EPPI0_LINE, val)
-#define bfin_read_EPPI0_CLKDIV()                bfin_read16(EPPI0_CLKDIV)
-#define bfin_write_EPPI0_CLKDIV(val)            bfin_write16(EPPI0_CLKDIV, val)
-#define bfin_read_EPPI0_CONTROL()               bfin_read32(EPPI0_CONTROL)
-#define bfin_write_EPPI0_CONTROL(val)           bfin_write32(EPPI0_CONTROL, val)
-#define bfin_read_EPPI0_FS1W_HBL()              bfin_read32(EPPI0_FS1W_HBL)
-#define bfin_write_EPPI0_FS1W_HBL(val)          bfin_write32(EPPI0_FS1W_HBL, val)
-#define bfin_read_EPPI0_FS1P_AVPL()             bfin_read32(EPPI0_FS1P_AVPL)
-#define bfin_write_EPPI0_FS1P_AVPL(val)         bfin_write32(EPPI0_FS1P_AVPL, val)
-#define bfin_read_EPPI0_FS2W_LVB()              bfin_read32(EPPI0_FS2W_LVB)
-#define bfin_write_EPPI0_FS2W_LVB(val)          bfin_write32(EPPI0_FS2W_LVB, val)
-#define bfin_read_EPPI0_FS2P_LAVF()             bfin_read32(EPPI0_FS2P_LAVF)
-#define bfin_write_EPPI0_FS2P_LAVF(val)         bfin_write32(EPPI0_FS2P_LAVF, val)
-#define bfin_read_EPPI0_CLIP()                  bfin_read32(EPPI0_CLIP)
-#define bfin_write_EPPI0_CLIP(val)              bfin_write32(EPPI0_CLIP, val)
-
-/* UART2 Registers */
-
-#define bfin_read_UART2_DLL()                   bfin_read16(UART2_DLL)
-#define bfin_write_UART2_DLL(val)               bfin_write16(UART2_DLL, val)
-#define bfin_read_UART2_DLH()                   bfin_read16(UART2_DLH)
-#define bfin_write_UART2_DLH(val)               bfin_write16(UART2_DLH, val)
-#define bfin_read_UART2_GCTL()                  bfin_read16(UART2_GCTL)
-#define bfin_write_UART2_GCTL(val)              bfin_write16(UART2_GCTL, val)
-#define bfin_read_UART2_LCR()                   bfin_read16(UART2_LCR)
-#define bfin_write_UART2_LCR(val)               bfin_write16(UART2_LCR, val)
-#define bfin_read_UART2_MCR()                   bfin_read16(UART2_MCR)
-#define bfin_write_UART2_MCR(val)               bfin_write16(UART2_MCR, val)
-#define bfin_read_UART2_LSR()                   bfin_read16(UART2_LSR)
-#define bfin_write_UART2_LSR(val)               bfin_write16(UART2_LSR, val)
-#define bfin_read_UART2_MSR()                   bfin_read16(UART2_MSR)
-#define bfin_write_UART2_MSR(val)               bfin_write16(UART2_MSR, val)
-#define bfin_read_UART2_SCR()                   bfin_read16(UART2_SCR)
-#define bfin_write_UART2_SCR(val)               bfin_write16(UART2_SCR, val)
-#define bfin_read_UART2_IER_SET()               bfin_read16(UART2_IER_SET)
-#define bfin_write_UART2_IER_SET(val)           bfin_write16(UART2_IER_SET, val)
-#define bfin_read_UART2_IER_CLEAR()             bfin_read16(UART2_IER_CLEAR)
-#define bfin_write_UART2_IER_CLEAR(val)         bfin_write16(UART2_IER_CLEAR, val)
-#define bfin_read_UART2_RBR()                   bfin_read16(UART2_RBR)
-#define bfin_write_UART2_RBR(val)               bfin_write16(UART2_RBR, val)
-
-/* Two Wire Interface Registers (TWI1) */
-
-/* SPI2 Registers */
-
-#define bfin_read_SPI2_CTL()            bfin_read16(SPI2_CTL)
-#define bfin_write_SPI2_CTL(val)        bfin_write16(SPI2_CTL, val)
-#define bfin_read_SPI2_FLG()            bfin_read16(SPI2_FLG)
-#define bfin_write_SPI2_FLG(val)        bfin_write16(SPI2_FLG, val)
-#define bfin_read_SPI2_STAT()           bfin_read16(SPI2_STAT)
-#define bfin_write_SPI2_STAT(val)       bfin_write16(SPI2_STAT, val)
-#define bfin_read_SPI2_TDBR()           bfin_read16(SPI2_TDBR)
-#define bfin_write_SPI2_TDBR(val)       bfin_write16(SPI2_TDBR, val)
-#define bfin_read_SPI2_RDBR()           bfin_read16(SPI2_RDBR)
-#define bfin_write_SPI2_RDBR(val)       bfin_write16(SPI2_RDBR, val)
-#define bfin_read_SPI2_BAUD()           bfin_read16(SPI2_BAUD)
-#define bfin_write_SPI2_BAUD(val)       bfin_write16(SPI2_BAUD, val)
-#define bfin_read_SPI2_SHADOW()         bfin_read16(SPI2_SHADOW)
-#define bfin_write_SPI2_SHADOW(val)     bfin_write16(SPI2_SHADOW, val)
+/* The BF549 is like the BF544, but has MXVR */
+#include "cdefBF547.h"
 
 /* MXVR Registers */
 
@@ -464,1376 +307,4 @@
 #define bfin_read_MXVR_SCLK_CNT()               bfin_read16(MXVR_SCLK_CNT)
 #define bfin_write_MXVR_SCLK_CNT(val)           bfin_write16(MXVR_SCLK_CNT, val)
 
-/* CAN Controller 1 Config 1 Registers */
-
-#define bfin_read_CAN1_MC1()            bfin_read16(CAN1_MC1)
-#define bfin_write_CAN1_MC1(val)        bfin_write16(CAN1_MC1, val)
-#define bfin_read_CAN1_MD1()            bfin_read16(CAN1_MD1)
-#define bfin_write_CAN1_MD1(val)        bfin_write16(CAN1_MD1, val)
-#define bfin_read_CAN1_TRS1()           bfin_read16(CAN1_TRS1)
-#define bfin_write_CAN1_TRS1(val)       bfin_write16(CAN1_TRS1, val)
-#define bfin_read_CAN1_TRR1()           bfin_read16(CAN1_TRR1)
-#define bfin_write_CAN1_TRR1(val)       bfin_write16(CAN1_TRR1, val)
-#define bfin_read_CAN1_TA1()            bfin_read16(CAN1_TA1)
-#define bfin_write_CAN1_TA1(val)        bfin_write16(CAN1_TA1, val)
-#define bfin_read_CAN1_AA1()            bfin_read16(CAN1_AA1)
-#define bfin_write_CAN1_AA1(val)        bfin_write16(CAN1_AA1, val)
-#define bfin_read_CAN1_RMP1()           bfin_read16(CAN1_RMP1)
-#define bfin_write_CAN1_RMP1(val)       bfin_write16(CAN1_RMP1, val)
-#define bfin_read_CAN1_RML1()           bfin_read16(CAN1_RML1)
-#define bfin_write_CAN1_RML1(val)       bfin_write16(CAN1_RML1, val)
-#define bfin_read_CAN1_MBTIF1()         bfin_read16(CAN1_MBTIF1)
-#define bfin_write_CAN1_MBTIF1(val)     bfin_write16(CAN1_MBTIF1, val)
-#define bfin_read_CAN1_MBRIF1()         bfin_read16(CAN1_MBRIF1)
-#define bfin_write_CAN1_MBRIF1(val)     bfin_write16(CAN1_MBRIF1, val)
-#define bfin_read_CAN1_MBIM1()          bfin_read16(CAN1_MBIM1)
-#define bfin_write_CAN1_MBIM1(val)      bfin_write16(CAN1_MBIM1, val)
-#define bfin_read_CAN1_RFH1()           bfin_read16(CAN1_RFH1)
-#define bfin_write_CAN1_RFH1(val)       bfin_write16(CAN1_RFH1, val)
-#define bfin_read_CAN1_OPSS1()          bfin_read16(CAN1_OPSS1)
-#define bfin_write_CAN1_OPSS1(val)      bfin_write16(CAN1_OPSS1, val)
-
-/* CAN Controller 1 Config 2 Registers */
-
-#define bfin_read_CAN1_MC2()            bfin_read16(CAN1_MC2)
-#define bfin_write_CAN1_MC2(val)        bfin_write16(CAN1_MC2, val)
-#define bfin_read_CAN1_MD2()            bfin_read16(CAN1_MD2)
-#define bfin_write_CAN1_MD2(val)        bfin_write16(CAN1_MD2, val)
-#define bfin_read_CAN1_TRS2()           bfin_read16(CAN1_TRS2)
-#define bfin_write_CAN1_TRS2(val)       bfin_write16(CAN1_TRS2, val)
-#define bfin_read_CAN1_TRR2()           bfin_read16(CAN1_TRR2)
-#define bfin_write_CAN1_TRR2(val)       bfin_write16(CAN1_TRR2, val)
-#define bfin_read_CAN1_TA2()            bfin_read16(CAN1_TA2)
-#define bfin_write_CAN1_TA2(val)        bfin_write16(CAN1_TA2, val)
-#define bfin_read_CAN1_AA2()            bfin_read16(CAN1_AA2)
-#define bfin_write_CAN1_AA2(val)        bfin_write16(CAN1_AA2, val)
-#define bfin_read_CAN1_RMP2()           bfin_read16(CAN1_RMP2)
-#define bfin_write_CAN1_RMP2(val)       bfin_write16(CAN1_RMP2, val)
-#define bfin_read_CAN1_RML2()           bfin_read16(CAN1_RML2)
-#define bfin_write_CAN1_RML2(val)       bfin_write16(CAN1_RML2, val)
-#define bfin_read_CAN1_MBTIF2()         bfin_read16(CAN1_MBTIF2)
-#define bfin_write_CAN1_MBTIF2(val)     bfin_write16(CAN1_MBTIF2, val)
-#define bfin_read_CAN1_MBRIF2()         bfin_read16(CAN1_MBRIF2)
-#define bfin_write_CAN1_MBRIF2(val)     bfin_write16(CAN1_MBRIF2, val)
-#define bfin_read_CAN1_MBIM2()          bfin_read16(CAN1_MBIM2)
-#define bfin_write_CAN1_MBIM2(val)      bfin_write16(CAN1_MBIM2, val)
-#define bfin_read_CAN1_RFH2()           bfin_read16(CAN1_RFH2)
-#define bfin_write_CAN1_RFH2(val)       bfin_write16(CAN1_RFH2, val)
-#define bfin_read_CAN1_OPSS2()          bfin_read16(CAN1_OPSS2)
-#define bfin_write_CAN1_OPSS2(val)      bfin_write16(CAN1_OPSS2, val)
-
-/* CAN Controller 1 Clock/Interrubfin_read_()t/Counter Registers */
-
-#define bfin_read_CAN1_CLOCK()          bfin_read16(CAN1_CLOCK)
-#define bfin_write_CAN1_CLOCK(val)      bfin_write16(CAN1_CLOCK, val)
-#define bfin_read_CAN1_TIMING()         bfin_read16(CAN1_TIMING)
-#define bfin_write_CAN1_TIMING(val)     bfin_write16(CAN1_TIMING, val)
-#define bfin_read_CAN1_DEBUG()          bfin_read16(CAN1_DEBUG)
-#define bfin_write_CAN1_DEBUG(val)      bfin_write16(CAN1_DEBUG, val)
-#define bfin_read_CAN1_STATUS()         bfin_read16(CAN1_STATUS)
-#define bfin_write_CAN1_STATUS(val)     bfin_write16(CAN1_STATUS, val)
-#define bfin_read_CAN1_CEC()            bfin_read16(CAN1_CEC)
-#define bfin_write_CAN1_CEC(val)        bfin_write16(CAN1_CEC, val)
-#define bfin_read_CAN1_GIS()            bfin_read16(CAN1_GIS)
-#define bfin_write_CAN1_GIS(val)        bfin_write16(CAN1_GIS, val)
-#define bfin_read_CAN1_GIM()            bfin_read16(CAN1_GIM)
-#define bfin_write_CAN1_GIM(val)        bfin_write16(CAN1_GIM, val)
-#define bfin_read_CAN1_GIF()            bfin_read16(CAN1_GIF)
-#define bfin_write_CAN1_GIF(val)        bfin_write16(CAN1_GIF, val)
-#define bfin_read_CAN1_CONTROL()        bfin_read16(CAN1_CONTROL)
-#define bfin_write_CAN1_CONTROL(val)    bfin_write16(CAN1_CONTROL, val)
-#define bfin_read_CAN1_INTR()           bfin_read16(CAN1_INTR)
-#define bfin_write_CAN1_INTR(val)       bfin_write16(CAN1_INTR, val)
-#define bfin_read_CAN1_MBTD()           bfin_read16(CAN1_MBTD)
-#define bfin_write_CAN1_MBTD(val)       bfin_write16(CAN1_MBTD, val)
-#define bfin_read_CAN1_EWR()            bfin_read16(CAN1_EWR)
-#define bfin_write_CAN1_EWR(val)        bfin_write16(CAN1_EWR, val)
-#define bfin_read_CAN1_ESR()            bfin_read16(CAN1_ESR)
-#define bfin_write_CAN1_ESR(val)        bfin_write16(CAN1_ESR, val)
-#define bfin_read_CAN1_UCCNT()          bfin_read16(CAN1_UCCNT)
-#define bfin_write_CAN1_UCCNT(val)      bfin_write16(CAN1_UCCNT, val)
-#define bfin_read_CAN1_UCRC()           bfin_read16(CAN1_UCRC)
-#define bfin_write_CAN1_UCRC(val)       bfin_write16(CAN1_UCRC, val)
-#define bfin_read_CAN1_UCCNF()          bfin_read16(CAN1_UCCNF)
-#define bfin_write_CAN1_UCCNF(val)      bfin_write16(CAN1_UCCNF, val)
-
-/* CAN Controller 1 Mailbox Accebfin_read_()tance Registers */
-
-#define bfin_read_CAN1_AM00L()          bfin_read16(CAN1_AM00L)
-#define bfin_write_CAN1_AM00L(val)      bfin_write16(CAN1_AM00L, val)
-#define bfin_read_CAN1_AM00H()          bfin_read16(CAN1_AM00H)
-#define bfin_write_CAN1_AM00H(val)      bfin_write16(CAN1_AM00H, val)
-#define bfin_read_CAN1_AM01L()          bfin_read16(CAN1_AM01L)
-#define bfin_write_CAN1_AM01L(val)      bfin_write16(CAN1_AM01L, val)
-#define bfin_read_CAN1_AM01H()          bfin_read16(CAN1_AM01H)
-#define bfin_write_CAN1_AM01H(val)      bfin_write16(CAN1_AM01H, val)
-#define bfin_read_CAN1_AM02L()          bfin_read16(CAN1_AM02L)
-#define bfin_write_CAN1_AM02L(val)      bfin_write16(CAN1_AM02L, val)
-#define bfin_read_CAN1_AM02H()          bfin_read16(CAN1_AM02H)
-#define bfin_write_CAN1_AM02H(val)      bfin_write16(CAN1_AM02H, val)
-#define bfin_read_CAN1_AM03L()          bfin_read16(CAN1_AM03L)
-#define bfin_write_CAN1_AM03L(val)      bfin_write16(CAN1_AM03L, val)
-#define bfin_read_CAN1_AM03H()          bfin_read16(CAN1_AM03H)
-#define bfin_write_CAN1_AM03H(val)      bfin_write16(CAN1_AM03H, val)
-#define bfin_read_CAN1_AM04L()          bfin_read16(CAN1_AM04L)
-#define bfin_write_CAN1_AM04L(val)      bfin_write16(CAN1_AM04L, val)
-#define bfin_read_CAN1_AM04H()          bfin_read16(CAN1_AM04H)
-#define bfin_write_CAN1_AM04H(val)      bfin_write16(CAN1_AM04H, val)
-#define bfin_read_CAN1_AM05L()          bfin_read16(CAN1_AM05L)
-#define bfin_write_CAN1_AM05L(val)      bfin_write16(CAN1_AM05L, val)
-#define bfin_read_CAN1_AM05H()          bfin_read16(CAN1_AM05H)
-#define bfin_write_CAN1_AM05H(val)      bfin_write16(CAN1_AM05H, val)
-#define bfin_read_CAN1_AM06L()          bfin_read16(CAN1_AM06L)
-#define bfin_write_CAN1_AM06L(val)      bfin_write16(CAN1_AM06L, val)
-#define bfin_read_CAN1_AM06H()          bfin_read16(CAN1_AM06H)
-#define bfin_write_CAN1_AM06H(val)      bfin_write16(CAN1_AM06H, val)
-#define bfin_read_CAN1_AM07L()          bfin_read16(CAN1_AM07L)
-#define bfin_write_CAN1_AM07L(val)      bfin_write16(CAN1_AM07L, val)
-#define bfin_read_CAN1_AM07H()          bfin_read16(CAN1_AM07H)
-#define bfin_write_CAN1_AM07H(val)      bfin_write16(CAN1_AM07H, val)
-#define bfin_read_CAN1_AM08L()          bfin_read16(CAN1_AM08L)
-#define bfin_write_CAN1_AM08L(val)      bfin_write16(CAN1_AM08L, val)
-#define bfin_read_CAN1_AM08H()          bfin_read16(CAN1_AM08H)
-#define bfin_write_CAN1_AM08H(val)      bfin_write16(CAN1_AM08H, val)
-#define bfin_read_CAN1_AM09L()          bfin_read16(CAN1_AM09L)
-#define bfin_write_CAN1_AM09L(val)      bfin_write16(CAN1_AM09L, val)
-#define bfin_read_CAN1_AM09H()          bfin_read16(CAN1_AM09H)
-#define bfin_write_CAN1_AM09H(val)      bfin_write16(CAN1_AM09H, val)
-#define bfin_read_CAN1_AM10L()          bfin_read16(CAN1_AM10L)
-#define bfin_write_CAN1_AM10L(val)      bfin_write16(CAN1_AM10L, val)
-#define bfin_read_CAN1_AM10H()          bfin_read16(CAN1_AM10H)
-#define bfin_write_CAN1_AM10H(val)      bfin_write16(CAN1_AM10H, val)
-#define bfin_read_CAN1_AM11L()          bfin_read16(CAN1_AM11L)
-#define bfin_write_CAN1_AM11L(val)      bfin_write16(CAN1_AM11L, val)
-#define bfin_read_CAN1_AM11H()          bfin_read16(CAN1_AM11H)
-#define bfin_write_CAN1_AM11H(val)      bfin_write16(CAN1_AM11H, val)
-#define bfin_read_CAN1_AM12L()          bfin_read16(CAN1_AM12L)
-#define bfin_write_CAN1_AM12L(val)      bfin_write16(CAN1_AM12L, val)
-#define bfin_read_CAN1_AM12H()          bfin_read16(CAN1_AM12H)
-#define bfin_write_CAN1_AM12H(val)      bfin_write16(CAN1_AM12H, val)
-#define bfin_read_CAN1_AM13L()          bfin_read16(CAN1_AM13L)
-#define bfin_write_CAN1_AM13L(val)      bfin_write16(CAN1_AM13L, val)
-#define bfin_read_CAN1_AM13H()          bfin_read16(CAN1_AM13H)
-#define bfin_write_CAN1_AM13H(val)      bfin_write16(CAN1_AM13H, val)
-#define bfin_read_CAN1_AM14L()          bfin_read16(CAN1_AM14L)
-#define bfin_write_CAN1_AM14L(val)      bfin_write16(CAN1_AM14L, val)
-#define bfin_read_CAN1_AM14H()          bfin_read16(CAN1_AM14H)
-#define bfin_write_CAN1_AM14H(val)      bfin_write16(CAN1_AM14H, val)
-#define bfin_read_CAN1_AM15L()          bfin_read16(CAN1_AM15L)
-#define bfin_write_CAN1_AM15L(val)      bfin_write16(CAN1_AM15L, val)
-#define bfin_read_CAN1_AM15H()          bfin_read16(CAN1_AM15H)
-#define bfin_write_CAN1_AM15H(val)      bfin_write16(CAN1_AM15H, val)
-
-/* CAN Controller 1 Mailbox Accebfin_read_()tance Registers */
-
-#define bfin_read_CAN1_AM16L()          bfin_read16(CAN1_AM16L)
-#define bfin_write_CAN1_AM16L(val)      bfin_write16(CAN1_AM16L, val)
-#define bfin_read_CAN1_AM16H()          bfin_read16(CAN1_AM16H)
-#define bfin_write_CAN1_AM16H(val)      bfin_write16(CAN1_AM16H, val)
-#define bfin_read_CAN1_AM17L()          bfin_read16(CAN1_AM17L)
-#define bfin_write_CAN1_AM17L(val)      bfin_write16(CAN1_AM17L, val)
-#define bfin_read_CAN1_AM17H()          bfin_read16(CAN1_AM17H)
-#define bfin_write_CAN1_AM17H(val)      bfin_write16(CAN1_AM17H, val)
-#define bfin_read_CAN1_AM18L()          bfin_read16(CAN1_AM18L)
-#define bfin_write_CAN1_AM18L(val)      bfin_write16(CAN1_AM18L, val)
-#define bfin_read_CAN1_AM18H()          bfin_read16(CAN1_AM18H)
-#define bfin_write_CAN1_AM18H(val)      bfin_write16(CAN1_AM18H, val)
-#define bfin_read_CAN1_AM19L()          bfin_read16(CAN1_AM19L)
-#define bfin_write_CAN1_AM19L(val)      bfin_write16(CAN1_AM19L, val)
-#define bfin_read_CAN1_AM19H()          bfin_read16(CAN1_AM19H)
-#define bfin_write_CAN1_AM19H(val)      bfin_write16(CAN1_AM19H, val)
-#define bfin_read_CAN1_AM20L()          bfin_read16(CAN1_AM20L)
-#define bfin_write_CAN1_AM20L(val)      bfin_write16(CAN1_AM20L, val)
-#define bfin_read_CAN1_AM20H()          bfin_read16(CAN1_AM20H)
-#define bfin_write_CAN1_AM20H(val)      bfin_write16(CAN1_AM20H, val)
-#define bfin_read_CAN1_AM21L()          bfin_read16(CAN1_AM21L)
-#define bfin_write_CAN1_AM21L(val)      bfin_write16(CAN1_AM21L, val)
-#define bfin_read_CAN1_AM21H()          bfin_read16(CAN1_AM21H)
-#define bfin_write_CAN1_AM21H(val)      bfin_write16(CAN1_AM21H, val)
-#define bfin_read_CAN1_AM22L()          bfin_read16(CAN1_AM22L)
-#define bfin_write_CAN1_AM22L(val)      bfin_write16(CAN1_AM22L, val)
-#define bfin_read_CAN1_AM22H()          bfin_read16(CAN1_AM22H)
-#define bfin_write_CAN1_AM22H(val)      bfin_write16(CAN1_AM22H, val)
-#define bfin_read_CAN1_AM23L()          bfin_read16(CAN1_AM23L)
-#define bfin_write_CAN1_AM23L(val)      bfin_write16(CAN1_AM23L, val)
-#define bfin_read_CAN1_AM23H()          bfin_read16(CAN1_AM23H)
-#define bfin_write_CAN1_AM23H(val)      bfin_write16(CAN1_AM23H, val)
-#define bfin_read_CAN1_AM24L()          bfin_read16(CAN1_AM24L)
-#define bfin_write_CAN1_AM24L(val)      bfin_write16(CAN1_AM24L, val)
-#define bfin_read_CAN1_AM24H()          bfin_read16(CAN1_AM24H)
-#define bfin_write_CAN1_AM24H(val)      bfin_write16(CAN1_AM24H, val)
-#define bfin_read_CAN1_AM25L()          bfin_read16(CAN1_AM25L)
-#define bfin_write_CAN1_AM25L(val)      bfin_write16(CAN1_AM25L, val)
-#define bfin_read_CAN1_AM25H()          bfin_read16(CAN1_AM25H)
-#define bfin_write_CAN1_AM25H(val)      bfin_write16(CAN1_AM25H, val)
-#define bfin_read_CAN1_AM26L()          bfin_read16(CAN1_AM26L)
-#define bfin_write_CAN1_AM26L(val)      bfin_write16(CAN1_AM26L, val)
-#define bfin_read_CAN1_AM26H()          bfin_read16(CAN1_AM26H)
-#define bfin_write_CAN1_AM26H(val)      bfin_write16(CAN1_AM26H, val)
-#define bfin_read_CAN1_AM27L()          bfin_read16(CAN1_AM27L)
-#define bfin_write_CAN1_AM27L(val)      bfin_write16(CAN1_AM27L, val)
-#define bfin_read_CAN1_AM27H()          bfin_read16(CAN1_AM27H)
-#define bfin_write_CAN1_AM27H(val)      bfin_write16(CAN1_AM27H, val)
-#define bfin_read_CAN1_AM28L()          bfin_read16(CAN1_AM28L)
-#define bfin_write_CAN1_AM28L(val)      bfin_write16(CAN1_AM28L, val)
-#define bfin_read_CAN1_AM28H()          bfin_read16(CAN1_AM28H)
-#define bfin_write_CAN1_AM28H(val)      bfin_write16(CAN1_AM28H, val)
-#define bfin_read_CAN1_AM29L()          bfin_read16(CAN1_AM29L)
-#define bfin_write_CAN1_AM29L(val)      bfin_write16(CAN1_AM29L, val)
-#define bfin_read_CAN1_AM29H()          bfin_read16(CAN1_AM29H)
-#define bfin_write_CAN1_AM29H(val)      bfin_write16(CAN1_AM29H, val)
-#define bfin_read_CAN1_AM30L()          bfin_read16(CAN1_AM30L)
-#define bfin_write_CAN1_AM30L(val)      bfin_write16(CAN1_AM30L, val)
-#define bfin_read_CAN1_AM30H()          bfin_read16(CAN1_AM30H)
-#define bfin_write_CAN1_AM30H(val)      bfin_write16(CAN1_AM30H, val)
-#define bfin_read_CAN1_AM31L()          bfin_read16(CAN1_AM31L)
-#define bfin_write_CAN1_AM31L(val)      bfin_write16(CAN1_AM31L, val)
-#define bfin_read_CAN1_AM31H()          bfin_read16(CAN1_AM31H)
-#define bfin_write_CAN1_AM31H(val)      bfin_write16(CAN1_AM31H, val)
-
-/* CAN Controller 1 Mailbox Data Registers */
-
-#define bfin_read_CAN1_MB00_DATA0()             bfin_read16(CAN1_MB00_DATA0)
-#define bfin_write_CAN1_MB00_DATA0(val)         bfin_write16(CAN1_MB00_DATA0, val)
-#define bfin_read_CAN1_MB00_DATA1()             bfin_read16(CAN1_MB00_DATA1)
-#define bfin_write_CAN1_MB00_DATA1(val)         bfin_write16(CAN1_MB00_DATA1, val)
-#define bfin_read_CAN1_MB00_DATA2()             bfin_read16(CAN1_MB00_DATA2)
-#define bfin_write_CAN1_MB00_DATA2(val)         bfin_write16(CAN1_MB00_DATA2, val)
-#define bfin_read_CAN1_MB00_DATA3()             bfin_read16(CAN1_MB00_DATA3)
-#define bfin_write_CAN1_MB00_DATA3(val)         bfin_write16(CAN1_MB00_DATA3, val)
-#define bfin_read_CAN1_MB00_LENGTH()            bfin_read16(CAN1_MB00_LENGTH)
-#define bfin_write_CAN1_MB00_LENGTH(val)        bfin_write16(CAN1_MB00_LENGTH, val)
-#define bfin_read_CAN1_MB00_TIMESTAMP()         bfin_read16(CAN1_MB00_TIMESTAMP)
-#define bfin_write_CAN1_MB00_TIMESTAMP(val)     bfin_write16(CAN1_MB00_TIMESTAMP, val)
-#define bfin_read_CAN1_MB00_ID0()               bfin_read16(CAN1_MB00_ID0)
-#define bfin_write_CAN1_MB00_ID0(val)           bfin_write16(CAN1_MB00_ID0, val)
-#define bfin_read_CAN1_MB00_ID1()               bfin_read16(CAN1_MB00_ID1)
-#define bfin_write_CAN1_MB00_ID1(val)           bfin_write16(CAN1_MB00_ID1, val)
-#define bfin_read_CAN1_MB01_DATA0()             bfin_read16(CAN1_MB01_DATA0)
-#define bfin_write_CAN1_MB01_DATA0(val)         bfin_write16(CAN1_MB01_DATA0, val)
-#define bfin_read_CAN1_MB01_DATA1()             bfin_read16(CAN1_MB01_DATA1)
-#define bfin_write_CAN1_MB01_DATA1(val)         bfin_write16(CAN1_MB01_DATA1, val)
-#define bfin_read_CAN1_MB01_DATA2()             bfin_read16(CAN1_MB01_DATA2)
-#define bfin_write_CAN1_MB01_DATA2(val)         bfin_write16(CAN1_MB01_DATA2, val)
-#define bfin_read_CAN1_MB01_DATA3()             bfin_read16(CAN1_MB01_DATA3)
-#define bfin_write_CAN1_MB01_DATA3(val)         bfin_write16(CAN1_MB01_DATA3, val)
-#define bfin_read_CAN1_MB01_LENGTH()            bfin_read16(CAN1_MB01_LENGTH)
-#define bfin_write_CAN1_MB01_LENGTH(val)        bfin_write16(CAN1_MB01_LENGTH, val)
-#define bfin_read_CAN1_MB01_TIMESTAMP()         bfin_read16(CAN1_MB01_TIMESTAMP)
-#define bfin_write_CAN1_MB01_TIMESTAMP(val)     bfin_write16(CAN1_MB01_TIMESTAMP, val)
-#define bfin_read_CAN1_MB01_ID0()               bfin_read16(CAN1_MB01_ID0)
-#define bfin_write_CAN1_MB01_ID0(val)           bfin_write16(CAN1_MB01_ID0, val)
-#define bfin_read_CAN1_MB01_ID1()               bfin_read16(CAN1_MB01_ID1)
-#define bfin_write_CAN1_MB01_ID1(val)           bfin_write16(CAN1_MB01_ID1, val)
-#define bfin_read_CAN1_MB02_DATA0()             bfin_read16(CAN1_MB02_DATA0)
-#define bfin_write_CAN1_MB02_DATA0(val)         bfin_write16(CAN1_MB02_DATA0, val)
-#define bfin_read_CAN1_MB02_DATA1()             bfin_read16(CAN1_MB02_DATA1)
-#define bfin_write_CAN1_MB02_DATA1(val)         bfin_write16(CAN1_MB02_DATA1, val)
-#define bfin_read_CAN1_MB02_DATA2()             bfin_read16(CAN1_MB02_DATA2)
-#define bfin_write_CAN1_MB02_DATA2(val)         bfin_write16(CAN1_MB02_DATA2, val)
-#define bfin_read_CAN1_MB02_DATA3()             bfin_read16(CAN1_MB02_DATA3)
-#define bfin_write_CAN1_MB02_DATA3(val)         bfin_write16(CAN1_MB02_DATA3, val)
-#define bfin_read_CAN1_MB02_LENGTH()            bfin_read16(CAN1_MB02_LENGTH)
-#define bfin_write_CAN1_MB02_LENGTH(val)        bfin_write16(CAN1_MB02_LENGTH, val)
-#define bfin_read_CAN1_MB02_TIMESTAMP()         bfin_read16(CAN1_MB02_TIMESTAMP)
-#define bfin_write_CAN1_MB02_TIMESTAMP(val)     bfin_write16(CAN1_MB02_TIMESTAMP, val)
-#define bfin_read_CAN1_MB02_ID0()               bfin_read16(CAN1_MB02_ID0)
-#define bfin_write_CAN1_MB02_ID0(val)           bfin_write16(CAN1_MB02_ID0, val)
-#define bfin_read_CAN1_MB02_ID1()               bfin_read16(CAN1_MB02_ID1)
-#define bfin_write_CAN1_MB02_ID1(val)           bfin_write16(CAN1_MB02_ID1, val)
-#define bfin_read_CAN1_MB03_DATA0()             bfin_read16(CAN1_MB03_DATA0)
-#define bfin_write_CAN1_MB03_DATA0(val)         bfin_write16(CAN1_MB03_DATA0, val)
-#define bfin_read_CAN1_MB03_DATA1()             bfin_read16(CAN1_MB03_DATA1)
-#define bfin_write_CAN1_MB03_DATA1(val)         bfin_write16(CAN1_MB03_DATA1, val)
-#define bfin_read_CAN1_MB03_DATA2()             bfin_read16(CAN1_MB03_DATA2)
-#define bfin_write_CAN1_MB03_DATA2(val)         bfin_write16(CAN1_MB03_DATA2, val)
-#define bfin_read_CAN1_MB03_DATA3()             bfin_read16(CAN1_MB03_DATA3)
-#define bfin_write_CAN1_MB03_DATA3(val)         bfin_write16(CAN1_MB03_DATA3, val)
-#define bfin_read_CAN1_MB03_LENGTH()            bfin_read16(CAN1_MB03_LENGTH)
-#define bfin_write_CAN1_MB03_LENGTH(val)        bfin_write16(CAN1_MB03_LENGTH, val)
-#define bfin_read_CAN1_MB03_TIMESTAMP()         bfin_read16(CAN1_MB03_TIMESTAMP)
-#define bfin_write_CAN1_MB03_TIMESTAMP(val)     bfin_write16(CAN1_MB03_TIMESTAMP, val)
-#define bfin_read_CAN1_MB03_ID0()               bfin_read16(CAN1_MB03_ID0)
-#define bfin_write_CAN1_MB03_ID0(val)           bfin_write16(CAN1_MB03_ID0, val)
-#define bfin_read_CAN1_MB03_ID1()               bfin_read16(CAN1_MB03_ID1)
-#define bfin_write_CAN1_MB03_ID1(val)           bfin_write16(CAN1_MB03_ID1, val)
-#define bfin_read_CAN1_MB04_DATA0()             bfin_read16(CAN1_MB04_DATA0)
-#define bfin_write_CAN1_MB04_DATA0(val)         bfin_write16(CAN1_MB04_DATA0, val)
-#define bfin_read_CAN1_MB04_DATA1()             bfin_read16(CAN1_MB04_DATA1)
-#define bfin_write_CAN1_MB04_DATA1(val)         bfin_write16(CAN1_MB04_DATA1, val)
-#define bfin_read_CAN1_MB04_DATA2()             bfin_read16(CAN1_MB04_DATA2)
-#define bfin_write_CAN1_MB04_DATA2(val)         bfin_write16(CAN1_MB04_DATA2, val)
-#define bfin_read_CAN1_MB04_DATA3()             bfin_read16(CAN1_MB04_DATA3)
-#define bfin_write_CAN1_MB04_DATA3(val)         bfin_write16(CAN1_MB04_DATA3, val)
-#define bfin_read_CAN1_MB04_LENGTH()            bfin_read16(CAN1_MB04_LENGTH)
-#define bfin_write_CAN1_MB04_LENGTH(val)        bfin_write16(CAN1_MB04_LENGTH, val)
-#define bfin_read_CAN1_MB04_TIMESTAMP()         bfin_read16(CAN1_MB04_TIMESTAMP)
-#define bfin_write_CAN1_MB04_TIMESTAMP(val)     bfin_write16(CAN1_MB04_TIMESTAMP, val)
-#define bfin_read_CAN1_MB04_ID0()               bfin_read16(CAN1_MB04_ID0)
-#define bfin_write_CAN1_MB04_ID0(val)           bfin_write16(CAN1_MB04_ID0, val)
-#define bfin_read_CAN1_MB04_ID1()               bfin_read16(CAN1_MB04_ID1)
-#define bfin_write_CAN1_MB04_ID1(val)           bfin_write16(CAN1_MB04_ID1, val)
-#define bfin_read_CAN1_MB05_DATA0()             bfin_read16(CAN1_MB05_DATA0)
-#define bfin_write_CAN1_MB05_DATA0(val)         bfin_write16(CAN1_MB05_DATA0, val)
-#define bfin_read_CAN1_MB05_DATA1()             bfin_read16(CAN1_MB05_DATA1)
-#define bfin_write_CAN1_MB05_DATA1(val)         bfin_write16(CAN1_MB05_DATA1, val)
-#define bfin_read_CAN1_MB05_DATA2()             bfin_read16(CAN1_MB05_DATA2)
-#define bfin_write_CAN1_MB05_DATA2(val)         bfin_write16(CAN1_MB05_DATA2, val)
-#define bfin_read_CAN1_MB05_DATA3()             bfin_read16(CAN1_MB05_DATA3)
-#define bfin_write_CAN1_MB05_DATA3(val)         bfin_write16(CAN1_MB05_DATA3, val)
-#define bfin_read_CAN1_MB05_LENGTH()            bfin_read16(CAN1_MB05_LENGTH)
-#define bfin_write_CAN1_MB05_LENGTH(val)        bfin_write16(CAN1_MB05_LENGTH, val)
-#define bfin_read_CAN1_MB05_TIMESTAMP()         bfin_read16(CAN1_MB05_TIMESTAMP)
-#define bfin_write_CAN1_MB05_TIMESTAMP(val)     bfin_write16(CAN1_MB05_TIMESTAMP, val)
-#define bfin_read_CAN1_MB05_ID0()               bfin_read16(CAN1_MB05_ID0)
-#define bfin_write_CAN1_MB05_ID0(val)           bfin_write16(CAN1_MB05_ID0, val)
-#define bfin_read_CAN1_MB05_ID1()               bfin_read16(CAN1_MB05_ID1)
-#define bfin_write_CAN1_MB05_ID1(val)           bfin_write16(CAN1_MB05_ID1, val)
-#define bfin_read_CAN1_MB06_DATA0()             bfin_read16(CAN1_MB06_DATA0)
-#define bfin_write_CAN1_MB06_DATA0(val)         bfin_write16(CAN1_MB06_DATA0, val)
-#define bfin_read_CAN1_MB06_DATA1()             bfin_read16(CAN1_MB06_DATA1)
-#define bfin_write_CAN1_MB06_DATA1(val)         bfin_write16(CAN1_MB06_DATA1, val)
-#define bfin_read_CAN1_MB06_DATA2()             bfin_read16(CAN1_MB06_DATA2)
-#define bfin_write_CAN1_MB06_DATA2(val)         bfin_write16(CAN1_MB06_DATA2, val)
-#define bfin_read_CAN1_MB06_DATA3()             bfin_read16(CAN1_MB06_DATA3)
-#define bfin_write_CAN1_MB06_DATA3(val)         bfin_write16(CAN1_MB06_DATA3, val)
-#define bfin_read_CAN1_MB06_LENGTH()            bfin_read16(CAN1_MB06_LENGTH)
-#define bfin_write_CAN1_MB06_LENGTH(val)        bfin_write16(CAN1_MB06_LENGTH, val)
-#define bfin_read_CAN1_MB06_TIMESTAMP()         bfin_read16(CAN1_MB06_TIMESTAMP)
-#define bfin_write_CAN1_MB06_TIMESTAMP(val)     bfin_write16(CAN1_MB06_TIMESTAMP, val)
-#define bfin_read_CAN1_MB06_ID0()               bfin_read16(CAN1_MB06_ID0)
-#define bfin_write_CAN1_MB06_ID0(val)           bfin_write16(CAN1_MB06_ID0, val)
-#define bfin_read_CAN1_MB06_ID1()               bfin_read16(CAN1_MB06_ID1)
-#define bfin_write_CAN1_MB06_ID1(val)           bfin_write16(CAN1_MB06_ID1, val)
-#define bfin_read_CAN1_MB07_DATA0()             bfin_read16(CAN1_MB07_DATA0)
-#define bfin_write_CAN1_MB07_DATA0(val)         bfin_write16(CAN1_MB07_DATA0, val)
-#define bfin_read_CAN1_MB07_DATA1()             bfin_read16(CAN1_MB07_DATA1)
-#define bfin_write_CAN1_MB07_DATA1(val)         bfin_write16(CAN1_MB07_DATA1, val)
-#define bfin_read_CAN1_MB07_DATA2()             bfin_read16(CAN1_MB07_DATA2)
-#define bfin_write_CAN1_MB07_DATA2(val)         bfin_write16(CAN1_MB07_DATA2, val)
-#define bfin_read_CAN1_MB07_DATA3()             bfin_read16(CAN1_MB07_DATA3)
-#define bfin_write_CAN1_MB07_DATA3(val)         bfin_write16(CAN1_MB07_DATA3, val)
-#define bfin_read_CAN1_MB07_LENGTH()            bfin_read16(CAN1_MB07_LENGTH)
-#define bfin_write_CAN1_MB07_LENGTH(val)        bfin_write16(CAN1_MB07_LENGTH, val)
-#define bfin_read_CAN1_MB07_TIMESTAMP()         bfin_read16(CAN1_MB07_TIMESTAMP)
-#define bfin_write_CAN1_MB07_TIMESTAMP(val)     bfin_write16(CAN1_MB07_TIMESTAMP, val)
-#define bfin_read_CAN1_MB07_ID0()               bfin_read16(CAN1_MB07_ID0)
-#define bfin_write_CAN1_MB07_ID0(val)           bfin_write16(CAN1_MB07_ID0, val)
-#define bfin_read_CAN1_MB07_ID1()               bfin_read16(CAN1_MB07_ID1)
-#define bfin_write_CAN1_MB07_ID1(val)           bfin_write16(CAN1_MB07_ID1, val)
-#define bfin_read_CAN1_MB08_DATA0()             bfin_read16(CAN1_MB08_DATA0)
-#define bfin_write_CAN1_MB08_DATA0(val)         bfin_write16(CAN1_MB08_DATA0, val)
-#define bfin_read_CAN1_MB08_DATA1()             bfin_read16(CAN1_MB08_DATA1)
-#define bfin_write_CAN1_MB08_DATA1(val)         bfin_write16(CAN1_MB08_DATA1, val)
-#define bfin_read_CAN1_MB08_DATA2()             bfin_read16(CAN1_MB08_DATA2)
-#define bfin_write_CAN1_MB08_DATA2(val)         bfin_write16(CAN1_MB08_DATA2, val)
-#define bfin_read_CAN1_MB08_DATA3()             bfin_read16(CAN1_MB08_DATA3)
-#define bfin_write_CAN1_MB08_DATA3(val)         bfin_write16(CAN1_MB08_DATA3, val)
-#define bfin_read_CAN1_MB08_LENGTH()            bfin_read16(CAN1_MB08_LENGTH)
-#define bfin_write_CAN1_MB08_LENGTH(val)        bfin_write16(CAN1_MB08_LENGTH, val)
-#define bfin_read_CAN1_MB08_TIMESTAMP()         bfin_read16(CAN1_MB08_TIMESTAMP)
-#define bfin_write_CAN1_MB08_TIMESTAMP(val)     bfin_write16(CAN1_MB08_TIMESTAMP, val)
-#define bfin_read_CAN1_MB08_ID0()               bfin_read16(CAN1_MB08_ID0)
-#define bfin_write_CAN1_MB08_ID0(val)           bfin_write16(CAN1_MB08_ID0, val)
-#define bfin_read_CAN1_MB08_ID1()               bfin_read16(CAN1_MB08_ID1)
-#define bfin_write_CAN1_MB08_ID1(val)           bfin_write16(CAN1_MB08_ID1, val)
-#define bfin_read_CAN1_MB09_DATA0()             bfin_read16(CAN1_MB09_DATA0)
-#define bfin_write_CAN1_MB09_DATA0(val)         bfin_write16(CAN1_MB09_DATA0, val)
-#define bfin_read_CAN1_MB09_DATA1()             bfin_read16(CAN1_MB09_DATA1)
-#define bfin_write_CAN1_MB09_DATA1(val)         bfin_write16(CAN1_MB09_DATA1, val)
-#define bfin_read_CAN1_MB09_DATA2()             bfin_read16(CAN1_MB09_DATA2)
-#define bfin_write_CAN1_MB09_DATA2(val)         bfin_write16(CAN1_MB09_DATA2, val)
-#define bfin_read_CAN1_MB09_DATA3()             bfin_read16(CAN1_MB09_DATA3)
-#define bfin_write_CAN1_MB09_DATA3(val)         bfin_write16(CAN1_MB09_DATA3, val)
-#define bfin_read_CAN1_MB09_LENGTH()            bfin_read16(CAN1_MB09_LENGTH)
-#define bfin_write_CAN1_MB09_LENGTH(val)        bfin_write16(CAN1_MB09_LENGTH, val)
-#define bfin_read_CAN1_MB09_TIMESTAMP()         bfin_read16(CAN1_MB09_TIMESTAMP)
-#define bfin_write_CAN1_MB09_TIMESTAMP(val)     bfin_write16(CAN1_MB09_TIMESTAMP, val)
-#define bfin_read_CAN1_MB09_ID0()               bfin_read16(CAN1_MB09_ID0)
-#define bfin_write_CAN1_MB09_ID0(val)           bfin_write16(CAN1_MB09_ID0, val)
-#define bfin_read_CAN1_MB09_ID1()               bfin_read16(CAN1_MB09_ID1)
-#define bfin_write_CAN1_MB09_ID1(val)           bfin_write16(CAN1_MB09_ID1, val)
-#define bfin_read_CAN1_MB10_DATA0()             bfin_read16(CAN1_MB10_DATA0)
-#define bfin_write_CAN1_MB10_DATA0(val)         bfin_write16(CAN1_MB10_DATA0, val)
-#define bfin_read_CAN1_MB10_DATA1()             bfin_read16(CAN1_MB10_DATA1)
-#define bfin_write_CAN1_MB10_DATA1(val)         bfin_write16(CAN1_MB10_DATA1, val)
-#define bfin_read_CAN1_MB10_DATA2()             bfin_read16(CAN1_MB10_DATA2)
-#define bfin_write_CAN1_MB10_DATA2(val)         bfin_write16(CAN1_MB10_DATA2, val)
-#define bfin_read_CAN1_MB10_DATA3()             bfin_read16(CAN1_MB10_DATA3)
-#define bfin_write_CAN1_MB10_DATA3(val)         bfin_write16(CAN1_MB10_DATA3, val)
-#define bfin_read_CAN1_MB10_LENGTH()            bfin_read16(CAN1_MB10_LENGTH)
-#define bfin_write_CAN1_MB10_LENGTH(val)        bfin_write16(CAN1_MB10_LENGTH, val)
-#define bfin_read_CAN1_MB10_TIMESTAMP()         bfin_read16(CAN1_MB10_TIMESTAMP)
-#define bfin_write_CAN1_MB10_TIMESTAMP(val)     bfin_write16(CAN1_MB10_TIMESTAMP, val)
-#define bfin_read_CAN1_MB10_ID0()               bfin_read16(CAN1_MB10_ID0)
-#define bfin_write_CAN1_MB10_ID0(val)           bfin_write16(CAN1_MB10_ID0, val)
-#define bfin_read_CAN1_MB10_ID1()               bfin_read16(CAN1_MB10_ID1)
-#define bfin_write_CAN1_MB10_ID1(val)           bfin_write16(CAN1_MB10_ID1, val)
-#define bfin_read_CAN1_MB11_DATA0()             bfin_read16(CAN1_MB11_DATA0)
-#define bfin_write_CAN1_MB11_DATA0(val)         bfin_write16(CAN1_MB11_DATA0, val)
-#define bfin_read_CAN1_MB11_DATA1()             bfin_read16(CAN1_MB11_DATA1)
-#define bfin_write_CAN1_MB11_DATA1(val)         bfin_write16(CAN1_MB11_DATA1, val)
-#define bfin_read_CAN1_MB11_DATA2()             bfin_read16(CAN1_MB11_DATA2)
-#define bfin_write_CAN1_MB11_DATA2(val)         bfin_write16(CAN1_MB11_DATA2, val)
-#define bfin_read_CAN1_MB11_DATA3()             bfin_read16(CAN1_MB11_DATA3)
-#define bfin_write_CAN1_MB11_DATA3(val)         bfin_write16(CAN1_MB11_DATA3, val)
-#define bfin_read_CAN1_MB11_LENGTH()            bfin_read16(CAN1_MB11_LENGTH)
-#define bfin_write_CAN1_MB11_LENGTH(val)        bfin_write16(CAN1_MB11_LENGTH, val)
-#define bfin_read_CAN1_MB11_TIMESTAMP()         bfin_read16(CAN1_MB11_TIMESTAMP)
-#define bfin_write_CAN1_MB11_TIMESTAMP(val)     bfin_write16(CAN1_MB11_TIMESTAMP, val)
-#define bfin_read_CAN1_MB11_ID0()               bfin_read16(CAN1_MB11_ID0)
-#define bfin_write_CAN1_MB11_ID0(val)           bfin_write16(CAN1_MB11_ID0, val)
-#define bfin_read_CAN1_MB11_ID1()               bfin_read16(CAN1_MB11_ID1)
-#define bfin_write_CAN1_MB11_ID1(val)           bfin_write16(CAN1_MB11_ID1, val)
-#define bfin_read_CAN1_MB12_DATA0()             bfin_read16(CAN1_MB12_DATA0)
-#define bfin_write_CAN1_MB12_DATA0(val)         bfin_write16(CAN1_MB12_DATA0, val)
-#define bfin_read_CAN1_MB12_DATA1()             bfin_read16(CAN1_MB12_DATA1)
-#define bfin_write_CAN1_MB12_DATA1(val)         bfin_write16(CAN1_MB12_DATA1, val)
-#define bfin_read_CAN1_MB12_DATA2()             bfin_read16(CAN1_MB12_DATA2)
-#define bfin_write_CAN1_MB12_DATA2(val)         bfin_write16(CAN1_MB12_DATA2, val)
-#define bfin_read_CAN1_MB12_DATA3()             bfin_read16(CAN1_MB12_DATA3)
-#define bfin_write_CAN1_MB12_DATA3(val)         bfin_write16(CAN1_MB12_DATA3, val)
-#define bfin_read_CAN1_MB12_LENGTH()            bfin_read16(CAN1_MB12_LENGTH)
-#define bfin_write_CAN1_MB12_LENGTH(val)        bfin_write16(CAN1_MB12_LENGTH, val)
-#define bfin_read_CAN1_MB12_TIMESTAMP()         bfin_read16(CAN1_MB12_TIMESTAMP)
-#define bfin_write_CAN1_MB12_TIMESTAMP(val)     bfin_write16(CAN1_MB12_TIMESTAMP, val)
-#define bfin_read_CAN1_MB12_ID0()               bfin_read16(CAN1_MB12_ID0)
-#define bfin_write_CAN1_MB12_ID0(val)           bfin_write16(CAN1_MB12_ID0, val)
-#define bfin_read_CAN1_MB12_ID1()               bfin_read16(CAN1_MB12_ID1)
-#define bfin_write_CAN1_MB12_ID1(val)           bfin_write16(CAN1_MB12_ID1, val)
-#define bfin_read_CAN1_MB13_DATA0()             bfin_read16(CAN1_MB13_DATA0)
-#define bfin_write_CAN1_MB13_DATA0(val)         bfin_write16(CAN1_MB13_DATA0, val)
-#define bfin_read_CAN1_MB13_DATA1()             bfin_read16(CAN1_MB13_DATA1)
-#define bfin_write_CAN1_MB13_DATA1(val)         bfin_write16(CAN1_MB13_DATA1, val)
-#define bfin_read_CAN1_MB13_DATA2()             bfin_read16(CAN1_MB13_DATA2)
-#define bfin_write_CAN1_MB13_DATA2(val)         bfin_write16(CAN1_MB13_DATA2, val)
-#define bfin_read_CAN1_MB13_DATA3()             bfin_read16(CAN1_MB13_DATA3)
-#define bfin_write_CAN1_MB13_DATA3(val)         bfin_write16(CAN1_MB13_DATA3, val)
-#define bfin_read_CAN1_MB13_LENGTH()            bfin_read16(CAN1_MB13_LENGTH)
-#define bfin_write_CAN1_MB13_LENGTH(val)        bfin_write16(CAN1_MB13_LENGTH, val)
-#define bfin_read_CAN1_MB13_TIMESTAMP()         bfin_read16(CAN1_MB13_TIMESTAMP)
-#define bfin_write_CAN1_MB13_TIMESTAMP(val)     bfin_write16(CAN1_MB13_TIMESTAMP, val)
-#define bfin_read_CAN1_MB13_ID0()               bfin_read16(CAN1_MB13_ID0)
-#define bfin_write_CAN1_MB13_ID0(val)           bfin_write16(CAN1_MB13_ID0, val)
-#define bfin_read_CAN1_MB13_ID1()               bfin_read16(CAN1_MB13_ID1)
-#define bfin_write_CAN1_MB13_ID1(val)           bfin_write16(CAN1_MB13_ID1, val)
-#define bfin_read_CAN1_MB14_DATA0()             bfin_read16(CAN1_MB14_DATA0)
-#define bfin_write_CAN1_MB14_DATA0(val)         bfin_write16(CAN1_MB14_DATA0, val)
-#define bfin_read_CAN1_MB14_DATA1()             bfin_read16(CAN1_MB14_DATA1)
-#define bfin_write_CAN1_MB14_DATA1(val)         bfin_write16(CAN1_MB14_DATA1, val)
-#define bfin_read_CAN1_MB14_DATA2()             bfin_read16(CAN1_MB14_DATA2)
-#define bfin_write_CAN1_MB14_DATA2(val)         bfin_write16(CAN1_MB14_DATA2, val)
-#define bfin_read_CAN1_MB14_DATA3()             bfin_read16(CAN1_MB14_DATA3)
-#define bfin_write_CAN1_MB14_DATA3(val)         bfin_write16(CAN1_MB14_DATA3, val)
-#define bfin_read_CAN1_MB14_LENGTH()            bfin_read16(CAN1_MB14_LENGTH)
-#define bfin_write_CAN1_MB14_LENGTH(val)        bfin_write16(CAN1_MB14_LENGTH, val)
-#define bfin_read_CAN1_MB14_TIMESTAMP()         bfin_read16(CAN1_MB14_TIMESTAMP)
-#define bfin_write_CAN1_MB14_TIMESTAMP(val)     bfin_write16(CAN1_MB14_TIMESTAMP, val)
-#define bfin_read_CAN1_MB14_ID0()               bfin_read16(CAN1_MB14_ID0)
-#define bfin_write_CAN1_MB14_ID0(val)           bfin_write16(CAN1_MB14_ID0, val)
-#define bfin_read_CAN1_MB14_ID1()               bfin_read16(CAN1_MB14_ID1)
-#define bfin_write_CAN1_MB14_ID1(val)           bfin_write16(CAN1_MB14_ID1, val)
-#define bfin_read_CAN1_MB15_DATA0()             bfin_read16(CAN1_MB15_DATA0)
-#define bfin_write_CAN1_MB15_DATA0(val)         bfin_write16(CAN1_MB15_DATA0, val)
-#define bfin_read_CAN1_MB15_DATA1()             bfin_read16(CAN1_MB15_DATA1)
-#define bfin_write_CAN1_MB15_DATA1(val)         bfin_write16(CAN1_MB15_DATA1, val)
-#define bfin_read_CAN1_MB15_DATA2()             bfin_read16(CAN1_MB15_DATA2)
-#define bfin_write_CAN1_MB15_DATA2(val)         bfin_write16(CAN1_MB15_DATA2, val)
-#define bfin_read_CAN1_MB15_DATA3()             bfin_read16(CAN1_MB15_DATA3)
-#define bfin_write_CAN1_MB15_DATA3(val)         bfin_write16(CAN1_MB15_DATA3, val)
-#define bfin_read_CAN1_MB15_LENGTH()            bfin_read16(CAN1_MB15_LENGTH)
-#define bfin_write_CAN1_MB15_LENGTH(val)        bfin_write16(CAN1_MB15_LENGTH, val)
-#define bfin_read_CAN1_MB15_TIMESTAMP()         bfin_read16(CAN1_MB15_TIMESTAMP)
-#define bfin_write_CAN1_MB15_TIMESTAMP(val)     bfin_write16(CAN1_MB15_TIMESTAMP, val)
-#define bfin_read_CAN1_MB15_ID0()               bfin_read16(CAN1_MB15_ID0)
-#define bfin_write_CAN1_MB15_ID0(val)           bfin_write16(CAN1_MB15_ID0, val)
-#define bfin_read_CAN1_MB15_ID1()               bfin_read16(CAN1_MB15_ID1)
-#define bfin_write_CAN1_MB15_ID1(val)           bfin_write16(CAN1_MB15_ID1, val)
-
-/* CAN Controller 1 Mailbox Data Registers */
-
-#define bfin_read_CAN1_MB16_DATA0()             bfin_read16(CAN1_MB16_DATA0)
-#define bfin_write_CAN1_MB16_DATA0(val)         bfin_write16(CAN1_MB16_DATA0, val)
-#define bfin_read_CAN1_MB16_DATA1()             bfin_read16(CAN1_MB16_DATA1)
-#define bfin_write_CAN1_MB16_DATA1(val)         bfin_write16(CAN1_MB16_DATA1, val)
-#define bfin_read_CAN1_MB16_DATA2()             bfin_read16(CAN1_MB16_DATA2)
-#define bfin_write_CAN1_MB16_DATA2(val)         bfin_write16(CAN1_MB16_DATA2, val)
-#define bfin_read_CAN1_MB16_DATA3()             bfin_read16(CAN1_MB16_DATA3)
-#define bfin_write_CAN1_MB16_DATA3(val)         bfin_write16(CAN1_MB16_DATA3, val)
-#define bfin_read_CAN1_MB16_LENGTH()            bfin_read16(CAN1_MB16_LENGTH)
-#define bfin_write_CAN1_MB16_LENGTH(val)        bfin_write16(CAN1_MB16_LENGTH, val)
-#define bfin_read_CAN1_MB16_TIMESTAMP()         bfin_read16(CAN1_MB16_TIMESTAMP)
-#define bfin_write_CAN1_MB16_TIMESTAMP(val)     bfin_write16(CAN1_MB16_TIMESTAMP, val)
-#define bfin_read_CAN1_MB16_ID0()               bfin_read16(CAN1_MB16_ID0)
-#define bfin_write_CAN1_MB16_ID0(val)           bfin_write16(CAN1_MB16_ID0, val)
-#define bfin_read_CAN1_MB16_ID1()               bfin_read16(CAN1_MB16_ID1)
-#define bfin_write_CAN1_MB16_ID1(val)           bfin_write16(CAN1_MB16_ID1, val)
-#define bfin_read_CAN1_MB17_DATA0()             bfin_read16(CAN1_MB17_DATA0)
-#define bfin_write_CAN1_MB17_DATA0(val)         bfin_write16(CAN1_MB17_DATA0, val)
-#define bfin_read_CAN1_MB17_DATA1()             bfin_read16(CAN1_MB17_DATA1)
-#define bfin_write_CAN1_MB17_DATA1(val)         bfin_write16(CAN1_MB17_DATA1, val)
-#define bfin_read_CAN1_MB17_DATA2()             bfin_read16(CAN1_MB17_DATA2)
-#define bfin_write_CAN1_MB17_DATA2(val)         bfin_write16(CAN1_MB17_DATA2, val)
-#define bfin_read_CAN1_MB17_DATA3()             bfin_read16(CAN1_MB17_DATA3)
-#define bfin_write_CAN1_MB17_DATA3(val)         bfin_write16(CAN1_MB17_DATA3, val)
-#define bfin_read_CAN1_MB17_LENGTH()            bfin_read16(CAN1_MB17_LENGTH)
-#define bfin_write_CAN1_MB17_LENGTH(val)        bfin_write16(CAN1_MB17_LENGTH, val)
-#define bfin_read_CAN1_MB17_TIMESTAMP()         bfin_read16(CAN1_MB17_TIMESTAMP)
-#define bfin_write_CAN1_MB17_TIMESTAMP(val)     bfin_write16(CAN1_MB17_TIMESTAMP, val)
-#define bfin_read_CAN1_MB17_ID0()               bfin_read16(CAN1_MB17_ID0)
-#define bfin_write_CAN1_MB17_ID0(val)           bfin_write16(CAN1_MB17_ID0, val)
-#define bfin_read_CAN1_MB17_ID1()               bfin_read16(CAN1_MB17_ID1)
-#define bfin_write_CAN1_MB17_ID1(val)           bfin_write16(CAN1_MB17_ID1, val)
-#define bfin_read_CAN1_MB18_DATA0()             bfin_read16(CAN1_MB18_DATA0)
-#define bfin_write_CAN1_MB18_DATA0(val)         bfin_write16(CAN1_MB18_DATA0, val)
-#define bfin_read_CAN1_MB18_DATA1()             bfin_read16(CAN1_MB18_DATA1)
-#define bfin_write_CAN1_MB18_DATA1(val)         bfin_write16(CAN1_MB18_DATA1, val)
-#define bfin_read_CAN1_MB18_DATA2()             bfin_read16(CAN1_MB18_DATA2)
-#define bfin_write_CAN1_MB18_DATA2(val)         bfin_write16(CAN1_MB18_DATA2, val)
-#define bfin_read_CAN1_MB18_DATA3()             bfin_read16(CAN1_MB18_DATA3)
-#define bfin_write_CAN1_MB18_DATA3(val)         bfin_write16(CAN1_MB18_DATA3, val)
-#define bfin_read_CAN1_MB18_LENGTH()            bfin_read16(CAN1_MB18_LENGTH)
-#define bfin_write_CAN1_MB18_LENGTH(val)        bfin_write16(CAN1_MB18_LENGTH, val)
-#define bfin_read_CAN1_MB18_TIMESTAMP()         bfin_read16(CAN1_MB18_TIMESTAMP)
-#define bfin_write_CAN1_MB18_TIMESTAMP(val)     bfin_write16(CAN1_MB18_TIMESTAMP, val)
-#define bfin_read_CAN1_MB18_ID0()               bfin_read16(CAN1_MB18_ID0)
-#define bfin_write_CAN1_MB18_ID0(val)           bfin_write16(CAN1_MB18_ID0, val)
-#define bfin_read_CAN1_MB18_ID1()               bfin_read16(CAN1_MB18_ID1)
-#define bfin_write_CAN1_MB18_ID1(val)           bfin_write16(CAN1_MB18_ID1, val)
-#define bfin_read_CAN1_MB19_DATA0()             bfin_read16(CAN1_MB19_DATA0)
-#define bfin_write_CAN1_MB19_DATA0(val)         bfin_write16(CAN1_MB19_DATA0, val)
-#define bfin_read_CAN1_MB19_DATA1()             bfin_read16(CAN1_MB19_DATA1)
-#define bfin_write_CAN1_MB19_DATA1(val)         bfin_write16(CAN1_MB19_DATA1, val)
-#define bfin_read_CAN1_MB19_DATA2()             bfin_read16(CAN1_MB19_DATA2)
-#define bfin_write_CAN1_MB19_DATA2(val)         bfin_write16(CAN1_MB19_DATA2, val)
-#define bfin_read_CAN1_MB19_DATA3()             bfin_read16(CAN1_MB19_DATA3)
-#define bfin_write_CAN1_MB19_DATA3(val)         bfin_write16(CAN1_MB19_DATA3, val)
-#define bfin_read_CAN1_MB19_LENGTH()            bfin_read16(CAN1_MB19_LENGTH)
-#define bfin_write_CAN1_MB19_LENGTH(val)        bfin_write16(CAN1_MB19_LENGTH, val)
-#define bfin_read_CAN1_MB19_TIMESTAMP()         bfin_read16(CAN1_MB19_TIMESTAMP)
-#define bfin_write_CAN1_MB19_TIMESTAMP(val)     bfin_write16(CAN1_MB19_TIMESTAMP, val)
-#define bfin_read_CAN1_MB19_ID0()               bfin_read16(CAN1_MB19_ID0)
-#define bfin_write_CAN1_MB19_ID0(val)           bfin_write16(CAN1_MB19_ID0, val)
-#define bfin_read_CAN1_MB19_ID1()               bfin_read16(CAN1_MB19_ID1)
-#define bfin_write_CAN1_MB19_ID1(val)           bfin_write16(CAN1_MB19_ID1, val)
-#define bfin_read_CAN1_MB20_DATA0()             bfin_read16(CAN1_MB20_DATA0)
-#define bfin_write_CAN1_MB20_DATA0(val)         bfin_write16(CAN1_MB20_DATA0, val)
-#define bfin_read_CAN1_MB20_DATA1()             bfin_read16(CAN1_MB20_DATA1)
-#define bfin_write_CAN1_MB20_DATA1(val)         bfin_write16(CAN1_MB20_DATA1, val)
-#define bfin_read_CAN1_MB20_DATA2()             bfin_read16(CAN1_MB20_DATA2)
-#define bfin_write_CAN1_MB20_DATA2(val)         bfin_write16(CAN1_MB20_DATA2, val)
-#define bfin_read_CAN1_MB20_DATA3()             bfin_read16(CAN1_MB20_DATA3)
-#define bfin_write_CAN1_MB20_DATA3(val)         bfin_write16(CAN1_MB20_DATA3, val)
-#define bfin_read_CAN1_MB20_LENGTH()            bfin_read16(CAN1_MB20_LENGTH)
-#define bfin_write_CAN1_MB20_LENGTH(val)        bfin_write16(CAN1_MB20_LENGTH, val)
-#define bfin_read_CAN1_MB20_TIMESTAMP()         bfin_read16(CAN1_MB20_TIMESTAMP)
-#define bfin_write_CAN1_MB20_TIMESTAMP(val)     bfin_write16(CAN1_MB20_TIMESTAMP, val)
-#define bfin_read_CAN1_MB20_ID0()               bfin_read16(CAN1_MB20_ID0)
-#define bfin_write_CAN1_MB20_ID0(val)           bfin_write16(CAN1_MB20_ID0, val)
-#define bfin_read_CAN1_MB20_ID1()               bfin_read16(CAN1_MB20_ID1)
-#define bfin_write_CAN1_MB20_ID1(val)           bfin_write16(CAN1_MB20_ID1, val)
-#define bfin_read_CAN1_MB21_DATA0()             bfin_read16(CAN1_MB21_DATA0)
-#define bfin_write_CAN1_MB21_DATA0(val)         bfin_write16(CAN1_MB21_DATA0, val)
-#define bfin_read_CAN1_MB21_DATA1()             bfin_read16(CAN1_MB21_DATA1)
-#define bfin_write_CAN1_MB21_DATA1(val)         bfin_write16(CAN1_MB21_DATA1, val)
-#define bfin_read_CAN1_MB21_DATA2()             bfin_read16(CAN1_MB21_DATA2)
-#define bfin_write_CAN1_MB21_DATA2(val)         bfin_write16(CAN1_MB21_DATA2, val)
-#define bfin_read_CAN1_MB21_DATA3()             bfin_read16(CAN1_MB21_DATA3)
-#define bfin_write_CAN1_MB21_DATA3(val)         bfin_write16(CAN1_MB21_DATA3, val)
-#define bfin_read_CAN1_MB21_LENGTH()            bfin_read16(CAN1_MB21_LENGTH)
-#define bfin_write_CAN1_MB21_LENGTH(val)        bfin_write16(CAN1_MB21_LENGTH, val)
-#define bfin_read_CAN1_MB21_TIMESTAMP()         bfin_read16(CAN1_MB21_TIMESTAMP)
-#define bfin_write_CAN1_MB21_TIMESTAMP(val)     bfin_write16(CAN1_MB21_TIMESTAMP, val)
-#define bfin_read_CAN1_MB21_ID0()               bfin_read16(CAN1_MB21_ID0)
-#define bfin_write_CAN1_MB21_ID0(val)           bfin_write16(CAN1_MB21_ID0, val)
-#define bfin_read_CAN1_MB21_ID1()               bfin_read16(CAN1_MB21_ID1)
-#define bfin_write_CAN1_MB21_ID1(val)           bfin_write16(CAN1_MB21_ID1, val)
-#define bfin_read_CAN1_MB22_DATA0()             bfin_read16(CAN1_MB22_DATA0)
-#define bfin_write_CAN1_MB22_DATA0(val)         bfin_write16(CAN1_MB22_DATA0, val)
-#define bfin_read_CAN1_MB22_DATA1()             bfin_read16(CAN1_MB22_DATA1)
-#define bfin_write_CAN1_MB22_DATA1(val)         bfin_write16(CAN1_MB22_DATA1, val)
-#define bfin_read_CAN1_MB22_DATA2()             bfin_read16(CAN1_MB22_DATA2)
-#define bfin_write_CAN1_MB22_DATA2(val)         bfin_write16(CAN1_MB22_DATA2, val)
-#define bfin_read_CAN1_MB22_DATA3()             bfin_read16(CAN1_MB22_DATA3)
-#define bfin_write_CAN1_MB22_DATA3(val)         bfin_write16(CAN1_MB22_DATA3, val)
-#define bfin_read_CAN1_MB22_LENGTH()            bfin_read16(CAN1_MB22_LENGTH)
-#define bfin_write_CAN1_MB22_LENGTH(val)        bfin_write16(CAN1_MB22_LENGTH, val)
-#define bfin_read_CAN1_MB22_TIMESTAMP()         bfin_read16(CAN1_MB22_TIMESTAMP)
-#define bfin_write_CAN1_MB22_TIMESTAMP(val)     bfin_write16(CAN1_MB22_TIMESTAMP, val)
-#define bfin_read_CAN1_MB22_ID0()               bfin_read16(CAN1_MB22_ID0)
-#define bfin_write_CAN1_MB22_ID0(val)           bfin_write16(CAN1_MB22_ID0, val)
-#define bfin_read_CAN1_MB22_ID1()               bfin_read16(CAN1_MB22_ID1)
-#define bfin_write_CAN1_MB22_ID1(val)           bfin_write16(CAN1_MB22_ID1, val)
-#define bfin_read_CAN1_MB23_DATA0()             bfin_read16(CAN1_MB23_DATA0)
-#define bfin_write_CAN1_MB23_DATA0(val)         bfin_write16(CAN1_MB23_DATA0, val)
-#define bfin_read_CAN1_MB23_DATA1()             bfin_read16(CAN1_MB23_DATA1)
-#define bfin_write_CAN1_MB23_DATA1(val)         bfin_write16(CAN1_MB23_DATA1, val)
-#define bfin_read_CAN1_MB23_DATA2()             bfin_read16(CAN1_MB23_DATA2)
-#define bfin_write_CAN1_MB23_DATA2(val)         bfin_write16(CAN1_MB23_DATA2, val)
-#define bfin_read_CAN1_MB23_DATA3()             bfin_read16(CAN1_MB23_DATA3)
-#define bfin_write_CAN1_MB23_DATA3(val)         bfin_write16(CAN1_MB23_DATA3, val)
-#define bfin_read_CAN1_MB23_LENGTH()            bfin_read16(CAN1_MB23_LENGTH)
-#define bfin_write_CAN1_MB23_LENGTH(val)        bfin_write16(CAN1_MB23_LENGTH, val)
-#define bfin_read_CAN1_MB23_TIMESTAMP()         bfin_read16(CAN1_MB23_TIMESTAMP)
-#define bfin_write_CAN1_MB23_TIMESTAMP(val)     bfin_write16(CAN1_MB23_TIMESTAMP, val)
-#define bfin_read_CAN1_MB23_ID0()               bfin_read16(CAN1_MB23_ID0)
-#define bfin_write_CAN1_MB23_ID0(val)           bfin_write16(CAN1_MB23_ID0, val)
-#define bfin_read_CAN1_MB23_ID1()               bfin_read16(CAN1_MB23_ID1)
-#define bfin_write_CAN1_MB23_ID1(val)           bfin_write16(CAN1_MB23_ID1, val)
-#define bfin_read_CAN1_MB24_DATA0()             bfin_read16(CAN1_MB24_DATA0)
-#define bfin_write_CAN1_MB24_DATA0(val)         bfin_write16(CAN1_MB24_DATA0, val)
-#define bfin_read_CAN1_MB24_DATA1()             bfin_read16(CAN1_MB24_DATA1)
-#define bfin_write_CAN1_MB24_DATA1(val)         bfin_write16(CAN1_MB24_DATA1, val)
-#define bfin_read_CAN1_MB24_DATA2()             bfin_read16(CAN1_MB24_DATA2)
-#define bfin_write_CAN1_MB24_DATA2(val)         bfin_write16(CAN1_MB24_DATA2, val)
-#define bfin_read_CAN1_MB24_DATA3()             bfin_read16(CAN1_MB24_DATA3)
-#define bfin_write_CAN1_MB24_DATA3(val)         bfin_write16(CAN1_MB24_DATA3, val)
-#define bfin_read_CAN1_MB24_LENGTH()            bfin_read16(CAN1_MB24_LENGTH)
-#define bfin_write_CAN1_MB24_LENGTH(val)        bfin_write16(CAN1_MB24_LENGTH, val)
-#define bfin_read_CAN1_MB24_TIMESTAMP()         bfin_read16(CAN1_MB24_TIMESTAMP)
-#define bfin_write_CAN1_MB24_TIMESTAMP(val)     bfin_write16(CAN1_MB24_TIMESTAMP, val)
-#define bfin_read_CAN1_MB24_ID0()               bfin_read16(CAN1_MB24_ID0)
-#define bfin_write_CAN1_MB24_ID0(val)           bfin_write16(CAN1_MB24_ID0, val)
-#define bfin_read_CAN1_MB24_ID1()               bfin_read16(CAN1_MB24_ID1)
-#define bfin_write_CAN1_MB24_ID1(val)           bfin_write16(CAN1_MB24_ID1, val)
-#define bfin_read_CAN1_MB25_DATA0()             bfin_read16(CAN1_MB25_DATA0)
-#define bfin_write_CAN1_MB25_DATA0(val)         bfin_write16(CAN1_MB25_DATA0, val)
-#define bfin_read_CAN1_MB25_DATA1()             bfin_read16(CAN1_MB25_DATA1)
-#define bfin_write_CAN1_MB25_DATA1(val)         bfin_write16(CAN1_MB25_DATA1, val)
-#define bfin_read_CAN1_MB25_DATA2()             bfin_read16(CAN1_MB25_DATA2)
-#define bfin_write_CAN1_MB25_DATA2(val)         bfin_write16(CAN1_MB25_DATA2, val)
-#define bfin_read_CAN1_MB25_DATA3()             bfin_read16(CAN1_MB25_DATA3)
-#define bfin_write_CAN1_MB25_DATA3(val)         bfin_write16(CAN1_MB25_DATA3, val)
-#define bfin_read_CAN1_MB25_LENGTH()            bfin_read16(CAN1_MB25_LENGTH)
-#define bfin_write_CAN1_MB25_LENGTH(val)        bfin_write16(CAN1_MB25_LENGTH, val)
-#define bfin_read_CAN1_MB25_TIMESTAMP()         bfin_read16(CAN1_MB25_TIMESTAMP)
-#define bfin_write_CAN1_MB25_TIMESTAMP(val)     bfin_write16(CAN1_MB25_TIMESTAMP, val)
-#define bfin_read_CAN1_MB25_ID0()               bfin_read16(CAN1_MB25_ID0)
-#define bfin_write_CAN1_MB25_ID0(val)           bfin_write16(CAN1_MB25_ID0, val)
-#define bfin_read_CAN1_MB25_ID1()               bfin_read16(CAN1_MB25_ID1)
-#define bfin_write_CAN1_MB25_ID1(val)           bfin_write16(CAN1_MB25_ID1, val)
-#define bfin_read_CAN1_MB26_DATA0()             bfin_read16(CAN1_MB26_DATA0)
-#define bfin_write_CAN1_MB26_DATA0(val)         bfin_write16(CAN1_MB26_DATA0, val)
-#define bfin_read_CAN1_MB26_DATA1()             bfin_read16(CAN1_MB26_DATA1)
-#define bfin_write_CAN1_MB26_DATA1(val)         bfin_write16(CAN1_MB26_DATA1, val)
-#define bfin_read_CAN1_MB26_DATA2()             bfin_read16(CAN1_MB26_DATA2)
-#define bfin_write_CAN1_MB26_DATA2(val)         bfin_write16(CAN1_MB26_DATA2, val)
-#define bfin_read_CAN1_MB26_DATA3()             bfin_read16(CAN1_MB26_DATA3)
-#define bfin_write_CAN1_MB26_DATA3(val)         bfin_write16(CAN1_MB26_DATA3, val)
-#define bfin_read_CAN1_MB26_LENGTH()            bfin_read16(CAN1_MB26_LENGTH)
-#define bfin_write_CAN1_MB26_LENGTH(val)        bfin_write16(CAN1_MB26_LENGTH, val)
-#define bfin_read_CAN1_MB26_TIMESTAMP()         bfin_read16(CAN1_MB26_TIMESTAMP)
-#define bfin_write_CAN1_MB26_TIMESTAMP(val)     bfin_write16(CAN1_MB26_TIMESTAMP, val)
-#define bfin_read_CAN1_MB26_ID0()               bfin_read16(CAN1_MB26_ID0)
-#define bfin_write_CAN1_MB26_ID0(val)           bfin_write16(CAN1_MB26_ID0, val)
-#define bfin_read_CAN1_MB26_ID1()               bfin_read16(CAN1_MB26_ID1)
-#define bfin_write_CAN1_MB26_ID1(val)           bfin_write16(CAN1_MB26_ID1, val)
-#define bfin_read_CAN1_MB27_DATA0()             bfin_read16(CAN1_MB27_DATA0)
-#define bfin_write_CAN1_MB27_DATA0(val)         bfin_write16(CAN1_MB27_DATA0, val)
-#define bfin_read_CAN1_MB27_DATA1()             bfin_read16(CAN1_MB27_DATA1)
-#define bfin_write_CAN1_MB27_DATA1(val)         bfin_write16(CAN1_MB27_DATA1, val)
-#define bfin_read_CAN1_MB27_DATA2()             bfin_read16(CAN1_MB27_DATA2)
-#define bfin_write_CAN1_MB27_DATA2(val)         bfin_write16(CAN1_MB27_DATA2, val)
-#define bfin_read_CAN1_MB27_DATA3()             bfin_read16(CAN1_MB27_DATA3)
-#define bfin_write_CAN1_MB27_DATA3(val)         bfin_write16(CAN1_MB27_DATA3, val)
-#define bfin_read_CAN1_MB27_LENGTH()            bfin_read16(CAN1_MB27_LENGTH)
-#define bfin_write_CAN1_MB27_LENGTH(val)        bfin_write16(CAN1_MB27_LENGTH, val)
-#define bfin_read_CAN1_MB27_TIMESTAMP()         bfin_read16(CAN1_MB27_TIMESTAMP)
-#define bfin_write_CAN1_MB27_TIMESTAMP(val)     bfin_write16(CAN1_MB27_TIMESTAMP, val)
-#define bfin_read_CAN1_MB27_ID0()               bfin_read16(CAN1_MB27_ID0)
-#define bfin_write_CAN1_MB27_ID0(val)           bfin_write16(CAN1_MB27_ID0, val)
-#define bfin_read_CAN1_MB27_ID1()               bfin_read16(CAN1_MB27_ID1)
-#define bfin_write_CAN1_MB27_ID1(val)           bfin_write16(CAN1_MB27_ID1, val)
-#define bfin_read_CAN1_MB28_DATA0()             bfin_read16(CAN1_MB28_DATA0)
-#define bfin_write_CAN1_MB28_DATA0(val)         bfin_write16(CAN1_MB28_DATA0, val)
-#define bfin_read_CAN1_MB28_DATA1()             bfin_read16(CAN1_MB28_DATA1)
-#define bfin_write_CAN1_MB28_DATA1(val)         bfin_write16(CAN1_MB28_DATA1, val)
-#define bfin_read_CAN1_MB28_DATA2()             bfin_read16(CAN1_MB28_DATA2)
-#define bfin_write_CAN1_MB28_DATA2(val)         bfin_write16(CAN1_MB28_DATA2, val)
-#define bfin_read_CAN1_MB28_DATA3()             bfin_read16(CAN1_MB28_DATA3)
-#define bfin_write_CAN1_MB28_DATA3(val)         bfin_write16(CAN1_MB28_DATA3, val)
-#define bfin_read_CAN1_MB28_LENGTH()            bfin_read16(CAN1_MB28_LENGTH)
-#define bfin_write_CAN1_MB28_LENGTH(val)        bfin_write16(CAN1_MB28_LENGTH, val)
-#define bfin_read_CAN1_MB28_TIMESTAMP()         bfin_read16(CAN1_MB28_TIMESTAMP)
-#define bfin_write_CAN1_MB28_TIMESTAMP(val)     bfin_write16(CAN1_MB28_TIMESTAMP, val)
-#define bfin_read_CAN1_MB28_ID0()               bfin_read16(CAN1_MB28_ID0)
-#define bfin_write_CAN1_MB28_ID0(val)           bfin_write16(CAN1_MB28_ID0, val)
-#define bfin_read_CAN1_MB28_ID1()               bfin_read16(CAN1_MB28_ID1)
-#define bfin_write_CAN1_MB28_ID1(val)           bfin_write16(CAN1_MB28_ID1, val)
-#define bfin_read_CAN1_MB29_DATA0()             bfin_read16(CAN1_MB29_DATA0)
-#define bfin_write_CAN1_MB29_DATA0(val)         bfin_write16(CAN1_MB29_DATA0, val)
-#define bfin_read_CAN1_MB29_DATA1()             bfin_read16(CAN1_MB29_DATA1)
-#define bfin_write_CAN1_MB29_DATA1(val)         bfin_write16(CAN1_MB29_DATA1, val)
-#define bfin_read_CAN1_MB29_DATA2()             bfin_read16(CAN1_MB29_DATA2)
-#define bfin_write_CAN1_MB29_DATA2(val)         bfin_write16(CAN1_MB29_DATA2, val)
-#define bfin_read_CAN1_MB29_DATA3()             bfin_read16(CAN1_MB29_DATA3)
-#define bfin_write_CAN1_MB29_DATA3(val)         bfin_write16(CAN1_MB29_DATA3, val)
-#define bfin_read_CAN1_MB29_LENGTH()            bfin_read16(CAN1_MB29_LENGTH)
-#define bfin_write_CAN1_MB29_LENGTH(val)        bfin_write16(CAN1_MB29_LENGTH, val)
-#define bfin_read_CAN1_MB29_TIMESTAMP()         bfin_read16(CAN1_MB29_TIMESTAMP)
-#define bfin_write_CAN1_MB29_TIMESTAMP(val)     bfin_write16(CAN1_MB29_TIMESTAMP, val)
-#define bfin_read_CAN1_MB29_ID0()               bfin_read16(CAN1_MB29_ID0)
-#define bfin_write_CAN1_MB29_ID0(val)           bfin_write16(CAN1_MB29_ID0, val)
-#define bfin_read_CAN1_MB29_ID1()               bfin_read16(CAN1_MB29_ID1)
-#define bfin_write_CAN1_MB29_ID1(val)           bfin_write16(CAN1_MB29_ID1, val)
-#define bfin_read_CAN1_MB30_DATA0()             bfin_read16(CAN1_MB30_DATA0)
-#define bfin_write_CAN1_MB30_DATA0(val)         bfin_write16(CAN1_MB30_DATA0, val)
-#define bfin_read_CAN1_MB30_DATA1()             bfin_read16(CAN1_MB30_DATA1)
-#define bfin_write_CAN1_MB30_DATA1(val)         bfin_write16(CAN1_MB30_DATA1, val)
-#define bfin_read_CAN1_MB30_DATA2()             bfin_read16(CAN1_MB30_DATA2)
-#define bfin_write_CAN1_MB30_DATA2(val)         bfin_write16(CAN1_MB30_DATA2, val)
-#define bfin_read_CAN1_MB30_DATA3()             bfin_read16(CAN1_MB30_DATA3)
-#define bfin_write_CAN1_MB30_DATA3(val)         bfin_write16(CAN1_MB30_DATA3, val)
-#define bfin_read_CAN1_MB30_LENGTH()            bfin_read16(CAN1_MB30_LENGTH)
-#define bfin_write_CAN1_MB30_LENGTH(val)        bfin_write16(CAN1_MB30_LENGTH, val)
-#define bfin_read_CAN1_MB30_TIMESTAMP()         bfin_read16(CAN1_MB30_TIMESTAMP)
-#define bfin_write_CAN1_MB30_TIMESTAMP(val)     bfin_write16(CAN1_MB30_TIMESTAMP, val)
-#define bfin_read_CAN1_MB30_ID0()               bfin_read16(CAN1_MB30_ID0)
-#define bfin_write_CAN1_MB30_ID0(val)           bfin_write16(CAN1_MB30_ID0, val)
-#define bfin_read_CAN1_MB30_ID1()               bfin_read16(CAN1_MB30_ID1)
-#define bfin_write_CAN1_MB30_ID1(val)           bfin_write16(CAN1_MB30_ID1, val)
-#define bfin_read_CAN1_MB31_DATA0()             bfin_read16(CAN1_MB31_DATA0)
-#define bfin_write_CAN1_MB31_DATA0(val)         bfin_write16(CAN1_MB31_DATA0, val)
-#define bfin_read_CAN1_MB31_DATA1()             bfin_read16(CAN1_MB31_DATA1)
-#define bfin_write_CAN1_MB31_DATA1(val)         bfin_write16(CAN1_MB31_DATA1, val)
-#define bfin_read_CAN1_MB31_DATA2()             bfin_read16(CAN1_MB31_DATA2)
-#define bfin_write_CAN1_MB31_DATA2(val)         bfin_write16(CAN1_MB31_DATA2, val)
-#define bfin_read_CAN1_MB31_DATA3()             bfin_read16(CAN1_MB31_DATA3)
-#define bfin_write_CAN1_MB31_DATA3(val)         bfin_write16(CAN1_MB31_DATA3, val)
-#define bfin_read_CAN1_MB31_LENGTH()            bfin_read16(CAN1_MB31_LENGTH)
-#define bfin_write_CAN1_MB31_LENGTH(val)        bfin_write16(CAN1_MB31_LENGTH, val)
-#define bfin_read_CAN1_MB31_TIMESTAMP()         bfin_read16(CAN1_MB31_TIMESTAMP)
-#define bfin_write_CAN1_MB31_TIMESTAMP(val)     bfin_write16(CAN1_MB31_TIMESTAMP, val)
-#define bfin_read_CAN1_MB31_ID0()               bfin_read16(CAN1_MB31_ID0)
-#define bfin_write_CAN1_MB31_ID0(val)           bfin_write16(CAN1_MB31_ID0, val)
-#define bfin_read_CAN1_MB31_ID1()               bfin_read16(CAN1_MB31_ID1)
-#define bfin_write_CAN1_MB31_ID1(val)           bfin_write16(CAN1_MB31_ID1, val)
-
-/* ATAPI Registers */
-
-#define bfin_read_ATAPI_CONTROL()               bfin_read16(ATAPI_CONTROL)
-#define bfin_write_ATAPI_CONTROL(val)           bfin_write16(ATAPI_CONTROL, val)
-#define bfin_read_ATAPI_STATUS()                bfin_read16(ATAPI_STATUS)
-#define bfin_write_ATAPI_STATUS(val)            bfin_write16(ATAPI_STATUS, val)
-#define bfin_read_ATAPI_DEV_ADDR()              bfin_read16(ATAPI_DEV_ADDR)
-#define bfin_write_ATAPI_DEV_ADDR(val)          bfin_write16(ATAPI_DEV_ADDR, val)
-#define bfin_read_ATAPI_DEV_TXBUF()             bfin_read16(ATAPI_DEV_TXBUF)
-#define bfin_write_ATAPI_DEV_TXBUF(val)         bfin_write16(ATAPI_DEV_TXBUF, val)
-#define bfin_read_ATAPI_DEV_RXBUF()             bfin_read16(ATAPI_DEV_RXBUF)
-#define bfin_write_ATAPI_DEV_RXBUF(val)         bfin_write16(ATAPI_DEV_RXBUF, val)
-#define bfin_read_ATAPI_INT_MASK()              bfin_read16(ATAPI_INT_MASK)
-#define bfin_write_ATAPI_INT_MASK(val)          bfin_write16(ATAPI_INT_MASK, val)
-#define bfin_read_ATAPI_INT_STATUS()            bfin_read16(ATAPI_INT_STATUS)
-#define bfin_write_ATAPI_INT_STATUS(val)        bfin_write16(ATAPI_INT_STATUS, val)
-#define bfin_read_ATAPI_XFER_LEN()              bfin_read16(ATAPI_XFER_LEN)
-#define bfin_write_ATAPI_XFER_LEN(val)          bfin_write16(ATAPI_XFER_LEN, val)
-#define bfin_read_ATAPI_LINE_STATUS()           bfin_read16(ATAPI_LINE_STATUS)
-#define bfin_write_ATAPI_LINE_STATUS(val)       bfin_write16(ATAPI_LINE_STATUS, val)
-#define bfin_read_ATAPI_SM_STATE()              bfin_read16(ATAPI_SM_STATE)
-#define bfin_write_ATAPI_SM_STATE(val)          bfin_write16(ATAPI_SM_STATE, val)
-#define bfin_read_ATAPI_TERMINATE()             bfin_read16(ATAPI_TERMINATE)
-#define bfin_write_ATAPI_TERMINATE(val)         bfin_write16(ATAPI_TERMINATE, val)
-#define bfin_read_ATAPI_PIO_TFRCNT()            bfin_read16(ATAPI_PIO_TFRCNT)
-#define bfin_write_ATAPI_PIO_TFRCNT(val)        bfin_write16(ATAPI_PIO_TFRCNT, val)
-#define bfin_read_ATAPI_DMA_TFRCNT()            bfin_read16(ATAPI_DMA_TFRCNT)
-#define bfin_write_ATAPI_DMA_TFRCNT(val)        bfin_write16(ATAPI_DMA_TFRCNT, val)
-#define bfin_read_ATAPI_UMAIN_TFRCNT()          bfin_read16(ATAPI_UMAIN_TFRCNT)
-#define bfin_write_ATAPI_UMAIN_TFRCNT(val)      bfin_write16(ATAPI_UMAIN_TFRCNT, val)
-#define bfin_read_ATAPI_UDMAOUT_TFRCNT()        bfin_read16(ATAPI_UDMAOUT_TFRCNT)
-#define bfin_write_ATAPI_UDMAOUT_TFRCNT(val)    bfin_write16(ATAPI_UDMAOUT_TFRCNT, val)
-#define bfin_read_ATAPI_REG_TIM_0()             bfin_read16(ATAPI_REG_TIM_0)
-#define bfin_write_ATAPI_REG_TIM_0(val)         bfin_write16(ATAPI_REG_TIM_0, val)
-#define bfin_read_ATAPI_PIO_TIM_0()             bfin_read16(ATAPI_PIO_TIM_0)
-#define bfin_write_ATAPI_PIO_TIM_0(val)         bfin_write16(ATAPI_PIO_TIM_0, val)
-#define bfin_read_ATAPI_PIO_TIM_1()             bfin_read16(ATAPI_PIO_TIM_1)
-#define bfin_write_ATAPI_PIO_TIM_1(val)         bfin_write16(ATAPI_PIO_TIM_1, val)
-#define bfin_read_ATAPI_MULTI_TIM_0()           bfin_read16(ATAPI_MULTI_TIM_0)
-#define bfin_write_ATAPI_MULTI_TIM_0(val)       bfin_write16(ATAPI_MULTI_TIM_0, val)
-#define bfin_read_ATAPI_MULTI_TIM_1()           bfin_read16(ATAPI_MULTI_TIM_1)
-#define bfin_write_ATAPI_MULTI_TIM_1(val)       bfin_write16(ATAPI_MULTI_TIM_1, val)
-#define bfin_read_ATAPI_MULTI_TIM_2()           bfin_read16(ATAPI_MULTI_TIM_2)
-#define bfin_write_ATAPI_MULTI_TIM_2(val)       bfin_write16(ATAPI_MULTI_TIM_2, val)
-#define bfin_read_ATAPI_ULTRA_TIM_0()           bfin_read16(ATAPI_ULTRA_TIM_0)
-#define bfin_write_ATAPI_ULTRA_TIM_0(val)       bfin_write16(ATAPI_ULTRA_TIM_0, val)
-#define bfin_read_ATAPI_ULTRA_TIM_1()           bfin_read16(ATAPI_ULTRA_TIM_1)
-#define bfin_write_ATAPI_ULTRA_TIM_1(val)       bfin_write16(ATAPI_ULTRA_TIM_1, val)
-#define bfin_read_ATAPI_ULTRA_TIM_2()           bfin_read16(ATAPI_ULTRA_TIM_2)
-#define bfin_write_ATAPI_ULTRA_TIM_2(val)       bfin_write16(ATAPI_ULTRA_TIM_2, val)
-#define bfin_read_ATAPI_ULTRA_TIM_3()           bfin_read16(ATAPI_ULTRA_TIM_3)
-#define bfin_write_ATAPI_ULTRA_TIM_3(val)       bfin_write16(ATAPI_ULTRA_TIM_3, val)
-
-/* SDH Registers */
-
-#define bfin_read_SDH_PWR_CTL()         bfin_read16(SDH_PWR_CTL)
-#define bfin_write_SDH_PWR_CTL(val)     bfin_write16(SDH_PWR_CTL, val)
-#define bfin_read_SDH_CLK_CTL()         bfin_read16(SDH_CLK_CTL)
-#define bfin_write_SDH_CLK_CTL(val)     bfin_write16(SDH_CLK_CTL, val)
-#define bfin_read_SDH_ARGUMENT()        bfin_read32(SDH_ARGUMENT)
-#define bfin_write_SDH_ARGUMENT(val)    bfin_write32(SDH_ARGUMENT, val)
-#define bfin_read_SDH_COMMAND()         bfin_read16(SDH_COMMAND)
-#define bfin_write_SDH_COMMAND(val)     bfin_write16(SDH_COMMAND, val)
-#define bfin_read_SDH_RESP_CMD()        bfin_read16(SDH_RESP_CMD)
-#define bfin_write_SDH_RESP_CMD(val)    bfin_write16(SDH_RESP_CMD, val)
-#define bfin_read_SDH_RESPONSE0()       bfin_read32(SDH_RESPONSE0)
-#define bfin_write_SDH_RESPONSE0(val)   bfin_write32(SDH_RESPONSE0, val)
-#define bfin_read_SDH_RESPONSE1()       bfin_read32(SDH_RESPONSE1)
-#define bfin_write_SDH_RESPONSE1(val)   bfin_write32(SDH_RESPONSE1, val)
-#define bfin_read_SDH_RESPONSE2()       bfin_read32(SDH_RESPONSE2)
-#define bfin_write_SDH_RESPONSE2(val)   bfin_write32(SDH_RESPONSE2, val)
-#define bfin_read_SDH_RESPONSE3()       bfin_read32(SDH_RESPONSE3)
-#define bfin_write_SDH_RESPONSE3(val)   bfin_write32(SDH_RESPONSE3, val)
-#define bfin_read_SDH_DATA_TIMER()      bfin_read32(SDH_DATA_TIMER)
-#define bfin_write_SDH_DATA_TIMER(val)  bfin_write32(SDH_DATA_TIMER, val)
-#define bfin_read_SDH_DATA_LGTH()       bfin_read16(SDH_DATA_LGTH)
-#define bfin_write_SDH_DATA_LGTH(val)   bfin_write16(SDH_DATA_LGTH, val)
-#define bfin_read_SDH_DATA_CTL()        bfin_read16(SDH_DATA_CTL)
-#define bfin_write_SDH_DATA_CTL(val)    bfin_write16(SDH_DATA_CTL, val)
-#define bfin_read_SDH_DATA_CNT()        bfin_read16(SDH_DATA_CNT)
-#define bfin_write_SDH_DATA_CNT(val)    bfin_write16(SDH_DATA_CNT, val)
-#define bfin_read_SDH_STATUS()          bfin_read32(SDH_STATUS)
-#define bfin_write_SDH_STATUS(val)      bfin_write32(SDH_STATUS, val)
-#define bfin_read_SDH_STATUS_CLR()      bfin_read16(SDH_STATUS_CLR)
-#define bfin_write_SDH_STATUS_CLR(val)  bfin_write16(SDH_STATUS_CLR, val)
-#define bfin_read_SDH_MASK0()           bfin_read32(SDH_MASK0)
-#define bfin_write_SDH_MASK0(val)       bfin_write32(SDH_MASK0, val)
-#define bfin_read_SDH_MASK1()           bfin_read32(SDH_MASK1)
-#define bfin_write_SDH_MASK1(val)       bfin_write32(SDH_MASK1, val)
-#define bfin_read_SDH_FIFO_CNT()        bfin_read16(SDH_FIFO_CNT)
-#define bfin_write_SDH_FIFO_CNT(val)    bfin_write16(SDH_FIFO_CNT, val)
-#define bfin_read_SDH_FIFO()            bfin_read32(SDH_FIFO)
-#define bfin_write_SDH_FIFO(val)        bfin_write32(SDH_FIFO, val)
-#define bfin_read_SDH_E_STATUS()        bfin_read16(SDH_E_STATUS)
-#define bfin_write_SDH_E_STATUS(val)    bfin_write16(SDH_E_STATUS, val)
-#define bfin_read_SDH_E_MASK()          bfin_read16(SDH_E_MASK)
-#define bfin_write_SDH_E_MASK(val)      bfin_write16(SDH_E_MASK, val)
-#define bfin_read_SDH_CFG()             bfin_read16(SDH_CFG)
-#define bfin_write_SDH_CFG(val)         bfin_write16(SDH_CFG, val)
-#define bfin_read_SDH_RD_WAIT_EN()      bfin_read16(SDH_RD_WAIT_EN)
-#define bfin_write_SDH_RD_WAIT_EN(val)  bfin_write16(SDH_RD_WAIT_EN, val)
-#define bfin_read_SDH_PID0()            bfin_read16(SDH_PID0)
-#define bfin_write_SDH_PID0(val)        bfin_write16(SDH_PID0, val)
-#define bfin_read_SDH_PID1()            bfin_read16(SDH_PID1)
-#define bfin_write_SDH_PID1(val)        bfin_write16(SDH_PID1, val)
-#define bfin_read_SDH_PID2()            bfin_read16(SDH_PID2)
-#define bfin_write_SDH_PID2(val)        bfin_write16(SDH_PID2, val)
-#define bfin_read_SDH_PID3()            bfin_read16(SDH_PID3)
-#define bfin_write_SDH_PID3(val)        bfin_write16(SDH_PID3, val)
-#define bfin_read_SDH_PID4()            bfin_read16(SDH_PID4)
-#define bfin_write_SDH_PID4(val)        bfin_write16(SDH_PID4, val)
-#define bfin_read_SDH_PID5()            bfin_read16(SDH_PID5)
-#define bfin_write_SDH_PID5(val)        bfin_write16(SDH_PID5, val)
-#define bfin_read_SDH_PID6()            bfin_read16(SDH_PID6)
-#define bfin_write_SDH_PID6(val)        bfin_write16(SDH_PID6, val)
-#define bfin_read_SDH_PID7()            bfin_read16(SDH_PID7)
-#define bfin_write_SDH_PID7(val)        bfin_write16(SDH_PID7, val)
-
-/* HOST Port Registers */
-
-#define bfin_read_HOST_CONTROL()        bfin_read16(HOST_CONTROL)
-#define bfin_write_HOST_CONTROL(val)    bfin_write16(HOST_CONTROL, val)
-#define bfin_read_HOST_STATUS()         bfin_read16(HOST_STATUS)
-#define bfin_write_HOST_STATUS(val)     bfin_write16(HOST_STATUS, val)
-#define bfin_read_HOST_TIMEOUT()        bfin_read16(HOST_TIMEOUT)
-#define bfin_write_HOST_TIMEOUT(val)    bfin_write16(HOST_TIMEOUT, val)
-
-/* USB Control Registers */
-
-#define bfin_read_USB_FADDR()           bfin_read16(USB_FADDR)
-#define bfin_write_USB_FADDR(val)       bfin_write16(USB_FADDR, val)
-#define bfin_read_USB_POWER()           bfin_read16(USB_POWER)
-#define bfin_write_USB_POWER(val)       bfin_write16(USB_POWER, val)
-#define bfin_read_USB_INTRTX()          bfin_read16(USB_INTRTX)
-#define bfin_write_USB_INTRTX(val)      bfin_write16(USB_INTRTX, val)
-#define bfin_read_USB_INTRRX()          bfin_read16(USB_INTRRX)
-#define bfin_write_USB_INTRRX(val)      bfin_write16(USB_INTRRX, val)
-#define bfin_read_USB_INTRTXE()         bfin_read16(USB_INTRTXE)
-#define bfin_write_USB_INTRTXE(val)     bfin_write16(USB_INTRTXE, val)
-#define bfin_read_USB_INTRRXE()         bfin_read16(USB_INTRRXE)
-#define bfin_write_USB_INTRRXE(val)     bfin_write16(USB_INTRRXE, val)
-#define bfin_read_USB_INTRUSB()         bfin_read16(USB_INTRUSB)
-#define bfin_write_USB_INTRUSB(val)     bfin_write16(USB_INTRUSB, val)
-#define bfin_read_USB_INTRUSBE()        bfin_read16(USB_INTRUSBE)
-#define bfin_write_USB_INTRUSBE(val)    bfin_write16(USB_INTRUSBE, val)
-#define bfin_read_USB_FRAME()           bfin_read16(USB_FRAME)
-#define bfin_write_USB_FRAME(val)       bfin_write16(USB_FRAME, val)
-#define bfin_read_USB_INDEX()           bfin_read16(USB_INDEX)
-#define bfin_write_USB_INDEX(val)       bfin_write16(USB_INDEX, val)
-#define bfin_read_USB_TESTMODE()        bfin_read16(USB_TESTMODE)
-#define bfin_write_USB_TESTMODE(val)    bfin_write16(USB_TESTMODE, val)
-#define bfin_read_USB_GLOBINTR()        bfin_read16(USB_GLOBINTR)
-#define bfin_write_USB_GLOBINTR(val)    bfin_write16(USB_GLOBINTR, val)
-#define bfin_read_USB_GLOBAL_CTL()      bfin_read16(USB_GLOBAL_CTL)
-#define bfin_write_USB_GLOBAL_CTL(val)  bfin_write16(USB_GLOBAL_CTL, val)
-
-/* USB Packet Control Registers */
-
-#define bfin_read_USB_TX_MAX_PACKET()           bfin_read16(USB_TX_MAX_PACKET)
-#define bfin_write_USB_TX_MAX_PACKET(val)       bfin_write16(USB_TX_MAX_PACKET, val)
-#define bfin_read_USB_CSR0()                    bfin_read16(USB_CSR0)
-#define bfin_write_USB_CSR0(val)                bfin_write16(USB_CSR0, val)
-#define bfin_read_USB_TXCSR()                   bfin_read16(USB_TXCSR)
-#define bfin_write_USB_TXCSR(val)               bfin_write16(USB_TXCSR, val)
-#define bfin_read_USB_RX_MAX_PACKET()           bfin_read16(USB_RX_MAX_PACKET)
-#define bfin_write_USB_RX_MAX_PACKET(val)       bfin_write16(USB_RX_MAX_PACKET, val)
-#define bfin_read_USB_RXCSR()                   bfin_read16(USB_RXCSR)
-#define bfin_write_USB_RXCSR(val)               bfin_write16(USB_RXCSR, val)
-#define bfin_read_USB_COUNT0()                  bfin_read16(USB_COUNT0)
-#define bfin_write_USB_COUNT0(val)              bfin_write16(USB_COUNT0, val)
-#define bfin_read_USB_RXCOUNT()                 bfin_read16(USB_RXCOUNT)
-#define bfin_write_USB_RXCOUNT(val)             bfin_write16(USB_RXCOUNT, val)
-#define bfin_read_USB_TXTYPE()                  bfin_read16(USB_TXTYPE)
-#define bfin_write_USB_TXTYPE(val)              bfin_write16(USB_TXTYPE, val)
-#define bfin_read_USB_NAKLIMIT0()               bfin_read16(USB_NAKLIMIT0)
-#define bfin_write_USB_NAKLIMIT0(val)           bfin_write16(USB_NAKLIMIT0, val)
-#define bfin_read_USB_TXINTERVAL()              bfin_read16(USB_TXINTERVAL)
-#define bfin_write_USB_TXINTERVAL(val)          bfin_write16(USB_TXINTERVAL, val)
-#define bfin_read_USB_RXTYPE()                  bfin_read16(USB_RXTYPE)
-#define bfin_write_USB_RXTYPE(val)              bfin_write16(USB_RXTYPE, val)
-#define bfin_read_USB_RXINTERVAL()              bfin_read16(USB_RXINTERVAL)
-#define bfin_write_USB_RXINTERVAL(val)          bfin_write16(USB_RXINTERVAL, val)
-#define bfin_read_USB_TXCOUNT()                 bfin_read16(USB_TXCOUNT)
-#define bfin_write_USB_TXCOUNT(val)             bfin_write16(USB_TXCOUNT, val)
-
-/* USB Endbfin_read_()oint FIFO Registers */
-
-#define bfin_read_USB_EP0_FIFO()                bfin_read16(USB_EP0_FIFO)
-#define bfin_write_USB_EP0_FIFO(val)            bfin_write16(USB_EP0_FIFO, val)
-#define bfin_read_USB_EP1_FIFO()                bfin_read16(USB_EP1_FIFO)
-#define bfin_write_USB_EP1_FIFO(val)            bfin_write16(USB_EP1_FIFO, val)
-#define bfin_read_USB_EP2_FIFO()                bfin_read16(USB_EP2_FIFO)
-#define bfin_write_USB_EP2_FIFO(val)            bfin_write16(USB_EP2_FIFO, val)
-#define bfin_read_USB_EP3_FIFO()                bfin_read16(USB_EP3_FIFO)
-#define bfin_write_USB_EP3_FIFO(val)            bfin_write16(USB_EP3_FIFO, val)
-#define bfin_read_USB_EP4_FIFO()                bfin_read16(USB_EP4_FIFO)
-#define bfin_write_USB_EP4_FIFO(val)            bfin_write16(USB_EP4_FIFO, val)
-#define bfin_read_USB_EP5_FIFO()                bfin_read16(USB_EP5_FIFO)
-#define bfin_write_USB_EP5_FIFO(val)            bfin_write16(USB_EP5_FIFO, val)
-#define bfin_read_USB_EP6_FIFO()                bfin_read16(USB_EP6_FIFO)
-#define bfin_write_USB_EP6_FIFO(val)            bfin_write16(USB_EP6_FIFO, val)
-#define bfin_read_USB_EP7_FIFO()                bfin_read16(USB_EP7_FIFO)
-#define bfin_write_USB_EP7_FIFO(val)            bfin_write16(USB_EP7_FIFO, val)
-
-/* USB OTG Control Registers */
-
-#define bfin_read_USB_OTG_DEV_CTL()             bfin_read16(USB_OTG_DEV_CTL)
-#define bfin_write_USB_OTG_DEV_CTL(val)         bfin_write16(USB_OTG_DEV_CTL, val)
-#define bfin_read_USB_OTG_VBUS_IRQ()            bfin_read16(USB_OTG_VBUS_IRQ)
-#define bfin_write_USB_OTG_VBUS_IRQ(val)        bfin_write16(USB_OTG_VBUS_IRQ, val)
-#define bfin_read_USB_OTG_VBUS_MASK()           bfin_read16(USB_OTG_VBUS_MASK)
-#define bfin_write_USB_OTG_VBUS_MASK(val)       bfin_write16(USB_OTG_VBUS_MASK, val)
-
-/* USB Phy Control Registers */
-
-#define bfin_read_USB_LINKINFO()                bfin_read16(USB_LINKINFO)
-#define bfin_write_USB_LINKINFO(val)            bfin_write16(USB_LINKINFO, val)
-#define bfin_read_USB_VPLEN()                   bfin_read16(USB_VPLEN)
-#define bfin_write_USB_VPLEN(val)               bfin_write16(USB_VPLEN, val)
-#define bfin_read_USB_HS_EOF1()                 bfin_read16(USB_HS_EOF1)
-#define bfin_write_USB_HS_EOF1(val)             bfin_write16(USB_HS_EOF1, val)
-#define bfin_read_USB_FS_EOF1()                 bfin_read16(USB_FS_EOF1)
-#define bfin_write_USB_FS_EOF1(val)             bfin_write16(USB_FS_EOF1, val)
-#define bfin_read_USB_LS_EOF1()                 bfin_read16(USB_LS_EOF1)
-#define bfin_write_USB_LS_EOF1(val)             bfin_write16(USB_LS_EOF1, val)
-
-/* (APHY_CNTRL is for ADI usage only) */
-
-#define bfin_read_USB_APHY_CNTRL()              bfin_read16(USB_APHY_CNTRL)
-#define bfin_write_USB_APHY_CNTRL(val)          bfin_write16(USB_APHY_CNTRL, val)
-
-/* (APHY_CALIB is for ADI usage only) */
-
-#define bfin_read_USB_APHY_CALIB()              bfin_read16(USB_APHY_CALIB)
-#define bfin_write_USB_APHY_CALIB(val)          bfin_write16(USB_APHY_CALIB, val)
-#define bfin_read_USB_APHY_CNTRL2()             bfin_read16(USB_APHY_CNTRL2)
-#define bfin_write_USB_APHY_CNTRL2(val)         bfin_write16(USB_APHY_CNTRL2, val)
-
-/* (PHY_TEST is for ADI usage only) */
-
-#define bfin_read_USB_PHY_TEST()                bfin_read16(USB_PHY_TEST)
-#define bfin_write_USB_PHY_TEST(val)            bfin_write16(USB_PHY_TEST, val)
-#define bfin_read_USB_PLLOSC_CTRL()             bfin_read16(USB_PLLOSC_CTRL)
-#define bfin_write_USB_PLLOSC_CTRL(val)         bfin_write16(USB_PLLOSC_CTRL, val)
-#define bfin_read_USB_SRP_CLKDIV()              bfin_read16(USB_SRP_CLKDIV)
-#define bfin_write_USB_SRP_CLKDIV(val)          bfin_write16(USB_SRP_CLKDIV, val)
-
-/* USB Endbfin_read_()oint 0 Control Registers */
-
-#define bfin_read_USB_EP_NI0_TXMAXP()           bfin_read16(USB_EP_NI0_TXMAXP)
-#define bfin_write_USB_EP_NI0_TXMAXP(val)       bfin_write16(USB_EP_NI0_TXMAXP, val)
-#define bfin_read_USB_EP_NI0_TXCSR()            bfin_read16(USB_EP_NI0_TXCSR)
-#define bfin_write_USB_EP_NI0_TXCSR(val)        bfin_write16(USB_EP_NI0_TXCSR, val)
-#define bfin_read_USB_EP_NI0_RXMAXP()           bfin_read16(USB_EP_NI0_RXMAXP)
-#define bfin_write_USB_EP_NI0_RXMAXP(val)       bfin_write16(USB_EP_NI0_RXMAXP, val)
-#define bfin_read_USB_EP_NI0_RXCSR()            bfin_read16(USB_EP_NI0_RXCSR)
-#define bfin_write_USB_EP_NI0_RXCSR(val)        bfin_write16(USB_EP_NI0_RXCSR, val)
-#define bfin_read_USB_EP_NI0_RXCOUNT()          bfin_read16(USB_EP_NI0_RXCOUNT)
-#define bfin_write_USB_EP_NI0_RXCOUNT(val)      bfin_write16(USB_EP_NI0_RXCOUNT, val)
-#define bfin_read_USB_EP_NI0_TXTYPE()           bfin_read16(USB_EP_NI0_TXTYPE)
-#define bfin_write_USB_EP_NI0_TXTYPE(val)       bfin_write16(USB_EP_NI0_TXTYPE, val)
-#define bfin_read_USB_EP_NI0_TXINTERVAL()       bfin_read16(USB_EP_NI0_TXINTERVAL)
-#define bfin_write_USB_EP_NI0_TXINTERVAL(val)   bfin_write16(USB_EP_NI0_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI0_RXTYPE()           bfin_read16(USB_EP_NI0_RXTYPE)
-#define bfin_write_USB_EP_NI0_RXTYPE(val)       bfin_write16(USB_EP_NI0_RXTYPE, val)
-#define bfin_read_USB_EP_NI0_RXINTERVAL()       bfin_read16(USB_EP_NI0_RXINTERVAL)
-#define bfin_write_USB_EP_NI0_RXINTERVAL(val)   bfin_write16(USB_EP_NI0_RXINTERVAL, val)
-
-/* USB Endbfin_read_()oint 1 Control Registers */
-
-#define bfin_read_USB_EP_NI0_TXCOUNT()          bfin_read16(USB_EP_NI0_TXCOUNT)
-#define bfin_write_USB_EP_NI0_TXCOUNT(val)      bfin_write16(USB_EP_NI0_TXCOUNT, val)
-#define bfin_read_USB_EP_NI1_TXMAXP()           bfin_read16(USB_EP_NI1_TXMAXP)
-#define bfin_write_USB_EP_NI1_TXMAXP(val)       bfin_write16(USB_EP_NI1_TXMAXP, val)
-#define bfin_read_USB_EP_NI1_TXCSR()            bfin_read16(USB_EP_NI1_TXCSR)
-#define bfin_write_USB_EP_NI1_TXCSR(val)        bfin_write16(USB_EP_NI1_TXCSR, val)
-#define bfin_read_USB_EP_NI1_RXMAXP()           bfin_read16(USB_EP_NI1_RXMAXP)
-#define bfin_write_USB_EP_NI1_RXMAXP(val)       bfin_write16(USB_EP_NI1_RXMAXP, val)
-#define bfin_read_USB_EP_NI1_RXCSR()            bfin_read16(USB_EP_NI1_RXCSR)
-#define bfin_write_USB_EP_NI1_RXCSR(val)        bfin_write16(USB_EP_NI1_RXCSR, val)
-#define bfin_read_USB_EP_NI1_RXCOUNT()          bfin_read16(USB_EP_NI1_RXCOUNT)
-#define bfin_write_USB_EP_NI1_RXCOUNT(val)      bfin_write16(USB_EP_NI1_RXCOUNT, val)
-#define bfin_read_USB_EP_NI1_TXTYPE()           bfin_read16(USB_EP_NI1_TXTYPE)
-#define bfin_write_USB_EP_NI1_TXTYPE(val)       bfin_write16(USB_EP_NI1_TXTYPE, val)
-#define bfin_read_USB_EP_NI1_TXINTERVAL()       bfin_read16(USB_EP_NI1_TXINTERVAL)
-#define bfin_write_USB_EP_NI1_TXINTERVAL(val)   bfin_write16(USB_EP_NI1_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI1_RXTYPE()           bfin_read16(USB_EP_NI1_RXTYPE)
-#define bfin_write_USB_EP_NI1_RXTYPE(val)       bfin_write16(USB_EP_NI1_RXTYPE, val)
-#define bfin_read_USB_EP_NI1_RXINTERVAL()       bfin_read16(USB_EP_NI1_RXINTERVAL)
-#define bfin_write_USB_EP_NI1_RXINTERVAL(val)   bfin_write16(USB_EP_NI1_RXINTERVAL, val)
-
-/* USB Endbfin_read_()oint 2 Control Registers */
-
-#define bfin_read_USB_EP_NI1_TXCOUNT()          bfin_read16(USB_EP_NI1_TXCOUNT)
-#define bfin_write_USB_EP_NI1_TXCOUNT(val)      bfin_write16(USB_EP_NI1_TXCOUNT, val)
-#define bfin_read_USB_EP_NI2_TXMAXP()           bfin_read16(USB_EP_NI2_TXMAXP)
-#define bfin_write_USB_EP_NI2_TXMAXP(val)       bfin_write16(USB_EP_NI2_TXMAXP, val)
-#define bfin_read_USB_EP_NI2_TXCSR()            bfin_read16(USB_EP_NI2_TXCSR)
-#define bfin_write_USB_EP_NI2_TXCSR(val)        bfin_write16(USB_EP_NI2_TXCSR, val)
-#define bfin_read_USB_EP_NI2_RXMAXP()           bfin_read16(USB_EP_NI2_RXMAXP)
-#define bfin_write_USB_EP_NI2_RXMAXP(val)       bfin_write16(USB_EP_NI2_RXMAXP, val)
-#define bfin_read_USB_EP_NI2_RXCSR()            bfin_read16(USB_EP_NI2_RXCSR)
-#define bfin_write_USB_EP_NI2_RXCSR(val)        bfin_write16(USB_EP_NI2_RXCSR, val)
-#define bfin_read_USB_EP_NI2_RXCOUNT()          bfin_read16(USB_EP_NI2_RXCOUNT)
-#define bfin_write_USB_EP_NI2_RXCOUNT(val)      bfin_write16(USB_EP_NI2_RXCOUNT, val)
-#define bfin_read_USB_EP_NI2_TXTYPE()           bfin_read16(USB_EP_NI2_TXTYPE)
-#define bfin_write_USB_EP_NI2_TXTYPE(val)       bfin_write16(USB_EP_NI2_TXTYPE, val)
-#define bfin_read_USB_EP_NI2_TXINTERVAL()       bfin_read16(USB_EP_NI2_TXINTERVAL)
-#define bfin_write_USB_EP_NI2_TXINTERVAL(val)   bfin_write16(USB_EP_NI2_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI2_RXTYPE()           bfin_read16(USB_EP_NI2_RXTYPE)
-#define bfin_write_USB_EP_NI2_RXTYPE(val)       bfin_write16(USB_EP_NI2_RXTYPE, val)
-#define bfin_read_USB_EP_NI2_RXINTERVAL()       bfin_read16(USB_EP_NI2_RXINTERVAL)
-#define bfin_write_USB_EP_NI2_RXINTERVAL(val)   bfin_write16(USB_EP_NI2_RXINTERVAL, val)
-
-/* USB Endbfin_read_()oint 3 Control Registers */
-
-#define bfin_read_USB_EP_NI2_TXCOUNT()          bfin_read16(USB_EP_NI2_TXCOUNT)
-#define bfin_write_USB_EP_NI2_TXCOUNT(val)      bfin_write16(USB_EP_NI2_TXCOUNT, val)
-#define bfin_read_USB_EP_NI3_TXMAXP()           bfin_read16(USB_EP_NI3_TXMAXP)
-#define bfin_write_USB_EP_NI3_TXMAXP(val)       bfin_write16(USB_EP_NI3_TXMAXP, val)
-#define bfin_read_USB_EP_NI3_TXCSR()            bfin_read16(USB_EP_NI3_TXCSR)
-#define bfin_write_USB_EP_NI3_TXCSR(val)        bfin_write16(USB_EP_NI3_TXCSR, val)
-#define bfin_read_USB_EP_NI3_RXMAXP()           bfin_read16(USB_EP_NI3_RXMAXP)
-#define bfin_write_USB_EP_NI3_RXMAXP(val)       bfin_write16(USB_EP_NI3_RXMAXP, val)
-#define bfin_read_USB_EP_NI3_RXCSR()            bfin_read16(USB_EP_NI3_RXCSR)
-#define bfin_write_USB_EP_NI3_RXCSR(val)        bfin_write16(USB_EP_NI3_RXCSR, val)
-#define bfin_read_USB_EP_NI3_RXCOUNT()          bfin_read16(USB_EP_NI3_RXCOUNT)
-#define bfin_write_USB_EP_NI3_RXCOUNT(val)      bfin_write16(USB_EP_NI3_RXCOUNT, val)
-#define bfin_read_USB_EP_NI3_TXTYPE()           bfin_read16(USB_EP_NI3_TXTYPE)
-#define bfin_write_USB_EP_NI3_TXTYPE(val)       bfin_write16(USB_EP_NI3_TXTYPE, val)
-#define bfin_read_USB_EP_NI3_TXINTERVAL()       bfin_read16(USB_EP_NI3_TXINTERVAL)
-#define bfin_write_USB_EP_NI3_TXINTERVAL(val)   bfin_write16(USB_EP_NI3_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI3_RXTYPE()           bfin_read16(USB_EP_NI3_RXTYPE)
-#define bfin_write_USB_EP_NI3_RXTYPE(val)       bfin_write16(USB_EP_NI3_RXTYPE, val)
-#define bfin_read_USB_EP_NI3_RXINTERVAL()       bfin_read16(USB_EP_NI3_RXINTERVAL)
-#define bfin_write_USB_EP_NI3_RXINTERVAL(val)   bfin_write16(USB_EP_NI3_RXINTERVAL, val)
-
-/* USB Endbfin_read_()oint 4 Control Registers */
-
-#define bfin_read_USB_EP_NI3_TXCOUNT()          bfin_read16(USB_EP_NI3_TXCOUNT)
-#define bfin_write_USB_EP_NI3_TXCOUNT(val)      bfin_write16(USB_EP_NI3_TXCOUNT, val)
-#define bfin_read_USB_EP_NI4_TXMAXP()           bfin_read16(USB_EP_NI4_TXMAXP)
-#define bfin_write_USB_EP_NI4_TXMAXP(val)       bfin_write16(USB_EP_NI4_TXMAXP, val)
-#define bfin_read_USB_EP_NI4_TXCSR()            bfin_read16(USB_EP_NI4_TXCSR)
-#define bfin_write_USB_EP_NI4_TXCSR(val)        bfin_write16(USB_EP_NI4_TXCSR, val)
-#define bfin_read_USB_EP_NI4_RXMAXP()           bfin_read16(USB_EP_NI4_RXMAXP)
-#define bfin_write_USB_EP_NI4_RXMAXP(val)       bfin_write16(USB_EP_NI4_RXMAXP, val)
-#define bfin_read_USB_EP_NI4_RXCSR()            bfin_read16(USB_EP_NI4_RXCSR)
-#define bfin_write_USB_EP_NI4_RXCSR(val)        bfin_write16(USB_EP_NI4_RXCSR, val)
-#define bfin_read_USB_EP_NI4_RXCOUNT()          bfin_read16(USB_EP_NI4_RXCOUNT)
-#define bfin_write_USB_EP_NI4_RXCOUNT(val)      bfin_write16(USB_EP_NI4_RXCOUNT, val)
-#define bfin_read_USB_EP_NI4_TXTYPE()           bfin_read16(USB_EP_NI4_TXTYPE)
-#define bfin_write_USB_EP_NI4_TXTYPE(val)       bfin_write16(USB_EP_NI4_TXTYPE, val)
-#define bfin_read_USB_EP_NI4_TXINTERVAL()       bfin_read16(USB_EP_NI4_TXINTERVAL)
-#define bfin_write_USB_EP_NI4_TXINTERVAL(val)   bfin_write16(USB_EP_NI4_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI4_RXTYPE()           bfin_read16(USB_EP_NI4_RXTYPE)
-#define bfin_write_USB_EP_NI4_RXTYPE(val)       bfin_write16(USB_EP_NI4_RXTYPE, val)
-#define bfin_read_USB_EP_NI4_RXINTERVAL()       bfin_read16(USB_EP_NI4_RXINTERVAL)
-#define bfin_write_USB_EP_NI4_RXINTERVAL(val)   bfin_write16(USB_EP_NI4_RXINTERVAL, val)
-
-/* USB Endbfin_read_()oint 5 Control Registers */
-
-#define bfin_read_USB_EP_NI4_TXCOUNT()          bfin_read16(USB_EP_NI4_TXCOUNT)
-#define bfin_write_USB_EP_NI4_TXCOUNT(val)      bfin_write16(USB_EP_NI4_TXCOUNT, val)
-#define bfin_read_USB_EP_NI5_TXMAXP()           bfin_read16(USB_EP_NI5_TXMAXP)
-#define bfin_write_USB_EP_NI5_TXMAXP(val)       bfin_write16(USB_EP_NI5_TXMAXP, val)
-#define bfin_read_USB_EP_NI5_TXCSR()            bfin_read16(USB_EP_NI5_TXCSR)
-#define bfin_write_USB_EP_NI5_TXCSR(val)        bfin_write16(USB_EP_NI5_TXCSR, val)
-#define bfin_read_USB_EP_NI5_RXMAXP()           bfin_read16(USB_EP_NI5_RXMAXP)
-#define bfin_write_USB_EP_NI5_RXMAXP(val)       bfin_write16(USB_EP_NI5_RXMAXP, val)
-#define bfin_read_USB_EP_NI5_RXCSR()            bfin_read16(USB_EP_NI5_RXCSR)
-#define bfin_write_USB_EP_NI5_RXCSR(val)        bfin_write16(USB_EP_NI5_RXCSR, val)
-#define bfin_read_USB_EP_NI5_RXCOUNT()          bfin_read16(USB_EP_NI5_RXCOUNT)
-#define bfin_write_USB_EP_NI5_RXCOUNT(val)      bfin_write16(USB_EP_NI5_RXCOUNT, val)
-#define bfin_read_USB_EP_NI5_TXTYPE()           bfin_read16(USB_EP_NI5_TXTYPE)
-#define bfin_write_USB_EP_NI5_TXTYPE(val)       bfin_write16(USB_EP_NI5_TXTYPE, val)
-#define bfin_read_USB_EP_NI5_TXINTERVAL()       bfin_read16(USB_EP_NI5_TXINTERVAL)
-#define bfin_write_USB_EP_NI5_TXINTERVAL(val)   bfin_write16(USB_EP_NI5_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI5_RXTYPE()           bfin_read16(USB_EP_NI5_RXTYPE)
-#define bfin_write_USB_EP_NI5_RXTYPE(val)       bfin_write16(USB_EP_NI5_RXTYPE, val)
-#define bfin_read_USB_EP_NI5_RXINTERVAL()       bfin_read16(USB_EP_NI5_RXINTERVAL)
-#define bfin_write_USB_EP_NI5_RXINTERVAL(val)   bfin_write16(USB_EP_NI5_RXINTERVAL, val)
-
-/* USB Endbfin_read_()oint 6 Control Registers */
-
-#define bfin_read_USB_EP_NI5_TXCOUNT()          bfin_read16(USB_EP_NI5_TXCOUNT)
-#define bfin_write_USB_EP_NI5_TXCOUNT(val)      bfin_write16(USB_EP_NI5_TXCOUNT, val)
-#define bfin_read_USB_EP_NI6_TXMAXP()           bfin_read16(USB_EP_NI6_TXMAXP)
-#define bfin_write_USB_EP_NI6_TXMAXP(val)       bfin_write16(USB_EP_NI6_TXMAXP, val)
-#define bfin_read_USB_EP_NI6_TXCSR()            bfin_read16(USB_EP_NI6_TXCSR)
-#define bfin_write_USB_EP_NI6_TXCSR(val)        bfin_write16(USB_EP_NI6_TXCSR, val)
-#define bfin_read_USB_EP_NI6_RXMAXP()           bfin_read16(USB_EP_NI6_RXMAXP)
-#define bfin_write_USB_EP_NI6_RXMAXP(val)       bfin_write16(USB_EP_NI6_RXMAXP, val)
-#define bfin_read_USB_EP_NI6_RXCSR()            bfin_read16(USB_EP_NI6_RXCSR)
-#define bfin_write_USB_EP_NI6_RXCSR(val)        bfin_write16(USB_EP_NI6_RXCSR, val)
-#define bfin_read_USB_EP_NI6_RXCOUNT()          bfin_read16(USB_EP_NI6_RXCOUNT)
-#define bfin_write_USB_EP_NI6_RXCOUNT(val)      bfin_write16(USB_EP_NI6_RXCOUNT, val)
-#define bfin_read_USB_EP_NI6_TXTYPE()           bfin_read16(USB_EP_NI6_TXTYPE)
-#define bfin_write_USB_EP_NI6_TXTYPE(val)       bfin_write16(USB_EP_NI6_TXTYPE, val)
-#define bfin_read_USB_EP_NI6_TXINTERVAL()       bfin_read16(USB_EP_NI6_TXINTERVAL)
-#define bfin_write_USB_EP_NI6_TXINTERVAL(val)   bfin_write16(USB_EP_NI6_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI6_RXTYPE()           bfin_read16(USB_EP_NI6_RXTYPE)
-#define bfin_write_USB_EP_NI6_RXTYPE(val)       bfin_write16(USB_EP_NI6_RXTYPE, val)
-#define bfin_read_USB_EP_NI6_RXINTERVAL()       bfin_read16(USB_EP_NI6_RXINTERVAL)
-#define bfin_write_USB_EP_NI6_RXINTERVAL(val)   bfin_write16(USB_EP_NI6_RXINTERVAL, val)
-
-/* USB Endbfin_read_()oint 7 Control Registers */
-
-#define bfin_read_USB_EP_NI6_TXCOUNT()          bfin_read16(USB_EP_NI6_TXCOUNT)
-#define bfin_write_USB_EP_NI6_TXCOUNT(val)      bfin_write16(USB_EP_NI6_TXCOUNT, val)
-#define bfin_read_USB_EP_NI7_TXMAXP()           bfin_read16(USB_EP_NI7_TXMAXP)
-#define bfin_write_USB_EP_NI7_TXMAXP(val)       bfin_write16(USB_EP_NI7_TXMAXP, val)
-#define bfin_read_USB_EP_NI7_TXCSR()            bfin_read16(USB_EP_NI7_TXCSR)
-#define bfin_write_USB_EP_NI7_TXCSR(val)        bfin_write16(USB_EP_NI7_TXCSR, val)
-#define bfin_read_USB_EP_NI7_RXMAXP()           bfin_read16(USB_EP_NI7_RXMAXP)
-#define bfin_write_USB_EP_NI7_RXMAXP(val)       bfin_write16(USB_EP_NI7_RXMAXP, val)
-#define bfin_read_USB_EP_NI7_RXCSR()            bfin_read16(USB_EP_NI7_RXCSR)
-#define bfin_write_USB_EP_NI7_RXCSR(val)        bfin_write16(USB_EP_NI7_RXCSR, val)
-#define bfin_read_USB_EP_NI7_RXCOUNT()          bfin_read16(USB_EP_NI7_RXCOUNT)
-#define bfin_write_USB_EP_NI7_RXCOUNT(val)      bfin_write16(USB_EP_NI7_RXCOUNT, val)
-#define bfin_read_USB_EP_NI7_TXTYPE()           bfin_read16(USB_EP_NI7_TXTYPE)
-#define bfin_write_USB_EP_NI7_TXTYPE(val)       bfin_write16(USB_EP_NI7_TXTYPE, val)
-#define bfin_read_USB_EP_NI7_TXINTERVAL()       bfin_read16(USB_EP_NI7_TXINTERVAL)
-#define bfin_write_USB_EP_NI7_TXINTERVAL(val)   bfin_write16(USB_EP_NI7_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI7_RXTYPE()           bfin_read16(USB_EP_NI7_RXTYPE)
-#define bfin_write_USB_EP_NI7_RXTYPE(val)       bfin_write16(USB_EP_NI7_RXTYPE, val)
-#define bfin_read_USB_EP_NI7_RXINTERVAL()       bfin_read16(USB_EP_NI7_RXINTERVAL)
-#define bfin_write_USB_EP_NI7_RXINTERVAL(val)   bfin_write16(USB_EP_NI7_RXINTERVAL, val)
-#define bfin_read_USB_EP_NI7_TXCOUNT()          bfin_read16(USB_EP_NI7_TXCOUNT)
-#define bfin_write_USB_EP_NI7_TXCOUNT(val)      bfin_write16(USB_EP_NI7_TXCOUNT, val)
-#define bfin_read_USB_DMA_INTERRUPT()           bfin_read16(USB_DMA_INTERRUPT)
-#define bfin_write_USB_DMA_INTERRUPT(val)       bfin_write16(USB_DMA_INTERRUPT, val)
-
-/* USB Channel 0 Config Registers */
-
-#define bfin_read_USB_DMA0CONTROL()             bfin_read16(USB_DMA0CONTROL)
-#define bfin_write_USB_DMA0CONTROL(val)         bfin_write16(USB_DMA0CONTROL, val)
-#define bfin_read_USB_DMA0ADDRLOW()             bfin_read16(USB_DMA0ADDRLOW)
-#define bfin_write_USB_DMA0ADDRLOW(val)         bfin_write16(USB_DMA0ADDRLOW, val)
-#define bfin_read_USB_DMA0ADDRHIGH()            bfin_read16(USB_DMA0ADDRHIGH)
-#define bfin_write_USB_DMA0ADDRHIGH(val)        bfin_write16(USB_DMA0ADDRHIGH, val)
-#define bfin_read_USB_DMA0COUNTLOW()            bfin_read16(USB_DMA0COUNTLOW)
-#define bfin_write_USB_DMA0COUNTLOW(val)        bfin_write16(USB_DMA0COUNTLOW, val)
-#define bfin_read_USB_DMA0COUNTHIGH()           bfin_read16(USB_DMA0COUNTHIGH)
-#define bfin_write_USB_DMA0COUNTHIGH(val)       bfin_write16(USB_DMA0COUNTHIGH, val)
-
-/* USB Channel 1 Config Registers */
-
-#define bfin_read_USB_DMA1CONTROL()             bfin_read16(USB_DMA1CONTROL)
-#define bfin_write_USB_DMA1CONTROL(val)         bfin_write16(USB_DMA1CONTROL, val)
-#define bfin_read_USB_DMA1ADDRLOW()             bfin_read16(USB_DMA1ADDRLOW)
-#define bfin_write_USB_DMA1ADDRLOW(val)         bfin_write16(USB_DMA1ADDRLOW, val)
-#define bfin_read_USB_DMA1ADDRHIGH()            bfin_read16(USB_DMA1ADDRHIGH)
-#define bfin_write_USB_DMA1ADDRHIGH(val)        bfin_write16(USB_DMA1ADDRHIGH, val)
-#define bfin_read_USB_DMA1COUNTLOW()            bfin_read16(USB_DMA1COUNTLOW)
-#define bfin_write_USB_DMA1COUNTLOW(val)        bfin_write16(USB_DMA1COUNTLOW, val)
-#define bfin_read_USB_DMA1COUNTHIGH()           bfin_read16(USB_DMA1COUNTHIGH)
-#define bfin_write_USB_DMA1COUNTHIGH(val)       bfin_write16(USB_DMA1COUNTHIGH, val)
-
-/* USB Channel 2 Config Registers */
-
-#define bfin_read_USB_DMA2CONTROL()             bfin_read16(USB_DMA2CONTROL)
-#define bfin_write_USB_DMA2CONTROL(val)         bfin_write16(USB_DMA2CONTROL, val)
-#define bfin_read_USB_DMA2ADDRLOW()             bfin_read16(USB_DMA2ADDRLOW)
-#define bfin_write_USB_DMA2ADDRLOW(val)         bfin_write16(USB_DMA2ADDRLOW, val)
-#define bfin_read_USB_DMA2ADDRHIGH()            bfin_read16(USB_DMA2ADDRHIGH)
-#define bfin_write_USB_DMA2ADDRHIGH(val)        bfin_write16(USB_DMA2ADDRHIGH, val)
-#define bfin_read_USB_DMA2COUNTLOW()            bfin_read16(USB_DMA2COUNTLOW)
-#define bfin_write_USB_DMA2COUNTLOW(val)        bfin_write16(USB_DMA2COUNTLOW, val)
-#define bfin_read_USB_DMA2COUNTHIGH()           bfin_read16(USB_DMA2COUNTHIGH)
-#define bfin_write_USB_DMA2COUNTHIGH(val)       bfin_write16(USB_DMA2COUNTHIGH, val)
-
-/* USB Channel 3 Config Registers */
-
-#define bfin_read_USB_DMA3CONTROL()             bfin_read16(USB_DMA3CONTROL)
-#define bfin_write_USB_DMA3CONTROL(val)         bfin_write16(USB_DMA3CONTROL, val)
-#define bfin_read_USB_DMA3ADDRLOW()             bfin_read16(USB_DMA3ADDRLOW)
-#define bfin_write_USB_DMA3ADDRLOW(val)         bfin_write16(USB_DMA3ADDRLOW, val)
-#define bfin_read_USB_DMA3ADDRHIGH()            bfin_read16(USB_DMA3ADDRHIGH)
-#define bfin_write_USB_DMA3ADDRHIGH(val)        bfin_write16(USB_DMA3ADDRHIGH, val)
-#define bfin_read_USB_DMA3COUNTLOW()            bfin_read16(USB_DMA3COUNTLOW)
-#define bfin_write_USB_DMA3COUNTLOW(val)        bfin_write16(USB_DMA3COUNTLOW, val)
-#define bfin_read_USB_DMA3COUNTHIGH()           bfin_read16(USB_DMA3COUNTHIGH)
-#define bfin_write_USB_DMA3COUNTHIGH(val)       bfin_write16(USB_DMA3COUNTHIGH, val)
-
-/* USB Channel 4 Config Registers */
-
-#define bfin_read_USB_DMA4CONTROL()             bfin_read16(USB_DMA4CONTROL)
-#define bfin_write_USB_DMA4CONTROL(val)         bfin_write16(USB_DMA4CONTROL, val)
-#define bfin_read_USB_DMA4ADDRLOW()             bfin_read16(USB_DMA4ADDRLOW)
-#define bfin_write_USB_DMA4ADDRLOW(val)         bfin_write16(USB_DMA4ADDRLOW, val)
-#define bfin_read_USB_DMA4ADDRHIGH()            bfin_read16(USB_DMA4ADDRHIGH)
-#define bfin_write_USB_DMA4ADDRHIGH(val)        bfin_write16(USB_DMA4ADDRHIGH, val)
-#define bfin_read_USB_DMA4COUNTLOW()            bfin_read16(USB_DMA4COUNTLOW)
-#define bfin_write_USB_DMA4COUNTLOW(val)        bfin_write16(USB_DMA4COUNTLOW, val)
-#define bfin_read_USB_DMA4COUNTHIGH()           bfin_read16(USB_DMA4COUNTHIGH)
-#define bfin_write_USB_DMA4COUNTHIGH(val)       bfin_write16(USB_DMA4COUNTHIGH, val)
-
-/* USB Channel 5 Config Registers */
-
-#define bfin_read_USB_DMA5CONTROL()             bfin_read16(USB_DMA5CONTROL)
-#define bfin_write_USB_DMA5CONTROL(val)         bfin_write16(USB_DMA5CONTROL, val)
-#define bfin_read_USB_DMA5ADDRLOW()             bfin_read16(USB_DMA5ADDRLOW)
-#define bfin_write_USB_DMA5ADDRLOW(val)         bfin_write16(USB_DMA5ADDRLOW, val)
-#define bfin_read_USB_DMA5ADDRHIGH()            bfin_read16(USB_DMA5ADDRHIGH)
-#define bfin_write_USB_DMA5ADDRHIGH(val)                bfin_write16(USB_DMA5ADDRHIGH, val)
-#define bfin_read_USB_DMA5COUNTLOW()            bfin_read16(USB_DMA5COUNTLOW)
-#define bfin_write_USB_DMA5COUNTLOW(val)        bfin_write16(USB_DMA5COUNTLOW, val)
-#define bfin_read_USB_DMA5COUNTHIGH()           bfin_read16(USB_DMA5COUNTHIGH)
-#define bfin_write_USB_DMA5COUNTHIGH(val)       bfin_write16(USB_DMA5COUNTHIGH, val)
-
-/* USB Channel 6 Config Registers */
-
-#define bfin_read_USB_DMA6CONTROL()             bfin_read16(USB_DMA6CONTROL)
-#define bfin_write_USB_DMA6CONTROL(val)         bfin_write16(USB_DMA6CONTROL, val)
-#define bfin_read_USB_DMA6ADDRLOW()             bfin_read16(USB_DMA6ADDRLOW)
-#define bfin_write_USB_DMA6ADDRLOW(val)         bfin_write16(USB_DMA6ADDRLOW, val)
-#define bfin_read_USB_DMA6ADDRHIGH()            bfin_read16(USB_DMA6ADDRHIGH)
-#define bfin_write_USB_DMA6ADDRHIGH(val)        bfin_write16(USB_DMA6ADDRHIGH, val)
-#define bfin_read_USB_DMA6COUNTLOW()            bfin_read16(USB_DMA6COUNTLOW)
-#define bfin_write_USB_DMA6COUNTLOW(val)        bfin_write16(USB_DMA6COUNTLOW, val)
-#define bfin_read_USB_DMA6COUNTHIGH()           bfin_read16(USB_DMA6COUNTHIGH)
-#define bfin_write_USB_DMA6COUNTHIGH(val)       bfin_write16(USB_DMA6COUNTHIGH, val)
-
-/* USB Channel 7 Config Registers */
-
-#define bfin_read_USB_DMA7CONTROL()             bfin_read16(USB_DMA7CONTROL)
-#define bfin_write_USB_DMA7CONTROL(val)         bfin_write16(USB_DMA7CONTROL, val)
-#define bfin_read_USB_DMA7ADDRLOW()             bfin_read16(USB_DMA7ADDRLOW)
-#define bfin_write_USB_DMA7ADDRLOW(val)         bfin_write16(USB_DMA7ADDRLOW, val)
-#define bfin_read_USB_DMA7ADDRHIGH()            bfin_read16(USB_DMA7ADDRHIGH)
-#define bfin_write_USB_DMA7ADDRHIGH(val)        bfin_write16(USB_DMA7ADDRHIGH, val)
-#define bfin_read_USB_DMA7COUNTLOW()            bfin_read16(USB_DMA7COUNTLOW)
-#define bfin_write_USB_DMA7COUNTLOW(val)        bfin_write16(USB_DMA7COUNTLOW, val)
-#define bfin_read_USB_DMA7COUNTHIGH()           bfin_read16(USB_DMA7COUNTHIGH)
-#define bfin_write_USB_DMA7COUNTHIGH(val)       bfin_write16(USB_DMA7COUNTHIGH, val)
-
-/* Keybfin_read_()ad Registers */
-
-#define bfin_read_KPAD_CTL()            bfin_read16(KPAD_CTL)
-#define bfin_write_KPAD_CTL(val)        bfin_write16(KPAD_CTL, val)
-#define bfin_read_KPAD_PRESCALE()       bfin_read16(KPAD_PRESCALE)
-#define bfin_write_KPAD_PRESCALE(val)   bfin_write16(KPAD_PRESCALE, val)
-#define bfin_read_KPAD_MSEL()           bfin_read16(KPAD_MSEL)
-#define bfin_write_KPAD_MSEL(val)       bfin_write16(KPAD_MSEL, val)
-#define bfin_read_KPAD_ROWCOL()         bfin_read16(KPAD_ROWCOL)
-#define bfin_write_KPAD_ROWCOL(val)     bfin_write16(KPAD_ROWCOL, val)
-#define bfin_read_KPAD_STAT()           bfin_read16(KPAD_STAT)
-#define bfin_write_KPAD_STAT(val)       bfin_write16(KPAD_STAT, val)
-#define bfin_read_KPAD_SOFTEVAL()       bfin_read16(KPAD_SOFTEVAL)
-#define bfin_write_KPAD_SOFTEVAL(val)   bfin_write16(KPAD_SOFTEVAL, val)
-
-/* Pixel Combfin_read_()ositor (PIXC) Registers */
-
-#define bfin_read_PIXC_CTL()            bfin_read16(PIXC_CTL)
-#define bfin_write_PIXC_CTL(val)        bfin_write16(PIXC_CTL, val)
-#define bfin_read_PIXC_PPL()            bfin_read16(PIXC_PPL)
-#define bfin_write_PIXC_PPL(val)        bfin_write16(PIXC_PPL, val)
-#define bfin_read_PIXC_LPF()            bfin_read16(PIXC_LPF)
-#define bfin_write_PIXC_LPF(val)        bfin_write16(PIXC_LPF, val)
-#define bfin_read_PIXC_AHSTART()        bfin_read16(PIXC_AHSTART)
-#define bfin_write_PIXC_AHSTART(val)    bfin_write16(PIXC_AHSTART, val)
-#define bfin_read_PIXC_AHEND()          bfin_read16(PIXC_AHEND)
-#define bfin_write_PIXC_AHEND(val)      bfin_write16(PIXC_AHEND, val)
-#define bfin_read_PIXC_AVSTART()        bfin_read16(PIXC_AVSTART)
-#define bfin_write_PIXC_AVSTART(val)    bfin_write16(PIXC_AVSTART, val)
-#define bfin_read_PIXC_AVEND()          bfin_read16(PIXC_AVEND)
-#define bfin_write_PIXC_AVEND(val)      bfin_write16(PIXC_AVEND, val)
-#define bfin_read_PIXC_ATRANSP()        bfin_read16(PIXC_ATRANSP)
-#define bfin_write_PIXC_ATRANSP(val)    bfin_write16(PIXC_ATRANSP, val)
-#define bfin_read_PIXC_BHSTART()        bfin_read16(PIXC_BHSTART)
-#define bfin_write_PIXC_BHSTART(val)    bfin_write16(PIXC_BHSTART, val)
-#define bfin_read_PIXC_BHEND()          bfin_read16(PIXC_BHEND)
-#define bfin_write_PIXC_BHEND(val)      bfin_write16(PIXC_BHEND, val)
-#define bfin_read_PIXC_BVSTART()        bfin_read16(PIXC_BVSTART)
-#define bfin_write_PIXC_BVSTART(val)    bfin_write16(PIXC_BVSTART, val)
-#define bfin_read_PIXC_BVEND()          bfin_read16(PIXC_BVEND)
-#define bfin_write_PIXC_BVEND(val)      bfin_write16(PIXC_BVEND, val)
-#define bfin_read_PIXC_BTRANSP()        bfin_read16(PIXC_BTRANSP)
-#define bfin_write_PIXC_BTRANSP(val)    bfin_write16(PIXC_BTRANSP, val)
-#define bfin_read_PIXC_INTRSTAT()       bfin_read16(PIXC_INTRSTAT)
-#define bfin_write_PIXC_INTRSTAT(val)   bfin_write16(PIXC_INTRSTAT, val)
-#define bfin_read_PIXC_RYCON()          bfin_read32(PIXC_RYCON)
-#define bfin_write_PIXC_RYCON(val)      bfin_write32(PIXC_RYCON, val)
-#define bfin_read_PIXC_GUCON()          bfin_read32(PIXC_GUCON)
-#define bfin_write_PIXC_GUCON(val)      bfin_write32(PIXC_GUCON, val)
-#define bfin_read_PIXC_BVCON()          bfin_read32(PIXC_BVCON)
-#define bfin_write_PIXC_BVCON(val)      bfin_write32(PIXC_BVCON, val)
-#define bfin_read_PIXC_CCBIAS()         bfin_read32(PIXC_CCBIAS)
-#define bfin_write_PIXC_CCBIAS(val)     bfin_write32(PIXC_CCBIAS, val)
-#define bfin_read_PIXC_TC()             bfin_read32(PIXC_TC)
-#define bfin_write_PIXC_TC(val)         bfin_write32(PIXC_TC, val)
-
-/* Handshake MDMA 0 Registers */
-
-#define bfin_read_HMDMA0_CONTROL()              bfin_read16(HMDMA0_CONTROL)
-#define bfin_write_HMDMA0_CONTROL(val)          bfin_write16(HMDMA0_CONTROL, val)
-#define bfin_read_HMDMA0_ECINIT()               bfin_read16(HMDMA0_ECINIT)
-#define bfin_write_HMDMA0_ECINIT(val)           bfin_write16(HMDMA0_ECINIT, val)
-#define bfin_read_HMDMA0_BCINIT()               bfin_read16(HMDMA0_BCINIT)
-#define bfin_write_HMDMA0_BCINIT(val)           bfin_write16(HMDMA0_BCINIT, val)
-#define bfin_read_HMDMA0_ECURGENT()             bfin_read16(HMDMA0_ECURGENT)
-#define bfin_write_HMDMA0_ECURGENT(val)         bfin_write16(HMDMA0_ECURGENT, val)
-#define bfin_read_HMDMA0_ECOVERFLOW()           bfin_read16(HMDMA0_ECOVERFLOW)
-#define bfin_write_HMDMA0_ECOVERFLOW(val)       bfin_write16(HMDMA0_ECOVERFLOW, val)
-#define bfin_read_HMDMA0_ECOUNT()               bfin_read16(HMDMA0_ECOUNT)
-#define bfin_write_HMDMA0_ECOUNT(val)           bfin_write16(HMDMA0_ECOUNT, val)
-#define bfin_read_HMDMA0_BCOUNT()               bfin_read16(HMDMA0_BCOUNT)
-#define bfin_write_HMDMA0_BCOUNT(val)           bfin_write16(HMDMA0_BCOUNT, val)
-
-/* Handshake MDMA 1 Registers */
-
-#define bfin_read_HMDMA1_CONTROL()              bfin_read16(HMDMA1_CONTROL)
-#define bfin_write_HMDMA1_CONTROL(val)          bfin_write16(HMDMA1_CONTROL, val)
-#define bfin_read_HMDMA1_ECINIT()               bfin_read16(HMDMA1_ECINIT)
-#define bfin_write_HMDMA1_ECINIT(val)           bfin_write16(HMDMA1_ECINIT, val)
-#define bfin_read_HMDMA1_BCINIT()               bfin_read16(HMDMA1_BCINIT)
-#define bfin_write_HMDMA1_BCINIT(val)           bfin_write16(HMDMA1_BCINIT, val)
-#define bfin_read_HMDMA1_ECURGENT()             bfin_read16(HMDMA1_ECURGENT)
-#define bfin_write_HMDMA1_ECURGENT(val)         bfin_write16(HMDMA1_ECURGENT, val)
-#define bfin_read_HMDMA1_ECOVERFLOW()           bfin_read16(HMDMA1_ECOVERFLOW)
-#define bfin_write_HMDMA1_ECOVERFLOW(val)       bfin_write16(HMDMA1_ECOVERFLOW, val)
-#define bfin_read_HMDMA1_ECOUNT()               bfin_read16(HMDMA1_ECOUNT)
-#define bfin_write_HMDMA1_ECOUNT(val)           bfin_write16(HMDMA1_ECOUNT, val)
-#define bfin_read_HMDMA1_BCOUNT()               bfin_read16(HMDMA1_BCOUNT)
-#define bfin_write_HMDMA1_BCOUNT(val)           bfin_write16(HMDMA1_BCOUNT, val)
-
 #endif /* _CDEF_BF549_H */
diff --git a/arch/blackfin/mach-bf548/include/mach/cdefBF54x_base.h b/arch/blackfin/mach-bf548/include/mach/cdefBF54x_base.h
index a2e9d9849eba..32f71e6a7c15 100644
--- a/arch/blackfin/mach-bf548/include/mach/cdefBF54x_base.h
+++ b/arch/blackfin/mach-bf548/include/mach/cdefBF54x_base.h
@@ -2615,17 +2615,6 @@
 #define bfin_read_CNT_MIN()             bfin_read32(CNT_MIN)
 #define bfin_write_CNT_MIN(val)         bfin_write32(CNT_MIN, val)
 
-/* OTP/FUSE Registers */
-
-#define bfin_read_OTP_CONTROL()         bfin_read16(OTP_CONTROL)
-#define bfin_write_OTP_CONTROL(val)     bfin_write16(OTP_CONTROL, val)
-#define bfin_read_OTP_BEN()             bfin_read16(OTP_BEN)
-#define bfin_write_OTP_BEN(val)         bfin_write16(OTP_BEN, val)
-#define bfin_read_OTP_STATUS()          bfin_read16(OTP_STATUS)
-#define bfin_write_OTP_STATUS(val)      bfin_write16(OTP_STATUS, val)
-#define bfin_read_OTP_TIMING()          bfin_read32(OTP_TIMING)
-#define bfin_write_OTP_TIMING(val)      bfin_write32(OTP_TIMING, val)
-
 /* Security Registers */
 
 #define bfin_read_SECURE_SYSSWT()       bfin_read32(SECURE_SYSSWT)
@@ -2640,17 +2629,6 @@
 #define bfin_read_DMAC1_PERIMUX()       bfin_read16(DMAC1_PERIMUX)
 #define bfin_write_DMAC1_PERIMUX(val)   bfin_write16(DMAC1_PERIMUX, val)
 
-/* OTP Read/Write Data Buffer Registers */
-
-#define bfin_read_OTP_DATA0()           bfin_read32(OTP_DATA0)
-#define bfin_write_OTP_DATA0(val)       bfin_write32(OTP_DATA0, val)
-#define bfin_read_OTP_DATA1()           bfin_read32(OTP_DATA1)
-#define bfin_write_OTP_DATA1(val)       bfin_write32(OTP_DATA1, val)
-#define bfin_read_OTP_DATA2()           bfin_read32(OTP_DATA2)
-#define bfin_write_OTP_DATA2(val)       bfin_write32(OTP_DATA2, val)
-#define bfin_read_OTP_DATA3()           bfin_read32(OTP_DATA3)
-#define bfin_write_OTP_DATA3(val)       bfin_write32(OTP_DATA3, val)
-
 /* Handshake MDMA is not defined in the shared file because it is not available on the ADSP-BF542 bfin_read_()rocessor */
 
 /* legacy definitions */
diff --git a/arch/blackfin/mach-bf548/include/mach/defBF544.h b/arch/blackfin/mach-bf548/include/mach/defBF544.h
index 39f588dcd382..f916c52a148a 100644
--- a/arch/blackfin/mach-bf548/include/mach/defBF544.h
+++ b/arch/blackfin/mach-bf548/include/mach/defBF544.h
@@ -624,9 +624,9 @@
 #define                 DMA_READY  0x1        /* DMA Ready */
 #define                  FIFOFULL  0x2        /* FIFO Full */
 #define                 FIFOEMPTY  0x4        /* FIFO Empty */
-#define                  COMPLETE  0x8        /* DMA Complete */
+#define              DMA_COMPLETE  0x8        /* DMA Complete */
 #define                      HSHK  0x10       /* Host Handshake */
-#define                   TIMEOUT  0x20       /* Host Timeout */
+#define                 HSTIMEOUT  0x20       /* Host Timeout */
 #define                      HIRQ  0x40       /* Host Interrupt Request */
 #define                ALLOW_CNFG  0x80       /* Allow New Configuration */
 #define                   DMA_DIR  0x100      /* DMA Direction */
diff --git a/arch/blackfin/mach-bf548/include/mach/defBF547.h b/arch/blackfin/mach-bf548/include/mach/defBF547.h
index c4dcf302d9f5..72c343646b2a 100644
--- a/arch/blackfin/mach-bf548/include/mach/defBF547.h
+++ b/arch/blackfin/mach-bf548/include/mach/defBF547.h
@@ -4,18 +4,18 @@
  * Licensed under the ADI BSD license or the GPL-2 (or later)
  */
 
-#ifndef _DEF_BF548_H
-#define _DEF_BF548_H
+#ifndef _DEF_BF547_H
+#define _DEF_BF547_H
 
 /* Include all Core registers and bit definitions */
 #include <asm/def_LPBlackfin.h>
 
-/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF548 */
+/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF547 */
 
 /* Include defBF54x_base.h for the set of #defines that are common to all ADSP-BF54x processors */
 #include "defBF54x_base.h"
 
-/* The following are the #defines needed by ADSP-BF548 that are not in the common header */
+/* The following are the #defines needed by ADSP-BF547 that are not in the common header */
 
 /* Timer Registers */
 
@@ -1217,4 +1217,4 @@
 /* ******************************************* */
 
 
-#endif /* _DEF_BF548_H */
+#endif /* _DEF_BF547_H */
diff --git a/arch/blackfin/mach-bf548/include/mach/defBF548.h b/arch/blackfin/mach-bf548/include/mach/defBF548.h
index a5079980968c..3fb33b040ab7 100644
--- a/arch/blackfin/mach-bf548/include/mach/defBF548.h
+++ b/arch/blackfin/mach-bf548/include/mach/defBF548.h
@@ -15,115 +15,8 @@
 /* Include defBF54x_base.h for the set of #defines that are common to all ADSP-BF54x processors */
 #include "defBF54x_base.h"
 
-/* The following are the #defines needed by ADSP-BF548 that are not in the common header */
-
-/* Timer Registers */
-
-#define                    TIMER8_CONFIG  0xffc00600   /* Timer 8 Configuration Register */
-#define                   TIMER8_COUNTER  0xffc00604   /* Timer 8 Counter Register */
-#define                    TIMER8_PERIOD  0xffc00608   /* Timer 8 Period Register */
-#define                     TIMER8_WIDTH  0xffc0060c   /* Timer 8 Width Register */
-#define                    TIMER9_CONFIG  0xffc00610   /* Timer 9 Configuration Register */
-#define                   TIMER9_COUNTER  0xffc00614   /* Timer 9 Counter Register */
-#define                    TIMER9_PERIOD  0xffc00618   /* Timer 9 Period Register */
-#define                     TIMER9_WIDTH  0xffc0061c   /* Timer 9 Width Register */
-#define                   TIMER10_CONFIG  0xffc00620   /* Timer 10 Configuration Register */
-#define                  TIMER10_COUNTER  0xffc00624   /* Timer 10 Counter Register */
-#define                   TIMER10_PERIOD  0xffc00628   /* Timer 10 Period Register */
-#define                    TIMER10_WIDTH  0xffc0062c   /* Timer 10 Width Register */
-
-/* Timer Group of 3 Registers */
-
-#define                    TIMER_ENABLE1  0xffc00640   /* Timer Group of 3 Enable Register */
-#define                   TIMER_DISABLE1  0xffc00644   /* Timer Group of 3 Disable Register */
-#define                    TIMER_STATUS1  0xffc00648   /* Timer Group of 3 Status Register */
-
-/* SPORT0 Registers */
-
-#define                      SPORT0_TCR1  0xffc00800   /* SPORT0 Transmit Configuration 1 Register */
-#define                      SPORT0_TCR2  0xffc00804   /* SPORT0 Transmit Configuration 2 Register */
-#define                   SPORT0_TCLKDIV  0xffc00808   /* SPORT0 Transmit Serial Clock Divider Register */
-#define                    SPORT0_TFSDIV  0xffc0080c   /* SPORT0 Transmit Frame Sync Divider Register */
-#define                        SPORT0_TX  0xffc00810   /* SPORT0 Transmit Data Register */
-#define                        SPORT0_RX  0xffc00818   /* SPORT0 Receive Data Register */
-#define                      SPORT0_RCR1  0xffc00820   /* SPORT0 Receive Configuration 1 Register */
-#define                      SPORT0_RCR2  0xffc00824   /* SPORT0 Receive Configuration 2 Register */
-#define                   SPORT0_RCLKDIV  0xffc00828   /* SPORT0 Receive Serial Clock Divider Register */
-#define                    SPORT0_RFSDIV  0xffc0082c   /* SPORT0 Receive Frame Sync Divider Register */
-#define                      SPORT0_STAT  0xffc00830   /* SPORT0 Status Register */
-#define                      SPORT0_CHNL  0xffc00834   /* SPORT0 Current Channel Register */
-#define                     SPORT0_MCMC1  0xffc00838   /* SPORT0 Multi channel Configuration Register 1 */
-#define                     SPORT0_MCMC2  0xffc0083c   /* SPORT0 Multi channel Configuration Register 2 */
-#define                     SPORT0_MTCS0  0xffc00840   /* SPORT0 Multi channel Transmit Select Register 0 */
-#define                     SPORT0_MTCS1  0xffc00844   /* SPORT0 Multi channel Transmit Select Register 1 */
-#define                     SPORT0_MTCS2  0xffc00848   /* SPORT0 Multi channel Transmit Select Register 2 */
-#define                     SPORT0_MTCS3  0xffc0084c   /* SPORT0 Multi channel Transmit Select Register 3 */
-#define                     SPORT0_MRCS0  0xffc00850   /* SPORT0 Multi channel Receive Select Register 0 */
-#define                     SPORT0_MRCS1  0xffc00854   /* SPORT0 Multi channel Receive Select Register 1 */
-#define                     SPORT0_MRCS2  0xffc00858   /* SPORT0 Multi channel Receive Select Register 2 */
-#define                     SPORT0_MRCS3  0xffc0085c   /* SPORT0 Multi channel Receive Select Register 3 */
-
-/* EPPI0 Registers */
-
-#define                     EPPI0_STATUS  0xffc01000   /* EPPI0 Status Register */
-#define                     EPPI0_HCOUNT  0xffc01004   /* EPPI0 Horizontal Transfer Count Register */
-#define                     EPPI0_HDELAY  0xffc01008   /* EPPI0 Horizontal Delay Count Register */
-#define                     EPPI0_VCOUNT  0xffc0100c   /* EPPI0 Vertical Transfer Count Register */
-#define                     EPPI0_VDELAY  0xffc01010   /* EPPI0 Vertical Delay Count Register */
-#define                      EPPI0_FRAME  0xffc01014   /* EPPI0 Lines per Frame Register */
-#define                       EPPI0_LINE  0xffc01018   /* EPPI0 Samples per Line Register */
-#define                     EPPI0_CLKDIV  0xffc0101c   /* EPPI0 Clock Divide Register */
-#define                    EPPI0_CONTROL  0xffc01020   /* EPPI0 Control Register */
-#define                   EPPI0_FS1W_HBL  0xffc01024   /* EPPI0 FS1 Width Register / EPPI0 Horizontal Blanking Samples Per Line Register */
-#define                  EPPI0_FS1P_AVPL  0xffc01028   /* EPPI0 FS1 Period Register / EPPI0 Active Video Samples Per Line Register */
-#define                   EPPI0_FS2W_LVB  0xffc0102c   /* EPPI0 FS2 Width Register / EPPI0 Lines of Vertical Blanking Register */
-#define                  EPPI0_FS2P_LAVF  0xffc01030   /* EPPI0 FS2 Period Register/ EPPI0 Lines of Active Video Per Field Register */
-#define                       EPPI0_CLIP  0xffc01034   /* EPPI0 Clipping Register */
-
-/* UART2 Registers */
-
-#define                        UART2_DLL  0xffc02100   /* Divisor Latch Low Byte */
-#define                        UART2_DLH  0xffc02104   /* Divisor Latch High Byte */
-#define                       UART2_GCTL  0xffc02108   /* Global Control Register */
-#define                        UART2_LCR  0xffc0210c   /* Line Control Register */
-#define                        UART2_MCR  0xffc02110   /* Modem Control Register */
-#define                        UART2_LSR  0xffc02114   /* Line Status Register */
-#define                        UART2_MSR  0xffc02118   /* Modem Status Register */
-#define                        UART2_SCR  0xffc0211c   /* Scratch Register */
-#define                    UART2_IER_SET  0xffc02120   /* Interrupt Enable Register Set */
-#define                  UART2_IER_CLEAR  0xffc02124   /* Interrupt Enable Register Clear */
-#define                        UART2_RBR  0xffc0212c   /* Receive Buffer Register */
-
-/* Two Wire Interface Registers (TWI1) */
-
-#define                     TWI1_REGBASE  0xffc02200
-#define                      TWI1_CLKDIV  0xffc02200   /* Clock Divider Register */
-#define                     TWI1_CONTROL  0xffc02204   /* TWI Control Register */
-#define                  TWI1_SLAVE_CTRL  0xffc02208   /* TWI Slave Mode Control Register */
-#define                  TWI1_SLAVE_STAT  0xffc0220c   /* TWI Slave Mode Status Register */
-#define                  TWI1_SLAVE_ADDR  0xffc02210   /* TWI Slave Mode Address Register */
-#define                 TWI1_MASTER_CTRL  0xffc02214   /* TWI Master Mode Control Register */
-#define                 TWI1_MASTER_STAT  0xffc02218   /* TWI Master Mode Status Register */
-#define                 TWI1_MASTER_ADDR  0xffc0221c   /* TWI Master Mode Address Register */
-#define                    TWI1_INT_STAT  0xffc02220   /* TWI Interrupt Status Register */
-#define                    TWI1_INT_MASK  0xffc02224   /* TWI Interrupt Mask Register */
-#define                   TWI1_FIFO_CTRL  0xffc02228   /* TWI FIFO Control Register */
-#define                   TWI1_FIFO_STAT  0xffc0222c   /* TWI FIFO Status Register */
-#define                   TWI1_XMT_DATA8  0xffc02280   /* TWI FIFO Transmit Data Single Byte Register */
-#define                  TWI1_XMT_DATA16  0xffc02284   /* TWI FIFO Transmit Data Double Byte Register */
-#define                   TWI1_RCV_DATA8  0xffc02288   /* TWI FIFO Receive Data Single Byte Register */
-#define                  TWI1_RCV_DATA16  0xffc0228c   /* TWI FIFO Receive Data Double Byte Register */
-
-/* SPI2  Registers */
-
-#define                     SPI2_REGBASE  0xffc02400
-#define                         SPI2_CTL  0xffc02400   /* SPI2 Control Register */
-#define                         SPI2_FLG  0xffc02404   /* SPI2 Flag Register */
-#define                        SPI2_STAT  0xffc02408   /* SPI2 Status Register */
-#define                        SPI2_TDBR  0xffc0240c   /* SPI2 Transmit Data Buffer Register */
-#define                        SPI2_RDBR  0xffc02410   /* SPI2 Receive Data Buffer Register */
-#define                        SPI2_BAUD  0xffc02414   /* SPI2 Baud Rate Register */
-#define                      SPI2_SHADOW  0xffc02418   /* SPI2 Receive Data Buffer Shadow Register */
+/* The BF548 is like the BF547, but has additional CANs */
+#include "defBF547.h"
 
 /* CAN Controller 1 Config 1 Registers */
 
@@ -508,1096 +401,4 @@
 #define                    CAN1_MB31_ID0  0xffc037f8   /* CAN Controller 1 Mailbox 31 ID0 Register */
 #define                    CAN1_MB31_ID1  0xffc037fc   /* CAN Controller 1 Mailbox 31 ID1 Register */
 
-/* ATAPI Registers */
-
-#define                    ATAPI_CONTROL  0xffc03800   /* ATAPI Control Register */
-#define                     ATAPI_STATUS  0xffc03804   /* ATAPI Status Register */
-#define                   ATAPI_DEV_ADDR  0xffc03808   /* ATAPI Device Register Address */
-#define                  ATAPI_DEV_TXBUF  0xffc0380c   /* ATAPI Device Register Write Data */
-#define                  ATAPI_DEV_RXBUF  0xffc03810   /* ATAPI Device Register Read Data */
-#define                   ATAPI_INT_MASK  0xffc03814   /* ATAPI Interrupt Mask Register */
-#define                 ATAPI_INT_STATUS  0xffc03818   /* ATAPI Interrupt Status Register */
-#define                   ATAPI_XFER_LEN  0xffc0381c   /* ATAPI Length of Transfer */
-#define                ATAPI_LINE_STATUS  0xffc03820   /* ATAPI Line Status */
-#define                   ATAPI_SM_STATE  0xffc03824   /* ATAPI State Machine Status */
-#define                  ATAPI_TERMINATE  0xffc03828   /* ATAPI Host Terminate */
-#define                 ATAPI_PIO_TFRCNT  0xffc0382c   /* ATAPI PIO mode transfer count */
-#define                 ATAPI_DMA_TFRCNT  0xffc03830   /* ATAPI DMA mode transfer count */
-#define               ATAPI_UMAIN_TFRCNT  0xffc03834   /* ATAPI UDMAIN transfer count */
-#define             ATAPI_UDMAOUT_TFRCNT  0xffc03838   /* ATAPI UDMAOUT transfer count */
-#define                  ATAPI_REG_TIM_0  0xffc03840   /* ATAPI Register Transfer Timing 0 */
-#define                  ATAPI_PIO_TIM_0  0xffc03844   /* ATAPI PIO Timing 0 Register */
-#define                  ATAPI_PIO_TIM_1  0xffc03848   /* ATAPI PIO Timing 1 Register */
-#define                ATAPI_MULTI_TIM_0  0xffc03850   /* ATAPI Multi-DMA Timing 0 Register */
-#define                ATAPI_MULTI_TIM_1  0xffc03854   /* ATAPI Multi-DMA Timing 1 Register */
-#define                ATAPI_MULTI_TIM_2  0xffc03858   /* ATAPI Multi-DMA Timing 2 Register */
-#define                ATAPI_ULTRA_TIM_0  0xffc03860   /* ATAPI Ultra-DMA Timing 0 Register */
-#define                ATAPI_ULTRA_TIM_1  0xffc03864   /* ATAPI Ultra-DMA Timing 1 Register */
-#define                ATAPI_ULTRA_TIM_2  0xffc03868   /* ATAPI Ultra-DMA Timing 2 Register */
-#define                ATAPI_ULTRA_TIM_3  0xffc0386c   /* ATAPI Ultra-DMA Timing 3 Register */
-
-/* SDH Registers */
-
-#define                      SDH_PWR_CTL  0xffc03900   /* SDH Power Control */
-#define                      SDH_CLK_CTL  0xffc03904   /* SDH Clock Control */
-#define                     SDH_ARGUMENT  0xffc03908   /* SDH Argument */
-#define                      SDH_COMMAND  0xffc0390c   /* SDH Command */
-#define                     SDH_RESP_CMD  0xffc03910   /* SDH Response Command */
-#define                    SDH_RESPONSE0  0xffc03914   /* SDH Response0 */
-#define                    SDH_RESPONSE1  0xffc03918   /* SDH Response1 */
-#define                    SDH_RESPONSE2  0xffc0391c   /* SDH Response2 */
-#define                    SDH_RESPONSE3  0xffc03920   /* SDH Response3 */
-#define                   SDH_DATA_TIMER  0xffc03924   /* SDH Data Timer */
-#define                    SDH_DATA_LGTH  0xffc03928   /* SDH Data Length */
-#define                     SDH_DATA_CTL  0xffc0392c   /* SDH Data Control */
-#define                     SDH_DATA_CNT  0xffc03930   /* SDH Data Counter */
-#define                       SDH_STATUS  0xffc03934   /* SDH Status */
-#define                   SDH_STATUS_CLR  0xffc03938   /* SDH Status Clear */
-#define                        SDH_MASK0  0xffc0393c   /* SDH Interrupt0 Mask */
-#define                        SDH_MASK1  0xffc03940   /* SDH Interrupt1 Mask */
-#define                     SDH_FIFO_CNT  0xffc03948   /* SDH FIFO Counter */
-#define                         SDH_FIFO  0xffc03980   /* SDH Data FIFO */
-#define                     SDH_E_STATUS  0xffc039c0   /* SDH Exception Status */
-#define                       SDH_E_MASK  0xffc039c4   /* SDH Exception Mask */
-#define                          SDH_CFG  0xffc039c8   /* SDH Configuration */
-#define                   SDH_RD_WAIT_EN  0xffc039cc   /* SDH Read Wait Enable */
-#define                         SDH_PID0  0xffc039d0   /* SDH Peripheral Identification0 */
-#define                         SDH_PID1  0xffc039d4   /* SDH Peripheral Identification1 */
-#define                         SDH_PID2  0xffc039d8   /* SDH Peripheral Identification2 */
-#define                         SDH_PID3  0xffc039dc   /* SDH Peripheral Identification3 */
-#define                         SDH_PID4  0xffc039e0   /* SDH Peripheral Identification4 */
-#define                         SDH_PID5  0xffc039e4   /* SDH Peripheral Identification5 */
-#define                         SDH_PID6  0xffc039e8   /* SDH Peripheral Identification6 */
-#define                         SDH_PID7  0xffc039ec   /* SDH Peripheral Identification7 */
-
-/* HOST Port Registers */
-
-#define                     HOST_CONTROL  0xffc03a00   /* HOST Control Register */
-#define                      HOST_STATUS  0xffc03a04   /* HOST Status Register */
-#define                     HOST_TIMEOUT  0xffc03a08   /* HOST Acknowledge Mode Timeout Register */
-
-/* USB Control Registers */
-
-#define                        USB_FADDR  0xffc03c00   /* Function address register */
-#define                        USB_POWER  0xffc03c04   /* Power management register */
-#define                       USB_INTRTX  0xffc03c08   /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */
-#define                       USB_INTRRX  0xffc03c0c   /* Interrupt register for Rx endpoints 1 to 7 */
-#define                      USB_INTRTXE  0xffc03c10   /* Interrupt enable register for IntrTx */
-#define                      USB_INTRRXE  0xffc03c14   /* Interrupt enable register for IntrRx */
-#define                      USB_INTRUSB  0xffc03c18   /* Interrupt register for common USB interrupts */
-#define                     USB_INTRUSBE  0xffc03c1c   /* Interrupt enable register for IntrUSB */
-#define                        USB_FRAME  0xffc03c20   /* USB frame number */
-#define                        USB_INDEX  0xffc03c24   /* Index register for selecting the indexed endpoint registers */
-#define                     USB_TESTMODE  0xffc03c28   /* Enabled USB 20 test modes */
-#define                     USB_GLOBINTR  0xffc03c2c   /* Global Interrupt Mask register and Wakeup Exception Interrupt */
-#define                   USB_GLOBAL_CTL  0xffc03c30   /* Global Clock Control for the core */
-
-/* USB Packet Control Registers */
-
-#define                USB_TX_MAX_PACKET  0xffc03c40   /* Maximum packet size for Host Tx endpoint */
-#define                         USB_CSR0  0xffc03c44   /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
-#define                        USB_TXCSR  0xffc03c44   /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
-#define                USB_RX_MAX_PACKET  0xffc03c48   /* Maximum packet size for Host Rx endpoint */
-#define                        USB_RXCSR  0xffc03c4c   /* Control Status register for Host Rx endpoint */
-#define                       USB_COUNT0  0xffc03c50   /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
-#define                      USB_RXCOUNT  0xffc03c50   /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
-#define                       USB_TXTYPE  0xffc03c54   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */
-#define                    USB_NAKLIMIT0  0xffc03c58   /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
-#define                   USB_TXINTERVAL  0xffc03c58   /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
-#define                       USB_RXTYPE  0xffc03c5c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */
-#define                   USB_RXINTERVAL  0xffc03c60   /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */
-#define                      USB_TXCOUNT  0xffc03c68   /* Number of bytes to be written to the selected endpoint Tx FIFO */
-
-/* USB Endpoint FIFO Registers */
-
-#define                     USB_EP0_FIFO  0xffc03c80   /* Endpoint 0 FIFO */
-#define                     USB_EP1_FIFO  0xffc03c88   /* Endpoint 1 FIFO */
-#define                     USB_EP2_FIFO  0xffc03c90   /* Endpoint 2 FIFO */
-#define                     USB_EP3_FIFO  0xffc03c98   /* Endpoint 3 FIFO */
-#define                     USB_EP4_FIFO  0xffc03ca0   /* Endpoint 4 FIFO */
-#define                     USB_EP5_FIFO  0xffc03ca8   /* Endpoint 5 FIFO */
-#define                     USB_EP6_FIFO  0xffc03cb0   /* Endpoint 6 FIFO */
-#define                     USB_EP7_FIFO  0xffc03cb8   /* Endpoint 7 FIFO */
-
-/* USB OTG Control Registers */
-
-#define                  USB_OTG_DEV_CTL  0xffc03d00   /* OTG Device Control Register */
-#define                 USB_OTG_VBUS_IRQ  0xffc03d04   /* OTG VBUS Control Interrupts */
-#define                USB_OTG_VBUS_MASK  0xffc03d08   /* VBUS Control Interrupt Enable */
-
-/* USB Phy Control Registers */
-
-#define                     USB_LINKINFO  0xffc03d48   /* Enables programming of some PHY-side delays */
-#define                        USB_VPLEN  0xffc03d4c   /* Determines duration of VBUS pulse for VBUS charging */
-#define                      USB_HS_EOF1  0xffc03d50   /* Time buffer for High-Speed transactions */
-#define                      USB_FS_EOF1  0xffc03d54   /* Time buffer for Full-Speed transactions */
-#define                      USB_LS_EOF1  0xffc03d58   /* Time buffer for Low-Speed transactions */
-
-/* (APHY_CNTRL is for ADI usage only) */
-
-#define                   USB_APHY_CNTRL  0xffc03de0   /* Register that increases visibility of Analog PHY */
-
-/* (APHY_CALIB is for ADI usage only) */
-
-#define                   USB_APHY_CALIB  0xffc03de4   /* Register used to set some calibration values */
-#define                  USB_APHY_CNTRL2  0xffc03de8   /* Register used to prevent re-enumeration once Moab goes into hibernate mode */
-
-/* (PHY_TEST is for ADI usage only) */
-
-#define                     USB_PHY_TEST  0xffc03dec   /* Used for reducing simulation time and simplifies FIFO testability */
-#define                  USB_PLLOSC_CTRL  0xffc03df0   /* Used to program different parameters for USB PLL and Oscillator */
-#define                   USB_SRP_CLKDIV  0xffc03df4   /* Used to program clock divide value for the clock fed to the SRP detection logic */
-
-/* USB Endpoint 0 Control Registers */
-
-#define                USB_EP_NI0_TXMAXP  0xffc03e00   /* Maximum packet size for Host Tx endpoint0 */
-#define                 USB_EP_NI0_TXCSR  0xffc03e04   /* Control Status register for endpoint 0 */
-#define                USB_EP_NI0_RXMAXP  0xffc03e08   /* Maximum packet size for Host Rx endpoint0 */
-#define                 USB_EP_NI0_RXCSR  0xffc03e0c   /* Control Status register for Host Rx endpoint0 */
-#define               USB_EP_NI0_RXCOUNT  0xffc03e10   /* Number of bytes received in endpoint 0 FIFO */
-#define                USB_EP_NI0_TXTYPE  0xffc03e14   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */
-#define            USB_EP_NI0_TXINTERVAL  0xffc03e18   /* Sets the NAK response timeout on Endpoint 0 */
-#define                USB_EP_NI0_RXTYPE  0xffc03e1c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */
-#define            USB_EP_NI0_RXINTERVAL  0xffc03e20   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */
-
-/* USB Endpoint 1 Control Registers */
-
-#define               USB_EP_NI0_TXCOUNT  0xffc03e28   /* Number of bytes to be written to the endpoint0 Tx FIFO */
-#define                USB_EP_NI1_TXMAXP  0xffc03e40   /* Maximum packet size for Host Tx endpoint1 */
-#define                 USB_EP_NI1_TXCSR  0xffc03e44   /* Control Status register for endpoint1 */
-#define                USB_EP_NI1_RXMAXP  0xffc03e48   /* Maximum packet size for Host Rx endpoint1 */
-#define                 USB_EP_NI1_RXCSR  0xffc03e4c   /* Control Status register for Host Rx endpoint1 */
-#define               USB_EP_NI1_RXCOUNT  0xffc03e50   /* Number of bytes received in endpoint1 FIFO */
-#define                USB_EP_NI1_TXTYPE  0xffc03e54   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */
-#define            USB_EP_NI1_TXINTERVAL  0xffc03e58   /* Sets the NAK response timeout on Endpoint1 */
-#define                USB_EP_NI1_RXTYPE  0xffc03e5c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */
-#define            USB_EP_NI1_RXINTERVAL  0xffc03e60   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */
-
-/* USB Endpoint 2 Control Registers */
-
-#define               USB_EP_NI1_TXCOUNT  0xffc03e68   /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */
-#define                USB_EP_NI2_TXMAXP  0xffc03e80   /* Maximum packet size for Host Tx endpoint2 */
-#define                 USB_EP_NI2_TXCSR  0xffc03e84   /* Control Status register for endpoint2 */
-#define                USB_EP_NI2_RXMAXP  0xffc03e88   /* Maximum packet size for Host Rx endpoint2 */
-#define                 USB_EP_NI2_RXCSR  0xffc03e8c   /* Control Status register for Host Rx endpoint2 */
-#define               USB_EP_NI2_RXCOUNT  0xffc03e90   /* Number of bytes received in endpoint2 FIFO */
-#define                USB_EP_NI2_TXTYPE  0xffc03e94   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */
-#define            USB_EP_NI2_TXINTERVAL  0xffc03e98   /* Sets the NAK response timeout on Endpoint2 */
-#define                USB_EP_NI2_RXTYPE  0xffc03e9c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */
-#define            USB_EP_NI2_RXINTERVAL  0xffc03ea0   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */
-
-/* USB Endpoint 3 Control Registers */
-
-#define               USB_EP_NI2_TXCOUNT  0xffc03ea8   /* Number of bytes to be written to the endpoint2 Tx FIFO */
-#define                USB_EP_NI3_TXMAXP  0xffc03ec0   /* Maximum packet size for Host Tx endpoint3 */
-#define                 USB_EP_NI3_TXCSR  0xffc03ec4   /* Control Status register for endpoint3 */
-#define                USB_EP_NI3_RXMAXP  0xffc03ec8   /* Maximum packet size for Host Rx endpoint3 */
-#define                 USB_EP_NI3_RXCSR  0xffc03ecc   /* Control Status register for Host Rx endpoint3 */
-#define               USB_EP_NI3_RXCOUNT  0xffc03ed0   /* Number of bytes received in endpoint3 FIFO */
-#define                USB_EP_NI3_TXTYPE  0xffc03ed4   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */
-#define            USB_EP_NI3_TXINTERVAL  0xffc03ed8   /* Sets the NAK response timeout on Endpoint3 */
-#define                USB_EP_NI3_RXTYPE  0xffc03edc   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */
-#define            USB_EP_NI3_RXINTERVAL  0xffc03ee0   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */
-
-/* USB Endpoint 4 Control Registers */
-
-#define               USB_EP_NI3_TXCOUNT  0xffc03ee8   /* Number of bytes to be written to the H124endpoint3 Tx FIFO */
-#define                USB_EP_NI4_TXMAXP  0xffc03f00   /* Maximum packet size for Host Tx endpoint4 */
-#define                 USB_EP_NI4_TXCSR  0xffc03f04   /* Control Status register for endpoint4 */
-#define                USB_EP_NI4_RXMAXP  0xffc03f08   /* Maximum packet size for Host Rx endpoint4 */
-#define                 USB_EP_NI4_RXCSR  0xffc03f0c   /* Control Status register for Host Rx endpoint4 */
-#define               USB_EP_NI4_RXCOUNT  0xffc03f10   /* Number of bytes received in endpoint4 FIFO */
-#define                USB_EP_NI4_TXTYPE  0xffc03f14   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */
-#define            USB_EP_NI4_TXINTERVAL  0xffc03f18   /* Sets the NAK response timeout on Endpoint4 */
-#define                USB_EP_NI4_RXTYPE  0xffc03f1c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */
-#define            USB_EP_NI4_RXINTERVAL  0xffc03f20   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */
-
-/* USB Endpoint 5 Control Registers */
-
-#define               USB_EP_NI4_TXCOUNT  0xffc03f28   /* Number of bytes to be written to the endpoint4 Tx FIFO */
-#define                USB_EP_NI5_TXMAXP  0xffc03f40   /* Maximum packet size for Host Tx endpoint5 */
-#define                 USB_EP_NI5_TXCSR  0xffc03f44   /* Control Status register for endpoint5 */
-#define                USB_EP_NI5_RXMAXP  0xffc03f48   /* Maximum packet size for Host Rx endpoint5 */
-#define                 USB_EP_NI5_RXCSR  0xffc03f4c   /* Control Status register for Host Rx endpoint5 */
-#define               USB_EP_NI5_RXCOUNT  0xffc03f50   /* Number of bytes received in endpoint5 FIFO */
-#define                USB_EP_NI5_TXTYPE  0xffc03f54   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */
-#define            USB_EP_NI5_TXINTERVAL  0xffc03f58   /* Sets the NAK response timeout on Endpoint5 */
-#define                USB_EP_NI5_RXTYPE  0xffc03f5c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */
-#define            USB_EP_NI5_RXINTERVAL  0xffc03f60   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */
-
-/* USB Endpoint 6 Control Registers */
-
-#define               USB_EP_NI5_TXCOUNT  0xffc03f68   /* Number of bytes to be written to the H145endpoint5 Tx FIFO */
-#define                USB_EP_NI6_TXMAXP  0xffc03f80   /* Maximum packet size for Host Tx endpoint6 */
-#define                 USB_EP_NI6_TXCSR  0xffc03f84   /* Control Status register for endpoint6 */
-#define                USB_EP_NI6_RXMAXP  0xffc03f88   /* Maximum packet size for Host Rx endpoint6 */
-#define                 USB_EP_NI6_RXCSR  0xffc03f8c   /* Control Status register for Host Rx endpoint6 */
-#define               USB_EP_NI6_RXCOUNT  0xffc03f90   /* Number of bytes received in endpoint6 FIFO */
-#define                USB_EP_NI6_TXTYPE  0xffc03f94   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */
-#define            USB_EP_NI6_TXINTERVAL  0xffc03f98   /* Sets the NAK response timeout on Endpoint6 */
-#define                USB_EP_NI6_RXTYPE  0xffc03f9c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */
-#define            USB_EP_NI6_RXINTERVAL  0xffc03fa0   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */
-
-/* USB Endpoint 7 Control Registers */
-
-#define               USB_EP_NI6_TXCOUNT  0xffc03fa8   /* Number of bytes to be written to the endpoint6 Tx FIFO */
-#define                USB_EP_NI7_TXMAXP  0xffc03fc0   /* Maximum packet size for Host Tx endpoint7 */
-#define                 USB_EP_NI7_TXCSR  0xffc03fc4   /* Control Status register for endpoint7 */
-#define                USB_EP_NI7_RXMAXP  0xffc03fc8   /* Maximum packet size for Host Rx endpoint7 */
-#define                 USB_EP_NI7_RXCSR  0xffc03fcc   /* Control Status register for Host Rx endpoint7 */
-#define               USB_EP_NI7_RXCOUNT  0xffc03fd0   /* Number of bytes received in endpoint7 FIFO */
-#define                USB_EP_NI7_TXTYPE  0xffc03fd4   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */
-#define            USB_EP_NI7_TXINTERVAL  0xffc03fd8   /* Sets the NAK response timeout on Endpoint7 */
-#define                USB_EP_NI7_RXTYPE  0xffc03fdc   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */
-#define            USB_EP_NI7_RXINTERVAL  0xffc03ff0   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */
-#define               USB_EP_NI7_TXCOUNT  0xffc03ff8   /* Number of bytes to be written to the endpoint7 Tx FIFO */
-#define                USB_DMA_INTERRUPT  0xffc04000   /* Indicates pending interrupts for the DMA channels */
-
-/* USB Channel 0 Config Registers */
-
-#define                  USB_DMA0CONTROL  0xffc04004   /* DMA master channel 0 configuration */
-#define                  USB_DMA0ADDRLOW  0xffc04008   /* Lower 16-bits of memory source/destination address for DMA master channel 0 */
-#define                 USB_DMA0ADDRHIGH  0xffc0400c   /* Upper 16-bits of memory source/destination address for DMA master channel 0 */
-#define                 USB_DMA0COUNTLOW  0xffc04010   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */
-#define                USB_DMA0COUNTHIGH  0xffc04014   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */
-
-/* USB Channel 1 Config Registers */
-
-#define                  USB_DMA1CONTROL  0xffc04024   /* DMA master channel 1 configuration */
-#define                  USB_DMA1ADDRLOW  0xffc04028   /* Lower 16-bits of memory source/destination address for DMA master channel 1 */
-#define                 USB_DMA1ADDRHIGH  0xffc0402c   /* Upper 16-bits of memory source/destination address for DMA master channel 1 */
-#define                 USB_DMA1COUNTLOW  0xffc04030   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */
-#define                USB_DMA1COUNTHIGH  0xffc04034   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */
-
-/* USB Channel 2 Config Registers */
-
-#define                  USB_DMA2CONTROL  0xffc04044   /* DMA master channel 2 configuration */
-#define                  USB_DMA2ADDRLOW  0xffc04048   /* Lower 16-bits of memory source/destination address for DMA master channel 2 */
-#define                 USB_DMA2ADDRHIGH  0xffc0404c   /* Upper 16-bits of memory source/destination address for DMA master channel 2 */
-#define                 USB_DMA2COUNTLOW  0xffc04050   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */
-#define                USB_DMA2COUNTHIGH  0xffc04054   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */
-
-/* USB Channel 3 Config Registers */
-
-#define                  USB_DMA3CONTROL  0xffc04064   /* DMA master channel 3 configuration */
-#define                  USB_DMA3ADDRLOW  0xffc04068   /* Lower 16-bits of memory source/destination address for DMA master channel 3 */
-#define                 USB_DMA3ADDRHIGH  0xffc0406c   /* Upper 16-bits of memory source/destination address for DMA master channel 3 */
-#define                 USB_DMA3COUNTLOW  0xffc04070   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */
-#define                USB_DMA3COUNTHIGH  0xffc04074   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */
-
-/* USB Channel 4 Config Registers */
-
-#define                  USB_DMA4CONTROL  0xffc04084   /* DMA master channel 4 configuration */
-#define                  USB_DMA4ADDRLOW  0xffc04088   /* Lower 16-bits of memory source/destination address for DMA master channel 4 */
-#define                 USB_DMA4ADDRHIGH  0xffc0408c   /* Upper 16-bits of memory source/destination address for DMA master channel 4 */
-#define                 USB_DMA4COUNTLOW  0xffc04090   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */
-#define                USB_DMA4COUNTHIGH  0xffc04094   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */
-
-/* USB Channel 5 Config Registers */
-
-#define                  USB_DMA5CONTROL  0xffc040a4   /* DMA master channel 5 configuration */
-#define                  USB_DMA5ADDRLOW  0xffc040a8   /* Lower 16-bits of memory source/destination address for DMA master channel 5 */
-#define                 USB_DMA5ADDRHIGH  0xffc040ac   /* Upper 16-bits of memory source/destination address for DMA master channel 5 */
-#define                 USB_DMA5COUNTLOW  0xffc040b0   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */
-#define                USB_DMA5COUNTHIGH  0xffc040b4   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */
-
-/* USB Channel 6 Config Registers */
-
-#define                  USB_DMA6CONTROL  0xffc040c4   /* DMA master channel 6 configuration */
-#define                  USB_DMA6ADDRLOW  0xffc040c8   /* Lower 16-bits of memory source/destination address for DMA master channel 6 */
-#define                 USB_DMA6ADDRHIGH  0xffc040cc   /* Upper 16-bits of memory source/destination address for DMA master channel 6 */
-#define                 USB_DMA6COUNTLOW  0xffc040d0   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */
-#define                USB_DMA6COUNTHIGH  0xffc040d4   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */
-
-/* USB Channel 7 Config Registers */
-
-#define                  USB_DMA7CONTROL  0xffc040e4   /* DMA master channel 7 configuration */
-#define                  USB_DMA7ADDRLOW  0xffc040e8   /* Lower 16-bits of memory source/destination address for DMA master channel 7 */
-#define                 USB_DMA7ADDRHIGH  0xffc040ec   /* Upper 16-bits of memory source/destination address for DMA master channel 7 */
-#define                 USB_DMA7COUNTLOW  0xffc040f0   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */
-#define                USB_DMA7COUNTHIGH  0xffc040f4   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */
-
-/* Keypad Registers */
-
-#define                         KPAD_CTL  0xffc04100   /* Controls keypad module enable and disable */
-#define                    KPAD_PRESCALE  0xffc04104   /* Establish a time base for programing the KPAD_MSEL register */
-#define                        KPAD_MSEL  0xffc04108   /* Selects delay parameters for keypad interface sensitivity */
-#define                      KPAD_ROWCOL  0xffc0410c   /* Captures the row and column output values of the keys pressed */
-#define                        KPAD_STAT  0xffc04110   /* Holds and clears the status of the keypad interface interrupt */
-#define                    KPAD_SOFTEVAL  0xffc04114   /* Lets software force keypad interface to check for keys being pressed */
-
-/* Pixel Compositor (PIXC) Registers */
-
-#define                         PIXC_CTL  0xffc04400   /* Overlay enable, resampling mode, I/O data format, transparency enable, watermark level, FIFO status */
-#define                         PIXC_PPL  0xffc04404   /* Holds the number of pixels per line of the display */
-#define                         PIXC_LPF  0xffc04408   /* Holds the number of lines per frame of the display */
-#define                     PIXC_AHSTART  0xffc0440c   /* Contains horizontal start pixel information of the overlay data (set A) */
-#define                       PIXC_AHEND  0xffc04410   /* Contains horizontal end pixel information of the overlay data (set A) */
-#define                     PIXC_AVSTART  0xffc04414   /* Contains vertical start pixel information of the overlay data (set A) */
-#define                       PIXC_AVEND  0xffc04418   /* Contains vertical end pixel information of the overlay data (set A) */
-#define                     PIXC_ATRANSP  0xffc0441c   /* Contains the transparency ratio (set A) */
-#define                     PIXC_BHSTART  0xffc04420   /* Contains horizontal start pixel information of the overlay data (set B) */
-#define                       PIXC_BHEND  0xffc04424   /* Contains horizontal end pixel information of the overlay data (set B) */
-#define                     PIXC_BVSTART  0xffc04428   /* Contains vertical start pixel information of the overlay data (set B) */
-#define                       PIXC_BVEND  0xffc0442c   /* Contains vertical end pixel information of the overlay data (set B) */
-#define                     PIXC_BTRANSP  0xffc04430   /* Contains the transparency ratio (set B) */
-#define                    PIXC_INTRSTAT  0xffc0443c   /* Overlay interrupt configuration/status */
-#define                       PIXC_RYCON  0xffc04440   /* Color space conversion matrix register. Contains the R/Y conversion coefficients */
-#define                       PIXC_GUCON  0xffc04444   /* Color space conversion matrix register. Contains the G/U conversion coefficients */
-#define                       PIXC_BVCON  0xffc04448   /* Color space conversion matrix register. Contains the B/V conversion coefficients */
-#define                      PIXC_CCBIAS  0xffc0444c   /* Bias values for the color space conversion matrix */
-#define                          PIXC_TC  0xffc04450   /* Holds the transparent color value */
-
-/* Handshake MDMA 0 Registers */
-
-#define                   HMDMA0_CONTROL  0xffc04500   /* Handshake MDMA0 Control Register */
-#define                    HMDMA0_ECINIT  0xffc04504   /* Handshake MDMA0 Initial Edge Count Register */
-#define                    HMDMA0_BCINIT  0xffc04508   /* Handshake MDMA0 Initial Block Count Register */
-#define                  HMDMA0_ECURGENT  0xffc0450c   /* Handshake MDMA0 Urgent Edge Count Threshold Register */
-#define                HMDMA0_ECOVERFLOW  0xffc04510   /* Handshake MDMA0 Edge Count Overflow Interrupt Register */
-#define                    HMDMA0_ECOUNT  0xffc04514   /* Handshake MDMA0 Current Edge Count Register */
-#define                    HMDMA0_BCOUNT  0xffc04518   /* Handshake MDMA0 Current Block Count Register */
-
-/* Handshake MDMA 1 Registers */
-
-#define                   HMDMA1_CONTROL  0xffc04540   /* Handshake MDMA1 Control Register */
-#define                    HMDMA1_ECINIT  0xffc04544   /* Handshake MDMA1 Initial Edge Count Register */
-#define                    HMDMA1_BCINIT  0xffc04548   /* Handshake MDMA1 Initial Block Count Register */
-#define                  HMDMA1_ECURGENT  0xffc0454c   /* Handshake MDMA1 Urgent Edge Count Threshold Register */
-#define                HMDMA1_ECOVERFLOW  0xffc04550   /* Handshake MDMA1 Edge Count Overflow Interrupt Register */
-#define                    HMDMA1_ECOUNT  0xffc04554   /* Handshake MDMA1 Current Edge Count Register */
-#define                    HMDMA1_BCOUNT  0xffc04558   /* Handshake MDMA1 Current Block Count Register */
-
-
-/* ********************************************************** */
-/*     SINGLE BIT MACRO PAIRS (bit mask and negated one)      */
-/*     and MULTI BIT READ MACROS                              */
-/* ********************************************************** */
-
-/* Bit masks for PIXC_CTL */
-
-#define                   PIXC_EN  0x1        /* Pixel Compositor Enable */
-#define                  OVR_A_EN  0x2        /* Overlay A Enable */
-#define                  OVR_B_EN  0x4        /* Overlay B Enable */
-#define                  IMG_FORM  0x8        /* Image Data Format */
-#define                  OVR_FORM  0x10       /* Overlay Data Format */
-#define                  OUT_FORM  0x20       /* Output Data Format */
-#define                   UDS_MOD  0x40       /* Resampling Mode */
-#define                     TC_EN  0x80       /* Transparent Color Enable */
-#define                  IMG_STAT  0x300      /* Image FIFO Status */
-#define                  OVR_STAT  0xc00      /* Overlay FIFO Status */
-#define                    WM_LVL  0x3000     /* FIFO Watermark Level */
-
-/* Bit masks for PIXC_AHSTART */
-
-#define                  A_HSTART  0xfff      /* Horizontal Start Coordinates */
-
-/* Bit masks for PIXC_AHEND */
-
-#define                    A_HEND  0xfff      /* Horizontal End Coordinates */
-
-/* Bit masks for PIXC_AVSTART */
-
-#define                  A_VSTART  0x3ff      /* Vertical Start Coordinates */
-
-/* Bit masks for PIXC_AVEND */
-
-#define                    A_VEND  0x3ff      /* Vertical End Coordinates */
-
-/* Bit masks for PIXC_ATRANSP */
-
-#define                  A_TRANSP  0xf        /* Transparency Value */
-
-/* Bit masks for PIXC_BHSTART */
-
-#define                  B_HSTART  0xfff      /* Horizontal Start Coordinates */
-
-/* Bit masks for PIXC_BHEND */
-
-#define                    B_HEND  0xfff      /* Horizontal End Coordinates */
-
-/* Bit masks for PIXC_BVSTART */
-
-#define                  B_VSTART  0x3ff      /* Vertical Start Coordinates */
-
-/* Bit masks for PIXC_BVEND */
-
-#define                    B_VEND  0x3ff      /* Vertical End Coordinates */
-
-/* Bit masks for PIXC_BTRANSP */
-
-#define                  B_TRANSP  0xf        /* Transparency Value */
-
-/* Bit masks for PIXC_INTRSTAT */
-
-#define                OVR_INT_EN  0x1        /* Interrupt at End of Last Valid Overlay */
-#define                FRM_INT_EN  0x2        /* Interrupt at End of Frame */
-#define              OVR_INT_STAT  0x4        /* Overlay Interrupt Status */
-#define              FRM_INT_STAT  0x8        /* Frame Interrupt Status */
-
-/* Bit masks for PIXC_RYCON */
-
-#define                       A11  0x3ff      /* A11 in the Coefficient Matrix */
-#define                       A12  0xffc00    /* A12 in the Coefficient Matrix */
-#define                       A13  0x3ff00000 /* A13 in the Coefficient Matrix */
-#define                  RY_MULT4  0x40000000 /* Multiply Row by 4 */
-
-/* Bit masks for PIXC_GUCON */
-
-#define                       A21  0x3ff      /* A21 in the Coefficient Matrix */
-#define                       A22  0xffc00    /* A22 in the Coefficient Matrix */
-#define                       A23  0x3ff00000 /* A23 in the Coefficient Matrix */
-#define                  GU_MULT4  0x40000000 /* Multiply Row by 4 */
-
-/* Bit masks for PIXC_BVCON */
-
-#define                       A31  0x3ff      /* A31 in the Coefficient Matrix */
-#define                       A32  0xffc00    /* A32 in the Coefficient Matrix */
-#define                       A33  0x3ff00000 /* A33 in the Coefficient Matrix */
-#define                  BV_MULT4  0x40000000 /* Multiply Row by 4 */
-
-/* Bit masks for PIXC_CCBIAS */
-
-#define                       A14  0x3ff      /* A14 in the Bias Vector */
-#define                       A24  0xffc00    /* A24 in the Bias Vector */
-#define                       A34  0x3ff00000 /* A34 in the Bias Vector */
-
-/* Bit masks for PIXC_TC */
-
-#define                  RY_TRANS  0xff       /* Transparent Color - R/Y Component */
-#define                  GU_TRANS  0xff00     /* Transparent Color - G/U Component */
-#define                  BV_TRANS  0xff0000   /* Transparent Color - B/V Component */
-
-/* Bit masks for HOST_CONTROL */
-
-#define                   HOST_EN  0x1        /* Host Enable */
-#define                  HOST_END  0x2        /* Host Endianess */
-#define                 DATA_SIZE  0x4        /* Data Size */
-#define                  HOST_RST  0x8        /* Host Reset */
-#define                  HRDY_OVR  0x20       /* Host Ready Override */
-#define                  INT_MODE  0x40       /* Interrupt Mode */
-#define                     BT_EN  0x80       /* Bus Timeout Enable */
-#define                       EHW  0x100      /* Enable Host Write */
-#define                       EHR  0x200      /* Enable Host Read */
-#define                       BDR  0x400      /* Burst DMA Requests */
-
-/* Bit masks for HOST_STATUS */
-
-#define                 DMA_READY  0x1        /* DMA Ready */
-#define                  FIFOFULL  0x2        /* FIFO Full */
-#define                 FIFOEMPTY  0x4        /* FIFO Empty */
-#define              DMA_COMPLETE  0x8        /* DMA Complete */
-#define                      HSHK  0x10       /* Host Handshake */
-#define                 HSTIMEOUT  0x20       /* Host Timeout */
-#define                      HIRQ  0x40       /* Host Interrupt Request */
-#define                ALLOW_CNFG  0x80       /* Allow New Configuration */
-#define                   DMA_DIR  0x100      /* DMA Direction */
-#define                       BTE  0x200      /* Bus Timeout Enabled */
-
-/* Bit masks for HOST_TIMEOUT */
-
-#define             COUNT_TIMEOUT  0x7ff      /* Host Timeout count */
-
-/* Bit masks for KPAD_CTL */
-
-#define                   KPAD_EN  0x1        /* Keypad Enable */
-#define              KPAD_IRQMODE  0x6        /* Key Press Interrupt Enable */
-#define                KPAD_ROWEN  0x1c00     /* Row Enable Width */
-#define                KPAD_COLEN  0xe000     /* Column Enable Width */
-
-/* Bit masks for KPAD_PRESCALE */
-
-#define         KPAD_PRESCALE_VAL  0x3f       /* Key Prescale Value */
-
-/* Bit masks for KPAD_MSEL */
-
-#define                DBON_SCALE  0xff       /* Debounce Scale Value */
-#define              COLDRV_SCALE  0xff00     /* Column Driver Scale Value */
-
-/* Bit masks for KPAD_ROWCOL */
-
-#define                  KPAD_ROW  0xff       /* Rows Pressed */
-#define                  KPAD_COL  0xff00     /* Columns Pressed */
-
-/* Bit masks for KPAD_STAT */
-
-#define                  KPAD_IRQ  0x1        /* Keypad Interrupt Status */
-#define              KPAD_MROWCOL  0x6        /* Multiple Row/Column Keypress Status */
-#define              KPAD_PRESSED  0x8        /* Key press current status */
-
-/* Bit masks for KPAD_SOFTEVAL */
-
-#define           KPAD_SOFTEVAL_E  0x2        /* Software Programmable Force Evaluate */
-
-/* Bit masks for SDH_COMMAND */
-
-#define                   CMD_IDX  0x3f       /* Command Index */
-#define                   CMD_RSP  0x40       /* Response */
-#define                 CMD_L_RSP  0x80       /* Long Response */
-#define                 CMD_INT_E  0x100      /* Command Interrupt */
-#define                CMD_PEND_E  0x200      /* Command Pending */
-#define                     CMD_E  0x400      /* Command Enable */
-
-/* Bit masks for SDH_PWR_CTL */
-
-#define                    PWR_ON  0x3        /* Power On */
-#if 0
-#define                       TBD  0x3c       /* TBD */
-#endif
-#define                 SD_CMD_OD  0x40       /* Open Drain Output */
-#define                   ROD_CTL  0x80       /* Rod Control */
-
-/* Bit masks for SDH_CLK_CTL */
-
-#define                    CLKDIV  0xff       /* MC_CLK Divisor */
-#define                     CLK_E  0x100      /* MC_CLK Bus Clock Enable */
-#define                  PWR_SV_E  0x200      /* Power Save Enable */
-#define             CLKDIV_BYPASS  0x400      /* Bypass Divisor */
-#define                  WIDE_BUS  0x800      /* Wide Bus Mode Enable */
-
-/* Bit masks for SDH_RESP_CMD */
-
-#define                  RESP_CMD  0x3f       /* Response Command */
-
-/* Bit masks for SDH_DATA_CTL */
-
-#define                     DTX_E  0x1        /* Data Transfer Enable */
-#define                   DTX_DIR  0x2        /* Data Transfer Direction */
-#define                  DTX_MODE  0x4        /* Data Transfer Mode */
-#define                 DTX_DMA_E  0x8        /* Data Transfer DMA Enable */
-#define              DTX_BLK_LGTH  0xf0       /* Data Transfer Block Length */
-
-/* Bit masks for SDH_STATUS */
-
-#define              CMD_CRC_FAIL  0x1        /* CMD CRC Fail */
-#define              DAT_CRC_FAIL  0x2        /* Data CRC Fail */
-#define               CMD_TIME_OUT  0x4        /* CMD Time Out */
-#define               DAT_TIME_OUT  0x8        /* Data Time Out */
-#define               TX_UNDERRUN  0x10       /* Transmit Underrun */
-#define                RX_OVERRUN  0x20       /* Receive Overrun */
-#define              CMD_RESP_END  0x40       /* CMD Response End */
-#define                  CMD_SENT  0x80       /* CMD Sent */
-#define                   DAT_END  0x100      /* Data End */
-#define             START_BIT_ERR  0x200      /* Start Bit Error */
-#define               DAT_BLK_END  0x400      /* Data Block End */
-#define                   CMD_ACT  0x800      /* CMD Active */
-#define                    TX_ACT  0x1000     /* Transmit Active */
-#define                    RX_ACT  0x2000     /* Receive Active */
-#define              TX_FIFO_STAT  0x4000     /* Transmit FIFO Status */
-#define              RX_FIFO_STAT  0x8000     /* Receive FIFO Status */
-#define              TX_FIFO_FULL  0x10000    /* Transmit FIFO Full */
-#define              RX_FIFO_FULL  0x20000    /* Receive FIFO Full */
-#define              TX_FIFO_ZERO  0x40000    /* Transmit FIFO Empty */
-#define               RX_DAT_ZERO  0x80000    /* Receive FIFO Empty */
-#define                TX_DAT_RDY  0x100000   /* Transmit Data Available */
-#define               RX_FIFO_RDY  0x200000   /* Receive Data Available */
-
-/* Bit masks for SDH_STATUS_CLR */
-
-#define         CMD_CRC_FAIL_STAT  0x1        /* CMD CRC Fail Status */
-#define         DAT_CRC_FAIL_STAT  0x2        /* Data CRC Fail Status */
-#define          CMD_TIMEOUT_STAT  0x4        /* CMD Time Out Status */
-#define          DAT_TIMEOUT_STAT  0x8        /* Data Time Out status */
-#define          TX_UNDERRUN_STAT  0x10       /* Transmit Underrun Status */
-#define           RX_OVERRUN_STAT  0x20       /* Receive Overrun Status */
-#define         CMD_RESP_END_STAT  0x40       /* CMD Response End Status */
-#define             CMD_SENT_STAT  0x80       /* CMD Sent Status */
-#define              DAT_END_STAT  0x100      /* Data End Status */
-#define        START_BIT_ERR_STAT  0x200      /* Start Bit Error Status */
-#define          DAT_BLK_END_STAT  0x400      /* Data Block End Status */
-
-/* Bit masks for SDH_MASK0 */
-
-#define         CMD_CRC_FAIL_MASK  0x1        /* CMD CRC Fail Mask */
-#define         DAT_CRC_FAIL_MASK  0x2        /* Data CRC Fail Mask */
-#define          CMD_TIMEOUT_MASK  0x4        /* CMD Time Out Mask */
-#define          DAT_TIMEOUT_MASK  0x8        /* Data Time Out Mask */
-#define          TX_UNDERRUN_MASK  0x10       /* Transmit Underrun Mask */
-#define           RX_OVERRUN_MASK  0x20       /* Receive Overrun Mask */
-#define         CMD_RESP_END_MASK  0x40       /* CMD Response End Mask */
-#define             CMD_SENT_MASK  0x80       /* CMD Sent Mask */
-#define              DAT_END_MASK  0x100      /* Data End Mask */
-#define        START_BIT_ERR_MASK  0x200      /* Start Bit Error Mask */
-#define          DAT_BLK_END_MASK  0x400      /* Data Block End Mask */
-#define              CMD_ACT_MASK  0x800      /* CMD Active Mask */
-#define               TX_ACT_MASK  0x1000     /* Transmit Active Mask */
-#define               RX_ACT_MASK  0x2000     /* Receive Active Mask */
-#define         TX_FIFO_STAT_MASK  0x4000     /* Transmit FIFO Status Mask */
-#define         RX_FIFO_STAT_MASK  0x8000     /* Receive FIFO Status Mask */
-#define         TX_FIFO_FULL_MASK  0x10000    /* Transmit FIFO Full Mask */
-#define         RX_FIFO_FULL_MASK  0x20000    /* Receive FIFO Full Mask */
-#define         TX_FIFO_ZERO_MASK  0x40000    /* Transmit FIFO Empty Mask */
-#define          RX_DAT_ZERO_MASK  0x80000    /* Receive FIFO Empty Mask */
-#define           TX_DAT_RDY_MASK  0x100000   /* Transmit Data Available Mask */
-#define          RX_FIFO_RDY_MASK  0x200000   /* Receive Data Available Mask */
-
-/* Bit masks for SDH_FIFO_CNT */
-
-#define                FIFO_COUNT  0x7fff     /* FIFO Count */
-
-/* Bit masks for SDH_E_STATUS */
-
-#define              SDIO_INT_DET  0x2        /* SDIO Int Detected */
-#define               SD_CARD_DET  0x10       /* SD Card Detect */
-
-/* Bit masks for SDH_E_MASK */
-
-#define                  SDIO_MSK  0x2        /* Mask SDIO Int Detected */
-#define                   SCD_MSK  0x40       /* Mask Card Detect */
-
-/* Bit masks for SDH_CFG */
-
-#define                   CLKS_EN  0x1        /* Clocks Enable */
-#define                      SD4E  0x4        /* SDIO 4-Bit Enable */
-#define                       MWE  0x8        /* Moving Window Enable */
-#define                    SD_RST  0x10       /* SDMMC Reset */
-#define                 PUP_SDDAT  0x20       /* Pull-up SD_DAT */
-#define                PUP_SDDAT3  0x40       /* Pull-up SD_DAT3 */
-#define                 PD_SDDAT3  0x80       /* Pull-down SD_DAT3 */
-
-/* Bit masks for SDH_RD_WAIT_EN */
-
-#define                       RWR  0x1        /* Read Wait Request */
-
-/* Bit masks for ATAPI_CONTROL */
-
-#define                 PIO_START  0x1        /* Start PIO/Reg Op */
-#define               MULTI_START  0x2        /* Start Multi-DMA Op */
-#define               ULTRA_START  0x4        /* Start Ultra-DMA Op */
-#define                  XFER_DIR  0x8        /* Transfer Direction */
-#define                  IORDY_EN  0x10       /* IORDY Enable */
-#define                FIFO_FLUSH  0x20       /* Flush FIFOs */
-#define                  SOFT_RST  0x40       /* Soft Reset */
-#define                   DEV_RST  0x80       /* Device Reset */
-#define                TFRCNT_RST  0x100      /* Trans Count Reset */
-#define               END_ON_TERM  0x200      /* End/Terminate Select */
-#define               PIO_USE_DMA  0x400      /* PIO-DMA Enable */
-#define          UDMAIN_FIFO_THRS  0xf000     /* Ultra DMA-IN FIFO Threshold */
-
-/* Bit masks for ATAPI_STATUS */
-
-#define               PIO_XFER_ON  0x1        /* PIO transfer in progress */
-#define             MULTI_XFER_ON  0x2        /* Multi-word DMA transfer in progress */
-#define             ULTRA_XFER_ON  0x4        /* Ultra DMA transfer in progress */
-#define               ULTRA_IN_FL  0xf0       /* Ultra DMA Input FIFO Level */
-
-/* Bit masks for ATAPI_DEV_ADDR */
-
-#define                  DEV_ADDR  0x1f       /* Device Address */
-
-/* Bit masks for ATAPI_INT_MASK */
-
-#define        ATAPI_DEV_INT_MASK  0x1        /* Device interrupt mask */
-#define             PIO_DONE_MASK  0x2        /* PIO transfer done interrupt mask */
-#define           MULTI_DONE_MASK  0x4        /* Multi-DMA transfer done interrupt mask */
-#define          UDMAIN_DONE_MASK  0x8        /* Ultra-DMA in transfer done interrupt mask */
-#define         UDMAOUT_DONE_MASK  0x10       /* Ultra-DMA out transfer done interrupt mask */
-#define       HOST_TERM_XFER_MASK  0x20       /* Host terminate current transfer interrupt mask */
-#define           MULTI_TERM_MASK  0x40       /* Device terminate Multi-DMA transfer interrupt mask */
-#define          UDMAIN_TERM_MASK  0x80       /* Device terminate Ultra-DMA-in transfer interrupt mask */
-#define         UDMAOUT_TERM_MASK  0x100      /* Device terminate Ultra-DMA-out transfer interrupt mask */
-
-/* Bit masks for ATAPI_INT_STATUS */
-
-#define             ATAPI_DEV_INT  0x1        /* Device interrupt status */
-#define              PIO_DONE_INT  0x2        /* PIO transfer done interrupt status */
-#define            MULTI_DONE_INT  0x4        /* Multi-DMA transfer done interrupt status */
-#define           UDMAIN_DONE_INT  0x8        /* Ultra-DMA in transfer done interrupt status */
-#define          UDMAOUT_DONE_INT  0x10       /* Ultra-DMA out transfer done interrupt status */
-#define        HOST_TERM_XFER_INT  0x20       /* Host terminate current transfer interrupt status */
-#define            MULTI_TERM_INT  0x40       /* Device terminate Multi-DMA transfer interrupt status */
-#define           UDMAIN_TERM_INT  0x80       /* Device terminate Ultra-DMA-in transfer interrupt status */
-#define          UDMAOUT_TERM_INT  0x100      /* Device terminate Ultra-DMA-out transfer interrupt status */
-
-/* Bit masks for ATAPI_LINE_STATUS */
-
-#define                ATAPI_INTR  0x1        /* Device interrupt to host line status */
-#define                ATAPI_DASP  0x2        /* Device dasp to host line status */
-#define                ATAPI_CS0N  0x4        /* ATAPI chip select 0 line status */
-#define                ATAPI_CS1N  0x8        /* ATAPI chip select 1 line status */
-#define                ATAPI_ADDR  0x70       /* ATAPI address line status */
-#define              ATAPI_DMAREQ  0x80       /* ATAPI DMA request line status */
-#define             ATAPI_DMAACKN  0x100      /* ATAPI DMA acknowledge line status */
-#define               ATAPI_DIOWN  0x200      /* ATAPI write line status */
-#define               ATAPI_DIORN  0x400      /* ATAPI read line status */
-#define               ATAPI_IORDY  0x800      /* ATAPI IORDY line status */
-
-/* Bit masks for ATAPI_SM_STATE */
-
-#define                PIO_CSTATE  0xf        /* PIO mode state machine current state */
-#define                DMA_CSTATE  0xf0       /* DMA mode state machine current state */
-#define             UDMAIN_CSTATE  0xf00      /* Ultra DMA-In mode state machine current state */
-#define            UDMAOUT_CSTATE  0xf000     /* ATAPI IORDY line status */
-
-/* Bit masks for ATAPI_TERMINATE */
-
-#define           ATAPI_HOST_TERM  0x1        /* Host terminationation */
-
-/* Bit masks for ATAPI_REG_TIM_0 */
-
-#define                    T2_REG  0xff       /* End of cycle time for register access transfers */
-#define                  TEOC_REG  0xff00     /* Selects DIOR/DIOW pulsewidth */
-
-/* Bit masks for ATAPI_PIO_TIM_0 */
-
-#define                    T1_REG  0xf        /* Time from address valid to DIOR/DIOW */
-#define                T2_REG_PIO  0xff0      /* DIOR/DIOW pulsewidth */
-#define                    T4_REG  0xf000     /* DIOW data hold */
-
-/* Bit masks for ATAPI_PIO_TIM_1 */
-
-#define              TEOC_REG_PIO  0xff       /* End of cycle time for PIO access transfers. */
-
-/* Bit masks for ATAPI_MULTI_TIM_0 */
-
-#define                        TD  0xff       /* DIOR/DIOW asserted pulsewidth */
-#define                        TM  0xff00     /* Time from address valid to DIOR/DIOW */
-
-/* Bit masks for ATAPI_MULTI_TIM_1 */
-
-#define                       TKW  0xff       /* Selects DIOW negated pulsewidth */
-#define                       TKR  0xff00     /* Selects DIOR negated pulsewidth */
-
-/* Bit masks for ATAPI_MULTI_TIM_2 */
-
-#define                        TH  0xff       /* Selects DIOW data hold */
-#define                      TEOC  0xff00     /* Selects end of cycle for DMA */
-
-/* Bit masks for ATAPI_ULTRA_TIM_0 */
-
-#define                      TACK  0xff       /* Selects setup and hold times for TACK */
-#define                      TENV  0xff00     /* Selects envelope time */
-
-/* Bit masks for ATAPI_ULTRA_TIM_1 */
-
-#define                      TDVS  0xff       /* Selects data valid setup time */
-#define                 TCYC_TDVS  0xff00     /* Selects cycle time - TDVS time */
-
-/* Bit masks for ATAPI_ULTRA_TIM_2 */
-
-#define                       TSS  0xff       /* Selects time from STROBE edge to negation of DMARQ or assertion of STOP */
-#define                      TMLI  0xff00     /* Selects interlock time */
-
-/* Bit masks for ATAPI_ULTRA_TIM_3 */
-
-#define                      TZAH  0xff       /* Selects minimum delay required for output */
-#define               READY_PAUSE  0xff00     /* Selects ready to pause */
-
-/* Bit masks for TIMER_ENABLE1 */
-
-#define                    TIMEN8  0x1        /* Timer 8 Enable */
-#define                    TIMEN9  0x2        /* Timer 9 Enable */
-#define                   TIMEN10  0x4        /* Timer 10 Enable */
-
-/* Bit masks for TIMER_DISABLE1 */
-
-#define                   TIMDIS8  0x1        /* Timer 8 Disable */
-#define                   TIMDIS9  0x2        /* Timer 9 Disable */
-#define                  TIMDIS10  0x4        /* Timer 10 Disable */
-
-/* Bit masks for TIMER_STATUS1 */
-
-#define                    TIMIL8  0x1        /* Timer 8 Interrupt */
-#define                    TIMIL9  0x2        /* Timer 9 Interrupt */
-#define                   TIMIL10  0x4        /* Timer 10 Interrupt */
-#define                 TOVF_ERR8  0x10       /* Timer 8 Counter Overflow */
-#define                 TOVF_ERR9  0x20       /* Timer 9 Counter Overflow */
-#define                TOVF_ERR10  0x40       /* Timer 10 Counter Overflow */
-#define                     TRUN8  0x1000     /* Timer 8 Slave Enable Status */
-#define                     TRUN9  0x2000     /* Timer 9 Slave Enable Status */
-#define                    TRUN10  0x4000     /* Timer 10 Slave Enable Status */
-
-/* Bit masks for EPPI0 are obtained from common base header for EPPIx (EPPI1 and EPPI2) */
-
-/* Bit masks for USB_FADDR */
-
-#define          FUNCTION_ADDRESS  0x7f       /* Function address */
-
-/* Bit masks for USB_POWER */
-
-#define           ENABLE_SUSPENDM  0x1        /* enable SuspendM output */
-#define              SUSPEND_MODE  0x2        /* Suspend Mode indicator */
-#define               RESUME_MODE  0x4        /* DMA Mode */
-#define                     RESET  0x8        /* Reset indicator */
-#define                   HS_MODE  0x10       /* High Speed mode indicator */
-#define                 HS_ENABLE  0x20       /* high Speed Enable */
-#define                 SOFT_CONN  0x40       /* Soft connect */
-#define                ISO_UPDATE  0x80       /* Isochronous update */
-
-/* Bit masks for USB_INTRTX */
-
-#define                    EP0_TX  0x1        /* Tx Endpoint 0 interrupt */
-#define                    EP1_TX  0x2        /* Tx Endpoint 1 interrupt */
-#define                    EP2_TX  0x4        /* Tx Endpoint 2 interrupt */
-#define                    EP3_TX  0x8        /* Tx Endpoint 3 interrupt */
-#define                    EP4_TX  0x10       /* Tx Endpoint 4 interrupt */
-#define                    EP5_TX  0x20       /* Tx Endpoint 5 interrupt */
-#define                    EP6_TX  0x40       /* Tx Endpoint 6 interrupt */
-#define                    EP7_TX  0x80       /* Tx Endpoint 7 interrupt */
-
-/* Bit masks for USB_INTRRX */
-
-#define                    EP1_RX  0x2        /* Rx Endpoint 1 interrupt */
-#define                    EP2_RX  0x4        /* Rx Endpoint 2 interrupt */
-#define                    EP3_RX  0x8        /* Rx Endpoint 3 interrupt */
-#define                    EP4_RX  0x10       /* Rx Endpoint 4 interrupt */
-#define                    EP5_RX  0x20       /* Rx Endpoint 5 interrupt */
-#define                    EP6_RX  0x40       /* Rx Endpoint 6 interrupt */
-#define                    EP7_RX  0x80       /* Rx Endpoint 7 interrupt */
-
-/* Bit masks for USB_INTRTXE */
-
-#define                  EP0_TX_E  0x1        /* Endpoint 0 interrupt Enable */
-#define                  EP1_TX_E  0x2        /* Tx Endpoint 1 interrupt  Enable */
-#define                  EP2_TX_E  0x4        /* Tx Endpoint 2 interrupt  Enable */
-#define                  EP3_TX_E  0x8        /* Tx Endpoint 3 interrupt  Enable */
-#define                  EP4_TX_E  0x10       /* Tx Endpoint 4 interrupt  Enable */
-#define                  EP5_TX_E  0x20       /* Tx Endpoint 5 interrupt  Enable */
-#define                  EP6_TX_E  0x40       /* Tx Endpoint 6 interrupt  Enable */
-#define                  EP7_TX_E  0x80       /* Tx Endpoint 7 interrupt  Enable */
-
-/* Bit masks for USB_INTRRXE */
-
-#define                  EP1_RX_E  0x2        /* Rx Endpoint 1 interrupt  Enable */
-#define                  EP2_RX_E  0x4        /* Rx Endpoint 2 interrupt  Enable */
-#define                  EP3_RX_E  0x8        /* Rx Endpoint 3 interrupt  Enable */
-#define                  EP4_RX_E  0x10       /* Rx Endpoint 4 interrupt  Enable */
-#define                  EP5_RX_E  0x20       /* Rx Endpoint 5 interrupt  Enable */
-#define                  EP6_RX_E  0x40       /* Rx Endpoint 6 interrupt  Enable */
-#define                  EP7_RX_E  0x80       /* Rx Endpoint 7 interrupt  Enable */
-
-/* Bit masks for USB_INTRUSB */
-
-#define                 SUSPEND_B  0x1        /* Suspend indicator */
-#define                  RESUME_B  0x2        /* Resume indicator */
-#define          RESET_OR_BABLE_B  0x4        /* Reset/babble indicator */
-#define                     SOF_B  0x8        /* Start of frame */
-#define                    CONN_B  0x10       /* Connection indicator */
-#define                  DISCON_B  0x20       /* Disconnect indicator */
-#define             SESSION_REQ_B  0x40       /* Session Request */
-#define              VBUS_ERROR_B  0x80       /* Vbus threshold indicator */
-
-/* Bit masks for USB_INTRUSBE */
-
-#define                SUSPEND_BE  0x1        /* Suspend indicator int enable */
-#define                 RESUME_BE  0x2        /* Resume indicator int enable */
-#define         RESET_OR_BABLE_BE  0x4        /* Reset/babble indicator int enable */
-#define                    SOF_BE  0x8        /* Start of frame int enable */
-#define                   CONN_BE  0x10       /* Connection indicator int enable */
-#define                 DISCON_BE  0x20       /* Disconnect indicator int enable */
-#define            SESSION_REQ_BE  0x40       /* Session Request int enable */
-#define             VBUS_ERROR_BE  0x80       /* Vbus threshold indicator int enable */
-
-/* Bit masks for USB_FRAME */
-
-#define              FRAME_NUMBER  0x7ff      /* Frame number */
-
-/* Bit masks for USB_INDEX */
-
-#define         SELECTED_ENDPOINT  0xf        /* selected endpoint */
-
-/* Bit masks for USB_GLOBAL_CTL */
-
-#define                GLOBAL_ENA  0x1        /* enables USB module */
-#define                EP1_TX_ENA  0x2        /* Transmit endpoint 1 enable */
-#define                EP2_TX_ENA  0x4        /* Transmit endpoint 2 enable */
-#define                EP3_TX_ENA  0x8        /* Transmit endpoint 3 enable */
-#define                EP4_TX_ENA  0x10       /* Transmit endpoint 4 enable */
-#define                EP5_TX_ENA  0x20       /* Transmit endpoint 5 enable */
-#define                EP6_TX_ENA  0x40       /* Transmit endpoint 6 enable */
-#define                EP7_TX_ENA  0x80       /* Transmit endpoint 7 enable */
-#define                EP1_RX_ENA  0x100      /* Receive endpoint 1 enable */
-#define                EP2_RX_ENA  0x200      /* Receive endpoint 2 enable */
-#define                EP3_RX_ENA  0x400      /* Receive endpoint 3 enable */
-#define                EP4_RX_ENA  0x800      /* Receive endpoint 4 enable */
-#define                EP5_RX_ENA  0x1000     /* Receive endpoint 5 enable */
-#define                EP6_RX_ENA  0x2000     /* Receive endpoint 6 enable */
-#define                EP7_RX_ENA  0x4000     /* Receive endpoint 7 enable */
-
-/* Bit masks for USB_OTG_DEV_CTL */
-
-#define                   SESSION  0x1        /* session indicator */
-#define                  HOST_REQ  0x2        /* Host negotiation request */
-#define                 HOST_MODE  0x4        /* indicates USBDRC is a host */
-#define                     VBUS0  0x8        /* Vbus level indicator[0] */
-#define                     VBUS1  0x10       /* Vbus level indicator[1] */
-#define                     LSDEV  0x20       /* Low-speed indicator */
-#define                     FSDEV  0x40       /* Full or High-speed indicator */
-#define                  B_DEVICE  0x80       /* A' or 'B' device indicator */
-
-/* Bit masks for USB_OTG_VBUS_IRQ */
-
-#define             DRIVE_VBUS_ON  0x1        /* indicator to drive VBUS control circuit */
-#define            DRIVE_VBUS_OFF  0x2        /* indicator to shut off charge pump */
-#define           CHRG_VBUS_START  0x4        /* indicator for external circuit to start charging VBUS */
-#define             CHRG_VBUS_END  0x8        /* indicator for external circuit to end charging VBUS */
-#define        DISCHRG_VBUS_START  0x10       /* indicator to start discharging VBUS */
-#define          DISCHRG_VBUS_END  0x20       /* indicator to stop discharging VBUS */
-
-/* Bit masks for USB_OTG_VBUS_MASK */
-
-#define         DRIVE_VBUS_ON_ENA  0x1        /* enable DRIVE_VBUS_ON interrupt */
-#define        DRIVE_VBUS_OFF_ENA  0x2        /* enable DRIVE_VBUS_OFF interrupt */
-#define       CHRG_VBUS_START_ENA  0x4        /* enable CHRG_VBUS_START interrupt */
-#define         CHRG_VBUS_END_ENA  0x8        /* enable CHRG_VBUS_END interrupt */
-#define    DISCHRG_VBUS_START_ENA  0x10       /* enable DISCHRG_VBUS_START interrupt */
-#define      DISCHRG_VBUS_END_ENA  0x20       /* enable DISCHRG_VBUS_END interrupt */
-
-/* Bit masks for USB_CSR0 */
-
-#define                  RXPKTRDY  0x1        /* data packet receive indicator */
-#define                  TXPKTRDY  0x2        /* data packet in FIFO indicator */
-#define                STALL_SENT  0x4        /* STALL handshake sent */
-#define                   DATAEND  0x8        /* Data end indicator */
-#define                  SETUPEND  0x10       /* Setup end */
-#define                 SENDSTALL  0x20       /* Send STALL handshake */
-#define         SERVICED_RXPKTRDY  0x40       /* used to clear the RxPktRdy bit */
-#define         SERVICED_SETUPEND  0x80       /* used to clear the SetupEnd bit */
-#define                 FLUSHFIFO  0x100      /* flush endpoint FIFO */
-#define          STALL_RECEIVED_H  0x4        /* STALL handshake received host mode */
-#define                SETUPPKT_H  0x8        /* send Setup token host mode */
-#define                   ERROR_H  0x10       /* timeout error indicator host mode */
-#define                  REQPKT_H  0x20       /* Request an IN transaction host mode */
-#define               STATUSPKT_H  0x40       /* Status stage transaction host mode */
-#define             NAK_TIMEOUT_H  0x80       /* EP0 halted after a NAK host mode */
-
-/* Bit masks for USB_COUNT0 */
-
-#define              EP0_RX_COUNT  0x7f       /* number of received bytes in EP0 FIFO */
-
-/* Bit masks for USB_NAKLIMIT0 */
-
-#define             EP0_NAK_LIMIT  0x1f       /* number of frames/micro frames after which EP0 timeouts */
-
-/* Bit masks for USB_TX_MAX_PACKET */
-
-#define         MAX_PACKET_SIZE_T  0x7ff      /* maximum data pay load in a frame */
-
-/* Bit masks for USB_RX_MAX_PACKET */
-
-#define         MAX_PACKET_SIZE_R  0x7ff      /* maximum data pay load in a frame */
-
-/* Bit masks for USB_TXCSR */
-
-#define                TXPKTRDY_T  0x1        /* data packet in FIFO indicator */
-#define          FIFO_NOT_EMPTY_T  0x2        /* FIFO not empty */
-#define                UNDERRUN_T  0x4        /* TxPktRdy not set  for an IN token */
-#define               FLUSHFIFO_T  0x8        /* flush endpoint FIFO */
-#define              STALL_SEND_T  0x10       /* issue a Stall handshake */
-#define              STALL_SENT_T  0x20       /* Stall handshake transmitted */
-#define        CLEAR_DATATOGGLE_T  0x40       /* clear endpoint data toggle */
-#define                INCOMPTX_T  0x80       /* indicates that a large packet is split */
-#define              DMAREQMODE_T  0x400      /* DMA mode (0 or 1) selection */
-#define        FORCE_DATATOGGLE_T  0x800      /* Force data toggle */
-#define              DMAREQ_ENA_T  0x1000     /* Enable DMA request for Tx EP */
-#define                     ISO_T  0x4000     /* enable Isochronous transfers */
-#define                 AUTOSET_T  0x8000     /* allows TxPktRdy to be set automatically */
-#define                  ERROR_TH  0x4        /* error condition host mode */
-#define         STALL_RECEIVED_TH  0x20       /* Stall handshake received host mode */
-#define            NAK_TIMEOUT_TH  0x80       /* NAK timeout host mode */
-
-/* Bit masks for USB_TXCOUNT */
-
-#define                  TX_COUNT  0x1fff     /* Number of bytes to be written to the selected endpoint Tx FIFO */
-
-/* Bit masks for USB_RXCSR */
-
-#define                RXPKTRDY_R  0x1        /* data packet in FIFO indicator */
-#define               FIFO_FULL_R  0x2        /* FIFO not empty */
-#define                 OVERRUN_R  0x4        /* TxPktRdy not set  for an IN token */
-#define               DATAERROR_R  0x8        /* Out packet cannot be loaded into Rx  FIFO */
-#define               FLUSHFIFO_R  0x10       /* flush endpoint FIFO */
-#define              STALL_SEND_R  0x20       /* issue a Stall handshake */
-#define              STALL_SENT_R  0x40       /* Stall handshake transmitted */
-#define        CLEAR_DATATOGGLE_R  0x80       /* clear endpoint data toggle */
-#define                INCOMPRX_R  0x100      /* indicates that a large packet is split */
-#define              DMAREQMODE_R  0x800      /* DMA mode (0 or 1) selection */
-#define                 DISNYET_R  0x1000     /* disable Nyet handshakes */
-#define              DMAREQ_ENA_R  0x2000     /* Enable DMA request for Tx EP */
-#define                     ISO_R  0x4000     /* enable Isochronous transfers */
-#define               AUTOCLEAR_R  0x8000     /* allows TxPktRdy to be set automatically */
-#define                  ERROR_RH  0x4        /* TxPktRdy not set  for an IN token host mode */
-#define                 REQPKT_RH  0x20       /* request an IN transaction host mode */
-#define         STALL_RECEIVED_RH  0x40       /* Stall handshake received host mode */
-#define               INCOMPRX_RH  0x100      /* indicates that a large packet is split host mode */
-#define             DMAREQMODE_RH  0x800      /* DMA mode (0 or 1) selection host mode */
-#define                AUTOREQ_RH  0x4000     /* sets ReqPkt automatically host mode */
-
-/* Bit masks for USB_RXCOUNT */
-
-#define                  RX_COUNT  0x1fff     /* Number of received bytes in the packet in the Rx FIFO */
-
-/* Bit masks for USB_TXTYPE */
-
-#define            TARGET_EP_NO_T  0xf        /* EP number */
-#define                PROTOCOL_T  0xc        /* transfer type */
-
-/* Bit masks for USB_TXINTERVAL */
-
-#define          TX_POLL_INTERVAL  0xff       /* polling interval for selected Tx EP */
-
-/* Bit masks for USB_RXTYPE */
-
-#define            TARGET_EP_NO_R  0xf        /* EP number */
-#define                PROTOCOL_R  0xc        /* transfer type */
-
-/* Bit masks for USB_RXINTERVAL */
-
-#define          RX_POLL_INTERVAL  0xff       /* polling interval for selected Rx EP */
-
-/* Bit masks for USB_DMA_INTERRUPT */
-
-#define                  DMA0_INT  0x1        /* DMA0 pending interrupt */
-#define                  DMA1_INT  0x2        /* DMA1 pending interrupt */
-#define                  DMA2_INT  0x4        /* DMA2 pending interrupt */
-#define                  DMA3_INT  0x8        /* DMA3 pending interrupt */
-#define                  DMA4_INT  0x10       /* DMA4 pending interrupt */
-#define                  DMA5_INT  0x20       /* DMA5 pending interrupt */
-#define                  DMA6_INT  0x40       /* DMA6 pending interrupt */
-#define                  DMA7_INT  0x80       /* DMA7 pending interrupt */
-
-/* Bit masks for USB_DMAxCONTROL */
-
-#define                   DMA_ENA  0x1        /* DMA enable */
-#define                 DIRECTION  0x2        /* direction of DMA transfer */
-#define                      MODE  0x4        /* DMA Bus error */
-#define                   INT_ENA  0x8        /* Interrupt enable */
-#define                     EPNUM  0xf0       /* EP number */
-#define                  BUSERROR  0x100      /* DMA Bus error */
-
-/* Bit masks for USB_DMAxADDRHIGH */
-
-#define             DMA_ADDR_HIGH  0xffff     /* Upper 16-bits of memory source/destination address for the DMA master channel */
-
-/* Bit masks for USB_DMAxADDRLOW */
-
-#define              DMA_ADDR_LOW  0xffff     /* Lower 16-bits of memory source/destination address for the DMA master channel */
-
-/* Bit masks for USB_DMAxCOUNTHIGH */
-
-#define            DMA_COUNT_HIGH  0xffff     /* Upper 16-bits of byte count of DMA transfer for DMA master channel */
-
-/* Bit masks for USB_DMAxCOUNTLOW */
-
-#define             DMA_COUNT_LOW  0xffff     /* Lower 16-bits of byte count of DMA transfer for DMA master channel */
-
-/* Bit masks for HMDMAx_CONTROL */
-
-#define                   HMDMAEN  0x1        /* Handshake MDMA Enable */
-#define                       REP  0x2        /* Handshake MDMA Request Polarity */
-#define                       UTE  0x8        /* Urgency Threshold Enable */
-#define                       OIE  0x10       /* Overflow Interrupt Enable */
-#define                      BDIE  0x20       /* Block Done Interrupt Enable */
-#define                      MBDI  0x40       /* Mask Block Done Interrupt */
-#define                       DRQ  0x300      /* Handshake MDMA Request Type */
-#define                       RBC  0x1000     /* Force Reload of BCOUNT */
-#define                        PS  0x2000     /* Pin Status */
-#define                        OI  0x4000     /* Overflow Interrupt Generated */
-#define                       BDI  0x8000     /* Block Done Interrupt Generated */
-
-/* ******************************************* */
-/*     MULTI BIT MACRO ENUMERATIONS            */
-/* ******************************************* */
-
-
 #endif /* _DEF_BF548_H */
diff --git a/arch/blackfin/mach-bf548/include/mach/defBF549.h b/arch/blackfin/mach-bf548/include/mach/defBF549.h
index f7f043560c6f..5a04e6d4017e 100644
--- a/arch/blackfin/mach-bf548/include/mach/defBF549.h
+++ b/arch/blackfin/mach-bf548/include/mach/defBF549.h
@@ -10,121 +10,13 @@
 /* Include all Core registers and bit definitions */
 #include <asm/def_LPBlackfin.h>
 
-
 /* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF549 */
 
 /* Include defBF54x_base.h for the set of #defines that are common to all ADSP-BF54x processors */
 #include "defBF54x_base.h"
 
-/* The following are the #defines needed by ADSP-BF549 that are not in the common header */
-
-/* Timer Registers */
-
-#define                    TIMER8_CONFIG  0xffc00600   /* Timer 8 Configuration Register */
-#define                   TIMER8_COUNTER  0xffc00604   /* Timer 8 Counter Register */
-#define                    TIMER8_PERIOD  0xffc00608   /* Timer 8 Period Register */
-#define                     TIMER8_WIDTH  0xffc0060c   /* Timer 8 Width Register */
-#define                    TIMER9_CONFIG  0xffc00610   /* Timer 9 Configuration Register */
-#define                   TIMER9_COUNTER  0xffc00614   /* Timer 9 Counter Register */
-#define                    TIMER9_PERIOD  0xffc00618   /* Timer 9 Period Register */
-#define                     TIMER9_WIDTH  0xffc0061c   /* Timer 9 Width Register */
-#define                   TIMER10_CONFIG  0xffc00620   /* Timer 10 Configuration Register */
-#define                  TIMER10_COUNTER  0xffc00624   /* Timer 10 Counter Register */
-#define                   TIMER10_PERIOD  0xffc00628   /* Timer 10 Period Register */
-#define                    TIMER10_WIDTH  0xffc0062c   /* Timer 10 Width Register */
-
-/* Timer Group of 3 Registers */
-
-#define                    TIMER_ENABLE1  0xffc00640   /* Timer Group of 3 Enable Register */
-#define                   TIMER_DISABLE1  0xffc00644   /* Timer Group of 3 Disable Register */
-#define                    TIMER_STATUS1  0xffc00648   /* Timer Group of 3 Status Register */
-
-/* SPORT0 Registers */
-
-#define                      SPORT0_TCR1  0xffc00800   /* SPORT0 Transmit Configuration 1 Register */
-#define                      SPORT0_TCR2  0xffc00804   /* SPORT0 Transmit Configuration 2 Register */
-#define                   SPORT0_TCLKDIV  0xffc00808   /* SPORT0 Transmit Serial Clock Divider Register */
-#define                    SPORT0_TFSDIV  0xffc0080c   /* SPORT0 Transmit Frame Sync Divider Register */
-#define                        SPORT0_TX  0xffc00810   /* SPORT0 Transmit Data Register */
-#define                        SPORT0_RX  0xffc00818   /* SPORT0 Receive Data Register */
-#define                      SPORT0_RCR1  0xffc00820   /* SPORT0 Receive Configuration 1 Register */
-#define                      SPORT0_RCR2  0xffc00824   /* SPORT0 Receive Configuration 2 Register */
-#define                   SPORT0_RCLKDIV  0xffc00828   /* SPORT0 Receive Serial Clock Divider Register */
-#define                    SPORT0_RFSDIV  0xffc0082c   /* SPORT0 Receive Frame Sync Divider Register */
-#define                      SPORT0_STAT  0xffc00830   /* SPORT0 Status Register */
-#define                      SPORT0_CHNL  0xffc00834   /* SPORT0 Current Channel Register */
-#define                     SPORT0_MCMC1  0xffc00838   /* SPORT0 Multi channel Configuration Register 1 */
-#define                     SPORT0_MCMC2  0xffc0083c   /* SPORT0 Multi channel Configuration Register 2 */
-#define                     SPORT0_MTCS0  0xffc00840   /* SPORT0 Multi channel Transmit Select Register 0 */
-#define                     SPORT0_MTCS1  0xffc00844   /* SPORT0 Multi channel Transmit Select Register 1 */
-#define                     SPORT0_MTCS2  0xffc00848   /* SPORT0 Multi channel Transmit Select Register 2 */
-#define                     SPORT0_MTCS3  0xffc0084c   /* SPORT0 Multi channel Transmit Select Register 3 */
-#define                     SPORT0_MRCS0  0xffc00850   /* SPORT0 Multi channel Receive Select Register 0 */
-#define                     SPORT0_MRCS1  0xffc00854   /* SPORT0 Multi channel Receive Select Register 1 */
-#define                     SPORT0_MRCS2  0xffc00858   /* SPORT0 Multi channel Receive Select Register 2 */
-#define                     SPORT0_MRCS3  0xffc0085c   /* SPORT0 Multi channel Receive Select Register 3 */
-
-/* EPPI0 Registers */
-
-#define                     EPPI0_STATUS  0xffc01000   /* EPPI0 Status Register */
-#define                     EPPI0_HCOUNT  0xffc01004   /* EPPI0 Horizontal Transfer Count Register */
-#define                     EPPI0_HDELAY  0xffc01008   /* EPPI0 Horizontal Delay Count Register */
-#define                     EPPI0_VCOUNT  0xffc0100c   /* EPPI0 Vertical Transfer Count Register */
-#define                     EPPI0_VDELAY  0xffc01010   /* EPPI0 Vertical Delay Count Register */
-#define                      EPPI0_FRAME  0xffc01014   /* EPPI0 Lines per Frame Register */
-#define                       EPPI0_LINE  0xffc01018   /* EPPI0 Samples per Line Register */
-#define                     EPPI0_CLKDIV  0xffc0101c   /* EPPI0 Clock Divide Register */
-#define                    EPPI0_CONTROL  0xffc01020   /* EPPI0 Control Register */
-#define                   EPPI0_FS1W_HBL  0xffc01024   /* EPPI0 FS1 Width Register / EPPI0 Horizontal Blanking Samples Per Line Register */
-#define                  EPPI0_FS1P_AVPL  0xffc01028   /* EPPI0 FS1 Period Register / EPPI0 Active Video Samples Per Line Register */
-#define                   EPPI0_FS2W_LVB  0xffc0102c   /* EPPI0 FS2 Width Register / EPPI0 Lines of Vertical Blanking Register */
-#define                  EPPI0_FS2P_LAVF  0xffc01030   /* EPPI0 FS2 Period Register/ EPPI0 Lines of Active Video Per Field Register */
-#define                       EPPI0_CLIP  0xffc01034   /* EPPI0 Clipping Register */
-
-/* UART2 Registers */
-
-#define                        UART2_DLL  0xffc02100   /* Divisor Latch Low Byte */
-#define                        UART2_DLH  0xffc02104   /* Divisor Latch High Byte */
-#define                       UART2_GCTL  0xffc02108   /* Global Control Register */
-#define                        UART2_LCR  0xffc0210c   /* Line Control Register */
-#define                        UART2_MCR  0xffc02110   /* Modem Control Register */
-#define                        UART2_LSR  0xffc02114   /* Line Status Register */
-#define                        UART2_MSR  0xffc02118   /* Modem Status Register */
-#define                        UART2_SCR  0xffc0211c   /* Scratch Register */
-#define                    UART2_IER_SET  0xffc02120   /* Interrupt Enable Register Set */
-#define                  UART2_IER_CLEAR  0xffc02124   /* Interrupt Enable Register Clear */
-#define                        UART2_RBR  0xffc0212c   /* Receive Buffer Register */
-
-/* Two Wire Interface Registers (TWI1) */
-
-#define                     TWI1_REGBASE  0xffc02200
-#define                      TWI1_CLKDIV  0xffc02200   /* Clock Divider Register */
-#define                     TWI1_CONTROL  0xffc02204   /* TWI Control Register */
-#define                  TWI1_SLAVE_CTRL  0xffc02208   /* TWI Slave Mode Control Register */
-#define                  TWI1_SLAVE_STAT  0xffc0220c   /* TWI Slave Mode Status Register */
-#define                  TWI1_SLAVE_ADDR  0xffc02210   /* TWI Slave Mode Address Register */
-#define                 TWI1_MASTER_CTRL  0xffc02214   /* TWI Master Mode Control Register */
-#define                 TWI1_MASTER_STAT  0xffc02218   /* TWI Master Mode Status Register */
-#define                 TWI1_MASTER_ADDR  0xffc0221c   /* TWI Master Mode Address Register */
-#define                    TWI1_INT_STAT  0xffc02220   /* TWI Interrupt Status Register */
-#define                    TWI1_INT_MASK  0xffc02224   /* TWI Interrupt Mask Register */
-#define                   TWI1_FIFO_CTRL  0xffc02228   /* TWI FIFO Control Register */
-#define                   TWI1_FIFO_STAT  0xffc0222c   /* TWI FIFO Status Register */
-#define                   TWI1_XMT_DATA8  0xffc02280   /* TWI FIFO Transmit Data Single Byte Register */
-#define                  TWI1_XMT_DATA16  0xffc02284   /* TWI FIFO Transmit Data Double Byte Register */
-#define                   TWI1_RCV_DATA8  0xffc02288   /* TWI FIFO Receive Data Single Byte Register */
-#define                  TWI1_RCV_DATA16  0xffc0228c   /* TWI FIFO Receive Data Double Byte Register */
-
-/* SPI2  Registers */
-
-#define                     SPI2_REGBASE  0xffc02400
-#define                         SPI2_CTL  0xffc02400   /* SPI2 Control Register */
-#define                         SPI2_FLG  0xffc02404   /* SPI2 Flag Register */
-#define                        SPI2_STAT  0xffc02408   /* SPI2 Status Register */
-#define                        SPI2_TDBR  0xffc0240c   /* SPI2 Transmit Data Buffer Register */
-#define                        SPI2_RDBR  0xffc02410   /* SPI2 Receive Data Buffer Register */
-#define                        SPI2_BAUD  0xffc02414   /* SPI2 Baud Rate Register */
-#define                      SPI2_SHADOW  0xffc02418   /* SPI2 Receive Data Buffer Shadow Register */
+/* The BF549 is like the BF544, but has MXVR */
+#include "defBF547.h"
 
 /* MXVR Registers */
 
@@ -296,2418 +188,4 @@
 #define                     MXVR_PIN_CTL  0xffc028dc   /* MXVR Pin Control Register */
 #define                    MXVR_SCLK_CNT  0xffc028e0   /* MXVR System Clock Counter Register */
 
-/* CAN Controller 1 Config 1 Registers */
-
-#define                         CAN1_MC1  0xffc03200   /* CAN Controller 1 Mailbox Configuration Register 1 */
-#define                         CAN1_MD1  0xffc03204   /* CAN Controller 1 Mailbox Direction Register 1 */
-#define                        CAN1_TRS1  0xffc03208   /* CAN Controller 1 Transmit Request Set Register 1 */
-#define                        CAN1_TRR1  0xffc0320c   /* CAN Controller 1 Transmit Request Reset Register 1 */
-#define                         CAN1_TA1  0xffc03210   /* CAN Controller 1 Transmit Acknowledge Register 1 */
-#define                         CAN1_AA1  0xffc03214   /* CAN Controller 1 Abort Acknowledge Register 1 */
-#define                        CAN1_RMP1  0xffc03218   /* CAN Controller 1 Receive Message Pending Register 1 */
-#define                        CAN1_RML1  0xffc0321c   /* CAN Controller 1 Receive Message Lost Register 1 */
-#define                      CAN1_MBTIF1  0xffc03220   /* CAN Controller 1 Mailbox Transmit Interrupt Flag Register 1 */
-#define                      CAN1_MBRIF1  0xffc03224   /* CAN Controller 1 Mailbox Receive Interrupt Flag Register 1 */
-#define                       CAN1_MBIM1  0xffc03228   /* CAN Controller 1 Mailbox Interrupt Mask Register 1 */
-#define                        CAN1_RFH1  0xffc0322c   /* CAN Controller 1 Remote Frame Handling Enable Register 1 */
-#define                       CAN1_OPSS1  0xffc03230   /* CAN Controller 1 Overwrite Protection Single Shot Transmit Register 1 */
-
-/* CAN Controller 1 Config 2 Registers */
-
-#define                         CAN1_MC2  0xffc03240   /* CAN Controller 1 Mailbox Configuration Register 2 */
-#define                         CAN1_MD2  0xffc03244   /* CAN Controller 1 Mailbox Direction Register 2 */
-#define                        CAN1_TRS2  0xffc03248   /* CAN Controller 1 Transmit Request Set Register 2 */
-#define                        CAN1_TRR2  0xffc0324c   /* CAN Controller 1 Transmit Request Reset Register 2 */
-#define                         CAN1_TA2  0xffc03250   /* CAN Controller 1 Transmit Acknowledge Register 2 */
-#define                         CAN1_AA2  0xffc03254   /* CAN Controller 1 Abort Acknowledge Register 2 */
-#define                        CAN1_RMP2  0xffc03258   /* CAN Controller 1 Receive Message Pending Register 2 */
-#define                        CAN1_RML2  0xffc0325c   /* CAN Controller 1 Receive Message Lost Register 2 */
-#define                      CAN1_MBTIF2  0xffc03260   /* CAN Controller 1 Mailbox Transmit Interrupt Flag Register 2 */
-#define                      CAN1_MBRIF2  0xffc03264   /* CAN Controller 1 Mailbox Receive Interrupt Flag Register 2 */
-#define                       CAN1_MBIM2  0xffc03268   /* CAN Controller 1 Mailbox Interrupt Mask Register 2 */
-#define                        CAN1_RFH2  0xffc0326c   /* CAN Controller 1 Remote Frame Handling Enable Register 2 */
-#define                       CAN1_OPSS2  0xffc03270   /* CAN Controller 1 Overwrite Protection Single Shot Transmit Register 2 */
-
-/* CAN Controller 1 Clock/Interrupt/Counter Registers */
-
-#define                       CAN1_CLOCK  0xffc03280   /* CAN Controller 1 Clock Register */
-#define                      CAN1_TIMING  0xffc03284   /* CAN Controller 1 Timing Register */
-#define                       CAN1_DEBUG  0xffc03288   /* CAN Controller 1 Debug Register */
-#define                      CAN1_STATUS  0xffc0328c   /* CAN Controller 1 Global Status Register */
-#define                         CAN1_CEC  0xffc03290   /* CAN Controller 1 Error Counter Register */
-#define                         CAN1_GIS  0xffc03294   /* CAN Controller 1 Global Interrupt Status Register */
-#define                         CAN1_GIM  0xffc03298   /* CAN Controller 1 Global Interrupt Mask Register */
-#define                         CAN1_GIF  0xffc0329c   /* CAN Controller 1 Global Interrupt Flag Register */
-#define                     CAN1_CONTROL  0xffc032a0   /* CAN Controller 1 Master Control Register */
-#define                        CAN1_INTR  0xffc032a4   /* CAN Controller 1 Interrupt Pending Register */
-#define                        CAN1_MBTD  0xffc032ac   /* CAN Controller 1 Mailbox Temporary Disable Register */
-#define                         CAN1_EWR  0xffc032b0   /* CAN Controller 1 Programmable Warning Level Register */
-#define                         CAN1_ESR  0xffc032b4   /* CAN Controller 1 Error Status Register */
-#define                       CAN1_UCCNT  0xffc032c4   /* CAN Controller 1 Universal Counter Register */
-#define                        CAN1_UCRC  0xffc032c8   /* CAN Controller 1 Universal Counter Force Reload Register */
-#define                       CAN1_UCCNF  0xffc032cc   /* CAN Controller 1 Universal Counter Configuration Register */
-
-/* CAN Controller 1 Mailbox Acceptance Registers */
-
-#define                       CAN1_AM00L  0xffc03300   /* CAN Controller 1 Mailbox 0 Acceptance Mask High Register */
-#define                       CAN1_AM00H  0xffc03304   /* CAN Controller 1 Mailbox 0 Acceptance Mask Low Register */
-#define                       CAN1_AM01L  0xffc03308   /* CAN Controller 1 Mailbox 1 Acceptance Mask High Register */
-#define                       CAN1_AM01H  0xffc0330c   /* CAN Controller 1 Mailbox 1 Acceptance Mask Low Register */
-#define                       CAN1_AM02L  0xffc03310   /* CAN Controller 1 Mailbox 2 Acceptance Mask High Register */
-#define                       CAN1_AM02H  0xffc03314   /* CAN Controller 1 Mailbox 2 Acceptance Mask Low Register */
-#define                       CAN1_AM03L  0xffc03318   /* CAN Controller 1 Mailbox 3 Acceptance Mask High Register */
-#define                       CAN1_AM03H  0xffc0331c   /* CAN Controller 1 Mailbox 3 Acceptance Mask Low Register */
-#define                       CAN1_AM04L  0xffc03320   /* CAN Controller 1 Mailbox 4 Acceptance Mask High Register */
-#define                       CAN1_AM04H  0xffc03324   /* CAN Controller 1 Mailbox 4 Acceptance Mask Low Register */
-#define                       CAN1_AM05L  0xffc03328   /* CAN Controller 1 Mailbox 5 Acceptance Mask High Register */
-#define                       CAN1_AM05H  0xffc0332c   /* CAN Controller 1 Mailbox 5 Acceptance Mask Low Register */
-#define                       CAN1_AM06L  0xffc03330   /* CAN Controller 1 Mailbox 6 Acceptance Mask High Register */
-#define                       CAN1_AM06H  0xffc03334   /* CAN Controller 1 Mailbox 6 Acceptance Mask Low Register */
-#define                       CAN1_AM07L  0xffc03338   /* CAN Controller 1 Mailbox 7 Acceptance Mask High Register */
-#define                       CAN1_AM07H  0xffc0333c   /* CAN Controller 1 Mailbox 7 Acceptance Mask Low Register */
-#define                       CAN1_AM08L  0xffc03340   /* CAN Controller 1 Mailbox 8 Acceptance Mask High Register */
-#define                       CAN1_AM08H  0xffc03344   /* CAN Controller 1 Mailbox 8 Acceptance Mask Low Register */
-#define                       CAN1_AM09L  0xffc03348   /* CAN Controller 1 Mailbox 9 Acceptance Mask High Register */
-#define                       CAN1_AM09H  0xffc0334c   /* CAN Controller 1 Mailbox 9 Acceptance Mask Low Register */
-#define                       CAN1_AM10L  0xffc03350   /* CAN Controller 1 Mailbox 10 Acceptance Mask High Register */
-#define                       CAN1_AM10H  0xffc03354   /* CAN Controller 1 Mailbox 10 Acceptance Mask Low Register */
-#define                       CAN1_AM11L  0xffc03358   /* CAN Controller 1 Mailbox 11 Acceptance Mask High Register */
-#define                       CAN1_AM11H  0xffc0335c   /* CAN Controller 1 Mailbox 11 Acceptance Mask Low Register */
-#define                       CAN1_AM12L  0xffc03360   /* CAN Controller 1 Mailbox 12 Acceptance Mask High Register */
-#define                       CAN1_AM12H  0xffc03364   /* CAN Controller 1 Mailbox 12 Acceptance Mask Low Register */
-#define                       CAN1_AM13L  0xffc03368   /* CAN Controller 1 Mailbox 13 Acceptance Mask High Register */
-#define                       CAN1_AM13H  0xffc0336c   /* CAN Controller 1 Mailbox 13 Acceptance Mask Low Register */
-#define                       CAN1_AM14L  0xffc03370   /* CAN Controller 1 Mailbox 14 Acceptance Mask High Register */
-#define                       CAN1_AM14H  0xffc03374   /* CAN Controller 1 Mailbox 14 Acceptance Mask Low Register */
-#define                       CAN1_AM15L  0xffc03378   /* CAN Controller 1 Mailbox 15 Acceptance Mask High Register */
-#define                       CAN1_AM15H  0xffc0337c   /* CAN Controller 1 Mailbox 15 Acceptance Mask Low Register */
-
-/* CAN Controller 1 Mailbox Acceptance Registers */
-
-#define                       CAN1_AM16L  0xffc03380   /* CAN Controller 1 Mailbox 16 Acceptance Mask High Register */
-#define                       CAN1_AM16H  0xffc03384   /* CAN Controller 1 Mailbox 16 Acceptance Mask Low Register */
-#define                       CAN1_AM17L  0xffc03388   /* CAN Controller 1 Mailbox 17 Acceptance Mask High Register */
-#define                       CAN1_AM17H  0xffc0338c   /* CAN Controller 1 Mailbox 17 Acceptance Mask Low Register */
-#define                       CAN1_AM18L  0xffc03390   /* CAN Controller 1 Mailbox 18 Acceptance Mask High Register */
-#define                       CAN1_AM18H  0xffc03394   /* CAN Controller 1 Mailbox 18 Acceptance Mask Low Register */
-#define                       CAN1_AM19L  0xffc03398   /* CAN Controller 1 Mailbox 19 Acceptance Mask High Register */
-#define                       CAN1_AM19H  0xffc0339c   /* CAN Controller 1 Mailbox 19 Acceptance Mask Low Register */
-#define                       CAN1_AM20L  0xffc033a0   /* CAN Controller 1 Mailbox 20 Acceptance Mask High Register */
-#define                       CAN1_AM20H  0xffc033a4   /* CAN Controller 1 Mailbox 20 Acceptance Mask Low Register */
-#define                       CAN1_AM21L  0xffc033a8   /* CAN Controller 1 Mailbox 21 Acceptance Mask High Register */
-#define                       CAN1_AM21H  0xffc033ac   /* CAN Controller 1 Mailbox 21 Acceptance Mask Low Register */
-#define                       CAN1_AM22L  0xffc033b0   /* CAN Controller 1 Mailbox 22 Acceptance Mask High Register */
-#define                       CAN1_AM22H  0xffc033b4   /* CAN Controller 1 Mailbox 22 Acceptance Mask Low Register */
-#define                       CAN1_AM23L  0xffc033b8   /* CAN Controller 1 Mailbox 23 Acceptance Mask High Register */
-#define                       CAN1_AM23H  0xffc033bc   /* CAN Controller 1 Mailbox 23 Acceptance Mask Low Register */
-#define                       CAN1_AM24L  0xffc033c0   /* CAN Controller 1 Mailbox 24 Acceptance Mask High Register */
-#define                       CAN1_AM24H  0xffc033c4   /* CAN Controller 1 Mailbox 24 Acceptance Mask Low Register */
-#define                       CAN1_AM25L  0xffc033c8   /* CAN Controller 1 Mailbox 25 Acceptance Mask High Register */
-#define                       CAN1_AM25H  0xffc033cc   /* CAN Controller 1 Mailbox 25 Acceptance Mask Low Register */
-#define                       CAN1_AM26L  0xffc033d0   /* CAN Controller 1 Mailbox 26 Acceptance Mask High Register */
-#define                       CAN1_AM26H  0xffc033d4   /* CAN Controller 1 Mailbox 26 Acceptance Mask Low Register */
-#define                       CAN1_AM27L  0xffc033d8   /* CAN Controller 1 Mailbox 27 Acceptance Mask High Register */
-#define                       CAN1_AM27H  0xffc033dc   /* CAN Controller 1 Mailbox 27 Acceptance Mask Low Register */
-#define                       CAN1_AM28L  0xffc033e0   /* CAN Controller 1 Mailbox 28 Acceptance Mask High Register */
-#define                       CAN1_AM28H  0xffc033e4   /* CAN Controller 1 Mailbox 28 Acceptance Mask Low Register */
-#define                       CAN1_AM29L  0xffc033e8   /* CAN Controller 1 Mailbox 29 Acceptance Mask High Register */
-#define                       CAN1_AM29H  0xffc033ec   /* CAN Controller 1 Mailbox 29 Acceptance Mask Low Register */
-#define                       CAN1_AM30L  0xffc033f0   /* CAN Controller 1 Mailbox 30 Acceptance Mask High Register */
-#define                       CAN1_AM30H  0xffc033f4   /* CAN Controller 1 Mailbox 30 Acceptance Mask Low Register */
-#define                       CAN1_AM31L  0xffc033f8   /* CAN Controller 1 Mailbox 31 Acceptance Mask High Register */
-#define                       CAN1_AM31H  0xffc033fc   /* CAN Controller 1 Mailbox 31 Acceptance Mask Low Register */
-
-/* CAN Controller 1 Mailbox Data Registers */
-
-#define                  CAN1_MB00_DATA0  0xffc03400   /* CAN Controller 1 Mailbox 0 Data 0 Register */
-#define                  CAN1_MB00_DATA1  0xffc03404   /* CAN Controller 1 Mailbox 0 Data 1 Register */
-#define                  CAN1_MB00_DATA2  0xffc03408   /* CAN Controller 1 Mailbox 0 Data 2 Register */
-#define                  CAN1_MB00_DATA3  0xffc0340c   /* CAN Controller 1 Mailbox 0 Data 3 Register */
-#define                 CAN1_MB00_LENGTH  0xffc03410   /* CAN Controller 1 Mailbox 0 Length Register */
-#define              CAN1_MB00_TIMESTAMP  0xffc03414   /* CAN Controller 1 Mailbox 0 Timestamp Register */
-#define                    CAN1_MB00_ID0  0xffc03418   /* CAN Controller 1 Mailbox 0 ID0 Register */
-#define                    CAN1_MB00_ID1  0xffc0341c   /* CAN Controller 1 Mailbox 0 ID1 Register */
-#define                  CAN1_MB01_DATA0  0xffc03420   /* CAN Controller 1 Mailbox 1 Data 0 Register */
-#define                  CAN1_MB01_DATA1  0xffc03424   /* CAN Controller 1 Mailbox 1 Data 1 Register */
-#define                  CAN1_MB01_DATA2  0xffc03428   /* CAN Controller 1 Mailbox 1 Data 2 Register */
-#define                  CAN1_MB01_DATA3  0xffc0342c   /* CAN Controller 1 Mailbox 1 Data 3 Register */
-#define                 CAN1_MB01_LENGTH  0xffc03430   /* CAN Controller 1 Mailbox 1 Length Register */
-#define              CAN1_MB01_TIMESTAMP  0xffc03434   /* CAN Controller 1 Mailbox 1 Timestamp Register */
-#define                    CAN1_MB01_ID0  0xffc03438   /* CAN Controller 1 Mailbox 1 ID0 Register */
-#define                    CAN1_MB01_ID1  0xffc0343c   /* CAN Controller 1 Mailbox 1 ID1 Register */
-#define                  CAN1_MB02_DATA0  0xffc03440   /* CAN Controller 1 Mailbox 2 Data 0 Register */
-#define                  CAN1_MB02_DATA1  0xffc03444   /* CAN Controller 1 Mailbox 2 Data 1 Register */
-#define                  CAN1_MB02_DATA2  0xffc03448   /* CAN Controller 1 Mailbox 2 Data 2 Register */
-#define                  CAN1_MB02_DATA3  0xffc0344c   /* CAN Controller 1 Mailbox 2 Data 3 Register */
-#define                 CAN1_MB02_LENGTH  0xffc03450   /* CAN Controller 1 Mailbox 2 Length Register */
-#define              CAN1_MB02_TIMESTAMP  0xffc03454   /* CAN Controller 1 Mailbox 2 Timestamp Register */
-#define                    CAN1_MB02_ID0  0xffc03458   /* CAN Controller 1 Mailbox 2 ID0 Register */
-#define                    CAN1_MB02_ID1  0xffc0345c   /* CAN Controller 1 Mailbox 2 ID1 Register */
-#define                  CAN1_MB03_DATA0  0xffc03460   /* CAN Controller 1 Mailbox 3 Data 0 Register */
-#define                  CAN1_MB03_DATA1  0xffc03464   /* CAN Controller 1 Mailbox 3 Data 1 Register */
-#define                  CAN1_MB03_DATA2  0xffc03468   /* CAN Controller 1 Mailbox 3 Data 2 Register */
-#define                  CAN1_MB03_DATA3  0xffc0346c   /* CAN Controller 1 Mailbox 3 Data 3 Register */
-#define                 CAN1_MB03_LENGTH  0xffc03470   /* CAN Controller 1 Mailbox 3 Length Register */
-#define              CAN1_MB03_TIMESTAMP  0xffc03474   /* CAN Controller 1 Mailbox 3 Timestamp Register */
-#define                    CAN1_MB03_ID0  0xffc03478   /* CAN Controller 1 Mailbox 3 ID0 Register */
-#define                    CAN1_MB03_ID1  0xffc0347c   /* CAN Controller 1 Mailbox 3 ID1 Register */
-#define                  CAN1_MB04_DATA0  0xffc03480   /* CAN Controller 1 Mailbox 4 Data 0 Register */
-#define                  CAN1_MB04_DATA1  0xffc03484   /* CAN Controller 1 Mailbox 4 Data 1 Register */
-#define                  CAN1_MB04_DATA2  0xffc03488   /* CAN Controller 1 Mailbox 4 Data 2 Register */
-#define                  CAN1_MB04_DATA3  0xffc0348c   /* CAN Controller 1 Mailbox 4 Data 3 Register */
-#define                 CAN1_MB04_LENGTH  0xffc03490   /* CAN Controller 1 Mailbox 4 Length Register */
-#define              CAN1_MB04_TIMESTAMP  0xffc03494   /* CAN Controller 1 Mailbox 4 Timestamp Register */
-#define                    CAN1_MB04_ID0  0xffc03498   /* CAN Controller 1 Mailbox 4 ID0 Register */
-#define                    CAN1_MB04_ID1  0xffc0349c   /* CAN Controller 1 Mailbox 4 ID1 Register */
-#define                  CAN1_MB05_DATA0  0xffc034a0   /* CAN Controller 1 Mailbox 5 Data 0 Register */
-#define                  CAN1_MB05_DATA1  0xffc034a4   /* CAN Controller 1 Mailbox 5 Data 1 Register */
-#define                  CAN1_MB05_DATA2  0xffc034a8   /* CAN Controller 1 Mailbox 5 Data 2 Register */
-#define                  CAN1_MB05_DATA3  0xffc034ac   /* CAN Controller 1 Mailbox 5 Data 3 Register */
-#define                 CAN1_MB05_LENGTH  0xffc034b0   /* CAN Controller 1 Mailbox 5 Length Register */
-#define              CAN1_MB05_TIMESTAMP  0xffc034b4   /* CAN Controller 1 Mailbox 5 Timestamp Register */
-#define                    CAN1_MB05_ID0  0xffc034b8   /* CAN Controller 1 Mailbox 5 ID0 Register */
-#define                    CAN1_MB05_ID1  0xffc034bc   /* CAN Controller 1 Mailbox 5 ID1 Register */
-#define                  CAN1_MB06_DATA0  0xffc034c0   /* CAN Controller 1 Mailbox 6 Data 0 Register */
-#define                  CAN1_MB06_DATA1  0xffc034c4   /* CAN Controller 1 Mailbox 6 Data 1 Register */
-#define                  CAN1_MB06_DATA2  0xffc034c8   /* CAN Controller 1 Mailbox 6 Data 2 Register */
-#define                  CAN1_MB06_DATA3  0xffc034cc   /* CAN Controller 1 Mailbox 6 Data 3 Register */
-#define                 CAN1_MB06_LENGTH  0xffc034d0   /* CAN Controller 1 Mailbox 6 Length Register */
-#define              CAN1_MB06_TIMESTAMP  0xffc034d4   /* CAN Controller 1 Mailbox 6 Timestamp Register */
-#define                    CAN1_MB06_ID0  0xffc034d8   /* CAN Controller 1 Mailbox 6 ID0 Register */
-#define                    CAN1_MB06_ID1  0xffc034dc   /* CAN Controller 1 Mailbox 6 ID1 Register */
-#define                  CAN1_MB07_DATA0  0xffc034e0   /* CAN Controller 1 Mailbox 7 Data 0 Register */
-#define                  CAN1_MB07_DATA1  0xffc034e4   /* CAN Controller 1 Mailbox 7 Data 1 Register */
-#define                  CAN1_MB07_DATA2  0xffc034e8   /* CAN Controller 1 Mailbox 7 Data 2 Register */
-#define                  CAN1_MB07_DATA3  0xffc034ec   /* CAN Controller 1 Mailbox 7 Data 3 Register */
-#define                 CAN1_MB07_LENGTH  0xffc034f0   /* CAN Controller 1 Mailbox 7 Length Register */
-#define              CAN1_MB07_TIMESTAMP  0xffc034f4   /* CAN Controller 1 Mailbox 7 Timestamp Register */
-#define                    CAN1_MB07_ID0  0xffc034f8   /* CAN Controller 1 Mailbox 7 ID0 Register */
-#define                    CAN1_MB07_ID1  0xffc034fc   /* CAN Controller 1 Mailbox 7 ID1 Register */
-#define                  CAN1_MB08_DATA0  0xffc03500   /* CAN Controller 1 Mailbox 8 Data 0 Register */
-#define                  CAN1_MB08_DATA1  0xffc03504   /* CAN Controller 1 Mailbox 8 Data 1 Register */
-#define                  CAN1_MB08_DATA2  0xffc03508   /* CAN Controller 1 Mailbox 8 Data 2 Register */
-#define                  CAN1_MB08_DATA3  0xffc0350c   /* CAN Controller 1 Mailbox 8 Data 3 Register */
-#define                 CAN1_MB08_LENGTH  0xffc03510   /* CAN Controller 1 Mailbox 8 Length Register */
-#define              CAN1_MB08_TIMESTAMP  0xffc03514   /* CAN Controller 1 Mailbox 8 Timestamp Register */
-#define                    CAN1_MB08_ID0  0xffc03518   /* CAN Controller 1 Mailbox 8 ID0 Register */
-#define                    CAN1_MB08_ID1  0xffc0351c   /* CAN Controller 1 Mailbox 8 ID1 Register */
-#define                  CAN1_MB09_DATA0  0xffc03520   /* CAN Controller 1 Mailbox 9 Data 0 Register */
-#define                  CAN1_MB09_DATA1  0xffc03524   /* CAN Controller 1 Mailbox 9 Data 1 Register */
-#define                  CAN1_MB09_DATA2  0xffc03528   /* CAN Controller 1 Mailbox 9 Data 2 Register */
-#define                  CAN1_MB09_DATA3  0xffc0352c   /* CAN Controller 1 Mailbox 9 Data 3 Register */
-#define                 CAN1_MB09_LENGTH  0xffc03530   /* CAN Controller 1 Mailbox 9 Length Register */
-#define              CAN1_MB09_TIMESTAMP  0xffc03534   /* CAN Controller 1 Mailbox 9 Timestamp Register */
-#define                    CAN1_MB09_ID0  0xffc03538   /* CAN Controller 1 Mailbox 9 ID0 Register */
-#define                    CAN1_MB09_ID1  0xffc0353c   /* CAN Controller 1 Mailbox 9 ID1 Register */
-#define                  CAN1_MB10_DATA0  0xffc03540   /* CAN Controller 1 Mailbox 10 Data 0 Register */
-#define                  CAN1_MB10_DATA1  0xffc03544   /* CAN Controller 1 Mailbox 10 Data 1 Register */
-#define                  CAN1_MB10_DATA2  0xffc03548   /* CAN Controller 1 Mailbox 10 Data 2 Register */
-#define                  CAN1_MB10_DATA3  0xffc0354c   /* CAN Controller 1 Mailbox 10 Data 3 Register */
-#define                 CAN1_MB10_LENGTH  0xffc03550   /* CAN Controller 1 Mailbox 10 Length Register */
-#define              CAN1_MB10_TIMESTAMP  0xffc03554   /* CAN Controller 1 Mailbox 10 Timestamp Register */
-#define                    CAN1_MB10_ID0  0xffc03558   /* CAN Controller 1 Mailbox 10 ID0 Register */
-#define                    CAN1_MB10_ID1  0xffc0355c   /* CAN Controller 1 Mailbox 10 ID1 Register */
-#define                  CAN1_MB11_DATA0  0xffc03560   /* CAN Controller 1 Mailbox 11 Data 0 Register */
-#define                  CAN1_MB11_DATA1  0xffc03564   /* CAN Controller 1 Mailbox 11 Data 1 Register */
-#define                  CAN1_MB11_DATA2  0xffc03568   /* CAN Controller 1 Mailbox 11 Data 2 Register */
-#define                  CAN1_MB11_DATA3  0xffc0356c   /* CAN Controller 1 Mailbox 11 Data 3 Register */
-#define                 CAN1_MB11_LENGTH  0xffc03570   /* CAN Controller 1 Mailbox 11 Length Register */
-#define              CAN1_MB11_TIMESTAMP  0xffc03574   /* CAN Controller 1 Mailbox 11 Timestamp Register */
-#define                    CAN1_MB11_ID0  0xffc03578   /* CAN Controller 1 Mailbox 11 ID0 Register */
-#define                    CAN1_MB11_ID1  0xffc0357c   /* CAN Controller 1 Mailbox 11 ID1 Register */
-#define                  CAN1_MB12_DATA0  0xffc03580   /* CAN Controller 1 Mailbox 12 Data 0 Register */
-#define                  CAN1_MB12_DATA1  0xffc03584   /* CAN Controller 1 Mailbox 12 Data 1 Register */
-#define                  CAN1_MB12_DATA2  0xffc03588   /* CAN Controller 1 Mailbox 12 Data 2 Register */
-#define                  CAN1_MB12_DATA3  0xffc0358c   /* CAN Controller 1 Mailbox 12 Data 3 Register */
-#define                 CAN1_MB12_LENGTH  0xffc03590   /* CAN Controller 1 Mailbox 12 Length Register */
-#define              CAN1_MB12_TIMESTAMP  0xffc03594   /* CAN Controller 1 Mailbox 12 Timestamp Register */
-#define                    CAN1_MB12_ID0  0xffc03598   /* CAN Controller 1 Mailbox 12 ID0 Register */
-#define                    CAN1_MB12_ID1  0xffc0359c   /* CAN Controller 1 Mailbox 12 ID1 Register */
-#define                  CAN1_MB13_DATA0  0xffc035a0   /* CAN Controller 1 Mailbox 13 Data 0 Register */
-#define                  CAN1_MB13_DATA1  0xffc035a4   /* CAN Controller 1 Mailbox 13 Data 1 Register */
-#define                  CAN1_MB13_DATA2  0xffc035a8   /* CAN Controller 1 Mailbox 13 Data 2 Register */
-#define                  CAN1_MB13_DATA3  0xffc035ac   /* CAN Controller 1 Mailbox 13 Data 3 Register */
-#define                 CAN1_MB13_LENGTH  0xffc035b0   /* CAN Controller 1 Mailbox 13 Length Register */
-#define              CAN1_MB13_TIMESTAMP  0xffc035b4   /* CAN Controller 1 Mailbox 13 Timestamp Register */
-#define                    CAN1_MB13_ID0  0xffc035b8   /* CAN Controller 1 Mailbox 13 ID0 Register */
-#define                    CAN1_MB13_ID1  0xffc035bc   /* CAN Controller 1 Mailbox 13 ID1 Register */
-#define                  CAN1_MB14_DATA0  0xffc035c0   /* CAN Controller 1 Mailbox 14 Data 0 Register */
-#define                  CAN1_MB14_DATA1  0xffc035c4   /* CAN Controller 1 Mailbox 14 Data 1 Register */
-#define                  CAN1_MB14_DATA2  0xffc035c8   /* CAN Controller 1 Mailbox 14 Data 2 Register */
-#define                  CAN1_MB14_DATA3  0xffc035cc   /* CAN Controller 1 Mailbox 14 Data 3 Register */
-#define                 CAN1_MB14_LENGTH  0xffc035d0   /* CAN Controller 1 Mailbox 14 Length Register */
-#define              CAN1_MB14_TIMESTAMP  0xffc035d4   /* CAN Controller 1 Mailbox 14 Timestamp Register */
-#define                    CAN1_MB14_ID0  0xffc035d8   /* CAN Controller 1 Mailbox 14 ID0 Register */
-#define                    CAN1_MB14_ID1  0xffc035dc   /* CAN Controller 1 Mailbox 14 ID1 Register */
-#define                  CAN1_MB15_DATA0  0xffc035e0   /* CAN Controller 1 Mailbox 15 Data 0 Register */
-#define                  CAN1_MB15_DATA1  0xffc035e4   /* CAN Controller 1 Mailbox 15 Data 1 Register */
-#define                  CAN1_MB15_DATA2  0xffc035e8   /* CAN Controller 1 Mailbox 15 Data 2 Register */
-#define                  CAN1_MB15_DATA3  0xffc035ec   /* CAN Controller 1 Mailbox 15 Data 3 Register */
-#define                 CAN1_MB15_LENGTH  0xffc035f0   /* CAN Controller 1 Mailbox 15 Length Register */
-#define              CAN1_MB15_TIMESTAMP  0xffc035f4   /* CAN Controller 1 Mailbox 15 Timestamp Register */
-#define                    CAN1_MB15_ID0  0xffc035f8   /* CAN Controller 1 Mailbox 15 ID0 Register */
-#define                    CAN1_MB15_ID1  0xffc035fc   /* CAN Controller 1 Mailbox 15 ID1 Register */
-
-/* CAN Controller 1 Mailbox Data Registers */
-
-#define                  CAN1_MB16_DATA0  0xffc03600   /* CAN Controller 1 Mailbox 16 Data 0 Register */
-#define                  CAN1_MB16_DATA1  0xffc03604   /* CAN Controller 1 Mailbox 16 Data 1 Register */
-#define                  CAN1_MB16_DATA2  0xffc03608   /* CAN Controller 1 Mailbox 16 Data 2 Register */
-#define                  CAN1_MB16_DATA3  0xffc0360c   /* CAN Controller 1 Mailbox 16 Data 3 Register */
-#define                 CAN1_MB16_LENGTH  0xffc03610   /* CAN Controller 1 Mailbox 16 Length Register */
-#define              CAN1_MB16_TIMESTAMP  0xffc03614   /* CAN Controller 1 Mailbox 16 Timestamp Register */
-#define                    CAN1_MB16_ID0  0xffc03618   /* CAN Controller 1 Mailbox 16 ID0 Register */
-#define                    CAN1_MB16_ID1  0xffc0361c   /* CAN Controller 1 Mailbox 16 ID1 Register */
-#define                  CAN1_MB17_DATA0  0xffc03620   /* CAN Controller 1 Mailbox 17 Data 0 Register */
-#define                  CAN1_MB17_DATA1  0xffc03624   /* CAN Controller 1 Mailbox 17 Data 1 Register */
-#define                  CAN1_MB17_DATA2  0xffc03628   /* CAN Controller 1 Mailbox 17 Data 2 Register */
-#define                  CAN1_MB17_DATA3  0xffc0362c   /* CAN Controller 1 Mailbox 17 Data 3 Register */
-#define                 CAN1_MB17_LENGTH  0xffc03630   /* CAN Controller 1 Mailbox 17 Length Register */
-#define              CAN1_MB17_TIMESTAMP  0xffc03634   /* CAN Controller 1 Mailbox 17 Timestamp Register */
-#define                    CAN1_MB17_ID0  0xffc03638   /* CAN Controller 1 Mailbox 17 ID0 Register */
-#define                    CAN1_MB17_ID1  0xffc0363c   /* CAN Controller 1 Mailbox 17 ID1 Register */
-#define                  CAN1_MB18_DATA0  0xffc03640   /* CAN Controller 1 Mailbox 18 Data 0 Register */
-#define                  CAN1_MB18_DATA1  0xffc03644   /* CAN Controller 1 Mailbox 18 Data 1 Register */
-#define                  CAN1_MB18_DATA2  0xffc03648   /* CAN Controller 1 Mailbox 18 Data 2 Register */
-#define                  CAN1_MB18_DATA3  0xffc0364c   /* CAN Controller 1 Mailbox 18 Data 3 Register */
-#define                 CAN1_MB18_LENGTH  0xffc03650   /* CAN Controller 1 Mailbox 18 Length Register */
-#define              CAN1_MB18_TIMESTAMP  0xffc03654   /* CAN Controller 1 Mailbox 18 Timestamp Register */
-#define                    CAN1_MB18_ID0  0xffc03658   /* CAN Controller 1 Mailbox 18 ID0 Register */
-#define                    CAN1_MB18_ID1  0xffc0365c   /* CAN Controller 1 Mailbox 18 ID1 Register */
-#define                  CAN1_MB19_DATA0  0xffc03660   /* CAN Controller 1 Mailbox 19 Data 0 Register */
-#define                  CAN1_MB19_DATA1  0xffc03664   /* CAN Controller 1 Mailbox 19 Data 1 Register */
-#define                  CAN1_MB19_DATA2  0xffc03668   /* CAN Controller 1 Mailbox 19 Data 2 Register */
-#define                  CAN1_MB19_DATA3  0xffc0366c   /* CAN Controller 1 Mailbox 19 Data 3 Register */
-#define                 CAN1_MB19_LENGTH  0xffc03670   /* CAN Controller 1 Mailbox 19 Length Register */
-#define              CAN1_MB19_TIMESTAMP  0xffc03674   /* CAN Controller 1 Mailbox 19 Timestamp Register */
-#define                    CAN1_MB19_ID0  0xffc03678   /* CAN Controller 1 Mailbox 19 ID0 Register */
-#define                    CAN1_MB19_ID1  0xffc0367c   /* CAN Controller 1 Mailbox 19 ID1 Register */
-#define                  CAN1_MB20_DATA0  0xffc03680   /* CAN Controller 1 Mailbox 20 Data 0 Register */
-#define                  CAN1_MB20_DATA1  0xffc03684   /* CAN Controller 1 Mailbox 20 Data 1 Register */
-#define                  CAN1_MB20_DATA2  0xffc03688   /* CAN Controller 1 Mailbox 20 Data 2 Register */
-#define                  CAN1_MB20_DATA3  0xffc0368c   /* CAN Controller 1 Mailbox 20 Data 3 Register */
-#define                 CAN1_MB20_LENGTH  0xffc03690   /* CAN Controller 1 Mailbox 20 Length Register */
-#define              CAN1_MB20_TIMESTAMP  0xffc03694   /* CAN Controller 1 Mailbox 20 Timestamp Register */
-#define                    CAN1_MB20_ID0  0xffc03698   /* CAN Controller 1 Mailbox 20 ID0 Register */
-#define                    CAN1_MB20_ID1  0xffc0369c   /* CAN Controller 1 Mailbox 20 ID1 Register */
-#define                  CAN1_MB21_DATA0  0xffc036a0   /* CAN Controller 1 Mailbox 21 Data 0 Register */
-#define                  CAN1_MB21_DATA1  0xffc036a4   /* CAN Controller 1 Mailbox 21 Data 1 Register */
-#define                  CAN1_MB21_DATA2  0xffc036a8   /* CAN Controller 1 Mailbox 21 Data 2 Register */
-#define                  CAN1_MB21_DATA3  0xffc036ac   /* CAN Controller 1 Mailbox 21 Data 3 Register */
-#define                 CAN1_MB21_LENGTH  0xffc036b0   /* CAN Controller 1 Mailbox 21 Length Register */
-#define              CAN1_MB21_TIMESTAMP  0xffc036b4   /* CAN Controller 1 Mailbox 21 Timestamp Register */
-#define                    CAN1_MB21_ID0  0xffc036b8   /* CAN Controller 1 Mailbox 21 ID0 Register */
-#define                    CAN1_MB21_ID1  0xffc036bc   /* CAN Controller 1 Mailbox 21 ID1 Register */
-#define                  CAN1_MB22_DATA0  0xffc036c0   /* CAN Controller 1 Mailbox 22 Data 0 Register */
-#define                  CAN1_MB22_DATA1  0xffc036c4   /* CAN Controller 1 Mailbox 22 Data 1 Register */
-#define                  CAN1_MB22_DATA2  0xffc036c8   /* CAN Controller 1 Mailbox 22 Data 2 Register */
-#define                  CAN1_MB22_DATA3  0xffc036cc   /* CAN Controller 1 Mailbox 22 Data 3 Register */
-#define                 CAN1_MB22_LENGTH  0xffc036d0   /* CAN Controller 1 Mailbox 22 Length Register */
-#define              CAN1_MB22_TIMESTAMP  0xffc036d4   /* CAN Controller 1 Mailbox 22 Timestamp Register */
-#define                    CAN1_MB22_ID0  0xffc036d8   /* CAN Controller 1 Mailbox 22 ID0 Register */
-#define                    CAN1_MB22_ID1  0xffc036dc   /* CAN Controller 1 Mailbox 22 ID1 Register */
-#define                  CAN1_MB23_DATA0  0xffc036e0   /* CAN Controller 1 Mailbox 23 Data 0 Register */
-#define                  CAN1_MB23_DATA1  0xffc036e4   /* CAN Controller 1 Mailbox 23 Data 1 Register */
-#define                  CAN1_MB23_DATA2  0xffc036e8   /* CAN Controller 1 Mailbox 23 Data 2 Register */
-#define                  CAN1_MB23_DATA3  0xffc036ec   /* CAN Controller 1 Mailbox 23 Data 3 Register */
-#define                 CAN1_MB23_LENGTH  0xffc036f0   /* CAN Controller 1 Mailbox 23 Length Register */
-#define              CAN1_MB23_TIMESTAMP  0xffc036f4   /* CAN Controller 1 Mailbox 23 Timestamp Register */
-#define                    CAN1_MB23_ID0  0xffc036f8   /* CAN Controller 1 Mailbox 23 ID0 Register */
-#define                    CAN1_MB23_ID1  0xffc036fc   /* CAN Controller 1 Mailbox 23 ID1 Register */
-#define                  CAN1_MB24_DATA0  0xffc03700   /* CAN Controller 1 Mailbox 24 Data 0 Register */
-#define                  CAN1_MB24_DATA1  0xffc03704   /* CAN Controller 1 Mailbox 24 Data 1 Register */
-#define                  CAN1_MB24_DATA2  0xffc03708   /* CAN Controller 1 Mailbox 24 Data 2 Register */
-#define                  CAN1_MB24_DATA3  0xffc0370c   /* CAN Controller 1 Mailbox 24 Data 3 Register */
-#define                 CAN1_MB24_LENGTH  0xffc03710   /* CAN Controller 1 Mailbox 24 Length Register */
-#define              CAN1_MB24_TIMESTAMP  0xffc03714   /* CAN Controller 1 Mailbox 24 Timestamp Register */
-#define                    CAN1_MB24_ID0  0xffc03718   /* CAN Controller 1 Mailbox 24 ID0 Register */
-#define                    CAN1_MB24_ID1  0xffc0371c   /* CAN Controller 1 Mailbox 24 ID1 Register */
-#define                  CAN1_MB25_DATA0  0xffc03720   /* CAN Controller 1 Mailbox 25 Data 0 Register */
-#define                  CAN1_MB25_DATA1  0xffc03724   /* CAN Controller 1 Mailbox 25 Data 1 Register */
-#define                  CAN1_MB25_DATA2  0xffc03728   /* CAN Controller 1 Mailbox 25 Data 2 Register */
-#define                  CAN1_MB25_DATA3  0xffc0372c   /* CAN Controller 1 Mailbox 25 Data 3 Register */
-#define                 CAN1_MB25_LENGTH  0xffc03730   /* CAN Controller 1 Mailbox 25 Length Register */
-#define              CAN1_MB25_TIMESTAMP  0xffc03734   /* CAN Controller 1 Mailbox 25 Timestamp Register */
-#define                    CAN1_MB25_ID0  0xffc03738   /* CAN Controller 1 Mailbox 25 ID0 Register */
-#define                    CAN1_MB25_ID1  0xffc0373c   /* CAN Controller 1 Mailbox 25 ID1 Register */
-#define                  CAN1_MB26_DATA0  0xffc03740   /* CAN Controller 1 Mailbox 26 Data 0 Register */
-#define                  CAN1_MB26_DATA1  0xffc03744   /* CAN Controller 1 Mailbox 26 Data 1 Register */
-#define                  CAN1_MB26_DATA2  0xffc03748   /* CAN Controller 1 Mailbox 26 Data 2 Register */
-#define                  CAN1_MB26_DATA3  0xffc0374c   /* CAN Controller 1 Mailbox 26 Data 3 Register */
-#define                 CAN1_MB26_LENGTH  0xffc03750   /* CAN Controller 1 Mailbox 26 Length Register */
-#define              CAN1_MB26_TIMESTAMP  0xffc03754   /* CAN Controller 1 Mailbox 26 Timestamp Register */
-#define                    CAN1_MB26_ID0  0xffc03758   /* CAN Controller 1 Mailbox 26 ID0 Register */
-#define                    CAN1_MB26_ID1  0xffc0375c   /* CAN Controller 1 Mailbox 26 ID1 Register */
-#define                  CAN1_MB27_DATA0  0xffc03760   /* CAN Controller 1 Mailbox 27 Data 0 Register */
-#define                  CAN1_MB27_DATA1  0xffc03764   /* CAN Controller 1 Mailbox 27 Data 1 Register */
-#define                  CAN1_MB27_DATA2  0xffc03768   /* CAN Controller 1 Mailbox 27 Data 2 Register */
-#define                  CAN1_MB27_DATA3  0xffc0376c   /* CAN Controller 1 Mailbox 27 Data 3 Register */
-#define                 CAN1_MB27_LENGTH  0xffc03770   /* CAN Controller 1 Mailbox 27 Length Register */
-#define              CAN1_MB27_TIMESTAMP  0xffc03774   /* CAN Controller 1 Mailbox 27 Timestamp Register */
-#define                    CAN1_MB27_ID0  0xffc03778   /* CAN Controller 1 Mailbox 27 ID0 Register */
-#define                    CAN1_MB27_ID1  0xffc0377c   /* CAN Controller 1 Mailbox 27 ID1 Register */
-#define                  CAN1_MB28_DATA0  0xffc03780   /* CAN Controller 1 Mailbox 28 Data 0 Register */
-#define                  CAN1_MB28_DATA1  0xffc03784   /* CAN Controller 1 Mailbox 28 Data 1 Register */
-#define                  CAN1_MB28_DATA2  0xffc03788   /* CAN Controller 1 Mailbox 28 Data 2 Register */
-#define                  CAN1_MB28_DATA3  0xffc0378c   /* CAN Controller 1 Mailbox 28 Data 3 Register */
-#define                 CAN1_MB28_LENGTH  0xffc03790   /* CAN Controller 1 Mailbox 28 Length Register */
-#define              CAN1_MB28_TIMESTAMP  0xffc03794   /* CAN Controller 1 Mailbox 28 Timestamp Register */
-#define                    CAN1_MB28_ID0  0xffc03798   /* CAN Controller 1 Mailbox 28 ID0 Register */
-#define                    CAN1_MB28_ID1  0xffc0379c   /* CAN Controller 1 Mailbox 28 ID1 Register */
-#define                  CAN1_MB29_DATA0  0xffc037a0   /* CAN Controller 1 Mailbox 29 Data 0 Register */
-#define                  CAN1_MB29_DATA1  0xffc037a4   /* CAN Controller 1 Mailbox 29 Data 1 Register */
-#define                  CAN1_MB29_DATA2  0xffc037a8   /* CAN Controller 1 Mailbox 29 Data 2 Register */
-#define                  CAN1_MB29_DATA3  0xffc037ac   /* CAN Controller 1 Mailbox 29 Data 3 Register */
-#define                 CAN1_MB29_LENGTH  0xffc037b0   /* CAN Controller 1 Mailbox 29 Length Register */
-#define              CAN1_MB29_TIMESTAMP  0xffc037b4   /* CAN Controller 1 Mailbox 29 Timestamp Register */
-#define                    CAN1_MB29_ID0  0xffc037b8   /* CAN Controller 1 Mailbox 29 ID0 Register */
-#define                    CAN1_MB29_ID1  0xffc037bc   /* CAN Controller 1 Mailbox 29 ID1 Register */
-#define                  CAN1_MB30_DATA0  0xffc037c0   /* CAN Controller 1 Mailbox 30 Data 0 Register */
-#define                  CAN1_MB30_DATA1  0xffc037c4   /* CAN Controller 1 Mailbox 30 Data 1 Register */
-#define                  CAN1_MB30_DATA2  0xffc037c8   /* CAN Controller 1 Mailbox 30 Data 2 Register */
-#define                  CAN1_MB30_DATA3  0xffc037cc   /* CAN Controller 1 Mailbox 30 Data 3 Register */
-#define                 CAN1_MB30_LENGTH  0xffc037d0   /* CAN Controller 1 Mailbox 30 Length Register */
-#define              CAN1_MB30_TIMESTAMP  0xffc037d4   /* CAN Controller 1 Mailbox 30 Timestamp Register */
-#define                    CAN1_MB30_ID0  0xffc037d8   /* CAN Controller 1 Mailbox 30 ID0 Register */
-#define                    CAN1_MB30_ID1  0xffc037dc   /* CAN Controller 1 Mailbox 30 ID1 Register */
-#define                  CAN1_MB31_DATA0  0xffc037e0   /* CAN Controller 1 Mailbox 31 Data 0 Register */
-#define                  CAN1_MB31_DATA1  0xffc037e4   /* CAN Controller 1 Mailbox 31 Data 1 Register */
-#define                  CAN1_MB31_DATA2  0xffc037e8   /* CAN Controller 1 Mailbox 31 Data 2 Register */
-#define                  CAN1_MB31_DATA3  0xffc037ec   /* CAN Controller 1 Mailbox 31 Data 3 Register */
-#define                 CAN1_MB31_LENGTH  0xffc037f0   /* CAN Controller 1 Mailbox 31 Length Register */
-#define              CAN1_MB31_TIMESTAMP  0xffc037f4   /* CAN Controller 1 Mailbox 31 Timestamp Register */
-#define                    CAN1_MB31_ID0  0xffc037f8   /* CAN Controller 1 Mailbox 31 ID0 Register */
-#define                    CAN1_MB31_ID1  0xffc037fc   /* CAN Controller 1 Mailbox 31 ID1 Register */
-
-/* ATAPI Registers */
-
-#define                    ATAPI_CONTROL  0xffc03800   /* ATAPI Control Register */
-#define                     ATAPI_STATUS  0xffc03804   /* ATAPI Status Register */
-#define                   ATAPI_DEV_ADDR  0xffc03808   /* ATAPI Device Register Address */
-#define                  ATAPI_DEV_TXBUF  0xffc0380c   /* ATAPI Device Register Write Data */
-#define                  ATAPI_DEV_RXBUF  0xffc03810   /* ATAPI Device Register Read Data */
-#define                   ATAPI_INT_MASK  0xffc03814   /* ATAPI Interrupt Mask Register */
-#define                 ATAPI_INT_STATUS  0xffc03818   /* ATAPI Interrupt Status Register */
-#define                   ATAPI_XFER_LEN  0xffc0381c   /* ATAPI Length of Transfer */
-#define                ATAPI_LINE_STATUS  0xffc03820   /* ATAPI Line Status */
-#define                   ATAPI_SM_STATE  0xffc03824   /* ATAPI State Machine Status */
-#define                  ATAPI_TERMINATE  0xffc03828   /* ATAPI Host Terminate */
-#define                 ATAPI_PIO_TFRCNT  0xffc0382c   /* ATAPI PIO mode transfer count */
-#define                 ATAPI_DMA_TFRCNT  0xffc03830   /* ATAPI DMA mode transfer count */
-#define               ATAPI_UMAIN_TFRCNT  0xffc03834   /* ATAPI UDMAIN transfer count */
-#define             ATAPI_UDMAOUT_TFRCNT  0xffc03838   /* ATAPI UDMAOUT transfer count */
-#define                  ATAPI_REG_TIM_0  0xffc03840   /* ATAPI Register Transfer Timing 0 */
-#define                  ATAPI_PIO_TIM_0  0xffc03844   /* ATAPI PIO Timing 0 Register */
-#define                  ATAPI_PIO_TIM_1  0xffc03848   /* ATAPI PIO Timing 1 Register */
-#define                ATAPI_MULTI_TIM_0  0xffc03850   /* ATAPI Multi-DMA Timing 0 Register */
-#define                ATAPI_MULTI_TIM_1  0xffc03854   /* ATAPI Multi-DMA Timing 1 Register */
-#define                ATAPI_MULTI_TIM_2  0xffc03858   /* ATAPI Multi-DMA Timing 2 Register */
-#define                ATAPI_ULTRA_TIM_0  0xffc03860   /* ATAPI Ultra-DMA Timing 0 Register */
-#define                ATAPI_ULTRA_TIM_1  0xffc03864   /* ATAPI Ultra-DMA Timing 1 Register */
-#define                ATAPI_ULTRA_TIM_2  0xffc03868   /* ATAPI Ultra-DMA Timing 2 Register */
-#define                ATAPI_ULTRA_TIM_3  0xffc0386c   /* ATAPI Ultra-DMA Timing 3 Register */
-
-/* SDH Registers */
-
-#define                      SDH_PWR_CTL  0xffc03900   /* SDH Power Control */
-#define                      SDH_CLK_CTL  0xffc03904   /* SDH Clock Control */
-#define                     SDH_ARGUMENT  0xffc03908   /* SDH Argument */
-#define                      SDH_COMMAND  0xffc0390c   /* SDH Command */
-#define                     SDH_RESP_CMD  0xffc03910   /* SDH Response Command */
-#define                    SDH_RESPONSE0  0xffc03914   /* SDH Response0 */
-#define                    SDH_RESPONSE1  0xffc03918   /* SDH Response1 */
-#define                    SDH_RESPONSE2  0xffc0391c   /* SDH Response2 */
-#define                    SDH_RESPONSE3  0xffc03920   /* SDH Response3 */
-#define                   SDH_DATA_TIMER  0xffc03924   /* SDH Data Timer */
-#define                    SDH_DATA_LGTH  0xffc03928   /* SDH Data Length */
-#define                     SDH_DATA_CTL  0xffc0392c   /* SDH Data Control */
-#define                     SDH_DATA_CNT  0xffc03930   /* SDH Data Counter */
-#define                       SDH_STATUS  0xffc03934   /* SDH Status */
-#define                   SDH_STATUS_CLR  0xffc03938   /* SDH Status Clear */
-#define                        SDH_MASK0  0xffc0393c   /* SDH Interrupt0 Mask */
-#define                        SDH_MASK1  0xffc03940   /* SDH Interrupt1 Mask */
-#define                     SDH_FIFO_CNT  0xffc03948   /* SDH FIFO Counter */
-#define                         SDH_FIFO  0xffc03980   /* SDH Data FIFO */
-#define                     SDH_E_STATUS  0xffc039c0   /* SDH Exception Status */
-#define                       SDH_E_MASK  0xffc039c4   /* SDH Exception Mask */
-#define                          SDH_CFG  0xffc039c8   /* SDH Configuration */
-#define                   SDH_RD_WAIT_EN  0xffc039cc   /* SDH Read Wait Enable */
-#define                         SDH_PID0  0xffc039d0   /* SDH Peripheral Identification0 */
-#define                         SDH_PID1  0xffc039d4   /* SDH Peripheral Identification1 */
-#define                         SDH_PID2  0xffc039d8   /* SDH Peripheral Identification2 */
-#define                         SDH_PID3  0xffc039dc   /* SDH Peripheral Identification3 */
-#define                         SDH_PID4  0xffc039e0   /* SDH Peripheral Identification4 */
-#define                         SDH_PID5  0xffc039e4   /* SDH Peripheral Identification5 */
-#define                         SDH_PID6  0xffc039e8   /* SDH Peripheral Identification6 */
-#define                         SDH_PID7  0xffc039ec   /* SDH Peripheral Identification7 */
-
-/* HOST Port Registers */
-
-#define                     HOST_CONTROL  0xffc03a00   /* HOST Control Register */
-#define                      HOST_STATUS  0xffc03a04   /* HOST Status Register */
-#define                     HOST_TIMEOUT  0xffc03a08   /* HOST Acknowledge Mode Timeout Register */
-
-/* USB Control Registers */
-
-#define                        USB_FADDR  0xffc03c00   /* Function address register */
-#define                        USB_POWER  0xffc03c04   /* Power management register */
-#define                       USB_INTRTX  0xffc03c08   /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */
-#define                       USB_INTRRX  0xffc03c0c   /* Interrupt register for Rx endpoints 1 to 7 */
-#define                      USB_INTRTXE  0xffc03c10   /* Interrupt enable register for IntrTx */
-#define                      USB_INTRRXE  0xffc03c14   /* Interrupt enable register for IntrRx */
-#define                      USB_INTRUSB  0xffc03c18   /* Interrupt register for common USB interrupts */
-#define                     USB_INTRUSBE  0xffc03c1c   /* Interrupt enable register for IntrUSB */
-#define                        USB_FRAME  0xffc03c20   /* USB frame number */
-#define                        USB_INDEX  0xffc03c24   /* Index register for selecting the indexed endpoint registers */
-#define                     USB_TESTMODE  0xffc03c28   /* Enabled USB 20 test modes */
-#define                     USB_GLOBINTR  0xffc03c2c   /* Global Interrupt Mask register and Wakeup Exception Interrupt */
-#define                   USB_GLOBAL_CTL  0xffc03c30   /* Global Clock Control for the core */
-
-/* USB Packet Control Registers */
-
-#define                USB_TX_MAX_PACKET  0xffc03c40   /* Maximum packet size for Host Tx endpoint */
-#define                         USB_CSR0  0xffc03c44   /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
-#define                        USB_TXCSR  0xffc03c44   /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
-#define                USB_RX_MAX_PACKET  0xffc03c48   /* Maximum packet size for Host Rx endpoint */
-#define                        USB_RXCSR  0xffc03c4c   /* Control Status register for Host Rx endpoint */
-#define                       USB_COUNT0  0xffc03c50   /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
-#define                      USB_RXCOUNT  0xffc03c50   /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
-#define                       USB_TXTYPE  0xffc03c54   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */
-#define                    USB_NAKLIMIT0  0xffc03c58   /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
-#define                   USB_TXINTERVAL  0xffc03c58   /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
-#define                       USB_RXTYPE  0xffc03c5c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */
-#define                   USB_RXINTERVAL  0xffc03c60   /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */
-#define                      USB_TXCOUNT  0xffc03c68   /* Number of bytes to be written to the selected endpoint Tx FIFO */
-
-/* USB Endpoint FIFO Registers */
-
-#define                     USB_EP0_FIFO  0xffc03c80   /* Endpoint 0 FIFO */
-#define                     USB_EP1_FIFO  0xffc03c88   /* Endpoint 1 FIFO */
-#define                     USB_EP2_FIFO  0xffc03c90   /* Endpoint 2 FIFO */
-#define                     USB_EP3_FIFO  0xffc03c98   /* Endpoint 3 FIFO */
-#define                     USB_EP4_FIFO  0xffc03ca0   /* Endpoint 4 FIFO */
-#define                     USB_EP5_FIFO  0xffc03ca8   /* Endpoint 5 FIFO */
-#define                     USB_EP6_FIFO  0xffc03cb0   /* Endpoint 6 FIFO */
-#define                     USB_EP7_FIFO  0xffc03cb8   /* Endpoint 7 FIFO */
-
-/* USB OTG Control Registers */
-
-#define                  USB_OTG_DEV_CTL  0xffc03d00   /* OTG Device Control Register */
-#define                 USB_OTG_VBUS_IRQ  0xffc03d04   /* OTG VBUS Control Interrupts */
-#define                USB_OTG_VBUS_MASK  0xffc03d08   /* VBUS Control Interrupt Enable */
-
-/* USB Phy Control Registers */
-
-#define                     USB_LINKINFO  0xffc03d48   /* Enables programming of some PHY-side delays */
-#define                        USB_VPLEN  0xffc03d4c   /* Determines duration of VBUS pulse for VBUS charging */
-#define                      USB_HS_EOF1  0xffc03d50   /* Time buffer for High-Speed transactions */
-#define                      USB_FS_EOF1  0xffc03d54   /* Time buffer for Full-Speed transactions */
-#define                      USB_LS_EOF1  0xffc03d58   /* Time buffer for Low-Speed transactions */
-
-/* (APHY_CNTRL is for ADI usage only) */
-
-#define                   USB_APHY_CNTRL  0xffc03de0   /* Register that increases visibility of Analog PHY */
-
-/* (APHY_CALIB is for ADI usage only) */
-
-#define                   USB_APHY_CALIB  0xffc03de4   /* Register used to set some calibration values */
-#define                  USB_APHY_CNTRL2  0xffc03de8   /* Register used to prevent re-enumeration once Moab goes into hibernate mode */
-
-/* (PHY_TEST is for ADI usage only) */
-
-#define                     USB_PHY_TEST  0xffc03dec   /* Used for reducing simulation time and simplifies FIFO testability */
-#define                  USB_PLLOSC_CTRL  0xffc03df0   /* Used to program different parameters for USB PLL and Oscillator */
-#define                   USB_SRP_CLKDIV  0xffc03df4   /* Used to program clock divide value for the clock fed to the SRP detection logic */
-
-/* USB Endpoint 0 Control Registers */
-
-#define                USB_EP_NI0_TXMAXP  0xffc03e00   /* Maximum packet size for Host Tx endpoint0 */
-#define                 USB_EP_NI0_TXCSR  0xffc03e04   /* Control Status register for endpoint 0 */
-#define                USB_EP_NI0_RXMAXP  0xffc03e08   /* Maximum packet size for Host Rx endpoint0 */
-#define                 USB_EP_NI0_RXCSR  0xffc03e0c   /* Control Status register for Host Rx endpoint0 */
-#define               USB_EP_NI0_RXCOUNT  0xffc03e10   /* Number of bytes received in endpoint 0 FIFO */
-#define                USB_EP_NI0_TXTYPE  0xffc03e14   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */
-#define            USB_EP_NI0_TXINTERVAL  0xffc03e18   /* Sets the NAK response timeout on Endpoint 0 */
-#define                USB_EP_NI0_RXTYPE  0xffc03e1c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */
-#define            USB_EP_NI0_RXINTERVAL  0xffc03e20   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */
-
-/* USB Endpoint 1 Control Registers */
-
-#define               USB_EP_NI0_TXCOUNT  0xffc03e28   /* Number of bytes to be written to the endpoint0 Tx FIFO */
-#define                USB_EP_NI1_TXMAXP  0xffc03e40   /* Maximum packet size for Host Tx endpoint1 */
-#define                 USB_EP_NI1_TXCSR  0xffc03e44   /* Control Status register for endpoint1 */
-#define                USB_EP_NI1_RXMAXP  0xffc03e48   /* Maximum packet size for Host Rx endpoint1 */
-#define                 USB_EP_NI1_RXCSR  0xffc03e4c   /* Control Status register for Host Rx endpoint1 */
-#define               USB_EP_NI1_RXCOUNT  0xffc03e50   /* Number of bytes received in endpoint1 FIFO */
-#define                USB_EP_NI1_TXTYPE  0xffc03e54   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */
-#define            USB_EP_NI1_TXINTERVAL  0xffc03e58   /* Sets the NAK response timeout on Endpoint1 */
-#define                USB_EP_NI1_RXTYPE  0xffc03e5c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */
-#define            USB_EP_NI1_RXINTERVAL  0xffc03e60   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */
-
-/* USB Endpoint 2 Control Registers */
-
-#define               USB_EP_NI1_TXCOUNT  0xffc03e68   /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */
-#define                USB_EP_NI2_TXMAXP  0xffc03e80   /* Maximum packet size for Host Tx endpoint2 */
-#define                 USB_EP_NI2_TXCSR  0xffc03e84   /* Control Status register for endpoint2 */
-#define                USB_EP_NI2_RXMAXP  0xffc03e88   /* Maximum packet size for Host Rx endpoint2 */
-#define                 USB_EP_NI2_RXCSR  0xffc03e8c   /* Control Status register for Host Rx endpoint2 */
-#define               USB_EP_NI2_RXCOUNT  0xffc03e90   /* Number of bytes received in endpoint2 FIFO */
-#define                USB_EP_NI2_TXTYPE  0xffc03e94   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */
-#define            USB_EP_NI2_TXINTERVAL  0xffc03e98   /* Sets the NAK response timeout on Endpoint2 */
-#define                USB_EP_NI2_RXTYPE  0xffc03e9c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */
-#define            USB_EP_NI2_RXINTERVAL  0xffc03ea0   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */
-
-/* USB Endpoint 3 Control Registers */
-
-#define               USB_EP_NI2_TXCOUNT  0xffc03ea8   /* Number of bytes to be written to the endpoint2 Tx FIFO */
-#define                USB_EP_NI3_TXMAXP  0xffc03ec0   /* Maximum packet size for Host Tx endpoint3 */
-#define                 USB_EP_NI3_TXCSR  0xffc03ec4   /* Control Status register for endpoint3 */
-#define                USB_EP_NI3_RXMAXP  0xffc03ec8   /* Maximum packet size for Host Rx endpoint3 */
-#define                 USB_EP_NI3_RXCSR  0xffc03ecc   /* Control Status register for Host Rx endpoint3 */
-#define               USB_EP_NI3_RXCOUNT  0xffc03ed0   /* Number of bytes received in endpoint3 FIFO */
-#define                USB_EP_NI3_TXTYPE  0xffc03ed4   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */
-#define            USB_EP_NI3_TXINTERVAL  0xffc03ed8   /* Sets the NAK response timeout on Endpoint3 */
-#define                USB_EP_NI3_RXTYPE  0xffc03edc   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */
-#define            USB_EP_NI3_RXINTERVAL  0xffc03ee0   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */
-
-/* USB Endpoint 4 Control Registers */
-
-#define               USB_EP_NI3_TXCOUNT  0xffc03ee8   /* Number of bytes to be written to the H124endpoint3 Tx FIFO */
-#define                USB_EP_NI4_TXMAXP  0xffc03f00   /* Maximum packet size for Host Tx endpoint4 */
-#define                 USB_EP_NI4_TXCSR  0xffc03f04   /* Control Status register for endpoint4 */
-#define                USB_EP_NI4_RXMAXP  0xffc03f08   /* Maximum packet size for Host Rx endpoint4 */
-#define                 USB_EP_NI4_RXCSR  0xffc03f0c   /* Control Status register for Host Rx endpoint4 */
-#define               USB_EP_NI4_RXCOUNT  0xffc03f10   /* Number of bytes received in endpoint4 FIFO */
-#define                USB_EP_NI4_TXTYPE  0xffc03f14   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */
-#define            USB_EP_NI4_TXINTERVAL  0xffc03f18   /* Sets the NAK response timeout on Endpoint4 */
-#define                USB_EP_NI4_RXTYPE  0xffc03f1c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */
-#define            USB_EP_NI4_RXINTERVAL  0xffc03f20   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */
-
-/* USB Endpoint 5 Control Registers */
-
-#define               USB_EP_NI4_TXCOUNT  0xffc03f28   /* Number of bytes to be written to the endpoint4 Tx FIFO */
-#define                USB_EP_NI5_TXMAXP  0xffc03f40   /* Maximum packet size for Host Tx endpoint5 */
-#define                 USB_EP_NI5_TXCSR  0xffc03f44   /* Control Status register for endpoint5 */
-#define                USB_EP_NI5_RXMAXP  0xffc03f48   /* Maximum packet size for Host Rx endpoint5 */
-#define                 USB_EP_NI5_RXCSR  0xffc03f4c   /* Control Status register for Host Rx endpoint5 */
-#define               USB_EP_NI5_RXCOUNT  0xffc03f50   /* Number of bytes received in endpoint5 FIFO */
-#define                USB_EP_NI5_TXTYPE  0xffc03f54   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */
-#define            USB_EP_NI5_TXINTERVAL  0xffc03f58   /* Sets the NAK response timeout on Endpoint5 */
-#define                USB_EP_NI5_RXTYPE  0xffc03f5c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */
-#define            USB_EP_NI5_RXINTERVAL  0xffc03f60   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */
-
-/* USB Endpoint 6 Control Registers */
-
-#define               USB_EP_NI5_TXCOUNT  0xffc03f68   /* Number of bytes to be written to the H145endpoint5 Tx FIFO */
-#define                USB_EP_NI6_TXMAXP  0xffc03f80   /* Maximum packet size for Host Tx endpoint6 */
-#define                 USB_EP_NI6_TXCSR  0xffc03f84   /* Control Status register for endpoint6 */
-#define                USB_EP_NI6_RXMAXP  0xffc03f88   /* Maximum packet size for Host Rx endpoint6 */
-#define                 USB_EP_NI6_RXCSR  0xffc03f8c   /* Control Status register for Host Rx endpoint6 */
-#define               USB_EP_NI6_RXCOUNT  0xffc03f90   /* Number of bytes received in endpoint6 FIFO */
-#define                USB_EP_NI6_TXTYPE  0xffc03f94   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */
-#define            USB_EP_NI6_TXINTERVAL  0xffc03f98   /* Sets the NAK response timeout on Endpoint6 */
-#define                USB_EP_NI6_RXTYPE  0xffc03f9c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */
-#define            USB_EP_NI6_RXINTERVAL  0xffc03fa0   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */
-
-/* USB Endpoint 7 Control Registers */
-
-#define               USB_EP_NI6_TXCOUNT  0xffc03fa8   /* Number of bytes to be written to the endpoint6 Tx FIFO */
-#define                USB_EP_NI7_TXMAXP  0xffc03fc0   /* Maximum packet size for Host Tx endpoint7 */
-#define                 USB_EP_NI7_TXCSR  0xffc03fc4   /* Control Status register for endpoint7 */
-#define                USB_EP_NI7_RXMAXP  0xffc03fc8   /* Maximum packet size for Host Rx endpoint7 */
-#define                 USB_EP_NI7_RXCSR  0xffc03fcc   /* Control Status register for Host Rx endpoint7 */
-#define               USB_EP_NI7_RXCOUNT  0xffc03fd0   /* Number of bytes received in endpoint7 FIFO */
-#define                USB_EP_NI7_TXTYPE  0xffc03fd4   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */
-#define            USB_EP_NI7_TXINTERVAL  0xffc03fd8   /* Sets the NAK response timeout on Endpoint7 */
-#define                USB_EP_NI7_RXTYPE  0xffc03fdc   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */
-#define            USB_EP_NI7_RXINTERVAL  0xffc03ff0   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */
-#define               USB_EP_NI7_TXCOUNT  0xffc03ff8   /* Number of bytes to be written to the endpoint7 Tx FIFO */
-#define                USB_DMA_INTERRUPT  0xffc04000   /* Indicates pending interrupts for the DMA channels */
-
-/* USB Channel 0 Config Registers */
-
-#define                  USB_DMA0CONTROL  0xffc04004   /* DMA master channel 0 configuration */
-#define                  USB_DMA0ADDRLOW  0xffc04008   /* Lower 16-bits of memory source/destination address for DMA master channel 0 */
-#define                 USB_DMA0ADDRHIGH  0xffc0400c   /* Upper 16-bits of memory source/destination address for DMA master channel 0 */
-#define                 USB_DMA0COUNTLOW  0xffc04010   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */
-#define                USB_DMA0COUNTHIGH  0xffc04014   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */
-
-/* USB Channel 1 Config Registers */
-
-#define                  USB_DMA1CONTROL  0xffc04024   /* DMA master channel 1 configuration */
-#define                  USB_DMA1ADDRLOW  0xffc04028   /* Lower 16-bits of memory source/destination address for DMA master channel 1 */
-#define                 USB_DMA1ADDRHIGH  0xffc0402c   /* Upper 16-bits of memory source/destination address for DMA master channel 1 */
-#define                 USB_DMA1COUNTLOW  0xffc04030   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */
-#define                USB_DMA1COUNTHIGH  0xffc04034   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */
-
-/* USB Channel 2 Config Registers */
-
-#define                  USB_DMA2CONTROL  0xffc04044   /* DMA master channel 2 configuration */
-#define                  USB_DMA2ADDRLOW  0xffc04048   /* Lower 16-bits of memory source/destination address for DMA master channel 2 */
-#define                 USB_DMA2ADDRHIGH  0xffc0404c   /* Upper 16-bits of memory source/destination address for DMA master channel 2 */
-#define                 USB_DMA2COUNTLOW  0xffc04050   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */
-#define                USB_DMA2COUNTHIGH  0xffc04054   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */
-
-/* USB Channel 3 Config Registers */
-
-#define                  USB_DMA3CONTROL  0xffc04064   /* DMA master channel 3 configuration */
-#define                  USB_DMA3ADDRLOW  0xffc04068   /* Lower 16-bits of memory source/destination address for DMA master channel 3 */
-#define                 USB_DMA3ADDRHIGH  0xffc0406c   /* Upper 16-bits of memory source/destination address for DMA master channel 3 */
-#define                 USB_DMA3COUNTLOW  0xffc04070   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */
-#define                USB_DMA3COUNTHIGH  0xffc04074   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */
-
-/* USB Channel 4 Config Registers */
-
-#define                  USB_DMA4CONTROL  0xffc04084   /* DMA master channel 4 configuration */
-#define                  USB_DMA4ADDRLOW  0xffc04088   /* Lower 16-bits of memory source/destination address for DMA master channel 4 */
-#define                 USB_DMA4ADDRHIGH  0xffc0408c   /* Upper 16-bits of memory source/destination address for DMA master channel 4 */
-#define                 USB_DMA4COUNTLOW  0xffc04090   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */
-#define                USB_DMA4COUNTHIGH  0xffc04094   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */
-
-/* USB Channel 5 Config Registers */
-
-#define                  USB_DMA5CONTROL  0xffc040a4   /* DMA master channel 5 configuration */
-#define                  USB_DMA5ADDRLOW  0xffc040a8   /* Lower 16-bits of memory source/destination address for DMA master channel 5 */
-#define                 USB_DMA5ADDRHIGH  0xffc040ac   /* Upper 16-bits of memory source/destination address for DMA master channel 5 */
-#define                 USB_DMA5COUNTLOW  0xffc040b0   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */
-#define                USB_DMA5COUNTHIGH  0xffc040b4   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */
-
-/* USB Channel 6 Config Registers */
-
-#define                  USB_DMA6CONTROL  0xffc040c4   /* DMA master channel 6 configuration */
-#define                  USB_DMA6ADDRLOW  0xffc040c8   /* Lower 16-bits of memory source/destination address for DMA master channel 6 */
-#define                 USB_DMA6ADDRHIGH  0xffc040cc   /* Upper 16-bits of memory source/destination address for DMA master channel 6 */
-#define                 USB_DMA6COUNTLOW  0xffc040d0   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */
-#define                USB_DMA6COUNTHIGH  0xffc040d4   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */
-
-/* USB Channel 7 Config Registers */
-
-#define                  USB_DMA7CONTROL  0xffc040e4   /* DMA master channel 7 configuration */
-#define                  USB_DMA7ADDRLOW  0xffc040e8   /* Lower 16-bits of memory source/destination address for DMA master channel 7 */
-#define                 USB_DMA7ADDRHIGH  0xffc040ec   /* Upper 16-bits of memory source/destination address for DMA master channel 7 */
-#define                 USB_DMA7COUNTLOW  0xffc040f0   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */
-#define                USB_DMA7COUNTHIGH  0xffc040f4   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */
-
-/* Keypad Registers */
-
-#define                         KPAD_CTL  0xffc04100   /* Controls keypad module enable and disable */
-#define                    KPAD_PRESCALE  0xffc04104   /* Establish a time base for programing the KPAD_MSEL register */
-#define                        KPAD_MSEL  0xffc04108   /* Selects delay parameters for keypad interface sensitivity */
-#define                      KPAD_ROWCOL  0xffc0410c   /* Captures the row and column output values of the keys pressed */
-#define                        KPAD_STAT  0xffc04110   /* Holds and clears the status of the keypad interface interrupt */
-#define                    KPAD_SOFTEVAL  0xffc04114   /* Lets software force keypad interface to check for keys being pressed */
-
-/* Pixel Compositor (PIXC) Registers */
-
-#define                         PIXC_CTL  0xffc04400   /* Overlay enable, resampling mode, I/O data format, transparency enable, watermark level, FIFO status */
-#define                         PIXC_PPL  0xffc04404   /* Holds the number of pixels per line of the display */
-#define                         PIXC_LPF  0xffc04408   /* Holds the number of lines per frame of the display */
-#define                     PIXC_AHSTART  0xffc0440c   /* Contains horizontal start pixel information of the overlay data (set A) */
-#define                       PIXC_AHEND  0xffc04410   /* Contains horizontal end pixel information of the overlay data (set A) */
-#define                     PIXC_AVSTART  0xffc04414   /* Contains vertical start pixel information of the overlay data (set A) */
-#define                       PIXC_AVEND  0xffc04418   /* Contains vertical end pixel information of the overlay data (set A) */
-#define                     PIXC_ATRANSP  0xffc0441c   /* Contains the transparency ratio (set A) */
-#define                     PIXC_BHSTART  0xffc04420   /* Contains horizontal start pixel information of the overlay data (set B) */
-#define                       PIXC_BHEND  0xffc04424   /* Contains horizontal end pixel information of the overlay data (set B) */
-#define                     PIXC_BVSTART  0xffc04428   /* Contains vertical start pixel information of the overlay data (set B) */
-#define                       PIXC_BVEND  0xffc0442c   /* Contains vertical end pixel information of the overlay data (set B) */
-#define                     PIXC_BTRANSP  0xffc04430   /* Contains the transparency ratio (set B) */
-#define                    PIXC_INTRSTAT  0xffc0443c   /* Overlay interrupt configuration/status */
-#define                       PIXC_RYCON  0xffc04440   /* Color space conversion matrix register. Contains the R/Y conversion coefficients */
-#define                       PIXC_GUCON  0xffc04444   /* Color space conversion matrix register. Contains the G/U conversion coefficients */
-#define                       PIXC_BVCON  0xffc04448   /* Color space conversion matrix register. Contains the B/V conversion coefficients */
-#define                      PIXC_CCBIAS  0xffc0444c   /* Bias values for the color space conversion matrix */
-#define                          PIXC_TC  0xffc04450   /* Holds the transparent color value */
-
-/* Handshake MDMA 0 Registers */
-
-#define                   HMDMA0_CONTROL  0xffc04500   /* Handshake MDMA0 Control Register */
-#define                    HMDMA0_ECINIT  0xffc04504   /* Handshake MDMA0 Initial Edge Count Register */
-#define                    HMDMA0_BCINIT  0xffc04508   /* Handshake MDMA0 Initial Block Count Register */
-#define                  HMDMA0_ECURGENT  0xffc0450c   /* Handshake MDMA0 Urgent Edge Count Threshold Register */
-#define                HMDMA0_ECOVERFLOW  0xffc04510   /* Handshake MDMA0 Edge Count Overflow Interrupt Register */
-#define                    HMDMA0_ECOUNT  0xffc04514   /* Handshake MDMA0 Current Edge Count Register */
-#define                    HMDMA0_BCOUNT  0xffc04518   /* Handshake MDMA0 Current Block Count Register */
-
-/* Handshake MDMA 1 Registers */
-
-#define                   HMDMA1_CONTROL  0xffc04540   /* Handshake MDMA1 Control Register */
-#define                    HMDMA1_ECINIT  0xffc04544   /* Handshake MDMA1 Initial Edge Count Register */
-#define                    HMDMA1_BCINIT  0xffc04548   /* Handshake MDMA1 Initial Block Count Register */
-#define                  HMDMA1_ECURGENT  0xffc0454c   /* Handshake MDMA1 Urgent Edge Count Threshold Register */
-#define                HMDMA1_ECOVERFLOW  0xffc04550   /* Handshake MDMA1 Edge Count Overflow Interrupt Register */
-#define                    HMDMA1_ECOUNT  0xffc04554   /* Handshake MDMA1 Current Edge Count Register */
-#define                    HMDMA1_BCOUNT  0xffc04558   /* Handshake MDMA1 Current Block Count Register */
-
-
-/* ********************************************************** */
-/*     SINGLE BIT MACRO PAIRS (bit mask and negated one)      */
-/*     and MULTI BIT READ MACROS                              */
-/* ********************************************************** */
-
-/* Bit masks for PIXC_CTL */
-
-#define                   PIXC_EN  0x1        /* Pixel Compositor Enable */
-#define                  OVR_A_EN  0x2        /* Overlay A Enable */
-#define                  OVR_B_EN  0x4        /* Overlay B Enable */
-#define                  IMG_FORM  0x8        /* Image Data Format */
-#define                  OVR_FORM  0x10       /* Overlay Data Format */
-#define                  OUT_FORM  0x20       /* Output Data Format */
-#define                   UDS_MOD  0x40       /* Resampling Mode */
-#define                     TC_EN  0x80       /* Transparent Color Enable */
-#define                  IMG_STAT  0x300      /* Image FIFO Status */
-#define                  OVR_STAT  0xc00      /* Overlay FIFO Status */
-#define                    WM_LVL  0x3000     /* FIFO Watermark Level */
-
-/* Bit masks for PIXC_AHSTART */
-
-#define                  A_HSTART  0xfff      /* Horizontal Start Coordinates */
-
-/* Bit masks for PIXC_AHEND */
-
-#define                    A_HEND  0xfff      /* Horizontal End Coordinates */
-
-/* Bit masks for PIXC_AVSTART */
-
-#define                  A_VSTART  0x3ff      /* Vertical Start Coordinates */
-
-/* Bit masks for PIXC_AVEND */
-
-#define                    A_VEND  0x3ff      /* Vertical End Coordinates */
-
-/* Bit masks for PIXC_ATRANSP */
-
-#define                  A_TRANSP  0xf        /* Transparency Value */
-
-/* Bit masks for PIXC_BHSTART */
-
-#define                  B_HSTART  0xfff      /* Horizontal Start Coordinates */
-
-/* Bit masks for PIXC_BHEND */
-
-#define                    B_HEND  0xfff      /* Horizontal End Coordinates */
-
-/* Bit masks for PIXC_BVSTART */
-
-#define                  B_VSTART  0x3ff      /* Vertical Start Coordinates */
-
-/* Bit masks for PIXC_BVEND */
-
-#define                    B_VEND  0x3ff      /* Vertical End Coordinates */
-
-/* Bit masks for PIXC_BTRANSP */
-
-#define                  B_TRANSP  0xf        /* Transparency Value */
-
-/* Bit masks for PIXC_INTRSTAT */
-
-#define                OVR_INT_EN  0x1        /* Interrupt at End of Last Valid Overlay */
-#define                FRM_INT_EN  0x2        /* Interrupt at End of Frame */
-#define              OVR_INT_STAT  0x4        /* Overlay Interrupt Status */
-#define              FRM_INT_STAT  0x8        /* Frame Interrupt Status */
-
-/* Bit masks for PIXC_RYCON */
-
-#define                       A11  0x3ff      /* A11 in the Coefficient Matrix */
-#define                       A12  0xffc00    /* A12 in the Coefficient Matrix */
-#define                       A13  0x3ff00000 /* A13 in the Coefficient Matrix */
-#define                  RY_MULT4  0x40000000 /* Multiply Row by 4 */
-
-/* Bit masks for PIXC_GUCON */
-
-#define                       A21  0x3ff      /* A21 in the Coefficient Matrix */
-#define                       A22  0xffc00    /* A22 in the Coefficient Matrix */
-#define                       A23  0x3ff00000 /* A23 in the Coefficient Matrix */
-#define                  GU_MULT4  0x40000000 /* Multiply Row by 4 */
-
-/* Bit masks for PIXC_BVCON */
-
-#define                       A31  0x3ff      /* A31 in the Coefficient Matrix */
-#define                       A32  0xffc00    /* A32 in the Coefficient Matrix */
-#define                       A33  0x3ff00000 /* A33 in the Coefficient Matrix */
-#define                  BV_MULT4  0x40000000 /* Multiply Row by 4 */
-
-/* Bit masks for PIXC_CCBIAS */
-
-#define                       A14  0x3ff      /* A14 in the Bias Vector */
-#define                       A24  0xffc00    /* A24 in the Bias Vector */
-#define                       A34  0x3ff00000 /* A34 in the Bias Vector */
-
-/* Bit masks for PIXC_TC */
-
-#define                  RY_TRANS  0xff       /* Transparent Color - R/Y Component */
-#define                  GU_TRANS  0xff00     /* Transparent Color - G/U Component */
-#define                  BV_TRANS  0xff0000   /* Transparent Color - B/V Component */
-
-/* Bit masks for HOST_CONTROL */
-
-#define                   HOST_EN  0x1        /* Host Enable */
-#define                  HOST_END  0x2        /* Host Endianess */
-#define                 DATA_SIZE  0x4        /* Data Size */
-#define                  HOST_RST  0x8        /* Host Reset */
-#define                  HRDY_OVR  0x20       /* Host Ready Override */
-#define                  INT_MODE  0x40       /* Interrupt Mode */
-#define                     BT_EN  0x80       /* Bus Timeout Enable */
-#define                       EHW  0x100      /* Enable Host Write */
-#define                       EHR  0x200      /* Enable Host Read */
-#define                       BDR  0x400      /* Burst DMA Requests */
-
-/* Bit masks for HOST_STATUS */
-
-#define                 DMA_READY  0x1        /* DMA Ready */
-#define                  FIFOFULL  0x2        /* FIFO Full */
-#define                 FIFOEMPTY  0x4        /* FIFO Empty */
-#define              DMA_COMPLETE  0x8        /* DMA Complete */
-#define                      HSHK  0x10       /* Host Handshake */
-#define                   TIMEOUT  0x20       /* Host Timeout */
-#define                      HIRQ  0x40       /* Host Interrupt Request */
-#define                ALLOW_CNFG  0x80       /* Allow New Configuration */
-#define                   DMA_DIR  0x100      /* DMA Direction */
-#define                       BTE  0x200      /* Bus Timeout Enabled */
-
-/* Bit masks for HOST_TIMEOUT */
-
-#define             COUNT_TIMEOUT  0x7ff      /* Host Timeout count */
-
-/* Bit masks for MXVR_CONFIG */
-
-#define                    MXVREN  0x1        /* MXVR Enable */
-#define                      MMSM  0x2        /* MXVR Master/Slave Mode Select */
-#define                    ACTIVE  0x4        /* Active Mode */
-#define                    SDELAY  0x8        /* Synchronous Data Delay */
-#define                   NCMRXEN  0x10       /* Normal Control Message Receive Enable */
-#define                   RWRRXEN  0x20       /* Remote Write Receive Enable */
-#define                     MTXEN  0x40       /* MXVR Transmit Data Enable */
-#define                    MTXONB  0x80       /* MXVR Phy Transmitter On */
-#define                   EPARITY  0x100      /* Even Parity Select */
-#define                       MSB  0x1e00     /* Master Synchronous Boundary */
-#define                    APRXEN  0x2000     /* Asynchronous Packet Receive Enable */
-#define                    WAKEUP  0x4000     /* Wake-Up */
-#define                     LMECH  0x8000     /* Lock Mechanism Select */
-
-/* Bit masks for MXVR_STATE_0 */
-
-#define                      NACT  0x1        /* Network Activity */
-#define                    SBLOCK  0x2        /* Super Block Lock */
-#define                   FMPLLST  0xc        /* Frequency Multiply PLL SM State */
-#define                  CDRPLLST  0xe0       /* Clock/Data Recovery PLL SM State */
-#define                     APBSY  0x100      /* Asynchronous Packet Transmit Buffer Busy */
-#define                     APARB  0x200      /* Asynchronous Packet Arbitrating */
-#define                      APTX  0x400      /* Asynchronous Packet Transmitting */
-#define                      APRX  0x800      /* Receiving Asynchronous Packet */
-#define                     CMBSY  0x1000     /* Control Message Transmit Buffer Busy */
-#define                     CMARB  0x2000     /* Control Message Arbitrating */
-#define                      CMTX  0x4000     /* Control Message Transmitting */
-#define                      CMRX  0x8000     /* Receiving Control Message */
-#define                    MRXONB  0x10000    /* MRXONB Pin State */
-#define                     RGSIP  0x20000    /* Remote Get Source In Progress */
-#define                     DALIP  0x40000    /* Resource Deallocate In Progress */
-#define                      ALIP  0x80000    /* Resource Allocate In Progress */
-#define                     RRDIP  0x100000   /* Remote Read In Progress */
-#define                     RWRIP  0x200000   /* Remote Write In Progress */
-#define                     FLOCK  0x400000   /* Frame Lock */
-#define                     BLOCK  0x800000   /* Block Lock */
-#define                       RSB  0xf000000  /* Received Synchronous Boundary */
-#define                   DERRNUM  0xf0000000 /* DMA Error Channel Number */
-
-/* Bit masks for MXVR_STATE_1 */
-
-#define                   SRXNUMB  0xf        /* Synchronous Receive FIFO Number of Bytes */
-#define                   STXNUMB  0xf0       /* Synchronous Transmit FIFO Number of Bytes */
-#define                    APCONT  0x100      /* Asynchronous Packet Continuation */
-#define                  OBERRNUM  0xe00      /* DMA Out of Bounds Error Channel Number */
-#define                DMAACTIVE0  0x10000    /* DMA0 Active */
-#define                DMAACTIVE1  0x20000    /* DMA1 Active */
-#define                DMAACTIVE2  0x40000    /* DMA2 Active */
-#define                DMAACTIVE3  0x80000    /* DMA3 Active */
-#define                DMAACTIVE4  0x100000   /* DMA4 Active */
-#define                DMAACTIVE5  0x200000   /* DMA5 Active */
-#define                DMAACTIVE6  0x400000   /* DMA6 Active */
-#define                DMAACTIVE7  0x800000   /* DMA7 Active */
-#define                  DMAPMEN0  0x1000000  /* DMA0 Pattern Matching Enabled */
-#define                  DMAPMEN1  0x2000000  /* DMA1 Pattern Matching Enabled */
-#define                  DMAPMEN2  0x4000000  /* DMA2 Pattern Matching Enabled */
-#define                  DMAPMEN3  0x8000000  /* DMA3 Pattern Matching Enabled */
-#define                  DMAPMEN4  0x10000000 /* DMA4 Pattern Matching Enabled */
-#define                  DMAPMEN5  0x20000000 /* DMA5 Pattern Matching Enabled */
-#define                  DMAPMEN6  0x40000000 /* DMA6 Pattern Matching Enabled */
-#define                  DMAPMEN7  0x80000000 /* DMA7 Pattern Matching Enabled */
-
-/* Bit masks for MXVR_INT_STAT_0 */
-
-#define                      NI2A  0x1        /* Network Inactive to Active */
-#define                      NA2I  0x2        /* Network Active to Inactive */
-#define                     SBU2L  0x4        /* Super Block Unlock to Lock */
-#define                     SBL2U  0x8        /* Super Block Lock to Unlock */
-#define                       PRU  0x10       /* Position Register Updated */
-#define                      MPRU  0x20       /* Maximum Position Register Updated */
-#define                       DRU  0x40       /* Delay Register Updated */
-#define                      MDRU  0x80       /* Maximum Delay Register Updated */
-#define                       SBU  0x100      /* Synchronous Boundary Updated */
-#define                       ATU  0x200      /* Allocation Table Updated */
-#define                      FCZ0  0x400      /* Frame Counter 0 Zero */
-#define                      FCZ1  0x800      /* Frame Counter 1 Zero */
-#define                      PERR  0x1000     /* Parity Error */
-#define                      MH2L  0x2000     /* MRXONB High to Low */
-#define                      ML2H  0x4000     /* MRXONB Low to High */
-#define                       WUP  0x8000     /* Wake-Up Preamble Received */
-#define                      FU2L  0x10000    /* Frame Unlock to Lock */
-#define                      FL2U  0x20000    /* Frame Lock to Unlock */
-#define                      BU2L  0x40000    /* Block Unlock to Lock */
-#define                      BL2U  0x80000    /* Block Lock to Unlock */
-#define                     OBERR  0x100000   /* DMA Out of Bounds Error */
-#define                       PFL  0x200000   /* PLL Frequency Locked */
-#define                       SCZ  0x400000   /* System Clock Counter Zero */
-#define                      FERR  0x800000   /* FIFO Error */
-#define                       CMR  0x1000000  /* Control Message Received */
-#define                     CMROF  0x2000000  /* Control Message Receive Buffer Overflow */
-#define                      CMTS  0x4000000  /* Control Message Transmit Buffer Successfully Sent */
-#define                      CMTC  0x8000000  /* Control Message Transmit Buffer Successfully Cancelled */
-#define                      RWRC  0x10000000 /* Remote Write Control Message Completed */
-#define                       BCZ  0x20000000 /* Block Counter Zero */
-#define                     BMERR  0x40000000 /* Biphase Mark Coding Error */
-#define                      DERR  0x80000000 /* DMA Error */
-
-/* Bit masks for MXVR_INT_STAT_1 */
-
-#define                    HDONE0  0x1        /* DMA0 Half Done */
-#define                     DONE0  0x2        /* DMA0 Done */
-#define                       APR  0x4        /* Asynchronous Packet Received */
-#define                     APROF  0x8        /* Asynchronous Packet Receive Buffer Overflow */
-#define                    HDONE1  0x10       /* DMA1 Half Done */
-#define                     DONE1  0x20       /* DMA1 Done */
-#define                      APTS  0x40       /* Asynchronous Packet Transmit Buffer Successfully Sent */
-#define                      APTC  0x80       /* Asynchronous Packet Transmit Buffer Successfully Cancelled */
-#define                    HDONE2  0x100      /* DMA2 Half Done */
-#define                     DONE2  0x200      /* DMA2 Done */
-#define                     APRCE  0x400      /* Asynchronous Packet Receive CRC Error */
-#define                     APRPE  0x800      /* Asynchronous Packet Receive Packet Error */
-#define                    HDONE3  0x1000     /* DMA3 Half Done */
-#define                     DONE3  0x2000     /* DMA3 Done */
-#define                    HDONE4  0x10000    /* DMA4 Half Done */
-#define                     DONE4  0x20000    /* DMA4 Done */
-#define                    HDONE5  0x100000   /* DMA5 Half Done */
-#define                     DONE5  0x200000   /* DMA5 Done */
-#define                    HDONE6  0x1000000  /* DMA6 Half Done */
-#define                     DONE6  0x2000000  /* DMA6 Done */
-#define                    HDONE7  0x10000000 /* DMA7 Half Done */
-#define                     DONE7  0x20000000 /* DMA7 Done */
-
-/* Bit masks for MXVR_INT_EN_0 */
-
-#define                    NI2AEN  0x1        /* Network Inactive to Active Interrupt Enable */
-#define                    NA2IEN  0x2        /* Network Active to Inactive Interrupt Enable */
-#define                   SBU2LEN  0x4        /* Super Block Unlock to Lock Interrupt Enable */
-#define                   SBL2UEN  0x8        /* Super Block Lock to Unlock Interrupt Enable */
-#define                     PRUEN  0x10       /* Position Register Updated Interrupt Enable */
-#define                    MPRUEN  0x20       /* Maximum Position Register Updated Interrupt Enable */
-#define                     DRUEN  0x40       /* Delay Register Updated Interrupt Enable */
-#define                    MDRUEN  0x80       /* Maximum Delay Register Updated Interrupt Enable */
-#define                     SBUEN  0x100      /* Synchronous Boundary Updated Interrupt Enable */
-#define                     ATUEN  0x200      /* Allocation Table Updated Interrupt Enable */
-#define                    FCZ0EN  0x400      /* Frame Counter 0 Zero Interrupt Enable */
-#define                    FCZ1EN  0x800      /* Frame Counter 1 Zero Interrupt Enable */
-#define                    PERREN  0x1000     /* Parity Error Interrupt Enable */
-#define                    MH2LEN  0x2000     /* MRXONB High to Low Interrupt Enable */
-#define                    ML2HEN  0x4000     /* MRXONB Low to High Interrupt Enable */
-#define                     WUPEN  0x8000     /* Wake-Up Preamble Received Interrupt Enable */
-#define                    FU2LEN  0x10000    /* Frame Unlock to Lock Interrupt Enable */
-#define                    FL2UEN  0x20000    /* Frame Lock to Unlock Interrupt Enable */
-#define                    BU2LEN  0x40000    /* Block Unlock to Lock Interrupt Enable */
-#define                    BL2UEN  0x80000    /* Block Lock to Unlock Interrupt Enable */
-#define                   OBERREN  0x100000   /* DMA Out of Bounds Error Interrupt Enable */
-#define                     PFLEN  0x200000   /* PLL Frequency Locked Interrupt Enable */
-#define                     SCZEN  0x400000   /* System Clock Counter Zero Interrupt Enable */
-#define                    FERREN  0x800000   /* FIFO Error Interrupt Enable */
-#define                     CMREN  0x1000000  /* Control Message Received Interrupt Enable */
-#define                   CMROFEN  0x2000000  /* Control Message Receive Buffer Overflow Interrupt Enable */
-#define                    CMTSEN  0x4000000  /* Control Message Transmit Buffer Successfully Sent Interrupt Enable */
-#define                    CMTCEN  0x8000000  /* Control Message Transmit Buffer Successfully Cancelled Interrupt Enable */
-#define                    RWRCEN  0x10000000 /* Remote Write Control Message Completed Interrupt Enable */
-#define                     BCZEN  0x20000000 /* Block Counter Zero Interrupt Enable */
-#define                   BMERREN  0x40000000 /* Biphase Mark Coding Error Interrupt Enable */
-#define                    DERREN  0x80000000 /* DMA Error Interrupt Enable */
-
-/* Bit masks for MXVR_INT_EN_1 */
-
-#define                  HDONEEN0  0x1        /* DMA0 Half Done Interrupt Enable */
-#define                   DONEEN0  0x2        /* DMA0 Done Interrupt Enable */
-#define                     APREN  0x4        /* Asynchronous Packet Received Interrupt Enable */
-#define                   APROFEN  0x8        /* Asynchronous Packet Receive Buffer Overflow Interrupt Enable */
-#define                  HDONEEN1  0x10       /* DMA1 Half Done Interrupt Enable */
-#define                   DONEEN1  0x20       /* DMA1 Done Interrupt Enable */
-#define                    APTSEN  0x40       /* Asynchronous Packet Transmit Buffer Successfully Sent Interrupt Enable */
-#define                    APTCEN  0x80       /* Asynchronous Packet Transmit Buffer Successfully Cancelled Interrupt Enable */
-#define                  HDONEEN2  0x100      /* DMA2 Half Done Interrupt Enable */
-#define                   DONEEN2  0x200      /* DMA2 Done Interrupt Enable */
-#define                   APRCEEN  0x400      /* Asynchronous Packet Receive CRC Error Interrupt Enable */
-#define                   APRPEEN  0x800      /* Asynchronous Packet Receive Packet Error Interrupt Enable */
-#define                  HDONEEN3  0x1000     /* DMA3 Half Done Interrupt Enable */
-#define                   DONEEN3  0x2000     /* DMA3 Done Interrupt Enable */
-#define                  HDONEEN4  0x10000    /* DMA4 Half Done Interrupt Enable */
-#define                   DONEEN4  0x20000    /* DMA4 Done Interrupt Enable */
-#define                  HDONEEN5  0x100000   /* DMA5 Half Done Interrupt Enable */
-#define                   DONEEN5  0x200000   /* DMA5 Done Interrupt Enable */
-#define                  HDONEEN6  0x1000000  /* DMA6 Half Done Interrupt Enable */
-#define                   DONEEN6  0x2000000  /* DMA6 Done Interrupt Enable */
-#define                  HDONEEN7  0x10000000 /* DMA7 Half Done Interrupt Enable */
-#define                   DONEEN7  0x20000000 /* DMA7 Done Interrupt Enable */
-
-/* Bit masks for MXVR_POSITION */
-
-#define                  POSITION  0x3f       /* Node Position */
-#define                    PVALID  0x8000     /* Node Position Valid */
-
-/* Bit masks for MXVR_MAX_POSITION */
-
-#define                 MPOSITION  0x3f       /* Maximum Node Position */
-#define                   MPVALID  0x8000     /* Maximum Node Position Valid */
-
-/* Bit masks for MXVR_DELAY */
-
-#define                     DELAY  0x3f       /* Node Frame Delay */
-#define                    DVALID  0x8000     /* Node Frame Delay Valid */
-
-/* Bit masks for MXVR_MAX_DELAY */
-
-#define                    MDELAY  0x3f       /* Maximum Node Frame Delay */
-#define                   MDVALID  0x8000     /* Maximum Node Frame Delay Valid */
-
-/* Bit masks for MXVR_LADDR */
-
-#define                     LADDR  0xffff     /* Logical Address */
-#define                    LVALID  0x80000000 /* Logical Address Valid */
-
-/* Bit masks for MXVR_GADDR */
-
-#define                    GADDRL  0xff       /* Group Address Lower Byte */
-#define                    GVALID  0x8000     /* Group Address Valid */
-
-/* Bit masks for MXVR_AADDR */
-
-#define                     AADDR  0xffff     /* Alternate Address */
-#define                    AVALID  0x80000000 /* Alternate Address Valid */
-
-/* Bit masks for MXVR_ALLOC_0 */
-
-#define                       CL0  0x7f       /* Channel 0 Connection Label */
-#define                      CIU0  0x80       /* Channel 0 In Use */
-#define                       CL1  0x7f00     /* Channel 0 Connection Label */
-#define                      CIU1  0x8000     /* Channel 0 In Use */
-#define                       CL2  0x7f0000   /* Channel 0 Connection Label */
-#define                      CIU2  0x800000   /* Channel 0 In Use */
-#define                       CL3  0x7f000000 /* Channel 0 Connection Label */
-#define                      CIU3  0x80000000 /* Channel 0 In Use */
-
-/* Bit masks for MXVR_ALLOC_1 */
-
-#define                       CL4  0x7f       /* Channel 4 Connection Label */
-#define                      CIU4  0x80       /* Channel 4 In Use */
-#define                       CL5  0x7f00     /* Channel 5 Connection Label */
-#define                      CIU5  0x8000     /* Channel 5 In Use */
-#define                       CL6  0x7f0000   /* Channel 6 Connection Label */
-#define                      CIU6  0x800000   /* Channel 6 In Use */
-#define                       CL7  0x7f000000 /* Channel 7 Connection Label */
-#define                      CIU7  0x80000000 /* Channel 7 In Use */
-
-/* Bit masks for MXVR_ALLOC_2 */
-
-#define                       CL8  0x7f       /* Channel 8 Connection Label */
-#define                      CIU8  0x80       /* Channel 8 In Use */
-#define                       CL9  0x7f00     /* Channel 9 Connection Label */
-#define                      CIU9  0x8000     /* Channel 9 In Use */
-#define                      CL10  0x7f0000   /* Channel 10 Connection Label */
-#define                     CIU10  0x800000   /* Channel 10 In Use */
-#define                      CL11  0x7f000000 /* Channel 11 Connection Label */
-#define                     CIU11  0x80000000 /* Channel 11 In Use */
-
-/* Bit masks for MXVR_ALLOC_3 */
-
-#define                      CL12  0x7f       /* Channel 12 Connection Label */
-#define                     CIU12  0x80       /* Channel 12 In Use */
-#define                      CL13  0x7f00     /* Channel 13 Connection Label */
-#define                     CIU13  0x8000     /* Channel 13 In Use */
-#define                      CL14  0x7f0000   /* Channel 14 Connection Label */
-#define                     CIU14  0x800000   /* Channel 14 In Use */
-#define                      CL15  0x7f000000 /* Channel 15 Connection Label */
-#define                     CIU15  0x80000000 /* Channel 15 In Use */
-
-/* Bit masks for MXVR_ALLOC_4 */
-
-#define                      CL16  0x7f       /* Channel 16 Connection Label */
-#define                     CIU16  0x80       /* Channel 16 In Use */
-#define                      CL17  0x7f00     /* Channel 17 Connection Label */
-#define                     CIU17  0x8000     /* Channel 17 In Use */
-#define                      CL18  0x7f0000   /* Channel 18 Connection Label */
-#define                     CIU18  0x800000   /* Channel 18 In Use */
-#define                      CL19  0x7f000000 /* Channel 19 Connection Label */
-#define                     CIU19  0x80000000 /* Channel 19 In Use */
-
-/* Bit masks for MXVR_ALLOC_5 */
-
-#define                      CL20  0x7f       /* Channel 20 Connection Label */
-#define                     CIU20  0x80       /* Channel 20 In Use */
-#define                      CL21  0x7f00     /* Channel 21 Connection Label */
-#define                     CIU21  0x8000     /* Channel 21 In Use */
-#define                      CL22  0x7f0000   /* Channel 22 Connection Label */
-#define                     CIU22  0x800000   /* Channel 22 In Use */
-#define                      CL23  0x7f000000 /* Channel 23 Connection Label */
-#define                     CIU23  0x80000000 /* Channel 23 In Use */
-
-/* Bit masks for MXVR_ALLOC_6 */
-
-#define                      CL24  0x7f       /* Channel 24 Connection Label */
-#define                     CIU24  0x80       /* Channel 24 In Use */
-#define                      CL25  0x7f00     /* Channel 25 Connection Label */
-#define                     CIU25  0x8000     /* Channel 25 In Use */
-#define                      CL26  0x7f0000   /* Channel 26 Connection Label */
-#define                     CIU26  0x800000   /* Channel 26 In Use */
-#define                      CL27  0x7f000000 /* Channel 27 Connection Label */
-#define                     CIU27  0x80000000 /* Channel 27 In Use */
-
-/* Bit masks for MXVR_ALLOC_7 */
-
-#define                      CL28  0x7f       /* Channel 28 Connection Label */
-#define                     CIU28  0x80       /* Channel 28 In Use */
-#define                      CL29  0x7f00     /* Channel 29 Connection Label */
-#define                     CIU29  0x8000     /* Channel 29 In Use */
-#define                      CL30  0x7f0000   /* Channel 30 Connection Label */
-#define                     CIU30  0x800000   /* Channel 30 In Use */
-#define                      CL31  0x7f000000 /* Channel 31 Connection Label */
-#define                     CIU31  0x80000000 /* Channel 31 In Use */
-
-/* Bit masks for MXVR_ALLOC_8 */
-
-#define                      CL32  0x7f       /* Channel 32 Connection Label */
-#define                     CIU32  0x80       /* Channel 32 In Use */
-#define                      CL33  0x7f00     /* Channel 33 Connection Label */
-#define                     CIU33  0x8000     /* Channel 33 In Use */
-#define                      CL34  0x7f0000   /* Channel 34 Connection Label */
-#define                     CIU34  0x800000   /* Channel 34 In Use */
-#define                      CL35  0x7f000000 /* Channel 35 Connection Label */
-#define                     CIU35  0x80000000 /* Channel 35 In Use */
-
-/* Bit masks for MXVR_ALLOC_9 */
-
-#define                      CL36  0x7f       /* Channel 36 Connection Label */
-#define                     CIU36  0x80       /* Channel 36 In Use */
-#define                      CL37  0x7f00     /* Channel 37 Connection Label */
-#define                     CIU37  0x8000     /* Channel 37 In Use */
-#define                      CL38  0x7f0000   /* Channel 38 Connection Label */
-#define                     CIU38  0x800000   /* Channel 38 In Use */
-#define                      CL39  0x7f000000 /* Channel 39 Connection Label */
-#define                     CIU39  0x80000000 /* Channel 39 In Use */
-
-/* Bit masks for MXVR_ALLOC_10 */
-
-#define                      CL40  0x7f       /* Channel 40 Connection Label */
-#define                     CIU40  0x80       /* Channel 40 In Use */
-#define                      CL41  0x7f00     /* Channel 41 Connection Label */
-#define                     CIU41  0x8000     /* Channel 41 In Use */
-#define                      CL42  0x7f0000   /* Channel 42 Connection Label */
-#define                     CIU42  0x800000   /* Channel 42 In Use */
-#define                      CL43  0x7f000000 /* Channel 43 Connection Label */
-#define                     CIU43  0x80000000 /* Channel 43 In Use */
-
-/* Bit masks for MXVR_ALLOC_11 */
-
-#define                      CL44  0x7f       /* Channel 44 Connection Label */
-#define                     CIU44  0x80       /* Channel 44 In Use */
-#define                      CL45  0x7f00     /* Channel 45 Connection Label */
-#define                     CIU45  0x8000     /* Channel 45 In Use */
-#define                      CL46  0x7f0000   /* Channel 46 Connection Label */
-#define                     CIU46  0x800000   /* Channel 46 In Use */
-#define                      CL47  0x7f000000 /* Channel 47 Connection Label */
-#define                     CIU47  0x80000000 /* Channel 47 In Use */
-
-/* Bit masks for MXVR_ALLOC_12 */
-
-#define                      CL48  0x7f       /* Channel 48 Connection Label */
-#define                     CIU48  0x80       /* Channel 48 In Use */
-#define                      CL49  0x7f00     /* Channel 49 Connection Label */
-#define                     CIU49  0x8000     /* Channel 49 In Use */
-#define                      CL50  0x7f0000   /* Channel 50 Connection Label */
-#define                     CIU50  0x800000   /* Channel 50 In Use */
-#define                      CL51  0x7f000000 /* Channel 51 Connection Label */
-#define                     CIU51  0x80000000 /* Channel 51 In Use */
-
-/* Bit masks for MXVR_ALLOC_13 */
-
-#define                      CL52  0x7f       /* Channel 52 Connection Label */
-#define                     CIU52  0x80       /* Channel 52 In Use */
-#define                      CL53  0x7f00     /* Channel 53 Connection Label */
-#define                     CIU53  0x8000     /* Channel 53 In Use */
-#define                      CL54  0x7f0000   /* Channel 54 Connection Label */
-#define                     CIU54  0x800000   /* Channel 54 In Use */
-#define                      CL55  0x7f000000 /* Channel 55 Connection Label */
-#define                     CIU55  0x80000000 /* Channel 55 In Use */
-
-/* Bit masks for MXVR_ALLOC_14 */
-
-#define                      CL56  0x7f       /* Channel 56 Connection Label */
-#define                     CIU56  0x80       /* Channel 56 In Use */
-#define                      CL57  0x7f00     /* Channel 57 Connection Label */
-#define                     CIU57  0x8000     /* Channel 57 In Use */
-#define                      CL58  0x7f0000   /* Channel 58 Connection Label */
-#define                     CIU58  0x800000   /* Channel 58 In Use */
-#define                      CL59  0x7f000000 /* Channel 59 Connection Label */
-#define                     CIU59  0x80000000 /* Channel 59 In Use */
-
-/* MXVR_SYNC_LCHAN_0 Masks */
-
-#define LCHANPC0     0x0000000Flu
-#define LCHANPC1     0x000000F0lu
-#define LCHANPC2     0x00000F00lu
-#define LCHANPC3     0x0000F000lu
-#define LCHANPC4     0x000F0000lu
-#define LCHANPC5     0x00F00000lu
-#define LCHANPC6     0x0F000000lu
-#define LCHANPC7     0xF0000000lu
-
-
-/* MXVR_SYNC_LCHAN_1 Masks */
-
-#define LCHANPC8     0x0000000Flu
-#define LCHANPC9     0x000000F0lu
-#define LCHANPC10    0x00000F00lu
-#define LCHANPC11    0x0000F000lu
-#define LCHANPC12    0x000F0000lu
-#define LCHANPC13    0x00F00000lu
-#define LCHANPC14    0x0F000000lu
-#define LCHANPC15    0xF0000000lu
-
-
-/* MXVR_SYNC_LCHAN_2 Masks */
-
-#define LCHANPC16    0x0000000Flu
-#define LCHANPC17    0x000000F0lu
-#define LCHANPC18    0x00000F00lu
-#define LCHANPC19    0x0000F000lu
-#define LCHANPC20    0x000F0000lu
-#define LCHANPC21    0x00F00000lu
-#define LCHANPC22    0x0F000000lu
-#define LCHANPC23    0xF0000000lu
-
-
-/* MXVR_SYNC_LCHAN_3 Masks */
-
-#define LCHANPC24    0x0000000Flu
-#define LCHANPC25    0x000000F0lu
-#define LCHANPC26    0x00000F00lu
-#define LCHANPC27    0x0000F000lu
-#define LCHANPC28    0x000F0000lu
-#define LCHANPC29    0x00F00000lu
-#define LCHANPC30    0x0F000000lu
-#define LCHANPC31    0xF0000000lu
-
-
-/* MXVR_SYNC_LCHAN_4 Masks */
-
-#define LCHANPC32    0x0000000Flu
-#define LCHANPC33    0x000000F0lu
-#define LCHANPC34    0x00000F00lu
-#define LCHANPC35    0x0000F000lu
-#define LCHANPC36    0x000F0000lu
-#define LCHANPC37    0x00F00000lu
-#define LCHANPC38    0x0F000000lu
-#define LCHANPC39    0xF0000000lu
-
-
-/* MXVR_SYNC_LCHAN_5 Masks */
-
-#define LCHANPC40    0x0000000Flu
-#define LCHANPC41    0x000000F0lu
-#define LCHANPC42    0x00000F00lu
-#define LCHANPC43    0x0000F000lu
-#define LCHANPC44    0x000F0000lu
-#define LCHANPC45    0x00F00000lu
-#define LCHANPC46    0x0F000000lu
-#define LCHANPC47    0xF0000000lu
-
-
-/* MXVR_SYNC_LCHAN_6 Masks */
-
-#define LCHANPC48    0x0000000Flu
-#define LCHANPC49    0x000000F0lu
-#define LCHANPC50    0x00000F00lu
-#define LCHANPC51    0x0000F000lu
-#define LCHANPC52    0x000F0000lu
-#define LCHANPC53    0x00F00000lu
-#define LCHANPC54    0x0F000000lu
-#define LCHANPC55    0xF0000000lu
-
-
-/* MXVR_SYNC_LCHAN_7 Masks */
-
-#define LCHANPC56    0x0000000Flu
-#define LCHANPC57    0x000000F0lu
-#define LCHANPC58    0x00000F00lu
-#define LCHANPC59    0x0000F000lu
-
-/* Bit masks for MXVR_DMAx_CONFIG */
-
-#define                    MDMAEN  0x1        /* DMA Channel Enable */
-#define                     DMADD  0x2        /* DMA Channel Direction */
-#define                 BY4SWAPEN  0x20       /* DMA Channel Four Byte Swap Enable */
-#define                     LCHAN  0x3c0      /* DMA Channel Logical Channel */
-#define                 BITSWAPEN  0x400      /* DMA Channel Bit Swap Enable */
-#define                 BY2SWAPEN  0x800      /* DMA Channel Two Byte Swap Enable */
-#define                     MFLOW  0x7000     /* DMA Channel Operation Flow */
-#define                   FIXEDPM  0x80000    /* DMA Channel Fixed Pattern Matching Select */
-#define                  STARTPAT  0x300000   /* DMA Channel Start Pattern Select */
-#define                   STOPPAT  0xc00000   /* DMA Channel Stop Pattern Select */
-#define                  COUNTPOS  0x1c000000 /* DMA Channel Count Position */
-
-/* Bit masks for MXVR_AP_CTL */
-
-#define                   STARTAP  0x1        /* Start Asynchronous Packet Transmission */
-#define                  CANCELAP  0x2        /* Cancel Asynchronous Packet Transmission */
-#define                   RESETAP  0x4        /* Reset Asynchronous Packet Arbitration */
-#define                    APRBE0  0x4000     /* Asynchronous Packet Receive Buffer Entry 0 */
-#define                    APRBE1  0x8000     /* Asynchronous Packet Receive Buffer Entry 1 */
-
-/* Bit masks for MXVR_APRB_START_ADDR */
-
-#define      MXVR_APRB_START_ADDR_MASK  0x1fffffe  /* Asynchronous Packet Receive Buffer Start Address */
-
-/* Bit masks for MXVR_APRB_CURR_ADDR */
-
-#define       MXVR_APRB_CURR_ADDR_MASK  0xffffffff /* Asynchronous Packet Receive Buffer Current Address */
-
-/* Bit masks for MXVR_APTB_START_ADDR */
-
-#define       MXVR_APTB_START_ADDR_MASK  0x1fffffe  /* Asynchronous Packet Transmit Buffer Start Address */
-
-/* Bit masks for MXVR_APTB_CURR_ADDR */
-
-#define        MXVR_APTB_CURR_ADDR_MASK  0xffffffff /* Asynchronous Packet Transmit Buffer Current Address */
-
-/* Bit masks for MXVR_CM_CTL */
-
-#define                   STARTCM  0x1        /* Start Control Message Transmission */
-#define                  CANCELCM  0x2        /* Cancel Control Message Transmission */
-#define                    CMRBE0  0x10000    /* Control Message Receive Buffer Entry 0 */
-#define                    CMRBE1  0x20000    /* Control Message Receive Buffer Entry 1 */
-#define                    CMRBE2  0x40000    /* Control Message Receive Buffer Entry 2 */
-#define                    CMRBE3  0x80000    /* Control Message Receive Buffer Entry 3 */
-#define                    CMRBE4  0x100000   /* Control Message Receive Buffer Entry 4 */
-#define                    CMRBE5  0x200000   /* Control Message Receive Buffer Entry 5 */
-#define                    CMRBE6  0x400000   /* Control Message Receive Buffer Entry 6 */
-#define                    CMRBE7  0x800000   /* Control Message Receive Buffer Entry 7 */
-#define                    CMRBE8  0x1000000  /* Control Message Receive Buffer Entry 8 */
-#define                    CMRBE9  0x2000000  /* Control Message Receive Buffer Entry 9 */
-#define                   CMRBE10  0x4000000  /* Control Message Receive Buffer Entry 10 */
-#define                   CMRBE11  0x8000000  /* Control Message Receive Buffer Entry 11 */
-#define                   CMRBE12  0x10000000 /* Control Message Receive Buffer Entry 12 */
-#define                   CMRBE13  0x20000000 /* Control Message Receive Buffer Entry 13 */
-#define                   CMRBE14  0x40000000 /* Control Message Receive Buffer Entry 14 */
-#define                   CMRBE15  0x80000000 /* Control Message Receive Buffer Entry 15 */
-
-/* Bit masks for MXVR_CMRB_START_ADDR */
-
-#define      MXVR_CMRB_START_ADDR_MASK  0x1fffffe  /* Control Message Receive Buffer Start Address */
-
-/* Bit masks for MXVR_CMRB_CURR_ADDR */
-
-#define       MXVR_CMRB_CURR_ADDR_MASK  0xffffffff /* Control Message Receive Buffer Current Address */
-
-/* Bit masks for MXVR_CMTB_START_ADDR */
-
-#define      MXVR_CMTB_START_ADDR_MASK  0x1fffffe  /* Control Message Transmit Buffer Start Address */
-
-/* Bit masks for MXVR_CMTB_CURR_ADDR */
-
-#define       MXVR_CMTB_CURR_ADDR_MASK  0xffffffff /* Control Message Transmit Buffer Current Address */
-
-/* Bit masks for MXVR_RRDB_START_ADDR */
-
-#define      MXVR_RRDB_START_ADDR_MASK  0x1fffffe  /* Remote Read Buffer Start Address */
-
-/* Bit masks for MXVR_RRDB_CURR_ADDR */
-
-#define       MXVR_RRDB_CURR_ADDR_MASK  0xffffffff /* Remote Read Buffer Current Address */
-
-/* Bit masks for MXVR_PAT_DATAx */
-
-#define              MATCH_DATA_0  0xff       /* Pattern Match Data Byte 0 */
-#define              MATCH_DATA_1  0xff00     /* Pattern Match Data Byte 1 */
-#define              MATCH_DATA_2  0xff0000   /* Pattern Match Data Byte 2 */
-#define              MATCH_DATA_3  0xff000000 /* Pattern Match Data Byte 3 */
-
-/* Bit masks for MXVR_PAT_EN_0 */
-
-#define              MATCH_EN_0_0  0x1        /* Pattern Match Enable Byte 0 Bit 0 */
-#define              MATCH_EN_0_1  0x2        /* Pattern Match Enable Byte 0 Bit 1 */
-#define              MATCH_EN_0_2  0x4        /* Pattern Match Enable Byte 0 Bit 2 */
-#define              MATCH_EN_0_3  0x8        /* Pattern Match Enable Byte 0 Bit 3 */
-#define              MATCH_EN_0_4  0x10       /* Pattern Match Enable Byte 0 Bit 4 */
-#define              MATCH_EN_0_5  0x20       /* Pattern Match Enable Byte 0 Bit 5 */
-#define              MATCH_EN_0_6  0x40       /* Pattern Match Enable Byte 0 Bit 6 */
-#define              MATCH_EN_0_7  0x80       /* Pattern Match Enable Byte 0 Bit 7 */
-#define              MATCH_EN_1_0  0x100      /* Pattern Match Enable Byte 1 Bit 0 */
-#define              MATCH_EN_1_1  0x200      /* Pattern Match Enable Byte 1 Bit 1 */
-#define              MATCH_EN_1_2  0x400      /* Pattern Match Enable Byte 1 Bit 2 */
-#define              MATCH_EN_1_3  0x800      /* Pattern Match Enable Byte 1 Bit 3 */
-#define              MATCH_EN_1_4  0x1000     /* Pattern Match Enable Byte 1 Bit 4 */
-#define              MATCH_EN_1_5  0x2000     /* Pattern Match Enable Byte 1 Bit 5 */
-#define              MATCH_EN_1_6  0x4000     /* Pattern Match Enable Byte 1 Bit 6 */
-#define              MATCH_EN_1_7  0x8000     /* Pattern Match Enable Byte 1 Bit 7 */
-#define              MATCH_EN_2_0  0x10000    /* Pattern Match Enable Byte 2 Bit 0 */
-#define              MATCH_EN_2_1  0x20000    /* Pattern Match Enable Byte 2 Bit 1 */
-#define              MATCH_EN_2_2  0x40000    /* Pattern Match Enable Byte 2 Bit 2 */
-#define              MATCH_EN_2_3  0x80000    /* Pattern Match Enable Byte 2 Bit 3 */
-#define              MATCH_EN_2_4  0x100000   /* Pattern Match Enable Byte 2 Bit 4 */
-#define              MATCH_EN_2_5  0x200000   /* Pattern Match Enable Byte 2 Bit 5 */
-#define              MATCH_EN_2_6  0x400000   /* Pattern Match Enable Byte 2 Bit 6 */
-#define              MATCH_EN_2_7  0x800000   /* Pattern Match Enable Byte 2 Bit 7 */
-#define              MATCH_EN_3_0  0x1000000  /* Pattern Match Enable Byte 3 Bit 0 */
-#define              MATCH_EN_3_1  0x2000000  /* Pattern Match Enable Byte 3 Bit 1 */
-#define              MATCH_EN_3_2  0x4000000  /* Pattern Match Enable Byte 3 Bit 2 */
-#define              MATCH_EN_3_3  0x8000000  /* Pattern Match Enable Byte 3 Bit 3 */
-#define              MATCH_EN_3_4  0x10000000 /* Pattern Match Enable Byte 3 Bit 4 */
-#define              MATCH_EN_3_5  0x20000000 /* Pattern Match Enable Byte 3 Bit 5 */
-#define              MATCH_EN_3_6  0x40000000 /* Pattern Match Enable Byte 3 Bit 6 */
-#define              MATCH_EN_3_7  0x80000000 /* Pattern Match Enable Byte 3 Bit 7 */
-
-/* Bit masks for MXVR_PAT_EN_1 */
-
-#define              MATCH_EN_0_0  0x1        /* Pattern Match Enable Byte 0 Bit 0 */
-#define              MATCH_EN_0_1  0x2        /* Pattern Match Enable Byte 0 Bit 1 */
-#define              MATCH_EN_0_2  0x4        /* Pattern Match Enable Byte 0 Bit 2 */
-#define              MATCH_EN_0_3  0x8        /* Pattern Match Enable Byte 0 Bit 3 */
-#define              MATCH_EN_0_4  0x10       /* Pattern Match Enable Byte 0 Bit 4 */
-#define              MATCH_EN_0_5  0x20       /* Pattern Match Enable Byte 0 Bit 5 */
-#define              MATCH_EN_0_6  0x40       /* Pattern Match Enable Byte 0 Bit 6 */
-#define              MATCH_EN_0_7  0x80       /* Pattern Match Enable Byte 0 Bit 7 */
-#define              MATCH_EN_1_0  0x100      /* Pattern Match Enable Byte 1 Bit 0 */
-#define              MATCH_EN_1_1  0x200      /* Pattern Match Enable Byte 1 Bit 1 */
-#define              MATCH_EN_1_2  0x400      /* Pattern Match Enable Byte 1 Bit 2 */
-#define              MATCH_EN_1_3  0x800      /* Pattern Match Enable Byte 1 Bit 3 */
-#define              MATCH_EN_1_4  0x1000     /* Pattern Match Enable Byte 1 Bit 4 */
-#define              MATCH_EN_1_5  0x2000     /* Pattern Match Enable Byte 1 Bit 5 */
-#define              MATCH_EN_1_6  0x4000     /* Pattern Match Enable Byte 1 Bit 6 */
-#define              MATCH_EN_1_7  0x8000     /* Pattern Match Enable Byte 1 Bit 7 */
-#define              MATCH_EN_2_0  0x10000    /* Pattern Match Enable Byte 2 Bit 0 */
-#define              MATCH_EN_2_1  0x20000    /* Pattern Match Enable Byte 2 Bit 1 */
-#define              MATCH_EN_2_2  0x40000    /* Pattern Match Enable Byte 2 Bit 2 */
-#define              MATCH_EN_2_3  0x80000    /* Pattern Match Enable Byte 2 Bit 3 */
-#define              MATCH_EN_2_4  0x100000   /* Pattern Match Enable Byte 2 Bit 4 */
-#define              MATCH_EN_2_5  0x200000   /* Pattern Match Enable Byte 2 Bit 5 */
-#define              MATCH_EN_2_6  0x400000   /* Pattern Match Enable Byte 2 Bit 6 */
-#define              MATCH_EN_2_7  0x800000   /* Pattern Match Enable Byte 2 Bit 7 */
-#define              MATCH_EN_3_0  0x1000000  /* Pattern Match Enable Byte 3 Bit 0 */
-#define              MATCH_EN_3_1  0x2000000  /* Pattern Match Enable Byte 3 Bit 1 */
-#define              MATCH_EN_3_2  0x4000000  /* Pattern Match Enable Byte 3 Bit 2 */
-#define              MATCH_EN_3_3  0x8000000  /* Pattern Match Enable Byte 3 Bit 3 */
-#define              MATCH_EN_3_4  0x10000000 /* Pattern Match Enable Byte 3 Bit 4 */
-#define              MATCH_EN_3_5  0x20000000 /* Pattern Match Enable Byte 3 Bit 5 */
-#define              MATCH_EN_3_6  0x40000000 /* Pattern Match Enable Byte 3 Bit 6 */
-#define              MATCH_EN_3_7  0x80000000 /* Pattern Match Enable Byte 3 Bit 7 */
-
-/* Bit masks for MXVR_FRAME_CNT_0 */
-
-#define                      FCNT  0xffff     /* Frame Count */
-
-/* Bit masks for MXVR_FRAME_CNT_1 */
-
-#define                      FCNT  0xffff     /* Frame Count */
-
-/* Bit masks for MXVR_ROUTING_0 */
-
-#define                    TX_CH0  0x3f       /* Transmit Channel 0 */
-#define                  MUTE_CH0  0x80       /* Mute Channel 0 */
-#define                    TX_CH1  0x3f00     /* Transmit Channel 0 */
-#define                  MUTE_CH1  0x8000     /* Mute Channel 0 */
-#define                    TX_CH2  0x3f0000   /* Transmit Channel 0 */
-#define                  MUTE_CH2  0x800000   /* Mute Channel 0 */
-#define                    TX_CH3  0x3f000000 /* Transmit Channel 0 */
-#define                  MUTE_CH3  0x80000000 /* Mute Channel 0 */
-
-/* Bit masks for MXVR_ROUTING_1 */
-
-#define                    TX_CH4  0x3f       /* Transmit Channel 4 */
-#define                  MUTE_CH4  0x80       /* Mute Channel 4 */
-#define                    TX_CH5  0x3f00     /* Transmit Channel 5 */
-#define                  MUTE_CH5  0x8000     /* Mute Channel 5 */
-#define                    TX_CH6  0x3f0000   /* Transmit Channel 6 */
-#define                  MUTE_CH6  0x800000   /* Mute Channel 6 */
-#define                    TX_CH7  0x3f000000 /* Transmit Channel 7 */
-#define                  MUTE_CH7  0x80000000 /* Mute Channel 7 */
-
-/* Bit masks for MXVR_ROUTING_2 */
-
-#define                    TX_CH8  0x3f       /* Transmit Channel 8 */
-#define                  MUTE_CH8  0x80       /* Mute Channel 8 */
-#define                    TX_CH9  0x3f00     /* Transmit Channel 9 */
-#define                  MUTE_CH9  0x8000     /* Mute Channel 9 */
-#define                   TX_CH10  0x3f0000   /* Transmit Channel 10 */
-#define                 MUTE_CH10  0x800000   /* Mute Channel 10 */
-#define                   TX_CH11  0x3f000000 /* Transmit Channel 11 */
-#define                 MUTE_CH11  0x80000000 /* Mute Channel 11 */
-
-/* Bit masks for MXVR_ROUTING_3 */
-
-#define                   TX_CH12  0x3f       /* Transmit Channel 12 */
-#define                 MUTE_CH12  0x80       /* Mute Channel 12 */
-#define                   TX_CH13  0x3f00     /* Transmit Channel 13 */
-#define                 MUTE_CH13  0x8000     /* Mute Channel 13 */
-#define                   TX_CH14  0x3f0000   /* Transmit Channel 14 */
-#define                 MUTE_CH14  0x800000   /* Mute Channel 14 */
-#define                   TX_CH15  0x3f000000 /* Transmit Channel 15 */
-#define                 MUTE_CH15  0x80000000 /* Mute Channel 15 */
-
-/* Bit masks for MXVR_ROUTING_4 */
-
-#define                   TX_CH16  0x3f       /* Transmit Channel 16 */
-#define                 MUTE_CH16  0x80       /* Mute Channel 16 */
-#define                   TX_CH17  0x3f00     /* Transmit Channel 17 */
-#define                 MUTE_CH17  0x8000     /* Mute Channel 17 */
-#define                   TX_CH18  0x3f0000   /* Transmit Channel 18 */
-#define                 MUTE_CH18  0x800000   /* Mute Channel 18 */
-#define                   TX_CH19  0x3f000000 /* Transmit Channel 19 */
-#define                 MUTE_CH19  0x80000000 /* Mute Channel 19 */
-
-/* Bit masks for MXVR_ROUTING_5 */
-
-#define                   TX_CH20  0x3f       /* Transmit Channel 20 */
-#define                 MUTE_CH20  0x80       /* Mute Channel 20 */
-#define                   TX_CH21  0x3f00     /* Transmit Channel 21 */
-#define                 MUTE_CH21  0x8000     /* Mute Channel 21 */
-#define                   TX_CH22  0x3f0000   /* Transmit Channel 22 */
-#define                 MUTE_CH22  0x800000   /* Mute Channel 22 */
-#define                   TX_CH23  0x3f000000 /* Transmit Channel 23 */
-#define                 MUTE_CH23  0x80000000 /* Mute Channel 23 */
-
-/* Bit masks for MXVR_ROUTING_6 */
-
-#define                   TX_CH24  0x3f       /* Transmit Channel 24 */
-#define                 MUTE_CH24  0x80       /* Mute Channel 24 */
-#define                   TX_CH25  0x3f00     /* Transmit Channel 25 */
-#define                 MUTE_CH25  0x8000     /* Mute Channel 25 */
-#define                   TX_CH26  0x3f0000   /* Transmit Channel 26 */
-#define                 MUTE_CH26  0x800000   /* Mute Channel 26 */
-#define                   TX_CH27  0x3f000000 /* Transmit Channel 27 */
-#define                 MUTE_CH27  0x80000000 /* Mute Channel 27 */
-
-/* Bit masks for MXVR_ROUTING_7 */
-
-#define                   TX_CH28  0x3f       /* Transmit Channel 28 */
-#define                 MUTE_CH28  0x80       /* Mute Channel 28 */
-#define                   TX_CH29  0x3f00     /* Transmit Channel 29 */
-#define                 MUTE_CH29  0x8000     /* Mute Channel 29 */
-#define                   TX_CH30  0x3f0000   /* Transmit Channel 30 */
-#define                 MUTE_CH30  0x800000   /* Mute Channel 30 */
-#define                   TX_CH31  0x3f000000 /* Transmit Channel 31 */
-#define                 MUTE_CH31  0x80000000 /* Mute Channel 31 */
-
-/* Bit masks for MXVR_ROUTING_8 */
-
-#define                   TX_CH32  0x3f       /* Transmit Channel 32 */
-#define                 MUTE_CH32  0x80       /* Mute Channel 32 */
-#define                   TX_CH33  0x3f00     /* Transmit Channel 33 */
-#define                 MUTE_CH33  0x8000     /* Mute Channel 33 */
-#define                   TX_CH34  0x3f0000   /* Transmit Channel 34 */
-#define                 MUTE_CH34  0x800000   /* Mute Channel 34 */
-#define                   TX_CH35  0x3f000000 /* Transmit Channel 35 */
-#define                 MUTE_CH35  0x80000000 /* Mute Channel 35 */
-
-/* Bit masks for MXVR_ROUTING_9 */
-
-#define                   TX_CH36  0x3f       /* Transmit Channel 36 */
-#define                 MUTE_CH36  0x80       /* Mute Channel 36 */
-#define                   TX_CH37  0x3f00     /* Transmit Channel 37 */
-#define                 MUTE_CH37  0x8000     /* Mute Channel 37 */
-#define                   TX_CH38  0x3f0000   /* Transmit Channel 38 */
-#define                 MUTE_CH38  0x800000   /* Mute Channel 38 */
-#define                   TX_CH39  0x3f000000 /* Transmit Channel 39 */
-#define                 MUTE_CH39  0x80000000 /* Mute Channel 39 */
-
-/* Bit masks for MXVR_ROUTING_10 */
-
-#define                   TX_CH40  0x3f       /* Transmit Channel 40 */
-#define                 MUTE_CH40  0x80       /* Mute Channel 40 */
-#define                   TX_CH41  0x3f00     /* Transmit Channel 41 */
-#define                 MUTE_CH41  0x8000     /* Mute Channel 41 */
-#define                   TX_CH42  0x3f0000   /* Transmit Channel 42 */
-#define                 MUTE_CH42  0x800000   /* Mute Channel 42 */
-#define                   TX_CH43  0x3f000000 /* Transmit Channel 43 */
-#define                 MUTE_CH43  0x80000000 /* Mute Channel 43 */
-
-/* Bit masks for MXVR_ROUTING_11 */
-
-#define                   TX_CH44  0x3f       /* Transmit Channel 44 */
-#define                 MUTE_CH44  0x80       /* Mute Channel 44 */
-#define                   TX_CH45  0x3f00     /* Transmit Channel 45 */
-#define                 MUTE_CH45  0x8000     /* Mute Channel 45 */
-#define                   TX_CH46  0x3f0000   /* Transmit Channel 46 */
-#define                 MUTE_CH46  0x800000   /* Mute Channel 46 */
-#define                   TX_CH47  0x3f000000 /* Transmit Channel 47 */
-#define                 MUTE_CH47  0x80000000 /* Mute Channel 47 */
-
-/* Bit masks for MXVR_ROUTING_12 */
-
-#define                   TX_CH48  0x3f       /* Transmit Channel 48 */
-#define                 MUTE_CH48  0x80       /* Mute Channel 48 */
-#define                   TX_CH49  0x3f00     /* Transmit Channel 49 */
-#define                 MUTE_CH49  0x8000     /* Mute Channel 49 */
-#define                   TX_CH50  0x3f0000   /* Transmit Channel 50 */
-#define                 MUTE_CH50  0x800000   /* Mute Channel 50 */
-#define                   TX_CH51  0x3f000000 /* Transmit Channel 51 */
-#define                 MUTE_CH51  0x80000000 /* Mute Channel 51 */
-
-/* Bit masks for MXVR_ROUTING_13 */
-
-#define                   TX_CH52  0x3f       /* Transmit Channel 52 */
-#define                 MUTE_CH52  0x80       /* Mute Channel 52 */
-#define                   TX_CH53  0x3f00     /* Transmit Channel 53 */
-#define                 MUTE_CH53  0x8000     /* Mute Channel 53 */
-#define                   TX_CH54  0x3f0000   /* Transmit Channel 54 */
-#define                 MUTE_CH54  0x800000   /* Mute Channel 54 */
-#define                   TX_CH55  0x3f000000 /* Transmit Channel 55 */
-#define                 MUTE_CH55  0x80000000 /* Mute Channel 55 */
-
-/* Bit masks for MXVR_ROUTING_14 */
-
-#define                   TX_CH56  0x3f       /* Transmit Channel 56 */
-#define                 MUTE_CH56  0x80       /* Mute Channel 56 */
-#define                   TX_CH57  0x3f00     /* Transmit Channel 57 */
-#define                 MUTE_CH57  0x8000     /* Mute Channel 57 */
-#define                   TX_CH58  0x3f0000   /* Transmit Channel 58 */
-#define                 MUTE_CH58  0x800000   /* Mute Channel 58 */
-#define                   TX_CH59  0x3f000000 /* Transmit Channel 59 */
-#define                 MUTE_CH59  0x80000000 /* Mute Channel 59 */
-
-/* Bit masks for MXVR_BLOCK_CNT */
-
-#define                      BCNT  0xffff     /* Block Count */
-
-/* Bit masks for MXVR_CLK_CTL */
-
-#define                  MXTALCEN  0x1        /* MXVR Crystal Oscillator Clock Enable */
-#define                  MXTALFEN  0x2        /* MXVR Crystal Oscillator Feedback Enable */
-#define                  MXTALMUL  0x30       /* MXVR Crystal Multiplier */
-#define                  CLKX3SEL  0x80       /* Clock Generation Source Select */
-#define                   MMCLKEN  0x100      /* Master Clock Enable */
-#define                  MMCLKMUL  0x1e00     /* Master Clock Multiplication Factor */
-#define                   PLLSMPS  0xe000     /* MXVR PLL State Machine Prescaler */
-#define                   MBCLKEN  0x10000    /* Bit Clock Enable */
-#define                  MBCLKDIV  0x1e0000   /* Bit Clock Divide Factor */
-#define                     INVRX  0x800000   /* Invert Receive Data */
-#define                     MFSEN  0x1000000  /* Frame Sync Enable */
-#define                    MFSDIV  0x1e000000 /* Frame Sync Divide Factor */
-#define                    MFSSEL  0x60000000 /* Frame Sync Select */
-#define                   MFSSYNC  0x80000000 /* Frame Sync Synchronization Select */
-
-/* Bit masks for MXVR_CDRPLL_CTL */
-
-#define                   CDRSMEN  0x1        /* MXVR CDRPLL State Machine Enable */
-#define                   CDRRSTB  0x2        /* MXVR CDRPLL Reset */
-#define                   CDRSVCO  0x4        /* MXVR CDRPLL Start VCO */
-#define                   CDRMODE  0x8        /* MXVR CDRPLL CDR Mode Select */
-#define                   CDRSCNT  0x3f0      /* MXVR CDRPLL Start Counter */
-#define                   CDRLCNT  0xfc00     /* MXVR CDRPLL Lock Counter */
-#define                 CDRSHPSEL  0x3f0000   /* MXVR CDRPLL Shaper Select */
-#define                  CDRSHPEN  0x800000   /* MXVR CDRPLL Shaper Enable */
-#define                  CDRCPSEL  0xff000000 /* MXVR CDRPLL Charge Pump Current Select */
-
-/* Bit masks for MXVR_FMPLL_CTL */
-
-#define                    FMSMEN  0x1        /* MXVR FMPLL State Machine Enable */
-#define                    FMRSTB  0x2        /* MXVR FMPLL Reset */
-#define                    FMSVCO  0x4        /* MXVR FMPLL Start VCO */
-#define                    FMSCNT  0x3f0      /* MXVR FMPLL Start Counter */
-#define                    FMLCNT  0xfc00     /* MXVR FMPLL Lock Counter */
-#define                   FMCPSEL  0xff000000 /* MXVR FMPLL Charge Pump Current Select */
-
-/* Bit masks for MXVR_PIN_CTL */
-
-#define                  MTXONBOD  0x1        /* MTXONB Open Drain Select */
-#define                   MTXONBG  0x2        /* MTXONB Gates MTX Select */
-#define                     MFSOE  0x10       /* MFS Output Enable */
-#define                  MFSGPSEL  0x20       /* MFS General Purpose Output Select */
-#define                  MFSGPDAT  0x40       /* MFS General Purpose Output Data */
-
-/* Bit masks for MXVR_SCLK_CNT */
-
-#define                      SCNT  0xffff     /* System Clock Count */
-
-/* Bit masks for KPAD_CTL */
-
-#define                   KPAD_EN  0x1        /* Keypad Enable */
-#define              KPAD_IRQMODE  0x6        /* Key Press Interrupt Enable */
-#define                KPAD_ROWEN  0x1c00     /* Row Enable Width */
-#define                KPAD_COLEN  0xe000     /* Column Enable Width */
-
-/* Bit masks for KPAD_PRESCALE */
-
-#define         KPAD_PRESCALE_VAL  0x3f       /* Key Prescale Value */
-
-/* Bit masks for KPAD_MSEL */
-
-#define                DBON_SCALE  0xff       /* Debounce Scale Value */
-#define              COLDRV_SCALE  0xff00     /* Column Driver Scale Value */
-
-/* Bit masks for KPAD_ROWCOL */
-
-#define                  KPAD_ROW  0xff       /* Rows Pressed */
-#define                  KPAD_COL  0xff00     /* Columns Pressed */
-
-/* Bit masks for KPAD_STAT */
-
-#define                  KPAD_IRQ  0x1        /* Keypad Interrupt Status */
-#define              KPAD_MROWCOL  0x6        /* Multiple Row/Column Keypress Status */
-#define              KPAD_PRESSED  0x8        /* Key press current status */
-
-/* Bit masks for KPAD_SOFTEVAL */
-
-#define           KPAD_SOFTEVAL_E  0x2        /* Software Programmable Force Evaluate */
-
-/* Bit masks for SDH_COMMAND */
-
-#define                   CMD_IDX  0x3f       /* Command Index */
-#define                   CMD_RSP  0x40       /* Response */
-#define                 CMD_L_RSP  0x80       /* Long Response */
-#define                 CMD_INT_E  0x100      /* Command Interrupt */
-#define                CMD_PEND_E  0x200      /* Command Pending */
-#define                     CMD_E  0x400      /* Command Enable */
-
-/* Bit masks for SDH_PWR_CTL */
-
-#define                    PWR_ON  0x3        /* Power On */
-#if 0
-#define                       TBD  0x3c       /* TBD */
-#endif
-#define                 SD_CMD_OD  0x40       /* Open Drain Output */
-#define                   ROD_CTL  0x80       /* Rod Control */
-
-/* Bit masks for SDH_CLK_CTL */
-
-#define                    CLKDIV  0xff       /* MC_CLK Divisor */
-#define                     CLK_E  0x100      /* MC_CLK Bus Clock Enable */
-#define                  PWR_SV_E  0x200      /* Power Save Enable */
-#define             CLKDIV_BYPASS  0x400      /* Bypass Divisor */
-#define                  WIDE_BUS  0x800      /* Wide Bus Mode Enable */
-
-/* Bit masks for SDH_RESP_CMD */
-
-#define                  RESP_CMD  0x3f       /* Response Command */
-
-/* Bit masks for SDH_DATA_CTL */
-
-#define                     DTX_E  0x1        /* Data Transfer Enable */
-#define                   DTX_DIR  0x2        /* Data Transfer Direction */
-#define                  DTX_MODE  0x4        /* Data Transfer Mode */
-#define                 DTX_DMA_E  0x8        /* Data Transfer DMA Enable */
-#define              DTX_BLK_LGTH  0xf0       /* Data Transfer Block Length */
-
-/* Bit masks for SDH_STATUS */
-
-#define              CMD_CRC_FAIL  0x1        /* CMD CRC Fail */
-#define              DAT_CRC_FAIL  0x2        /* Data CRC Fail */
-#define               CMD_TIME_OUT  0x4        /* CMD Time Out */
-#define               DAT_TIME_OUT  0x8        /* Data Time Out */
-#define               TX_UNDERRUN  0x10       /* Transmit Underrun */
-#define                RX_OVERRUN  0x20       /* Receive Overrun */
-#define              CMD_RESP_END  0x40       /* CMD Response End */
-#define                  CMD_SENT  0x80       /* CMD Sent */
-#define                   DAT_END  0x100      /* Data End */
-#define             START_BIT_ERR  0x200      /* Start Bit Error */
-#define               DAT_BLK_END  0x400      /* Data Block End */
-#define                   CMD_ACT  0x800      /* CMD Active */
-#define                    TX_ACT  0x1000     /* Transmit Active */
-#define                    RX_ACT  0x2000     /* Receive Active */
-#define              TX_FIFO_STAT  0x4000     /* Transmit FIFO Status */
-#define              RX_FIFO_STAT  0x8000     /* Receive FIFO Status */
-#define              TX_FIFO_FULL  0x10000    /* Transmit FIFO Full */
-#define              RX_FIFO_FULL  0x20000    /* Receive FIFO Full */
-#define              TX_FIFO_ZERO  0x40000    /* Transmit FIFO Empty */
-#define               RX_DAT_ZERO  0x80000    /* Receive FIFO Empty */
-#define                TX_DAT_RDY  0x100000   /* Transmit Data Available */
-#define               RX_FIFO_RDY  0x200000   /* Receive Data Available */
-
-/* Bit masks for SDH_STATUS_CLR */
-
-#define         CMD_CRC_FAIL_STAT  0x1        /* CMD CRC Fail Status */
-#define         DAT_CRC_FAIL_STAT  0x2        /* Data CRC Fail Status */
-#define          CMD_TIMEOUT_STAT  0x4        /* CMD Time Out Status */
-#define          DAT_TIMEOUT_STAT  0x8        /* Data Time Out status */
-#define          TX_UNDERRUN_STAT  0x10       /* Transmit Underrun Status */
-#define           RX_OVERRUN_STAT  0x20       /* Receive Overrun Status */
-#define         CMD_RESP_END_STAT  0x40       /* CMD Response End Status */
-#define             CMD_SENT_STAT  0x80       /* CMD Sent Status */
-#define              DAT_END_STAT  0x100      /* Data End Status */
-#define        START_BIT_ERR_STAT  0x200      /* Start Bit Error Status */
-#define          DAT_BLK_END_STAT  0x400      /* Data Block End Status */
-
-/* Bit masks for SDH_MASK0 */
-
-#define         CMD_CRC_FAIL_MASK  0x1        /* CMD CRC Fail Mask */
-#define         DAT_CRC_FAIL_MASK  0x2        /* Data CRC Fail Mask */
-#define          CMD_TIMEOUT_MASK  0x4        /* CMD Time Out Mask */
-#define          DAT_TIMEOUT_MASK  0x8        /* Data Time Out Mask */
-#define          TX_UNDERRUN_MASK  0x10       /* Transmit Underrun Mask */
-#define           RX_OVERRUN_MASK  0x20       /* Receive Overrun Mask */
-#define         CMD_RESP_END_MASK  0x40       /* CMD Response End Mask */
-#define             CMD_SENT_MASK  0x80       /* CMD Sent Mask */
-#define              DAT_END_MASK  0x100      /* Data End Mask */
-#define        START_BIT_ERR_MASK  0x200      /* Start Bit Error Mask */
-#define          DAT_BLK_END_MASK  0x400      /* Data Block End Mask */
-#define              CMD_ACT_MASK  0x800      /* CMD Active Mask */
-#define               TX_ACT_MASK  0x1000     /* Transmit Active Mask */
-#define               RX_ACT_MASK  0x2000     /* Receive Active Mask */
-#define         TX_FIFO_STAT_MASK  0x4000     /* Transmit FIFO Status Mask */
-#define         RX_FIFO_STAT_MASK  0x8000     /* Receive FIFO Status Mask */
-#define         TX_FIFO_FULL_MASK  0x10000    /* Transmit FIFO Full Mask */
-#define         RX_FIFO_FULL_MASK  0x20000    /* Receive FIFO Full Mask */
-#define         TX_FIFO_ZERO_MASK  0x40000    /* Transmit FIFO Empty Mask */
-#define          RX_DAT_ZERO_MASK  0x80000    /* Receive FIFO Empty Mask */
-#define           TX_DAT_RDY_MASK  0x100000   /* Transmit Data Available Mask */
-#define          RX_FIFO_RDY_MASK  0x200000   /* Receive Data Available Mask */
-
-/* Bit masks for SDH_FIFO_CNT */
-
-#define                FIFO_COUNT  0x7fff     /* FIFO Count */
-
-/* Bit masks for SDH_E_STATUS */
-
-#define              SDIO_INT_DET  0x2        /* SDIO Int Detected */
-#define               SD_CARD_DET  0x10       /* SD Card Detect */
-
-/* Bit masks for SDH_E_MASK */
-
-#define                  SDIO_MSK  0x2        /* Mask SDIO Int Detected */
-#define                   SCD_MSK  0x40       /* Mask Card Detect */
-
-/* Bit masks for SDH_CFG */
-
-#define                   CLKS_EN  0x1        /* Clocks Enable */
-#define                      SD4E  0x4        /* SDIO 4-Bit Enable */
-#define                       MWE  0x8        /* Moving Window Enable */
-#define                    SD_RST  0x10       /* SDMMC Reset */
-#define                 PUP_SDDAT  0x20       /* Pull-up SD_DAT */
-#define                PUP_SDDAT3  0x40       /* Pull-up SD_DAT3 */
-#define                 PD_SDDAT3  0x80       /* Pull-down SD_DAT3 */
-
-/* Bit masks for SDH_RD_WAIT_EN */
-
-#define                       RWR  0x1        /* Read Wait Request */
-
-/* Bit masks for ATAPI_CONTROL */
-
-#define                 PIO_START  0x1        /* Start PIO/Reg Op */
-#define               MULTI_START  0x2        /* Start Multi-DMA Op */
-#define               ULTRA_START  0x4        /* Start Ultra-DMA Op */
-#define                  XFER_DIR  0x8        /* Transfer Direction */
-#define                  IORDY_EN  0x10       /* IORDY Enable */
-#define                FIFO_FLUSH  0x20       /* Flush FIFOs */
-#define                  SOFT_RST  0x40       /* Soft Reset */
-#define                   DEV_RST  0x80       /* Device Reset */
-#define                TFRCNT_RST  0x100      /* Trans Count Reset */
-#define               END_ON_TERM  0x200      /* End/Terminate Select */
-#define               PIO_USE_DMA  0x400      /* PIO-DMA Enable */
-#define          UDMAIN_FIFO_THRS  0xf000     /* Ultra DMA-IN FIFO Threshold */
-
-/* Bit masks for ATAPI_STATUS */
-
-#define               PIO_XFER_ON  0x1        /* PIO transfer in progress */
-#define             MULTI_XFER_ON  0x2        /* Multi-word DMA transfer in progress */
-#define             ULTRA_XFER_ON  0x4        /* Ultra DMA transfer in progress */
-#define               ULTRA_IN_FL  0xf0       /* Ultra DMA Input FIFO Level */
-
-/* Bit masks for ATAPI_DEV_ADDR */
-
-#define                  DEV_ADDR  0x1f       /* Device Address */
-
-/* Bit masks for ATAPI_INT_MASK */
-
-#define        ATAPI_DEV_INT_MASK  0x1        /* Device interrupt mask */
-#define             PIO_DONE_MASK  0x2        /* PIO transfer done interrupt mask */
-#define           MULTI_DONE_MASK  0x4        /* Multi-DMA transfer done interrupt mask */
-#define          UDMAIN_DONE_MASK  0x8        /* Ultra-DMA in transfer done interrupt mask */
-#define         UDMAOUT_DONE_MASK  0x10       /* Ultra-DMA out transfer done interrupt mask */
-#define       HOST_TERM_XFER_MASK  0x20       /* Host terminate current transfer interrupt mask */
-#define           MULTI_TERM_MASK  0x40       /* Device terminate Multi-DMA transfer interrupt mask */
-#define          UDMAIN_TERM_MASK  0x80       /* Device terminate Ultra-DMA-in transfer interrupt mask */
-#define         UDMAOUT_TERM_MASK  0x100      /* Device terminate Ultra-DMA-out transfer interrupt mask */
-
-/* Bit masks for ATAPI_INT_STATUS */
-
-#define             ATAPI_DEV_INT  0x1        /* Device interrupt status */
-#define              PIO_DONE_INT  0x2        /* PIO transfer done interrupt status */
-#define            MULTI_DONE_INT  0x4        /* Multi-DMA transfer done interrupt status */
-#define           UDMAIN_DONE_INT  0x8        /* Ultra-DMA in transfer done interrupt status */
-#define          UDMAOUT_DONE_INT  0x10       /* Ultra-DMA out transfer done interrupt status */
-#define        HOST_TERM_XFER_INT  0x20       /* Host terminate current transfer interrupt status */
-#define            MULTI_TERM_INT  0x40       /* Device terminate Multi-DMA transfer interrupt status */
-#define           UDMAIN_TERM_INT  0x80       /* Device terminate Ultra-DMA-in transfer interrupt status */
-#define          UDMAOUT_TERM_INT  0x100      /* Device terminate Ultra-DMA-out transfer interrupt status */
-
-/* Bit masks for ATAPI_LINE_STATUS */
-
-#define                ATAPI_INTR  0x1        /* Device interrupt to host line status */
-#define                ATAPI_DASP  0x2        /* Device dasp to host line status */
-#define                ATAPI_CS0N  0x4        /* ATAPI chip select 0 line status */
-#define                ATAPI_CS1N  0x8        /* ATAPI chip select 1 line status */
-#define                ATAPI_ADDR  0x70       /* ATAPI address line status */
-#define              ATAPI_DMAREQ  0x80       /* ATAPI DMA request line status */
-#define             ATAPI_DMAACKN  0x100      /* ATAPI DMA acknowledge line status */
-#define               ATAPI_DIOWN  0x200      /* ATAPI write line status */
-#define               ATAPI_DIORN  0x400      /* ATAPI read line status */
-#define               ATAPI_IORDY  0x800      /* ATAPI IORDY line status */
-
-/* Bit masks for ATAPI_SM_STATE */
-
-#define                PIO_CSTATE  0xf        /* PIO mode state machine current state */
-#define                DMA_CSTATE  0xf0       /* DMA mode state machine current state */
-#define             UDMAIN_CSTATE  0xf00      /* Ultra DMA-In mode state machine current state */
-#define            UDMAOUT_CSTATE  0xf000     /* ATAPI IORDY line status */
-
-/* Bit masks for ATAPI_TERMINATE */
-
-#define           ATAPI_HOST_TERM  0x1        /* Host terminationation */
-
-/* Bit masks for ATAPI_REG_TIM_0 */
-
-#define                    T2_REG  0xff       /* End of cycle time for register access transfers */
-#define                  TEOC_REG  0xff00     /* Selects DIOR/DIOW pulsewidth */
-
-/* Bit masks for ATAPI_PIO_TIM_0 */
-
-#define                    T1_REG  0xf        /* Time from address valid to DIOR/DIOW */
-#define                T2_REG_PIO  0xff0      /* DIOR/DIOW pulsewidth */
-#define                    T4_REG  0xf000     /* DIOW data hold */
-
-/* Bit masks for ATAPI_PIO_TIM_1 */
-
-#define              TEOC_REG_PIO  0xff       /* End of cycle time for PIO access transfers. */
-
-/* Bit masks for ATAPI_MULTI_TIM_0 */
-
-#define                        TD  0xff       /* DIOR/DIOW asserted pulsewidth */
-#define                        TM  0xff00     /* Time from address valid to DIOR/DIOW */
-
-/* Bit masks for ATAPI_MULTI_TIM_1 */
-
-#define                       TKW  0xff       /* Selects DIOW negated pulsewidth */
-#define                       TKR  0xff00     /* Selects DIOR negated pulsewidth */
-
-/* Bit masks for ATAPI_MULTI_TIM_2 */
-
-#define                        TH  0xff       /* Selects DIOW data hold */
-#define                      TEOC  0xff00     /* Selects end of cycle for DMA */
-
-/* Bit masks for ATAPI_ULTRA_TIM_0 */
-
-#define                      TACK  0xff       /* Selects setup and hold times for TACK */
-#define                      TENV  0xff00     /* Selects envelope time */
-
-/* Bit masks for ATAPI_ULTRA_TIM_1 */
-
-#define                      TDVS  0xff       /* Selects data valid setup time */
-#define                 TCYC_TDVS  0xff00     /* Selects cycle time - TDVS time */
-
-/* Bit masks for ATAPI_ULTRA_TIM_2 */
-
-#define                       TSS  0xff       /* Selects time from STROBE edge to negation of DMARQ or assertion of STOP */
-#define                      TMLI  0xff00     /* Selects interlock time */
-
-/* Bit masks for ATAPI_ULTRA_TIM_3 */
-
-#define                      TZAH  0xff       /* Selects minimum delay required for output */
-#define               READY_PAUSE  0xff00     /* Selects ready to pause */
-
-/* Bit masks for TIMER_ENABLE1 */
-
-#define                    TIMEN8  0x1        /* Timer 8 Enable */
-#define                    TIMEN9  0x2        /* Timer 9 Enable */
-#define                   TIMEN10  0x4        /* Timer 10 Enable */
-
-/* Bit masks for TIMER_DISABLE1 */
-
-#define                   TIMDIS8  0x1        /* Timer 8 Disable */
-#define                   TIMDIS9  0x2        /* Timer 9 Disable */
-#define                  TIMDIS10  0x4        /* Timer 10 Disable */
-
-/* Bit masks for TIMER_STATUS1 */
-
-#define                    TIMIL8  0x1        /* Timer 8 Interrupt */
-#define                    TIMIL9  0x2        /* Timer 9 Interrupt */
-#define                   TIMIL10  0x4        /* Timer 10 Interrupt */
-#define                 TOVF_ERR8  0x10       /* Timer 8 Counter Overflow */
-#define                 TOVF_ERR9  0x20       /* Timer 9 Counter Overflow */
-#define                TOVF_ERR10  0x40       /* Timer 10 Counter Overflow */
-#define                     TRUN8  0x1000     /* Timer 8 Slave Enable Status */
-#define                     TRUN9  0x2000     /* Timer 9 Slave Enable Status */
-#define                    TRUN10  0x4000     /* Timer 10 Slave Enable Status */
-
-/* Bit masks for EPPI0 are obtained from common base header for EPPIx (EPPI1 and EPPI2) */
-
-/* Bit masks for USB_FADDR */
-
-#define          FUNCTION_ADDRESS  0x7f       /* Function address */
-
-/* Bit masks for USB_POWER */
-
-#define           ENABLE_SUSPENDM  0x1        /* enable SuspendM output */
-#define              SUSPEND_MODE  0x2        /* Suspend Mode indicator */
-#define               RESUME_MODE  0x4        /* DMA Mode */
-#define                     RESET  0x8        /* Reset indicator */
-#define                   HS_MODE  0x10       /* High Speed mode indicator */
-#define                 HS_ENABLE  0x20       /* high Speed Enable */
-#define                 SOFT_CONN  0x40       /* Soft connect */
-#define                ISO_UPDATE  0x80       /* Isochronous update */
-
-/* Bit masks for USB_INTRTX */
-
-#define                    EP0_TX  0x1        /* Tx Endpoint 0 interrupt */
-#define                    EP1_TX  0x2        /* Tx Endpoint 1 interrupt */
-#define                    EP2_TX  0x4        /* Tx Endpoint 2 interrupt */
-#define                    EP3_TX  0x8        /* Tx Endpoint 3 interrupt */
-#define                    EP4_TX  0x10       /* Tx Endpoint 4 interrupt */
-#define                    EP5_TX  0x20       /* Tx Endpoint 5 interrupt */
-#define                    EP6_TX  0x40       /* Tx Endpoint 6 interrupt */
-#define                    EP7_TX  0x80       /* Tx Endpoint 7 interrupt */
-
-/* Bit masks for USB_INTRRX */
-
-#define                    EP1_RX  0x2        /* Rx Endpoint 1 interrupt */
-#define                    EP2_RX  0x4        /* Rx Endpoint 2 interrupt */
-#define                    EP3_RX  0x8        /* Rx Endpoint 3 interrupt */
-#define                    EP4_RX  0x10       /* Rx Endpoint 4 interrupt */
-#define                    EP5_RX  0x20       /* Rx Endpoint 5 interrupt */
-#define                    EP6_RX  0x40       /* Rx Endpoint 6 interrupt */
-#define                    EP7_RX  0x80       /* Rx Endpoint 7 interrupt */
-
-/* Bit masks for USB_INTRTXE */
-
-#define                  EP0_TX_E  0x1        /* Endpoint 0 interrupt Enable */
-#define                  EP1_TX_E  0x2        /* Tx Endpoint 1 interrupt  Enable */
-#define                  EP2_TX_E  0x4        /* Tx Endpoint 2 interrupt  Enable */
-#define                  EP3_TX_E  0x8        /* Tx Endpoint 3 interrupt  Enable */
-#define                  EP4_TX_E  0x10       /* Tx Endpoint 4 interrupt  Enable */
-#define                  EP5_TX_E  0x20       /* Tx Endpoint 5 interrupt  Enable */
-#define                  EP6_TX_E  0x40       /* Tx Endpoint 6 interrupt  Enable */
-#define                  EP7_TX_E  0x80       /* Tx Endpoint 7 interrupt  Enable */
-
-/* Bit masks for USB_INTRRXE */
-
-#define                  EP1_RX_E  0x2        /* Rx Endpoint 1 interrupt  Enable */
-#define                  EP2_RX_E  0x4        /* Rx Endpoint 2 interrupt  Enable */
-#define                  EP3_RX_E  0x8        /* Rx Endpoint 3 interrupt  Enable */
-#define                  EP4_RX_E  0x10       /* Rx Endpoint 4 interrupt  Enable */
-#define                  EP5_RX_E  0x20       /* Rx Endpoint 5 interrupt  Enable */
-#define                  EP6_RX_E  0x40       /* Rx Endpoint 6 interrupt  Enable */
-#define                  EP7_RX_E  0x80       /* Rx Endpoint 7 interrupt  Enable */
-
-/* Bit masks for USB_INTRUSB */
-
-#define                 SUSPEND_B  0x1        /* Suspend indicator */
-#define                  RESUME_B  0x2        /* Resume indicator */
-#define          RESET_OR_BABLE_B  0x4        /* Reset/babble indicator */
-#define                     SOF_B  0x8        /* Start of frame */
-#define                    CONN_B  0x10       /* Connection indicator */
-#define                  DISCON_B  0x20       /* Disconnect indicator */
-#define             SESSION_REQ_B  0x40       /* Session Request */
-#define              VBUS_ERROR_B  0x80       /* Vbus threshold indicator */
-
-/* Bit masks for USB_INTRUSBE */
-
-#define                SUSPEND_BE  0x1        /* Suspend indicator int enable */
-#define                 RESUME_BE  0x2        /* Resume indicator int enable */
-#define         RESET_OR_BABLE_BE  0x4        /* Reset/babble indicator int enable */
-#define                    SOF_BE  0x8        /* Start of frame int enable */
-#define                   CONN_BE  0x10       /* Connection indicator int enable */
-#define                 DISCON_BE  0x20       /* Disconnect indicator int enable */
-#define            SESSION_REQ_BE  0x40       /* Session Request int enable */
-#define             VBUS_ERROR_BE  0x80       /* Vbus threshold indicator int enable */
-
-/* Bit masks for USB_FRAME */
-
-#define              FRAME_NUMBER  0x7ff      /* Frame number */
-
-/* Bit masks for USB_INDEX */
-
-#define         SELECTED_ENDPOINT  0xf        /* selected endpoint */
-
-/* Bit masks for USB_GLOBAL_CTL */
-
-#define                GLOBAL_ENA  0x1        /* enables USB module */
-#define                EP1_TX_ENA  0x2        /* Transmit endpoint 1 enable */
-#define                EP2_TX_ENA  0x4        /* Transmit endpoint 2 enable */
-#define                EP3_TX_ENA  0x8        /* Transmit endpoint 3 enable */
-#define                EP4_TX_ENA  0x10       /* Transmit endpoint 4 enable */
-#define                EP5_TX_ENA  0x20       /* Transmit endpoint 5 enable */
-#define                EP6_TX_ENA  0x40       /* Transmit endpoint 6 enable */
-#define                EP7_TX_ENA  0x80       /* Transmit endpoint 7 enable */
-#define                EP1_RX_ENA  0x100      /* Receive endpoint 1 enable */
-#define                EP2_RX_ENA  0x200      /* Receive endpoint 2 enable */
-#define                EP3_RX_ENA  0x400      /* Receive endpoint 3 enable */
-#define                EP4_RX_ENA  0x800      /* Receive endpoint 4 enable */
-#define                EP5_RX_ENA  0x1000     /* Receive endpoint 5 enable */
-#define                EP6_RX_ENA  0x2000     /* Receive endpoint 6 enable */
-#define                EP7_RX_ENA  0x4000     /* Receive endpoint 7 enable */
-
-/* Bit masks for USB_OTG_DEV_CTL */
-
-#define                   SESSION  0x1        /* session indicator */
-#define                  HOST_REQ  0x2        /* Host negotiation request */
-#define                 HOST_MODE  0x4        /* indicates USBDRC is a host */
-#define                     VBUS0  0x8        /* Vbus level indicator[0] */
-#define                     VBUS1  0x10       /* Vbus level indicator[1] */
-#define                     LSDEV  0x20       /* Low-speed indicator */
-#define                     FSDEV  0x40       /* Full or High-speed indicator */
-#define                  B_DEVICE  0x80       /* A' or 'B' device indicator */
-
-/* Bit masks for USB_OTG_VBUS_IRQ */
-
-#define             DRIVE_VBUS_ON  0x1        /* indicator to drive VBUS control circuit */
-#define            DRIVE_VBUS_OFF  0x2        /* indicator to shut off charge pump */
-#define           CHRG_VBUS_START  0x4        /* indicator for external circuit to start charging VBUS */
-#define             CHRG_VBUS_END  0x8        /* indicator for external circuit to end charging VBUS */
-#define        DISCHRG_VBUS_START  0x10       /* indicator to start discharging VBUS */
-#define          DISCHRG_VBUS_END  0x20       /* indicator to stop discharging VBUS */
-
-/* Bit masks for USB_OTG_VBUS_MASK */
-
-#define         DRIVE_VBUS_ON_ENA  0x1        /* enable DRIVE_VBUS_ON interrupt */
-#define        DRIVE_VBUS_OFF_ENA  0x2        /* enable DRIVE_VBUS_OFF interrupt */
-#define       CHRG_VBUS_START_ENA  0x4        /* enable CHRG_VBUS_START interrupt */
-#define         CHRG_VBUS_END_ENA  0x8        /* enable CHRG_VBUS_END interrupt */
-#define    DISCHRG_VBUS_START_ENA  0x10       /* enable DISCHRG_VBUS_START interrupt */
-#define      DISCHRG_VBUS_END_ENA  0x20       /* enable DISCHRG_VBUS_END interrupt */
-
-/* Bit masks for USB_CSR0 */
-
-#define                  RXPKTRDY  0x1        /* data packet receive indicator */
-#define                  TXPKTRDY  0x2        /* data packet in FIFO indicator */
-#define                STALL_SENT  0x4        /* STALL handshake sent */
-#define                   DATAEND  0x8        /* Data end indicator */
-#define                  SETUPEND  0x10       /* Setup end */
-#define                 SENDSTALL  0x20       /* Send STALL handshake */
-#define         SERVICED_RXPKTRDY  0x40       /* used to clear the RxPktRdy bit */
-#define         SERVICED_SETUPEND  0x80       /* used to clear the SetupEnd bit */
-#define                 FLUSHFIFO  0x100      /* flush endpoint FIFO */
-#define          STALL_RECEIVED_H  0x4        /* STALL handshake received host mode */
-#define                SETUPPKT_H  0x8        /* send Setup token host mode */
-#define                   ERROR_H  0x10       /* timeout error indicator host mode */
-#define                  REQPKT_H  0x20       /* Request an IN transaction host mode */
-#define               STATUSPKT_H  0x40       /* Status stage transaction host mode */
-#define             NAK_TIMEOUT_H  0x80       /* EP0 halted after a NAK host mode */
-
-/* Bit masks for USB_COUNT0 */
-
-#define              EP0_RX_COUNT  0x7f       /* number of received bytes in EP0 FIFO */
-
-/* Bit masks for USB_NAKLIMIT0 */
-
-#define             EP0_NAK_LIMIT  0x1f       /* number of frames/micro frames after which EP0 timeouts */
-
-/* Bit masks for USB_TX_MAX_PACKET */
-
-#define         MAX_PACKET_SIZE_T  0x7ff      /* maximum data pay load in a frame */
-
-/* Bit masks for USB_RX_MAX_PACKET */
-
-#define         MAX_PACKET_SIZE_R  0x7ff      /* maximum data pay load in a frame */
-
-/* Bit masks for USB_TXCSR */
-
-#define                TXPKTRDY_T  0x1        /* data packet in FIFO indicator */
-#define          FIFO_NOT_EMPTY_T  0x2        /* FIFO not empty */
-#define                UNDERRUN_T  0x4        /* TxPktRdy not set  for an IN token */
-#define               FLUSHFIFO_T  0x8        /* flush endpoint FIFO */
-#define              STALL_SEND_T  0x10       /* issue a Stall handshake */
-#define              STALL_SENT_T  0x20       /* Stall handshake transmitted */
-#define        CLEAR_DATATOGGLE_T  0x40       /* clear endpoint data toggle */
-#define                INCOMPTX_T  0x80       /* indicates that a large packet is split */
-#define              DMAREQMODE_T  0x400      /* DMA mode (0 or 1) selection */
-#define        FORCE_DATATOGGLE_T  0x800      /* Force data toggle */
-#define              DMAREQ_ENA_T  0x1000     /* Enable DMA request for Tx EP */
-#define                     ISO_T  0x4000     /* enable Isochronous transfers */
-#define                 AUTOSET_T  0x8000     /* allows TxPktRdy to be set automatically */
-#define                  ERROR_TH  0x4        /* error condition host mode */
-#define         STALL_RECEIVED_TH  0x20       /* Stall handshake received host mode */
-#define            NAK_TIMEOUT_TH  0x80       /* NAK timeout host mode */
-
-/* Bit masks for USB_TXCOUNT */
-
-#define                  TX_COUNT  0x1fff     /* Number of bytes to be written to the selected endpoint Tx FIFO */
-
-/* Bit masks for USB_RXCSR */
-
-#define                RXPKTRDY_R  0x1        /* data packet in FIFO indicator */
-#define               FIFO_FULL_R  0x2        /* FIFO not empty */
-#define                 OVERRUN_R  0x4        /* TxPktRdy not set  for an IN token */
-#define               DATAERROR_R  0x8        /* Out packet cannot be loaded into Rx  FIFO */
-#define               FLUSHFIFO_R  0x10       /* flush endpoint FIFO */
-#define              STALL_SEND_R  0x20       /* issue a Stall handshake */
-#define              STALL_SENT_R  0x40       /* Stall handshake transmitted */
-#define        CLEAR_DATATOGGLE_R  0x80       /* clear endpoint data toggle */
-#define                INCOMPRX_R  0x100      /* indicates that a large packet is split */
-#define              DMAREQMODE_R  0x800      /* DMA mode (0 or 1) selection */
-#define                 DISNYET_R  0x1000     /* disable Nyet handshakes */
-#define              DMAREQ_ENA_R  0x2000     /* Enable DMA request for Tx EP */
-#define                     ISO_R  0x4000     /* enable Isochronous transfers */
-#define               AUTOCLEAR_R  0x8000     /* allows TxPktRdy to be set automatically */
-#define                  ERROR_RH  0x4        /* TxPktRdy not set  for an IN token host mode */
-#define                 REQPKT_RH  0x20       /* request an IN transaction host mode */
-#define         STALL_RECEIVED_RH  0x40       /* Stall handshake received host mode */
-#define               INCOMPRX_RH  0x100      /* indicates that a large packet is split host mode */
-#define             DMAREQMODE_RH  0x800      /* DMA mode (0 or 1) selection host mode */
-#define                AUTOREQ_RH  0x4000     /* sets ReqPkt automatically host mode */
-
-/* Bit masks for USB_RXCOUNT */
-
-#define                  RX_COUNT  0x1fff     /* Number of received bytes in the packet in the Rx FIFO */
-
-/* Bit masks for USB_TXTYPE */
-
-#define            TARGET_EP_NO_T  0xf        /* EP number */
-#define                PROTOCOL_T  0xc        /* transfer type */
-
-/* Bit masks for USB_TXINTERVAL */
-
-#define          TX_POLL_INTERVAL  0xff       /* polling interval for selected Tx EP */
-
-/* Bit masks for USB_RXTYPE */
-
-#define            TARGET_EP_NO_R  0xf        /* EP number */
-#define                PROTOCOL_R  0xc        /* transfer type */
-
-/* Bit masks for USB_RXINTERVAL */
-
-#define          RX_POLL_INTERVAL  0xff       /* polling interval for selected Rx EP */
-
-/* Bit masks for USB_DMA_INTERRUPT */
-
-#define                  DMA0_INT  0x1        /* DMA0 pending interrupt */
-#define                  DMA1_INT  0x2        /* DMA1 pending interrupt */
-#define                  DMA2_INT  0x4        /* DMA2 pending interrupt */
-#define                  DMA3_INT  0x8        /* DMA3 pending interrupt */
-#define                  DMA4_INT  0x10       /* DMA4 pending interrupt */
-#define                  DMA5_INT  0x20       /* DMA5 pending interrupt */
-#define                  DMA6_INT  0x40       /* DMA6 pending interrupt */
-#define                  DMA7_INT  0x80       /* DMA7 pending interrupt */
-
-/* Bit masks for USB_DMAxCONTROL */
-
-#define                   DMA_ENA  0x1        /* DMA enable */
-#define                 DIRECTION  0x2        /* direction of DMA transfer */
-#define                      MODE  0x4        /* DMA Bus error */
-#define                   INT_ENA  0x8        /* Interrupt enable */
-#define                     EPNUM  0xf0       /* EP number */
-#define                  BUSERROR  0x100      /* DMA Bus error */
-
-/* Bit masks for USB_DMAxADDRHIGH */
-
-#define             DMA_ADDR_HIGH  0xffff     /* Upper 16-bits of memory source/destination address for the DMA master channel */
-
-/* Bit masks for USB_DMAxADDRLOW */
-
-#define              DMA_ADDR_LOW  0xffff     /* Lower 16-bits of memory source/destination address for the DMA master channel */
-
-/* Bit masks for USB_DMAxCOUNTHIGH */
-
-#define            DMA_COUNT_HIGH  0xffff     /* Upper 16-bits of byte count of DMA transfer for DMA master channel */
-
-/* Bit masks for USB_DMAxCOUNTLOW */
-
-#define             DMA_COUNT_LOW  0xffff     /* Lower 16-bits of byte count of DMA transfer for DMA master channel */
-
-/* Bit masks for HMDMAx_CONTROL */
-
-#define                   HMDMAEN  0x1        /* Handshake MDMA Enable */
-#define                       REP  0x2        /* Handshake MDMA Request Polarity */
-#define                       UTE  0x8        /* Urgency Threshold Enable */
-#define                       OIE  0x10       /* Overflow Interrupt Enable */
-#define                      BDIE  0x20       /* Block Done Interrupt Enable */
-#define                      MBDI  0x40       /* Mask Block Done Interrupt */
-#define                       DRQ  0x300      /* Handshake MDMA Request Type */
-#define                       RBC  0x1000     /* Force Reload of BCOUNT */
-#define                        PS  0x2000     /* Pin Status */
-#define                        OI  0x4000     /* Overflow Interrupt Generated */
-#define                       BDI  0x8000     /* Block Done Interrupt Generated */
-
-/* ******************************************* */
-/*     MULTI BIT MACRO ENUMERATIONS            */
-/* ******************************************* */
-
-/* ************************ */
-/*   MXVR Address Offsets   */
-/* ************************ */
-
-/* Control Message Receive Buffer (CMRB) Address Offsets */
-
-#define CMRB_STRIDE       0x00000016lu
-
-#define CMRB_DST_OFFSET   0x00000000lu
-#define CMRB_SRC_OFFSET   0x00000002lu
-#define CMRB_DATA_OFFSET  0x00000005lu
-
-/* Control Message Transmit Buffer (CMTB) Address Offsets */
-
-#define CMTB_PRIO_OFFSET    0x00000000lu
-#define CMTB_DST_OFFSET     0x00000002lu
-#define CMTB_SRC_OFFSET     0x00000004lu
-#define CMTB_TYPE_OFFSET    0x00000006lu
-#define CMTB_DATA_OFFSET    0x00000007lu
-
-#define CMTB_ANSWER_OFFSET  0x0000000Alu
-
-#define CMTB_STAT_N_OFFSET  0x00000018lu
-#define CMTB_STAT_A_OFFSET  0x00000016lu
-#define CMTB_STAT_D_OFFSET  0x0000000Elu
-#define CMTB_STAT_R_OFFSET  0x00000014lu
-#define CMTB_STAT_W_OFFSET  0x00000014lu
-#define CMTB_STAT_G_OFFSET  0x00000014lu
-
-/* Asynchronous Packet Receive Buffer (APRB) Address Offsets */
-
-#define APRB_STRIDE       0x00000400lu
-
-#define APRB_DST_OFFSET   0x00000000lu
-#define APRB_LEN_OFFSET   0x00000002lu
-#define APRB_SRC_OFFSET   0x00000004lu
-#define APRB_DATA_OFFSET  0x00000006lu
-
-/* Asynchronous Packet Transmit Buffer (APTB) Address Offsets */
-
-#define APTB_PRIO_OFFSET  0x00000000lu
-#define APTB_DST_OFFSET   0x00000002lu
-#define APTB_LEN_OFFSET   0x00000004lu
-#define APTB_SRC_OFFSET   0x00000006lu
-#define APTB_DATA_OFFSET  0x00000008lu
-
-/* Remote Read Buffer (RRDB) Address Offsets */
-
-#define RRDB_WADDR_OFFSET 0x00000100lu
-#define RRDB_WLEN_OFFSET  0x00000101lu
-
-/* **************** */
-/*   MXVR Macros    */
-/* **************** */
-
-/* MXVR_CONFIG Macros */
-
-#define SET_MSB(x)       ( ( (x) & 0xF  ) << 9)
-
-/* MXVR_INT_STAT_1 Macros */
-
-#define DONEX(x)         (0x00000002 << (4 * (x)))
-#define HDONEX(x)        (0x00000001 << (4 * (x)))
-
-/* MXVR_INT_EN_1 Macros */
-
-#define DONEENX(x)       (0x00000002 << (4 * (x)))
-#define HDONEENX(x)      (0x00000001 << (4 * (x)))
-
-/* MXVR_CDRPLL_CTL Macros */
-
-#define SET_CDRSHPSEL(x) ( ( (x) & 0x3F ) << 16)
-
-/* MXVR_FMPLL_CTL Macros */
-
-#define SET_CDRCPSEL(x)  ( ( (x) & 0xFF ) << 24)
-#define SET_FMCPSEL(x)   ( ( (x) & 0xFF ) << 24)
-
 #endif /* _DEF_BF549_H */
diff --git a/arch/blackfin/mach-bf548/include/mach/defBF54x_base.h b/arch/blackfin/mach-bf548/include/mach/defBF54x_base.h
index 8590c8c78336..ab04d137fd8b 100644
--- a/arch/blackfin/mach-bf548/include/mach/defBF54x_base.h
+++ b/arch/blackfin/mach-bf548/include/mach/defBF54x_base.h
@@ -1609,44 +1609,6 @@
 #define                 PINT2  0x40000000 /* Pin Interrupt 2 */
 #define                 PINT3  0x80000000 /* Pin Interrupt 3 */
 
-/* Bit masks for DMAx_CONFIG, MDMA_Sx_CONFIG, MDMA_Dx_CONFIG */
-
-#define                     DMAEN  0x1        /* DMA Channel Enable */
-#define                       WNR  0x2        /* DMA Direction */
-#define                  WDSIZE_8  0x0        /* Transfer Word Size = 8 */
-#define                 WDSIZE_16  0x4        /* Transfer Word Size = 16 */
-#define                 WDSIZE_32  0x8        /* Transfer Word Size = 32 */
-#define                     DMA2D  0x10       /* DMA Mode */
-#define                   RESTART  0x20       /* Work Unit Transitions */
-#define                    DI_SEL  0x40       /* Data Interrupt Timing Select */
-#define                     DI_EN  0x80       /* Data Interrupt Enable */
-
-#define                    NDSIZE  0xf00      /* Flex Descriptor Size */
-#define                  NDSIZE_0 0x0000      /* Next Descriptor Size = 0 (Stop/Autobuffer) */
-#define                  NDSIZE_1 0x0100      /* Next Descriptor Size = 1 */
-#define                  NDSIZE_2 0x0200      /* Next Descriptor Size = 2 */
-#define                  NDSIZE_3 0x0300      /* Next Descriptor Size = 3 */
-#define                  NDSIZE_4 0x0400      /* Next Descriptor Size = 4 */
-#define                  NDSIZE_5 0x0500      /* Next Descriptor Size = 5 */
-#define                  NDSIZE_6 0x0600      /* Next Descriptor Size = 6 */
-#define                  NDSIZE_7 0x0700      /* Next Descriptor Size = 7 */
-#define                  NDSIZE_8 0x0800      /* Next Descriptor Size = 8 */
-#define                  NDSIZE_9 0x0900      /* Next Descriptor Size = 9 */
-
-#define                   DMAFLOW  0xf000     /* Next Operation */
-#define              DMAFLOW_STOP  0x0000     /* Stop Mode */
-#define              DMAFLOW_AUTO  0x1000     /* Autobuffer Mode */
-#define             DMAFLOW_ARRAY  0x4000     /* Descriptor Array Mode */
-#define             DMAFLOW_SMALL  0x6000     /* Small Model Descriptor List Mode */
-#define             DMAFLOW_LARGE  0x7000     /* Large Model Descriptor List Mode */
-
-/* Bit masks for DMAx_IRQ_STATUS, MDMA_Sx_IRQ_STATUS, MDMA_Dx_IRQ_STATUS */
-
-#define                  DMA_DONE  0x1        /* DMA Completion Interrupt Status */
-#define                   DMA_ERR  0x2        /* DMA Error Interrupt Status */
-#define                    DFETCH  0x4        /* DMA Descriptor Fetch */
-#define                   DMA_RUN  0x8        /* DMA Channel Running */
-
 /* Bit masks for DMAx_PERIPHERAL_MAP, MDMA_Sx_IRQ_STATUS, MDMA_Dx_IRQ_STATUS */
 
 #define                     CTYPE  0x40       /* DMA Channel Type */
@@ -1815,10 +1777,6 @@
 #define               DEB3_MERROR  0x40       /* DEB3 Error (2nd) */
 #define               CORE_MERROR  0x80       /* Core Error (2nd) */
 
-/* Bit masks for EBIU_ERRADD */
-
-#define             ERROR_ADDRESS  0xffffffff /* Error Address */
-
 /* Bit masks for EBIU_RSTCTL */
 
 #define                 DDRSRESET  0x1        /* DDR soft reset */
@@ -1827,98 +1785,6 @@
 #define                     SRACK  0x10       /* Self-refresh acknowledge */
 #define                MDDRENABLE  0x20       /* Mobile DDR enable */
 
-/* Bit masks for EBIU_DDRBRC0 */
-
-#define                      BRC0  0xffffffff /* Count */
-
-/* Bit masks for EBIU_DDRBRC1 */
-
-#define                      BRC1  0xffffffff /* Count */
-
-/* Bit masks for EBIU_DDRBRC2 */
-
-#define                      BRC2  0xffffffff /* Count */
-
-/* Bit masks for EBIU_DDRBRC3 */
-
-#define                      BRC3  0xffffffff /* Count */
-
-/* Bit masks for EBIU_DDRBRC4 */
-
-#define                      BRC4  0xffffffff /* Count */
-
-/* Bit masks for EBIU_DDRBRC5 */
-
-#define                      BRC5  0xffffffff /* Count */
-
-/* Bit masks for EBIU_DDRBRC6 */
-
-#define                      BRC6  0xffffffff /* Count */
-
-/* Bit masks for EBIU_DDRBRC7 */
-
-#define                      BRC7  0xffffffff /* Count */
-
-/* Bit masks for EBIU_DDRBWC0 */
-
-#define                      BWC0  0xffffffff /* Count */
-
-/* Bit masks for EBIU_DDRBWC1 */
-
-#define                      BWC1  0xffffffff /* Count */
-
-/* Bit masks for EBIU_DDRBWC2 */
-
-#define                      BWC2  0xffffffff /* Count */
-
-/* Bit masks for EBIU_DDRBWC3 */
-
-#define                      BWC3  0xffffffff /* Count */
-
-/* Bit masks for EBIU_DDRBWC4 */
-
-#define                      BWC4  0xffffffff /* Count */
-
-/* Bit masks for EBIU_DDRBWC5 */
-
-#define                      BWC5  0xffffffff /* Count */
-
-/* Bit masks for EBIU_DDRBWC6 */
-
-#define                      BWC6  0xffffffff /* Count */
-
-/* Bit masks for EBIU_DDRBWC7 */
-
-#define                      BWC7  0xffffffff /* Count */
-
-/* Bit masks for EBIU_DDRACCT */
-
-#define                      ACCT  0xffffffff /* Count */
-
-/* Bit masks for EBIU_DDRTACT */
-
-#define                      TECT  0xffffffff /* Count */
-
-/* Bit masks for EBIU_DDRARCT */
-
-#define                      ARCT  0xffffffff /* Count */
-
-/* Bit masks for EBIU_DDRGC0 */
-
-#define                       GC0  0xffffffff /* Count */
-
-/* Bit masks for EBIU_DDRGC1 */
-
-#define                       GC1  0xffffffff /* Count */
-
-/* Bit masks for EBIU_DDRGC2 */
-
-#define                       GC2  0xffffffff /* Count */
-
-/* Bit masks for EBIU_DDRGC3 */
-
-#define                       GC3  0xffffffff /* Count */
-
 /* Bit masks for EBIU_DDRMCEN */
 
 #define                B0WCENABLE  0x1        /* Bank 0 write count enable */
@@ -2092,12 +1958,6 @@
 #define                     TRUN6  0x40000000 /* Timer 6 Slave Enable Status */
 #define                     TRUN7  0x80000000 /* Timer 7 Slave Enable Status */
 
-/* Bit masks for WDOG_CTL */
-
-#define                      WDEV  0x6        /* Watchdog Event */
-#define                      WDEN  0xff0      /* Watchdog Enable */
-#define                      WDRO  0x8000     /* Watchdog Rolled Over */
-
 /* Bit masks for CNT_CONFIG */
 
 #define                      CNTE  0x1        /* Counter Enable */
@@ -2149,81 +2009,6 @@
 
 #define                 DPRESCALE  0xf        /* Load Counter Register */
 
-/* Bit masks for RTC_STAT */
-
-#define                   SECONDS  0x3f       /* Seconds */
-#define                   MINUTES  0xfc0      /* Minutes */
-#define                     HOURS  0x1f000    /* Hours */
-#define               DAY_COUNTER  0xfffe0000 /* Day Counter */
-
-/* Bit masks for RTC_ICTL */
-
-#define STOPWATCH_INTERRUPT_ENABLE  0x1        /* Stopwatch Interrupt Enable */
-#define    ALARM_INTERRUPT_ENABLE  0x2        /* Alarm Interrupt Enable */
-#define  SECONDS_INTERRUPT_ENABLE  0x4        /* Seconds Interrupt Enable */
-#define  MINUTES_INTERRUPT_ENABLE  0x8        /* Minutes Interrupt Enable */
-#define    HOURS_INTERRUPT_ENABLE  0x10       /* Hours Interrupt Enable */
-#define TWENTY_FOUR_HOURS_INTERRUPT_ENABLE  0x20       /* 24 Hours Interrupt Enable */
-#define DAY_ALARM_INTERRUPT_ENABLE  0x40       /* Day Alarm Interrupt Enable */
-#define WRITE_COMPLETE_INTERRUPT_ENABLE  0x8000     /* Write Complete Interrupt Enable */
-
-/* Bit masks for RTC_ISTAT */
-
-#define      STOPWATCH_EVENT_FLAG  0x1        /* Stopwatch Event Flag */
-#define          ALARM_EVENT_FLAG  0x2        /* Alarm Event Flag */
-#define        SECONDS_EVENT_FLAG  0x4        /* Seconds Event Flag */
-#define        MINUTES_EVENT_FLAG  0x8        /* Minutes Event Flag */
-#define          HOURS_EVENT_FLAG  0x10       /* Hours Event Flag */
-#define TWENTY_FOUR_HOURS_EVENT_FLAG  0x20       /* 24 Hours Event Flag */
-#define      DAY_ALARM_EVENT_FLAG  0x40       /* Day Alarm Event Flag */
-#define     WRITE_PENDING__STATUS  0x4000     /* Write Pending  Status */
-#define            WRITE_COMPLETE  0x8000     /* Write Complete */
-
-/* Bit masks for RTC_SWCNT */
-
-#define           STOPWATCH_COUNT  0xffff     /* Stopwatch Count */
-
-/* Bit masks for RTC_ALARM */
-
-#define                   SECONDS  0x3f       /* Seconds */
-#define                   MINUTES  0xfc0      /* Minutes */
-#define                     HOURS  0x1f000    /* Hours */
-#define                       DAY  0xfffe0000 /* Day */
-
-/* Bit masks for RTC_PREN */
-
-#define                      PREN  0x1        /* Prescaler Enable */
-
-/* Bit masks for OTP_CONTROL */
-
-#define                FUSE_FADDR  0x1ff      /* OTP/Fuse Address */
-#define                      FIEN  0x800      /* OTP/Fuse Interrupt Enable */
-#define                  FTESTDEC  0x1000     /* OTP/Fuse Test Decoder */
-#define                   FWRTEST  0x2000     /* OTP/Fuse Write Test */
-#define                     FRDEN  0x4000     /* OTP/Fuse Read Enable */
-#define                     FWREN  0x8000     /* OTP/Fuse Write Enable */
-
-/* Bit masks for OTP_BEN */
-
-#define                      FBEN  0xffff     /* OTP/Fuse Byte Enable */
-
-/* Bit masks for OTP_STATUS */
-
-#define                     FCOMP  0x1        /* OTP/Fuse Access Complete */
-#define                    FERROR  0x2        /* OTP/Fuse Access Error */
-#define                  MMRGLOAD  0x10       /* Memory Mapped Register Gasket Load */
-#define                  MMRGLOCK  0x20       /* Memory Mapped Register Gasket Lock */
-#define                    FPGMEN  0x40       /* OTP/Fuse Program Enable */
-
-/* Bit masks for OTP_TIMING */
-
-#define                   USECDIV  0xff       /* Micro Second Divider */
-#define                   READACC  0x7f00     /* Read Access Time */
-#define                   CPUMPRL  0x38000    /* Charge Pump Release Time */
-#define                   CPUMPSU  0xc0000    /* Charge Pump Setup Time */
-#define                   CPUMPHD  0xf00000   /* Charge Pump Hold Time */
-#define                   PGMTIME  0xff000000 /* Program Time */
-
 /* Bit masks for SECURE_SYSSWT */
 
 #define                   EMUDABL  0x1        /* Emulation Disable. */
@@ -2252,26 +2037,6 @@
 #define                    AFEXIT  0x10       /* Authentication Firmware Exit */
 #define                   SECSTAT  0xe0       /* Secure Status */
 
-/* Bit masks for PLL_DIV */
-
-#define                      CSEL  0x30       /* Core Select */
-#define                      SSEL  0xf        /* System Select */
-#define                 CSEL_DIV1       0x0000  /* CCLK = VCO / 1 */
-#define                 CSEL_DIV2       0x0010  /* CCLK = VCO / 2 */
-#define                 CSEL_DIV4       0x0020  /* CCLK = VCO / 4 */
-#define                 CSEL_DIV8       0x0030  /* CCLK = VCO / 8 */
-
-/* Bit masks for PLL_CTL */
-
-#define                      MSEL  0x7e00     /* Multiplier Select */
-#define                    BYPASS  0x100      /* PLL Bypass Enable */
-#define              OUTPUT_DELAY  0x80       /* External Memory Output Delay Enable */
-#define               INPUT_DELAY  0x40       /* External Memory Input Delay Enable */
-#define                      PDWN  0x20       /* Power Down */
-#define                    STOPCK  0x8        /* Stop Clock */
-#define                   PLL_OFF  0x2        /* Disable PLL */
-#define                        DF  0x1        /* Divide Frequency */
-
 /* SWRST Masks */
 #define              SYSTEM_RESET 0x0007       /* Initiates A System Software Reset */
 #define              DOUBLE_FAULT 0x0008       /* Core Double Fault Causes Reset */
@@ -2279,52 +2044,6 @@
 #define                RESET_WDOG 0x4000       /* SW Reset Generated By Watchdog Timer */
 #define            RESET_SOFTWARE 0x8000       /* SW Reset Occurred Since Last Read Of SWRST */
 
-/* Bit masks for PLL_STAT */
-
-#define                PLL_LOCKED  0x20       /* PLL Locked Status */
-#define        ACTIVE_PLLDISABLED  0x4        /* Active Mode With PLL Disabled */
-#define                   FULL_ON  0x2        /* Full-On Mode */
-#define         ACTIVE_PLLENABLED  0x1        /* Active Mode With PLL Enabled */
-#define                     RTCWS  0x400      /* RTC/Reset Wake-Up Status */
-#define                     CANWS  0x800      /* CAN Wake-Up Status */
-#define                     USBWS  0x2000     /* USB Wake-Up Status */
-#define                    KPADWS  0x4000     /* Keypad Wake-Up Status */
-#define                     ROTWS  0x8000     /* Rotary Wake-Up Status */
-#define                      GPWS  0x1000     /* General-Purpose Wake-Up Status */
-
-/* Bit masks for VR_CTL */
-
-#define                      FREQ  0x3        /* Regulator Switching Frequency */
-#define                      GAIN  0xc        /* Voltage Output Level Gain */
-#define                      VLEV  0xf0       /* Internal Voltage Level */
-#define                   SCKELOW  0x8000     /* Drive SCKE Low During Reset Enable */
-#define                      WAKE  0x100      /* RTC/Reset Wake-Up Enable */
-#define                     CANWE  0x200      /* CAN0/1 Wake-Up Enable */
-#define                      GPWE  0x400      /* General-Purpose Wake-Up Enable */
-#define                     USBWE  0x800      /* USB Wake-Up Enable */
-#define                    KPADWE  0x1000     /* Keypad Wake-Up Enable */
-#define                     ROTWE  0x2000     /* Rotary Wake-Up Enable */
-
-#define FREQ_333                0x0001  /* Switching Frequency Is 333 kHz */
-#define FREQ_667                0x0002  /* Switching Frequency Is 667 kHz */
-#define FREQ_1000               0x0003  /* Switching Frequency Is 1 MHz */
-
-#define GAIN_5                  0x0000  /* GAIN = 5*/
-#define GAIN_10                 0x0004  /* GAIN = 1*/
-#define GAIN_20                 0x0008  /* GAIN = 2*/
-#define GAIN_50                 0x000C  /* GAIN = 5*/
-
-#define VLEV_085                0x0060  /* VLEV = 0.85 V (-5% - +10% Accuracy) */
-#define VLEV_090                0x0070  /* VLEV = 0.90 V (-5% - +10% Accuracy) */
-#define VLEV_095                0x0080  /* VLEV = 0.95 V (-5% - +10% Accuracy) */
-#define VLEV_100                0x0090  /* VLEV = 1.00 V (-5% - +10% Accuracy) */
-#define VLEV_105                0x00A0  /* VLEV = 1.05 V (-5% - +10% Accuracy) */
-#define VLEV_110                0x00B0  /* VLEV = 1.10 V (-5% - +10% Accuracy) */
-#define VLEV_115                0x00C0  /* VLEV = 1.15 V (-5% - +10% Accuracy) */
-#define VLEV_120                0x00D0  /* VLEV = 1.20 V (-5% - +10% Accuracy) */
-#define VLEV_125                0x00E0  /* VLEV = 1.25 V (-5% - +10% Accuracy) */
-#define VLEV_130                0x00F0  /* VLEV = 1.30 V (-5% - +10% Accuracy) */
-
 /* Bit masks for NFC_CTL */
 
 #define                    WR_DLY  0xf        /* Write Strobe Delay */
@@ -2489,14 +2208,6 @@
 #define                      UCCT  0x40       /* Universal Counter CAN Trigger */
 #define                       UCE  0x80       /* Universal Counter Enable */
 
-/* Bit masks for CAN0_UCCNT */
-
-#define                     UCCNT  0xffff     /* Universal Counter Count Value */
-
-/* Bit masks for CAN0_UCRC */
-
-#define                     UCVAL  0xffff     /* Universal Counter Reload/Capture Value */
-
 /* Bit masks for CAN0_CEC */
 
 #define                    RXECNT  0xff       /* Receive Error Counter */
diff --git a/arch/blackfin/mach-bf561/boards/Kconfig b/arch/blackfin/mach-bf561/boards/Kconfig
index e4bc6d7c5a6a..1aa529b9f8bb 100644
--- a/arch/blackfin/mach-bf561/boards/Kconfig
+++ b/arch/blackfin/mach-bf561/boards/Kconfig
@@ -19,4 +19,11 @@ config BFIN561_BLUETECHNIX_CM
         help
           CM-BF561 support for EVAL- and DEV-Board.
 
+config BFIN561_ACVILON
+        bool "BF561-ACVILON"
+        help
+          BF561-ACVILON System On Module support (SO-DIMM 144).
+          For more information about Acvilon BF561 SoM
+          please go to http://www.niistt.ru/
+
 endchoice
diff --git a/arch/blackfin/mach-bf561/boards/Makefile b/arch/blackfin/mach-bf561/boards/Makefile
index 3a152559e957..a5879f7857ad 100644
--- a/arch/blackfin/mach-bf561/boards/Makefile
+++ b/arch/blackfin/mach-bf561/boards/Makefile
@@ -2,6 +2,7 @@
 # arch/blackfin/mach-bf561/boards/Makefile
 #
 
+obj-$(CONFIG_BFIN561_ACVILON)          += acvilon.o
 obj-$(CONFIG_BFIN561_BLUETECHNIX_CM)   += cm_bf561.o
 obj-$(CONFIG_BFIN561_EZKIT)            += ezkit.o
 obj-$(CONFIG_BFIN561_TEPLA)            += tepla.o
diff --git a/arch/blackfin/mach-bf561/boards/acvilon.c b/arch/blackfin/mach-bf561/boards/acvilon.c
new file mode 100644
index 000000000000..07e8dc8770da
--- /dev/null
+++ b/arch/blackfin/mach-bf561/boards/acvilon.c
@@ -0,0 +1,551 @@
+/*
+ * File:         arch/blackfin/mach-bf561/acvilon.c
+ * Based on:     arch/blackfin/mach-bf561/ezkit.c
+ * Author:
+ *
+ * Created:
+ * Description:
+ *
+ * Modified:
+ *               Copyright 2004-2006 Analog Devices Inc.
+ *               Copyright 2009 CJSC "NII STT"
+ *
+ * Bugs:
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see the file COPYING, or write
+ * to the Free Software Foundation, Inc.,
+ * 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ *
+ *
+ * For more information about Acvilon BF561 SoM please
+ * go to http://www.niistt.ru/
+ *
+ */
+
+#include <linux/device.h>
+#include <linux/platform_device.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/partitions.h>
+#include <linux/mtd/physmap.h>
+#include <linux/mtd/nand.h>
+#include <linux/mtd/plat-ram.h>
+#include <linux/spi/spi.h>
+#include <linux/spi/flash.h>
+#include <linux/irq.h>
+#include <linux/interrupt.h>
+#include <linux/i2c-pca-platform.h>
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <asm/dma.h>
+#include <asm/bfin5xx_spi.h>
+#include <asm/portmux.h>
+#include <asm/dpmc.h>
+#include <asm/cacheflush.h>
+#include <linux/i2c.h>
+
+/*
+ * Name the Board for the /proc/cpuinfo
+ */
+const char bfin_board_name[] = "Acvilon board";
+
+#if defined(CONFIG_USB_ISP1760_HCD) || defined(CONFIG_USB_ISP1760_HCD_MODULE)
+#include <linux/usb/isp1760.h>
+static struct resource bfin_isp1760_resources[] = {
+        [0] = {
+               .start = 0x20000000,
+               .end = 0x20000000 + 0x000fffff,
+               .flags = IORESOURCE_MEM,
+               },
+        [1] = {
+               .start = IRQ_PF15,
+               .end = IRQ_PF15,
+               .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
+               },
+};
+
+static struct isp1760_platform_data isp1760_priv = {
+        .is_isp1761 = 0,
+        .port1_disable = 0,
+        .bus_width_16 = 1,
+        .port1_otg = 0,
+        .analog_oc = 0,
+        .dack_polarity_high = 0,
+        .dreq_polarity_high = 0,
+};
+
+static struct platform_device bfin_isp1760_device = {
+        .name = "isp1760-hcd",
+        .id = 0,
+        .dev = {
+                .platform_data = &isp1760_priv,
+                },
+        .num_resources = ARRAY_SIZE(bfin_isp1760_resources),
+        .resource = bfin_isp1760_resources,
+};
+#endif
+
+static struct resource bfin_i2c_pca_resources[] = {
+        {
+         .name = "pca9564-regs",
+         .start = 0x2C000000,
+         .end = 0x2C000000 + 16,
+         .flags = IORESOURCE_MEM | IORESOURCE_MEM_32BIT,
+         }, {
+
+             .start = IRQ_PF8,
+             .end = IRQ_PF8,
+             .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
+             },
+};
+
+struct i2c_pca9564_pf_platform_data pca9564_platform_data = {
+        .gpio = -1,
+        .i2c_clock_speed = 330000,
+        .timeout = 10000
+};
+
+/* PCA9564 I2C Bus driver */
+static struct platform_device bfin_i2c_pca_device = {
+        .name = "i2c-pca-platform",
+        .id = 0,
+        .num_resources = ARRAY_SIZE(bfin_i2c_pca_resources),
+        .resource = bfin_i2c_pca_resources,
+        .dev = {
+                .platform_data = &pca9564_platform_data,
+                }
+};
+
+/* I2C devices fitted. */
+static struct i2c_board_info acvilon_i2c_devs[] __initdata = {
+        {
+         I2C_BOARD_INFO("ds1339", 0x68),
+         },
+        {
+         I2C_BOARD_INFO("tcn75", 0x49),
+         },
+};
+
+#if defined(CONFIG_MTD_PLATRAM) || defined(CONFIG_MTD_PLATRAM_MODULE)
+static struct platdata_mtd_ram mtd_ram_data = {
+        .mapname = "rootfs(RAM)",
+        .bankwidth = 4,
+};
+
+static struct resource mtd_ram_resource = {
+        .start = 0x4000000,
+        .end = 0x5ffffff,
+        .flags = IORESOURCE_MEM,
+};
+
+static struct platform_device mtd_ram_device = {
+        .name = "mtd-ram",
+        .id = 0,
+        .dev = {
+                .platform_data = &mtd_ram_data,
+                },
+        .num_resources = 1,
+        .resource = &mtd_ram_resource,
+};
+#endif
+
+#if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE)
+#include <linux/smsc911x.h>
+static struct resource smsc911x_resources[] = {
+        {
+         .name = "smsc911x-memory",
+         .start = 0x28000000,
+         .end = 0x28000000 + 0xFF,
+         .flags = IORESOURCE_MEM,
+         },
+        {
+         .start = IRQ_PF7,
+         .end = IRQ_PF7,
+         .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
+         },
+};
+
+static struct smsc911x_platform_config smsc911x_config = {
+        .flags = SMSC911X_USE_32BIT,
+        .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
+        .irq_type = SMSC911X_IRQ_TYPE_OPEN_DRAIN,
+        .phy_interface = PHY_INTERFACE_MODE_MII,
+};
+
+static struct platform_device smsc911x_device = {
+        .name = "smsc911x",
+        .id = 0,
+        .num_resources = ARRAY_SIZE(smsc911x_resources),
+        .resource = smsc911x_resources,
+        .dev = {
+                .platform_data = &smsc911x_config,
+                },
+};
+#endif
+
+#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
+#ifdef CONFIG_SERIAL_BFIN_UART0
+static struct resource bfin_uart0_resources[] = {
+        {
+         .start = BFIN_UART_THR,
+         .end = BFIN_UART_GCTL + 2,
+         .flags = IORESOURCE_MEM,
+         },
+        {
+         .start = IRQ_UART_RX,
+         .end = IRQ_UART_RX + 1,
+         .flags = IORESOURCE_IRQ,
+         },
+        {
+         .start = IRQ_UART_ERROR,
+         .end = IRQ_UART_ERROR,
+         .flags = IORESOURCE_IRQ,
+         },
+        {
+         .start = CH_UART_TX,
+         .end = CH_UART_TX,
+         .flags = IORESOURCE_DMA,
+         },
+        {
+         .start = CH_UART_RX,
+         .end = CH_UART_RX,
+         .flags = IORESOURCE_DMA,
+         },
+};
+
+unsigned short bfin_uart0_peripherals[] = {
+        P_UART0_TX, P_UART0_RX, 0
+};
+
+static struct platform_device bfin_uart0_device = {
+        .name = "bfin-uart",
+        .id = 0,
+        .num_resources = ARRAY_SIZE(bfin_uart0_resources),
+        .resource = bfin_uart0_resources,
+        .dev = {
+                /* Passed to driver */
+                .platform_data = &bfin_uart0_peripherals,
+                },
+};
+#endif
+#endif
+
+#if defined(CONFIG_MTD_NAND_PLATFORM) || defined(CONFIG_MTD_NAND_PLATFORM_MODULE)
+
+#ifdef CONFIG_MTD_PARTITIONS
+const char *part_probes[] = { "cmdlinepart", NULL };
+
+static struct mtd_partition bfin_plat_nand_partitions[] = {
+        {
+         .name = "params(nand)",
+         .size = 32 * 1024 * 1024,
+         .offset = 0,
+         }, {
+             .name = "userfs(nand)",
+             .size = MTDPART_SIZ_FULL,
+             .offset = MTDPART_OFS_APPEND,
+             },
+};
+#endif
+
+#define BFIN_NAND_PLAT_CLE 2
+#define BFIN_NAND_PLAT_ALE 3
+
+static void bfin_plat_nand_cmd_ctrl(struct mtd_info *mtd, int cmd,
+                                    unsigned int ctrl)
+{
+        struct nand_chip *this = mtd->priv;
+
+        if (cmd == NAND_CMD_NONE)
+                return;
+
+        if (ctrl & NAND_CLE)
+                writeb(cmd, this->IO_ADDR_W + (1 << BFIN_NAND_PLAT_CLE));
+        else
+                writeb(cmd, this->IO_ADDR_W + (1 << BFIN_NAND_PLAT_ALE));
+}
+
+#define BFIN_NAND_PLAT_READY GPIO_PF10
+static int bfin_plat_nand_dev_ready(struct mtd_info *mtd)
+{
+        return gpio_get_value(BFIN_NAND_PLAT_READY);
+}
+
+static struct platform_nand_data bfin_plat_nand_data = {
+        .chip = {
+                 .chip_delay = 30,
+#ifdef CONFIG_MTD_PARTITIONS
+                 .part_probe_types = part_probes,
+                 .partitions = bfin_plat_nand_partitions,
+                 .nr_partitions = ARRAY_SIZE(bfin_plat_nand_partitions),
+#endif
+                 },
+        .ctrl = {
+                 .cmd_ctrl = bfin_plat_nand_cmd_ctrl,
+                 .dev_ready = bfin_plat_nand_dev_ready,
+                 },
+};
+
+#define MAX(x, y) (x > y ? x : y)
+static struct resource bfin_plat_nand_resources = {
+        .start = 0x24000000,
+        .end = 0x24000000 + (1 << MAX(BFIN_NAND_PLAT_CLE, BFIN_NAND_PLAT_ALE)),
+        .flags = IORESOURCE_IO,
+};
+
+static struct platform_device bfin_async_nand_device = {
+        .name = "gen_nand",
+        .id = -1,
+        .num_resources = 1,
+        .resource = &bfin_plat_nand_resources,
+        .dev = {
+                .platform_data = &bfin_plat_nand_data,
+                },
+};
+
+static void bfin_plat_nand_init(void)
+{
+        gpio_request(BFIN_NAND_PLAT_READY, "bfin_nand_plat");
+}
+#else
+static void bfin_plat_nand_init(void)
+{
+}
+#endif
+
+#if defined(CONFIG_MTD_DATAFLASH) || defined(CONFIG_MTD_DATAFLASH_MODULE)
+static struct mtd_partition bfin_spi_dataflash_partitions[] = {
+        {
+         .name = "bootloader",
+         .size = 0x4200,
+         .offset = 0,
+         .mask_flags = MTD_CAP_ROM},
+        {
+         .name = "u-boot",
+         .size = 0x42000,
+         .offset = MTDPART_OFS_APPEND,
+         },
+        {
+         .name = "u-boot(params)",
+         .size = 0x4200,
+         .offset = MTDPART_OFS_APPEND,
+         },
+        {
+         .name = "kernel",
+         .size = 0x294000,
+         .offset = MTDPART_OFS_APPEND,
+         },
+        {
+         .name = "params",
+         .size = 0x42000,
+         .offset = MTDPART_OFS_APPEND,
+         },
+        {
+         .name = "rootfs",
+         .size = MTDPART_SIZ_FULL,
+         .offset = MTDPART_OFS_APPEND,
+         }
+};
+
+static struct flash_platform_data bfin_spi_dataflash_data = {
+        .name = "SPI Dataflash",
+        .parts = bfin_spi_dataflash_partitions,
+        .nr_parts = ARRAY_SIZE(bfin_spi_dataflash_partitions),
+};
+
+/* DataFlash chip */
+static struct bfin5xx_spi_chip data_flash_chip_info = {
+        .enable_dma = 0,        /* use dma transfer with this chip */
+        .bits_per_word = 8,
+};
+#endif
+
+#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
+static struct bfin5xx_spi_chip spidev_chip_info = {
+        .enable_dma = 0,
+        .bits_per_word = 8,
+};
+#endif
+
+#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
+/* SPI (0) */
+static struct resource bfin_spi0_resource[] = {
+        [0] = {
+               .start = SPI0_REGBASE,
+               .end = SPI0_REGBASE + 0xFF,
+               .flags = IORESOURCE_MEM,
+               },
+        [1] = {
+               .start = CH_SPI,
+               .end = CH_SPI,
+               .flags = IORESOURCE_DMA,
+               },
+        [2] = {
+               .start = IRQ_SPI,
+               .end = IRQ_SPI,
+               .flags = IORESOURCE_IRQ,
+               },
+};
+
+/* SPI controller data */
+static struct bfin5xx_spi_master bfin_spi0_info = {
+        .num_chipselect = 8,
+        .enable_dma = 1,        /* master has the ability to do dma transfer */
+        .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
+};
+
+static struct platform_device bfin_spi0_device = {
+        .name = "bfin-spi",
+        .id = 0,                /* Bus number */
+        .num_resources = ARRAY_SIZE(bfin_spi0_resource),
+        .resource = bfin_spi0_resource,
+        .dev = {
+                .platform_data = &bfin_spi0_info,       /* Passed to driver */
+                },
+};
+#endif
+
+static struct spi_board_info bfin_spi_board_info[] __initdata = {
+#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
+        {
+         .modalias = "spidev",
+         .max_speed_hz = 3125000,       /* max spi clock (SCK) speed in HZ */
+         .bus_num = 0,
+         .chip_select = 3,
+         .controller_data = &spidev_chip_info,
+         },
+#endif
+#if defined(CONFIG_MTD_DATAFLASH) || defined(CONFIG_MTD_DATAFLASH_MODULE)
+        {                       /* DataFlash chip */
+         .modalias = "mtd_dataflash",
+         .max_speed_hz = 33250000,      /* max spi clock (SCK) speed in HZ */
+         .bus_num = 0,          /* Framework bus number */
+         .chip_select = 2,      /* Framework chip select */
+         .platform_data = &bfin_spi_dataflash_data,
+         .controller_data = &data_flash_chip_info,
+         .mode = SPI_MODE_3,
+         },
+#endif
+};
+
+static struct resource bfin_gpios_resources = {
+        .start = 31,
+/*      .end   = MAX_BLACKFIN_GPIOS - 1, */
+        .end = 32,
+        .flags = IORESOURCE_IRQ,
+};
+
+static struct platform_device bfin_gpios_device = {
+        .name = "simple-gpio",
+        .id = -1,
+        .num_resources = 1,
+        .resource = &bfin_gpios_resources,
+};
+
+static const unsigned int cclk_vlev_datasheet[] = {
+        VRPAIR(VLEV_085, 250000000),
+        VRPAIR(VLEV_090, 300000000),
+        VRPAIR(VLEV_095, 313000000),
+        VRPAIR(VLEV_100, 350000000),
+        VRPAIR(VLEV_105, 400000000),
+        VRPAIR(VLEV_110, 444000000),
+        VRPAIR(VLEV_115, 450000000),
+        VRPAIR(VLEV_120, 475000000),
+        VRPAIR(VLEV_125, 500000000),
+        VRPAIR(VLEV_130, 600000000),
+};
+
+static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = {
+        .tuple_tab = cclk_vlev_datasheet,
+        .tabsize = ARRAY_SIZE(cclk_vlev_datasheet),
+        .vr_settling_time = 25 /* us */ ,
+};
+
+static struct platform_device bfin_dpmc = {
+        .name = "bfin dpmc",
+        .dev = {
+                .platform_data = &bfin_dmpc_vreg_data,
+                },
+};
+
+static struct platform_device *acvilon_devices[] __initdata = {
+        &bfin_dpmc,
+
+#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
+        &bfin_spi0_device,
+#endif
+
+#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
+#ifdef CONFIG_SERIAL_BFIN_UART0
+        &bfin_uart0_device,
+#endif
+#endif
+
+        &bfin_gpios_device,
+
+#if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE)
+        &smsc911x_device,
+#endif
+
+        &bfin_i2c_pca_device,
+
+#if defined(CONFIG_MTD_NAND_PLATFORM) || defined(CONFIG_MTD_NAND_PLATFORM_MODULE)
+        &bfin_async_nand_device,
+#endif
+
+#if defined(CONFIG_MTD_PLATRAM) || defined(CONFIG_MTD_PLATRAM_MODULE)
+        &mtd_ram_device,
+#endif
+
+};
+
+static int __init acvilon_init(void)
+{
+        int ret;
+
+        printk(KERN_INFO "%s(): registering device resources\n", __func__);
+
+        bfin_plat_nand_init();
+        ret =
+            platform_add_devices(acvilon_devices, ARRAY_SIZE(acvilon_devices));
+        if (ret < 0)
+                return ret;
+
+        i2c_register_board_info(0, acvilon_i2c_devs,
+                                ARRAY_SIZE(acvilon_i2c_devs));
+
+        bfin_write_FIO0_FLAG_C(1 << 14);
+        msleep(5);
+        bfin_write_FIO0_FLAG_S(1 << 14);
+
+        spi_register_board_info(bfin_spi_board_info,
+                                ARRAY_SIZE(bfin_spi_board_info));
+        return 0;
+}
+
+arch_initcall(acvilon_init);
+
+static struct platform_device *acvilon_early_devices[] __initdata = {
+#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
+#ifdef CONFIG_SERIAL_BFIN_UART0
+        &bfin_uart0_device,
+#endif
+#endif
+};
+
+void __init native_machine_early_platform_add_devices(void)
+{
+        printk(KERN_INFO "register early platform devices\n");
+        early_platform_add_devices(acvilon_early_devices,
+                                   ARRAY_SIZE(acvilon_early_devices));
+}
diff --git a/arch/blackfin/mach-bf561/boards/ezkit.c b/arch/blackfin/mach-bf561/boards/ezkit.c
index 9e2d8cfba546..ffd3e6a80d1a 100644
--- a/arch/blackfin/mach-bf561/boards/ezkit.c
+++ b/arch/blackfin/mach-bf561/boards/ezkit.c
@@ -49,7 +49,7 @@ static struct isp1760_platform_data isp1760_priv = {
 };
 
 static struct platform_device bfin_isp1760_device = {
-        .name           = "isp1760-hcd",
+        .name           = "isp1760",
         .id             = 0,
         .dev = {
                 .platform_data = &isp1760_priv,
@@ -159,28 +159,6 @@ static struct platform_device smc91x_device = {
 };
 #endif
 
-#if defined(CONFIG_AX88180) || defined(CONFIG_AX88180_MODULE)
-static struct resource ax88180_resources[] = {
-        [0] = {
-                .start  = 0x2c000000,
-                .end    = 0x2c000000 + 0x8000,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = IRQ_PF10,
-                .end    = IRQ_PF10,
-                .flags  = (IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL),
-        },
-};
-
-static struct platform_device ax88180_device = {
-        .name           = "ax88180",
-        .id             = -1,
-        .num_resources  = ARRAY_SIZE(ax88180_resources),
-        .resource       = ax88180_resources,
-};
-#endif
-
 #if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
 static struct resource bfin_uart_resources[] = {
         {
@@ -421,10 +399,6 @@ static struct platform_device *ezkit_devices[] __initdata = {
         &smc91x_device,
 #endif
 
-#if defined(CONFIG_AX88180) || defined(CONFIG_AX88180_MODULE)
-        &ax88180_device,
-#endif
-
 #if defined(CONFIG_USB_NET2272) || defined(CONFIG_USB_NET2272_MODULE)
         &net2272_bfin_device,
 #endif
diff --git a/arch/blackfin/mach-bf561/coreb.c b/arch/blackfin/mach-bf561/coreb.c
index 1e60a92dd602..deb2271d09a3 100644
--- a/arch/blackfin/mach-bf561/coreb.c
+++ b/arch/blackfin/mach-bf561/coreb.c
@@ -22,8 +22,8 @@
 #define CMD_COREB_STOP          3
 #define CMD_COREB_RESET         4
 
-static int
-coreb_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg)
+static long
+coreb_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
 {
         int ret = 0;
 
@@ -49,8 +49,8 @@ coreb_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned l
 }
 
 static const struct file_operations coreb_fops = {
-        .owner   = THIS_MODULE,
-        .ioctl   = coreb_ioctl,
+        .owner          = THIS_MODULE,
+        .unlocked_ioctl = coreb_ioctl,
 };
 
 static struct miscdevice coreb_dev = {
diff --git a/arch/blackfin/mach-bf561/include/mach/defBF561.h b/arch/blackfin/mach-bf561/include/mach/defBF561.h
index a31e509553fb..4c8e36b7fb33 100644
--- a/arch/blackfin/mach-bf561/include/mach/defBF561.h
+++ b/arch/blackfin/mach-bf561/include/mach/defBF561.h
@@ -884,65 +884,11 @@
 /* System MMR Register Bits */
 /******************************************************************************* */
 
-/* ********************* PLL AND RESET MASKS ************************ */
-
-/* PLL_CTL Masks */
-#define PLL_CLKIN              0x00000000       /* Pass CLKIN to PLL */
-#define PLL_CLKIN_DIV2         0x00000001       /* Pass CLKIN/2 to PLL */
-#define PLL_OFF                0x00000002       /* Shut off PLL clocks */
-#define STOPCK_OFF             0x00000008       /* Core clock off */
-#define PDWN                   0x00000020       /* Put the PLL in a Deep Sleep state */
-#define BYPASS                 0x00000100       /* Bypass the PLL */
-
 /* CHIPID Masks */
 #define CHIPID_VERSION         0xF0000000
 #define CHIPID_FAMILY          0x0FFFF000
 #define CHIPID_MANUFACTURE     0x00000FFE
 
-/* VR_CTL Masks                                                                                                                                 */
-#define FREQ                    0x0003  /* Switching Oscillator Frequency For Regulator */
-#define HIBERNATE               0x0000  /* Powerdown/Bypass On-Board Regulation */
-#define FREQ_333                0x0001  /* Switching Frequency Is 333 kHz */
-#define FREQ_667                0x0002  /* Switching Frequency Is 667 kHz */
-#define FREQ_1000               0x0003  /* Switching Frequency Is 1 MHz */
-
-#define GAIN                    0x000C  /* Voltage Level Gain   */
-#define GAIN_5                  0x0000  /* GAIN = 5*/
-#define GAIN_10                 0x0004  /* GAIN = 1*/
-#define GAIN_20                 0x0008  /* GAIN = 2*/
-#define GAIN_50                 0x000C  /* GAIN = 5*/
-
-#define VLEV                    0x00F0  /* Internal Voltage Level */
-#define VLEV_085                0x0060  /* VLEV = 0.85 V (-5% - +10% Accuracy) */
-#define VLEV_090                0x0070  /* VLEV = 0.90 V (-5% - +10% Accuracy) */
-#define VLEV_095                0x0080  /* VLEV = 0.95 V (-5% - +10% Accuracy) */
-#define VLEV_100                0x0090  /* VLEV = 1.00 V (-5% - +10% Accuracy) */
-#define VLEV_105                0x00A0  /* VLEV = 1.05 V (-5% - +10% Accuracy) */
-#define VLEV_110                0x00B0  /* VLEV = 1.10 V (-5% - +10% Accuracy) */
-#define VLEV_115                0x00C0  /* VLEV = 1.15 V (-5% - +10% Accuracy) */
-#define VLEV_120                0x00D0  /* VLEV = 1.20 V (-5% - +10% Accuracy) */
-#define VLEV_125                0x00E0  /* VLEV = 1.25 V (-5% - +10% Accuracy) */
-#define VLEV_130                0x00F0  /* VLEV = 1.30 V (-5% - +10% Accuracy) */
-
-#define WAKE                    0x0100  /* Enable RTC/Reset Wakeup From Hibernate */
-#define SCKELOW                 0x8000  /* Do Not Drive SCKE High During Reset After Hibernate */
-
-/* PLL_DIV Masks */
-#define SCLK_DIV(x)  (x)        /* SCLK = VCO / x */
-
-#define CSEL                    0x30            /* Core Select */
-#define SSEL                    0xf             /* System Select */
-#define CCLK_DIV1              0x00000000       /* CCLK = VCO / 1 */
-#define CCLK_DIV2              0x00000010       /* CCLK = VCO / 2 */
-#define CCLK_DIV4              0x00000020       /* CCLK = VCO / 4 */
-#define CCLK_DIV8              0x00000030       /* CCLK = VCO / 8 */
-
-/* PLL_STAT Masks                                                                                                                                       */
-#define ACTIVE_PLLENABLED       0x0001  /* Processor In Active Mode With PLL Enabled    */
-#define FULL_ON                         0x0002  /* Processor In Full On Mode                                    */
-#define ACTIVE_PLLDISABLED      0x0004  /* Processor In Active Mode With PLL Disabled   */
-#define PLL_LOCKED                      0x0020  /* PLL_LOCKCNT Has Been Reached                                 */
-
 /* SICA_SYSCR Masks */
 #define COREB_SRAM_INIT         0x0020
 
@@ -1150,53 +1096,6 @@
 
 /* **********  DMA CONTROLLER MASKS  *********************8 */
 
-/* DMAx_CONFIG, MDMA_yy_CONFIG, IMDMA_yy_CONFIG Masks */
-#define DMAEN           0x00000001      /* Channel Enable */
-#define WNR             0x00000002      /* Channel Direction (W/R*) */
-#define WDSIZE_8        0x00000000      /* Word Size 8 bits */
-#define WDSIZE_16       0x00000004      /* Word Size 16 bits */
-#define WDSIZE_32       0x00000008      /* Word Size 32 bits */
-#define DMA2D           0x00000010      /* 2D/1D* Mode */
-#define RESTART         0x00000020      /* Restart */
-#define DI_SEL          0x00000040      /* Data Interrupt Select */
-#define DI_EN           0x00000080      /* Data Interrupt Enable */
-#define NDSIZE_0                0x0000  /* Next Descriptor Size = 0 (Stop/Autobuffer)   */
-#define NDSIZE_1                0x0100  /* Next Descriptor Size = 1                                             */
-#define NDSIZE_2                0x0200  /* Next Descriptor Size = 2                                             */
-#define NDSIZE_3                0x0300  /* Next Descriptor Size = 3                                             */
-#define NDSIZE_4                0x0400  /* Next Descriptor Size = 4                                             */
-#define NDSIZE_5                0x0500  /* Next Descriptor Size = 5                                             */
-#define NDSIZE_6                0x0600  /* Next Descriptor Size = 6                                             */
-#define NDSIZE_7                0x0700  /* Next Descriptor Size = 7                                             */
-#define NDSIZE_8                0x0800  /* Next Descriptor Size = 8                                             */
-#define NDSIZE_9                0x0900  /* Next Descriptor Size = 9                                             */
-#define NDSIZE          0x00000900      /* Next Descriptor Size */
-#define DMAFLOW         0x00007000      /* Flow Control */
-#define DMAFLOW_STOP            0x0000  /* Stop Mode */
-#define DMAFLOW_AUTO            0x1000  /* Autobuffer Mode */
-#define DMAFLOW_ARRAY           0x4000  /* Descriptor Array Mode */
-#define DMAFLOW_SMALL           0x6000  /* Small Model Descriptor List Mode */
-#define DMAFLOW_LARGE           0x7000  /* Large Model Descriptor List Mode */
-
-#define DMAEN_P                 0       /* Channel Enable */
-#define WNR_P                   1       /* Channel Direction (W/R*) */
-#define DMA2D_P                 4       /* 2D/1D* Mode */
-#define RESTART_P               5       /* Restart */
-#define DI_SEL_P                6       /* Data Interrupt Select */
-#define DI_EN_P                 7       /* Data Interrupt Enable */
-
-/* DMAx_IRQ_STATUS, MDMA_yy_IRQ_STATUS, IMDMA_yy_IRQ_STATUS Masks */
-
-#define DMA_DONE                0x00000001      /* DMA Done Indicator */
-#define DMA_ERR                 0x00000002      /* DMA Error Indicator */
-#define DFETCH                  0x00000004      /* Descriptor Fetch Indicator */
-#define DMA_RUN                 0x00000008      /* DMA Running Indicator */
-
-#define DMA_DONE_P              0       /* DMA Done Indicator */
-#define DMA_ERR_P               1       /* DMA Error Indicator */
-#define DFETCH_P                2       /* Descriptor Fetch Indicator */
-#define DMA_RUN_P               3       /* DMA Running Indicator */
-
 /* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP, IMDMA_yy_PERIPHERAL_MAP Masks */
 
 #define CTYPE               0x00000040  /* DMA Channel Type Indicator */
diff --git a/arch/blackfin/mach-bf561/smp.c b/arch/blackfin/mach-bf561/smp.c
index 510f57641495..0192532e96a2 100644
--- a/arch/blackfin/mach-bf561/smp.c
+++ b/arch/blackfin/mach-bf561/smp.c
@@ -52,8 +52,6 @@ int __init setup_profiling_timer(unsigned int multiplier) /* not supported */
 
 void __cpuinit platform_secondary_init(unsigned int cpu)
 {
-        local_irq_disable();
-
         /* Clone setup for peripheral interrupt sources from CoreA. */
         bfin_write_SICB_IMASK0(bfin_read_SICA_IMASK0());
         bfin_write_SICB_IMASK1(bfin_read_SICA_IMASK1());
@@ -70,11 +68,6 @@ void __cpuinit platform_secondary_init(unsigned int cpu)
         bfin_write_SICB_IAR7(bfin_read_SICA_IAR7());
         SSYNC();
 
-        local_irq_enable();
-
-        /* Calibrate loops per jiffy value. */
-        calibrate_delay();
-
         /* Store CPU-private information to the cpu_data array. */
         bfin_setup_cpudata(cpu);
 
@@ -108,9 +101,13 @@ int __cpuinit platform_boot_secondary(unsigned int cpu, struct task_struct *idle
                 barrier();
         }
 
-        spin_unlock(&boot_lock);
-
-        return cpu_isset(cpu, cpu_callin_map) ? 0 : -ENOSYS;
+        if (cpu_isset(cpu, cpu_callin_map)) {
+                cpu_set(cpu, cpu_online_map);
+                /* release the lock and let coreb run */
+                spin_unlock(&boot_lock);
+                return 0;
+        } else
+                panic("CPU%u: processor failed to boot\n", cpu);
 }
 
 void __init platform_request_ipi(irq_handler_t handler)
diff --git a/arch/blackfin/mach-common/clocks-init.c b/arch/blackfin/mach-common/clocks-init.c
index ef6870e9eea6..d5cfe611b778 100644
--- a/arch/blackfin/mach-common/clocks-init.c
+++ b/arch/blackfin/mach-common/clocks-init.c
@@ -13,6 +13,7 @@
 #include <asm/dma.h>
 #include <asm/clocks.h>
 #include <asm/mem_init.h>
+#include <asm/dpmc.h>
 
 #define SDGCTL_WIDTH (1 << 31)  /* SDRAM external data path width */
 #define PLL_CTL_VAL \
diff --git a/arch/blackfin/mach-common/cpufreq.c b/arch/blackfin/mach-common/cpufreq.c
index 01506504e6d0..777582897253 100644
--- a/arch/blackfin/mach-common/cpufreq.c
+++ b/arch/blackfin/mach-common/cpufreq.c
@@ -13,7 +13,7 @@
 #include <linux/fs.h>
 #include <asm/blackfin.h>
 #include <asm/time.h>
-
+#include <asm/dpmc.h>
 
 /* this is the table of CCLK frequencies, in Hz */
 /* .index is the entry in the auxillary dpm_state_table[] */
@@ -138,7 +138,8 @@ static int __init __bfin_cpu_init(struct cpufreq_policy *policy)
                                                  dpm_state_table[index].tscale);
         }
 
-        policy->cpuinfo.transition_latency = (bfin_read_PLL_LOCKCNT() / (sclk / 1000000)) * 1000;
+        policy->cpuinfo.transition_latency = 50000; /* 50us assumed */
+
         /*Now ,only support one cpu */
         policy->cur = cclk;
         cpufreq_frequency_table_get_attr(bfin_freq_table, policy->cpu);
diff --git a/arch/blackfin/mach-common/dpmc_modes.S b/arch/blackfin/mach-common/dpmc_modes.S
index 8009a512fb11..b03716896051 100644
--- a/arch/blackfin/mach-common/dpmc_modes.S
+++ b/arch/blackfin/mach-common/dpmc_modes.S
@@ -404,6 +404,21 @@ ENTRY(_do_hibernate)
         PM_SYS_PUSH(EBIU_FCTL)
 #endif
 
+#ifdef PORTCIO_FER
+        PM_SYS_PUSH16(PORTCIO_DIR)
+        PM_SYS_PUSH16(PORTCIO_INEN)
+        PM_SYS_PUSH16(PORTCIO)
+        PM_SYS_PUSH16(PORTCIO_FER)
+        PM_SYS_PUSH16(PORTDIO_DIR)
+        PM_SYS_PUSH16(PORTDIO_INEN)
+        PM_SYS_PUSH16(PORTDIO)
+        PM_SYS_PUSH16(PORTDIO_FER)
+        PM_SYS_PUSH16(PORTEIO_DIR)
+        PM_SYS_PUSH16(PORTEIO_INEN)
+        PM_SYS_PUSH16(PORTEIO)
+        PM_SYS_PUSH16(PORTEIO_FER)
+#endif
+
         PM_SYS_PUSH16(SYSCR)
 
         /* Save Core MMRs */
@@ -716,6 +731,21 @@ ENTRY(_do_hibernate)
         P0.L = lo(PLL_CTL);
         PM_SYS_POP16(SYSCR)
 
+#ifdef PORTCIO_FER
+        PM_SYS_POP16(PORTEIO_FER)
+        PM_SYS_POP16(PORTEIO)
+        PM_SYS_POP16(PORTEIO_INEN)
+        PM_SYS_POP16(PORTEIO_DIR)
+        PM_SYS_POP16(PORTDIO_FER)
+        PM_SYS_POP16(PORTDIO)
+        PM_SYS_POP16(PORTDIO_INEN)
+        PM_SYS_POP16(PORTDIO_DIR)
+        PM_SYS_POP16(PORTCIO_FER)
+        PM_SYS_POP16(PORTCIO)
+        PM_SYS_POP16(PORTCIO_INEN)
+        PM_SYS_POP16(PORTCIO_DIR)
+#endif
+
 #ifdef EBIU_FCTL
         PM_SYS_POP(EBIU_FCTL)
         PM_SYS_POP(EBIU_MODE)
diff --git a/arch/blackfin/mach-common/entry.S b/arch/blackfin/mach-common/entry.S
index a50637a8b9bd..b0ed0b487ff2 100644
--- a/arch/blackfin/mach-common/entry.S
+++ b/arch/blackfin/mach-common/entry.S
@@ -713,6 +713,8 @@ ENTRY(_system_call)
         cc = BITTST(r7, TIF_RESTORE_SIGMASK);
         if cc jump .Lsyscall_do_signals;
         cc = BITTST(r7, TIF_SIGPENDING);
+        if cc jump .Lsyscall_do_signals;
+        cc = BITTST(r7, TIF_NOTIFY_RESUME);
         if !cc jump .Lsyscall_really_exit;
 .Lsyscall_do_signals:
         /* Reenable interrupts.  */
@@ -721,7 +723,7 @@ ENTRY(_system_call)
 
         r0 = sp;
         SP += -12;
-        call _do_signal;
+        call _do_notify_resume;
         SP += 12;
 
 .Lsyscall_really_exit:
@@ -1422,7 +1424,7 @@ ENTRY(_sys_call_table)
         .long _sys_ni_syscall   /* streams2 */
         .long _sys_vfork                /* 190 */
         .long _sys_getrlimit
-        .long _sys_mmap2
+        .long _sys_mmap_pgoff
         .long _sys_truncate64
         .long _sys_ftruncate64
         .long _sys_stat64       /* 195 */
diff --git a/arch/blackfin/mach-common/ints-priority.c b/arch/blackfin/mach-common/ints-priority.c
index 660ea1bec54c..1873b2c1fede 100644
--- a/arch/blackfin/mach-common/ints-priority.c
+++ b/arch/blackfin/mach-common/ints-priority.c
@@ -25,11 +25,20 @@
 #include <asm/blackfin.h>
 #include <asm/gpio.h>
 #include <asm/irq_handler.h>
+#include <asm/dpmc.h>
+#include <asm/bfin5xx_spi.h>
+#include <asm/bfin_sport.h>
 
 #define SIC_SYSIRQ(irq) (irq - (IRQ_CORETMR + 1))
 
 #ifdef BF537_FAMILY
 # define BF537_GENERIC_ERROR_INT_DEMUX
+# define SPI_ERR_MASK   (BIT_STAT_TXCOL | BIT_STAT_RBSY | BIT_STAT_MODF | BIT_STAT_TXE) /* SPI_STAT */
+# define SPORT_ERR_MASK (ROVF | RUVF | TOVF | TUVF)     /* SPORT_STAT */
+# define PPI_ERR_MASK   (0xFFFF & ~FLD) /* PPI_STATUS */
+# define EMAC_ERR_MASK  (PHYINT | MMCINT | RXFSINT | TXFSINT | WAKEDET | RXDMAERR | TXDMAERR | STMDONE) /* EMAC_SYSTAT */
+# define UART_ERR_MASK  (0x6)   /* UART_IIR */
+# define CAN_ERR_MASK   (EWTIF | EWRIF | EPIF | BOIF | WUIF | UIAIF | AAIF | RMLIF | UCEIF | EXTIF | ADIF)      /* CAN_GIF */
 #else
 # undef BF537_GENERIC_ERROR_INT_DEMUX
 #endif
@@ -324,11 +333,9 @@ static void bfin_demux_error_irq(unsigned int int_err_irq,
                 irq = IRQ_CAN_ERROR;
         else if (bfin_read_SPI_STAT() & SPI_ERR_MASK)
                 irq = IRQ_SPI_ERROR;
-        else if ((bfin_read_UART0_IIR() & UART_ERR_MASK_STAT1) &&
-                 (bfin_read_UART0_IIR() & UART_ERR_MASK_STAT0))
+        else if ((bfin_read_UART0_IIR() & UART_ERR_MASK) == UART_ERR_MASK)
                 irq = IRQ_UART0_ERROR;
-        else if ((bfin_read_UART1_IIR() & UART_ERR_MASK_STAT1) &&
-                 (bfin_read_UART1_IIR() & UART_ERR_MASK_STAT0))
+        else if ((bfin_read_UART1_IIR() & UART_ERR_MASK) == UART_ERR_MASK)
                 irq = IRQ_UART1_ERROR;
 
         if (irq) {
diff --git a/arch/blackfin/mach-common/smp.c b/arch/blackfin/mach-common/smp.c
index d92b168c8328..369e687582b7 100644
--- a/arch/blackfin/mach-common/smp.c
+++ b/arch/blackfin/mach-common/smp.c
@@ -336,13 +336,6 @@ int __cpuinit __cpu_up(unsigned int cpu)
 
         ret = platform_boot_secondary(cpu, idle);
 
-        if (ret) {
-                cpu_clear(cpu, cpu_present_map);
-                printk(KERN_CRIT "CPU%u: processor failed to boot (%d)\n", cpu, ret);
-                free_task(idle);
-        } else
-                cpu_set(cpu, cpu_online_map);
-
         secondary_stack = NULL;
 
         return ret;
@@ -418,9 +411,16 @@ void __cpuinit secondary_start_kernel(void)
 
         setup_secondary(cpu);
 
+        platform_secondary_init(cpu);
+
         local_irq_enable();
 
-        platform_secondary_init(cpu);
+        /*
+         * Calibrate loops per jiffy value.
+         * IRQs need to be enabled here - D-cache can be invalidated
+         * in timer irq handler, so core B can read correct jiffies.
+         */
+        calibrate_delay();
 
         cpu_idle();
 }
diff --git a/arch/cris/arch-v32/kernel/head.S b/arch/cris/arch-v32/kernel/head.S
index 3db478eb5155..76266f80a5f1 100644
--- a/arch/cris/arch-v32/kernel/head.S
+++ b/arch/cris/arch-v32/kernel/head.S
@@ -10,7 +10,6 @@
  * The macros found in mmu_defs_asm.h uses the ## concatenation operator, so
  * -traditional must not be used when assembling this file.
  */
-#include <linux/autoconf.h>
 #include <arch/memmap.h>
 #include <hwregs/reg_rdwr.h>
 #include <hwregs/intr_vect.h>
diff --git a/arch/cris/include/arch-v32/arch/spinlock.h b/arch/cris/include/arch-v32/arch/spinlock.h
index 367a53ea10c5..f171a6600fbc 100644
--- a/arch/cris/include/arch-v32/arch/spinlock.h
+++ b/arch/cris/include/arch-v32/arch/spinlock.h
@@ -9,12 +9,12 @@ extern void cris_spin_unlock(void *l, int val);
 extern void cris_spin_lock(void *l);
 extern int cris_spin_trylock(void *l);
 
-static inline int __raw_spin_is_locked(raw_spinlock_t *x)
+static inline int arch_spin_is_locked(arch_spinlock_t *x)
 {
         return *(volatile signed char *)(&(x)->slock) <= 0;
 }
 
-static inline void __raw_spin_unlock(raw_spinlock_t *lock)
+static inline void arch_spin_unlock(arch_spinlock_t *lock)
 {
         __asm__ volatile ("move.d %1,%0" \
                           : "=m" (lock->slock) \
@@ -22,26 +22,26 @@ static inline void __raw_spin_unlock(raw_spinlock_t *lock)
                           : "memory");
 }
 
-static inline void __raw_spin_unlock_wait(raw_spinlock_t *lock)
+static inline void arch_spin_unlock_wait(arch_spinlock_t *lock)
 {
-        while (__raw_spin_is_locked(lock))
+        while (arch_spin_is_locked(lock))
                 cpu_relax();
 }
 
-static inline int __raw_spin_trylock(raw_spinlock_t *lock)
+static inline int arch_spin_trylock(arch_spinlock_t *lock)
 {
         return cris_spin_trylock((void *)&lock->slock);
 }
 
-static inline void __raw_spin_lock(raw_spinlock_t *lock)
+static inline void arch_spin_lock(arch_spinlock_t *lock)
 {
         cris_spin_lock((void *)&lock->slock);
 }
 
 static inline void
-__raw_spin_lock_flags(raw_spinlock_t *lock, unsigned long flags)
+arch_spin_lock_flags(arch_spinlock_t *lock, unsigned long flags)
 {
-        __raw_spin_lock(lock);
+        arch_spin_lock(lock);
 }
 
 /*
@@ -56,76 +56,76 @@ __raw_spin_lock_flags(raw_spinlock_t *lock, unsigned long flags)
  *
  */
 
-static inline int __raw_read_can_lock(raw_rwlock_t *x)
+static inline int arch_read_can_lock(arch_rwlock_t *x)
 {
         return (int)(x)->lock > 0;
 }
 
-static inline int __raw_write_can_lock(raw_rwlock_t *x)
+static inline int arch_write_can_lock(arch_rwlock_t *x)
 {
         return (x)->lock == RW_LOCK_BIAS;
 }
 
-static  inline void __raw_read_lock(raw_rwlock_t *rw)
+static  inline void arch_read_lock(arch_rwlock_t *rw)
 {
-        __raw_spin_lock(&rw->slock);
+        arch_spin_lock(&rw->slock);
         while (rw->lock == 0);
         rw->lock--;
-        __raw_spin_unlock(&rw->slock);
+        arch_spin_unlock(&rw->slock);
 }
 
-static  inline void __raw_write_lock(raw_rwlock_t *rw)
+static  inline void arch_write_lock(arch_rwlock_t *rw)
 {
-        __raw_spin_lock(&rw->slock);
+        arch_spin_lock(&rw->slock);
         while (rw->lock != RW_LOCK_BIAS);
         rw->lock = 0;
-        __raw_spin_unlock(&rw->slock);
+        arch_spin_unlock(&rw->slock);
 }
 
-static  inline void __raw_read_unlock(raw_rwlock_t *rw)
+static  inline void arch_read_unlock(arch_rwlock_t *rw)
 {
-        __raw_spin_lock(&rw->slock);
+        arch_spin_lock(&rw->slock);
         rw->lock++;
-        __raw_spin_unlock(&rw->slock);
+        arch_spin_unlock(&rw->slock);
 }
 
-static  inline void __raw_write_unlock(raw_rwlock_t *rw)
+static  inline void arch_write_unlock(arch_rwlock_t *rw)
 {
-        __raw_spin_lock(&rw->slock);
+        arch_spin_lock(&rw->slock);
         while (rw->lock != RW_LOCK_BIAS);
         rw->lock = RW_LOCK_BIAS;
-        __raw_spin_unlock(&rw->slock);
+        arch_spin_unlock(&rw->slock);
 }
 
-static  inline int __raw_read_trylock(raw_rwlock_t *rw)
+static  inline int arch_read_trylock(arch_rwlock_t *rw)
 {
         int ret = 0;
-        __raw_spin_lock(&rw->slock);
+        arch_spin_lock(&rw->slock);
         if (rw->lock != 0) {
                 rw->lock--;
                 ret = 1;
         }
-        __raw_spin_unlock(&rw->slock);
+        arch_spin_unlock(&rw->slock);
         return ret;
 }
 
-static  inline int __raw_write_trylock(raw_rwlock_t *rw)
+static  inline int arch_write_trylock(arch_rwlock_t *rw)
 {
         int ret = 0;
-        __raw_spin_lock(&rw->slock);
+        arch_spin_lock(&rw->slock);
         if (rw->lock == RW_LOCK_BIAS) {
                 rw->lock = 0;
                 ret = 1;
         }
-        __raw_spin_unlock(&rw->slock);
+        arch_spin_unlock(&rw->slock);
         return 1;
 }
 
 #define _raw_read_lock_flags(lock, flags) _raw_read_lock(lock)
 #define _raw_write_lock_flags(lock, flags) _raw_write_lock(lock)
 
-#define _raw_spin_relax(lock)   cpu_relax()
-#define _raw_read_relax(lock)   cpu_relax()
-#define _raw_write_relax(lock)  cpu_relax()
+#define arch_spin_relax(lock)   cpu_relax()
+#define arch_read_relax(lock)   cpu_relax()
+#define arch_write_relax(lock)  cpu_relax()
 
 #endif /* __ASM_ARCH_SPINLOCK_H */
diff --git a/arch/cris/include/asm/asm-offsets.h b/arch/cris/include/asm/asm-offsets.h
new file mode 100644
index 000000000000..d370ee36a182
--- /dev/null
+++ b/arch/cris/include/asm/asm-offsets.h
@@ -0,0 +1 @@
+#include <generated/asm-offsets.h>
diff --git a/arch/cris/include/asm/elf.h b/arch/cris/include/asm/elf.h
index 0f51b10b9f4f..8a3d8e2b33c1 100644
--- a/arch/cris/include/asm/elf.h
+++ b/arch/cris/include/asm/elf.h
@@ -64,8 +64,6 @@ typedef unsigned long elf_fpregset_t;
 #define EF_CRIS_VARIANT_COMMON_V10_V32  0x00000004
 /* End of excerpt from {binutils}/include/elf/cris.h.  */
 
-#define USE_ELF_CORE_DUMP
-
 #define ELF_EXEC_PAGESIZE       8192
 
 /* This is the location that an ET_DYN program is loaded if exec'ed.  Typical
diff --git a/arch/cris/kernel/asm-offsets.c b/arch/cris/kernel/asm-offsets.c
index ddd6fbbe75de..dd7b8e983221 100644
--- a/arch/cris/kernel/asm-offsets.c
+++ b/arch/cris/kernel/asm-offsets.c
@@ -1,6 +1,5 @@
 #include <linux/sched.h>
 #include <asm/thread_info.h>
-#include <linux/autoconf.h>
 
 /*
  * Generate definitions needed by assembly language modules.
diff --git a/arch/cris/kernel/irq.c b/arch/cris/kernel/irq.c
index 0ca7d9892cc6..b5ce0724a88f 100644
--- a/arch/cris/kernel/irq.c
+++ b/arch/cris/kernel/irq.c
@@ -52,7 +52,7 @@ int show_interrupts(struct seq_file *p, void *v)
         }
 
         if (i < NR_IRQS) {
-                spin_lock_irqsave(&irq_desc[i].lock, flags);
+                raw_spin_lock_irqsave(&irq_desc[i].lock, flags);
                 action = irq_desc[i].action;
                 if (!action)
                         goto skip;
@@ -71,7 +71,7 @@ int show_interrupts(struct seq_file *p, void *v)
 
                 seq_putc(p, '\n');
 skip:
-                spin_unlock_irqrestore(&irq_desc[i].lock, flags);
+                raw_spin_unlock_irqrestore(&irq_desc[i].lock, flags);
         }
         return 0;
 }
diff --git a/arch/cris/kernel/sys_cris.c b/arch/cris/kernel/sys_cris.c
index 2ad962c7e88e..c2bbb1ac98a9 100644
--- a/arch/cris/kernel/sys_cris.c
+++ b/arch/cris/kernel/sys_cris.c
@@ -26,31 +26,6 @@
 #include <asm/uaccess.h>
 #include <asm/segment.h>
 
-/* common code for old and new mmaps */
-static inline long
-do_mmap2(unsigned long addr, unsigned long len, unsigned long prot,
-        unsigned long flags, unsigned long fd, unsigned long pgoff)
-{
-        int error = -EBADF;
-        struct file * file = NULL;
-
-        flags &= ~(MAP_EXECUTABLE | MAP_DENYWRITE);
-        if (!(flags & MAP_ANONYMOUS)) {
-                file = fget(fd);
-                if (!file)
-                        goto out;
-        }
-
-        down_write(&current->mm->mmap_sem);
-        error = do_mmap_pgoff(file, addr, len, prot, flags, pgoff);
-        up_write(&current->mm->mmap_sem);
-
-        if (file)
-                fput(file);
-out:
-        return error;
-}
-
 asmlinkage unsigned long old_mmap(unsigned long __user *args)
 {        
         unsigned long buffer[6];
@@ -63,7 +38,7 @@ asmlinkage unsigned long old_mmap(unsigned long __user *args)
         if (buffer[5] & ~PAGE_MASK) /* verify that offset is on page boundary */
                 goto out;
 
-        err = do_mmap2(buffer[0], buffer[1], buffer[2], buffer[3],
+        err = sys_mmap_pgoff(buffer[0], buffer[1], buffer[2], buffer[3],
                        buffer[4], buffer[5] >> PAGE_SHIFT);
 out:
         return err;
@@ -73,7 +48,8 @@ asmlinkage long
 sys_mmap2(unsigned long addr, unsigned long len, unsigned long prot,
           unsigned long flags, unsigned long fd, unsigned long pgoff)
 {
-        return do_mmap2(addr, len, prot, flags, fd, pgoff);
+        /* bug(?): 8Kb pages here */
+        return sys_mmap_pgoff(addr, len, prot, flags, fd, pgoff);
 }
 
 /*
diff --git a/arch/cris/kernel/vmlinux.lds.S b/arch/cris/kernel/vmlinux.lds.S
index bbfda67d2907..d49d17d2a14f 100644
--- a/arch/cris/kernel/vmlinux.lds.S
+++ b/arch/cris/kernel/vmlinux.lds.S
@@ -8,7 +8,6 @@
  * the kernel has booted.
  */
 
-#include <linux/autoconf.h>
 #include <asm-generic/vmlinux.lds.h>
 #include <asm/page.h>
 
diff --git a/arch/frv/include/asm/asm-offsets.h b/arch/frv/include/asm/asm-offsets.h
new file mode 100644
index 000000000000..d370ee36a182
--- /dev/null
+++ b/arch/frv/include/asm/asm-offsets.h
@@ -0,0 +1 @@
+#include <generated/asm-offsets.h>
diff --git a/arch/frv/include/asm/elf.h b/arch/frv/include/asm/elf.h
index 7bbf6e47f8c8..c3819804a74b 100644
--- a/arch/frv/include/asm/elf.h
+++ b/arch/frv/include/asm/elf.h
@@ -115,7 +115,6 @@ do {											\
         __kernel_frame0_ptr->gr29       = 0;                                            \
 } while(0)
 
-#define USE_ELF_CORE_DUMP
 #define CORE_DUMP_USE_REGSET
 #define ELF_FDPIC_CORE_EFLAGS   EF_FRV_FDPIC
 #define ELF_EXEC_PAGESIZE       16384
diff --git a/arch/frv/kernel/irq.c b/arch/frv/kernel/irq.c
index af3e824b91b3..62d1aba615dc 100644
--- a/arch/frv/kernel/irq.c
+++ b/arch/frv/kernel/irq.c
@@ -69,7 +69,7 @@ int show_interrupts(struct seq_file *p, void *v)
         }
 
         if (i < NR_IRQS) {
-                spin_lock_irqsave(&irq_desc[i].lock, flags);
+                raw_spin_lock_irqsave(&irq_desc[i].lock, flags);
                 action = irq_desc[i].action;
                 if (action) {
                         seq_printf(p, "%3d: ", i);
@@ -85,7 +85,7 @@ int show_interrupts(struct seq_file *p, void *v)
                         seq_putc(p, '\n');
                 }
 
-                spin_unlock_irqrestore(&irq_desc[i].lock, flags);
+                raw_spin_unlock_irqrestore(&irq_desc[i].lock, flags);
         } else if (i == NR_IRQS) {
                 seq_printf(p, "Err: %10u\n", atomic_read(&irq_err_count));
         }
diff --git a/arch/frv/kernel/setup.c b/arch/frv/kernel/setup.c
index 55e4fab7c0bc..75cf7f4b2fa8 100644
--- a/arch/frv/kernel/setup.c
+++ b/arch/frv/kernel/setup.c
@@ -10,7 +10,7 @@
  * 2 of the License, or (at your option) any later version.
  */
 
-#include <linux/utsrelease.h>
+#include <generated/utsrelease.h>
 #include <linux/kernel.h>
 #include <linux/sched.h>
 #include <linux/delay.h>
diff --git a/arch/frv/kernel/sys_frv.c b/arch/frv/kernel/sys_frv.c
index 2b6b5289cdcc..1d3d4c9e2521 100644
--- a/arch/frv/kernel/sys_frv.c
+++ b/arch/frv/kernel/sys_frv.c
@@ -31,9 +31,6 @@ asmlinkage long sys_mmap2(unsigned long addr, unsigned long len,
                           unsigned long prot, unsigned long flags,
                           unsigned long fd, unsigned long pgoff)
 {
-        int error = -EBADF;
-        struct file * file = NULL;
-
         /* As with sparc32, make sure the shift for mmap2 is constant
            (12), no matter what PAGE_SIZE we have.... */
 
@@ -41,69 +38,10 @@ asmlinkage long sys_mmap2(unsigned long addr, unsigned long len,
            trying to map something we can't */
         if (pgoff & ((1 << (PAGE_SHIFT - 12)) - 1))
                 return -EINVAL;
-        pgoff >>= PAGE_SHIFT - 12;
-
-        flags &= ~(MAP_EXECUTABLE | MAP_DENYWRITE);
-        if (!(flags & MAP_ANONYMOUS)) {
-                file = fget(fd);
-                if (!file)
-                        goto out;
-        }
-
-        down_write(&current->mm->mmap_sem);
-        error = do_mmap_pgoff(file, addr, len, prot, flags, pgoff);
-        up_write(&current->mm->mmap_sem);
-
-        if (file)
-                fput(file);
-out:
-        return error;
-}
-
-#if 0 /* DAVIDM - do we want this */
-struct mmap_arg_struct64 {
-        __u32 addr;
-        __u32 len;
-        __u32 prot;
-        __u32 flags;
-        __u64 offset; /* 64 bits */
-        __u32 fd;
-};
-
-asmlinkage long sys_mmap64(struct mmap_arg_struct64 *arg)
-{
-        int error = -EFAULT;
-        struct file * file = NULL;
-        struct mmap_arg_struct64 a;
-        unsigned long pgoff;
-
-        if (copy_from_user(&a, arg, sizeof(a)))
-                return -EFAULT;
-
-        if ((long)a.offset & ~PAGE_MASK)
-                return -EINVAL;
-
-        pgoff = a.offset >> PAGE_SHIFT;
-        if ((a.offset >> PAGE_SHIFT) != pgoff)
-                return -EINVAL;
-
-        if (!(a.flags & MAP_ANONYMOUS)) {
-                error = -EBADF;
-                file = fget(a.fd);
-                if (!file)
-                        goto out;
-        }
-        a.flags &= ~(MAP_EXECUTABLE | MAP_DENYWRITE);
 
-        down_write(&current->mm->mmap_sem);
-        error = do_mmap_pgoff(file, a.addr, a.len, a.prot, a.flags, pgoff);
-        up_write(&current->mm->mmap_sem);
-        if (file)
-                fput(file);
-out:
-        return error;
+        return sys_mmap_pgoff(addr, len, prot, flags, fd,
+                              pgoff >> (PAGE_SHIFT - 12));
 }
-#endif
 
 /*
  * sys_ipc() is the de-multiplexer for the SysV IPC calls..
diff --git a/arch/h8300/Kconfig b/arch/h8300/Kconfig
index 9420648352b8..53cc669e6d59 100644
--- a/arch/h8300/Kconfig
+++ b/arch/h8300/Kconfig
@@ -10,6 +10,10 @@ config H8300
         default y
         select HAVE_IDE
 
+config SYMBOL_PREFIX
+        string
+        default "_"
+
 config MMU
         bool
         default n
diff --git a/arch/h8300/include/asm/asm-offsets.h b/arch/h8300/include/asm/asm-offsets.h
new file mode 100644
index 000000000000..d370ee36a182
--- /dev/null
+++ b/arch/h8300/include/asm/asm-offsets.h
@@ -0,0 +1 @@
+#include <generated/asm-offsets.h>
diff --git a/arch/h8300/include/asm/elf.h b/arch/h8300/include/asm/elf.h
index 94e2284c8816..c24fa250d653 100644
--- a/arch/h8300/include/asm/elf.h
+++ b/arch/h8300/include/asm/elf.h
@@ -34,7 +34,6 @@ typedef unsigned long elf_fpregset_t;
 
 #define ELF_PLAT_INIT(_r)       _r->er1 = 0
 
-#define USE_ELF_CORE_DUMP
 #define ELF_EXEC_PAGESIZE       4096
 
 /* This is the location that an ET_DYN program is loaded if exec'ed.  Typical
diff --git a/arch/h8300/include/asm/module.h b/arch/h8300/include/asm/module.h
index de23231f3196..8e46724b7c09 100644
--- a/arch/h8300/include/asm/module.h
+++ b/arch/h8300/include/asm/module.h
@@ -8,6 +8,4 @@ struct mod_arch_specific { };
 #define Elf_Sym Elf32_Sym
 #define Elf_Ehdr Elf32_Ehdr
 
-#define MODULE_SYMBOL_PREFIX "_"
-
 #endif /* _ASM_H8/300_MODULE_H */
diff --git a/arch/h8300/kernel/irq.c b/arch/h8300/kernel/irq.c
index 5c913d472119..c25dc2c2b1da 100644
--- a/arch/h8300/kernel/irq.c
+++ b/arch/h8300/kernel/irq.c
@@ -186,7 +186,7 @@ int show_interrupts(struct seq_file *p, void *v)
                 seq_puts(p, "           CPU0");
 
         if (i < NR_IRQS) {
-                spin_lock_irqsave(&irq_desc[i].lock, flags);
+                raw_spin_lock_irqsave(&irq_desc[i].lock, flags);
                 action = irq_desc[i].action;
                 if (!action)
                         goto unlock;
@@ -200,7 +200,7 @@ int show_interrupts(struct seq_file *p, void *v)
                         seq_printf(p, ", %s", action->name);
                 seq_putc(p, '\n');
 unlock:
-                spin_unlock_irqrestore(&irq_desc[i].lock, flags);
+                raw_spin_unlock_irqrestore(&irq_desc[i].lock, flags);
         }
         return 0;
 }
diff --git a/arch/h8300/kernel/sys_h8300.c b/arch/h8300/kernel/sys_h8300.c
index 8cb5d73a0e35..b5969db0ca10 100644
--- a/arch/h8300/kernel/sys_h8300.c
+++ b/arch/h8300/kernel/sys_h8300.c
@@ -26,39 +26,6 @@
 #include <asm/traps.h>
 #include <asm/unistd.h>
 
-/* common code for old and new mmaps */
-static inline long do_mmap2(
-        unsigned long addr, unsigned long len,
-        unsigned long prot, unsigned long flags,
-        unsigned long fd, unsigned long pgoff)
-{
-        int error = -EBADF;
-        struct file * file = NULL;
-
-        flags &= ~(MAP_EXECUTABLE | MAP_DENYWRITE);
-        if (!(flags & MAP_ANONYMOUS)) {
-                file = fget(fd);
-                if (!file)
-                        goto out;
-        }
-
-        down_write(&current->mm->mmap_sem);
-        error = do_mmap_pgoff(file, addr, len, prot, flags, pgoff);
-        up_write(&current->mm->mmap_sem);
-
-        if (file)
-                fput(file);
-out:
-        return error;
-}
-
-asmlinkage long sys_mmap2(unsigned long addr, unsigned long len,
-        unsigned long prot, unsigned long flags,
-        unsigned long fd, unsigned long pgoff)
-{
-        return do_mmap2(addr, len, prot, flags, fd, pgoff);
-}
-
 /*
  * Perform the select(nd, in, out, ex, tv) and mmap() system
  * calls. Linux/m68k cloned Linux/i386, which didn't use to be able to
@@ -87,57 +54,11 @@ asmlinkage int old_mmap(struct mmap_arg_struct *arg)
         if (a.offset & ~PAGE_MASK)
                 goto out;
 
-        a.flags &= ~(MAP_EXECUTABLE | MAP_DENYWRITE);
-
-        error = do_mmap2(a.addr, a.len, a.prot, a.flags, a.fd, a.offset >> PAGE_SHIFT);
-out:
-        return error;
-}
-
-#if 0 /* DAVIDM - do we want this */
-struct mmap_arg_struct64 {
-        __u32 addr;
-        __u32 len;
-        __u32 prot;
-        __u32 flags;
-        __u64 offset; /* 64 bits */
-        __u32 fd;
-};
-
-asmlinkage long sys_mmap64(struct mmap_arg_struct64 *arg)
-{
-        int error = -EFAULT;
-        struct file * file = NULL;
-        struct mmap_arg_struct64 a;
-        unsigned long pgoff;
-
-        if (copy_from_user(&a, arg, sizeof(a)))
-                return -EFAULT;
-
-        if ((long)a.offset & ~PAGE_MASK)
-                return -EINVAL;
-
-        pgoff = a.offset >> PAGE_SHIFT;
-        if ((a.offset >> PAGE_SHIFT) != pgoff)
-                return -EINVAL;
-
-        if (!(a.flags & MAP_ANONYMOUS)) {
-                error = -EBADF;
-                file = fget(a.fd);
-                if (!file)
-                        goto out;
-        }
-        a.flags &= ~(MAP_EXECUTABLE | MAP_DENYWRITE);
-
-        down_write(&current->mm->mmap_sem);
-        error = do_mmap_pgoff(file, a.addr, a.len, a.prot, a.flags, pgoff);
-        up_write(&current->mm->mmap_sem);
-        if (file)
-                fput(file);
+        error = sys_mmap_pgoff(a.addr, a.len, a.prot, a.flags, a.fd,
+                               a.offset >> PAGE_SHIFT);
 out:
         return error;
 }
-#endif
 
 struct sel_arg_struct {
         unsigned long n;
diff --git a/arch/h8300/kernel/syscalls.S b/arch/h8300/kernel/syscalls.S
index 4eb67faac633..2d69881eda6a 100644
--- a/arch/h8300/kernel/syscalls.S
+++ b/arch/h8300/kernel/syscalls.S
@@ -206,7 +206,7 @@ SYMBOL_NAME_LABEL(sys_call_table)
         .long SYMBOL_NAME(sys_ni_syscall)       /* streams2 */
         .long SYMBOL_NAME(sys_vfork)            /* 190 */
         .long SYMBOL_NAME(sys_getrlimit)
-        .long SYMBOL_NAME(sys_mmap2)
+        .long SYMBOL_NAME(sys_mmap_pgoff)
         .long SYMBOL_NAME(sys_truncate64)
         .long SYMBOL_NAME(sys_ftruncate64)
         .long SYMBOL_NAME(sys_stat64)           /* 195 */
diff --git a/arch/h8300/kernel/vmlinux.lds.S b/arch/h8300/kernel/vmlinux.lds.S
index b9e24907e6ea..03d356d96e5d 100644
--- a/arch/h8300/kernel/vmlinux.lds.S
+++ b/arch/h8300/kernel/vmlinux.lds.S
@@ -1,4 +1,3 @@
-#define VMLINUX_SYMBOL(_sym_) _##_sym_
 #include <asm-generic/vmlinux.lds.h>
 #include <asm/page.h>
 
diff --git a/arch/ia64/Kconfig b/arch/ia64/Kconfig
index 1ee596cd942f..2d7f56a98e0f 100644
--- a/arch/ia64/Kconfig
+++ b/arch/ia64/Kconfig
@@ -87,9 +87,6 @@ config GENERIC_TIME_VSYSCALL
         bool
         default y
 
-config HAVE_LEGACY_PER_CPU_AREA
-        def_bool y
-
 config HAVE_SETUP_PER_CPU_AREA
         def_bool y
 
diff --git a/arch/ia64/Makefile b/arch/ia64/Makefile
index e7cbaa02cd0b..475e2725fbde 100644
--- a/arch/ia64/Makefile
+++ b/arch/ia64/Makefile
@@ -103,4 +103,4 @@ archprepare: make_nr_irqs_h FORCE
 PHONY += make_nr_irqs_h FORCE
 
 make_nr_irqs_h: FORCE
-        $(Q)$(MAKE) $(build)=arch/ia64/kernel include/asm-ia64/nr-irqs.h
+        $(Q)$(MAKE) $(build)=arch/ia64/kernel include/generated/nr-irqs.h
diff --git a/arch/ia64/hp/common/sba_iommu.c b/arch/ia64/hp/common/sba_iommu.c
index f332e3fe4237..e14c492a8a93 100644
--- a/arch/ia64/hp/common/sba_iommu.c
+++ b/arch/ia64/hp/common/sba_iommu.c
@@ -677,12 +677,19 @@ sba_alloc_range(struct ioc *ioc, struct device *dev, size_t size)
                         spin_unlock_irqrestore(&ioc->saved_lock, flags);
 
                         pide = sba_search_bitmap(ioc, dev, pages_needed, 0);
-                        if (unlikely(pide >= (ioc->res_size << 3)))
-                                panic(__FILE__ ": I/O MMU @ %p is out of mapping resources\n",
-                                      ioc->ioc_hpa);
+                        if (unlikely(pide >= (ioc->res_size << 3))) {
+                                printk(KERN_WARNING "%s: I/O MMU @ %p is"
+                                       "out of mapping resources, %u %u %lx\n",
+                                       __func__, ioc->ioc_hpa, ioc->res_size,
+                                       pages_needed, dma_get_seg_boundary(dev));
+                                return -1;
+                        }
 #else
-                        panic(__FILE__ ": I/O MMU @ %p is out of mapping resources\n",
-                              ioc->ioc_hpa);
+                        printk(KERN_WARNING "%s: I/O MMU @ %p is"
+                               "out of mapping resources, %u %u %lx\n",
+                               __func__, ioc->ioc_hpa, ioc->res_size,
+                               pages_needed, dma_get_seg_boundary(dev));
+                        return -1;
 #endif
                 }
         }
@@ -965,6 +972,8 @@ static dma_addr_t sba_map_page(struct device *dev, struct page *page,
 #endif
 
         pide = sba_alloc_range(ioc, dev, size);
+        if (pide < 0)
+                return 0;
 
         iovp = (dma_addr_t) pide << iovp_shift;
 
@@ -1320,6 +1329,7 @@ sba_coalesce_chunks(struct ioc *ioc, struct device *dev,
         unsigned long dma_offset, dma_len; /* start/len of DMA stream */
         int n_mappings = 0;
         unsigned int max_seg_size = dma_get_max_seg_size(dev);
+        int idx;
 
         while (nents > 0) {
                 unsigned long vaddr = (unsigned long) sba_sg_address(startsg);
@@ -1418,16 +1428,22 @@ sba_coalesce_chunks(struct ioc *ioc, struct device *dev,
                 vcontig_sg->dma_length = vcontig_len;
                 dma_len = (dma_len + dma_offset + ~iovp_mask) & iovp_mask;
                 ASSERT(dma_len <= DMA_CHUNK_SIZE);
-                dma_sg->dma_address = (dma_addr_t) (PIDE_FLAG
-                        | (sba_alloc_range(ioc, dev, dma_len) << iovp_shift)
-                        | dma_offset);
+                idx = sba_alloc_range(ioc, dev, dma_len);
+                if (idx < 0) {
+                        dma_sg->dma_length = 0;
+                        return -1;
+                }
+                dma_sg->dma_address = (dma_addr_t)(PIDE_FLAG | (idx << iovp_shift)
+                                                   | dma_offset);
                 n_mappings++;
         }
 
         return n_mappings;
 }
 
-
+static void sba_unmap_sg_attrs(struct device *dev, struct scatterlist *sglist,
+                               int nents, enum dma_data_direction dir,
+                               struct dma_attrs *attrs);
 /**
  * sba_map_sg - map Scatter/Gather list
  * @dev: instance of PCI owned by the driver that's asking.
@@ -1493,6 +1509,10 @@ static int sba_map_sg_attrs(struct device *dev, struct scatterlist *sglist,
         ** Access to the virtual address is what forces a two pass algorithm.
         */
         coalesced = sba_coalesce_chunks(ioc, dev, sglist, nents);
+        if (coalesced < 0) {
+                sba_unmap_sg_attrs(dev, sglist, nents, dir, attrs);
+                return 0;
+        }
 
         /*
         ** Program the I/O Pdir
diff --git a/arch/ia64/ia32/elfcore32.h b/arch/ia64/ia32/elfcore32.h
index 9a3abf58cea3..657725742617 100644
--- a/arch/ia64/ia32/elfcore32.h
+++ b/arch/ia64/ia32/elfcore32.h
@@ -11,8 +11,6 @@
 #include <asm/intrinsics.h>
 #include <asm/uaccess.h>
 
-#define USE_ELF_CORE_DUMP 1
-
 /* Override elfcore.h */
 #define _LINUX_ELFCORE_H 1
 typedef unsigned int elf_greg_t;
diff --git a/arch/ia64/ia32/sys_ia32.c b/arch/ia64/ia32/sys_ia32.c
index 429ec968c9ee..045b746b9808 100644
--- a/arch/ia64/ia32/sys_ia32.c
+++ b/arch/ia64/ia32/sys_ia32.c
@@ -858,6 +858,9 @@ ia32_do_mmap (struct file *file, unsigned long addr, unsigned long len, int prot
 
         prot = get_prot32(prot);
 
+        if (flags & MAP_HUGETLB)
+                return -ENOMEM;
+
 #if PAGE_SHIFT > IA32_PAGE_SHIFT
         mutex_lock(&ia32_mmap_mutex);
         {
diff --git a/arch/ia64/include/asm/asm-offsets.h b/arch/ia64/include/asm/asm-offsets.h
new file mode 100644
index 000000000000..d370ee36a182
--- /dev/null
+++ b/arch/ia64/include/asm/asm-offsets.h
@@ -0,0 +1 @@
+#include <generated/asm-offsets.h>
diff --git a/arch/ia64/include/asm/bitops.h b/arch/ia64/include/asm/bitops.h
index 57a2787bc9fb..6ebc229a1c51 100644
--- a/arch/ia64/include/asm/bitops.h
+++ b/arch/ia64/include/asm/bitops.h
@@ -127,7 +127,7 @@ clear_bit_unlock (int nr, volatile void *addr)
  * @addr: Address to start counting from
  *
  * Similarly to clear_bit_unlock, the implementation uses a store
- * with release semantics. See also __raw_spin_unlock().
+ * with release semantics. See also arch_spin_unlock().
  */
 static __inline__ void
 __clear_bit_unlock(int nr, void *addr)
diff --git a/arch/ia64/include/asm/dma-mapping.h b/arch/ia64/include/asm/dma-mapping.h
index 8d3c79cd81e7..7d09a09cdaad 100644
--- a/arch/ia64/include/asm/dma-mapping.h
+++ b/arch/ia64/include/asm/dma-mapping.h
@@ -73,7 +73,7 @@ static inline bool dma_capable(struct device *dev, dma_addr_t addr, size_t size)
         if (!dev->dma_mask)
                 return 0;
 
-        return addr + size <= *dev->dma_mask;
+        return addr + size - 1 <= *dev->dma_mask;
 }
 
 static inline dma_addr_t phys_to_dma(struct device *dev, phys_addr_t paddr)
diff --git a/arch/ia64/include/asm/elf.h b/arch/ia64/include/asm/elf.h
index 86eddee029cb..e14108b19c09 100644
--- a/arch/ia64/include/asm/elf.h
+++ b/arch/ia64/include/asm/elf.h
@@ -25,7 +25,6 @@
 #define ELF_DATA        ELFDATA2LSB
 #define ELF_ARCH        EM_IA_64
 
-#define USE_ELF_CORE_DUMP
 #define CORE_DUMP_USE_REGSET
 
 /* Least-significant four bits of ELF header's e_flags are OS-specific.  The bits are
diff --git a/arch/ia64/include/asm/hw_irq.h b/arch/ia64/include/asm/hw_irq.h
index 91619b31dbf5..bf2e37493e04 100644
--- a/arch/ia64/include/asm/hw_irq.h
+++ b/arch/ia64/include/asm/hw_irq.h
@@ -59,7 +59,13 @@ typedef u16 ia64_vector;
 extern int ia64_first_device_vector;
 extern int ia64_last_device_vector;
 
+#if defined(CONFIG_SMP) && (defined(CONFIG_IA64_GENERIC) || defined (CONFIG_IA64_DIG))
+/* Reserve the lower priority vector than device vectors for "move IRQ" IPI */
+#define IA64_IRQ_MOVE_VECTOR            0x30    /* "move IRQ" IPI */
+#define IA64_DEF_FIRST_DEVICE_VECTOR    0x31
+#else
 #define IA64_DEF_FIRST_DEVICE_VECTOR    0x30
+#endif
 #define IA64_DEF_LAST_DEVICE_VECTOR     0xe7
 #define IA64_FIRST_DEVICE_VECTOR        ia64_first_device_vector
 #define IA64_LAST_DEVICE_VECTOR         ia64_last_device_vector
diff --git a/arch/ia64/include/asm/io.h b/arch/ia64/include/asm/io.h
index 0d9d16e2d949..cc8335eb3110 100644
--- a/arch/ia64/include/asm/io.h
+++ b/arch/ia64/include/asm/io.h
@@ -424,6 +424,8 @@ __writeq (unsigned long val, volatile void __iomem *addr)
 extern void __iomem * ioremap(unsigned long offset, unsigned long size);
 extern void __iomem * ioremap_nocache (unsigned long offset, unsigned long size);
 extern void iounmap (volatile void __iomem *addr);
+extern void __iomem * early_ioremap (unsigned long phys_addr, unsigned long size);
+extern void early_iounmap (volatile void __iomem *addr, unsigned long size);
 
 /*
  * String version of IO memory access ops:
diff --git a/arch/ia64/include/asm/irq.h b/arch/ia64/include/asm/irq.h
index 5282546cdf82..91b920fd7d53 100644
--- a/arch/ia64/include/asm/irq.h
+++ b/arch/ia64/include/asm/irq.h
@@ -13,7 +13,7 @@
 
 #include <linux/types.h>
 #include <linux/cpumask.h>
-#include <asm-ia64/nr-irqs.h>
+#include <generated/nr-irqs.h>
 
 static __inline__ int
 irq_canonicalize (int irq)
diff --git a/arch/ia64/include/asm/mca.h b/arch/ia64/include/asm/mca.h
index c171cdf0a789..43f96ab18fa0 100644
--- a/arch/ia64/include/asm/mca.h
+++ b/arch/ia64/include/asm/mca.h
@@ -106,6 +106,11 @@ struct ia64_sal_os_state {
         unsigned long           os_status;              /* OS status to SAL, enum below */
         unsigned long           context;                /* 0 if return to same context
                                                            1 if return to new context */
+
+        /* I-resources */
+        unsigned long           iip;
+        unsigned long           ipsr;
+        unsigned long           ifs;
 };
 
 enum {
diff --git a/arch/ia64/include/asm/meminit.h b/arch/ia64/include/asm/meminit.h
index 688a812c017d..61c7b1750b16 100644
--- a/arch/ia64/include/asm/meminit.h
+++ b/arch/ia64/include/asm/meminit.h
@@ -61,7 +61,7 @@ extern int register_active_ranges(u64 start, u64 len, int nid);
 
 #ifdef CONFIG_VIRTUAL_MEM_MAP
 # define LARGE_GAP      0x40000000 /* Use virtual mem map if hole is > than this */
-  extern unsigned long vmalloc_end;
+  extern unsigned long VMALLOC_END;
   extern struct page *vmem_map;
   extern int find_largest_hole(u64 start, u64 end, void *arg);
   extern int create_mem_map_page_table(u64 start, u64 end, void *arg);
diff --git a/arch/ia64/include/asm/numa.h b/arch/ia64/include/asm/numa.h
index 3499ff57bf42..6a8a27cfae3e 100644
--- a/arch/ia64/include/asm/numa.h
+++ b/arch/ia64/include/asm/numa.h
@@ -22,8 +22,6 @@
 
 #include <asm/mmzone.h>
 
-#define NUMA_NO_NODE    -1
-
 extern u16 cpu_to_node_map[NR_CPUS] __cacheline_aligned;
 extern cpumask_t node_to_cpu_mask[MAX_NUMNODES] __cacheline_aligned;
 extern pg_data_t *pgdat_list[MAX_NUMNODES];
diff --git a/arch/ia64/include/asm/pgtable.h b/arch/ia64/include/asm/pgtable.h
index 8840a690d1e7..69bf13857a9f 100644
--- a/arch/ia64/include/asm/pgtable.h
+++ b/arch/ia64/include/asm/pgtable.h
@@ -228,8 +228,7 @@ ia64_phys_addr_valid (unsigned long addr)
 #define VMALLOC_START           (RGN_BASE(RGN_GATE) + 0x200000000UL)
 #ifdef CONFIG_VIRTUAL_MEM_MAP
 # define VMALLOC_END_INIT       (RGN_BASE(RGN_GATE) + (1UL << (4*PAGE_SHIFT - 9)))
-# define VMALLOC_END            vmalloc_end
-  extern unsigned long vmalloc_end;
+extern unsigned long VMALLOC_END;
 #else
 #if defined(CONFIG_SPARSEMEM) && defined(CONFIG_SPARSEMEM_VMEMMAP)
 /* SPARSEMEM_VMEMMAP uses half of vmalloc... */
diff --git a/arch/ia64/include/asm/processor.h b/arch/ia64/include/asm/processor.h
index 3eaeedf1aef2..7fa90f73f6be 100644
--- a/arch/ia64/include/asm/processor.h
+++ b/arch/ia64/include/asm/processor.h
@@ -229,7 +229,7 @@ struct cpuinfo_ia64 {
 #endif
 };
 
-DECLARE_PER_CPU(struct cpuinfo_ia64, cpu_info);
+DECLARE_PER_CPU(struct cpuinfo_ia64, ia64_cpu_info);
 
 /*
  * The "local" data variable.  It refers to the per-CPU data of the currently executing
@@ -237,8 +237,8 @@ DECLARE_PER_CPU(struct cpuinfo_ia64, cpu_info);
  * Do not use the address of local_cpu_data, since it will be different from
  * cpu_data(smp_processor_id())!
  */
-#define local_cpu_data          (&__ia64_per_cpu_var(cpu_info))
-#define cpu_data(cpu)           (&per_cpu(cpu_info, cpu))
+#define local_cpu_data          (&__ia64_per_cpu_var(ia64_cpu_info))
+#define cpu_data(cpu)           (&per_cpu(ia64_cpu_info, cpu))
 
 extern void print_cpu_info (struct cpuinfo_ia64 *);
 
diff --git a/arch/ia64/include/asm/rwsem.h b/arch/ia64/include/asm/rwsem.h
index fbee74b15782..e8762688e8e3 100644
--- a/arch/ia64/include/asm/rwsem.h
+++ b/arch/ia64/include/asm/rwsem.h
@@ -47,7 +47,7 @@ struct rw_semaphore {
 #define RWSEM_ACTIVE_WRITE_BIAS         (RWSEM_WAITING_BIAS + RWSEM_ACTIVE_BIAS)
 
 #define __RWSEM_INITIALIZER(name) \
-        { RWSEM_UNLOCKED_VALUE, SPIN_LOCK_UNLOCKED, \
+        { RWSEM_UNLOCKED_VALUE, __SPIN_LOCK_UNLOCKED((name).wait_lock), \
           LIST_HEAD_INIT((name).wait_list) }
 
 #define DECLARE_RWSEM(name) \
diff --git a/arch/ia64/include/asm/spinlock.h b/arch/ia64/include/asm/spinlock.h
index 239ecdc9516d..1a91c9121d17 100644
--- a/arch/ia64/include/asm/spinlock.h
+++ b/arch/ia64/include/asm/spinlock.h
@@ -17,7 +17,7 @@
 #include <asm/intrinsics.h>
 #include <asm/system.h>
 
-#define __raw_spin_lock_init(x)                 ((x)->lock = 0)
+#define arch_spin_lock_init(x)                  ((x)->lock = 0)
 
 /*
  * Ticket locks are conceptually two parts, one indicating the current head of
@@ -38,7 +38,7 @@
 #define TICKET_BITS     15
 #define TICKET_MASK     ((1 << TICKET_BITS) - 1)
 
-static __always_inline void __ticket_spin_lock(raw_spinlock_t *lock)
+static __always_inline void __ticket_spin_lock(arch_spinlock_t *lock)
 {
         int     *p = (int *)&lock->lock, ticket, serve;
 
@@ -58,7 +58,7 @@ static __always_inline void __ticket_spin_lock(raw_spinlock_t *lock)
         }
 }
 
-static __always_inline int __ticket_spin_trylock(raw_spinlock_t *lock)
+static __always_inline int __ticket_spin_trylock(arch_spinlock_t *lock)
 {
         int tmp = ACCESS_ONCE(lock->lock);
 
@@ -67,7 +67,7 @@ static __always_inline int __ticket_spin_trylock(raw_spinlock_t *lock)
         return 0;
 }
 
-static __always_inline void __ticket_spin_unlock(raw_spinlock_t *lock)
+static __always_inline void __ticket_spin_unlock(arch_spinlock_t *lock)
 {
         unsigned short  *p = (unsigned short *)&lock->lock + 1, tmp;
 
@@ -75,7 +75,7 @@ static __always_inline void __ticket_spin_unlock(raw_spinlock_t *lock)
         ACCESS_ONCE(*p) = (tmp + 2) & ~1;
 }
 
-static __always_inline void __ticket_spin_unlock_wait(raw_spinlock_t *lock)
+static __always_inline void __ticket_spin_unlock_wait(arch_spinlock_t *lock)
 {
         int     *p = (int *)&lock->lock, ticket;
 
@@ -89,64 +89,64 @@ static __always_inline void __ticket_spin_unlock_wait(raw_spinlock_t *lock)
         }
 }
 
-static inline int __ticket_spin_is_locked(raw_spinlock_t *lock)
+static inline int __ticket_spin_is_locked(arch_spinlock_t *lock)
 {
         long tmp = ACCESS_ONCE(lock->lock);
 
         return !!(((tmp >> TICKET_SHIFT) ^ tmp) & TICKET_MASK);
 }
 
-static inline int __ticket_spin_is_contended(raw_spinlock_t *lock)
+static inline int __ticket_spin_is_contended(arch_spinlock_t *lock)
 {
         long tmp = ACCESS_ONCE(lock->lock);
 
         return ((tmp - (tmp >> TICKET_SHIFT)) & TICKET_MASK) > 1;
 }
 
-static inline int __raw_spin_is_locked(raw_spinlock_t *lock)
+static inline int arch_spin_is_locked(arch_spinlock_t *lock)
 {
         return __ticket_spin_is_locked(lock);
 }
 
-static inline int __raw_spin_is_contended(raw_spinlock_t *lock)
+static inline int arch_spin_is_contended(arch_spinlock_t *lock)
 {
         return __ticket_spin_is_contended(lock);
 }
-#define __raw_spin_is_contended __raw_spin_is_contended
+#define arch_spin_is_contended  arch_spin_is_contended
 
-static __always_inline void __raw_spin_lock(raw_spinlock_t *lock)
+static __always_inline void arch_spin_lock(arch_spinlock_t *lock)
 {
         __ticket_spin_lock(lock);
 }
 
-static __always_inline int __raw_spin_trylock(raw_spinlock_t *lock)
+static __always_inline int arch_spin_trylock(arch_spinlock_t *lock)
 {
         return __ticket_spin_trylock(lock);
 }
 
-static __always_inline void __raw_spin_unlock(raw_spinlock_t *lock)
+static __always_inline void arch_spin_unlock(arch_spinlock_t *lock)
 {
         __ticket_spin_unlock(lock);
 }
 
-static __always_inline void __raw_spin_lock_flags(raw_spinlock_t *lock,
+static __always_inline void arch_spin_lock_flags(arch_spinlock_t *lock,
                                                   unsigned long flags)
 {
-        __raw_spin_lock(lock);
+        arch_spin_lock(lock);
 }
 
-static inline void __raw_spin_unlock_wait(raw_spinlock_t *lock)
+static inline void arch_spin_unlock_wait(arch_spinlock_t *lock)
 {
         __ticket_spin_unlock_wait(lock);
 }
 
-#define __raw_read_can_lock(rw)         (*(volatile int *)(rw) >= 0)
-#define __raw_write_can_lock(rw)        (*(volatile int *)(rw) == 0)
+#define arch_read_can_lock(rw)          (*(volatile int *)(rw) >= 0)
+#define arch_write_can_lock(rw) (*(volatile int *)(rw) == 0)
 
 #ifdef ASM_SUPPORTED
 
 static __always_inline void
-__raw_read_lock_flags(raw_rwlock_t *lock, unsigned long flags)
+arch_read_lock_flags(arch_rwlock_t *lock, unsigned long flags)
 {
         __asm__ __volatile__ (
                 "tbit.nz p6, p0 = %1,%2\n"
@@ -169,15 +169,15 @@ __raw_read_lock_flags(raw_rwlock_t *lock, unsigned long flags)
                 : "p6", "p7", "r2", "memory");
 }
 
-#define __raw_read_lock(lock) __raw_read_lock_flags(lock, 0)
+#define arch_read_lock(lock) arch_read_lock_flags(lock, 0)
 
 #else /* !ASM_SUPPORTED */
 
-#define __raw_read_lock_flags(rw, flags) __raw_read_lock(rw)
+#define arch_read_lock_flags(rw, flags) arch_read_lock(rw)
 
-#define __raw_read_lock(rw)                                                             \
+#define arch_read_lock(rw)                                                              \
 do {                                                                                    \
-        raw_rwlock_t *__read_lock_ptr = (rw);                                           \
+        arch_rwlock_t *__read_lock_ptr = (rw);                                          \
                                                                                         \
         while (unlikely(ia64_fetchadd(1, (int *) __read_lock_ptr, acq) < 0)) {          \
                 ia64_fetchadd(-1, (int *) __read_lock_ptr, rel);                        \
@@ -188,16 +188,16 @@ do {											\
 
 #endif /* !ASM_SUPPORTED */
 
-#define __raw_read_unlock(rw)                                   \
+#define arch_read_unlock(rw)                                    \
 do {                                                            \
-        raw_rwlock_t *__read_lock_ptr = (rw);                   \
+        arch_rwlock_t *__read_lock_ptr = (rw);                  \
         ia64_fetchadd(-1, (int *) __read_lock_ptr, rel);        \
 } while (0)
 
 #ifdef ASM_SUPPORTED
 
 static __always_inline void
-__raw_write_lock_flags(raw_rwlock_t *lock, unsigned long flags)
+arch_write_lock_flags(arch_rwlock_t *lock, unsigned long flags)
 {
         __asm__ __volatile__ (
                 "tbit.nz p6, p0 = %1, %2\n"
@@ -221,9 +221,9 @@ __raw_write_lock_flags(raw_rwlock_t *lock, unsigned long flags)
                 : "ar.ccv", "p6", "p7", "r2", "r29", "memory");
 }
 
-#define __raw_write_lock(rw) __raw_write_lock_flags(rw, 0)
+#define arch_write_lock(rw) arch_write_lock_flags(rw, 0)
 
-#define __raw_write_trylock(rw)                                                 \
+#define arch_write_trylock(rw)                                                  \
 ({                                                                              \
         register long result;                                                   \
                                                                                 \
@@ -235,7 +235,7 @@ __raw_write_lock_flags(raw_rwlock_t *lock, unsigned long flags)
         (result == 0);                                                          \
 })
 
-static inline void __raw_write_unlock(raw_rwlock_t *x)
+static inline void arch_write_unlock(arch_rwlock_t *x)
 {
         u8 *y = (u8 *)x;
         barrier();
@@ -244,9 +244,9 @@ static inline void __raw_write_unlock(raw_rwlock_t *x)
 
 #else /* !ASM_SUPPORTED */
 
-#define __raw_write_lock_flags(l, flags) __raw_write_lock(l)
+#define arch_write_lock_flags(l, flags) arch_write_lock(l)
 
-#define __raw_write_lock(l)                                                             \
+#define arch_write_lock(l)                                                              \
 ({                                                                                      \
         __u64 ia64_val, ia64_set_val = ia64_dep_mi(-1, 0, 31, 1);                       \
         __u32 *ia64_write_lock_ptr = (__u32 *) (l);                                     \
@@ -257,7 +257,7 @@ static inline void __raw_write_unlock(raw_rwlock_t *x)
         } while (ia64_val);                                                             \
 })
 
-#define __raw_write_trylock(rw)                                         \
+#define arch_write_trylock(rw)                                          \
 ({                                                                      \
         __u64 ia64_val;                                                 \
         __u64 ia64_set_val = ia64_dep_mi(-1, 0, 31,1);                  \
@@ -265,7 +265,7 @@ static inline void __raw_write_unlock(raw_rwlock_t *x)
         (ia64_val == 0);                                                \
 })
 
-static inline void __raw_write_unlock(raw_rwlock_t *x)
+static inline void arch_write_unlock(arch_rwlock_t *x)
 {
         barrier();
         x->write_lock = 0;
@@ -273,10 +273,10 @@ static inline void __raw_write_unlock(raw_rwlock_t *x)
 
 #endif /* !ASM_SUPPORTED */
 
-static inline int __raw_read_trylock(raw_rwlock_t *x)
+static inline int arch_read_trylock(arch_rwlock_t *x)
 {
         union {
-                raw_rwlock_t lock;
+                arch_rwlock_t lock;
                 __u32 word;
         } old, new;
         old.lock = new.lock = *x;
@@ -285,8 +285,8 @@ static inline int __raw_read_trylock(raw_rwlock_t *x)
         return (u32)ia64_cmpxchg4_acq((__u32 *)(x), new.word, old.word) == old.word;
 }
 
-#define _raw_spin_relax(lock)   cpu_relax()
-#define _raw_read_relax(lock)   cpu_relax()
-#define _raw_write_relax(lock)  cpu_relax()
+#define arch_spin_relax(lock)   cpu_relax()
+#define arch_read_relax(lock)   cpu_relax()
+#define arch_write_relax(lock)  cpu_relax()
 
 #endif /*  _ASM_IA64_SPINLOCK_H */
diff --git a/arch/ia64/include/asm/spinlock_types.h b/arch/ia64/include/asm/spinlock_types.h
index 474e46f1ab4a..e2b42a52a6d3 100644
--- a/arch/ia64/include/asm/spinlock_types.h
+++ b/arch/ia64/include/asm/spinlock_types.h
@@ -7,15 +7,15 @@
 
 typedef struct {
         volatile unsigned int lock;
-} raw_spinlock_t;
+} arch_spinlock_t;
 
-#define __RAW_SPIN_LOCK_UNLOCKED        { 0 }
+#define __ARCH_SPIN_LOCK_UNLOCKED       { 0 }
 
 typedef struct {
         volatile unsigned int read_counter      : 31;
         volatile unsigned int write_lock        :  1;
-} raw_rwlock_t;
+} arch_rwlock_t;
 
-#define __RAW_RW_LOCK_UNLOCKED          { 0, 0 }
+#define __ARCH_RW_LOCK_UNLOCKED         { 0, 0 }
 
 #endif
diff --git a/arch/ia64/include/asm/xen/hypervisor.h b/arch/ia64/include/asm/xen/hypervisor.h
index 88afb54501e4..67455c2ed2b1 100644
--- a/arch/ia64/include/asm/xen/hypervisor.h
+++ b/arch/ia64/include/asm/xen/hypervisor.h
@@ -37,35 +37,9 @@
 #include <xen/interface/xen.h>
 #include <xen/interface/version.h>      /* to compile feature.c */
 #include <xen/features.h>               /* to comiple xen-netfront.c */
+#include <xen/xen.h>
 #include <asm/xen/hypercall.h>
 
-/* xen_domain_type is set before executing any C code by early_xen_setup */
-enum xen_domain_type {
-        XEN_NATIVE,     /* running on bare hardware */
-        XEN_PV_DOMAIN,  /* running in a PV domain */
-        XEN_HVM_DOMAIN, /* running in a Xen hvm domain*/
-};
-
-#ifdef CONFIG_XEN
-extern enum xen_domain_type xen_domain_type;
-#else
-#define xen_domain_type         XEN_NATIVE
-#endif
-
-#define xen_domain()            (xen_domain_type != XEN_NATIVE)
-#define xen_pv_domain()         (xen_domain() &&                        \
-                                 xen_domain_type == XEN_PV_DOMAIN)
-#define xen_hvm_domain()        (xen_domain() &&                        \
-                                 xen_domain_type == XEN_HVM_DOMAIN)
-
-#ifdef CONFIG_XEN_DOM0
-#define xen_initial_domain()    (xen_pv_domain() &&                     \
-                                 (xen_start_info->flags & SIF_INITDOMAIN))
-#else
-#define xen_initial_domain()    (0)
-#endif
-
-
 #ifdef CONFIG_XEN
 extern struct shared_info *HYPERVISOR_shared_info;
 extern struct start_info *xen_start_info;
diff --git a/arch/ia64/kernel/Makefile b/arch/ia64/kernel/Makefile
index 6b7edcab0cb5..2a75e937ae8d 100644
--- a/arch/ia64/kernel/Makefile
+++ b/arch/ia64/kernel/Makefile
@@ -81,17 +81,14 @@ define cmd_nr_irqs
 endef
 
 # We use internal kbuild rules to avoid the "is up to date" message from make
-arch/$(SRCARCH)/kernel/nr-irqs.s: $(srctree)/arch/$(SRCARCH)/kernel/nr-irqs.c \
-                                $(wildcard $(srctree)/include/asm-ia64/*/irq.h)
+arch/$(SRCARCH)/kernel/nr-irqs.s: arch/$(SRCARCH)/kernel/nr-irqs.c
         $(Q)mkdir -p $(dir $@)
         $(call if_changed_dep,cc_s_c)
 
-include/asm-ia64/nr-irqs.h: arch/$(SRCARCH)/kernel/nr-irqs.s
+include/generated/nr-irqs.h: arch/$(SRCARCH)/kernel/nr-irqs.s
         $(Q)mkdir -p $(dir $@)
         $(call cmd,nr_irqs)
 
-clean-files += $(objtree)/include/asm-ia64/nr-irqs.h
-
 #
 # native ivt.S, entry.S and fsys.S
 #
diff --git a/arch/ia64/kernel/acpi.c b/arch/ia64/kernel/acpi.c
index baec6f00f7f3..40574ae11401 100644
--- a/arch/ia64/kernel/acpi.c
+++ b/arch/ia64/kernel/acpi.c
@@ -702,11 +702,23 @@ int __init early_acpi_boot_init(void)
                 printk(KERN_ERR PREFIX
                        "Error parsing MADT - no LAPIC entries\n");
 
+#ifdef CONFIG_SMP
+        if (available_cpus == 0) {
+                printk(KERN_INFO "ACPI: Found 0 CPUS; assuming 1\n");
+                printk(KERN_INFO "CPU 0 (0x%04x)", hard_smp_processor_id());
+                smp_boot_data.cpu_phys_id[available_cpus] =
+                    hard_smp_processor_id();
+                available_cpus = 1;     /* We've got at least one of these, no? */
+        }
+        smp_boot_data.cpu_count = available_cpus;
+#endif
+        /* Make boot-up look pretty */
+        printk(KERN_INFO "%d CPUs available, %d CPUs total\n", available_cpus,
+               total_cpus);
+
         return 0;
 }
 
-
-
 int __init acpi_boot_init(void)
 {
 
@@ -769,18 +781,8 @@ int __init acpi_boot_init(void)
         if (acpi_table_parse(ACPI_SIG_FADT, acpi_parse_fadt))
                 printk(KERN_ERR PREFIX "Can't find FADT\n");
 
+#ifdef CONFIG_ACPI_NUMA
 #ifdef CONFIG_SMP
-        if (available_cpus == 0) {
-                printk(KERN_INFO "ACPI: Found 0 CPUS; assuming 1\n");
-                printk(KERN_INFO "CPU 0 (0x%04x)", hard_smp_processor_id());
-                smp_boot_data.cpu_phys_id[available_cpus] =
-                    hard_smp_processor_id();
-                available_cpus = 1;     /* We've got at least one of these, no? */
-        }
-        smp_boot_data.cpu_count = available_cpus;
-
-        smp_build_cpu_map();
-# ifdef CONFIG_ACPI_NUMA
         if (srat_num_cpus == 0) {
                 int cpu, i = 1;
                 for (cpu = 0; cpu < smp_boot_data.cpu_count; cpu++)
@@ -789,14 +791,9 @@ int __init acpi_boot_init(void)
                                 node_cpuid[i++].phys_id =
                                     smp_boot_data.cpu_phys_id[cpu];
         }
-# endif
 #endif
-#ifdef CONFIG_ACPI_NUMA
         build_cpu_to_node_map();
 #endif
-        /* Make boot-up look pretty */
-        printk(KERN_INFO "%d CPUs available, %d CPUs total\n", available_cpus,
-               total_cpus);
         return 0;
 }
 
diff --git a/arch/ia64/kernel/head.S b/arch/ia64/kernel/head.S
index 696eff28a0c4..17a9fba38930 100644
--- a/arch/ia64/kernel/head.S
+++ b/arch/ia64/kernel/head.S
@@ -1051,7 +1051,7 @@ END(ia64_delay_loop)
  * intermediate precision so that we can produce a full 64-bit result.
  */
 GLOBAL_ENTRY(ia64_native_sched_clock)
-        addl r8=THIS_CPU(cpu_info) + IA64_CPUINFO_NSEC_PER_CYC_OFFSET,r0
+        addl r8=THIS_CPU(ia64_cpu_info) + IA64_CPUINFO_NSEC_PER_CYC_OFFSET,r0
         mov.m r9=ar.itc         // fetch cycle-counter                          (35 cyc)
         ;;
         ldf8 f8=[r8]
@@ -1077,7 +1077,7 @@ sched_clock = ia64_native_sched_clock
 #ifdef CONFIG_VIRT_CPU_ACCOUNTING
 GLOBAL_ENTRY(cycle_to_cputime)
         alloc r16=ar.pfs,1,0,0,0
-        addl r8=THIS_CPU(cpu_info) + IA64_CPUINFO_NSEC_PER_CYC_OFFSET,r0
+        addl r8=THIS_CPU(ia64_cpu_info) + IA64_CPUINFO_NSEC_PER_CYC_OFFSET,r0
         ;;
         ldf8 f8=[r8]
         ;;
diff --git a/arch/ia64/kernel/ia64_ksyms.c b/arch/ia64/kernel/ia64_ksyms.c
index 14d39e300627..461b99902bf6 100644
--- a/arch/ia64/kernel/ia64_ksyms.c
+++ b/arch/ia64/kernel/ia64_ksyms.c
@@ -30,7 +30,7 @@ EXPORT_SYMBOL(max_low_pfn);	/* defined by bootmem.c, but not exported by generic
 #endif
 
 #include <asm/processor.h>
-EXPORT_SYMBOL(per_cpu__cpu_info);
+EXPORT_SYMBOL(per_cpu__ia64_cpu_info);
 #ifdef CONFIG_SMP
 EXPORT_SYMBOL(per_cpu__local_per_cpu_offset);
 #endif
diff --git a/arch/ia64/kernel/iosapic.c b/arch/ia64/kernel/iosapic.c
index dab4d393908c..95ac77aeae9b 100644
--- a/arch/ia64/kernel/iosapic.c
+++ b/arch/ia64/kernel/iosapic.c
@@ -793,12 +793,12 @@ iosapic_register_intr (unsigned int gsi,
                         goto unlock_iosapic_lock;
         }
 
-        spin_lock(&irq_desc[irq].lock);
+        raw_spin_lock(&irq_desc[irq].lock);
         dest = get_target_cpu(gsi, irq);
         dmode = choose_dmode();
         err = register_intr(gsi, irq, dmode, polarity, trigger);
         if (err < 0) {
-                spin_unlock(&irq_desc[irq].lock);
+                raw_spin_unlock(&irq_desc[irq].lock);
                 irq = err;
                 goto unlock_iosapic_lock;
         }
@@ -817,7 +817,7 @@ iosapic_register_intr (unsigned int gsi,
                (polarity == IOSAPIC_POL_HIGH ? "high" : "low"),
                cpu_logical_id(dest), dest, irq_to_vector(irq));
 
-        spin_unlock(&irq_desc[irq].lock);
+        raw_spin_unlock(&irq_desc[irq].lock);
  unlock_iosapic_lock:
         spin_unlock_irqrestore(&iosapic_lock, flags);
         return irq;
diff --git a/arch/ia64/kernel/irq.c b/arch/ia64/kernel/irq.c
index 7d8951229e7c..94ee9d067cbd 100644
--- a/arch/ia64/kernel/irq.c
+++ b/arch/ia64/kernel/irq.c
@@ -71,7 +71,7 @@ int show_interrupts(struct seq_file *p, void *v)
         }
 
         if (i < NR_IRQS) {
-                spin_lock_irqsave(&irq_desc[i].lock, flags);
+                raw_spin_lock_irqsave(&irq_desc[i].lock, flags);
                 action = irq_desc[i].action;
                 if (!action)
                         goto skip;
@@ -91,7 +91,7 @@ int show_interrupts(struct seq_file *p, void *v)
 
                 seq_putc(p, '\n');
 skip:
-                spin_unlock_irqrestore(&irq_desc[i].lock, flags);
+                raw_spin_unlock_irqrestore(&irq_desc[i].lock, flags);
         } else if (i == NR_IRQS)
                 seq_printf(p, "ERR: %10u\n", atomic_read(&irq_err_count));
         return 0;
diff --git a/arch/ia64/kernel/irq_ia64.c b/arch/ia64/kernel/irq_ia64.c
index dd9d7b54f1a1..d4093a173a3e 100644
--- a/arch/ia64/kernel/irq_ia64.c
+++ b/arch/ia64/kernel/irq_ia64.c
@@ -260,7 +260,6 @@ void __setup_vector_irq(int cpu)
 }
 
 #if defined(CONFIG_SMP) && (defined(CONFIG_IA64_GENERIC) || defined(CONFIG_IA64_DIG))
-#define IA64_IRQ_MOVE_VECTOR    IA64_DEF_FIRST_DEVICE_VECTOR
 
 static enum vector_domain_type {
         VECTOR_DOMAIN_NONE,
@@ -345,7 +344,7 @@ static irqreturn_t smp_irq_move_cleanup_interrupt(int irq, void *dev_id)
 
                 desc = irq_desc + irq;
                 cfg = irq_cfg + irq;
-                spin_lock(&desc->lock);
+                raw_spin_lock(&desc->lock);
                 if (!cfg->move_cleanup_count)
                         goto unlock;
 
@@ -358,7 +357,7 @@ static irqreturn_t smp_irq_move_cleanup_interrupt(int irq, void *dev_id)
                 spin_unlock_irqrestore(&vector_lock, flags);
                 cfg->move_cleanup_count--;
         unlock:
-                spin_unlock(&desc->lock);
+                raw_spin_unlock(&desc->lock);
         }
         return IRQ_HANDLED;
 }
@@ -659,11 +658,8 @@ init_IRQ (void)
         register_percpu_irq(IA64_SPURIOUS_INT_VECTOR, NULL);
 #ifdef CONFIG_SMP
 #if defined(CONFIG_IA64_GENERIC) || defined(CONFIG_IA64_DIG)
-        if (vector_domain_type != VECTOR_DOMAIN_NONE) {
-                BUG_ON(IA64_FIRST_DEVICE_VECTOR != IA64_IRQ_MOVE_VECTOR);
-                IA64_FIRST_DEVICE_VECTOR++;
+        if (vector_domain_type != VECTOR_DOMAIN_NONE)
                 register_percpu_irq(IA64_IRQ_MOVE_VECTOR, &irq_move_irqaction);
-        }
 #endif
 #endif
 #ifdef CONFIG_PERFMON
diff --git a/arch/ia64/kernel/mca.c b/arch/ia64/kernel/mca.c
index 496ac7a99488..32f2639e9b0a 100644
--- a/arch/ia64/kernel/mca.c
+++ b/arch/ia64/kernel/mca.c
@@ -888,9 +888,10 @@ ia64_mca_modify_comm(const struct task_struct *previous_current)
 }
 
 static void
-finish_pt_regs(struct pt_regs *regs, const pal_min_state_area_t *ms,
+finish_pt_regs(struct pt_regs *regs, struct ia64_sal_os_state *sos,
                 unsigned long *nat)
 {
+        const pal_min_state_area_t *ms = sos->pal_min_state;
         const u64 *bank;
 
         /* If ipsr.ic then use pmsa_{iip,ipsr,ifs}, else use
@@ -904,6 +905,10 @@ finish_pt_regs(struct pt_regs *regs, const pal_min_state_area_t *ms,
                 regs->cr_iip = ms->pmsa_xip;
                 regs->cr_ipsr = ms->pmsa_xpsr;
                 regs->cr_ifs = ms->pmsa_xfs;
+
+                sos->iip = ms->pmsa_iip;
+                sos->ipsr = ms->pmsa_ipsr;
+                sos->ifs = ms->pmsa_ifs;
         }
         regs->pr = ms->pmsa_pr;
         regs->b0 = ms->pmsa_br0;
@@ -1079,7 +1084,7 @@ ia64_mca_modify_original_stack(struct pt_regs *regs,
         memcpy(old_regs, regs, sizeof(*regs));
         old_regs->loadrs = loadrs;
         old_unat = old_regs->ar_unat;
-        finish_pt_regs(old_regs, ms, &old_unat);
+        finish_pt_regs(old_regs, sos, &old_unat);
 
         /* Next stack a struct switch_stack.  mca_asm.S built a partial
          * switch_stack, copy it and fill in the blanks using pt_regs and
@@ -1150,7 +1155,7 @@ no_mod:
         mprintk(KERN_INFO "cpu %d, %s %s, original stack not modified\n",
                         smp_processor_id(), type, msg);
         old_unat = regs->ar_unat;
-        finish_pt_regs(regs, ms, &old_unat);
+        finish_pt_regs(regs, sos, &old_unat);
         return previous_current;
 }
 
diff --git a/arch/ia64/kernel/mca_asm.S b/arch/ia64/kernel/mca_asm.S
index 7461d2573d41..d5bdf9de36b6 100644
--- a/arch/ia64/kernel/mca_asm.S
+++ b/arch/ia64/kernel/mca_asm.S
@@ -59,7 +59,7 @@
 ia64_do_tlb_purge:
 #define O(member)       IA64_CPUINFO_##member##_OFFSET
 
-        GET_THIS_PADDR(r2, cpu_info)    // load phys addr of cpu_info into r2
+        GET_THIS_PADDR(r2, ia64_cpu_info) // load phys addr of cpu_info into r2
         ;;
         addl r17=O(PTCE_STRIDE),r2
         addl r2=O(PTCE_BASE),r2
diff --git a/arch/ia64/kernel/perfmon.c b/arch/ia64/kernel/perfmon.c
index 599b233bef75..5246285a95fb 100644
--- a/arch/ia64/kernel/perfmon.c
+++ b/arch/ia64/kernel/perfmon.c
@@ -2200,7 +2200,7 @@ pfm_alloc_file(pfm_context_t *ctx)
 {
         struct file *file;
         struct inode *inode;
-        struct dentry *dentry;
+        struct path path;
         char name[32];
         struct qstr this;
 
@@ -2225,18 +2225,19 @@ pfm_alloc_file(pfm_context_t *ctx)
         /*
          * allocate a new dcache entry
          */
-        dentry = d_alloc(pfmfs_mnt->mnt_sb->s_root, &this);
-        if (!dentry) {
+        path.dentry = d_alloc(pfmfs_mnt->mnt_sb->s_root, &this);
+        if (!path.dentry) {
                 iput(inode);
                 return ERR_PTR(-ENOMEM);
         }
+        path.mnt = mntget(pfmfs_mnt);
 
-        dentry->d_op = &pfmfs_dentry_operations;
-        d_add(dentry, inode);
+        path.dentry->d_op = &pfmfs_dentry_operations;
+        d_add(path.dentry, inode);
 
-        file = alloc_file(pfmfs_mnt, dentry, FMODE_READ, &pfm_file_ops);
+        file = alloc_file(&path, FMODE_READ, &pfm_file_ops);
         if (!file) {
-                dput(dentry);
+                path_put(&path);
                 return ERR_PTR(-ENFILE);
         }
 
diff --git a/arch/ia64/kernel/relocate_kernel.S b/arch/ia64/kernel/relocate_kernel.S
index 32f6fc131fbe..c370e02f0061 100644
--- a/arch/ia64/kernel/relocate_kernel.S
+++ b/arch/ia64/kernel/relocate_kernel.S
@@ -61,7 +61,7 @@ GLOBAL_ENTRY(relocate_new_kernel)
 
         // purge all TC entries
 #define O(member)       IA64_CPUINFO_##member##_OFFSET
-        GET_THIS_PADDR(r2, cpu_info)    // load phys addr of cpu_info into r2
+        GET_THIS_PADDR(r2, ia64_cpu_info) // load phys addr of cpu_info into r2
         ;;
         addl r17=O(PTCE_STRIDE),r2
         addl r2=O(PTCE_BASE),r2
diff --git a/arch/ia64/kernel/setup.c b/arch/ia64/kernel/setup.c
index 1de86c96801d..a1ea87919777 100644
--- a/arch/ia64/kernel/setup.c
+++ b/arch/ia64/kernel/setup.c
@@ -74,7 +74,7 @@ unsigned long __per_cpu_offset[NR_CPUS];
 EXPORT_SYMBOL(__per_cpu_offset);
 #endif
 
-DEFINE_PER_CPU(struct cpuinfo_ia64, cpu_info);
+DEFINE_PER_CPU(struct cpuinfo_ia64, ia64_cpu_info);
 DEFINE_PER_CPU(unsigned long, local_per_cpu_offset);
 unsigned long ia64_cycles_per_usec;
 struct ia64_boot_param *ia64_boot_param;
@@ -566,19 +566,18 @@ setup_arch (char **cmdline_p)
         early_acpi_boot_init();
 # ifdef CONFIG_ACPI_NUMA
         acpi_numa_init();
-#ifdef CONFIG_ACPI_HOTPLUG_CPU
+#  ifdef CONFIG_ACPI_HOTPLUG_CPU
         prefill_possible_map();
-#endif
+#  endif
         per_cpu_scan_finalize((cpus_weight(early_cpu_possible_map) == 0 ?
                 32 : cpus_weight(early_cpu_possible_map)),
                 additional_cpus > 0 ? additional_cpus : 0);
 # endif
-#else
-# ifdef CONFIG_SMP
-        smp_build_cpu_map();    /* happens, e.g., with the Ski simulator */
-# endif
 #endif /* CONFIG_APCI_BOOT */
 
+#ifdef CONFIG_SMP
+        smp_build_cpu_map();
+#endif
         find_memory();
 
         /* process SAL system table: */
@@ -856,18 +855,6 @@ identify_cpu (struct cpuinfo_ia64 *c)
 }
 
 /*
- * In UP configuration, setup_per_cpu_areas() is defined in
- * include/linux/percpu.h
- */
-#ifdef CONFIG_SMP
-void __init
-setup_per_cpu_areas (void)
-{
-        /* start_kernel() requires this... */
-}
-#endif
-
-/*
  * Do the following calculations:
  *
  * 1. the max. cache line size.
@@ -980,7 +967,7 @@ cpu_init (void)
          * depends on the data returned by identify_cpu().  We break the dependency by
          * accessing cpu_data() through the canonical per-CPU address.
          */
-        cpu_info = cpu_data + ((char *) &__ia64_per_cpu_var(cpu_info) - __per_cpu_start);
+        cpu_info = cpu_data + ((char *) &__ia64_per_cpu_var(ia64_cpu_info) - __per_cpu_start);
         identify_cpu(cpu_info);
 
 #ifdef CONFIG_MCKINLEY
diff --git a/arch/ia64/kernel/sys_ia64.c b/arch/ia64/kernel/sys_ia64.c
index 92ed83f34036..609d50056a6c 100644
--- a/arch/ia64/kernel/sys_ia64.c
+++ b/arch/ia64/kernel/sys_ia64.c
@@ -100,51 +100,7 @@ sys_getpagesize (void)
 asmlinkage unsigned long
 ia64_brk (unsigned long brk)
 {
-        unsigned long rlim, retval, newbrk, oldbrk;
-        struct mm_struct *mm = current->mm;
-
-        /*
-         * Most of this replicates the code in sys_brk() except for an additional safety
-         * check and the clearing of r8.  However, we can't call sys_brk() because we need
-         * to acquire the mmap_sem before we can do the test...
-         */
-        down_write(&mm->mmap_sem);
-
-        if (brk < mm->end_code)
-                goto out;
-        newbrk = PAGE_ALIGN(brk);
-        oldbrk = PAGE_ALIGN(mm->brk);
-        if (oldbrk == newbrk)
-                goto set_brk;
-
-        /* Always allow shrinking brk. */
-        if (brk <= mm->brk) {
-                if (!do_munmap(mm, newbrk, oldbrk-newbrk))
-                        goto set_brk;
-                goto out;
-        }
-
-        /* Check against unimplemented/unmapped addresses: */
-        if ((newbrk - oldbrk) > RGN_MAP_LIMIT || REGION_OFFSET(newbrk) > RGN_MAP_LIMIT)
-                goto out;
-
-        /* Check against rlimit.. */
-        rlim = current->signal->rlim[RLIMIT_DATA].rlim_cur;
-        if (rlim < RLIM_INFINITY && brk - mm->start_data > rlim)
-                goto out;
-
-        /* Check against existing mmap mappings. */
-        if (find_vma_intersection(mm, oldbrk, newbrk+PAGE_SIZE))
-                goto out;
-
-        /* Ok, looks good - let it rip. */
-        if (do_brk(oldbrk, newbrk-oldbrk) != oldbrk)
-                goto out;
-set_brk:
-        mm->brk = brk;
-out:
-        retval = mm->brk;
-        up_write(&mm->mmap_sem);
+        unsigned long retval = sys_brk(brk);
         force_successful_syscall_return();
         return retval;
 }
@@ -185,39 +141,6 @@ int ia64_mmap_check(unsigned long addr, unsigned long len,
         return 0;
 }
 
-static inline unsigned long
-do_mmap2 (unsigned long addr, unsigned long len, int prot, int flags, int fd, unsigned long pgoff)
-{
-        struct file *file = NULL;
-
-        flags &= ~(MAP_EXECUTABLE | MAP_DENYWRITE);
-        if (!(flags & MAP_ANONYMOUS)) {
-                file = fget(fd);
-                if (!file)
-                        return -EBADF;
-
-                if (!file->f_op || !file->f_op->mmap) {
-                        addr = -ENODEV;
-                        goto out;
-                }
-        }
-
-        /* Careful about overflows.. */
-        len = PAGE_ALIGN(len);
-        if (!len || len > TASK_SIZE) {
-                addr = -EINVAL;
-                goto out;
-        }
-
-        down_write(&current->mm->mmap_sem);
-        addr = do_mmap_pgoff(file, addr, len, prot, flags, pgoff);
-        up_write(&current->mm->mmap_sem);
-
-out:    if (file)
-                fput(file);
-        return addr;
-}
-
 /*
  * mmap2() is like mmap() except that the offset is expressed in units
  * of PAGE_SIZE (instead of bytes).  This allows to mmap2() (pieces
@@ -226,7 +149,7 @@ out:	if (file)
 asmlinkage unsigned long
 sys_mmap2 (unsigned long addr, unsigned long len, int prot, int flags, int fd, long pgoff)
 {
-        addr = do_mmap2(addr, len, prot, flags, fd, pgoff);
+        addr = sys_mmap_pgoff(addr, len, prot, flags, fd, pgoff);
         if (!IS_ERR((void *) addr))
                 force_successful_syscall_return();
         return addr;
@@ -238,7 +161,7 @@ sys_mmap (unsigned long addr, unsigned long len, int prot, int flags, int fd, lo
         if (offset_in_page(off) != 0)
                 return -EINVAL;
 
-        addr = do_mmap2(addr, len, prot, flags, fd, off >> PAGE_SHIFT);
+        addr = sys_mmap_pgoff(addr, len, prot, flags, fd, off >> PAGE_SHIFT);
         if (!IS_ERR((void *) addr))
                 force_successful_syscall_return();
         return addr;
diff --git a/arch/ia64/kernel/vmlinux.lds.S b/arch/ia64/kernel/vmlinux.lds.S
index 0a0c77b2c988..1295ba327f6f 100644
--- a/arch/ia64/kernel/vmlinux.lds.S
+++ b/arch/ia64/kernel/vmlinux.lds.S
@@ -166,6 +166,12 @@ SECTIONS
         }
 #endif
 
+#ifdef  CONFIG_SMP
+  . = ALIGN(PERCPU_PAGE_SIZE);
+  __cpu0_per_cpu = .;
+  . = . + PERCPU_PAGE_SIZE;     /* cpu0 per-cpu space */
+#endif
+
   . = ALIGN(PAGE_SIZE);
   __init_end = .;
 
@@ -198,11 +204,6 @@ SECTIONS
   data : { } :data
   .data : AT(ADDR(.data) - LOAD_OFFSET)
         {
-#ifdef  CONFIG_SMP
-  . = ALIGN(PERCPU_PAGE_SIZE);
-                __cpu0_per_cpu = .;
-  . = . + PERCPU_PAGE_SIZE;     /* cpu0 per-cpu space */
-#endif
                 INIT_TASK_DATA(PAGE_SIZE)
                 CACHELINE_ALIGNED_DATA(SMP_CACHE_BYTES)
                 READ_MOSTLY_DATA(SMP_CACHE_BYTES)
diff --git a/arch/ia64/kvm/asm-offsets.c b/arch/ia64/kvm/asm-offsets.c
index 0c3564a7a033..9324c875caf5 100644
--- a/arch/ia64/kvm/asm-offsets.c
+++ b/arch/ia64/kvm/asm-offsets.c
@@ -22,7 +22,6 @@
  *
  */
 
-#include <linux/autoconf.h>
 #include <linux/kvm_host.h>
 #include <linux/kbuild.h>
 
diff --git a/arch/ia64/mm/contig.c b/arch/ia64/mm/contig.c
index 2f724d2bf299..54bf54059811 100644
--- a/arch/ia64/mm/contig.c
+++ b/arch/ia64/mm/contig.c
@@ -154,38 +154,99 @@ static void *cpu_data;
 void * __cpuinit
 per_cpu_init (void)
 {
-        int cpu;
-        static int first_time=1;
+        static bool first_time = true;
+        void *cpu0_data = __cpu0_per_cpu;
+        unsigned int cpu;
+
+        if (!first_time)
+                goto skip;
+        first_time = false;
 
         /*
-         * get_free_pages() cannot be used before cpu_init() done.  BSP
-         * allocates "NR_CPUS" pages for all CPUs to avoid that AP calls
-         * get_zeroed_page().
+         * get_free_pages() cannot be used before cpu_init() done.
+         * BSP allocates PERCPU_PAGE_SIZE bytes for all possible CPUs
+         * to avoid that AP calls get_zeroed_page().
          */
-        if (first_time) {
-                void *cpu0_data = __cpu0_per_cpu;
+        for_each_possible_cpu(cpu) {
+                void *src = cpu == 0 ? cpu0_data : __phys_per_cpu_start;
 
-                first_time=0;
+                memcpy(cpu_data, src, __per_cpu_end - __per_cpu_start);
+                __per_cpu_offset[cpu] = (char *)cpu_data - __per_cpu_start;
+                per_cpu(local_per_cpu_offset, cpu) = __per_cpu_offset[cpu];
 
-                __per_cpu_offset[0] = (char *) cpu0_data - __per_cpu_start;
-                per_cpu(local_per_cpu_offset, 0) = __per_cpu_offset[0];
+                /*
+                 * percpu area for cpu0 is moved from the __init area
+                 * which is setup by head.S and used till this point.
+                 * Update ar.k3.  This move is ensures that percpu
+                 * area for cpu0 is on the correct node and its
+                 * virtual address isn't insanely far from other
+                 * percpu areas which is important for congruent
+                 * percpu allocator.
+                 */
+                if (cpu == 0)
+                        ia64_set_kr(IA64_KR_PER_CPU_DATA, __pa(cpu_data) -
+                                    (unsigned long)__per_cpu_start);
 
-                for (cpu = 1; cpu < NR_CPUS; cpu++) {
-                        memcpy(cpu_data, __phys_per_cpu_start, __per_cpu_end - __per_cpu_start);
-                        __per_cpu_offset[cpu] = (char *) cpu_data - __per_cpu_start;
-                        cpu_data += PERCPU_PAGE_SIZE;
-                        per_cpu(local_per_cpu_offset, cpu) = __per_cpu_offset[cpu];
-                }
+                cpu_data += PERCPU_PAGE_SIZE;
         }
+skip:
         return __per_cpu_start + __per_cpu_offset[smp_processor_id()];
 }
 
 static inline void
 alloc_per_cpu_data(void)
 {
-        cpu_data = __alloc_bootmem(PERCPU_PAGE_SIZE * NR_CPUS-1,
+        cpu_data = __alloc_bootmem(PERCPU_PAGE_SIZE * num_possible_cpus(),
                                    PERCPU_PAGE_SIZE, __pa(MAX_DMA_ADDRESS));
 }
+
+/**
+ * setup_per_cpu_areas - setup percpu areas
+ *
+ * Arch code has already allocated and initialized percpu areas.  All
+ * this function has to do is to teach the determined layout to the
+ * dynamic percpu allocator, which happens to be more complex than
+ * creating whole new ones using helpers.
+ */
+void __init
+setup_per_cpu_areas(void)
+{
+        struct pcpu_alloc_info *ai;
+        struct pcpu_group_info *gi;
+        unsigned int cpu;
+        ssize_t static_size, reserved_size, dyn_size;
+        int rc;
+
+        ai = pcpu_alloc_alloc_info(1, num_possible_cpus());
+        if (!ai)
+                panic("failed to allocate pcpu_alloc_info");
+        gi = &ai->groups[0];
+
+        /* units are assigned consecutively to possible cpus */
+        for_each_possible_cpu(cpu)
+                gi->cpu_map[gi->nr_units++] = cpu;
+
+        /* set parameters */
+        static_size = __per_cpu_end - __per_cpu_start;
+        reserved_size = PERCPU_MODULE_RESERVE;
+        dyn_size = PERCPU_PAGE_SIZE - static_size - reserved_size;
+        if (dyn_size < 0)
+                panic("percpu area overflow static=%zd reserved=%zd\n",
+                      static_size, reserved_size);
+
+        ai->static_size         = static_size;
+        ai->reserved_size       = reserved_size;
+        ai->dyn_size            = dyn_size;
+        ai->unit_size           = PERCPU_PAGE_SIZE;
+        ai->atom_size           = PAGE_SIZE;
+        ai->alloc_size          = PERCPU_PAGE_SIZE;
+
+        rc = pcpu_setup_first_chunk(ai, __per_cpu_start + __per_cpu_offset[0]);
+        if (rc)
+                panic("failed to setup percpu area (err=%d)", rc);
+
+        pcpu_free_alloc_info(ai);
+}
 #else
 #define alloc_per_cpu_data() do { } while (0)
 #endif /* CONFIG_SMP */
@@ -270,8 +331,8 @@ paging_init (void)
 
                 map_size = PAGE_ALIGN(ALIGN(max_low_pfn, MAX_ORDER_NR_PAGES) *
                         sizeof(struct page));
-                vmalloc_end -= map_size;
-                vmem_map = (struct page *) vmalloc_end;
+                VMALLOC_END -= map_size;
+                vmem_map = (struct page *) VMALLOC_END;
                 efi_memmap_walk(create_mem_map_page_table, NULL);
 
                 /*
diff --git a/arch/ia64/mm/discontig.c b/arch/ia64/mm/discontig.c
index d85ba98d9008..19c4b2195dce 100644
--- a/arch/ia64/mm/discontig.c
+++ b/arch/ia64/mm/discontig.c
@@ -143,22 +143,120 @@ static void *per_cpu_node_setup(void *cpu_data, int node)
         int cpu;
 
         for_each_possible_early_cpu(cpu) {
-                if (cpu == 0) {
-                        void *cpu0_data = __cpu0_per_cpu;
-                        __per_cpu_offset[cpu] = (char*)cpu0_data -
-                                __per_cpu_start;
-                } else if (node == node_cpuid[cpu].nid) {
-                        memcpy(__va(cpu_data), __phys_per_cpu_start,
-                               __per_cpu_end - __per_cpu_start);
-                        __per_cpu_offset[cpu] = (char*)__va(cpu_data) -
-                                __per_cpu_start;
-                        cpu_data += PERCPU_PAGE_SIZE;
-                }
+                void *src = cpu == 0 ? __cpu0_per_cpu : __phys_per_cpu_start;
+
+                if (node != node_cpuid[cpu].nid)
+                        continue;
+
+                memcpy(__va(cpu_data), src, __per_cpu_end - __per_cpu_start);
+                __per_cpu_offset[cpu] = (char *)__va(cpu_data) -
+                        __per_cpu_start;
+
+                /*
+                 * percpu area for cpu0 is moved from the __init area
+                 * which is setup by head.S and used till this point.
+                 * Update ar.k3.  This move is ensures that percpu
+                 * area for cpu0 is on the correct node and its
+                 * virtual address isn't insanely far from other
+                 * percpu areas which is important for congruent
+                 * percpu allocator.
+                 */
+                if (cpu == 0)
+                        ia64_set_kr(IA64_KR_PER_CPU_DATA,
+                                    (unsigned long)cpu_data -
+                                    (unsigned long)__per_cpu_start);
+
+                cpu_data += PERCPU_PAGE_SIZE;
         }
 #endif
         return cpu_data;
 }
 
+#ifdef CONFIG_SMP
+/**
+ * setup_per_cpu_areas - setup percpu areas
+ *
+ * Arch code has already allocated and initialized percpu areas.  All
+ * this function has to do is to teach the determined layout to the
+ * dynamic percpu allocator, which happens to be more complex than
+ * creating whole new ones using helpers.
+ */
+void __init setup_per_cpu_areas(void)
+{
+        struct pcpu_alloc_info *ai;
+        struct pcpu_group_info *uninitialized_var(gi);
+        unsigned int *cpu_map;
+        void *base;
+        unsigned long base_offset;
+        unsigned int cpu;
+        ssize_t static_size, reserved_size, dyn_size;
+        int node, prev_node, unit, nr_units, rc;
+
+        ai = pcpu_alloc_alloc_info(MAX_NUMNODES, nr_cpu_ids);
+        if (!ai)
+                panic("failed to allocate pcpu_alloc_info");
+        cpu_map = ai->groups[0].cpu_map;
+
+        /* determine base */
+        base = (void *)ULONG_MAX;
+        for_each_possible_cpu(cpu)
+                base = min(base,
+                           (void *)(__per_cpu_offset[cpu] + __per_cpu_start));
+        base_offset = (void *)__per_cpu_start - base;
+
+        /* build cpu_map, units are grouped by node */
+        unit = 0;
+        for_each_node(node)
+                for_each_possible_cpu(cpu)
+                        if (node == node_cpuid[cpu].nid)
+                                cpu_map[unit++] = cpu;
+        nr_units = unit;
+
+        /* set basic parameters */
+        static_size = __per_cpu_end - __per_cpu_start;
+        reserved_size = PERCPU_MODULE_RESERVE;
+        dyn_size = PERCPU_PAGE_SIZE - static_size - reserved_size;
+        if (dyn_size < 0)
+                panic("percpu area overflow static=%zd reserved=%zd\n",
+                      static_size, reserved_size);
+
+        ai->static_size         = static_size;
+        ai->reserved_size       = reserved_size;
+        ai->dyn_size            = dyn_size;
+        ai->unit_size           = PERCPU_PAGE_SIZE;
+        ai->atom_size           = PAGE_SIZE;
+        ai->alloc_size          = PERCPU_PAGE_SIZE;
+
+        /*
+         * CPUs are put into groups according to node.  Walk cpu_map
+         * and create new groups at node boundaries.
+         */
+        prev_node = -1;
+        ai->nr_groups = 0;
+        for (unit = 0; unit < nr_units; unit++) {
+                cpu = cpu_map[unit];
+                node = node_cpuid[cpu].nid;
+
+                if (node == prev_node) {
+                        gi->nr_units++;
+                        continue;
+                }
+                prev_node = node;
+
+                gi = &ai->groups[ai->nr_groups++];
+                gi->nr_units            = 1;
+                gi->base_offset         = __per_cpu_offset[cpu] + base_offset;
+                gi->cpu_map             = &cpu_map[unit];
+        }
+
+        rc = pcpu_setup_first_chunk(ai, base);
+        if (rc)
+                panic("failed to setup percpu area (err=%d)", rc);
+
+        pcpu_free_alloc_info(ai);
+}
+#endif
+
 /**
  * fill_pernode - initialize pernode data.
  * @node: the node id.
@@ -352,7 +450,8 @@ static void __init initialize_pernode_data(void)
         /* Set the node_data pointer for each per-cpu struct */
         for_each_possible_early_cpu(cpu) {
                 node = node_cpuid[cpu].nid;
-                per_cpu(cpu_info, cpu).node_data = mem_data[node].node_data;
+                per_cpu(ia64_cpu_info, cpu).node_data =
+                        mem_data[node].node_data;
         }
 #else
         {
@@ -360,7 +459,7 @@ static void __init initialize_pernode_data(void)
                 cpu = 0;
                 node = node_cpuid[cpu].nid;
                 cpu0_cpu_info = (struct cpuinfo_ia64 *)(__phys_per_cpu_start +
-                        ((char *)&per_cpu__cpu_info - __per_cpu_start));
+                        ((char *)&per_cpu__ia64_cpu_info - __per_cpu_start));
                 cpu0_cpu_info->node_data = mem_data[node].node_data;
         }
 #endif /* CONFIG_SMP */
@@ -666,9 +765,9 @@ void __init paging_init(void)
         sparse_init();
 
 #ifdef CONFIG_VIRTUAL_MEM_MAP
-        vmalloc_end -= PAGE_ALIGN(ALIGN(max_low_pfn, MAX_ORDER_NR_PAGES) *
+        VMALLOC_END -= PAGE_ALIGN(ALIGN(max_low_pfn, MAX_ORDER_NR_PAGES) *
                 sizeof(struct page));
-        vmem_map = (struct page *) vmalloc_end;
+        vmem_map = (struct page *) VMALLOC_END;
         efi_memmap_walk(create_mem_map_page_table, NULL);
         printk("Virtual mem_map starts at 0x%p\n", vmem_map);
 #endif
diff --git a/arch/ia64/mm/init.c b/arch/ia64/mm/init.c
index 1857766a63c1..b9609c69343a 100644
--- a/arch/ia64/mm/init.c
+++ b/arch/ia64/mm/init.c
@@ -44,8 +44,8 @@ extern void ia64_tlb_init (void);
 unsigned long MAX_DMA_ADDRESS = PAGE_OFFSET + 0x100000000UL;
 
 #ifdef CONFIG_VIRTUAL_MEM_MAP
-unsigned long vmalloc_end = VMALLOC_END_INIT;
-EXPORT_SYMBOL(vmalloc_end);
+unsigned long VMALLOC_END = VMALLOC_END_INIT;
+EXPORT_SYMBOL(VMALLOC_END);
 struct page *vmem_map;
 EXPORT_SYMBOL(vmem_map);
 #endif
diff --git a/arch/ia64/mm/ioremap.c b/arch/ia64/mm/ioremap.c
index 2a140627dfd6..3dccdd8eb275 100644
--- a/arch/ia64/mm/ioremap.c
+++ b/arch/ia64/mm/ioremap.c
@@ -22,6 +22,12 @@ __ioremap (unsigned long phys_addr)
 }
 
 void __iomem *
+early_ioremap (unsigned long phys_addr, unsigned long size)
+{
+        return __ioremap(phys_addr);
+}
+
+void __iomem *
 ioremap (unsigned long phys_addr, unsigned long size)
 {
         void __iomem *addr;
@@ -102,6 +108,11 @@ ioremap_nocache (unsigned long phys_addr, unsigned long size)
 EXPORT_SYMBOL(ioremap_nocache);
 
 void
+early_iounmap (volatile void __iomem *addr, unsigned long size)
+{
+}
+
+void
 iounmap (volatile void __iomem *addr)
 {
         if (REGION_NUMBER(addr) == RGN_GATE)
diff --git a/arch/ia64/pci/pci.c b/arch/ia64/pci/pci.c
index c0fca2c1c858..df639db779f9 100644
--- a/arch/ia64/pci/pci.c
+++ b/arch/ia64/pci/pci.c
@@ -131,6 +131,7 @@ alloc_pci_controller (int seg)
 }
 
 struct pci_root_info {
+        struct acpi_device *bridge;
         struct pci_controller *controller;
         char *name;
 };
@@ -297,9 +298,20 @@ static __devinit acpi_status add_window(struct acpi_resource *res, void *data)
         window->offset = offset;
 
         if (insert_resource(root, &window->resource)) {
-                printk(KERN_ERR "alloc 0x%llx-0x%llx from %s for %s failed\n",
-                        window->resource.start, window->resource.end,
-                        root->name, info->name);
+                dev_err(&info->bridge->dev,
+                        "can't allocate host bridge window %pR\n",
+                        &window->resource);
+        } else {
+                if (offset)
+                        dev_info(&info->bridge->dev, "host bridge window %pR "
+                                 "(PCI address [%#llx-%#llx])\n",
+                                 &window->resource,
+                                 window->resource.start - offset,
+                                 window->resource.end - offset);
+                else
+                        dev_info(&info->bridge->dev,
+                                 "host bridge window %pR\n",
+                                 &window->resource);
         }
 
         return AE_OK;
@@ -319,8 +331,9 @@ pcibios_setup_root_windows(struct pci_bus *bus, struct pci_controller *ctrl)
                     (res->end - res->start < 16))
                         continue;
                 if (j >= PCI_BUS_NUM_RESOURCES) {
-                        printk("Ignoring range [%#llx-%#llx] (%lx)\n",
-                                        res->start, res->end, res->flags);
+                        dev_warn(&bus->dev,
+                                 "ignoring host bridge window %pR (no space)\n",
+                                 res);
                         continue;
                 }
                 bus->resource[j++] = res;
@@ -364,6 +377,7 @@ pci_acpi_scan_root(struct acpi_device *device, int domain, int bus)
                         goto out3;
 
                 sprintf(name, "PCI Bus %04x:%02x", domain, bus);
+                info.bridge = device;
                 info.controller = controller;
                 info.name = name;
                 acpi_walk_resources(device->handle, METHOD_NAME__CRS,
@@ -720,9 +734,6 @@ int ia64_pci_legacy_write(struct pci_bus *bus, u16 port, u32 val, u8 size)
         return ret;
 }
 
-/* It's defined in drivers/pci/pci.c */
-extern u8 pci_cache_line_size;
-
 /**
  * set_pci_cacheline_size - determine cacheline size for PCI devices
  *
@@ -731,7 +742,7 @@ extern u8 pci_cache_line_size;
  *
  * Code mostly taken from arch/ia64/kernel/palinfo.c:cache_info().
  */
-static void __init set_pci_cacheline_size(void)
+static void __init set_pci_dfl_cacheline_size(void)
 {
         unsigned long levels, unique_caches;
         long status;
@@ -751,7 +762,7 @@ static void __init set_pci_cacheline_size(void)
                         "(status=%ld)\n", __func__, status);
                 return;
         }
-        pci_cache_line_size = (1 << cci.pcci_line_size) / 4;
+        pci_dfl_cache_line_size = (1 << cci.pcci_line_size) / 4;
 }
 
 u64 ia64_dma_get_required_mask(struct device *dev)
@@ -782,7 +793,7 @@ EXPORT_SYMBOL_GPL(dma_get_required_mask);
 
 static int __init pcibios_init(void)
 {
-        set_pci_cacheline_size();
+        set_pci_dfl_cacheline_size();
         return 0;
 }
 
diff --git a/arch/ia64/sn/kernel/sn2/sn2_smp.c b/arch/ia64/sn/kernel/sn2/sn2_smp.c
index 1176506b2bae..e884ba4e031d 100644
--- a/arch/ia64/sn/kernel/sn2/sn2_smp.c
+++ b/arch/ia64/sn/kernel/sn2/sn2_smp.c
@@ -496,13 +496,13 @@ static int sn2_ptc_seq_show(struct seq_file *file, void *data)
                 seq_printf(file, "cpu %d %ld %ld %ld %ld %ld %ld %ld %ld %ld %ld %ld %ld\n", cpu, stat->ptc_l,
                                 stat->change_rid, stat->shub_ptc_flushes, stat->nodes_flushed,
                                 stat->deadlocks,
-                                1000 * stat->lock_itc_clocks / per_cpu(cpu_info, cpu).cyc_per_usec,
-                                1000 * stat->shub_itc_clocks / per_cpu(cpu_info, cpu).cyc_per_usec,
-                                1000 * stat->shub_itc_clocks_max / per_cpu(cpu_info, cpu).cyc_per_usec,
+                                1000 * stat->lock_itc_clocks / per_cpu(ia64_cpu_info, cpu).cyc_per_usec,
+                                1000 * stat->shub_itc_clocks / per_cpu(ia64_cpu_info, cpu).cyc_per_usec,
+                                1000 * stat->shub_itc_clocks_max / per_cpu(ia64_cpu_info, cpu).cyc_per_usec,
                                 stat->shub_ptc_flushes_not_my_mm,
                                 stat->deadlocks2,
                                 stat->shub_ipi_flushes,
-                                1000 * stat->shub_ipi_flushes_itc_clocks / per_cpu(cpu_info, cpu).cyc_per_usec);
+                                1000 * stat->shub_ipi_flushes_itc_clocks / per_cpu(ia64_cpu_info, cpu).cyc_per_usec);
         }
         return 0;
 }
diff --git a/arch/ia64/sn/pci/tioca_provider.c b/arch/ia64/sn/pci/tioca_provider.c
index 35b2a27d2e77..efb454534e52 100644
--- a/arch/ia64/sn/pci/tioca_provider.c
+++ b/arch/ia64/sn/pci/tioca_provider.c
@@ -9,6 +9,7 @@
 #include <linux/types.h>
 #include <linux/interrupt.h>
 #include <linux/pci.h>
+#include <linux/bitmap.h>
 #include <asm/sn/sn_sal.h>
 #include <asm/sn/addrs.h>
 #include <asm/sn/io.h>
@@ -369,7 +370,7 @@ tioca_dma_d48(struct pci_dev *pdev, u64 paddr)
 static dma_addr_t
 tioca_dma_mapped(struct pci_dev *pdev, unsigned long paddr, size_t req_size)
 {
-        int i, ps, ps_shift, entry, entries, mapsize, last_entry;
+        int ps, ps_shift, entry, entries, mapsize;
         u64 xio_addr, end_xio_addr;
         struct tioca_common *tioca_common;
         struct tioca_kernel *tioca_kern;
@@ -410,23 +411,13 @@ tioca_dma_mapped(struct pci_dev *pdev, unsigned long paddr, size_t req_size)
         map = tioca_kern->ca_pcigart_pagemap;
         mapsize = tioca_kern->ca_pcigart_entries;
 
-        entry = find_first_zero_bit(map, mapsize);
-        while (entry < mapsize) {
-                last_entry = find_next_bit(map, mapsize, entry);
-
-                if (last_entry - entry >= entries)
-                        break;
-
-                entry = find_next_zero_bit(map, mapsize, last_entry);
-        }
-
-        if (entry > mapsize) {
+        entry = bitmap_find_next_zero_area(map, mapsize, 0, entries, 0);
+        if (entry >= mapsize) {
                 kfree(ca_dmamap);
                 goto map_return;
         }
 
-        for (i = 0; i < entries; i++)
-                set_bit(entry + i, map);
+        bitmap_set(map, entry, entries);
 
         bus_addr = tioca_kern->ca_pciap_base + (entry * ps);
 
diff --git a/arch/ia64/xen/irq_xen.c b/arch/ia64/xen/irq_xen.c
index f042e192d2fe..a3fb7cf9ae1d 100644
--- a/arch/ia64/xen/irq_xen.c
+++ b/arch/ia64/xen/irq_xen.c
@@ -63,19 +63,19 @@ xen_free_irq_vector(int vector)
 }
 
 
-static DEFINE_PER_CPU(int, timer_irq) = -1;
-static DEFINE_PER_CPU(int, ipi_irq) = -1;
-static DEFINE_PER_CPU(int, resched_irq) = -1;
-static DEFINE_PER_CPU(int, cmc_irq) = -1;
-static DEFINE_PER_CPU(int, cmcp_irq) = -1;
-static DEFINE_PER_CPU(int, cpep_irq) = -1;
+static DEFINE_PER_CPU(int, xen_timer_irq) = -1;
+static DEFINE_PER_CPU(int, xen_ipi_irq) = -1;
+static DEFINE_PER_CPU(int, xen_resched_irq) = -1;
+static DEFINE_PER_CPU(int, xen_cmc_irq) = -1;
+static DEFINE_PER_CPU(int, xen_cmcp_irq) = -1;
+static DEFINE_PER_CPU(int, xen_cpep_irq) = -1;
 #define NAME_SIZE       15
-static DEFINE_PER_CPU(char[NAME_SIZE], timer_name);
-static DEFINE_PER_CPU(char[NAME_SIZE], ipi_name);
-static DEFINE_PER_CPU(char[NAME_SIZE], resched_name);
-static DEFINE_PER_CPU(char[NAME_SIZE], cmc_name);
-static DEFINE_PER_CPU(char[NAME_SIZE], cmcp_name);
-static DEFINE_PER_CPU(char[NAME_SIZE], cpep_name);
+static DEFINE_PER_CPU(char[NAME_SIZE], xen_timer_name);
+static DEFINE_PER_CPU(char[NAME_SIZE], xen_ipi_name);
+static DEFINE_PER_CPU(char[NAME_SIZE], xen_resched_name);
+static DEFINE_PER_CPU(char[NAME_SIZE], xen_cmc_name);
+static DEFINE_PER_CPU(char[NAME_SIZE], xen_cmcp_name);
+static DEFINE_PER_CPU(char[NAME_SIZE], xen_cpep_name);
 #undef NAME_SIZE
 
 struct saved_irq {
@@ -144,64 +144,64 @@ __xen_register_percpu_irq(unsigned int cpu, unsigned int vec,
         if (xen_slab_ready) {
                 switch (vec) {
                 case IA64_TIMER_VECTOR:
-                        snprintf(per_cpu(timer_name, cpu),
-                                 sizeof(per_cpu(timer_name, cpu)),
+                        snprintf(per_cpu(xen_timer_name, cpu),
+                                 sizeof(per_cpu(xen_timer_name, cpu)),
                                  "%s%d", action->name, cpu);
                         irq = bind_virq_to_irqhandler(VIRQ_ITC, cpu,
                                 action->handler, action->flags,
-                                per_cpu(timer_name, cpu), action->dev_id);
-                        per_cpu(timer_irq, cpu) = irq;
+                                per_cpu(xen_timer_name, cpu), action->dev_id);
+                        per_cpu(xen_timer_irq, cpu) = irq;
                         break;
                 case IA64_IPI_RESCHEDULE:
-                        snprintf(per_cpu(resched_name, cpu),
-                                 sizeof(per_cpu(resched_name, cpu)),
+                        snprintf(per_cpu(xen_resched_name, cpu),
+                                 sizeof(per_cpu(xen_resched_name, cpu)),
                                  "%s%d", action->name, cpu);
                         irq = bind_ipi_to_irqhandler(XEN_RESCHEDULE_VECTOR, cpu,
                                 action->handler, action->flags,
-                                per_cpu(resched_name, cpu), action->dev_id);
-                        per_cpu(resched_irq, cpu) = irq;
+                                per_cpu(xen_resched_name, cpu), action->dev_id);
+                        per_cpu(xen_resched_irq, cpu) = irq;
                         break;
                 case IA64_IPI_VECTOR:
-                        snprintf(per_cpu(ipi_name, cpu),
-                                 sizeof(per_cpu(ipi_name, cpu)),
+                        snprintf(per_cpu(xen_ipi_name, cpu),
+                                 sizeof(per_cpu(xen_ipi_name, cpu)),
                                  "%s%d", action->name, cpu);
                         irq = bind_ipi_to_irqhandler(XEN_IPI_VECTOR, cpu,
                                 action->handler, action->flags,
-                                per_cpu(ipi_name, cpu), action->dev_id);
-                        per_cpu(ipi_irq, cpu) = irq;
+                                per_cpu(xen_ipi_name, cpu), action->dev_id);
+                        per_cpu(xen_ipi_irq, cpu) = irq;
                         break;
                 case IA64_CMC_VECTOR:
-                        snprintf(per_cpu(cmc_name, cpu),
-                                 sizeof(per_cpu(cmc_name, cpu)),
+                        snprintf(per_cpu(xen_cmc_name, cpu),
+                                 sizeof(per_cpu(xen_cmc_name, cpu)),
                                  "%s%d", action->name, cpu);
                         irq = bind_virq_to_irqhandler(VIRQ_MCA_CMC, cpu,
-                                                      action->handler,
-                                                      action->flags,
-                                                      per_cpu(cmc_name, cpu),
-                                                      action->dev_id);
-                        per_cpu(cmc_irq, cpu) = irq;
+                                                action->handler,
+                                                action->flags,
+                                                per_cpu(xen_cmc_name, cpu),
+                                                action->dev_id);
+                        per_cpu(xen_cmc_irq, cpu) = irq;
                         break;
                 case IA64_CMCP_VECTOR:
-                        snprintf(per_cpu(cmcp_name, cpu),
-                                 sizeof(per_cpu(cmcp_name, cpu)),
+                        snprintf(per_cpu(xen_cmcp_name, cpu),
+                                 sizeof(per_cpu(xen_cmcp_name, cpu)),
                                  "%s%d", action->name, cpu);
                         irq = bind_ipi_to_irqhandler(XEN_CMCP_VECTOR, cpu,
-                                                     action->handler,
-                                                     action->flags,
-                                                     per_cpu(cmcp_name, cpu),
-                                                     action->dev_id);
-                        per_cpu(cmcp_irq, cpu) = irq;
+                                                action->handler,
+                                                action->flags,
+                                                per_cpu(xen_cmcp_name, cpu),
+                                                action->dev_id);
+                        per_cpu(xen_cmcp_irq, cpu) = irq;
                         break;
                 case IA64_CPEP_VECTOR:
-                        snprintf(per_cpu(cpep_name, cpu),
-                                 sizeof(per_cpu(cpep_name, cpu)),
+                        snprintf(per_cpu(xen_cpep_name, cpu),
+                                 sizeof(per_cpu(xen_cpep_name, cpu)),
                                  "%s%d", action->name, cpu);
                         irq = bind_ipi_to_irqhandler(XEN_CPEP_VECTOR, cpu,
-                                                     action->handler,
-                                                     action->flags,
-                                                     per_cpu(cpep_name, cpu),
-                                                     action->dev_id);
-                        per_cpu(cpep_irq, cpu) = irq;
+                                                action->handler,
+                                                action->flags,
+                                                per_cpu(xen_cpep_name, cpu),
+                                                action->dev_id);
+                        per_cpu(xen_cpep_irq, cpu) = irq;
                         break;
                 case IA64_CPE_VECTOR:
                 case IA64_MCA_RENDEZ_VECTOR:
@@ -275,30 +275,33 @@ unbind_evtchn_callback(struct notifier_block *nfb,
 
         if (action == CPU_DEAD) {
                 /* Unregister evtchn.  */
-                if (per_cpu(cpep_irq, cpu) >= 0) {
-                        unbind_from_irqhandler(per_cpu(cpep_irq, cpu), NULL);
-                        per_cpu(cpep_irq, cpu) = -1;
+                if (per_cpu(xen_cpep_irq, cpu) >= 0) {
+                        unbind_from_irqhandler(per_cpu(xen_cpep_irq, cpu),
+                                               NULL);
+                        per_cpu(xen_cpep_irq, cpu) = -1;
                 }
-                if (per_cpu(cmcp_irq, cpu) >= 0) {
-                        unbind_from_irqhandler(per_cpu(cmcp_irq, cpu), NULL);
-                        per_cpu(cmcp_irq, cpu) = -1;
+                if (per_cpu(xen_cmcp_irq, cpu) >= 0) {
+                        unbind_from_irqhandler(per_cpu(xen_cmcp_irq, cpu),
+                                               NULL);
+                        per_cpu(xen_cmcp_irq, cpu) = -1;
                 }
-                if (per_cpu(cmc_irq, cpu) >= 0) {
-                        unbind_from_irqhandler(per_cpu(cmc_irq, cpu), NULL);
-                        per_cpu(cmc_irq, cpu) = -1;
+                if (per_cpu(xen_cmc_irq, cpu) >= 0) {
+                        unbind_from_irqhandler(per_cpu(xen_cmc_irq, cpu), NULL);
+                        per_cpu(xen_cmc_irq, cpu) = -1;
                 }
-                if (per_cpu(ipi_irq, cpu) >= 0) {
-                        unbind_from_irqhandler(per_cpu(ipi_irq, cpu), NULL);
-                        per_cpu(ipi_irq, cpu) = -1;
+                if (per_cpu(xen_ipi_irq, cpu) >= 0) {
+                        unbind_from_irqhandler(per_cpu(xen_ipi_irq, cpu), NULL);
+                        per_cpu(xen_ipi_irq, cpu) = -1;
                 }
-                if (per_cpu(resched_irq, cpu) >= 0) {
-                        unbind_from_irqhandler(per_cpu(resched_irq, cpu),
-                                                NULL);
-                        per_cpu(resched_irq, cpu) = -1;
+                if (per_cpu(xen_resched_irq, cpu) >= 0) {
+                        unbind_from_irqhandler(per_cpu(xen_resched_irq, cpu),
+                                               NULL);
+                        per_cpu(xen_resched_irq, cpu) = -1;
                 }
-                if (per_cpu(timer_irq, cpu) >= 0) {
-                        unbind_from_irqhandler(per_cpu(timer_irq, cpu), NULL);
-                        per_cpu(timer_irq, cpu) = -1;
+                if (per_cpu(xen_timer_irq, cpu) >= 0) {
+                        unbind_from_irqhandler(per_cpu(xen_timer_irq, cpu),
+                                               NULL);
+                        per_cpu(xen_timer_irq, cpu) = -1;
                 }
         }
         return NOTIFY_OK;
diff --git a/arch/ia64/xen/time.c b/arch/ia64/xen/time.c
index dbeadb9c8e20..c1c544513e8d 100644
--- a/arch/ia64/xen/time.c
+++ b/arch/ia64/xen/time.c
@@ -34,15 +34,15 @@
 
 #include "../kernel/fsyscall_gtod_data.h"
 
-DEFINE_PER_CPU(struct vcpu_runstate_info, runstate);
-DEFINE_PER_CPU(unsigned long, processed_stolen_time);
-DEFINE_PER_CPU(unsigned long, processed_blocked_time);
+static DEFINE_PER_CPU(struct vcpu_runstate_info, xen_runstate);
+static DEFINE_PER_CPU(unsigned long, xen_stolen_time);
+static DEFINE_PER_CPU(unsigned long, xen_blocked_time);
 
 /* taken from i386/kernel/time-xen.c */
 static void xen_init_missing_ticks_accounting(int cpu)
 {
         struct vcpu_register_runstate_memory_area area;
-        struct vcpu_runstate_info *runstate = &per_cpu(runstate, cpu);
+        struct vcpu_runstate_info *runstate = &per_cpu(xen_runstate, cpu);
         int rc;
 
         memset(runstate, 0, sizeof(*runstate));
@@ -52,8 +52,8 @@ static void xen_init_missing_ticks_accounting(int cpu)
                                 &area);
         WARN_ON(rc && rc != -ENOSYS);
 
-        per_cpu(processed_blocked_time, cpu) = runstate->time[RUNSTATE_blocked];
-        per_cpu(processed_stolen_time, cpu) = runstate->time[RUNSTATE_runnable]
+        per_cpu(xen_blocked_time, cpu) = runstate->time[RUNSTATE_blocked];
+        per_cpu(xen_stolen_time, cpu) = runstate->time[RUNSTATE_runnable]
                                             + runstate->time[RUNSTATE_offline];
 }
 
@@ -68,7 +68,7 @@ static void get_runstate_snapshot(struct vcpu_runstate_info *res)
 
         BUG_ON(preemptible());
 
-        state = &__get_cpu_var(runstate);
+        state = &__get_cpu_var(xen_runstate);
 
         /*
          * The runstate info is always updated by the hypervisor on
@@ -103,12 +103,12 @@ consider_steal_time(unsigned long new_itm)
          * This function just checks and reject this effect.
          */
         if (!time_after_eq(runstate.time[RUNSTATE_blocked],
-                           per_cpu(processed_blocked_time, cpu)))
+                           per_cpu(xen_blocked_time, cpu)))
                 blocked = 0;
 
         if (!time_after_eq(runstate.time[RUNSTATE_runnable] +
                            runstate.time[RUNSTATE_offline],
-                           per_cpu(processed_stolen_time, cpu)))
+                           per_cpu(xen_stolen_time, cpu)))
                 stolen = 0;
 
         if (!time_after(delta_itm + new_itm, ia64_get_itc()))
@@ -147,8 +147,8 @@ consider_steal_time(unsigned long new_itm)
                 } else {
                         local_cpu_data->itm_next = delta_itm + new_itm;
                 }
-                per_cpu(processed_stolen_time, cpu) += NS_PER_TICK * stolen;
-                per_cpu(processed_blocked_time, cpu) += NS_PER_TICK * blocked;
+                per_cpu(xen_stolen_time, cpu) += NS_PER_TICK * stolen;
+                per_cpu(xen_blocked_time, cpu) += NS_PER_TICK * blocked;
         }
         return delta_itm;
 }
diff --git a/arch/m32r/include/asm/elf.h b/arch/m32r/include/asm/elf.h
index 0cc34c94bf2b..2f85412ef730 100644
--- a/arch/m32r/include/asm/elf.h
+++ b/arch/m32r/include/asm/elf.h
@@ -102,7 +102,6 @@ typedef elf_fpreg_t elf_fpregset_t;
  */
 #define ELF_PLAT_INIT(_r, load_addr)    (_r)->r0 = 0
 
-#define USE_ELF_CORE_DUMP
 #define ELF_EXEC_PAGESIZE       PAGE_SIZE
 
 /*
diff --git a/arch/m32r/include/asm/spinlock.h b/arch/m32r/include/asm/spinlock.h
index dded923883b2..179a06489b10 100644
--- a/arch/m32r/include/asm/spinlock.h
+++ b/arch/m32r/include/asm/spinlock.h
@@ -24,19 +24,19 @@
  * We make no fairness assumptions. They have a cost.
  */
 
-#define __raw_spin_is_locked(x)         (*(volatile int *)(&(x)->slock) <= 0)
-#define __raw_spin_lock_flags(lock, flags) __raw_spin_lock(lock)
-#define __raw_spin_unlock_wait(x) \
-                do { cpu_relax(); } while (__raw_spin_is_locked(x))
+#define arch_spin_is_locked(x)          (*(volatile int *)(&(x)->slock) <= 0)
+#define arch_spin_lock_flags(lock, flags) arch_spin_lock(lock)
+#define arch_spin_unlock_wait(x) \
+                do { cpu_relax(); } while (arch_spin_is_locked(x))
 
 /**
- * __raw_spin_trylock - Try spin lock and return a result
+ * arch_spin_trylock - Try spin lock and return a result
  * @lock: Pointer to the lock variable
  *
- * __raw_spin_trylock() tries to get the lock and returns a result.
+ * arch_spin_trylock() tries to get the lock and returns a result.
  * On the m32r, the result value is 1 (= Success) or 0 (= Failure).
  */
-static inline int __raw_spin_trylock(raw_spinlock_t *lock)
+static inline int arch_spin_trylock(arch_spinlock_t *lock)
 {
         int oldval;
         unsigned long tmp1, tmp2;
@@ -50,7 +50,7 @@ static inline int __raw_spin_trylock(raw_spinlock_t *lock)
          * }
          */
         __asm__ __volatile__ (
-                "# __raw_spin_trylock           \n\t"
+                "# arch_spin_trylock            \n\t"
                 "ldi    %1, #0;                 \n\t"
                 "mvfc   %2, psw;                \n\t"
                 "clrpsw #0x40 -> nop;           \n\t"
@@ -69,7 +69,7 @@ static inline int __raw_spin_trylock(raw_spinlock_t *lock)
         return (oldval > 0);
 }
 
-static inline void __raw_spin_lock(raw_spinlock_t *lock)
+static inline void arch_spin_lock(arch_spinlock_t *lock)
 {
         unsigned long tmp0, tmp1;
 
@@ -84,7 +84,7 @@ static inline void __raw_spin_lock(raw_spinlock_t *lock)
          * }
          */
         __asm__ __volatile__ (
-                "# __raw_spin_lock              \n\t"
+                "# arch_spin_lock               \n\t"
                 ".fillinsn                      \n"
                 "1:                             \n\t"
                 "mvfc   %1, psw;                \n\t"
@@ -111,7 +111,7 @@ static inline void __raw_spin_lock(raw_spinlock_t *lock)
         );
 }
 
-static inline void __raw_spin_unlock(raw_spinlock_t *lock)
+static inline void arch_spin_unlock(arch_spinlock_t *lock)
 {
         mb();
         lock->slock = 1;
@@ -140,15 +140,15 @@ static inline void __raw_spin_unlock(raw_spinlock_t *lock)
  * read_can_lock - would read_trylock() succeed?
  * @lock: the rwlock in question.
  */
-#define __raw_read_can_lock(x) ((int)(x)->lock > 0)
+#define arch_read_can_lock(x) ((int)(x)->lock > 0)
 
 /**
  * write_can_lock - would write_trylock() succeed?
  * @lock: the rwlock in question.
  */
-#define __raw_write_can_lock(x) ((x)->lock == RW_LOCK_BIAS)
+#define arch_write_can_lock(x) ((x)->lock == RW_LOCK_BIAS)
 
-static inline void __raw_read_lock(raw_rwlock_t *rw)
+static inline void arch_read_lock(arch_rwlock_t *rw)
 {
         unsigned long tmp0, tmp1;
 
@@ -199,7 +199,7 @@ static inline void __raw_read_lock(raw_rwlock_t *rw)
         );
 }
 
-static inline void __raw_write_lock(raw_rwlock_t *rw)
+static inline void arch_write_lock(arch_rwlock_t *rw)
 {
         unsigned long tmp0, tmp1, tmp2;
 
@@ -252,7 +252,7 @@ static inline void __raw_write_lock(raw_rwlock_t *rw)
         );
 }
 
-static inline void __raw_read_unlock(raw_rwlock_t *rw)
+static inline void arch_read_unlock(arch_rwlock_t *rw)
 {
         unsigned long tmp0, tmp1;
 
@@ -274,7 +274,7 @@ static inline void __raw_read_unlock(raw_rwlock_t *rw)
         );
 }
 
-static inline void __raw_write_unlock(raw_rwlock_t *rw)
+static inline void arch_write_unlock(arch_rwlock_t *rw)
 {
         unsigned long tmp0, tmp1, tmp2;
 
@@ -298,7 +298,7 @@ static inline void __raw_write_unlock(raw_rwlock_t *rw)
         );
 }
 
-static inline int __raw_read_trylock(raw_rwlock_t *lock)
+static inline int arch_read_trylock(arch_rwlock_t *lock)
 {
         atomic_t *count = (atomic_t*)lock;
         if (atomic_dec_return(count) >= 0)
@@ -307,7 +307,7 @@ static inline int __raw_read_trylock(raw_rwlock_t *lock)
         return 0;
 }
 
-static inline int __raw_write_trylock(raw_rwlock_t *lock)
+static inline int arch_write_trylock(arch_rwlock_t *lock)
 {
         atomic_t *count = (atomic_t *)lock;
         if (atomic_sub_and_test(RW_LOCK_BIAS, count))
@@ -316,11 +316,11 @@ static inline int __raw_write_trylock(raw_rwlock_t *lock)
         return 0;
 }
 
-#define __raw_read_lock_flags(lock, flags) __raw_read_lock(lock)
-#define __raw_write_lock_flags(lock, flags) __raw_write_lock(lock)
+#define arch_read_lock_flags(lock, flags) arch_read_lock(lock)
+#define arch_write_lock_flags(lock, flags) arch_write_lock(lock)
 
-#define _raw_spin_relax(lock)   cpu_relax()
-#define _raw_read_relax(lock)   cpu_relax()
-#define _raw_write_relax(lock)  cpu_relax()
+#define arch_spin_relax(lock)   cpu_relax()
+#define arch_read_relax(lock)   cpu_relax()
+#define arch_write_relax(lock)  cpu_relax()
 
 #endif  /* _ASM_M32R_SPINLOCK_H */
diff --git a/arch/m32r/include/asm/spinlock_types.h b/arch/m32r/include/asm/spinlock_types.h
index 83f52105c0e4..92e27672661f 100644
--- a/arch/m32r/include/asm/spinlock_types.h
+++ b/arch/m32r/include/asm/spinlock_types.h
@@ -7,17 +7,17 @@
 
 typedef struct {
         volatile int slock;
-} raw_spinlock_t;
+} arch_spinlock_t;
 
-#define __RAW_SPIN_LOCK_UNLOCKED        { 1 }
+#define __ARCH_SPIN_LOCK_UNLOCKED       { 1 }
 
 typedef struct {
         volatile int lock;
-} raw_rwlock_t;
+} arch_rwlock_t;
 
 #define RW_LOCK_BIAS                    0x01000000
 #define RW_LOCK_BIAS_STR                "0x01000000"
 
-#define __RAW_RW_LOCK_UNLOCKED          { RW_LOCK_BIAS }
+#define __ARCH_RW_LOCK_UNLOCKED         { RW_LOCK_BIAS }
 
 #endif /* _ASM_M32R_SPINLOCK_TYPES_H */
diff --git a/arch/m32r/kernel/irq.c b/arch/m32r/kernel/irq.c
index 8dfd31e87c4c..3c71f776872c 100644
--- a/arch/m32r/kernel/irq.c
+++ b/arch/m32r/kernel/irq.c
@@ -40,7 +40,7 @@ int show_interrupts(struct seq_file *p, void *v)
         }
 
         if (i < NR_IRQS) {
-                spin_lock_irqsave(&irq_desc[i].lock, flags);
+                raw_spin_lock_irqsave(&irq_desc[i].lock, flags);
                 action = irq_desc[i].action;
                 if (!action)
                         goto skip;
@@ -59,7 +59,7 @@ int show_interrupts(struct seq_file *p, void *v)
 
                 seq_putc(p, '\n');
 skip:
-                spin_unlock_irqrestore(&irq_desc[i].lock, flags);
+                raw_spin_unlock_irqrestore(&irq_desc[i].lock, flags);
         }
         return 0;
 }
diff --git a/arch/m32r/kernel/sys_m32r.c b/arch/m32r/kernel/sys_m32r.c
index 305ac852bbed..d3c865c5a6ba 100644
--- a/arch/m32r/kernel/sys_m32r.c
+++ b/arch/m32r/kernel/sys_m32r.c
@@ -76,30 +76,6 @@ asmlinkage int sys_tas(int __user *addr)
         return oldval;
 }
 
-asmlinkage long sys_mmap2(unsigned long addr, unsigned long len,
-        unsigned long prot, unsigned long flags,
-        unsigned long fd, unsigned long pgoff)
-{
-        int error = -EBADF;
-        struct file *file = NULL;
-
-        flags &= ~(MAP_EXECUTABLE | MAP_DENYWRITE);
-        if (!(flags & MAP_ANONYMOUS)) {
-                file = fget(fd);
-                if (!file)
-                        goto out;
-        }
-
-        down_write(&current->mm->mmap_sem);
-        error = do_mmap_pgoff(file, addr, len, prot, flags, pgoff);
-        up_write(&current->mm->mmap_sem);
-
-        if (file)
-                fput(file);
-out:
-        return error;
-}
-
 /*
  * sys_ipc() is the de-multiplexer for the SysV IPC calls..
  *
diff --git a/arch/m32r/kernel/syscall_table.S b/arch/m32r/kernel/syscall_table.S
index aa3bf4cfab37..60536e271233 100644
--- a/arch/m32r/kernel/syscall_table.S
+++ b/arch/m32r/kernel/syscall_table.S
@@ -191,7 +191,7 @@ ENTRY(sys_call_table)
         .long sys_ni_syscall            /* streams2 */
         .long sys_vfork                 /* 190 */
         .long sys_getrlimit
-        .long sys_mmap2
+        .long sys_mmap_pgoff
         .long sys_truncate64
         .long sys_ftruncate64
         .long sys_stat64                /* 195 */
diff --git a/arch/m68k/include/asm/asm-offsets.h b/arch/m68k/include/asm/asm-offsets.h
new file mode 100644
index 000000000000..d370ee36a182
--- /dev/null
+++ b/arch/m68k/include/asm/asm-offsets.h
@@ -0,0 +1 @@
+#include <generated/asm-offsets.h>
diff --git a/arch/m68k/include/asm/elf.h b/arch/m68k/include/asm/elf.h
index 0b0f49eb876b..01c193d91412 100644
--- a/arch/m68k/include/asm/elf.h
+++ b/arch/m68k/include/asm/elf.h
@@ -59,7 +59,6 @@ typedef struct user_m68kfp_struct elf_fpregset_t;
    is actually used on ASV.  */
 #define ELF_PLAT_INIT(_r, load_addr)    _r->a1 = 0
 
-#define USE_ELF_CORE_DUMP
 #ifndef CONFIG_SUN3
 #define ELF_EXEC_PAGESIZE       4096
 #else
diff --git a/arch/m68k/include/asm/pgtable_mm.h b/arch/m68k/include/asm/pgtable_mm.h
index fe60e1abaee8..aca0e28581c7 100644
--- a/arch/m68k/include/asm/pgtable_mm.h
+++ b/arch/m68k/include/asm/pgtable_mm.h
@@ -83,9 +83,9 @@
 #define VMALLOC_START (((unsigned long) high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1))
 #define VMALLOC_END KMAP_START
 #else
-extern unsigned long vmalloc_end;
+extern unsigned long m68k_vmalloc_end;
 #define VMALLOC_START 0x0f800000
-#define VMALLOC_END vmalloc_end
+#define VMALLOC_END m68k_vmalloc_end
 #endif /* CONFIG_SUN3 */
 
 /* zero page used for uninitialized stuff */
diff --git a/arch/m68k/kernel/head.S b/arch/m68k/kernel/head.S
index 86edb5fbcfc3..ef54128baa0b 100644
--- a/arch/m68k/kernel/head.S
+++ b/arch/m68k/kernel/head.S
@@ -196,7 +196,7 @@
  * for them and trying to understand what they mean.
  *
  * CONFIG_xxx:  These are the obvious machine configuration defines created
- * during configuration.  These are defined in include/linux/autoconf.h.
+ * during configuration.  These are defined in autoconf.h.
  *
  * CONSOLE:     There is support for head.S console in this file.  This
  * console can talk to a Mac frame buffer, but could easily be extrapolated
diff --git a/arch/m68k/kernel/sys_m68k.c b/arch/m68k/kernel/sys_m68k.c
index 7deb402bfc75..218f441de667 100644
--- a/arch/m68k/kernel/sys_m68k.c
+++ b/arch/m68k/kernel/sys_m68k.c
@@ -29,37 +29,16 @@
 #include <asm/page.h>
 #include <asm/unistd.h>
 
-/* common code for old and new mmaps */
-static inline long do_mmap2(
-        unsigned long addr, unsigned long len,
-        unsigned long prot, unsigned long flags,
-        unsigned long fd, unsigned long pgoff)
-{
-        int error = -EBADF;
-        struct file * file = NULL;
-
-        flags &= ~(MAP_EXECUTABLE | MAP_DENYWRITE);
-        if (!(flags & MAP_ANONYMOUS)) {
-                file = fget(fd);
-                if (!file)
-                        goto out;
-        }
-
-        down_write(&current->mm->mmap_sem);
-        error = do_mmap_pgoff(file, addr, len, prot, flags, pgoff);
-        up_write(&current->mm->mmap_sem);
-
-        if (file)
-                fput(file);
-out:
-        return error;
-}
-
 asmlinkage long sys_mmap2(unsigned long addr, unsigned long len,
         unsigned long prot, unsigned long flags,
         unsigned long fd, unsigned long pgoff)
 {
-        return do_mmap2(addr, len, prot, flags, fd, pgoff);
+        /*
+         * This is wrong for sun3 - there PAGE_SIZE is 8Kb,
+         * so we need to shift the argument down by 1; m68k mmap64(3)
+         * (in libc) expects the last argument of mmap2 in 4Kb units.
+         */
+        return sys_mmap_pgoff(addr, len, prot, flags, fd, pgoff);
 }
 
 /*
@@ -90,57 +69,11 @@ asmlinkage int old_mmap(struct mmap_arg_struct __user *arg)
         if (a.offset & ~PAGE_MASK)
                 goto out;
 
-        a.flags &= ~(MAP_EXECUTABLE | MAP_DENYWRITE);
-
-        error = do_mmap2(a.addr, a.len, a.prot, a.flags, a.fd, a.offset >> PAGE_SHIFT);
-out:
-        return error;
-}
-
-#if 0
-struct mmap_arg_struct64 {
-        __u32 addr;
-        __u32 len;
-        __u32 prot;
-        __u32 flags;
-        __u64 offset; /* 64 bits */
-        __u32 fd;
-};
-
-asmlinkage long sys_mmap64(struct mmap_arg_struct64 *arg)
-{
-        int error = -EFAULT;
-        struct file * file = NULL;
-        struct mmap_arg_struct64 a;
-        unsigned long pgoff;
-
-        if (copy_from_user(&a, arg, sizeof(a)))
-                return -EFAULT;
-
-        if ((long)a.offset & ~PAGE_MASK)
-                return -EINVAL;
-
-        pgoff = a.offset >> PAGE_SHIFT;
-        if ((a.offset >> PAGE_SHIFT) != pgoff)
-                return -EINVAL;
-
-        if (!(a.flags & MAP_ANONYMOUS)) {
-                error = -EBADF;
-                file = fget(a.fd);
-                if (!file)
-                        goto out;
-        }
-        a.flags &= ~(MAP_EXECUTABLE | MAP_DENYWRITE);
-
-        down_write(&current->mm->mmap_sem);
-        error = do_mmap_pgoff(file, a.addr, a.len, a.prot, a.flags, pgoff);
-        up_write(&current->mm->mmap_sem);
-        if (file)
-                fput(file);
+        error = sys_mmap_pgoff(a.addr, a.len, a.prot, a.flags, a.fd,
+                               a.offset >> PAGE_SHIFT);
 out:
         return error;
 }
-#endif
 
 struct sel_arg_struct {
         unsigned long n;
diff --git a/arch/m68k/sun3/mmu_emu.c b/arch/m68k/sun3/mmu_emu.c
index 3cd19390aae5..94f81ecfe3f8 100644
--- a/arch/m68k/sun3/mmu_emu.c
+++ b/arch/m68k/sun3/mmu_emu.c
@@ -45,8 +45,8 @@
 ** Globals
 */
 
-unsigned long vmalloc_end;
-EXPORT_SYMBOL(vmalloc_end);
+unsigned long m68k_vmalloc_end;
+EXPORT_SYMBOL(m68k_vmalloc_end);
 
 unsigned long pmeg_vaddr[PMEGS_NUM];
 unsigned char pmeg_alloc[PMEGS_NUM];
@@ -172,8 +172,8 @@ void mmu_emu_init(unsigned long bootmem_end)
 #endif
                         // the lowest mapping here is the end of our
                         // vmalloc region
-                        if(!vmalloc_end)
-                                vmalloc_end = seg;
+                        if (!m68k_vmalloc_end)
+                                m68k_vmalloc_end = seg;
 
                         // mark the segmap alloc'd, and reserve any
                         // of the first 0xbff pages the hardware is
diff --git a/arch/m68knommu/kernel/sys_m68k.c b/arch/m68knommu/kernel/sys_m68k.c
index efdd090778a3..b67cbc735a9b 100644
--- a/arch/m68knommu/kernel/sys_m68k.c
+++ b/arch/m68knommu/kernel/sys_m68k.c
@@ -27,39 +27,6 @@
 #include <asm/cacheflush.h>
 #include <asm/unistd.h>
 
-/* common code for old and new mmaps */
-static inline long do_mmap2(
-        unsigned long addr, unsigned long len,
-        unsigned long prot, unsigned long flags,
-        unsigned long fd, unsigned long pgoff)
-{
-        int error = -EBADF;
-        struct file * file = NULL;
-
-        flags &= ~(MAP_EXECUTABLE | MAP_DENYWRITE);
-        if (!(flags & MAP_ANONYMOUS)) {
-                file = fget(fd);
-                if (!file)
-                        goto out;
-        }
-
-        down_write(&current->mm->mmap_sem);
-        error = do_mmap_pgoff(file, addr, len, prot, flags, pgoff);
-        up_write(&current->mm->mmap_sem);
-
-        if (file)
-                fput(file);
-out:
-        return error;
-}
-
-asmlinkage long sys_mmap2(unsigned long addr, unsigned long len,
-        unsigned long prot, unsigned long flags,
-        unsigned long fd, unsigned long pgoff)
-{
-        return do_mmap2(addr, len, prot, flags, fd, pgoff);
-}
-
 /*
  * Perform the select(nd, in, out, ex, tv) and mmap() system
  * calls. Linux/m68k cloned Linux/i386, which didn't use to be able to
@@ -88,9 +55,8 @@ asmlinkage int old_mmap(struct mmap_arg_struct *arg)
         if (a.offset & ~PAGE_MASK)
                 goto out;
 
-        a.flags &= ~(MAP_EXECUTABLE | MAP_DENYWRITE);
-
-        error = do_mmap2(a.addr, a.len, a.prot, a.flags, a.fd, a.offset >> PAGE_SHIFT);
+        error = sys_mmap_pgoff(a.addr, a.len, a.prot, a.flags, a.fd,
+                                a.offset >> PAGE_SHIFT);
 out:
         return error;
 }
diff --git a/arch/m68knommu/kernel/syscalltable.S b/arch/m68knommu/kernel/syscalltable.S
index 23535cc415ae..486837efa3d7 100644
--- a/arch/m68knommu/kernel/syscalltable.S
+++ b/arch/m68knommu/kernel/syscalltable.S
@@ -210,7 +210,7 @@ ENTRY(sys_call_table)
         .long sys_ni_syscall    /* streams2 */
         .long sys_vfork         /* 190 */
         .long sys_getrlimit
-        .long sys_mmap2
+        .long sys_mmap_pgoff
         .long sys_truncate64
         .long sys_ftruncate64
         .long sys_stat64        /* 195 */
diff --git a/arch/microblaze/Kconfig b/arch/microblaze/Kconfig
index bbd8327f1890..fd53e500be67 100644
--- a/arch/microblaze/Kconfig
+++ b/arch/microblaze/Kconfig
@@ -6,8 +6,15 @@ mainmenu "Linux/Microblaze Kernel Configuration"
 config MICROBLAZE
         def_bool y
         select HAVE_LMB
+        select HAVE_FUNCTION_TRACER
+        select HAVE_FUNCTION_TRACE_MCOUNT_TEST
+        select HAVE_FUNCTION_GRAPH_TRACER
+        select HAVE_DYNAMIC_FTRACE
+        select HAVE_FTRACE_MCOUNT_RECORD
         select USB_ARCH_HAS_EHCI
         select ARCH_WANT_OPTIONAL_GPIOLIB
+        select HAVE_OPROFILE
+        select TRACING_SUPPORT
 
 config SWAP
         def_bool n
@@ -57,12 +64,24 @@ config GENERIC_GPIO
 config GENERIC_CSUM
         def_bool y
 
+config STACKTRACE_SUPPORT
+        def_bool y
+
+config LOCKDEP_SUPPORT
+        def_bool y
+
+config HAVE_LATENCYTOP_SUPPORT
+        def_bool y
+
 config PCI
         def_bool n
 
 config NO_DMA
         def_bool y
 
+config DTC
+        def_bool y
+
 source "init/Kconfig"
 
 source "kernel/Kconfig.freezer"
diff --git a/arch/microblaze/Kconfig.debug b/arch/microblaze/Kconfig.debug
index 242cd35bdb4b..9dc708a7f700 100644
--- a/arch/microblaze/Kconfig.debug
+++ b/arch/microblaze/Kconfig.debug
@@ -3,6 +3,9 @@
 
 menu "Kernel hacking"
 
+config TRACE_IRQFLAGS_SUPPORT
+        def_bool y
+
 source "lib/Kconfig.debug"
 
 config EARLY_PRINTK
diff --git a/arch/microblaze/Makefile b/arch/microblaze/Makefile
index 34187354304a..d2d6cfcb1a30 100644
--- a/arch/microblaze/Makefile
+++ b/arch/microblaze/Makefile
@@ -51,6 +51,8 @@ core-y += arch/microblaze/kernel/
 core-y += arch/microblaze/mm/
 core-y += arch/microblaze/platform/
 
+drivers-$(CONFIG_OPROFILE) += arch/microblaze/oprofile/
+
 boot := arch/microblaze/boot
 
 # Are we making a simpleImage.<boardname> target? If so, crack out the boardname
diff --git a/arch/microblaze/boot/Makefile b/arch/microblaze/boot/Makefile
index 21f13322a4ca..902cf9846c3c 100644
--- a/arch/microblaze/boot/Makefile
+++ b/arch/microblaze/boot/Makefile
@@ -2,11 +2,13 @@
 # arch/microblaze/boot/Makefile
 #
 
+MKIMAGE := $(srctree)/scripts/mkuboot.sh
+
 obj-y += linked_dtb.o
 
 targets := linux.bin linux.bin.gz simpleImage.%
 
-OBJCOPYFLAGS_linux.bin  := -O binary
+OBJCOPYFLAGS := -O binary
 
 # Where the DTS files live
 dtstree         := $(srctree)/$(src)/dts
@@ -24,6 +26,7 @@ $(obj)/linux.bin: vmlinux FORCE
         [ -n $(CONFIG_INITRAMFS_SOURCE) ] && [ ! -e $(CONFIG_INITRAMFS_SOURCE) ] && \
         touch $(CONFIG_INITRAMFS_SOURCE) || echo "No CPIO image"
         $(call if_changed,objcopy)
+        $(call if_changed,uimage)
         @echo 'Kernel: $@ is ready' ' (#'`cat .version`')'
 
 $(obj)/linux.bin.gz: $(obj)/linux.bin FORCE
@@ -36,8 +39,16 @@ quiet_cmd_cp = CP      $< $@$2
 quiet_cmd_strip = STRIP   $@
       cmd_strip = $(STRIP) -K _start -K _end -K __log_buf -K _fdt_start vmlinux -o $@
 
+quiet_cmd_uimage = UIMAGE  $@.ub
+      cmd_uimage = $(CONFIG_SHELL) $(MKIMAGE) -A microblaze -O linux -T kernel \
+                   -C none -n 'Linux-$(KERNELRELEASE)' \
+                   -a $(CONFIG_KERNEL_BASE_ADDR) -e $(CONFIG_KERNEL_BASE_ADDR) \
+                   -d $@ $@.ub
+
 $(obj)/simpleImage.%: vmlinux FORCE
         $(call if_changed,cp,.unstrip)
+        $(call if_changed,objcopy)
+        $(call if_changed,uimage)
         $(call if_changed,strip)
         @echo 'Kernel: $@ is ready' ' (#'`cat .version`')'
 
@@ -53,4 +64,4 @@ $(obj)/%.dtb: $(dtstree)/%.dts FORCE
 
 clean-kernel += linux.bin linux.bin.gz simpleImage.*
 
-clean-files += *.dtb
+clean-files += *.dtb simpleImage.*.unstrip
diff --git a/arch/microblaze/include/asm/asm-offsets.h b/arch/microblaze/include/asm/asm-offsets.h
new file mode 100644
index 000000000000..d370ee36a182
--- /dev/null
+++ b/arch/microblaze/include/asm/asm-offsets.h
@@ -0,0 +1 @@
+#include <generated/asm-offsets.h>
diff --git a/arch/microblaze/include/asm/cache.h b/arch/microblaze/include/asm/cache.h
index c209c47509d5..e52210891d78 100644
--- a/arch/microblaze/include/asm/cache.h
+++ b/arch/microblaze/include/asm/cache.h
@@ -21,20 +21,4 @@
 
 #define SMP_CACHE_BYTES L1_CACHE_BYTES
 
-void _enable_icache(void);
-void _disable_icache(void);
-void _invalidate_icache(unsigned int addr);
-
-#define __enable_icache()               _enable_icache()
-#define __disable_icache()              _disable_icache()
-#define __invalidate_icache(addr)       _invalidate_icache(addr)
-
-void _enable_dcache(void);
-void _disable_dcache(void);
-void _invalidate_dcache(unsigned int addr);
-
-#define __enable_dcache()               _enable_dcache()
-#define __disable_dcache()              _disable_dcache()
-#define __invalidate_dcache(addr)       _invalidate_dcache(addr)
-
 #endif /* _ASM_MICROBLAZE_CACHE_H */
diff --git a/arch/microblaze/include/asm/cacheflush.h b/arch/microblaze/include/asm/cacheflush.h
index 088076e657b3..a6edd356cd08 100644
--- a/arch/microblaze/include/asm/cacheflush.h
+++ b/arch/microblaze/include/asm/cacheflush.h
@@ -18,6 +18,8 @@
 /* Somebody depends on this; sigh... */
 #include <linux/mm.h>
 
+/* Look at Documentation/cachetlb.txt */
+
 /*
  * Cache handling functions.
  * Microblaze has a write-through data cache, meaning that the data cache
@@ -27,78 +29,81 @@
  * instruction cache to make sure we don't fetch old, bad code.
  */
 
+/* struct cache, d=dcache, i=icache, fl = flush, iv = invalidate,
+ * suffix r = range */
+struct scache {
+        /* icache */
+        void (*ie)(void); /* enable */
+        void (*id)(void); /* disable */
+        void (*ifl)(void); /* flush */
+        void (*iflr)(unsigned long a, unsigned long b);
+        void (*iin)(void); /* invalidate */
+        void (*iinr)(unsigned long a, unsigned long b);
+        /* dcache */
+        void (*de)(void); /* enable */
+        void (*dd)(void); /* disable */
+        void (*dfl)(void); /* flush */
+        void (*dflr)(unsigned long a, unsigned long b);
+        void (*din)(void); /* invalidate */
+        void (*dinr)(unsigned long a, unsigned long b);
+};
+
+/* microblaze cache */
+extern struct scache *mbc;
+
+void microblaze_cache_init(void);
+
+#define enable_icache()                                 mbc->ie();
+#define disable_icache()                                mbc->id();
+#define flush_icache()                                  mbc->ifl();
+#define flush_icache_range(start, end)                  mbc->iflr(start, end);
+#define invalidate_icache()                             mbc->iin();
+#define invalidate_icache_range(start, end)             mbc->iinr(start, end);
+
+
+#define flush_icache_user_range(vma, pg, adr, len)      flush_icache();
+#define flush_icache_page(vma, pg)                      do { } while (0)
+
+#define enable_dcache()                                 mbc->de();
+#define disable_dcache()                                mbc->dd();
 /* FIXME for LL-temac driver */
-#define invalidate_dcache_range(start, end) \
-                        __invalidate_dcache_range(start, end)
-
-#define flush_cache_all()                       __invalidate_cache_all()
-#define flush_cache_mm(mm)                      do { } while (0)
-#define flush_cache_range(vma, start, end)      __invalidate_cache_all()
-#define flush_cache_page(vma, vmaddr, pfn)      do { } while (0)
+#define invalidate_dcache()                             mbc->din();
+#define invalidate_dcache_range(start, end)             mbc->dinr(start, end);
+#define flush_dcache()                                  mbc->dfl();
+#define flush_dcache_range(start, end)                  mbc->dflr(start, end);
 
-#define flush_dcache_range(start, end)  __invalidate_dcache_range(start, end)
 #define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 0
+/* D-cache aliasing problem can't happen - cache is between MMU and ram */
 #define flush_dcache_page(page)                 do { } while (0)
 #define flush_dcache_mmap_lock(mapping)         do { } while (0)
 #define flush_dcache_mmap_unlock(mapping)       do { } while (0)
 
-#define flush_icache_range(start, len)  __invalidate_icache_range(start, len)
-#define flush_icache_page(vma, pg)              do { } while (0)
-
-#ifndef CONFIG_MMU
-# define flush_icache_user_range(start, len)    do { } while (0)
-#else
-# define flush_icache_user_range(vma, pg, adr, len) __invalidate_icache_all()
-
-# define flush_page_to_ram(page)                do { } while (0)
 
-# define flush_icache()                 __invalidate_icache_all()
-# define flush_cache_sigtramp(vaddr) \
-                        __invalidate_icache_range(vaddr, vaddr + 8)
-
-# define flush_dcache_mmap_lock(mapping)        do { } while (0)
-# define flush_dcache_mmap_unlock(mapping)      do { } while (0)
+#define flush_cache_dup_mm(mm)                          do { } while (0)
+#define flush_cache_vmap(start, end)                    do { } while (0)
+#define flush_cache_vunmap(start, end)                  do { } while (0)
+#define flush_cache_mm(mm)                      do { } while (0)
+#define flush_cache_page(vma, vmaddr, pfn)      do { } while (0)
 
-# define flush_cache_dup_mm(mm)                 do { } while (0)
+/* MS: kgdb code use this macro, wrong len with FLASH */
+#if 0
+#define flush_cache_range(vma, start, len)      {       \
+        flush_icache_range((unsigned) (start), (unsigned) (start) + (len)); \
+        flush_dcache_range((unsigned) (start), (unsigned) (start) + (len)); \
+}
 #endif
 
-#define flush_cache_vmap(start, end)            do { } while (0)
-#define flush_cache_vunmap(start, end)          do { } while (0)
-
-struct page;
-struct mm_struct;
-struct vm_area_struct;
-
-/* see arch/microblaze/kernel/cache.c */
-extern void __invalidate_icache_all(void);
-extern void __invalidate_icache_range(unsigned long start, unsigned long end);
-extern void __invalidate_icache_page(struct vm_area_struct *vma,
-                                struct page *page);
-extern void __invalidate_icache_user_range(struct vm_area_struct *vma,
-                                struct page *page,
-                                unsigned long adr, int len);
-extern void __invalidate_cache_sigtramp(unsigned long addr);
-
-extern void __invalidate_dcache_all(void);
-extern void __invalidate_dcache_range(unsigned long start, unsigned long end);
-extern void __invalidate_dcache_page(struct vm_area_struct *vma,
-                                struct page *page);
-extern void __invalidate_dcache_user_range(struct vm_area_struct *vma,
-                                struct page *page,
-                                unsigned long adr, int len);
-
-extern inline void __invalidate_cache_all(void)
-{
-        __invalidate_icache_all();
-        __invalidate_dcache_all();
-}
+#define flush_cache_range(vma, start, len) do { } while (0)
 
-#define copy_to_user_page(vma, page, vaddr, dst, src, len) \
-do { memcpy((dst), (src), (len)); \
-        flush_icache_range((unsigned) (dst), (unsigned) (dst) + (len)); \
+#define copy_to_user_page(vma, page, vaddr, dst, src, len)              \
+do {                                                                    \
+        memcpy((dst), (src), (len));                                    \
+        flush_icache_range((unsigned) (dst), (unsigned) (dst) + (len)); \
 } while (0)
 
-#define copy_from_user_page(vma, page, vaddr, dst, src, len) \
-        memcpy((dst), (src), (len))
+#define copy_from_user_page(vma, page, vaddr, dst, src, len)            \
+do {                                                                    \
+        memcpy((dst), (src), (len));                                    \
+} while (0)
 
 #endif /* _ASM_MICROBLAZE_CACHEFLUSH_H */
diff --git a/arch/microblaze/include/asm/cpuinfo.h b/arch/microblaze/include/asm/cpuinfo.h
index 52f28f6dc4eb..b4f5ca33aebf 100644
--- a/arch/microblaze/include/asm/cpuinfo.h
+++ b/arch/microblaze/include/asm/cpuinfo.h
@@ -43,7 +43,7 @@ struct cpuinfo {
         u32 use_icache;
         u32 icache_tagbits;
         u32 icache_write;
-        u32 icache_line;
+        u32 icache_line_length;
         u32 icache_size;
         unsigned long icache_base;
         unsigned long icache_high;
@@ -51,8 +51,9 @@ struct cpuinfo {
         u32 use_dcache;
         u32 dcache_tagbits;
         u32 dcache_write;
-        u32 dcache_line;
+        u32 dcache_line_length;
         u32 dcache_size;
+        u32 dcache_wb;
         unsigned long dcache_base;
         unsigned long dcache_high;
 
diff --git a/arch/microblaze/include/asm/device.h b/arch/microblaze/include/asm/device.h
index 30286db27c1c..78a038452c0f 100644
--- a/arch/microblaze/include/asm/device.h
+++ b/arch/microblaze/include/asm/device.h
@@ -19,6 +19,18 @@ struct dev_archdata {
 struct pdev_archdata {
 };
 
+static inline void dev_archdata_set_node(struct dev_archdata *ad,
+                                         struct device_node *np)
+{
+        ad->of_node = np;
+}
+
+static inline struct device_node *
+dev_archdata_get_node(const struct dev_archdata *ad)
+{
+        return ad->of_node;
+}
+
 #endif /* _ASM_MICROBLAZE_DEVICE_H */
 
 
diff --git a/arch/microblaze/include/asm/elf.h b/arch/microblaze/include/asm/elf.h
index f92fc0dda006..7d4acf2b278e 100644
--- a/arch/microblaze/include/asm/elf.h
+++ b/arch/microblaze/include/asm/elf.h
@@ -77,7 +77,6 @@ typedef elf_fpreg_t elf_fpregset_t[ELF_NFPREG];
 #define ELF_DATA        ELFDATA2MSB
 #endif
 
-#define USE_ELF_CORE_DUMP
 #define ELF_EXEC_PAGESIZE       4096
 
 
diff --git a/arch/microblaze/include/asm/ftrace.h b/arch/microblaze/include/asm/ftrace.h
index 8b137891791f..fd2fa2eca62f 100644
--- a/arch/microblaze/include/asm/ftrace.h
+++ b/arch/microblaze/include/asm/ftrace.h
@@ -1 +1,26 @@
+#ifndef _ASM_MICROBLAZE_FTRACE
+#define _ASM_MICROBLAZE_FTRACE
 
+#ifdef CONFIG_FUNCTION_TRACER
+
+#define MCOUNT_ADDR             ((long)(_mcount))
+#define MCOUNT_INSN_SIZE        8 /* sizeof mcount call */
+
+#ifndef __ASSEMBLY__
+extern void _mcount(void);
+extern void ftrace_call_graph(void);
+#endif
+
+#ifdef CONFIG_DYNAMIC_FTRACE
+/* reloction of mcount call site is the same as the address */
+static inline unsigned long ftrace_call_adjust(unsigned long addr)
+{
+        return addr;
+}
+
+struct dyn_arch_ftrace {
+};
+#endif /* CONFIG_DYNAMIC_FTRACE */
+
+#endif /* CONFIG_FUNCTION_TRACER */
+#endif /* _ASM_MICROBLAZE_FTRACE */
diff --git a/arch/microblaze/include/asm/futex.h b/arch/microblaze/include/asm/futex.h
index 0b745828f42b..8dbb6e7a03a2 100644
--- a/arch/microblaze/include/asm/futex.h
+++ b/arch/microblaze/include/asm/futex.h
@@ -1 +1,126 @@
-#include <asm-generic/futex.h>
+#ifndef _ASM_MICROBLAZE_FUTEX_H
+#define _ASM_MICROBLAZE_FUTEX_H
+
+#ifdef __KERNEL__
+
+#include <linux/futex.h>
+#include <linux/uaccess.h>
+#include <asm/errno.h>
+
+#define __futex_atomic_op(insn, ret, oldval, uaddr, oparg) \
+({                                                                      \
+        __asm__ __volatile__ (                                          \
+                        "1:     lwx     %0, %2, r0; "                   \
+                                insn                                    \
+                        "2:     swx     %1, %2, r0;                     \
+                                addic   %1, r0, 0;                      \
+                                bnei    %1, 1b;                         \
+                        3:                                              \
+                        .section .fixup,\"ax\";                         \
+                        4:      brid    3b;                             \
+                                addik   %1, r0, %3;                     \
+                        .previous;                                      \
+                        .section __ex_table,\"a\";                      \
+                        .word   1b,4b,2b,4b;                            \
+                        .previous;"                                     \
+        : "=&r" (oldval), "=&r" (ret)                                   \
+        : "b" (uaddr), "i" (-EFAULT), "r" (oparg)                       \
+        );                                                              \
+})
+
+static inline int
+futex_atomic_op_inuser(int encoded_op, int __user *uaddr)
+{
+        int op = (encoded_op >> 28) & 7;
+        int cmp = (encoded_op >> 24) & 15;
+        int oparg = (encoded_op << 8) >> 20;
+        int cmparg = (encoded_op << 20) >> 20;
+        int oldval = 0, ret;
+        if (encoded_op & (FUTEX_OP_OPARG_SHIFT << 28))
+                oparg = 1 << oparg;
+
+        if (!access_ok(VERIFY_WRITE, uaddr, sizeof(int)))
+                return -EFAULT;
+
+        pagefault_disable();
+
+        switch (op) {
+        case FUTEX_OP_SET:
+                __futex_atomic_op("or %1,%4,%4;", ret, oldval, uaddr, oparg);
+                break;
+        case FUTEX_OP_ADD:
+                __futex_atomic_op("add %1,%0,%4;", ret, oldval, uaddr, oparg);
+                break;
+        case FUTEX_OP_OR:
+                __futex_atomic_op("or %1,%0,%4;", ret, oldval, uaddr, oparg);
+                break;
+        case FUTEX_OP_ANDN:
+                __futex_atomic_op("and %1,%0,%4;", ret, oldval, uaddr, oparg);
+                break;
+        case FUTEX_OP_XOR:
+                __futex_atomic_op("xor %1,%0,%4;", ret, oldval, uaddr, oparg);
+                break;
+        default:
+                ret = -ENOSYS;
+        }
+
+        pagefault_enable();
+
+        if (!ret) {
+                switch (cmp) {
+                case FUTEX_OP_CMP_EQ:
+                        ret = (oldval == cmparg);
+                        break;
+                case FUTEX_OP_CMP_NE:
+                        ret = (oldval != cmparg);
+                        break;
+                case FUTEX_OP_CMP_LT:
+                        ret = (oldval < cmparg);
+                        break;
+                case FUTEX_OP_CMP_GE:
+                        ret = (oldval >= cmparg);
+                        break;
+                case FUTEX_OP_CMP_LE:
+                        ret = (oldval <= cmparg);
+                        break;
+                case FUTEX_OP_CMP_GT:
+                        ret = (oldval > cmparg);
+                        break;
+                default:
+                        ret = -ENOSYS;
+                }
+        }
+        return ret;
+}
+
+static inline int
+futex_atomic_cmpxchg_inatomic(int __user *uaddr, int oldval, int newval)
+{
+        int prev, cmp;
+
+        if (!access_ok(VERIFY_WRITE, uaddr, sizeof(int)))
+                return -EFAULT;
+
+        __asm__ __volatile__ ("1:       lwx     %0, %2, r0;             \
+                                        cmp     %1, %0, %3;             \
+                                        beqi    %1, 3f;                 \
+                                2:      swx     %4, %2, r0;             \
+                                        addic   %1, r0, 0;              \
+                                        bnei    %1, 1b;                 \
+                                3:                                      \
+                                .section .fixup,\"ax\";                 \
+                                4:      brid    3b;                     \
+                                        addik   %0, r0, %5;             \
+                                .previous;                              \
+                                .section __ex_table,\"a\";              \
+                                .word   1b,4b,2b,4b;                    \
+                                .previous;"                             \
+                : "=&r" (prev), "=&r"(cmp)                              \
+                : "r" (uaddr), "r" (oldval), "r" (newval), "i" (-EFAULT));
+
+        return prev;
+}
+
+#endif /* __KERNEL__ */
+
+#endif
diff --git a/arch/microblaze/include/asm/irqflags.h b/arch/microblaze/include/asm/irqflags.h
index dea65645a4f8..2c38c6d80176 100644
--- a/arch/microblaze/include/asm/irqflags.h
+++ b/arch/microblaze/include/asm/irqflags.h
@@ -10,78 +10,73 @@
 #define _ASM_MICROBLAZE_IRQFLAGS_H
 
 #include <linux/irqflags.h>
+#include <asm/registers.h>
 
 # if CONFIG_XILINX_MICROBLAZE0_USE_MSR_INSTR
 
-# define local_irq_save(flags)                          \
+# define raw_local_irq_save(flags)                      \
         do {                                            \
-                asm volatile ("# local_irq_save \n\t"   \
-                                "msrclr %0, %1  \n\t"   \
-                                "nop    \n\t"           \
+                asm volatile (" msrclr %0, %1;          \
+                                nop;"                   \
                                 : "=r"(flags)           \
                                 : "i"(MSR_IE)           \
                                 : "memory");            \
         } while (0)
 
-# define local_irq_disable()                                    \
-        do {                                                    \
-                asm volatile ("# local_irq_disable \n\t"        \
-                                "msrclr r0, %0 \n\t"            \
-                                "nop    \n\t"                   \
-                                :                               \
-                                : "i"(MSR_IE)                   \
-                                : "memory");                    \
+# define raw_local_irq_disable()                        \
+        do {                                            \
+                asm volatile (" msrclr r0, %0;          \
+                                nop;"                   \
+                                :                       \
+                                : "i"(MSR_IE)           \
+                                : "memory");            \
         } while (0)
 
-# define local_irq_enable()                                     \
-        do {                                                    \
-                asm volatile ("# local_irq_enable \n\t"         \
-                                "msrset r0, %0 \n\t"            \
-                                "nop    \n\t"                   \
-                                :                               \
-                                : "i"(MSR_IE)                   \
-                                : "memory");                    \
+# define raw_local_irq_enable()                         \
+        do {                                            \
+                asm volatile (" msrset  r0, %0;         \
+                                nop;"                   \
+                                :                       \
+                                : "i"(MSR_IE)           \
+                                : "memory");            \
         } while (0)
 
 # else /* CONFIG_XILINX_MICROBLAZE0_USE_MSR_INSTR == 0 */
 
-# define local_irq_save(flags)                                  \
+# define raw_local_irq_save(flags)                              \
         do {                                                    \
                 register unsigned tmp;                          \
-                asm volatile ("# local_irq_save \n\t"           \
-                                "mfs    %0, rmsr \n\t"          \
-                                "nop \n\t"                      \
-                                "andi   %1, %0, %2 \n\t"        \
-                                "mts    rmsr, %1 \n\t"          \
-                                "nop \n\t"                      \
+                asm volatile (" mfs     %0, rmsr;               \
+                                nop;                            \
+                                andi    %1, %0, %2;             \
+                                mts     rmsr, %1;               \
+                                nop;"                           \
                                 : "=r"(flags), "=r" (tmp)       \
                                 : "i"(~MSR_IE)                  \
                                 : "memory");                    \
         } while (0)
 
-# define local_irq_disable()                                    \
+# define raw_local_irq_disable()                                \
         do {                                                    \
                 register unsigned tmp;                          \
-                asm volatile ("# local_irq_disable \n\t"        \
-                                "mfs    %0, rmsr \n\t"          \
-                                "nop \n\t"                      \
-                                "andi   %0, %0, %1 \n\t"        \
-                                "mts    rmsr, %0 \n\t"          \
-                                "nop \n\t"                      \
+                asm volatile (" mfs     %0, rmsr;               \
+                                nop;                            \
+                                andi    %0, %0, %1;             \
+                                mts     rmsr, %0;               \
+                                nop;"                   \
                                 : "=r"(tmp)                     \
                                 : "i"(~MSR_IE)                  \
                                 : "memory");                    \
         } while (0)
 
-# define local_irq_enable()                                     \
+# define raw_local_irq_enable()                                 \
         do {                                                    \
                 register unsigned tmp;                          \
-                asm volatile ("# local_irq_enable \n\t"         \
-                                "mfs    %0, rmsr \n\t"          \
-                                "nop \n\t"                      \
-                                "ori    %0, %0, %1 \n\t"        \
-                                "mts    rmsr, %0 \n\t"          \
-                                "nop \n\t"                      \
+                asm volatile (" mfs     %0, rmsr;               \
+                                nop;                            \
+                                ori     %0, %0, %1;             \
+                                mts     rmsr, %0;               \
+                                nop;"                           \
                                 : "=r"(tmp)                     \
                                 : "i"(MSR_IE)                   \
                                 : "memory");                    \
@@ -89,35 +84,28 @@
 
 # endif /* CONFIG_XILINX_MICROBLAZE0_USE_MSR_INSTR */
 
-#define local_save_flags(flags)                                 \
+#define raw_local_irq_restore(flags)                            \
         do {                                                    \
-                asm volatile ("# local_save_flags \n\t"         \
-                                "mfs    %0, rmsr \n\t"          \
-                                "nop    \n\t"                   \
-                                : "=r"(flags)                   \
+                asm volatile (" mts     rmsr, %0;               \
+                                nop;"                           \
                                 :                               \
+                                : "r"(flags)                    \
                                 : "memory");                    \
         } while (0)
 
-#define local_irq_restore(flags)                        \
-        do {                                            \
-                asm volatile ("# local_irq_restore \n\t"\
-                                "mts    rmsr, %0 \n\t"  \
-                                "nop    \n\t"           \
-                                :                       \
-                                : "r"(flags)            \
-                                : "memory");            \
-        } while (0)
-
-static inline int irqs_disabled(void)
+static inline unsigned long get_msr(void)
 {
         unsigned long flags;
-
-        local_save_flags(flags);
-        return ((flags & MSR_IE) == 0);
+        asm volatile (" mfs     %0, rmsr;       \
+                        nop;"                   \
+                        : "=r"(flags)           \
+                        :                       \
+                        : "memory");            \
+        return flags;
 }
 
-#define raw_irqs_disabled irqs_disabled
-#define raw_irqs_disabled_flags(flags)  ((flags) == 0)
+#define raw_local_save_flags(flags)     ((flags) = get_msr())
+#define raw_irqs_disabled()             ((get_msr() & MSR_IE) == 0)
+#define raw_irqs_disabled_flags(flags)  ((flags & MSR_IE) == 0)
 
 #endif /* _ASM_MICROBLAZE_IRQFLAGS_H */
diff --git a/arch/microblaze/include/asm/page.h b/arch/microblaze/include/asm/page.h
index 880c988c2237..9b66c0fa9a32 100644
--- a/arch/microblaze/include/asm/page.h
+++ b/arch/microblaze/include/asm/page.h
@@ -164,7 +164,8 @@ extern int page_is_ram(unsigned long pfn);
 #  endif /* CONFIG_MMU */
 
 #  ifndef CONFIG_MMU
-#  define pfn_valid(pfn)        ((pfn) >= min_low_pfn && (pfn) <= max_mapnr)
+#  define pfn_valid(pfn)        (((pfn) >= min_low_pfn) && \
+                                ((pfn) <= (min_low_pfn + max_mapnr)))
 #  define ARCH_PFN_OFFSET       (PAGE_OFFSET >> PAGE_SHIFT)
 #  else /* CONFIG_MMU */
 #  define ARCH_PFN_OFFSET       (memory_start >> PAGE_SHIFT)
diff --git a/arch/microblaze/include/asm/pgalloc.h b/arch/microblaze/include/asm/pgalloc.h
index b0131da1387b..7547f5064560 100644
--- a/arch/microblaze/include/asm/pgalloc.h
+++ b/arch/microblaze/include/asm/pgalloc.h
@@ -106,9 +106,6 @@ extern inline void free_pgd_slow(pgd_t *pgd)
  */
 #define pmd_alloc_one_fast(mm, address) ({ BUG(); ((pmd_t *)1); })
 #define pmd_alloc_one(mm, address)      ({ BUG(); ((pmd_t *)2); })
-/* FIXME two definition - look below */
-#define pmd_free(mm, x)                 do { } while (0)
-#define pgd_populate(mm, pmd, pte)      BUG()
 
 static inline pte_t *pte_alloc_one_kernel(struct mm_struct *mm,
                 unsigned long address)
@@ -192,14 +189,14 @@ extern inline void pte_free(struct mm_struct *mm, struct page *ptepage)
  * the pgd will always be present..
  */
 #define pmd_alloc_one(mm, address)      ({ BUG(); ((pmd_t *)2); })
-/*#define pmd_free(mm, x)                       do { } while (0)*/
-#define __pmd_free_tlb(tlb, x, addr)    do { } while (0)
+#define pmd_free(mm, x)                 do { } while (0)
+#define __pmd_free_tlb(tlb, x, addr)    pmd_free((tlb)->mm, x)
 #define pgd_populate(mm, pmd, pte)      BUG()
 
 extern int do_check_pgt_cache(int, int);
 
 #endif /* CONFIG_MMU */
 
-#define check_pgt_cache()       do {} while (0)
+#define check_pgt_cache()               do { } while (0)
 
 #endif /* _ASM_MICROBLAZE_PGALLOC_H */
diff --git a/arch/microblaze/include/asm/pvr.h b/arch/microblaze/include/asm/pvr.h
index 66f1b30dd097..e38abc7714b6 100644
--- a/arch/microblaze/include/asm/pvr.h
+++ b/arch/microblaze/include/asm/pvr.h
@@ -76,20 +76,23 @@ struct pvr_s {
 #define PVR3_FSL_LINKS_MASK             0x00000380
 
 /* ICache config PVR masks */
-#define PVR4_USE_ICACHE_MASK            0x80000000
-#define PVR4_ICACHE_ADDR_TAG_BITS_MASK  0x7C000000
-#define PVR4_ICACHE_USE_FSL_MASK        0x02000000
-#define PVR4_ICACHE_ALLOW_WR_MASK       0x01000000
-#define PVR4_ICACHE_LINE_LEN_MASK       0x00E00000
-#define PVR4_ICACHE_BYTE_SIZE_MASK      0x001F0000
+#define PVR4_USE_ICACHE_MASK            0x80000000 /* ICU */
+#define PVR4_ICACHE_ADDR_TAG_BITS_MASK  0x7C000000 /* ICTS */
+#define PVR4_ICACHE_ALLOW_WR_MASK       0x01000000 /* ICW */
+#define PVR4_ICACHE_LINE_LEN_MASK       0x00E00000 /* ICLL */
+#define PVR4_ICACHE_BYTE_SIZE_MASK      0x001F0000 /* ICBS */
+#define PVR4_ICACHE_ALWAYS_USED         0x00008000 /* IAU */
+#define PVR4_ICACHE_INTERFACE           0x00002000 /* ICI */
 
 /* DCache config PVR masks */
-#define PVR5_USE_DCACHE_MASK            0x80000000
-#define PVR5_DCACHE_ADDR_TAG_BITS_MASK  0x7C000000
-#define PVR5_DCACHE_USE_FSL_MASK        0x02000000
-#define PVR5_DCACHE_ALLOW_WR_MASK       0x01000000
-#define PVR5_DCACHE_LINE_LEN_MASK       0x00E00000
-#define PVR5_DCACHE_BYTE_SIZE_MASK      0x001F0000
+#define PVR5_USE_DCACHE_MASK            0x80000000 /* DCU */
+#define PVR5_DCACHE_ADDR_TAG_BITS_MASK  0x7C000000 /* DCTS */
+#define PVR5_DCACHE_ALLOW_WR_MASK       0x01000000 /* DCW */
+#define PVR5_DCACHE_LINE_LEN_MASK       0x00E00000 /* DCLL */
+#define PVR5_DCACHE_BYTE_SIZE_MASK      0x001F0000 /* DCBS */
+#define PVR5_DCACHE_ALWAYS_USED         0x00008000 /* DAU */
+#define PVR5_DCACHE_USE_WRITEBACK       0x00004000 /* DWB */
+#define PVR5_DCACHE_INTERFACE           0x00002000 /* DCI */
 
 /* ICache base address PVR mask */
 #define PVR6_ICACHE_BASEADDR_MASK       0xFFFFFFFF
@@ -178,11 +181,14 @@ struct pvr_s {
                         ((pvr.pvr[5] & PVR5_DCACHE_ADDR_TAG_BITS_MASK) >> 26)
 #define PVR_DCACHE_USE_FSL(pvr)         (pvr.pvr[5] & PVR5_DCACHE_USE_FSL_MASK)
 #define PVR_DCACHE_ALLOW_WR(pvr)        (pvr.pvr[5] & PVR5_DCACHE_ALLOW_WR_MASK)
+/* FIXME two shifts on one line needs any comment */
 #define PVR_DCACHE_LINE_LEN(pvr) \
                         (1 << ((pvr.pvr[5] & PVR5_DCACHE_LINE_LEN_MASK) >> 21))
 #define PVR_DCACHE_BYTE_SIZE(pvr) \
                         (1 << ((pvr.pvr[5] & PVR5_DCACHE_BYTE_SIZE_MASK) >> 16))
 
+#define PVR_DCACHE_USE_WRITEBACK(pvr) \
+                        ((pvr.pvr[5] & PVR5_DCACHE_USE_WRITEBACK) >> 14)
 
 #define PVR_ICACHE_BASEADDR(pvr)        (pvr.pvr[6] & PVR6_ICACHE_BASEADDR_MASK)
 #define PVR_ICACHE_HIGHADDR(pvr)        (pvr.pvr[7] & PVR7_ICACHE_HIGHADDR_MASK)
diff --git a/arch/microblaze/include/asm/setup.h b/arch/microblaze/include/asm/setup.h
index ed67c9ed15b8..7f31394985e0 100644
--- a/arch/microblaze/include/asm/setup.h
+++ b/arch/microblaze/include/asm/setup.h
@@ -35,6 +35,8 @@ extern void mmu_reset(void);
 extern void early_console_reg_tlb_alloc(unsigned int addr);
 #   endif /* CONFIG_MMU */
 
+extern void of_platform_reset_gpio_probe(void);
+
 void time_init(void);
 void init_IRQ(void);
 void machine_early_init(const char *cmdline, unsigned int ram,
diff --git a/arch/microblaze/include/asm/system.h b/arch/microblaze/include/asm/system.h
index b1ed61590660..157970688b2a 100644
--- a/arch/microblaze/include/asm/system.h
+++ b/arch/microblaze/include/asm/system.h
@@ -16,6 +16,8 @@
 #include <asm-generic/cmpxchg.h>
 #include <asm-generic/cmpxchg-local.h>
 
+#define __ARCH_WANT_INTERRUPTS_ON_CTXSW
+
 struct task_struct;
 struct thread_info;
 
diff --git a/arch/microblaze/include/asm/uaccess.h b/arch/microblaze/include/asm/uaccess.h
index 5431b4631a7a..371bd6e56d9a 100644
--- a/arch/microblaze/include/asm/uaccess.h
+++ b/arch/microblaze/include/asm/uaccess.h
@@ -272,8 +272,9 @@ static inline int clear_user(char *to, int size)
         return size;
 }
 
-extern unsigned long __copy_tofrom_user(void __user *to,
-                const void __user *from, unsigned long size);
+#define __copy_from_user(to, from, n)   copy_from_user((to), (from), (n))
+#define __copy_from_user_inatomic(to, from, n) \
+                copy_from_user((to), (from), (n))
 
 #define copy_to_user(to, from, n)                                       \
         (access_ok(VERIFY_WRITE, (to), (n)) ?                           \
@@ -290,10 +291,6 @@ extern unsigned long __copy_tofrom_user(void __user *to,
                         (void __user *)(from), (n))                     \
                 : -EFAULT)
 
-#define __copy_from_user(to, from, n)   copy_from_user((to), (from), (n))
-#define __copy_from_user_inatomic(to, from, n) \
-                copy_from_user((to), (from), (n))
-
 extern int __strncpy_user(char *to, const char __user *from, int len);
 extern int __strnlen_user(const char __user *sstr, int len);
 
@@ -305,6 +302,9 @@ extern int __strnlen_user(const char __user *sstr, int len);
 
 #endif /* CONFIG_MMU */
 
+extern unsigned long __copy_tofrom_user(void __user *to,
+                const void __user *from, unsigned long size);
+
 /*
  * The exception table consists of pairs of addresses: the first is the
  * address of an instruction that is allowed to fault, and the second is
diff --git a/arch/microblaze/kernel/Makefile b/arch/microblaze/kernel/Makefile
index d487729683de..b07594eccf9b 100644
--- a/arch/microblaze/kernel/Makefile
+++ b/arch/microblaze/kernel/Makefile
@@ -2,12 +2,22 @@
 # Makefile
 #
 
+ifdef CONFIG_FUNCTION_TRACER
+# Do not trace early boot code and low level code
+CFLAGS_REMOVE_timer.o = -pg
+CFLAGS_REMOVE_intc.o = -pg
+CFLAGS_REMOVE_early_printk.o = -pg
+CFLAGS_REMOVE_selfmod.o = -pg
+CFLAGS_REMOVE_heartbeat.o = -pg
+CFLAGS_REMOVE_ftrace.o = -pg
+endif
+
 extra-y := head.o vmlinux.lds
 
 obj-y += exceptions.o \
         hw_exception_handler.o init_task.o intc.o irq.o of_device.o \
         of_platform.o process.o prom.o prom_parse.o ptrace.o \
-        setup.o signal.o sys_microblaze.o timer.o traps.o
+        setup.o signal.o sys_microblaze.o timer.o traps.o reset.o
 
 obj-y += cpu/
 
@@ -16,5 +26,7 @@ obj-$(CONFIG_SELFMOD)		+= selfmod.o
 obj-$(CONFIG_HEART_BEAT)        += heartbeat.o
 obj-$(CONFIG_MODULES)           += microblaze_ksyms.o module.o
 obj-$(CONFIG_MMU)               += misc.o
+obj-$(CONFIG_STACKTRACE)        += stacktrace.o
+obj-$(CONFIG_FUNCTION_TRACER)   += ftrace.o mcount.o
 
 obj-y   += entry$(MMU).o
diff --git a/arch/microblaze/kernel/cpu/Makefile b/arch/microblaze/kernel/cpu/Makefile
index 20646e549271..59cc7bceaf8c 100644
--- a/arch/microblaze/kernel/cpu/Makefile
+++ b/arch/microblaze/kernel/cpu/Makefile
@@ -2,6 +2,10 @@
 # Build the appropriate CPU version support
 #
 
+ifdef CONFIG_FUNCTION_TRACER
+CFLAGS_REMOVE_cache.o = -pg
+endif
+
 EXTRA_CFLAGS += -DCPU_MAJOR=$(CPU_MAJOR) -DCPU_MINOR=$(CPU_MINOR) \
                 -DCPU_REV=$(CPU_REV)
 
diff --git a/arch/microblaze/kernel/cpu/cache.c b/arch/microblaze/kernel/cpu/cache.c
index af866a450125..d9d63831cc2f 100644
--- a/arch/microblaze/kernel/cpu/cache.c
+++ b/arch/microblaze/kernel/cpu/cache.c
@@ -3,7 +3,7 @@
  *
  * Copyright (C) 2007-2009 Michal Simek <monstr@monstr.eu>
  * Copyright (C) 2007-2009 PetaLogix
- * Copyright (C) 2007 John Williams <john.williams@petalogix.com>
+ * Copyright (C) 2007-2009 John Williams <john.williams@petalogix.com>
  *
  * This file is subject to the terms and conditions of the GNU General
  * Public License. See the file COPYING in the main directory of this
@@ -13,243 +13,534 @@
 #include <asm/cacheflush.h>
 #include <linux/cache.h>
 #include <asm/cpuinfo.h>
+#include <asm/pvr.h>
 
-/* Exported functions */
+static inline void __invalidate_flush_icache(unsigned int addr)
+{
+        __asm__ __volatile__ ("wic      %0, r0;"        \
+                                        : : "r" (addr));
+}
+
+static inline void __flush_dcache(unsigned int addr)
+{
+        __asm__ __volatile__ ("wdc.flush        %0, r0;"        \
+                                        : : "r" (addr));
+}
+
+static inline void __invalidate_dcache(unsigned int baseaddr,
+                                                unsigned int offset)
+{
+        __asm__ __volatile__ ("wdc.clear        %0, %1;"        \
+                                        : : "r" (baseaddr), "r" (offset));
+}
 
-void _enable_icache(void)
+static inline void __enable_icache_msr(void)
 {
-        if (cpuinfo.use_icache) {
-#if CONFIG_XILINX_MICROBLAZE0_USE_MSR_INSTR
-                __asm__ __volatile__ ("                                 \
-                                msrset  r0, %0;                         \
-                                nop; "                                  \
-                                :                                       \
-                                : "i" (MSR_ICE)                         \
+        __asm__ __volatile__ (" msrset  r0, %0;         \
+                                nop; "                  \
+                        : : "i" (MSR_ICE) : "memory");
+}
+
+static inline void __disable_icache_msr(void)
+{
+        __asm__ __volatile__ (" msrclr  r0, %0;         \
+                                nop; "                  \
+                        : : "i" (MSR_ICE) : "memory");
+}
+
+static inline void __enable_dcache_msr(void)
+{
+        __asm__ __volatile__ (" msrset  r0, %0;         \
+                                nop; "                  \
+                                :                       \
+                                : "i" (MSR_DCE)         \
                                 : "memory");
-#else
-                __asm__ __volatile__ ("                                 \
-                                mfs     r12, rmsr;                      \
-                                nop;                                    \
-                                ori     r12, r12, %0;                   \
-                                mts     rmsr, r12;                      \
-                                nop; "                                  \
-                                :                                       \
-                                : "i" (MSR_ICE)                         \
-                                : "memory", "r12");
-#endif
-        }
 }
 
-void _disable_icache(void)
+static inline void __disable_dcache_msr(void)
 {
-        if (cpuinfo.use_icache) {
-#if CONFIG_XILINX_MICROBLAZE0_USE_MSR_INSTR
-                __asm__ __volatile__ ("                                 \
-                                msrclr r0, %0;                          \
-                                nop; "                                  \
-                                :                                       \
-                                : "i" (MSR_ICE)                         \
+        __asm__ __volatile__ (" msrclr  r0, %0;         \
+                                nop; "                  \
+                                :                       \
+                                : "i" (MSR_DCE)         \
                                 : "memory");
-#else
-                __asm__ __volatile__ ("                                 \
-                                mfs     r12, rmsr;                      \
-                                nop;                                    \
-                                andi    r12, r12, ~%0;                  \
-                                mts     rmsr, r12;                      \
-                                nop; "                                  \
-                                :                                       \
-                                : "i" (MSR_ICE)                         \
+}
+
+static inline void __enable_icache_nomsr(void)
+{
+        __asm__ __volatile__ (" mfs     r12, rmsr;      \
+                                nop;                    \
+                                ori     r12, r12, %0;   \
+                                mts     rmsr, r12;      \
+                                nop; "                  \
+                                :                       \
+                                : "i" (MSR_ICE)         \
                                 : "memory", "r12");
-#endif
-        }
 }
 
-void _invalidate_icache(unsigned int addr)
+static inline void __disable_icache_nomsr(void)
 {
-        if (cpuinfo.use_icache) {
-                __asm__ __volatile__ ("                                 \
-                                wic     %0, r0"                         \
-                                :                                       \
-                                : "r" (addr));
-        }
+        __asm__ __volatile__ (" mfs     r12, rmsr;      \
+                                nop;                    \
+                                andi    r12, r12, ~%0;  \
+                                mts     rmsr, r12;      \
+                                nop; "                  \
+                                :                       \
+                                : "i" (MSR_ICE)         \
+                                : "memory", "r12");
 }
 
-void _enable_dcache(void)
+static inline void __enable_dcache_nomsr(void)
 {
-        if (cpuinfo.use_dcache) {
-#if CONFIG_XILINX_MICROBLAZE0_USE_MSR_INSTR
-                __asm__ __volatile__ ("                                 \
-                                msrset  r0, %0;                         \
-                                nop; "                                  \
-                                :                                       \
-                                : "i" (MSR_DCE)                         \
-                                : "memory");
-#else
-                __asm__ __volatile__ ("                                 \
-                                mfs     r12, rmsr;                      \
-                                nop;                                    \
-                                ori     r12, r12, %0;                   \
-                                mts     rmsr, r12;                      \
-                                nop; "                                  \
-                                :                                       \
-                                : "i" (MSR_DCE)                 \
+        __asm__ __volatile__ (" mfs     r12, rmsr;      \
+                                nop;                    \
+                                ori     r12, r12, %0;   \
+                                mts     rmsr, r12;      \
+                                nop; "                  \
+                                :                       \
+                                : "i" (MSR_DCE)         \
                                 : "memory", "r12");
-#endif
-        }
 }
 
-void _disable_dcache(void)
+static inline void __disable_dcache_nomsr(void)
 {
-#if CONFIG_XILINX_MICROBLAZE0_USE_MSR_INSTR
-                __asm__ __volatile__ ("                                 \
-                                msrclr  r0, %0;                         \
-                                nop; "                                  \
-                                :                                       \
-                                : "i" (MSR_DCE)                 \
-                                : "memory");
-#else
-                __asm__ __volatile__ ("                                 \
-                                mfs     r12, rmsr;                      \
-                                nop;                                    \
-                                andi    r12, r12, ~%0;                  \
-                                mts     rmsr, r12;                      \
-                                nop; "                                  \
-                                :                                       \
-                                : "i" (MSR_DCE)                 \
+        __asm__ __volatile__ (" mfs     r12, rmsr;      \
+                                nop;                    \
+                                andi    r12, r12, ~%0;  \
+                                mts     rmsr, r12;      \
+                                nop; "                  \
+                                :                       \
+                                : "i" (MSR_DCE)         \
                                 : "memory", "r12");
-#endif
 }
 
-void _invalidate_dcache(unsigned int addr)
+
+/* Helper macro for computing the limits of cache range loops */
+#define CACHE_LOOP_LIMITS(start, end, cache_line_length, cache_size)    \
+do {                                                                    \
+        int align = ~(cache_line_length - 1);                           \
+        end = min(start + cache_size, end);                             \
+        start &= align;                                                 \
+        end = ((end & align) + cache_line_length);                      \
+} while (0);
+
+/*
+ * Helper macro to loop over the specified cache_size/line_length and
+ * execute 'op' on that cacheline
+ */
+#define CACHE_ALL_LOOP(cache_size, line_length, op)                     \
+do {                                                                    \
+        unsigned int len = cache_size;                                  \
+        int step = -line_length;                                        \
+        BUG_ON(step >= 0);                                              \
+                                                                        \
+        __asm__ __volatile__ (" 1:      " #op " %0, r0;                 \
+                                        bgtid   %0, 1b;                 \
+                                        addk    %0, %0, %1;             \
+                                        " : : "r" (len), "r" (step)     \
+                                        : "memory");                    \
+} while (0);
+
+
+#define CACHE_ALL_LOOP2(cache_size, line_length, op)                    \
+do {                                                                    \
+        unsigned int len = cache_size;                                  \
+        int step = -line_length;                                        \
+        BUG_ON(step >= 0);                                              \
+                                                                        \
+        __asm__ __volatile__ (" 1:      " #op " r0, %0;                 \
+                                        bgtid   %0, 1b;                 \
+                                        addk    %0, %0, %1;             \
+                                        " : : "r" (len), "r" (step)     \
+                                        : "memory");                    \
+} while (0);
+
+/* for wdc.flush/clear */
+#define CACHE_RANGE_LOOP_2(start, end, line_length, op)                 \
+do {                                                                    \
+        int step = -line_length;                                        \
+        int count = end - start;                                        \
+        BUG_ON(count <= 0);                                             \
+                                                                        \
+        __asm__ __volatile__ (" 1:      " #op " %0, %1;                 \
+                                        bgtid   %1, 1b;                 \
+                                        addk    %1, %1, %2;             \
+                                        " : : "r" (start), "r" (count), \
+                                        "r" (step) : "memory");         \
+} while (0);
+
+/* It is used only first parameter for OP - for wic, wdc */
+#define CACHE_RANGE_LOOP_1(start, end, line_length, op)                 \
+do {                                                                    \
+        int step = -line_length;                                        \
+        int count = end - start;                                        \
+        BUG_ON(count <= 0);                                             \
+                                                                        \
+        __asm__ __volatile__ (" 1:      addk    %0, %0, %1;             \
+                                        " #op " %0, r0;                 \
+                                        bgtid   %1, 1b;                 \
+                                        addk    %1, %1, %2;             \
+                                        " : : "r" (start), "r" (count), \
+                                        "r" (step) : "memory");         \
+} while (0);
+
+static void __flush_icache_range_msr_irq(unsigned long start, unsigned long end)
 {
-                __asm__ __volatile__ ("                                 \
-                                wdc     %0, r0"                         \
-                                :                                       \
-                                : "r" (addr));
+        unsigned long flags;
+
+        pr_debug("%s: start 0x%x, end 0x%x\n", __func__,
+                                (unsigned int)start, (unsigned int) end);
+
+        CACHE_LOOP_LIMITS(start, end,
+                        cpuinfo.icache_line_length, cpuinfo.icache_size);
+
+        local_irq_save(flags);
+        __disable_icache_msr();
+
+        CACHE_RANGE_LOOP_1(start, end, cpuinfo.icache_line_length, wic);
+
+        __enable_icache_msr();
+        local_irq_restore(flags);
 }
 
-void __invalidate_icache_all(void)
+static void __flush_icache_range_nomsr_irq(unsigned long start,
+                                unsigned long end)
 {
-        unsigned int i;
-        unsigned flags;
+        unsigned long flags;
 
-        if (cpuinfo.use_icache) {
-                local_irq_save(flags);
-                __disable_icache();
+        pr_debug("%s: start 0x%x, end 0x%x\n", __func__,
+                                (unsigned int)start, (unsigned int) end);
 
-                /* Just loop through cache size and invalidate, no need to add
-                        CACHE_BASE address */
-                for (i = 0; i < cpuinfo.icache_size;
-                        i += cpuinfo.icache_line)
-                                __invalidate_icache(i);
+        CACHE_LOOP_LIMITS(start, end,
+                        cpuinfo.icache_line_length, cpuinfo.icache_size);
 
-                __enable_icache();
-                local_irq_restore(flags);
-        }
+        local_irq_save(flags);
+        __disable_icache_nomsr();
+
+        CACHE_RANGE_LOOP_1(start, end, cpuinfo.icache_line_length, wic);
+
+        __enable_icache_nomsr();
+        local_irq_restore(flags);
 }
 
-void __invalidate_icache_range(unsigned long start, unsigned long end)
+static void __flush_icache_range_noirq(unsigned long start,
+                                unsigned long end)
 {
-        unsigned int i;
-        unsigned flags;
-        unsigned int align;
-
-        if (cpuinfo.use_icache) {
-                /*
-                 * No need to cover entire cache range,
-                 * just cover cache footprint
-                 */
-                end = min(start + cpuinfo.icache_size, end);
-                align = ~(cpuinfo.icache_line - 1);
-                start &= align; /* Make sure we are aligned */
-                /* Push end up to the next cache line */
-                end = ((end & align) + cpuinfo.icache_line);
-
-                local_irq_save(flags);
-                __disable_icache();
-
-                for (i = start; i < end; i += cpuinfo.icache_line)
-                        __invalidate_icache(i);
-
-                __enable_icache();
-                local_irq_restore(flags);
-        }
+        pr_debug("%s: start 0x%x, end 0x%x\n", __func__,
+                                (unsigned int)start, (unsigned int) end);
+
+        CACHE_LOOP_LIMITS(start, end,
+                        cpuinfo.icache_line_length, cpuinfo.icache_size);
+        CACHE_RANGE_LOOP_1(start, end, cpuinfo.icache_line_length, wic);
+}
+
+static void __flush_icache_all_msr_irq(void)
+{
+        unsigned long flags;
+
+        pr_debug("%s\n", __func__);
+
+        local_irq_save(flags);
+        __disable_icache_msr();
+
+        CACHE_ALL_LOOP(cpuinfo.icache_size, cpuinfo.icache_line_length, wic);
+
+        __enable_icache_msr();
+        local_irq_restore(flags);
+}
+
+static void __flush_icache_all_nomsr_irq(void)
+{
+        unsigned long flags;
+
+        pr_debug("%s\n", __func__);
+
+        local_irq_save(flags);
+        __disable_icache_nomsr();
+
+        CACHE_ALL_LOOP(cpuinfo.icache_size, cpuinfo.icache_line_length, wic);
+
+        __enable_icache_nomsr();
+        local_irq_restore(flags);
 }
 
-void __invalidate_icache_page(struct vm_area_struct *vma, struct page *page)
+static void __flush_icache_all_noirq(void)
 {
-        __invalidate_icache_all();
+        pr_debug("%s\n", __func__);
+        CACHE_ALL_LOOP(cpuinfo.icache_size, cpuinfo.icache_line_length, wic);
 }
 
-void __invalidate_icache_user_range(struct vm_area_struct *vma,
-                                struct page *page, unsigned long adr,
-                                int len)
+static void __invalidate_dcache_all_msr_irq(void)
 {
-        __invalidate_icache_all();
+        unsigned long flags;
+
+        pr_debug("%s\n", __func__);
+
+        local_irq_save(flags);
+        __disable_dcache_msr();
+
+        CACHE_ALL_LOOP(cpuinfo.dcache_size, cpuinfo.dcache_line_length, wdc);
+
+        __enable_dcache_msr();
+        local_irq_restore(flags);
 }
 
-void __invalidate_cache_sigtramp(unsigned long addr)
+static void __invalidate_dcache_all_nomsr_irq(void)
 {
-        __invalidate_icache_range(addr, addr + 8);
+        unsigned long flags;
+
+        pr_debug("%s\n", __func__);
+
+        local_irq_save(flags);
+        __disable_dcache_nomsr();
+
+        CACHE_ALL_LOOP(cpuinfo.dcache_size, cpuinfo.dcache_line_length, wdc);
+
+        __enable_dcache_nomsr();
+        local_irq_restore(flags);
 }
 
-void __invalidate_dcache_all(void)
+static void __invalidate_dcache_all_noirq_wt(void)
 {
-        unsigned int i;
-        unsigned flags;
-
-        if (cpuinfo.use_dcache) {
-                local_irq_save(flags);
-                __disable_dcache();
-
-                /*
-                 * Just loop through cache size and invalidate,
-                 * no need to add CACHE_BASE address
-                 */
-                for (i = 0; i < cpuinfo.dcache_size;
-                        i += cpuinfo.dcache_line)
-                                __invalidate_dcache(i);
-
-                __enable_dcache();
-                local_irq_restore(flags);
-        }
+        pr_debug("%s\n", __func__);
+        CACHE_ALL_LOOP(cpuinfo.dcache_size, cpuinfo.dcache_line_length, wdc)
 }
 
-void __invalidate_dcache_range(unsigned long start, unsigned long end)
+/* FIXME this is weird - should be only wdc but not work
+ * MS: I am getting bus errors and other weird things */
+static void __invalidate_dcache_all_wb(void)
 {
+        pr_debug("%s\n", __func__);
+        CACHE_ALL_LOOP2(cpuinfo.dcache_size, cpuinfo.dcache_line_length,
+                                        wdc.clear)
+
+#if 0
         unsigned int i;
-        unsigned flags;
-        unsigned int align;
-
-        if (cpuinfo.use_dcache) {
-                /*
-                 * No need to cover entire cache range,
-                 * just cover cache footprint
-                 */
-                end = min(start + cpuinfo.dcache_size, end);
-                align = ~(cpuinfo.dcache_line - 1);
-                start &= align; /* Make sure we are aligned */
-                /* Push end up to the next cache line */
-                end = ((end & align) + cpuinfo.dcache_line);
-                local_irq_save(flags);
-                __disable_dcache();
-
-                for (i = start; i < end; i += cpuinfo.dcache_line)
-                        __invalidate_dcache(i);
-
-                __enable_dcache();
-                local_irq_restore(flags);
-        }
+
+        pr_debug("%s\n", __func__);
+
+        /* Just loop through cache size and invalidate it */
+        for (i = 0; i < cpuinfo.dcache_size; i += cpuinfo.dcache_line_length)
+                        __invalidate_dcache(0, i);
+#endif
+}
+
+static void __invalidate_dcache_range_wb(unsigned long start,
+                                                unsigned long end)
+{
+        pr_debug("%s: start 0x%x, end 0x%x\n", __func__,
+                                (unsigned int)start, (unsigned int) end);
+
+        CACHE_LOOP_LIMITS(start, end,
+                        cpuinfo.dcache_line_length, cpuinfo.dcache_size);
+        CACHE_RANGE_LOOP_2(start, end, cpuinfo.dcache_line_length, wdc.clear);
+}
+
+static void __invalidate_dcache_range_nomsr_wt(unsigned long start,
+                                                        unsigned long end)
+{
+        pr_debug("%s: start 0x%x, end 0x%x\n", __func__,
+                                (unsigned int)start, (unsigned int) end);
+        CACHE_LOOP_LIMITS(start, end,
+                        cpuinfo.dcache_line_length, cpuinfo.dcache_size);
+
+        CACHE_RANGE_LOOP_1(start, end, cpuinfo.dcache_line_length, wdc);
 }
 
-void __invalidate_dcache_page(struct vm_area_struct *vma, struct page *page)
+static void __invalidate_dcache_range_msr_irq_wt(unsigned long start,
+                                                        unsigned long end)
 {
-        __invalidate_dcache_all();
+        unsigned long flags;
+
+        pr_debug("%s: start 0x%x, end 0x%x\n", __func__,
+                                (unsigned int)start, (unsigned int) end);
+        CACHE_LOOP_LIMITS(start, end,
+                        cpuinfo.dcache_line_length, cpuinfo.dcache_size);
+
+        local_irq_save(flags);
+        __disable_dcache_msr();
+
+        CACHE_RANGE_LOOP_1(start, end, cpuinfo.dcache_line_length, wdc);
+
+        __enable_dcache_msr();
+        local_irq_restore(flags);
+}
+
+static void __invalidate_dcache_range_nomsr_irq(unsigned long start,
+                                                        unsigned long end)
+{
+        unsigned long flags;
+
+        pr_debug("%s: start 0x%x, end 0x%x\n", __func__,
+                                (unsigned int)start, (unsigned int) end);
+
+        CACHE_LOOP_LIMITS(start, end,
+                        cpuinfo.dcache_line_length, cpuinfo.dcache_size);
+
+        local_irq_save(flags);
+        __disable_dcache_nomsr();
+
+        CACHE_RANGE_LOOP_1(start, end, cpuinfo.dcache_line_length, wdc);
+
+        __enable_dcache_nomsr();
+        local_irq_restore(flags);
+}
+
+static void __flush_dcache_all_wb(void)
+{
+        pr_debug("%s\n", __func__);
+        CACHE_ALL_LOOP(cpuinfo.dcache_size, cpuinfo.dcache_line_length,
+                                wdc.flush);
 }
 
-void __invalidate_dcache_user_range(struct vm_area_struct *vma,
-                                struct page *page, unsigned long adr,
-                                int len)
+static void __flush_dcache_range_wb(unsigned long start, unsigned long end)
 {
-        __invalidate_dcache_all();
+        pr_debug("%s: start 0x%x, end 0x%x\n", __func__,
+                                (unsigned int)start, (unsigned int) end);
+
+        CACHE_LOOP_LIMITS(start, end,
+                        cpuinfo.dcache_line_length, cpuinfo.dcache_size);
+        CACHE_RANGE_LOOP_2(start, end, cpuinfo.dcache_line_length, wdc.flush);
+}
+
+/* struct for wb caches and for wt caches */
+struct scache *mbc;
+
+/* new wb cache model */
+const struct scache wb_msr = {
+        .ie = __enable_icache_msr,
+        .id = __disable_icache_msr,
+        .ifl = __flush_icache_all_noirq,
+        .iflr = __flush_icache_range_noirq,
+        .iin = __flush_icache_all_noirq,
+        .iinr = __flush_icache_range_noirq,
+        .de = __enable_dcache_msr,
+        .dd = __disable_dcache_msr,
+        .dfl = __flush_dcache_all_wb,
+        .dflr = __flush_dcache_range_wb,
+        .din = __invalidate_dcache_all_wb,
+        .dinr = __invalidate_dcache_range_wb,
+};
+
+/* There is only difference in ie, id, de, dd functions */
+const struct scache wb_nomsr = {
+        .ie = __enable_icache_nomsr,
+        .id = __disable_icache_nomsr,
+        .ifl = __flush_icache_all_noirq,
+        .iflr = __flush_icache_range_noirq,
+        .iin = __flush_icache_all_noirq,
+        .iinr = __flush_icache_range_noirq,
+        .de = __enable_dcache_nomsr,
+        .dd = __disable_dcache_nomsr,
+        .dfl = __flush_dcache_all_wb,
+        .dflr = __flush_dcache_range_wb,
+        .din = __invalidate_dcache_all_wb,
+        .dinr = __invalidate_dcache_range_wb,
+};
+
+/* Old wt cache model with disabling irq and turn off cache */
+const struct scache wt_msr = {
+        .ie = __enable_icache_msr,
+        .id = __disable_icache_msr,
+        .ifl = __flush_icache_all_msr_irq,
+        .iflr = __flush_icache_range_msr_irq,
+        .iin = __flush_icache_all_msr_irq,
+        .iinr = __flush_icache_range_msr_irq,
+        .de = __enable_dcache_msr,
+        .dd = __disable_dcache_msr,
+        .dfl = __invalidate_dcache_all_msr_irq,
+        .dflr = __invalidate_dcache_range_msr_irq_wt,
+        .din = __invalidate_dcache_all_msr_irq,
+        .dinr = __invalidate_dcache_range_msr_irq_wt,
+};
+
+const struct scache wt_nomsr = {
+        .ie = __enable_icache_nomsr,
+        .id = __disable_icache_nomsr,
+        .ifl = __flush_icache_all_nomsr_irq,
+        .iflr = __flush_icache_range_nomsr_irq,
+        .iin = __flush_icache_all_nomsr_irq,
+        .iinr = __flush_icache_range_nomsr_irq,
+        .de = __enable_dcache_nomsr,
+        .dd = __disable_dcache_nomsr,
+        .dfl = __invalidate_dcache_all_nomsr_irq,
+        .dflr = __invalidate_dcache_range_nomsr_irq,
+        .din = __invalidate_dcache_all_nomsr_irq,
+        .dinr = __invalidate_dcache_range_nomsr_irq,
+};
+
+/* New wt cache model for newer Microblaze versions */
+const struct scache wt_msr_noirq = {
+        .ie = __enable_icache_msr,
+        .id = __disable_icache_msr,
+        .ifl = __flush_icache_all_noirq,
+        .iflr = __flush_icache_range_noirq,
+        .iin = __flush_icache_all_noirq,
+        .iinr = __flush_icache_range_noirq,
+        .de = __enable_dcache_msr,
+        .dd = __disable_dcache_msr,
+        .dfl = __invalidate_dcache_all_noirq_wt,
+        .dflr = __invalidate_dcache_range_nomsr_wt,
+        .din = __invalidate_dcache_all_noirq_wt,
+        .dinr = __invalidate_dcache_range_nomsr_wt,
+};
+
+const struct scache wt_nomsr_noirq = {
+        .ie = __enable_icache_nomsr,
+        .id = __disable_icache_nomsr,
+        .ifl = __flush_icache_all_noirq,
+        .iflr = __flush_icache_range_noirq,
+        .iin = __flush_icache_all_noirq,
+        .iinr = __flush_icache_range_noirq,
+        .de = __enable_dcache_nomsr,
+        .dd = __disable_dcache_nomsr,
+        .dfl = __invalidate_dcache_all_noirq_wt,
+        .dflr = __invalidate_dcache_range_nomsr_wt,
+        .din = __invalidate_dcache_all_noirq_wt,
+        .dinr = __invalidate_dcache_range_nomsr_wt,
+};
+
+/* CPU version code for 7.20.c - see arch/microblaze/kernel/cpu/cpuinfo.c */
+#define CPUVER_7_20_A   0x0c
+#define CPUVER_7_20_D   0x0f
+
+#define INFO(s) printk(KERN_INFO "cache: " s " \n");
+
+void microblaze_cache_init(void)
+{
+        if (cpuinfo.use_instr & PVR2_USE_MSR_INSTR) {
+                if (cpuinfo.dcache_wb) {
+                        INFO("wb_msr");
+                        mbc = (struct scache *)&wb_msr;
+                        if (cpuinfo.ver_code < CPUVER_7_20_D) {
+                                /* MS: problem with signal handling - hw bug */
+                                INFO("WB won't work properly");
+                        }
+                } else {
+                        if (cpuinfo.ver_code >= CPUVER_7_20_A) {
+                                INFO("wt_msr_noirq");
+                                mbc = (struct scache *)&wt_msr_noirq;
+                        } else {
+                                INFO("wt_msr");
+                                mbc = (struct scache *)&wt_msr;
+                        }
+                }
+        } else {
+                if (cpuinfo.dcache_wb) {
+                        INFO("wb_nomsr");
+                        mbc = (struct scache *)&wb_nomsr;
+                        if (cpuinfo.ver_code < CPUVER_7_20_D) {
+                                /* MS: problem with signal handling - hw bug */
+                                INFO("WB won't work properly");
+                        }
+                } else {
+                        if (cpuinfo.ver_code >= CPUVER_7_20_A) {
+                                INFO("wt_nomsr_noirq");
+                                mbc = (struct scache *)&wt_nomsr_noirq;
+                        } else {
+                                INFO("wt_nomsr");
+                                mbc = (struct scache *)&wt_nomsr;
+                        }
+                }
+        }
 }
diff --git a/arch/microblaze/kernel/cpu/cpuinfo-pvr-full.c b/arch/microblaze/kernel/cpu/cpuinfo-pvr-full.c
index c259786e7faa..f72dbd66c844 100644
--- a/arch/microblaze/kernel/cpu/cpuinfo-pvr-full.c
+++ b/arch/microblaze/kernel/cpu/cpuinfo-pvr-full.c
@@ -21,8 +21,14 @@
  */
 
 #define CI(c, p) { ci->c = PVR_##p(pvr); }
+
+#if defined(CONFIG_EARLY_PRINTK) && defined(CONFIG_SERIAL_UARTLITE_CONSOLE)
 #define err_printk(x) \
         early_printk("ERROR: Microblaze " x "-different for PVR and DTS\n");
+#else
+#define err_printk(x) \
+        printk(KERN_INFO "ERROR: Microblaze " x "-different for PVR and DTS\n");
+#endif
 
 void set_cpuinfo_pvr_full(struct cpuinfo *ci, struct device_node *cpu)
 {
@@ -70,7 +76,7 @@ void set_cpuinfo_pvr_full(struct cpuinfo *ci, struct device_node *cpu)
         CI(use_icache, USE_ICACHE);
         CI(icache_tagbits, ICACHE_ADDR_TAG_BITS);
         CI(icache_write, ICACHE_ALLOW_WR);
-        CI(icache_line, ICACHE_LINE_LEN);
+        ci->icache_line_length = PVR_ICACHE_LINE_LEN(pvr) << 2;
         CI(icache_size, ICACHE_BYTE_SIZE);
         CI(icache_base, ICACHE_BASEADDR);
         CI(icache_high, ICACHE_HIGHADDR);
@@ -78,11 +84,16 @@ void set_cpuinfo_pvr_full(struct cpuinfo *ci, struct device_node *cpu)
         CI(use_dcache, USE_DCACHE);
         CI(dcache_tagbits, DCACHE_ADDR_TAG_BITS);
         CI(dcache_write, DCACHE_ALLOW_WR);
-        CI(dcache_line, DCACHE_LINE_LEN);
+        ci->dcache_line_length = PVR_DCACHE_LINE_LEN(pvr) << 2;
         CI(dcache_size, DCACHE_BYTE_SIZE);
         CI(dcache_base, DCACHE_BASEADDR);
         CI(dcache_high, DCACHE_HIGHADDR);
 
+        temp = PVR_DCACHE_USE_WRITEBACK(pvr);
+        if (ci->dcache_wb != temp)
+                err_printk("DCACHE WB");
+        ci->dcache_wb = temp;
+
         CI(use_dopb, D_OPB);
         CI(use_iopb, I_OPB);
         CI(use_dlmb, D_LMB);
diff --git a/arch/microblaze/kernel/cpu/cpuinfo-static.c b/arch/microblaze/kernel/cpu/cpuinfo-static.c
index adb448f93d5f..6095aa6b5c88 100644
--- a/arch/microblaze/kernel/cpu/cpuinfo-static.c
+++ b/arch/microblaze/kernel/cpu/cpuinfo-static.c
@@ -72,12 +72,12 @@ void __init set_cpuinfo_static(struct cpuinfo *ci, struct device_node *cpu)
         ci->use_icache = fcpu(cpu, "xlnx,use-icache");
         ci->icache_tagbits = fcpu(cpu, "xlnx,addr-tag-bits");
         ci->icache_write = fcpu(cpu, "xlnx,allow-icache-wr");
-        ci->icache_line = fcpu(cpu, "xlnx,icache-line-len") << 2;
-        if (!ci->icache_line) {
+        ci->icache_line_length = fcpu(cpu, "xlnx,icache-line-len") << 2;
+        if (!ci->icache_line_length) {
                 if (fcpu(cpu, "xlnx,icache-use-fsl"))
-                        ci->icache_line = 4 << 2;
+                        ci->icache_line_length = 4 << 2;
                 else
-                        ci->icache_line = 1 << 2;
+                        ci->icache_line_length = 1 << 2;
         }
         ci->icache_size = fcpu(cpu, "i-cache-size");
         ci->icache_base = fcpu(cpu, "i-cache-baseaddr");
@@ -86,16 +86,17 @@ void __init set_cpuinfo_static(struct cpuinfo *ci, struct device_node *cpu)
         ci->use_dcache = fcpu(cpu, "xlnx,use-dcache");
         ci->dcache_tagbits = fcpu(cpu, "xlnx,dcache-addr-tag");
         ci->dcache_write = fcpu(cpu, "xlnx,allow-dcache-wr");
-        ci->dcache_line = fcpu(cpu, "xlnx,dcache-line-len") << 2;
-        if (!ci->dcache_line) {
+        ci->dcache_line_length = fcpu(cpu, "xlnx,dcache-line-len") << 2;
+        if (!ci->dcache_line_length) {
                 if (fcpu(cpu, "xlnx,dcache-use-fsl"))
-                        ci->dcache_line = 4 << 2;
+                        ci->dcache_line_length = 4 << 2;
                 else
-                        ci->dcache_line = 1 << 2;
+                        ci->dcache_line_length = 1 << 2;
         }
         ci->dcache_size = fcpu(cpu, "d-cache-size");
         ci->dcache_base = fcpu(cpu, "d-cache-baseaddr");
         ci->dcache_high = fcpu(cpu, "d-cache-highaddr");
+        ci->dcache_wb = fcpu(cpu, "xlnx,dcache-use-writeback");
 
         ci->use_dopb = fcpu(cpu, "xlnx,d-opb");
         ci->use_iopb = fcpu(cpu, "xlnx,i-opb");
diff --git a/arch/microblaze/kernel/cpu/cpuinfo.c b/arch/microblaze/kernel/cpu/cpuinfo.c
index 3539babc1c18..991d71311b0e 100644
--- a/arch/microblaze/kernel/cpu/cpuinfo.c
+++ b/arch/microblaze/kernel/cpu/cpuinfo.c
@@ -29,11 +29,8 @@ const struct cpu_ver_key cpu_ver_lookup[] = {
         {"7.20.a", 0x0c},
         {"7.20.b", 0x0d},
         {"7.20.c", 0x0e},
-        /* FIXME There is no keycode defined in MBV for these versions */
-        {"2.10.a", 0x10},
-        {"3.00.a", 0x20},
-        {"4.00.a", 0x30},
-        {"4.00.b", 0x40},
+        {"7.20.d", 0x0f},
+        {"7.30.a", 0x10},
         {NULL, 0},
 };
 
diff --git a/arch/microblaze/kernel/cpu/mb.c b/arch/microblaze/kernel/cpu/mb.c
index 4dcfccdbc364..0c912b2a8e03 100644
--- a/arch/microblaze/kernel/cpu/mb.c
+++ b/arch/microblaze/kernel/cpu/mb.c
@@ -103,11 +103,15 @@ static int show_cpuinfo(struct seq_file *m, void *v)
         else
                 count += seq_printf(m, "Icache:\t\tno\n");
 
-        if (cpuinfo.use_dcache)
+        if (cpuinfo.use_dcache) {
                 count += seq_printf(m,
                                 "Dcache:\t\t%ukB\n",
                                 cpuinfo.dcache_size >> 10);
-        else
+                if (cpuinfo.dcache_wb)
+                        count += seq_printf(m, "\t\twrite-back\n");
+                else
+                        count += seq_printf(m, "\t\twrite-through\n");
+        } else
                 count += seq_printf(m, "Dcache:\t\tno\n");
 
         count += seq_printf(m,
diff --git a/arch/microblaze/kernel/cpu/pvr.c b/arch/microblaze/kernel/cpu/pvr.c
index c9a4340ddd53..9bee9382bf74 100644
--- a/arch/microblaze/kernel/cpu/pvr.c
+++ b/arch/microblaze/kernel/cpu/pvr.c
@@ -45,7 +45,7 @@
 
 int cpu_has_pvr(void)
 {
-        unsigned flags;
+        unsigned long flags;
         unsigned pvr0;
 
         local_save_flags(flags);
diff --git a/arch/microblaze/kernel/entry-nommu.S b/arch/microblaze/kernel/entry-nommu.S
index 9083d85376a4..95b0855802df 100644
--- a/arch/microblaze/kernel/entry-nommu.S
+++ b/arch/microblaze/kernel/entry-nommu.S
@@ -208,8 +208,6 @@ ENTRY(_user_exception)
         lwi     r1, r1, TS_THREAD_INFO          /* get the thread info */
         /* calculate kernel stack pointer */
         addik   r1, r1, THREAD_SIZE - PT_SIZE
-        swi     r11, r0, PER_CPU(R11_SAVE)      /* temporarily save r11 */
-        lwi     r11, r0, PER_CPU(KM)            /* load mode indicator */
 2:
         swi     r11, r1, PT_MODE                /* store the mode */
         lwi     r11, r0, PER_CPU(R11_SAVE)      /* reload r11 */
diff --git a/arch/microblaze/kernel/entry.S b/arch/microblaze/kernel/entry.S
index e3ecb36dd554..3bad4ff49471 100644
--- a/arch/microblaze/kernel/entry.S
+++ b/arch/microblaze/kernel/entry.S
@@ -31,6 +31,8 @@
 #include <linux/errno.h>
 #include <asm/signal.h>
 
+#undef DEBUG
+
 /* The size of a state save frame. */
 #define STATE_SAVE_SIZE         (PT_SIZE + STATE_SAVE_ARG_SPACE)
 
@@ -352,10 +354,12 @@ C_ENTRY(_user_exception):
         add     r12, r12, r12;                  /* convert num -> ptr */
         add     r12, r12, r12;
 
+#ifdef DEBUG
         /* Trac syscalls and stored them to r0_ram */
         lwi     r3, r12, 0x400 + r0_ram
         addi    r3, r3, 1
         swi     r3, r12, 0x400 + r0_ram
+#endif
 
         # Find and jump into the syscall handler.
         lwi     r12, r12, sys_call_table
@@ -496,17 +500,6 @@ C_ENTRY(sys_execve):
         brid    microblaze_execve;      /* Do real work (tail-call).*/
         nop;
 
-C_ENTRY(sys_rt_sigsuspend_wrapper):
-        swi     r3, r1, PTO+PT_R3; /* restore saved r3, r4 registers */
-        swi     r4, r1, PTO+PT_R4;
-        la      r7, r1, PTO;            /* add user context as 3rd arg */
-        brlid   r15, sys_rt_sigsuspend; /* Do real work.*/
-        nop;
-        lwi     r3, r1, PTO+PT_R3; /* restore saved r3, r4 registers */
-        lwi     r4, r1, PTO+PT_R4;
-        bri ret_from_trap /* fall through will not work here due to align */
-        nop;
-
 C_ENTRY(sys_rt_sigreturn_wrapper):
         swi     r3, r1, PTO+PT_R3; /* restore saved r3, r4 registers */
         swi     r4, r1, PTO+PT_R4;
@@ -711,15 +704,11 @@ C_ENTRY(ret_from_exc):
          * (in a possibly modified form) after do_signal returns.
          * store return registers separately because this macros is use
          * for others exceptions */
-        swi     r3, r1, PTO + PT_R3;
-        swi     r4, r1, PTO + PT_R4;
         la      r5, r1, PTO;            /* Arg 1: struct pt_regs *regs */
         add     r6, r0, r0;             /* Arg 2: sigset_t *oldset */
         addi    r7, r0, 0;              /* Arg 3: int in_syscall */
         bralid  r15, do_signal; /* Handle any signals */
         nop;
-        lwi     r3, r1, PTO+PT_R3; /* restore saved r3, r4 registers */
-        lwi     r4, r1, PTO+PT_R4;
 
 /* Finally, return to user state.  */
 1:      swi     r0, r0, PER_CPU(KM);    /* Now officially in user state. */
diff --git a/arch/microblaze/kernel/ftrace.c b/arch/microblaze/kernel/ftrace.c
new file mode 100644
index 000000000000..388b31ca65a1
--- /dev/null
+++ b/arch/microblaze/kernel/ftrace.c
@@ -0,0 +1,237 @@
+/*
+ * Ftrace support for Microblaze.
+ *
+ * Copyright (C) 2009 Michal Simek <monstr@monstr.eu>
+ * Copyright (C) 2009 PetaLogix
+ *
+ * Based on MIPS and PowerPC ftrace code
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+
+#include <asm/cacheflush.h>
+#include <linux/ftrace.h>
+
+#ifdef CONFIG_FUNCTION_GRAPH_TRACER
+/*
+ * Hook the return address and push it in the stack of return addrs
+ * in current thread info.
+ */
+void prepare_ftrace_return(unsigned long *parent, unsigned long self_addr)
+{
+        unsigned long old;
+        int faulted, err;
+        struct ftrace_graph_ent trace;
+        unsigned long return_hooker = (unsigned long)
+                                &return_to_handler;
+
+        if (unlikely(atomic_read(&current->tracing_graph_pause)))
+                return;
+
+        /*
+         * Protect against fault, even if it shouldn't
+         * happen. This tool is too much intrusive to
+         * ignore such a protection.
+         */
+        asm volatile("  1:      lwi     %0, %2, 0;              \
+                        2:      swi     %3, %2, 0;              \
+                                addik   %1, r0, 0;              \
+                        3:                                      \
+                                .section .fixup, \"ax\";        \
+                        4:      brid    3b;                     \
+                                addik   %1, r0, 1;              \
+                                .previous;                      \
+                                .section __ex_table,\"a\";      \
+                                .word   1b,4b;                  \
+                                .word   2b,4b;                  \
+                                .previous;"                     \
+                        : "=&r" (old), "=r" (faulted)
+                        : "r" (parent), "r" (return_hooker)
+        );
+
+        if (unlikely(faulted)) {
+                ftrace_graph_stop();
+                WARN_ON(1);
+                return;
+        }
+
+        err = ftrace_push_return_trace(old, self_addr, &trace.depth, 0);
+        if (err == -EBUSY) {
+                *parent = old;
+                return;
+        }
+
+        trace.func = self_addr;
+        /* Only trace if the calling function expects to */
+        if (!ftrace_graph_entry(&trace)) {
+                current->curr_ret_stack--;
+                *parent = old;
+        }
+}
+#endif /* CONFIG_FUNCTION_GRAPH_TRACER */
+
+#ifdef CONFIG_DYNAMIC_FTRACE
+/* save value to addr - it is save to do it in asm */
+static int ftrace_modify_code(unsigned long addr, unsigned int value)
+{
+        int faulted = 0;
+
+        __asm__ __volatile__("  1:      swi     %2, %1, 0;              \
+                                        addik   %0, r0, 0;              \
+                                2:                                      \
+                                        .section .fixup, \"ax\";        \
+                                3:      brid    2b;                     \
+                                        addik   %0, r0, 1;              \
+                                        .previous;                      \
+                                        .section __ex_table,\"a\";      \
+                                        .word   1b,3b;                  \
+                                        .previous;"                     \
+                                : "=r" (faulted)
+                                : "r" (addr), "r" (value)
+        );
+
+        if (unlikely(faulted))
+                return -EFAULT;
+
+        return 0;
+}
+
+#define MICROBLAZE_NOP 0x80000000
+#define MICROBLAZE_BRI 0xb800000C
+
+static unsigned int recorded; /* if save was or not */
+static unsigned int imm; /* saving whole imm instruction */
+
+/* There are two approaches howto solve ftrace_make nop function - look below */
+#undef USE_FTRACE_NOP
+
+#ifdef USE_FTRACE_NOP
+static unsigned int bralid; /* saving whole bralid instruction */
+#endif
+
+int ftrace_make_nop(struct module *mod,
+                        struct dyn_ftrace *rec, unsigned long addr)
+{
+        /* we have this part of code which we are working with
+         * b000c000        imm     -16384
+         * b9fc8e30        bralid  r15, -29136     // c0008e30 <_mcount>
+         * 80000000        or      r0, r0, r0
+         *
+         * The first solution (!USE_FTRACE_NOP-could be called branch solution)
+         * b000c000        bri  12 (0xC - jump to any other instruction)
+         * b9fc8e30        bralid  r15, -29136     // c0008e30 <_mcount>
+         * 80000000        or      r0, r0, r0
+         * any other instruction
+         *
+         * The second solution (USE_FTRACE_NOP) - no jump just nops
+         * 80000000        or      r0, r0, r0
+         * 80000000        or      r0, r0, r0
+         * 80000000        or      r0, r0, r0
+         */
+        int ret = 0;
+
+        if (recorded == 0) {
+                recorded = 1;
+                imm = *(unsigned int *)rec->ip;
+                pr_debug("%s: imm:0x%x\n", __func__, imm);
+#ifdef USE_FTRACE_NOP
+                bralid = *(unsigned int *)(rec->ip + 4);
+                pr_debug("%s: bralid 0x%x\n", __func__, bralid);
+#endif /* USE_FTRACE_NOP */
+        }
+
+#ifdef USE_FTRACE_NOP
+        ret = ftrace_modify_code(rec->ip, MICROBLAZE_NOP);
+        ret += ftrace_modify_code(rec->ip + 4, MICROBLAZE_NOP);
+#else /* USE_FTRACE_NOP */
+        ret = ftrace_modify_code(rec->ip, MICROBLAZE_BRI);
+#endif /* USE_FTRACE_NOP */
+        return ret;
+}
+
+static int ret_addr; /* initialized as 0 by default */
+
+/* I believe that first is called ftrace_make_nop before this function */
+int ftrace_make_call(struct dyn_ftrace *rec, unsigned long addr)
+{
+        int ret;
+        ret_addr = addr; /* saving where the barrier jump is */
+        pr_debug("%s: addr:0x%x, rec->ip: 0x%x, imm:0x%x\n",
+                __func__, (unsigned int)addr, (unsigned int)rec->ip, imm);
+        ret = ftrace_modify_code(rec->ip, imm);
+#ifdef USE_FTRACE_NOP
+        pr_debug("%s: bralid:0x%x\n", __func__, bralid);
+        ret += ftrace_modify_code(rec->ip + 4, bralid);
+#endif /* USE_FTRACE_NOP */
+        return ret;
+}
+
+int __init ftrace_dyn_arch_init(void *data)
+{
+        /* The return code is retured via data */
+        *(unsigned long *)data = 0;
+
+        return 0;
+}
+
+int ftrace_update_ftrace_func(ftrace_func_t func)
+{
+        unsigned long ip = (unsigned long)(&ftrace_call);
+        unsigned int upper = (unsigned int)func;
+        unsigned int lower = (unsigned int)func;
+        int ret = 0;
+
+        /* create proper saving to ftrace_call poll */
+        upper = 0xb0000000 + (upper >> 16); /* imm func_upper */
+        lower = 0x32800000 + (lower & 0xFFFF); /* addik r20, r0, func_lower */
+
+        pr_debug("%s: func=0x%x, ip=0x%x, upper=0x%x, lower=0x%x\n",
+                __func__, (unsigned int)func, (unsigned int)ip, upper, lower);
+
+        /* save upper and lower code */
+        ret = ftrace_modify_code(ip, upper);
+        ret += ftrace_modify_code(ip + 4, lower);
+
+        /* We just need to remove the rtsd r15, 8 by NOP */
+        BUG_ON(!ret_addr);
+        if (ret_addr)
+                ret += ftrace_modify_code(ret_addr, MICROBLAZE_NOP);
+        else
+                ret = 1; /* fault */
+
+        /* All changes are done - lets do caches consistent */
+        flush_icache();
+        return ret;
+}
+
+#ifdef CONFIG_FUNCTION_GRAPH_TRACER
+unsigned int old_jump; /* saving place for jump instruction */
+
+int ftrace_enable_ftrace_graph_caller(void)
+{
+        unsigned int ret;
+        unsigned long ip = (unsigned long)(&ftrace_call_graph);
+
+        old_jump = *(unsigned int *)ip; /* save jump over instruction */
+        ret = ftrace_modify_code(ip, MICROBLAZE_NOP);
+        flush_icache();
+
+        pr_debug("%s: Replace instruction: 0x%x\n", __func__, old_jump);
+        return ret;
+}
+
+int ftrace_disable_ftrace_graph_caller(void)
+{
+        unsigned int ret;
+        unsigned long ip = (unsigned long)(&ftrace_call_graph);
+
+        ret = ftrace_modify_code(ip, old_jump);
+        flush_icache();
+
+        pr_debug("%s\n", __func__);
+        return ret;
+}
+#endif /* CONFIG_FUNCTION_GRAPH_TRACER */
+#endif /* CONFIG_DYNAMIC_FTRACE */
diff --git a/arch/microblaze/kernel/heartbeat.c b/arch/microblaze/kernel/heartbeat.c
index 1bdf20222b92..522751737cfa 100644
--- a/arch/microblaze/kernel/heartbeat.c
+++ b/arch/microblaze/kernel/heartbeat.c
@@ -45,6 +45,7 @@ void heartbeat(void)
 void setup_heartbeat(void)
 {
         struct device_node *gpio = NULL;
+        int *prop;
         int j;
         char *gpio_list[] = {
                                 "xlnx,xps-gpio-1.00.a",
@@ -58,10 +59,14 @@ void setup_heartbeat(void)
                         break;
         }
 
-        base_addr = *(int *) of_get_property(gpio, "reg", NULL);
-        base_addr = (unsigned long) ioremap(base_addr, PAGE_SIZE);
-        printk(KERN_NOTICE "Heartbeat GPIO at 0x%x\n", base_addr);
+        if (gpio) {
+                base_addr = *(int *) of_get_property(gpio, "reg", NULL);
+                base_addr = (unsigned long) ioremap(base_addr, PAGE_SIZE);
+                printk(KERN_NOTICE "Heartbeat GPIO at 0x%x\n", base_addr);
 
-        if (*(int *) of_get_property(gpio, "xlnx,is-bidir", NULL))
-                out_be32(base_addr + 4, 0); /* GPIO is configured as output */
+                /* GPIO is configured as output */
+                prop = (int *) of_get_property(gpio, "xlnx,is-bidir", NULL);
+                if (prop)
+                        out_be32(base_addr + 4, 0);
+        }
 }
diff --git a/arch/microblaze/kernel/intc.c b/arch/microblaze/kernel/intc.c
index 6eea6f92b84e..03172c1da770 100644
--- a/arch/microblaze/kernel/intc.c
+++ b/arch/microblaze/kernel/intc.c
@@ -42,8 +42,16 @@ unsigned int nr_irq;
 
 static void intc_enable_or_unmask(unsigned int irq)
 {
+        unsigned long mask = 1 << irq;
         pr_debug("enable_or_unmask: %d\n", irq);
-        out_be32(INTC_BASE + SIE, 1 << irq);
+        out_be32(INTC_BASE + SIE, mask);
+
+        /* ack level irqs because they can't be acked during
+         * ack function since the handle_level_irq function
+         * acks the irq before calling the interrupt handler
+         */
+        if (irq_desc[irq].status & IRQ_LEVEL)
+                out_be32(INTC_BASE + IAR, mask);
 }
 
 static void intc_disable_or_mask(unsigned int irq)
diff --git a/arch/microblaze/kernel/irq.c b/arch/microblaze/kernel/irq.c
index 7d5ddd62d4d2..0f06034d1fe0 100644
--- a/arch/microblaze/kernel/irq.c
+++ b/arch/microblaze/kernel/irq.c
@@ -68,7 +68,7 @@ int show_interrupts(struct seq_file *p, void *v)
         }
 
         if (i < nr_irq) {
-                spin_lock_irqsave(&irq_desc[i].lock, flags);
+                raw_spin_lock_irqsave(&irq_desc[i].lock, flags);
                 action = irq_desc[i].action;
                 if (!action)
                         goto skip;
@@ -89,7 +89,7 @@ int show_interrupts(struct seq_file *p, void *v)
 
                 seq_putc(p, '\n');
 skip:
-                spin_unlock_irqrestore(&irq_desc[i].lock, flags);
+                raw_spin_unlock_irqrestore(&irq_desc[i].lock, flags);
         }
         return 0;
 }
diff --git a/arch/microblaze/kernel/mcount.S b/arch/microblaze/kernel/mcount.S
new file mode 100644
index 000000000000..e7eaa7a8cbd3
--- /dev/null
+++ b/arch/microblaze/kernel/mcount.S
@@ -0,0 +1,170 @@
+/*
+ * Low-level ftrace handling
+ *
+ * Copyright (C) 2009 Michal Simek <monstr@monstr.eu>
+ * Copyright (C) 2009 PetaLogix
+ *
+ * This file is subject to the terms and conditions of the GNU General
+ * Public License. See the file COPYING in the main directory of this
+ * archive for more details.
+ */
+
+#include <linux/linkage.h>
+
+#define NOALIGN_ENTRY(name)     .globl name; name:
+
+/* FIXME MS: I think that I don't need to save all regs */
+#define SAVE_REGS               \
+        addik   r1, r1, -120;   \
+        swi     r2, r1, 4;      \
+        swi     r3, r1, 8;      \
+        swi     r4, r1, 12;     \
+        swi     r5, r1, 116;    \
+        swi     r6, r1, 16;     \
+        swi     r7, r1, 20;     \
+        swi     r8, r1, 24;     \
+        swi     r9, r1, 28;     \
+        swi     r10, r1, 32;    \
+        swi     r11, r1, 36;    \
+        swi     r12, r1, 40;    \
+        swi     r13, r1, 44;    \
+        swi     r14, r1, 48;    \
+        swi     r16, r1, 52;    \
+        swi     r17, r1, 56;    \
+        swi     r18, r1, 60;    \
+        swi     r19, r1, 64;    \
+        swi     r20, r1, 68;    \
+        swi     r21, r1, 72;    \
+        swi     r22, r1, 76;    \
+        swi     r23, r1, 80;    \
+        swi     r24, r1, 84;    \
+        swi     r25, r1, 88;    \
+        swi     r26, r1, 92;    \
+        swi     r27, r1, 96;    \
+        swi     r28, r1, 100;   \
+        swi     r29, r1, 104;   \
+        swi     r30, r1, 108;   \
+        swi     r31, r1, 112;
+
+#define RESTORE_REGS            \
+        lwi     r2, r1, 4;      \
+        lwi     r3, r1, 8;      \
+        lwi     r4, r1, 12;     \
+        lwi     r5, r1, 116;    \
+        lwi     r6, r1, 16;     \
+        lwi     r7, r1, 20;     \
+        lwi     r8, r1, 24;     \
+        lwi     r9, r1, 28;     \
+        lwi     r10, r1, 32;    \
+        lwi     r11, r1, 36;    \
+        lwi     r12, r1, 40;    \
+        lwi     r13, r1, 44;    \
+        lwi     r14, r1, 48;    \
+        lwi     r16, r1, 52;    \
+        lwi     r17, r1, 56;    \
+        lwi     r18, r1, 60;    \
+        lwi     r19, r1, 64;    \
+        lwi     r20, r1, 68;    \
+        lwi     r21, r1, 72;    \
+        lwi     r22, r1, 76;    \
+        lwi     r23, r1, 80;    \
+        lwi     r24, r1, 84;    \
+        lwi     r25, r1, 88;    \
+        lwi     r26, r1, 92;    \
+        lwi     r27, r1, 96;    \
+        lwi     r28, r1, 100;   \
+        lwi     r29, r1, 104;   \
+        lwi     r30, r1, 108;   \
+        lwi     r31, r1, 112;   \
+        addik   r1, r1, 120;
+
+ENTRY(ftrace_stub)
+        rtsd    r15, 8;
+        nop;
+
+ENTRY(_mcount)
+#ifdef CONFIG_DYNAMIC_FTRACE
+ENTRY(ftrace_caller)
+        /* MS: It is just barrier which is removed from C code */
+        rtsd    r15, 8
+        nop
+#endif /* CONFIG_DYNAMIC_FTRACE */
+        SAVE_REGS
+        swi     r15, r1, 0;
+        /* MS: HAVE_FUNCTION_TRACE_MCOUNT_TEST begin of checking */
+        lwi     r5, r0, function_trace_stop;
+        bneid   r5, end;
+        nop;
+        /* MS: HAVE_FUNCTION_TRACE_MCOUNT_TEST end of checking */
+#ifdef CONFIG_FUNCTION_GRAPH_TRACER
+#ifndef CONFIG_DYNAMIC_FTRACE
+        lwi     r5, r0, ftrace_graph_return;
+        addik   r6, r0, ftrace_stub; /* asm implementation */
+        cmpu    r5, r5, r6; /* ftrace_graph_return != ftrace_stub */
+        beqid   r5, end_graph_tracer;
+        nop;
+
+        lwi     r6, r0, ftrace_graph_entry;
+        addik   r5, r0, ftrace_graph_entry_stub; /* implemented in C */
+        cmpu    r5, r5, r6; /* ftrace_graph_entry != ftrace_graph_entry_stub */
+        beqid   r5, end_graph_tracer;
+        nop;
+#else /* CONFIG_DYNAMIC_FTRACE */
+NOALIGN_ENTRY(ftrace_call_graph)
+        /* MS: jump over graph function - replaced from C code */
+        bri     end_graph_tracer
+#endif /* CONFIG_DYNAMIC_FTRACE */
+        addik   r5, r1, 120; /* MS: load parent addr */
+        addik   r6, r15, 0; /* MS: load current function addr */
+        bralid  r15, prepare_ftrace_return;
+        nop;
+        /* MS: graph was taken that's why - can jump over function trace */
+        brid    end;
+        nop;
+end_graph_tracer:
+#endif /* CONFIG_FUNCTION_GRAPH_TRACER */
+#ifndef CONFIG_DYNAMIC_FTRACE
+        /* MS: test function trace if is taken or not */
+        lwi     r20, r0, ftrace_trace_function;
+        addik   r6, r0, ftrace_stub;
+        cmpu    r5, r20, r6; /* ftrace_trace_function != ftrace_stub */
+        beqid   r5, end; /* MS: not taken -> jump over */
+        nop;
+#else /* CONFIG_DYNAMIC_FTRACE */
+NOALIGN_ENTRY(ftrace_call)
+/* instruction for setup imm FUNC_part1, addik r20, r0, FUNC_part2 */
+        nop
+        nop
+#endif /* CONFIG_DYNAMIC_FTRACE */
+/* static normal trace */
+        lwi     r6, r1, 120; /* MS: load parent addr */
+        addik   r5, r15, 0; /* MS: load current function addr */
+        /* MS: here is dependency on previous code */
+        brald   r15, r20; /* MS: jump to ftrace handler */
+        nop;
+end:
+        lwi     r15, r1, 0;
+        RESTORE_REGS
+
+        rtsd    r15, 8; /* MS: jump back */
+        nop;
+
+#ifdef CONFIG_FUNCTION_GRAPH_TRACER
+ENTRY(return_to_handler)
+        nop; /* MS: just barrier for rtsd r15, 8 */
+        nop;
+        SAVE_REGS
+        swi     r15, r1, 0;
+
+        /* MS: find out returning address */
+        bralid  r15, ftrace_return_to_handler;
+        nop;
+
+        /* MS: return value from ftrace_return_to_handler is my returning addr
+         * must be before restore regs because I have to restore r3 content */
+        addik   r15, r3, 0;
+        RESTORE_REGS
+
+        rtsd    r15, 8; /* MS: jump back */
+        nop;
+#endif  /* CONFIG_FUNCTION_TRACER */
diff --git a/arch/microblaze/kernel/microblaze_ksyms.c b/arch/microblaze/kernel/microblaze_ksyms.c
index 59ff20e33e0c..bc4dcb7d3861 100644
--- a/arch/microblaze/kernel/microblaze_ksyms.c
+++ b/arch/microblaze/kernel/microblaze_ksyms.c
@@ -18,6 +18,7 @@
 #include <linux/io.h>
 #include <asm/page.h>
 #include <asm/system.h>
+#include <linux/ftrace.h>
 #include <linux/uaccess.h>
 
 /*
@@ -47,3 +48,7 @@ extern void __umodsi3(void);
 EXPORT_SYMBOL(__umodsi3);
 extern char *_ebss;
 EXPORT_SYMBOL_GPL(_ebss);
+#ifdef CONFIG_FUNCTION_TRACER
+extern void _mcount(void);
+EXPORT_SYMBOL(_mcount);
+#endif
diff --git a/arch/microblaze/kernel/process.c b/arch/microblaze/kernel/process.c
index c592d475b3d8..812f1bf06c9e 100644
--- a/arch/microblaze/kernel/process.c
+++ b/arch/microblaze/kernel/process.c
@@ -15,6 +15,7 @@
 #include <linux/bitops.h>
 #include <asm/system.h>
 #include <asm/pgalloc.h>
+#include <asm/cacheflush.h>
 
 void show_regs(struct pt_regs *regs)
 {
diff --git a/arch/microblaze/kernel/reset.c b/arch/microblaze/kernel/reset.c
new file mode 100644
index 000000000000..a1721a33042e
--- /dev/null
+++ b/arch/microblaze/kernel/reset.c
@@ -0,0 +1,140 @@
+/*
+ * Copyright (C) 2009 Michal Simek <monstr@monstr.eu>
+ * Copyright (C) 2009 PetaLogix
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+
+#include <linux/init.h>
+#include <linux/of_platform.h>
+#include <asm/prom.h>
+
+/* Trigger specific functions */
+#ifdef CONFIG_GPIOLIB
+
+#include <linux/of_gpio.h>
+
+static int handle; /* reset pin handle */
+static unsigned int reset_val;
+
+static int of_reset_gpio_handle(void)
+{
+        int ret; /* variable which stored handle reset gpio pin */
+        struct device_node *root; /* root node */
+        struct device_node *gpio; /* gpio node */
+        struct of_gpio_chip *of_gc = NULL;
+        enum of_gpio_flags flags ;
+        const void *gpio_spec;
+
+        /* find out root node */
+        root = of_find_node_by_path("/");
+
+        /* give me handle for gpio node to be possible allocate pin */
+        ret = of_parse_phandles_with_args(root, "hard-reset-gpios",
+                                "#gpio-cells", 0, &gpio, &gpio_spec);
+        if (ret) {
+                pr_debug("%s: can't parse gpios property\n", __func__);
+                goto err0;
+        }
+
+        of_gc = gpio->data;
+        if (!of_gc) {
+                pr_debug("%s: gpio controller %s isn't registered\n",
+                         root->full_name, gpio->full_name);
+                ret = -ENODEV;
+                goto err1;
+        }
+
+        ret = of_gc->xlate(of_gc, root, gpio_spec, &flags);
+        if (ret < 0)
+                goto err1;
+
+        ret += of_gc->gc.base;
+err1:
+        of_node_put(gpio);
+err0:
+        pr_debug("%s exited with status %d\n", __func__, ret);
+        return ret;
+}
+
+void of_platform_reset_gpio_probe(void)
+{
+        int ret;
+        handle = of_reset_gpio_handle();
+
+        if (!gpio_is_valid(handle)) {
+                printk(KERN_INFO "Skipping unavailable RESET gpio %d (%s)\n",
+                                handle, "reset");
+        }
+
+        ret = gpio_request(handle, "reset");
+        if (ret < 0) {
+                printk(KERN_INFO "GPIO pin is already allocated\n");
+                return;
+        }
+
+        /* get current setup value */
+        reset_val = gpio_get_value(handle);
+        /* FIXME maybe worth to perform any action */
+        pr_debug("Reset: Gpio output state: 0x%x\n", reset_val);
+
+        /* Setup GPIO as output */
+        ret = gpio_direction_output(handle, 0);
+        if (ret < 0)
+                goto err;
+
+        /* Setup output direction */
+        gpio_set_value(handle, 0);
+
+        printk(KERN_INFO "RESET: Registered gpio device: %d, current val: %d\n",
+                                                        handle, reset_val);
+        return;
+err:
+        gpio_free(handle);
+        return;
+}
+
+
+static void gpio_system_reset(void)
+{
+        gpio_set_value(handle, 1 - reset_val);
+}
+#else
+#define gpio_system_reset() do {} while (0)
+void of_platform_reset_gpio_probe(void)
+{
+        return;
+}
+#endif
+
+void machine_restart(char *cmd)
+{
+        printk(KERN_NOTICE "Machine restart...\n");
+        gpio_system_reset();
+        dump_stack();
+        while (1)
+                ;
+}
+
+void machine_shutdown(void)
+{
+        printk(KERN_NOTICE "Machine shutdown...\n");
+        while (1)
+                ;
+}
+
+void machine_halt(void)
+{
+        printk(KERN_NOTICE "Machine halt...\n");
+        while (1)
+                ;
+}
+
+void machine_power_off(void)
+{
+        printk(KERN_NOTICE "Machine power off...\n");
+        while (1)
+                ;
+}
diff --git a/arch/microblaze/kernel/setup.c b/arch/microblaze/kernel/setup.c
index 8c1e0f4dcf18..5372b24ad049 100644
--- a/arch/microblaze/kernel/setup.c
+++ b/arch/microblaze/kernel/setup.c
@@ -52,13 +52,12 @@ void __init setup_arch(char **cmdline_p)
         /* irq_early_init(); */
         setup_cpuinfo();
 
-        __invalidate_icache_all();
-        __enable_icache();
+        microblaze_cache_init();
 
-        __invalidate_dcache_all();
-        __enable_dcache();
+        enable_dcache();
 
-        panic_timeout = 120;
+        invalidate_icache();
+        enable_icache();
 
         setup_memory();
 
@@ -131,6 +130,8 @@ void __init machine_early_init(const char *cmdline, unsigned int ram,
                 strlcpy(cmd_line, cmdline, COMMAND_LINE_SIZE);
 #endif
 
+        lockdep_init();
+
 /* initialize device tree for usage in early_printk */
         early_init_devtree((void *)_fdt_start);
 
@@ -186,32 +187,3 @@ static int microblaze_debugfs_init(void)
 }
 arch_initcall(microblaze_debugfs_init);
 #endif
-
-void machine_restart(char *cmd)
-{
-        printk(KERN_NOTICE "Machine restart...\n");
-        dump_stack();
-        while (1)
-                ;
-}
-
-void machine_shutdown(void)
-{
-        printk(KERN_NOTICE "Machine shutdown...\n");
-        while (1)
-                ;
-}
-
-void machine_halt(void)
-{
-        printk(KERN_NOTICE "Machine halt...\n");
-        while (1)
-                ;
-}
-
-void machine_power_off(void)
-{
-        printk(KERN_NOTICE "Machine power off...\n");
-        while (1)
-                ;
-}
diff --git a/arch/microblaze/kernel/signal.c b/arch/microblaze/kernel/signal.c
index 1c80e4fc40ce..d8d3bb396cd6 100644
--- a/arch/microblaze/kernel/signal.c
+++ b/arch/microblaze/kernel/signal.c
@@ -44,7 +44,6 @@
 
 asmlinkage int do_signal(struct pt_regs *regs, sigset_t *oldset, int in_sycall);
 
-
 asmlinkage long
 sys_sigaltstack(const stack_t __user *uss, stack_t __user *uoss,
                 struct pt_regs *regs)
@@ -176,6 +175,11 @@ static void setup_rt_frame(int sig, struct k_sigaction *ka, siginfo_t *info,
         struct rt_sigframe __user *frame;
         int err = 0;
         int signal;
+        unsigned long address = 0;
+#ifdef CONFIG_MMU
+        pmd_t *pmdp;
+        pte_t *ptep;
+#endif
 
         frame = get_sigframe(ka, regs, sizeof(*frame));
 
@@ -216,8 +220,29 @@ static void setup_rt_frame(int sig, struct k_sigaction *ka, siginfo_t *info,
          Negative 8 offset because return is rtsd r15, 8 */
         regs->r15 = ((unsigned long)frame->tramp)-8;
 
-        __invalidate_cache_sigtramp((unsigned long)frame->tramp);
-
+        address = ((unsigned long)frame->tramp);
+#ifdef CONFIG_MMU
+        pmdp = pmd_offset(pud_offset(
+                        pgd_offset(current->mm, address),
+                                        address), address);
+
+        preempt_disable();
+        ptep = pte_offset_map(pmdp, address);
+        if (pte_present(*ptep)) {
+                address = (unsigned long) page_address(pte_page(*ptep));
+                /* MS: I need add offset in page */
+                address += ((unsigned long)frame->tramp) & ~PAGE_MASK;
+                /* MS address is virtual */
+                address = virt_to_phys(address);
+                invalidate_icache_range(address, address + 8);
+                flush_dcache_range(address, address + 8);
+        }
+        pte_unmap(ptep);
+        preempt_enable();
+#else
+        flush_icache_range(address, address + 8);
+        flush_dcache_range(address, address + 8);
+#endif
         if (err)
                 goto give_sigsegv;
 
@@ -233,6 +258,10 @@ static void setup_rt_frame(int sig, struct k_sigaction *ka, siginfo_t *info,
 
         set_fs(USER_DS);
 
+        /* the tracer may want to single-step inside the handler */
+        if (test_thread_flag(TIF_SINGLESTEP))
+                ptrace_notify(SIGTRAP);
+
 #ifdef DEBUG_SIG
         printk(KERN_INFO "SIG deliver (%s:%d): sp=%p pc=%08lx\n",
                 current->comm, current->pid, frame, regs->pc);
diff --git a/arch/microblaze/kernel/stacktrace.c b/arch/microblaze/kernel/stacktrace.c
new file mode 100644
index 000000000000..123692f22647
--- /dev/null
+++ b/arch/microblaze/kernel/stacktrace.c
@@ -0,0 +1,65 @@
+/*
+ * Stack trace support for Microblaze.
+ *
+ * Copyright (C) 2009 Michal Simek <monstr@monstr.eu>
+ * Copyright (C) 2009 PetaLogix
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+
+#include <linux/sched.h>
+#include <linux/stacktrace.h>
+#include <linux/thread_info.h>
+#include <linux/ptrace.h>
+#include <linux/module.h>
+
+/* FIXME initial support */
+void save_stack_trace(struct stack_trace *trace)
+{
+        unsigned long *sp;
+        unsigned long addr;
+        asm("addik %0, r1, 0" : "=r" (sp));
+
+        while (!kstack_end(sp)) {
+                addr = *sp++;
+                if (__kernel_text_address(addr)) {
+                        if (trace->skip > 0)
+                                trace->skip--;
+                        else
+                                trace->entries[trace->nr_entries++] = addr;
+
+                        if (trace->nr_entries >= trace->max_entries)
+                                break;
+                }
+        }
+}
+EXPORT_SYMBOL_GPL(save_stack_trace);
+
+void save_stack_trace_tsk(struct task_struct *tsk, struct stack_trace *trace)
+{
+        unsigned int *sp;
+        unsigned long addr;
+
+        struct thread_info *ti = task_thread_info(tsk);
+
+        if (tsk == current)
+                asm("addik %0, r1, 0" : "=r" (sp));
+        else
+                sp = (unsigned int *)ti->cpu_context.r1;
+
+        while (!kstack_end(sp)) {
+                addr = *sp++;
+                if (__kernel_text_address(addr)) {
+                        if (trace->skip > 0)
+                                trace->skip--;
+                        else
+                                trace->entries[trace->nr_entries++] = addr;
+
+                        if (trace->nr_entries >= trace->max_entries)
+                                break;
+                }
+        }
+}
+EXPORT_SYMBOL_GPL(save_stack_trace_tsk);
diff --git a/arch/microblaze/kernel/sys_microblaze.c b/arch/microblaze/kernel/sys_microblaze.c
index 07cabed4b947..9f3c205fb75b 100644
--- a/arch/microblaze/kernel/sys_microblaze.c
+++ b/arch/microblaze/kernel/sys_microblaze.c
@@ -62,46 +62,14 @@ out:
         return error;
 }
 
-asmlinkage long
-sys_mmap2(unsigned long addr, unsigned long len,
-        unsigned long prot, unsigned long flags,
-        unsigned long fd, unsigned long pgoff)
-{
-        struct file *file = NULL;
-        int ret = -EBADF;
-
-        flags &= ~(MAP_EXECUTABLE | MAP_DENYWRITE);
-        if (!(flags & MAP_ANONYMOUS)) {
-                file = fget(fd);
-                if (!file) {
-                        printk(KERN_INFO "no fd in mmap\r\n");
-                        goto out;
-                }
-        }
-
-        down_write(&current->mm->mmap_sem);
-        ret = do_mmap_pgoff(file, addr, len, prot, flags, pgoff);
-        up_write(&current->mm->mmap_sem);
-        if (file)
-                fput(file);
-out:
-        return ret;
-}
-
 asmlinkage long sys_mmap(unsigned long addr, unsigned long len,
                         unsigned long prot, unsigned long flags,
                         unsigned long fd, off_t pgoff)
 {
-        int err = -EINVAL;
-
-        if (pgoff & ~PAGE_MASK) {
-                printk(KERN_INFO "no pagemask in mmap\r\n");
-                goto out;
-        }
+        if (pgoff & ~PAGE_MASK)
+                return -EINVAL;
 
-        err = sys_mmap2(addr, len, prot, flags, fd, pgoff >> PAGE_SHIFT);
-out:
-        return err;
+        return sys_mmap_pgoff(addr, len, prot, flags, fd, pgoff >> PAGE_SHIFT);
 }
 
 /*
diff --git a/arch/microblaze/kernel/syscall_table.S b/arch/microblaze/kernel/syscall_table.S
index c1ab1dc10898..4088be7d4e29 100644
--- a/arch/microblaze/kernel/syscall_table.S
+++ b/arch/microblaze/kernel/syscall_table.S
@@ -183,7 +183,7 @@ ENTRY(sys_call_table)
         .long sys_rt_sigpending
         .long sys_rt_sigtimedwait
         .long sys_rt_sigqueueinfo
-        .long sys_rt_sigsuspend_wrapper
+        .long sys_rt_sigsuspend
         .long sys_pread64               /* 180 */
         .long sys_pwrite64
         .long sys_chown
@@ -196,7 +196,7 @@ ENTRY(sys_call_table)
         .long sys_ni_syscall            /* reserved for streams2 */
         .long sys_vfork         /* 190 */
         .long sys_getrlimit
-        .long sys_mmap2                 /* mmap2 */
+        .long sys_mmap_pgoff            /* mmap2 */
         .long sys_truncate64
         .long sys_ftruncate64
         .long sys_stat64                /* 195 */
@@ -303,7 +303,7 @@ ENTRY(sys_call_table)
         .long sys_mkdirat
         .long sys_mknodat
         .long sys_fchownat
-        .long sys_ni_syscall
+        .long sys_futimesat
         .long sys_fstatat64             /* 300 */
         .long sys_unlinkat
         .long sys_renameat
diff --git a/arch/microblaze/kernel/timer.c b/arch/microblaze/kernel/timer.c
index 5499deae7fa6..ed61b2f17719 100644
--- a/arch/microblaze/kernel/timer.c
+++ b/arch/microblaze/kernel/timer.c
@@ -183,6 +183,31 @@ static cycle_t microblaze_read(struct clocksource *cs)
         return (cycle_t) (in_be32(TIMER_BASE + TCR1));
 }
 
+static struct timecounter microblaze_tc = {
+        .cc = NULL,
+};
+
+static cycle_t microblaze_cc_read(const struct cyclecounter *cc)
+{
+        return microblaze_read(NULL);
+}
+
+static struct cyclecounter microblaze_cc = {
+        .read = microblaze_cc_read,
+        .mask = CLOCKSOURCE_MASK(32),
+        .shift = 24,
+};
+
+int __init init_microblaze_timecounter(void)
+{
+        microblaze_cc.mult = div_sc(cpuinfo.cpu_clock_freq, NSEC_PER_SEC,
+                                microblaze_cc.shift);
+
+        timecounter_init(&microblaze_tc, &microblaze_cc, sched_clock());
+
+        return 0;
+}
+
 static struct clocksource clocksource_microblaze = {
         .name           = "microblaze_clocksource",
         .rating         = 300,
@@ -204,6 +229,9 @@ static int __init microblaze_clocksource_init(void)
         out_be32(TIMER_BASE + TCSR1, in_be32(TIMER_BASE + TCSR1) & ~TCSR_ENT);
         /* start timer1 - up counting without interrupt */
         out_be32(TIMER_BASE + TCSR1, TCSR_TINT|TCSR_ENT|TCSR_ARHT);
+
+        /* register timecounter - for ftrace support */
+        init_microblaze_timecounter();
         return 0;
 }
 
diff --git a/arch/microblaze/kernel/vmlinux.lds.S b/arch/microblaze/kernel/vmlinux.lds.S
index e704188d7855..5ef619aad634 100644
--- a/arch/microblaze/kernel/vmlinux.lds.S
+++ b/arch/microblaze/kernel/vmlinux.lds.S
@@ -26,11 +26,12 @@ SECTIONS {
                 _stext = . ;
                 *(.text .text.*)
                 *(.fixup)
-               EXIT_TEXT
-               EXIT_CALL
+                EXIT_TEXT
+                EXIT_CALL
                 SCHED_TEXT
                 LOCK_TEXT
                 KPROBES_TEXT
+                IRQENTRY_TEXT
                 . = ALIGN (4) ;
                 _etext = . ;
         }
@@ -86,6 +87,7 @@ SECTIONS {
                 _KERNEL_SDA_BASE_ = _ssro + (_ssro_size / 2) ;
         }
 
+        . = ALIGN(PAGE_SIZE);
         __init_begin = .;
 
         INIT_TEXT_SECTION(PAGE_SIZE)
diff --git a/arch/microblaze/lib/uaccess.c b/arch/microblaze/lib/uaccess.c
index 8eb9df5a26c9..a853fe089c44 100644
--- a/arch/microblaze/lib/uaccess.c
+++ b/arch/microblaze/lib/uaccess.c
@@ -39,3 +39,10 @@ long strncpy_from_user(char *dst, const char __user *src, long count)
                 __do_strncpy_from_user(dst, src, count, res);
         return res;
 }
+
+unsigned long __copy_tofrom_user(void __user *to,
+                const void __user *from, unsigned long size)
+{
+        memcpy(to, from, size);
+        return 0;
+}
diff --git a/arch/microblaze/mm/init.c b/arch/microblaze/mm/init.c
index a44892e7cd5b..a57cedf36715 100644
--- a/arch/microblaze/mm/init.c
+++ b/arch/microblaze/mm/init.c
@@ -41,6 +41,7 @@ char *klimit = _end;
  * have available.
  */
 unsigned long memory_start;
+EXPORT_SYMBOL(memory_start);
 unsigned long memory_end; /* due to mm/nommu.c */
 unsigned long memory_size;
 
diff --git a/arch/microblaze/mm/pgtable.c b/arch/microblaze/mm/pgtable.c
index 46c4ca5d15c5..2820081b21ab 100644
--- a/arch/microblaze/mm/pgtable.c
+++ b/arch/microblaze/mm/pgtable.c
@@ -144,7 +144,6 @@ int map_page(unsigned long va, phys_addr_t pa, int flags)
         pmd_t *pd;
         pte_t *pg;
         int err = -ENOMEM;
-        /* spin_lock(&init_mm.page_table_lock); */
         /* Use upper 10 bits of VA to index the first level map */
         pd = pmd_offset(pgd_offset_k(va), va);
         /* Use middle 10 bits of VA to index the second-level map */
@@ -158,9 +157,7 @@ int map_page(unsigned long va, phys_addr_t pa, int flags)
                 if (mem_init_done)
                         flush_HPTE(0, va, pmd_val(*pd));
                         /* flush_HPTE(0, va, pg); */
-
         }
-        /* spin_unlock(&init_mm.page_table_lock); */
         return err;
 }
 
@@ -182,12 +179,6 @@ void __init adjust_total_lowmem(void)
 #endif
 }
 
-static void show_tmem(unsigned long tmem)
-{
-        volatile unsigned long a;
-        a = a + tmem;
-}
-
 /*
  * Map in all of physical memory starting at CONFIG_KERNEL_START.
  */
@@ -197,7 +188,6 @@ void __init mapin_ram(void)
 
         v = CONFIG_KERNEL_START;
         p = memory_start;
-        show_tmem(memory_size);
         for (s = 0; s < memory_size; s += PAGE_SIZE) {
                 f = _PAGE_PRESENT | _PAGE_ACCESSED |
                                 _PAGE_SHARED | _PAGE_HWEXEC;
diff --git a/arch/microblaze/oprofile/Makefile b/arch/microblaze/oprofile/Makefile
new file mode 100644
index 000000000000..0d0348c8af97
--- /dev/null
+++ b/arch/microblaze/oprofile/Makefile
@@ -0,0 +1,13 @@
+#
+# arch/microblaze/oprofile/Makefile
+#
+
+obj-$(CONFIG_OPROFILE) += oprofile.o
+
+DRIVER_OBJS := $(addprefix ../../../drivers/oprofile/, \
+                oprof.o cpu_buffer.o buffer_sync.o \
+                event_buffer.o oprofile_files.o \
+                oprofilefs.o oprofile_stats.o \
+                timer_int.o )
+
+oprofile-y := $(DRIVER_OBJS) microblaze_oprofile.o
diff --git a/arch/microblaze/oprofile/microblaze_oprofile.c b/arch/microblaze/oprofile/microblaze_oprofile.c
new file mode 100644
index 000000000000..def17e59888e
--- /dev/null
+++ b/arch/microblaze/oprofile/microblaze_oprofile.c
@@ -0,0 +1,22 @@
+/*
+ * Microblaze oprofile code
+ *
+ * Copyright (C) 2009 Michal Simek <monstr@monstr.eu>
+ * Copyright (C) 2009 PetaLogix
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+
+#include <linux/oprofile.h>
+#include <linux/init.h>
+
+int __init oprofile_arch_init(struct oprofile_operations *ops)
+{
+        return -1;
+}
+
+void oprofile_arch_exit(void)
+{
+}
diff --git a/arch/microblaze/platform/Kconfig.platform b/arch/microblaze/platform/Kconfig.platform
index 8e9b4752d3ff..669c7eec293e 100644
--- a/arch/microblaze/platform/Kconfig.platform
+++ b/arch/microblaze/platform/Kconfig.platform
@@ -53,31 +53,12 @@ config OPT_LIB_FUNCTION
 
 config OPT_LIB_ASM
         bool "Optimalized lib function ASM"
-        depends on OPT_LIB_FUNCTION
+        depends on OPT_LIB_FUNCTION && (XILINX_MICROBLAZE0_USE_BARREL = 1)
         default n
         help
           Allows turn on optimalized library function (memcpy and memmove).
           Function are written in asm code.
 
-# This is still a bit broken - disabling for now JW 20070504
-config ALLOW_EDIT_AUTO
-        bool "Permit Display/edit of Kconfig.auto platform settings"
-        default n
-        help
-          Allows the editing of auto-generated platform settings from
-          the Kconfig.auto file. Obviously this does not change the
-          underlying hardware, so be very careful if you go editing
-          these settings.
-
-          Also, if you enable this, and edit various Kconfig.auto
-          settings, YOUR CHANGES WILL BE LOST if you then disable it
-          again. You have been warned!
-
-          If unsure, say no.
-
-comment "Automatic platform settings from Kconfig.auto"
-        depends on ALLOW_EDIT_AUTO
-
 if PLATFORM_GENERIC=y
         source "arch/microblaze/platform/generic/Kconfig.auto"
 endif
diff --git a/arch/microblaze/platform/generic/Kconfig.auto b/arch/microblaze/platform/generic/Kconfig.auto
index fbca22d9c8b9..5d86fc19029d 100644
--- a/arch/microblaze/platform/generic/Kconfig.auto
+++ b/arch/microblaze/platform/generic/Kconfig.auto
@@ -21,7 +21,6 @@
 
 # Definitions for MICROBLAZE0
 comment "Definitions for MICROBLAZE0"
-        depends on ALLOW_EDIT_AUTO
 
 config KERNEL_BASE_ADDR
         hex "Physical address where Linux Kernel is"
@@ -30,33 +29,33 @@ config KERNEL_BASE_ADDR
           BASE Address for kernel
 
 config XILINX_MICROBLAZE0_FAMILY
-        string "Targetted FPGA family" if ALLOW_EDIT_AUTO
+        string "Targetted FPGA family"
         default "virtex5"
 
 config XILINX_MICROBLAZE0_USE_MSR_INSTR
-        int "USE_MSR_INSTR range (0:1)" if ALLOW_EDIT_AUTO
-        default 1
+        int "USE_MSR_INSTR range (0:1)"
+        default 0
 
 config XILINX_MICROBLAZE0_USE_PCMP_INSTR
-        int "USE_PCMP_INSTR range (0:1)" if ALLOW_EDIT_AUTO
-        default 1
+        int "USE_PCMP_INSTR range (0:1)"
+        default 0
 
 config XILINX_MICROBLAZE0_USE_BARREL
-        int "USE_BARREL range (0:1)" if ALLOW_EDIT_AUTO
-        default 1
+        int "USE_BARREL range (0:1)"
+        default 0
 
 config XILINX_MICROBLAZE0_USE_DIV
-        int "USE_DIV range (0:1)" if ALLOW_EDIT_AUTO
-        default 1
+        int "USE_DIV range (0:1)"
+        default 0
 
 config XILINX_MICROBLAZE0_USE_HW_MUL
-        int "USE_HW_MUL values (0=NONE, 1=MUL32, 2=MUL64)" if ALLOW_EDIT_AUTO
-        default 2
+        int "USE_HW_MUL values (0=NONE, 1=MUL32, 2=MUL64)"
+        default 0
 
 config XILINX_MICROBLAZE0_USE_FPU
-        int "USE_FPU values (0=NONE, 1=BASIC, 2=EXTENDED)" if ALLOW_EDIT_AUTO
-        default 2
+        int "USE_FPU values (0=NONE, 1=BASIC, 2=EXTENDED)"
+        default 0
 
 config XILINX_MICROBLAZE0_HW_VER
-        string "Core version number" if ALLOW_EDIT_AUTO
+        string "Core version number"
         default 7.10.d
diff --git a/arch/microblaze/platform/generic/system.dts b/arch/microblaze/platform/generic/system.dts
index 29993f62b30a..2d5c41767cd0 100644
--- a/arch/microblaze/platform/generic/system.dts
+++ b/arch/microblaze/platform/generic/system.dts
@@ -32,11 +32,16 @@
         #address-cells = <1>;
         #size-cells = <1>;
         compatible = "xlnx,microblaze";
+        hard-reset-gpios = <&LEDs_8Bit 2 1>;
         model = "testing";
         DDR2_SDRAM: memory@90000000 {
                 device_type = "memory";
                 reg = < 0x90000000 0x10000000 >;
         } ;
+        aliases {
+                ethernet0 = &Hard_Ethernet_MAC;
+                serial0 = &RS232_Uart_1;
+        } ;
         chosen {
                 bootargs = "console=ttyUL0,115200 highres=on";
                 linux,stdout-path = "/plb@0/serial@84000000";
@@ -127,7 +132,7 @@
         mb_plb: plb@0 {
                 #address-cells = <1>;
                 #size-cells = <1>;
-                compatible = "xlnx,plb-v46-1.03.a", "simple-bus";
+                compatible = "xlnx,plb-v46-1.03.a", "xlnx,plb-v46-1.00.a", "simple-bus";
                 ranges ;
                 FLASH: flash@a0000000 {
                         bank-width = <2>;
@@ -214,12 +219,12 @@
                         #size-cells = <1>;
                         compatible = "xlnx,compound";
                         ethernet@81c00000 {
-                                compatible = "xlnx,xps-ll-temac-1.01.b";
+                                compatible = "xlnx,xps-ll-temac-1.01.b", "xlnx,xps-ll-temac-1.00.a";
                                 device_type = "network";
                                 interrupt-parent = <&xps_intc_0>;
                                 interrupts = < 5 2 >;
                                 llink-connected = <&PIM3>;
-                                local-mac-address = [ 02 00 00 00 00 00 ];
+                                local-mac-address = [ 00 0a 35 00 00 00 ];
                                 reg = < 0x81c00000 0x40 >;
                                 xlnx,bus2core-clk-ratio = <0x1>;
                                 xlnx,phy-type = <0x1>;
@@ -261,6 +266,33 @@
                         xlnx,is-dual = <0x0>;
                         xlnx,tri-default = <0xffffffff>;
                         xlnx,tri-default-2 = <0xffffffff>;
+                        #gpio-cells = <2>;
+                        gpio-controller;
+                } ;
+
+                gpio-leds {
+                        compatible = "gpio-leds";
+
+                        heartbeat {
+                                label = "Heartbeat";
+                                gpios = <&LEDs_8Bit 4 1>;
+                                linux,default-trigger = "heartbeat";
+                        };
+
+                        yellow {
+                                label = "Yellow";
+                                gpios = <&LEDs_8Bit 5 1>;
+                        };
+
+                        red {
+                                label = "Red";
+                                gpios = <&LEDs_8Bit 6 1>;
+                        };
+
+                        green {
+                                label = "Green";
+                                gpios = <&LEDs_8Bit 7 1>;
+                        };
                 } ;
                 RS232_Uart_1: serial@84000000 {
                         clock-frequency = <125000000>;
diff --git a/arch/microblaze/platform/platform.c b/arch/microblaze/platform/platform.c
index 56e0234fa34b..5b89b58c5aed 100644
--- a/arch/microblaze/platform/platform.c
+++ b/arch/microblaze/platform/platform.c
@@ -13,6 +13,7 @@
 #include <linux/init.h>
 #include <linux/of_platform.h>
 #include <asm/prom.h>
+#include <asm/setup.h>
 
 static struct of_device_id xilinx_of_bus_ids[] __initdata = {
         { .compatible = "simple-bus", },
@@ -26,6 +27,7 @@ static struct of_device_id xilinx_of_bus_ids[] __initdata = {
 static int __init microblaze_device_probe(void)
 {
         of_platform_bus_probe(NULL, xilinx_of_bus_ids, NULL);
+        of_platform_reset_gpio_probe();
         return 0;
 }
 device_initcall(microblaze_device_probe);
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index fd7620f025fa..9541171f1220 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -5,9 +5,12 @@ config MIPS
         select HAVE_IDE
         select HAVE_OPROFILE
         select HAVE_ARCH_KGDB
-        # Horrible source of confusion.  Die, die, die ...
-        select EMBEDDED
-        select RTC_LIB if !LEMOTE_FULOONG2E
+        select HAVE_FUNCTION_TRACER
+        select HAVE_FUNCTION_TRACE_MCOUNT_TEST
+        select HAVE_DYNAMIC_FTRACE
+        select HAVE_FTRACE_MCOUNT_RECORD
+        select HAVE_FUNCTION_GRAPH_TRACER
+        select RTC_LIB if !MACH_LOONGSON
 
 mainmenu "Linux/MIPS Kernel Configuration"
 
@@ -22,6 +25,7 @@ choice
 
 config MACH_ALCHEMY
         bool "Alchemy processor based machines"
+        select SYS_SUPPORTS_ZBOOT
 
 config AR7
         bool "Texas Instruments AR7"
@@ -36,6 +40,7 @@ config AR7
         select SYS_HAS_EARLY_PRINTK
         select SYS_SUPPORTS_32BIT_KERNEL
         select SYS_SUPPORTS_LITTLE_ENDIAN
+        select SYS_SUPPORTS_ZBOOT_UART16550
         select GENERIC_GPIO
         select GCD
         select VLYNQ
@@ -43,23 +48,6 @@ config AR7
           Support for the Texas Instruments AR7 System-on-a-Chip
           family: TNETD7100, 7200 and 7300.
 
-config BASLER_EXCITE
-        bool "Basler eXcite smart camera"
-        select CEVT_R4K
-        select CSRC_R4K
-        select DMA_COHERENT
-        select HW_HAS_PCI
-        select IRQ_CPU
-        select IRQ_CPU_RM7K
-        select IRQ_CPU_RM9K
-        select MIPS_RM9122
-        select SYS_HAS_CPU_RM9000
-        select SYS_SUPPORTS_32BIT_KERNEL
-        select SYS_SUPPORTS_BIG_ENDIAN
-        help
-          The eXcite is a smart camera platform manufactured by
-          Basler Vision Technologies AG.
-
 config BCM47XX
         bool "BCM47XX based boards"
         select CEVT_R4K
@@ -192,6 +180,7 @@ config LASAT
 
 config MACH_LOONGSON
         bool "Loongson family of machines"
+        select SYS_SUPPORTS_ZBOOT_UART16550
         help
           This enables the support of Loongson family of machines.
 
@@ -233,6 +222,7 @@ config MIPS_MALTA
         select SYS_SUPPORTS_MIPS_CMP
         select SYS_SUPPORTS_MULTITHREADING
         select SYS_SUPPORTS_SMARTMIPS
+        select SYS_SUPPORTS_ZBOOT
         help
           This enables support for the MIPS Technologies Malta evaluation
           board.
@@ -334,6 +324,24 @@ config PMC_YOSEMITE
           Yosemite is an evaluation board for the RM9000x2 processor
           manufactured by PMC-Sierra.
 
+config POWERTV
+        bool "Cisco PowerTV"
+        select BOOT_ELF32
+        select CEVT_R4K
+        select CPU_MIPSR2_IRQ_VI
+        select CPU_MIPSR2_IRQ_EI
+        select CSRC_POWERTV
+        select DMA_NONCOHERENT
+        select HW_HAS_PCI
+        select SYS_HAS_EARLY_PRINTK
+        select SYS_HAS_CPU_MIPS32_R2
+        select SYS_SUPPORTS_32BIT_KERNEL
+        select SYS_SUPPORTS_BIG_ENDIAN
+        select SYS_SUPPORTS_HIGHMEM
+        select USB_OHCI_LITTLE_ENDIAN
+        help
+          This enables support for the Cisco PowerTV Platform.
+
 config SGI_IP22
         bool "SGI IP22 (Indy/Indigo2)"
         select ARC
@@ -674,11 +682,11 @@ config CAVIUM_OCTEON_REFERENCE_BOARD
 endchoice
 
 source "arch/mips/alchemy/Kconfig"
-source "arch/mips/basler/excite/Kconfig"
 source "arch/mips/bcm63xx/Kconfig"
 source "arch/mips/jazz/Kconfig"
 source "arch/mips/lasat/Kconfig"
 source "arch/mips/pmc-sierra/Kconfig"
+source "arch/mips/powertv/Kconfig"
 source "arch/mips/sgi-ip27/Kconfig"
 source "arch/mips/sibyte/Kconfig"
 source "arch/mips/txx9/Kconfig"
@@ -778,6 +786,9 @@ config CSRC_BCM1480
 config CSRC_IOASIC
         bool
 
+config CSRC_POWERTV
+        bool
+
 config CSRC_R4K_LIB
         bool
 
@@ -806,20 +817,6 @@ config DMA_NONCOHERENT
 config DMA_NEED_PCI_MAP_STATE
         bool
 
-config EARLY_PRINTK
-        bool "Early printk" if EMBEDDED && DEBUG_KERNEL
-        depends on SYS_HAS_EARLY_PRINTK
-        default y
-        help
-          This option enables special console drivers which allow the kernel
-          to print messages very early in the bootup process.
-
-          This is useful for kernel debugging when your machine crashes very
-          early before the console code is initialized. For normal operation,
-          it is not recommended because it looks ugly on some machines and
-          doesn't cooperate with an X server. You should normally say N here,
-          unless you want to debug such a crash.
-
 config SYS_HAS_EARLY_PRINTK
         bool
 
@@ -1069,6 +1066,21 @@ config CPU_LOONGSON2E
           The Loongson 2E processor implements the MIPS III instruction set
           with many extensions.
 
+          It has an internal FPGA northbridge, which is compatiable to
+          bonito64.
+
+config CPU_LOONGSON2F
+        bool "Loongson 2F"
+        depends on SYS_HAS_CPU_LOONGSON2F
+        select CPU_LOONGSON2
+        help
+          The Loongson 2F processor implements the MIPS III instruction set
+          with many extensions.
+
+          Loongson2F have built-in DDR2 and PCIX controller. The PCIX controller
+          have a similar programming interface with FPGA northbridge used in
+          Loongson2E.
+
 config CPU_MIPS32_R1
         bool "MIPS32 Release 1"
         depends on SYS_HAS_CPU_MIPS32_R1
@@ -1294,6 +1306,16 @@ config CPU_CAVIUM_OCTEON
 
 endchoice
 
+config SYS_SUPPORTS_ZBOOT
+        bool
+        select HAVE_KERNEL_GZIP
+        select HAVE_KERNEL_BZIP2
+        select HAVE_KERNEL_LZMA
+
+config SYS_SUPPORTS_ZBOOT_UART16550
+        bool
+        select SYS_SUPPORTS_ZBOOT
+
 config CPU_LOONGSON2
         bool
         select CPU_SUPPORTS_32BIT_KERNEL
@@ -1303,6 +1325,12 @@ config CPU_LOONGSON2
 config SYS_HAS_CPU_LOONGSON2E
         bool
 
+config SYS_HAS_CPU_LOONGSON2F
+        bool
+        select CPU_SUPPORTS_CPUFREQ
+        select CPU_SUPPORTS_ADDRWINCFG if 64BIT
+        select CPU_SUPPORTS_UNCACHED_ACCELERATED
+
 config SYS_HAS_CPU_MIPS32_R1
         bool
 
@@ -1411,8 +1439,17 @@ config CPU_SUPPORTS_32BIT_KERNEL
         bool
 config CPU_SUPPORTS_64BIT_KERNEL
         bool
+config CPU_SUPPORTS_CPUFREQ
+        bool
+config CPU_SUPPORTS_ADDRWINCFG
+        bool
 config CPU_SUPPORTS_HUGEPAGES
         bool
+config CPU_SUPPORTS_UNCACHED_ACCELERATED
+        bool
+config MIPS_PGD_C0_CONTEXT
+        bool
+        default y if 64BIT && CPU_MIPSR2
 
 #
 # Set to y for ptrace access to watch registers.
@@ -2024,15 +2061,6 @@ config STACKTRACE_SUPPORT
 
 source "init/Kconfig"
 
-config PROBE_INITRD_HEADER
-        bool "Probe initrd header created by addinitrd"
-        depends on BLK_DEV_INITRD
-        help
-          Probe initrd header at the last page of kernel image.
-          Say Y here if you are using arch/mips/boot/addinitrd.c to
-          add initrd or initramfs image to the kernel image.
-          Otherwise, say N.
-
 source "kernel/Kconfig.freezer"
 
 menu "Bus options (PCI, PCMCIA, EISA, ISA, TC)"
@@ -2104,6 +2132,7 @@ config MMU
 
 config I8253
         bool
+        select MIPS_EXTERNAL_TIMER
 
 config ZONE_DMA32
         bool
@@ -2180,6 +2209,8 @@ source "kernel/power/Kconfig"
 
 endmenu
 
+source "arch/mips/kernel/cpufreq/Kconfig"
+
 source "net/Kconfig"
 
 source "drivers/Kconfig"
diff --git a/arch/mips/Kconfig.debug b/arch/mips/Kconfig.debug
index 364ca8938807..d2b88a0be519 100644
--- a/arch/mips/Kconfig.debug
+++ b/arch/mips/Kconfig.debug
@@ -6,15 +6,66 @@ config TRACE_IRQFLAGS_SUPPORT
 
 source "lib/Kconfig.debug"
 
+config EARLY_PRINTK
+        bool "Early printk" if EMBEDDED
+        depends on SYS_HAS_EARLY_PRINTK
+        default y
+        help
+          This option enables special console drivers which allow the kernel
+          to print messages very early in the bootup process.
+
+          This is useful for kernel debugging when your machine crashes very
+          early before the console code is initialized. For normal operation,
+          it is not recommended because it looks ugly on some machines and
+          doesn't cooperate with an X server. You should normally say N here,
+          unless you want to debug such a crash.
+
+config CMDLINE_BOOL
+        bool "Built-in kernel command line"
+        default n
+        help
+          For most systems, it is firmware or second stage bootloader that
+          by default specifies the kernel command line options.  However,
+          it might be necessary or advantageous to either override the
+          default kernel command line or add a few extra options to it.
+          For such cases, this option allows you to hardcode your own
+          command line options directly into the kernel.  For that, you
+          should choose 'Y' here, and fill in the extra boot arguments
+          in CONFIG_CMDLINE.
+
+          The built-in options will be concatenated to the default command
+          line if CMDLINE_OVERRIDE is set to 'N'. Otherwise, the default
+          command line will be ignored and replaced by the built-in string.
+
+          Most MIPS systems will normally expect 'N' here and rely upon
+          the command line from the firmware or the second-stage bootloader.
+
 config CMDLINE
         string "Default kernel command string"
+        depends on CMDLINE_BOOL
         default ""
         help
           On some platforms, there is currently no way for the boot loader to
-          pass arguments to the kernel. For these platforms, you can supply
-          some command-line options at build time by entering them here.  In
-          other cases you can specify kernel args so that you don't have
-          to set them up in board prom initialization routines.
+          pass arguments to the kernel.  For these platforms, and for the cases
+          when you want to add some extra options to the command line or ignore
+          the default command line, you can supply some command-line options at
+          build time by entering them here.  In other cases you can specify
+          kernel args so that you don't have to set them up in board prom
+          initialization routines.
+
+          For more information, see the CMDLINE_BOOL and CMDLINE_OVERRIDE
+          options.
+
+config CMDLINE_OVERRIDE
+        bool "Built-in command line overrides firware arguments"
+        default n
+        depends on CMDLINE_BOOL
+        help
+          By setting this option to 'Y' you will have your kernel ignore
+          command line arguments from firmware or second stage bootloader.
+          Instead, the built-in command line will be used exclusively.
+
+          Normally, you will choose 'N' here.
 
 config DEBUG_STACK_USAGE
         bool "Enable stack utilization instrumentation"
diff --git a/arch/mips/Makefile b/arch/mips/Makefile
index 77f5021218d3..1893efd43fca 100644
--- a/arch/mips/Makefile
+++ b/arch/mips/Makefile
@@ -48,7 +48,16 @@ ifneq ($(SUBARCH),$(ARCH))
   endif
 endif
 
+ifndef CONFIG_FUNCTION_TRACER
 cflags-y := -ffunction-sections
+endif
+ifdef CONFIG_FUNCTION_GRAPH_TRACER
+  ifndef KBUILD_MCOUNT_RA_ADDRESS
+    ifeq ($(call cc-option-yn,-mmcount-ra-address), y)
+      cflags-y += -mmcount-ra-address -DKBUILD_MCOUNT_RA_ADDRESS
+    endif
+  endif
+endif
 cflags-y += $(call cc-option, -mno-check-zero-division)
 
 ifdef CONFIG_32BIT
@@ -69,6 +78,7 @@ endif
 
 all-$(CONFIG_BOOT_ELF32)        := $(vmlinux-32)
 all-$(CONFIG_BOOT_ELF64)        := $(vmlinux-64)
+all-$(CONFIG_SYS_SUPPORTS_ZBOOT)+= vmlinuz
 
 #
 # GCC uses -G 0 -mabicalls -fpic as default.  We don't want PIC in the kernel
@@ -124,6 +134,8 @@ cflags-$(CONFIG_CPU_TX49XX)	+= -march=r4600 -Wa,--trap
 cflags-$(CONFIG_CPU_LOONGSON2)  += -Wa,--trap
 cflags-$(CONFIG_CPU_LOONGSON2E) += \
         $(call cc-option,-march=loongson2e,-march=r4600)
+cflags-$(CONFIG_CPU_LOONGSON2F) += \
+        $(call cc-option,-march=loongson2f,-march=r4600)
 
 cflags-$(CONFIG_CPU_MIPS32_R1)  += $(call cc-option,-march=mips32,-mips32 -U_MIPS_ISA -D_MIPS_ISA=_MIPS_ISA_MIPS32) \
                         -Wa,-mips32 -Wa,--trap
@@ -324,6 +336,7 @@ core-$(CONFIG_MACH_LOONGSON) +=arch/mips/loongson/
 cflags-$(CONFIG_MACH_LOONGSON) += -I$(srctree)/arch/mips/include/asm/mach-loongson \
                     -mno-branch-likely
 load-$(CONFIG_LEMOTE_FULOONG2E) +=0xffffffff80100000
+load-$(CONFIG_LEMOTE_MACH2F) +=0xffffffff80200000
 
 #
 # MIPS Malta board
@@ -331,7 +344,7 @@ load-$(CONFIG_LEMOTE_FULOONG2E) +=0xffffffff80100000
 core-$(CONFIG_MIPS_MALTA)       += arch/mips/mti-malta/
 cflags-$(CONFIG_MIPS_MALTA)     += -I$(srctree)/arch/mips/include/asm/mach-malta
 load-$(CONFIG_MIPS_MALTA)       += 0xffffffff80100000
-all-$(CONFIG_MIPS_MALTA)        := vmlinux.bin
+all-$(CONFIG_MIPS_MALTA)        := vmlinuz.bin
 
 #
 # MIPS SIM
@@ -356,13 +369,6 @@ cflags-$(CONFIG_PMC_YOSEMITE)	+= -I$(srctree)/arch/mips/include/asm/mach-yosemit
 load-$(CONFIG_PMC_YOSEMITE)     += 0xffffffff80100000
 
 #
-# Basler eXcite
-#
-core-$(CONFIG_BASLER_EXCITE)    += arch/mips/basler/excite/
-cflags-$(CONFIG_BASLER_EXCITE)  += -I$(srctree)/arch/mips/include/asm/mach-excite
-load-$(CONFIG_BASLER_EXCITE)    += 0x80100000
-
-#
 # LASAT platforms
 #
 core-$(CONFIG_LASAT)            += arch/mips/lasat/
@@ -441,6 +447,13 @@ core-$(CONFIG_NEC_MARKEINS)	+= arch/mips/emma/markeins/
 load-$(CONFIG_NEC_MARKEINS)     += 0xffffffff88100000
 
 #
+# Cisco PowerTV Platform
+#
+core-$(CONFIG_POWERTV)          += arch/mips/powertv/
+cflags-$(CONFIG_POWERTV)        += -I$(srctree)/arch/mips/include/asm/mach-powertv
+load-$(CONFIG_POWERTV)          += 0xffffffff90800000
+
+#
 # SGI IP22 (Indy/Indigo2)
 #
 # Set the load address to >= 0xffffffff88069000 if you want to leave space for
@@ -581,7 +594,7 @@ load-$(CONFIG_SNI_RM)		+= 0xffffffff80600000
 else
 load-$(CONFIG_SNI_RM)           += 0xffffffff80030000
 endif
-all-$(CONFIG_SNI_RM)            := vmlinux.ecoff
+all-$(CONFIG_SNI_RM)            := vmlinuz.ecoff
 
 #
 # Common TXx9
@@ -699,9 +712,23 @@ vmlinux.64: vmlinux
         $(OBJCOPY) -O $(64bit-bfd) $(OBJCOPYFLAGS) $< $@
 
 makeboot =$(Q)$(MAKE) $(build)=arch/mips/boot VMLINUX=$(vmlinux-32) $(1)
+makezboot =$(Q)$(MAKE) $(build)=arch/mips/boot/compressed \
+           VMLINUX_LOAD_ADDRESS=$(load-y) 32bit-bfd=$(32bit-bfd) $(1)
 
 all:    $(all-y)
 
+vmlinuz: vmlinux FORCE
+        +@$(call makezboot,$@)
+
+vmlinuz.bin: vmlinux
+        +@$(call makezboot,$@)
+
+vmlinuz.ecoff: vmlinux
+        +@$(call makezboot,$@)
+
+vmlinuz.srec: vmlinux
+        +@$(call makezboot,$@)
+
 vmlinux.bin: $(vmlinux-32)
         +@$(call makeboot,$@)
 
@@ -726,11 +753,13 @@ endif
 
 install:
         $(Q)install -D -m 755 vmlinux $(INSTALL_PATH)/vmlinux-$(KERNELRELEASE)
+        $(Q)install -D -m 755 vmlinuz $(INSTALL_PATH)/vmlinuz-$(KERNELRELEASE)
         $(Q)install -D -m 644 .config $(INSTALL_PATH)/config-$(KERNELRELEASE)
         $(Q)install -D -m 644 System.map $(INSTALL_PATH)/System.map-$(KERNELRELEASE)
 
 archclean:
         @$(MAKE) $(clean)=arch/mips/boot
+        @$(MAKE) $(clean)=arch/mips/boot/compressed
         @$(MAKE) $(clean)=arch/mips/lasat
 
 define archhelp
@@ -738,10 +767,18 @@ define archhelp
         echo '  vmlinux.ecoff        - ECOFF boot image'
         echo '  vmlinux.bin          - Raw binary boot image'
         echo '  vmlinux.srec         - SREC boot image'
+        echo '  vmlinuz              - Compressed boot(zboot) image'
+        echo '  vmlinuz.ecoff        - ECOFF zboot image'
+        echo '  vmlinuz.bin          - Raw binary zboot image'
+        echo '  vmlinuz.srec         - SREC zboot image'
         echo
         echo '  These will be default as apropriate for a configured platform.'
 endef
 
 CLEAN_FILES += vmlinux.32 \
                vmlinux.64 \
-               vmlinux.ecoff
+               vmlinux.ecoff \
+               vmlinuz \
+               vmlinuz.ecoff \
+               vmlinuz.bin \
+               vmlinuz.srec
diff --git a/arch/mips/ar7/platform.c b/arch/mips/ar7/platform.c
index 835f3f0319ca..85169c08d8dc 100644
--- a/arch/mips/ar7/platform.c
+++ b/arch/mips/ar7/platform.c
@@ -505,7 +505,7 @@ static int __init ar7_register_devices(void)
         int res;
         u32 *bootcr, val;
 #ifdef CONFIG_SERIAL_8250
-        static struct uart_port uart_port[2];
+        static struct uart_port uart_port[2] __initdata;
 
         memset(uart_port, 0, sizeof(struct uart_port) * 2);
 
diff --git a/arch/mips/basler/excite/Kconfig b/arch/mips/basler/excite/Kconfig
deleted file mode 100644
index ba506075608b..000000000000
--- a/arch/mips/basler/excite/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-config BASLER_EXCITE_PROTOTYPE
-        bool "Support for pre-release units"
-        depends on BASLER_EXCITE
-        default n
-        help
-          Pre-series (prototype) units are different from later ones in
-          some ways. Select this option if you have one of these. Please
-          note that a kernel built with this option selected will not be
-          able to run on normal units.
diff --git a/arch/mips/basler/excite/Makefile b/arch/mips/basler/excite/Makefile
deleted file mode 100644
index cff29cf46d03..000000000000
--- a/arch/mips/basler/excite/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# Makefile for Basler eXcite
-#
-
-obj-$(CONFIG_BASLER_EXCITE)     += excite_irq.o excite_prom.o excite_setup.o \
-                                   excite_device.o excite_procfs.o
-
-obj-m                           += excite_iodev.o
diff --git a/arch/mips/basler/excite/excite_device.c b/arch/mips/basler/excite/excite_device.c
deleted file mode 100644
index e00bc2d7f301..000000000000
--- a/arch/mips/basler/excite/excite_device.c
+++ /dev/null
@@ -1,403 +0,0 @@
-/*
- *  Copyright (C) 2004 by Basler Vision Technologies AG
- *  Author: Thomas Koeller <thomas.koeller@baslerweb.com>
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License
- *  along with this program; if not, write to the Free Software
- *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/ioport.h>
-#include <linux/err.h>
-#include <linux/jiffies.h>
-#include <linux/sched.h>
-#include <asm/types.h>
-#include <asm/rm9k-ocd.h>
-
-#include <excite.h>
-#include <rm9k_eth.h>
-#include <rm9k_wdt.h>
-#include <rm9k_xicap.h>
-#include <excite_nandflash.h>
-
-#include "excite_iodev.h"
-
-#define RM9K_GE_UNIT    0
-#define XICAP_UNIT      0
-#define NAND_UNIT       0
-
-#define DLL_TIMEOUT     3               /* seconds */
-
-
-#define RINIT(__start__, __end__, __name__, __parent__) {       \
-        .name   = __name__ "_0",                                \
-        .start  = (__start__),                                  \
-        .end    = (__end__),                                    \
-        .flags  = 0,                                            \
-        .parent = (__parent__)                                  \
-}
-
-#define RINIT_IRQ(__irq__, __name__) {  \
-        .name   = __name__ "_0",        \
-        .start  = (__irq__),            \
-        .end    = (__irq__),            \
-        .flags  = IORESOURCE_IRQ,       \
-        .parent = NULL                  \
-}
-
-
-
-enum {
-        slice_xicap,
-        slice_eth
-};
-
-
-
-static struct resource
-        excite_ctr_resource __maybe_unused = {
-                .name           = "GPI counters",
-                .start          = 0,
-                .end            = 5,
-                .flags          = 0,
-                .parent         = NULL,
-                .sibling        = NULL,
-                .child          = NULL
-        },
-        excite_gpislice_resource __maybe_unused = {
-                .name           = "GPI slices",
-                .start          = 0,
-                .end            = 1,
-                .flags          = 0,
-                .parent         = NULL,
-                .sibling        = NULL,
-                .child          = NULL
-        },
-        excite_mdio_channel_resource __maybe_unused = {
-                .name           = "MDIO channels",
-                .start          = 0,
-                .end            = 1,
-                .flags          = 0,
-                .parent         = NULL,
-                .sibling        = NULL,
-                .child          = NULL
-        },
-        excite_fifomem_resource __maybe_unused = {
-                .name           = "FIFO memory",
-                .start          = 0,
-                .end            = 767,
-                .flags          = 0,
-                .parent         = NULL,
-                .sibling        = NULL,
-                .child          = NULL
-        },
-        excite_scram_resource __maybe_unused = {
-                .name           = "Scratch RAM",
-                .start          = EXCITE_PHYS_SCRAM,
-                .end            = EXCITE_PHYS_SCRAM + EXCITE_SIZE_SCRAM - 1,
-                .flags          = IORESOURCE_MEM,
-                .parent         = NULL,
-                .sibling        = NULL,
-                .child          = NULL
-        },
-        excite_fpga_resource __maybe_unused = {
-                .name           = "System FPGA",
-                .start          = EXCITE_PHYS_FPGA,
-                .end            = EXCITE_PHYS_FPGA + EXCITE_SIZE_FPGA - 1,
-                .flags          = IORESOURCE_MEM,
-                .parent         = NULL,
-                .sibling        = NULL,
-                .child          = NULL
-        },
-        excite_nand_resource __maybe_unused = {
-                .name           = "NAND flash control",
-                .start          = EXCITE_PHYS_NAND,
-                .end            = EXCITE_PHYS_NAND + EXCITE_SIZE_NAND - 1,
-                .flags          = IORESOURCE_MEM,
-                .parent         = NULL,
-                .sibling        = NULL,
-                .child          = NULL
-        },
-        excite_titan_resource __maybe_unused = {
-                .name           = "TITAN registers",
-                .start          = EXCITE_PHYS_TITAN,
-                .end            = EXCITE_PHYS_TITAN + EXCITE_SIZE_TITAN - 1,
-                .flags          = IORESOURCE_MEM,
-                .parent         = NULL,
-                .sibling        = NULL,
-                .child          = NULL
-        };
-
-
-
-static void adjust_resources(struct resource *res, unsigned int n)
-{
-        struct resource *p;
-        const unsigned long mask = IORESOURCE_IO | IORESOURCE_MEM
-                                   | IORESOURCE_IRQ | IORESOURCE_DMA;
-
-        for (p = res; p < res + n; p++) {
-                const struct resource * const parent = p->parent;
-                if (parent) {
-                        p->start += parent->start;
-                        p->end   += parent->start;
-                        p->flags =  parent->flags & mask;
-                }
-        }
-}
-
-
-
-#if defined(CONFIG_EXCITE_FCAP_GPI) || defined(CONFIG_EXCITE_FCAP_GPI_MODULE)
-static struct resource xicap_rsrc[] = {
-        RINIT(0x4840, 0x486f, XICAP_RESOURCE_FIFO_RX, &excite_titan_resource),
-        RINIT(0x4940, 0x494b, XICAP_RESOURCE_FIFO_TX, &excite_titan_resource),
-        RINIT(0x5040, 0x5127, XICAP_RESOURCE_XDMA, &excite_titan_resource),
-        RINIT(0x1000, 0x112f, XICAP_RESOURCE_PKTPROC, &excite_titan_resource),
-        RINIT(0x1100, 0x110f, XICAP_RESOURCE_PKT_STREAM, &excite_fpga_resource),
-        RINIT(0x0800, 0x0bff, XICAP_RESOURCE_DMADESC, &excite_scram_resource),
-        RINIT(slice_xicap, slice_xicap, XICAP_RESOURCE_GPI_SLICE, &excite_gpislice_resource),
-        RINIT(0x0100, 0x02ff, XICAP_RESOURCE_FIFO_BLK, &excite_fifomem_resource),
-        RINIT_IRQ(TITAN_IRQ,  XICAP_RESOURCE_IRQ)
-};
-
-static struct platform_device xicap_pdev = {
-        .name           = XICAP_NAME,
-        .id             = XICAP_UNIT,
-        .num_resources  = ARRAY_SIZE(xicap_rsrc),
-        .resource       = xicap_rsrc
-};
-
-/*
- * Create a platform device for the GPI port that receives the
- * image data from the embedded camera.
- */
-static int __init xicap_devinit(void)
-{
-        unsigned long tend;
-        u32 reg;
-        int retval;
-
-        adjust_resources(xicap_rsrc, ARRAY_SIZE(xicap_rsrc));
-
-        /* Power up the slice and configure it. */
-        reg = titan_readl(CPTC1R);
-        reg &= ~(0x11100 << slice_xicap);
-        titan_writel(reg, CPTC1R);
-
-        /* Enable slice & DLL. */
-        reg= titan_readl(CPRR);
-        reg &= ~(0x00030003 << (slice_xicap * 2));
-        titan_writel(reg, CPRR);
-
-        /* Wait for DLLs to lock */
-        tend = jiffies + DLL_TIMEOUT * HZ;
-        while (time_before(jiffies, tend)) {
-                if (!(~titan_readl(CPDSR) & (0x1 << (slice_xicap * 4))))
-                        break;
-                yield();
-        }
-
-        if (~titan_readl(CPDSR) & (0x1 << (slice_xicap * 4))) {
-                printk(KERN_ERR "%s: DLL not locked after %u seconds\n",
-                       xicap_pdev.name, DLL_TIMEOUT);
-                retval = -ETIME;
-        } else {
-                /* Register platform device */
-                retval = platform_device_register(&xicap_pdev);
-        }
-
-        return retval;
-}
-
-device_initcall(xicap_devinit);
-#endif /* defined(CONFIG_EXCITE_FCAP_GPI) || defined(CONFIG_EXCITE_FCAP_GPI_MODULE) */
-
-
-
-#if defined(CONFIG_WDT_RM9K_GPI) || defined(CONFIG_WDT_RM9K_GPI_MODULE)
-static struct resource wdt_rsrc[] = {
-        RINIT(0, 0, WDT_RESOURCE_COUNTER, &excite_ctr_resource),
-        RINIT(0x0084, 0x008f, WDT_RESOURCE_REGS, &excite_titan_resource),
-        RINIT_IRQ(TITAN_IRQ,  WDT_RESOURCE_IRQ)
-};
-
-static struct platform_device wdt_pdev = {
-        .name           = WDT_NAME,
-        .id             = -1,
-        .num_resources  = ARRAY_SIZE(wdt_rsrc),
-        .resource       = wdt_rsrc
-};
-
-/*
- * Create a platform device for the GPI port that receives the
- * image data from the embedded camera.
- */
-static int __init wdt_devinit(void)
-{
-        adjust_resources(wdt_rsrc, ARRAY_SIZE(wdt_rsrc));
-        return platform_device_register(&wdt_pdev);
-}
-
-device_initcall(wdt_devinit);
-#endif /* defined(CONFIG_WDT_RM9K_GPI) || defined(CONFIG_WDT_RM9K_GPI_MODULE) */
-
-
-
-static struct resource excite_nandflash_rsrc[] = {
-        RINIT(0x2000, 0x201f, EXCITE_NANDFLASH_RESOURCE_REGS,  &excite_nand_resource)
-};
-
-static struct platform_device excite_nandflash_pdev = {
-        .name           = "excite_nand",
-        .id             = NAND_UNIT,
-        .num_resources  = ARRAY_SIZE(excite_nandflash_rsrc),
-        .resource       = excite_nandflash_rsrc
-};
-
-/*
- * Create a platform device for the access to the nand-flash
- * port
- */
-static int __init excite_nandflash_devinit(void)
-{
-        adjust_resources(excite_nandflash_rsrc, ARRAY_SIZE(excite_nandflash_rsrc));
-
-        /* nothing to be done here */
-
-        /* Register platform device */
-        return platform_device_register(&excite_nandflash_pdev);
-}
-
-device_initcall(excite_nandflash_devinit);
-
-
-
-static struct resource iodev_rsrc[] = {
-        RINIT_IRQ(FPGA1_IRQ,  IODEV_RESOURCE_IRQ)
-};
-
-static struct platform_device io_pdev = {
-        .name           = IODEV_NAME,
-        .id             = -1,
-        .num_resources  = ARRAY_SIZE(iodev_rsrc),
-        .resource       = iodev_rsrc
-};
-
-/*
- * Create a platform device for the external I/O ports.
- */
-static int __init io_devinit(void)
-{
-        adjust_resources(iodev_rsrc, ARRAY_SIZE(iodev_rsrc));
-        return platform_device_register(&io_pdev);
-}
-
-device_initcall(io_devinit);
-
-
-
-
-#if defined(CONFIG_RM9K_GE) || defined(CONFIG_RM9K_GE_MODULE)
-static struct resource rm9k_ge_rsrc[] = {
-        RINIT(0x2200, 0x27ff, RM9K_GE_RESOURCE_MAC, &excite_titan_resource),
-        RINIT(0x1800, 0x1fff, RM9K_GE_RESOURCE_MSTAT, &excite_titan_resource),
-        RINIT(0x2000, 0x212f, RM9K_GE_RESOURCE_PKTPROC, &excite_titan_resource),
-        RINIT(0x5140, 0x5227, RM9K_GE_RESOURCE_XDMA, &excite_titan_resource),
-        RINIT(0x4870, 0x489f, RM9K_GE_RESOURCE_FIFO_RX, &excite_titan_resource),
-        RINIT(0x494c, 0x4957, RM9K_GE_RESOURCE_FIFO_TX, &excite_titan_resource),
-        RINIT(0x0000, 0x007f, RM9K_GE_RESOURCE_FIFOMEM_RX, &excite_fifomem_resource),
-        RINIT(0x0080, 0x00ff, RM9K_GE_RESOURCE_FIFOMEM_TX, &excite_fifomem_resource),
-        RINIT(0x0180, 0x019f, RM9K_GE_RESOURCE_PHY, &excite_titan_resource),
-        RINIT(0x0000, 0x03ff, RM9K_GE_RESOURCE_DMADESC_RX, &excite_scram_resource),
-        RINIT(0x0400, 0x07ff, RM9K_GE_RESOURCE_DMADESC_TX, &excite_scram_resource),
-        RINIT(slice_eth, slice_eth, RM9K_GE_RESOURCE_GPI_SLICE, &excite_gpislice_resource),
-        RINIT(0, 0, RM9K_GE_RESOURCE_MDIO_CHANNEL, &excite_mdio_channel_resource),
-        RINIT_IRQ(TITAN_IRQ,  RM9K_GE_RESOURCE_IRQ_MAIN),
-        RINIT_IRQ(PHY_IRQ, RM9K_GE_RESOURCE_IRQ_PHY)
-};
-
-static struct platform_device rm9k_ge_pdev = {
-        .name           = RM9K_GE_NAME,
-        .id             = RM9K_GE_UNIT,
-        .num_resources  = ARRAY_SIZE(rm9k_ge_rsrc),
-        .resource       = rm9k_ge_rsrc
-};
-
-
-
-/*
- * Create a platform device for the Ethernet port.
- */
-static int __init rm9k_ge_devinit(void)
-{
-        u32 reg;
-
-        adjust_resources(rm9k_ge_rsrc, ARRAY_SIZE(rm9k_ge_rsrc));
-
-        /* Power up the slice and configure it. */
-        reg = titan_readl(CPTC1R);
-        reg &= ~(0x11000 << slice_eth);
-        reg |= 0x100 << slice_eth;
-        titan_writel(reg, CPTC1R);
-
-        /* Take the MAC out of reset, reset the DLLs. */
-        reg = titan_readl(CPRR);
-        reg &= ~(0x00030000 << (slice_eth * 2));
-        reg |= 0x3 << (slice_eth * 2);
-        titan_writel(reg, CPRR);
-
-        return platform_device_register(&rm9k_ge_pdev);
-}
-
-device_initcall(rm9k_ge_devinit);
-#endif /* defined(CONFIG_RM9K_GE) || defined(CONFIG_RM9K_GE_MODULE) */
-
-
-
-static int __init excite_setup_devs(void)
-{
-        int res;
-        u32 reg;
-
-        /* Enable xdma and fifo interrupts */
-        reg = titan_readl(0x0050);
-        titan_writel(reg | 0x18000000, 0x0050);
-
-        res = request_resource(&iomem_resource, &excite_titan_resource);
-        if (res)
-                return res;
-        res = request_resource(&iomem_resource, &excite_scram_resource);
-        if (res)
-                return res;
-        res = request_resource(&iomem_resource, &excite_fpga_resource);
-        if (res)
-                return res;
-        res = request_resource(&iomem_resource, &excite_nand_resource);
-        if (res)
-                return res;
-        excite_fpga_resource.flags = excite_fpga_resource.parent->flags &
-                                   ( IORESOURCE_IO | IORESOURCE_MEM
-                                   | IORESOURCE_IRQ | IORESOURCE_DMA);
-        excite_nand_resource.flags = excite_nand_resource.parent->flags &
-                                   ( IORESOURCE_IO | IORESOURCE_MEM
-                                   | IORESOURCE_IRQ | IORESOURCE_DMA);
-
-        return 0;
-}
-
-arch_initcall(excite_setup_devs);
-
diff --git a/arch/mips/basler/excite/excite_iodev.c b/arch/mips/basler/excite/excite_iodev.c
deleted file mode 100644
index 938b1d0b7652..000000000000
--- a/arch/mips/basler/excite/excite_iodev.c
+++ /dev/null
@@ -1,178 +0,0 @@
-/*
- *  Copyright (C) 2005 by Basler Vision Technologies AG
- *  Author: Thomas Koeller <thomas.koeller@baslerweb.com>
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License
- *  along with this program; if not, write to the Free Software
- *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-
-#include <linux/compiler.h>
-#include <linux/init.h>
-#include <linux/module.h>
-#include <linux/sched.h>
-#include <linux/wait.h>
-#include <linux/poll.h>
-#include <linux/interrupt.h>
-#include <linux/platform_device.h>
-#include <linux/miscdevice.h>
-#include <linux/smp_lock.h>
-
-#include "excite_iodev.h"
-
-
-
-static const struct resource *iodev_get_resource(struct platform_device *, const char *, unsigned int);
-static int __init iodev_probe(struct platform_device *);
-static int __exit iodev_remove(struct platform_device *);
-static int iodev_open(struct inode *, struct file *);
-static int iodev_release(struct inode *, struct file *);
-static ssize_t iodev_read(struct file *, char __user *, size_t s, loff_t *);
-static unsigned int iodev_poll(struct file *, struct poll_table_struct *);
-static irqreturn_t iodev_irqhdl(int, void *);
-
-
-
-static const char iodev_name[] = "iodev";
-static unsigned int iodev_irq;
-static DECLARE_WAIT_QUEUE_HEAD(wq);
-
-
-
-static const struct file_operations fops =
-{
-        .owner          = THIS_MODULE,
-        .open           = iodev_open,
-        .release        = iodev_release,
-        .read           = iodev_read,
-        .poll           = iodev_poll
-};
-
-static struct miscdevice miscdev =
-{
-        .minor          = MISC_DYNAMIC_MINOR,
-        .name           = iodev_name,
-        .fops           = &fops
-};
-
-static struct platform_driver iodev_driver = {
-        .driver = {
-                .name           = iodev_name,
-                .owner          = THIS_MODULE,
-        },
-        .probe          = iodev_probe,
-        .remove         = __devexit_p(iodev_remove),
-};
-
-
-
-static const struct resource *
-iodev_get_resource(struct platform_device *pdv, const char *name,
-                     unsigned int type)
-{
-        char buf[80];
-        if (snprintf(buf, sizeof buf, "%s_0", name) >= sizeof buf)
-                return NULL;
-        return platform_get_resource_byname(pdv, type, buf);
-}
-
-
-
-/* No hotplugging on the platform bus - use __init */
-static int __init iodev_probe(struct platform_device *dev)
-{
-        const struct resource * const ri =
-                iodev_get_resource(dev, IODEV_RESOURCE_IRQ, IORESOURCE_IRQ);
-
-        if (unlikely(!ri))
-                return -ENXIO;
-
-        iodev_irq = ri->start;
-        return misc_register(&miscdev);
-}
-
-
-
-static int __exit iodev_remove(struct platform_device *dev)
-{
-        return misc_deregister(&miscdev);
-}
-
-static int iodev_open(struct inode *i, struct file *f)
-{
-        int ret;
-
-        ret = request_irq(iodev_irq, iodev_irqhdl, IRQF_DISABLED,
-                           iodev_name, &miscdev);
-
-        return ret;
-}
-
-static int iodev_release(struct inode *i, struct file *f)
-{
-        free_irq(iodev_irq, &miscdev);
-        return 0;
-}
-
-
-
-
-static ssize_t
-iodev_read(struct file *f, char __user *d, size_t s, loff_t *o)
-{
-        ssize_t ret;
-        DEFINE_WAIT(w);
-
-        prepare_to_wait(&wq, &w, TASK_INTERRUPTIBLE);
-        if (!signal_pending(current))
-                schedule();
-        ret = signal_pending(current) ? -ERESTARTSYS : 0;
-        finish_wait(&wq, &w);
-        return ret;
-}
-
-
-static unsigned int iodev_poll(struct file *f, struct poll_table_struct *p)
-{
-        poll_wait(f, &wq, p);
-        return POLLOUT | POLLWRNORM;
-}
-
-static irqreturn_t iodev_irqhdl(int irq, void *ctxt)
-{
-        wake_up(&wq);
-
-        return IRQ_HANDLED;
-}
-
-static int __init iodev_init_module(void)
-{
-        return platform_driver_register(&iodev_driver);
-}
-
-
-
-static void __exit iodev_cleanup_module(void)
-{
-        platform_driver_unregister(&iodev_driver);
-}
-
-module_init(iodev_init_module);
-module_exit(iodev_cleanup_module);
-
-
-
-MODULE_AUTHOR("Thomas Koeller <thomas.koeller@baslerweb.com>");
-MODULE_DESCRIPTION("Basler eXcite i/o interrupt handler");
-MODULE_VERSION("0.0");
-MODULE_LICENSE("GPL");
diff --git a/arch/mips/basler/excite/excite_iodev.h b/arch/mips/basler/excite/excite_iodev.h
deleted file mode 100644
index cbfbb5d2ee62..000000000000
--- a/arch/mips/basler/excite/excite_iodev.h
+++ /dev/null
@@ -1,10 +0,0 @@
-#ifndef __EXCITE_IODEV_H__
-#define __EXCITE_IODEV_H__
-
-/* Device name */
-#define IODEV_NAME              "iodev"
-
-/* Resource names */
-#define IODEV_RESOURCE_IRQ      "excite_iodev_irq"
-
-#endif /* __EXCITE_IODEV_H__ */
diff --git a/arch/mips/basler/excite/excite_irq.c b/arch/mips/basler/excite/excite_irq.c
deleted file mode 100644
index 934e0a6b1011..000000000000
--- a/arch/mips/basler/excite/excite_irq.c
+++ /dev/null
@@ -1,122 +0,0 @@
-/*
- *  Copyright (C) by Basler Vision Technologies AG
- *  Author: Thomas Koeller <thomas.koeller@baslereb.com>
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License
- *  along with this program; if not, write to the Free Software
- *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-
-#include <linux/errno.h>
-#include <linux/init.h>
-#include <linux/kernel_stat.h>
-#include <linux/module.h>
-#include <linux/signal.h>
-#include <linux/sched.h>
-#include <linux/types.h>
-#include <linux/interrupt.h>
-#include <linux/ioport.h>
-#include <linux/timex.h>
-#include <linux/slab.h>
-#include <linux/random.h>
-#include <linux/bitops.h>
-#include <asm/bootinfo.h>
-#include <asm/io.h>
-#include <asm/irq.h>
-#include <asm/irq_cpu.h>
-#include <asm/mipsregs.h>
-#include <asm/system.h>
-#include <asm/rm9k-ocd.h>
-
-#include <excite.h>
-
-extern asmlinkage void excite_handle_int(void);
-
-/*
- * Initialize the interrupt handler
- */
-void __init arch_init_irq(void)
-{
-        mips_cpu_irq_init();
-        rm7k_cpu_irq_init();
-        rm9k_cpu_irq_init();
-}
-
-asmlinkage void plat_irq_dispatch(void)
-{
-        const u32
-                interrupts = read_c0_cause() >> 8,
-                mask = ((read_c0_status() >> 8) & 0x000000ff) |
-                       (read_c0_intcontrol() & 0x0000ff00),
-                pending = interrupts & mask;
-        u32 msgintflags, msgintmask, msgint;
-
-        /* process timer interrupt */
-        if (pending & (1 << TIMER_IRQ)) {
-                do_IRQ(TIMER_IRQ);
-                return;
-        }
-
-        /* Process PCI interrupts */
-#if USB_IRQ < 10
-        msgintflags = ocd_readl(INTP0Status0 + (USB_MSGINT / 0x20 * 0x10));
-        msgintmask  = ocd_readl(INTP0Mask0 + (USB_MSGINT / 0x20 * 0x10));
-        msgint      = msgintflags & msgintmask & (0x1 << (USB_MSGINT % 0x20));
-        if ((pending & (1 << USB_IRQ)) && msgint) {
-#else
-        if (pending & (1 << USB_IRQ)) {
-#endif
-                do_IRQ(USB_IRQ);
-                return;
-        }
-
-        /* Process TITAN interrupts */
-        msgintflags = ocd_readl(INTP0Status0 + (TITAN_MSGINT / 0x20 * 0x10));
-        msgintmask  = ocd_readl(INTP0Mask0 + (TITAN_MSGINT / 0x20 * 0x10));
-        msgint      = msgintflags & msgintmask & (0x1 << (TITAN_MSGINT % 0x20));
-        if ((pending & (1 << TITAN_IRQ)) && msgint) {
-                ocd_writel(msgint, INTP0Clear0 + (TITAN_MSGINT / 0x20 * 0x10));
-                do_IRQ(TITAN_IRQ);
-                return;
-        }
-
-        /* Process FPGA line #0 interrupts */
-        msgintflags = ocd_readl(INTP0Status0 + (FPGA0_MSGINT / 0x20 * 0x10));
-        msgintmask  = ocd_readl(INTP0Mask0 + (FPGA0_MSGINT / 0x20 * 0x10));
-        msgint      = msgintflags & msgintmask & (0x1 << (FPGA0_MSGINT % 0x20));
-        if ((pending & (1 << FPGA0_IRQ)) && msgint) {
-                do_IRQ(FPGA0_IRQ);
-                return;
-        }
-
-        /* Process FPGA line #1 interrupts */
-        msgintflags = ocd_readl(INTP0Status0 + (FPGA1_MSGINT / 0x20 * 0x10));
-        msgintmask  = ocd_readl(INTP0Mask0 + (FPGA1_MSGINT / 0x20 * 0x10));
-        msgint      = msgintflags & msgintmask & (0x1 << (FPGA1_MSGINT % 0x20));
-        if ((pending & (1 << FPGA1_IRQ)) && msgint) {
-                do_IRQ(FPGA1_IRQ);
-                return;
-        }
-
-        /* Process PHY interrupts */
-        msgintflags = ocd_readl(INTP0Status0 + (PHY_MSGINT / 0x20 * 0x10));
-        msgintmask  = ocd_readl(INTP0Mask0 + (PHY_MSGINT / 0x20 * 0x10));
-        msgint      = msgintflags & msgintmask & (0x1 << (PHY_MSGINT % 0x20));
-        if ((pending & (1 << PHY_IRQ)) && msgint) {
-                do_IRQ(PHY_IRQ);
-                return;
-        }
-
-        /* Process spurious interrupts */
-        spurious_interrupt();
-}
diff --git a/arch/mips/basler/excite/excite_procfs.c b/arch/mips/basler/excite/excite_procfs.c
deleted file mode 100644
index 08923e6825b5..000000000000
--- a/arch/mips/basler/excite/excite_procfs.c
+++ /dev/null
@@ -1,92 +0,0 @@
-/*
- *  Copyright (C) 2004, 2005 by Basler Vision Technologies AG
- *  Author: Thomas Koeller <thomas.koeller@baslerweb.com>
- *
- *  Procfs support for Basler eXcite
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License
- *  along with this program; if not, write to the Free Software
- *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#include <linux/module.h>
-#include <linux/proc_fs.h>
-#include <linux/seq_file.h>
-#include <linux/stat.h>
-#include <asm/page.h>
-#include <asm/io.h>
-#include <asm/system.h>
-#include <asm/rm9k-ocd.h>
-
-#include <excite.h>
-
-static int excite_unit_id_proc_show(struct seq_file *m, void *v)
-{
-        seq_printf(m, "%06x", unit_id);
-        return 0;
-}
-
-static int excite_unit_id_proc_open(struct inode *inode, struct file *file)
-{
-        return single_open(file, excite_unit_id_proc_show, NULL);
-}
-
-static const struct file_operations excite_unit_id_proc_fops = {
-        .owner          = THIS_MODULE,
-        .open           = excite_unit_id_proc_open,
-        .read           = seq_read,
-        .llseek         = seq_lseek,
-        .release        = single_release,
-};
-
-static int
-excite_bootrom_read(char *page, char **start, off_t off, int count,
-                  int *eof, void *data)
-{
-        void __iomem * src;
-
-        if (off >= EXCITE_SIZE_BOOTROM) {
-                *eof = 1;
-                return 0;
-        }
-
-        if ((off + count) > EXCITE_SIZE_BOOTROM)
-                count = EXCITE_SIZE_BOOTROM - off;
-
-        src = ioremap(EXCITE_PHYS_BOOTROM + off, count);
-        if (src) {
-                memcpy_fromio(page, src, count);
-                iounmap(src);
-                *start = page;
-        } else {
-                count = -ENOMEM;
-        }
-
-        return count;
-}
-
-void excite_procfs_init(void)
-{
-        /* Create & populate /proc/excite */
-        struct proc_dir_entry * const pdir = proc_mkdir("excite", NULL);
-        if (pdir) {
-                struct proc_dir_entry * e;
-
-                e = proc_create("unit_id", S_IRUGO, pdir,
-                                &excite_unit_id_proc_fops);
-                if (e) e->size = 6;
-
-                e = create_proc_read_entry("bootrom", S_IRUGO, pdir,
-                                           excite_bootrom_read, NULL);
-                if (e) e->size = EXCITE_SIZE_BOOTROM;
-        }
-}
diff --git a/arch/mips/basler/excite/excite_prom.c b/arch/mips/basler/excite/excite_prom.c
deleted file mode 100644
index 68d8bc597e34..000000000000
--- a/arch/mips/basler/excite/excite_prom.c
+++ /dev/null
@@ -1,144 +0,0 @@
-/*
- *  Copyright (C) 2004, 2005 by Thomas Koeller (thomas.koeller@baslerweb.com)
- *  Based on the PMC-Sierra Yosemite board support by Ralf Baechle and
- *  Manish Lachwani.
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License
- *  along with this program; if not, write to the Free Software
- *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-
-#include <linux/init.h>
-#include <linux/sched.h>
-#include <linux/mm.h>
-#include <linux/delay.h>
-#include <linux/smp.h>
-#include <linux/module.h>
-#include <asm/io.h>
-#include <asm/pgtable.h>
-#include <asm/processor.h>
-#include <asm/reboot.h>
-#include <asm/system.h>
-#include <asm/bootinfo.h>
-#include <asm/string.h>
-
-#include <excite.h>
-
-/* This struct is used by Redboot to pass arguments to the kernel */
-typedef struct
-{
-        char *name;
-        char *val;
-} t_env_var;
-
-struct parmblock {
-        t_env_var memsize;
-        t_env_var modetty0;
-        t_env_var ethaddr;
-        t_env_var env_end;
-        char *argv[2];
-        char text[0];
-};
-
-static unsigned int prom_argc;
-static const char ** prom_argv;
-static const t_env_var * prom_env;
-
-static void prom_halt(void) __attribute__((noreturn));
-static void prom_exit(void) __attribute__((noreturn));
-
-
-
-const char *get_system_type(void)
-{
-        return "Basler eXcite";
-}
-
-/*
- * Halt the system
- */
-static void prom_halt(void)
-{
-        printk(KERN_NOTICE "\n** System halted.\n");
-        while (1)
-                asm volatile (
-                        "\t.set\tmips3\n"
-                        "\twait\n"
-                        "\t.set\tmips0\n"
-                );
-}
-
-/*
- * Reset the CPU and re-enter Redboot
- */
-static void prom_exit(void)
-{
-        unsigned int i;
-        volatile unsigned char * const flg =
-                (volatile unsigned char *) (EXCITE_ADDR_FPGA + EXCITE_FPGA_DPR);
-
-        /* Clear the watchdog reset flag, set the reboot flag */
-        *flg &= ~0x01;
-        *flg |= 0x80;
-
-        for (i = 0; i < 10; i++) {
-                *(volatile unsigned char *)  (EXCITE_ADDR_FPGA + EXCITE_FPGA_SYSCTL) = 0x02;
-                iob();
-                mdelay(1000);
-        }
-
-        printk(KERN_NOTICE "Reset failed\n");
-        prom_halt();
-}
-
-static const char __init *prom_getenv(char *name)
-{
-        const t_env_var * p;
-        for (p = prom_env; p->name != NULL; p++)
-                if(strcmp(name, p->name) == 0)
-                        break;
-        return p->val;
-}
-
-/*
- * Init routine which accepts the variables from Redboot
- */
-void __init prom_init(void)
-{
-        const struct parmblock * const pb = (struct parmblock *) fw_arg2;
-
-        prom_argc = fw_arg0;
-        prom_argv = (const char **) fw_arg1;
-        prom_env = &pb->memsize;
-
-        /* Callbacks for halt, restart */
-        _machine_restart = (void (*)(char *)) prom_exit;
-        _machine_halt = prom_halt;
-
-#ifdef CONFIG_32BIT
-        /* copy command line */
-        strcpy(arcs_cmdline, prom_argv[1]);
-        memsize = simple_strtol(prom_getenv("memsize"), NULL, 16);
-        strcpy(modetty, prom_getenv("modetty0"));
-#endif /* CONFIG_32BIT */
-
-#ifdef CONFIG_64BIT
-#       error 64 bit support not implemented
-#endif /* CONFIG_64BIT */
-}
-
-/* This is called from free_initmem(), so we need to provide it */
-void __init prom_free_prom_memory(void)
-{
-        /* Nothing to do */
-}
diff --git a/arch/mips/basler/excite/excite_setup.c b/arch/mips/basler/excite/excite_setup.c
deleted file mode 100644
index d66b3b8edf2a..000000000000
--- a/arch/mips/basler/excite/excite_setup.c
+++ /dev/null
@@ -1,302 +0,0 @@
-/*
- *  Copyright (C) 2004, 2005 by Basler Vision Technologies AG
- *  Author: Thomas Koeller <thomas.koeller@baslerweb.com>
- *  Based on the PMC-Sierra Yosemite board support by Ralf Baechle and
- *  Manish Lachwani.
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License
- *  along with this program; if not, write to the Free Software
- *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-
-#include <linux/types.h>
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/string.h>
-#include <linux/tty.h>
-#include <linux/serial_core.h>
-#include <linux/serial.h>
-#include <linux/serial_8250.h>
-#include <linux/ioport.h>
-#include <linux/spinlock.h>
-#include <asm/bootinfo.h>
-#include <asm/mipsregs.h>
-#include <asm/pgtable-32.h>
-#include <asm/io.h>
-#include <asm/time.h>
-#include <asm/rm9k-ocd.h>
-
-#include <excite.h>
-
-#define TITAN_UART_CLK  25000000
-
-#if 1
-/* normal serial port assignment */
-#define REGBASE_SER0    0x0208
-#define REGBASE_SER1    0x0238
-#define MASK_SER0       0x1
-#define MASK_SER1       0x2
-#else
-/* serial ports swapped */
-#define REGBASE_SER0    0x0238
-#define REGBASE_SER1    0x0208
-#define MASK_SER0       0x2
-#define MASK_SER1       0x1
-#endif
-
-unsigned long memsize;
-char modetty[30];
-unsigned int titan_irq = TITAN_IRQ;
-static void __iomem * ctl_regs;
-u32 unit_id;
-
-volatile void __iomem * const ocd_base = (void *) (EXCITE_ADDR_OCD);
-volatile void __iomem * const titan_base = (void *) (EXCITE_ADDR_TITAN);
-
-/* Protect access to shared GPI registers */
-DEFINE_SPINLOCK(titan_lock);
-int titan_irqflags;
-
-
-/*
- * The eXcite platform uses the alternate timer interrupt
- *
- * Fixme: At the time of this writing cevt-r4k.c doesn't yet know about how
- * to handle the alternate timer interrupt of the RM9000.
- */
-void __init plat_time_init(void)
-{
-        const u32 modebit5 = ocd_readl(0x00e4);
-        unsigned int mult = ((modebit5 >> 11) & 0x1f) + 2;
-        unsigned int div = ((modebit5 >> 16) & 0x1f) + 2;
-
-        if (div == 33)
-                div = 1;
-        mips_hpt_frequency = EXCITE_CPU_EXT_CLOCK * mult / div / 2;
-}
-
-static int __init excite_init_console(void)
-{
-#if defined(CONFIG_SERIAL_8250)
-        static __initdata char serr[] =
-                KERN_ERR "Serial port #%u setup failed\n";
-        struct uart_port up;
-
-        /* Take the DUART out of reset */
-        titan_writel(0x00ff1cff, CPRR);
-
-#if (CONFIG_SERIAL_8250_NR_UARTS > 1)
-        /* Enable both ports */
-        titan_writel(MASK_SER0 | MASK_SER1, UACFG);
-#else
-        /* Enable port #0 only */
-        titan_writel(MASK_SER0, UACFG);
-#endif
-
-        /*
-         * Set up serial port #0. Do not use autodetection; the result is
-         * not what we want.
-         */
-        memset(&up, 0, sizeof(up));
-        up.membase      = (char *) titan_addr(REGBASE_SER0);
-        up.irq          = TITAN_IRQ;
-        up.uartclk      = TITAN_UART_CLK;
-        up.regshift     = 0;
-        up.iotype       = UPIO_RM9000;
-        up.type         = PORT_RM9000;
-        up.flags        = UPF_SHARE_IRQ;
-        up.line         = 0;
-        if (early_serial_setup(&up))
-                printk(serr, up.line);
-
-#if CONFIG_SERIAL_8250_NR_UARTS > 1
-        /* And now for port #1. */
-        up.membase      = (char *) titan_addr(REGBASE_SER1);
-        up.line         = 1;
-        if (early_serial_setup(&up))
-                printk(serr, up.line);
-#endif /* CONFIG_SERIAL_8250_NR_UARTS > 1 */
-#else
-        /* Leave the DUART in reset */
-        titan_writel(0x00ff3cff, CPRR);
-#endif  /* defined(CONFIG_SERIAL_8250) */
-
-        return 0;
-}
-
-static int __init excite_platform_init(void)
-{
-        unsigned int i;
-        unsigned char buf[3];
-        u8 reg;
-        void __iomem * dpr;
-
-        /* BIU buffer allocations */
-        ocd_writel(8, CPURSLMT);        /* CPU */
-        titan_writel(4, CPGRWL);        /* GPI / Ethernet */
-
-        /* Map control registers located in FPGA */
-        ctl_regs = ioremap_nocache(EXCITE_PHYS_FPGA + EXCITE_FPGA_SYSCTL, 16);
-        if (!ctl_regs)
-                panic("eXcite: failed to map platform control registers\n");
-        memcpy_fromio(buf, ctl_regs + 2, ARRAY_SIZE(buf));
-        unit_id = buf[0] | (buf[1] << 8) | (buf[2] << 16);
-
-        /* Clear the reboot flag */
-        dpr = ioremap_nocache(EXCITE_PHYS_FPGA + EXCITE_FPGA_DPR, 1);
-        reg = __raw_readb(dpr);
-        __raw_writeb(reg & 0x7f, dpr);
-        iounmap(dpr);
-
-        /* Interrupt controller setup */
-        for (i = INTP0Status0; i < INTP0Status0 + 0x80; i += 0x10) {
-                ocd_writel(0x00000000, i + 0x04);
-                ocd_writel(0xffffffff, i + 0x0c);
-        }
-        ocd_writel(0x2, NMICONFIG);
-
-        ocd_writel(0x1 << (TITAN_MSGINT % 0x20),
-                   INTP0Mask0 + (0x10 * (TITAN_MSGINT / 0x20)));
-        ocd_writel((0x1 << (FPGA0_MSGINT % 0x20))
-                   | ocd_readl(INTP0Mask0 + (0x10 * (FPGA0_MSGINT / 0x20))),
-                   INTP0Mask0 + (0x10 * (FPGA0_MSGINT / 0x20)));
-        ocd_writel((0x1 << (FPGA1_MSGINT % 0x20))
-                   | ocd_readl(INTP0Mask0 + (0x10 * (FPGA1_MSGINT / 0x20))),
-                   INTP0Mask0 + (0x10 * (FPGA1_MSGINT / 0x20)));
-        ocd_writel((0x1 << (PHY_MSGINT % 0x20))
-                   | ocd_readl(INTP0Mask0 + (0x10 * (PHY_MSGINT / 0x20))),
-                   INTP0Mask0 + (0x10 * (PHY_MSGINT / 0x20)));
-#if USB_IRQ < 10
-        ocd_writel((0x1 << (USB_MSGINT % 0x20))
-                   | ocd_readl(INTP0Mask0 + (0x10 * (USB_MSGINT / 0x20))),
-                   INTP0Mask0 + (0x10 * (USB_MSGINT / 0x20)));
-#endif
-        /* Enable the packet FIFO, XDMA and XDMA arbiter */
-        titan_writel(0x00ff18ff, CPRR);
-
-        /*
-         * Set up the PADMUX. Power down all ethernet slices,
-         * they will be powered up and configured at device startup.
-         */
-        titan_writel(0x00878206, CPTC1R);
-        titan_writel(0x00001100, CPTC0R); /* latch PADMUX, enable WCIMODE */
-
-        /* Reset and enable the FIFO block */
-        titan_writel(0x00000001, SDRXFCIE);
-        titan_writel(0x00000001, SDTXFCIE);
-        titan_writel(0x00000100, SDRXFCIE);
-        titan_writel(0x00000000, SDTXFCIE);
-
-        /*
-         * Initialize the common interrupt shared by all components of
-         * the GPI/Ethernet subsystem.
-         */
-        titan_writel((EXCITE_PHYS_OCD >> 12), CPCFG0);
-        titan_writel(TITAN_MSGINT, CPCFG1);
-
-        /*
-         * XDMA configuration.
-         * In order for the XDMA to be sharable among multiple drivers,
-         * the setup must be done here in the platform. The reason is that
-         * this setup can only be done while the XDMA is in reset. If this
-         * were done in a driver, it would interrupt all other drivers
-         * using the XDMA.
-         */
-        titan_writel(0x80021dff, GXCFG);        /* XDMA reset */
-        titan_writel(0x00000000, CPXCISRA);
-        titan_writel(0x00000000, CPXCISRB);     /* clear pending interrupts */
-#if defined(CONFIG_HIGHMEM)
-#       error change for HIGHMEM support!
-#else
-        titan_writel(0x00000000, GXDMADRPFX);   /* buffer address prefix */
-#endif
-        titan_writel(0, GXDMA_DESCADR);
-
-        for (i = 0x5040; i <= 0x5300; i += 0x0040)
-                titan_writel(0x80080000, i);    /* reset channel */
-
-        titan_writel((0x1 << 29)                        /* no sparse tx descr. */
-                     | (0x1 << 28)                      /* no sparse rx descr. */
-                     | (0x1 << 23) | (0x1 << 24)        /* descriptor coherency */
-                     | (0x1 << 21) | (0x1 << 22)        /* data coherency */
-                     | (0x1 << 17)
-                     | 0x1dff,
-                     GXCFG);
-
-#if defined(CONFIG_SMP)
-#       error No SMP support
-#else
-        /* All interrupts go to core #0 only. */
-        titan_writel(0x1f007fff, CPDST0A);
-        titan_writel(0x00000000, CPDST0B);
-        titan_writel(0x0000ff3f, CPDST1A);
-        titan_writel(0x00000000, CPDST1B);
-        titan_writel(0x00ffffff, CPXDSTA);
-        titan_writel(0x00000000, CPXDSTB);
-#endif
-
-        /* Enable DUART interrupts, disable everything else. */
-        titan_writel(0x04000000, CPGIG0ER);
-        titan_writel(0x000000c0, CPGIG1ER);
-
-        excite_procfs_init();
-        return 0;
-}
-
-void __init plat_mem_setup(void)
-{
-        volatile u32 * const boot_ocd_base = (u32 *) 0xbf7fc000;
-
-        /* Announce RAM to system */
-        add_memory_region(0x00000000, memsize, BOOT_MEM_RAM);
-
-        /* Set up the peripheral address map */
-        *(boot_ocd_base + (LKB9 / sizeof(u32))) = 0;
-        *(boot_ocd_base + (LKB10 / sizeof(u32))) = 0;
-        *(boot_ocd_base + (LKB11 / sizeof(u32))) = 0;
-        *(boot_ocd_base + (LKB12 / sizeof(u32))) = 0;
-        wmb();
-        *(boot_ocd_base + (LKB0 / sizeof(u32))) = EXCITE_PHYS_OCD >> 4;
-        wmb();
-
-        ocd_writel((EXCITE_PHYS_TITAN >> 4) | 0x1UL, LKB5);
-        ocd_writel(((EXCITE_SIZE_TITAN >> 4) & 0x7fffff00) - 0x100, LKM5);
-        ocd_writel((EXCITE_PHYS_SCRAM >> 4) | 0x1UL, LKB13);
-        ocd_writel(((EXCITE_SIZE_SCRAM >> 4) & 0xffffff00) - 0x100, LKM13);
-
-        /* Local bus slot #0 */
-        ocd_writel(0x00040510, LDP0);
-        ocd_writel((EXCITE_PHYS_BOOTROM >> 4) | 0x1UL, LKB9);
-        ocd_writel(((EXCITE_SIZE_BOOTROM >> 4) & 0x03ffff00) - 0x100, LKM9);
-
-        /* Local bus slot #2 */
-        ocd_writel(0x00000330, LDP2);
-        ocd_writel((EXCITE_PHYS_FPGA >> 4) | 0x1, LKB11);
-        ocd_writel(((EXCITE_SIZE_FPGA >> 4) - 0x100) & 0x03ffff00, LKM11);
-
-        /* Local bus slot #3 */
-        ocd_writel(0x00123413, LDP3);
-        ocd_writel((EXCITE_PHYS_NAND >> 4) | 0x1, LKB12);
-        ocd_writel(((EXCITE_SIZE_NAND >> 4) - 0x100) & 0x03ffff00, LKM12);
-}
-
-
-
-console_initcall(excite_init_console);
-arch_initcall(excite_platform_init);
-
-EXPORT_SYMBOL(titan_lock);
-EXPORT_SYMBOL(titan_irqflags);
-EXPORT_SYMBOL(titan_irq);
-EXPORT_SYMBOL(ocd_base);
-EXPORT_SYMBOL(titan_base);
diff --git a/arch/mips/bcm47xx/prom.c b/arch/mips/bcm47xx/prom.c
index fb284c3b2cff..c51405e57921 100644
--- a/arch/mips/bcm47xx/prom.c
+++ b/arch/mips/bcm47xx/prom.c
@@ -100,11 +100,11 @@ static __init void prom_init_console(void)
 
 static __init void prom_init_cmdline(void)
 {
-        static char buf[CL_SIZE] __initdata;
+        static char buf[COMMAND_LINE_SIZE] __initdata;
 
         /* Get the kernel command line from CFE */
-        if (cfe_getenv("LINUX_CMDLINE", buf, CL_SIZE) >= 0) {
-                buf[CL_SIZE-1] = 0;
+        if (cfe_getenv("LINUX_CMDLINE", buf, COMMAND_LINE_SIZE) >= 0) {
+                buf[COMMAND_LINE_SIZE - 1] = 0;
                 strcpy(arcs_cmdline, buf);
         }
 
@@ -112,13 +112,13 @@ static __init void prom_init_cmdline(void)
          * as CFE is not available anymore later in the boot process. */
         if ((strstr(arcs_cmdline, "console=")) == NULL) {
                 /* Try to read the default serial port used by CFE */
-                if ((cfe_getenv("BOOT_CONSOLE", buf, CL_SIZE) < 0)
+                if ((cfe_getenv("BOOT_CONSOLE", buf, COMMAND_LINE_SIZE) < 0)
                     || (strncmp("uart", buf, 4)))
                         /* Default to uart0 */
                         strcpy(buf, "uart0");
 
                 /* Compute the new command line */
-                snprintf(arcs_cmdline, CL_SIZE, "%s console=ttyS%c,115200",
+                snprintf(arcs_cmdline, COMMAND_LINE_SIZE, "%s console=ttyS%c,115200",
                          arcs_cmdline, buf[4]);
         }
 }
diff --git a/arch/mips/boot/Makefile b/arch/mips/boot/Makefile
index 2a209d74f0b4..094bc84765a3 100644
--- a/arch/mips/boot/Makefile
+++ b/arch/mips/boot/Makefile
@@ -25,7 +25,7 @@ strip-flags	= $(addprefix --remove-section=,$(drop-sections))
 
 VMLINUX = vmlinux
 
-all: vmlinux.ecoff vmlinux.srec addinitrd
+all: vmlinux.ecoff vmlinux.srec
 
 vmlinux.ecoff: $(obj)/elf2ecoff $(VMLINUX)
         $(obj)/elf2ecoff $(VMLINUX) vmlinux.ecoff $(E2EFLAGS)
@@ -39,11 +39,7 @@ vmlinux.bin: $(VMLINUX)
 vmlinux.srec: $(VMLINUX)
         $(OBJCOPY) -S -O srec $(strip-flags) $(VMLINUX) $(obj)/vmlinux.srec
 
-$(obj)/addinitrd: $(obj)/addinitrd.c
-        $(HOSTCC) -o $@ $^
-
-clean-files += addinitrd \
-               elf2ecoff \
+clean-files += elf2ecoff \
                vmlinux.bin \
                vmlinux.ecoff \
                vmlinux.srec
diff --git a/arch/mips/boot/addinitrd.c b/arch/mips/boot/addinitrd.c
deleted file mode 100644
index b5b3febc10cc..000000000000
--- a/arch/mips/boot/addinitrd.c
+++ /dev/null
@@ -1,131 +0,0 @@
-/*
- * addinitrd - program to add a initrd image to an ecoff kernel
- *
- * (C) 1999 Thomas Bogendoerfer
- * minor modifications, cleanup: Guido Guenther <agx@sigxcpu.org>
- * further cleanup: Maciej W. Rozycki
- */
-
-#include <sys/types.h>
-#include <sys/stat.h>
-#include <fcntl.h>
-#include <unistd.h>
-#include <stdio.h>
-#include <netinet/in.h>
-
-#include "ecoff.h"
-
-#define MIPS_PAGE_SIZE  4096
-#define MIPS_PAGE_MASK  (MIPS_PAGE_SIZE-1)
-
-#define swab16(x) \
-        ((unsigned short)( \
-                (((unsigned short)(x) & (unsigned short)0x00ffU) << 8) | \
-                (((unsigned short)(x) & (unsigned short)0xff00U) >> 8) ))
-
-#define swab32(x) \
-        ((unsigned int)( \
-                (((unsigned int)(x) & (unsigned int)0x000000ffUL) << 24) | \
-                (((unsigned int)(x) & (unsigned int)0x0000ff00UL) <<  8) | \
-                (((unsigned int)(x) & (unsigned int)0x00ff0000UL) >>  8) | \
-                (((unsigned int)(x) & (unsigned int)0xff000000UL) >> 24) ))
-
-#define SWAB(a) (swab ? swab32(a) : (a))
-
-void die(char *s)
-{
-        perror(s);
-        exit(1);
-}
-
-int main(int argc, char *argv[])
-{
-        int fd_vmlinux, fd_initrd, fd_outfile;
-        FILHDR efile;
-        AOUTHDR eaout;
-        SCNHDR esecs[3];
-        struct stat st;
-        char buf[1024];
-        unsigned long loadaddr;
-        unsigned long initrd_header[2];
-        int i, cnt;
-        int swab = 0;
-
-        if (argc != 4) {
-                printf("Usage: %s <vmlinux> <initrd> <outfile>\n", argv[0]);
-                exit(1);
-        }
-
-        if ((fd_vmlinux = open (argv[1], O_RDONLY)) < 0)
-                 die("open vmlinux");
-        if (read (fd_vmlinux, &efile, sizeof efile) != sizeof efile)
-                die("read file header");
-        if (read (fd_vmlinux, &eaout, sizeof eaout) != sizeof eaout)
-                die("read aout header");
-        if (read (fd_vmlinux, esecs, sizeof esecs) != sizeof esecs)
-                die("read section headers");
-        /*
-         * check whether the file is good for us
-         */
-        /* TBD */
-
-        /*
-         * check, if we have to swab words
-         */
-        if (ntohs(0xaa55) == 0xaa55) {
-                if (efile.f_magic == swab16(MIPSELMAGIC))
-                        swab = 1;
-        } else {
-                if (efile.f_magic == swab16(MIPSEBMAGIC))
-                        swab = 1;
-        }
-
-        /* make sure we have an empty data segment for the initrd */
-        if (eaout.dsize || esecs[1].s_size) {
-                fprintf(stderr, "Data segment not empty. Giving up!\n");
-                exit(1);
-        }
-        if ((fd_initrd = open (argv[2], O_RDONLY)) < 0)
-                die("open initrd");
-        if (fstat (fd_initrd, &st) < 0)
-                die("fstat initrd");
-        loadaddr = ((SWAB(esecs[2].s_vaddr) + SWAB(esecs[2].s_size)
-                        + MIPS_PAGE_SIZE-1) & ~MIPS_PAGE_MASK) - 8;
-        if (loadaddr < (SWAB(esecs[2].s_vaddr) + SWAB(esecs[2].s_size)))
-                loadaddr += MIPS_PAGE_SIZE;
-        initrd_header[0] = SWAB(0x494E5244);
-        initrd_header[1] = SWAB(st.st_size);
-        eaout.dsize = esecs[1].s_size = initrd_header[1] = SWAB(st.st_size+8);
-        eaout.data_start = esecs[1].s_vaddr = esecs[1].s_paddr = SWAB(loadaddr);
-
-        if ((fd_outfile = open (argv[3], O_RDWR|O_CREAT|O_TRUNC, 0666)) < 0)
-                die("open outfile");
-        if (write (fd_outfile, &efile, sizeof efile) != sizeof efile)
-                die("write file header");
-        if (write (fd_outfile, &eaout, sizeof eaout) != sizeof eaout)
-                die("write aout header");
-        if (write (fd_outfile, esecs, sizeof esecs) != sizeof esecs)
-                die("write section headers");
-        /* skip padding */
-        if(lseek(fd_vmlinux, SWAB(esecs[0].s_scnptr), SEEK_SET) == (off_t)-1)
-                die("lseek vmlinux");
-        if(lseek(fd_outfile, SWAB(esecs[0].s_scnptr), SEEK_SET) == (off_t)-1)
-                die("lseek outfile");
-        /* copy text segment */
-        cnt = SWAB(eaout.tsize);
-        while (cnt) {
-                if ((i = read (fd_vmlinux, buf, sizeof buf)) <= 0)
-                        die("read vmlinux");
-                if (write (fd_outfile, buf, i) != i)
-                        die("write vmlinux");
-                cnt -= i;
-        }
-        if (write (fd_outfile, initrd_header, sizeof initrd_header) != sizeof initrd_header)
-                die("write initrd header");
-        while ((i = read (fd_initrd, buf, sizeof buf)) > 0)
-                if (write (fd_outfile, buf, i) != i)
-                        die("write initrd");
-        close(fd_vmlinux);
-        close(fd_initrd);
-        return 0;
-}
diff --git a/arch/mips/boot/compressed/Makefile b/arch/mips/boot/compressed/Makefile
new file mode 100644
index 000000000000..e27f40bbd4e5
--- /dev/null
+++ b/arch/mips/boot/compressed/Makefile
@@ -0,0 +1,100 @@
+#
+# This file is subject to the terms and conditions of the GNU General Public
+# License.
+#
+# Adapted for MIPS Pete Popov, Dan Malek
+#
+# Copyright (C) 1994 by Linus Torvalds
+# Adapted for PowerPC by Gary Thomas
+# modified by Cort (cort@cs.nmt.edu)
+#
+# Copyright (C) 2009 Lemote Inc. & DSLab, Lanzhou University
+# Author: Wu Zhangjin <wuzj@lemote.com>
+#
+
+# compressed kernel load addr: VMLINUZ_LOAD_ADDRESS > VMLINUX_LOAD_ADDRESS + VMLINUX_SIZE
+VMLINUX_SIZE := $(shell wc -c $(objtree)/$(KBUILD_IMAGE) 2>/dev/null | cut -d' ' -f1)
+VMLINUX_SIZE := $(shell [ -n "$(VMLINUX_SIZE)" ] && echo $$(($(VMLINUX_SIZE) + (65536 - $(VMLINUX_SIZE) % 65536))))
+VMLINUZ_LOAD_ADDRESS := 0x$(shell [ -n "$(VMLINUX_SIZE)" ] && printf %x $$(($(VMLINUX_LOAD_ADDRESS) + $(VMLINUX_SIZE))))
+
+# set the default size of the mallocing area for decompressing
+BOOT_HEAP_SIZE := 0x400000
+
+# Disable Function Tracer
+KBUILD_CFLAGS := $(shell echo $(KBUILD_CFLAGS) | sed -e "s/-pg//")
+
+KBUILD_CFLAGS := $(LINUXINCLUDE) $(KBUILD_CFLAGS) -D__KERNEL__ \
+        -DBOOT_HEAP_SIZE=$(BOOT_HEAP_SIZE) -D"VMLINUX_LOAD_ADDRESS_ULL=$(VMLINUX_LOAD_ADDRESS)ull" \
+
+KBUILD_AFLAGS := $(LINUXINCLUDE) $(KBUILD_AFLAGS) -D__ASSEMBLY__ \
+        -DKERNEL_ENTRY=0x$(shell $(NM) $(objtree)/$(KBUILD_IMAGE) 2>/dev/null | grep " kernel_entry" | cut -f1 -d \ ) \
+        -DBOOT_HEAP_SIZE=$(BOOT_HEAP_SIZE)
+
+obj-y := $(obj)/head.o $(obj)/decompress.o $(obj)/dbg.o
+
+obj-$(CONFIG_SYS_SUPPORTS_ZBOOT_UART16550) += $(obj)/uart-16550.o
+
+OBJCOPYFLAGS_vmlinux.bin := $(OBJCOPYFLAGS) -O binary -R .comment -S
+$(obj)/vmlinux.bin: $(KBUILD_IMAGE)
+        $(call if_changed,objcopy)
+
+suffix_$(CONFIG_KERNEL_GZIP)  = gz
+suffix_$(CONFIG_KERNEL_BZIP2) = bz2
+suffix_$(CONFIG_KERNEL_LZMA)  = lzma
+tool_$(CONFIG_KERNEL_GZIP)    = gzip
+tool_$(CONFIG_KERNEL_BZIP2)   = bzip2
+tool_$(CONFIG_KERNEL_LZMA)    = lzma
+$(obj)/vmlinux.$(suffix_y): $(obj)/vmlinux.bin
+        $(call if_changed,$(tool_y))
+
+$(obj)/piggy.o: $(obj)/vmlinux.$(suffix_y) $(obj)/dummy.o
+        $(Q)$(OBJCOPY) $(OBJCOPYFLAGS) \
+                --add-section=.image=$< \
+                --set-section-flags=.image=contents,alloc,load,readonly,data \
+                $(obj)/dummy.o $@
+
+LDFLAGS_vmlinuz := $(LDFLAGS) -Ttext $(VMLINUZ_LOAD_ADDRESS) -T
+vmlinuz: $(src)/ld.script $(obj-y) $(obj)/piggy.o
+        $(call if_changed,ld)
+        $(Q)$(OBJCOPY) $(OBJCOPYFLAGS) -R .comment -R .stab -R .stabstr -R .initrd -R .sysmap $@
+
+#
+# Some DECstations need all possible sections of an ECOFF executable
+#
+ifdef CONFIG_MACH_DECSTATION
+  E2EFLAGS = -a
+else
+  E2EFLAGS =
+endif
+
+# elf2ecoff can only handle 32bit image
+
+ifdef CONFIG_32BIT
+        VMLINUZ = vmlinuz
+else
+        VMLINUZ = vmlinuz.32
+endif
+
+vmlinuz.32: vmlinuz
+        $(Q)$(OBJCOPY) -O $(32bit-bfd) $(OBJCOPYFLAGS) $< $@
+
+vmlinuz.ecoff: $(obj)/../elf2ecoff $(VMLINUZ)
+        $(Q)$(obj)/../elf2ecoff $(VMLINUZ) vmlinuz.ecoff $(E2EFLAGS)
+
+$(obj)/../elf2ecoff: $(src)/../elf2ecoff.c
+        $(Q)$(HOSTCC) -o $@ $^
+
+drop-sections   = .reginfo .mdebug .comment .note .pdr .options .MIPS.options
+strip-flags     = $(addprefix --remove-section=,$(drop-sections))
+
+OBJCOPYFLAGS_vmlinuz.bin := $(OBJCOPYFLAGS) -O binary $(strip-flags)
+vmlinuz.bin: vmlinuz
+        $(call if_changed,objcopy)
+
+OBJCOPYFLAGS_vmlinuz.srec := $(OBJCOPYFLAGS) -S -O srec $(strip-flags)
+vmlinuz.srec: vmlinuz
+        $(call if_changed,objcopy)
+
+clean:
+clean-files += *.o \
+               vmlinu*
diff --git a/arch/mips/boot/compressed/dbg.c b/arch/mips/boot/compressed/dbg.c
new file mode 100644
index 000000000000..ff4dc7a33a9f
--- /dev/null
+++ b/arch/mips/boot/compressed/dbg.c
@@ -0,0 +1,37 @@
+/*
+ * MIPS-specific debug support for pre-boot environment
+ *
+ * NOTE: putc() is board specific, if your board have a 16550 compatible uart,
+ * please select SYS_SUPPORTS_ZBOOT_UART16550 for your machine. othewise, you
+ * need to implement your own putc().
+ */
+
+#include <linux/init.h>
+#include <linux/types.h>
+
+void __attribute__ ((weak)) putc(char c)
+{
+}
+
+void puts(const char *s)
+{
+        char c;
+        while ((c = *s++) != '\0') {
+                putc(c);
+                if (c == '\n')
+                        putc('\r');
+        }
+}
+
+void puthex(unsigned long long val)
+{
+
+        unsigned char buf[10];
+        int i;
+        for (i = 7; i >= 0; i--) {
+                buf[i] = "0123456789ABCDEF"[val & 0x0F];
+                val >>= 4;
+        }
+        buf[8] = '\0';
+        puts(buf);
+}
diff --git a/arch/mips/boot/compressed/decompress.c b/arch/mips/boot/compressed/decompress.c
new file mode 100644
index 000000000000..67330c2f7318
--- /dev/null
+++ b/arch/mips/boot/compressed/decompress.c
@@ -0,0 +1,126 @@
+/*
+ * Misc. bootloader code for many machines.
+ *
+ * Copyright 2001 MontaVista Software Inc.
+ * Author: Matt Porter <mporter@mvista.com> Derived from
+ * arch/ppc/boot/prep/misc.c
+ *
+ * Copyright (C) 2009 Lemote, Inc. & Institute of Computing Technology
+ * Author: Wu Zhangjin <wuzj@lemote.com>
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/types.h>
+#include <linux/kernel.h>
+
+#include <asm/addrspace.h>
+
+/* These two variables specify the free mem region
+ * that can be used for temporary malloc area
+ */
+unsigned long free_mem_ptr;
+unsigned long free_mem_end_ptr;
+char *zimage_start;
+
+/* The linker tells us where the image is. */
+extern unsigned char __image_begin, __image_end;
+extern unsigned char __ramdisk_begin, __ramdisk_end;
+unsigned long initrd_size;
+
+/* debug interfaces  */
+extern void puts(const char *s);
+extern void puthex(unsigned long long val);
+
+void error(char *x)
+{
+        puts("\n\n");
+        puts(x);
+        puts("\n\n -- System halted");
+
+        while (1)
+                ;       /* Halt */
+}
+
+/* activate the code for pre-boot environment */
+#define STATIC static
+
+#ifdef CONFIG_KERNEL_GZIP
+void *memcpy(void *dest, const void *src, size_t n)
+{
+        int i;
+        const char *s = src;
+        char *d = dest;
+
+        for (i = 0; i < n; i++)
+                d[i] = s[i];
+        return dest;
+}
+#include "../../../../lib/decompress_inflate.c"
+#endif
+
+#ifdef CONFIG_KERNEL_BZIP2
+void *memset(void *s, int c, size_t n)
+{
+        int i;
+        char *ss = s;
+
+        for (i = 0; i < n; i++)
+                ss[i] = c;
+        return s;
+}
+#include "../../../../lib/decompress_bunzip2.c"
+#endif
+
+#ifdef CONFIG_KERNEL_LZMA
+#include "../../../../lib/decompress_unlzma.c"
+#endif
+
+void decompress_kernel(unsigned long boot_heap_start)
+{
+        int zimage_size;
+
+        /*
+         * We link ourself to an arbitrary low address.  When we run, we
+         * relocate outself to that address.  __image_beign points to
+         * the part of the image where the zImage is. -- Tom
+         */
+        zimage_start = (char *)(unsigned long)(&__image_begin);
+        zimage_size = (unsigned long)(&__image_end) -
+            (unsigned long)(&__image_begin);
+
+        /*
+         * The zImage and initrd will be between start and _end, so they've
+         * already been moved once.  We're good to go now. -- Tom
+         */
+        puts("zimage at:     ");
+        puthex((unsigned long)zimage_start);
+        puts(" ");
+        puthex((unsigned long)(zimage_size + zimage_start));
+        puts("\n");
+
+        if (initrd_size) {
+                puts("initrd at:     ");
+                puthex((unsigned long)(&__ramdisk_begin));
+                puts(" ");
+                puthex((unsigned long)(&__ramdisk_end));
+                puts("\n");
+        }
+
+        /* this area are prepared for mallocing when decompressing */
+        free_mem_ptr = boot_heap_start;
+        free_mem_end_ptr = boot_heap_start + BOOT_HEAP_SIZE;
+
+        /* Display standard Linux/MIPS boot prompt for kernel args */
+        puts("Uncompressing Linux at load address ");
+        puthex(VMLINUX_LOAD_ADDRESS_ULL);
+        puts("\n");
+        /* Decompress the kernel with according algorithm */
+        decompress(zimage_start, zimage_size, 0, 0,
+                   (void *)VMLINUX_LOAD_ADDRESS_ULL, 0, error);
+        /* FIXME: is there a need to flush cache here? */
+        puts("Now, booting the kernel...\n");
+}
diff --git a/arch/mips/boot/compressed/dummy.c b/arch/mips/boot/compressed/dummy.c
new file mode 100644
index 000000000000..31dbf45bf99c
--- /dev/null
+++ b/arch/mips/boot/compressed/dummy.c
@@ -0,0 +1,4 @@
+int main(void)
+{
+        return 0;
+}
diff --git a/arch/mips/boot/compressed/head.S b/arch/mips/boot/compressed/head.S
new file mode 100644
index 000000000000..4e65a8420bee
--- /dev/null
+++ b/arch/mips/boot/compressed/head.S
@@ -0,0 +1,56 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1994, 1995 Waldorf Electronics
+ * Written by Ralf Baechle and Andreas Busse
+ * Copyright (C) 1995 - 1999 Ralf Baechle
+ * Copyright (C) 1996 Paul M. Antoine
+ * Modified for DECStation and hence R3000 support by Paul M. Antoine
+ * Further modifications by David S. Miller and Harald Koerfgen
+ * Copyright (C) 1999 Silicon Graphics, Inc.
+ */
+
+#include <asm/asm.h>
+#include <asm/regdef.h>
+
+        .set noreorder
+        .cprestore
+        LEAF(start)
+start:
+        /* Save boot rom start args */
+        move    s0, a0
+        move    s1, a1
+        move    s2, a2
+        move    s3, a3
+
+        /* Clear BSS */
+        PTR_LA  a0, _edata
+        PTR_LA  a2, _end
+1:      sw      zero, 0(a0)
+        bne     a2, a0, 1b
+         addiu  a0, a0, 4
+
+        PTR_LA  a0, (.heap)          /* heap address */
+        PTR_LA  sp, (.stack + 8192)  /* stack address */
+
+        PTR_LA  ra, 2f
+        PTR_LA  k0, decompress_kernel
+        jr      k0
+         nop
+2:
+        move    a0, s0
+        move    a1, s1
+        move    a2, s2
+        move    a3, s3
+        PTR_LI  k0, KERNEL_ENTRY
+        jr      k0
+         nop
+3:
+        b       3b
+         nop
+        END(start)
+
+        .comm .heap,BOOT_HEAP_SIZE,4
+        .comm .stack,4096*2,4
diff --git a/arch/mips/boot/compressed/ld.script b/arch/mips/boot/compressed/ld.script
new file mode 100644
index 000000000000..29e9f4c0d5d8
--- /dev/null
+++ b/arch/mips/boot/compressed/ld.script
@@ -0,0 +1,150 @@
+OUTPUT_ARCH(mips)
+ENTRY(start)
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  .init          : { *(.init)           } =0
+  .text      :
+  {
+    _ftext = . ;
+    *(.text)
+    *(.rodata)
+    *(.rodata1)
+    /* .gnu.warning sections are handled specially by elf32.em.  */
+    *(.gnu.warning)
+  } =0
+  .kstrtab : { *(.kstrtab) }
+
+  . = ALIGN(16);                /* Exception table */
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  __start___dbe_table = .;      /* Exception table for data bus errors */
+  __dbe_table : { *(__dbe_table) }
+  __stop___dbe_table = .;
+
+  __start___ksymtab = .;        /* Kernel symbol table */
+  __ksymtab : { *(__ksymtab) }
+  __stop___ksymtab = .;
+
+  _etext = .;
+
+  . = ALIGN(8192);
+  .data.init_task : { *(.data.init_task) }
+
+  /* Startup code */
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(16);
+  __setup_start = .;
+  .setup.init : { *(.setup.init) }
+  __setup_end = .;
+  __initcall_start = .;
+  .initcall.init : { *(.initcall.init) }
+  __initcall_end = .;
+  . = ALIGN(4096);      /* Align double page for init_task_union */
+  __init_end = .;
+
+  . = ALIGN(4096);
+  .data.page_aligned : { *(.data.idt) }
+
+  . = ALIGN(32);
+  .data.cacheline_aligned : { *(.data.cacheline_aligned) }
+
+  .fini      : { *(.fini)    } =0
+  .reginfo : { *(.reginfo) }
+  /* Adjust the address for the data segment.  We want to adjust up to
+     the same address within the page on the next page up.  It would
+     be more correct to do this:
+       . = .;
+     The current expression does not correctly handle the case of a
+     text segment ending precisely at the end of a page; it causes the
+     data segment to skip a page.  The above expression does not have
+     this problem, but it will currently (2/95) cause BFD to allocate
+     a single segment, combining both text and data, for this case.
+     This will prevent the text segment from being shared among
+     multiple executions of the program; I think that is more
+     important than losing a page of the virtual address space (note
+     that no actual memory is lost; the page which is skipped can not
+     be referenced).  */
+  . = .;
+  .data    :
+  {
+    _fdata = . ;
+    *(.data)
+
+   /* Put the compressed image here, so bss is on the end. */
+   __image_begin = .;
+   *(.image)
+   __image_end = .;
+   /* Align the initial ramdisk image (INITRD) on page boundaries. */
+   . = ALIGN(4096);
+   __ramdisk_begin = .;
+   *(.initrd)
+   __ramdisk_end = .;
+   . = ALIGN(4096);
+
+    CONSTRUCTORS
+  }
+  .data1   : { *(.data1) }
+  _gp = . + 0x8000;
+  .lit8 : { *(.lit8) }
+  .lit4 : { *(.lit4) }
+  .ctors         : { *(.ctors)   }
+  .dtors         : { *(.dtors)   }
+  .got           : { *(.got.plt) *(.got) }
+  .dynamic       : { *(.dynamic) }
+  /* We want the small data sections together, so single-instruction offsets
+     can access them all, and initialized data all before uninitialized, so
+     we can shorten the on-disk segment size.  */
+  .sdata     : { *(.sdata) }
+  . = ALIGN(4);
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __bss_start = .;
+  _fbss = .;
+  .sbss      : { *(.sbss) *(.scommon) }
+  .bss       :
+  {
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+   .  = ALIGN(4);
+  _end = . ;
+  PROVIDE (end = .);
+  }
+
+  /* Sections to be discarded */
+  /DISCARD/ :
+  {
+        *(.text.exit)
+        *(.data.exit)
+        *(.exitcall.exit)
+  }
+
+  /* This is the MIPS specific mdebug section.  */
+  .mdebug : { *(.mdebug) }
+  /* These are needed for ELF backends which have not yet been
+     converted to the new style linker.  */
+  .stab 0 : { *(.stab) }
+  .stabstr 0 : { *(.stabstr) }
+  /* DWARF debug sections.
+     Symbols in the .debug DWARF section are relative to the beginning of the
+     section so we begin .debug at 0.  It's not clear yet what needs to happen
+     for the others.   */
+  .debug          0 : { *(.debug) }
+  .debug_srcinfo  0 : { *(.debug_srcinfo) }
+  .debug_aranges  0 : { *(.debug_aranges) }
+  .debug_pubnames 0 : { *(.debug_pubnames) }
+  .debug_sfnames  0 : { *(.debug_sfnames) }
+  .line           0 : { *(.line) }
+  /* These must appear regardless of  .  */
+  .gptab.sdata : { *(.gptab.data) *(.gptab.sdata) }
+  .gptab.sbss : { *(.gptab.bss) *(.gptab.sbss) }
+  .comment : { *(.comment) }
+  .note : { *(.note) }
+}
diff --git a/arch/mips/boot/compressed/uart-16550.c b/arch/mips/boot/compressed/uart-16550.c
new file mode 100644
index 000000000000..c9caaf4fbf60
--- /dev/null
+++ b/arch/mips/boot/compressed/uart-16550.c
@@ -0,0 +1,43 @@
+/*
+ * 16550 compatible uart based serial debug support for zboot
+ */
+
+#include <linux/types.h>
+#include <linux/serial_reg.h>
+#include <linux/init.h>
+
+#include <asm/addrspace.h>
+
+#if defined(CONFIG_MACH_LOONGSON) || defined(CONFIG_MIPS_MALTA)
+#define UART_BASE 0x1fd003f8
+#define PORT(offset) (CKSEG1ADDR(UART_BASE) + (offset))
+#endif
+
+#ifdef CONFIG_AR7
+#include <ar7.h>
+#define PORT(offset) (CKSEG1ADDR(AR7_REGS_UART0) + (4 * offset))
+#endif
+
+#ifndef PORT
+#error please define the serial port address for your own machine
+#endif
+
+static inline unsigned int serial_in(int offset)
+{
+        return *((char *)PORT(offset));
+}
+
+static inline void serial_out(int offset, int value)
+{
+        *((char *)PORT(offset)) = value;
+}
+
+void putc(char c)
+{
+        int timeout = 1024;
+
+        while (((serial_in(UART_LSR) & UART_LSR_THRE) == 0) && (timeout-- > 0))
+                ;
+
+        serial_out(UART_TX, c);
+}
diff --git a/arch/mips/cavium-octeon/Makefile b/arch/mips/cavium-octeon/Makefile
index 139436280520..3e9876317e61 100644
--- a/arch/mips/cavium-octeon/Makefile
+++ b/arch/mips/cavium-octeon/Makefile
@@ -9,7 +9,7 @@
 # Copyright (C) 2005-2009 Cavium Networks
 #
 
-obj-y := setup.o serial.o octeon-platform.o octeon-irq.o csrc-octeon.o
+obj-y := cpu.o setup.o serial.o octeon-platform.o octeon-irq.o csrc-octeon.o
 obj-y += dma-octeon.o flash_setup.o
 obj-y += octeon-memcpy.o
 
diff --git a/arch/mips/cavium-octeon/cpu.c b/arch/mips/cavium-octeon/cpu.c
new file mode 100644
index 000000000000..b6df5387e855
--- /dev/null
+++ b/arch/mips/cavium-octeon/cpu.c
@@ -0,0 +1,52 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2009 Wind River Systems,
+ *   written by Ralf Baechle <ralf@linux-mips.org>
+ */
+#include <linux/init.h>
+#include <linux/irqflags.h>
+#include <linux/notifier.h>
+#include <linux/prefetch.h>
+#include <linux/sched.h>
+
+#include <asm/cop2.h>
+#include <asm/current.h>
+#include <asm/mipsregs.h>
+#include <asm/page.h>
+#include <asm/octeon/octeon.h>
+
+static int cnmips_cu2_call(struct notifier_block *nfb, unsigned long action,
+        void *data)
+{
+        unsigned long flags;
+        unsigned int status;
+
+        switch (action) {
+        case CU2_EXCEPTION:
+                prefetch(&current->thread.cp2);
+                local_irq_save(flags);
+                KSTK_STATUS(current) |= ST0_CU2;
+                status = read_c0_status();
+                write_c0_status(status | ST0_CU2);
+                octeon_cop2_restore(&(current->thread.cp2));
+                write_c0_status(status & ~ST0_CU2);
+                local_irq_restore(flags);
+
+                return NOTIFY_BAD;      /* Don't call default notifier */
+        }
+
+        return NOTIFY_OK;               /* Let default notifier send signals */
+}
+
+static struct notifier_block cnmips_cu2_notifier = {
+        .notifier_call = cnmips_cu2_call,
+};
+
+static int cnmips_cu2_setup(void)
+{
+        return register_cu2_notifier(&cnmips_cu2_notifier);
+}
+early_initcall(cnmips_cu2_setup);
diff --git a/arch/mips/cavium-octeon/octeon-platform.c b/arch/mips/cavium-octeon/octeon-platform.c
index be711dd2d918..cfdb4c2ac5c3 100644
--- a/arch/mips/cavium-octeon/octeon-platform.c
+++ b/arch/mips/cavium-octeon/octeon-platform.c
@@ -159,6 +159,94 @@ out:
 }
 device_initcall(octeon_rng_device_init);
 
+/* Octeon SMI/MDIO interface.  */
+static int __init octeon_mdiobus_device_init(void)
+{
+        struct platform_device *pd;
+        int ret = 0;
+
+        if (octeon_is_simulation())
+                return 0; /* No mdio in the simulator. */
+
+        /* The bus number is the platform_device id.  */
+        pd = platform_device_alloc("mdio-octeon", 0);
+        if (!pd) {
+                ret = -ENOMEM;
+                goto out;
+        }
+
+        ret = platform_device_add(pd);
+        if (ret)
+                goto fail;
+
+        return ret;
+fail:
+        platform_device_put(pd);
+
+out:
+        return ret;
+
+}
+device_initcall(octeon_mdiobus_device_init);
+
+/* Octeon mgmt port Ethernet interface.  */
+static int __init octeon_mgmt_device_init(void)
+{
+        struct platform_device *pd;
+        int ret = 0;
+        int port, num_ports;
+
+        struct resource mgmt_port_resource = {
+                .flags  = IORESOURCE_IRQ,
+                .start  = -1,
+                .end    = -1
+        };
+
+        if (!OCTEON_IS_MODEL(OCTEON_CN56XX) && !OCTEON_IS_MODEL(OCTEON_CN52XX))
+                return 0;
+
+        if (OCTEON_IS_MODEL(OCTEON_CN56XX))
+                num_ports = 1;
+        else
+                num_ports = 2;
+
+        for (port = 0; port < num_ports; port++) {
+                pd = platform_device_alloc("octeon_mgmt", port);
+                if (!pd) {
+                        ret = -ENOMEM;
+                        goto out;
+                }
+                switch (port) {
+                case 0:
+                        mgmt_port_resource.start = OCTEON_IRQ_MII0;
+                        break;
+                case 1:
+                        mgmt_port_resource.start = OCTEON_IRQ_MII1;
+                        break;
+                default:
+                        BUG();
+                }
+                mgmt_port_resource.end = mgmt_port_resource.start;
+
+                ret = platform_device_add_resources(pd, &mgmt_port_resource, 1);
+
+                if (ret)
+                        goto fail;
+
+                ret = platform_device_add(pd);
+                if (ret)
+                        goto fail;
+        }
+        return ret;
+fail:
+        platform_device_put(pd);
+
+out:
+        return ret;
+
+}
+device_initcall(octeon_mgmt_device_init);
+
 MODULE_AUTHOR("David Daney <ddaney@caviumnetworks.com>");
 MODULE_LICENSE("GPL");
 MODULE_DESCRIPTION("Platform driver for Octeon SOC");
diff --git a/arch/mips/configs/ar7_defconfig b/arch/mips/configs/ar7_defconfig
index 35648302f7cc..5a5b6ba7514e 100644
--- a/arch/mips/configs/ar7_defconfig
+++ b/arch/mips/configs/ar7_defconfig
@@ -10,7 +10,6 @@ CONFIG_MIPS=y
 #
 # CONFIG_MACH_ALCHEMY is not set
 CONFIG_AR7=y
-# CONFIG_BASLER_EXCITE is not set
 # CONFIG_BCM47XX is not set
 # CONFIG_MIPS_COBALT is not set
 # CONFIG_MACH_DECSTATION is not set
@@ -265,7 +264,6 @@ CONFIG_DEFAULT_DEADLINE=y
 # CONFIG_DEFAULT_CFQ is not set
 # CONFIG_DEFAULT_NOOP is not set
 CONFIG_DEFAULT_IOSCHED="deadline"
-CONFIG_PROBE_INITRD_HEADER=y
 # CONFIG_FREEZER is not set
 
 #
@@ -1053,7 +1051,9 @@ CONFIG_TRACING_SUPPORT=y
 # CONFIG_DYNAMIC_DEBUG is not set
 # CONFIG_SAMPLES is not set
 CONFIG_HAVE_ARCH_KGDB=y
+CONFIG_CMDLINE_BOOL=y
 CONFIG_CMDLINE="rootfstype=squashfs,jffs2"
+# CONFIG_CMDLINE_OVERRIDE is not set
 
 #
 # Security options
diff --git a/arch/mips/configs/bcm47xx_defconfig b/arch/mips/configs/bcm47xx_defconfig
index 94b7d57f906d..267bd46120bc 100644
--- a/arch/mips/configs/bcm47xx_defconfig
+++ b/arch/mips/configs/bcm47xx_defconfig
@@ -9,7 +9,6 @@ CONFIG_MIPS=y
 # Machine selection
 #
 # CONFIG_MACH_ALCHEMY is not set
-# CONFIG_BASLER_EXCITE is not set
 CONFIG_BCM47XX=y
 # CONFIG_MIPS_COBALT is not set
 # CONFIG_MACH_DECSTATION is not set
@@ -1853,7 +1852,7 @@ CONFIG_DEBUG_FS=y
 # CONFIG_HEADERS_CHECK is not set
 # CONFIG_DEBUG_KERNEL is not set
 # CONFIG_SAMPLES is not set
-CONFIG_CMDLINE=""
+# CONFIG_CMDLINE_BOOL is not set
 
 #
 # Security options
diff --git a/arch/mips/configs/bcm63xx_defconfig b/arch/mips/configs/bcm63xx_defconfig
index ea00c18d1f7b..7fee0273c829 100644
--- a/arch/mips/configs/bcm63xx_defconfig
+++ b/arch/mips/configs/bcm63xx_defconfig
@@ -9,7 +9,6 @@ CONFIG_MIPS=y
 # Machine selection
 #
 # CONFIG_MACH_ALCHEMY is not set
-# CONFIG_BASLER_EXCITE is not set
 # CONFIG_BCM47XX is not set
 CONFIG_BCM63XX=y
 # CONFIG_MIPS_COBALT is not set
@@ -942,7 +941,9 @@ CONFIG_TRACING_SUPPORT=y
 # CONFIG_BLK_DEV_IO_TRACE is not set
 # CONFIG_SAMPLES is not set
 CONFIG_HAVE_ARCH_KGDB=y
+CONFIG_CMDLINE_BOOL=y
 CONFIG_CMDLINE="console=ttyS0,115200"
+# CONFIG_CMDLINE_OVERRIDE is not set
 
 #
 # Security options
diff --git a/arch/mips/configs/bigsur_defconfig b/arch/mips/configs/bigsur_defconfig
index 13d9eb4736c0..c2f06e38c854 100644
--- a/arch/mips/configs/bigsur_defconfig
+++ b/arch/mips/configs/bigsur_defconfig
@@ -9,7 +9,6 @@ CONFIG_MIPS=y
 # Machine selection
 #
 # CONFIG_MACH_ALCHEMY is not set
-# CONFIG_BASLER_EXCITE is not set
 # CONFIG_BCM47XX is not set
 # CONFIG_MIPS_COBALT is not set
 # CONFIG_MACH_DECSTATION is not set
@@ -1237,7 +1236,7 @@ CONFIG_DEBUG_MUTEXES=y
 # CONFIG_BACKTRACE_SELF_TEST is not set
 # CONFIG_FAULT_INJECTION is not set
 # CONFIG_SAMPLES is not set
-CONFIG_CMDLINE=""
+# CONFIG_CMDLINE_BOOL is not set
 # CONFIG_DEBUG_STACK_USAGE is not set
 # CONFIG_SB1XXX_CORELIS is not set
 # CONFIG_RUNTIME_DEBUG is not set
diff --git a/arch/mips/configs/capcella_defconfig b/arch/mips/configs/capcella_defconfig
index 185df23fd460..72b7e456916e 100644
--- a/arch/mips/configs/capcella_defconfig
+++ b/arch/mips/configs/capcella_defconfig
@@ -9,7 +9,6 @@ CONFIG_MIPS=y
 # Machine selection
 #
 # CONFIG_MACH_ALCHEMY is not set
-# CONFIG_BASLER_EXCITE is not set
 # CONFIG_MIPS_COBALT is not set
 # CONFIG_MACH_DECSTATION is not set
 # CONFIG_MACH_JAZZ is not set
@@ -783,7 +782,9 @@ CONFIG_ENABLE_MUST_CHECK=y
 # CONFIG_HEADERS_CHECK is not set
 # CONFIG_DEBUG_KERNEL is not set
 CONFIG_CROSSCOMPILE=y
+CONFIG_CMDLINE_BOOL=y
 CONFIG_CMDLINE="mem=32M console=ttyVR0,38400"
+# CONFIG_CMDLINE_OVERRIDE is not set
 
 #
 # Security options
diff --git a/arch/mips/configs/cavium-octeon_defconfig b/arch/mips/configs/cavium-octeon_defconfig
index 7afaa28a3768..c8507bc8e925 100644
--- a/arch/mips/configs/cavium-octeon_defconfig
+++ b/arch/mips/configs/cavium-octeon_defconfig
@@ -9,7 +9,6 @@ CONFIG_MIPS=y
 # Machine selection
 #
 # CONFIG_MACH_ALCHEMY is not set
-# CONFIG_BASLER_EXCITE is not set
 # CONFIG_BCM47XX is not set
 # CONFIG_MIPS_COBALT is not set
 # CONFIG_MACH_DECSTATION is not set
@@ -269,7 +268,6 @@ CONFIG_DEFAULT_CFQ=y
 # CONFIG_DEFAULT_NOOP is not set
 CONFIG_DEFAULT_IOSCHED="cfq"
 CONFIG_CLASSIC_RCU=y
-# CONFIG_PROBE_INITRD_HEADER is not set
 # CONFIG_FREEZER is not set
 
 #
@@ -822,7 +820,7 @@ CONFIG_SYSCTL_SYSCALL_CHECK=y
 # CONFIG_SAMPLES is not set
 CONFIG_HAVE_ARCH_KGDB=y
 # CONFIG_KGDB is not set
-CONFIG_CMDLINE=""
+# CONFIG_CMDLINE_BOOL is not set
 # CONFIG_DEBUG_STACK_USAGE is not set
 # CONFIG_RUNTIME_DEBUG is not set
 
diff --git a/arch/mips/configs/cobalt_defconfig b/arch/mips/configs/cobalt_defconfig
index 6c8cca8589ba..49e61312e006 100644
--- a/arch/mips/configs/cobalt_defconfig
+++ b/arch/mips/configs/cobalt_defconfig
@@ -9,7 +9,6 @@ CONFIG_MIPS=y
 # Machine selection
 #
 # CONFIG_MACH_ALCHEMY is not set
-# CONFIG_BASLER_EXCITE is not set
 # CONFIG_BCM47XX is not set
 CONFIG_MIPS_COBALT=y
 # CONFIG_MACH_DECSTATION is not set
@@ -1126,7 +1125,7 @@ CONFIG_FRAME_WARN=1024
 # CONFIG_SLUB_STATS is not set
 # CONFIG_DEBUG_MEMORY_INIT is not set
 # CONFIG_SAMPLES is not set
-CONFIG_CMDLINE=""
+# CONFIG_CMDLINE_BOOL is not set
 
 #
 # Security options
diff --git a/arch/mips/configs/db1000_defconfig b/arch/mips/configs/db1000_defconfig
index dbdf3bb1a34a..68e90cd6b2d4 100644
--- a/arch/mips/configs/db1000_defconfig
+++ b/arch/mips/configs/db1000_defconfig
@@ -23,7 +23,6 @@ CONFIG_MIPS_DB1000=y
 # CONFIG_MIPS_DB1550 is not set
 # CONFIG_MIPS_DB1200 is not set
 # CONFIG_MIPS_MIRAGE is not set
-# CONFIG_BASLER_EXCITE is not set
 # CONFIG_MIPS_COBALT is not set
 # CONFIG_MACH_DECSTATION is not set
 # CONFIG_MACH_JAZZ is not set
@@ -1090,7 +1089,7 @@ CONFIG_ENABLE_MUST_CHECK=y
 # CONFIG_DEBUG_KERNEL is not set
 CONFIG_LOG_BUF_SHIFT=14
 CONFIG_CROSSCOMPILE=y
-CONFIG_CMDLINE=""
+# CONFIG_CMDLINE_BOOL is not set
 
 #
 # Security options
diff --git a/arch/mips/configs/db1100_defconfig b/arch/mips/configs/db1100_defconfig
index fa6814475898..90812830e940 100644
--- a/arch/mips/configs/db1100_defconfig
+++ b/arch/mips/configs/db1100_defconfig
@@ -23,7 +23,6 @@ CONFIG_MIPS_DB1100=y
 # CONFIG_MIPS_DB1550 is not set
 # CONFIG_MIPS_DB1200 is not set
 # CONFIG_MIPS_MIRAGE is not set
-# CONFIG_BASLER_EXCITE is not set
 # CONFIG_MIPS_COBALT is not set
 # CONFIG_MACH_DECSTATION is not set
 # CONFIG_MACH_JAZZ is not set
@@ -1090,7 +1089,7 @@ CONFIG_ENABLE_MUST_CHECK=y
 # CONFIG_DEBUG_KERNEL is not set
 CONFIG_LOG_BUF_SHIFT=14
 CONFIG_CROSSCOMPILE=y
-CONFIG_CMDLINE=""
+# CONFIG_CMDLINE_BOOL is not set
 
 #
 # Security options
diff --git a/arch/mips/configs/db1200_defconfig b/arch/mips/configs/db1200_defconfig
index d73f1de43b5d..dabf03032e06 100644
--- a/arch/mips/configs/db1200_defconfig
+++ b/arch/mips/configs/db1200_defconfig
@@ -23,7 +23,6 @@ CONFIG_MACH_ALCHEMY=y
 # CONFIG_MIPS_DB1550 is not set
 CONFIG_MIPS_DB1200=y
 # CONFIG_MIPS_MIRAGE is not set
-# CONFIG_BASLER_EXCITE is not set
 # CONFIG_MIPS_COBALT is not set
 # CONFIG_MACH_DECSTATION is not set
 # CONFIG_MACH_JAZZ is not set
@@ -1172,7 +1171,9 @@ CONFIG_ENABLE_MUST_CHECK=y
 # CONFIG_DEBUG_KERNEL is not set
 CONFIG_LOG_BUF_SHIFT=14
 CONFIG_CROSSCOMPILE=y
+CONFIG_CMDLINE_BOOL=y
 CONFIG_CMDLINE="mem=48M"
+# CONFIG_CMDLINE_OVERRIDE is not set
 
 #
 # Security options
diff --git a/arch/mips/configs/db1500_defconfig b/arch/mips/configs/db1500_defconfig
index ec3e028a5b2e..a15131373138 100644
--- a/arch/mips/configs/db1500_defconfig
+++ b/arch/mips/configs/db1500_defconfig
@@ -23,7 +23,6 @@ CONFIG_MIPS_DB1500=y
 # CONFIG_MIPS_DB1550 is not set
 # CONFIG_MIPS_DB1200 is not set
 # CONFIG_MIPS_MIRAGE is not set
-# CONFIG_BASLER_EXCITE is not set
 # CONFIG_MIPS_COBALT is not set
 # CONFIG_MACH_DECSTATION is not set
 # CONFIG_MACH_JAZZ is not set
@@ -1390,7 +1389,7 @@ CONFIG_ENABLE_MUST_CHECK=y
 # CONFIG_DEBUG_KERNEL is not set
 CONFIG_LOG_BUF_SHIFT=14
 CONFIG_CROSSCOMPILE=y
-CONFIG_CMDLINE=""
+# CONFIG_CMDLINE_BOOL is not set
 
 #
 # Security options
diff --git a/arch/mips/configs/db1550_defconfig b/arch/mips/configs/db1550_defconfig
index 7631dae51be9..6b64339c0014 100644
--- a/arch/mips/configs/db1550_defconfig
+++ b/arch/mips/configs/db1550_defconfig
@@ -23,7 +23,6 @@ CONFIG_MACH_ALCHEMY=y
 CONFIG_MIPS_DB1550=y
 # CONFIG_MIPS_DB1200 is not set
 # CONFIG_MIPS_MIRAGE is not set
-# CONFIG_BASLER_EXCITE is not set
 # CONFIG_MIPS_COBALT is not set
 # CONFIG_MACH_DECSTATION is not set
 # CONFIG_MACH_JAZZ is not set
@@ -1207,7 +1206,7 @@ CONFIG_ENABLE_MUST_CHECK=y
 # CONFIG_DEBUG_KERNEL is not set
 CONFIG_LOG_BUF_SHIFT=14
 CONFIG_CROSSCOMPILE=y
-CONFIG_CMDLINE=""
+# CONFIG_CMDLINE_BOOL is not set
 
 #
 # Security options
diff --git a/arch/mips/configs/decstation_defconfig b/arch/mips/configs/decstation_defconfig
index 9e65e6a2dcb3..cbb4d86f2912 100644
--- a/arch/mips/configs/decstation_defconfig
+++ b/arch/mips/configs/decstation_defconfig
@@ -22,7 +22,6 @@ CONFIG_ZONE_DMA=y
 # CONFIG_MIPS_DB1550 is not set
 # CONFIG_MIPS_DB1200 is not set
 # CONFIG_MIPS_MIRAGE is not set
-# CONFIG_BASLER_EXCITE is not set
 # CONFIG_MIPS_COBALT is not set
 CONFIG_MACH_DECSTATION=y
 # CONFIG_MACH_JAZZ is not set
@@ -882,7 +881,7 @@ CONFIG_MAGIC_SYSRQ=y
 # CONFIG_DEBUG_KERNEL is not set
 CONFIG_LOG_BUF_SHIFT=14
 CONFIG_CROSSCOMPILE=y
-CONFIG_CMDLINE=""
+# CONFIG_CMDLINE_BOOL is not set
 
 #
 # Security options
diff --git a/arch/mips/configs/e55_defconfig b/arch/mips/configs/e55_defconfig
index 1bd84d42b14f..52968c46c806 100644
--- a/arch/mips/configs/e55_defconfig
+++ b/arch/mips/configs/e55_defconfig
@@ -9,7 +9,6 @@ CONFIG_MIPS=y
 # Machine selection
 #
 # CONFIG_MACH_ALCHEMY is not set
-# CONFIG_BASLER_EXCITE is not set
 # CONFIG_MIPS_COBALT is not set
 # CONFIG_MACH_DECSTATION is not set
 # CONFIG_MACH_JAZZ is not set
@@ -561,7 +560,9 @@ CONFIG_ENABLE_MUST_CHECK=y
 # CONFIG_HEADERS_CHECK is not set
 # CONFIG_DEBUG_KERNEL is not set
 CONFIG_CROSSCOMPILE=y
+CONFIG_CMDLINE_BOOL=y
 CONFIG_CMDLINE="console=ttyVR0,19200 ide0=0x1f0,0x3f6,40 mem=8M"
+# CONFIG_CMDLINE_OVERRIDE is not set
 
 #
 # Security options
diff --git a/arch/mips/configs/excite_defconfig b/arch/mips/configs/excite_defconfig
deleted file mode 100644
index 1995d43a2ed1..000000000000
--- a/arch/mips/configs/excite_defconfig
+++ /dev/null
@@ -1,1335 +0,0 @@
-#
-# Automatically generated make config: don't edit
-# Linux kernel version: 2.6.20
-# Tue Feb 20 21:47:31 2007
-#
-CONFIG_MIPS=y
-
-#
-# Machine selection
-#
-CONFIG_ZONE_DMA=y
-# CONFIG_MIPS_MTX1 is not set
-# CONFIG_MIPS_BOSPORUS is not set
-# CONFIG_MIPS_PB1000 is not set
-# CONFIG_MIPS_PB1100 is not set
-# CONFIG_MIPS_PB1500 is not set
-# CONFIG_MIPS_PB1550 is not set
-# CONFIG_MIPS_PB1200 is not set
-# CONFIG_MIPS_DB1000 is not set
-# CONFIG_MIPS_DB1100 is not set
-# CONFIG_MIPS_DB1500 is not set
-# CONFIG_MIPS_DB1550 is not set
-# CONFIG_MIPS_DB1200 is not set
-# CONFIG_MIPS_MIRAGE is not set
-CONFIG_BASLER_EXCITE=y
-# CONFIG_BASLER_EXCITE_PROTOTYPE is not set
-# CONFIG_MIPS_COBALT is not set
-# CONFIG_MACH_DECSTATION is not set
-# CONFIG_MACH_JAZZ is not set
-# CONFIG_MIPS_MALTA is not set
-# CONFIG_WR_PPMC is not set
-# CONFIG_MIPS_SIM is not set
-# CONFIG_MOMENCO_JAGUAR_ATX is not set
-# CONFIG_MIPS_XXS1500 is not set
-# CONFIG_PNX8550_JBS is not set
-# CONFIG_PNX8550_STB810 is not set
-# CONFIG_MACH_VR41XX is not set
-# CONFIG_PMC_YOSEMITE is not set
-# CONFIG_MARKEINS is not set
-# CONFIG_SGI_IP22 is not set
-# CONFIG_SGI_IP27 is not set
-# CONFIG_SGI_IP32 is not set
-# CONFIG_SIBYTE_BIGSUR is not set
-# CONFIG_SIBYTE_SWARM is not set
-# CONFIG_SIBYTE_SENTOSA is not set
-# CONFIG_SIBYTE_RHONE is not set
-# CONFIG_SIBYTE_CARMEL is not set
-# CONFIG_SIBYTE_LITTLESUR is not set
-# CONFIG_SIBYTE_CRHINE is not set
-# CONFIG_SIBYTE_CRHONE is not set
-# CONFIG_SNI_RM is not set
-# CONFIG_TOSHIBA_JMR3927 is not set
-# CONFIG_TOSHIBA_RBTX4927 is not set
-# CONFIG_TOSHIBA_RBTX4938 is not set
-CONFIG_RWSEM_GENERIC_SPINLOCK=y
-# CONFIG_ARCH_HAS_ILOG2_U32 is not set
-# CONFIG_ARCH_HAS_ILOG2_U64 is not set
-CONFIG_GENERIC_FIND_NEXT_BIT=y
-CONFIG_GENERIC_HWEIGHT=y
-CONFIG_GENERIC_CALIBRATE_DELAY=y
-CONFIG_GENERIC_TIME=y
-CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
-# CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ is not set
-CONFIG_DMA_COHERENT=y
-CONFIG_CPU_BIG_ENDIAN=y
-# CONFIG_CPU_LITTLE_ENDIAN is not set
-CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y
-CONFIG_IRQ_CPU=y
-CONFIG_IRQ_CPU_RM7K=y
-CONFIG_IRQ_CPU_RM9K=y
-CONFIG_MIPS_RM9122=y
-CONFIG_SERIAL_RM9000=y
-CONFIG_GPI_RM9000=y
-CONFIG_WDT_RM9000=y
-CONFIG_MIPS_L1_CACHE_SHIFT=5
-
-#
-# CPU selection
-#
-# CONFIG_CPU_MIPS32_R1 is not set
-# CONFIG_CPU_MIPS32_R2 is not set
-# CONFIG_CPU_MIPS64_R1 is not set
-# CONFIG_CPU_MIPS64_R2 is not set
-# CONFIG_CPU_R3000 is not set
-# CONFIG_CPU_TX39XX is not set
-# CONFIG_CPU_VR41XX is not set
-# CONFIG_CPU_R4300 is not set
-# CONFIG_CPU_R4X00 is not set
-# CONFIG_CPU_TX49XX is not set
-# CONFIG_CPU_R5000 is not set
-# CONFIG_CPU_R5432 is not set
-# CONFIG_CPU_R6000 is not set
-# CONFIG_CPU_NEVADA is not set
-# CONFIG_CPU_R8000 is not set
-# CONFIG_CPU_R10000 is not set
-# CONFIG_CPU_RM7000 is not set
-CONFIG_CPU_RM9000=y
-# CONFIG_CPU_SB1 is not set
-CONFIG_SYS_HAS_CPU_RM9000=y
-CONFIG_WEAK_ORDERING=y
-CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
-CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y
-CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
-CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y
-
-#
-# Kernel type
-#
-CONFIG_32BIT=y
-# CONFIG_64BIT is not set
-CONFIG_PAGE_SIZE_4KB=y
-# CONFIG_PAGE_SIZE_8KB is not set
-# CONFIG_PAGE_SIZE_16KB is not set
-# CONFIG_PAGE_SIZE_64KB is not set
-CONFIG_CPU_HAS_PREFETCH=y
-CONFIG_MIPS_MT_DISABLED=y
-# CONFIG_MIPS_MT_SMP is not set
-# CONFIG_MIPS_MT_SMTC is not set
-# CONFIG_MIPS_VPE_LOADER is not set
-# CONFIG_64BIT_PHYS_ADDR is not set
-CONFIG_CPU_HAS_SYNC=y
-CONFIG_GENERIC_HARDIRQS=y
-CONFIG_GENERIC_IRQ_PROBE=y
-CONFIG_CPU_SUPPORTS_HIGHMEM=y
-CONFIG_ARCH_FLATMEM_ENABLE=y
-CONFIG_SELECT_MEMORY_MODEL=y
-CONFIG_FLATMEM_MANUAL=y
-# CONFIG_DISCONTIGMEM_MANUAL is not set
-# CONFIG_SPARSEMEM_MANUAL is not set
-CONFIG_FLATMEM=y
-CONFIG_FLAT_NODE_MEM_MAP=y
-# CONFIG_SPARSEMEM_STATIC is not set
-CONFIG_SPLIT_PTLOCK_CPUS=4
-# CONFIG_RESOURCES_64BIT is not set
-CONFIG_ZONE_DMA_FLAG=1
-# CONFIG_HZ_48 is not set
-# CONFIG_HZ_100 is not set
-# CONFIG_HZ_128 is not set
-# CONFIG_HZ_250 is not set
-# CONFIG_HZ_256 is not set
-CONFIG_HZ_1000=y
-# CONFIG_HZ_1024 is not set
-CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
-CONFIG_HZ=1000
-# CONFIG_PREEMPT_NONE is not set
-# CONFIG_PREEMPT_VOLUNTARY is not set
-CONFIG_PREEMPT=y
-CONFIG_PREEMPT_BKL=y
-# CONFIG_KEXEC is not set
-CONFIG_LOCKDEP_SUPPORT=y
-CONFIG_STACKTRACE_SUPPORT=y
-CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
-
-#
-# Code maturity level options
-#
-CONFIG_EXPERIMENTAL=y
-CONFIG_BROKEN_ON_SMP=y
-CONFIG_LOCK_KERNEL=y
-CONFIG_INIT_ENV_ARG_LIMIT=32
-
-#
-# General setup
-#
-CONFIG_LOCALVERSION=""
-# CONFIG_LOCALVERSION_AUTO is not set
-CONFIG_SWAP=y
-CONFIG_SYSVIPC=y
-# CONFIG_IPC_NS is not set
-CONFIG_SYSVIPC_SYSCTL=y
-CONFIG_POSIX_MQUEUE=y
-# CONFIG_BSD_PROCESS_ACCT is not set
-# CONFIG_TASKSTATS is not set
-# CONFIG_UTS_NS is not set
-# CONFIG_AUDIT is not set
-# CONFIG_IKCONFIG is not set
-CONFIG_SYSFS_DEPRECATED=y
-# CONFIG_RELAY is not set
-CONFIG_CC_OPTIMIZE_FOR_SIZE=y
-CONFIG_SYSCTL=y
-CONFIG_EMBEDDED=y
-CONFIG_SYSCTL_SYSCALL=y
-CONFIG_KALLSYMS=y
-# CONFIG_KALLSYMS_EXTRA_PASS is not set
-CONFIG_HOTPLUG=y
-CONFIG_PRINTK=y
-CONFIG_BUG=y
-CONFIG_ELF_CORE=y
-CONFIG_BASE_FULL=y
-CONFIG_FUTEX=y
-CONFIG_EPOLL=y
-CONFIG_SHMEM=y
-CONFIG_SLAB=y
-CONFIG_VM_EVENT_COUNTERS=y
-CONFIG_RT_MUTEXES=y
-# CONFIG_TINY_SHMEM is not set
-CONFIG_BASE_SMALL=0
-# CONFIG_SLOB is not set
-
-#
-# Loadable module support
-#
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_MODULE_FORCE_UNLOAD is not set
-# CONFIG_MODVERSIONS is not set
-# CONFIG_MODULE_SRCVERSION_ALL is not set
-CONFIG_KMOD=y
-
-#
-# Block layer
-#
-CONFIG_BLOCK=y
-# CONFIG_LBD is not set
-# CONFIG_BLK_DEV_IO_TRACE is not set
-# CONFIG_LSF is not set
-
-#
-# IO Schedulers
-#
-CONFIG_IOSCHED_NOOP=y
-CONFIG_IOSCHED_AS=y
-CONFIG_IOSCHED_DEADLINE=y
-CONFIG_IOSCHED_CFQ=y
-CONFIG_DEFAULT_AS=y
-# CONFIG_DEFAULT_DEADLINE is not set
-# CONFIG_DEFAULT_CFQ is not set
-# CONFIG_DEFAULT_NOOP is not set
-CONFIG_DEFAULT_IOSCHED="anticipatory"
-
-#
-# Bus options (PCI, PCMCIA, EISA, ISA, TC)
-#
-CONFIG_HW_HAS_PCI=y
-CONFIG_PCI=y
-CONFIG_MMU=y
-
-#
-# PCCARD (PCMCIA/CardBus) support
-#
-# CONFIG_PCCARD is not set
-
-#
-# PCI Hotplug Support
-#
-# CONFIG_HOTPLUG_PCI is not set
-
-#
-# Executable file formats
-#
-CONFIG_BINFMT_ELF=y
-# CONFIG_BINFMT_MISC is not set
-CONFIG_TRAD_SIGNALS=y
-
-#
-# Power management options
-#
-CONFIG_PM=y
-# CONFIG_PM_LEGACY is not set
-# CONFIG_PM_DEBUG is not set
-# CONFIG_PM_SYSFS_DEPRECATED is not set
-
-#
-# Networking
-#
-CONFIG_NET=y
-
-#
-# Networking options
-#
-# CONFIG_NETDEBUG is not set
-CONFIG_PACKET=y
-CONFIG_PACKET_MMAP=y
-CONFIG_UNIX=y
-CONFIG_XFRM=y
-# CONFIG_XFRM_USER is not set
-# CONFIG_XFRM_SUB_POLICY is not set
-CONFIG_XFRM_MIGRATE=y
-# CONFIG_NET_KEY is not set
-CONFIG_INET=y
-# CONFIG_IP_MULTICAST is not set
-# CONFIG_IP_ADVANCED_ROUTER is not set
-CONFIG_IP_FIB_HASH=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_DHCP=y
-# CONFIG_IP_PNP_BOOTP is not set
-# CONFIG_IP_PNP_RARP is not set
-# CONFIG_NET_IPIP is not set
-# CONFIG_NET_IPGRE is not set
-# CONFIG_ARPD is not set
-# CONFIG_SYN_COOKIES is not set
-# CONFIG_INET_AH is not set
-# CONFIG_INET_ESP is not set
-# CONFIG_INET_IPCOMP is not set
-# CONFIG_INET_XFRM_TUNNEL is not set
-# CONFIG_INET_TUNNEL is not set
-CONFIG_INET_XFRM_MODE_TRANSPORT=m
-CONFIG_INET_XFRM_MODE_TUNNEL=m
-CONFIG_INET_XFRM_MODE_BEET=m
-CONFIG_INET_DIAG=y
-CONFIG_INET_TCP_DIAG=y
-# CONFIG_TCP_CONG_ADVANCED is not set
-CONFIG_TCP_CONG_CUBIC=y
-CONFIG_DEFAULT_TCP_CONG="cubic"
-CONFIG_TCP_MD5SIG=y
-# CONFIG_IPV6 is not set
-# CONFIG_INET6_XFRM_TUNNEL is not set
-# CONFIG_INET6_TUNNEL is not set
-CONFIG_NETWORK_SECMARK=y
-# CONFIG_NETFILTER is not set
-
-#
-# DCCP Configuration (EXPERIMENTAL)
-#
-# CONFIG_IP_DCCP is not set
-
-#
-# SCTP Configuration (EXPERIMENTAL)
-#
-# CONFIG_IP_SCTP is not set
-
-#
-# TIPC Configuration (EXPERIMENTAL)
-#
-# CONFIG_TIPC is not set
-# CONFIG_ATM is not set
-# CONFIG_BRIDGE is not set
-# CONFIG_VLAN_8021Q is not set
-# CONFIG_DECNET is not set
-# CONFIG_LLC2 is not set
-# CONFIG_IPX is not set
-# CONFIG_ATALK is not set
-# CONFIG_X25 is not set
-# CONFIG_LAPB is not set
-# CONFIG_ECONET is not set
-# CONFIG_WAN_ROUTER is not set
-
-#
-# QoS and/or fair queueing
-#
-# CONFIG_NET_SCHED is not set
-
-#
-# Network testing
-#
-# CONFIG_NET_PKTGEN is not set
-# CONFIG_HAMRADIO is not set
-# CONFIG_IRDA is not set
-# CONFIG_BT is not set
-# CONFIG_IEEE80211 is not set
-
-#
-# Device Drivers
-#
-
-#
-# Generic Driver Options
-#
-CONFIG_STANDALONE=y
-CONFIG_PREVENT_FIRMWARE_BUILD=y
-CONFIG_FW_LOADER=m
-# CONFIG_SYS_HYPERVISOR is not set
-
-#
-# Connector - unified userspace <-> kernelspace linker
-#
-# CONFIG_CONNECTOR is not set
-
-#
-# Memory Technology Devices (MTD)
-#
-CONFIG_MTD=y
-# CONFIG_MTD_DEBUG is not set
-# CONFIG_MTD_CONCAT is not set
-CONFIG_MTD_PARTITIONS=y
-# CONFIG_MTD_REDBOOT_PARTS is not set
-# CONFIG_MTD_CMDLINE_PARTS is not set
-
-#
-# User Modules And Translation Layers
-#
-CONFIG_MTD_CHAR=y
-CONFIG_MTD_BLKDEVS=y
-CONFIG_MTD_BLOCK=y
-# CONFIG_FTL is not set
-# CONFIG_NFTL is not set
-# CONFIG_INFTL is not set
-# CONFIG_RFD_FTL is not set
-# CONFIG_SSFDC is not set
-
-#
-# RAM/ROM/Flash chip drivers
-#
-# CONFIG_MTD_CFI is not set
-# CONFIG_MTD_JEDECPROBE is not set
-CONFIG_MTD_MAP_BANK_WIDTH_1=y
-CONFIG_MTD_MAP_BANK_WIDTH_2=y
-CONFIG_MTD_MAP_BANK_WIDTH_4=y
-# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
-# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
-# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
-CONFIG_MTD_CFI_I1=y
-CONFIG_MTD_CFI_I2=y
-# CONFIG_MTD_CFI_I4 is not set
-# CONFIG_MTD_CFI_I8 is not set
-# CONFIG_MTD_RAM is not set
-# CONFIG_MTD_ROM is not set
-# CONFIG_MTD_ABSENT is not set
-# CONFIG_MTD_OBSOLETE_CHIPS is not set
-
-#
-# Mapping drivers for chip access
-#
-# CONFIG_MTD_COMPLEX_MAPPINGS is not set
-# CONFIG_MTD_PLATRAM is not set
-
-#
-# Self-contained MTD device drivers
-#
-# CONFIG_MTD_PMC551 is not set
-# CONFIG_MTD_SLRAM is not set
-# CONFIG_MTD_PHRAM is not set
-# CONFIG_MTD_MTDRAM is not set
-# CONFIG_MTD_BLOCK2MTD is not set
-
-#
-# Disk-On-Chip Device Drivers
-#
-# CONFIG_MTD_DOC2000 is not set
-# CONFIG_MTD_DOC2001 is not set
-# CONFIG_MTD_DOC2001PLUS is not set
-
-#
-# NAND Flash Device Drivers
-#
-CONFIG_MTD_NAND=y
-CONFIG_MTD_NAND_VERIFY_WRITE=y
-# CONFIG_MTD_NAND_ECC_SMC is not set
-CONFIG_MTD_NAND_IDS=y
-# CONFIG_MTD_NAND_DISKONCHIP is not set
-# CONFIG_MTD_NAND_BASLER_EXCITE is not set
-# CONFIG_MTD_NAND_CAFE is not set
-# CONFIG_MTD_NAND_NANDSIM is not set
-
-#
-# OneNAND Flash Device Drivers
-#
-# CONFIG_MTD_ONENAND is not set
-
-#
-# Parallel port support
-#
-# CONFIG_PARPORT is not set
-
-#
-# Plug and Play support
-#
-# CONFIG_PNPACPI is not set
-
-#
-# Block devices
-#
-# CONFIG_BLK_CPQ_DA is not set
-# CONFIG_BLK_CPQ_CISS_DA is not set
-# CONFIG_BLK_DEV_DAC960 is not set
-# CONFIG_BLK_DEV_UMEM is not set
-# CONFIG_BLK_DEV_COW_COMMON is not set
-CONFIG_BLK_DEV_LOOP=m
-# CONFIG_BLK_DEV_CRYPTOLOOP is not set
-# CONFIG_BLK_DEV_NBD is not set
-# CONFIG_BLK_DEV_SX8 is not set
-# CONFIG_BLK_DEV_UB is not set
-# CONFIG_BLK_DEV_RAM is not set
-# CONFIG_BLK_DEV_INITRD is not set
-# CONFIG_CDROM_PKTCDVD is not set
-# CONFIG_ATA_OVER_ETH is not set
-
-#
-# Misc devices
-#
-CONFIG_SGI_IOC4=m
-# CONFIG_TIFM_CORE is not set
-
-#
-# ATA/ATAPI/MFM/RLL support
-#
-# CONFIG_IDE is not set
-
-#
-# SCSI device support
-#
-# CONFIG_RAID_ATTRS is not set
-CONFIG_SCSI=y
-CONFIG_SCSI_TGT=m
-# CONFIG_SCSI_NETLINK is not set
-# CONFIG_SCSI_PROC_FS is not set
-
-#
-# SCSI support type (disk, tape, CD-ROM)
-#
-CONFIG_BLK_DEV_SD=y
-# CONFIG_CHR_DEV_ST is not set
-# CONFIG_CHR_DEV_OSST is not set
-# CONFIG_BLK_DEV_SR is not set
-# CONFIG_CHR_DEV_SG is not set
-# CONFIG_CHR_DEV_SCH is not set
-
-#
-# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
-#
-# CONFIG_SCSI_MULTI_LUN is not set
-# CONFIG_SCSI_CONSTANTS is not set
-# CONFIG_SCSI_LOGGING is not set
-CONFIG_SCSI_SCAN_ASYNC=y
-
-#
-# SCSI Transports
-#
-# CONFIG_SCSI_SPI_ATTRS is not set
-# CONFIG_SCSI_FC_ATTRS is not set
-# CONFIG_SCSI_ISCSI_ATTRS is not set
-CONFIG_SCSI_SAS_ATTRS=m
-CONFIG_SCSI_SAS_LIBSAS=m
-# CONFIG_SCSI_SAS_LIBSAS_DEBUG is not set
-
-#
-# SCSI low-level drivers
-#
-# CONFIG_ISCSI_TCP is not set
-# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
-# CONFIG_SCSI_3W_9XXX is not set
-# CONFIG_SCSI_ACARD is not set
-# CONFIG_SCSI_AACRAID is not set
-# CONFIG_SCSI_AIC7XXX is not set
-# CONFIG_SCSI_AIC7XXX_OLD is not set
-# CONFIG_SCSI_AIC79XX is not set
-CONFIG_SCSI_AIC94XX=m
-# CONFIG_AIC94XX_DEBUG is not set
-# CONFIG_SCSI_DPT_I2O is not set
-# CONFIG_SCSI_ARCMSR is not set
-# CONFIG_MEGARAID_NEWGEN is not set
-# CONFIG_MEGARAID_LEGACY is not set
-# CONFIG_MEGARAID_SAS is not set
-# CONFIG_SCSI_HPTIOP is not set
-# CONFIG_SCSI_DMX3191D is not set
-# CONFIG_SCSI_FUTURE_DOMAIN is not set
-# CONFIG_SCSI_IPS is not set
-# CONFIG_SCSI_INITIO is not set
-# CONFIG_SCSI_INIA100 is not set
-# CONFIG_SCSI_STEX is not set
-# CONFIG_SCSI_SYM53C8XX_2 is not set
-# CONFIG_SCSI_QLOGIC_1280 is not set
-# CONFIG_SCSI_QLA_FC is not set
-# CONFIG_SCSI_QLA_ISCSI is not set
-# CONFIG_SCSI_LPFC is not set
-# CONFIG_SCSI_DC395x is not set
-# CONFIG_SCSI_DC390T is not set
-# CONFIG_SCSI_NSP32 is not set
-# CONFIG_SCSI_DEBUG is not set
-# CONFIG_SCSI_SRP is not set
-
-#
-# Serial ATA (prod) and Parallel ATA (experimental) drivers
-#
-# CONFIG_ATA is not set
-
-#
-# Multi-device support (RAID and LVM)
-#
-# CONFIG_MD is not set
-
-#
-# Fusion MPT device support
-#
-# CONFIG_FUSION is not set
-# CONFIG_FUSION_SPI is not set
-# CONFIG_FUSION_FC is not set
-# CONFIG_FUSION_SAS is not set
-
-#
-# IEEE 1394 (FireWire) support
-#
-# CONFIG_IEEE1394 is not set
-
-#
-# I2O device support
-#
-# CONFIG_I2O is not set
-
-#
-# Network device support
-#
-CONFIG_NETDEVICES=y
-# CONFIG_DUMMY is not set
-# CONFIG_BONDING is not set
-# CONFIG_EQUALIZER is not set
-# CONFIG_TUN is not set
-
-#
-# ARCnet devices
-#
-# CONFIG_ARCNET is not set
-
-#
-# PHY device support
-#
-
-#
-# Ethernet (10 or 100Mbit)
-#
-# CONFIG_NET_ETHERNET is not set
-
-#
-# Ethernet (1000 Mbit)
-#
-# CONFIG_ACENIC is not set
-# CONFIG_DL2K is not set
-# CONFIG_E1000 is not set
-# CONFIG_NS83820 is not set
-# CONFIG_HAMACHI is not set
-# CONFIG_YELLOWFIN is not set
-# CONFIG_R8169 is not set
-# CONFIG_SIS190 is not set
-# CONFIG_SKGE is not set
-# CONFIG_SKY2 is not set
-# CONFIG_SK98LIN is not set
-# CONFIG_TIGON3 is not set
-# CONFIG_BNX2 is not set
-CONFIG_QLA3XXX=m
-# CONFIG_ATL1 is not set
-
-#
-# Ethernet (10000 Mbit)
-#
-# CONFIG_CHELSIO_T1 is not set
-CONFIG_CHELSIO_T3=m
-# CONFIG_IXGB is not set
-# CONFIG_S2IO is not set
-# CONFIG_MYRI10GE is not set
-CONFIG_NETXEN_NIC=m
-
-#
-# Token Ring devices
-#
-# CONFIG_TR is not set
-
-#
-# Wireless LAN (non-hamradio)
-#
-# CONFIG_NET_RADIO is not set
-
-#
-# Wan interfaces
-#
-# CONFIG_WAN is not set
-# CONFIG_FDDI is not set
-# CONFIG_HIPPI is not set
-# CONFIG_PPP is not set
-# CONFIG_SLIP is not set
-# CONFIG_NET_FC is not set
-# CONFIG_SHAPER is not set
-# CONFIG_NETCONSOLE is not set
-# CONFIG_NETPOLL is not set
-# CONFIG_NET_POLL_CONTROLLER is not set
-
-#
-# ISDN subsystem
-#
-# CONFIG_ISDN is not set
-
-#
-# Telephony Support
-#
-# CONFIG_PHONE is not set
-
-#
-# Input device support
-#
-CONFIG_INPUT=y
-# CONFIG_INPUT_FF_MEMLESS is not set
-
-#
-# Userland interfaces
-#
-CONFIG_INPUT_MOUSEDEV=m
-CONFIG_INPUT_MOUSEDEV_PSAUX=y
-CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
-CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
-# CONFIG_INPUT_JOYDEV is not set
-# CONFIG_INPUT_TSDEV is not set
-CONFIG_INPUT_EVDEV=m
-# CONFIG_INPUT_EVBUG is not set
-
-#
-# Input Device Drivers
-#
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-# CONFIG_INPUT_JOYSTICK is not set
-# CONFIG_INPUT_TOUCHSCREEN is not set
-# CONFIG_INPUT_MISC is not set
-
-#
-# Hardware I/O ports
-#
-# CONFIG_SERIO is not set
-# CONFIG_GAMEPORT is not set
-
-#
-# Character devices
-#
-CONFIG_VT=y
-CONFIG_VT_CONSOLE=y
-CONFIG_HW_CONSOLE=y
-CONFIG_VT_HW_CONSOLE_BINDING=y
-# CONFIG_SERIAL_NONSTANDARD is not set
-
-#
-# Serial drivers
-#
-CONFIG_SERIAL_8250=y
-CONFIG_SERIAL_8250_CONSOLE=y
-CONFIG_SERIAL_8250_PCI=y
-CONFIG_SERIAL_8250_NR_UARTS=2
-CONFIG_SERIAL_8250_RUNTIME_UARTS=2
-CONFIG_SERIAL_8250_EXTENDED=y
-# CONFIG_SERIAL_8250_MANY_PORTS is not set
-CONFIG_SERIAL_8250_SHARE_IRQ=y
-# CONFIG_SERIAL_8250_DETECT_IRQ is not set
-# CONFIG_SERIAL_8250_RSA is not set
-
-#
-# Non-8250 serial port support
-#
-CONFIG_SERIAL_CORE=y
-CONFIG_SERIAL_CORE_CONSOLE=y
-# CONFIG_SERIAL_JSM is not set
-CONFIG_UNIX98_PTYS=y
-# CONFIG_LEGACY_PTYS is not set
-
-#
-# IPMI
-#
-# CONFIG_IPMI_HANDLER is not set
-
-#
-# Watchdog Cards
-#
-CONFIG_WATCHDOG=y
-# CONFIG_WATCHDOG_NOWAYOUT is not set
-
-#
-# Watchdog Device Drivers
-#
-# CONFIG_SOFT_WATCHDOG is not set
-CONFIG_WDT_RM9K_GPI=m
-
-#
-# PCI-based Watchdog Cards
-#
-# CONFIG_PCIPCWATCHDOG is not set
-# CONFIG_WDTPCI is not set
-
-#
-# USB-based Watchdog Cards
-#
-# CONFIG_USBPCWATCHDOG is not set
-# CONFIG_HW_RANDOM is not set
-# CONFIG_RTC is not set
-# CONFIG_GEN_RTC is not set
-# CONFIG_DTLK is not set
-# CONFIG_R3964 is not set
-# CONFIG_APPLICOM is not set
-# CONFIG_DRM is not set
-# CONFIG_RAW_DRIVER is not set
-
-#
-# TPM devices
-#
-# CONFIG_TCG_TPM is not set
-
-#
-# I2C support
-#
-# CONFIG_I2C is not set
-
-#
-# SPI support
-#
-# CONFIG_SPI is not set
-# CONFIG_SPI_MASTER is not set
-
-#
-# Dallas's 1-wire bus
-#
-# CONFIG_W1 is not set
-
-#
-# Hardware Monitoring support
-#
-# CONFIG_HWMON is not set
-# CONFIG_HWMON_VID is not set
-
-#
-# Multimedia devices
-#
-# CONFIG_VIDEO_DEV is not set
-
-#
-# Digital Video Broadcasting Devices
-#
-# CONFIG_DVB is not set
-# CONFIG_USB_DABUSB is not set
-
-#
-# Graphics support
-#
-# CONFIG_FIRMWARE_EDID is not set
-CONFIG_FB=y
-# CONFIG_FB_CFB_FILLRECT is not set
-# CONFIG_FB_CFB_COPYAREA is not set
-# CONFIG_FB_CFB_IMAGEBLIT is not set
-# CONFIG_FB_SVGALIB is not set
-# CONFIG_FB_MACMODES is not set
-# CONFIG_FB_BACKLIGHT is not set
-# CONFIG_FB_MODE_HELPERS is not set
-# CONFIG_FB_TILEBLITTING is not set
-# CONFIG_FB_CIRRUS is not set
-# CONFIG_FB_PM2 is not set
-# CONFIG_FB_CYBER2000 is not set
-# CONFIG_FB_ASILIANT is not set
-# CONFIG_FB_IMSTT is not set
-# CONFIG_FB_S1D13XXX is not set
-# CONFIG_FB_NVIDIA is not set
-# CONFIG_FB_RIVA is not set
-# CONFIG_FB_MATROX is not set
-# CONFIG_FB_RADEON is not set
-# CONFIG_FB_ATY128 is not set
-# CONFIG_FB_ATY is not set
-# CONFIG_FB_S3 is not set
-# CONFIG_FB_SAVAGE is not set
-# CONFIG_FB_SIS is not set
-# CONFIG_FB_NEOMAGIC is not set
-# CONFIG_FB_KYRO is not set
-# CONFIG_FB_3DFX is not set
-# CONFIG_FB_VOODOO1 is not set
-# CONFIG_FB_SMIVGX is not set
-# CONFIG_FB_TRIDENT is not set
-# CONFIG_FB_VIRTUAL is not set
-
-#
-# Console display driver support
-#
-# CONFIG_VGA_CONSOLE is not set
-CONFIG_DUMMY_CONSOLE=y
-CONFIG_FRAMEBUFFER_CONSOLE=m
-# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
-# CONFIG_FONTS is not set
-CONFIG_FONT_8x8=y
-CONFIG_FONT_8x16=y
-
-#
-# Logo configuration
-#
-# CONFIG_LOGO is not set
-# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
-
-#
-# Sound
-#
-# CONFIG_SOUND is not set
-
-#
-# HID Devices
-#
-CONFIG_HID=y
-# CONFIG_HID_DEBUG is not set
-
-#
-# USB support
-#
-CONFIG_USB_ARCH_HAS_HCD=y
-CONFIG_USB_ARCH_HAS_OHCI=y
-CONFIG_USB_ARCH_HAS_EHCI=y
-CONFIG_USB=y
-# CONFIG_USB_DEBUG is not set
-
-#
-# Miscellaneous USB options
-#
-CONFIG_USB_DEVICEFS=y
-# CONFIG_USB_DYNAMIC_MINORS is not set
-# CONFIG_USB_SUSPEND is not set
-# CONFIG_USB_OTG is not set
-
-#
-# USB Host Controller Drivers
-#
-CONFIG_USB_EHCI_HCD=y
-# CONFIG_USB_EHCI_SPLIT_ISO is not set
-# CONFIG_USB_EHCI_ROOT_HUB_TT is not set
-# CONFIG_USB_EHCI_TT_NEWSCHED is not set
-# CONFIG_USB_EHCI_BIG_ENDIAN_MMIO is not set
-# CONFIG_USB_ISP116X_HCD is not set
-CONFIG_USB_OHCI_HCD=y
-# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
-# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
-CONFIG_USB_OHCI_LITTLE_ENDIAN=y
-# CONFIG_USB_UHCI_HCD is not set
-# CONFIG_USB_SL811_HCD is not set
-
-#
-# USB Device Class drivers
-#
-# CONFIG_USB_ACM is not set
-# CONFIG_USB_PRINTER is not set
-
-#
-# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
-#
-
-#
-# may also be needed; see USB_STORAGE Help for more information
-#
-CONFIG_USB_STORAGE=y
-# CONFIG_USB_STORAGE_DEBUG is not set
-# CONFIG_USB_STORAGE_DATAFAB is not set
-# CONFIG_USB_STORAGE_FREECOM is not set
-# CONFIG_USB_STORAGE_DPCM is not set
-# CONFIG_USB_STORAGE_USBAT is not set
-# CONFIG_USB_STORAGE_SDDR09 is not set
-# CONFIG_USB_STORAGE_SDDR55 is not set
-# CONFIG_USB_STORAGE_JUMPSHOT is not set
-# CONFIG_USB_STORAGE_ALAUDA is not set
-# CONFIG_USB_STORAGE_KARMA is not set
-# CONFIG_USB_LIBUSUAL is not set
-
-#
-# USB Input Devices
-#
-CONFIG_USB_HID=m
-# CONFIG_USB_HIDINPUT_POWERBOOK is not set
-# CONFIG_HID_FF is not set
-# CONFIG_USB_HIDDEV is not set
-
-#
-# USB HID Boot Protocol drivers
-#
-# CONFIG_USB_KBD is not set
-# CONFIG_USB_MOUSE is not set
-# CONFIG_USB_AIPTEK is not set
-# CONFIG_USB_WACOM is not set
-# CONFIG_USB_ACECAD is not set
-# CONFIG_USB_KBTAB is not set
-# CONFIG_USB_POWERMATE is not set
-# CONFIG_USB_TOUCHSCREEN is not set
-# CONFIG_USB_YEALINK is not set
-# CONFIG_USB_XPAD is not set
-# CONFIG_USB_ATI_REMOTE is not set
-# CONFIG_USB_ATI_REMOTE2 is not set
-# CONFIG_USB_KEYSPAN_REMOTE is not set
-# CONFIG_USB_APPLETOUCH is not set
-# CONFIG_USB_GTCO is not set
-
-#
-# USB Imaging devices
-#
-# CONFIG_USB_MDC800 is not set
-# CONFIG_USB_MICROTEK is not set
-
-#
-# USB Network Adapters
-#
-# CONFIG_USB_CATC is not set
-# CONFIG_USB_KAWETH is not set
-# CONFIG_USB_PEGASUS is not set
-# CONFIG_USB_RTL8150 is not set
-# CONFIG_USB_USBNET_MII is not set
-# CONFIG_USB_USBNET is not set
-# CONFIG_USB_MON is not set
-
-#
-# USB port drivers
-#
-
-#
-# USB Serial Converter support
-#
-# CONFIG_USB_SERIAL is not set
-
-#
-# USB Miscellaneous drivers
-#
-# CONFIG_USB_EMI62 is not set
-# CONFIG_USB_EMI26 is not set
-# CONFIG_USB_ADUTUX is not set
-# CONFIG_USB_AUERSWALD is not set
-# CONFIG_USB_RIO500 is not set
-# CONFIG_USB_LEGOTOWER is not set
-# CONFIG_USB_LCD is not set
-# CONFIG_USB_BERRY_CHARGE is not set
-# CONFIG_USB_LED is not set
-# CONFIG_USB_CYPRESS_CY7C63 is not set
-# CONFIG_USB_CYTHERM is not set
-# CONFIG_USB_PHIDGET is not set
-# CONFIG_USB_IDMOUSE is not set
-# CONFIG_USB_FTDI_ELAN is not set
-# CONFIG_USB_APPLEDISPLAY is not set
-# CONFIG_USB_SISUSBVGA is not set
-# CONFIG_USB_LD is not set
-# CONFIG_USB_TRANCEVIBRATOR is not set
-# CONFIG_USB_TEST is not set
-
-#
-# USB DSL modem support
-#
-
-#
-# USB Gadget Support
-#
-# CONFIG_USB_GADGET is not set
-
-#
-# MMC/SD Card support
-#
-# CONFIG_MMC is not set
-
-#
-# LED devices
-#
-# CONFIG_NEW_LEDS is not set
-
-#
-# LED drivers
-#
-
-#
-# LED Triggers
-#
-
-#
-# InfiniBand support
-#
-# CONFIG_INFINIBAND is not set
-
-#
-# EDAC - error detection and reporting (RAS) (EXPERIMENTAL)
-#
-
-#
-# Real Time Clock
-#
-# CONFIG_RTC_CLASS is not set
-
-#
-# DMA Engine support
-#
-# CONFIG_DMA_ENGINE is not set
-
-#
-# DMA Clients
-#
-
-#
-# DMA Devices
-#
-
-#
-# Auxiliary Display support
-#
-
-#
-# Virtualization
-#
-
-#
-# File systems
-#
-CONFIG_EXT2_FS=y
-# CONFIG_EXT2_FS_XATTR is not set
-# CONFIG_EXT2_FS_XIP is not set
-# CONFIG_EXT3_FS is not set
-# CONFIG_EXT4DEV_FS is not set
-# CONFIG_REISERFS_FS is not set
-# CONFIG_JFS_FS is not set
-CONFIG_FS_POSIX_ACL=y
-# CONFIG_XFS_FS is not set
-# CONFIG_GFS2_FS is not set
-# CONFIG_OCFS2_FS is not set
-# CONFIG_MINIX_FS is not set
-# CONFIG_ROMFS_FS is not set
-CONFIG_INOTIFY=y
-CONFIG_INOTIFY_USER=y
-# CONFIG_QUOTA is not set
-# CONFIG_DNOTIFY is not set
-# CONFIG_AUTOFS_FS is not set
-# CONFIG_AUTOFS4_FS is not set
-# CONFIG_FUSE_FS is not set
-CONFIG_GENERIC_ACL=y
-
-#
-# CD-ROM/DVD Filesystems
-#
-# CONFIG_ISO9660_FS is not set
-# CONFIG_UDF_FS is not set
-
-#
-# DOS/FAT/NT Filesystems
-#
-CONFIG_FAT_FS=m
-CONFIG_MSDOS_FS=m
-CONFIG_VFAT_FS=m
-CONFIG_FAT_DEFAULT_CODEPAGE=437
-CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
-# CONFIG_NTFS_FS is not set
-
-#
-# Pseudo filesystems
-#
-CONFIG_PROC_FS=y
-CONFIG_PROC_KCORE=y
-CONFIG_PROC_SYSCTL=y
-CONFIG_SYSFS=y
-CONFIG_TMPFS=y
-CONFIG_TMPFS_POSIX_ACL=y
-# CONFIG_HUGETLB_PAGE is not set
-CONFIG_RAMFS=y
-CONFIG_CONFIGFS_FS=m
-
-#
-# Miscellaneous filesystems
-#
-# CONFIG_ADFS_FS is not set
-# CONFIG_AFFS_FS is not set
-# CONFIG_HFS_FS is not set
-# CONFIG_HFSPLUS_FS is not set
-# CONFIG_BEFS_FS is not set
-# CONFIG_BFS_FS is not set
-# CONFIG_EFS_FS is not set
-CONFIG_JFFS2_FS=y
-CONFIG_JFFS2_FS_DEBUG=0
-CONFIG_JFFS2_FS_WRITEBUFFER=y
-# CONFIG_JFFS2_SUMMARY is not set
-# CONFIG_JFFS2_FS_XATTR is not set
-# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
-CONFIG_JFFS2_ZLIB=y
-CONFIG_JFFS2_RTIME=y
-# CONFIG_JFFS2_RUBIN is not set
-# CONFIG_CRAMFS is not set
-# CONFIG_VXFS_FS is not set
-# CONFIG_HPFS_FS is not set
-# CONFIG_QNX4FS_FS is not set
-# CONFIG_SYSV_FS is not set
-# CONFIG_UFS_FS is not set
-
-#
-# Network File Systems
-#
-CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
-# CONFIG_NFS_V3_ACL is not set
-# CONFIG_NFS_V4 is not set
-# CONFIG_NFS_DIRECTIO is not set
-# CONFIG_NFSD is not set
-CONFIG_ROOT_NFS=y
-CONFIG_LOCKD=y
-CONFIG_LOCKD_V4=y
-CONFIG_NFS_COMMON=y
-CONFIG_SUNRPC=y
-# CONFIG_RPCSEC_GSS_KRB5 is not set
-# CONFIG_RPCSEC_GSS_SPKM3 is not set
-# CONFIG_SMB_FS is not set
-# CONFIG_CIFS is not set
-# CONFIG_NCP_FS is not set
-# CONFIG_CODA_FS is not set
-# CONFIG_AFS_FS is not set
-# CONFIG_9P_FS is not set
-
-#
-# Partition Types
-#
-CONFIG_PARTITION_ADVANCED=y
-# CONFIG_ACORN_PARTITION is not set
-# CONFIG_OSF_PARTITION is not set
-# CONFIG_AMIGA_PARTITION is not set
-# CONFIG_ATARI_PARTITION is not set
-# CONFIG_MAC_PARTITION is not set
-CONFIG_MSDOS_PARTITION=y
-# CONFIG_BSD_DISKLABEL is not set
-# CONFIG_MINIX_SUBPARTITION is not set
-# CONFIG_SOLARIS_X86_PARTITION is not set
-# CONFIG_UNIXWARE_DISKLABEL is not set
-# CONFIG_LDM_PARTITION is not set
-# CONFIG_SGI_PARTITION is not set
-# CONFIG_ULTRIX_PARTITION is not set
-# CONFIG_SUN_PARTITION is not set
-# CONFIG_KARMA_PARTITION is not set
-# CONFIG_EFI_PARTITION is not set
-
-#
-# Native Language Support
-#
-CONFIG_NLS=y
-CONFIG_NLS_DEFAULT="iso8859-1"
-CONFIG_NLS_CODEPAGE_437=m
-# CONFIG_NLS_CODEPAGE_737 is not set
-# CONFIG_NLS_CODEPAGE_775 is not set
-CONFIG_NLS_CODEPAGE_850=m
-# CONFIG_NLS_CODEPAGE_852 is not set
-# CONFIG_NLS_CODEPAGE_855 is not set
-# CONFIG_NLS_CODEPAGE_857 is not set
-# CONFIG_NLS_CODEPAGE_860 is not set
-# CONFIG_NLS_CODEPAGE_861 is not set
-# CONFIG_NLS_CODEPAGE_862 is not set
-# CONFIG_NLS_CODEPAGE_863 is not set
-# CONFIG_NLS_CODEPAGE_864 is not set
-# CONFIG_NLS_CODEPAGE_865 is not set
-# CONFIG_NLS_CODEPAGE_866 is not set
-# CONFIG_NLS_CODEPAGE_869 is not set
-# CONFIG_NLS_CODEPAGE_936 is not set
-# CONFIG_NLS_CODEPAGE_950 is not set
-# CONFIG_NLS_CODEPAGE_932 is not set
-# CONFIG_NLS_CODEPAGE_949 is not set
-# CONFIG_NLS_CODEPAGE_874 is not set
-# CONFIG_NLS_ISO8859_8 is not set
-# CONFIG_NLS_CODEPAGE_1250 is not set
-# CONFIG_NLS_CODEPAGE_1251 is not set
-# CONFIG_NLS_ASCII is not set
-CONFIG_NLS_ISO8859_1=m
-# CONFIG_NLS_ISO8859_2 is not set
-# CONFIG_NLS_ISO8859_3 is not set
-# CONFIG_NLS_ISO8859_4 is not set
-# CONFIG_NLS_ISO8859_5 is not set
-# CONFIG_NLS_ISO8859_6 is not set
-# CONFIG_NLS_ISO8859_7 is not set
-# CONFIG_NLS_ISO8859_9 is not set
-# CONFIG_NLS_ISO8859_13 is not set
-# CONFIG_NLS_ISO8859_14 is not set
-# CONFIG_NLS_ISO8859_15 is not set
-# CONFIG_NLS_KOI8_R is not set
-# CONFIG_NLS_KOI8_U is not set
-# CONFIG_NLS_UTF8 is not set
-
-#
-# Distributed Lock Manager
-#
-CONFIG_DLM=m
-CONFIG_DLM_TCP=y
-# CONFIG_DLM_SCTP is not set
-# CONFIG_DLM_DEBUG is not set
-
-#
-# Profiling support
-#
-# CONFIG_PROFILING is not set
-
-#
-# Kernel hacking
-#
-CONFIG_TRACE_IRQFLAGS_SUPPORT=y
-# CONFIG_PRINTK_TIME is not set
-CONFIG_ENABLE_MUST_CHECK=y
-# CONFIG_MAGIC_SYSRQ is not set
-# CONFIG_UNUSED_SYMBOLS is not set
-# CONFIG_DEBUG_FS is not set
-# CONFIG_HEADERS_CHECK is not set
-# CONFIG_DEBUG_KERNEL is not set
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_CROSSCOMPILE=y
-CONFIG_CMDLINE=""
-
-#
-# Security options
-#
-# CONFIG_KEYS is not set
-# CONFIG_SECURITY is not set
-
-#
-# Cryptographic options
-#
-CONFIG_CRYPTO=y
-CONFIG_CRYPTO_ALGAPI=y
-CONFIG_CRYPTO_BLKCIPHER=m
-CONFIG_CRYPTO_HASH=m
-CONFIG_CRYPTO_MANAGER=m
-# CONFIG_CRYPTO_HMAC is not set
-CONFIG_CRYPTO_XCBC=m
-# CONFIG_CRYPTO_NULL is not set
-# CONFIG_CRYPTO_MD4 is not set
-CONFIG_CRYPTO_MD5=y
-# CONFIG_CRYPTO_SHA1 is not set
-# CONFIG_CRYPTO_SHA256 is not set
-# CONFIG_CRYPTO_SHA512 is not set
-# CONFIG_CRYPTO_WP512 is not set
-# CONFIG_CRYPTO_TGR192 is not set
-CONFIG_CRYPTO_GF128MUL=m
-CONFIG_CRYPTO_ECB=m
-CONFIG_CRYPTO_CBC=m
-CONFIG_CRYPTO_PCBC=m
-CONFIG_CRYPTO_LRW=m
-# CONFIG_CRYPTO_DES is not set
-CONFIG_CRYPTO_FCRYPT=m
-# CONFIG_CRYPTO_BLOWFISH is not set
-# CONFIG_CRYPTO_TWOFISH is not set
-# CONFIG_CRYPTO_SERPENT is not set
-# CONFIG_CRYPTO_AES is not set
-# CONFIG_CRYPTO_CAST5 is not set
-# CONFIG_CRYPTO_CAST6 is not set
-# CONFIG_CRYPTO_TEA is not set
-# CONFIG_CRYPTO_ARC4 is not set
-# CONFIG_CRYPTO_KHAZAD is not set
-# CONFIG_CRYPTO_ANUBIS is not set
-# CONFIG_CRYPTO_DEFLATE is not set
-# CONFIG_CRYPTO_MICHAEL_MIC is not set
-# CONFIG_CRYPTO_CRC32C is not set
-CONFIG_CRYPTO_CAMELLIA=m
-# CONFIG_CRYPTO_TEST is not set
-
-#
-# Hardware crypto devices
-#
-
-#
-# Library routines
-#
-CONFIG_BITREVERSE=y
-# CONFIG_CRC_CCITT is not set
-# CONFIG_CRC16 is not set
-CONFIG_CRC32=y
-# CONFIG_LIBCRC32C is not set
-CONFIG_ZLIB_INFLATE=y
-CONFIG_ZLIB_DEFLATE=y
-CONFIG_PLIST=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT=y
diff --git a/arch/mips/configs/fuloong2e_defconfig b/arch/mips/configs/fuloong2e_defconfig
index 0197f0de6b3f..a09dd03aa8c8 100644
--- a/arch/mips/configs/fuloong2e_defconfig
+++ b/arch/mips/configs/fuloong2e_defconfig
@@ -1,7 +1,7 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.31-rc1
-# Thu Jul  2 22:37:00 2009
+# Linux kernel version: 2.6.32-rc4
+# Fri Oct 16 13:18:01 2009
 #
 CONFIG_MIPS=y
 
@@ -10,8 +10,8 @@ CONFIG_MIPS=y
 #
 # CONFIG_MACH_ALCHEMY is not set
 # CONFIG_AR7 is not set
-# CONFIG_BASLER_EXCITE is not set
 # CONFIG_BCM47XX is not set
+# CONFIG_BCM63XX is not set
 # CONFIG_MIPS_COBALT is not set
 # CONFIG_MACH_DECSTATION is not set
 # CONFIG_MACH_JAZZ is not set
@@ -105,6 +105,8 @@ CONFIG_CPU_LOONGSON2E=y
 # CONFIG_CPU_RM9000 is not set
 # CONFIG_CPU_SB1 is not set
 # CONFIG_CPU_CAVIUM_OCTEON is not set
+CONFIG_SYS_SUPPORTS_ZBOOT=y
+CONFIG_SYS_SUPPORTS_ZBOOT_UART16550=y
 CONFIG_CPU_LOONGSON2=y
 CONFIG_SYS_HAS_CPU_LOONGSON2E=y
 CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
@@ -135,12 +137,16 @@ CONFIG_SYS_SUPPORTS_HIGHMEM=y
 CONFIG_ARCH_FLATMEM_ENABLE=y
 CONFIG_ARCH_POPULATES_NODE_MAP=y
 CONFIG_SELECT_MEMORY_MODEL=y
-CONFIG_FLATMEM_MANUAL=y
+# CONFIG_FLATMEM_MANUAL is not set
 # CONFIG_DISCONTIGMEM_MANUAL is not set
-# CONFIG_SPARSEMEM_MANUAL is not set
-CONFIG_FLATMEM=y
-CONFIG_FLAT_NODE_MEM_MAP=y
+CONFIG_SPARSEMEM_MANUAL=y
+CONFIG_SPARSEMEM=y
+CONFIG_HAVE_MEMORY_PRESENT=y
 CONFIG_SPARSEMEM_STATIC=y
+
+#
+# Memory hotplug is currently incompatible with Software Suspend
+#
 CONFIG_PAGEFLAGS_EXTENDED=y
 CONFIG_SPLIT_PTLOCK_CPUS=4
 CONFIG_PHYS_ADDR_T_64BIT=y
@@ -148,6 +154,7 @@ CONFIG_ZONE_DMA_FLAG=0
 CONFIG_VIRT_TO_BUS=y
 CONFIG_HAVE_MLOCK=y
 CONFIG_HAVE_MLOCKED_PAGE_BIT=y
+# CONFIG_KSM is not set
 CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
 CONFIG_TICK_ONESHOT=y
 CONFIG_NO_HZ=y
@@ -180,6 +187,12 @@ CONFIG_BROKEN_ON_SMP=y
 CONFIG_INIT_ENV_ARG_LIMIT=32
 CONFIG_LOCALVERSION="-fuloong2e"
 # CONFIG_LOCALVERSION_AUTO is not set
+CONFIG_HAVE_KERNEL_GZIP=y
+CONFIG_HAVE_KERNEL_BZIP2=y
+CONFIG_HAVE_KERNEL_LZMA=y
+CONFIG_KERNEL_GZIP=y
+# CONFIG_KERNEL_BZIP2 is not set
+# CONFIG_KERNEL_LZMA is not set
 CONFIG_SWAP=y
 CONFIG_SYSVIPC=y
 CONFIG_SYSVIPC_SYSCTL=y
@@ -193,11 +206,12 @@ CONFIG_BSD_PROCESS_ACCT=y
 #
 # RCU Subsystem
 #
-CONFIG_CLASSIC_RCU=y
-# CONFIG_TREE_RCU is not set
-# CONFIG_PREEMPT_RCU is not set
+CONFIG_TREE_RCU=y
+# CONFIG_TREE_PREEMPT_RCU is not set
+# CONFIG_RCU_TRACE is not set
+CONFIG_RCU_FANOUT=64
+# CONFIG_RCU_FANOUT_EXACT is not set
 # CONFIG_TREE_RCU_TRACE is not set
-# CONFIG_PREEMPT_RCU_TRACE is not set
 CONFIG_IKCONFIG=y
 CONFIG_IKCONFIG_PROC=y
 CONFIG_LOG_BUF_SHIFT=14
@@ -235,18 +249,16 @@ CONFIG_SHMEM=y
 CONFIG_AIO=y
 
 #
-# Performance Counters
+# Kernel Performance Events And Counters
 #
 CONFIG_VM_EVENT_COUNTERS=y
 CONFIG_PCI_QUIRKS=y
-# CONFIG_STRIP_ASM_SYMS is not set
 # CONFIG_COMPAT_BRK is not set
 CONFIG_SLAB=y
 # CONFIG_SLUB is not set
 # CONFIG_SLOB is not set
 CONFIG_PROFILING=y
 CONFIG_TRACEPOINTS=y
-CONFIG_MARKERS=y
 CONFIG_OPROFILE=m
 CONFIG_HAVE_OPROFILE=y
 CONFIG_HAVE_SYSCALL_WRAPPERS=y
@@ -255,8 +267,8 @@ CONFIG_HAVE_SYSCALL_WRAPPERS=y
 # GCOV-based kernel profiling
 #
 # CONFIG_GCOV_KERNEL is not set
-# CONFIG_SLOW_WORK is not set
-# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
+CONFIG_SLOW_WORK=y
+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
 CONFIG_SLABINFO=y
 CONFIG_RT_MUTEXES=y
 CONFIG_BASE_SMALL=0
@@ -283,7 +295,7 @@ CONFIG_IOSCHED_CFQ=y
 CONFIG_DEFAULT_CFQ=y
 # CONFIG_DEFAULT_NOOP is not set
 CONFIG_DEFAULT_IOSCHED="cfq"
-# CONFIG_FREEZER is not set
+CONFIG_FREEZER=y
 
 #
 # Bus options (PCI, PCMCIA, EISA, ISA, TC)
@@ -321,9 +333,14 @@ CONFIG_ARCH_HIBERNATION_POSSIBLE=y
 CONFIG_ARCH_SUSPEND_POSSIBLE=y
 CONFIG_PM=y
 # CONFIG_PM_DEBUG is not set
+CONFIG_PM_SLEEP=y
 # CONFIG_SUSPEND is not set
-# CONFIG_HIBERNATION is not set
+CONFIG_HIBERNATION_NVS=y
+CONFIG_HIBERNATION=y
+CONFIG_PM_STD_PARTITION="/dev/hda3"
+# CONFIG_PM_RUNTIME is not set
 CONFIG_NET=y
+CONFIG_COMPAT_NETLINK_MESSAGES=y
 
 #
 # Networking options
@@ -442,6 +459,7 @@ CONFIG_IP_NF_ARPFILTER=m
 CONFIG_IP_NF_ARP_MANGLE=m
 # CONFIG_IP_DCCP is not set
 # CONFIG_IP_SCTP is not set
+# CONFIG_RDS is not set
 # CONFIG_TIPC is not set
 # CONFIG_ATM is not set
 # CONFIG_BRIDGE is not set
@@ -473,6 +491,7 @@ CONFIG_NET_CLS_ROUTE=y
 # CONFIG_AF_RXRPC is not set
 CONFIG_WIRELESS=y
 # CONFIG_CFG80211 is not set
+CONFIG_CFG80211_DEFAULT_PS_VALUE=0
 CONFIG_WIRELESS_OLD_REGULATORY=y
 CONFIG_WIRELESS_EXT=y
 CONFIG_WIRELESS_EXT_SYSFS=y
@@ -481,7 +500,6 @@ CONFIG_WIRELESS_EXT_SYSFS=y
 #
 # CFG80211 needs to be enabled for MAC80211
 #
-CONFIG_MAC80211_DEFAULT_PS_VALUE=0
 # CONFIG_WIMAX is not set
 # CONFIG_RFKILL is not set
 CONFIG_NET_9P=m
@@ -495,6 +513,7 @@ CONFIG_NET_9P=m
 # Generic Driver Options
 #
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+# CONFIG_DEVTMPFS is not set
 CONFIG_STANDALONE=y
 CONFIG_PREVENT_FIRMWARE_BUILD=y
 CONFIG_FW_LOADER=m
@@ -504,9 +523,9 @@ CONFIG_EXTRA_FIRMWARE=""
 # CONFIG_CONNECTOR is not set
 CONFIG_MTD=m
 # CONFIG_MTD_DEBUG is not set
+# CONFIG_MTD_TESTS is not set
 # CONFIG_MTD_CONCAT is not set
 # CONFIG_MTD_PARTITIONS is not set
-# CONFIG_MTD_TESTS is not set
 
 #
 # User Modules And Translation Layers
@@ -820,6 +839,7 @@ CONFIG_8139TOO=y
 # CONFIG_SUNDANCE is not set
 # CONFIG_TLAN is not set
 # CONFIG_KS8842 is not set
+# CONFIG_KS8851_MLL is not set
 # CONFIG_VIA_RHINE is not set
 # CONFIG_SC92031 is not set
 # CONFIG_ATL2 is not set
@@ -867,10 +887,7 @@ CONFIG_CHELSIO_T3_DEPENDS=y
 # CONFIG_SFC is not set
 # CONFIG_BE2NET is not set
 # CONFIG_TR is not set
-
-#
-# Wireless LAN
-#
+CONFIG_WLAN=y
 # CONFIG_WLAN_PRE80211 is not set
 # CONFIG_WLAN_80211 is not set
 
@@ -886,6 +903,7 @@ CONFIG_CHELSIO_T3_DEPENDS=y
 # CONFIG_USB_PEGASUS is not set
 # CONFIG_USB_RTL8150 is not set
 # CONFIG_USB_USBNET is not set
+# CONFIG_USB_CDC_PHONET is not set
 # CONFIG_WAN is not set
 # CONFIG_FDDI is not set
 # CONFIG_HIPPI is not set
@@ -933,12 +951,16 @@ CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
 # Input Device Drivers
 #
 CONFIG_INPUT_KEYBOARD=y
+# CONFIG_KEYBOARD_ADP5588 is not set
 CONFIG_KEYBOARD_ATKBD=y
-# CONFIG_KEYBOARD_SUNKBD is not set
+# CONFIG_QT2160 is not set
 # CONFIG_KEYBOARD_LKKBD is not set
-# CONFIG_KEYBOARD_XTKBD is not set
+# CONFIG_KEYBOARD_MAX7359 is not set
 # CONFIG_KEYBOARD_NEWTON is not set
+# CONFIG_KEYBOARD_OPENCORES is not set
 # CONFIG_KEYBOARD_STOWAWAY is not set
+# CONFIG_KEYBOARD_SUNKBD is not set
+# CONFIG_KEYBOARD_XTKBD is not set
 CONFIG_INPUT_MOUSE=y
 CONFIG_MOUSE_PS2=y
 CONFIG_MOUSE_PS2_ALPS=y
@@ -946,6 +968,7 @@ CONFIG_MOUSE_PS2_LOGIPS2PP=y
 CONFIG_MOUSE_PS2_SYNAPTICS=y
 CONFIG_MOUSE_PS2_TRACKPOINT=y
 # CONFIG_MOUSE_PS2_ELANTECH is not set
+# CONFIG_MOUSE_PS2_SENTELIC is not set
 # CONFIG_MOUSE_PS2_TOUCHKIT is not set
 CONFIG_MOUSE_SERIAL=y
 # CONFIG_MOUSE_APPLETOUCH is not set
@@ -1015,6 +1038,7 @@ CONFIG_RTC=y
 CONFIG_DEVPORT=y
 CONFIG_I2C=m
 CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_COMPAT=y
 CONFIG_I2C_CHARDEV=m
 CONFIG_I2C_HELPER_AUTO=y
 
@@ -1070,9 +1094,6 @@ CONFIG_I2C_VIAPRO=m
 # Miscellaneous I2C Chip support
 #
 # CONFIG_DS1682 is not set
-# CONFIG_SENSORS_PCF8574 is not set
-# CONFIG_PCF8575 is not set
-# CONFIG_SENSORS_PCA9539 is not set
 # CONFIG_SENSORS_TSL2550 is not set
 # CONFIG_I2C_DEBUG_CORE is not set
 # CONFIG_I2C_DEBUG_ALGO is not set
@@ -1088,7 +1109,6 @@ CONFIG_I2C_VIAPRO=m
 # CONFIG_POWER_SUPPLY is not set
 # CONFIG_HWMON is not set
 # CONFIG_THERMAL is not set
-# CONFIG_THERMAL_HWMON is not set
 # CONFIG_WATCHDOG is not set
 CONFIG_SSB_POSSIBLE=y
 
@@ -1105,6 +1125,7 @@ CONFIG_SSB_POSSIBLE=y
 # CONFIG_HTC_PASIC3 is not set
 # CONFIG_MFD_TMIO is not set
 # CONFIG_MFD_WM8400 is not set
+# CONFIG_MFD_WM831X is not set
 # CONFIG_MFD_WM8350_I2C is not set
 # CONFIG_MFD_PCF50633 is not set
 # CONFIG_AB3100_CORE is not set
@@ -1114,6 +1135,7 @@ CONFIG_SSB_POSSIBLE=y
 #
 # Graphics support
 #
+CONFIG_VGA_ARB=y
 # CONFIG_DRM is not set
 # CONFIG_VGASTATE is not set
 CONFIG_VIDEO_OUTPUT_CONTROL=m
@@ -1198,6 +1220,7 @@ CONFIG_FONT_8x16=y
 # CONFIG_LOGO is not set
 CONFIG_SOUND=y
 CONFIG_SOUND_OSS_CORE=y
+CONFIG_SOUND_OSS_CORE_PRECLAIM=y
 CONFIG_SND=m
 CONFIG_SND_TIMER=m
 CONFIG_SND_PCM=m
@@ -1304,7 +1327,6 @@ CONFIG_SND_USB=y
 CONFIG_AC97_BUS=m
 CONFIG_HID_SUPPORT=y
 CONFIG_HID=y
-# CONFIG_HID_DEBUG is not set
 CONFIG_HIDRAW=y
 
 #
@@ -1356,6 +1378,7 @@ CONFIG_USB_EHCI_TT_NEWSCHED=y
 # CONFIG_USB_OXU210HP_HCD is not set
 # CONFIG_USB_ISP116X_HCD is not set
 CONFIG_USB_ISP1760_HCD=m
+# CONFIG_USB_ISP1362_HCD is not set
 CONFIG_USB_OHCI_HCD=y
 # CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
 # CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
@@ -1453,6 +1476,7 @@ CONFIG_UIO_CIF=m
 # CONFIG_UIO_SMX is not set
 # CONFIG_UIO_AEC is not set
 # CONFIG_UIO_SERCOS3 is not set
+# CONFIG_UIO_PCI_GENERIC is not set
 
 #
 # TI VLYNQ
@@ -1469,10 +1493,10 @@ CONFIG_EXT3_FS=y
 # CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
 # CONFIG_EXT3_FS_XATTR is not set
 CONFIG_EXT4_FS=m
-CONFIG_EXT4DEV_COMPAT=y
 CONFIG_EXT4_FS_XATTR=y
 CONFIG_EXT4_FS_POSIX_ACL=y
 CONFIG_EXT4_FS_SECURITY=y
+# CONFIG_EXT4_DEBUG is not set
 CONFIG_FS_XIP=y
 CONFIG_JBD=y
 # CONFIG_JBD_DEBUG is not set
@@ -1489,6 +1513,7 @@ CONFIG_FS_POSIX_ACL=y
 # CONFIG_GFS2_FS is not set
 # CONFIG_OCFS2_FS is not set
 # CONFIG_BTRFS_FS is not set
+# CONFIG_NILFS2_FS is not set
 CONFIG_FILE_LOCKING=y
 CONFIG_FSNOTIFY=y
 CONFIG_DNOTIFY=y
@@ -1557,7 +1582,6 @@ CONFIG_OMFS_FS=m
 # CONFIG_ROMFS_FS is not set
 # CONFIG_SYSV_FS is not set
 # CONFIG_UFS_FS is not set
-# CONFIG_NILFS2_FS is not set
 CONFIG_NETWORK_FILESYSTEMS=y
 CONFIG_NFS_FS=m
 CONFIG_NFS_V3=y
@@ -1666,6 +1690,7 @@ CONFIG_ENABLE_WARN_DEPRECATED=y
 # CONFIG_ENABLE_MUST_CHECK is not set
 CONFIG_FRAME_WARN=2048
 # CONFIG_MAGIC_SYSRQ is not set
+# CONFIG_STRIP_ASM_SYMS is not set
 # CONFIG_UNUSED_SYMBOLS is not set
 CONFIG_DEBUG_FS=y
 # CONFIG_HEADERS_CHECK is not set
@@ -1678,13 +1703,14 @@ CONFIG_NOP_TRACER=y
 CONFIG_RING_BUFFER=y
 CONFIG_EVENT_TRACING=y
 CONFIG_CONTEXT_SWITCH_TRACER=y
+CONFIG_RING_BUFFER_ALLOW_SWAP=y
 CONFIG_TRACING=y
 CONFIG_TRACING_SUPPORT=y
 # CONFIG_FTRACE is not set
 # CONFIG_DYNAMIC_DEBUG is not set
 # CONFIG_SAMPLES is not set
 CONFIG_HAVE_ARCH_KGDB=y
-CONFIG_CMDLINE=""
+# CONFIG_CMDLINE_BOOL is not set
 
 #
 # Security options
@@ -1742,11 +1768,13 @@ CONFIG_CRYPTO_XTS=m
 #
 CONFIG_CRYPTO_HMAC=y
 # CONFIG_CRYPTO_XCBC is not set
+# CONFIG_CRYPTO_VMAC is not set
 
 #
 # Digest
 #
 # CONFIG_CRYPTO_CRC32C is not set
+CONFIG_CRYPTO_GHASH=m
 # CONFIG_CRYPTO_MD4 is not set
 CONFIG_CRYPTO_MD5=m
 # CONFIG_CRYPTO_MICHAEL_MIC is not set
diff --git a/arch/mips/configs/ip22_defconfig b/arch/mips/configs/ip22_defconfig
index f14d38ba6034..222d7eca2fe4 100644
--- a/arch/mips/configs/ip22_defconfig
+++ b/arch/mips/configs/ip22_defconfig
@@ -9,7 +9,6 @@ CONFIG_MIPS=y
 # Machine selection
 #
 # CONFIG_MACH_ALCHEMY is not set
-# CONFIG_BASLER_EXCITE is not set
 # CONFIG_BCM47XX is not set
 # CONFIG_MIPS_COBALT is not set
 # CONFIG_MACH_DECSTATION is not set
@@ -1188,7 +1187,7 @@ CONFIG_DEBUG_MEMORY_INIT=y
 CONFIG_DYNAMIC_PRINTK_DEBUG=y
 # CONFIG_SAMPLES is not set
 CONFIG_HAVE_ARCH_KGDB=y
-CONFIG_CMDLINE=""
+# CONFIG_CMDLINE_BOOL is not set
 
 #
 # Security options
diff --git a/arch/mips/configs/ip27_defconfig b/arch/mips/configs/ip27_defconfig
index 1fc73aa7b509..ed84b4cb3c8d 100644
--- a/arch/mips/configs/ip27_defconfig
+++ b/arch/mips/configs/ip27_defconfig
@@ -9,7 +9,6 @@ CONFIG_MIPS=y
 # Machine selection
 #
 # CONFIG_MACH_ALCHEMY is not set
-# CONFIG_BASLER_EXCITE is not set
 # CONFIG_MIPS_COBALT is not set
 # CONFIG_MACH_DECSTATION is not set
 # CONFIG_MACH_JAZZ is not set
@@ -940,7 +939,7 @@ CONFIG_ENABLE_MUST_CHECK=y
 # CONFIG_HEADERS_CHECK is not set
 # CONFIG_DEBUG_KERNEL is not set
 CONFIG_CROSSCOMPILE=y
-CONFIG_CMDLINE=""
+# CONFIG_CMDLINE_BOOL is not set
 
 #
 # Security options
diff --git a/arch/mips/configs/ip28_defconfig b/arch/mips/configs/ip28_defconfig
index 539dccb0345d..dab2e5aaadaf 100644
--- a/arch/mips/configs/ip28_defconfig
+++ b/arch/mips/configs/ip28_defconfig
@@ -9,7 +9,6 @@ CONFIG_MIPS=y
 # Machine selection
 #
 # CONFIG_MACH_ALCHEMY is not set
-# CONFIG_BASLER_EXCITE is not set
 # CONFIG_BCM47XX is not set
 # CONFIG_MIPS_COBALT is not set
 # CONFIG_MACH_DECSTATION is not set
@@ -816,7 +815,7 @@ CONFIG_MAGIC_SYSRQ=y
 # CONFIG_HEADERS_CHECK is not set
 # CONFIG_DEBUG_KERNEL is not set
 # CONFIG_SAMPLES is not set
-CONFIG_CMDLINE=""
+# CONFIG_CMDLINE_BOOL is not set
 
 #
 # Security options
diff --git a/arch/mips/configs/ip32_defconfig b/arch/mips/configs/ip32_defconfig
index d934bdefb393..1841c88d3d24 100644
--- a/arch/mips/configs/ip32_defconfig
+++ b/arch/mips/configs/ip32_defconfig
@@ -9,7 +9,6 @@ CONFIG_MIPS=y
 # Machine selection
 #
 # CONFIG_MACH_ALCHEMY is not set
-# CONFIG_BASLER_EXCITE is not set
 # CONFIG_BCM47XX is not set
 # CONFIG_MIPS_COBALT is not set
 # CONFIG_MACH_DECSTATION is not set
@@ -1126,7 +1125,7 @@ CONFIG_SYSCTL_SYSCALL_CHECK=y
 # CONFIG_DYNAMIC_PRINTK_DEBUG is not set
 # CONFIG_SAMPLES is not set
 CONFIG_HAVE_ARCH_KGDB=y
-CONFIG_CMDLINE=""
+# CONFIG_CMDLINE_BOOL is not set
 
 #
 # Security options
diff --git a/arch/mips/configs/jazz_defconfig b/arch/mips/configs/jazz_defconfig
index d22df61833a8..14c2ab3b2674 100644
--- a/arch/mips/configs/jazz_defconfig
+++ b/arch/mips/configs/jazz_defconfig
@@ -22,7 +22,6 @@ CONFIG_ZONE_DMA=y
 # CONFIG_MIPS_DB1550 is not set
 # CONFIG_MIPS_DB1200 is not set
 # CONFIG_MIPS_MIRAGE is not set
-# CONFIG_BASLER_EXCITE is not set
 # CONFIG_MIPS_COBALT is not set
 # CONFIG_MACH_DECSTATION is not set
 CONFIG_MACH_JAZZ=y
@@ -1374,7 +1373,7 @@ CONFIG_ENABLE_MUST_CHECK=y
 # CONFIG_DEBUG_KERNEL is not set
 CONFIG_LOG_BUF_SHIFT=14
 CONFIG_CROSSCOMPILE=y
-CONFIG_CMDLINE=""
+# CONFIG_CMDLINE_BOOL is not set
 
 #
 # Security options
diff --git a/arch/mips/configs/jmr3927_defconfig b/arch/mips/configs/jmr3927_defconfig
index 5380f1f582d9..4d66c44cced8 100644
--- a/arch/mips/configs/jmr3927_defconfig
+++ b/arch/mips/configs/jmr3927_defconfig
@@ -9,7 +9,6 @@ CONFIG_MIPS=y
 # Machine selection
 #
 # CONFIG_MACH_ALCHEMY is not set
-# CONFIG_BASLER_EXCITE is not set
 # CONFIG_BCM47XX is not set
 # CONFIG_MIPS_COBALT is not set
 # CONFIG_MACH_DECSTATION is not set
@@ -835,7 +834,7 @@ CONFIG_SYSCTL_SYSCALL_CHECK=y
 # CONFIG_DYNAMIC_PRINTK_DEBUG is not set
 # CONFIG_SAMPLES is not set
 CONFIG_HAVE_ARCH_KGDB=y
-CONFIG_CMDLINE=""
+# CONFIG_CMDLINE_BOOL is not set
 
 #
 # Security options
diff --git a/arch/mips/configs/lasat_defconfig b/arch/mips/configs/lasat_defconfig
index 044074db7e55..08d481e3d42a 100644
--- a/arch/mips/configs/lasat_defconfig
+++ b/arch/mips/configs/lasat_defconfig
@@ -9,7 +9,6 @@ CONFIG_MIPS=y
 # Machine selection
 #
 # CONFIG_MACH_ALCHEMY is not set
-# CONFIG_BASLER_EXCITE is not set
 # CONFIG_MIPS_COBALT is not set
 # CONFIG_MACH_DECSTATION is not set
 # CONFIG_MACH_JAZZ is not set
@@ -798,7 +797,7 @@ CONFIG_MAGIC_SYSRQ=y
 # CONFIG_HEADERS_CHECK is not set
 # CONFIG_DEBUG_KERNEL is not set
 CONFIG_CROSSCOMPILE=y
-CONFIG_CMDLINE=""
+# CONFIG_CMDLINE_BOOL is not set
 
 #
 # Security options
diff --git a/arch/mips/configs/lemote2f_defconfig b/arch/mips/configs/lemote2f_defconfig
new file mode 100644
index 000000000000..b71a0a4fb95f
--- /dev/null
+++ b/arch/mips/configs/lemote2f_defconfig
@@ -0,0 +1,1835 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.32-rc6
+# Mon Nov  9 23:42:42 2009
+#
+CONFIG_MIPS=y
+
+#
+# Machine selection
+#
+# CONFIG_MACH_ALCHEMY is not set
+# CONFIG_AR7 is not set
+# CONFIG_BCM47XX is not set
+# CONFIG_BCM63XX is not set
+# CONFIG_MIPS_COBALT is not set
+# CONFIG_MACH_DECSTATION is not set
+# CONFIG_MACH_JAZZ is not set
+# CONFIG_LASAT is not set
+CONFIG_MACH_LOONGSON=y
+# CONFIG_MIPS_MALTA is not set
+# CONFIG_MIPS_SIM is not set
+# CONFIG_NEC_MARKEINS is not set
+# CONFIG_MACH_VR41XX is not set
+# CONFIG_NXP_STB220 is not set
+# CONFIG_NXP_STB225 is not set
+# CONFIG_PNX8550_JBS is not set
+# CONFIG_PNX8550_STB810 is not set
+# CONFIG_PMC_MSP is not set
+# CONFIG_PMC_YOSEMITE is not set
+# CONFIG_SGI_IP22 is not set
+# CONFIG_SGI_IP27 is not set
+# CONFIG_SGI_IP28 is not set
+# CONFIG_SGI_IP32 is not set
+# CONFIG_SIBYTE_CRHINE is not set
+# CONFIG_SIBYTE_CARMEL is not set
+# CONFIG_SIBYTE_CRHONE is not set
+# CONFIG_SIBYTE_RHONE is not set
+# CONFIG_SIBYTE_SWARM is not set
+# CONFIG_SIBYTE_LITTLESUR is not set
+# CONFIG_SIBYTE_SENTOSA is not set
+# CONFIG_SIBYTE_BIGSUR is not set
+# CONFIG_SNI_RM is not set
+# CONFIG_MACH_TX39XX is not set
+# CONFIG_MACH_TX49XX is not set
+# CONFIG_MIKROTIK_RB532 is not set
+# CONFIG_WR_PPMC is not set
+# CONFIG_CAVIUM_OCTEON_SIMULATOR is not set
+# CONFIG_CAVIUM_OCTEON_REFERENCE_BOARD is not set
+# CONFIG_ALCHEMY_GPIO_INDIRECT is not set
+CONFIG_ARCH_SPARSEMEM_ENABLE=y
+# CONFIG_LEMOTE_FULOONG2E is not set
+CONFIG_LEMOTE_MACH2F=y
+CONFIG_CS5536=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_ARCH_SUPPORTS_OPROFILE=y
+CONFIG_GENERIC_FIND_NEXT_BIT=y
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_CMOS_UPDATE=y
+CONFIG_SCHED_OMIT_FRAME_POINTER=y
+CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
+CONFIG_CEVT_R4K_LIB=y
+CONFIG_CEVT_R4K=y
+CONFIG_CSRC_R4K_LIB=y
+CONFIG_CSRC_R4K=y
+CONFIG_DMA_NONCOHERENT=y
+CONFIG_DMA_NEED_PCI_MAP_STATE=y
+CONFIG_EARLY_PRINTK=y
+CONFIG_SYS_HAS_EARLY_PRINTK=y
+CONFIG_I8259=y
+# CONFIG_NO_IOPORT is not set
+CONFIG_GENERIC_ISA_DMA=y
+CONFIG_GENERIC_ISA_DMA_SUPPORT_BROKEN=y
+# CONFIG_CPU_BIG_ENDIAN is not set
+CONFIG_CPU_LITTLE_ENDIAN=y
+CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
+CONFIG_IRQ_CPU=y
+CONFIG_BOOT_ELF32=y
+CONFIG_MIPS_L1_CACHE_SHIFT=5
+
+#
+# CPU selection
+#
+# CONFIG_CPU_LOONGSON2E is not set
+CONFIG_CPU_LOONGSON2F=y
+# CONFIG_CPU_MIPS32_R1 is not set
+# CONFIG_CPU_MIPS32_R2 is not set
+# CONFIG_CPU_MIPS64_R1 is not set
+# CONFIG_CPU_MIPS64_R2 is not set
+# CONFIG_CPU_R3000 is not set
+# CONFIG_CPU_TX39XX is not set
+# CONFIG_CPU_VR41XX is not set
+# CONFIG_CPU_R4300 is not set
+# CONFIG_CPU_R4X00 is not set
+# CONFIG_CPU_TX49XX is not set
+# CONFIG_CPU_R5000 is not set
+# CONFIG_CPU_R5432 is not set
+# CONFIG_CPU_R5500 is not set
+# CONFIG_CPU_R6000 is not set
+# CONFIG_CPU_NEVADA is not set
+# CONFIG_CPU_R8000 is not set
+# CONFIG_CPU_R10000 is not set
+# CONFIG_CPU_RM7000 is not set
+# CONFIG_CPU_RM9000 is not set
+# CONFIG_CPU_SB1 is not set
+# CONFIG_CPU_CAVIUM_OCTEON is not set
+CONFIG_SYS_SUPPORTS_ZBOOT=y
+CONFIG_SYS_SUPPORTS_ZBOOT_UART16550=y
+CONFIG_CPU_LOONGSON2=y
+CONFIG_SYS_HAS_CPU_LOONGSON2F=y
+CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
+CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y
+CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
+CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y
+
+#
+# Kernel type
+#
+# CONFIG_32BIT is not set
+CONFIG_64BIT=y
+# CONFIG_PAGE_SIZE_4KB is not set
+# CONFIG_PAGE_SIZE_8KB is not set
+CONFIG_PAGE_SIZE_16KB=y
+# CONFIG_PAGE_SIZE_32KB is not set
+# CONFIG_PAGE_SIZE_64KB is not set
+CONFIG_BOARD_SCACHE=y
+CONFIG_MIPS_MT_DISABLED=y
+# CONFIG_MIPS_MT_SMP is not set
+# CONFIG_MIPS_MT_SMTC is not set
+CONFIG_CPU_HAS_WB=y
+CONFIG_CPU_HAS_SYNC=y
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_CPU_SUPPORTS_HIGHMEM=y
+CONFIG_SYS_SUPPORTS_HIGHMEM=y
+CONFIG_ARCH_FLATMEM_ENABLE=y
+CONFIG_ARCH_POPULATES_NODE_MAP=y
+CONFIG_SELECT_MEMORY_MODEL=y
+# CONFIG_FLATMEM_MANUAL is not set
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+CONFIG_SPARSEMEM_MANUAL=y
+CONFIG_SPARSEMEM=y
+CONFIG_HAVE_MEMORY_PRESENT=y
+CONFIG_SPARSEMEM_STATIC=y
+
+#
+# Memory hotplug is currently incompatible with Software Suspend
+#
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_SPLIT_PTLOCK_CPUS=4
+CONFIG_PHYS_ADDR_T_64BIT=y
+CONFIG_ZONE_DMA_FLAG=0
+CONFIG_VIRT_TO_BUS=y
+CONFIG_HAVE_MLOCK=y
+CONFIG_HAVE_MLOCKED_PAGE_BIT=y
+# CONFIG_KSM is not set
+CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
+CONFIG_TICK_ONESHOT=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+# CONFIG_HZ_48 is not set
+# CONFIG_HZ_100 is not set
+# CONFIG_HZ_128 is not set
+CONFIG_HZ_250=y
+# CONFIG_HZ_256 is not set
+# CONFIG_HZ_1000 is not set
+# CONFIG_HZ_1024 is not set
+CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
+CONFIG_HZ=250
+# CONFIG_PREEMPT_NONE is not set
+# CONFIG_PREEMPT_VOLUNTARY is not set
+CONFIG_PREEMPT=y
+# CONFIG_KEXEC is not set
+# CONFIG_SECCOMP is not set
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+CONFIG_CONSTRUCTORS=y
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_LOCK_KERNEL=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION=""
+# CONFIG_LOCALVERSION_AUTO is not set
+CONFIG_HAVE_KERNEL_GZIP=y
+CONFIG_HAVE_KERNEL_BZIP2=y
+CONFIG_HAVE_KERNEL_LZMA=y
+# CONFIG_KERNEL_GZIP is not set
+# CONFIG_KERNEL_BZIP2 is not set
+CONFIG_KERNEL_LZMA=y
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+# CONFIG_POSIX_MQUEUE is not set
+CONFIG_BSD_PROCESS_ACCT=y
+CONFIG_BSD_PROCESS_ACCT_V3=y
+# CONFIG_TASKSTATS is not set
+CONFIG_AUDIT=y
+
+#
+# RCU Subsystem
+#
+CONFIG_TREE_RCU=y
+# CONFIG_TREE_PREEMPT_RCU is not set
+# CONFIG_RCU_TRACE is not set
+CONFIG_RCU_FANOUT=64
+# CONFIG_RCU_FANOUT_EXACT is not set
+# CONFIG_TREE_RCU_TRACE is not set
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=15
+# CONFIG_GROUP_SCHED is not set
+# CONFIG_CGROUPS is not set
+CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SYSFS_DEPRECATED_V2=y
+# CONFIG_RELAY is not set
+# CONFIG_NAMESPACES is not set
+# CONFIG_BLK_DEV_INITRD is not set
+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+CONFIG_SYSCTL=y
+CONFIG_ANON_INODES=y
+CONFIG_EMBEDDED=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_PCSPKR_PLATFORM=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_AIO=y
+
+#
+# Kernel Performance Events And Counters
+#
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_PCI_QUIRKS=y
+CONFIG_SLUB_DEBUG=y
+CONFIG_COMPAT_BRK=y
+# CONFIG_SLAB is not set
+CONFIG_SLUB=y
+# CONFIG_SLOB is not set
+# CONFIG_PROFILING is not set
+CONFIG_HAVE_OPROFILE=y
+CONFIG_HAVE_SYSCALL_WRAPPERS=y
+
+#
+# GCOV-based kernel profiling
+#
+# CONFIG_SLOW_WORK is not set
+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+# CONFIG_MODULE_FORCE_LOAD is not set
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODULE_FORCE_UNLOAD is not set
+CONFIG_MODVERSIONS=y
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+CONFIG_BLOCK=y
+CONFIG_BLK_DEV_BSG=y
+CONFIG_BLK_DEV_INTEGRITY=y
+CONFIG_BLOCK_COMPAT=y
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+# CONFIG_DEFAULT_AS is not set
+# CONFIG_DEFAULT_DEADLINE is not set
+CONFIG_DEFAULT_CFQ=y
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="cfq"
+CONFIG_FREEZER=y
+
+#
+# Bus options (PCI, PCMCIA, EISA, ISA, TC)
+#
+CONFIG_HW_HAS_PCI=y
+CONFIG_PCI=y
+CONFIG_PCI_DOMAINS=y
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+CONFIG_PCI_LEGACY=y
+# CONFIG_PCI_STUB is not set
+# CONFIG_PCI_IOV is not set
+CONFIG_ISA=y
+CONFIG_MMU=y
+# CONFIG_PCCARD is not set
+# CONFIG_HOTPLUG_PCI is not set
+
+#
+# Executable file formats
+#
+CONFIG_BINFMT_ELF=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+# CONFIG_HAVE_AOUT is not set
+# CONFIG_BINFMT_MISC is not set
+CONFIG_MIPS32_COMPAT=y
+CONFIG_COMPAT=y
+CONFIG_SYSVIPC_COMPAT=y
+CONFIG_MIPS32_O32=y
+CONFIG_MIPS32_N32=y
+CONFIG_BINFMT_ELF32=y
+
+#
+# Power management options
+#
+CONFIG_ARCH_HIBERNATION_POSSIBLE=y
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_PM=y
+# CONFIG_PM_DEBUG is not set
+CONFIG_PM_SLEEP=y
+CONFIG_SUSPEND=y
+CONFIG_SUSPEND_FREEZER=y
+CONFIG_HIBERNATION_NVS=y
+CONFIG_HIBERNATION=y
+CONFIG_PM_STD_PARTITION="/dev/hda3"
+# CONFIG_PM_RUNTIME is not set
+CONFIG_NET=y
+CONFIG_COMPAT_NETLINK_MESSAGES=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+CONFIG_PACKET_MMAP=y
+CONFIG_UNIX=y
+CONFIG_XFRM=y
+# CONFIG_XFRM_USER is not set
+# CONFIG_XFRM_SUB_POLICY is not set
+# CONFIG_XFRM_MIGRATE is not set
+# CONFIG_XFRM_STATISTICS is not set
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_ADVANCED_ROUTER=y
+CONFIG_ASK_IP_FIB_HASH=y
+# CONFIG_IP_FIB_TRIE is not set
+CONFIG_IP_FIB_HASH=y
+CONFIG_IP_MULTIPLE_TABLES=y
+CONFIG_IP_ROUTE_MULTIPATH=y
+CONFIG_IP_ROUTE_VERBOSE=y
+# CONFIG_IP_PNP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+CONFIG_IP_MROUTE=y
+CONFIG_IP_PIMSM_V1=y
+CONFIG_IP_PIMSM_V2=y
+# CONFIG_ARPD is not set
+CONFIG_SYN_COOKIES=y
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
+CONFIG_INET_TUNNEL=m
+CONFIG_INET_XFRM_MODE_TRANSPORT=m
+CONFIG_INET_XFRM_MODE_TUNNEL=m
+CONFIG_INET_XFRM_MODE_BEET=m
+CONFIG_INET_LRO=y
+CONFIG_INET_DIAG=y
+CONFIG_INET_TCP_DIAG=y
+CONFIG_TCP_CONG_ADVANCED=y
+CONFIG_TCP_CONG_BIC=y
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_TCP_CONG_WESTWOOD=m
+CONFIG_TCP_CONG_HTCP=m
+# CONFIG_TCP_CONG_HSTCP is not set
+# CONFIG_TCP_CONG_HYBLA is not set
+# CONFIG_TCP_CONG_VEGAS is not set
+# CONFIG_TCP_CONG_SCALABLE is not set
+# CONFIG_TCP_CONG_LP is not set
+# CONFIG_TCP_CONG_VENO is not set
+# CONFIG_TCP_CONG_YEAH is not set
+# CONFIG_TCP_CONG_ILLINOIS is not set
+CONFIG_DEFAULT_BIC=y
+# CONFIG_DEFAULT_CUBIC is not set
+# CONFIG_DEFAULT_HTCP is not set
+# CONFIG_DEFAULT_VEGAS is not set
+# CONFIG_DEFAULT_WESTWOOD is not set
+# CONFIG_DEFAULT_RENO is not set
+CONFIG_DEFAULT_TCP_CONG="bic"
+# CONFIG_TCP_MD5SIG is not set
+CONFIG_IPV6=m
+CONFIG_IPV6_PRIVACY=y
+# CONFIG_IPV6_ROUTER_PREF is not set
+# CONFIG_IPV6_OPTIMISTIC_DAD is not set
+# CONFIG_INET6_AH is not set
+# CONFIG_INET6_ESP is not set
+# CONFIG_INET6_IPCOMP is not set
+# CONFIG_IPV6_MIP6 is not set
+# CONFIG_INET6_XFRM_TUNNEL is not set
+# CONFIG_INET6_TUNNEL is not set
+CONFIG_INET6_XFRM_MODE_TRANSPORT=m
+CONFIG_INET6_XFRM_MODE_TUNNEL=m
+CONFIG_INET6_XFRM_MODE_BEET=m
+# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set
+CONFIG_IPV6_SIT=m
+CONFIG_IPV6_NDISC_NODETYPE=y
+# CONFIG_IPV6_TUNNEL is not set
+# CONFIG_IPV6_MULTIPLE_TABLES is not set
+# CONFIG_IPV6_MROUTE is not set
+CONFIG_NETWORK_SECMARK=y
+CONFIG_NETFILTER=y
+# CONFIG_NETFILTER_DEBUG is not set
+CONFIG_NETFILTER_ADVANCED=y
+
+#
+# Core Netfilter Configuration
+#
+# CONFIG_NETFILTER_NETLINK_QUEUE is not set
+# CONFIG_NETFILTER_NETLINK_LOG is not set
+# CONFIG_NF_CONNTRACK is not set
+# CONFIG_NETFILTER_XTABLES is not set
+# CONFIG_IP_VS is not set
+
+#
+# IP: Netfilter Configuration
+#
+# CONFIG_NF_DEFRAG_IPV4 is not set
+# CONFIG_IP_NF_QUEUE is not set
+# CONFIG_IP_NF_IPTABLES is not set
+# CONFIG_IP_NF_ARPTABLES is not set
+
+#
+# IPv6: Netfilter Configuration
+#
+# CONFIG_IP6_NF_QUEUE is not set
+# CONFIG_IP6_NF_IPTABLES is not set
+# CONFIG_IP_DCCP is not set
+# CONFIG_IP_SCTP is not set
+# CONFIG_RDS is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_NET_DSA is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_PHONET is not set
+# CONFIG_IEEE802154 is not set
+CONFIG_NET_SCHED=y
+
+#
+# Queueing/Scheduling
+#
+# CONFIG_NET_SCH_CBQ is not set
+# CONFIG_NET_SCH_HTB is not set
+# CONFIG_NET_SCH_HFSC is not set
+# CONFIG_NET_SCH_PRIO is not set
+# CONFIG_NET_SCH_MULTIQ is not set
+# CONFIG_NET_SCH_RED is not set
+# CONFIG_NET_SCH_SFQ is not set
+# CONFIG_NET_SCH_TEQL is not set
+# CONFIG_NET_SCH_TBF is not set
+# CONFIG_NET_SCH_GRED is not set
+# CONFIG_NET_SCH_DSMARK is not set
+# CONFIG_NET_SCH_NETEM is not set
+# CONFIG_NET_SCH_DRR is not set
+# CONFIG_NET_SCH_INGRESS is not set
+
+#
+# Classification
+#
+CONFIG_NET_CLS=y
+# CONFIG_NET_CLS_BASIC is not set
+# CONFIG_NET_CLS_TCINDEX is not set
+# CONFIG_NET_CLS_ROUTE4 is not set
+# CONFIG_NET_CLS_FW is not set
+# CONFIG_NET_CLS_U32 is not set
+# CONFIG_NET_CLS_RSVP is not set
+# CONFIG_NET_CLS_RSVP6 is not set
+# CONFIG_NET_CLS_FLOW is not set
+CONFIG_NET_EMATCH=y
+CONFIG_NET_EMATCH_STACK=32
+# CONFIG_NET_EMATCH_CMP is not set
+# CONFIG_NET_EMATCH_NBYTE is not set
+# CONFIG_NET_EMATCH_U32 is not set
+# CONFIG_NET_EMATCH_META is not set
+# CONFIG_NET_EMATCH_TEXT is not set
+CONFIG_NET_CLS_ACT=y
+# CONFIG_NET_ACT_POLICE is not set
+# CONFIG_NET_ACT_GACT is not set
+# CONFIG_NET_ACT_MIRRED is not set
+# CONFIG_NET_ACT_NAT is not set
+# CONFIG_NET_ACT_PEDIT is not set
+# CONFIG_NET_ACT_SIMP is not set
+# CONFIG_NET_ACT_SKBEDIT is not set
+CONFIG_NET_SCH_FIFO=y
+# CONFIG_DCB is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+# CONFIG_AF_RXRPC is not set
+CONFIG_FIB_RULES=y
+CONFIG_WIRELESS=y
+# CONFIG_CFG80211 is not set
+CONFIG_CFG80211_DEFAULT_PS_VALUE=0
+# CONFIG_WIRELESS_OLD_REGULATORY is not set
+CONFIG_WIRELESS_EXT=y
+CONFIG_WIRELESS_EXT_SYSFS=y
+# CONFIG_LIB80211 is not set
+
+#
+# CFG80211 needs to be enabled for MAC80211
+#
+# CONFIG_WIMAX is not set
+CONFIG_RFKILL=m
+# CONFIG_RFKILL_INPUT is not set
+# CONFIG_NET_9P is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+# CONFIG_DEVTMPFS is not set
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+CONFIG_FW_LOADER=y
+CONFIG_FIRMWARE_IN_KERNEL=y
+CONFIG_EXTRA_FIRMWARE=""
+# CONFIG_SYS_HYPERVISOR is not set
+# CONFIG_CONNECTOR is not set
+# CONFIG_MTD is not set
+# CONFIG_PARPORT is not set
+# CONFIG_PNP is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_CPQ_DA is not set
+# CONFIG_BLK_CPQ_CISS_DA is not set
+# CONFIG_BLK_DEV_DAC960 is not set
+# CONFIG_BLK_DEV_UMEM is not set
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_CRYPTOLOOP=y
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_SX8 is not set
+# CONFIG_BLK_DEV_UB is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=8192
+# CONFIG_BLK_DEV_XIP is not set
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+# CONFIG_BLK_DEV_HD is not set
+CONFIG_MISC_DEVICES=y
+# CONFIG_PHANTOM is not set
+# CONFIG_SGI_IOC4 is not set
+# CONFIG_TIFM_CORE is not set
+# CONFIG_ENCLOSURE_SERVICES is not set
+# CONFIG_HP_ILO is not set
+# CONFIG_C2PORT is not set
+
+#
+# EEPROM support
+#
+# CONFIG_EEPROM_93CX6 is not set
+# CONFIG_CB710_CORE is not set
+CONFIG_HAVE_IDE=y
+CONFIG_IDE=y
+
+#
+# Please see Documentation/ide/ide.txt for help/info on IDE drives
+#
+CONFIG_IDE_XFER_MODE=y
+CONFIG_IDE_TIMINGS=y
+# CONFIG_BLK_DEV_IDE_SATA is not set
+CONFIG_IDE_GD=y
+CONFIG_IDE_GD_ATA=y
+# CONFIG_IDE_GD_ATAPI is not set
+# CONFIG_BLK_DEV_IDECD is not set
+# CONFIG_BLK_DEV_IDETAPE is not set
+CONFIG_IDE_TASK_IOCTL=y
+CONFIG_IDE_PROC_FS=y
+
+#
+# IDE chipset support/bugfixes
+#
+# CONFIG_IDE_GENERIC is not set
+# CONFIG_BLK_DEV_PLATFORM is not set
+CONFIG_BLK_DEV_IDEDMA_SFF=y
+
+#
+# PCI IDE chipsets support
+#
+CONFIG_BLK_DEV_IDEPCI=y
+# CONFIG_IDEPCI_PCIBUS_ORDER is not set
+# CONFIG_BLK_DEV_OFFBOARD is not set
+CONFIG_BLK_DEV_GENERIC=y
+# CONFIG_BLK_DEV_OPTI621 is not set
+CONFIG_BLK_DEV_IDEDMA_PCI=y
+# CONFIG_BLK_DEV_AEC62XX is not set
+# CONFIG_BLK_DEV_ALI15X3 is not set
+CONFIG_BLK_DEV_AMD74XX=y
+# CONFIG_BLK_DEV_CMD64X is not set
+# CONFIG_BLK_DEV_TRIFLEX is not set
+# CONFIG_BLK_DEV_CS5520 is not set
+# CONFIG_BLK_DEV_CS5530 is not set
+# CONFIG_BLK_DEV_HPT366 is not set
+# CONFIG_BLK_DEV_JMICRON is not set
+# CONFIG_BLK_DEV_SC1200 is not set
+# CONFIG_BLK_DEV_PIIX is not set
+# CONFIG_BLK_DEV_IT8172 is not set
+# CONFIG_BLK_DEV_IT8213 is not set
+# CONFIG_BLK_DEV_IT821X is not set
+# CONFIG_BLK_DEV_NS87415 is not set
+# CONFIG_BLK_DEV_PDC202XX_OLD is not set
+# CONFIG_BLK_DEV_PDC202XX_NEW is not set
+# CONFIG_BLK_DEV_SVWKS is not set
+# CONFIG_BLK_DEV_SIIMAGE is not set
+# CONFIG_BLK_DEV_SLC90E66 is not set
+# CONFIG_BLK_DEV_TRM290 is not set
+# CONFIG_BLK_DEV_VIA82CXXX is not set
+# CONFIG_BLK_DEV_TC86C001 is not set
+
+#
+# Other IDE chipsets support
+#
+
+#
+# Note: most of these also require special kernel boot parameters
+#
+# CONFIG_BLK_DEV_4DRIVES is not set
+# CONFIG_BLK_DEV_ALI14XX is not set
+# CONFIG_BLK_DEV_DTC2278 is not set
+# CONFIG_BLK_DEV_HT6560B is not set
+# CONFIG_BLK_DEV_QD65XX is not set
+# CONFIG_BLK_DEV_UMC8672 is not set
+CONFIG_BLK_DEV_IDEDMA=y
+
+#
+# SCSI device support
+#
+# CONFIG_RAID_ATTRS is not set
+CONFIG_SCSI=m
+CONFIG_SCSI_DMA=y
+# CONFIG_SCSI_TGT is not set
+# CONFIG_SCSI_NETLINK is not set
+CONFIG_SCSI_PROC_FS=y
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=m
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+# CONFIG_BLK_DEV_SR is not set
+CONFIG_CHR_DEV_SG=m
+# CONFIG_CHR_DEV_SCH is not set
+CONFIG_SCSI_MULTI_LUN=y
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+# CONFIG_SCSI_SCAN_ASYNC is not set
+CONFIG_SCSI_WAIT_SCAN=m
+
+#
+# SCSI Transports
+#
+# CONFIG_SCSI_SPI_ATTRS is not set
+# CONFIG_SCSI_FC_ATTRS is not set
+# CONFIG_SCSI_ISCSI_ATTRS is not set
+# CONFIG_SCSI_SAS_ATTRS is not set
+# CONFIG_SCSI_SAS_LIBSAS is not set
+# CONFIG_SCSI_SRP_ATTRS is not set
+# CONFIG_SCSI_LOWLEVEL is not set
+# CONFIG_SCSI_DH is not set
+# CONFIG_SCSI_OSD_INITIATOR is not set
+# CONFIG_ATA is not set
+# CONFIG_MD is not set
+# CONFIG_FUSION is not set
+
+#
+# IEEE 1394 (FireWire) support
+#
+
+#
+# You can enable one or both FireWire driver stacks.
+#
+
+#
+# See the help texts for more information.
+#
+# CONFIG_FIREWIRE is not set
+# CONFIG_IEEE1394 is not set
+# CONFIG_I2O is not set
+CONFIG_NETDEVICES=y
+# CONFIG_IFB is not set
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_VETH is not set
+# CONFIG_ARCNET is not set
+# CONFIG_PHYLIB is not set
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
+# CONFIG_AX88796 is not set
+# CONFIG_HAPPYMEAL is not set
+# CONFIG_SUNGEM is not set
+# CONFIG_CASSINI is not set
+# CONFIG_NET_VENDOR_3COM is not set
+# CONFIG_NET_VENDOR_SMC is not set
+# CONFIG_SMC91X is not set
+# CONFIG_DM9000 is not set
+# CONFIG_ETHOC is not set
+# CONFIG_NET_VENDOR_RACAL is not set
+# CONFIG_DNET is not set
+# CONFIG_NET_TULIP is not set
+# CONFIG_AT1700 is not set
+# CONFIG_DEPCA is not set
+# CONFIG_HP100 is not set
+# CONFIG_NET_ISA is not set
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
+# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
+# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
+CONFIG_NET_PCI=y
+# CONFIG_PCNET32 is not set
+# CONFIG_AMD8111_ETH is not set
+# CONFIG_ADAPTEC_STARFIRE is not set
+# CONFIG_AC3200 is not set
+# CONFIG_APRICOT is not set
+# CONFIG_B44 is not set
+# CONFIG_FORCEDETH is not set
+# CONFIG_CS89x0 is not set
+# CONFIG_TC35815 is not set
+# CONFIG_E100 is not set
+# CONFIG_FEALNX is not set
+# CONFIG_NATSEMI is not set
+# CONFIG_NE2K_PCI is not set
+# CONFIG_8139CP is not set
+CONFIG_8139TOO=y
+# CONFIG_8139TOO_PIO is not set
+CONFIG_8139TOO_TUNE_TWISTER=y
+# CONFIG_8139TOO_8129 is not set
+# CONFIG_8139_OLD_RX_RESET is not set
+# CONFIG_R6040 is not set
+# CONFIG_SIS900 is not set
+# CONFIG_EPIC100 is not set
+# CONFIG_SMSC9420 is not set
+# CONFIG_SUNDANCE is not set
+# CONFIG_TLAN is not set
+# CONFIG_KS8842 is not set
+# CONFIG_KS8851_MLL is not set
+# CONFIG_VIA_RHINE is not set
+# CONFIG_SC92031 is not set
+# CONFIG_ATL2 is not set
+CONFIG_NETDEV_1000=y
+# CONFIG_ACENIC is not set
+# CONFIG_DL2K is not set
+# CONFIG_E1000 is not set
+# CONFIG_E1000E is not set
+# CONFIG_IP1000 is not set
+# CONFIG_IGB is not set
+# CONFIG_IGBVF is not set
+# CONFIG_NS83820 is not set
+# CONFIG_HAMACHI is not set
+# CONFIG_YELLOWFIN is not set
+CONFIG_R8169=y
+# CONFIG_SIS190 is not set
+# CONFIG_SKGE is not set
+# CONFIG_SKY2 is not set
+# CONFIG_VIA_VELOCITY is not set
+# CONFIG_TIGON3 is not set
+# CONFIG_BNX2 is not set
+# CONFIG_CNIC is not set
+# CONFIG_QLA3XXX is not set
+# CONFIG_ATL1 is not set
+# CONFIG_ATL1E is not set
+# CONFIG_ATL1C is not set
+# CONFIG_JME is not set
+# CONFIG_NETDEV_10000 is not set
+# CONFIG_TR is not set
+CONFIG_WLAN=y
+CONFIG_WLAN_PRE80211=y
+# CONFIG_STRIP is not set
+# CONFIG_WAVELAN is not set
+CONFIG_WLAN_80211=y
+# CONFIG_LIBERTAS is not set
+# CONFIG_ATMEL is not set
+# CONFIG_PRISM54 is not set
+# CONFIG_USB_ZD1201 is not set
+# CONFIG_HOSTAP is not set
+
+#
+# Enable WiMAX (Networking options) to see the WiMAX drivers
+#
+
+#
+# USB Network Adapters
+#
+# CONFIG_USB_CATC is not set
+# CONFIG_USB_KAWETH is not set
+# CONFIG_USB_PEGASUS is not set
+# CONFIG_USB_RTL8150 is not set
+# CONFIG_USB_USBNET is not set
+# CONFIG_USB_HSO is not set
+# CONFIG_WAN is not set
+# CONFIG_FDDI is not set
+# CONFIG_HIPPI is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+# CONFIG_NET_FC is not set
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_ISDN is not set
+# CONFIG_PHONE is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
+
+#
+# Userland interfaces
+#
+CONFIG_INPUT_MOUSEDEV=y
+CONFIG_INPUT_MOUSEDEV_PSAUX=y
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+# CONFIG_INPUT_JOYDEV is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input Device Drivers
+#
+CONFIG_INPUT_KEYBOARD=y
+CONFIG_KEYBOARD_ATKBD=y
+# CONFIG_KEYBOARD_LKKBD is not set
+# CONFIG_KEYBOARD_NEWTON is not set
+# CONFIG_KEYBOARD_OPENCORES is not set
+# CONFIG_KEYBOARD_STOWAWAY is not set
+# CONFIG_KEYBOARD_SUNKBD is not set
+# CONFIG_KEYBOARD_XTKBD is not set
+CONFIG_INPUT_MOUSE=y
+CONFIG_MOUSE_PS2=y
+# CONFIG_MOUSE_PS2_ALPS is not set
+# CONFIG_MOUSE_PS2_LOGIPS2PP is not set
+CONFIG_MOUSE_PS2_SYNAPTICS=y
+# CONFIG_MOUSE_PS2_TRACKPOINT is not set
+# CONFIG_MOUSE_PS2_ELANTECH is not set
+# CONFIG_MOUSE_PS2_SENTELIC is not set
+# CONFIG_MOUSE_PS2_TOUCHKIT is not set
+# CONFIG_MOUSE_SERIAL is not set
+# CONFIG_MOUSE_APPLETOUCH is not set
+# CONFIG_MOUSE_BCM5974 is not set
+# CONFIG_MOUSE_INPORT is not set
+# CONFIG_MOUSE_LOGIBM is not set
+# CONFIG_MOUSE_PC110PAD is not set
+# CONFIG_MOUSE_VSXXXAA is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+# CONFIG_INPUT_MISC is not set
+
+#
+# Hardware I/O ports
+#
+CONFIG_SERIO=y
+CONFIG_SERIO_I8042=y
+# CONFIG_SERIO_SERPORT is not set
+# CONFIG_SERIO_PCIPS2 is not set
+CONFIG_SERIO_LIBPS2=y
+# CONFIG_SERIO_RAW is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+# CONFIG_VT_HW_CONSOLE_BINDING is not set
+CONFIG_DEVKMEM=y
+CONFIG_SERIAL_NONSTANDARD=y
+# CONFIG_COMPUTONE is not set
+# CONFIG_ROCKETPORT is not set
+# CONFIG_CYCLADES is not set
+# CONFIG_DIGIEPCA is not set
+# CONFIG_MOXA_INTELLIO is not set
+# CONFIG_MOXA_SMARTIO is not set
+# CONFIG_ISI is not set
+# CONFIG_SYNCLINKMP is not set
+# CONFIG_SYNCLINK_GT is not set
+# CONFIG_N_HDLC is not set
+# CONFIG_RISCOM8 is not set
+# CONFIG_SPECIALIX is not set
+# CONFIG_STALDRV is not set
+# CONFIG_NOZOMI is not set
+
+#
+# Serial drivers
+#
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+# CONFIG_SERIAL_8250_PCI is not set
+CONFIG_SERIAL_8250_NR_UARTS=16
+CONFIG_SERIAL_8250_RUNTIME_UARTS=4
+CONFIG_SERIAL_8250_EXTENDED=y
+CONFIG_SERIAL_8250_MANY_PORTS=y
+CONFIG_SERIAL_8250_FOURPORT=y
+# CONFIG_SERIAL_8250_ACCENT is not set
+# CONFIG_SERIAL_8250_BOCA is not set
+# CONFIG_SERIAL_8250_EXAR_ST16C554 is not set
+# CONFIG_SERIAL_8250_HUB6 is not set
+# CONFIG_SERIAL_8250_SHARE_IRQ is not set
+# CONFIG_SERIAL_8250_DETECT_IRQ is not set
+# CONFIG_SERIAL_8250_RSA is not set
+
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+# CONFIG_SERIAL_JSM is not set
+CONFIG_UNIX98_PTYS=y
+# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
+CONFIG_LEGACY_PTYS=y
+CONFIG_LEGACY_PTY_COUNT=16
+# CONFIG_IPMI_HANDLER is not set
+CONFIG_HW_RANDOM=y
+# CONFIG_HW_RANDOM_TIMERIOMEM is not set
+CONFIG_RTC=y
+# CONFIG_DTLK is not set
+# CONFIG_R3964 is not set
+# CONFIG_APPLICOM is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+CONFIG_DEVPORT=y
+# CONFIG_I2C is not set
+# CONFIG_SPI is not set
+
+#
+# PPS support
+#
+# CONFIG_PPS is not set
+# CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
+CONFIG_HWMON=y
+# CONFIG_HWMON_VID is not set
+# CONFIG_HWMON_DEBUG_CHIP is not set
+
+#
+# Native drivers
+#
+# CONFIG_SENSORS_I5K_AMB is not set
+# CONFIG_SENSORS_F71805F is not set
+# CONFIG_SENSORS_F71882FG is not set
+# CONFIG_SENSORS_IT87 is not set
+# CONFIG_SENSORS_PC87360 is not set
+# CONFIG_SENSORS_PC87427 is not set
+# CONFIG_SENSORS_SIS5595 is not set
+# CONFIG_SENSORS_SMSC47M1 is not set
+# CONFIG_SENSORS_SMSC47B397 is not set
+# CONFIG_SENSORS_VIA686A is not set
+# CONFIG_SENSORS_VT1211 is not set
+# CONFIG_SENSORS_VT8231 is not set
+# CONFIG_SENSORS_W83627HF is not set
+# CONFIG_SENSORS_W83627EHF is not set
+CONFIG_THERMAL=y
+# CONFIG_THERMAL_HWMON is not set
+# CONFIG_WATCHDOG is not set
+CONFIG_SSB_POSSIBLE=y
+
+#
+# Sonics Silicon Backplane
+#
+# CONFIG_SSB is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_CORE is not set
+# CONFIG_MFD_SM501 is not set
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_MFD_TMIO is not set
+# CONFIG_REGULATOR is not set
+CONFIG_MEDIA_SUPPORT=m
+
+#
+# Multimedia core support
+#
+CONFIG_VIDEO_DEV=m
+CONFIG_VIDEO_V4L2_COMMON=m
+CONFIG_VIDEO_ALLOW_V4L1=y
+CONFIG_VIDEO_V4L1_COMPAT=y
+# CONFIG_DVB_CORE is not set
+CONFIG_VIDEO_MEDIA=m
+
+#
+# Multimedia drivers
+#
+# CONFIG_MEDIA_ATTACH is not set
+CONFIG_VIDEO_V4L2=m
+CONFIG_VIDEO_V4L1=m
+CONFIG_VIDEO_CAPTURE_DRIVERS=y
+# CONFIG_VIDEO_ADV_DEBUG is not set
+# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set
+CONFIG_VIDEO_HELPER_CHIPS_AUTO=y
+# CONFIG_VIDEO_VIVI is not set
+# CONFIG_VIDEO_PMS is not set
+# CONFIG_VIDEO_CPIA is not set
+# CONFIG_VIDEO_CPIA2 is not set
+# CONFIG_VIDEO_STRADIS is not set
+CONFIG_V4L_USB_DRIVERS=y
+CONFIG_USB_VIDEO_CLASS=m
+CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y
+CONFIG_USB_GSPCA=m
+# CONFIG_USB_M5602 is not set
+# CONFIG_USB_STV06XX is not set
+# CONFIG_USB_GL860 is not set
+# CONFIG_USB_GSPCA_CONEX is not set
+# CONFIG_USB_GSPCA_ETOMS is not set
+# CONFIG_USB_GSPCA_FINEPIX is not set
+# CONFIG_USB_GSPCA_JEILINJ is not set
+# CONFIG_USB_GSPCA_MARS is not set
+# CONFIG_USB_GSPCA_MR97310A is not set
+# CONFIG_USB_GSPCA_OV519 is not set
+# CONFIG_USB_GSPCA_OV534 is not set
+# CONFIG_USB_GSPCA_PAC207 is not set
+# CONFIG_USB_GSPCA_PAC7311 is not set
+# CONFIG_USB_GSPCA_SN9C20X is not set
+# CONFIG_USB_GSPCA_SONIXB is not set
+# CONFIG_USB_GSPCA_SONIXJ is not set
+# CONFIG_USB_GSPCA_SPCA500 is not set
+# CONFIG_USB_GSPCA_SPCA501 is not set
+# CONFIG_USB_GSPCA_SPCA505 is not set
+# CONFIG_USB_GSPCA_SPCA506 is not set
+# CONFIG_USB_GSPCA_SPCA508 is not set
+# CONFIG_USB_GSPCA_SPCA561 is not set
+# CONFIG_USB_GSPCA_SQ905 is not set
+# CONFIG_USB_GSPCA_SQ905C is not set
+# CONFIG_USB_GSPCA_STK014 is not set
+# CONFIG_USB_GSPCA_SUNPLUS is not set
+# CONFIG_USB_GSPCA_T613 is not set
+# CONFIG_USB_GSPCA_TV8532 is not set
+# CONFIG_USB_GSPCA_VC032X is not set
+# CONFIG_USB_GSPCA_ZC3XX is not set
+# CONFIG_VIDEO_HDPVR is not set
+# CONFIG_USB_VICAM is not set
+# CONFIG_USB_IBMCAM is not set
+# CONFIG_USB_KONICAWC is not set
+# CONFIG_USB_QUICKCAM_MESSENGER is not set
+# CONFIG_USB_ET61X251 is not set
+# CONFIG_USB_OV511 is not set
+# CONFIG_USB_SE401 is not set
+# CONFIG_USB_SN9C102 is not set
+# CONFIG_USB_STV680 is not set
+# CONFIG_USB_ZC0301 is not set
+# CONFIG_USB_PWC is not set
+CONFIG_USB_PWC_INPUT_EVDEV=y
+# CONFIG_USB_ZR364XX is not set
+# CONFIG_USB_STKWEBCAM is not set
+# CONFIG_USB_S2255 is not set
+# CONFIG_RADIO_ADAPTERS is not set
+# CONFIG_DAB is not set
+
+#
+# Graphics support
+#
+CONFIG_VGA_ARB=y
+# CONFIG_DRM is not set
+# CONFIG_VGASTATE is not set
+CONFIG_VIDEO_OUTPUT_CONTROL=y
+CONFIG_FB=y
+CONFIG_FIRMWARE_EDID=y
+# CONFIG_FB_DDC is not set
+CONFIG_FB_BOOT_VESA_SUPPORT=y
+CONFIG_FB_CFB_FILLRECT=y
+CONFIG_FB_CFB_COPYAREA=y
+CONFIG_FB_CFB_IMAGEBLIT=y
+# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
+# CONFIG_FB_SYS_FILLRECT is not set
+# CONFIG_FB_SYS_COPYAREA is not set
+# CONFIG_FB_SYS_IMAGEBLIT is not set
+# CONFIG_FB_FOREIGN_ENDIAN is not set
+# CONFIG_FB_SYS_FOPS is not set
+# CONFIG_FB_SVGALIB is not set
+# CONFIG_FB_MACMODES is not set
+# CONFIG_FB_BACKLIGHT is not set
+CONFIG_FB_MODE_HELPERS=y
+CONFIG_FB_TILEBLITTING=y
+
+#
+# Frame buffer hardware drivers
+#
+# CONFIG_FB_CIRRUS is not set
+# CONFIG_FB_PM2 is not set
+# CONFIG_FB_CYBER2000 is not set
+# CONFIG_FB_ASILIANT is not set
+# CONFIG_FB_IMSTT is not set
+# CONFIG_FB_S1D13XXX is not set
+# CONFIG_FB_NVIDIA is not set
+# CONFIG_FB_RIVA is not set
+# CONFIG_FB_MATROX is not set
+# CONFIG_FB_RADEON is not set
+# CONFIG_FB_ATY128 is not set
+# CONFIG_FB_ATY is not set
+# CONFIG_FB_S3 is not set
+# CONFIG_FB_SAVAGE is not set
+CONFIG_FB_SIS=y
+CONFIG_FB_SIS_300=y
+CONFIG_FB_SIS_315=y
+# CONFIG_FB_VIA is not set
+# CONFIG_FB_NEOMAGIC is not set
+# CONFIG_FB_KYRO is not set
+# CONFIG_FB_3DFX is not set
+# CONFIG_FB_VOODOO1 is not set
+# CONFIG_FB_VT8623 is not set
+# CONFIG_FB_TRIDENT is not set
+# CONFIG_FB_ARK is not set
+# CONFIG_FB_PM3 is not set
+# CONFIG_FB_CARMINE is not set
+# CONFIG_FB_VIRTUAL is not set
+# CONFIG_FB_METRONOME is not set
+# CONFIG_FB_MB862XX is not set
+# CONFIG_FB_BROADSHEET is not set
+CONFIG_BACKLIGHT_LCD_SUPPORT=y
+# CONFIG_LCD_CLASS_DEVICE is not set
+CONFIG_BACKLIGHT_CLASS_DEVICE=y
+CONFIG_BACKLIGHT_GENERIC=y
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+
+#
+# Console display driver support
+#
+# CONFIG_VGA_CONSOLE is not set
+# CONFIG_MDA_CONSOLE is not set
+CONFIG_DUMMY_CONSOLE=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
+# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
+CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y
+CONFIG_FONTS=y
+CONFIG_FONT_8x8=y
+CONFIG_FONT_8x16=y
+CONFIG_FONT_6x11=y
+CONFIG_FONT_7x14=y
+CONFIG_FONT_PEARL_8x8=y
+CONFIG_FONT_ACORN_8x8=y
+CONFIG_FONT_MINI_4x6=y
+CONFIG_FONT_SUN8x16=y
+CONFIG_FONT_SUN12x22=y
+CONFIG_FONT_10x18=y
+CONFIG_LOGO=y
+# CONFIG_LOGO_LINUX_MONO is not set
+# CONFIG_LOGO_LINUX_VGA16 is not set
+CONFIG_LOGO_LINUX_CLUT224=y
+CONFIG_SOUND=m
+# CONFIG_SOUND_OSS_CORE is not set
+CONFIG_SND=m
+CONFIG_SND_TIMER=m
+CONFIG_SND_PCM=m
+# CONFIG_SND_SEQUENCER is not set
+# CONFIG_SND_MIXER_OSS is not set
+# CONFIG_SND_PCM_OSS is not set
+# CONFIG_SND_HRTIMER is not set
+# CONFIG_SND_RTCTIMER is not set
+# CONFIG_SND_DYNAMIC_MINORS is not set
+# CONFIG_SND_SUPPORT_OLD_API is not set
+# CONFIG_SND_VERBOSE_PROCFS is not set
+# CONFIG_SND_VERBOSE_PRINTK is not set
+# CONFIG_SND_DEBUG is not set
+CONFIG_SND_VMASTER=y
+# CONFIG_SND_RAWMIDI_SEQ is not set
+# CONFIG_SND_OPL3_LIB_SEQ is not set
+# CONFIG_SND_OPL4_LIB_SEQ is not set
+# CONFIG_SND_SBAWE_SEQ is not set
+# CONFIG_SND_EMU10K1_SEQ is not set
+CONFIG_SND_AC97_CODEC=m
+# CONFIG_SND_DRIVERS is not set
+CONFIG_SND_PCI=y
+# CONFIG_SND_AD1889 is not set
+# CONFIG_SND_ALS300 is not set
+# CONFIG_SND_ALI5451 is not set
+# CONFIG_SND_ATIIXP is not set
+# CONFIG_SND_ATIIXP_MODEM is not set
+# CONFIG_SND_AU8810 is not set
+# CONFIG_SND_AU8820 is not set
+# CONFIG_SND_AU8830 is not set
+# CONFIG_SND_AW2 is not set
+# CONFIG_SND_AZT3328 is not set
+# CONFIG_SND_BT87X is not set
+# CONFIG_SND_CA0106 is not set
+# CONFIG_SND_CMIPCI is not set
+# CONFIG_SND_OXYGEN is not set
+# CONFIG_SND_CS4281 is not set
+# CONFIG_SND_CS46XX is not set
+CONFIG_SND_CS5535AUDIO=m
+# CONFIG_SND_CTXFI is not set
+# CONFIG_SND_DARLA20 is not set
+# CONFIG_SND_GINA20 is not set
+# CONFIG_SND_LAYLA20 is not set
+# CONFIG_SND_DARLA24 is not set
+# CONFIG_SND_GINA24 is not set
+# CONFIG_SND_LAYLA24 is not set
+# CONFIG_SND_MONA is not set
+# CONFIG_SND_MIA is not set
+# CONFIG_SND_ECHO3G is not set
+# CONFIG_SND_INDIGO is not set
+# CONFIG_SND_INDIGOIO is not set
+# CONFIG_SND_INDIGODJ is not set
+# CONFIG_SND_INDIGOIOX is not set
+# CONFIG_SND_INDIGODJX is not set
+# CONFIG_SND_EMU10K1 is not set
+# CONFIG_SND_EMU10K1X is not set
+# CONFIG_SND_ENS1370 is not set
+# CONFIG_SND_ENS1371 is not set
+# CONFIG_SND_ES1938 is not set
+# CONFIG_SND_ES1968 is not set
+# CONFIG_SND_FM801 is not set
+# CONFIG_SND_HDA_INTEL is not set
+# CONFIG_SND_HDSP is not set
+# CONFIG_SND_HDSPM is not set
+# CONFIG_SND_HIFIER is not set
+# CONFIG_SND_ICE1712 is not set
+# CONFIG_SND_ICE1724 is not set
+# CONFIG_SND_INTEL8X0 is not set
+# CONFIG_SND_INTEL8X0M is not set
+# CONFIG_SND_KORG1212 is not set
+# CONFIG_SND_LX6464ES is not set
+# CONFIG_SND_MAESTRO3 is not set
+# CONFIG_SND_MIXART is not set
+# CONFIG_SND_NM256 is not set
+# CONFIG_SND_PCXHR is not set
+# CONFIG_SND_RIPTIDE is not set
+# CONFIG_SND_RME32 is not set
+# CONFIG_SND_RME96 is not set
+# CONFIG_SND_RME9652 is not set
+# CONFIG_SND_SONICVIBES is not set
+# CONFIG_SND_TRIDENT is not set
+# CONFIG_SND_VIA82XX is not set
+# CONFIG_SND_VIA82XX_MODEM is not set
+# CONFIG_SND_VIRTUOSO is not set
+# CONFIG_SND_VX222 is not set
+# CONFIG_SND_YMFPCI is not set
+# CONFIG_SND_MIPS is not set
+# CONFIG_SND_USB is not set
+# CONFIG_SND_SOC is not set
+# CONFIG_SOUND_PRIME is not set
+CONFIG_AC97_BUS=m
+CONFIG_HID_SUPPORT=y
+CONFIG_HID=y
+CONFIG_HIDRAW=y
+
+#
+# USB Input Devices
+#
+CONFIG_USB_HID=y
+# CONFIG_HID_PID is not set
+CONFIG_USB_HIDDEV=y
+
+#
+# Special HID drivers
+#
+# CONFIG_HID_A4TECH is not set
+# CONFIG_HID_APPLE is not set
+# CONFIG_HID_BELKIN is not set
+# CONFIG_HID_CHERRY is not set
+# CONFIG_HID_CHICONY is not set
+# CONFIG_HID_CYPRESS is not set
+# CONFIG_HID_DRAGONRISE is not set
+# CONFIG_HID_EZKEY is not set
+# CONFIG_HID_KYE is not set
+# CONFIG_HID_GYRATION is not set
+# CONFIG_HID_TWINHAN is not set
+# CONFIG_HID_KENSINGTON is not set
+# CONFIG_HID_LOGITECH is not set
+# CONFIG_HID_MICROSOFT is not set
+# CONFIG_HID_MONTEREY is not set
+# CONFIG_HID_NTRIG is not set
+# CONFIG_HID_PANTHERLORD is not set
+# CONFIG_HID_PETALYNX is not set
+# CONFIG_HID_SAMSUNG is not set
+# CONFIG_HID_SONY is not set
+# CONFIG_HID_SUNPLUS is not set
+# CONFIG_HID_GREENASIA is not set
+# CONFIG_HID_SMARTJOYPLUS is not set
+# CONFIG_HID_TOPSEED is not set
+# CONFIG_HID_THRUSTMASTER is not set
+# CONFIG_HID_ZEROPLUS is not set
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_ARCH_HAS_HCD=y
+CONFIG_USB_ARCH_HAS_OHCI=y
+CONFIG_USB_ARCH_HAS_EHCI=y
+CONFIG_USB=y
+# CONFIG_USB_DEBUG is not set
+# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
+
+#
+# Miscellaneous USB options
+#
+CONFIG_USB_DEVICEFS=y
+# CONFIG_USB_DEVICE_CLASS is not set
+CONFIG_USB_DYNAMIC_MINORS=y
+CONFIG_USB_SUSPEND=y
+# CONFIG_USB_OTG is not set
+CONFIG_USB_OTG_WHITELIST=y
+# CONFIG_USB_OTG_BLACKLIST_HUB is not set
+CONFIG_USB_MON=y
+# CONFIG_USB_WUSB is not set
+# CONFIG_USB_WUSB_CBAF is not set
+
+#
+# USB Host Controller Drivers
+#
+# CONFIG_USB_C67X00_HCD is not set
+# CONFIG_USB_XHCI_HCD is not set
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_ROOT_HUB_TT=y
+# CONFIG_USB_EHCI_TT_NEWSCHED is not set
+# CONFIG_USB_OXU210HP_HCD is not set
+# CONFIG_USB_ISP116X_HCD is not set
+# CONFIG_USB_ISP1760_HCD is not set
+# CONFIG_USB_ISP1362_HCD is not set
+CONFIG_USB_OHCI_HCD=y
+# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
+# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
+CONFIG_USB_OHCI_LITTLE_ENDIAN=y
+CONFIG_USB_UHCI_HCD=m
+# CONFIG_USB_SL811_HCD is not set
+# CONFIG_USB_R8A66597_HCD is not set
+# CONFIG_USB_WHCI_HCD is not set
+# CONFIG_USB_HWA_HCD is not set
+
+#
+# USB Device Class drivers
+#
+CONFIG_USB_ACM=m
+# CONFIG_USB_PRINTER is not set
+CONFIG_USB_WDM=m
+# CONFIG_USB_TMC is not set
+
+#
+# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
+#
+
+#
+# also be needed; see USB_STORAGE Help for more info
+#
+CONFIG_USB_STORAGE=m
+# CONFIG_USB_STORAGE_DEBUG is not set
+CONFIG_USB_STORAGE_DATAFAB=m
+CONFIG_USB_STORAGE_FREECOM=m
+CONFIG_USB_STORAGE_ISD200=m
+CONFIG_USB_STORAGE_USBAT=m
+CONFIG_USB_STORAGE_SDDR09=m
+CONFIG_USB_STORAGE_SDDR55=m
+CONFIG_USB_STORAGE_JUMPSHOT=m
+CONFIG_USB_STORAGE_ALAUDA=m
+# CONFIG_USB_STORAGE_ONETOUCH is not set
+# CONFIG_USB_STORAGE_KARMA is not set
+# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
+# CONFIG_USB_LIBUSUAL is not set
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_MICROTEK is not set
+
+#
+# USB port drivers
+#
+CONFIG_USB_SERIAL=m
+# CONFIG_USB_EZUSB is not set
+CONFIG_USB_SERIAL_GENERIC=y
+# CONFIG_USB_SERIAL_AIRCABLE is not set
+# CONFIG_USB_SERIAL_ARK3116 is not set
+# CONFIG_USB_SERIAL_BELKIN is not set
+# CONFIG_USB_SERIAL_CH341 is not set
+# CONFIG_USB_SERIAL_WHITEHEAT is not set
+# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set
+# CONFIG_USB_SERIAL_CP210X is not set
+# CONFIG_USB_SERIAL_CYPRESS_M8 is not set
+# CONFIG_USB_SERIAL_EMPEG is not set
+# CONFIG_USB_SERIAL_FTDI_SIO is not set
+# CONFIG_USB_SERIAL_FUNSOFT is not set
+# CONFIG_USB_SERIAL_VISOR is not set
+# CONFIG_USB_SERIAL_IPAQ is not set
+# CONFIG_USB_SERIAL_IR is not set
+# CONFIG_USB_SERIAL_EDGEPORT is not set
+# CONFIG_USB_SERIAL_EDGEPORT_TI is not set
+# CONFIG_USB_SERIAL_GARMIN is not set
+# CONFIG_USB_SERIAL_IPW is not set
+# CONFIG_USB_SERIAL_IUU is not set
+# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set
+# CONFIG_USB_SERIAL_KEYSPAN is not set
+# CONFIG_USB_SERIAL_KLSI is not set
+# CONFIG_USB_SERIAL_KOBIL_SCT is not set
+# CONFIG_USB_SERIAL_MCT_U232 is not set
+# CONFIG_USB_SERIAL_MOS7720 is not set
+# CONFIG_USB_SERIAL_MOS7840 is not set
+# CONFIG_USB_SERIAL_MOTOROLA is not set
+# CONFIG_USB_SERIAL_NAVMAN is not set
+# CONFIG_USB_SERIAL_PL2303 is not set
+# CONFIG_USB_SERIAL_OTI6858 is not set
+# CONFIG_USB_SERIAL_QUALCOMM is not set
+# CONFIG_USB_SERIAL_SPCP8X5 is not set
+# CONFIG_USB_SERIAL_HP4X is not set
+# CONFIG_USB_SERIAL_SAFE is not set
+# CONFIG_USB_SERIAL_SIEMENS_MPI is not set
+# CONFIG_USB_SERIAL_SIERRAWIRELESS is not set
+# CONFIG_USB_SERIAL_SYMBOL is not set
+# CONFIG_USB_SERIAL_TI is not set
+# CONFIG_USB_SERIAL_CYBERJACK is not set
+# CONFIG_USB_SERIAL_XIRCOM is not set
+# CONFIG_USB_SERIAL_OPTION is not set
+# CONFIG_USB_SERIAL_OMNINET is not set
+# CONFIG_USB_SERIAL_OPTICON is not set
+# CONFIG_USB_SERIAL_DEBUG is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_EMI62 is not set
+# CONFIG_USB_EMI26 is not set
+# CONFIG_USB_ADUTUX is not set
+# CONFIG_USB_SEVSEG is not set
+# CONFIG_USB_RIO500 is not set
+# CONFIG_USB_LEGOTOWER is not set
+# CONFIG_USB_LCD is not set
+# CONFIG_USB_BERRY_CHARGE is not set
+# CONFIG_USB_LED is not set
+# CONFIG_USB_CYPRESS_CY7C63 is not set
+# CONFIG_USB_CYTHERM is not set
+# CONFIG_USB_IDMOUSE is not set
+# CONFIG_USB_FTDI_ELAN is not set
+# CONFIG_USB_APPLEDISPLAY is not set
+# CONFIG_USB_SISUSBVGA is not set
+# CONFIG_USB_LD is not set
+# CONFIG_USB_TRANCEVIBRATOR is not set
+# CONFIG_USB_IOWARRIOR is not set
+# CONFIG_USB_TEST is not set
+# CONFIG_USB_ISIGHTFW is not set
+# CONFIG_USB_VST is not set
+# CONFIG_USB_GADGET is not set
+
+#
+# OTG and related infrastructure
+#
+# CONFIG_NOP_USB_XCEIV is not set
+# CONFIG_UWB is not set
+# CONFIG_MMC is not set
+# CONFIG_MEMSTICK is not set
+# CONFIG_NEW_LEDS is not set
+# CONFIG_ACCESSIBILITY is not set
+# CONFIG_INFINIBAND is not set
+# CONFIG_RTC_CLASS is not set
+# CONFIG_DMADEVICES is not set
+# CONFIG_AUXDISPLAY is not set
+# CONFIG_UIO is not set
+
+#
+# TI VLYNQ
+#
+CONFIG_STAGING=y
+# CONFIG_STAGING_EXCLUDE_BUILD is not set
+# CONFIG_ET131X is not set
+# CONFIG_USB_IP_COMMON is not set
+# CONFIG_PRISM2_USB is not set
+# CONFIG_ECHO is not set
+# CONFIG_COMEDI is not set
+# CONFIG_ASUS_OLED is not set
+# CONFIG_ALTERA_PCIE_CHDMA is not set
+# CONFIG_RTL8187SE is not set
+# CONFIG_RTL8192SU is not set
+# CONFIG_RTL8192E is not set
+# CONFIG_INPUT_MIMIO is not set
+# CONFIG_TRANZPORT is not set
+
+#
+# Android
+#
+
+#
+# Qualcomm MSM Camera And Video
+#
+
+#
+# Camera Sensor Selection
+#
+# CONFIG_INPUT_GPIO is not set
+# CONFIG_DST is not set
+# CONFIG_POHMELFS is not set
+# CONFIG_B3DFG is not set
+# CONFIG_PLAN9AUTH is not set
+# CONFIG_LINE6_USB is not set
+# CONFIG_USB_SERIAL_QUATECH2 is not set
+# CONFIG_USB_SERIAL_QUATECH_USB2 is not set
+# CONFIG_VT6655 is not set
+# CONFIG_VT6656 is not set
+# CONFIG_FB_UDL is not set
+# CONFIG_VME_BUS is not set
+
+#
+# RAR Register Driver
+#
+# CONFIG_RAR_REGISTER is not set
+# CONFIG_IIO is not set
+CONFIG_FB_SM7XX=y
+CONFIG_FB_SM7XX_ACCEL=y
+
+#
+# File systems
+#
+# CONFIG_EXT2_FS is not set
+CONFIG_EXT3_FS=y
+# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
+CONFIG_EXT3_FS_XATTR=y
+CONFIG_EXT3_FS_POSIX_ACL=y
+CONFIG_EXT3_FS_SECURITY=y
+# CONFIG_EXT4_FS is not set
+CONFIG_JBD=y
+CONFIG_FS_MBCACHE=y
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+CONFIG_FS_POSIX_ACL=y
+# CONFIG_XFS_FS is not set
+# CONFIG_GFS2_FS is not set
+# CONFIG_OCFS2_FS is not set
+# CONFIG_BTRFS_FS is not set
+# CONFIG_NILFS2_FS is not set
+CONFIG_FILE_LOCKING=y
+CONFIG_FSNOTIFY=y
+CONFIG_DNOTIFY=y
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
+CONFIG_QUOTA=y
+# CONFIG_QUOTA_NETLINK_INTERFACE is not set
+CONFIG_PRINT_QUOTA_WARNING=y
+# CONFIG_QFMT_V1 is not set
+# CONFIG_QFMT_V2 is not set
+CONFIG_QUOTACTL=y
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_FUSE_FS is not set
+
+#
+# Caches
+#
+# CONFIG_FSCACHE is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+CONFIG_ISO9660_FS=m
+CONFIG_JOLIET=y
+CONFIG_ZISOFS=y
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=m
+# CONFIG_MSDOS_FS is not set
+CONFIG_VFAT_FS=m
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_KCORE=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_HUGETLB_PAGE is not set
+# CONFIG_CONFIGFS_FS is not set
+# CONFIG_MISC_FILESYSTEMS is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_NFS_FS=m
+CONFIG_NFS_V3=y
+CONFIG_NFS_V3_ACL=y
+# CONFIG_NFS_V4 is not set
+# CONFIG_NFSD is not set
+CONFIG_LOCKD=m
+CONFIG_LOCKD_V4=y
+CONFIG_NFS_ACL_SUPPORT=m
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=m
+# CONFIG_RPCSEC_GSS_KRB5 is not set
+# CONFIG_RPCSEC_GSS_SPKM3 is not set
+# CONFIG_SMB_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="utf-8"
+# CONFIG_NLS_CODEPAGE_437 is not set
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+# CONFIG_NLS_ASCII is not set
+# CONFIG_NLS_ISO8859_1 is not set
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+# CONFIG_NLS_UTF8 is not set
+# CONFIG_DLM is not set
+
+#
+# Kernel hacking
+#
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_PRINTK_TIME=y
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_FRAME_WARN=1024
+# CONFIG_MAGIC_SYSRQ is not set
+CONFIG_STRIP_ASM_SYMS=y
+# CONFIG_UNUSED_SYMBOLS is not set
+# CONFIG_DEBUG_FS is not set
+# CONFIG_HEADERS_CHECK is not set
+# CONFIG_DEBUG_KERNEL is not set
+# CONFIG_SLUB_DEBUG_ON is not set
+# CONFIG_SLUB_STATS is not set
+# CONFIG_DEBUG_MEMORY_INIT is not set
+# CONFIG_RCU_CPU_STALL_DETECTOR is not set
+CONFIG_SYSCTL_SYSCALL_CHECK=y
+CONFIG_TRACING_SUPPORT=y
+# CONFIG_FTRACE is not set
+# CONFIG_SAMPLES is not set
+CONFIG_HAVE_ARCH_KGDB=y
+# CONFIG_CMDLINE_BOOL is not set
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITYFS is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+CONFIG_CRYPTO=y
+
+#
+# Crypto core or helper
+#
+CONFIG_CRYPTO_ALGAPI=y
+CONFIG_CRYPTO_ALGAPI2=y
+CONFIG_CRYPTO_AEAD2=y
+CONFIG_CRYPTO_BLKCIPHER=y
+CONFIG_CRYPTO_BLKCIPHER2=y
+CONFIG_CRYPTO_HASH2=y
+CONFIG_CRYPTO_RNG2=y
+CONFIG_CRYPTO_PCOMP=y
+CONFIG_CRYPTO_MANAGER=y
+CONFIG_CRYPTO_MANAGER2=y
+# CONFIG_CRYPTO_GF128MUL is not set
+# CONFIG_CRYPTO_NULL is not set
+CONFIG_CRYPTO_WORKQUEUE=y
+# CONFIG_CRYPTO_CRYPTD is not set
+# CONFIG_CRYPTO_AUTHENC is not set
+# CONFIG_CRYPTO_TEST is not set
+
+#
+# Authenticated Encryption with Associated Data
+#
+# CONFIG_CRYPTO_CCM is not set
+# CONFIG_CRYPTO_GCM is not set
+# CONFIG_CRYPTO_SEQIV is not set
+
+#
+# Block modes
+#
+CONFIG_CRYPTO_CBC=y
+# CONFIG_CRYPTO_CTR is not set
+# CONFIG_CRYPTO_CTS is not set
+# CONFIG_CRYPTO_ECB is not set
+# CONFIG_CRYPTO_LRW is not set
+# CONFIG_CRYPTO_PCBC is not set
+# CONFIG_CRYPTO_XTS is not set
+
+#
+# Hash modes
+#
+# CONFIG_CRYPTO_HMAC is not set
+# CONFIG_CRYPTO_XCBC is not set
+# CONFIG_CRYPTO_VMAC is not set
+
+#
+# Digest
+#
+# CONFIG_CRYPTO_CRC32C is not set
+# CONFIG_CRYPTO_GHASH is not set
+# CONFIG_CRYPTO_MD4 is not set
+# CONFIG_CRYPTO_MD5 is not set
+# CONFIG_CRYPTO_MICHAEL_MIC is not set
+# CONFIG_CRYPTO_RMD128 is not set
+# CONFIG_CRYPTO_RMD160 is not set
+# CONFIG_CRYPTO_RMD256 is not set
+# CONFIG_CRYPTO_RMD320 is not set
+# CONFIG_CRYPTO_SHA1 is not set
+# CONFIG_CRYPTO_SHA256 is not set
+# CONFIG_CRYPTO_SHA512 is not set
+# CONFIG_CRYPTO_TGR192 is not set
+# CONFIG_CRYPTO_WP512 is not set
+
+#
+# Ciphers
+#
+# CONFIG_CRYPTO_AES is not set
+# CONFIG_CRYPTO_ANUBIS is not set
+# CONFIG_CRYPTO_ARC4 is not set
+# CONFIG_CRYPTO_BLOWFISH is not set
+# CONFIG_CRYPTO_CAMELLIA is not set
+# CONFIG_CRYPTO_CAST5 is not set
+# CONFIG_CRYPTO_CAST6 is not set
+# CONFIG_CRYPTO_DES is not set
+# CONFIG_CRYPTO_FCRYPT is not set
+# CONFIG_CRYPTO_KHAZAD is not set
+# CONFIG_CRYPTO_SALSA20 is not set
+# CONFIG_CRYPTO_SEED is not set
+# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_TEA is not set
+# CONFIG_CRYPTO_TWOFISH is not set
+
+#
+# Compression
+#
+# CONFIG_CRYPTO_DEFLATE is not set
+# CONFIG_CRYPTO_ZLIB is not set
+# CONFIG_CRYPTO_LZO is not set
+
+#
+# Random Number Generation
+#
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
+CONFIG_CRYPTO_HW=y
+# CONFIG_CRYPTO_DEV_HIFN_795X is not set
+# CONFIG_BINARY_PRINTF is not set
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+CONFIG_GENERIC_FIND_LAST_BIT=y
+# CONFIG_CRC_CCITT is not set
+# CONFIG_CRC16 is not set
+CONFIG_CRC_T10DIF=y
+# CONFIG_CRC_ITU_T is not set
+CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
+# CONFIG_LIBCRC32C is not set
+CONFIG_AUDIT_GENERIC=y
+CONFIG_ZLIB_INFLATE=m
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
+CONFIG_NLATTR=y
diff --git a/arch/mips/configs/malta_defconfig b/arch/mips/configs/malta_defconfig
index 3f01870b4d65..d3c601206db2 100644
--- a/arch/mips/configs/malta_defconfig
+++ b/arch/mips/configs/malta_defconfig
@@ -10,7 +10,6 @@ CONFIG_MIPS=y
 #
 CONFIG_ZONE_DMA=y
 # CONFIG_MACH_ALCHEMY is not set
-# CONFIG_BASLER_EXCITE is not set
 # CONFIG_BCM47XX is not set
 # CONFIG_MIPS_COBALT is not set
 # CONFIG_MACH_DECSTATION is not set
@@ -1591,7 +1590,7 @@ CONFIG_FRAME_WARN=1024
 # CONFIG_DYNAMIC_PRINTK_DEBUG is not set
 # CONFIG_SAMPLES is not set
 CONFIG_HAVE_ARCH_KGDB=y
-CONFIG_CMDLINE=""
+# CONFIG_CMDLINE_BOOL is not set
 
 #
 # Security options
diff --git a/arch/mips/configs/markeins_defconfig b/arch/mips/configs/markeins_defconfig
index d001f7e87418..6a325c02b63c 100644
--- a/arch/mips/configs/markeins_defconfig
+++ b/arch/mips/configs/markeins_defconfig
@@ -22,7 +22,6 @@ CONFIG_ZONE_DMA=y
 # CONFIG_MIPS_DB1550 is not set
 # CONFIG_MIPS_DB1200 is not set
 # CONFIG_MIPS_MIRAGE is not set
-# CONFIG_BASLER_EXCITE is not set
 # CONFIG_MIPS_COBALT is not set
 # CONFIG_MACH_DECSTATION is not set
 # CONFIG_MACH_JAZZ is not set
@@ -1366,7 +1365,9 @@ CONFIG_ENABLE_MUST_CHECK=y
 # CONFIG_DEBUG_KERNEL is not set
 CONFIG_LOG_BUF_SHIFT=14
 CONFIG_CROSSCOMPILE=y
+CONFIG_CMDLINE_BOOL=y
 CONFIG_CMDLINE="console=ttyS0,115200 mem=192m ip=bootp root=/dev/nfs rw"
+# CONFIG_CMDLINE_OVERRIDE is not set
 
 #
 # Security options
diff --git a/arch/mips/configs/mipssim_defconfig b/arch/mips/configs/mipssim_defconfig
index 7358454deaa6..f77a34e0f938 100644
--- a/arch/mips/configs/mipssim_defconfig
+++ b/arch/mips/configs/mipssim_defconfig
@@ -9,7 +9,6 @@ CONFIG_MIPS=y
 # Machine selection
 #
 # CONFIG_MACH_ALCHEMY is not set
-# CONFIG_BASLER_EXCITE is not set
 # CONFIG_BCM47XX is not set
 # CONFIG_MIPS_COBALT is not set
 # CONFIG_MACH_DECSTATION is not set
@@ -635,7 +634,9 @@ CONFIG_FORCED_INLINING=y
 # CONFIG_RCU_TORTURE_TEST is not set
 # CONFIG_FAULT_INJECTION is not set
 CONFIG_CROSSCOMPILE=y
+CONFIG_CMDLINE_BOOL=y
 CONFIG_CMDLINE="nfsroot=192.168.192.169:/u1/mipsel,timeo=20 ip=dhcp"
+# CONFIG_CMDLINE_OVERRIDE is not set
 # CONFIG_DEBUG_STACK_USAGE is not set
 # CONFIG_RUNTIME_DEBUG is not set
 
diff --git a/arch/mips/configs/mpc30x_defconfig b/arch/mips/configs/mpc30x_defconfig
index 8c720e51795b..17203056b22b 100644
--- a/arch/mips/configs/mpc30x_defconfig
+++ b/arch/mips/configs/mpc30x_defconfig
@@ -9,7 +9,6 @@ CONFIG_MIPS=y
 # Machine selection
 #
 # CONFIG_MACH_ALCHEMY is not set
-# CONFIG_BASLER_EXCITE is not set
 # CONFIG_MIPS_COBALT is not set
 # CONFIG_MACH_DECSTATION is not set
 # CONFIG_MACH_JAZZ is not set
@@ -817,7 +816,9 @@ CONFIG_ENABLE_MUST_CHECK=y
 # CONFIG_HEADERS_CHECK is not set
 # CONFIG_DEBUG_KERNEL is not set
 CONFIG_CROSSCOMPILE=y
+CONFIG_CMDLINE_BOOL=y
 CONFIG_CMDLINE="mem=32M console=ttyVR0,19200 ide0=0x170,0x376,73"
+# CONFIG_CMDLINE_OVERRIDE is not set
 
 #
 # Security options
diff --git a/arch/mips/configs/msp71xx_defconfig b/arch/mips/configs/msp71xx_defconfig
index ecbc030b7b6c..000d185ddf42 100644
--- a/arch/mips/configs/msp71xx_defconfig
+++ b/arch/mips/configs/msp71xx_defconfig
@@ -22,7 +22,6 @@ CONFIG_ZONE_DMA=y
 # CONFIG_MIPS_DB1550 is not set
 # CONFIG_MIPS_DB1200 is not set
 # CONFIG_MIPS_MIRAGE is not set
-# CONFIG_BASLER_EXCITE is not set
 # CONFIG_MIPS_COBALT is not set
 # CONFIG_MACH_DECSTATION is not set
 # CONFIG_MACH_JAZZ is not set
@@ -1412,7 +1411,7 @@ CONFIG_FORCED_INLINING=y
 # CONFIG_RCU_TORTURE_TEST is not set
 # CONFIG_FAULT_INJECTION is not set
 CONFIG_CROSSCOMPILE=y
-CONFIG_CMDLINE=""
+# CONFIG_CMDLINE_BOOL is not set
 # CONFIG_DEBUG_STACK_USAGE is not set
 # CONFIG_RUNTIME_DEBUG is not set
 # CONFIG_MIPS_UNCACHED is not set
diff --git a/arch/mips/configs/mtx1_defconfig b/arch/mips/configs/mtx1_defconfig
index 9477f040796d..144b94d9a6ad 100644
--- a/arch/mips/configs/mtx1_defconfig
+++ b/arch/mips/configs/mtx1_defconfig
@@ -9,7 +9,6 @@ CONFIG_MIPS=y
 # Machine selection
 #
 CONFIG_MACH_ALCHEMY=y
-# CONFIG_BASLER_EXCITE is not set
 # CONFIG_MIPS_COBALT is not set
 # CONFIG_MACH_DECSTATION is not set
 # CONFIG_MACH_JAZZ is not set
@@ -3018,7 +3017,7 @@ CONFIG_MAGIC_SYSRQ=y
 # CONFIG_HEADERS_CHECK is not set
 # CONFIG_DEBUG_KERNEL is not set
 CONFIG_CROSSCOMPILE=y
-CONFIG_CMDLINE=""
+# CONFIG_CMDLINE_BOOL is not set
 
 #
 # Security options
diff --git a/arch/mips/configs/pb1100_defconfig b/arch/mips/configs/pb1100_defconfig
index be8091ef0a79..ddf67f639194 100644
--- a/arch/mips/configs/pb1100_defconfig
+++ b/arch/mips/configs/pb1100_defconfig
@@ -23,7 +23,6 @@ CONFIG_MIPS_PB1100=y
 # CONFIG_MIPS_DB1550 is not set
 # CONFIG_MIPS_DB1200 is not set
 # CONFIG_MIPS_MIRAGE is not set
-# CONFIG_BASLER_EXCITE is not set
 # CONFIG_MIPS_COBALT is not set
 # CONFIG_MACH_DECSTATION is not set
 # CONFIG_MACH_JAZZ is not set
@@ -1083,7 +1082,7 @@ CONFIG_ENABLE_MUST_CHECK=y
 # CONFIG_DEBUG_KERNEL is not set
 CONFIG_LOG_BUF_SHIFT=14
 CONFIG_CROSSCOMPILE=y
-CONFIG_CMDLINE=""
+# CONFIG_CMDLINE_BOOL is not set
 
 #
 # Security options
diff --git a/arch/mips/configs/pb1500_defconfig b/arch/mips/configs/pb1500_defconfig
index e74ba794c789..5ec60836b645 100644
--- a/arch/mips/configs/pb1500_defconfig
+++ b/arch/mips/configs/pb1500_defconfig
@@ -23,7 +23,6 @@ CONFIG_MIPS_PB1500=y
 # CONFIG_MIPS_DB1550 is not set
 # CONFIG_MIPS_DB1200 is not set
 # CONFIG_MIPS_MIRAGE is not set
-# CONFIG_BASLER_EXCITE is not set
 # CONFIG_MIPS_COBALT is not set
 # CONFIG_MACH_DECSTATION is not set
 # CONFIG_MACH_JAZZ is not set
@@ -1200,7 +1199,7 @@ CONFIG_ENABLE_MUST_CHECK=y
 # CONFIG_DEBUG_KERNEL is not set
 CONFIG_LOG_BUF_SHIFT=14
 CONFIG_CROSSCOMPILE=y
-CONFIG_CMDLINE=""
+# CONFIG_CMDLINE_BOOL is not set
 
 #
 # Security options
diff --git a/arch/mips/configs/pb1550_defconfig b/arch/mips/configs/pb1550_defconfig
index 1d896fd830da..6647642b5d97 100644
--- a/arch/mips/configs/pb1550_defconfig
+++ b/arch/mips/configs/pb1550_defconfig
@@ -23,7 +23,6 @@ CONFIG_MIPS_PB1550=y
 # CONFIG_MIPS_DB1550 is not set
 # CONFIG_MIPS_DB1200 is not set
 # CONFIG_MIPS_MIRAGE is not set
-# CONFIG_BASLER_EXCITE is not set
 # CONFIG_MIPS_COBALT is not set
 # CONFIG_MACH_DECSTATION is not set
 # CONFIG_MACH_JAZZ is not set
@@ -1193,7 +1192,7 @@ CONFIG_ENABLE_MUST_CHECK=y
 # CONFIG_DEBUG_KERNEL is not set
 CONFIG_LOG_BUF_SHIFT=14
 CONFIG_CROSSCOMPILE=y
-CONFIG_CMDLINE=""
+# CONFIG_CMDLINE_BOOL is not set
 
 #
 # Security options
diff --git a/arch/mips/configs/pnx8335-stb225_defconfig b/arch/mips/configs/pnx8335-stb225_defconfig
index fef4d31c2055..848344d588d1 100644
--- a/arch/mips/configs/pnx8335-stb225_defconfig
+++ b/arch/mips/configs/pnx8335-stb225_defconfig
@@ -9,7 +9,6 @@ CONFIG_MIPS=y
 # Machine selection
 #
 # CONFIG_MACH_ALCHEMY is not set
-# CONFIG_BASLER_EXCITE is not set
 # CONFIG_BCM47XX is not set
 # CONFIG_MIPS_COBALT is not set
 # CONFIG_MACH_DECSTATION is not set
@@ -1034,7 +1033,7 @@ CONFIG_FRAME_WARN=1024
 # CONFIG_DEBUG_KERNEL is not set
 # CONFIG_SAMPLES is not set
 # CONFIG_KERNEL_TESTS is not set
-CONFIG_CMDLINE=""
+# CONFIG_CMDLINE_BOOL is not set
 
 #
 # Security options
diff --git a/arch/mips/configs/pnx8550-jbs_defconfig b/arch/mips/configs/pnx8550-jbs_defconfig
index e10c7116c3c2..9d721fdccb30 100644
--- a/arch/mips/configs/pnx8550-jbs_defconfig
+++ b/arch/mips/configs/pnx8550-jbs_defconfig
@@ -22,7 +22,6 @@ CONFIG_ZONE_DMA=y
 # CONFIG_MIPS_DB1550 is not set
 # CONFIG_MIPS_DB1200 is not set
 # CONFIG_MIPS_MIRAGE is not set
-# CONFIG_BASLER_EXCITE is not set
 # CONFIG_MIPS_COBALT is not set
 # CONFIG_MACH_DECSTATION is not set
 # CONFIG_MACH_JAZZ is not set
@@ -1215,7 +1214,9 @@ CONFIG_DEBUG_MUTEXES=y
 CONFIG_FORCED_INLINING=y
 # CONFIG_RCU_TORTURE_TEST is not set
 CONFIG_CROSSCOMPILE=y
+CONFIG_CMDLINE_BOOL=y
 CONFIG_CMDLINE="console=ttyS1,38400n8 root=/dev/nfs ip=bootp"
+# CONFIG_CMDLINE_OVERRIDE is not set
 # CONFIG_DEBUG_STACK_USAGE is not set
 # CONFIG_RUNTIME_DEBUG is not set
 
diff --git a/arch/mips/configs/pnx8550-stb810_defconfig b/arch/mips/configs/pnx8550-stb810_defconfig
index 5ed3c8dfa0a1..ab07ec08c6fa 100644
--- a/arch/mips/configs/pnx8550-stb810_defconfig
+++ b/arch/mips/configs/pnx8550-stb810_defconfig
@@ -22,7 +22,6 @@ CONFIG_ZONE_DMA=y
 # CONFIG_MIPS_DB1550 is not set
 # CONFIG_MIPS_DB1200 is not set
 # CONFIG_MIPS_MIRAGE is not set
-# CONFIG_BASLER_EXCITE is not set
 # CONFIG_MIPS_COBALT is not set
 # CONFIG_MACH_DECSTATION is not set
 # CONFIG_MACH_JAZZ is not set
@@ -1205,7 +1204,9 @@ CONFIG_DEBUG_SLAB=y
 CONFIG_FORCED_INLINING=y
 # CONFIG_RCU_TORTURE_TEST is not set
 CONFIG_CROSSCOMPILE=y
+CONFIG_CMDLINE_BOOL=y
 CONFIG_CMDLINE="console=ttyS1,38400n8 root=/dev/nfs ip=bootp"
+# CONFIG_CMDLINE_OVERRIDE is not set
 # CONFIG_DEBUG_STACK_USAGE is not set
 # CONFIG_RUNTIME_DEBUG is not set
 
diff --git a/arch/mips/configs/powertv_defconfig b/arch/mips/configs/powertv_defconfig
new file mode 100644
index 000000000000..7291633d81cc
--- /dev/null
+++ b/arch/mips/configs/powertv_defconfig
@@ -0,0 +1,1550 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.31-rc5
+# Fri Aug 28 14:49:33 2009
+#
+CONFIG_MIPS=y
+
+#
+# Machine selection
+#
+# CONFIG_MACH_ALCHEMY is not set
+# CONFIG_AR7 is not set
+# CONFIG_BCM47XX is not set
+# CONFIG_MIPS_COBALT is not set
+# CONFIG_MACH_DECSTATION is not set
+# CONFIG_MACH_JAZZ is not set
+# CONFIG_LASAT is not set
+# CONFIG_LEMOTE_FULONG is not set
+# CONFIG_MIPS_MALTA is not set
+# CONFIG_MIPS_SIM is not set
+# CONFIG_NEC_MARKEINS is not set
+# CONFIG_MACH_VR41XX is not set
+# CONFIG_NXP_STB220 is not set
+# CONFIG_NXP_STB225 is not set
+# CONFIG_PNX8550_JBS is not set
+# CONFIG_PNX8550_STB810 is not set
+# CONFIG_PMC_MSP is not set
+# CONFIG_PMC_YOSEMITE is not set
+CONFIG_POWERTV=y
+# CONFIG_SGI_IP22 is not set
+# CONFIG_SGI_IP27 is not set
+# CONFIG_SGI_IP28 is not set
+# CONFIG_SGI_IP32 is not set
+# CONFIG_SIBYTE_CRHINE is not set
+# CONFIG_SIBYTE_CARMEL is not set
+# CONFIG_SIBYTE_CRHONE is not set
+# CONFIG_SIBYTE_RHONE is not set
+# CONFIG_SIBYTE_SWARM is not set
+# CONFIG_SIBYTE_LITTLESUR is not set
+# CONFIG_SIBYTE_SENTOSA is not set
+# CONFIG_SIBYTE_BIGSUR is not set
+# CONFIG_SNI_RM is not set
+# CONFIG_MACH_TX39XX is not set
+# CONFIG_MACH_TX49XX is not set
+# CONFIG_MIKROTIK_RB532 is not set
+# CONFIG_WR_PPMC is not set
+# CONFIG_CAVIUM_OCTEON_SIMULATOR is not set
+# CONFIG_CAVIUM_OCTEON_REFERENCE_BOARD is not set
+# CONFIG_ALCHEMY_GPIO_INDIRECT is not set
+# CONFIG_MIN_RUNTIME_RESOURCES is not set
+# CONFIG_BOOTLOADER_DRIVER is not set
+CONFIG_BOOTLOADER_FAMILY="R2"
+CONFIG_CSRC_POWERTV=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_ARCH_SUPPORTS_OPROFILE=y
+CONFIG_GENERIC_FIND_NEXT_BIT=y
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_CMOS_UPDATE=y
+CONFIG_SCHED_OMIT_FRAME_POINTER=y
+CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
+CONFIG_CEVT_R4K_LIB=y
+CONFIG_CEVT_R4K=y
+CONFIG_DMA_NONCOHERENT=y
+CONFIG_DMA_NEED_PCI_MAP_STATE=y
+# CONFIG_EARLY_PRINTK is not set
+CONFIG_SYS_HAS_EARLY_PRINTK=y
+# CONFIG_NO_IOPORT is not set
+CONFIG_CPU_BIG_ENDIAN=y
+# CONFIG_CPU_LITTLE_ENDIAN is not set
+CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y
+CONFIG_BOOT_ELF32=y
+CONFIG_MIPS_L1_CACHE_SHIFT=5
+
+#
+# CPU selection
+#
+# CONFIG_CPU_LOONGSON2 is not set
+# CONFIG_CPU_MIPS32_R1 is not set
+CONFIG_CPU_MIPS32_R2=y
+# CONFIG_CPU_MIPS64_R1 is not set
+# CONFIG_CPU_MIPS64_R2 is not set
+# CONFIG_CPU_R3000 is not set
+# CONFIG_CPU_TX39XX is not set
+# CONFIG_CPU_VR41XX is not set
+# CONFIG_CPU_R4300 is not set
+# CONFIG_CPU_R4X00 is not set
+# CONFIG_CPU_TX49XX is not set
+# CONFIG_CPU_R5000 is not set
+# CONFIG_CPU_R5432 is not set
+# CONFIG_CPU_R5500 is not set
+# CONFIG_CPU_R6000 is not set
+# CONFIG_CPU_NEVADA is not set
+# CONFIG_CPU_R8000 is not set
+# CONFIG_CPU_R10000 is not set
+# CONFIG_CPU_RM7000 is not set
+# CONFIG_CPU_RM9000 is not set
+# CONFIG_CPU_SB1 is not set
+# CONFIG_CPU_CAVIUM_OCTEON is not set
+CONFIG_SYS_HAS_CPU_MIPS32_R2=y
+CONFIG_CPU_MIPS32=y
+CONFIG_CPU_MIPSR2=y
+CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
+CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
+CONFIG_HARDWARE_WATCHPOINTS=y
+
+#
+# Kernel type
+#
+CONFIG_32BIT=y
+# CONFIG_64BIT is not set
+CONFIG_PAGE_SIZE_4KB=y
+# CONFIG_PAGE_SIZE_8KB is not set
+# CONFIG_PAGE_SIZE_16KB is not set
+# CONFIG_PAGE_SIZE_32KB is not set
+# CONFIG_PAGE_SIZE_64KB is not set
+CONFIG_CPU_HAS_PREFETCH=y
+CONFIG_MIPS_MT_DISABLED=y
+# CONFIG_MIPS_MT_SMP is not set
+# CONFIG_MIPS_MT_SMTC is not set
+CONFIG_CPU_HAS_LLSC=y
+CONFIG_CPU_MIPSR2_IRQ_VI=y
+CONFIG_CPU_MIPSR2_IRQ_EI=y
+CONFIG_CPU_HAS_SYNC=y
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_GENERIC_IRQ_PROBE=y
+# CONFIG_HIGHMEM is not set
+CONFIG_CPU_SUPPORTS_HIGHMEM=y
+CONFIG_SYS_SUPPORTS_HIGHMEM=y
+CONFIG_ARCH_FLATMEM_ENABLE=y
+CONFIG_ARCH_POPULATES_NODE_MAP=y
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_SPLIT_PTLOCK_CPUS=4
+# CONFIG_PHYS_ADDR_T_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=0
+CONFIG_VIRT_TO_BUS=y
+CONFIG_HAVE_MLOCK=y
+CONFIG_HAVE_MLOCKED_PAGE_BIT=y
+CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
+CONFIG_TICK_ONESHOT=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+# CONFIG_HZ_48 is not set
+# CONFIG_HZ_100 is not set
+# CONFIG_HZ_128 is not set
+# CONFIG_HZ_250 is not set
+# CONFIG_HZ_256 is not set
+CONFIG_HZ_1000=y
+# CONFIG_HZ_1024 is not set
+CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
+CONFIG_HZ=1000
+# CONFIG_PREEMPT_NONE is not set
+# CONFIG_PREEMPT_VOLUNTARY is not set
+CONFIG_PREEMPT=y
+# CONFIG_KEXEC is not set
+# CONFIG_SECCOMP is not set
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+CONFIG_CONSTRUCTORS=y
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_LOCK_KERNEL=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION=""
+CONFIG_LOCALVERSION_AUTO=y
+# CONFIG_SWAP is not set
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+# CONFIG_POSIX_MQUEUE is not set
+# CONFIG_BSD_PROCESS_ACCT is not set
+# CONFIG_TASKSTATS is not set
+# CONFIG_AUDIT is not set
+
+#
+# RCU Subsystem
+#
+CONFIG_CLASSIC_RCU=y
+# CONFIG_TREE_RCU is not set
+# CONFIG_PREEMPT_RCU is not set
+# CONFIG_TREE_RCU_TRACE is not set
+# CONFIG_PREEMPT_RCU_TRACE is not set
+# CONFIG_IKCONFIG is not set
+CONFIG_LOG_BUF_SHIFT=16
+CONFIG_GROUP_SCHED=y
+CONFIG_FAIR_GROUP_SCHED=y
+# CONFIG_RT_GROUP_SCHED is not set
+CONFIG_USER_SCHED=y
+# CONFIG_CGROUP_SCHED is not set
+# CONFIG_CGROUPS is not set
+# CONFIG_SYSFS_DEPRECATED_V2 is not set
+CONFIG_RELAY=y
+# CONFIG_NAMESPACES is not set
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+# CONFIG_RD_GZIP is not set
+# CONFIG_RD_BZIP2 is not set
+# CONFIG_RD_LZMA is not set
+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+CONFIG_SYSCTL=y
+CONFIG_ANON_INODES=y
+CONFIG_EMBEDDED=y
+# CONFIG_SYSCTL_SYSCALL is not set
+CONFIG_KALLSYMS=y
+CONFIG_KALLSYMS_ALL=y
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+# CONFIG_PCSPKR_PLATFORM is not set
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+# CONFIG_EPOLL is not set
+# CONFIG_SIGNALFD is not set
+CONFIG_TIMERFD=y
+# CONFIG_EVENTFD is not set
+CONFIG_SHMEM=y
+CONFIG_AIO=y
+
+#
+# Performance Counters
+#
+# CONFIG_VM_EVENT_COUNTERS is not set
+CONFIG_PCI_QUIRKS=y
+# CONFIG_SLUB_DEBUG is not set
+# CONFIG_STRIP_ASM_SYMS is not set
+CONFIG_COMPAT_BRK=y
+# CONFIG_SLAB is not set
+CONFIG_SLUB=y
+# CONFIG_SLOB is not set
+# CONFIG_PROFILING is not set
+# CONFIG_MARKERS is not set
+CONFIG_HAVE_OPROFILE=y
+
+#
+# GCOV-based kernel profiling
+#
+# CONFIG_GCOV_KERNEL is not set
+# CONFIG_SLOW_WORK is not set
+# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
+CONFIG_RT_MUTEXES=y
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+# CONFIG_MODULE_FORCE_LOAD is not set
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODULE_FORCE_UNLOAD is not set
+CONFIG_MODVERSIONS=y
+CONFIG_MODULE_SRCVERSION_ALL=y
+CONFIG_BLOCK=y
+CONFIG_LBDAF=y
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_BLK_DEV_INTEGRITY is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+# CONFIG_IOSCHED_AS is not set
+# CONFIG_IOSCHED_DEADLINE is not set
+# CONFIG_IOSCHED_CFQ is not set
+# CONFIG_DEFAULT_AS is not set
+# CONFIG_DEFAULT_DEADLINE is not set
+# CONFIG_DEFAULT_CFQ is not set
+CONFIG_DEFAULT_NOOP=y
+CONFIG_DEFAULT_IOSCHED="noop"
+# CONFIG_PROBE_INITRD_HEADER is not set
+# CONFIG_FREEZER is not set
+
+#
+# Bus options (PCI, PCMCIA, EISA, ISA, TC)
+#
+CONFIG_HW_HAS_PCI=y
+CONFIG_PCI=y
+CONFIG_PCI_DOMAINS=y
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+# CONFIG_PCI_LEGACY is not set
+# CONFIG_PCI_DEBUG is not set
+# CONFIG_PCI_STUB is not set
+# CONFIG_PCI_IOV is not set
+CONFIG_MMU=y
+# CONFIG_PCCARD is not set
+# CONFIG_HOTPLUG_PCI is not set
+
+#
+# Executable file formats
+#
+CONFIG_BINFMT_ELF=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+# CONFIG_HAVE_AOUT is not set
+# CONFIG_BINFMT_MISC is not set
+CONFIG_TRAD_SIGNALS=y
+
+#
+# Power management options
+#
+CONFIG_ARCH_HIBERNATION_POSSIBLE=y
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+# CONFIG_PM is not set
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+CONFIG_PACKET_MMAP=y
+CONFIG_UNIX=y
+CONFIG_XFRM=y
+# CONFIG_XFRM_USER is not set
+# CONFIG_XFRM_SUB_POLICY is not set
+# CONFIG_XFRM_MIGRATE is not set
+# CONFIG_XFRM_STATISTICS is not set
+CONFIG_XFRM_IPCOMP=y
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_ADVANCED_ROUTER=y
+CONFIG_ASK_IP_FIB_HASH=y
+# CONFIG_IP_FIB_TRIE is not set
+CONFIG_IP_FIB_HASH=y
+# CONFIG_IP_MULTIPLE_TABLES is not set
+# CONFIG_IP_ROUTE_MULTIPATH is not set
+# CONFIG_IP_ROUTE_VERBOSE is not set
+CONFIG_IP_PNP=y
+# CONFIG_IP_PNP_DHCP is not set
+# CONFIG_IP_PNP_BOOTP is not set
+# CONFIG_IP_PNP_RARP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_IP_MROUTE is not set
+# CONFIG_ARPD is not set
+CONFIG_SYN_COOKIES=y
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
+# CONFIG_INET_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_LRO is not set
+# CONFIG_INET_DIAG is not set
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+CONFIG_IPV6=y
+CONFIG_IPV6_PRIVACY=y
+# CONFIG_IPV6_ROUTER_PREF is not set
+# CONFIG_IPV6_OPTIMISTIC_DAD is not set
+CONFIG_INET6_AH=y
+CONFIG_INET6_ESP=y
+CONFIG_INET6_IPCOMP=y
+# CONFIG_IPV6_MIP6 is not set
+CONFIG_INET6_XFRM_TUNNEL=y
+CONFIG_INET6_TUNNEL=y
+# CONFIG_INET6_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET6_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET6_XFRM_MODE_BEET is not set
+# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set
+# CONFIG_IPV6_SIT is not set
+CONFIG_IPV6_TUNNEL=y
+# CONFIG_IPV6_MULTIPLE_TABLES is not set
+# CONFIG_IPV6_MROUTE is not set
+# CONFIG_NETWORK_SECMARK is not set
+CONFIG_NETFILTER=y
+# CONFIG_NETFILTER_DEBUG is not set
+CONFIG_NETFILTER_ADVANCED=y
+# CONFIG_BRIDGE_NETFILTER is not set
+
+#
+# Core Netfilter Configuration
+#
+# CONFIG_NETFILTER_NETLINK_QUEUE is not set
+# CONFIG_NETFILTER_NETLINK_LOG is not set
+# CONFIG_NF_CONNTRACK is not set
+CONFIG_NETFILTER_XTABLES=y
+# CONFIG_NETFILTER_XT_TARGET_CLASSIFY is not set
+# CONFIG_NETFILTER_XT_TARGET_MARK is not set
+# CONFIG_NETFILTER_XT_TARGET_NFLOG is not set
+# CONFIG_NETFILTER_XT_TARGET_NFQUEUE is not set
+# CONFIG_NETFILTER_XT_TARGET_RATEEST is not set
+# CONFIG_NETFILTER_XT_TARGET_TCPMSS is not set
+# CONFIG_NETFILTER_XT_MATCH_COMMENT is not set
+# CONFIG_NETFILTER_XT_MATCH_DCCP is not set
+# CONFIG_NETFILTER_XT_MATCH_DSCP is not set
+# CONFIG_NETFILTER_XT_MATCH_ESP is not set
+# CONFIG_NETFILTER_XT_MATCH_HASHLIMIT is not set
+# CONFIG_NETFILTER_XT_MATCH_HL is not set
+# CONFIG_NETFILTER_XT_MATCH_IPRANGE is not set
+# CONFIG_NETFILTER_XT_MATCH_LENGTH is not set
+# CONFIG_NETFILTER_XT_MATCH_LIMIT is not set
+# CONFIG_NETFILTER_XT_MATCH_MAC is not set
+# CONFIG_NETFILTER_XT_MATCH_MARK is not set
+CONFIG_NETFILTER_XT_MATCH_MULTIPORT=y
+# CONFIG_NETFILTER_XT_MATCH_OWNER is not set
+# CONFIG_NETFILTER_XT_MATCH_POLICY is not set
+# CONFIG_NETFILTER_XT_MATCH_PKTTYPE is not set
+# CONFIG_NETFILTER_XT_MATCH_QUOTA is not set
+# CONFIG_NETFILTER_XT_MATCH_RATEEST is not set
+# CONFIG_NETFILTER_XT_MATCH_REALM is not set
+# CONFIG_NETFILTER_XT_MATCH_RECENT is not set
+# CONFIG_NETFILTER_XT_MATCH_SCTP is not set
+# CONFIG_NETFILTER_XT_MATCH_STATISTIC is not set
+# CONFIG_NETFILTER_XT_MATCH_STRING is not set
+# CONFIG_NETFILTER_XT_MATCH_TCPMSS is not set
+# CONFIG_NETFILTER_XT_MATCH_TIME is not set
+# CONFIG_NETFILTER_XT_MATCH_U32 is not set
+# CONFIG_IP_VS is not set
+
+#
+# IP: Netfilter Configuration
+#
+# CONFIG_NF_DEFRAG_IPV4 is not set
+# CONFIG_IP_NF_QUEUE is not set
+CONFIG_IP_NF_IPTABLES=y
+# CONFIG_IP_NF_MATCH_ADDRTYPE is not set
+# CONFIG_IP_NF_MATCH_AH is not set
+# CONFIG_IP_NF_MATCH_ECN is not set
+# CONFIG_IP_NF_MATCH_TTL is not set
+CONFIG_IP_NF_FILTER=y
+# CONFIG_IP_NF_TARGET_REJECT is not set
+# CONFIG_IP_NF_TARGET_LOG is not set
+# CONFIG_IP_NF_TARGET_ULOG is not set
+# CONFIG_IP_NF_MANGLE is not set
+# CONFIG_IP_NF_TARGET_TTL is not set
+# CONFIG_IP_NF_RAW is not set
+CONFIG_IP_NF_ARPTABLES=y
+CONFIG_IP_NF_ARPFILTER=y
+# CONFIG_IP_NF_ARP_MANGLE is not set
+
+#
+# IPv6: Netfilter Configuration
+#
+# CONFIG_IP6_NF_QUEUE is not set
+CONFIG_IP6_NF_IPTABLES=y
+# CONFIG_IP6_NF_MATCH_AH is not set
+# CONFIG_IP6_NF_MATCH_EUI64 is not set
+# CONFIG_IP6_NF_MATCH_FRAG is not set
+# CONFIG_IP6_NF_MATCH_OPTS is not set
+# CONFIG_IP6_NF_MATCH_HL is not set
+# CONFIG_IP6_NF_MATCH_IPV6HEADER is not set
+# CONFIG_IP6_NF_MATCH_MH is not set
+# CONFIG_IP6_NF_MATCH_RT is not set
+# CONFIG_IP6_NF_TARGET_HL is not set
+# CONFIG_IP6_NF_TARGET_LOG is not set
+CONFIG_IP6_NF_FILTER=y
+# CONFIG_IP6_NF_TARGET_REJECT is not set
+# CONFIG_IP6_NF_MANGLE is not set
+# CONFIG_IP6_NF_RAW is not set
+# CONFIG_IP_DCCP is not set
+# CONFIG_IP_SCTP is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+CONFIG_STP=y
+CONFIG_BRIDGE=y
+# CONFIG_NET_DSA is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+CONFIG_LLC=y
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_PHONET is not set
+# CONFIG_IEEE802154 is not set
+CONFIG_NET_SCHED=y
+
+#
+# Queueing/Scheduling
+#
+# CONFIG_NET_SCH_CBQ is not set
+# CONFIG_NET_SCH_HTB is not set
+# CONFIG_NET_SCH_HFSC is not set
+# CONFIG_NET_SCH_PRIO is not set
+# CONFIG_NET_SCH_MULTIQ is not set
+# CONFIG_NET_SCH_RED is not set
+# CONFIG_NET_SCH_SFQ is not set
+# CONFIG_NET_SCH_TEQL is not set
+CONFIG_NET_SCH_TBF=y
+# CONFIG_NET_SCH_GRED is not set
+# CONFIG_NET_SCH_DSMARK is not set
+# CONFIG_NET_SCH_NETEM is not set
+# CONFIG_NET_SCH_DRR is not set
+
+#
+# Classification
+#
+# CONFIG_NET_CLS_BASIC is not set
+# CONFIG_NET_CLS_TCINDEX is not set
+# CONFIG_NET_CLS_ROUTE4 is not set
+# CONFIG_NET_CLS_FW is not set
+# CONFIG_NET_CLS_U32 is not set
+# CONFIG_NET_CLS_RSVP is not set
+# CONFIG_NET_CLS_RSVP6 is not set
+# CONFIG_NET_CLS_FLOW is not set
+# CONFIG_NET_EMATCH is not set
+# CONFIG_NET_CLS_ACT is not set
+CONFIG_NET_SCH_FIFO=y
+# CONFIG_DCB is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+# CONFIG_AF_RXRPC is not set
+# CONFIG_WIRELESS is not set
+# CONFIG_WIMAX is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+CONFIG_FW_LOADER=y
+CONFIG_FIRMWARE_IN_KERNEL=y
+CONFIG_EXTRA_FIRMWARE=""
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
+# CONFIG_SYS_HYPERVISOR is not set
+# CONFIG_CONNECTOR is not set
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+# CONFIG_MTD_CONCAT is not set
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_TESTS is not set
+# CONFIG_MTD_REDBOOT_PARTS is not set
+CONFIG_MTD_CMDLINE_PARTS=y
+# CONFIG_MTD_AR7_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+# CONFIG_MTD_CFI is not set
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+# CONFIG_MTD_INTEL_VR_NOR is not set
+# CONFIG_MTD_PLATRAM is not set
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_PMC551 is not set
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+CONFIG_MTD_NAND=y
+# CONFIG_MTD_NAND_VERIFY_WRITE is not set
+# CONFIG_MTD_NAND_ECC_SMC is not set
+# CONFIG_MTD_NAND_MUSEUM_IDS is not set
+CONFIG_MTD_NAND_IDS=y
+# CONFIG_MTD_NAND_DISKONCHIP is not set
+# CONFIG_MTD_NAND_CAFE is not set
+# CONFIG_MTD_NAND_NANDSIM is not set
+# CONFIG_MTD_NAND_PLATFORM is not set
+# CONFIG_MTD_ALAUDA is not set
+# CONFIG_MTD_ONENAND is not set
+
+#
+# LPDDR flash memory drivers
+#
+# CONFIG_MTD_LPDDR is not set
+
+#
+# UBI - Unsorted block images
+#
+# CONFIG_MTD_UBI is not set
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_CPQ_DA is not set
+# CONFIG_BLK_CPQ_CISS_DA is not set
+# CONFIG_BLK_DEV_DAC960 is not set
+# CONFIG_BLK_DEV_UMEM is not set
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=y
+# CONFIG_BLK_DEV_CRYPTOLOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_SX8 is not set
+# CONFIG_BLK_DEV_UB is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=32768
+# CONFIG_BLK_DEV_XIP is not set
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+# CONFIG_BLK_DEV_HD is not set
+# CONFIG_MISC_DEVICES is not set
+CONFIG_HAVE_IDE=y
+# CONFIG_IDE is not set
+
+#
+# SCSI device support
+#
+# CONFIG_RAID_ATTRS is not set
+CONFIG_SCSI=y
+CONFIG_SCSI_DMA=y
+# CONFIG_SCSI_TGT is not set
+# CONFIG_SCSI_NETLINK is not set
+# CONFIG_SCSI_PROC_FS is not set
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+# CONFIG_BLK_DEV_SR is not set
+# CONFIG_CHR_DEV_SG is not set
+# CONFIG_CHR_DEV_SCH is not set
+# CONFIG_SCSI_MULTI_LUN is not set
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+# CONFIG_SCSI_SCAN_ASYNC is not set
+CONFIG_SCSI_WAIT_SCAN=m
+
+#
+# SCSI Transports
+#
+# CONFIG_SCSI_SPI_ATTRS is not set
+# CONFIG_SCSI_FC_ATTRS is not set
+# CONFIG_SCSI_ISCSI_ATTRS is not set
+# CONFIG_SCSI_SAS_LIBSAS is not set
+# CONFIG_SCSI_SRP_ATTRS is not set
+# CONFIG_SCSI_LOWLEVEL is not set
+# CONFIG_SCSI_DH is not set
+# CONFIG_SCSI_OSD_INITIATOR is not set
+CONFIG_ATA=y
+# CONFIG_ATA_NONSTANDARD is not set
+CONFIG_SATA_PMP=y
+# CONFIG_SATA_AHCI is not set
+# CONFIG_SATA_SIL24 is not set
+CONFIG_ATA_SFF=y
+# CONFIG_SATA_SVW is not set
+# CONFIG_ATA_PIIX is not set
+# CONFIG_SATA_MV is not set
+# CONFIG_SATA_NV is not set
+# CONFIG_PDC_ADMA is not set
+# CONFIG_SATA_QSTOR is not set
+# CONFIG_SATA_PROMISE is not set
+# CONFIG_SATA_SX4 is not set
+# CONFIG_SATA_SIL is not set
+# CONFIG_SATA_SIS is not set
+# CONFIG_SATA_ULI is not set
+# CONFIG_SATA_VIA is not set
+# CONFIG_SATA_VITESSE is not set
+# CONFIG_SATA_INIC162X is not set
+# CONFIG_PATA_ALI is not set
+# CONFIG_PATA_AMD is not set
+# CONFIG_PATA_ARTOP is not set
+# CONFIG_PATA_ATIIXP is not set
+# CONFIG_PATA_CMD640_PCI is not set
+# CONFIG_PATA_CMD64X is not set
+# CONFIG_PATA_CS5520 is not set
+# CONFIG_PATA_CS5530 is not set
+# CONFIG_PATA_CYPRESS is not set
+# CONFIG_PATA_EFAR is not set
+# CONFIG_ATA_GENERIC is not set
+# CONFIG_PATA_HPT366 is not set
+# CONFIG_PATA_HPT37X is not set
+# CONFIG_PATA_HPT3X2N is not set
+# CONFIG_PATA_HPT3X3 is not set
+# CONFIG_PATA_IT821X is not set
+# CONFIG_PATA_IT8213 is not set
+# CONFIG_PATA_JMICRON is not set
+# CONFIG_PATA_TRIFLEX is not set
+# CONFIG_PATA_MARVELL is not set
+# CONFIG_PATA_MPIIX is not set
+# CONFIG_PATA_OLDPIIX is not set
+# CONFIG_PATA_NETCELL is not set
+# CONFIG_PATA_NINJA32 is not set
+# CONFIG_PATA_NS87410 is not set
+# CONFIG_PATA_NS87415 is not set
+# CONFIG_PATA_OPTI is not set
+# CONFIG_PATA_OPTIDMA is not set
+# CONFIG_PATA_PDC_OLD is not set
+# CONFIG_PATA_RADISYS is not set
+# CONFIG_PATA_RZ1000 is not set
+# CONFIG_PATA_SC1200 is not set
+# CONFIG_PATA_SERVERWORKS is not set
+# CONFIG_PATA_PDC2027X is not set
+# CONFIG_PATA_SIL680 is not set
+# CONFIG_PATA_SIS is not set
+# CONFIG_PATA_VIA is not set
+# CONFIG_PATA_WINBOND is not set
+# CONFIG_PATA_PLATFORM is not set
+# CONFIG_PATA_SCH is not set
+# CONFIG_MD is not set
+# CONFIG_FUSION is not set
+
+#
+# IEEE 1394 (FireWire) support
+#
+
+#
+# You can enable one or both FireWire driver stacks.
+#
+
+#
+# See the help texts for more information.
+#
+# CONFIG_FIREWIRE is not set
+# CONFIG_IEEE1394 is not set
+# CONFIG_I2O is not set
+CONFIG_NETDEVICES=y
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_VETH is not set
+# CONFIG_ARCNET is not set
+# CONFIG_PHYLIB is not set
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
+# CONFIG_AX88796 is not set
+# CONFIG_HAPPYMEAL is not set
+# CONFIG_SUNGEM is not set
+# CONFIG_CASSINI is not set
+# CONFIG_NET_VENDOR_3COM is not set
+# CONFIG_SMC91X is not set
+# CONFIG_DM9000 is not set
+# CONFIG_ETHOC is not set
+# CONFIG_DNET is not set
+# CONFIG_NET_TULIP is not set
+# CONFIG_HP100 is not set
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
+# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
+# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
+# CONFIG_NET_PCI is not set
+# CONFIG_B44 is not set
+# CONFIG_KS8842 is not set
+# CONFIG_ATL2 is not set
+CONFIG_NETDEV_1000=y
+# CONFIG_ACENIC is not set
+# CONFIG_DL2K is not set
+# CONFIG_E1000 is not set
+# CONFIG_E1000E is not set
+# CONFIG_IP1000 is not set
+# CONFIG_IGB is not set
+# CONFIG_IGBVF is not set
+# CONFIG_NS83820 is not set
+# CONFIG_HAMACHI is not set
+# CONFIG_YELLOWFIN is not set
+# CONFIG_R8169 is not set
+# CONFIG_SIS190 is not set
+# CONFIG_SKGE is not set
+# CONFIG_SKY2 is not set
+# CONFIG_VIA_VELOCITY is not set
+# CONFIG_TIGON3 is not set
+# CONFIG_BNX2 is not set
+# CONFIG_CNIC is not set
+# CONFIG_QLA3XXX is not set
+# CONFIG_ATL1 is not set
+# CONFIG_ATL1E is not set
+# CONFIG_ATL1C is not set
+# CONFIG_JME is not set
+CONFIG_NETDEV_10000=y
+# CONFIG_CHELSIO_T1 is not set
+CONFIG_CHELSIO_T3_DEPENDS=y
+# CONFIG_CHELSIO_T3 is not set
+# CONFIG_ENIC is not set
+# CONFIG_IXGBE is not set
+# CONFIG_IXGB is not set
+# CONFIG_S2IO is not set
+# CONFIG_VXGE is not set
+# CONFIG_MYRI10GE is not set
+# CONFIG_NETXEN_NIC is not set
+# CONFIG_NIU is not set
+# CONFIG_MLX4_EN is not set
+# CONFIG_MLX4_CORE is not set
+# CONFIG_TEHUTI is not set
+# CONFIG_BNX2X is not set
+# CONFIG_QLGE is not set
+# CONFIG_SFC is not set
+# CONFIG_BE2NET is not set
+# CONFIG_TR is not set
+
+#
+# Wireless LAN
+#
+# CONFIG_WLAN_PRE80211 is not set
+# CONFIG_WLAN_80211 is not set
+
+#
+# Enable WiMAX (Networking options) to see the WiMAX drivers
+#
+
+#
+# USB Network Adapters
+#
+# CONFIG_USB_CATC is not set
+# CONFIG_USB_KAWETH is not set
+# CONFIG_USB_PEGASUS is not set
+CONFIG_USB_RTL8150=y
+# CONFIG_USB_USBNET is not set
+# CONFIG_WAN is not set
+# CONFIG_FDDI is not set
+# CONFIG_HIPPI is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+# CONFIG_NET_FC is not set
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_ISDN is not set
+# CONFIG_PHONE is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
+
+#
+# Userland interfaces
+#
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_JOYDEV is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input Device Drivers
+#
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+# CONFIG_INPUT_MISC is not set
+
+#
+# Hardware I/O ports
+#
+# CONFIG_SERIO is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+# CONFIG_VT is not set
+# CONFIG_DEVKMEM is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+# CONFIG_NOZOMI is not set
+
+#
+# Serial drivers
+#
+# CONFIG_SERIAL_8250 is not set
+
+#
+# Non-8250 serial port support
+#
+# CONFIG_SERIAL_JSM is not set
+CONFIG_UNIX98_PTYS=y
+# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
+# CONFIG_LEGACY_PTYS is not set
+# CONFIG_IPMI_HANDLER is not set
+# CONFIG_HW_RANDOM is not set
+# CONFIG_R3964 is not set
+# CONFIG_APPLICOM is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+CONFIG_DEVPORT=y
+# CONFIG_I2C is not set
+# CONFIG_SPI is not set
+
+#
+# PPS support
+#
+# CONFIG_PPS is not set
+# CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
+# CONFIG_HWMON is not set
+# CONFIG_THERMAL is not set
+# CONFIG_THERMAL_HWMON is not set
+# CONFIG_WATCHDOG is not set
+CONFIG_SSB_POSSIBLE=y
+
+#
+# Sonics Silicon Backplane
+#
+# CONFIG_SSB is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_CORE is not set
+# CONFIG_MFD_SM501 is not set
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_MFD_TMIO is not set
+# CONFIG_REGULATOR is not set
+# CONFIG_MEDIA_SUPPORT is not set
+
+#
+# Graphics support
+#
+# CONFIG_DRM is not set
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+# CONFIG_FB is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+# CONFIG_SOUND is not set
+CONFIG_HID_SUPPORT=y
+CONFIG_HID=y
+# CONFIG_HID_DEBUG is not set
+# CONFIG_HIDRAW is not set
+
+#
+# USB Input Devices
+#
+CONFIG_USB_HID=y
+# CONFIG_HID_PID is not set
+CONFIG_USB_HIDDEV=y
+
+#
+# Special HID drivers
+#
+# CONFIG_HID_A4TECH is not set
+# CONFIG_HID_APPLE is not set
+# CONFIG_HID_BELKIN is not set
+# CONFIG_HID_CHERRY is not set
+# CONFIG_HID_CHICONY is not set
+# CONFIG_HID_CYPRESS is not set
+# CONFIG_HID_DRAGONRISE is not set
+# CONFIG_HID_EZKEY is not set
+# CONFIG_HID_KYE is not set
+# CONFIG_HID_GYRATION is not set
+# CONFIG_HID_KENSINGTON is not set
+# CONFIG_HID_LOGITECH is not set
+# CONFIG_HID_MICROSOFT is not set
+# CONFIG_HID_MONTEREY is not set
+# CONFIG_HID_NTRIG is not set
+# CONFIG_HID_PANTHERLORD is not set
+# CONFIG_HID_PETALYNX is not set
+# CONFIG_HID_SAMSUNG is not set
+# CONFIG_HID_SONY is not set
+# CONFIG_HID_SUNPLUS is not set
+# CONFIG_HID_GREENASIA is not set
+# CONFIG_HID_SMARTJOYPLUS is not set
+# CONFIG_HID_TOPSEED is not set
+# CONFIG_HID_THRUSTMASTER is not set
+# CONFIG_HID_ZEROPLUS is not set
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_ARCH_HAS_HCD=y
+CONFIG_USB_ARCH_HAS_OHCI=y
+CONFIG_USB_ARCH_HAS_EHCI=y
+CONFIG_USB=y
+# CONFIG_USB_DEBUG is not set
+CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
+
+#
+# Miscellaneous USB options
+#
+CONFIG_USB_DEVICEFS=y
+# CONFIG_USB_DEVICE_CLASS is not set
+# CONFIG_USB_DYNAMIC_MINORS is not set
+# CONFIG_USB_OTG is not set
+# CONFIG_USB_OTG_WHITELIST is not set
+# CONFIG_USB_OTG_BLACKLIST_HUB is not set
+# CONFIG_USB_MON is not set
+# CONFIG_USB_WUSB is not set
+# CONFIG_USB_WUSB_CBAF is not set
+
+#
+# USB Host Controller Drivers
+#
+# CONFIG_USB_C67X00_HCD is not set
+# CONFIG_USB_XHCI_HCD is not set
+CONFIG_USB_EHCI_HCD=y
+# CONFIG_USB_EHCI_ROOT_HUB_TT is not set
+# CONFIG_USB_EHCI_TT_NEWSCHED is not set
+# CONFIG_USB_OXU210HP_HCD is not set
+# CONFIG_USB_ISP116X_HCD is not set
+# CONFIG_USB_ISP1760_HCD is not set
+CONFIG_USB_OHCI_HCD=y
+# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
+# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
+CONFIG_USB_OHCI_LITTLE_ENDIAN=y
+# CONFIG_USB_UHCI_HCD is not set
+# CONFIG_USB_SL811_HCD is not set
+# CONFIG_USB_R8A66597_HCD is not set
+# CONFIG_USB_WHCI_HCD is not set
+# CONFIG_USB_HWA_HCD is not set
+
+#
+# USB Device Class drivers
+#
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+# CONFIG_USB_WDM is not set
+# CONFIG_USB_TMC is not set
+
+#
+# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
+#
+
+#
+# also be needed; see USB_STORAGE Help for more info
+#
+CONFIG_USB_STORAGE=y
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
+# CONFIG_USB_STORAGE_USBAT is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_SDDR55 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_STORAGE_ALAUDA is not set
+# CONFIG_USB_STORAGE_ONETOUCH is not set
+# CONFIG_USB_STORAGE_KARMA is not set
+# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
+# CONFIG_USB_LIBUSUAL is not set
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_MICROTEK is not set
+
+#
+# USB port drivers
+#
+CONFIG_USB_SERIAL=y
+CONFIG_USB_SERIAL_CONSOLE=y
+# CONFIG_USB_EZUSB is not set
+# CONFIG_USB_SERIAL_GENERIC is not set
+# CONFIG_USB_SERIAL_AIRCABLE is not set
+# CONFIG_USB_SERIAL_ARK3116 is not set
+# CONFIG_USB_SERIAL_BELKIN is not set
+# CONFIG_USB_SERIAL_CH341 is not set
+# CONFIG_USB_SERIAL_WHITEHEAT is not set
+# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set
+CONFIG_USB_SERIAL_CP210X=y
+# CONFIG_USB_SERIAL_CYPRESS_M8 is not set
+# CONFIG_USB_SERIAL_EMPEG is not set
+# CONFIG_USB_SERIAL_FTDI_SIO is not set
+# CONFIG_USB_SERIAL_FUNSOFT is not set
+# CONFIG_USB_SERIAL_VISOR is not set
+# CONFIG_USB_SERIAL_IPAQ is not set
+# CONFIG_USB_SERIAL_IR is not set
+# CONFIG_USB_SERIAL_EDGEPORT is not set
+# CONFIG_USB_SERIAL_EDGEPORT_TI is not set
+# CONFIG_USB_SERIAL_GARMIN is not set
+# CONFIG_USB_SERIAL_IPW is not set
+# CONFIG_USB_SERIAL_IUU is not set
+# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set
+# CONFIG_USB_SERIAL_KEYSPAN is not set
+# CONFIG_USB_SERIAL_KLSI is not set
+# CONFIG_USB_SERIAL_KOBIL_SCT is not set
+# CONFIG_USB_SERIAL_MCT_U232 is not set
+# CONFIG_USB_SERIAL_MOS7720 is not set
+# CONFIG_USB_SERIAL_MOS7840 is not set
+# CONFIG_USB_SERIAL_MOTOROLA is not set
+# CONFIG_USB_SERIAL_NAVMAN is not set
+# CONFIG_USB_SERIAL_PL2303 is not set
+# CONFIG_USB_SERIAL_OTI6858 is not set
+# CONFIG_USB_SERIAL_QUALCOMM is not set
+# CONFIG_USB_SERIAL_SPCP8X5 is not set
+# CONFIG_USB_SERIAL_HP4X is not set
+# CONFIG_USB_SERIAL_SAFE is not set
+# CONFIG_USB_SERIAL_SIEMENS_MPI is not set
+# CONFIG_USB_SERIAL_SIERRAWIRELESS is not set
+# CONFIG_USB_SERIAL_SYMBOL is not set
+# CONFIG_USB_SERIAL_TI is not set
+# CONFIG_USB_SERIAL_CYBERJACK is not set
+# CONFIG_USB_SERIAL_XIRCOM is not set
+# CONFIG_USB_SERIAL_OPTION is not set
+# CONFIG_USB_SERIAL_OMNINET is not set
+# CONFIG_USB_SERIAL_OPTICON is not set
+# CONFIG_USB_SERIAL_DEBUG is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_EMI62 is not set
+# CONFIG_USB_EMI26 is not set
+# CONFIG_USB_ADUTUX is not set
+# CONFIG_USB_SEVSEG is not set
+# CONFIG_USB_RIO500 is not set
+# CONFIG_USB_LEGOTOWER is not set
+# CONFIG_USB_LCD is not set
+# CONFIG_USB_BERRY_CHARGE is not set
+# CONFIG_USB_LED is not set
+# CONFIG_USB_CYPRESS_CY7C63 is not set
+# CONFIG_USB_CYTHERM is not set
+# CONFIG_USB_IDMOUSE is not set
+# CONFIG_USB_FTDI_ELAN is not set
+# CONFIG_USB_APPLEDISPLAY is not set
+# CONFIG_USB_SISUSBVGA is not set
+# CONFIG_USB_LD is not set
+# CONFIG_USB_TRANCEVIBRATOR is not set
+# CONFIG_USB_IOWARRIOR is not set
+# CONFIG_USB_TEST is not set
+# CONFIG_USB_ISIGHTFW is not set
+# CONFIG_USB_VST is not set
+# CONFIG_USB_GADGET is not set
+
+#
+# OTG and related infrastructure
+#
+# CONFIG_NOP_USB_XCEIV is not set
+# CONFIG_UWB is not set
+# CONFIG_MMC is not set
+# CONFIG_MEMSTICK is not set
+# CONFIG_NEW_LEDS is not set
+# CONFIG_ACCESSIBILITY is not set
+# CONFIG_INFINIBAND is not set
+CONFIG_RTC_LIB=y
+# CONFIG_RTC_CLASS is not set
+# CONFIG_DMADEVICES is not set
+# CONFIG_AUXDISPLAY is not set
+# CONFIG_UIO is not set
+
+#
+# TI VLYNQ
+#
+# CONFIG_STAGING is not set
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+# CONFIG_EXT2_FS_XATTR is not set
+# CONFIG_EXT2_FS_XIP is not set
+CONFIG_EXT3_FS=y
+# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
+# CONFIG_EXT3_FS_XATTR is not set
+# CONFIG_EXT4_FS is not set
+CONFIG_JBD=y
+# CONFIG_JBD_DEBUG is not set
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+# CONFIG_FS_POSIX_ACL is not set
+# CONFIG_XFS_FS is not set
+# CONFIG_GFS2_FS is not set
+# CONFIG_OCFS2_FS is not set
+# CONFIG_BTRFS_FS is not set
+CONFIG_FILE_LOCKING=y
+CONFIG_FSNOTIFY=y
+# CONFIG_DNOTIFY is not set
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+CONFIG_FUSE_FS=y
+# CONFIG_CUSE is not set
+
+#
+# Caches
+#
+# CONFIG_FSCACHE is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+# CONFIG_MSDOS_FS is not set
+# CONFIG_VFAT_FS is not set
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_KCORE=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_HUGETLB_PAGE is not set
+# CONFIG_CONFIGFS_FS is not set
+CONFIG_MISC_FILESYSTEMS=y
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_DEBUG=0
+CONFIG_JFFS2_FS_WRITEBUFFER=y
+# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
+# CONFIG_JFFS2_SUMMARY is not set
+# CONFIG_JFFS2_FS_XATTR is not set
+# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
+CONFIG_JFFS2_ZLIB=y
+# CONFIG_JFFS2_LZO is not set
+CONFIG_JFFS2_RTIME=y
+# CONFIG_JFFS2_RUBIN is not set
+CONFIG_CRAMFS=y
+# CONFIG_SQUASHFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_OMFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+# CONFIG_NILFS2_FS is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+# CONFIG_NFS_V3_ACL is not set
+# CONFIG_NFS_V4 is not set
+CONFIG_ROOT_NFS=y
+# CONFIG_NFSD is not set
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=y
+# CONFIG_RPCSEC_GSS_KRB5 is not set
+# CONFIG_RPCSEC_GSS_SPKM3 is not set
+# CONFIG_SMB_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="iso8859-1"
+# CONFIG_NLS_CODEPAGE_437 is not set
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+# CONFIG_NLS_ASCII is not set
+# CONFIG_NLS_ISO8859_1 is not set
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+# CONFIG_NLS_UTF8 is not set
+# CONFIG_DLM is not set
+
+#
+# Kernel hacking
+#
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_PRINTK_TIME=y
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_FRAME_WARN=1024
+# CONFIG_MAGIC_SYSRQ is not set
+# CONFIG_UNUSED_SYMBOLS is not set
+CONFIG_DEBUG_FS=y
+# CONFIG_HEADERS_CHECK is not set
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_SHIRQ is not set
+CONFIG_DETECT_SOFTLOCKUP=y
+# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
+CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
+CONFIG_DETECT_HUNG_TASK=y
+# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set
+CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0
+# CONFIG_SCHED_DEBUG is not set
+# CONFIG_SCHEDSTATS is not set
+# CONFIG_TIMER_STATS is not set
+# CONFIG_DEBUG_OBJECTS is not set
+# CONFIG_DEBUG_PREEMPT is not set
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_RT_MUTEX_TESTER is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_DEBUG_MUTEXES is not set
+# CONFIG_DEBUG_LOCK_ALLOC is not set
+# CONFIG_PROVE_LOCKING is not set
+# CONFIG_LOCK_STAT is not set
+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+# CONFIG_DEBUG_KOBJECT is not set
+CONFIG_DEBUG_INFO=y
+# CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_WRITECOUNT is not set
+# CONFIG_DEBUG_MEMORY_INIT is not set
+# CONFIG_DEBUG_LIST is not set
+# CONFIG_DEBUG_SG is not set
+# CONFIG_DEBUG_NOTIFIERS is not set
+# CONFIG_BOOT_PRINTK_DELAY is not set
+# CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_RCU_CPU_STALL_DETECTOR is not set
+# CONFIG_BACKTRACE_SELF_TEST is not set
+# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
+# CONFIG_FAULT_INJECTION is not set
+# CONFIG_PAGE_POISONING is not set
+CONFIG_TRACING_SUPPORT=y
+CONFIG_FTRACE=y
+# CONFIG_IRQSOFF_TRACER is not set
+# CONFIG_PREEMPT_TRACER is not set
+# CONFIG_SCHED_TRACER is not set
+# CONFIG_ENABLE_DEFAULT_TRACERS is not set
+# CONFIG_BOOT_TRACER is not set
+CONFIG_BRANCH_PROFILE_NONE=y
+# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set
+# CONFIG_PROFILE_ALL_BRANCHES is not set
+# CONFIG_KMEMTRACE is not set
+# CONFIG_WORKQUEUE_TRACER is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_DYNAMIC_DEBUG is not set
+# CONFIG_SAMPLES is not set
+CONFIG_HAVE_ARCH_KGDB=y
+# CONFIG_KGDB is not set
+# CONFIG_KMEMCHECK is not set
+CONFIG_CMDLINE_BOOL=y
+CONFIG_CMDLINE="rw dhash_entries=1024 ihash_entries=1024 ip=10.0.1.3:10.0.1.1:10.0.1.1:255.255.255.0:zeus:eth0: root=/dev/nfs nfsroot=/nfsroot/cramfs,wsize=512,rsize=512,tcp nokgdb console=ttyUSB0,115200 memsize=252M"
+# CONFIG_CMDLINE_OVERRIDE is not set
+# CONFIG_DEBUG_STACK_USAGE is not set
+# CONFIG_RUNTIME_DEBUG is not set
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITYFS is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+CONFIG_CRYPTO=y
+
+#
+# Crypto core or helper
+#
+# CONFIG_CRYPTO_FIPS is not set
+CONFIG_CRYPTO_ALGAPI=y
+CONFIG_CRYPTO_ALGAPI2=y
+CONFIG_CRYPTO_AEAD=y
+CONFIG_CRYPTO_AEAD2=y
+CONFIG_CRYPTO_BLKCIPHER=y
+CONFIG_CRYPTO_BLKCIPHER2=y
+CONFIG_CRYPTO_HASH=y
+CONFIG_CRYPTO_HASH2=y
+CONFIG_CRYPTO_RNG2=y
+CONFIG_CRYPTO_PCOMP=y
+CONFIG_CRYPTO_MANAGER=y
+CONFIG_CRYPTO_MANAGER2=y
+# CONFIG_CRYPTO_GF128MUL is not set
+# CONFIG_CRYPTO_NULL is not set
+CONFIG_CRYPTO_WORKQUEUE=y
+# CONFIG_CRYPTO_CRYPTD is not set
+CONFIG_CRYPTO_AUTHENC=y
+# CONFIG_CRYPTO_TEST is not set
+
+#
+# Authenticated Encryption with Associated Data
+#
+# CONFIG_CRYPTO_CCM is not set
+# CONFIG_CRYPTO_GCM is not set
+# CONFIG_CRYPTO_SEQIV is not set
+
+#
+# Block modes
+#
+CONFIG_CRYPTO_CBC=y
+# CONFIG_CRYPTO_CTR is not set
+# CONFIG_CRYPTO_CTS is not set
+# CONFIG_CRYPTO_ECB is not set
+# CONFIG_CRYPTO_LRW is not set
+# CONFIG_CRYPTO_PCBC is not set
+# CONFIG_CRYPTO_XTS is not set
+
+#
+# Hash modes
+#
+CONFIG_CRYPTO_HMAC=y
+# CONFIG_CRYPTO_XCBC is not set
+
+#
+# Digest
+#
+# CONFIG_CRYPTO_CRC32C is not set
+# CONFIG_CRYPTO_MD4 is not set
+CONFIG_CRYPTO_MD5=y
+# CONFIG_CRYPTO_MICHAEL_MIC is not set
+# CONFIG_CRYPTO_RMD128 is not set
+# CONFIG_CRYPTO_RMD160 is not set
+# CONFIG_CRYPTO_RMD256 is not set
+# CONFIG_CRYPTO_RMD320 is not set
+CONFIG_CRYPTO_SHA1=y
+# CONFIG_CRYPTO_SHA256 is not set
+# CONFIG_CRYPTO_SHA512 is not set
+# CONFIG_CRYPTO_TGR192 is not set
+# CONFIG_CRYPTO_WP512 is not set
+
+#
+# Ciphers
+#
+# CONFIG_CRYPTO_AES is not set
+# CONFIG_CRYPTO_ANUBIS is not set
+# CONFIG_CRYPTO_ARC4 is not set
+# CONFIG_CRYPTO_BLOWFISH is not set
+# CONFIG_CRYPTO_CAMELLIA is not set
+# CONFIG_CRYPTO_CAST5 is not set
+# CONFIG_CRYPTO_CAST6 is not set
+CONFIG_CRYPTO_DES=y
+# CONFIG_CRYPTO_FCRYPT is not set
+# CONFIG_CRYPTO_KHAZAD is not set
+# CONFIG_CRYPTO_SALSA20 is not set
+# CONFIG_CRYPTO_SEED is not set
+# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_TEA is not set
+# CONFIG_CRYPTO_TWOFISH is not set
+
+#
+# Compression
+#
+CONFIG_CRYPTO_DEFLATE=y
+# CONFIG_CRYPTO_ZLIB is not set
+# CONFIG_CRYPTO_LZO is not set
+
+#
+# Random Number Generation
+#
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
+# CONFIG_CRYPTO_HW is not set
+# CONFIG_BINARY_PRINTF is not set
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+CONFIG_GENERIC_FIND_LAST_BIT=y
+# CONFIG_CRC_CCITT is not set
+# CONFIG_CRC16 is not set
+# CONFIG_CRC_T10DIF is not set
+# CONFIG_CRC_ITU_T is not set
+CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
+# CONFIG_LIBCRC32C is not set
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
+CONFIG_NLATTR=y
diff --git a/arch/mips/configs/rb532_defconfig b/arch/mips/configs/rb532_defconfig
index f40c3a04739d..57a50483abdf 100644
--- a/arch/mips/configs/rb532_defconfig
+++ b/arch/mips/configs/rb532_defconfig
@@ -9,7 +9,6 @@ CONFIG_MIPS=y
 # Machine selection
 #
 # CONFIG_MACH_ALCHEMY is not set
-# CONFIG_BASLER_EXCITE is not set
 # CONFIG_BCM47XX is not set
 # CONFIG_MIPS_COBALT is not set
 # CONFIG_MACH_DECSTATION is not set
@@ -1204,7 +1203,7 @@ CONFIG_FRAME_WARN=1024
 # CONFIG_HEADERS_CHECK is not set
 # CONFIG_DEBUG_KERNEL is not set
 # CONFIG_SAMPLES is not set
-CONFIG_CMDLINE=""
+# CONFIG_CMDLINE_BOOL is not set
 
 #
 # Security options
diff --git a/arch/mips/configs/rbtx49xx_defconfig b/arch/mips/configs/rbtx49xx_defconfig
index 6c6a19aebe1f..21c2022d46ee 100644
--- a/arch/mips/configs/rbtx49xx_defconfig
+++ b/arch/mips/configs/rbtx49xx_defconfig
@@ -10,7 +10,6 @@ CONFIG_MIPS=y
 #
 # CONFIG_MACH_ALCHEMY is not set
 # CONFIG_AR7 is not set
-# CONFIG_BASLER_EXCITE is not set
 # CONFIG_BCM47XX is not set
 # CONFIG_BCM63XX is not set
 # CONFIG_MIPS_COBALT is not set
@@ -284,7 +283,6 @@ CONFIG_DEFAULT_AS=y
 # CONFIG_DEFAULT_CFQ is not set
 # CONFIG_DEFAULT_NOOP is not set
 CONFIG_DEFAULT_IOSCHED="anticipatory"
-# CONFIG_PROBE_INITRD_HEADER is not set
 # CONFIG_FREEZER is not set
 
 #
@@ -1063,7 +1061,7 @@ CONFIG_TRACING_SUPPORT=y
 # CONFIG_DYNAMIC_DEBUG is not set
 # CONFIG_SAMPLES is not set
 CONFIG_HAVE_ARCH_KGDB=y
-CONFIG_CMDLINE=""
+# CONFIG_CMDLINE_BOOL is not set
 
 #
 # Security options
diff --git a/arch/mips/configs/rm200_defconfig b/arch/mips/configs/rm200_defconfig
index e53b8d096cfc..790362890033 100644
--- a/arch/mips/configs/rm200_defconfig
+++ b/arch/mips/configs/rm200_defconfig
@@ -22,7 +22,6 @@ CONFIG_ZONE_DMA=y
 # CONFIG_MIPS_DB1550 is not set
 # CONFIG_MIPS_DB1200 is not set
 # CONFIG_MIPS_MIRAGE is not set
-# CONFIG_BASLER_EXCITE is not set
 # CONFIG_MIPS_COBALT is not set
 # CONFIG_MACH_DECSTATION is not set
 # CONFIG_MACH_JAZZ is not set
@@ -1694,7 +1693,7 @@ CONFIG_ENABLE_MUST_CHECK=y
 # CONFIG_DEBUG_KERNEL is not set
 CONFIG_LOG_BUF_SHIFT=14
 CONFIG_CROSSCOMPILE=y
-CONFIG_CMDLINE=""
+# CONFIG_CMDLINE_BOOL is not set
 
 #
 # Security options
diff --git a/arch/mips/configs/sb1250-swarm_defconfig b/arch/mips/configs/sb1250-swarm_defconfig
index 7f38c0b956f3..7f07bf02b838 100644
--- a/arch/mips/configs/sb1250-swarm_defconfig
+++ b/arch/mips/configs/sb1250-swarm_defconfig
@@ -9,7 +9,6 @@ CONFIG_MIPS=y
 # Machine selection
 #
 # CONFIG_MACH_ALCHEMY is not set
-# CONFIG_BASLER_EXCITE is not set
 # CONFIG_BCM47XX is not set
 # CONFIG_MIPS_COBALT is not set
 # CONFIG_MACH_DECSTATION is not set
@@ -961,7 +960,7 @@ CONFIG_ENABLE_MUST_CHECK=y
 # CONFIG_HEADERS_CHECK is not set
 # CONFIG_DEBUG_KERNEL is not set
 # CONFIG_SAMPLES is not set
-CONFIG_CMDLINE=""
+# CONFIG_CMDLINE_BOOL is not set
 # CONFIG_SB1XXX_CORELIS is not set
 
 #
diff --git a/arch/mips/configs/tb0219_defconfig b/arch/mips/configs/tb0219_defconfig
index b5059881bc7e..c54d1128f9a3 100644
--- a/arch/mips/configs/tb0219_defconfig
+++ b/arch/mips/configs/tb0219_defconfig
@@ -9,7 +9,6 @@ CONFIG_MIPS=y
 # Machine selection
 #
 # CONFIG_MACH_ALCHEMY is not set
-# CONFIG_BASLER_EXCITE is not set
 # CONFIG_BCM47XX is not set
 # CONFIG_MIPS_COBALT is not set
 # CONFIG_MACH_DECSTATION is not set
@@ -892,7 +891,9 @@ CONFIG_FRAME_WARN=1024
 # CONFIG_HEADERS_CHECK is not set
 # CONFIG_DEBUG_KERNEL is not set
 # CONFIG_SAMPLES is not set
+CONFIG_CMDLINE_BOOL=y
 CONFIG_CMDLINE="cca=3 mem=64M console=ttyVR0,115200 ip=any root=/dev/nfs"
+# CONFIG_CMDLINE_OVERRIDE is not set
 
 #
 # Security options
diff --git a/arch/mips/configs/tb0226_defconfig b/arch/mips/configs/tb0226_defconfig
index b06a716bf23f..e7c5cd32a2bd 100644
--- a/arch/mips/configs/tb0226_defconfig
+++ b/arch/mips/configs/tb0226_defconfig
@@ -9,7 +9,6 @@ CONFIG_MIPS=y
 # Machine selection
 #
 # CONFIG_MACH_ALCHEMY is not set
-# CONFIG_BASLER_EXCITE is not set
 # CONFIG_BCM47XX is not set
 # CONFIG_MIPS_COBALT is not set
 # CONFIG_MACH_DECSTATION is not set
@@ -895,7 +894,9 @@ CONFIG_FRAME_WARN=1024
 # CONFIG_HEADERS_CHECK is not set
 # CONFIG_DEBUG_KERNEL is not set
 # CONFIG_SAMPLES is not set
+CONFIG_CMDLINE_BOOL=y
 CONFIG_CMDLINE="cca=3 mem=32M console=ttyVR0,115200"
+# CONFIG_CMDLINE_OVERRIDE is not set
 
 #
 # Security options
diff --git a/arch/mips/configs/tb0287_defconfig b/arch/mips/configs/tb0287_defconfig
index 46512cf7ce04..b50032ba4d01 100644
--- a/arch/mips/configs/tb0287_defconfig
+++ b/arch/mips/configs/tb0287_defconfig
@@ -9,7 +9,6 @@ CONFIG_MIPS=y
 # Machine selection
 #
 # CONFIG_MACH_ALCHEMY is not set
-# CONFIG_BASLER_EXCITE is not set
 # CONFIG_BCM47XX is not set
 # CONFIG_MIPS_COBALT is not set
 # CONFIG_MACH_DECSTATION is not set
@@ -1077,7 +1076,9 @@ CONFIG_FRAME_WARN=1024
 # CONFIG_HEADERS_CHECK is not set
 # CONFIG_DEBUG_KERNEL is not set
 # CONFIG_SAMPLES is not set
+CONFIG_CMDLINE_BOOL=y
 CONFIG_CMDLINE="cca=3 mem=64M console=ttyVR0,115200 ip=any root=/dev/nfs"
+# CONFIG_CMDLINE_OVERRIDE is not set
 
 #
 # Security options
diff --git a/arch/mips/configs/workpad_defconfig b/arch/mips/configs/workpad_defconfig
index b437eb7f8672..c02ba08b69ab 100644
--- a/arch/mips/configs/workpad_defconfig
+++ b/arch/mips/configs/workpad_defconfig
@@ -9,7 +9,6 @@ CONFIG_MIPS=y
 # Machine selection
 #
 # CONFIG_MACH_ALCHEMY is not set
-# CONFIG_BASLER_EXCITE is not set
 # CONFIG_MIPS_COBALT is not set
 # CONFIG_MACH_DECSTATION is not set
 # CONFIG_MACH_JAZZ is not set
@@ -755,7 +754,9 @@ CONFIG_ENABLE_MUST_CHECK=y
 # CONFIG_HEADERS_CHECK is not set
 # CONFIG_DEBUG_KERNEL is not set
 CONFIG_CROSSCOMPILE=y
+CONFIG_CMDLINE_BOOL=y
 CONFIG_CMDLINE="console=ttyVR0,19200 ide0=0x170,0x376,49 mem=16M"
+# CONFIG_CMDLINE_OVERRIDE is not set
 
 #
 # Security options
diff --git a/arch/mips/configs/wrppmc_defconfig b/arch/mips/configs/wrppmc_defconfig
index 06acc7482e4c..a35bc41389e5 100644
--- a/arch/mips/configs/wrppmc_defconfig
+++ b/arch/mips/configs/wrppmc_defconfig
@@ -22,7 +22,6 @@ CONFIG_ZONE_DMA=y
 # CONFIG_MIPS_DB1550 is not set
 # CONFIG_MIPS_DB1200 is not set
 # CONFIG_MIPS_MIRAGE is not set
-# CONFIG_BASLER_EXCITE is not set
 # CONFIG_MIPS_COBALT is not set
 # CONFIG_MACH_DECSTATION is not set
 # CONFIG_MACH_JAZZ is not set
@@ -887,7 +886,9 @@ CONFIG_ENABLE_MUST_CHECK=y
 # CONFIG_DEBUG_KERNEL is not set
 CONFIG_LOG_BUF_SHIFT=14
 CONFIG_CROSSCOMPILE=y
+CONFIG_CMDLINE_BOOL=y
 CONFIG_CMDLINE="console=ttyS0,115200n8"
+# CONFIG_CMDLINE_OVERRIDE is not set
 
 #
 # Security options
diff --git a/arch/mips/configs/yosemite_defconfig b/arch/mips/configs/yosemite_defconfig
index 69feaf88b510..e3d68d651e7d 100644
--- a/arch/mips/configs/yosemite_defconfig
+++ b/arch/mips/configs/yosemite_defconfig
@@ -22,7 +22,6 @@ CONFIG_ZONE_DMA=y
 # CONFIG_MIPS_DB1550 is not set
 # CONFIG_MIPS_DB1200 is not set
 # CONFIG_MIPS_MIRAGE is not set
-# CONFIG_BASLER_EXCITE is not set
 # CONFIG_MIPS_COBALT is not set
 # CONFIG_MACH_DECSTATION is not set
 # CONFIG_MACH_JAZZ is not set
@@ -824,7 +823,7 @@ CONFIG_DEBUG_MUTEXES=y
 CONFIG_FORCED_INLINING=y
 # CONFIG_RCU_TORTURE_TEST is not set
 CONFIG_CROSSCOMPILE=y
-CONFIG_CMDLINE=""
+# CONFIG_CMDLINE_BOOL is not set
 # CONFIG_DEBUG_STACK_USAGE is not set
 # CONFIG_RUNTIME_DEBUG is not set
 
diff --git a/arch/mips/fw/arc/cmdline.c b/arch/mips/fw/arc/cmdline.c
index 4ca4eef934a5..5c8603c85f20 100644
--- a/arch/mips/fw/arc/cmdline.c
+++ b/arch/mips/fw/arc/cmdline.c
@@ -16,11 +16,6 @@
 
 #undef DEBUG_CMDLINE
 
-char * __init prom_getcmdline(void)
-{
-        return arcs_cmdline;
-}
-
 static char *ignored[] = {
         "ConsoleIn=",
         "ConsoleOut=",
diff --git a/arch/mips/include/asm/asm-offsets.h b/arch/mips/include/asm/asm-offsets.h
new file mode 100644
index 000000000000..d370ee36a182
--- /dev/null
+++ b/arch/mips/include/asm/asm-offsets.h
@@ -0,0 +1 @@
+#include <generated/asm-offsets.h>
diff --git a/arch/mips/include/asm/bootinfo.h b/arch/mips/include/asm/bootinfo.h
index f5dfaf6a1606..09eee09780f2 100644
--- a/arch/mips/include/asm/bootinfo.h
+++ b/arch/mips/include/asm/bootinfo.h
@@ -67,9 +67,9 @@
 #define MACH_LEMOTE_ML2F7      3
 #define MACH_LEMOTE_YL2F89     4
 #define MACH_DEXXON_GDIUM2F10  5
-#define MACH_LOONGSON_END      6
-
-#define CL_SIZE                 COMMAND_LINE_SIZE
+#define MACH_LEMOTE_NAS        6
+#define MACH_LEMOTE_LL2F       7
+#define MACH_LOONGSON_END      8
 
 extern char *system_type;
 const char *get_system_type(void);
@@ -107,7 +107,7 @@ extern void free_init_pages(const char *what,
 /*
  * Initial kernel command line, usually setup by prom_init()
  */
-extern char arcs_cmdline[CL_SIZE];
+extern char arcs_cmdline[COMMAND_LINE_SIZE];
 
 /*
  * Registers a0, a1, a3 and a4 as passed to the kernel entry by firmware
diff --git a/arch/mips/include/asm/clock.h b/arch/mips/include/asm/clock.h
new file mode 100644
index 000000000000..83894aa7932c
--- /dev/null
+++ b/arch/mips/include/asm/clock.h
@@ -0,0 +1,64 @@
+#ifndef __ASM_MIPS_CLOCK_H
+#define __ASM_MIPS_CLOCK_H
+
+#include <linux/kref.h>
+#include <linux/list.h>
+#include <linux/seq_file.h>
+#include <linux/clk.h>
+
+extern void (*cpu_wait) (void);
+
+struct clk;
+
+struct clk_ops {
+        void (*init) (struct clk *clk);
+        void (*enable) (struct clk *clk);
+        void (*disable) (struct clk *clk);
+        void (*recalc) (struct clk *clk);
+        int (*set_rate) (struct clk *clk, unsigned long rate, int algo_id);
+        long (*round_rate) (struct clk *clk, unsigned long rate);
+};
+
+struct clk {
+        struct list_head node;
+        const char *name;
+        int id;
+        struct module *owner;
+
+        struct clk *parent;
+        struct clk_ops *ops;
+
+        struct kref kref;
+
+        unsigned long rate;
+        unsigned long flags;
+};
+
+#define CLK_ALWAYS_ENABLED      (1 << 0)
+#define CLK_RATE_PROPAGATES     (1 << 1)
+
+/* Should be defined by processor-specific code */
+void arch_init_clk_ops(struct clk_ops **, int type);
+
+int clk_init(void);
+
+int __clk_enable(struct clk *);
+void __clk_disable(struct clk *);
+
+void clk_recalc_rate(struct clk *);
+
+int clk_register(struct clk *);
+void clk_unregister(struct clk *);
+
+/* the exported API, in addition to clk_set_rate */
+/**
+ * clk_set_rate_ex - set the clock rate for a clock source, with additional parameter
+ * @clk: clock source
+ * @rate: desired clock rate in Hz
+ * @algo_id: algorithm id to be passed down to ops->set_rate
+ *
+ * Returns success (0) or negative errno.
+ */
+int clk_set_rate_ex(struct clk *clk, unsigned long rate, int algo_id);
+
+#endif                          /* __ASM_MIPS_CLOCK_H */
diff --git a/arch/mips/include/asm/cop2.h b/arch/mips/include/asm/cop2.h
new file mode 100644
index 000000000000..6b04c98b7fad
--- /dev/null
+++ b/arch/mips/include/asm/cop2.h
@@ -0,0 +1,23 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2009 Wind River Systems,
+ *   written by Ralf Baechle <ralf@linux-mips.org>
+ */
+#ifndef __ASM_COP2_H
+#define __ASM_COP2_H
+
+enum cu2_ops {
+        CU2_EXCEPTION,
+        CU2_LWC2_OP,
+        CU2_LDC2_OP,
+        CU2_SWC2_OP,
+        CU2_SDC2_OP,
+};
+
+extern int register_cu2_notifier(struct notifier_block *nb);
+extern int cu2_notifier_call_chain(unsigned long val, void *v);
+
+#endif /* __ASM_COP2_H */
diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h
index 4b96d1a36056..cf373a95fe4a 100644
--- a/arch/mips/include/asm/cpu.h
+++ b/arch/mips/include/asm/cpu.h
@@ -154,6 +154,8 @@
 #define PRID_REV_VR4181A        0x0070  /* Same as VR4122 */
 #define PRID_REV_VR4130         0x0080
 #define PRID_REV_34K_V1_0_2     0x0022
+#define PRID_REV_LOONGSON2E     0x0002
+#define PRID_REV_LOONGSON2F     0x0003
 
 /*
  * Older processors used to encode processor version and revision in two
diff --git a/arch/mips/include/asm/elf.h b/arch/mips/include/asm/elf.h
index 7990694cda22..7a6a35dbe529 100644
--- a/arch/mips/include/asm/elf.h
+++ b/arch/mips/include/asm/elf.h
@@ -326,7 +326,6 @@ extern int dump_task_fpu(struct task_struct *, elf_fpregset_t *);
 #define ELF_CORE_COPY_FPREGS(tsk, elf_fpregs)                   \
         dump_task_fpu(tsk, elf_fpregs)
 
-#define USE_ELF_CORE_DUMP
 #define ELF_EXEC_PAGESIZE       PAGE_SIZE
 
 /* This yields a mask that user programs can use to figure out what
diff --git a/arch/mips/include/asm/fcntl.h b/arch/mips/include/asm/fcntl.h
index 2a52333a062d..e482fe90fe88 100644
--- a/arch/mips/include/asm/fcntl.h
+++ b/arch/mips/include/asm/fcntl.h
@@ -10,7 +10,7 @@
 
 
 #define O_APPEND        0x0008
-#define O_SYNC          0x0010
+#define O_DSYNC         0x0010  /* used to be O_SYNC, see below */
 #define O_NONBLOCK      0x0080
 #define O_CREAT         0x0100  /* not fcntl */
 #define O_TRUNC         0x0200  /* not fcntl */
@@ -18,6 +18,21 @@
 #define O_NOCTTY        0x0800  /* not fcntl */
 #define FASYNC          0x1000  /* fcntl, for BSD compatibility */
 #define O_LARGEFILE     0x2000  /* allow large file opens */
+/*
+ * Before Linux 2.6.33 only O_DSYNC semantics were implemented, but using
+ * the O_SYNC flag.  We continue to use the existing numerical value
+ * for O_DSYNC semantics now, but using the correct symbolic name for it.
+ * This new value is used to request true Posix O_SYNC semantics.  It is
+ * defined in this strange way to make sure applications compiled against
+ * new headers get at least O_DSYNC semantics on older kernels.
+ *
+ * This has the nice side-effect that we can simply test for O_DSYNC
+ * wherever we do not care if O_DSYNC or O_SYNC is used.
+ *
+ * Note: __O_SYNC must never be used directly.
+ */
+#define __O_SYNC        0x4000
+#define O_SYNC          (__O_SYNC|O_DSYNC)
 #define O_DIRECT        0x8000  /* direct disk access hint */
 
 #define F_GETLK         14
diff --git a/arch/mips/include/asm/fpu.h b/arch/mips/include/asm/fpu.h
index 8a3ef247659a..7fcef8ef3fab 100644
--- a/arch/mips/include/asm/fpu.h
+++ b/arch/mips/include/asm/fpu.h
@@ -28,15 +28,7 @@
 struct sigcontext;
 struct sigcontext32;
 
-extern asmlinkage int (*save_fp_context)(struct sigcontext __user *sc);
-extern asmlinkage int (*restore_fp_context)(struct sigcontext __user *sc);
-
-extern asmlinkage int (*save_fp_context32)(struct sigcontext32 __user *sc);
-extern asmlinkage int (*restore_fp_context32)(struct sigcontext32 __user *sc);
-
 extern void fpu_emulator_init_fpu(void);
-extern int fpu_emulator_save_context(struct sigcontext __user *sc);
-extern int fpu_emulator_restore_context(struct sigcontext __user *sc);
 extern void _init_fpu(void);
 extern void _save_fp(struct task_struct *);
 extern void _restore_fp(struct task_struct *);
diff --git a/arch/mips/include/asm/fpu_emulator.h b/arch/mips/include/asm/fpu_emulator.h
index e5189572956c..aecada6f6117 100644
--- a/arch/mips/include/asm/fpu_emulator.h
+++ b/arch/mips/include/asm/fpu_emulator.h
@@ -25,17 +25,27 @@
 
 #include <asm/break.h>
 #include <asm/inst.h>
+#include <asm/local.h>
+
+#ifdef CONFIG_DEBUG_FS
 
 struct mips_fpu_emulator_stats {
-        unsigned int emulated;
-        unsigned int loads;
-        unsigned int stores;
-        unsigned int cp1ops;
-        unsigned int cp1xops;
-        unsigned int errors;
+        local_t emulated;
+        local_t loads;
+        local_t stores;
+        local_t cp1ops;
+        local_t cp1xops;
+        local_t errors;
 };
 
-extern struct mips_fpu_emulator_stats fpuemustats;
+DECLARE_PER_CPU(struct mips_fpu_emulator_stats, fpuemustats);
+
+#define MIPS_FPU_EMU_INC_STATS(M)                                       \
+        cpu_local_wrap(__local_inc(&__get_cpu_var(fpuemustats).M))
+
+#else
+#define MIPS_FPU_EMU_INC_STATS(M) do { } while (0)
+#endif /* CONFIG_DEBUG_FS */
 
 extern int mips_dsemul(struct pt_regs *regs, mips_instruction ir,
         unsigned long cpc);
diff --git a/arch/mips/include/asm/ftrace.h b/arch/mips/include/asm/ftrace.h
index 40a8c178f10d..3986cd8704f3 100644
--- a/arch/mips/include/asm/ftrace.h
+++ b/arch/mips/include/asm/ftrace.h
@@ -1 +1,90 @@
-/* empty */
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive for
+ * more details.
+ *
+ * Copyright (C) 2009 DSLab, Lanzhou University, China
+ * Author: Wu Zhangjin <wuzj@lemote.com>
+ */
+
+#ifndef _ASM_MIPS_FTRACE_H
+#define _ASM_MIPS_FTRACE_H
+
+#ifdef CONFIG_FUNCTION_TRACER
+
+#define MCOUNT_ADDR ((unsigned long)(_mcount))
+#define MCOUNT_INSN_SIZE 4              /* sizeof mcount call */
+
+#ifndef __ASSEMBLY__
+extern void _mcount(void);
+#define mcount _mcount
+
+#define safe_load(load, src, dst, error)                \
+do {                                                    \
+        asm volatile (                                  \
+                "1: " load " %[" STR(dst) "], 0(%[" STR(src) "])\n"\
+                "   li %[" STR(error) "], 0\n"          \
+                "2:\n"                                  \
+                                                        \
+                ".section .fixup, \"ax\"\n"             \
+                "3: li %[" STR(error) "], 1\n"          \
+                "   j 2b\n"                             \
+                ".previous\n"                           \
+                                                        \
+                ".section\t__ex_table,\"a\"\n\t"        \
+                STR(PTR) "\t1b, 3b\n\t"                 \
+                ".previous\n"                           \
+                                                        \
+                : [dst] "=&r" (dst), [error] "=r" (error)\
+                : [src] "r" (src)                       \
+                : "memory"                              \
+        );                                              \
+} while (0)
+
+#define safe_store(store, src, dst, error)      \
+do {                                            \
+        asm volatile (                          \
+                "1: " store " %[" STR(src) "], 0(%[" STR(dst) "])\n"\
+                "   li %[" STR(error) "], 0\n"  \
+                "2:\n"                          \
+                                                \
+                ".section .fixup, \"ax\"\n"     \
+                "3: li %[" STR(error) "], 1\n"  \
+                "   j 2b\n"                     \
+                ".previous\n"                   \
+                                                \
+                ".section\t__ex_table,\"a\"\n\t"\
+                STR(PTR) "\t1b, 3b\n\t"         \
+                ".previous\n"                   \
+                                                \
+                : [error] "=r" (error)          \
+                : [dst] "r" (dst), [src] "r" (src)\
+                : "memory"                      \
+        );                                      \
+} while (0)
+
+#define safe_load_code(dst, src, error) \
+        safe_load(STR(lw), src, dst, error)
+#define safe_store_code(src, dst, error) \
+        safe_store(STR(sw), src, dst, error)
+
+#define safe_load_stack(dst, src, error) \
+        safe_load(STR(PTR_L), src, dst, error)
+
+#define safe_store_stack(src, dst, error) \
+        safe_store(STR(PTR_S), src, dst, error)
+
+
+#ifdef CONFIG_DYNAMIC_FTRACE
+static inline unsigned long ftrace_call_adjust(unsigned long addr)
+{
+        return addr;
+}
+
+struct dyn_arch_ftrace {
+};
+
+#endif /*  CONFIG_DYNAMIC_FTRACE */
+#endif /* __ASSEMBLY__ */
+#endif /* CONFIG_FUNCTION_TRACER */
+#endif /* _ASM_MIPS_FTRACE_H */
diff --git a/arch/mips/include/asm/irq.h b/arch/mips/include/asm/irq.h
index 09b08d05ff72..06960364c96b 100644
--- a/arch/mips/include/asm/irq.h
+++ b/arch/mips/include/asm/irq.h
@@ -113,36 +113,11 @@ do {									\
 
 #endif
 
-/*
- * do_IRQ handles all normal device IRQ's (the special
- * SMP cross-CPU interrupts have their own specific
- * handlers).
- *
- * Ideally there should be away to get this into kernel/irq/handle.c to
- * avoid the overhead of a call for just a tiny function ...
- */
-#define do_IRQ(irq)                                                     \
-do {                                                                    \
-        irq_enter();                                                    \
-        __DO_IRQ_SMTC_HOOK(irq);                                        \
-        generic_handle_irq(irq);                                        \
-        irq_exit();                                                     \
-} while (0)
+extern void do_IRQ(unsigned int irq);
 
 #ifdef CONFIG_MIPS_MT_SMTC_IRQAFF
-/*
- * To avoid inefficient and in some cases pathological re-checking of
- * IRQ affinity, we have this variant that skips the affinity check.
- */
-
 
-#define do_IRQ_no_affinity(irq)                                         \
-do {                                                                    \
-        irq_enter();                                                    \
-        __NO_AFFINITY_IRQ_SMTC_HOOK(irq);                               \
-        generic_handle_irq(irq);                                        \
-        irq_exit();                                                     \
-} while (0)
+extern void do_IRQ_no_affinity(unsigned int irq);
 
 #endif /* CONFIG_MIPS_MT_SMTC_IRQAFF */
 
diff --git a/arch/mips/include/asm/mach-excite/cpu-feature-overrides.h b/arch/mips/include/asm/mach-excite/cpu-feature-overrides.h
deleted file mode 100644
index 107104c3cd12..000000000000
--- a/arch/mips/include/asm/mach-excite/cpu-feature-overrides.h
+++ /dev/null
@@ -1,48 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2004 Thomas Koeller <thomas.koeller@baslerweb.com>
- * Copyright (C) 2007 Ralf Baechle (ralf@linux-mips.org)
- */
-#ifndef __ASM_MACH_EXCITE_CPU_FEATURE_OVERRIDES_H
-#define __ASM_MACH_EXCITE_CPU_FEATURE_OVERRIDES_H
-
-/*
- * Basler eXcite has an RM9122 processor.
- */
-#define cpu_has_watch           1
-#define cpu_has_mips16          0
-#define cpu_has_divec           0
-#define cpu_has_vce             0
-#define cpu_has_cache_cdex_p    0
-#define cpu_has_cache_cdex_s    0
-#define cpu_has_prefetch        1
-#define cpu_has_mcheck          0
-#define cpu_has_ejtag           0
-
-#define cpu_has_llsc            1
-#define cpu_has_vtag_icache     0
-#define cpu_has_dc_aliases      0
-#define cpu_has_ic_fills_f_dc   0
-#define cpu_has_dsp             0
-#define cpu_icache_snoops_remote_store  0
-#define cpu_has_mipsmt          0
-#define cpu_has_userlocal       0
-
-#define cpu_has_nofpuex         0
-#define cpu_has_64bits          1
-
-#define cpu_has_mips32r1        0
-#define cpu_has_mips32r2        0
-#define cpu_has_mips64r1        0
-#define cpu_has_mips64r2        0
-
-#define cpu_has_inclusive_pcaches       0
-
-#define cpu_dcache_line_size()  32
-#define cpu_icache_line_size()  32
-#define cpu_scache_line_size()  32
-
-#endif /* __ASM_MACH_EXCITE_CPU_FEATURE_OVERRIDES_H */
diff --git a/arch/mips/include/asm/mach-excite/excite.h b/arch/mips/include/asm/mach-excite/excite.h
deleted file mode 100644
index 4c29ba44992c..000000000000
--- a/arch/mips/include/asm/mach-excite/excite.h
+++ /dev/null
@@ -1,154 +0,0 @@
-#ifndef __EXCITE_H__
-#define __EXCITE_H__
-
-#include <linux/init.h>
-#include <asm/addrspace.h>
-#include <asm/types.h>
-
-#define EXCITE_CPU_EXT_CLOCK 100000000
-
-#if !defined(__ASSEMBLY__)
-void __init excite_kgdb_init(void);
-void excite_procfs_init(void);
-extern unsigned long memsize;
-extern char modetty[];
-extern u32 unit_id;
-#endif
-
-/* Base name for XICAP devices */
-#define XICAP_NAME      "xicap_gpi"
-
-/* OCD register offsets */
-#define LKB0            0x0038
-#define LKB5            0x0128
-#define LKM5            0x012C
-#define LKB7            0x0138
-#define LKM7            0x013c
-#define LKB8            0x0140
-#define LKM8            0x0144
-#define LKB9            0x0148
-#define LKM9            0x014c
-#define LKB10           0x0150
-#define LKM10           0x0154
-#define LKB11           0x0158
-#define LKM11           0x015c
-#define LKB12           0x0160
-#define LKM12           0x0164
-#define LKB13           0x0168
-#define LKM13           0x016c
-#define LDP0            0x0200
-#define LDP1            0x0210
-#define LDP2            0x0220
-#define LDP3            0x0230
-#define INTPIN0         0x0A40
-#define INTPIN1         0x0A44
-#define INTPIN2         0x0A48
-#define INTPIN3         0x0A4C
-#define INTPIN4         0x0A50
-#define INTPIN5         0x0A54
-#define INTPIN6         0x0A58
-#define INTPIN7         0x0A5C
-
-
-
-
-/* TITAN register offsets */
-#define CPRR            0x0004
-#define CPDSR           0x0008
-#define CPTC0R          0x000c
-#define CPTC1R          0x0010
-#define CPCFG0          0x0020
-#define CPCFG1          0x0024
-#define CPDST0A         0x0028
-#define CPDST0B         0x002c
-#define CPDST1A         0x0030
-#define CPDST1B         0x0034
-#define CPXDSTA         0x0038
-#define CPXDSTB         0x003c
-#define CPXCISRA        0x0048
-#define CPXCISRB        0x004c
-#define CPGIG0ER        0x0050
-#define CPGIG1ER        0x0054
-#define CPGRWL          0x0068
-#define CPURSLMT        0x00f8
-#define UACFG           0x0200
-#define UAINTS          0x0204
-#define SDRXFCIE        0x4828
-#define SDTXFCIE        0x4928
-#define INTP0Status0    0x1B00
-#define INTP0Mask0      0x1B04
-#define INTP0Set0       0x1B08
-#define INTP0Clear0     0x1B0C
-#define GXCFG           0x5000
-#define GXDMADRPFX      0x5018
-#define GXDMA_DESCADR   0x501c
-#define GXCH0TDESSTRT   0x5054
-
-/* IRQ definitions */
-#define NMICONFIG               0xac0
-#define TITAN_MSGINT    0xc4
-#define TITAN_IRQ       ((TITAN_MSGINT / 0x20) + 2)
-#define FPGA0_MSGINT    0x5a
-#define FPGA0_IRQ       ((FPGA0_MSGINT / 0x20) + 2)
-#define FPGA1_MSGINT    0x7b
-#define FPGA1_IRQ       ((FPGA1_MSGINT / 0x20) + 2)
-#define PHY_MSGINT      0x9c
-#define PHY_IRQ         ((PHY_MSGINT   / 0x20) + 2)
-
-#if defined(CONFIG_BASLER_EXCITE_PROTOTYPE)
-/* Pre-release units used interrupt pin #9 */
-#define USB_IRQ         11
-#else
-/* Re-designed units use interrupt pin #1 */
-#define USB_MSGINT      0x39
-#define USB_IRQ         ((USB_MSGINT / 0x20) + 2)
-#endif
-#define TIMER_IRQ       12
-
-
-/* Device address ranges */
-#define EXCITE_OFFS_OCD         0x1fffc000
-#define EXCITE_SIZE_OCD         (16 * 1024)
-#define EXCITE_PHYS_OCD         CPHYSADDR(EXCITE_OFFS_OCD)
-#define EXCITE_ADDR_OCD         CKSEG1ADDR(EXCITE_OFFS_OCD)
-
-#define EXCITE_OFFS_SCRAM       0x1fffa000
-#define EXCITE_SIZE_SCRAM       (8 << 10)
-#define EXCITE_PHYS_SCRAM       CPHYSADDR(EXCITE_OFFS_SCRAM)
-#define EXCITE_ADDR_SCRAM       CKSEG1ADDR(EXCITE_OFFS_SCRAM)
-
-#define EXCITE_OFFS_PCI_IO      0x1fff8000
-#define EXCITE_SIZE_PCI_IO      (8 << 10)
-#define EXCITE_PHYS_PCI_IO      CPHYSADDR(EXCITE_OFFS_PCI_IO)
-#define EXCITE_ADDR_PCI_IO      CKSEG1ADDR(EXCITE_OFFS_PCI_IO)
-
-#define EXCITE_OFFS_TITAN       0x1fff0000
-#define EXCITE_SIZE_TITAN       (32 << 10)
-#define EXCITE_PHYS_TITAN       CPHYSADDR(EXCITE_OFFS_TITAN)
-#define EXCITE_ADDR_TITAN       CKSEG1ADDR(EXCITE_OFFS_TITAN)
-
-#define EXCITE_OFFS_PCI_MEM     0x1ffe0000
-#define EXCITE_SIZE_PCI_MEM     (64 << 10)
-#define EXCITE_PHYS_PCI_MEM     CPHYSADDR(EXCITE_OFFS_PCI_MEM)
-#define EXCITE_ADDR_PCI_MEM     CKSEG1ADDR(EXCITE_OFFS_PCI_MEM)
-
-#define EXCITE_OFFS_FPGA        0x1ffdc000
-#define EXCITE_SIZE_FPGA        (16 << 10)
-#define EXCITE_PHYS_FPGA        CPHYSADDR(EXCITE_OFFS_FPGA)
-#define EXCITE_ADDR_FPGA        CKSEG1ADDR(EXCITE_OFFS_FPGA)
-
-#define EXCITE_OFFS_NAND        0x1ffd8000
-#define EXCITE_SIZE_NAND        (16 << 10)
-#define EXCITE_PHYS_NAND        CPHYSADDR(EXCITE_OFFS_NAND)
-#define EXCITE_ADDR_NAND        CKSEG1ADDR(EXCITE_OFFS_NAND)
-
-#define EXCITE_OFFS_BOOTROM     0x1f000000
-#define EXCITE_SIZE_BOOTROM     (8 << 20)
-#define EXCITE_PHYS_BOOTROM     CPHYSADDR(EXCITE_OFFS_BOOTROM)
-#define EXCITE_ADDR_BOOTROM     CKSEG1ADDR(EXCITE_OFFS_BOOTROM)
-
-/* FPGA address offsets */
-#define EXCITE_FPGA_DPR         0x0104  /* dual-ported ram */
-#define EXCITE_FPGA_SYSCTL      0x0200  /* system control register block */
-
-#endif /* __EXCITE_H__ */
diff --git a/arch/mips/include/asm/mach-excite/excite_fpga.h b/arch/mips/include/asm/mach-excite/excite_fpga.h
deleted file mode 100644
index 0a1ef69bece7..000000000000
--- a/arch/mips/include/asm/mach-excite/excite_fpga.h
+++ /dev/null
@@ -1,80 +0,0 @@
-#ifndef EXCITE_FPGA_H_INCLUDED
-#define EXCITE_FPGA_H_INCLUDED
-
-
-/**
- * Address alignment of the individual FPGA bytes.
- * The address arrangement of the individual bytes of the FPGA is two
- * byte aligned at the embedded MK2 platform.
- */
-#ifdef EXCITE_CCI_FPGA_MK2
-typedef unsigned char excite_cci_fpga_align_t __attribute__ ((aligned(2)));
-#else
-typedef unsigned char excite_cci_fpga_align_t;
-#endif
-
-
-/**
- * Size of Dual Ported RAM.
- */
-#define EXCITE_DPR_SIZE 263
-
-
-/**
- * Size of Reserved Status Fields in Dual Ported RAM.
- */
-#define EXCITE_DPR_STATUS_SIZE 7
-
-
-
-/**
- * FPGA.
- * Hardware register layout of the FPGA interface. The FPGA must accessed
- * byte wise solely.
- * @see EXCITE_CCI_DPR_MK2
- */
-typedef struct excite_fpga {
-
-        /**
-         * Dual Ported RAM.
-         */
-        excite_cci_fpga_align_t dpr[EXCITE_DPR_SIZE];
-
-        /**
-         * Status.
-         */
-        excite_cci_fpga_align_t status[EXCITE_DPR_STATUS_SIZE];
-
-#ifdef EXCITE_CCI_FPGA_MK2
-        /**
-         * RM9000 Interrupt.
-         * Write access initiates interrupt at the RM9000 (MIPS) processor of the eXcite.
-         */
-        excite_cci_fpga_align_t rm9k_int;
-#else
-        /**
-         * MK2 Interrupt.
-         * Write access initiates interrupt at the ARM processor of the MK2.
-         */
-        excite_cci_fpga_align_t mk2_int;
-
-        excite_cci_fpga_align_t gap[0x1000-0x10f];
-
-        /**
-         * IRQ Source/Acknowledge.
-         */
-        excite_cci_fpga_align_t rm9k_irq_src;
-
-        /**
-         * IRQ Mask.
-         * Set bits enable the related interrupt.
-         */
-        excite_cci_fpga_align_t rm9k_irq_mask;
-#endif
-
-
-} excite_fpga;
-
-
-
-#endif  /* ndef EXCITE_FPGA_H_INCLUDED */
diff --git a/arch/mips/include/asm/mach-excite/excite_nandflash.h b/arch/mips/include/asm/mach-excite/excite_nandflash.h
deleted file mode 100644
index c4cf6140622e..000000000000
--- a/arch/mips/include/asm/mach-excite/excite_nandflash.h
+++ /dev/null
@@ -1,7 +0,0 @@
-#ifndef __EXCITE_NANDFLASH_H__
-#define __EXCITE_NANDFLASH_H__
-
-/* Resource names */
-#define EXCITE_NANDFLASH_RESOURCE_REGS  "excite_nandflash_regs"
-
-#endif /* __EXCITE_NANDFLASH_H__ */
diff --git a/arch/mips/include/asm/mach-excite/rm9k_eth.h b/arch/mips/include/asm/mach-excite/rm9k_eth.h
deleted file mode 100644
index 94705a46f72e..000000000000
--- a/arch/mips/include/asm/mach-excite/rm9k_eth.h
+++ /dev/null
@@ -1,23 +0,0 @@
-#if !defined(__RM9K_ETH_H__)
-#define __RM9K_ETH_H__
-
-#define RM9K_GE_NAME                    "rm9k_ge"
-
-/* Resource names */
-#define RM9K_GE_RESOURCE_MAC            "rm9k_ge_mac"
-#define RM9K_GE_RESOURCE_MSTAT          "rm9k_ge_mstat"
-#define RM9K_GE_RESOURCE_PKTPROC        "rm9k_ge_pktproc"
-#define RM9K_GE_RESOURCE_XDMA           "rm9k_ge_xdma"
-#define RM9K_GE_RESOURCE_FIFO_RX        "rm9k_ge_fifo_rx"
-#define RM9K_GE_RESOURCE_FIFO_TX        "rm9k_ge_fifo_tx"
-#define RM9K_GE_RESOURCE_FIFOMEM_RX     "rm9k_ge_fifo_memory_rx"
-#define RM9K_GE_RESOURCE_FIFOMEM_TX     "rm9k_ge_fifo_memory_tx"
-#define RM9K_GE_RESOURCE_PHY            "rm9k_ge_phy"
-#define RM9K_GE_RESOURCE_DMADESC_RX     "rm9k_ge_dmadesc_rx"
-#define RM9K_GE_RESOURCE_DMADESC_TX     "rm9k_ge_dmadesc_tx"
-#define RM9K_GE_RESOURCE_IRQ_MAIN       "rm9k_ge_irq_main"
-#define RM9K_GE_RESOURCE_IRQ_PHY        "rm9k_ge_irq_phy"
-#define RM9K_GE_RESOURCE_GPI_SLICE      "rm9k_ge_gpi_slice"
-#define RM9K_GE_RESOURCE_MDIO_CHANNEL   "rm9k_ge_mdio_channel"
-
-#endif /* !defined(__RM9K_ETH_H__) */
diff --git a/arch/mips/include/asm/mach-excite/rm9k_wdt.h b/arch/mips/include/asm/mach-excite/rm9k_wdt.h
deleted file mode 100644
index 3fa3c08d2da7..000000000000
--- a/arch/mips/include/asm/mach-excite/rm9k_wdt.h
+++ /dev/null
@@ -1,12 +0,0 @@
-#ifndef __RM9K_WDT_H__
-#define __RM9K_WDT_H__
-
-/* Device name */
-#define WDT_NAME                "wdt_gpi"
-
-/* Resource names */
-#define WDT_RESOURCE_REGS       "excite_watchdog_regs"
-#define WDT_RESOURCE_IRQ        "excite_watchdog_irq"
-#define WDT_RESOURCE_COUNTER    "excite_watchdog_counter"
-
-#endif /* __RM9K_WDT_H__ */
diff --git a/arch/mips/include/asm/mach-excite/rm9k_xicap.h b/arch/mips/include/asm/mach-excite/rm9k_xicap.h
deleted file mode 100644
index 009577734a8d..000000000000
--- a/arch/mips/include/asm/mach-excite/rm9k_xicap.h
+++ /dev/null
@@ -1,16 +0,0 @@
-#ifndef __EXCITE_XICAP_H__
-#define __EXCITE_XICAP_H__
-
-
-/* Resource names */
-#define XICAP_RESOURCE_FIFO_RX          "xicap_fifo_rx"
-#define XICAP_RESOURCE_FIFO_TX          "xicap_fifo_tx"
-#define XICAP_RESOURCE_XDMA             "xicap_xdma"
-#define XICAP_RESOURCE_DMADESC          "xicap_dmadesc"
-#define XICAP_RESOURCE_PKTPROC          "xicap_pktproc"
-#define XICAP_RESOURCE_IRQ              "xicap_irq"
-#define XICAP_RESOURCE_GPI_SLICE        "xicap_gpi_slice"
-#define XICAP_RESOURCE_FIFO_BLK         "xicap_fifo_blocks"
-#define XICAP_RESOURCE_PKT_STREAM       "xicap_pkt_stream"
-
-#endif /* __EXCITE_XICAP_H__ */
diff --git a/arch/mips/include/asm/mach-loongson/cs5536/cs5536.h b/arch/mips/include/asm/mach-loongson/cs5536/cs5536.h
new file mode 100644
index 000000000000..021f77ca59ec
--- /dev/null
+++ b/arch/mips/include/asm/mach-loongson/cs5536/cs5536.h
@@ -0,0 +1,305 @@
+/*
+ * The header file of cs5536 sourth bridge.
+ *
+ * Copyright (C) 2007 Lemote, Inc.
+ * Author : jlliu <liujl@lemote.com>
+ */
+
+#ifndef _CS5536_H
+#define _CS5536_H
+
+#include <linux/types.h>
+
+extern void _rdmsr(u32 msr, u32 *hi, u32 *lo);
+extern void _wrmsr(u32 msr, u32 hi, u32 lo);
+
+/*
+ * MSR module base
+ */
+#define CS5536_SB_MSR_BASE      (0x00000000)
+#define CS5536_GLIU_MSR_BASE    (0x10000000)
+#define CS5536_ILLEGAL_MSR_BASE (0x20000000)
+#define CS5536_USB_MSR_BASE     (0x40000000)
+#define CS5536_IDE_MSR_BASE     (0x60000000)
+#define CS5536_DIVIL_MSR_BASE   (0x80000000)
+#define CS5536_ACC_MSR_BASE     (0xa0000000)
+#define CS5536_UNUSED_MSR_BASE  (0xc0000000)
+#define CS5536_GLCP_MSR_BASE    (0xe0000000)
+
+#define SB_MSR_REG(offset)      (CS5536_SB_MSR_BASE     | (offset))
+#define GLIU_MSR_REG(offset)    (CS5536_GLIU_MSR_BASE   | (offset))
+#define ILLEGAL_MSR_REG(offset) (CS5536_ILLEGAL_MSR_BASE | (offset))
+#define USB_MSR_REG(offset)     (CS5536_USB_MSR_BASE    | (offset))
+#define IDE_MSR_REG(offset)     (CS5536_IDE_MSR_BASE    | (offset))
+#define DIVIL_MSR_REG(offset)   (CS5536_DIVIL_MSR_BASE  | (offset))
+#define ACC_MSR_REG(offset)     (CS5536_ACC_MSR_BASE    | (offset))
+#define UNUSED_MSR_REG(offset)  (CS5536_UNUSED_MSR_BASE | (offset))
+#define GLCP_MSR_REG(offset)    (CS5536_GLCP_MSR_BASE   | (offset))
+
+/*
+ * BAR SPACE OF VIRTUAL PCI :
+ * range for pci probe use, length is the actual size.
+ */
+/* IO space for all DIVIL modules */
+#define CS5536_IRQ_RANGE        0xffffffe0 /* USERD FOR PCI PROBE */
+#define CS5536_IRQ_LENGTH       0x20    /* THE REGS ACTUAL LENGTH */
+#define CS5536_SMB_RANGE        0xfffffff8
+#define CS5536_SMB_LENGTH       0x08
+#define CS5536_GPIO_RANGE       0xffffff00
+#define CS5536_GPIO_LENGTH      0x100
+#define CS5536_MFGPT_RANGE      0xffffffc0
+#define CS5536_MFGPT_LENGTH     0x40
+#define CS5536_ACPI_RANGE       0xffffffe0
+#define CS5536_ACPI_LENGTH      0x20
+#define CS5536_PMS_RANGE        0xffffff80
+#define CS5536_PMS_LENGTH       0x80
+/* IO space for IDE */
+#define CS5536_IDE_RANGE        0xfffffff0
+#define CS5536_IDE_LENGTH       0x10
+/* IO space for ACC */
+#define CS5536_ACC_RANGE        0xffffff80
+#define CS5536_ACC_LENGTH       0x80
+/* MEM space for ALL USB modules */
+#define CS5536_OHCI_RANGE       0xfffff000
+#define CS5536_OHCI_LENGTH      0x1000
+#define CS5536_EHCI_RANGE       0xfffff000
+#define CS5536_EHCI_LENGTH      0x1000
+
+/*
+ * PCI MSR ACCESS
+ */
+#define PCI_MSR_CTRL            0xF0
+#define PCI_MSR_ADDR            0xF4
+#define PCI_MSR_DATA_LO         0xF8
+#define PCI_MSR_DATA_HI         0xFC
+
+/**************** MSR *****************************/
+
+/*
+ * GLIU STANDARD MSR
+ */
+#define GLIU_CAP                0x00
+#define GLIU_CONFIG             0x01
+#define GLIU_SMI                0x02
+#define GLIU_ERROR              0x03
+#define GLIU_PM                 0x04
+#define GLIU_DIAG               0x05
+
+/*
+ * GLIU SPEC. MSR
+ */
+#define GLIU_P2D_BM0            0x20
+#define GLIU_P2D_BM1            0x21
+#define GLIU_P2D_BM2            0x22
+#define GLIU_P2D_BMK0           0x23
+#define GLIU_P2D_BMK1           0x24
+#define GLIU_P2D_BM3            0x25
+#define GLIU_P2D_BM4            0x26
+#define GLIU_COH                0x80
+#define GLIU_PAE                0x81
+#define GLIU_ARB                0x82
+#define GLIU_ASMI               0x83
+#define GLIU_AERR               0x84
+#define GLIU_DEBUG              0x85
+#define GLIU_PHY_CAP            0x86
+#define GLIU_NOUT_RESP          0x87
+#define GLIU_NOUT_WDATA         0x88
+#define GLIU_WHOAMI             0x8B
+#define GLIU_SLV_DIS            0x8C
+#define GLIU_IOD_BM0            0xE0
+#define GLIU_IOD_BM1            0xE1
+#define GLIU_IOD_BM2            0xE2
+#define GLIU_IOD_BM3            0xE3
+#define GLIU_IOD_BM4            0xE4
+#define GLIU_IOD_BM5            0xE5
+#define GLIU_IOD_BM6            0xE6
+#define GLIU_IOD_BM7            0xE7
+#define GLIU_IOD_BM8            0xE8
+#define GLIU_IOD_BM9            0xE9
+#define GLIU_IOD_SC0            0xEA
+#define GLIU_IOD_SC1            0xEB
+#define GLIU_IOD_SC2            0xEC
+#define GLIU_IOD_SC3            0xED
+#define GLIU_IOD_SC4            0xEE
+#define GLIU_IOD_SC5            0xEF
+#define GLIU_IOD_SC6            0xF0
+#define GLIU_IOD_SC7            0xF1
+
+/*
+ * SB STANDARD
+ */
+#define SB_CAP          0x00
+#define SB_CONFIG       0x01
+#define SB_SMI          0x02
+#define SB_ERROR        0x03
+#define SB_MAR_ERR_EN           0x00000001
+#define SB_TAR_ERR_EN           0x00000002
+#define SB_RSVD_BIT1            0x00000004
+#define SB_EXCEP_ERR_EN         0x00000008
+#define SB_SYSE_ERR_EN          0x00000010
+#define SB_PARE_ERR_EN          0x00000020
+#define SB_TAS_ERR_EN           0x00000040
+#define SB_MAR_ERR_FLAG         0x00010000
+#define SB_TAR_ERR_FLAG         0x00020000
+#define SB_RSVD_BIT2            0x00040000
+#define SB_EXCEP_ERR_FLAG       0x00080000
+#define SB_SYSE_ERR_FLAG        0x00100000
+#define SB_PARE_ERR_FLAG        0x00200000
+#define SB_TAS_ERR_FLAG         0x00400000
+#define SB_PM           0x04
+#define SB_DIAG         0x05
+
+/*
+ * SB SPEC.
+ */
+#define SB_CTRL         0x10
+#define SB_R0           0x20
+#define SB_R1           0x21
+#define SB_R2           0x22
+#define SB_R3           0x23
+#define SB_R4           0x24
+#define SB_R5           0x25
+#define SB_R6           0x26
+#define SB_R7           0x27
+#define SB_R8           0x28
+#define SB_R9           0x29
+#define SB_R10          0x2A
+#define SB_R11          0x2B
+#define SB_R12          0x2C
+#define SB_R13          0x2D
+#define SB_R14          0x2E
+#define SB_R15          0x2F
+
+/*
+ * GLCP STANDARD
+ */
+#define GLCP_CAP                0x00
+#define GLCP_CONFIG             0x01
+#define GLCP_SMI                0x02
+#define GLCP_ERROR              0x03
+#define GLCP_PM                 0x04
+#define GLCP_DIAG               0x05
+
+/*
+ * GLCP SPEC.
+ */
+#define GLCP_CLK_DIS_DELAY      0x08
+#define GLCP_PM_CLK_DISABLE     0x09
+#define GLCP_GLB_PM             0x0B
+#define GLCP_DBG_OUT            0x0C
+#define GLCP_RSVD1              0x0D
+#define GLCP_SOFT_COM           0x0E
+#define SOFT_BAR_SMB_FLAG       0x00000001
+#define SOFT_BAR_GPIO_FLAG      0x00000002
+#define SOFT_BAR_MFGPT_FLAG     0x00000004
+#define SOFT_BAR_IRQ_FLAG       0x00000008
+#define SOFT_BAR_PMS_FLAG       0x00000010
+#define SOFT_BAR_ACPI_FLAG      0x00000020
+#define SOFT_BAR_IDE_FLAG       0x00000400
+#define SOFT_BAR_ACC_FLAG       0x00000800
+#define SOFT_BAR_OHCI_FLAG      0x00001000
+#define SOFT_BAR_EHCI_FLAG      0x00002000
+#define GLCP_RSVD2              0x0F
+#define GLCP_CLK_OFF            0x10
+#define GLCP_CLK_ACTIVE         0x11
+#define GLCP_CLK_DISABLE        0x12
+#define GLCP_CLK4ACK            0x13
+#define GLCP_SYS_RST            0x14
+#define GLCP_RSVD3              0x15
+#define GLCP_DBG_CLK_CTRL       0x16
+#define GLCP_CHIP_REV_ID        0x17
+
+/* PIC */
+#define PIC_YSEL_LOW            0x20
+#define PIC_YSEL_LOW_USB_SHIFT          8
+#define PIC_YSEL_LOW_ACC_SHIFT          16
+#define PIC_YSEL_LOW_FLASH_SHIFT        24
+#define PIC_YSEL_HIGH           0x21
+#define PIC_ZSEL_LOW            0x22
+#define PIC_ZSEL_HIGH           0x23
+#define PIC_IRQM_PRIM           0x24
+#define PIC_IRQM_LPC            0x25
+#define PIC_XIRR_STS_LOW        0x26
+#define PIC_XIRR_STS_HIGH       0x27
+#define PCI_SHDW                0x34
+
+/*
+ * DIVIL STANDARD
+ */
+#define DIVIL_CAP               0x00
+#define DIVIL_CONFIG            0x01
+#define DIVIL_SMI               0x02
+#define DIVIL_ERROR             0x03
+#define DIVIL_PM                0x04
+#define DIVIL_DIAG              0x05
+
+/*
+ * DIVIL SPEC.
+ */
+#define DIVIL_LBAR_IRQ          0x08
+#define DIVIL_LBAR_KEL          0x09
+#define DIVIL_LBAR_SMB          0x0B
+#define DIVIL_LBAR_GPIO         0x0C
+#define DIVIL_LBAR_MFGPT        0x0D
+#define DIVIL_LBAR_ACPI         0x0E
+#define DIVIL_LBAR_PMS          0x0F
+#define DIVIL_LEG_IO            0x14
+#define DIVIL_BALL_OPTS         0x15
+#define DIVIL_SOFT_IRQ          0x16
+#define DIVIL_SOFT_RESET        0x17
+
+/* MFGPT */
+#define MFGPT_IRQ       0x28
+
+/*
+ * IDE STANDARD
+ */
+#define IDE_CAP         0x00
+#define IDE_CONFIG      0x01
+#define IDE_SMI         0x02
+#define IDE_ERROR       0x03
+#define IDE_PM          0x04
+#define IDE_DIAG        0x05
+
+/*
+ * IDE SPEC.
+ */
+#define IDE_IO_BAR      0x08
+#define IDE_CFG         0x10
+#define IDE_DTC         0x12
+#define IDE_CAST        0x13
+#define IDE_ETC         0x14
+#define IDE_INTERNAL_PM 0x15
+
+/*
+ * ACC STANDARD
+ */
+#define ACC_CAP         0x00
+#define ACC_CONFIG      0x01
+#define ACC_SMI         0x02
+#define ACC_ERROR       0x03
+#define ACC_PM          0x04
+#define ACC_DIAG        0x05
+
+/*
+ * USB STANDARD
+ */
+#define USB_CAP         0x00
+#define USB_CONFIG      0x01
+#define USB_SMI         0x02
+#define USB_ERROR       0x03
+#define USB_PM          0x04
+#define USB_DIAG        0x05
+
+/*
+ * USB SPEC.
+ */
+#define USB_OHCI        0x08
+#define USB_EHCI        0x09
+
+/****************** NATIVE ***************************/
+/* GPIO : I/O SPACE; REG : 32BITS */
+#define GPIOL_OUT_VAL           0x00
+#define GPIOL_OUT_EN            0x04
+
+#endif                          /* _CS5536_H */
diff --git a/arch/mips/include/asm/mach-loongson/cs5536/cs5536_mfgpt.h b/arch/mips/include/asm/mach-loongson/cs5536/cs5536_mfgpt.h
new file mode 100644
index 000000000000..4b493d6772c2
--- /dev/null
+++ b/arch/mips/include/asm/mach-loongson/cs5536/cs5536_mfgpt.h
@@ -0,0 +1,35 @@
+/*
+ * cs5536 mfgpt header file
+ */
+
+#ifndef _CS5536_MFGPT_H
+#define _CS5536_MFGPT_H
+
+#include <cs5536/cs5536.h>
+#include <cs5536/cs5536_pci.h>
+
+#ifdef CONFIG_CS5536_MFGPT
+extern void setup_mfgpt0_timer(void);
+extern void disable_mfgpt0_counter(void);
+extern void enable_mfgpt0_counter(void);
+#else
+static inline void __maybe_unused setup_mfgpt0_timer(void)
+{
+}
+static inline void __maybe_unused disable_mfgpt0_counter(void)
+{
+}
+static inline void __maybe_unused enable_mfgpt0_counter(void)
+{
+}
+#endif
+
+#define MFGPT_TICK_RATE 14318000
+#define COMPARE  ((MFGPT_TICK_RATE + HZ/2) / HZ)
+
+#define MFGPT_BASE      mfgpt_base
+#define MFGPT0_CMP2     (MFGPT_BASE + 2)
+#define MFGPT0_CNT      (MFGPT_BASE + 4)
+#define MFGPT0_SETUP    (MFGPT_BASE + 6)
+
+#endif /*!_CS5536_MFGPT_H */
diff --git a/arch/mips/include/asm/mach-loongson/cs5536/cs5536_pci.h b/arch/mips/include/asm/mach-loongson/cs5536/cs5536_pci.h
new file mode 100644
index 000000000000..0dca9c89ee7c
--- /dev/null
+++ b/arch/mips/include/asm/mach-loongson/cs5536/cs5536_pci.h
@@ -0,0 +1,153 @@
+/*
+ * the definition file of cs5536 Virtual Support Module(VSM).
+ * pci configuration space can be accessed through the VSM, so
+ * there is no need of the MSR read/write now, except the spec.
+ * MSR registers which are not implemented yet.
+ *
+ * Copyright (C) 2007 Lemote Inc.
+ * Author : jlliu, liujl@lemote.com
+ */
+
+#ifndef _CS5536_PCI_H
+#define _CS5536_PCI_H
+
+#include <linux/types.h>
+#include <linux/pci_regs.h>
+
+extern void cs5536_pci_conf_write4(int function, int reg, u32 value);
+extern u32 cs5536_pci_conf_read4(int function, int reg);
+
+#define CS5536_ACC_INTR         9
+#define CS5536_IDE_INTR         14
+#define CS5536_USB_INTR         11
+#define CS5536_MFGPT_INTR       5
+#define CS5536_UART1_INTR       4
+#define CS5536_UART2_INTR       3
+
+/************** PCI BUS DEVICE FUNCTION ***************/
+
+/*
+ * PCI bus device function
+ */
+#define PCI_BUS_CS5536          0
+#define PCI_IDSEL_CS5536        14
+
+/********** STANDARD PCI-2.2 EXPANSION ****************/
+
+/*
+ * PCI configuration space
+ * we have to virtualize the PCI configure space head, so we should
+ * define the necessary IDs and some others.
+ */
+
+/* CONFIG of PCI VENDOR ID*/
+#define CFG_PCI_VENDOR_ID(mod_dev_id, sys_vendor_id) \
+        (((mod_dev_id) << 16) | (sys_vendor_id))
+
+/* VENDOR ID */
+#define CS5536_VENDOR_ID        0x1022
+
+/* DEVICE ID */
+#define CS5536_ISA_DEVICE_ID            0x2090
+#define CS5536_IDE_DEVICE_ID            0x209a
+#define CS5536_ACC_DEVICE_ID            0x2093
+#define CS5536_OHCI_DEVICE_ID           0x2094
+#define CS5536_EHCI_DEVICE_ID           0x2095
+
+/* CLASS CODE : CLASS SUB-CLASS INTERFACE */
+#define CS5536_ISA_CLASS_CODE           0x060100
+#define CS5536_IDE_CLASS_CODE           0x010180
+#define CS5536_ACC_CLASS_CODE           0x040100
+#define CS5536_OHCI_CLASS_CODE          0x0C0310
+#define CS5536_EHCI_CLASS_CODE          0x0C0320
+
+/* BHLC : BIST HEADER-TYPE LATENCY-TIMER CACHE-LINE-SIZE */
+
+#define CFG_PCI_CACHE_LINE_SIZE(header_type, latency_timer)     \
+        ((PCI_NONE_BIST << 24) | ((header_type) << 16) \
+                | ((latency_timer) << 8) | PCI_NORMAL_CACHE_LINE_SIZE);
+
+#define PCI_NONE_BIST                   0x00    /* RO not implemented yet. */
+#define PCI_BRIDGE_HEADER_TYPE          0x80    /* RO */
+#define PCI_NORMAL_HEADER_TYPE          0x00
+#define PCI_NORMAL_LATENCY_TIMER        0x00
+#define PCI_NORMAL_CACHE_LINE_SIZE      0x08    /* RW */
+
+/* BAR */
+#define PCI_BAR0_REG                    0x10
+#define PCI_BAR1_REG                    0x14
+#define PCI_BAR2_REG                    0x18
+#define PCI_BAR3_REG                    0x1c
+#define PCI_BAR4_REG                    0x20
+#define PCI_BAR5_REG                    0x24
+#define PCI_BAR_COUNT                   6
+#define PCI_BAR_RANGE_MASK              0xFFFFFFFF
+
+/* CARDBUS CIS POINTER */
+#define PCI_CARDBUS_CIS_POINTER         0x00000000
+
+/* SUBSYSTEM VENDOR ID  */
+#define CS5536_SUB_VENDOR_ID            CS5536_VENDOR_ID
+
+/* SUBSYSTEM ID */
+#define CS5536_ISA_SUB_ID               CS5536_ISA_DEVICE_ID
+#define CS5536_IDE_SUB_ID               CS5536_IDE_DEVICE_ID
+#define CS5536_ACC_SUB_ID               CS5536_ACC_DEVICE_ID
+#define CS5536_OHCI_SUB_ID              CS5536_OHCI_DEVICE_ID
+#define CS5536_EHCI_SUB_ID              CS5536_EHCI_DEVICE_ID
+
+/* EXPANSION ROM BAR */
+#define PCI_EXPANSION_ROM_BAR           0x00000000
+
+/* CAPABILITIES POINTER */
+#define PCI_CAPLIST_POINTER             0x00000000
+#define PCI_CAPLIST_USB_POINTER         0x40
+/* INTERRUPT */
+
+#define CFG_PCI_INTERRUPT_LINE(pin, mod_intr) \
+        ((PCI_MAX_LATENCY << 24) | (PCI_MIN_GRANT << 16) | \
+                ((pin) << 8) | (mod_intr))
+
+#define PCI_MAX_LATENCY                 0x40
+#define PCI_MIN_GRANT                   0x00
+#define PCI_DEFAULT_PIN                 0x01
+
+/*********** EXPANSION PCI REG ************************/
+
+/*
+ * ISA EXPANSION
+ */
+#define PCI_UART1_INT_REG       0x50
+#define PCI_UART2_INT_REG       0x54
+#define PCI_ISA_FIXUP_REG       0x58
+
+/*
+ * IDE EXPANSION
+ */
+#define PCI_IDE_CFG_REG         0x40
+#define CS5536_IDE_FLASH_SIGNATURE      0xDEADBEEF
+#define PCI_IDE_DTC_REG         0x48
+#define PCI_IDE_CAST_REG        0x4C
+#define PCI_IDE_ETC_REG         0x50
+#define PCI_IDE_PM_REG          0x54
+#define PCI_IDE_INT_REG         0x60
+
+/*
+ * ACC EXPANSION
+ */
+#define PCI_ACC_INT_REG         0x50
+
+/*
+ * OHCI EXPANSION : INTTERUPT IS IMPLEMENTED BY THE OHCI
+ */
+#define PCI_OHCI_PM_REG         0x40
+#define PCI_OHCI_INT_REG        0x50
+
+/*
+ * EHCI EXPANSION
+ */
+#define PCI_EHCI_LEGSMIEN_REG   0x50
+#define PCI_EHCI_LEGSMISTS_REG  0x54
+#define PCI_EHCI_FLADJ_REG      0x60
+
+#endif                          /* _CS5536_PCI_H_ */
diff --git a/arch/mips/include/asm/mach-loongson/cs5536/cs5536_vsm.h b/arch/mips/include/asm/mach-loongson/cs5536/cs5536_vsm.h
new file mode 100644
index 000000000000..6305bea7e18e
--- /dev/null
+++ b/arch/mips/include/asm/mach-loongson/cs5536/cs5536_vsm.h
@@ -0,0 +1,31 @@
+/*
+ * the read/write interfaces for Virtual Support Module(VSM)
+ *
+ * Copyright (C) 2009 Lemote, Inc.
+ * Author: Wu Zhangjin <wuzj@lemote.com>
+ */
+
+#ifndef _CS5536_VSM_H
+#define _CS5536_VSM_H
+
+#include <linux/types.h>
+
+typedef void (*cs5536_pci_vsm_write)(int reg, u32 value);
+typedef u32 (*cs5536_pci_vsm_read)(int reg);
+
+#define DECLARE_CS5536_MODULE(name) \
+extern void pci_##name##_write_reg(int reg, u32 value); \
+extern u32 pci_##name##_read_reg(int reg);
+
+/* ide module */
+DECLARE_CS5536_MODULE(ide)
+/* acc module */
+DECLARE_CS5536_MODULE(acc)
+/* ohci module */
+DECLARE_CS5536_MODULE(ohci)
+/* isa module */
+DECLARE_CS5536_MODULE(isa)
+/* ehci module */
+DECLARE_CS5536_MODULE(ehci)
+
+#endif                          /* _CS5536_VSM_H */
diff --git a/arch/mips/include/asm/mach-loongson/dma-coherence.h b/arch/mips/include/asm/mach-loongson/dma-coherence.h
index 71a6851ba833..981c75f91a7d 100644
--- a/arch/mips/include/asm/mach-loongson/dma-coherence.h
+++ b/arch/mips/include/asm/mach-loongson/dma-coherence.h
@@ -28,7 +28,11 @@ static inline dma_addr_t plat_map_dma_mem_page(struct device *dev,
 static inline unsigned long plat_dma_addr_to_phys(struct device *dev,
         dma_addr_t dma_addr)
 {
+#if defined(CONFIG_CPU_LOONGSON2F) && defined(CONFIG_64BIT)
+        return (dma_addr > 0x8fffffff) ? dma_addr : (dma_addr & 0x0fffffff);
+#else
         return dma_addr & 0x7fffffff;
+#endif
 }
 
 static inline void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr,
diff --git a/arch/mips/include/asm/mach-loongson/loongson.h b/arch/mips/include/asm/mach-loongson/loongson.h
index da70bcf2304e..ee8bc8376972 100644
--- a/arch/mips/include/asm/mach-loongson/loongson.h
+++ b/arch/mips/include/asm/mach-loongson/loongson.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2009 Lemote, Inc. & Institute of Computing Technology
+ * Copyright (C) 2009 Lemote, Inc.
  * Author: Wu Zhangjin <wuzj@lemote.com>
  *
  * This program is free software; you can redistribute  it and/or modify it
@@ -15,9 +15,6 @@
 #include <linux/io.h>
 #include <linux/init.h>
 
-/* there is an internal bonito64-compatiable northbridge in loongson2e/2f */
-#include <asm/mips-boards/bonito64.h>
-
 /* loongson internal northbridge initialization */
 extern void bonito_irq_init(void);
 
@@ -32,7 +29,19 @@ extern unsigned long memsize, highmemsize;
 /* loongson-specific command line, env and memory initialization */
 extern void __init prom_init_memory(void);
 extern void __init prom_init_cmdline(void);
+extern void __init prom_init_machtype(void);
 extern void __init prom_init_env(void);
+#ifdef CONFIG_LOONGSON_UART_BASE
+extern unsigned long _loongson_uart_base, loongson_uart_base;
+extern void prom_init_loongson_uart_base(void);
+#endif
+
+static inline void prom_init_uart_base(void)
+{
+#ifdef CONFIG_LOONGSON_UART_BASE
+        prom_init_loongson_uart_base();
+#endif
+}
 
 /* irq operation functions */
 extern void bonito_irqdispatch(void);
@@ -40,25 +49,276 @@ extern void __init bonito_irq_init(void);
 extern void __init set_irq_trigger_mode(void);
 extern void __init mach_init_irq(void);
 extern void mach_irq_dispatch(unsigned int pending);
+extern int mach_i8259_irq(void);
+
+/* We need this in some places... */
+#define delay() ({              \
+        int x;                          \
+        for (x = 0; x < 100000; x++)    \
+                __asm__ __volatile__(""); \
+})
+
+#define LOONGSON_REG(x) \
+        (*(volatile u32 *)((char *)CKSEG1ADDR(LOONGSON_REG_BASE) + (x)))
+
+#define LOONGSON_IRQ_BASE       32
+#define LOONGSON2_PERFCNT_IRQ   (MIPS_CPU_IRQ_BASE + 6) /* cpu perf counter */
+
+#define LOONGSON_FLASH_BASE     0x1c000000
+#define LOONGSON_FLASH_SIZE     0x02000000      /* 32M */
+#define LOONGSON_FLASH_TOP      (LOONGSON_FLASH_BASE+LOONGSON_FLASH_SIZE-1)
+
+#define LOONGSON_LIO0_BASE      0x1e000000
+#define LOONGSON_LIO0_SIZE      0x01C00000      /* 28M */
+#define LOONGSON_LIO0_TOP       (LOONGSON_LIO0_BASE+LOONGSON_LIO0_SIZE-1)
+
+#define LOONGSON_BOOT_BASE      0x1fc00000
+#define LOONGSON_BOOT_SIZE      0x00100000      /* 1M */
+#define LOONGSON_BOOT_TOP       (LOONGSON_BOOT_BASE+LOONGSON_BOOT_SIZE-1)
+#define LOONGSON_REG_BASE       0x1fe00000
+#define LOONGSON_REG_SIZE       0x00100000      /* 256Bytes + 256Bytes + ??? */
+#define LOONGSON_REG_TOP        (LOONGSON_REG_BASE+LOONGSON_REG_SIZE-1)
+
+#define LOONGSON_LIO1_BASE      0x1ff00000
+#define LOONGSON_LIO1_SIZE      0x00100000      /* 1M */
+#define LOONGSON_LIO1_TOP       (LOONGSON_LIO1_BASE+LOONGSON_LIO1_SIZE-1)
+
+#define LOONGSON_PCILO0_BASE    0x10000000
+#define LOONGSON_PCILO1_BASE    0x14000000
+#define LOONGSON_PCILO2_BASE    0x18000000
+#define LOONGSON_PCILO_BASE     LOONGSON_PCILO0_BASE
+#define LOONGSON_PCILO_SIZE     0x0c000000      /* 64M * 3 */
+#define LOONGSON_PCILO_TOP      (LOONGSON_PCILO0_BASE+LOONGSON_PCILO_SIZE-1)
+
+#define LOONGSON_PCICFG_BASE    0x1fe80000
+#define LOONGSON_PCICFG_SIZE    0x00000800      /* 2K */
+#define LOONGSON_PCICFG_TOP     (LOONGSON_PCICFG_BASE+LOONGSON_PCICFG_SIZE-1)
+#define LOONGSON_PCIIO_BASE     0x1fd00000
+#define LOONGSON_PCIIO_SIZE     0x00100000      /* 1M */
+#define LOONGSON_PCIIO_TOP      (LOONGSON_PCIIO_BASE+LOONGSON_PCIIO_SIZE-1)
+
+/* Loongson Register Bases */
+
+#define LOONGSON_PCICONFIGBASE  0x00
+#define LOONGSON_REGBASE        0x100
 
 /* PCI Configuration Registers */
-#define LOONGSON_PCI_ISR4C  BONITO_PCI_REG(0x4c)
+
+#define LOONGSON_PCI_REG(x)     LOONGSON_REG(LOONGSON_PCICONFIGBASE + (x))
+#define LOONGSON_PCIDID         LOONGSON_PCI_REG(0x00)
+#define LOONGSON_PCICMD         LOONGSON_PCI_REG(0x04)
+#define LOONGSON_PCICLASS       LOONGSON_PCI_REG(0x08)
+#define LOONGSON_PCILTIMER      LOONGSON_PCI_REG(0x0c)
+#define LOONGSON_PCIBASE0       LOONGSON_PCI_REG(0x10)
+#define LOONGSON_PCIBASE1       LOONGSON_PCI_REG(0x14)
+#define LOONGSON_PCIBASE2       LOONGSON_PCI_REG(0x18)
+#define LOONGSON_PCIBASE3       LOONGSON_PCI_REG(0x1c)
+#define LOONGSON_PCIBASE4       LOONGSON_PCI_REG(0x20)
+#define LOONGSON_PCIEXPRBASE    LOONGSON_PCI_REG(0x30)
+#define LOONGSON_PCIINT         LOONGSON_PCI_REG(0x3c)
+
+#define LOONGSON_PCI_ISR4C      LOONGSON_PCI_REG(0x4c)
+
+#define LOONGSON_PCICMD_PERR_CLR        0x80000000
+#define LOONGSON_PCICMD_SERR_CLR        0x40000000
+#define LOONGSON_PCICMD_MABORT_CLR      0x20000000
+#define LOONGSON_PCICMD_MTABORT_CLR     0x10000000
+#define LOONGSON_PCICMD_TABORT_CLR      0x08000000
+#define LOONGSON_PCICMD_MPERR_CLR       0x01000000
+#define LOONGSON_PCICMD_PERRRESPEN      0x00000040
+#define LOONGSON_PCICMD_ASTEPEN         0x00000080
+#define LOONGSON_PCICMD_SERREN          0x00000100
+#define LOONGSON_PCILTIMER_BUSLATENCY   0x0000ff00
+#define LOONGSON_PCILTIMER_BUSLATENCY_SHIFT     8
+
+/* Loongson h/w Configuration */
+
+#define LOONGSON_GENCFG_OFFSET          0x4
+#define LOONGSON_GENCFG LOONGSON_REG(LOONGSON_REGBASE + LOONGSON_GENCFG_OFFSET)
+
+#define LOONGSON_GENCFG_DEBUGMODE       0x00000001
+#define LOONGSON_GENCFG_SNOOPEN         0x00000002
+#define LOONGSON_GENCFG_CPUSELFRESET    0x00000004
+
+#define LOONGSON_GENCFG_FORCE_IRQA      0x00000008
+#define LOONGSON_GENCFG_IRQA_ISOUT      0x00000010
+#define LOONGSON_GENCFG_IRQA_FROM_INT1  0x00000020
+#define LOONGSON_GENCFG_BYTESWAP        0x00000040
+
+#define LOONGSON_GENCFG_UNCACHED        0x00000080
+#define LOONGSON_GENCFG_PREFETCHEN      0x00000100
+#define LOONGSON_GENCFG_WBEHINDEN       0x00000200
+#define LOONGSON_GENCFG_CACHEALG        0x00000c00
+#define LOONGSON_GENCFG_CACHEALG_SHIFT  10
+#define LOONGSON_GENCFG_PCIQUEUE        0x00001000
+#define LOONGSON_GENCFG_CACHESTOP       0x00002000
+#define LOONGSON_GENCFG_MSTRBYTESWAP    0x00004000
+#define LOONGSON_GENCFG_BUSERREN        0x00008000
+#define LOONGSON_GENCFG_NORETRYTIMEOUT  0x00010000
+#define LOONGSON_GENCFG_SHORTCOPYTIMEOUT        0x00020000
+
+/* PCI address map control */
+
+#define LOONGSON_PCIMAP                 LOONGSON_REG(LOONGSON_REGBASE + 0x10)
+#define LOONGSON_PCIMEMBASECFG          LOONGSON_REG(LOONGSON_REGBASE + 0x14)
+#define LOONGSON_PCIMAP_CFG             LOONGSON_REG(LOONGSON_REGBASE + 0x18)
+
+/* GPIO Regs - r/w */
+
+#define LOONGSON_GPIODATA               LOONGSON_REG(LOONGSON_REGBASE + 0x1c)
+#define LOONGSON_GPIOIE                 LOONGSON_REG(LOONGSON_REGBASE + 0x20)
+
+/* ICU Configuration Regs - r/w */
+
+#define LOONGSON_INTEDGE                LOONGSON_REG(LOONGSON_REGBASE + 0x24)
+#define LOONGSON_INTSTEER               LOONGSON_REG(LOONGSON_REGBASE + 0x28)
+#define LOONGSON_INTPOL                 LOONGSON_REG(LOONGSON_REGBASE + 0x2c)
+
+/* ICU Enable Regs - IntEn & IntISR are r/o. */
+
+#define LOONGSON_INTENSET               LOONGSON_REG(LOONGSON_REGBASE + 0x30)
+#define LOONGSON_INTENCLR               LOONGSON_REG(LOONGSON_REGBASE + 0x34)
+#define LOONGSON_INTEN                  LOONGSON_REG(LOONGSON_REGBASE + 0x38)
+#define LOONGSON_INTISR                 LOONGSON_REG(LOONGSON_REGBASE + 0x3c)
+
+/* ICU */
+#define LOONGSON_ICU_MBOXES             0x0000000f
+#define LOONGSON_ICU_MBOXES_SHIFT       0
+#define LOONGSON_ICU_DMARDY             0x00000010
+#define LOONGSON_ICU_DMAEMPTY           0x00000020
+#define LOONGSON_ICU_COPYRDY            0x00000040
+#define LOONGSON_ICU_COPYEMPTY          0x00000080
+#define LOONGSON_ICU_COPYERR            0x00000100
+#define LOONGSON_ICU_PCIIRQ             0x00000200
+#define LOONGSON_ICU_MASTERERR          0x00000400
+#define LOONGSON_ICU_SYSTEMERR          0x00000800
+#define LOONGSON_ICU_DRAMPERR           0x00001000
+#define LOONGSON_ICU_RETRYERR           0x00002000
+#define LOONGSON_ICU_GPIOS              0x01ff0000
+#define LOONGSON_ICU_GPIOS_SHIFT                16
+#define LOONGSON_ICU_GPINS              0x7e000000
+#define LOONGSON_ICU_GPINS_SHIFT                25
+#define LOONGSON_ICU_MBOX(N)            (1<<(LOONGSON_ICU_MBOXES_SHIFT+(N)))
+#define LOONGSON_ICU_GPIO(N)            (1<<(LOONGSON_ICU_GPIOS_SHIFT+(N)))
+#define LOONGSON_ICU_GPIN(N)            (1<<(LOONGSON_ICU_GPINS_SHIFT+(N)))
+
+/* PCI prefetch window base & mask */
+
+#define LOONGSON_MEM_WIN_BASE_L         LOONGSON_REG(LOONGSON_REGBASE + 0x40)
+#define LOONGSON_MEM_WIN_BASE_H         LOONGSON_REG(LOONGSON_REGBASE + 0x44)
+#define LOONGSON_MEM_WIN_MASK_L         LOONGSON_REG(LOONGSON_REGBASE + 0x48)
+#define LOONGSON_MEM_WIN_MASK_H         LOONGSON_REG(LOONGSON_REGBASE + 0x4c)
 
 /* PCI_Hit*_Sel_* */
 
-#define LOONGSON_PCI_HIT0_SEL_L     BONITO(BONITO_REGBASE + 0x50)
-#define LOONGSON_PCI_HIT0_SEL_H     BONITO(BONITO_REGBASE + 0x54)
-#define LOONGSON_PCI_HIT1_SEL_L     BONITO(BONITO_REGBASE + 0x58)
-#define LOONGSON_PCI_HIT1_SEL_H     BONITO(BONITO_REGBASE + 0x5c)
-#define LOONGSON_PCI_HIT2_SEL_L     BONITO(BONITO_REGBASE + 0x60)
-#define LOONGSON_PCI_HIT2_SEL_H     BONITO(BONITO_REGBASE + 0x64)
+#define LOONGSON_PCI_HIT0_SEL_L         LOONGSON_REG(LOONGSON_REGBASE + 0x50)
+#define LOONGSON_PCI_HIT0_SEL_H         LOONGSON_REG(LOONGSON_REGBASE + 0x54)
+#define LOONGSON_PCI_HIT1_SEL_L         LOONGSON_REG(LOONGSON_REGBASE + 0x58)
+#define LOONGSON_PCI_HIT1_SEL_H         LOONGSON_REG(LOONGSON_REGBASE + 0x5c)
+#define LOONGSON_PCI_HIT2_SEL_L         LOONGSON_REG(LOONGSON_REGBASE + 0x60)
+#define LOONGSON_PCI_HIT2_SEL_H         LOONGSON_REG(LOONGSON_REGBASE + 0x64)
 
 /* PXArb Config & Status */
 
-#define LOONGSON_PXARB_CFG      BONITO(BONITO_REGBASE + 0x68)
-#define LOONGSON_PXARB_STATUS       BONITO(BONITO_REGBASE + 0x6c)
+#define LOONGSON_PXARB_CFG              LOONGSON_REG(LOONGSON_REGBASE + 0x68)
+#define LOONGSON_PXARB_STATUS           LOONGSON_REG(LOONGSON_REGBASE + 0x6c)
+
+/* pcimap */
+
+#define LOONGSON_PCIMAP_PCIMAP_LO0      0x0000003f
+#define LOONGSON_PCIMAP_PCIMAP_LO0_SHIFT        0
+#define LOONGSON_PCIMAP_PCIMAP_LO1      0x00000fc0
+#define LOONGSON_PCIMAP_PCIMAP_LO1_SHIFT        6
+#define LOONGSON_PCIMAP_PCIMAP_LO2      0x0003f000
+#define LOONGSON_PCIMAP_PCIMAP_LO2_SHIFT        12
+#define LOONGSON_PCIMAP_PCIMAP_2        0x00040000
+#define LOONGSON_PCIMAP_WIN(WIN, ADDR)  \
+        ((((ADDR)>>26) & LOONGSON_PCIMAP_PCIMAP_LO0) << ((WIN)*6))
+
+#ifdef CONFIG_CPU_SUPPORTS_CPUFREQ
+#include <linux/cpufreq.h>
+extern void loongson2_cpu_wait(void);
+extern struct cpufreq_frequency_table loongson2_clockmod_table[];
+
+/* Chip Config */
+#define LOONGSON_CHIPCFG0               LOONGSON_REG(LOONGSON_REGBASE + 0x80)
+#endif
+
+/*
+ * address windows configuration module
+ *
+ * loongson2e do not have this module
+ */
+#ifdef CONFIG_CPU_SUPPORTS_ADDRWINCFG
+
+/* address window config module base address */
+#define LOONGSON_ADDRWINCFG_BASE                0x3ff00000ul
+#define LOONGSON_ADDRWINCFG_SIZE                0x180
+
+extern unsigned long _loongson_addrwincfg_base;
+#define LOONGSON_ADDRWINCFG(offset) \
+        (*(volatile u64 *)(_loongson_addrwincfg_base + (offset)))
+
+#define CPU_WIN0_BASE   LOONGSON_ADDRWINCFG(0x00)
+#define CPU_WIN1_BASE   LOONGSON_ADDRWINCFG(0x08)
+#define CPU_WIN2_BASE   LOONGSON_ADDRWINCFG(0x10)
+#define CPU_WIN3_BASE   LOONGSON_ADDRWINCFG(0x18)
+
+#define CPU_WIN0_MASK   LOONGSON_ADDRWINCFG(0x20)
+#define CPU_WIN1_MASK   LOONGSON_ADDRWINCFG(0x28)
+#define CPU_WIN2_MASK   LOONGSON_ADDRWINCFG(0x30)
+#define CPU_WIN3_MASK   LOONGSON_ADDRWINCFG(0x38)
+
+#define CPU_WIN0_MMAP   LOONGSON_ADDRWINCFG(0x40)
+#define CPU_WIN1_MMAP   LOONGSON_ADDRWINCFG(0x48)
+#define CPU_WIN2_MMAP   LOONGSON_ADDRWINCFG(0x50)
+#define CPU_WIN3_MMAP   LOONGSON_ADDRWINCFG(0x58)
+
+#define PCIDMA_WIN0_BASE        LOONGSON_ADDRWINCFG(0x60)
+#define PCIDMA_WIN1_BASE        LOONGSON_ADDRWINCFG(0x68)
+#define PCIDMA_WIN2_BASE        LOONGSON_ADDRWINCFG(0x70)
+#define PCIDMA_WIN3_BASE        LOONGSON_ADDRWINCFG(0x78)
+
+#define PCIDMA_WIN0_MASK        LOONGSON_ADDRWINCFG(0x80)
+#define PCIDMA_WIN1_MASK        LOONGSON_ADDRWINCFG(0x88)
+#define PCIDMA_WIN2_MASK        LOONGSON_ADDRWINCFG(0x90)
+#define PCIDMA_WIN3_MASK        LOONGSON_ADDRWINCFG(0x98)
+
+#define PCIDMA_WIN0_MMAP        LOONGSON_ADDRWINCFG(0xa0)
+#define PCIDMA_WIN1_MMAP        LOONGSON_ADDRWINCFG(0xa8)
+#define PCIDMA_WIN2_MMAP        LOONGSON_ADDRWINCFG(0xb0)
+#define PCIDMA_WIN3_MMAP        LOONGSON_ADDRWINCFG(0xb8)
+
+#define ADDRWIN_WIN0    0
+#define ADDRWIN_WIN1    1
+#define ADDRWIN_WIN2    2
+#define ADDRWIN_WIN3    3
+
+#define ADDRWIN_MAP_DST_DDR     0
+#define ADDRWIN_MAP_DST_PCI     1
+#define ADDRWIN_MAP_DST_LIO     1
+
+/*
+ * s: CPU, PCIDMA
+ * d: DDR, PCI, LIO
+ * win: 0, 1, 2, 3
+ * src: map source
+ * dst: map destination
+ * size: ~mask + 1
+ */
+#define LOONGSON_ADDRWIN_CFG(s, d, w, src, dst, size) do {\
+        s##_WIN##w##_BASE = (src); \
+        s##_WIN##w##_MMAP = (src) | ADDRWIN_MAP_DST_##d; \
+        s##_WIN##w##_MASK = ~(size-1); \
+} while (0)
+
+#define LOONGSON_ADDRWIN_CPUTOPCI(win, src, dst, size) \
+        LOONGSON_ADDRWIN_CFG(CPU, PCI, win, src, dst, size)
+#define LOONGSON_ADDRWIN_CPUTODDR(win, src, dst, size) \
+        LOONGSON_ADDRWIN_CFG(CPU, DDR, win, src, dst, size)
+#define LOONGSON_ADDRWIN_PCITODDR(win, src, dst, size) \
+        LOONGSON_ADDRWIN_CFG(PCIDMA, DDR, win, src, dst, size)
 
-/* loongson2-specific perf counter IRQ */
-#define LOONGSON2_PERFCNT_IRQ   (MIPS_CPU_IRQ_BASE + 6)
+#endif  /* ! CONFIG_CPU_SUPPORTS_ADDRWINCFG */
 
 #endif /* __ASM_MACH_LOONGSON_LOONGSON_H */
diff --git a/arch/mips/include/asm/mach-loongson/machine.h b/arch/mips/include/asm/mach-loongson/machine.h
index 206ea2067916..acf8359cb135 100644
--- a/arch/mips/include/asm/mach-loongson/machine.h
+++ b/arch/mips/include/asm/mach-loongson/machine.h
@@ -13,10 +13,15 @@
 
 #ifdef CONFIG_LEMOTE_FULOONG2E
 
-#define LOONGSON_UART_BASE (BONITO_PCIIO_BASE + 0x3f8)
-
 #define LOONGSON_MACHTYPE MACH_LEMOTE_FL2E
 
 #endif
 
+/* use fuloong2f as the default machine of LEMOTE_MACH2F */
+#ifdef CONFIG_LEMOTE_MACH2F
+
+#define LOONGSON_MACHTYPE MACH_LEMOTE_FL2F
+
+#endif
+
 #endif /* __ASM_MACH_LOONGSON_MACHINE_H */
diff --git a/arch/mips/include/asm/mach-loongson/mem.h b/arch/mips/include/asm/mach-loongson/mem.h
index bd7b3cba7e35..e9960f341b96 100644
--- a/arch/mips/include/asm/mach-loongson/mem.h
+++ b/arch/mips/include/asm/mach-loongson/mem.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2009 Lemote, Inc. & Institute of Computing Technology
+ * Copyright (C) 2009 Lemote, Inc.
  * Author: Wu Zhangjin <wuzj@lemote.com>
  *
  * This program is free software; you can redistribute  it and/or modify it
@@ -12,19 +12,30 @@
 #define __ASM_MACH_LOONGSON_MEM_H
 
 /*
- * On Lemote Loongson 2e
+ * high memory space
  *
- * the high memory space starts from 512M.
- * the peripheral registers reside between 0x1000:0000 and 0x2000:0000.
+ * in loongson2e, starts from 512M
+ * in loongson2f, starts from 2G 256M
  */
+#ifdef CONFIG_CPU_LOONGSON2E
+#define LOONGSON_HIGHMEM_START  0x20000000
+#else
+#define LOONGSON_HIGHMEM_START  0x90000000
+#endif
 
-#ifdef CONFIG_LEMOTE_FULOONG2E
-
-#define LOONGSON_HIGHMEM_START  0x20000000
+/*
+ * the peripheral registers(MMIO):
+ *
+ * On the Lemote Loongson 2e system, reside between 0x1000:0000 and 0x2000:0000.
+ * On the Lemote Loongson 2f system, reside between 0x1000:0000 and 0x8000:0000.
+ */
 
 #define LOONGSON_MMIO_MEM_START 0x10000000
-#define LOONGSON_MMIO_MEM_END   0x20000000
 
+#ifdef CONFIG_CPU_LOONGSON2E
+#define LOONGSON_MMIO_MEM_END   0x20000000
+#else
+#define LOONGSON_MMIO_MEM_END   0x80000000
 #endif
 
 #endif /* __ASM_MACH_LOONGSON_MEM_H */
diff --git a/arch/mips/include/asm/mach-loongson/pci.h b/arch/mips/include/asm/mach-loongson/pci.h
index f1663ca81da0..a199a4f6de4e 100644
--- a/arch/mips/include/asm/mach-loongson/pci.h
+++ b/arch/mips/include/asm/mach-loongson/pci.h
@@ -1,5 +1,6 @@
 /*
  * Copyright (c) 2008 Zhang Le <r0bertz@gentoo.org>
+ * Copyright (c) 2009 Wu Zhangjin <wuzj@lemote.com>
  *
  * This program is free software; you can redistribute it
  * and/or modify it under the terms of the GNU General
@@ -22,16 +23,39 @@
 #ifndef __ASM_MACH_LOONGSON_PCI_H_
 #define __ASM_MACH_LOONGSON_PCI_H_
 
-extern struct pci_ops bonito64_pci_ops;
+extern struct pci_ops loongson_pci_ops;
 
-#ifdef CONFIG_LEMOTE_FULOONG2E
+/* this is an offset from mips_io_port_base */
+#define LOONGSON_PCI_IO_START   0x00004000UL
+
+#ifdef CONFIG_CPU_SUPPORTS_ADDRWINCFG
+
+/*
+ * we use address window2 to map cpu address space to pci space
+ * window2: cpu [1G, 2G] -> pci [1G, 2G]
+ * why not use window 0 & 1? because they are used by cpu when booting.
+ * window0: cpu [0, 256M] -> ddr [0, 256M]
+ * window1: cpu [256M, 512M] -> pci [256M, 512M]
+ */
+
+/* the smallest LOONGSON_CPU_MEM_SRC can be 512M */
+#define LOONGSON_CPU_MEM_SRC    0x40000000ul            /* 1G */
+#define LOONGSON_PCI_MEM_DST    LOONGSON_CPU_MEM_SRC
+
+#define LOONGSON_PCI_MEM_START  LOONGSON_PCI_MEM_DST
+#define LOONGSON_PCI_MEM_END    (0x80000000ul-1)        /* 2G */
+
+#define MMAP_CPUTOPCI_SIZE      (LOONGSON_PCI_MEM_END - \
+                                        LOONGSON_PCI_MEM_START + 1)
+
+#else   /* loongson2f/32bit & loongson2e */
 
 /* this pci memory space is mapped by pcimap in pci.c */
-#define LOONGSON_PCI_MEM_START  BONITO_PCILO1_BASE
-#define LOONGSON_PCI_MEM_END    (BONITO_PCILO1_BASE + 0x04000000 * 2)
+#define LOONGSON_PCI_MEM_START  LOONGSON_PCILO1_BASE
+#define LOONGSON_PCI_MEM_END    (LOONGSON_PCILO1_BASE + 0x04000000 * 2)
 /* this is an offset from mips_io_port_base */
 #define LOONGSON_PCI_IO_START   0x00004000UL
 
-#endif
+#endif  /* !CONFIG_CPU_SUPPORTS_ADDRWINCFG */
 
 #endif /* !__ASM_MACH_LOONGSON_PCI_H_ */
diff --git a/arch/mips/include/asm/mach-powertv/asic.h b/arch/mips/include/asm/mach-powertv/asic.h
new file mode 100644
index 000000000000..bcad43a93ebf
--- /dev/null
+++ b/arch/mips/include/asm/mach-powertv/asic.h
@@ -0,0 +1,107 @@
+/*
+ * Copyright (C) 2009  Cisco Systems, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ */
+
+#ifndef _ASM_MACH_POWERTV_ASIC_H
+#define _ASM_MACH_POWERTV_ASIC_H
+
+#include <linux/ioport.h>
+#include <asm/mach-powertv/asic_regs.h>
+
+#define DVR_CAPABLE     (1<<0)
+#define PCIE_CAPABLE    (1<<1)
+#define FFS_CAPABLE     (1<<2)
+#define DISPLAY_CAPABLE (1<<3)
+
+/* Platform Family types
+ * For compitability, the new value must be added in the end */
+enum family_type {
+        FAMILY_8500,
+        FAMILY_8500RNG,
+        FAMILY_4500,
+        FAMILY_1500,
+        FAMILY_8600,
+        FAMILY_4600,
+        FAMILY_4600VZA,
+        FAMILY_8600VZB,
+        FAMILY_1500VZE,
+        FAMILY_1500VZF,
+        FAMILIES
+};
+
+/* Register maps for each ASIC */
+extern const struct register_map calliope_register_map;
+extern const struct register_map cronus_register_map;
+extern const struct register_map zeus_register_map;
+
+extern struct resource dvr_cronus_resources[];
+extern struct resource dvr_zeus_resources[];
+extern struct resource non_dvr_calliope_resources[];
+extern struct resource non_dvr_cronus_resources[];
+extern struct resource non_dvr_cronuslite_resources[];
+extern struct resource non_dvr_vz_calliope_resources[];
+extern struct resource non_dvr_vze_calliope_resources[];
+extern struct resource non_dvr_vzf_calliope_resources[];
+extern struct resource non_dvr_zeus_resources[];
+
+extern void powertv_platform_init(void);
+extern void platform_alloc_bootmem(void);
+extern enum asic_type platform_get_asic(void);
+extern enum family_type platform_get_family(void);
+extern int platform_supports_dvr(void);
+extern int platform_supports_ffs(void);
+extern int platform_supports_pcie(void);
+extern int platform_supports_display(void);
+extern void configure_platform(void);
+extern void platform_configure_usb_ehci(void);
+extern void platform_unconfigure_usb_ehci(void);
+extern void platform_configure_usb_ohci(void);
+extern void platform_unconfigure_usb_ohci(void);
+
+/* Platform Resources */
+#define ASIC_RESOURCE_GET_EXISTS 1
+extern struct resource *asic_resource_get(const char *name);
+extern void platform_release_memory(void *baddr, int size);
+
+/* Reboot Cause */
+extern void set_reboot_cause(char code, unsigned int data, unsigned int data2);
+extern void set_locked_reboot_cause(char code, unsigned int data,
+        unsigned int data2);
+
+enum sys_reboot_type {
+        sys_unknown_reboot = 0x00,      /* Unknown reboot cause */
+        sys_davic_change = 0x01,        /* Reboot due to change in DAVIC
+                                         * mode */
+        sys_user_reboot = 0x02,         /* Reboot initiated by user */
+        sys_system_reboot = 0x03,       /* Reboot initiated by OS */
+        sys_trap_reboot = 0x04,         /* Reboot due to a CPU trap */
+        sys_silent_reboot = 0x05,       /* Silent reboot */
+        sys_boot_ldr_reboot = 0x06,     /* Bootloader reboot */
+        sys_power_up_reboot = 0x07,     /* Power on bootup.  Older
+                                         * drivers may report as
+                                         * userReboot. */
+        sys_code_change = 0x08,         /* Reboot to take code change.
+                                         * Older drivers may report as
+                                         * userReboot. */
+        sys_hardware_reset = 0x09,      /* HW watchdog or front-panel
+                                         * reset button reset.  Older
+                                         * drivers may report as
+                                         * userReboot. */
+        sys_watchdogInterrupt = 0x0A    /* Pre-watchdog interrupt */
+};
+
+#endif /* _ASM_MACH_POWERTV_ASIC_H */
diff --git a/arch/mips/include/asm/mach-powertv/asic_regs.h b/arch/mips/include/asm/mach-powertv/asic_regs.h
new file mode 100644
index 000000000000..9a65c93782f9
--- /dev/null
+++ b/arch/mips/include/asm/mach-powertv/asic_regs.h
@@ -0,0 +1,155 @@
+/*
+ * Copyright (C) 2009  Cisco Systems, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ */
+
+#ifndef __ASM_MACH_POWERTV_ASIC_H_
+#define __ASM_MACH_POWERTV_ASIC_H_
+#include <linux/io.h>
+
+/* ASIC types */
+enum asic_type {
+        ASIC_UNKNOWN,
+        ASIC_ZEUS,
+        ASIC_CALLIOPE,
+        ASIC_CRONUS,
+        ASIC_CRONUSLITE,
+        ASICS
+};
+
+/* hardcoded values read from Chip Version registers */
+#define CRONUS_10       0x0B4C1C20
+#define CRONUS_11       0x0B4C1C21
+#define CRONUSLITE_10   0x0B4C1C40
+
+#define NAND_FLASH_BASE 0x03000000
+#define ZEUS_IO_BASE    0x09000000
+#define CALLIOPE_IO_BASE        0x08000000
+#define CRONUS_IO_BASE  0x09000000
+#define ASIC_IO_SIZE    0x01000000
+
+/* Definitions for backward compatibility */
+#define UART1_INTSTAT   uart1_intstat
+#define UART1_INTEN     uart1_inten
+#define UART1_CONFIG1   uart1_config1
+#define UART1_CONFIG2   uart1_config2
+#define UART1_DIVISORHI uart1_divisorhi
+#define UART1_DIVISORLO uart1_divisorlo
+#define UART1_DATA      uart1_data
+#define UART1_STATUS    uart1_status
+
+/* ASIC register enumeration */
+struct register_map {
+        u32 eic_slow0_strt_add;
+        u32 eic_cfg_bits;
+        u32 eic_ready_status;
+
+        u32 chipver3;
+        u32 chipver2;
+        u32 chipver1;
+        u32 chipver0;
+
+        u32 uart1_intstat;
+        u32 uart1_inten;
+        u32 uart1_config1;
+        u32 uart1_config2;
+        u32 uart1_divisorhi;
+        u32 uart1_divisorlo;
+        u32 uart1_data;
+        u32 uart1_status;
+
+        u32 int_stat_3;
+        u32 int_stat_2;
+        u32 int_stat_1;
+        u32 int_stat_0;
+        u32 int_config;
+        u32 int_int_scan;
+        u32 ien_int_3;
+        u32 ien_int_2;
+        u32 ien_int_1;
+        u32 ien_int_0;
+        u32 int_level_3_3;
+        u32 int_level_3_2;
+        u32 int_level_3_1;
+        u32 int_level_3_0;
+        u32 int_level_2_3;
+        u32 int_level_2_2;
+        u32 int_level_2_1;
+        u32 int_level_2_0;
+        u32 int_level_1_3;
+        u32 int_level_1_2;
+        u32 int_level_1_1;
+        u32 int_level_1_0;
+        u32 int_level_0_3;
+        u32 int_level_0_2;
+        u32 int_level_0_1;
+        u32 int_level_0_0;
+        u32 int_docsis_en;
+
+        u32 mips_pll_setup;
+        u32 usb_fs;
+        u32 test_bus;
+        u32 crt_spare;
+        u32 usb2_ohci_int_mask;
+        u32 usb2_strap;
+        u32 ehci_hcapbase;
+        u32 ohci_hc_revision;
+        u32 bcm1_bs_lmi_steer;
+        u32 usb2_control;
+        u32 usb2_stbus_obc;
+        u32 usb2_stbus_mess_size;
+        u32 usb2_stbus_chunk_size;
+
+        u32 pcie_regs;
+        u32 tim_ch;
+        u32 tim_cl;
+        u32 gpio_dout;
+        u32 gpio_din;
+        u32 gpio_dir;
+        u32 watchdog;
+        u32 front_panel;
+
+        u32 register_maps;
+};
+
+extern enum asic_type asic;
+extern const struct register_map *register_map;
+extern unsigned long asic_phy_base;     /* Physical address of ASIC */
+extern unsigned long asic_base;         /* Virtual address of ASIC */
+
+/*
+ * Macros to interface to registers through their ioremapped address
+ * asic_reg_offset      Returns the offset of a given register from the start
+ *                      of the ASIC address space
+ * asic_reg_phys_addr   Returns the physical address of the given register
+ * asic_reg_addr        Returns the iomapped virtual address of the given
+ *                      register.
+ */
+#define asic_reg_offset(x)      (register_map->x)
+#define asic_reg_phys_addr(x)   (asic_phy_base + asic_reg_offset(x))
+#define asic_reg_addr(x) \
+        ((unsigned int *) (asic_base + asic_reg_offset(x)))
+
+/*
+ * The asic_reg macro is gone. It should be replaced by either asic_read or
+ * asic_write, as appropriate.
+ */
+
+#define asic_read(x)            readl(asic_reg_addr(x))
+#define asic_write(v, x)        writel(v, asic_reg_addr(x))
+
+extern void asic_irq_init(void);
+#endif
diff --git a/arch/mips/include/asm/mach-powertv/dma-coherence.h b/arch/mips/include/asm/mach-powertv/dma-coherence.h
new file mode 100644
index 000000000000..5b8d5ebeb838
--- /dev/null
+++ b/arch/mips/include/asm/mach-powertv/dma-coherence.h
@@ -0,0 +1,119 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Version from mach-generic modified to support PowerTV port
+ * Portions Copyright (C) 2009  Cisco Systems, Inc.
+ * Copyright (C) 2006  Ralf Baechle <ralf@linux-mips.org>
+ *
+ */
+
+#ifndef __ASM_MACH_POWERTV_DMA_COHERENCE_H
+#define __ASM_MACH_POWERTV_DMA_COHERENCE_H
+
+#include <linux/sched.h>
+#include <linux/version.h>
+#include <linux/device.h>
+#include <asm/mach-powertv/asic.h>
+
+static inline bool is_kseg2(void *addr)
+{
+        return (unsigned long)addr >= KSEG2;
+}
+
+static inline unsigned long virt_to_phys_from_pte(void *addr)
+{
+        pgd_t *pgd;
+        pud_t *pud;
+        pmd_t *pmd;
+        pte_t *ptep, pte;
+
+        unsigned long virt_addr = (unsigned long)addr;
+        unsigned long phys_addr = 0UL;
+
+        /* get the page global directory. */
+        pgd = pgd_offset_k(virt_addr);
+
+        if (!pgd_none(*pgd)) {
+                /* get the page upper directory */
+                pud = pud_offset(pgd, virt_addr);
+                if (!pud_none(*pud)) {
+                        /* get the page middle directory */
+                        pmd = pmd_offset(pud, virt_addr);
+                        if (!pmd_none(*pmd)) {
+                                /* get a pointer to the page table entry */
+                                ptep = pte_offset(pmd, virt_addr);
+                                pte = *ptep;
+                                /* check for a valid page */
+                                if (pte_present(pte)) {
+                                        /* get the physical address the page is
+                                         * refering to */
+                                        phys_addr = (unsigned long)
+                                                page_to_phys(pte_page(pte));
+                                        /* add the offset within the page */
+                                        phys_addr |= (virt_addr & ~PAGE_MASK);
+                                }
+                        }
+                }
+        }
+
+        return phys_addr;
+}
+
+static inline dma_addr_t plat_map_dma_mem(struct device *dev, void *addr,
+        size_t size)
+{
+        if (is_kseg2(addr))
+                return phys_to_bus(virt_to_phys_from_pte(addr));
+        else
+                return phys_to_bus(virt_to_phys(addr));
+}
+
+static inline dma_addr_t plat_map_dma_mem_page(struct device *dev,
+        struct page *page)
+{
+        return phys_to_bus(page_to_phys(page));
+}
+
+static inline unsigned long plat_dma_addr_to_phys(struct device *dev,
+        dma_addr_t dma_addr)
+{
+        return bus_to_phys(dma_addr);
+}
+
+static inline void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr,
+        size_t size, enum dma_data_direction direction)
+{
+}
+
+static inline int plat_dma_supported(struct device *dev, u64 mask)
+{
+        /*
+         * we fall back to GFP_DMA when the mask isn't all 1s,
+         * so we can't guarantee allocations that must be
+         * within a tighter range than GFP_DMA..
+         */
+        if (mask < DMA_BIT_MASK(24))
+                return 0;
+
+        return 1;
+}
+
+static inline void plat_extra_sync_for_device(struct device *dev)
+{
+        return;
+}
+
+static inline int plat_dma_mapping_error(struct device *dev,
+                                         dma_addr_t dma_addr)
+{
+        return 0;
+}
+
+static inline int plat_device_is_coherent(struct device *dev)
+{
+        return 0;
+}
+
+#endif /* __ASM_MACH_POWERTV_DMA_COHERENCE_H */
diff --git a/arch/mips/include/asm/mach-powertv/interrupts.h b/arch/mips/include/asm/mach-powertv/interrupts.h
new file mode 100644
index 000000000000..629a57413657
--- /dev/null
+++ b/arch/mips/include/asm/mach-powertv/interrupts.h
@@ -0,0 +1,254 @@
+/*
+ * Copyright (C) 2009  Cisco Systems, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ */
+
+#ifndef _ASM_MACH_POWERTV_INTERRUPTS_H_
+#define _ASM_MACH_POWERTV_INTERRUPTS_H_
+
+/*
+ * Defines for all of the interrupt lines
+ */
+
+/* Definitions for backward compatibility */
+#define kIrq_Uart1              irq_uart1
+
+#define ibase 0
+
+/*------------- Register: int_stat_3 */
+/* 126 unused (bit 31) */
+#define irq_asc2video           (ibase+126)     /* ASC 2 Video Interrupt */
+#define irq_asc1video           (ibase+125)     /* ASC 1 Video Interrupt */
+#define irq_comms_block_wd      (ibase+124)     /* ASC 1 Video Interrupt */
+#define irq_fdma_mailbox        (ibase+123)     /* FDMA Mailbox Output */
+#define irq_fdma_gp             (ibase+122)     /* FDMA GP Output */
+#define irq_mips_pic            (ibase+121)     /* MIPS Performance Counter
+                                                 * Interrupt */
+#define irq_mips_timer          (ibase+120)     /* MIPS Timer Interrupt */
+#define irq_memory_protect      (ibase+119)     /* Memory Protection Interrupt
+                                                 * -- Ored by glue logic inside
+                                                 *  SPARC ILC (see
+                                                 *  INT_MEM_PROT_STAT, below,
+                                                 *  for individual interrupts)
+                                                 */
+/* 118 unused (bit 22) */
+#define irq_sbag                (ibase+117)     /* SBAG Interrupt -- Ored by
+                                                 * glue logic inside SPARC ILC
+                                                 * (see INT_SBAG_STAT, below,
+                                                 * for individual interrupts) */
+#define irq_qam_b_fec           (ibase+116)     /* QAM  B FEC Interrupt */
+#define irq_qam_a_fec           (ibase+115)     /* QAM A FEC Interrupt */
+/* 114 unused   (bit 18) */
+#define irq_mailbox             (ibase+113)     /* Mailbox Debug Interrupt  --
+                                                 * Ored by glue logic inside
+                                                 * SPARC ILC (see
+                                                 * INT_MAILBOX_STAT, below, for
+                                                 * individual interrupts) */
+#define irq_fuse_stat1          (ibase+112)     /* Fuse Status 1 */
+#define irq_fuse_stat2          (ibase+111)     /* Fuse Status 2 */
+#define irq_fuse_stat3          (ibase+110)     /* Blitter Interrupt / Fuse
+                                                 * Status 3 */
+#define irq_blitter             (ibase+110)     /* Blitter Interrupt / Fuse
+                                                 * Status 3 */
+#define irq_avc1_pp0            (ibase+109)     /* AVC Decoder #1 PP0
+                                                 * Interrupt */
+#define irq_avc1_pp1            (ibase+108)     /* AVC Decoder #1 PP1
+                                                 * Interrupt */
+#define irq_avc1_mbe            (ibase+107)     /* AVC Decoder #1 MBE
+                                                 * Interrupt */
+#define irq_avc2_pp0            (ibase+106)     /* AVC Decoder #2 PP0
+                                                 * Interrupt */
+#define irq_avc2_pp1            (ibase+105)     /* AVC Decoder #2 PP1
+                                                 * Interrupt */
+#define irq_avc2_mbe            (ibase+104)     /* AVC Decoder #2 MBE
+                                                 * Interrupt */
+#define irq_zbug_spi            (ibase+103)     /* Zbug SPI Slave Interrupt */
+#define irq_qam_mod2            (ibase+102)     /* QAM Modulator 2 DMA
+                                                 * Interrupt */
+#define irq_ir_rx               (ibase+101)     /* IR RX 2 Interrupt */
+#define irq_aud_dsp2            (ibase+100)     /* Audio DSP #2 Interrupt */
+#define irq_aud_dsp1            (ibase+99)      /* Audio DSP #1 Interrupt */
+#define irq_docsis              (ibase+98)      /* DOCSIS Debug Interrupt */
+#define irq_sd_dvp1             (ibase+97)      /* SD DVP #1 Interrupt */
+#define irq_sd_dvp2             (ibase+96)      /* SD DVP #2 Interrupt */
+/*------------- Register: int_stat_2 */
+#define irq_hd_dvp              (ibase+95)      /* HD DVP Interrupt */
+#define kIrq_Prewatchdog        (ibase+94)      /* watchdog Pre-Interrupt */
+#define irq_timer2              (ibase+93)      /* Programmable Timer
+                                                 * Interrupt 2 */
+#define irq_1394                (ibase+92)      /* 1394 Firewire Interrupt */
+#define irq_usbohci             (ibase+91)      /* USB 2.0 OHCI Interrupt */
+#define irq_usbehci             (ibase+90)      /* USB 2.0 EHCI Interrupt */
+#define irq_pciexp              (ibase+89)      /* PCI Express 0 Interrupt */
+#define irq_pciexp0             (ibase+89)      /* PCI Express 0 Interrupt */
+#define irq_afe1                (ibase+88)      /* AFE 1 Interrupt */
+#define irq_sata                (ibase+87)      /* SATA 1 Interrupt */
+#define irq_sata1               (ibase+87)      /* SATA 1 Interrupt */
+#define irq_dtcp                (ibase+86)      /* DTCP Interrupt */
+#define irq_pciexp1             (ibase+85)      /* PCI Express 1 Interrupt */
+/* 84 unused    (bit 20) */
+/* 83 unused    (bit 19) */
+/* 82 unused    (bit 18) */
+#define irq_sata2               (ibase+81)      /* SATA2 Interrupt */
+#define irq_uart2               (ibase+80)      /* UART2 Interrupt */
+#define irq_legacy_usb          (ibase+79)      /* Legacy USB Host ISR (1.1
+                                                 * Host module) */
+#define irq_pod                 (ibase+78)      /* POD Interrupt */
+#define irq_slave_usb           (ibase+77)      /* Slave USB */
+#define irq_denc1               (ibase+76)      /* DENC #1 VTG Interrupt */
+#define irq_vbi_vtg             (ibase+75)      /* VBI VTG Interrupt */
+#define irq_afe2                (ibase+74)      /* AFE 2 Interrupt */
+#define irq_denc2               (ibase+73)      /* DENC #2 VTG Interrupt */
+#define irq_asc2                (ibase+72)      /* ASC #2 Interrupt */
+#define irq_asc1                (ibase+71)      /* ASC #1 Interrupt */
+#define irq_mod_dma             (ibase+70)      /* Modulator DMA Interrupt */
+#define irq_byte_eng1           (ibase+69)      /* Byte Engine Interrupt [1] */
+#define irq_byte_eng0           (ibase+68)      /* Byte Engine Interrupt [0] */
+/* 67 unused    (bit 03) */
+/* 66 unused    (bit 02) */
+/* 65 unused    (bit 01) */
+/* 64 unused    (bit 00) */
+/*------------- Register: int_stat_1 */
+/* 63 unused    (bit 31) */
+/* 62 unused    (bit 30) */
+/* 61 unused    (bit 29) */
+/* 60 unused    (bit 28) */
+/* 59 unused    (bit 27) */
+/* 58 unused    (bit 26) */
+/* 57 unused    (bit 25) */
+/* 56 unused    (bit 24) */
+#define irq_buf_dma_mem2mem     (ibase+55)      /* BufDMA Memory to Memory
+                                                 * Interrupt */
+#define irq_buf_dma_usbtransmit (ibase+54)      /* BufDMA USB Transmit
+                                                 * Interrupt */
+#define irq_buf_dma_qpskpodtransmit (ibase+53)  /* BufDMA QPSK/POD Tramsit
+                                                 * Interrupt */
+#define irq_buf_dma_transmit_error (ibase+52)   /* BufDMA Transmit Error
+                                                 * Interrupt */
+#define irq_buf_dma_usbrecv     (ibase+51)      /* BufDMA USB Receive
+                                                 * Interrupt */
+#define irq_buf_dma_qpskpodrecv (ibase+50)      /* BufDMA QPSK/POD Receive
+                                                 * Interrupt */
+#define irq_buf_dma_recv_error  (ibase+49)      /* BufDMA Receive Error
+                                                 * Interrupt */
+#define irq_qamdma_transmit_play (ibase+48)     /* QAMDMA Transmit/Play
+                                                 * Interrupt */
+#define irq_qamdma_transmit_error (ibase+47)    /* QAMDMA Transmit Error
+                                                 * Interrupt */
+#define irq_qamdma_recv2high    (ibase+46)      /* QAMDMA Receive 2 High
+                                                 * (Chans 63-32) */
+#define irq_qamdma_recv2low     (ibase+45)      /* QAMDMA Receive 2 Low
+                                                 * (Chans 31-0) */
+#define irq_qamdma_recv1high    (ibase+44)      /* QAMDMA Receive 1 High
+                                                 * (Chans 63-32) */
+#define irq_qamdma_recv1low     (ibase+43)      /* QAMDMA Receive 1 Low
+                                                 * (Chans 31-0) */
+#define irq_qamdma_recv_error   (ibase+42)      /* QAMDMA Receive Error
+                                                 * Interrupt */
+#define irq_mpegsplice          (ibase+41)      /* MPEG Splice Interrupt */
+#define irq_deinterlace_rdy     (ibase+40)      /* Deinterlacer Frame Ready
+                                                 * Interrupt */
+#define irq_ext_in0             (ibase+39)      /* External Interrupt irq_in0 */
+#define irq_gpio3               (ibase+38)      /* GP I/O IRQ 3 - From GP I/O
+                                                 * Module */
+#define irq_gpio2               (ibase+37)      /* GP I/O IRQ 2 - From GP I/O
+                                                 * Module (ABE_intN) */
+#define irq_pcrcmplt1           (ibase+36)      /* PCR Capture Complete  or
+                                                 * Discontinuity 1 */
+#define irq_pcrcmplt2           (ibase+35)      /* PCR Capture Complete or
+                                                 * Discontinuity 2 */
+#define irq_parse_peierr        (ibase+34)      /* PID Parser Error Detect
+                                                 * (PEI) */
+#define irq_parse_cont_err      (ibase+33)      /* PID Parser continuity error
+                                                 * detect */
+#define irq_ds1framer           (ibase+32)      /* DS1 Framer Interrupt */
+/*------------- Register: int_stat_0 */
+#define irq_gpio1               (ibase+31)      /* GP I/O IRQ 1 - From GP I/O
+                                                 * Module */
+#define irq_gpio0               (ibase+30)      /* GP I/O IRQ 0 - From GP I/O
+                                                 * Module */
+#define irq_qpsk_out_aloha      (ibase+29)      /* QPSK Output Slotted Aloha
+                                                 * (chan 3) Transmission
+                                                 * Completed OK */
+#define irq_qpsk_out_tdma       (ibase+28)      /* QPSK Output TDMA (chan 2)
+                                                 * Transmission Completed OK */
+#define irq_qpsk_out_reserve    (ibase+27)      /* QPSK Output Reservation
+                                                 * (chan 1) Transmission
+                                                 * Completed OK */
+#define irq_qpsk_out_aloha_err  (ibase+26)      /* QPSK Output Slotted Aloha
+                                                 * (chan 3)Transmission
+                                                 * completed with Errors. */
+#define irq_qpsk_out_tdma_err   (ibase+25)      /* QPSK Output TDMA (chan 2)
+                                                 * Transmission completed with
+                                                 * Errors. */
+#define irq_qpsk_out_rsrv_err   (ibase+24)      /* QPSK Output Reservation
+                                                 * (chan 1) Transmission
+                                                 * completed with Errors */
+#define irq_aloha_fail          (ibase+23)      /* Unsuccessful Resend of Aloha
+                                                 * for N times. Aloha retry
+                                                 * timeout for channel 3. */
+#define irq_timer1              (ibase+22)      /* Programmable Timer
+                                                 * Interrupt */
+#define irq_keyboard            (ibase+21)      /* Keyboard Module Interrupt */
+#define irq_i2c                 (ibase+20)      /* I2C Module Interrupt */
+#define irq_spi                 (ibase+19)      /* SPI Module Interrupt */
+#define irq_irblaster           (ibase+18)      /* IR Blaster Interrupt */
+#define irq_splice_detect       (ibase+17)      /* PID Key Change Interrupt or
+                                                 * Splice Detect Interrupt */
+#define irq_se_micro            (ibase+16)      /* Secure Micro I/F Module
+                                                 * Interrupt */
+#define irq_uart1               (ibase+15)      /* UART Interrupt */
+#define irq_irrecv              (ibase+14)      /* IR Receiver Interrupt */
+#define irq_host_int1           (ibase+13)      /* Host-to-Host Interrupt 1 */
+#define irq_host_int0           (ibase+12)      /* Host-to-Host Interrupt 0 */
+#define irq_qpsk_hecerr         (ibase+11)      /* QPSK HEC Error Interrupt */
+#define irq_qpsk_crcerr         (ibase+10)      /* QPSK AAL-5 CRC Error
+                                                 * Interrupt */
+/* 9 unused     (bit 09) */
+/* 8 unused     (bit 08) */
+#define irq_psicrcerr           (ibase+7)       /* QAM PSI CRC Error
+                                                 * Interrupt */
+#define irq_psilength_err       (ibase+6)       /* QAM PSI Length Error
+                                                 * Interrupt */
+#define irq_esfforward          (ibase+5)       /* ESF Interrupt Mark From
+                                                 * Forward Path Reference -
+                                                 * every 3ms when forward Mbits
+                                                 * and forward slot control
+                                                 * bytes are updated. */
+#define irq_esfreverse          (ibase+4)       /* ESF Interrupt Mark from
+                                                 * Reverse Path Reference -
+                                                 * delayed from forward mark by
+                                                 * the ranging delay plus a
+                                                 * fixed amount. When reverse
+                                                 * Mbits and reverse slot
+                                                 * control bytes are updated.
+                                                 * Occurs every 3ms for 3.0M and
+                                                 * 1.554 M upstream rates and
+                                                 * every 6 ms for 256K upstream
+                                                 * rate. */
+#define irq_aloha_timeout       (ibase+3)       /* Slotted-Aloha timeout on
+                                                 * Channel 1. */
+#define irq_reservation         (ibase+2)       /* Partial (or Incremental)
+                                                 * Reservation Message Completed
+                                                 * or Slotted aloha verify for
+                                                 * channel 1. */
+#define irq_aloha3              (ibase+1)       /* Slotted-Aloha Message Verify
+                                                 * Interrupt or Reservation
+                                                 * increment completed for
+                                                 * channel 3. */
+#define irq_mpeg_d              (ibase+0)       /* MPEG Decoder Interrupt */
+#endif  /* _ASM_MACH_POWERTV_INTERRUPTS_H_ */
+
diff --git a/arch/mips/include/asm/mach-powertv/ioremap.h b/arch/mips/include/asm/mach-powertv/ioremap.h
new file mode 100644
index 000000000000..e6276d5146e8
--- /dev/null
+++ b/arch/mips/include/asm/mach-powertv/ioremap.h
@@ -0,0 +1,90 @@
+/*
+ *      This program is free software; you can redistribute it and/or
+ *      modify it under the terms of the GNU General Public License
+ *      as published by the Free Software Foundation; either version
+ *      2 of the License, or (at your option) any later version.
+ *
+ * Portions Copyright (C)  Cisco Systems, Inc.
+ */
+#ifndef __ASM_MACH_POWERTV_IOREMAP_H
+#define __ASM_MACH_POWERTV_IOREMAP_H
+
+#include <linux/types.h>
+
+#define LOW_MEM_BOUNDARY_PHYS   0x20000000
+#define LOW_MEM_BOUNDARY_MASK   (~(LOW_MEM_BOUNDARY_PHYS - 1))
+
+/*
+ * The bus addresses are different than the physical addresses that
+ * the processor sees by an offset. This offset varies by ASIC
+ * version. Define a variable to hold the offset and some macros to
+ * make the conversion simpler. */
+extern unsigned long phys_to_bus_offset;
+
+#ifdef CONFIG_HIGHMEM
+#define MEM_GAP_PHYS            0x60000000
+/*
+ * TODO: We will use the hard code for conversion between physical and
+ * bus until the bootloader releases their device tree to us.
+ */
+#define phys_to_bus(x) (((x) < LOW_MEM_BOUNDARY_PHYS) ? \
+        ((x) + phys_to_bus_offset) : (x))
+#define bus_to_phys(x) (((x) < MEM_GAP_PHYS_ADDR) ? \
+        ((x) - phys_to_bus_offset) : (x))
+#else
+#define phys_to_bus(x) ((x) + phys_to_bus_offset)
+#define bus_to_phys(x) ((x) - phys_to_bus_offset)
+#endif
+
+/*
+ * Determine whether the address we are given is for an ASIC device
+ * Params:  addr    Address to check
+ * Returns: Zero if the address is not for ASIC devices, non-zero
+ *      if it is.
+ */
+static inline int asic_is_device_addr(phys_t addr)
+{
+        return !((phys_t)addr & (phys_t) LOW_MEM_BOUNDARY_MASK);
+}
+
+/*
+ * Determine whether the address we are given is external RAM mappable
+ * into KSEG1.
+ * Params:  addr    Address to check
+ * Returns: Zero if the address is not for external RAM and
+ */
+static inline int asic_is_lowmem_ram_addr(phys_t addr)
+{
+        /*
+         * The RAM always starts at the following address in the processor's
+         * physical address space
+         */
+        static const phys_t phys_ram_base = 0x10000000;
+        phys_t bus_ram_base;
+
+        bus_ram_base = phys_to_bus_offset + phys_ram_base;
+
+        return addr >= bus_ram_base &&
+                addr < (bus_ram_base + (LOW_MEM_BOUNDARY_PHYS - phys_ram_base));
+}
+
+/*
+ * Allow physical addresses to be fixed up to help peripherals located
+ * outside the low 32-bit range -- generic pass-through version.
+ */
+static inline phys_t fixup_bigphys_addr(phys_t phys_addr, phys_t size)
+{
+        return phys_addr;
+}
+
+static inline void __iomem *plat_ioremap(phys_t offset, unsigned long size,
+        unsigned long flags)
+{
+        return NULL;
+}
+
+static inline int plat_iounmap(const volatile void __iomem *addr)
+{
+        return 0;
+}
+#endif /* __ASM_MACH_POWERTV_IOREMAP_H */
diff --git a/arch/mips/include/asm/mach-powertv/irq.h b/arch/mips/include/asm/mach-powertv/irq.h
new file mode 100644
index 000000000000..4bd5d0c61a91
--- /dev/null
+++ b/arch/mips/include/asm/mach-powertv/irq.h
@@ -0,0 +1,25 @@
+/*
+ * Copyright (C) 2009  Cisco Systems, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ */
+
+#ifndef _ASM_MACH_POWERTV_IRQ_H
+#define _ASM_MACH_POWERTV_IRQ_H
+#include <asm/mach-powertv/interrupts.h>
+
+#define MIPS_CPU_IRQ_BASE       ibase
+#define NR_IRQS                 127
+#endif
diff --git a/arch/mips/include/asm/mach-powertv/powertv-clock.h b/arch/mips/include/asm/mach-powertv/powertv-clock.h
new file mode 100644
index 000000000000..6f3e9a0fcf8c
--- /dev/null
+++ b/arch/mips/include/asm/mach-powertv/powertv-clock.h
@@ -0,0 +1,29 @@
+/*
+ * Copyright (C) 2009  Cisco Systems, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ */
+/*
+ * Local definitions for the powertv PCI code
+ */
+
+#ifndef _POWERTV_PCI_POWERTV_PCI_H_
+#define _POWERTV_PCI_POWERTV_PCI_H_
+extern int asic_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin);
+extern int asic_pcie_init(void);
+extern int asic_pcie_init(void);
+
+extern int log_level;
+#endif
diff --git a/arch/mips/include/asm/mach-excite/war.h b/arch/mips/include/asm/mach-powertv/war.h
index 1f82180c1598..7ac05ecc512b 100644
--- a/arch/mips/include/asm/mach-excite/war.h
+++ b/arch/mips/include/asm/mach-powertv/war.h
@@ -3,10 +3,13 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
+ * This version for the PowerTV platform copied from the Malta version.
+ *
  * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
+ * Portions copyright (C) 2009 Cisco Systems, Inc.
  */
-#ifndef __ASM_MIPS_MACH_EXCITE_WAR_H
-#define __ASM_MIPS_MACH_EXCITE_WAR_H
+#ifndef __ASM_MACH_POWERTV_WAR_H
+#define __ASM_MACH_POWERTV_WAR_H
 
 #define R4600_V1_INDEX_ICACHEOP_WAR     0
 #define R4600_V1_HIT_CACHEOP_WAR        0
@@ -14,12 +17,12 @@
 #define R5432_CP0_INTERRUPT_WAR         0
 #define BCM1250_M3_WAR                  0
 #define SIBYTE_1956_WAR                 0
-#define MIPS4K_ICACHE_REFILL_WAR        0
-#define MIPS_CACHE_SYNC_WAR             0
+#define MIPS4K_ICACHE_REFILL_WAR        1
+#define MIPS_CACHE_SYNC_WAR             1
 #define TX49XX_ICACHE_INDEX_INV_WAR     0
-#define RM9000_CDEX_SMP_WAR             1
-#define ICACHE_REFILLS_WORKAROUND_WAR   1
+#define RM9000_CDEX_SMP_WAR             0
+#define ICACHE_REFILLS_WORKAROUND_WAR   1
 #define R10000_LLSC_WAR                 0
-#define MIPS34K_MISSED_ITLB_WAR 0
+#define MIPS34K_MISSED_ITLB_WAR         0
 
-#endif /* __ASM_MIPS_MACH_EXCITE_WAR_H */
+#endif /* __ASM_MACH_POWERTV_WAR_H */
diff --git a/arch/mips/include/asm/mips-boards/bonito64.h b/arch/mips/include/asm/mips-boards/bonito64.h
index a576ce044c3c..d14e2adc4be5 100644
--- a/arch/mips/include/asm/mips-boards/bonito64.h
+++ b/arch/mips/include/asm/mips-boards/bonito64.h
@@ -26,11 +26,6 @@
 /* offsets from base register */
 #define BONITO(x)       (x)
 
-#elif defined(CONFIG_LEMOTE_FULOONG2E)
-
-#define BONITO(x) (*(volatile u32 *)((char *)CKSEG1ADDR(BONITO_REG_BASE) + (x)))
-#define BONITO_IRQ_BASE   32
-
 #else
 
 /*
diff --git a/arch/mips/include/asm/mmu_context.h b/arch/mips/include/asm/mmu_context.h
index 6083db586500..145bb81ccaa5 100644
--- a/arch/mips/include/asm/mmu_context.h
+++ b/arch/mips/include/asm/mmu_context.h
@@ -24,6 +24,33 @@
 #endif /* SMTC */
 #include <asm-generic/mm_hooks.h>
 
+#ifdef CONFIG_MIPS_PGD_C0_CONTEXT
+
+#define TLBMISS_HANDLER_SETUP_PGD(pgd)                          \
+        tlbmiss_handler_setup_pgd((unsigned long)(pgd))
+
+static inline void tlbmiss_handler_setup_pgd(unsigned long pgd)
+{
+        /* Check for swapper_pg_dir and convert to physical address. */
+        if ((pgd & CKSEG3) == CKSEG0)
+                pgd = CPHYSADDR(pgd);
+        write_c0_context(pgd << 11);
+}
+
+#define TLBMISS_HANDLER_SETUP()                                         \
+        do {                                                            \
+                TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir);              \
+                write_c0_xcontext((unsigned long) smp_processor_id() << 51); \
+        } while (0)
+
+
+static inline unsigned long get_current_pgd(void)
+{
+        return PHYS_TO_XKSEG_CACHED((read_c0_context() >> 11) & ~0xfffUL);
+}
+
+#else /* CONFIG_MIPS_PGD_C0_CONTEXT: using  pgd_current*/
+
 /*
  * For the fast tlb miss handlers, we keep a per cpu array of pointers
  * to the current pgd for each processor. Also, the proc. id is stuffed
@@ -46,7 +73,7 @@ extern unsigned long pgd_current[];
         back_to_back_c0_hazard();                                       \
         TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir)
 #endif
-
+#endif /* CONFIG_MIPS_PGD_C0_CONTEXT*/
 #if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
 
 #define ASID_INC        0x40
diff --git a/arch/mips/include/asm/octeon/cvmx-agl-defs.h b/arch/mips/include/asm/octeon/cvmx-agl-defs.h
new file mode 100644
index 000000000000..ec94b9ab7be1
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-agl-defs.h
@@ -0,0 +1,1194 @@
+/***********************license start***************
+ * Author: Cavium Networks
+ *
+ * Contact: support@caviumnetworks.com
+ * This file is part of the OCTEON SDK
+ *
+ * Copyright (c) 2003-2008 Cavium Networks
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful, but
+ * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
+ * NONINFRINGEMENT.  See the GNU General Public License for more
+ * details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this file; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * or visit http://www.gnu.org/licenses/.
+ *
+ * This file may also be available under a different license from Cavium.
+ * Contact Cavium Networks for more information
+ ***********************license end**************************************/
+
+#ifndef __CVMX_AGL_DEFS_H__
+#define __CVMX_AGL_DEFS_H__
+
+#define CVMX_AGL_GMX_BAD_REG \
+         CVMX_ADD_IO_SEG(0x00011800E0000518ull)
+#define CVMX_AGL_GMX_BIST \
+         CVMX_ADD_IO_SEG(0x00011800E0000400ull)
+#define CVMX_AGL_GMX_DRV_CTL \
+         CVMX_ADD_IO_SEG(0x00011800E00007F0ull)
+#define CVMX_AGL_GMX_INF_MODE \
+         CVMX_ADD_IO_SEG(0x00011800E00007F8ull)
+#define CVMX_AGL_GMX_PRTX_CFG(offset) \
+         CVMX_ADD_IO_SEG(0x00011800E0000010ull + (((offset) & 1) * 2048))
+#define CVMX_AGL_GMX_RXX_ADR_CAM0(offset) \
+         CVMX_ADD_IO_SEG(0x00011800E0000180ull + (((offset) & 1) * 2048))
+#define CVMX_AGL_GMX_RXX_ADR_CAM1(offset) \
+         CVMX_ADD_IO_SEG(0x00011800E0000188ull + (((offset) & 1) * 2048))
+#define CVMX_AGL_GMX_RXX_ADR_CAM2(offset) \
+         CVMX_ADD_IO_SEG(0x00011800E0000190ull + (((offset) & 1) * 2048))
+#define CVMX_AGL_GMX_RXX_ADR_CAM3(offset) \
+         CVMX_ADD_IO_SEG(0x00011800E0000198ull + (((offset) & 1) * 2048))
+#define CVMX_AGL_GMX_RXX_ADR_CAM4(offset) \
+         CVMX_ADD_IO_SEG(0x00011800E00001A0ull + (((offset) & 1) * 2048))
+#define CVMX_AGL_GMX_RXX_ADR_CAM5(offset) \
+         CVMX_ADD_IO_SEG(0x00011800E00001A8ull + (((offset) & 1) * 2048))
+#define CVMX_AGL_GMX_RXX_ADR_CAM_EN(offset) \
+         CVMX_ADD_IO_SEG(0x00011800E0000108ull + (((offset) & 1) * 2048))
+#define CVMX_AGL_GMX_RXX_ADR_CTL(offset) \
+         CVMX_ADD_IO_SEG(0x00011800E0000100ull + (((offset) & 1) * 2048))
+#define CVMX_AGL_GMX_RXX_DECISION(offset) \
+         CVMX_ADD_IO_SEG(0x00011800E0000040ull + (((offset) & 1) * 2048))
+#define CVMX_AGL_GMX_RXX_FRM_CHK(offset) \
+         CVMX_ADD_IO_SEG(0x00011800E0000020ull + (((offset) & 1) * 2048))
+#define CVMX_AGL_GMX_RXX_FRM_CTL(offset) \
+         CVMX_ADD_IO_SEG(0x00011800E0000018ull + (((offset) & 1) * 2048))
+#define CVMX_AGL_GMX_RXX_FRM_MAX(offset) \
+         CVMX_ADD_IO_SEG(0x00011800E0000030ull + (((offset) & 1) * 2048))
+#define CVMX_AGL_GMX_RXX_FRM_MIN(offset) \
+         CVMX_ADD_IO_SEG(0x00011800E0000028ull + (((offset) & 1) * 2048))
+#define CVMX_AGL_GMX_RXX_IFG(offset) \
+         CVMX_ADD_IO_SEG(0x00011800E0000058ull + (((offset) & 1) * 2048))
+#define CVMX_AGL_GMX_RXX_INT_EN(offset) \
+         CVMX_ADD_IO_SEG(0x00011800E0000008ull + (((offset) & 1) * 2048))
+#define CVMX_AGL_GMX_RXX_INT_REG(offset) \
+         CVMX_ADD_IO_SEG(0x00011800E0000000ull + (((offset) & 1) * 2048))
+#define CVMX_AGL_GMX_RXX_JABBER(offset) \
+         CVMX_ADD_IO_SEG(0x00011800E0000038ull + (((offset) & 1) * 2048))
+#define CVMX_AGL_GMX_RXX_PAUSE_DROP_TIME(offset) \
+         CVMX_ADD_IO_SEG(0x00011800E0000068ull + (((offset) & 1) * 2048))
+#define CVMX_AGL_GMX_RXX_STATS_CTL(offset) \
+         CVMX_ADD_IO_SEG(0x00011800E0000050ull + (((offset) & 1) * 2048))
+#define CVMX_AGL_GMX_RXX_STATS_OCTS(offset) \
+         CVMX_ADD_IO_SEG(0x00011800E0000088ull + (((offset) & 1) * 2048))
+#define CVMX_AGL_GMX_RXX_STATS_OCTS_CTL(offset) \
+         CVMX_ADD_IO_SEG(0x00011800E0000098ull + (((offset) & 1) * 2048))
+#define CVMX_AGL_GMX_RXX_STATS_OCTS_DMAC(offset) \
+         CVMX_ADD_IO_SEG(0x00011800E00000A8ull + (((offset) & 1) * 2048))
+#define CVMX_AGL_GMX_RXX_STATS_OCTS_DRP(offset) \
+         CVMX_ADD_IO_SEG(0x00011800E00000B8ull + (((offset) & 1) * 2048))
+#define CVMX_AGL_GMX_RXX_STATS_PKTS(offset) \
+         CVMX_ADD_IO_SEG(0x00011800E0000080ull + (((offset) & 1) * 2048))
+#define CVMX_AGL_GMX_RXX_STATS_PKTS_BAD(offset) \
+         CVMX_ADD_IO_SEG(0x00011800E00000C0ull + (((offset) & 1) * 2048))
+#define CVMX_AGL_GMX_RXX_STATS_PKTS_CTL(offset) \
+         CVMX_ADD_IO_SEG(0x00011800E0000090ull + (((offset) & 1) * 2048))
+#define CVMX_AGL_GMX_RXX_STATS_PKTS_DMAC(offset) \
+         CVMX_ADD_IO_SEG(0x00011800E00000A0ull + (((offset) & 1) * 2048))
+#define CVMX_AGL_GMX_RXX_STATS_PKTS_DRP(offset) \
+         CVMX_ADD_IO_SEG(0x00011800E00000B0ull + (((offset) & 1) * 2048))
+#define CVMX_AGL_GMX_RXX_UDD_SKP(offset) \
+         CVMX_ADD_IO_SEG(0x00011800E0000048ull + (((offset) & 1) * 2048))
+#define CVMX_AGL_GMX_RX_BP_DROPX(offset) \
+         CVMX_ADD_IO_SEG(0x00011800E0000420ull + (((offset) & 1) * 8))
+#define CVMX_AGL_GMX_RX_BP_OFFX(offset) \
+         CVMX_ADD_IO_SEG(0x00011800E0000460ull + (((offset) & 1) * 8))
+#define CVMX_AGL_GMX_RX_BP_ONX(offset) \
+         CVMX_ADD_IO_SEG(0x00011800E0000440ull + (((offset) & 1) * 8))
+#define CVMX_AGL_GMX_RX_PRT_INFO \
+         CVMX_ADD_IO_SEG(0x00011800E00004E8ull)
+#define CVMX_AGL_GMX_RX_TX_STATUS \
+         CVMX_ADD_IO_SEG(0x00011800E00007E8ull)
+#define CVMX_AGL_GMX_SMACX(offset) \
+         CVMX_ADD_IO_SEG(0x00011800E0000230ull + (((offset) & 1) * 2048))
+#define CVMX_AGL_GMX_STAT_BP \
+         CVMX_ADD_IO_SEG(0x00011800E0000520ull)
+#define CVMX_AGL_GMX_TXX_APPEND(offset) \
+         CVMX_ADD_IO_SEG(0x00011800E0000218ull + (((offset) & 1) * 2048))
+#define CVMX_AGL_GMX_TXX_CTL(offset) \
+         CVMX_ADD_IO_SEG(0x00011800E0000270ull + (((offset) & 1) * 2048))
+#define CVMX_AGL_GMX_TXX_MIN_PKT(offset) \
+         CVMX_ADD_IO_SEG(0x00011800E0000240ull + (((offset) & 1) * 2048))
+#define CVMX_AGL_GMX_TXX_PAUSE_PKT_INTERVAL(offset) \
+         CVMX_ADD_IO_SEG(0x00011800E0000248ull + (((offset) & 1) * 2048))
+#define CVMX_AGL_GMX_TXX_PAUSE_PKT_TIME(offset) \
+         CVMX_ADD_IO_SEG(0x00011800E0000238ull + (((offset) & 1) * 2048))
+#define CVMX_AGL_GMX_TXX_PAUSE_TOGO(offset) \
+         CVMX_ADD_IO_SEG(0x00011800E0000258ull + (((offset) & 1) * 2048))
+#define CVMX_AGL_GMX_TXX_PAUSE_ZERO(offset) \
+         CVMX_ADD_IO_SEG(0x00011800E0000260ull + (((offset) & 1) * 2048))
+#define CVMX_AGL_GMX_TXX_SOFT_PAUSE(offset) \
+         CVMX_ADD_IO_SEG(0x00011800E0000250ull + (((offset) & 1) * 2048))
+#define CVMX_AGL_GMX_TXX_STAT0(offset) \
+         CVMX_ADD_IO_SEG(0x00011800E0000280ull + (((offset) & 1) * 2048))
+#define CVMX_AGL_GMX_TXX_STAT1(offset) \
+         CVMX_ADD_IO_SEG(0x00011800E0000288ull + (((offset) & 1) * 2048))
+#define CVMX_AGL_GMX_TXX_STAT2(offset) \
+         CVMX_ADD_IO_SEG(0x00011800E0000290ull + (((offset) & 1) * 2048))
+#define CVMX_AGL_GMX_TXX_STAT3(offset) \
+         CVMX_ADD_IO_SEG(0x00011800E0000298ull + (((offset) & 1) * 2048))
+#define CVMX_AGL_GMX_TXX_STAT4(offset) \
+         CVMX_ADD_IO_SEG(0x00011800E00002A0ull + (((offset) & 1) * 2048))
+#define CVMX_AGL_GMX_TXX_STAT5(offset) \
+         CVMX_ADD_IO_SEG(0x00011800E00002A8ull + (((offset) & 1) * 2048))
+#define CVMX_AGL_GMX_TXX_STAT6(offset) \
+         CVMX_ADD_IO_SEG(0x00011800E00002B0ull + (((offset) & 1) * 2048))
+#define CVMX_AGL_GMX_TXX_STAT7(offset) \
+         CVMX_ADD_IO_SEG(0x00011800E00002B8ull + (((offset) & 1) * 2048))
+#define CVMX_AGL_GMX_TXX_STAT8(offset) \
+         CVMX_ADD_IO_SEG(0x00011800E00002C0ull + (((offset) & 1) * 2048))
+#define CVMX_AGL_GMX_TXX_STAT9(offset) \
+         CVMX_ADD_IO_SEG(0x00011800E00002C8ull + (((offset) & 1) * 2048))
+#define CVMX_AGL_GMX_TXX_STATS_CTL(offset) \
+         CVMX_ADD_IO_SEG(0x00011800E0000268ull + (((offset) & 1) * 2048))
+#define CVMX_AGL_GMX_TXX_THRESH(offset) \
+         CVMX_ADD_IO_SEG(0x00011800E0000210ull + (((offset) & 1) * 2048))
+#define CVMX_AGL_GMX_TX_BP \
+         CVMX_ADD_IO_SEG(0x00011800E00004D0ull)
+#define CVMX_AGL_GMX_TX_COL_ATTEMPT \
+         CVMX_ADD_IO_SEG(0x00011800E0000498ull)
+#define CVMX_AGL_GMX_TX_IFG \
+         CVMX_ADD_IO_SEG(0x00011800E0000488ull)
+#define CVMX_AGL_GMX_TX_INT_EN \
+         CVMX_ADD_IO_SEG(0x00011800E0000508ull)
+#define CVMX_AGL_GMX_TX_INT_REG \
+         CVMX_ADD_IO_SEG(0x00011800E0000500ull)
+#define CVMX_AGL_GMX_TX_JAM \
+         CVMX_ADD_IO_SEG(0x00011800E0000490ull)
+#define CVMX_AGL_GMX_TX_LFSR \
+         CVMX_ADD_IO_SEG(0x00011800E00004F8ull)
+#define CVMX_AGL_GMX_TX_OVR_BP \
+         CVMX_ADD_IO_SEG(0x00011800E00004C8ull)
+#define CVMX_AGL_GMX_TX_PAUSE_PKT_DMAC \
+         CVMX_ADD_IO_SEG(0x00011800E00004A0ull)
+#define CVMX_AGL_GMX_TX_PAUSE_PKT_TYPE \
+         CVMX_ADD_IO_SEG(0x00011800E00004A8ull)
+
+union cvmx_agl_gmx_bad_reg {
+        uint64_t u64;
+        struct cvmx_agl_gmx_bad_reg_s {
+                uint64_t reserved_38_63:26;
+                uint64_t txpsh1:1;
+                uint64_t txpop1:1;
+                uint64_t ovrflw1:1;
+                uint64_t txpsh:1;
+                uint64_t txpop:1;
+                uint64_t ovrflw:1;
+                uint64_t reserved_27_31:5;
+                uint64_t statovr:1;
+                uint64_t reserved_23_25:3;
+                uint64_t loststat:1;
+                uint64_t reserved_4_21:18;
+                uint64_t out_ovr:2;
+                uint64_t reserved_0_1:2;
+        } s;
+        struct cvmx_agl_gmx_bad_reg_s cn52xx;
+        struct cvmx_agl_gmx_bad_reg_s cn52xxp1;
+        struct cvmx_agl_gmx_bad_reg_cn56xx {
+                uint64_t reserved_35_63:29;
+                uint64_t txpsh:1;
+                uint64_t txpop:1;
+                uint64_t ovrflw:1;
+                uint64_t reserved_27_31:5;
+                uint64_t statovr:1;
+                uint64_t reserved_23_25:3;
+                uint64_t loststat:1;
+                uint64_t reserved_3_21:19;
+                uint64_t out_ovr:1;
+                uint64_t reserved_0_1:2;
+        } cn56xx;
+        struct cvmx_agl_gmx_bad_reg_cn56xx cn56xxp1;
+};
+
+union cvmx_agl_gmx_bist {
+        uint64_t u64;
+        struct cvmx_agl_gmx_bist_s {
+                uint64_t reserved_10_63:54;
+                uint64_t status:10;
+        } s;
+        struct cvmx_agl_gmx_bist_s cn52xx;
+        struct cvmx_agl_gmx_bist_s cn52xxp1;
+        struct cvmx_agl_gmx_bist_s cn56xx;
+        struct cvmx_agl_gmx_bist_s cn56xxp1;
+};
+
+union cvmx_agl_gmx_drv_ctl {
+        uint64_t u64;
+        struct cvmx_agl_gmx_drv_ctl_s {
+                uint64_t reserved_49_63:15;
+                uint64_t byp_en1:1;
+                uint64_t reserved_45_47:3;
+                uint64_t pctl1:5;
+                uint64_t reserved_37_39:3;
+                uint64_t nctl1:5;
+                uint64_t reserved_17_31:15;
+                uint64_t byp_en:1;
+                uint64_t reserved_13_15:3;
+                uint64_t pctl:5;
+                uint64_t reserved_5_7:3;
+                uint64_t nctl:5;
+        } s;
+        struct cvmx_agl_gmx_drv_ctl_s cn52xx;
+        struct cvmx_agl_gmx_drv_ctl_s cn52xxp1;
+        struct cvmx_agl_gmx_drv_ctl_cn56xx {
+                uint64_t reserved_17_63:47;
+                uint64_t byp_en:1;
+                uint64_t reserved_13_15:3;
+                uint64_t pctl:5;
+                uint64_t reserved_5_7:3;
+                uint64_t nctl:5;
+        } cn56xx;
+        struct cvmx_agl_gmx_drv_ctl_cn56xx cn56xxp1;
+};
+
+union cvmx_agl_gmx_inf_mode {
+        uint64_t u64;
+        struct cvmx_agl_gmx_inf_mode_s {
+                uint64_t reserved_2_63:62;
+                uint64_t en:1;
+                uint64_t reserved_0_0:1;
+        } s;
+        struct cvmx_agl_gmx_inf_mode_s cn52xx;
+        struct cvmx_agl_gmx_inf_mode_s cn52xxp1;
+        struct cvmx_agl_gmx_inf_mode_s cn56xx;
+        struct cvmx_agl_gmx_inf_mode_s cn56xxp1;
+};
+
+union cvmx_agl_gmx_prtx_cfg {
+        uint64_t u64;
+        struct cvmx_agl_gmx_prtx_cfg_s {
+                uint64_t reserved_6_63:58;
+                uint64_t tx_en:1;
+                uint64_t rx_en:1;
+                uint64_t slottime:1;
+                uint64_t duplex:1;
+                uint64_t speed:1;
+                uint64_t en:1;
+        } s;
+        struct cvmx_agl_gmx_prtx_cfg_s cn52xx;
+        struct cvmx_agl_gmx_prtx_cfg_s cn52xxp1;
+        struct cvmx_agl_gmx_prtx_cfg_s cn56xx;
+        struct cvmx_agl_gmx_prtx_cfg_s cn56xxp1;
+};
+
+union cvmx_agl_gmx_rxx_adr_cam0 {
+        uint64_t u64;
+        struct cvmx_agl_gmx_rxx_adr_cam0_s {
+                uint64_t adr:64;
+        } s;
+        struct cvmx_agl_gmx_rxx_adr_cam0_s cn52xx;
+        struct cvmx_agl_gmx_rxx_adr_cam0_s cn52xxp1;
+        struct cvmx_agl_gmx_rxx_adr_cam0_s cn56xx;
+        struct cvmx_agl_gmx_rxx_adr_cam0_s cn56xxp1;
+};
+
+union cvmx_agl_gmx_rxx_adr_cam1 {
+        uint64_t u64;
+        struct cvmx_agl_gmx_rxx_adr_cam1_s {
+                uint64_t adr:64;
+        } s;
+        struct cvmx_agl_gmx_rxx_adr_cam1_s cn52xx;
+        struct cvmx_agl_gmx_rxx_adr_cam1_s cn52xxp1;
+        struct cvmx_agl_gmx_rxx_adr_cam1_s cn56xx;
+        struct cvmx_agl_gmx_rxx_adr_cam1_s cn56xxp1;
+};
+
+union cvmx_agl_gmx_rxx_adr_cam2 {
+        uint64_t u64;
+        struct cvmx_agl_gmx_rxx_adr_cam2_s {
+                uint64_t adr:64;
+        } s;
+        struct cvmx_agl_gmx_rxx_adr_cam2_s cn52xx;
+        struct cvmx_agl_gmx_rxx_adr_cam2_s cn52xxp1;
+        struct cvmx_agl_gmx_rxx_adr_cam2_s cn56xx;
+        struct cvmx_agl_gmx_rxx_adr_cam2_s cn56xxp1;
+};
+
+union cvmx_agl_gmx_rxx_adr_cam3 {
+        uint64_t u64;
+        struct cvmx_agl_gmx_rxx_adr_cam3_s {
+                uint64_t adr:64;
+        } s;
+        struct cvmx_agl_gmx_rxx_adr_cam3_s cn52xx;
+        struct cvmx_agl_gmx_rxx_adr_cam3_s cn52xxp1;
+        struct cvmx_agl_gmx_rxx_adr_cam3_s cn56xx;
+        struct cvmx_agl_gmx_rxx_adr_cam3_s cn56xxp1;
+};
+
+union cvmx_agl_gmx_rxx_adr_cam4 {
+        uint64_t u64;
+        struct cvmx_agl_gmx_rxx_adr_cam4_s {
+                uint64_t adr:64;
+        } s;
+        struct cvmx_agl_gmx_rxx_adr_cam4_s cn52xx;
+        struct cvmx_agl_gmx_rxx_adr_cam4_s cn52xxp1;
+        struct cvmx_agl_gmx_rxx_adr_cam4_s cn56xx;
+        struct cvmx_agl_gmx_rxx_adr_cam4_s cn56xxp1;
+};
+
+union cvmx_agl_gmx_rxx_adr_cam5 {
+        uint64_t u64;
+        struct cvmx_agl_gmx_rxx_adr_cam5_s {
+                uint64_t adr:64;
+        } s;
+        struct cvmx_agl_gmx_rxx_adr_cam5_s cn52xx;
+        struct cvmx_agl_gmx_rxx_adr_cam5_s cn52xxp1;
+        struct cvmx_agl_gmx_rxx_adr_cam5_s cn56xx;
+        struct cvmx_agl_gmx_rxx_adr_cam5_s cn56xxp1;
+};
+
+union cvmx_agl_gmx_rxx_adr_cam_en {
+        uint64_t u64;
+        struct cvmx_agl_gmx_rxx_adr_cam_en_s {
+                uint64_t reserved_8_63:56;
+                uint64_t en:8;
+        } s;
+        struct cvmx_agl_gmx_rxx_adr_cam_en_s cn52xx;
+        struct cvmx_agl_gmx_rxx_adr_cam_en_s cn52xxp1;
+        struct cvmx_agl_gmx_rxx_adr_cam_en_s cn56xx;
+        struct cvmx_agl_gmx_rxx_adr_cam_en_s cn56xxp1;
+};
+
+union cvmx_agl_gmx_rxx_adr_ctl {
+        uint64_t u64;
+        struct cvmx_agl_gmx_rxx_adr_ctl_s {
+                uint64_t reserved_4_63:60;
+                uint64_t cam_mode:1;
+                uint64_t mcst:2;
+                uint64_t bcst:1;
+        } s;
+        struct cvmx_agl_gmx_rxx_adr_ctl_s cn52xx;
+        struct cvmx_agl_gmx_rxx_adr_ctl_s cn52xxp1;
+        struct cvmx_agl_gmx_rxx_adr_ctl_s cn56xx;
+        struct cvmx_agl_gmx_rxx_adr_ctl_s cn56xxp1;
+};
+
+union cvmx_agl_gmx_rxx_decision {
+        uint64_t u64;
+        struct cvmx_agl_gmx_rxx_decision_s {
+                uint64_t reserved_5_63:59;
+                uint64_t cnt:5;
+        } s;
+        struct cvmx_agl_gmx_rxx_decision_s cn52xx;
+        struct cvmx_agl_gmx_rxx_decision_s cn52xxp1;
+        struct cvmx_agl_gmx_rxx_decision_s cn56xx;
+        struct cvmx_agl_gmx_rxx_decision_s cn56xxp1;
+};
+
+union cvmx_agl_gmx_rxx_frm_chk {
+        uint64_t u64;
+        struct cvmx_agl_gmx_rxx_frm_chk_s {
+                uint64_t reserved_9_63:55;
+                uint64_t skperr:1;
+                uint64_t rcverr:1;
+                uint64_t lenerr:1;
+                uint64_t alnerr:1;
+                uint64_t fcserr:1;
+                uint64_t jabber:1;
+                uint64_t maxerr:1;
+                uint64_t reserved_1_1:1;
+                uint64_t minerr:1;
+        } s;
+        struct cvmx_agl_gmx_rxx_frm_chk_s cn52xx;
+        struct cvmx_agl_gmx_rxx_frm_chk_s cn52xxp1;
+        struct cvmx_agl_gmx_rxx_frm_chk_s cn56xx;
+        struct cvmx_agl_gmx_rxx_frm_chk_s cn56xxp1;
+};
+
+union cvmx_agl_gmx_rxx_frm_ctl {
+        uint64_t u64;
+        struct cvmx_agl_gmx_rxx_frm_ctl_s {
+                uint64_t reserved_10_63:54;
+                uint64_t pre_align:1;
+                uint64_t pad_len:1;
+                uint64_t vlan_len:1;
+                uint64_t pre_free:1;
+                uint64_t ctl_smac:1;
+                uint64_t ctl_mcst:1;
+                uint64_t ctl_bck:1;
+                uint64_t ctl_drp:1;
+                uint64_t pre_strp:1;
+                uint64_t pre_chk:1;
+        } s;
+        struct cvmx_agl_gmx_rxx_frm_ctl_s cn52xx;
+        struct cvmx_agl_gmx_rxx_frm_ctl_s cn52xxp1;
+        struct cvmx_agl_gmx_rxx_frm_ctl_s cn56xx;
+        struct cvmx_agl_gmx_rxx_frm_ctl_s cn56xxp1;
+};
+
+union cvmx_agl_gmx_rxx_frm_max {
+        uint64_t u64;
+        struct cvmx_agl_gmx_rxx_frm_max_s {
+                uint64_t reserved_16_63:48;
+                uint64_t len:16;
+        } s;
+        struct cvmx_agl_gmx_rxx_frm_max_s cn52xx;
+        struct cvmx_agl_gmx_rxx_frm_max_s cn52xxp1;
+        struct cvmx_agl_gmx_rxx_frm_max_s cn56xx;
+        struct cvmx_agl_gmx_rxx_frm_max_s cn56xxp1;
+};
+
+union cvmx_agl_gmx_rxx_frm_min {
+        uint64_t u64;
+        struct cvmx_agl_gmx_rxx_frm_min_s {
+                uint64_t reserved_16_63:48;
+                uint64_t len:16;
+        } s;
+        struct cvmx_agl_gmx_rxx_frm_min_s cn52xx;
+        struct cvmx_agl_gmx_rxx_frm_min_s cn52xxp1;
+        struct cvmx_agl_gmx_rxx_frm_min_s cn56xx;
+        struct cvmx_agl_gmx_rxx_frm_min_s cn56xxp1;
+};
+
+union cvmx_agl_gmx_rxx_ifg {
+        uint64_t u64;
+        struct cvmx_agl_gmx_rxx_ifg_s {
+                uint64_t reserved_4_63:60;
+                uint64_t ifg:4;
+        } s;
+        struct cvmx_agl_gmx_rxx_ifg_s cn52xx;
+        struct cvmx_agl_gmx_rxx_ifg_s cn52xxp1;
+        struct cvmx_agl_gmx_rxx_ifg_s cn56xx;
+        struct cvmx_agl_gmx_rxx_ifg_s cn56xxp1;
+};
+
+union cvmx_agl_gmx_rxx_int_en {
+        uint64_t u64;
+        struct cvmx_agl_gmx_rxx_int_en_s {
+                uint64_t reserved_20_63:44;
+                uint64_t pause_drp:1;
+                uint64_t reserved_16_18:3;
+                uint64_t ifgerr:1;
+                uint64_t coldet:1;
+                uint64_t falerr:1;
+                uint64_t rsverr:1;
+                uint64_t pcterr:1;
+                uint64_t ovrerr:1;
+                uint64_t reserved_9_9:1;
+                uint64_t skperr:1;
+                uint64_t rcverr:1;
+                uint64_t lenerr:1;
+                uint64_t alnerr:1;
+                uint64_t fcserr:1;
+                uint64_t jabber:1;
+                uint64_t maxerr:1;
+                uint64_t reserved_1_1:1;
+                uint64_t minerr:1;
+        } s;
+        struct cvmx_agl_gmx_rxx_int_en_s cn52xx;
+        struct cvmx_agl_gmx_rxx_int_en_s cn52xxp1;
+        struct cvmx_agl_gmx_rxx_int_en_s cn56xx;
+        struct cvmx_agl_gmx_rxx_int_en_s cn56xxp1;
+};
+
+union cvmx_agl_gmx_rxx_int_reg {
+        uint64_t u64;
+        struct cvmx_agl_gmx_rxx_int_reg_s {
+                uint64_t reserved_20_63:44;
+                uint64_t pause_drp:1;
+                uint64_t reserved_16_18:3;
+                uint64_t ifgerr:1;
+                uint64_t coldet:1;
+                uint64_t falerr:1;
+                uint64_t rsverr:1;
+                uint64_t pcterr:1;
+                uint64_t ovrerr:1;
+                uint64_t reserved_9_9:1;
+                uint64_t skperr:1;
+                uint64_t rcverr:1;
+                uint64_t lenerr:1;
+                uint64_t alnerr:1;
+                uint64_t fcserr:1;
+                uint64_t jabber:1;
+                uint64_t maxerr:1;
+                uint64_t reserved_1_1:1;
+                uint64_t minerr:1;
+        } s;
+        struct cvmx_agl_gmx_rxx_int_reg_s cn52xx;
+        struct cvmx_agl_gmx_rxx_int_reg_s cn52xxp1;
+        struct cvmx_agl_gmx_rxx_int_reg_s cn56xx;
+        struct cvmx_agl_gmx_rxx_int_reg_s cn56xxp1;
+};
+
+union cvmx_agl_gmx_rxx_jabber {
+        uint64_t u64;
+        struct cvmx_agl_gmx_rxx_jabber_s {
+                uint64_t reserved_16_63:48;
+                uint64_t cnt:16;
+        } s;
+        struct cvmx_agl_gmx_rxx_jabber_s cn52xx;
+        struct cvmx_agl_gmx_rxx_jabber_s cn52xxp1;
+        struct cvmx_agl_gmx_rxx_jabber_s cn56xx;
+        struct cvmx_agl_gmx_rxx_jabber_s cn56xxp1;
+};
+
+union cvmx_agl_gmx_rxx_pause_drop_time {
+        uint64_t u64;
+        struct cvmx_agl_gmx_rxx_pause_drop_time_s {
+                uint64_t reserved_16_63:48;
+                uint64_t status:16;
+        } s;
+        struct cvmx_agl_gmx_rxx_pause_drop_time_s cn52xx;
+        struct cvmx_agl_gmx_rxx_pause_drop_time_s cn52xxp1;
+        struct cvmx_agl_gmx_rxx_pause_drop_time_s cn56xx;
+        struct cvmx_agl_gmx_rxx_pause_drop_time_s cn56xxp1;
+};
+
+union cvmx_agl_gmx_rxx_stats_ctl {
+        uint64_t u64;
+        struct cvmx_agl_gmx_rxx_stats_ctl_s {
+                uint64_t reserved_1_63:63;
+                uint64_t rd_clr:1;
+        } s;
+        struct cvmx_agl_gmx_rxx_stats_ctl_s cn52xx;
+        struct cvmx_agl_gmx_rxx_stats_ctl_s cn52xxp1;
+        struct cvmx_agl_gmx_rxx_stats_ctl_s cn56xx;
+        struct cvmx_agl_gmx_rxx_stats_ctl_s cn56xxp1;
+};
+
+union cvmx_agl_gmx_rxx_stats_octs {
+        uint64_t u64;
+        struct cvmx_agl_gmx_rxx_stats_octs_s {
+                uint64_t reserved_48_63:16;
+                uint64_t cnt:48;
+        } s;
+        struct cvmx_agl_gmx_rxx_stats_octs_s cn52xx;
+        struct cvmx_agl_gmx_rxx_stats_octs_s cn52xxp1;
+        struct cvmx_agl_gmx_rxx_stats_octs_s cn56xx;
+        struct cvmx_agl_gmx_rxx_stats_octs_s cn56xxp1;
+};
+
+union cvmx_agl_gmx_rxx_stats_octs_ctl {
+        uint64_t u64;
+        struct cvmx_agl_gmx_rxx_stats_octs_ctl_s {
+                uint64_t reserved_48_63:16;
+                uint64_t cnt:48;
+        } s;
+        struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn52xx;
+        struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn52xxp1;
+        struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn56xx;
+        struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn56xxp1;
+};
+
+union cvmx_agl_gmx_rxx_stats_octs_dmac {
+        uint64_t u64;
+        struct cvmx_agl_gmx_rxx_stats_octs_dmac_s {
+                uint64_t reserved_48_63:16;
+                uint64_t cnt:48;
+        } s;
+        struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn52xx;
+        struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn52xxp1;
+        struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn56xx;
+        struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn56xxp1;
+};
+
+union cvmx_agl_gmx_rxx_stats_octs_drp {
+        uint64_t u64;
+        struct cvmx_agl_gmx_rxx_stats_octs_drp_s {
+                uint64_t reserved_48_63:16;
+                uint64_t cnt:48;
+        } s;
+        struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn52xx;
+        struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn52xxp1;
+        struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn56xx;
+        struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn56xxp1;
+};
+
+union cvmx_agl_gmx_rxx_stats_pkts {
+        uint64_t u64;
+        struct cvmx_agl_gmx_rxx_stats_pkts_s {
+                uint64_t reserved_32_63:32;
+                uint64_t cnt:32;
+        } s;
+        struct cvmx_agl_gmx_rxx_stats_pkts_s cn52xx;
+        struct cvmx_agl_gmx_rxx_stats_pkts_s cn52xxp1;
+        struct cvmx_agl_gmx_rxx_stats_pkts_s cn56xx;
+        struct cvmx_agl_gmx_rxx_stats_pkts_s cn56xxp1;
+};
+
+union cvmx_agl_gmx_rxx_stats_pkts_bad {
+        uint64_t u64;
+        struct cvmx_agl_gmx_rxx_stats_pkts_bad_s {
+                uint64_t reserved_32_63:32;
+                uint64_t cnt:32;
+        } s;
+        struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn52xx;
+        struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn52xxp1;
+        struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn56xx;
+        struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn56xxp1;
+};
+
+union cvmx_agl_gmx_rxx_stats_pkts_ctl {
+        uint64_t u64;
+        struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s {
+                uint64_t reserved_32_63:32;
+                uint64_t cnt:32;
+        } s;
+        struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn52xx;
+        struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn52xxp1;
+        struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn56xx;
+        struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn56xxp1;
+};
+
+union cvmx_agl_gmx_rxx_stats_pkts_dmac {
+        uint64_t u64;
+        struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s {
+                uint64_t reserved_32_63:32;
+                uint64_t cnt:32;
+        } s;
+        struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn52xx;
+        struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn52xxp1;
+        struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn56xx;
+        struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn56xxp1;
+};
+
+union cvmx_agl_gmx_rxx_stats_pkts_drp {
+        uint64_t u64;
+        struct cvmx_agl_gmx_rxx_stats_pkts_drp_s {
+                uint64_t reserved_32_63:32;
+                uint64_t cnt:32;
+        } s;
+        struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn52xx;
+        struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn52xxp1;
+        struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn56xx;
+        struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn56xxp1;
+};
+
+union cvmx_agl_gmx_rxx_udd_skp {
+        uint64_t u64;
+        struct cvmx_agl_gmx_rxx_udd_skp_s {
+                uint64_t reserved_9_63:55;
+                uint64_t fcssel:1;
+                uint64_t reserved_7_7:1;
+                uint64_t len:7;
+        } s;
+        struct cvmx_agl_gmx_rxx_udd_skp_s cn52xx;
+        struct cvmx_agl_gmx_rxx_udd_skp_s cn52xxp1;
+        struct cvmx_agl_gmx_rxx_udd_skp_s cn56xx;
+        struct cvmx_agl_gmx_rxx_udd_skp_s cn56xxp1;
+};
+
+union cvmx_agl_gmx_rx_bp_dropx {
+        uint64_t u64;
+        struct cvmx_agl_gmx_rx_bp_dropx_s {
+                uint64_t reserved_6_63:58;
+                uint64_t mark:6;
+        } s;
+        struct cvmx_agl_gmx_rx_bp_dropx_s cn52xx;
+        struct cvmx_agl_gmx_rx_bp_dropx_s cn52xxp1;
+        struct cvmx_agl_gmx_rx_bp_dropx_s cn56xx;
+        struct cvmx_agl_gmx_rx_bp_dropx_s cn56xxp1;
+};
+
+union cvmx_agl_gmx_rx_bp_offx {
+        uint64_t u64;
+        struct cvmx_agl_gmx_rx_bp_offx_s {
+                uint64_t reserved_6_63:58;
+                uint64_t mark:6;
+        } s;
+        struct cvmx_agl_gmx_rx_bp_offx_s cn52xx;
+        struct cvmx_agl_gmx_rx_bp_offx_s cn52xxp1;
+        struct cvmx_agl_gmx_rx_bp_offx_s cn56xx;
+        struct cvmx_agl_gmx_rx_bp_offx_s cn56xxp1;
+};
+
+union cvmx_agl_gmx_rx_bp_onx {
+        uint64_t u64;
+        struct cvmx_agl_gmx_rx_bp_onx_s {
+                uint64_t reserved_9_63:55;
+                uint64_t mark:9;
+        } s;
+        struct cvmx_agl_gmx_rx_bp_onx_s cn52xx;
+        struct cvmx_agl_gmx_rx_bp_onx_s cn52xxp1;
+        struct cvmx_agl_gmx_rx_bp_onx_s cn56xx;
+        struct cvmx_agl_gmx_rx_bp_onx_s cn56xxp1;
+};
+
+union cvmx_agl_gmx_rx_prt_info {
+        uint64_t u64;
+        struct cvmx_agl_gmx_rx_prt_info_s {
+                uint64_t reserved_18_63:46;
+                uint64_t drop:2;
+                uint64_t reserved_2_15:14;
+                uint64_t commit:2;
+        } s;
+        struct cvmx_agl_gmx_rx_prt_info_s cn52xx;
+        struct cvmx_agl_gmx_rx_prt_info_s cn52xxp1;
+        struct cvmx_agl_gmx_rx_prt_info_cn56xx {
+                uint64_t reserved_17_63:47;
+                uint64_t drop:1;
+                uint64_t reserved_1_15:15;
+                uint64_t commit:1;
+        } cn56xx;
+        struct cvmx_agl_gmx_rx_prt_info_cn56xx cn56xxp1;
+};
+
+union cvmx_agl_gmx_rx_tx_status {
+        uint64_t u64;
+        struct cvmx_agl_gmx_rx_tx_status_s {
+                uint64_t reserved_6_63:58;
+                uint64_t tx:2;
+                uint64_t reserved_2_3:2;
+                uint64_t rx:2;
+        } s;
+        struct cvmx_agl_gmx_rx_tx_status_s cn52xx;
+        struct cvmx_agl_gmx_rx_tx_status_s cn52xxp1;
+        struct cvmx_agl_gmx_rx_tx_status_cn56xx {
+                uint64_t reserved_5_63:59;
+                uint64_t tx:1;
+                uint64_t reserved_1_3:3;
+                uint64_t rx:1;
+        } cn56xx;
+        struct cvmx_agl_gmx_rx_tx_status_cn56xx cn56xxp1;
+};
+
+union cvmx_agl_gmx_smacx {
+        uint64_t u64;
+        struct cvmx_agl_gmx_smacx_s {
+                uint64_t reserved_48_63:16;
+                uint64_t smac:48;
+        } s;
+        struct cvmx_agl_gmx_smacx_s cn52xx;
+        struct cvmx_agl_gmx_smacx_s cn52xxp1;
+        struct cvmx_agl_gmx_smacx_s cn56xx;
+        struct cvmx_agl_gmx_smacx_s cn56xxp1;
+};
+
+union cvmx_agl_gmx_stat_bp {
+        uint64_t u64;
+        struct cvmx_agl_gmx_stat_bp_s {
+                uint64_t reserved_17_63:47;
+                uint64_t bp:1;
+                uint64_t cnt:16;
+        } s;
+        struct cvmx_agl_gmx_stat_bp_s cn52xx;
+        struct cvmx_agl_gmx_stat_bp_s cn52xxp1;
+        struct cvmx_agl_gmx_stat_bp_s cn56xx;
+        struct cvmx_agl_gmx_stat_bp_s cn56xxp1;
+};
+
+union cvmx_agl_gmx_txx_append {
+        uint64_t u64;
+        struct cvmx_agl_gmx_txx_append_s {
+                uint64_t reserved_4_63:60;
+                uint64_t force_fcs:1;
+                uint64_t fcs:1;
+                uint64_t pad:1;
+                uint64_t preamble:1;
+        } s;
+        struct cvmx_agl_gmx_txx_append_s cn52xx;
+        struct cvmx_agl_gmx_txx_append_s cn52xxp1;
+        struct cvmx_agl_gmx_txx_append_s cn56xx;
+        struct cvmx_agl_gmx_txx_append_s cn56xxp1;
+};
+
+union cvmx_agl_gmx_txx_ctl {
+        uint64_t u64;
+        struct cvmx_agl_gmx_txx_ctl_s {
+                uint64_t reserved_2_63:62;
+                uint64_t xsdef_en:1;
+                uint64_t xscol_en:1;
+        } s;
+        struct cvmx_agl_gmx_txx_ctl_s cn52xx;
+        struct cvmx_agl_gmx_txx_ctl_s cn52xxp1;
+        struct cvmx_agl_gmx_txx_ctl_s cn56xx;
+        struct cvmx_agl_gmx_txx_ctl_s cn56xxp1;
+};
+
+union cvmx_agl_gmx_txx_min_pkt {
+        uint64_t u64;
+        struct cvmx_agl_gmx_txx_min_pkt_s {
+                uint64_t reserved_8_63:56;
+                uint64_t min_size:8;
+        } s;
+        struct cvmx_agl_gmx_txx_min_pkt_s cn52xx;
+        struct cvmx_agl_gmx_txx_min_pkt_s cn52xxp1;
+        struct cvmx_agl_gmx_txx_min_pkt_s cn56xx;
+        struct cvmx_agl_gmx_txx_min_pkt_s cn56xxp1;
+};
+
+union cvmx_agl_gmx_txx_pause_pkt_interval {
+        uint64_t u64;
+        struct cvmx_agl_gmx_txx_pause_pkt_interval_s {
+                uint64_t reserved_16_63:48;
+                uint64_t interval:16;
+        } s;
+        struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn52xx;
+        struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn52xxp1;
+        struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn56xx;
+        struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn56xxp1;
+};
+
+union cvmx_agl_gmx_txx_pause_pkt_time {
+        uint64_t u64;
+        struct cvmx_agl_gmx_txx_pause_pkt_time_s {
+                uint64_t reserved_16_63:48;
+                uint64_t time:16;
+        } s;
+        struct cvmx_agl_gmx_txx_pause_pkt_time_s cn52xx;
+        struct cvmx_agl_gmx_txx_pause_pkt_time_s cn52xxp1;
+        struct cvmx_agl_gmx_txx_pause_pkt_time_s cn56xx;
+        struct cvmx_agl_gmx_txx_pause_pkt_time_s cn56xxp1;
+};
+
+union cvmx_agl_gmx_txx_pause_togo {
+        uint64_t u64;
+        struct cvmx_agl_gmx_txx_pause_togo_s {
+                uint64_t reserved_16_63:48;
+                uint64_t time:16;
+        } s;
+        struct cvmx_agl_gmx_txx_pause_togo_s cn52xx;
+        struct cvmx_agl_gmx_txx_pause_togo_s cn52xxp1;
+        struct cvmx_agl_gmx_txx_pause_togo_s cn56xx;
+        struct cvmx_agl_gmx_txx_pause_togo_s cn56xxp1;
+};
+
+union cvmx_agl_gmx_txx_pause_zero {
+        uint64_t u64;
+        struct cvmx_agl_gmx_txx_pause_zero_s {
+                uint64_t reserved_1_63:63;
+                uint64_t send:1;
+        } s;
+        struct cvmx_agl_gmx_txx_pause_zero_s cn52xx;
+        struct cvmx_agl_gmx_txx_pause_zero_s cn52xxp1;
+        struct cvmx_agl_gmx_txx_pause_zero_s cn56xx;
+        struct cvmx_agl_gmx_txx_pause_zero_s cn56xxp1;
+};
+
+union cvmx_agl_gmx_txx_soft_pause {
+        uint64_t u64;
+        struct cvmx_agl_gmx_txx_soft_pause_s {
+                uint64_t reserved_16_63:48;
+                uint64_t time:16;
+        } s;
+        struct cvmx_agl_gmx_txx_soft_pause_s cn52xx;
+        struct cvmx_agl_gmx_txx_soft_pause_s cn52xxp1;
+        struct cvmx_agl_gmx_txx_soft_pause_s cn56xx;
+        struct cvmx_agl_gmx_txx_soft_pause_s cn56xxp1;
+};
+
+union cvmx_agl_gmx_txx_stat0 {
+        uint64_t u64;
+        struct cvmx_agl_gmx_txx_stat0_s {
+                uint64_t xsdef:32;
+                uint64_t xscol:32;
+        } s;
+        struct cvmx_agl_gmx_txx_stat0_s cn52xx;
+        struct cvmx_agl_gmx_txx_stat0_s cn52xxp1;
+        struct cvmx_agl_gmx_txx_stat0_s cn56xx;
+        struct cvmx_agl_gmx_txx_stat0_s cn56xxp1;
+};
+
+union cvmx_agl_gmx_txx_stat1 {
+        uint64_t u64;
+        struct cvmx_agl_gmx_txx_stat1_s {
+                uint64_t scol:32;
+                uint64_t mcol:32;
+        } s;
+        struct cvmx_agl_gmx_txx_stat1_s cn52xx;
+        struct cvmx_agl_gmx_txx_stat1_s cn52xxp1;
+        struct cvmx_agl_gmx_txx_stat1_s cn56xx;
+        struct cvmx_agl_gmx_txx_stat1_s cn56xxp1;
+};
+
+union cvmx_agl_gmx_txx_stat2 {
+        uint64_t u64;
+        struct cvmx_agl_gmx_txx_stat2_s {
+                uint64_t reserved_48_63:16;
+                uint64_t octs:48;
+        } s;
+        struct cvmx_agl_gmx_txx_stat2_s cn52xx;
+        struct cvmx_agl_gmx_txx_stat2_s cn52xxp1;
+        struct cvmx_agl_gmx_txx_stat2_s cn56xx;
+        struct cvmx_agl_gmx_txx_stat2_s cn56xxp1;
+};
+
+union cvmx_agl_gmx_txx_stat3 {
+        uint64_t u64;
+        struct cvmx_agl_gmx_txx_stat3_s {
+                uint64_t reserved_32_63:32;
+                uint64_t pkts:32;
+        } s;
+        struct cvmx_agl_gmx_txx_stat3_s cn52xx;
+        struct cvmx_agl_gmx_txx_stat3_s cn52xxp1;
+        struct cvmx_agl_gmx_txx_stat3_s cn56xx;
+        struct cvmx_agl_gmx_txx_stat3_s cn56xxp1;
+};
+
+union cvmx_agl_gmx_txx_stat4 {
+        uint64_t u64;
+        struct cvmx_agl_gmx_txx_stat4_s {
+                uint64_t hist1:32;
+                uint64_t hist0:32;
+        } s;
+        struct cvmx_agl_gmx_txx_stat4_s cn52xx;
+        struct cvmx_agl_gmx_txx_stat4_s cn52xxp1;
+        struct cvmx_agl_gmx_txx_stat4_s cn56xx;
+        struct cvmx_agl_gmx_txx_stat4_s cn56xxp1;
+};
+
+union cvmx_agl_gmx_txx_stat5 {
+        uint64_t u64;
+        struct cvmx_agl_gmx_txx_stat5_s {
+                uint64_t hist3:32;
+                uint64_t hist2:32;
+        } s;
+        struct cvmx_agl_gmx_txx_stat5_s cn52xx;
+        struct cvmx_agl_gmx_txx_stat5_s cn52xxp1;
+        struct cvmx_agl_gmx_txx_stat5_s cn56xx;
+        struct cvmx_agl_gmx_txx_stat5_s cn56xxp1;
+};
+
+union cvmx_agl_gmx_txx_stat6 {
+        uint64_t u64;
+        struct cvmx_agl_gmx_txx_stat6_s {
+                uint64_t hist5:32;
+                uint64_t hist4:32;
+        } s;
+        struct cvmx_agl_gmx_txx_stat6_s cn52xx;
+        struct cvmx_agl_gmx_txx_stat6_s cn52xxp1;
+        struct cvmx_agl_gmx_txx_stat6_s cn56xx;
+        struct cvmx_agl_gmx_txx_stat6_s cn56xxp1;
+};
+
+union cvmx_agl_gmx_txx_stat7 {
+        uint64_t u64;
+        struct cvmx_agl_gmx_txx_stat7_s {
+                uint64_t hist7:32;
+                uint64_t hist6:32;
+        } s;
+        struct cvmx_agl_gmx_txx_stat7_s cn52xx;
+        struct cvmx_agl_gmx_txx_stat7_s cn52xxp1;
+        struct cvmx_agl_gmx_txx_stat7_s cn56xx;
+        struct cvmx_agl_gmx_txx_stat7_s cn56xxp1;
+};
+
+union cvmx_agl_gmx_txx_stat8 {
+        uint64_t u64;
+        struct cvmx_agl_gmx_txx_stat8_s {
+                uint64_t mcst:32;
+                uint64_t bcst:32;
+        } s;
+        struct cvmx_agl_gmx_txx_stat8_s cn52xx;
+        struct cvmx_agl_gmx_txx_stat8_s cn52xxp1;
+        struct cvmx_agl_gmx_txx_stat8_s cn56xx;
+        struct cvmx_agl_gmx_txx_stat8_s cn56xxp1;
+};
+
+union cvmx_agl_gmx_txx_stat9 {
+        uint64_t u64;
+        struct cvmx_agl_gmx_txx_stat9_s {
+                uint64_t undflw:32;
+                uint64_t ctl:32;
+        } s;
+        struct cvmx_agl_gmx_txx_stat9_s cn52xx;
+        struct cvmx_agl_gmx_txx_stat9_s cn52xxp1;
+        struct cvmx_agl_gmx_txx_stat9_s cn56xx;
+        struct cvmx_agl_gmx_txx_stat9_s cn56xxp1;
+};
+
+union cvmx_agl_gmx_txx_stats_ctl {
+        uint64_t u64;
+        struct cvmx_agl_gmx_txx_stats_ctl_s {
+                uint64_t reserved_1_63:63;
+                uint64_t rd_clr:1;
+        } s;
+        struct cvmx_agl_gmx_txx_stats_ctl_s cn52xx;
+        struct cvmx_agl_gmx_txx_stats_ctl_s cn52xxp1;
+        struct cvmx_agl_gmx_txx_stats_ctl_s cn56xx;
+        struct cvmx_agl_gmx_txx_stats_ctl_s cn56xxp1;
+};
+
+union cvmx_agl_gmx_txx_thresh {
+        uint64_t u64;
+        struct cvmx_agl_gmx_txx_thresh_s {
+                uint64_t reserved_6_63:58;
+                uint64_t cnt:6;
+        } s;
+        struct cvmx_agl_gmx_txx_thresh_s cn52xx;
+        struct cvmx_agl_gmx_txx_thresh_s cn52xxp1;
+        struct cvmx_agl_gmx_txx_thresh_s cn56xx;
+        struct cvmx_agl_gmx_txx_thresh_s cn56xxp1;
+};
+
+union cvmx_agl_gmx_tx_bp {
+        uint64_t u64;
+        struct cvmx_agl_gmx_tx_bp_s {
+                uint64_t reserved_2_63:62;
+                uint64_t bp:2;
+        } s;
+        struct cvmx_agl_gmx_tx_bp_s cn52xx;
+        struct cvmx_agl_gmx_tx_bp_s cn52xxp1;
+        struct cvmx_agl_gmx_tx_bp_cn56xx {
+                uint64_t reserved_1_63:63;
+                uint64_t bp:1;
+        } cn56xx;
+        struct cvmx_agl_gmx_tx_bp_cn56xx cn56xxp1;
+};
+
+union cvmx_agl_gmx_tx_col_attempt {
+        uint64_t u64;
+        struct cvmx_agl_gmx_tx_col_attempt_s {
+                uint64_t reserved_5_63:59;
+                uint64_t limit:5;
+        } s;
+        struct cvmx_agl_gmx_tx_col_attempt_s cn52xx;
+        struct cvmx_agl_gmx_tx_col_attempt_s cn52xxp1;
+        struct cvmx_agl_gmx_tx_col_attempt_s cn56xx;
+        struct cvmx_agl_gmx_tx_col_attempt_s cn56xxp1;
+};
+
+union cvmx_agl_gmx_tx_ifg {
+        uint64_t u64;
+        struct cvmx_agl_gmx_tx_ifg_s {
+                uint64_t reserved_8_63:56;
+                uint64_t ifg2:4;
+                uint64_t ifg1:4;
+        } s;
+        struct cvmx_agl_gmx_tx_ifg_s cn52xx;
+        struct cvmx_agl_gmx_tx_ifg_s cn52xxp1;
+        struct cvmx_agl_gmx_tx_ifg_s cn56xx;
+        struct cvmx_agl_gmx_tx_ifg_s cn56xxp1;
+};
+
+union cvmx_agl_gmx_tx_int_en {
+        uint64_t u64;
+        struct cvmx_agl_gmx_tx_int_en_s {
+                uint64_t reserved_18_63:46;
+                uint64_t late_col:2;
+                uint64_t reserved_14_15:2;
+                uint64_t xsdef:2;
+                uint64_t reserved_10_11:2;
+                uint64_t xscol:2;
+                uint64_t reserved_4_7:4;
+                uint64_t undflw:2;
+                uint64_t reserved_1_1:1;
+                uint64_t pko_nxa:1;
+        } s;
+        struct cvmx_agl_gmx_tx_int_en_s cn52xx;
+        struct cvmx_agl_gmx_tx_int_en_s cn52xxp1;
+        struct cvmx_agl_gmx_tx_int_en_cn56xx {
+                uint64_t reserved_17_63:47;
+                uint64_t late_col:1;
+                uint64_t reserved_13_15:3;
+                uint64_t xsdef:1;
+                uint64_t reserved_9_11:3;
+                uint64_t xscol:1;
+                uint64_t reserved_3_7:5;
+                uint64_t undflw:1;
+                uint64_t reserved_1_1:1;
+                uint64_t pko_nxa:1;
+        } cn56xx;
+        struct cvmx_agl_gmx_tx_int_en_cn56xx cn56xxp1;
+};
+
+union cvmx_agl_gmx_tx_int_reg {
+        uint64_t u64;
+        struct cvmx_agl_gmx_tx_int_reg_s {
+                uint64_t reserved_18_63:46;
+                uint64_t late_col:2;
+                uint64_t reserved_14_15:2;
+                uint64_t xsdef:2;
+                uint64_t reserved_10_11:2;
+                uint64_t xscol:2;
+                uint64_t reserved_4_7:4;
+                uint64_t undflw:2;
+                uint64_t reserved_1_1:1;
+                uint64_t pko_nxa:1;
+        } s;
+        struct cvmx_agl_gmx_tx_int_reg_s cn52xx;
+        struct cvmx_agl_gmx_tx_int_reg_s cn52xxp1;
+        struct cvmx_agl_gmx_tx_int_reg_cn56xx {
+                uint64_t reserved_17_63:47;
+                uint64_t late_col:1;
+                uint64_t reserved_13_15:3;
+                uint64_t xsdef:1;
+                uint64_t reserved_9_11:3;
+                uint64_t xscol:1;
+                uint64_t reserved_3_7:5;
+                uint64_t undflw:1;
+                uint64_t reserved_1_1:1;
+                uint64_t pko_nxa:1;
+        } cn56xx;
+        struct cvmx_agl_gmx_tx_int_reg_cn56xx cn56xxp1;
+};
+
+union cvmx_agl_gmx_tx_jam {
+        uint64_t u64;
+        struct cvmx_agl_gmx_tx_jam_s {
+                uint64_t reserved_8_63:56;
+                uint64_t jam:8;
+        } s;
+        struct cvmx_agl_gmx_tx_jam_s cn52xx;
+        struct cvmx_agl_gmx_tx_jam_s cn52xxp1;
+        struct cvmx_agl_gmx_tx_jam_s cn56xx;
+        struct cvmx_agl_gmx_tx_jam_s cn56xxp1;
+};
+
+union cvmx_agl_gmx_tx_lfsr {
+        uint64_t u64;
+        struct cvmx_agl_gmx_tx_lfsr_s {
+                uint64_t reserved_16_63:48;
+                uint64_t lfsr:16;
+        } s;
+        struct cvmx_agl_gmx_tx_lfsr_s cn52xx;
+        struct cvmx_agl_gmx_tx_lfsr_s cn52xxp1;
+        struct cvmx_agl_gmx_tx_lfsr_s cn56xx;
+        struct cvmx_agl_gmx_tx_lfsr_s cn56xxp1;
+};
+
+union cvmx_agl_gmx_tx_ovr_bp {
+        uint64_t u64;
+        struct cvmx_agl_gmx_tx_ovr_bp_s {
+                uint64_t reserved_10_63:54;
+                uint64_t en:2;
+                uint64_t reserved_6_7:2;
+                uint64_t bp:2;
+                uint64_t reserved_2_3:2;
+                uint64_t ign_full:2;
+        } s;
+        struct cvmx_agl_gmx_tx_ovr_bp_s cn52xx;
+        struct cvmx_agl_gmx_tx_ovr_bp_s cn52xxp1;
+        struct cvmx_agl_gmx_tx_ovr_bp_cn56xx {
+                uint64_t reserved_9_63:55;
+                uint64_t en:1;
+                uint64_t reserved_5_7:3;
+                uint64_t bp:1;
+                uint64_t reserved_1_3:3;
+                uint64_t ign_full:1;
+        } cn56xx;
+        struct cvmx_agl_gmx_tx_ovr_bp_cn56xx cn56xxp1;
+};
+
+union cvmx_agl_gmx_tx_pause_pkt_dmac {
+        uint64_t u64;
+        struct cvmx_agl_gmx_tx_pause_pkt_dmac_s {
+                uint64_t reserved_48_63:16;
+                uint64_t dmac:48;
+        } s;
+        struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn52xx;
+        struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn52xxp1;
+        struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn56xx;
+        struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn56xxp1;
+};
+
+union cvmx_agl_gmx_tx_pause_pkt_type {
+        uint64_t u64;
+        struct cvmx_agl_gmx_tx_pause_pkt_type_s {
+                uint64_t reserved_16_63:48;
+                uint64_t type:16;
+        } s;
+        struct cvmx_agl_gmx_tx_pause_pkt_type_s cn52xx;
+        struct cvmx_agl_gmx_tx_pause_pkt_type_s cn52xxp1;
+        struct cvmx_agl_gmx_tx_pause_pkt_type_s cn56xx;
+        struct cvmx_agl_gmx_tx_pause_pkt_type_s cn56xxp1;
+};
+
+#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-mixx-defs.h b/arch/mips/include/asm/octeon/cvmx-mixx-defs.h
new file mode 100644
index 000000000000..dab6dca492f9
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-mixx-defs.h
@@ -0,0 +1,248 @@
+/***********************license start***************
+ * Author: Cavium Networks
+ *
+ * Contact: support@caviumnetworks.com
+ * This file is part of the OCTEON SDK
+ *
+ * Copyright (c) 2003-2008 Cavium Networks
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful, but
+ * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
+ * NONINFRINGEMENT.  See the GNU General Public License for more
+ * details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this file; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * or visit http://www.gnu.org/licenses/.
+ *
+ * This file may also be available under a different license from Cavium.
+ * Contact Cavium Networks for more information
+ ***********************license end**************************************/
+
+#ifndef __CVMX_MIXX_DEFS_H__
+#define __CVMX_MIXX_DEFS_H__
+
+#define CVMX_MIXX_BIST(offset) \
+         CVMX_ADD_IO_SEG(0x0001070000100078ull + (((offset) & 1) * 2048))
+#define CVMX_MIXX_CTL(offset) \
+         CVMX_ADD_IO_SEG(0x0001070000100020ull + (((offset) & 1) * 2048))
+#define CVMX_MIXX_INTENA(offset) \
+         CVMX_ADD_IO_SEG(0x0001070000100050ull + (((offset) & 1) * 2048))
+#define CVMX_MIXX_IRCNT(offset) \
+         CVMX_ADD_IO_SEG(0x0001070000100030ull + (((offset) & 1) * 2048))
+#define CVMX_MIXX_IRHWM(offset) \
+         CVMX_ADD_IO_SEG(0x0001070000100028ull + (((offset) & 1) * 2048))
+#define CVMX_MIXX_IRING1(offset) \
+         CVMX_ADD_IO_SEG(0x0001070000100010ull + (((offset) & 1) * 2048))
+#define CVMX_MIXX_IRING2(offset) \
+         CVMX_ADD_IO_SEG(0x0001070000100018ull + (((offset) & 1) * 2048))
+#define CVMX_MIXX_ISR(offset) \
+         CVMX_ADD_IO_SEG(0x0001070000100048ull + (((offset) & 1) * 2048))
+#define CVMX_MIXX_ORCNT(offset) \
+         CVMX_ADD_IO_SEG(0x0001070000100040ull + (((offset) & 1) * 2048))
+#define CVMX_MIXX_ORHWM(offset) \
+         CVMX_ADD_IO_SEG(0x0001070000100038ull + (((offset) & 1) * 2048))
+#define CVMX_MIXX_ORING1(offset) \
+         CVMX_ADD_IO_SEG(0x0001070000100000ull + (((offset) & 1) * 2048))
+#define CVMX_MIXX_ORING2(offset) \
+         CVMX_ADD_IO_SEG(0x0001070000100008ull + (((offset) & 1) * 2048))
+#define CVMX_MIXX_REMCNT(offset) \
+         CVMX_ADD_IO_SEG(0x0001070000100058ull + (((offset) & 1) * 2048))
+
+union cvmx_mixx_bist {
+        uint64_t u64;
+        struct cvmx_mixx_bist_s {
+                uint64_t reserved_4_63:60;
+                uint64_t mrqdat:1;
+                uint64_t ipfdat:1;
+                uint64_t irfdat:1;
+                uint64_t orfdat:1;
+        } s;
+        struct cvmx_mixx_bist_s cn52xx;
+        struct cvmx_mixx_bist_s cn52xxp1;
+        struct cvmx_mixx_bist_s cn56xx;
+        struct cvmx_mixx_bist_s cn56xxp1;
+};
+
+union cvmx_mixx_ctl {
+        uint64_t u64;
+        struct cvmx_mixx_ctl_s {
+                uint64_t reserved_8_63:56;
+                uint64_t crc_strip:1;
+                uint64_t busy:1;
+                uint64_t en:1;
+                uint64_t reset:1;
+                uint64_t lendian:1;
+                uint64_t nbtarb:1;
+                uint64_t mrq_hwm:2;
+        } s;
+        struct cvmx_mixx_ctl_s cn52xx;
+        struct cvmx_mixx_ctl_s cn52xxp1;
+        struct cvmx_mixx_ctl_s cn56xx;
+        struct cvmx_mixx_ctl_s cn56xxp1;
+};
+
+union cvmx_mixx_intena {
+        uint64_t u64;
+        struct cvmx_mixx_intena_s {
+                uint64_t reserved_7_63:57;
+                uint64_t orunena:1;
+                uint64_t irunena:1;
+                uint64_t data_drpena:1;
+                uint64_t ithena:1;
+                uint64_t othena:1;
+                uint64_t ivfena:1;
+                uint64_t ovfena:1;
+        } s;
+        struct cvmx_mixx_intena_s cn52xx;
+        struct cvmx_mixx_intena_s cn52xxp1;
+        struct cvmx_mixx_intena_s cn56xx;
+        struct cvmx_mixx_intena_s cn56xxp1;
+};
+
+union cvmx_mixx_ircnt {
+        uint64_t u64;
+        struct cvmx_mixx_ircnt_s {
+                uint64_t reserved_20_63:44;
+                uint64_t ircnt:20;
+        } s;
+        struct cvmx_mixx_ircnt_s cn52xx;
+        struct cvmx_mixx_ircnt_s cn52xxp1;
+        struct cvmx_mixx_ircnt_s cn56xx;
+        struct cvmx_mixx_ircnt_s cn56xxp1;
+};
+
+union cvmx_mixx_irhwm {
+        uint64_t u64;
+        struct cvmx_mixx_irhwm_s {
+                uint64_t reserved_40_63:24;
+                uint64_t ibplwm:20;
+                uint64_t irhwm:20;
+        } s;
+        struct cvmx_mixx_irhwm_s cn52xx;
+        struct cvmx_mixx_irhwm_s cn52xxp1;
+        struct cvmx_mixx_irhwm_s cn56xx;
+        struct cvmx_mixx_irhwm_s cn56xxp1;
+};
+
+union cvmx_mixx_iring1 {
+        uint64_t u64;
+        struct cvmx_mixx_iring1_s {
+                uint64_t reserved_60_63:4;
+                uint64_t isize:20;
+                uint64_t reserved_36_39:4;
+                uint64_t ibase:33;
+                uint64_t reserved_0_2:3;
+        } s;
+        struct cvmx_mixx_iring1_s cn52xx;
+        struct cvmx_mixx_iring1_s cn52xxp1;
+        struct cvmx_mixx_iring1_s cn56xx;
+        struct cvmx_mixx_iring1_s cn56xxp1;
+};
+
+union cvmx_mixx_iring2 {
+        uint64_t u64;
+        struct cvmx_mixx_iring2_s {
+                uint64_t reserved_52_63:12;
+                uint64_t itlptr:20;
+                uint64_t reserved_20_31:12;
+                uint64_t idbell:20;
+        } s;
+        struct cvmx_mixx_iring2_s cn52xx;
+        struct cvmx_mixx_iring2_s cn52xxp1;
+        struct cvmx_mixx_iring2_s cn56xx;
+        struct cvmx_mixx_iring2_s cn56xxp1;
+};
+
+union cvmx_mixx_isr {
+        uint64_t u64;
+        struct cvmx_mixx_isr_s {
+                uint64_t reserved_7_63:57;
+                uint64_t orun:1;
+                uint64_t irun:1;
+                uint64_t data_drp:1;
+                uint64_t irthresh:1;
+                uint64_t orthresh:1;
+                uint64_t idblovf:1;
+                uint64_t odblovf:1;
+        } s;
+        struct cvmx_mixx_isr_s cn52xx;
+        struct cvmx_mixx_isr_s cn52xxp1;
+        struct cvmx_mixx_isr_s cn56xx;
+        struct cvmx_mixx_isr_s cn56xxp1;
+};
+
+union cvmx_mixx_orcnt {
+        uint64_t u64;
+        struct cvmx_mixx_orcnt_s {
+                uint64_t reserved_20_63:44;
+                uint64_t orcnt:20;
+        } s;
+        struct cvmx_mixx_orcnt_s cn52xx;
+        struct cvmx_mixx_orcnt_s cn52xxp1;
+        struct cvmx_mixx_orcnt_s cn56xx;
+        struct cvmx_mixx_orcnt_s cn56xxp1;
+};
+
+union cvmx_mixx_orhwm {
+        uint64_t u64;
+        struct cvmx_mixx_orhwm_s {
+                uint64_t reserved_20_63:44;
+                uint64_t orhwm:20;
+        } s;
+        struct cvmx_mixx_orhwm_s cn52xx;
+        struct cvmx_mixx_orhwm_s cn52xxp1;
+        struct cvmx_mixx_orhwm_s cn56xx;
+        struct cvmx_mixx_orhwm_s cn56xxp1;
+};
+
+union cvmx_mixx_oring1 {
+        uint64_t u64;
+        struct cvmx_mixx_oring1_s {
+                uint64_t reserved_60_63:4;
+                uint64_t osize:20;
+                uint64_t reserved_36_39:4;
+                uint64_t obase:33;
+                uint64_t reserved_0_2:3;
+        } s;
+        struct cvmx_mixx_oring1_s cn52xx;
+        struct cvmx_mixx_oring1_s cn52xxp1;
+        struct cvmx_mixx_oring1_s cn56xx;
+        struct cvmx_mixx_oring1_s cn56xxp1;
+};
+
+union cvmx_mixx_oring2 {
+        uint64_t u64;
+        struct cvmx_mixx_oring2_s {
+                uint64_t reserved_52_63:12;
+                uint64_t otlptr:20;
+                uint64_t reserved_20_31:12;
+                uint64_t odbell:20;
+        } s;
+        struct cvmx_mixx_oring2_s cn52xx;
+        struct cvmx_mixx_oring2_s cn52xxp1;
+        struct cvmx_mixx_oring2_s cn56xx;
+        struct cvmx_mixx_oring2_s cn56xxp1;
+};
+
+union cvmx_mixx_remcnt {
+        uint64_t u64;
+        struct cvmx_mixx_remcnt_s {
+                uint64_t reserved_52_63:12;
+                uint64_t iremcnt:20;
+                uint64_t reserved_20_31:12;
+                uint64_t oremcnt:20;
+        } s;
+        struct cvmx_mixx_remcnt_s cn52xx;
+        struct cvmx_mixx_remcnt_s cn52xxp1;
+        struct cvmx_mixx_remcnt_s cn56xx;
+        struct cvmx_mixx_remcnt_s cn56xxp1;
+};
+
+#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-smix-defs.h b/arch/mips/include/asm/octeon/cvmx-smix-defs.h
new file mode 100644
index 000000000000..9ae45fcbe3e3
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-smix-defs.h
@@ -0,0 +1,178 @@
+/***********************license start***************
+ * Author: Cavium Networks
+ *
+ * Contact: support@caviumnetworks.com
+ * This file is part of the OCTEON SDK
+ *
+ * Copyright (c) 2003-2008 Cavium Networks
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful, but
+ * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
+ * NONINFRINGEMENT.  See the GNU General Public License for more
+ * details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this file; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * or visit http://www.gnu.org/licenses/.
+ *
+ * This file may also be available under a different license from Cavium.
+ * Contact Cavium Networks for more information
+ ***********************license end**************************************/
+
+#ifndef __CVMX_SMIX_DEFS_H__
+#define __CVMX_SMIX_DEFS_H__
+
+#define CVMX_SMIX_CLK(offset) \
+         CVMX_ADD_IO_SEG(0x0001180000001818ull + (((offset) & 1) * 256))
+#define CVMX_SMIX_CMD(offset) \
+         CVMX_ADD_IO_SEG(0x0001180000001800ull + (((offset) & 1) * 256))
+#define CVMX_SMIX_EN(offset) \
+         CVMX_ADD_IO_SEG(0x0001180000001820ull + (((offset) & 1) * 256))
+#define CVMX_SMIX_RD_DAT(offset) \
+         CVMX_ADD_IO_SEG(0x0001180000001810ull + (((offset) & 1) * 256))
+#define CVMX_SMIX_WR_DAT(offset) \
+         CVMX_ADD_IO_SEG(0x0001180000001808ull + (((offset) & 1) * 256))
+
+union cvmx_smix_clk {
+        uint64_t u64;
+        struct cvmx_smix_clk_s {
+                uint64_t reserved_25_63:39;
+                uint64_t mode:1;
+                uint64_t reserved_21_23:3;
+                uint64_t sample_hi:5;
+                uint64_t sample_mode:1;
+                uint64_t reserved_14_14:1;
+                uint64_t clk_idle:1;
+                uint64_t preamble:1;
+                uint64_t sample:4;
+                uint64_t phase:8;
+        } s;
+        struct cvmx_smix_clk_cn30xx {
+                uint64_t reserved_21_63:43;
+                uint64_t sample_hi:5;
+                uint64_t reserved_14_15:2;
+                uint64_t clk_idle:1;
+                uint64_t preamble:1;
+                uint64_t sample:4;
+                uint64_t phase:8;
+        } cn30xx;
+        struct cvmx_smix_clk_cn30xx cn31xx;
+        struct cvmx_smix_clk_cn30xx cn38xx;
+        struct cvmx_smix_clk_cn30xx cn38xxp2;
+        struct cvmx_smix_clk_cn50xx {
+                uint64_t reserved_25_63:39;
+                uint64_t mode:1;
+                uint64_t reserved_21_23:3;
+                uint64_t sample_hi:5;
+                uint64_t reserved_14_15:2;
+                uint64_t clk_idle:1;
+                uint64_t preamble:1;
+                uint64_t sample:4;
+                uint64_t phase:8;
+        } cn50xx;
+        struct cvmx_smix_clk_s cn52xx;
+        struct cvmx_smix_clk_cn50xx cn52xxp1;
+        struct cvmx_smix_clk_s cn56xx;
+        struct cvmx_smix_clk_cn50xx cn56xxp1;
+        struct cvmx_smix_clk_cn30xx cn58xx;
+        struct cvmx_smix_clk_cn30xx cn58xxp1;
+};
+
+union cvmx_smix_cmd {
+        uint64_t u64;
+        struct cvmx_smix_cmd_s {
+                uint64_t reserved_18_63:46;
+                uint64_t phy_op:2;
+                uint64_t reserved_13_15:3;
+                uint64_t phy_adr:5;
+                uint64_t reserved_5_7:3;
+                uint64_t reg_adr:5;
+        } s;
+        struct cvmx_smix_cmd_cn30xx {
+                uint64_t reserved_17_63:47;
+                uint64_t phy_op:1;
+                uint64_t reserved_13_15:3;
+                uint64_t phy_adr:5;
+                uint64_t reserved_5_7:3;
+                uint64_t reg_adr:5;
+        } cn30xx;
+        struct cvmx_smix_cmd_cn30xx cn31xx;
+        struct cvmx_smix_cmd_cn30xx cn38xx;
+        struct cvmx_smix_cmd_cn30xx cn38xxp2;
+        struct cvmx_smix_cmd_s cn50xx;
+        struct cvmx_smix_cmd_s cn52xx;
+        struct cvmx_smix_cmd_s cn52xxp1;
+        struct cvmx_smix_cmd_s cn56xx;
+        struct cvmx_smix_cmd_s cn56xxp1;
+        struct cvmx_smix_cmd_cn30xx cn58xx;
+        struct cvmx_smix_cmd_cn30xx cn58xxp1;
+};
+
+union cvmx_smix_en {
+        uint64_t u64;
+        struct cvmx_smix_en_s {
+                uint64_t reserved_1_63:63;
+                uint64_t en:1;
+        } s;
+        struct cvmx_smix_en_s cn30xx;
+        struct cvmx_smix_en_s cn31xx;
+        struct cvmx_smix_en_s cn38xx;
+        struct cvmx_smix_en_s cn38xxp2;
+        struct cvmx_smix_en_s cn50xx;
+        struct cvmx_smix_en_s cn52xx;
+        struct cvmx_smix_en_s cn52xxp1;
+        struct cvmx_smix_en_s cn56xx;
+        struct cvmx_smix_en_s cn56xxp1;
+        struct cvmx_smix_en_s cn58xx;
+        struct cvmx_smix_en_s cn58xxp1;
+};
+
+union cvmx_smix_rd_dat {
+        uint64_t u64;
+        struct cvmx_smix_rd_dat_s {
+                uint64_t reserved_18_63:46;
+                uint64_t pending:1;
+                uint64_t val:1;
+                uint64_t dat:16;
+        } s;
+        struct cvmx_smix_rd_dat_s cn30xx;
+        struct cvmx_smix_rd_dat_s cn31xx;
+        struct cvmx_smix_rd_dat_s cn38xx;
+        struct cvmx_smix_rd_dat_s cn38xxp2;
+        struct cvmx_smix_rd_dat_s cn50xx;
+        struct cvmx_smix_rd_dat_s cn52xx;
+        struct cvmx_smix_rd_dat_s cn52xxp1;
+        struct cvmx_smix_rd_dat_s cn56xx;
+        struct cvmx_smix_rd_dat_s cn56xxp1;
+        struct cvmx_smix_rd_dat_s cn58xx;
+        struct cvmx_smix_rd_dat_s cn58xxp1;
+};
+
+union cvmx_smix_wr_dat {
+        uint64_t u64;
+        struct cvmx_smix_wr_dat_s {
+                uint64_t reserved_18_63:46;
+                uint64_t pending:1;
+                uint64_t val:1;
+                uint64_t dat:16;
+        } s;
+        struct cvmx_smix_wr_dat_s cn30xx;
+        struct cvmx_smix_wr_dat_s cn31xx;
+        struct cvmx_smix_wr_dat_s cn38xx;
+        struct cvmx_smix_wr_dat_s cn38xxp2;
+        struct cvmx_smix_wr_dat_s cn50xx;
+        struct cvmx_smix_wr_dat_s cn52xx;
+        struct cvmx_smix_wr_dat_s cn52xxp1;
+        struct cvmx_smix_wr_dat_s cn56xx;
+        struct cvmx_smix_wr_dat_s cn56xxp1;
+        struct cvmx_smix_wr_dat_s cn58xx;
+        struct cvmx_smix_wr_dat_s cn58xxp1;
+};
+
+#endif
diff --git a/arch/mips/include/asm/octeon/octeon.h b/arch/mips/include/asm/octeon/octeon.h
index cac9b1a206fc..4d0a8c61fc3e 100644
--- a/arch/mips/include/asm/octeon/octeon.h
+++ b/arch/mips/include/asm/octeon/octeon.h
@@ -47,6 +47,7 @@ struct octeon_cop2_state;
 extern unsigned long octeon_crypto_enable(struct octeon_cop2_state *state);
 extern void octeon_crypto_disable(struct octeon_cop2_state *state,
                                   unsigned long flags);
+extern asmlinkage void octeon_cop2_restore(struct octeon_cop2_state *task);
 
 extern void octeon_init_cvmcount(void);
 
diff --git a/arch/mips/include/asm/pgtable.h b/arch/mips/include/asm/pgtable.h
index d6eb6134abec..1854336e56a2 100644
--- a/arch/mips/include/asm/pgtable.h
+++ b/arch/mips/include/asm/pgtable.h
@@ -390,6 +390,19 @@ static inline int io_remap_pfn_range(struct vm_area_struct *vma,
 #include <asm-generic/pgtable.h>
 
 /*
+ * uncached accelerated TLB map for video memory access
+ */
+#ifdef CONFIG_CPU_SUPPORTS_UNCACHED_ACCELERATED
+#define __HAVE_PHYS_MEM_ACCESS_PROT
+
+struct file;
+pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
+                unsigned long size, pgprot_t vma_prot);
+int phys_mem_access_prot_allowed(struct file *file, unsigned long pfn,
+                unsigned long size, pgprot_t *vma_prot);
+#endif
+
+/*
  * We provide our own get_unmapped area to cope with the virtual aliasing
  * constraints placed on us by the cache architecture.
  */
diff --git a/arch/mips/include/asm/sgialib.h b/arch/mips/include/asm/sgialib.h
index bfce5c786f1c..63741ca1e422 100644
--- a/arch/mips/include/asm/sgialib.h
+++ b/arch/mips/include/asm/sgialib.h
@@ -85,8 +85,7 @@ extern void prom_identify_arch(void);
 extern PCHAR ArcGetEnvironmentVariable(PCHAR name);
 extern LONG ArcSetEnvironmentVariable(PCHAR name, PCHAR value);
 
-/* ARCS command line acquisition and parsing. */
-extern char *prom_getcmdline(void);
+/* ARCS command line parsing. */
 extern void prom_init_cmdline(void);
 
 /* Acquiring info about the current time, etc. */
diff --git a/arch/mips/include/asm/spinlock.h b/arch/mips/include/asm/spinlock.h
index 5b60a09a0f08..21ef9efbde43 100644
--- a/arch/mips/include/asm/spinlock.h
+++ b/arch/mips/include/asm/spinlock.h
@@ -34,33 +34,33 @@
  * becomes equal to the the initial value of the tail.
  */
 
-static inline int __raw_spin_is_locked(raw_spinlock_t *lock)
+static inline int arch_spin_is_locked(arch_spinlock_t *lock)
 {
         unsigned int counters = ACCESS_ONCE(lock->lock);
 
         return ((counters >> 14) ^ counters) & 0x1fff;
 }
 
-#define __raw_spin_lock_flags(lock, flags) __raw_spin_lock(lock)
-#define __raw_spin_unlock_wait(x) \
-        while (__raw_spin_is_locked(x)) { cpu_relax(); }
+#define arch_spin_lock_flags(lock, flags) arch_spin_lock(lock)
+#define arch_spin_unlock_wait(x) \
+        while (arch_spin_is_locked(x)) { cpu_relax(); }
 
-static inline int __raw_spin_is_contended(raw_spinlock_t *lock)
+static inline int arch_spin_is_contended(arch_spinlock_t *lock)
 {
         unsigned int counters = ACCESS_ONCE(lock->lock);
 
         return (((counters >> 14) - counters) & 0x1fff) > 1;
 }
-#define __raw_spin_is_contended __raw_spin_is_contended
+#define arch_spin_is_contended  arch_spin_is_contended
 
-static inline void __raw_spin_lock(raw_spinlock_t *lock)
+static inline void arch_spin_lock(arch_spinlock_t *lock)
 {
         int my_ticket;
         int tmp;
 
         if (R10000_LLSC_WAR) {
                 __asm__ __volatile__ (
-                "       .set push               # __raw_spin_lock       \n"
+                "       .set push               # arch_spin_lock        \n"
                 "       .set noreorder                                  \n"
                 "                                                       \n"
                 "1:     ll      %[ticket], %[ticket_ptr]                \n"
@@ -94,7 +94,7 @@ static inline void __raw_spin_lock(raw_spinlock_t *lock)
                   [my_ticket] "=&r" (my_ticket));
         } else {
                 __asm__ __volatile__ (
-                "       .set push               # __raw_spin_lock       \n"
+                "       .set push               # arch_spin_lock        \n"
                 "       .set noreorder                                  \n"
                 "                                                       \n"
                 "       ll      %[ticket], %[ticket_ptr]                \n"
@@ -134,7 +134,7 @@ static inline void __raw_spin_lock(raw_spinlock_t *lock)
         smp_llsc_mb();
 }
 
-static inline void __raw_spin_unlock(raw_spinlock_t *lock)
+static inline void arch_spin_unlock(arch_spinlock_t *lock)
 {
         int tmp;
 
@@ -142,7 +142,7 @@ static inline void __raw_spin_unlock(raw_spinlock_t *lock)
 
         if (R10000_LLSC_WAR) {
                 __asm__ __volatile__ (
-                "                               # __raw_spin_unlock     \n"
+                "                               # arch_spin_unlock      \n"
                 "1:     ll      %[ticket], %[ticket_ptr]                \n"
                 "       addiu   %[ticket], %[ticket], 1                 \n"
                 "       ori     %[ticket], %[ticket], 0x2000            \n"
@@ -153,7 +153,7 @@ static inline void __raw_spin_unlock(raw_spinlock_t *lock)
                   [ticket] "=&r" (tmp));
         } else {
                 __asm__ __volatile__ (
-                "       .set push               # __raw_spin_unlock     \n"
+                "       .set push               # arch_spin_unlock      \n"
                 "       .set noreorder                                  \n"
                 "                                                       \n"
                 "       ll      %[ticket], %[ticket_ptr]                \n"
@@ -174,13 +174,13 @@ static inline void __raw_spin_unlock(raw_spinlock_t *lock)
         }
 }
 
-static inline unsigned int __raw_spin_trylock(raw_spinlock_t *lock)
+static inline unsigned int arch_spin_trylock(arch_spinlock_t *lock)
 {
         int tmp, tmp2, tmp3;
 
         if (R10000_LLSC_WAR) {
                 __asm__ __volatile__ (
-                "       .set push               # __raw_spin_trylock    \n"
+                "       .set push               # arch_spin_trylock     \n"
                 "       .set noreorder                                  \n"
                 "                                                       \n"
                 "1:     ll      %[ticket], %[ticket_ptr]                \n"
@@ -204,7 +204,7 @@ static inline unsigned int __raw_spin_trylock(raw_spinlock_t *lock)
                   [now_serving] "=&r" (tmp3));
         } else {
                 __asm__ __volatile__ (
-                "       .set push               # __raw_spin_trylock    \n"
+                "       .set push               # arch_spin_trylock     \n"
                 "       .set noreorder                                  \n"
                 "                                                       \n"
                 "       ll      %[ticket], %[ticket_ptr]                \n"
@@ -248,21 +248,21 @@ static inline unsigned int __raw_spin_trylock(raw_spinlock_t *lock)
  * read_can_lock - would read_trylock() succeed?
  * @lock: the rwlock in question.
  */
-#define __raw_read_can_lock(rw) ((rw)->lock >= 0)
+#define arch_read_can_lock(rw)  ((rw)->lock >= 0)
 
 /*
  * write_can_lock - would write_trylock() succeed?
  * @lock: the rwlock in question.
  */
-#define __raw_write_can_lock(rw)        (!(rw)->lock)
+#define arch_write_can_lock(rw) (!(rw)->lock)
 
-static inline void __raw_read_lock(raw_rwlock_t *rw)
+static inline void arch_read_lock(arch_rwlock_t *rw)
 {
         unsigned int tmp;
 
         if (R10000_LLSC_WAR) {
                 __asm__ __volatile__(
-                "       .set    noreorder       # __raw_read_lock       \n"
+                "       .set    noreorder       # arch_read_lock        \n"
                 "1:     ll      %1, %2                                  \n"
                 "       bltz    %1, 1b                                  \n"
                 "        addu   %1, 1                                   \n"
@@ -275,7 +275,7 @@ static inline void __raw_read_lock(raw_rwlock_t *rw)
                 : "memory");
         } else {
                 __asm__ __volatile__(
-                "       .set    noreorder       # __raw_read_lock       \n"
+                "       .set    noreorder       # arch_read_lock        \n"
                 "1:     ll      %1, %2                                  \n"
                 "       bltz    %1, 2f                                  \n"
                 "        addu   %1, 1                                   \n"
@@ -301,7 +301,7 @@ static inline void __raw_read_lock(raw_rwlock_t *rw)
 /* Note the use of sub, not subu which will make the kernel die with an
    overflow exception if we ever try to unlock an rwlock that is already
    unlocked or is being held by a writer.  */
-static inline void __raw_read_unlock(raw_rwlock_t *rw)
+static inline void arch_read_unlock(arch_rwlock_t *rw)
 {
         unsigned int tmp;
 
@@ -309,7 +309,7 @@ static inline void __raw_read_unlock(raw_rwlock_t *rw)
 
         if (R10000_LLSC_WAR) {
                 __asm__ __volatile__(
-                "1:     ll      %1, %2          # __raw_read_unlock     \n"
+                "1:     ll      %1, %2          # arch_read_unlock      \n"
                 "       sub     %1, 1                                   \n"
                 "       sc      %1, %0                                  \n"
                 "       beqzl   %1, 1b                                  \n"
@@ -318,7 +318,7 @@ static inline void __raw_read_unlock(raw_rwlock_t *rw)
                 : "memory");
         } else {
                 __asm__ __volatile__(
-                "       .set    noreorder       # __raw_read_unlock     \n"
+                "       .set    noreorder       # arch_read_unlock      \n"
                 "1:     ll      %1, %2                                  \n"
                 "       sub     %1, 1                                   \n"
                 "       sc      %1, %0                                  \n"
@@ -335,13 +335,13 @@ static inline void __raw_read_unlock(raw_rwlock_t *rw)
         }
 }
 
-static inline void __raw_write_lock(raw_rwlock_t *rw)
+static inline void arch_write_lock(arch_rwlock_t *rw)
 {
         unsigned int tmp;
 
         if (R10000_LLSC_WAR) {
                 __asm__ __volatile__(
-                "       .set    noreorder       # __raw_write_lock      \n"
+                "       .set    noreorder       # arch_write_lock       \n"
                 "1:     ll      %1, %2                                  \n"
                 "       bnez    %1, 1b                                  \n"
                 "        lui    %1, 0x8000                              \n"
@@ -354,7 +354,7 @@ static inline void __raw_write_lock(raw_rwlock_t *rw)
                 : "memory");
         } else {
                 __asm__ __volatile__(
-                "       .set    noreorder       # __raw_write_lock      \n"
+                "       .set    noreorder       # arch_write_lock       \n"
                 "1:     ll      %1, %2                                  \n"
                 "       bnez    %1, 2f                                  \n"
                 "        lui    %1, 0x8000                              \n"
@@ -377,26 +377,26 @@ static inline void __raw_write_lock(raw_rwlock_t *rw)
         smp_llsc_mb();
 }
 
-static inline void __raw_write_unlock(raw_rwlock_t *rw)
+static inline void arch_write_unlock(arch_rwlock_t *rw)
 {
         smp_mb();
 
         __asm__ __volatile__(
-        "                               # __raw_write_unlock    \n"
+        "                               # arch_write_unlock     \n"
         "       sw      $0, %0                                  \n"
         : "=m" (rw->lock)
         : "m" (rw->lock)
         : "memory");
 }
 
-static inline int __raw_read_trylock(raw_rwlock_t *rw)
+static inline int arch_read_trylock(arch_rwlock_t *rw)
 {
         unsigned int tmp;
         int ret;
 
         if (R10000_LLSC_WAR) {
                 __asm__ __volatile__(
-                "       .set    noreorder       # __raw_read_trylock    \n"
+                "       .set    noreorder       # arch_read_trylock     \n"
                 "       li      %2, 0                                   \n"
                 "1:     ll      %1, %3                                  \n"
                 "       bltz    %1, 2f                                  \n"
@@ -413,7 +413,7 @@ static inline int __raw_read_trylock(raw_rwlock_t *rw)
                 : "memory");
         } else {
                 __asm__ __volatile__(
-                "       .set    noreorder       # __raw_read_trylock    \n"
+                "       .set    noreorder       # arch_read_trylock     \n"
                 "       li      %2, 0                                   \n"
                 "1:     ll      %1, %3                                  \n"
                 "       bltz    %1, 2f                                  \n"
@@ -433,14 +433,14 @@ static inline int __raw_read_trylock(raw_rwlock_t *rw)
         return ret;
 }
 
-static inline int __raw_write_trylock(raw_rwlock_t *rw)
+static inline int arch_write_trylock(arch_rwlock_t *rw)
 {
         unsigned int tmp;
         int ret;
 
         if (R10000_LLSC_WAR) {
                 __asm__ __volatile__(
-                "       .set    noreorder       # __raw_write_trylock   \n"
+                "       .set    noreorder       # arch_write_trylock    \n"
                 "       li      %2, 0                                   \n"
                 "1:     ll      %1, %3                                  \n"
                 "       bnez    %1, 2f                                  \n"
@@ -457,7 +457,7 @@ static inline int __raw_write_trylock(raw_rwlock_t *rw)
                 : "memory");
         } else {
                 __asm__ __volatile__(
-                "       .set    noreorder       # __raw_write_trylock   \n"
+                "       .set    noreorder       # arch_write_trylock    \n"
                 "       li      %2, 0                                   \n"
                 "1:     ll      %1, %3                                  \n"
                 "       bnez    %1, 2f                                  \n"
@@ -480,11 +480,11 @@ static inline int __raw_write_trylock(raw_rwlock_t *rw)
         return ret;
 }
 
-#define __raw_read_lock_flags(lock, flags) __raw_read_lock(lock)
-#define __raw_write_lock_flags(lock, flags) __raw_write_lock(lock)
+#define arch_read_lock_flags(lock, flags) arch_read_lock(lock)
+#define arch_write_lock_flags(lock, flags) arch_write_lock(lock)
 
-#define _raw_spin_relax(lock)   cpu_relax()
-#define _raw_read_relax(lock)   cpu_relax()
-#define _raw_write_relax(lock)  cpu_relax()
+#define arch_spin_relax(lock)   cpu_relax()
+#define arch_read_relax(lock)   cpu_relax()
+#define arch_write_relax(lock)  cpu_relax()
 
 #endif /* _ASM_SPINLOCK_H */
diff --git a/arch/mips/include/asm/spinlock_types.h b/arch/mips/include/asm/spinlock_types.h
index adeedaa116c1..ee197c2f9c98 100644
--- a/arch/mips/include/asm/spinlock_types.h
+++ b/arch/mips/include/asm/spinlock_types.h
@@ -12,14 +12,14 @@ typedef struct {
          * bits 15..28: ticket
          */
         unsigned int lock;
-} raw_spinlock_t;
+} arch_spinlock_t;
 
-#define __RAW_SPIN_LOCK_UNLOCKED        { 0 }
+#define __ARCH_SPIN_LOCK_UNLOCKED       { 0 }
 
 typedef struct {
         volatile unsigned int lock;
-} raw_rwlock_t;
+} arch_rwlock_t;
 
-#define __RAW_RW_LOCK_UNLOCKED          { 0 }
+#define __ARCH_RW_LOCK_UNLOCKED         { 0 }
 
 #endif
diff --git a/arch/mips/include/asm/stackframe.h b/arch/mips/include/asm/stackframe.h
index db0fa7b5aeaf..3b6da3330e32 100644
--- a/arch/mips/include/asm/stackframe.h
+++ b/arch/mips/include/asm/stackframe.h
@@ -51,9 +51,6 @@
                 LONG_S  v1, PT_ACX(sp)
 #else
                 mfhi    v1
-                LONG_S  v1, PT_HI(sp)
-                mflo    v1
-                LONG_S  v1, PT_LO(sp)
 #endif
 #ifdef CONFIG_32BIT
                 LONG_S  $8, PT_R8(sp)
@@ -62,10 +59,17 @@
                 LONG_S  $10, PT_R10(sp)
                 LONG_S  $11, PT_R11(sp)
                 LONG_S  $12, PT_R12(sp)
+#ifndef CONFIG_CPU_HAS_SMARTMIPS
+                LONG_S  v1, PT_HI(sp)
+                mflo    v1
+#endif
                 LONG_S  $13, PT_R13(sp)
                 LONG_S  $14, PT_R14(sp)
                 LONG_S  $15, PT_R15(sp)
                 LONG_S  $24, PT_R24(sp)
+#ifndef CONFIG_CPU_HAS_SMARTMIPS
+                LONG_S  v1, PT_LO(sp)
+#endif
                 .endm
 
                 .macro  SAVE_STATIC
@@ -83,15 +87,19 @@
 #ifdef CONFIG_SMP
 #ifdef CONFIG_MIPS_MT_SMTC
 #define PTEBASE_SHIFT   19      /* TCBIND */
+#define CPU_ID_REG CP0_TCBIND
+#define CPU_ID_MFC0 mfc0
+#elif defined(CONFIG_MIPS_PGD_C0_CONTEXT)
+#define PTEBASE_SHIFT   48      /* XCONTEXT */
+#define CPU_ID_REG CP0_XCONTEXT
+#define CPU_ID_MFC0 MFC0
 #else
 #define PTEBASE_SHIFT   23      /* CONTEXT */
+#define CPU_ID_REG CP0_CONTEXT
+#define CPU_ID_MFC0 MFC0
 #endif
                 .macro  get_saved_sp    /* SMP variation */
-#ifdef CONFIG_MIPS_MT_SMTC
-                mfc0    k0, CP0_TCBIND
-#else
-                MFC0    k0, CP0_CONTEXT
-#endif
+                CPU_ID_MFC0     k0, CPU_ID_REG
 #if defined(CONFIG_32BIT) || defined(KBUILD_64BIT_SYM32)
                 lui     k1, %hi(kernelsp)
 #else
@@ -107,11 +115,7 @@
                 .endm
 
                 .macro  set_saved_sp stackp temp temp2
-#ifdef CONFIG_MIPS_MT_SMTC
-                mfc0    \temp, CP0_TCBIND
-#else
-                MFC0    \temp, CP0_CONTEXT
-#endif
+                CPU_ID_MFC0     \temp, CPU_ID_REG
                 LONG_SRL        \temp, PTEBASE_SHIFT
                 LONG_S  \stackp, kernelsp(\temp)
                 .endm
@@ -166,7 +170,6 @@
                 LONG_S  $0, PT_R0(sp)
                 mfc0    v1, CP0_STATUS
                 LONG_S  $2, PT_R2(sp)
-                LONG_S  v1, PT_STATUS(sp)
 #ifdef CONFIG_MIPS_MT_SMTC
                 /*
                  * Ideally, these instructions would be shuffled in
@@ -178,20 +181,21 @@
                 LONG_S  v1, PT_TCSTATUS(sp)
 #endif /* CONFIG_MIPS_MT_SMTC */
                 LONG_S  $4, PT_R4(sp)
-                mfc0    v1, CP0_CAUSE
                 LONG_S  $5, PT_R5(sp)
-                LONG_S  v1, PT_CAUSE(sp)
+                LONG_S  v1, PT_STATUS(sp)
+                mfc0    v1, CP0_CAUSE
                 LONG_S  $6, PT_R6(sp)
-                MFC0    v1, CP0_EPC
                 LONG_S  $7, PT_R7(sp)
+                LONG_S  v1, PT_CAUSE(sp)
+                MFC0    v1, CP0_EPC
 #ifdef CONFIG_64BIT
                 LONG_S  $8, PT_R8(sp)
                 LONG_S  $9, PT_R9(sp)
 #endif
-                LONG_S  v1, PT_EPC(sp)
                 LONG_S  $25, PT_R25(sp)
                 LONG_S  $28, PT_R28(sp)
                 LONG_S  $31, PT_R31(sp)
+                LONG_S  v1, PT_EPC(sp)
                 ori     $28, sp, _THREAD_MASK
                 xori    $28, _THREAD_MASK
 #ifdef CONFIG_CPU_CAVIUM_OCTEON
diff --git a/arch/mips/kernel/Makefile b/arch/mips/kernel/Makefile
index eecd2a9f155c..9326af5186fe 100644
--- a/arch/mips/kernel/Makefile
+++ b/arch/mips/kernel/Makefile
@@ -2,14 +2,17 @@
 # Makefile for the Linux/MIPS kernel.
 #
 
-CPPFLAGS_vmlinux.lds := $(KBUILD_CFLAGS)
-
 extra-y         := head.o init_task.o vmlinux.lds
 
 obj-y           += cpu-probe.o branch.o entry.o genex.o irq.o process.o \
                    ptrace.o reset.o setup.o signal.o syscall.o \
                    time.o topology.o traps.o unaligned.o watch.o
 
+ifdef CONFIG_FUNCTION_TRACER
+CFLAGS_REMOVE_ftrace.o = -pg
+CFLAGS_REMOVE_early_printk.o = -pg
+endif
+
 obj-$(CONFIG_CEVT_BCM1480)      += cevt-bcm1480.o
 obj-$(CONFIG_CEVT_R4K_LIB)      += cevt-r4k.o
 obj-$(CONFIG_MIPS_MT_SMTC)      += cevt-smtc.o
@@ -19,6 +22,7 @@ obj-$(CONFIG_CEVT_SB1250)	+= cevt-sb1250.o
 obj-$(CONFIG_CEVT_TXX9)         += cevt-txx9.o
 obj-$(CONFIG_CSRC_BCM1480)      += csrc-bcm1480.o
 obj-$(CONFIG_CSRC_IOASIC)       += csrc-ioasic.o
+obj-$(CONFIG_CSRC_POWERTV)      += csrc-powertv.o
 obj-$(CONFIG_CSRC_R4K_LIB)      += csrc-r4k.o
 obj-$(CONFIG_CSRC_SB1250)       += csrc-sb1250.o
 obj-$(CONFIG_SYNC_R4K)          += sync-r4k.o
@@ -26,6 +30,8 @@ obj-$(CONFIG_SYNC_R4K)		+= sync-r4k.o
 obj-$(CONFIG_STACKTRACE)        += stacktrace.o
 obj-$(CONFIG_MODULES)           += mips_ksyms.o module.o
 
+obj-$(CONFIG_FUNCTION_TRACER)   += mcount.o ftrace.o
+
 obj-$(CONFIG_CPU_LOONGSON2)     += r4k_fpu.o r4k_switch.o
 obj-$(CONFIG_CPU_MIPS32)        += r4k_fpu.o r4k_switch.o
 obj-$(CONFIG_CPU_MIPS64)        += r4k_fpu.o r4k_switch.o
@@ -92,4 +98,8 @@ CFLAGS_cpu-bugs64.o	= $(shell if $(CC) $(KBUILD_CFLAGS) -Wa,-mdaddi -c -o /dev/n
 
 obj-$(CONFIG_HAVE_STD_PC_SERIAL_PORT)   += 8250-platform.o
 
+obj-$(CONFIG_MIPS_CPUFREQ)      += cpufreq/
+
 EXTRA_CFLAGS += -Werror
+
+CPPFLAGS_vmlinux.lds            := $(KBUILD_CFLAGS)
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index 7a51866068a4..80e202eca056 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -16,6 +16,7 @@
 #include <linux/ptrace.h>
 #include <linux/smp.h>
 #include <linux/stddef.h>
+#include <linux/module.h>
 
 #include <asm/bugs.h>
 #include <asm/cpu.h>
@@ -32,6 +33,7 @@
  * the CPU very much.
  */
 void (*cpu_wait)(void);
+EXPORT_SYMBOL(cpu_wait);
 
 static void r3081_wait(void)
 {
diff --git a/arch/mips/kernel/cpufreq/Kconfig b/arch/mips/kernel/cpufreq/Kconfig
new file mode 100644
index 000000000000..58c601eee6fd
--- /dev/null
+++ b/arch/mips/kernel/cpufreq/Kconfig
@@ -0,0 +1,41 @@
+#
+# CPU Frequency scaling
+#
+
+config MIPS_EXTERNAL_TIMER
+        bool
+
+config MIPS_CPUFREQ
+        bool
+        default y
+        depends on CPU_SUPPORTS_CPUFREQ && MIPS_EXTERNAL_TIMER
+
+if MIPS_CPUFREQ
+
+menu "CPU Frequency scaling"
+
+source "drivers/cpufreq/Kconfig"
+
+if CPU_FREQ
+
+comment "CPUFreq processor drivers"
+
+config LOONGSON2_CPUFREQ
+        tristate "Loongson2 CPUFreq Driver"
+        select CPU_FREQ_TABLE
+        depends on MIPS_CPUFREQ
+        help
+          This option adds a CPUFreq driver for loongson processors which
+          support software configurable cpu frequency.
+
+          Loongson2F and it's successors support this feature.
+
+          For details, take a look at <file:Documentation/cpu-freq/>.
+
+          If in doubt, say N.
+
+endif   # CPU_FREQ
+
+endmenu
+
+endif   # MIPS_CPUFREQ
diff --git a/arch/mips/kernel/cpufreq/Makefile b/arch/mips/kernel/cpufreq/Makefile
new file mode 100644
index 000000000000..c3479a432efe
--- /dev/null
+++ b/arch/mips/kernel/cpufreq/Makefile
@@ -0,0 +1,5 @@
+#
+# Makefile for the Linux/MIPS cpufreq.
+#
+
+obj-$(CONFIG_LOONGSON2_CPUFREQ) += loongson2_cpufreq.o loongson2_clock.o
diff --git a/arch/mips/kernel/cpufreq/loongson2_clock.c b/arch/mips/kernel/cpufreq/loongson2_clock.c
new file mode 100644
index 000000000000..d7ca256e33ef
--- /dev/null
+++ b/arch/mips/kernel/cpufreq/loongson2_clock.c
@@ -0,0 +1,166 @@
+/*
+ * Copyright (C) 2006 - 2008 Lemote Inc. & Insititute of Computing Technology
+ * Author: Yanhua, yanh@lemote.com
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+
+#include <linux/cpufreq.h>
+#include <linux/platform_device.h>
+
+#include <asm/clock.h>
+
+#include <loongson.h>
+
+static LIST_HEAD(clock_list);
+static DEFINE_SPINLOCK(clock_lock);
+static DEFINE_MUTEX(clock_list_sem);
+
+/* Minimum CLK support */
+enum {
+        DC_ZERO, DC_25PT = 2, DC_37PT, DC_50PT, DC_62PT, DC_75PT,
+        DC_87PT, DC_DISABLE, DC_RESV
+};
+
+struct cpufreq_frequency_table loongson2_clockmod_table[] = {
+        {DC_RESV, CPUFREQ_ENTRY_INVALID},
+        {DC_ZERO, CPUFREQ_ENTRY_INVALID},
+        {DC_25PT, 0},
+        {DC_37PT, 0},
+        {DC_50PT, 0},
+        {DC_62PT, 0},
+        {DC_75PT, 0},
+        {DC_87PT, 0},
+        {DC_DISABLE, 0},
+        {DC_RESV, CPUFREQ_TABLE_END},
+};
+EXPORT_SYMBOL_GPL(loongson2_clockmod_table);
+
+static struct clk cpu_clk = {
+        .name = "cpu_clk",
+        .flags = CLK_ALWAYS_ENABLED | CLK_RATE_PROPAGATES,
+        .rate = 800000000,
+};
+
+struct clk *clk_get(struct device *dev, const char *id)
+{
+        return &cpu_clk;
+}
+EXPORT_SYMBOL(clk_get);
+
+static void propagate_rate(struct clk *clk)
+{
+        struct clk *clkp;
+
+        list_for_each_entry(clkp, &clock_list, node) {
+                if (likely(clkp->parent != clk))
+                        continue;
+                if (likely(clkp->ops && clkp->ops->recalc))
+                        clkp->ops->recalc(clkp);
+                if (unlikely(clkp->flags & CLK_RATE_PROPAGATES))
+                        propagate_rate(clkp);
+        }
+}
+
+int clk_enable(struct clk *clk)
+{
+        return 0;
+}
+EXPORT_SYMBOL(clk_enable);
+
+void clk_disable(struct clk *clk)
+{
+}
+EXPORT_SYMBOL(clk_disable);
+
+unsigned long clk_get_rate(struct clk *clk)
+{
+        return (unsigned long)clk->rate;
+}
+EXPORT_SYMBOL(clk_get_rate);
+
+void clk_put(struct clk *clk)
+{
+}
+EXPORT_SYMBOL(clk_put);
+
+int clk_set_rate(struct clk *clk, unsigned long rate)
+{
+        return clk_set_rate_ex(clk, rate, 0);
+}
+EXPORT_SYMBOL_GPL(clk_set_rate);
+
+int clk_set_rate_ex(struct clk *clk, unsigned long rate, int algo_id)
+{
+        int ret = 0;
+        int regval;
+        int i;
+
+        if (likely(clk->ops && clk->ops->set_rate)) {
+                unsigned long flags;
+
+                spin_lock_irqsave(&clock_lock, flags);
+                ret = clk->ops->set_rate(clk, rate, algo_id);
+                spin_unlock_irqrestore(&clock_lock, flags);
+        }
+
+        if (unlikely(clk->flags & CLK_RATE_PROPAGATES))
+                propagate_rate(clk);
+
+        for (i = 0; loongson2_clockmod_table[i].frequency != CPUFREQ_TABLE_END;
+             i++) {
+                if (loongson2_clockmod_table[i].frequency ==
+                    CPUFREQ_ENTRY_INVALID)
+                        continue;
+                if (rate == loongson2_clockmod_table[i].frequency)
+                        break;
+        }
+        if (rate != loongson2_clockmod_table[i].frequency)
+                return -ENOTSUPP;
+
+        clk->rate = rate;
+
+        regval = LOONGSON_CHIPCFG0;
+        regval = (regval & ~0x7) | (loongson2_clockmod_table[i].index - 1);
+        LOONGSON_CHIPCFG0 = regval;
+
+        return ret;
+}
+EXPORT_SYMBOL_GPL(clk_set_rate_ex);
+
+long clk_round_rate(struct clk *clk, unsigned long rate)
+{
+        if (likely(clk->ops && clk->ops->round_rate)) {
+                unsigned long flags, rounded;
+
+                spin_lock_irqsave(&clock_lock, flags);
+                rounded = clk->ops->round_rate(clk, rate);
+                spin_unlock_irqrestore(&clock_lock, flags);
+
+                return rounded;
+        }
+
+        return rate;
+}
+EXPORT_SYMBOL_GPL(clk_round_rate);
+
+/*
+ * This is the simple version of Loongson-2 wait, Maybe we need do this in
+ * interrupt disabled content
+ */
+
+DEFINE_SPINLOCK(loongson2_wait_lock);
+void loongson2_cpu_wait(void)
+{
+        u32 cpu_freq;
+        unsigned long flags;
+
+        spin_lock_irqsave(&loongson2_wait_lock, flags);
+        cpu_freq = LOONGSON_CHIPCFG0;
+        LOONGSON_CHIPCFG0 &= ~0x7;      /* Put CPU into wait mode */
+        LOONGSON_CHIPCFG0 = cpu_freq;   /* Restore CPU state */
+        spin_unlock_irqrestore(&loongson2_wait_lock, flags);
+}
+EXPORT_SYMBOL_GPL(loongson2_cpu_wait);
diff --git a/arch/mips/kernel/cpufreq/loongson2_cpufreq.c b/arch/mips/kernel/cpufreq/loongson2_cpufreq.c
new file mode 100644
index 000000000000..2f6a0b147ab8
--- /dev/null
+++ b/arch/mips/kernel/cpufreq/loongson2_cpufreq.c
@@ -0,0 +1,227 @@
+/*
+ * Cpufreq driver for the loongson-2 processors
+ *
+ * The 2E revision of loongson processor not support this feature.
+ *
+ * Copyright (C) 2006 - 2008 Lemote Inc. & Insititute of Computing Technology
+ * Author: Yanhua, yanh@lemote.com
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#include <linux/cpufreq.h>
+#include <linux/module.h>
+#include <linux/err.h>
+#include <linux/sched.h>        /* set_cpus_allowed() */
+#include <linux/delay.h>
+#include <linux/platform_device.h>
+
+#include <asm/clock.h>
+
+#include <loongson.h>
+
+static uint nowait;
+
+static struct clk *cpuclk;
+
+static void (*saved_cpu_wait) (void);
+
+static int loongson2_cpu_freq_notifier(struct notifier_block *nb,
+                                        unsigned long val, void *data);
+
+static struct notifier_block loongson2_cpufreq_notifier_block = {
+        .notifier_call = loongson2_cpu_freq_notifier
+};
+
+static int loongson2_cpu_freq_notifier(struct notifier_block *nb,
+                                        unsigned long val, void *data)
+{
+        if (val == CPUFREQ_POSTCHANGE)
+                current_cpu_data.udelay_val = loops_per_jiffy;
+
+        return 0;
+}
+
+static unsigned int loongson2_cpufreq_get(unsigned int cpu)
+{
+        return clk_get_rate(cpuclk);
+}
+
+/*
+ * Here we notify other drivers of the proposed change and the final change.
+ */
+static int loongson2_cpufreq_target(struct cpufreq_policy *policy,
+                                     unsigned int target_freq,
+                                     unsigned int relation)
+{
+        unsigned int cpu = policy->cpu;
+        unsigned int newstate = 0;
+        cpumask_t cpus_allowed;
+        struct cpufreq_freqs freqs;
+        unsigned int freq;
+
+        if (!cpu_online(cpu))
+                return -ENODEV;
+
+        cpus_allowed = current->cpus_allowed;
+        set_cpus_allowed(current, cpumask_of_cpu(cpu));
+
+        if (cpufreq_frequency_table_target
+            (policy, &loongson2_clockmod_table[0], target_freq, relation,
+             &newstate))
+                return -EINVAL;
+
+        freq =
+            ((cpu_clock_freq / 1000) *
+             loongson2_clockmod_table[newstate].index) / 8;
+        if (freq < policy->min || freq > policy->max)
+                return -EINVAL;
+
+        pr_debug("cpufreq: requested frequency %u Hz\n", target_freq * 1000);
+
+        freqs.cpu = cpu;
+        freqs.old = loongson2_cpufreq_get(cpu);
+        freqs.new = freq;
+        freqs.flags = 0;
+
+        if (freqs.new == freqs.old)
+                return 0;
+
+        /* notifiers */
+        cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
+
+        set_cpus_allowed(current, cpus_allowed);
+
+        /* setting the cpu frequency */
+        clk_set_rate(cpuclk, freq);
+
+        /* notifiers */
+        cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
+
+        pr_debug("cpufreq: set frequency %u kHz\n", freq);
+
+        return 0;
+}
+
+static int loongson2_cpufreq_cpu_init(struct cpufreq_policy *policy)
+{
+        int i;
+
+        if (!cpu_online(policy->cpu))
+                return -ENODEV;
+
+        cpuclk = clk_get(NULL, "cpu_clk");
+        if (IS_ERR(cpuclk)) {
+                printk(KERN_ERR "cpufreq: couldn't get CPU clk\n");
+                return PTR_ERR(cpuclk);
+        }
+
+        cpuclk->rate = cpu_clock_freq / 1000;
+        if (!cpuclk->rate)
+                return -EINVAL;
+
+        /* clock table init */
+        for (i = 2;
+             (loongson2_clockmod_table[i].frequency != CPUFREQ_TABLE_END);
+             i++)
+                loongson2_clockmod_table[i].frequency = (cpuclk->rate * i) / 8;
+
+        policy->cur = loongson2_cpufreq_get(policy->cpu);
+
+        cpufreq_frequency_table_get_attr(&loongson2_clockmod_table[0],
+                                         policy->cpu);
+
+        return cpufreq_frequency_table_cpuinfo(policy,
+                                            &loongson2_clockmod_table[0]);
+}
+
+static int loongson2_cpufreq_verify(struct cpufreq_policy *policy)
+{
+        return cpufreq_frequency_table_verify(policy,
+                                              &loongson2_clockmod_table[0]);
+}
+
+static int loongson2_cpufreq_exit(struct cpufreq_policy *policy)
+{
+        clk_put(cpuclk);
+        return 0;
+}
+
+static struct freq_attr *loongson2_table_attr[] = {
+        &cpufreq_freq_attr_scaling_available_freqs,
+        NULL,
+};
+
+static struct cpufreq_driver loongson2_cpufreq_driver = {
+        .owner = THIS_MODULE,
+        .name = "loongson2",
+        .init = loongson2_cpufreq_cpu_init,
+        .verify = loongson2_cpufreq_verify,
+        .target = loongson2_cpufreq_target,
+        .get = loongson2_cpufreq_get,
+        .exit = loongson2_cpufreq_exit,
+        .attr = loongson2_table_attr,
+};
+
+static struct platform_device_id platform_device_ids[] = {
+        {
+                .name = "loongson2_cpufreq",
+        },
+        {}
+};
+
+MODULE_DEVICE_TABLE(platform, platform_device_ids);
+
+static struct platform_driver platform_driver = {
+        .driver = {
+                .name = "loongson2_cpufreq",
+                .owner = THIS_MODULE,
+        },
+        .id_table = platform_device_ids,
+};
+
+static int __init cpufreq_init(void)
+{
+        int ret;
+
+        /* Register platform stuff */
+        ret = platform_driver_register(&platform_driver);
+        if (ret)
+                return ret;
+
+        pr_info("cpufreq: Loongson-2F CPU frequency driver.\n");
+
+        cpufreq_register_notifier(&loongson2_cpufreq_notifier_block,
+                                  CPUFREQ_TRANSITION_NOTIFIER);
+
+        ret = cpufreq_register_driver(&loongson2_cpufreq_driver);
+
+        if (!ret && !nowait) {
+                saved_cpu_wait = cpu_wait;
+                cpu_wait = loongson2_cpu_wait;
+        }
+
+        return ret;
+}
+
+static void __exit cpufreq_exit(void)
+{
+        if (!nowait && saved_cpu_wait)
+                cpu_wait = saved_cpu_wait;
+        cpufreq_unregister_driver(&loongson2_cpufreq_driver);
+        cpufreq_unregister_notifier(&loongson2_cpufreq_notifier_block,
+                                    CPUFREQ_TRANSITION_NOTIFIER);
+
+        platform_driver_unregister(&platform_driver);
+}
+
+module_init(cpufreq_init);
+module_exit(cpufreq_exit);
+
+module_param(nowait, uint, 0644);
+MODULE_PARM_DESC(nowait, "Disable Loongson-2F specific wait");
+
+MODULE_AUTHOR("Yanhua <yanh@lemote.com>");
+MODULE_DESCRIPTION("cpufreq driver for Loongson2F");
+MODULE_LICENSE("GPL");
diff --git a/arch/mips/kernel/csrc-powertv.c b/arch/mips/kernel/csrc-powertv.c
new file mode 100644
index 000000000000..a27c16c8690e
--- /dev/null
+++ b/arch/mips/kernel/csrc-powertv.c
@@ -0,0 +1,180 @@
+/*
+ * Copyright (C) 2008 Scientific-Atlanta, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
+ */
+/*
+ * The file comes from kernel/csrc-r4k.c
+ */
+#include <linux/clocksource.h>
+#include <linux/init.h>
+
+#include <asm/time.h>                   /* Not included in linux/time.h */
+
+#include <asm/mach-powertv/asic_regs.h>
+#include "powertv-clock.h"
+
+/* MIPS PLL Register Definitions */
+#define PLL_GET_M(x)            (((x) >> 8) & 0x000000FF)
+#define PLL_GET_N(x)            (((x) >> 16) & 0x000000FF)
+#define PLL_GET_P(x)            (((x) >> 24) & 0x00000007)
+
+/*
+ * returns:  Clock frequency in kHz
+ */
+unsigned int __init mips_get_pll_freq(void)
+{
+        unsigned int pll_reg, m, n, p;
+        unsigned int fin = 54000; /* Base frequency in kHz */
+        unsigned int fout;
+
+        /* Read PLL register setting */
+        pll_reg = asic_read(mips_pll_setup);
+        m = PLL_GET_M(pll_reg);
+        n = PLL_GET_N(pll_reg);
+        p = PLL_GET_P(pll_reg);
+        pr_info("MIPS PLL Register:0x%x  M=%d  N=%d  P=%d\n", pll_reg, m, n, p);
+
+        /* Calculate clock frequency = (2 * N * 54MHz) / (M * (2**P)) */
+        fout = ((2 * n * fin) / (m * (0x01 << p)));
+
+        pr_info("MIPS Clock Freq=%d kHz\n", fout);
+
+        return fout;
+}
+
+static cycle_t c0_hpt_read(struct clocksource *cs)
+{
+        return read_c0_count();
+}
+
+static struct clocksource clocksource_mips = {
+        .name           = "powertv-counter",
+        .read           = c0_hpt_read,
+        .mask           = CLOCKSOURCE_MASK(32),
+        .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
+};
+
+static void __init powertv_c0_hpt_clocksource_init(void)
+{
+        unsigned int pll_freq = mips_get_pll_freq();
+
+        pr_info("CPU frequency %d.%02d MHz\n", pll_freq / 1000,
+                (pll_freq % 1000) * 100 / 1000);
+
+        mips_hpt_frequency = pll_freq / 2 * 1000;
+
+        clocksource_mips.rating = 200 + mips_hpt_frequency / 10000000;
+
+        clocksource_set_clock(&clocksource_mips, mips_hpt_frequency);
+
+        clocksource_register(&clocksource_mips);
+}
+
+/**
+ * struct tim_c - free running counter
+ * @hi: High 16 bits of the counter
+ * @lo: Low 32 bits of the counter
+ *
+ * Lays out the structure of the free running counter in memory. This counter
+ * increments at a rate of 27 MHz/8 on all platforms.
+ */
+struct tim_c {
+        unsigned int hi;
+        unsigned int lo;
+};
+
+static struct tim_c *tim_c;
+
+static cycle_t tim_c_read(struct clocksource *cs)
+{
+        unsigned int hi;
+        unsigned int next_hi;
+        unsigned int lo;
+
+        hi = readl(&tim_c->hi);
+
+        for (;;) {
+                lo = readl(&tim_c->lo);
+                next_hi = readl(&tim_c->hi);
+                if (next_hi == hi)
+                        break;
+                hi = next_hi;
+        }
+
+pr_crit("%s: read %llx\n", __func__, ((u64) hi << 32) | lo);
+        return ((u64) hi << 32) | lo;
+}
+
+#define TIM_C_SIZE              48              /* # bits in the timer */
+
+static struct clocksource clocksource_tim_c = {
+        .name           = "powertv-tim_c",
+        .read           = tim_c_read,
+        .mask           = CLOCKSOURCE_MASK(TIM_C_SIZE),
+        .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
+};
+
+/**
+ * powertv_tim_c_clocksource_init - set up a clock source for the TIM_C clock
+ *
+ * The hard part here is coming up with a constant k and shift s such that
+ * the 48-bit TIM_C value multiplied by k doesn't overflow and that value,
+ * when shifted right by s, yields the corresponding number of nanoseconds.
+ * We know that TIM_C counts at 27 MHz/8, so each cycle corresponds to
+ * 1 / (27,000,000/8) seconds. Multiply that by a billion and you get the
+ * number of nanoseconds. Since the TIM_C value has 48 bits and the math is
+ * done in 64 bits, avoiding an overflow means that k must be less than
+ * 64 - 48 = 16 bits.
+ */
+static void __init powertv_tim_c_clocksource_init(void)
+{
+        int                     prescale;
+        unsigned long           dividend;
+        unsigned long           k;
+        int                     s;
+        const int               max_k_bits = (64 - 48) - 1;
+        const unsigned long     billion = 1000000000;
+        const unsigned long     counts_per_second = 27000000 / 8;
+
+        prescale = BITS_PER_LONG - ilog2(billion) - 1;
+        dividend = billion << prescale;
+        k = dividend / counts_per_second;
+        s = ilog2(k) - max_k_bits;
+
+        if (s < 0)
+                s = prescale;
+
+        else {
+                k >>= s;
+                s += prescale;
+        }
+
+        clocksource_tim_c.mult = k;
+        clocksource_tim_c.shift = s;
+        clocksource_tim_c.rating = 200;
+
+        clocksource_register(&clocksource_tim_c);
+        tim_c = (struct tim_c *) asic_reg_addr(tim_ch);
+}
+
+/**
+ powertv_clocksource_init - initialize all clocksources
+ */
+void __init powertv_clocksource_init(void)
+{
+        powertv_c0_hpt_clocksource_init();
+        powertv_tim_c_clocksource_init();
+}
diff --git a/arch/mips/kernel/ftrace.c b/arch/mips/kernel/ftrace.c
new file mode 100644
index 000000000000..68b067040d8b
--- /dev/null
+++ b/arch/mips/kernel/ftrace.c
@@ -0,0 +1,275 @@
+/*
+ * Code for replacing ftrace calls with jumps.
+ *
+ * Copyright (C) 2007-2008 Steven Rostedt <srostedt@redhat.com>
+ * Copyright (C) 2009 DSLab, Lanzhou University, China
+ * Author: Wu Zhangjin <wuzj@lemote.com>
+ *
+ * Thanks goes to Steven Rostedt for writing the original x86 version.
+ */
+
+#include <linux/uaccess.h>
+#include <linux/init.h>
+#include <linux/ftrace.h>
+
+#include <asm/cacheflush.h>
+#include <asm/asm.h>
+#include <asm/asm-offsets.h>
+
+#ifdef CONFIG_DYNAMIC_FTRACE
+
+#define JAL 0x0c000000          /* jump & link: ip --> ra, jump to target */
+#define ADDR_MASK 0x03ffffff    /*  op_code|addr : 31...26|25 ....0 */
+#define jump_insn_encode(op_code, addr) \
+        ((unsigned int)((op_code) | (((addr) >> 2) & ADDR_MASK)))
+
+static unsigned int ftrace_nop = 0x00000000;
+
+static int ftrace_modify_code(unsigned long ip, unsigned int new_code)
+{
+        int faulted;
+
+        /* *(unsigned int *)ip = new_code; */
+        safe_store_code(new_code, ip, faulted);
+
+        if (unlikely(faulted))
+                return -EFAULT;
+
+        flush_icache_range(ip, ip + 8);
+
+        return 0;
+}
+
+static int lui_v1;
+static int jal_mcount;
+
+int ftrace_make_nop(struct module *mod,
+                    struct dyn_ftrace *rec, unsigned long addr)
+{
+        unsigned int new;
+        int faulted;
+        unsigned long ip = rec->ip;
+
+        /* We have compiled module with -mlong-calls, but compiled the kernel
+         * without it, we need to cope with them respectively. */
+        if (ip & 0x40000000) {
+                /* record it for ftrace_make_call */
+                if (lui_v1 == 0) {
+                        /* lui_v1 = *(unsigned int *)ip; */
+                        safe_load_code(lui_v1, ip, faulted);
+
+                        if (unlikely(faulted))
+                                return -EFAULT;
+                }
+
+                /* lui v1, hi_16bit_of_mcount        --> b 1f (0x10000004)
+                 * addiu v1, v1, low_16bit_of_mcount
+                 * move at, ra
+                 * jalr v1
+                 * nop
+                 *                                   1f: (ip + 12)
+                 */
+                new = 0x10000004;
+        } else {
+                /* record/calculate it for ftrace_make_call */
+                if (jal_mcount == 0) {
+                        /* We can record it directly like this:
+                         *     jal_mcount = *(unsigned int *)ip;
+                         * Herein, jump over the first two nop instructions */
+                        jal_mcount = jump_insn_encode(JAL, (MCOUNT_ADDR + 8));
+                }
+
+                /* move at, ra
+                 * jalr v1              --> nop
+                 */
+                new = ftrace_nop;
+        }
+        return ftrace_modify_code(ip, new);
+}
+
+static int modified;    /* initialized as 0 by default */
+
+int ftrace_make_call(struct dyn_ftrace *rec, unsigned long addr)
+{
+        unsigned int new;
+        unsigned long ip = rec->ip;
+
+        /* We just need to remove the "b ftrace_stub" at the fist time! */
+        if (modified == 0) {
+                modified = 1;
+                ftrace_modify_code(addr, ftrace_nop);
+        }
+        /* ip, module: 0xc0000000, kernel: 0x80000000 */
+        new = (ip & 0x40000000) ? lui_v1 : jal_mcount;
+
+        return ftrace_modify_code(ip, new);
+}
+
+#define FTRACE_CALL_IP ((unsigned long)(&ftrace_call))
+
+int ftrace_update_ftrace_func(ftrace_func_t func)
+{
+        unsigned int new;
+
+        new = jump_insn_encode(JAL, (unsigned long)func);
+
+        return ftrace_modify_code(FTRACE_CALL_IP, new);
+}
+
+int __init ftrace_dyn_arch_init(void *data)
+{
+        /* The return code is retured via data */
+        *(unsigned long *)data = 0;
+
+        return 0;
+}
+#endif                          /* CONFIG_DYNAMIC_FTRACE */
+
+#ifdef CONFIG_FUNCTION_GRAPH_TRACER
+
+#ifdef CONFIG_DYNAMIC_FTRACE
+
+extern void ftrace_graph_call(void);
+#define JMP     0x08000000      /* jump to target directly */
+#define CALL_FTRACE_GRAPH_CALLER \
+        jump_insn_encode(JMP, (unsigned long)(&ftrace_graph_caller))
+#define FTRACE_GRAPH_CALL_IP    ((unsigned long)(&ftrace_graph_call))
+
+int ftrace_enable_ftrace_graph_caller(void)
+{
+        return ftrace_modify_code(FTRACE_GRAPH_CALL_IP,
+                                  CALL_FTRACE_GRAPH_CALLER);
+}
+
+int ftrace_disable_ftrace_graph_caller(void)
+{
+        return ftrace_modify_code(FTRACE_GRAPH_CALL_IP, ftrace_nop);
+}
+
+#endif                          /* !CONFIG_DYNAMIC_FTRACE */
+
+#ifndef KBUILD_MCOUNT_RA_ADDRESS
+#define S_RA_SP (0xafbf << 16)  /* s{d,w} ra, offset(sp) */
+#define S_R_SP  (0xafb0 << 16)  /* s{d,w} R, offset(sp) */
+#define OFFSET_MASK     0xffff  /* stack offset range: 0 ~ PT_SIZE */
+
+unsigned long ftrace_get_parent_addr(unsigned long self_addr,
+                                     unsigned long parent,
+                                     unsigned long parent_addr,
+                                     unsigned long fp)
+{
+        unsigned long sp, ip, ra;
+        unsigned int code;
+        int faulted;
+
+        /* in module or kernel? */
+        if (self_addr & 0x40000000) {
+                /* module: move to the instruction "lui v1, HI_16BIT_OF_MCOUNT" */
+                ip = self_addr - 20;
+        } else {
+                /* kernel: move to the instruction "move ra, at" */
+                ip = self_addr - 12;
+        }
+
+        /* search the text until finding the non-store instruction or "s{d,w}
+         * ra, offset(sp)" instruction */
+        do {
+                ip -= 4;
+
+                /* get the code at "ip": code = *(unsigned int *)ip; */
+                safe_load_code(code, ip, faulted);
+
+                if (unlikely(faulted))
+                        return 0;
+
+                /* If we hit the non-store instruction before finding where the
+                 * ra is stored, then this is a leaf function and it does not
+                 * store the ra on the stack. */
+                if ((code & S_R_SP) != S_R_SP)
+                        return parent_addr;
+
+        } while (((code & S_RA_SP) != S_RA_SP));
+
+        sp = fp + (code & OFFSET_MASK);
+
+        /* ra = *(unsigned long *)sp; */
+        safe_load_stack(ra, sp, faulted);
+        if (unlikely(faulted))
+                return 0;
+
+        if (ra == parent)
+                return sp;
+        return 0;
+}
+
+#endif
+
+/*
+ * Hook the return address and push it in the stack of return addrs
+ * in current thread info.
+ */
+void prepare_ftrace_return(unsigned long *parent, unsigned long self_addr,
+                           unsigned long fp)
+{
+        unsigned long old;
+        struct ftrace_graph_ent trace;
+        unsigned long return_hooker = (unsigned long)
+            &return_to_handler;
+        int faulted;
+
+        if (unlikely(atomic_read(&current->tracing_graph_pause)))
+                return;
+
+        /* "parent" is the stack address saved the return address of the caller
+         * of _mcount.
+         *
+         * if the gcc < 4.5, a leaf function does not save the return address
+         * in the stack address, so, we "emulate" one in _mcount's stack space,
+         * and hijack it directly, but for a non-leaf function, it save the
+         * return address to the its own stack space, we can not hijack it
+         * directly, but need to find the real stack address,
+         * ftrace_get_parent_addr() does it!
+         *
+         * if gcc>= 4.5, with the new -mmcount-ra-address option, for a
+         * non-leaf function, the location of the return address will be saved
+         * to $12 for us, and for a leaf function, only put a zero into $12. we
+         * do it in ftrace_graph_caller of mcount.S.
+         */
+
+        /* old = *parent; */
+        safe_load_stack(old, parent, faulted);
+        if (unlikely(faulted))
+                goto out;
+#ifndef KBUILD_MCOUNT_RA_ADDRESS
+        parent = (unsigned long *)ftrace_get_parent_addr(self_addr, old,
+                                                         (unsigned long)parent,
+                                                         fp);
+        /* If fails when getting the stack address of the non-leaf function's
+         * ra, stop function graph tracer and return */
+        if (parent == 0)
+                goto out;
+#endif
+        /* *parent = return_hooker; */
+        safe_store_stack(return_hooker, parent, faulted);
+        if (unlikely(faulted))
+                goto out;
+
+        if (ftrace_push_return_trace(old, self_addr, &trace.depth, fp) ==
+            -EBUSY) {
+                *parent = old;
+                return;
+        }
+
+        trace.func = self_addr;
+
+        /* Only trace if the calling function expects to */
+        if (!ftrace_graph_entry(&trace)) {
+                current->curr_ret_stack--;
+                *parent = old;
+        }
+        return;
+out:
+        ftrace_graph_stop();
+        WARN_ON(1);
+}
+#endif                          /* CONFIG_FUNCTION_GRAPH_TRACER */
diff --git a/arch/mips/kernel/irq.c b/arch/mips/kernel/irq.c
index 7b845ba9dff4..981f86c26168 100644
--- a/arch/mips/kernel/irq.c
+++ b/arch/mips/kernel/irq.c
@@ -22,6 +22,7 @@
 #include <linux/seq_file.h>
 #include <linux/kallsyms.h>
 #include <linux/kgdb.h>
+#include <linux/ftrace.h>
 
 #include <asm/atomic.h>
 #include <asm/system.h>
@@ -99,7 +100,7 @@ int show_interrupts(struct seq_file *p, void *v)
         }
 
         if (i < NR_IRQS) {
-                spin_lock_irqsave(&irq_desc[i].lock, flags);
+                raw_spin_lock_irqsave(&irq_desc[i].lock, flags);
                 action = irq_desc[i].action;
                 if (!action)
                         goto skip;
@@ -118,7 +119,7 @@ int show_interrupts(struct seq_file *p, void *v)
 
                 seq_putc(p, '\n');
 skip:
-                spin_unlock_irqrestore(&irq_desc[i].lock, flags);
+                raw_spin_unlock_irqrestore(&irq_desc[i].lock, flags);
         } else if (i == NR_IRQS) {
                 seq_putc(p, '\n');
                 seq_printf(p, "ERR: %10u\n", atomic_read(&irq_err_count));
@@ -150,3 +151,32 @@ void __init init_IRQ(void)
                 kgdb_early_setup = 1;
 #endif
 }
+
+/*
+ * do_IRQ handles all normal device IRQ's (the special
+ * SMP cross-CPU interrupts have their own specific
+ * handlers).
+ */
+void __irq_entry do_IRQ(unsigned int irq)
+{
+        irq_enter();
+        __DO_IRQ_SMTC_HOOK(irq);
+        generic_handle_irq(irq);
+        irq_exit();
+}
+
+#ifdef CONFIG_MIPS_MT_SMTC_IRQAFF
+/*
+ * To avoid inefficient and in some cases pathological re-checking of
+ * IRQ affinity, we have this variant that skips the affinity check.
+ */
+
+void __irq_entry do_IRQ_no_affinity(unsigned int irq)
+{
+        irq_enter();
+        __NO_AFFINITY_IRQ_SMTC_HOOK(irq);
+        generic_handle_irq(irq);
+        irq_exit();
+}
+
+#endif /* CONFIG_MIPS_MT_SMTC_IRQAFF */
diff --git a/arch/mips/kernel/kspd.c b/arch/mips/kernel/kspd.c
index ad4e017ed2f3..80e2ba694bab 100644
--- a/arch/mips/kernel/kspd.c
+++ b/arch/mips/kernel/kspd.c
@@ -82,6 +82,7 @@ static int sp_stopping;
 #define MTSP_O_SHLOCK           0x0010
 #define MTSP_O_EXLOCK           0x0020
 #define MTSP_O_ASYNC            0x0040
+/* XXX: check which of these is actually O_SYNC vs O_DSYNC */
 #define MTSP_O_FSYNC            O_SYNC
 #define MTSP_O_NOFOLLOW         0x0100
 #define MTSP_O_SYNC             0x0080
diff --git a/arch/mips/kernel/linux32.c b/arch/mips/kernel/linux32.c
index 1a2793efdc4e..f042563c924f 100644
--- a/arch/mips/kernel/linux32.c
+++ b/arch/mips/kernel/linux32.c
@@ -67,28 +67,13 @@ SYSCALL_DEFINE6(32_mmap2, unsigned long, addr, unsigned long, len,
         unsigned long, prot, unsigned long, flags, unsigned long, fd,
         unsigned long, pgoff)
 {
-        struct file * file = NULL;
         unsigned long error;
 
         error = -EINVAL;
         if (pgoff & (~PAGE_MASK >> 12))
                 goto out;
-        pgoff >>= PAGE_SHIFT-12;
-
-        if (!(flags & MAP_ANONYMOUS)) {
-                error = -EBADF;
-                file = fget(fd);
-                if (!file)
-                        goto out;
-        }
-        flags &= ~(MAP_EXECUTABLE | MAP_DENYWRITE);
-
-        down_write(&current->mm->mmap_sem);
-        error = do_mmap_pgoff(file, addr, len, prot, flags, pgoff);
-        up_write(&current->mm->mmap_sem);
-        if (file)
-                fput(file);
-
+        error = sys_mmap_pgoff(addr, len, prot, flags, fd,
+                               pgoff >> (PAGE_SHIFT-12));
 out:
         return error;
 }
diff --git a/arch/mips/kernel/mcount.S b/arch/mips/kernel/mcount.S
new file mode 100644
index 000000000000..0a9cfdb271dd
--- /dev/null
+++ b/arch/mips/kernel/mcount.S
@@ -0,0 +1,189 @@
+/*
+ * MIPS specific _mcount support
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive for
+ * more details.
+ *
+ * Copyright (C) 2009 Lemote Inc. & DSLab, Lanzhou University, China
+ * Author: Wu Zhangjin <wuzj@lemote.com>
+ */
+
+#include <asm/regdef.h>
+#include <asm/stackframe.h>
+#include <asm/ftrace.h>
+
+        .text
+        .set noreorder
+        .set noat
+
+        .macro MCOUNT_SAVE_REGS
+        PTR_SUBU        sp, PT_SIZE
+        PTR_S   ra, PT_R31(sp)
+        PTR_S   AT, PT_R1(sp)
+        PTR_S   a0, PT_R4(sp)
+        PTR_S   a1, PT_R5(sp)
+        PTR_S   a2, PT_R6(sp)
+        PTR_S   a3, PT_R7(sp)
+#ifdef CONFIG_64BIT
+        PTR_S   a4, PT_R8(sp)
+        PTR_S   a5, PT_R9(sp)
+        PTR_S   a6, PT_R10(sp)
+        PTR_S   a7, PT_R11(sp)
+#endif
+        .endm
+
+        .macro MCOUNT_RESTORE_REGS
+        PTR_L   ra, PT_R31(sp)
+        PTR_L   AT, PT_R1(sp)
+        PTR_L   a0, PT_R4(sp)
+        PTR_L   a1, PT_R5(sp)
+        PTR_L   a2, PT_R6(sp)
+        PTR_L   a3, PT_R7(sp)
+#ifdef CONFIG_64BIT
+        PTR_L   a4, PT_R8(sp)
+        PTR_L   a5, PT_R9(sp)
+        PTR_L   a6, PT_R10(sp)
+        PTR_L   a7, PT_R11(sp)
+#endif
+#ifdef CONFIG_64BIT
+        PTR_ADDIU       sp, PT_SIZE
+#else
+        PTR_ADDIU       sp, (PT_SIZE + 8)
+#endif
+.endm
+
+        .macro RETURN_BACK
+        jr ra
+         move ra, AT
+        .endm
+
+#ifdef CONFIG_DYNAMIC_FTRACE
+
+NESTED(ftrace_caller, PT_SIZE, ra)
+        .globl _mcount
+_mcount:
+        b       ftrace_stub
+         nop
+        lw      t1, function_trace_stop
+        bnez    t1, ftrace_stub
+         nop
+
+        MCOUNT_SAVE_REGS
+#ifdef KBUILD_MCOUNT_RA_ADDRESS
+        PTR_S   t0, PT_R12(sp)  /* t0 saved the location of the return address(at) by -mmcount-ra-address */
+#endif
+
+        move    a0, ra          /* arg1: next ip, selfaddr */
+        .globl ftrace_call
+ftrace_call:
+        nop     /* a placeholder for the call to a real tracing function */
+         move   a1, AT          /* arg2: the caller's next ip, parent */
+
+#ifdef CONFIG_FUNCTION_GRAPH_TRACER
+        .globl ftrace_graph_call
+ftrace_graph_call:
+        nop
+         nop
+#endif
+
+        MCOUNT_RESTORE_REGS
+        .globl ftrace_stub
+ftrace_stub:
+        RETURN_BACK
+        END(ftrace_caller)
+
+#else   /* ! CONFIG_DYNAMIC_FTRACE */
+
+NESTED(_mcount, PT_SIZE, ra)
+        lw      t1, function_trace_stop
+        bnez    t1, ftrace_stub
+         nop
+        PTR_LA  t1, ftrace_stub
+        PTR_L   t2, ftrace_trace_function /* Prepare t2 for (1) */
+        bne     t1, t2, static_trace
+         nop
+
+#ifdef  CONFIG_FUNCTION_GRAPH_TRACER
+        PTR_L   t3, ftrace_graph_return
+        bne     t1, t3, ftrace_graph_caller
+         nop
+        PTR_LA  t1, ftrace_graph_entry_stub
+        PTR_L   t3, ftrace_graph_entry
+        bne     t1, t3, ftrace_graph_caller
+         nop
+#endif
+        b       ftrace_stub
+         nop
+
+static_trace:
+        MCOUNT_SAVE_REGS
+
+        move    a0, ra          /* arg1: next ip, selfaddr */
+        jalr    t2              /* (1) call *ftrace_trace_function */
+         move   a1, AT          /* arg2: the caller's next ip, parent */
+
+        MCOUNT_RESTORE_REGS
+        .globl ftrace_stub
+ftrace_stub:
+        RETURN_BACK
+        END(_mcount)
+
+#endif  /* ! CONFIG_DYNAMIC_FTRACE */
+
+#ifdef CONFIG_FUNCTION_GRAPH_TRACER
+
+NESTED(ftrace_graph_caller, PT_SIZE, ra)
+#ifdef CONFIG_DYNAMIC_FTRACE
+        PTR_L   a1, PT_R31(sp)  /* load the original ra from the stack */
+#ifdef KBUILD_MCOUNT_RA_ADDRESS
+        PTR_L   t0, PT_R12(sp)  /* load the original t0 from the stack */
+#endif
+#else
+        MCOUNT_SAVE_REGS
+        move    a1, ra          /* arg2: next ip, selfaddr */
+#endif
+
+#ifdef KBUILD_MCOUNT_RA_ADDRESS
+        bnez    t0, 1f          /* non-leaf func: t0 saved the location of the return address */
+         nop
+        PTR_LA  t0, PT_R1(sp)   /* leaf func: get the location of at(old ra) from our own stack */
+1:      move    a0, t0          /* arg1: the location of the return address */
+#else
+        PTR_LA  a0, PT_R1(sp)   /* arg1: &AT -> a0 */
+#endif
+        jal     prepare_ftrace_return
+#ifdef CONFIG_FRAME_POINTER
+         move   a2, fp          /* arg3: frame pointer */
+#else
+#ifdef CONFIG_64BIT
+         PTR_LA a2, PT_SIZE(sp)
+#else
+         PTR_LA a2, (PT_SIZE+8)(sp)
+#endif
+#endif
+
+        MCOUNT_RESTORE_REGS
+        RETURN_BACK
+        END(ftrace_graph_caller)
+
+        .align  2
+        .globl  return_to_handler
+return_to_handler:
+        PTR_SUBU        sp, PT_SIZE
+        PTR_S   v0, PT_R2(sp)
+
+        jal     ftrace_return_to_handler
+         PTR_S  v1, PT_R3(sp)
+
+        /* restore the real parent address: v0 -> ra */
+        move    ra, v0
+
+        PTR_L   v0, PT_R2(sp)
+        PTR_L   v1, PT_R3(sp)
+        jr      ra
+         PTR_ADDIU      sp, PT_SIZE
+#endif /* CONFIG_FUNCTION_GRAPH_TRACER */
+
+        .set at
+        .set reorder
diff --git a/arch/mips/kernel/mips_ksyms.c b/arch/mips/kernel/mips_ksyms.c
index 225755d0c1f6..1d04807874db 100644
--- a/arch/mips/kernel/mips_ksyms.c
+++ b/arch/mips/kernel/mips_ksyms.c
@@ -13,6 +13,7 @@
 #include <asm/checksum.h>
 #include <asm/pgtable.h>
 #include <asm/uaccess.h>
+#include <asm/ftrace.h>
 
 extern void *__bzero(void *__s, size_t __count);
 extern long __strncpy_from_user_nocheck_asm(char *__to,
@@ -51,3 +52,7 @@ EXPORT_SYMBOL(csum_partial_copy_nocheck);
 EXPORT_SYMBOL(__csum_partial_copy_user);
 
 EXPORT_SYMBOL(invalid_pte_table);
+#ifdef CONFIG_FUNCTION_TRACER
+/* _mcount is defined in arch/mips/kernel/mcount.S */
+EXPORT_SYMBOL(_mcount);
+#endif
diff --git a/arch/mips/kernel/setup.c b/arch/mips/kernel/setup.c
index 2b290d70083e..f9513f9e61d3 100644
--- a/arch/mips/kernel/setup.c
+++ b/arch/mips/kernel/setup.c
@@ -58,8 +58,12 @@ EXPORT_SYMBOL(mips_machtype);
 
 struct boot_mem_map boot_mem_map;
 
-static char command_line[CL_SIZE];
-       char arcs_cmdline[CL_SIZE]=CONFIG_CMDLINE;
+static char __initdata command_line[COMMAND_LINE_SIZE];
+char __initdata arcs_cmdline[COMMAND_LINE_SIZE];
+
+#ifdef CONFIG_CMDLINE_BOOL
+static char __initdata builtin_cmdline[COMMAND_LINE_SIZE] = CONFIG_CMDLINE;
+#endif
 
 /*
  * mips_io_port_base is the begin of the address space to which x86 style
@@ -166,26 +170,8 @@ static unsigned long __init init_initrd(void)
          * already set up initrd_start and initrd_end. In these cases
          * perfom sanity checks and use them if all looks good.
          */
-        if (!initrd_start || initrd_end <= initrd_start) {
-#ifdef CONFIG_PROBE_INITRD_HEADER
-                u32 *initrd_header;
-
-                /*
-                 * See if initrd has been added to the kernel image by
-                 * arch/mips/boot/addinitrd.c. In that case a header is
-                 * prepended to initrd and is made up by 8 bytes. The first
-                 * word is a magic number and the second one is the size of
-                 * initrd.  Initrd start must be page aligned in any cases.
-                 */
-                initrd_header = __va(PAGE_ALIGN(__pa_symbol(&_end) + 8)) - 8;
-                if (initrd_header[0] != 0x494E5244)
-                        goto disable;
-                initrd_start = (unsigned long)(initrd_header + 2);
-                initrd_end = initrd_start + initrd_header[1];
-#else
+        if (!initrd_start || initrd_end <= initrd_start)
                 goto disable;
-#endif
-        }
 
         if (initrd_start & ~PAGE_MASK) {
                 pr_err("initrd start must be page aligned\n");
@@ -476,8 +462,20 @@ static void __init arch_mem_init(char **cmdline_p)
         pr_info("Determined physical RAM map:\n");
         print_memory_map();
 
-        strlcpy(command_line, arcs_cmdline, sizeof(command_line));
-        strlcpy(boot_command_line, command_line, COMMAND_LINE_SIZE);
+#ifdef CONFIG_CMDLINE_BOOL
+#ifdef CONFIG_CMDLINE_OVERRIDE
+        strlcpy(boot_command_line, builtin_cmdline, COMMAND_LINE_SIZE);
+#else
+        if (builtin_cmdline[0]) {
+                strlcat(arcs_cmdline, " ", COMMAND_LINE_SIZE);
+                strlcat(arcs_cmdline, builtin_cmdline, COMMAND_LINE_SIZE);
+        }
+        strlcpy(boot_command_line, arcs_cmdline, COMMAND_LINE_SIZE);
+#endif
+#else
+        strlcpy(boot_command_line, arcs_cmdline, COMMAND_LINE_SIZE);
+#endif
+        strlcpy(command_line, boot_command_line, COMMAND_LINE_SIZE);
 
         *cmdline_p = command_line;
 
diff --git a/arch/mips/kernel/signal.c b/arch/mips/kernel/signal.c
index 6254041b942f..d0c68b5d717b 100644
--- a/arch/mips/kernel/signal.c
+++ b/arch/mips/kernel/signal.c
@@ -35,6 +35,15 @@
 
 #include "signal-common.h"
 
+static int (*save_fp_context)(struct sigcontext __user *sc);
+static int (*restore_fp_context)(struct sigcontext __user *sc);
+
+extern asmlinkage int _save_fp_context(struct sigcontext __user *sc);
+extern asmlinkage int _restore_fp_context(struct sigcontext __user *sc);
+
+extern asmlinkage int fpu_emulator_save_context(struct sigcontext __user *sc);
+extern asmlinkage int fpu_emulator_restore_context(struct sigcontext __user *sc);
+
 /*
  * Horribly complicated - with the bloody RM9000 workarounds enabled
  * the signal trampolines is moving to the end of the structure so we can
@@ -709,3 +718,40 @@ asmlinkage void do_notify_resume(struct pt_regs *regs, void *unused,
                         key_replace_session_keyring();
         }
 }
+
+#ifdef CONFIG_SMP
+static int smp_save_fp_context(struct sigcontext __user *sc)
+{
+        return raw_cpu_has_fpu
+               ? _save_fp_context(sc)
+               : fpu_emulator_save_context(sc);
+}
+
+static int smp_restore_fp_context(struct sigcontext __user *sc)
+{
+        return raw_cpu_has_fpu
+               ? _restore_fp_context(sc)
+               : fpu_emulator_restore_context(sc);
+}
+#endif
+
+static int signal_setup(void)
+{
+#ifdef CONFIG_SMP
+        /* For now just do the cpu_has_fpu check when the functions are invoked */
+        save_fp_context = smp_save_fp_context;
+        restore_fp_context = smp_restore_fp_context;
+#else
+        if (cpu_has_fpu) {
+                save_fp_context = _save_fp_context;
+                restore_fp_context = _restore_fp_context;
+        } else {
+                save_fp_context = fpu_emulator_save_context;
+                restore_fp_context = fpu_emulator_restore_context;
+        }
+#endif
+
+        return 0;
+}
+
+arch_initcall(signal_setup);
diff --git a/arch/mips/kernel/signal32.c b/arch/mips/kernel/signal32.c
index 2e74075ac0ca..03abaf048f09 100644
--- a/arch/mips/kernel/signal32.c
+++ b/arch/mips/kernel/signal32.c
@@ -35,6 +35,15 @@
 
 #include "signal-common.h"
 
+static int (*save_fp_context32)(struct sigcontext32 __user *sc);
+static int (*restore_fp_context32)(struct sigcontext32 __user *sc);
+
+extern asmlinkage int _save_fp_context32(struct sigcontext32 __user *sc);
+extern asmlinkage int _restore_fp_context32(struct sigcontext32 __user *sc);
+
+extern asmlinkage int fpu_emulator_save_context32(struct sigcontext32 __user *sc);
+extern asmlinkage int fpu_emulator_restore_context32(struct sigcontext32 __user *sc);
+
 /*
  * Including <asm/unistd.h> would give use the 64-bit syscall numbers ...
  */
@@ -828,3 +837,18 @@ SYSCALL_DEFINE5(32_waitid, int, which, compat_pid_t, pid,
         info.si_code |= __SI_CHLD;
         return copy_siginfo_to_user32(uinfo, &info);
 }
+
+static int signal32_init(void)
+{
+        if (cpu_has_fpu) {
+                save_fp_context32 = _save_fp_context32;
+                restore_fp_context32 = _restore_fp_context32;
+        } else {
+                save_fp_context32 = fpu_emulator_save_context32;
+                restore_fp_context32 = fpu_emulator_restore_context32;
+        }
+
+        return 0;
+}
+
+arch_initcall(signal32_init);
diff --git a/arch/mips/kernel/smp.c b/arch/mips/kernel/smp.c
index e72e6844d134..6cdca1956b77 100644
--- a/arch/mips/kernel/smp.c
+++ b/arch/mips/kernel/smp.c
@@ -32,6 +32,7 @@
 #include <linux/cpumask.h>
 #include <linux/cpu.h>
 #include <linux/err.h>
+#include <linux/ftrace.h>
 
 #include <asm/atomic.h>
 #include <asm/cpu.h>
@@ -130,7 +131,7 @@ asmlinkage __cpuinit void start_secondary(void)
 /*
  * Call into both interrupt handlers, as we share the IPI for them
  */
-void smp_call_function_interrupt(void)
+void __irq_entry smp_call_function_interrupt(void)
 {
         irq_enter();
         generic_smp_call_function_single_interrupt();
diff --git a/arch/mips/kernel/smtc.c b/arch/mips/kernel/smtc.c
index a38e3ee95515..23499b5bd9c3 100644
--- a/arch/mips/kernel/smtc.c
+++ b/arch/mips/kernel/smtc.c
@@ -25,6 +25,7 @@
 #include <linux/interrupt.h>
 #include <linux/kernel_stat.h>
 #include <linux/module.h>
+#include <linux/ftrace.h>
 
 #include <asm/cpu.h>
 #include <asm/processor.h>
@@ -939,23 +940,29 @@ static void ipi_call_interrupt(void)
 
 DECLARE_PER_CPU(struct clock_event_device, mips_clockevent_device);
 
-void ipi_decode(struct smtc_ipi *pipi)
+static void __irq_entry smtc_clock_tick_interrupt(void)
 {
         unsigned int cpu = smp_processor_id();
         struct clock_event_device *cd;
+        int irq = MIPS_CPU_IRQ_BASE + 1;
+
+        irq_enter();
+        kstat_incr_irqs_this_cpu(irq, irq_to_desc(irq));
+        cd = &per_cpu(mips_clockevent_device, cpu);
+        cd->event_handler(cd);
+        irq_exit();
+}
+
+void ipi_decode(struct smtc_ipi *pipi)
+{
         void *arg_copy = pipi->arg;
         int type_copy = pipi->type;
-        int irq = MIPS_CPU_IRQ_BASE + 1;
 
         smtc_ipi_nq(&freeIPIq, pipi);
 
         switch (type_copy) {
         case SMTC_CLOCK_TICK:
-                irq_enter();
-                kstat_incr_irqs_this_cpu(irq, irq_to_desc(irq));
-                cd = &per_cpu(mips_clockevent_device, cpu);
-                cd->event_handler(cd);
-                irq_exit();
+                smtc_clock_tick_interrupt();
                 break;
 
         case LINUX_SMP_IPI:
diff --git a/arch/mips/kernel/syscall.c b/arch/mips/kernel/syscall.c
index fe0d79805603..3f7f466190b4 100644
--- a/arch/mips/kernel/syscall.c
+++ b/arch/mips/kernel/syscall.c
@@ -93,7 +93,8 @@ unsigned long arch_get_unmapped_area(struct file *filp, unsigned long addr,
                  * We do not accept a shared mapping if it would violate
                  * cache aliasing constraints.
                  */
-                if ((flags & MAP_SHARED) && (addr & shm_align_mask))
+                if ((flags & MAP_SHARED) &&
+                    ((addr - (pgoff << PAGE_SHIFT)) & shm_align_mask))
                         return -EINVAL;
                 return addr;
         }
@@ -129,31 +130,6 @@ unsigned long arch_get_unmapped_area(struct file *filp, unsigned long addr,
         }
 }
 
-/* common code for old and new mmaps */
-static inline unsigned long
-do_mmap2(unsigned long addr, unsigned long len, unsigned long prot,
-        unsigned long flags, unsigned long fd, unsigned long pgoff)
-{
-        unsigned long error = -EBADF;
-        struct file * file = NULL;
-
-        flags &= ~(MAP_EXECUTABLE | MAP_DENYWRITE);
-        if (!(flags & MAP_ANONYMOUS)) {
-                file = fget(fd);
-                if (!file)
-                        goto out;
-        }
-
-        down_write(&current->mm->mmap_sem);
-        error = do_mmap_pgoff(file, addr, len, prot, flags, pgoff);
-        up_write(&current->mm->mmap_sem);
-
-        if (file)
-                fput(file);
-out:
-        return error;
-}
-
 SYSCALL_DEFINE6(mips_mmap, unsigned long, addr, unsigned long, len,
         unsigned long, prot, unsigned long, flags, unsigned long,
         fd, off_t, offset)
@@ -164,7 +140,7 @@ SYSCALL_DEFINE6(mips_mmap, unsigned long, addr, unsigned long, len,
         if (offset & ~PAGE_MASK)
                 goto out;
 
-        result = do_mmap2(addr, len, prot, flags, fd, offset >> PAGE_SHIFT);
+        result = sys_mmap_pgoff(addr, len, prot, flags, fd, offset >> PAGE_SHIFT);
 
 out:
         return result;
@@ -177,7 +153,7 @@ SYSCALL_DEFINE6(mips_mmap2, unsigned long, addr, unsigned long, len,
         if (pgoff & (~PAGE_MASK >> 12))
                 return -EINVAL;
 
-        return do_mmap2(addr, len, prot, flags, fd, pgoff >> (PAGE_SHIFT-12));
+        return sys_mmap_pgoff(addr, len, prot, flags, fd, pgoff >> (PAGE_SHIFT-12));
 }
 
 save_static_function(sys_fork);
diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index 0a18b4c62afb..308e43460864 100644
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -25,10 +25,12 @@
 #include <linux/ptrace.h>
 #include <linux/kgdb.h>
 #include <linux/kdebug.h>
+#include <linux/notifier.h>
 
 #include <asm/bootinfo.h>
 #include <asm/branch.h>
 #include <asm/break.h>
+#include <asm/cop2.h>
 #include <asm/cpu.h>
 #include <asm/dsp.h>
 #include <asm/fpu.h>
@@ -79,10 +81,6 @@ extern asmlinkage void handle_reserved(void);
 extern int fpu_emulator_cop1Handler(struct pt_regs *xcp,
         struct mips_fpu_struct *ctx, int has_fpu);
 
-#ifdef CONFIG_CPU_CAVIUM_OCTEON
-extern asmlinkage void octeon_cop2_restore(struct octeon_cop2_state *task);
-#endif
-
 void (*board_be_init)(void);
 int (*board_be_handler)(struct pt_regs *regs, int is_fixup);
 void (*board_nmi_handler_setup)(void);
@@ -857,6 +855,44 @@ static void mt_ase_fp_affinity(void)
 #endif /* CONFIG_MIPS_MT_FPAFF */
 }
 
+/*
+ * No lock; only written during early bootup by CPU 0.
+ */
+static RAW_NOTIFIER_HEAD(cu2_chain);
+
+int __ref register_cu2_notifier(struct notifier_block *nb)
+{
+        return raw_notifier_chain_register(&cu2_chain, nb);
+}
+
+int cu2_notifier_call_chain(unsigned long val, void *v)
+{
+        return raw_notifier_call_chain(&cu2_chain, val, v);
+}
+
+static int default_cu2_call(struct notifier_block *nfb, unsigned long action,
+        void *data)
+{
+        struct pt_regs *regs = data;
+
+        switch (action) {
+        default:
+                die_if_kernel("Unhandled kernel unaligned access or invalid "
+                              "instruction", regs);
+                /* Fall through  */
+
+        case CU2_EXCEPTION:
+                force_sig(SIGILL, current);
+        }
+
+        return NOTIFY_OK;
+}
+
+static struct notifier_block default_cu2_notifier = {
+        .notifier_call  = default_cu2_call,
+        .priority       = 0x80000000,           /* Run last  */
+};
+
 asmlinkage void do_cpu(struct pt_regs *regs)
 {
         unsigned int __user *epc;
@@ -920,17 +956,9 @@ asmlinkage void do_cpu(struct pt_regs *regs)
                 return;
 
         case 2:
-#ifdef CONFIG_CPU_CAVIUM_OCTEON
-                prefetch(&current->thread.cp2);
-                local_irq_save(flags);
-                KSTK_STATUS(current) |= ST0_CU2;
-                status = read_c0_status();
-                write_c0_status(status | ST0_CU2);
-                octeon_cop2_restore(&(current->thread.cp2));
-                write_c0_status(status & ~ST0_CU2);
-                local_irq_restore(flags);
-                return;
-#endif
+                raw_notifier_call_chain(&cu2_chain, CU2_EXCEPTION, regs);
+                break;
+
         case 3:
                 break;
         }
@@ -1367,77 +1395,6 @@ void *set_vi_handler(int n, vi_handler_t addr)
         return set_vi_srs_handler(n, addr, 0);
 }
 
-/*
- * This is used by native signal handling
- */
-asmlinkage int (*save_fp_context)(struct sigcontext __user *sc);
-asmlinkage int (*restore_fp_context)(struct sigcontext __user *sc);
-
-extern asmlinkage int _save_fp_context(struct sigcontext __user *sc);
-extern asmlinkage int _restore_fp_context(struct sigcontext __user *sc);
-
-extern asmlinkage int fpu_emulator_save_context(struct sigcontext __user *sc);
-extern asmlinkage int fpu_emulator_restore_context(struct sigcontext __user *sc);
-
-#ifdef CONFIG_SMP
-static int smp_save_fp_context(struct sigcontext __user *sc)
-{
-        return raw_cpu_has_fpu
-               ? _save_fp_context(sc)
-               : fpu_emulator_save_context(sc);
-}
-
-static int smp_restore_fp_context(struct sigcontext __user *sc)
-{
-        return raw_cpu_has_fpu
-               ? _restore_fp_context(sc)
-               : fpu_emulator_restore_context(sc);
-}
-#endif
-
-static inline void signal_init(void)
-{
-#ifdef CONFIG_SMP
-        /* For now just do the cpu_has_fpu check when the functions are invoked */
-        save_fp_context = smp_save_fp_context;
-        restore_fp_context = smp_restore_fp_context;
-#else
-        if (cpu_has_fpu) {
-                save_fp_context = _save_fp_context;
-                restore_fp_context = _restore_fp_context;
-        } else {
-                save_fp_context = fpu_emulator_save_context;
-                restore_fp_context = fpu_emulator_restore_context;
-        }
-#endif
-}
-
-#ifdef CONFIG_MIPS32_COMPAT
-
-/*
- * This is used by 32-bit signal stuff on the 64-bit kernel
- */
-asmlinkage int (*save_fp_context32)(struct sigcontext32 __user *sc);
-asmlinkage int (*restore_fp_context32)(struct sigcontext32 __user *sc);
-
-extern asmlinkage int _save_fp_context32(struct sigcontext32 __user *sc);
-extern asmlinkage int _restore_fp_context32(struct sigcontext32 __user *sc);
-
-extern asmlinkage int fpu_emulator_save_context32(struct sigcontext32 __user *sc);
-extern asmlinkage int fpu_emulator_restore_context32(struct sigcontext32 __user *sc);
-
-static inline void signal32_init(void)
-{
-        if (cpu_has_fpu) {
-                save_fp_context32 = _save_fp_context32;
-                restore_fp_context32 = _restore_fp_context32;
-        } else {
-                save_fp_context32 = fpu_emulator_save_context32;
-                restore_fp_context32 = fpu_emulator_restore_context32;
-        }
-}
-#endif
-
 extern void cpu_cache_init(void);
 extern void tlb_init(void);
 extern void flush_tlb_handlers(void);
@@ -1751,13 +1708,10 @@ void __init trap_init(void)
         else
                 memcpy((void *)(ebase + 0x080), &except_vec3_generic, 0x80);
 
-        signal_init();
-#ifdef CONFIG_MIPS32_COMPAT
-        signal32_init();
-#endif
-
         local_flush_icache_range(ebase, ebase + 0x400);
         flush_tlb_handlers();
 
         sort_extable(__start___dbe_table, __stop___dbe_table);
+
+        register_cu2_notifier(&default_cu2_notifier);
 }
diff --git a/arch/mips/kernel/unaligned.c b/arch/mips/kernel/unaligned.c
index 67bd626942ab..69b039ca8d83 100644
--- a/arch/mips/kernel/unaligned.c
+++ b/arch/mips/kernel/unaligned.c
@@ -81,6 +81,7 @@
 #include <asm/asm.h>
 #include <asm/branch.h>
 #include <asm/byteorder.h>
+#include <asm/cop2.h>
 #include <asm/inst.h>
 #include <asm/uaccess.h>
 #include <asm/system.h>
@@ -451,17 +452,27 @@ static void emulate_load_store_insn(struct pt_regs *regs,
                  */
                 goto sigbus;
 
+        /*
+         * COP2 is available to implementor for application specific use.
+         * It's up to applications to register a notifier chain and do
+         * whatever they have to do, including possible sending of signals.
+         */
         case lwc2_op:
+                cu2_notifier_call_chain(CU2_LWC2_OP, regs);
+                break;
+
         case ldc2_op:
+                cu2_notifier_call_chain(CU2_LDC2_OP, regs);
+                break;
+
         case swc2_op:
+                cu2_notifier_call_chain(CU2_SWC2_OP, regs);
+                break;
+
         case sdc2_op:
-                /*
-                 * These are the coprocessor 2 load/stores.  The current
-                 * implementations don't use cp2 and cp2 should always be
-                 * disabled in c0_status.  So send SIGILL.
-                 * (No longer true: The Sony Praystation uses cp2 for
-                 * 3D matrix operations.  Dunno if that thingy has a MMU ...)
-                 */
+                cu2_notifier_call_chain(CU2_SDC2_OP, regs);
+                break;
+
         default:
                 /*
                  * Pheeee...  We encountered an yet unknown instruction or
diff --git a/arch/mips/kernel/vmlinux.lds.S b/arch/mips/kernel/vmlinux.lds.S
index 162b29954baa..f25df73db923 100644
--- a/arch/mips/kernel/vmlinux.lds.S
+++ b/arch/mips/kernel/vmlinux.lds.S
@@ -46,6 +46,7 @@ SECTIONS
                 SCHED_TEXT
                 LOCK_TEXT
                 KPROBES_TEXT
+                IRQENTRY_TEXT
                 *(.text.*)
                 *(.fixup)
                 *(.gnu.warning)
diff --git a/arch/mips/lasat/picvue_proc.c b/arch/mips/lasat/picvue_proc.c
index 0bb6037afba3..8e388da1926f 100644
--- a/arch/mips/lasat/picvue_proc.c
+++ b/arch/mips/lasat/picvue_proc.c
@@ -4,12 +4,14 @@
  * Brian Murphy <brian.murphy@eicon.com>
  *
  */
+#include <linux/bug.h>
 #include <linux/kernel.h>
 #include <linux/module.h>
 #include <linux/init.h>
 #include <linux/errno.h>
 
 #include <linux/proc_fs.h>
+#include <linux/seq_file.h>
 #include <linux/interrupt.h>
 
 #include <linux/timer.h>
@@ -38,12 +40,9 @@ static void pvc_display(unsigned long data)
 
 static DECLARE_TASKLET(pvc_display_tasklet, &pvc_display, 0);
 
-static int pvc_proc_read_line(char *page, char **start,
-                             off_t off, int count,
-                             int *eof, void *data)
+static int pvc_line_proc_show(struct seq_file *m, void *v)
 {
-        char *origpage = page;
-        int lineno = *(int *)data;
+        int lineno = *(int *)m->private;
 
         if (lineno < 0 || lineno > PVC_NLINES) {
                 printk(KERN_WARNING "proc_read_line: invalid lineno %d\n", lineno);
@@ -51,45 +50,66 @@ static int pvc_proc_read_line(char *page, char **start,
         }
 
         mutex_lock(&pvc_mutex);
-        page += sprintf(page, "%s\n", pvc_lines[lineno]);
+        seq_printf(m, "%s\n", pvc_lines[lineno]);
         mutex_unlock(&pvc_mutex);
 
-        return page - origpage;
+        return 0;
 }
 
-static int pvc_proc_write_line(struct file *file, const char *buffer,
-                           unsigned long count, void *data)
+static int pvc_line_proc_open(struct inode *inode, struct file *file)
 {
-        int origcount = count;
-        int lineno = *(int *)data;
+        return single_open(file, pvc_line_proc_show, PDE(inode)->data);
+}
 
-        if (lineno < 0 || lineno > PVC_NLINES) {
-                printk(KERN_WARNING "proc_write_line: invalid lineno %d\n",
-                       lineno);
-                return origcount;
-        }
+static ssize_t pvc_line_proc_write(struct file *file, const char __user *buf,
+                                   size_t count, loff_t *pos)
+{
+        int lineno = *(int *)PDE(file->f_path.dentry->d_inode)->data;
+        char kbuf[PVC_LINELEN];
+        size_t len;
+
+        BUG_ON(lineno < 0 || lineno > PVC_NLINES);
 
-        if (count > PVC_LINELEN)
-                count = PVC_LINELEN;
+        len = min(count, sizeof(kbuf) - 1);
+        if (copy_from_user(kbuf, buf, len))
+                return -EFAULT;
+        kbuf[len] = '\0';
 
-        if (buffer[count-1] == '\n')
-                count--;
+        if (len > 0 && kbuf[len - 1] == '\n')
+                len--;
 
         mutex_lock(&pvc_mutex);
-        strncpy(pvc_lines[lineno], buffer, count);
-        pvc_lines[lineno][count] = '\0';
+        strncpy(pvc_lines[lineno], kbuf, len);
+        pvc_lines[lineno][len] = '\0';
         mutex_unlock(&pvc_mutex);
 
         tasklet_schedule(&pvc_display_tasklet);
 
-        return origcount;
+        return count;
 }
 
-static int pvc_proc_write_scroll(struct file *file, const char *buffer,
-                           unsigned long count, void *data)
+static const struct file_operations pvc_line_proc_fops = {
+        .owner          = THIS_MODULE,
+        .open           = pvc_line_proc_open,
+        .read           = seq_read,
+        .llseek         = seq_lseek,
+        .release        = single_release,
+        .write          = pvc_line_proc_write,
+};
+
+static ssize_t pvc_scroll_proc_write(struct file *file, const char __user *buf,
+                                     size_t count, loff_t *pos)
 {
-        int origcount = count;
-        int cmd = simple_strtol(buffer, NULL, 10);
+        char kbuf[42];
+        size_t len;
+        int cmd;
+
+        len = min(count, sizeof(kbuf) - 1);
+        if (copy_from_user(kbuf, buf, len))
+                return -EFAULT;
+        kbuf[len] = '\0';
+
+        cmd = simple_strtol(kbuf, NULL, 10);
 
         mutex_lock(&pvc_mutex);
         if (scroll_interval != 0)
@@ -110,22 +130,31 @@ static int pvc_proc_write_scroll(struct file *file, const char *buffer,
         }
         mutex_unlock(&pvc_mutex);
 
-        return origcount;
+        return count;
 }
 
-static int pvc_proc_read_scroll(char *page, char **start,
-                             off_t off, int count,
-                             int *eof, void *data)
+static int pvc_scroll_proc_show(struct seq_file *m, void *v)
 {
-        char *origpage = page;
-
         mutex_lock(&pvc_mutex);
-        page += sprintf(page, "%d\n", scroll_dir * scroll_interval);
+        seq_printf(m, "%d\n", scroll_dir * scroll_interval);
         mutex_unlock(&pvc_mutex);
 
-        return page - origpage;
+        return 0;
 }
 
+static int pvc_scroll_proc_open(struct inode *inode, struct file *file)
+{
+        return single_open(file, pvc_scroll_proc_show, NULL);
+}
+
+static const struct file_operations pvc_scroll_proc_fops = {
+        .owner          = THIS_MODULE,
+        .open           = pvc_scroll_proc_open,
+        .read           = seq_read,
+        .llseek         = seq_lseek,
+        .release        = single_release,
+        .write          = pvc_scroll_proc_write,
+};
 
 void pvc_proc_timerfunc(unsigned long data)
 {
@@ -163,22 +192,16 @@ static int __init pvc_proc_init(void)
                 pvc_linedata[i] = i;
         }
         for (i = 0; i < PVC_NLINES; i++) {
-                proc_entry = create_proc_entry(pvc_linename[i], 0644,
-                                               pvc_display_dir);
+                proc_entry = proc_create_data(pvc_linename[i], 0644, pvc_display_dir,
+                                        &pvc_line_proc_fops, &pvc_linedata[i]);
                 if (proc_entry == NULL)
                         goto error;
-
-                proc_entry->read_proc = pvc_proc_read_line;
-                proc_entry->write_proc = pvc_proc_write_line;
-                proc_entry->data = &pvc_linedata[i];
         }
-        proc_entry = create_proc_entry("scroll", 0644, pvc_display_dir);
+        proc_entry = proc_create("scroll", 0644, pvc_display_dir,
+                                 &pvc_scroll_proc_fops);
         if (proc_entry == NULL)
                 goto error;
 
-        proc_entry->write_proc = pvc_proc_write_scroll;
-        proc_entry->read_proc = pvc_proc_read_scroll;
-
         init_timer(&timer);
         timer.function = pvc_proc_timerfunc;
 
diff --git a/arch/mips/lasat/prom.c b/arch/mips/lasat/prom.c
index 6acc6cb85f0a..20fde19a5fbf 100644
--- a/arch/mips/lasat/prom.c
+++ b/arch/mips/lasat/prom.c
@@ -100,8 +100,8 @@ void __init prom_init(void)
 
         /* Get the command line */
         if (argc > 0) {
-                strncpy(arcs_cmdline, argv[0], CL_SIZE-1);
-                arcs_cmdline[CL_SIZE-1] = '\0';
+                strncpy(arcs_cmdline, argv[0], COMMAND_LINE_SIZE-1);
+                arcs_cmdline[COMMAND_LINE_SIZE-1] = '\0';
         }
 
         /* Set the I/O base address */
diff --git a/arch/mips/lasat/sysctl.c b/arch/mips/lasat/sysctl.c
index 14b9a28a4aec..d87ffd04cb0a 100644
--- a/arch/mips/lasat/sysctl.c
+++ b/arch/mips/lasat/sysctl.c
@@ -204,7 +204,7 @@ static ctl_table lasat_table[] = {
                 .maxlen         = sizeof(int),
                 .mode           = 0644,
                 .proc_handler   = proc_lasat_prid,
-.       },
+        },
 #ifdef CONFIG_INET
         {
                 .procname       = "ipaddr",
diff --git a/arch/mips/loongson/Kconfig b/arch/mips/loongson/Kconfig
index d45092505fa1..3df1967dea08 100644
--- a/arch/mips/loongson/Kconfig
+++ b/arch/mips/loongson/Kconfig
@@ -1,31 +1,85 @@
 choice
-    prompt "Machine Type"
-    depends on MACH_LOONGSON
+        prompt "Machine Type"
+        depends on MACH_LOONGSON
 
 config LEMOTE_FULOONG2E
-    bool "Lemote Fuloong(2e) mini-PC"
-    select ARCH_SPARSEMEM_ENABLE
-    select CEVT_R4K
-    select CSRC_R4K
-    select SYS_HAS_CPU_LOONGSON2E
-    select DMA_NONCOHERENT
-    select BOOT_ELF32
-    select BOARD_SCACHE
-    select HW_HAS_PCI
-    select I8259
-    select ISA
-    select IRQ_CPU
-    select SYS_SUPPORTS_32BIT_KERNEL
-    select SYS_SUPPORTS_64BIT_KERNEL
-    select SYS_SUPPORTS_LITTLE_ENDIAN
-    select SYS_SUPPORTS_HIGHMEM
-    select SYS_HAS_EARLY_PRINTK
-    select GENERIC_HARDIRQS_NO__DO_IRQ
-    select GENERIC_ISA_DMA_SUPPORT_BROKEN
-    select CPU_HAS_WB
-    help
-      Lemote Fuloong(2e) mini-PC board based on the Chinese Loongson-2E CPU and
-      an FPGA northbridge
-
-      Lemote Fuloong(2e) mini PC have a VIA686B south bridge.
+        bool "Lemote Fuloong(2e) mini-PC"
+        select ARCH_SPARSEMEM_ENABLE
+        select CEVT_R4K
+        select CSRC_R4K
+        select SYS_HAS_CPU_LOONGSON2E
+        select DMA_NONCOHERENT
+        select BOOT_ELF32
+        select BOARD_SCACHE
+        select HW_HAS_PCI
+        select I8259
+        select ISA
+        select IRQ_CPU
+        select SYS_SUPPORTS_32BIT_KERNEL
+        select SYS_SUPPORTS_64BIT_KERNEL
+        select SYS_SUPPORTS_LITTLE_ENDIAN
+        select SYS_SUPPORTS_HIGHMEM
+        select SYS_HAS_EARLY_PRINTK
+        select GENERIC_HARDIRQS_NO__DO_IRQ
+        select GENERIC_ISA_DMA_SUPPORT_BROKEN
+        select CPU_HAS_WB
+        help
+          Lemote Fuloong(2e) mini-PC board based on the Chinese Loongson-2E CPU and
+          an FPGA northbridge
+
+          Lemote Fuloong(2e) mini PC have a VIA686B south bridge.
+
+config LEMOTE_MACH2F
+        bool "Lemote Loongson 2F family machines"
+        select ARCH_SPARSEMEM_ENABLE
+        select BOARD_SCACHE
+        select BOOT_ELF32
+        select CEVT_R4K if ! MIPS_EXTERNAL_TIMER
+        select CPU_HAS_WB
+        select CS5536
+        select CSRC_R4K if ! MIPS_EXTERNAL_TIMER
+        select DMA_NONCOHERENT
+        select GENERIC_HARDIRQS_NO__DO_IRQ
+        select GENERIC_ISA_DMA_SUPPORT_BROKEN
+        select HW_HAS_PCI
+        select I8259
+        select IRQ_CPU
+        select ISA
+        select SYS_HAS_CPU_LOONGSON2F
+        select SYS_HAS_EARLY_PRINTK
+        select SYS_SUPPORTS_32BIT_KERNEL
+        select SYS_SUPPORTS_64BIT_KERNEL
+        select SYS_SUPPORTS_HIGHMEM
+        select SYS_SUPPORTS_LITTLE_ENDIAN
+        help
+          Lemote Loongson 2F family machines utilize the 2F revision of
+          Loongson processor and the AMD CS5536 south bridge.
+
+          These family machines include fuloong2f mini PC, yeeloong2f notebook,
+          LingLoong allinone PC and so forth.
 endchoice
+
+config CS5536
+        bool
+
+config CS5536_MFGPT
+        bool "CS5536 MFGPT Timer"
+        depends on CS5536
+        select MIPS_EXTERNAL_TIMER
+        help
+          This option enables the mfgpt0 timer of AMD CS5536.
+
+          If you want to enable the Loongson2 CPUFreq Driver, Please enable
+          this option at first, otherwise, You will get wrong system time.
+
+          If unsure, say Yes.
+
+config LOONGSON_SUSPEND
+        bool
+        default y
+        depends on CPU_SUPPORTS_CPUFREQ && SUSPEND
+
+config LOONGSON_UART_BASE
+        bool
+        default y
+        depends on EARLY_PRINTK || SERIAL_8250
diff --git a/arch/mips/loongson/Makefile b/arch/mips/loongson/Makefile
index 39048c455d7d..2b76cb0fb07d 100644
--- a/arch/mips/loongson/Makefile
+++ b/arch/mips/loongson/Makefile
@@ -9,3 +9,9 @@ obj-$(CONFIG_MACH_LOONGSON) += common/
 #
 
 obj-$(CONFIG_LEMOTE_FULOONG2E)  += fuloong-2e/
+
+#
+# Lemote loongson2f family machines
+#
+
+obj-$(CONFIG_LEMOTE_MACH2F)  += lemote-2f/
diff --git a/arch/mips/loongson/common/Makefile b/arch/mips/loongson/common/Makefile
index 656b3cc0a2a6..7668c4de1151 100644
--- a/arch/mips/loongson/common/Makefile
+++ b/arch/mips/loongson/common/Makefile
@@ -3,9 +3,23 @@
 #
 
 obj-y += setup.o init.o cmdline.o env.o time.o reset.o irq.o \
-    pci.o bonito-irq.o mem.o machtype.o
+    pci.o bonito-irq.o mem.o machtype.o platform.o
 
 #
-# Early printk support
+# Serial port support
 #
 obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
+obj-$(CONFIG_SERIAL_8250) += serial.o
+obj-$(CONFIG_LOONGSON_UART_BASE) += uart_base.o
+
+#
+# Enable CS5536 Virtual Support Module(VSM) to virtulize the PCI configure
+# space
+#
+obj-$(CONFIG_CS5536) += cs5536/
+
+#
+# Suspend Support
+#
+
+obj-$(CONFIG_LOONGSON_SUSPEND) += pm.o
diff --git a/arch/mips/loongson/common/bonito-irq.c b/arch/mips/loongson/common/bonito-irq.c
index 3e31e7ad713e..2dc2a4cc632a 100644
--- a/arch/mips/loongson/common/bonito-irq.c
+++ b/arch/mips/loongson/common/bonito-irq.c
@@ -12,18 +12,19 @@
  *  option) any later version.
  */
 #include <linux/interrupt.h>
+#include <linux/compiler.h>
 
 #include <loongson.h>
 
 static inline void bonito_irq_enable(unsigned int irq)
 {
-        BONITO_INTENSET = (1 << (irq - BONITO_IRQ_BASE));
+        LOONGSON_INTENSET = (1 << (irq - LOONGSON_IRQ_BASE));
         mmiowb();
 }
 
 static inline void bonito_irq_disable(unsigned int irq)
 {
-        BONITO_INTENCLR = (1 << (irq - BONITO_IRQ_BASE));
+        LOONGSON_INTENCLR = (1 << (irq - LOONGSON_IRQ_BASE));
         mmiowb();
 }
 
@@ -35,7 +36,7 @@ static struct irq_chip bonito_irq_type = {
         .unmask = bonito_irq_enable,
 };
 
-static struct irqaction dma_timeout_irqaction = {
+static struct irqaction __maybe_unused dma_timeout_irqaction = {
         .handler        = no_action,
         .name           = "dma_timeout",
 };
@@ -44,8 +45,10 @@ void bonito_irq_init(void)
 {
         u32 i;
 
-        for (i = BONITO_IRQ_BASE; i < BONITO_IRQ_BASE + 32; i++)
+        for (i = LOONGSON_IRQ_BASE; i < LOONGSON_IRQ_BASE + 32; i++)
                 set_irq_chip_and_handler(i, &bonito_irq_type, handle_level_irq);
 
-        setup_irq(BONITO_IRQ_BASE + 10, &dma_timeout_irqaction);
+#ifdef CONFIG_CPU_LOONGSON2E
+        setup_irq(LOONGSON_IRQ_BASE + 10, &dma_timeout_irqaction);
+#endif
 }
diff --git a/arch/mips/loongson/common/cmdline.c b/arch/mips/loongson/common/cmdline.c
index 75f1b243ee4e..7ad47f227477 100644
--- a/arch/mips/loongson/common/cmdline.c
+++ b/arch/mips/loongson/common/cmdline.c
@@ -9,7 +9,7 @@
  * Copyright (C) 2007 Lemote Inc. & Insititute of Computing Technology
  * Author: Fuxin Zhang, zhangfx@lemote.com
  *
- * Copyright (C) 2009 Lemote Inc. & Insititute of Computing Technology
+ * Copyright (C) 2009 Lemote Inc.
  * Author: Wu Zhangjin, wuzj@lemote.com
  *
  * This program is free software; you can redistribute  it and/or modify it
@@ -49,4 +49,6 @@ void __init prom_init_cmdline(void)
                 strcat(arcs_cmdline, " console=ttyS0,115200");
         if ((strstr(arcs_cmdline, "root=")) == NULL)
                 strcat(arcs_cmdline, " root=/dev/hda1");
+
+        prom_init_machtype();
 }
diff --git a/arch/mips/loongson/common/cs5536/Makefile b/arch/mips/loongson/common/cs5536/Makefile
new file mode 100644
index 000000000000..510d4cdc2378
--- /dev/null
+++ b/arch/mips/loongson/common/cs5536/Makefile
@@ -0,0 +1,13 @@
+#
+# Makefile for CS5536 support.
+#
+
+obj-$(CONFIG_CS5536) += cs5536_pci.o cs5536_ide.o cs5536_acc.o cs5536_ohci.o \
+                        cs5536_isa.o cs5536_ehci.o
+
+#
+# Enable cs5536 mfgpt Timer
+#
+obj-$(CONFIG_CS5536_MFGPT) += cs5536_mfgpt.o
+
+EXTRA_CFLAGS += -Werror
diff --git a/arch/mips/loongson/common/cs5536/cs5536_acc.c b/arch/mips/loongson/common/cs5536/cs5536_acc.c
new file mode 100644
index 000000000000..b49485f187e0
--- /dev/null
+++ b/arch/mips/loongson/common/cs5536/cs5536_acc.c
@@ -0,0 +1,140 @@
+/*
+ * the ACC Virtual Support Module of AMD CS5536
+ *
+ * Copyright (C) 2007 Lemote, Inc.
+ * Author : jlliu, liujl@lemote.com
+ *
+ * Copyright (C) 2009 Lemote, Inc.
+ * Author: Wu Zhangjin, wuzj@lemote.com
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#include <cs5536/cs5536.h>
+#include <cs5536/cs5536_pci.h>
+
+void pci_acc_write_reg(int reg, u32 value)
+{
+        u32 hi = 0, lo = value;
+
+        switch (reg) {
+        case PCI_COMMAND:
+                _rdmsr(GLIU_MSR_REG(GLIU_PAE), &hi, &lo);
+                if (value & PCI_COMMAND_MASTER)
+                        lo |= (0x03 << 8);
+                else
+                        lo &= ~(0x03 << 8);
+                _wrmsr(GLIU_MSR_REG(GLIU_PAE), hi, lo);
+                break;
+        case PCI_STATUS:
+                if (value & PCI_STATUS_PARITY) {
+                        _rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo);
+                        if (lo & SB_PARE_ERR_FLAG) {
+                                lo = (lo & 0x0000ffff) | SB_PARE_ERR_FLAG;
+                                _wrmsr(SB_MSR_REG(SB_ERROR), hi, lo);
+                        }
+                }
+                break;
+        case PCI_BAR0_REG:
+                if (value == PCI_BAR_RANGE_MASK) {
+                        _rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo);
+                        lo |= SOFT_BAR_ACC_FLAG;
+                        _wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo);
+                } else if (value & 0x01) {
+                        value &= 0xfffffffc;
+                        hi = 0xA0000000 | ((value & 0x000ff000) >> 12);
+                        lo = 0x000fff80 | ((value & 0x00000fff) << 20);
+                        _wrmsr(GLIU_MSR_REG(GLIU_IOD_BM1), hi, lo);
+                }
+                break;
+        case PCI_ACC_INT_REG:
+                _rdmsr(DIVIL_MSR_REG(PIC_YSEL_LOW), &hi, &lo);
+                /* disable all the usb interrupt in PIC */
+                lo &= ~(0xf << PIC_YSEL_LOW_ACC_SHIFT);
+                if (value)      /* enable all the acc interrupt in PIC */
+                        lo |= (CS5536_ACC_INTR << PIC_YSEL_LOW_ACC_SHIFT);
+                _wrmsr(DIVIL_MSR_REG(PIC_YSEL_LOW), hi, lo);
+                break;
+        default:
+                break;
+        }
+}
+
+u32 pci_acc_read_reg(int reg)
+{
+        u32 hi, lo;
+        u32 conf_data = 0;
+
+        switch (reg) {
+        case PCI_VENDOR_ID:
+                conf_data =
+                    CFG_PCI_VENDOR_ID(CS5536_ACC_DEVICE_ID, CS5536_VENDOR_ID);
+                break;
+        case PCI_COMMAND:
+                _rdmsr(GLIU_MSR_REG(GLIU_IOD_BM1), &hi, &lo);
+                if (((lo & 0xfff00000) || (hi & 0x000000ff))
+                    && ((hi & 0xf0000000) == 0xa0000000))
+                        conf_data |= PCI_COMMAND_IO;
+                _rdmsr(GLIU_MSR_REG(GLIU_PAE), &hi, &lo);
+                if ((lo & 0x300) == 0x300)
+                        conf_data |= PCI_COMMAND_MASTER;
+                break;
+        case PCI_STATUS:
+                conf_data |= PCI_STATUS_66MHZ;
+                conf_data |= PCI_STATUS_FAST_BACK;
+                _rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo);
+                if (lo & SB_PARE_ERR_FLAG)
+                        conf_data |= PCI_STATUS_PARITY;
+                conf_data |= PCI_STATUS_DEVSEL_MEDIUM;
+                break;
+        case PCI_CLASS_REVISION:
+                _rdmsr(ACC_MSR_REG(ACC_CAP), &hi, &lo);
+                conf_data = lo & 0x000000ff;
+                conf_data |= (CS5536_ACC_CLASS_CODE << 8);
+                break;
+        case PCI_CACHE_LINE_SIZE:
+                conf_data =
+                    CFG_PCI_CACHE_LINE_SIZE(PCI_NORMAL_HEADER_TYPE,
+                                            PCI_NORMAL_LATENCY_TIMER);
+                break;
+        case PCI_BAR0_REG:
+                _rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo);
+                if (lo & SOFT_BAR_ACC_FLAG) {
+                        conf_data = CS5536_ACC_RANGE |
+                            PCI_BASE_ADDRESS_SPACE_IO;
+                        lo &= ~SOFT_BAR_ACC_FLAG;
+                        _wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo);
+                } else {
+                        _rdmsr(GLIU_MSR_REG(GLIU_IOD_BM1), &hi, &lo);
+                        conf_data = (hi & 0x000000ff) << 12;
+                        conf_data |= (lo & 0xfff00000) >> 20;
+                        conf_data |= 0x01;
+                        conf_data &= ~0x02;
+                }
+                break;
+        case PCI_CARDBUS_CIS:
+                conf_data = PCI_CARDBUS_CIS_POINTER;
+                break;
+        case PCI_SUBSYSTEM_VENDOR_ID:
+                conf_data =
+                    CFG_PCI_VENDOR_ID(CS5536_ACC_SUB_ID, CS5536_SUB_VENDOR_ID);
+                break;
+        case PCI_ROM_ADDRESS:
+                conf_data = PCI_EXPANSION_ROM_BAR;
+                break;
+        case PCI_CAPABILITY_LIST:
+                conf_data = PCI_CAPLIST_USB_POINTER;
+                break;
+        case PCI_INTERRUPT_LINE:
+                conf_data =
+                    CFG_PCI_INTERRUPT_LINE(PCI_DEFAULT_PIN, CS5536_ACC_INTR);
+                break;
+        default:
+                break;
+        }
+
+        return conf_data;
+}
diff --git a/arch/mips/loongson/common/cs5536/cs5536_ehci.c b/arch/mips/loongson/common/cs5536/cs5536_ehci.c
new file mode 100644
index 000000000000..74f9c59d36af
--- /dev/null
+++ b/arch/mips/loongson/common/cs5536/cs5536_ehci.c
@@ -0,0 +1,158 @@
+/*
+ * the EHCI Virtual Support Module of AMD CS5536
+ *
+ * Copyright (C) 2007 Lemote, Inc.
+ * Author : jlliu, liujl@lemote.com
+ *
+ * Copyright (C) 2009 Lemote, Inc.
+ * Author: Wu Zhangjin, wuzj@lemote.com
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#include <cs5536/cs5536.h>
+#include <cs5536/cs5536_pci.h>
+
+void pci_ehci_write_reg(int reg, u32 value)
+{
+        u32 hi = 0, lo = value;
+
+        switch (reg) {
+        case PCI_COMMAND:
+                _rdmsr(USB_MSR_REG(USB_EHCI), &hi, &lo);
+                if (value & PCI_COMMAND_MASTER)
+                        hi |= PCI_COMMAND_MASTER;
+                else
+                        hi &= ~PCI_COMMAND_MASTER;
+
+                if (value & PCI_COMMAND_MEMORY)
+                        hi |= PCI_COMMAND_MEMORY;
+                else
+                        hi &= ~PCI_COMMAND_MEMORY;
+                _wrmsr(USB_MSR_REG(USB_EHCI), hi, lo);
+                break;
+        case PCI_STATUS:
+                if (value & PCI_STATUS_PARITY) {
+                        _rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo);
+                        if (lo & SB_PARE_ERR_FLAG) {
+                                lo = (lo & 0x0000ffff) | SB_PARE_ERR_FLAG;
+                                _wrmsr(SB_MSR_REG(SB_ERROR), hi, lo);
+                        }
+                }
+                break;
+        case PCI_BAR0_REG:
+                if (value == PCI_BAR_RANGE_MASK) {
+                        _rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo);
+                        lo |= SOFT_BAR_EHCI_FLAG;
+                        _wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo);
+                } else if ((value & 0x01) == 0x00) {
+                        _wrmsr(USB_MSR_REG(USB_EHCI), hi, lo);
+
+                        value &= 0xfffffff0;
+                        hi = 0x40000000 | ((value & 0xff000000) >> 24);
+                        lo = 0x000fffff | ((value & 0x00fff000) << 8);
+                        _wrmsr(GLIU_MSR_REG(GLIU_P2D_BM4), hi, lo);
+                }
+                break;
+        case PCI_EHCI_LEGSMIEN_REG:
+                _rdmsr(USB_MSR_REG(USB_EHCI), &hi, &lo);
+                hi &= 0x003f0000;
+                hi |= (value & 0x3f) << 16;
+                _wrmsr(USB_MSR_REG(USB_EHCI), hi, lo);
+                break;
+        case PCI_EHCI_FLADJ_REG:
+                _rdmsr(USB_MSR_REG(USB_EHCI), &hi, &lo);
+                hi &= ~0x00003f00;
+                hi |= value & 0x00003f00;
+                _wrmsr(USB_MSR_REG(USB_EHCI), hi, lo);
+                break;
+        default:
+                break;
+        }
+}
+
+u32 pci_ehci_read_reg(int reg)
+{
+        u32 conf_data = 0;
+        u32 hi, lo;
+
+        switch (reg) {
+        case PCI_VENDOR_ID:
+                conf_data =
+                    CFG_PCI_VENDOR_ID(CS5536_EHCI_DEVICE_ID, CS5536_VENDOR_ID);
+                break;
+        case PCI_COMMAND:
+                _rdmsr(USB_MSR_REG(USB_EHCI), &hi, &lo);
+                if (hi & PCI_COMMAND_MASTER)
+                        conf_data |= PCI_COMMAND_MASTER;
+                if (hi & PCI_COMMAND_MEMORY)
+                        conf_data |= PCI_COMMAND_MEMORY;
+                break;
+        case PCI_STATUS:
+                conf_data |= PCI_STATUS_66MHZ;
+                conf_data |= PCI_STATUS_FAST_BACK;
+                _rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo);
+                if (lo & SB_PARE_ERR_FLAG)
+                        conf_data |= PCI_STATUS_PARITY;
+                conf_data |= PCI_STATUS_DEVSEL_MEDIUM;
+                break;
+        case PCI_CLASS_REVISION:
+                _rdmsr(USB_MSR_REG(USB_CAP), &hi, &lo);
+                conf_data = lo & 0x000000ff;
+                conf_data |= (CS5536_EHCI_CLASS_CODE << 8);
+                break;
+        case PCI_CACHE_LINE_SIZE:
+                conf_data =
+                    CFG_PCI_CACHE_LINE_SIZE(PCI_NORMAL_HEADER_TYPE,
+                                            PCI_NORMAL_LATENCY_TIMER);
+                break;
+        case PCI_BAR0_REG:
+                _rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo);
+                if (lo & SOFT_BAR_EHCI_FLAG) {
+                        conf_data = CS5536_EHCI_RANGE |
+                            PCI_BASE_ADDRESS_SPACE_MEMORY;
+                        lo &= ~SOFT_BAR_EHCI_FLAG;
+                        _wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo);
+                } else {
+                        _rdmsr(USB_MSR_REG(USB_EHCI), &hi, &lo);
+                        conf_data = lo & 0xfffff000;
+                }
+                break;
+        case PCI_CARDBUS_CIS:
+                conf_data = PCI_CARDBUS_CIS_POINTER;
+                break;
+        case PCI_SUBSYSTEM_VENDOR_ID:
+                conf_data =
+                    CFG_PCI_VENDOR_ID(CS5536_EHCI_SUB_ID, CS5536_SUB_VENDOR_ID);
+                break;
+        case PCI_ROM_ADDRESS:
+                conf_data = PCI_EXPANSION_ROM_BAR;
+                break;
+        case PCI_CAPABILITY_LIST:
+                conf_data = PCI_CAPLIST_USB_POINTER;
+                break;
+        case PCI_INTERRUPT_LINE:
+                conf_data =
+                    CFG_PCI_INTERRUPT_LINE(PCI_DEFAULT_PIN, CS5536_USB_INTR);
+                break;
+        case PCI_EHCI_LEGSMIEN_REG:
+                _rdmsr(USB_MSR_REG(USB_EHCI), &hi, &lo);
+                conf_data = (hi & 0x003f0000) >> 16;
+                break;
+        case PCI_EHCI_LEGSMISTS_REG:
+                _rdmsr(USB_MSR_REG(USB_EHCI), &hi, &lo);
+                conf_data = (hi & 0x3f000000) >> 24;
+                break;
+        case PCI_EHCI_FLADJ_REG:
+                _rdmsr(USB_MSR_REG(USB_EHCI), &hi, &lo);
+                conf_data = hi & 0x00003f00;
+                break;
+        default:
+                break;
+        }
+
+        return conf_data;
+}
diff --git a/arch/mips/loongson/common/cs5536/cs5536_ide.c b/arch/mips/loongson/common/cs5536/cs5536_ide.c
new file mode 100644
index 000000000000..3f61594b3884
--- /dev/null
+++ b/arch/mips/loongson/common/cs5536/cs5536_ide.c
@@ -0,0 +1,179 @@
+/*
+ * the IDE Virtual Support Module of AMD CS5536
+ *
+ * Copyright (C) 2007 Lemote, Inc.
+ * Author : jlliu, liujl@lemote.com
+ *
+ * Copyright (C) 2009 Lemote, Inc.
+ * Author: Wu Zhangjin, wuzj@lemote.com
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#include <cs5536/cs5536.h>
+#include <cs5536/cs5536_pci.h>
+
+void pci_ide_write_reg(int reg, u32 value)
+{
+        u32 hi = 0, lo = value;
+
+        switch (reg) {
+        case PCI_COMMAND:
+                _rdmsr(GLIU_MSR_REG(GLIU_PAE), &hi, &lo);
+                if (value & PCI_COMMAND_MASTER)
+                        lo |= (0x03 << 4);
+                else
+                        lo &= ~(0x03 << 4);
+                _wrmsr(GLIU_MSR_REG(GLIU_PAE), hi, lo);
+                break;
+        case PCI_STATUS:
+                if (value & PCI_STATUS_PARITY) {
+                        _rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo);
+                        if (lo & SB_PARE_ERR_FLAG) {
+                                lo = (lo & 0x0000ffff) | SB_PARE_ERR_FLAG;
+                                _wrmsr(SB_MSR_REG(SB_ERROR), hi, lo);
+                        }
+                }
+                break;
+        case PCI_CACHE_LINE_SIZE:
+                value &= 0x0000ff00;
+                _rdmsr(SB_MSR_REG(SB_CTRL), &hi, &lo);
+                hi &= 0xffffff00;
+                hi |= (value >> 8);
+                _wrmsr(SB_MSR_REG(SB_CTRL), hi, lo);
+                break;
+        case PCI_BAR4_REG:
+                if (value == PCI_BAR_RANGE_MASK) {
+                        _rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo);
+                        lo |= SOFT_BAR_IDE_FLAG;
+                        _wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo);
+                } else if (value & 0x01) {
+                        lo = (value & 0xfffffff0) | 0x1;
+                        _wrmsr(IDE_MSR_REG(IDE_IO_BAR), hi, lo);
+
+                        value &= 0xfffffffc;
+                        hi = 0x60000000 | ((value & 0x000ff000) >> 12);
+                        lo = 0x000ffff0 | ((value & 0x00000fff) << 20);
+                        _wrmsr(GLIU_MSR_REG(GLIU_IOD_BM2), hi, lo);
+                }
+                break;
+        case PCI_IDE_CFG_REG:
+                if (value == CS5536_IDE_FLASH_SIGNATURE) {
+                        _rdmsr(DIVIL_MSR_REG(DIVIL_BALL_OPTS), &hi, &lo);
+                        lo |= 0x01;
+                        _wrmsr(DIVIL_MSR_REG(DIVIL_BALL_OPTS), hi, lo);
+                } else
+                        _wrmsr(IDE_MSR_REG(IDE_CFG), hi, lo);
+                break;
+        case PCI_IDE_DTC_REG:
+                _wrmsr(IDE_MSR_REG(IDE_DTC), hi, lo);
+                break;
+        case PCI_IDE_CAST_REG:
+                _wrmsr(IDE_MSR_REG(IDE_CAST), hi, lo);
+                break;
+        case PCI_IDE_ETC_REG:
+                _wrmsr(IDE_MSR_REG(IDE_ETC), hi, lo);
+                break;
+        case PCI_IDE_PM_REG:
+                _wrmsr(IDE_MSR_REG(IDE_INTERNAL_PM), hi, lo);
+                break;
+        default:
+                break;
+        }
+}
+
+u32 pci_ide_read_reg(int reg)
+{
+        u32 conf_data = 0;
+        u32 hi, lo;
+
+        switch (reg) {
+        case PCI_VENDOR_ID:
+                conf_data =
+                    CFG_PCI_VENDOR_ID(CS5536_IDE_DEVICE_ID, CS5536_VENDOR_ID);
+                break;
+        case PCI_COMMAND:
+                _rdmsr(IDE_MSR_REG(IDE_IO_BAR), &hi, &lo);
+                if (lo & 0xfffffff0)
+                        conf_data |= PCI_COMMAND_IO;
+                _rdmsr(GLIU_MSR_REG(GLIU_PAE), &hi, &lo);
+                if ((lo & 0x30) == 0x30)
+                        conf_data |= PCI_COMMAND_MASTER;
+                break;
+        case PCI_STATUS:
+                conf_data |= PCI_STATUS_66MHZ;
+                conf_data |= PCI_STATUS_FAST_BACK;
+                _rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo);
+                if (lo & SB_PARE_ERR_FLAG)
+                        conf_data |= PCI_STATUS_PARITY;
+                conf_data |= PCI_STATUS_DEVSEL_MEDIUM;
+                break;
+        case PCI_CLASS_REVISION:
+                _rdmsr(IDE_MSR_REG(IDE_CAP), &hi, &lo);
+                conf_data = lo & 0x000000ff;
+                conf_data |= (CS5536_IDE_CLASS_CODE << 8);
+                break;
+        case PCI_CACHE_LINE_SIZE:
+                _rdmsr(SB_MSR_REG(SB_CTRL), &hi, &lo);
+                hi &= 0x000000f8;
+                conf_data = CFG_PCI_CACHE_LINE_SIZE(PCI_NORMAL_HEADER_TYPE, hi);
+                break;
+        case PCI_BAR4_REG:
+                _rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo);
+                if (lo & SOFT_BAR_IDE_FLAG) {
+                        conf_data = CS5536_IDE_RANGE |
+                            PCI_BASE_ADDRESS_SPACE_IO;
+                        lo &= ~SOFT_BAR_IDE_FLAG;
+                        _wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo);
+                } else {
+                        _rdmsr(IDE_MSR_REG(IDE_IO_BAR), &hi, &lo);
+                        conf_data = lo & 0xfffffff0;
+                        conf_data |= 0x01;
+                        conf_data &= ~0x02;
+                }
+                break;
+        case PCI_CARDBUS_CIS:
+                conf_data = PCI_CARDBUS_CIS_POINTER;
+                break;
+        case PCI_SUBSYSTEM_VENDOR_ID:
+                conf_data =
+                    CFG_PCI_VENDOR_ID(CS5536_IDE_SUB_ID, CS5536_SUB_VENDOR_ID);
+                break;
+        case PCI_ROM_ADDRESS:
+                conf_data = PCI_EXPANSION_ROM_BAR;
+                break;
+        case PCI_CAPABILITY_LIST:
+                conf_data = PCI_CAPLIST_POINTER;
+                break;
+        case PCI_INTERRUPT_LINE:
+                conf_data =
+                    CFG_PCI_INTERRUPT_LINE(PCI_DEFAULT_PIN, CS5536_IDE_INTR);
+                break;
+        case PCI_IDE_CFG_REG:
+                _rdmsr(IDE_MSR_REG(IDE_CFG), &hi, &lo);
+                conf_data = lo;
+                break;
+        case PCI_IDE_DTC_REG:
+                _rdmsr(IDE_MSR_REG(IDE_DTC), &hi, &lo);
+                conf_data = lo;
+                break;
+        case PCI_IDE_CAST_REG:
+                _rdmsr(IDE_MSR_REG(IDE_CAST), &hi, &lo);
+                conf_data = lo;
+                break;
+        case PCI_IDE_ETC_REG:
+                _rdmsr(IDE_MSR_REG(IDE_ETC), &hi, &lo);
+                conf_data = lo;
+        case PCI_IDE_PM_REG:
+                _rdmsr(IDE_MSR_REG(IDE_INTERNAL_PM), &hi, &lo);
+                conf_data = lo;
+                break;
+        default:
+                break;
+        }
+
+        return conf_data;
+}
diff --git a/arch/mips/loongson/common/cs5536/cs5536_isa.c b/arch/mips/loongson/common/cs5536/cs5536_isa.c
new file mode 100644
index 000000000000..b6f17f538e48
--- /dev/null
+++ b/arch/mips/loongson/common/cs5536/cs5536_isa.c
@@ -0,0 +1,316 @@
+/*
+ * the ISA Virtual Support Module of AMD CS5536
+ *
+ * Copyright (C) 2007 Lemote, Inc.
+ * Author : jlliu, liujl@lemote.com
+ *
+ * Copyright (C) 2009 Lemote, Inc.
+ * Author: Wu Zhangjin, wuzj@lemote.com
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#include <cs5536/cs5536.h>
+#include <cs5536/cs5536_pci.h>
+
+/* common variables for PCI_ISA_READ/WRITE_BAR */
+static const u32 divil_msr_reg[6] = {
+        DIVIL_MSR_REG(DIVIL_LBAR_SMB), DIVIL_MSR_REG(DIVIL_LBAR_GPIO),
+        DIVIL_MSR_REG(DIVIL_LBAR_MFGPT), DIVIL_MSR_REG(DIVIL_LBAR_IRQ),
+        DIVIL_MSR_REG(DIVIL_LBAR_PMS), DIVIL_MSR_REG(DIVIL_LBAR_ACPI),
+};
+
+static const u32 soft_bar_flag[6] = {
+        SOFT_BAR_SMB_FLAG, SOFT_BAR_GPIO_FLAG, SOFT_BAR_MFGPT_FLAG,
+        SOFT_BAR_IRQ_FLAG, SOFT_BAR_PMS_FLAG, SOFT_BAR_ACPI_FLAG,
+};
+
+static const u32 sb_msr_reg[6] = {
+        SB_MSR_REG(SB_R0), SB_MSR_REG(SB_R1), SB_MSR_REG(SB_R2),
+        SB_MSR_REG(SB_R3), SB_MSR_REG(SB_R4), SB_MSR_REG(SB_R5),
+};
+
+static const u32 bar_space_range[6] = {
+        CS5536_SMB_RANGE, CS5536_GPIO_RANGE, CS5536_MFGPT_RANGE,
+        CS5536_IRQ_RANGE, CS5536_PMS_RANGE, CS5536_ACPI_RANGE,
+};
+
+static const int bar_space_len[6] = {
+        CS5536_SMB_LENGTH, CS5536_GPIO_LENGTH, CS5536_MFGPT_LENGTH,
+        CS5536_IRQ_LENGTH, CS5536_PMS_LENGTH, CS5536_ACPI_LENGTH,
+};
+
+/*
+ * enable the divil module bar space.
+ *
+ * For all the DIVIL module LBAR, you should control the DIVIL LBAR reg
+ * and the RCONFx(0~5) reg to use the modules.
+ */
+static void divil_lbar_enable(void)
+{
+        u32 hi, lo;
+        int offset;
+
+        /*
+         * The DIVIL IRQ is not used yet. and make the RCONF0 reserved.
+         */
+
+        for (offset = DIVIL_LBAR_SMB; offset <= DIVIL_LBAR_PMS; offset++) {
+                _rdmsr(DIVIL_MSR_REG(offset), &hi, &lo);
+                hi |= 0x01;
+                _wrmsr(DIVIL_MSR_REG(DIVIL_LBAR_SMB), hi, lo);
+        }
+}
+
+/*
+ * disable the divil module bar space.
+ */
+static void divil_lbar_disable(void)
+{
+        u32 hi, lo;
+        int offset;
+
+        for (offset = DIVIL_LBAR_SMB; offset <= DIVIL_LBAR_PMS; offset++) {
+                _rdmsr(DIVIL_MSR_REG(offset), &hi, &lo);
+                hi &= ~0x01;
+                _wrmsr(DIVIL_MSR_REG(DIVIL_LBAR_SMB), hi, lo);
+        }
+}
+
+/*
+ * BAR write: write value to the n BAR
+ */
+
+void pci_isa_write_bar(int n, u32 value)
+{
+        u32 hi = 0, lo = value;
+
+        if (value == PCI_BAR_RANGE_MASK) {
+                _rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo);
+                lo |= soft_bar_flag[n];
+                _wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo);
+        } else if (value & 0x01) {
+                /* NATIVE reg */
+                hi = 0x0000f001;
+                lo &= bar_space_range[n];
+                _wrmsr(divil_msr_reg[n], hi, lo);
+
+                /* RCONFx is 4bytes in units for I/O space */
+                hi = ((value & 0x000ffffc) << 12) |
+                    ((bar_space_len[n] - 4) << 12) | 0x01;
+                lo = ((value & 0x000ffffc) << 12) | 0x01;
+                _wrmsr(sb_msr_reg[n], hi, lo);
+        }
+}
+
+/*
+ * BAR read: read the n BAR
+ */
+
+u32 pci_isa_read_bar(int n)
+{
+        u32 conf_data = 0;
+        u32 hi, lo;
+
+        _rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo);
+        if (lo & soft_bar_flag[n]) {
+                conf_data = bar_space_range[n] | PCI_BASE_ADDRESS_SPACE_IO;
+                lo &= ~soft_bar_flag[n];
+                _wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo);
+        } else {
+                _rdmsr(divil_msr_reg[n], &hi, &lo);
+                conf_data = lo & bar_space_range[n];
+                conf_data |= 0x01;
+                conf_data &= ~0x02;
+        }
+        return conf_data;
+}
+
+/*
+ * isa_write: ISA write transfer
+ *
+ * We assume that this is not a bus master transfer.
+ */
+void pci_isa_write_reg(int reg, u32 value)
+{
+        u32 hi = 0, lo = value;
+        u32 temp;
+
+        switch (reg) {
+        case PCI_COMMAND:
+                if (value & PCI_COMMAND_IO)
+                        divil_lbar_enable();
+                else
+                        divil_lbar_disable();
+                break;
+        case PCI_STATUS:
+                _rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo);
+                temp = lo & 0x0000ffff;
+                if ((value & PCI_STATUS_SIG_TARGET_ABORT) &&
+                    (lo & SB_TAS_ERR_EN))
+                        temp |= SB_TAS_ERR_FLAG;
+
+                if ((value & PCI_STATUS_REC_TARGET_ABORT) &&
+                    (lo & SB_TAR_ERR_EN))
+                        temp |= SB_TAR_ERR_FLAG;
+
+                if ((value & PCI_STATUS_REC_MASTER_ABORT)
+                    && (lo & SB_MAR_ERR_EN))
+                        temp |= SB_MAR_ERR_FLAG;
+
+                if ((value & PCI_STATUS_DETECTED_PARITY)
+                    && (lo & SB_PARE_ERR_EN))
+                        temp |= SB_PARE_ERR_FLAG;
+
+                lo = temp;
+                _wrmsr(SB_MSR_REG(SB_ERROR), hi, lo);
+                break;
+        case PCI_CACHE_LINE_SIZE:
+                value &= 0x0000ff00;
+                _rdmsr(SB_MSR_REG(SB_CTRL), &hi, &lo);
+                hi &= 0xffffff00;
+                hi |= (value >> 8);
+                _wrmsr(SB_MSR_REG(SB_CTRL), hi, lo);
+                break;
+        case PCI_BAR0_REG:
+                pci_isa_write_bar(0, value);
+                break;
+        case PCI_BAR1_REG:
+                pci_isa_write_bar(1, value);
+                break;
+        case PCI_BAR2_REG:
+                pci_isa_write_bar(2, value);
+                break;
+        case PCI_BAR3_REG:
+                pci_isa_write_bar(3, value);
+                break;
+        case PCI_BAR4_REG:
+                pci_isa_write_bar(4, value);
+                break;
+        case PCI_BAR5_REG:
+                pci_isa_write_bar(5, value);
+                break;
+        case PCI_UART1_INT_REG:
+                _rdmsr(DIVIL_MSR_REG(PIC_YSEL_HIGH), &hi, &lo);
+                /* disable uart1 interrupt in PIC */
+                lo &= ~(0xf << 24);
+                if (value)      /* enable uart1 interrupt in PIC */
+                        lo |= (CS5536_UART1_INTR << 24);
+                _wrmsr(DIVIL_MSR_REG(PIC_YSEL_HIGH), hi, lo);
+                break;
+        case PCI_UART2_INT_REG:
+                _rdmsr(DIVIL_MSR_REG(PIC_YSEL_HIGH), &hi, &lo);
+                /* disable uart2 interrupt in PIC */
+                lo &= ~(0xf << 28);
+                if (value)      /* enable uart2 interrupt in PIC */
+                        lo |= (CS5536_UART2_INTR << 28);
+                _wrmsr(DIVIL_MSR_REG(PIC_YSEL_HIGH), hi, lo);
+                break;
+        case PCI_ISA_FIXUP_REG:
+                if (value) {
+                        /* enable the TARGET ABORT/MASTER ABORT etc. */
+                        _rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo);
+                        lo |= 0x00000063;
+                        _wrmsr(SB_MSR_REG(SB_ERROR), hi, lo);
+                }
+
+        default:
+                /* ALL OTHER PCI CONFIG SPACE HEADER IS NOT IMPLEMENTED. */
+                break;
+        }
+}
+
+/*
+ * isa_read: ISA read transfers
+ *
+ * We assume that this is not a bus master transfer.
+ */
+u32 pci_isa_read_reg(int reg)
+{
+        u32 conf_data = 0;
+        u32 hi, lo;
+
+        switch (reg) {
+        case PCI_VENDOR_ID:
+                conf_data =
+                    CFG_PCI_VENDOR_ID(CS5536_ISA_DEVICE_ID, CS5536_VENDOR_ID);
+                break;
+        case PCI_COMMAND:
+                /* we just check the first LBAR for the IO enable bit, */
+                /* maybe we should changed later. */
+                _rdmsr(DIVIL_MSR_REG(DIVIL_LBAR_SMB), &hi, &lo);
+                if (hi & 0x01)
+                        conf_data |= PCI_COMMAND_IO;
+                break;
+        case PCI_STATUS:
+                conf_data |= PCI_STATUS_66MHZ;
+                conf_data |= PCI_STATUS_DEVSEL_MEDIUM;
+                conf_data |= PCI_STATUS_FAST_BACK;
+
+                _rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo);
+                if (lo & SB_TAS_ERR_FLAG)
+                        conf_data |= PCI_STATUS_SIG_TARGET_ABORT;
+                if (lo & SB_TAR_ERR_FLAG)
+                        conf_data |= PCI_STATUS_REC_TARGET_ABORT;
+                if (lo & SB_MAR_ERR_FLAG)
+                        conf_data |= PCI_STATUS_REC_MASTER_ABORT;
+                if (lo & SB_PARE_ERR_FLAG)
+                        conf_data |= PCI_STATUS_DETECTED_PARITY;
+                break;
+        case PCI_CLASS_REVISION:
+                _rdmsr(GLCP_MSR_REG(GLCP_CHIP_REV_ID), &hi, &lo);
+                conf_data = lo & 0x000000ff;
+                conf_data |= (CS5536_ISA_CLASS_CODE << 8);
+                break;
+        case PCI_CACHE_LINE_SIZE:
+                _rdmsr(SB_MSR_REG(SB_CTRL), &hi, &lo);
+                hi &= 0x000000f8;
+                conf_data = CFG_PCI_CACHE_LINE_SIZE(PCI_BRIDGE_HEADER_TYPE, hi);
+                break;
+                /*
+                 * we only use the LBAR of DIVIL, no RCONF used.
+                 * all of them are IO space.
+                 */
+        case PCI_BAR0_REG:
+                return pci_isa_read_bar(0);
+                break;
+        case PCI_BAR1_REG:
+                return pci_isa_read_bar(1);
+                break;
+        case PCI_BAR2_REG:
+                return pci_isa_read_bar(2);
+                break;
+        case PCI_BAR3_REG:
+                break;
+        case PCI_BAR4_REG:
+                return pci_isa_read_bar(4);
+                break;
+        case PCI_BAR5_REG:
+                return pci_isa_read_bar(5);
+                break;
+        case PCI_CARDBUS_CIS:
+                conf_data = PCI_CARDBUS_CIS_POINTER;
+                break;
+        case PCI_SUBSYSTEM_VENDOR_ID:
+                conf_data =
+                    CFG_PCI_VENDOR_ID(CS5536_ISA_SUB_ID, CS5536_SUB_VENDOR_ID);
+                break;
+        case PCI_ROM_ADDRESS:
+                conf_data = PCI_EXPANSION_ROM_BAR;
+                break;
+        case PCI_CAPABILITY_LIST:
+                conf_data = PCI_CAPLIST_POINTER;
+                break;
+        case PCI_INTERRUPT_LINE:
+                /* no interrupt used here */
+                conf_data = CFG_PCI_INTERRUPT_LINE(0x00, 0x00);
+                break;
+        default:
+                break;
+        }
+
+        return conf_data;
+}
diff --git a/arch/mips/loongson/common/cs5536/cs5536_mfgpt.c b/arch/mips/loongson/common/cs5536/cs5536_mfgpt.c
new file mode 100644
index 000000000000..6cb44dbaeec2
--- /dev/null
+++ b/arch/mips/loongson/common/cs5536/cs5536_mfgpt.c
@@ -0,0 +1,217 @@
+/*
+ * CS5536 General timer functions
+ *
+ * Copyright (C) 2007 Lemote Inc. & Insititute of Computing Technology
+ * Author: Yanhua, yanh@lemote.com
+ *
+ * Copyright (C) 2009 Lemote Inc.
+ * Author: Wu zhangjin, wuzj@lemote.com
+ *
+ * Reference: AMD Geode(TM) CS5536 Companion Device Data Book
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ */
+
+#include <linux/io.h>
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/jiffies.h>
+#include <linux/spinlock.h>
+#include <linux/interrupt.h>
+#include <linux/clockchips.h>
+
+#include <asm/time.h>
+
+#include <cs5536/cs5536_mfgpt.h>
+
+DEFINE_SPINLOCK(mfgpt_lock);
+EXPORT_SYMBOL(mfgpt_lock);
+
+static u32 mfgpt_base;
+
+/*
+ * Initialize the MFGPT timer.
+ *
+ * This is also called after resume to bring the MFGPT into operation again.
+ */
+
+/* disable counter */
+void disable_mfgpt0_counter(void)
+{
+        outw(inw(MFGPT0_SETUP) & 0x7fff, MFGPT0_SETUP);
+}
+EXPORT_SYMBOL(disable_mfgpt0_counter);
+
+/* enable counter, comparator2 to event mode, 14.318MHz clock */
+void enable_mfgpt0_counter(void)
+{
+        outw(0xe310, MFGPT0_SETUP);
+}
+EXPORT_SYMBOL(enable_mfgpt0_counter);
+
+static void init_mfgpt_timer(enum clock_event_mode mode,
+                             struct clock_event_device *evt)
+{
+        spin_lock(&mfgpt_lock);
+
+        switch (mode) {
+        case CLOCK_EVT_MODE_PERIODIC:
+                outw(COMPARE, MFGPT0_CMP2);     /* set comparator2 */
+                outw(0, MFGPT0_CNT);    /* set counter to 0 */
+                enable_mfgpt0_counter();
+                break;
+
+        case CLOCK_EVT_MODE_SHUTDOWN:
+        case CLOCK_EVT_MODE_UNUSED:
+                if (evt->mode == CLOCK_EVT_MODE_PERIODIC ||
+                    evt->mode == CLOCK_EVT_MODE_ONESHOT)
+                        disable_mfgpt0_counter();
+                break;
+
+        case CLOCK_EVT_MODE_ONESHOT:
+                /* The oneshot mode have very high deviation, Not use it! */
+                break;
+
+        case CLOCK_EVT_MODE_RESUME:
+                /* Nothing to do here */
+                break;
+        }
+        spin_unlock(&mfgpt_lock);
+}
+
+static struct clock_event_device mfgpt_clockevent = {
+        .name = "mfgpt",
+        .features = CLOCK_EVT_FEAT_PERIODIC,
+        .set_mode = init_mfgpt_timer,
+        .irq = CS5536_MFGPT_INTR,
+};
+
+static irqreturn_t timer_interrupt(int irq, void *dev_id)
+{
+        u32 basehi;
+
+        /*
+         * get MFGPT base address
+         *
+         * NOTE: do not remove me, it's need for the value of mfgpt_base is
+         * variable
+         */
+        _rdmsr(DIVIL_MSR_REG(DIVIL_LBAR_MFGPT), &basehi, &mfgpt_base);
+
+        /* ack */
+        outw(inw(MFGPT0_SETUP) | 0x4000, MFGPT0_SETUP);
+
+        mfgpt_clockevent.event_handler(&mfgpt_clockevent);
+
+        return IRQ_HANDLED;
+}
+
+static struct irqaction irq5 = {
+        .handler = timer_interrupt,
+        .flags = IRQF_DISABLED | IRQF_NOBALANCING | IRQF_TIMER,
+        .name = "timer"
+};
+
+/*
+ * Initialize the conversion factor and the min/max deltas of the clock event
+ * structure and register the clock event source with the framework.
+ */
+void __init setup_mfgpt0_timer(void)
+{
+        u32 basehi;
+        struct clock_event_device *cd = &mfgpt_clockevent;
+        unsigned int cpu = smp_processor_id();
+
+        cd->cpumask = cpumask_of(cpu);
+        clockevent_set_clock(cd, MFGPT_TICK_RATE);
+        cd->max_delta_ns = clockevent_delta2ns(0xffff, cd);
+        cd->min_delta_ns = clockevent_delta2ns(0xf, cd);
+
+        /* Enable MFGPT0 Comparator 2 Output to the Interrupt Mapper */
+        _wrmsr(DIVIL_MSR_REG(MFGPT_IRQ), 0, 0x100);
+
+        /* Enable Interrupt Gate 5 */
+        _wrmsr(DIVIL_MSR_REG(PIC_ZSEL_LOW), 0, 0x50000);
+
+        /* get MFGPT base address */
+        _rdmsr(DIVIL_MSR_REG(DIVIL_LBAR_MFGPT), &basehi, &mfgpt_base);
+
+        clockevents_register_device(cd);
+
+        setup_irq(CS5536_MFGPT_INTR, &irq5);
+}
+
+/*
+ * Since the MFGPT overflows every tick, its not very useful
+ * to just read by itself. So use jiffies to emulate a free
+ * running counter:
+ */
+static cycle_t mfgpt_read(struct clocksource *cs)
+{
+        unsigned long flags;
+        int count;
+        u32 jifs;
+        static int old_count;
+        static u32 old_jifs;
+
+        spin_lock_irqsave(&mfgpt_lock, flags);
+        /*
+         * Although our caller may have the read side of xtime_lock,
+         * this is now a seqlock, and we are cheating in this routine
+         * by having side effects on state that we cannot undo if
+         * there is a collision on the seqlock and our caller has to
+         * retry.  (Namely, old_jifs and old_count.)  So we must treat
+         * jiffies as volatile despite the lock.  We read jiffies
+         * before latching the timer count to guarantee that although
+         * the jiffies value might be older than the count (that is,
+         * the counter may underflow between the last point where
+         * jiffies was incremented and the point where we latch the
+         * count), it cannot be newer.
+         */
+        jifs = jiffies;
+        /* read the count */
+        count = inw(MFGPT0_CNT);
+
+        /*
+         * It's possible for count to appear to go the wrong way for this
+         * reason:
+         *
+         *  The timer counter underflows, but we haven't handled the resulting
+         *  interrupt and incremented jiffies yet.
+         *
+         * Previous attempts to handle these cases intelligently were buggy, so
+         * we just do the simple thing now.
+         */
+        if (count < old_count && jifs == old_jifs)
+                count = old_count;
+
+        old_count = count;
+        old_jifs = jifs;
+
+        spin_unlock_irqrestore(&mfgpt_lock, flags);
+
+        return (cycle_t) (jifs * COMPARE) + count;
+}
+
+static struct clocksource clocksource_mfgpt = {
+        .name = "mfgpt",
+        .rating = 120, /* Functional for real use, but not desired */
+        .read = mfgpt_read,
+        .mask = CLOCKSOURCE_MASK(32),
+        .mult = 0,
+        .shift = 22,
+};
+
+int __init init_mfgpt_clocksource(void)
+{
+        if (num_possible_cpus() > 1)    /* MFGPT does not scale! */
+                return 0;
+
+        clocksource_mfgpt.mult = clocksource_hz2mult(MFGPT_TICK_RATE, 22);
+        return clocksource_register(&clocksource_mfgpt);
+}
+
+arch_initcall(init_mfgpt_clocksource);
diff --git a/arch/mips/loongson/common/cs5536/cs5536_ohci.c b/arch/mips/loongson/common/cs5536/cs5536_ohci.c
new file mode 100644
index 000000000000..8fdb02b6e90f
--- /dev/null
+++ b/arch/mips/loongson/common/cs5536/cs5536_ohci.c
@@ -0,0 +1,147 @@
+/*
+ * the OHCI Virtual Support Module of AMD CS5536
+ *
+ * Copyright (C) 2007 Lemote, Inc.
+ * Author : jlliu, liujl@lemote.com
+ *
+ * Copyright (C) 2009 Lemote, Inc.
+ * Author: Wu Zhangjin, wuzj@lemote.com
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#include <cs5536/cs5536.h>
+#include <cs5536/cs5536_pci.h>
+
+void pci_ohci_write_reg(int reg, u32 value)
+{
+        u32 hi = 0, lo = value;
+
+        switch (reg) {
+        case PCI_COMMAND:
+                _rdmsr(USB_MSR_REG(USB_OHCI), &hi, &lo);
+                if (value & PCI_COMMAND_MASTER)
+                        hi |= PCI_COMMAND_MASTER;
+                else
+                        hi &= ~PCI_COMMAND_MASTER;
+
+                if (value & PCI_COMMAND_MEMORY)
+                        hi |= PCI_COMMAND_MEMORY;
+                else
+                        hi &= ~PCI_COMMAND_MEMORY;
+                _wrmsr(USB_MSR_REG(USB_OHCI), hi, lo);
+                break;
+        case PCI_STATUS:
+                if (value & PCI_STATUS_PARITY) {
+                        _rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo);
+                        if (lo & SB_PARE_ERR_FLAG) {
+                                lo = (lo & 0x0000ffff) | SB_PARE_ERR_FLAG;
+                                _wrmsr(SB_MSR_REG(SB_ERROR), hi, lo);
+                        }
+                }
+                break;
+        case PCI_BAR0_REG:
+                if (value == PCI_BAR_RANGE_MASK) {
+                        _rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo);
+                        lo |= SOFT_BAR_OHCI_FLAG;
+                        _wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo);
+                } else if ((value & 0x01) == 0x00) {
+                        _wrmsr(USB_MSR_REG(USB_OHCI), hi, lo);
+
+                        value &= 0xfffffff0;
+                        hi = 0x40000000 | ((value & 0xff000000) >> 24);
+                        lo = 0x000fffff | ((value & 0x00fff000) << 8);
+                        _wrmsr(GLIU_MSR_REG(GLIU_P2D_BM3), hi, lo);
+                }
+                break;
+        case PCI_OHCI_INT_REG:
+                _rdmsr(DIVIL_MSR_REG(PIC_YSEL_LOW), &hi, &lo);
+                lo &= ~(0xf << PIC_YSEL_LOW_USB_SHIFT);
+                if (value)      /* enable all the usb interrupt in PIC */
+                        lo |= (CS5536_USB_INTR << PIC_YSEL_LOW_USB_SHIFT);
+                _wrmsr(DIVIL_MSR_REG(PIC_YSEL_LOW), hi, lo);
+                break;
+        default:
+                break;
+        }
+}
+
+u32 pci_ohci_read_reg(int reg)
+{
+        u32 conf_data = 0;
+        u32 hi, lo;
+
+        switch (reg) {
+        case PCI_VENDOR_ID:
+                conf_data =
+                    CFG_PCI_VENDOR_ID(CS5536_OHCI_DEVICE_ID, CS5536_VENDOR_ID);
+                break;
+        case PCI_COMMAND:
+                _rdmsr(USB_MSR_REG(USB_OHCI), &hi, &lo);
+                if (hi & PCI_COMMAND_MASTER)
+                        conf_data |= PCI_COMMAND_MASTER;
+                if (hi & PCI_COMMAND_MEMORY)
+                        conf_data |= PCI_COMMAND_MEMORY;
+                break;
+        case PCI_STATUS:
+                conf_data |= PCI_STATUS_66MHZ;
+                conf_data |= PCI_STATUS_FAST_BACK;
+                _rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo);
+                if (lo & SB_PARE_ERR_FLAG)
+                        conf_data |= PCI_STATUS_PARITY;
+                conf_data |= PCI_STATUS_DEVSEL_MEDIUM;
+                break;
+        case PCI_CLASS_REVISION:
+                _rdmsr(USB_MSR_REG(USB_CAP), &hi, &lo);
+                conf_data = lo & 0x000000ff;
+                conf_data |= (CS5536_OHCI_CLASS_CODE << 8);
+                break;
+        case PCI_CACHE_LINE_SIZE:
+                conf_data =
+                    CFG_PCI_CACHE_LINE_SIZE(PCI_NORMAL_HEADER_TYPE,
+                                            PCI_NORMAL_LATENCY_TIMER);
+                break;
+        case PCI_BAR0_REG:
+                _rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo);
+                if (lo & SOFT_BAR_OHCI_FLAG) {
+                        conf_data = CS5536_OHCI_RANGE |
+                            PCI_BASE_ADDRESS_SPACE_MEMORY;
+                        lo &= ~SOFT_BAR_OHCI_FLAG;
+                        _wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo);
+                } else {
+                        _rdmsr(USB_MSR_REG(USB_OHCI), &hi, &lo);
+                        conf_data = lo & 0xffffff00;
+                        conf_data &= ~0x0000000f;       /* 32bit mem */
+                }
+                break;
+        case PCI_CARDBUS_CIS:
+                conf_data = PCI_CARDBUS_CIS_POINTER;
+                break;
+        case PCI_SUBSYSTEM_VENDOR_ID:
+                conf_data =
+                    CFG_PCI_VENDOR_ID(CS5536_OHCI_SUB_ID, CS5536_SUB_VENDOR_ID);
+                break;
+        case PCI_ROM_ADDRESS:
+                conf_data = PCI_EXPANSION_ROM_BAR;
+                break;
+        case PCI_CAPABILITY_LIST:
+                conf_data = PCI_CAPLIST_USB_POINTER;
+                break;
+        case PCI_INTERRUPT_LINE:
+                conf_data =
+                    CFG_PCI_INTERRUPT_LINE(PCI_DEFAULT_PIN, CS5536_USB_INTR);
+                break;
+        case PCI_OHCI_INT_REG:
+                _rdmsr(DIVIL_MSR_REG(PIC_YSEL_LOW), &hi, &lo);
+                if ((lo & 0x00000f00) == CS5536_USB_INTR)
+                        conf_data = 1;
+                break;
+        default:
+                break;
+        }
+
+        return conf_data;
+}
diff --git a/arch/mips/loongson/common/cs5536/cs5536_pci.c b/arch/mips/loongson/common/cs5536/cs5536_pci.c
new file mode 100644
index 000000000000..e23f3d7d2c1d
--- /dev/null
+++ b/arch/mips/loongson/common/cs5536/cs5536_pci.c
@@ -0,0 +1,87 @@
+/*
+ * read/write operation to the PCI config space of CS5536
+ *
+ * Copyright (C) 2007 Lemote, Inc.
+ * Author : jlliu, liujl@lemote.com
+ *
+ * Copyright (C) 2009 Lemote, Inc.
+ * Author: Wu Zhangjin, wuzj@lemote.com
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ *
+ *      the Virtual Support Module(VSM) for virtulizing the PCI
+ *      configure space are defined in cs5536_modulename.c respectively,
+ *
+ *      after this virtulizing, user can access the PCI configure space
+ *      directly as a normal multi-function PCI device which follows
+ *      the PCI-2.2 spec.
+ */
+
+#include <linux/types.h>
+#include <cs5536/cs5536_vsm.h>
+
+enum {
+        CS5536_FUNC_START = -1,
+        CS5536_ISA_FUNC,
+        reserved_func,
+        CS5536_IDE_FUNC,
+        CS5536_ACC_FUNC,
+        CS5536_OHCI_FUNC,
+        CS5536_EHCI_FUNC,
+        CS5536_FUNC_END,
+};
+
+static const cs5536_pci_vsm_write vsm_conf_write[] = {
+        [CS5536_ISA_FUNC]       pci_isa_write_reg,
+        [reserved_func]         NULL,
+        [CS5536_IDE_FUNC]       pci_ide_write_reg,
+        [CS5536_ACC_FUNC]       pci_acc_write_reg,
+        [CS5536_OHCI_FUNC]      pci_ohci_write_reg,
+        [CS5536_EHCI_FUNC]      pci_ehci_write_reg,
+};
+
+static const cs5536_pci_vsm_read vsm_conf_read[] = {
+        [CS5536_ISA_FUNC]       pci_isa_read_reg,
+        [reserved_func]         NULL,
+        [CS5536_IDE_FUNC]       pci_ide_read_reg,
+        [CS5536_ACC_FUNC]       pci_acc_read_reg,
+        [CS5536_OHCI_FUNC]      pci_ohci_read_reg,
+        [CS5536_EHCI_FUNC]      pci_ehci_read_reg,
+};
+
+/*
+ * write to PCI config space and transfer it to MSR write.
+ */
+void cs5536_pci_conf_write4(int function, int reg, u32 value)
+{
+        if ((function <= CS5536_FUNC_START) || (function >= CS5536_FUNC_END))
+                return;
+        if ((reg < 0) || (reg > 0x100) || ((reg & 0x03) != 0))
+                return;
+
+        if (vsm_conf_write[function] != NULL)
+                vsm_conf_write[function](reg, value);
+}
+
+/*
+ * read PCI config space and transfer it to MSR access.
+ */
+u32 cs5536_pci_conf_read4(int function, int reg)
+{
+        u32 data = 0;
+
+        if ((function <= CS5536_FUNC_START) || (function >= CS5536_FUNC_END))
+                return 0;
+        if ((reg < 0) || ((reg & 0x03) != 0))
+                return 0;
+        if (reg > 0x100)
+                return 0xffffffff;
+
+        if (vsm_conf_read[function] != NULL)
+                data = vsm_conf_read[function](reg);
+
+        return data;
+}
diff --git a/arch/mips/loongson/common/early_printk.c b/arch/mips/loongson/common/early_printk.c
index bc73edc0cfd8..23e7a8f8897f 100644
--- a/arch/mips/loongson/common/early_printk.c
+++ b/arch/mips/loongson/common/early_printk.c
@@ -1,7 +1,7 @@
 /*  early printk support
  *
  *  Copyright (c) 2009 Philippe Vachon <philippe@cowpig.ca>
- *  Copyright (C) 2009 Lemote Inc. & Insititute of Computing Technology
+ *  Copyright (c) 2009 Lemote Inc.
  *  Author: Wu Zhangjin, wuzj@lemote.com
  *
  *  This program is free software; you can redistribute  it and/or modify it
@@ -12,26 +12,29 @@
 #include <linux/serial_reg.h>
 
 #include <loongson.h>
-#include <machine.h>
 
 #define PORT(base, offset) (u8 *)(base + offset)
 
-static inline unsigned int serial_in(phys_addr_t base, int offset)
+static inline unsigned int serial_in(unsigned char *base, int offset)
 {
         return readb(PORT(base, offset));
 }
 
-static inline void serial_out(phys_addr_t base, int offset, int value)
+static inline void serial_out(unsigned char *base, int offset, int value)
 {
         writeb(value, PORT(base, offset));
 }
 
 void prom_putchar(char c)
 {
-        phys_addr_t uart_base =
-                (phys_addr_t) ioremap_nocache(LOONGSON_UART_BASE, 8);
+        int timeout;
+        unsigned char *uart_base;
 
-        while ((serial_in(uart_base, UART_LSR) & UART_LSR_THRE) == 0)
+        uart_base = (unsigned char *)_loongson_uart_base;
+        timeout = 1024;
+
+        while (((serial_in(uart_base, UART_LSR) & UART_LSR_THRE) == 0) &&
+                        (timeout-- > 0))
                 ;
 
         serial_out(uart_base, UART_TX, c);
diff --git a/arch/mips/loongson/common/env.c b/arch/mips/loongson/common/env.c
index b9ef50385541..196d947d929a 100644
--- a/arch/mips/loongson/common/env.c
+++ b/arch/mips/loongson/common/env.c
@@ -17,11 +17,14 @@
  * Free Software Foundation;  either version 2 of the  License, or (at your
  * option) any later version.
  */
+#include <linux/module.h>
+
 #include <asm/bootinfo.h>
 
 #include <loongson.h>
 
 unsigned long bus_clock, cpu_clock_freq;
+EXPORT_SYMBOL(cpu_clock_freq);
 unsigned long memsize, highmemsize;
 
 /* pmon passes arguments in 32bit pointers */
diff --git a/arch/mips/loongson/common/init.c b/arch/mips/loongson/common/init.c
index 3abe927422a3..a2abd9355737 100644
--- a/arch/mips/loongson/common/init.c
+++ b/arch/mips/loongson/common/init.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2009 Lemote Inc. & Insititute of Computing Technology
+ * Copyright (C) 2009 Lemote Inc.
  * Author: Wu Zhangjin, wuzj@lemote.com
  *
  * This program is free software; you can redistribute  it and/or modify it
@@ -10,19 +10,28 @@
 
 #include <linux/bootmem.h>
 
-#include <asm/bootinfo.h>
-
 #include <loongson.h>
 
+/* Loongson CPU address windows config space base address */
+unsigned long __maybe_unused _loongson_addrwincfg_base;
+
 void __init prom_init(void)
 {
-    /* init base address of io space */
+        /* init base address of io space */
         set_io_port_base((unsigned long)
-                ioremap(BONITO_PCIIO_BASE, BONITO_PCIIO_SIZE));
+                ioremap(LOONGSON_PCIIO_BASE, LOONGSON_PCIIO_SIZE));
+
+#ifdef CONFIG_CPU_SUPPORTS_ADDRWINCFG
+        _loongson_addrwincfg_base = (unsigned long)
+                ioremap(LOONGSON_ADDRWINCFG_BASE, LOONGSON_ADDRWINCFG_SIZE);
+#endif
 
         prom_init_cmdline();
         prom_init_env();
         prom_init_memory();
+
+        /*init the uart base address */
+        prom_init_uart_base();
 }
 
 void __init prom_free_prom_memory(void)
diff --git a/arch/mips/loongson/common/irq.c b/arch/mips/loongson/common/irq.c
index b32b4a3e5137..20e732831978 100644
--- a/arch/mips/loongson/common/irq.c
+++ b/arch/mips/loongson/common/irq.c
@@ -20,21 +20,21 @@ void bonito_irqdispatch(void)
         int i;
 
         /* workaround the IO dma problem: let cpu looping to allow DMA finish */
-        int_status = BONITO_INTISR;
+        int_status = LOONGSON_INTISR;
         if (int_status & (1 << 10)) {
                 while (int_status & (1 << 10)) {
                         udelay(1);
-                        int_status = BONITO_INTISR;
+                        int_status = LOONGSON_INTISR;
                 }
         }
 
         /* Get pending sources, masked by current enables */
-        int_status = BONITO_INTISR & BONITO_INTEN;
+        int_status = LOONGSON_INTISR & LOONGSON_INTEN;
 
         if (int_status != 0) {
                 i = __ffs(int_status);
                 int_status &= ~(1 << i);
-                do_IRQ(BONITO_IRQ_BASE + i);
+                do_IRQ(LOONGSON_IRQ_BASE + i);
         }
 }
 
@@ -60,13 +60,13 @@ void __init arch_init_irq(void)
         set_irq_trigger_mode();
 
         /* no steer */
-        BONITO_INTSTEER = 0;
+        LOONGSON_INTSTEER = 0;
 
         /*
          * Mask out all interrupt by writing "1" to all bit position in
          * the interrupt reset reg.
          */
-        BONITO_INTENCLR = ~0;
+        LOONGSON_INTENCLR = ~0;
 
         /* machine specific irq init */
         mach_init_irq();
diff --git a/arch/mips/loongson/common/machtype.c b/arch/mips/loongson/common/machtype.c
index 7b348248de7d..0ed52b3f5314 100644
--- a/arch/mips/loongson/common/machtype.c
+++ b/arch/mips/loongson/common/machtype.c
@@ -15,6 +15,9 @@
 #include <loongson.h>
 #include <machine.h>
 
+/* please ensure the length of the machtype string is less than 50 */
+#define MACHTYPE_LEN 50
+
 static const char *system_types[] = {
         [MACH_LOONGSON_UNKNOWN]         "unknown loongson machine",
         [MACH_LEMOTE_FL2E]              "lemote-fuloong-2e-box",
@@ -22,29 +25,35 @@ static const char *system_types[] = {
         [MACH_LEMOTE_ML2F7]             "lemote-mengloong-2f-7inches",
         [MACH_LEMOTE_YL2F89]            "lemote-yeeloong-2f-8.9inches",
         [MACH_DEXXON_GDIUM2F10]         "dexxon-gidum-2f-10inches",
+        [MACH_LEMOTE_NAS]               "lemote-nas-2f",
+        [MACH_LEMOTE_LL2F]              "lemote-lynloong-2f",
         [MACH_LOONGSON_END]             NULL,
 };
 
 const char *get_system_type(void)
 {
-        if (mips_machtype == MACH_UNKNOWN)
-                mips_machtype = LOONGSON_MACHTYPE;
-
         return system_types[mips_machtype];
 }
 
-static __init int machtype_setup(char *str)
+void __init prom_init_machtype(void)
 {
+        char *p, str[MACHTYPE_LEN];
         int machtype = MACH_LEMOTE_FL2E;
 
-        if (!str)
-                return -EINVAL;
+        mips_machtype = LOONGSON_MACHTYPE;
+
+        p = strstr(arcs_cmdline, "machtype=");
+        if (!p)
+                return;
+        p += strlen("machtype=");
+        strncpy(str, p, MACHTYPE_LEN);
+        p = strstr(str, " ");
+        if (p)
+                *p = '\0';
 
         for (; system_types[machtype]; machtype++)
                 if (strstr(system_types[machtype], str)) {
                         mips_machtype = machtype;
                         break;
                 }
-        return 0;
 }
-__setup("machtype=", machtype_setup);
diff --git a/arch/mips/loongson/common/mem.c b/arch/mips/loongson/common/mem.c
index 7c92f79b6480..ceacd092b446 100644
--- a/arch/mips/loongson/common/mem.c
+++ b/arch/mips/loongson/common/mem.c
@@ -12,24 +12,107 @@
 
 #include <loongson.h>
 #include <mem.h>
+#include <pci.h>
 
 void __init prom_init_memory(void)
 {
     add_memory_region(0x0, (memsize << 20), BOOT_MEM_RAM);
+
+    add_memory_region(memsize << 20, LOONGSON_PCI_MEM_START - (memsize <<
+                            20), BOOT_MEM_RESERVED);
+#ifdef CONFIG_CPU_SUPPORTS_ADDRWINCFG
+        {
+                int bit;
+
+                bit = fls(memsize + highmemsize);
+                if (bit != ffs(memsize + highmemsize))
+                        bit += 20;
+                else
+                        bit = bit + 20 - 1;
+
+                /* set cpu window3 to map CPU to DDR: 2G -> 2G */
+                LOONGSON_ADDRWIN_CPUTODDR(ADDRWIN_WIN3, 0x80000000ul,
+                                          0x80000000ul, (1 << bit));
+                mmiowb();
+        }
+#endif /* !CONFIG_CPU_SUPPORTS_ADDRWINCFG */
+
 #ifdef CONFIG_64BIT
-    if (highmemsize > 0)
-        add_memory_region(LOONGSON_HIGHMEM_START,
-                highmemsize << 20, BOOT_MEM_RAM);
-#endif /* CONFIG_64BIT */
+        if (highmemsize > 0)
+                add_memory_region(LOONGSON_HIGHMEM_START,
+                                  highmemsize << 20, BOOT_MEM_RAM);
+
+        add_memory_region(LOONGSON_PCI_MEM_END + 1, LOONGSON_HIGHMEM_START -
+                          LOONGSON_PCI_MEM_END - 1, BOOT_MEM_RESERVED);
+
+#endif /* !CONFIG_64BIT */
 }
 
 /* override of arch/mips/mm/cache.c: __uncached_access */
 int __uncached_access(struct file *file, unsigned long addr)
 {
-        if (file->f_flags & O_SYNC)
+        if (file->f_flags & O_DSYNC)
                 return 1;
 
         return addr >= __pa(high_memory) ||
                 ((addr >= LOONGSON_MMIO_MEM_START) &&
                  (addr < LOONGSON_MMIO_MEM_END));
 }
+
+#ifdef CONFIG_CPU_SUPPORTS_UNCACHED_ACCELERATED
+
+#include <linux/pci.h>
+#include <linux/sched.h>
+#include <asm/current.h>
+
+static unsigned long uca_start, uca_end;
+
+pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
+                              unsigned long size, pgprot_t vma_prot)
+{
+        unsigned long offset = pfn << PAGE_SHIFT;
+        unsigned long end = offset + size;
+
+        if (__uncached_access(file, offset)) {
+                if (((uca_start && offset) >= uca_start) &&
+                    (end <= uca_end))
+                        return __pgprot((pgprot_val(vma_prot) &
+                                         ~_CACHE_MASK) |
+                                        _CACHE_UNCACHED_ACCELERATED);
+                else
+                        return pgprot_noncached(vma_prot);
+        }
+        return vma_prot;
+}
+
+static int __init find_vga_mem_init(void)
+{
+        struct pci_dev *dev = 0;
+        struct resource *r;
+        int idx;
+
+        if (uca_start)
+                return 0;
+
+        for_each_pci_dev(dev) {
+                if ((dev->class >> 8) == PCI_CLASS_DISPLAY_VGA) {
+                        for (idx = 0; idx < PCI_NUM_RESOURCES; idx++) {
+                                r = &dev->resource[idx];
+                                if (!r->start && r->end)
+                                        continue;
+                                if (r->flags & IORESOURCE_IO)
+                                        continue;
+                                if (r->flags & IORESOURCE_MEM) {
+                                        uca_start = r->start;
+                                        uca_end = r->end;
+                                        return 0;
+                                }
+                        }
+                }
+        }
+
+        return 0;
+}
+
+late_initcall(find_vga_mem_init);
+#endif /* !CONFIG_CPU_SUPPORTS_UNCACHED_ACCELERATED */
diff --git a/arch/mips/loongson/common/pci.c b/arch/mips/loongson/common/pci.c
index a3a4abfb6c9a..31d8c5ecd16c 100644
--- a/arch/mips/loongson/common/pci.c
+++ b/arch/mips/loongson/common/pci.c
@@ -27,7 +27,7 @@ static struct resource loongson_pci_io_resource = {
 };
 
 static struct pci_controller  loongson_pci_controller = {
-        .pci_ops        = &bonito64_pci_ops,
+        .pci_ops        = &loongson_pci_ops,
         .io_resource    = &loongson_pci_io_resource,
         .mem_resource   = &loongson_pci_mem_resource,
         .mem_offset     = 0x00000000UL,
@@ -44,15 +44,15 @@ static void __init setup_pcimap(void)
          * pcimap: PCI_MAP2  PCI_Mem_Lo2 PCI_Mem_Lo1 PCI_Mem_Lo0
          *           [<2G]   [384M,448M] [320M,384M] [0M,64M]
          */
-        BONITO_PCIMAP = BONITO_PCIMAP_PCIMAP_2 |
-                BONITO_PCIMAP_WIN(2, BONITO_PCILO2_BASE) |
-                BONITO_PCIMAP_WIN(1, BONITO_PCILO1_BASE) |
-                BONITO_PCIMAP_WIN(0, 0);
+        LOONGSON_PCIMAP = LOONGSON_PCIMAP_PCIMAP_2 |
+                LOONGSON_PCIMAP_WIN(2, LOONGSON_PCILO2_BASE) |
+                LOONGSON_PCIMAP_WIN(1, LOONGSON_PCILO1_BASE) |
+                LOONGSON_PCIMAP_WIN(0, 0);
 
         /*
          * PCI-DMA to local mapping: [2G,2G+256M] -> [0M,256M]
          */
-        BONITO_PCIBASE0 = 0x80000000ul;   /* base: 2G -> mmap: 0M */
+        LOONGSON_PCIBASE0 = 0x80000000ul;   /* base: 2G -> mmap: 0M */
         /* size: 256M, burst transmission, pre-fetch enable, 64bit */
         LOONGSON_PCI_HIT0_SEL_L = 0xc000000cul;
         LOONGSON_PCI_HIT0_SEL_H = 0xfffffffful;
@@ -67,6 +67,14 @@ static void __init setup_pcimap(void)
         /* can not change gnt to break pci transfer when device's gnt not
         deassert for some broken device */
         LOONGSON_PXARB_CFG = 0x00fe0105ul;
+
+#ifdef CONFIG_CPU_SUPPORTS_ADDRWINCFG
+        /*
+         * set cpu addr window2 to map CPU address space to PCI address space
+         */
+        LOONGSON_ADDRWIN_CPUTOPCI(ADDRWIN_WIN2, LOONGSON_CPU_MEM_SRC,
+                LOONGSON_PCI_MEM_DST, MMAP_CPUTOPCI_SIZE);
+#endif
 }
 
 static int __init pcibios_init(void)
diff --git a/arch/mips/loongson/common/platform.c b/arch/mips/loongson/common/platform.c
new file mode 100644
index 000000000000..be81777eb94d
--- /dev/null
+++ b/arch/mips/loongson/common/platform.c
@@ -0,0 +1,30 @@
+/*
+ * Copyright (C) 2009 Lemote Inc.
+ * Author: Wu Zhangjin, wuzj@lemote.com
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/err.h>
+#include <linux/platform_device.h>
+
+static struct platform_device loongson2_cpufreq_device = {
+        .name = "loongson2_cpufreq",
+        .id = -1,
+};
+
+static int __init loongson2_cpufreq_init(void)
+{
+        struct cpuinfo_mips *c = &current_cpu_data;
+
+        /* Only 2F revision and it's successors support CPUFreq */
+        if ((c->processor_id & PRID_REV_MASK) >= PRID_REV_LOONGSON2F)
+                return platform_device_register(&loongson2_cpufreq_device);
+
+        return -ENODEV;
+}
+
+arch_initcall(loongson2_cpufreq_init);
diff --git a/arch/mips/loongson/common/pm.c b/arch/mips/loongson/common/pm.c
new file mode 100644
index 000000000000..b625fec8a4d5
--- /dev/null
+++ b/arch/mips/loongson/common/pm.c
@@ -0,0 +1,161 @@
+/*
+ * loongson-specific suspend support
+ *
+ *  Copyright (C) 2009 Lemote Inc.
+ *  Author: Wu Zhangjin <wuzj@lemote.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+#include <linux/suspend.h>
+#include <linux/interrupt.h>
+#include <linux/pm.h>
+
+#include <asm/i8259.h>
+#include <asm/mipsregs.h>
+
+#include <loongson.h>
+
+static unsigned int __maybe_unused cached_master_mask;  /* i8259A */
+static unsigned int __maybe_unused cached_slave_mask;
+static unsigned int __maybe_unused cached_bonito_irq_mask; /* bonito */
+
+void arch_suspend_disable_irqs(void)
+{
+        /* disable all mips events */
+        local_irq_disable();
+
+#ifdef CONFIG_I8259
+        /* disable all events of i8259A */
+        cached_slave_mask = inb(PIC_SLAVE_IMR);
+        cached_master_mask = inb(PIC_MASTER_IMR);
+
+        outb(0xff, PIC_SLAVE_IMR);
+        inb(PIC_SLAVE_IMR);
+        outb(0xff, PIC_MASTER_IMR);
+        inb(PIC_MASTER_IMR);
+#endif
+        /* disable all events of bonito */
+        cached_bonito_irq_mask = LOONGSON_INTEN;
+        LOONGSON_INTENCLR = 0xffff;
+        (void)LOONGSON_INTENCLR;
+}
+
+void arch_suspend_enable_irqs(void)
+{
+        /* enable all mips events */
+        local_irq_enable();
+#ifdef CONFIG_I8259
+        /* only enable the cached events of i8259A */
+        outb(cached_slave_mask, PIC_SLAVE_IMR);
+        outb(cached_master_mask, PIC_MASTER_IMR);
+#endif
+        /* enable all cached events of bonito */
+        LOONGSON_INTENSET = cached_bonito_irq_mask;
+        (void)LOONGSON_INTENSET;
+}
+
+/*
+ * Setup the board-specific events for waking up loongson from wait mode
+ */
+void __weak setup_wakeup_events(void)
+{
+}
+
+/*
+ * Check wakeup events
+ */
+int __weak wakeup_loongson(void)
+{
+        return 1;
+}
+
+/*
+ * If the events are really what we want to wakeup the CPU, wake it up
+ * otherwise put the CPU asleep again.
+ */
+static void wait_for_wakeup_events(void)
+{
+        while (!wakeup_loongson())
+                LOONGSON_CHIPCFG0 &= ~0x7;
+}
+
+/*
+ * Stop all perf counters
+ *
+ * $24 is the control register of Loongson perf counter
+ */
+static inline void stop_perf_counters(void)
+{
+        __write_64bit_c0_register($24, 0, 0);
+}
+
+
+static void loongson_suspend_enter(void)
+{
+        static unsigned int cached_cpu_freq;
+
+        /* setup wakeup events via enabling the IRQs */
+        setup_wakeup_events();
+
+        stop_perf_counters();
+
+        cached_cpu_freq = LOONGSON_CHIPCFG0;
+
+        /* Put CPU into wait mode */
+        LOONGSON_CHIPCFG0 &= ~0x7;
+
+        /* wait for the given events to wakeup cpu from wait mode */
+        wait_for_wakeup_events();
+
+        LOONGSON_CHIPCFG0 = cached_cpu_freq;
+        mmiowb();
+}
+
+void __weak mach_suspend(void)
+{
+}
+
+void __weak mach_resume(void)
+{
+}
+
+static int loongson_pm_enter(suspend_state_t state)
+{
+        mach_suspend();
+
+        /* processor specific suspend */
+        loongson_suspend_enter();
+
+        mach_resume();
+
+        return 0;
+}
+
+static int loongson_pm_valid_state(suspend_state_t state)
+{
+        switch (state) {
+        case PM_SUSPEND_ON:
+        case PM_SUSPEND_STANDBY:
+        case PM_SUSPEND_MEM:
+                return 1;
+
+        default:
+                return 0;
+        }
+}
+
+static struct platform_suspend_ops loongson_pm_ops = {
+        .valid  = loongson_pm_valid_state,
+        .enter  = loongson_pm_enter,
+};
+
+static int __init loongson_pm_init(void)
+{
+        suspend_set_ops(&loongson_pm_ops);
+
+        return 0;
+}
+arch_initcall(loongson_pm_init);
diff --git a/arch/mips/loongson/common/reset.c b/arch/mips/loongson/common/reset.c
index 97e918251edd..d57f1719da95 100644
--- a/arch/mips/loongson/common/reset.c
+++ b/arch/mips/loongson/common/reset.c
@@ -22,7 +22,7 @@ static void loongson_restart(char *command)
         mach_prepare_reboot();
 
         /* reboot via jumping to boot base address */
-        ((void (*)(void))ioremap_nocache(BONITO_BOOT_BASE, 4)) ();
+        ((void (*)(void))ioremap_nocache(LOONGSON_BOOT_BASE, 4)) ();
 }
 
 static void loongson_halt(void)
diff --git a/arch/mips/loongson/common/serial.c b/arch/mips/loongson/common/serial.c
new file mode 100644
index 000000000000..23b66a5f88cb
--- /dev/null
+++ b/arch/mips/loongson/common/serial.c
@@ -0,0 +1,76 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2007 Ralf Baechle (ralf@linux-mips.org)
+ *
+ * Copyright (C) 2009 Lemote, Inc.
+ * Author: Yan hua (yanhua@lemote.com)
+ * Author: Wu Zhangjin (wuzj@lemote.com)
+ */
+
+#include <linux/io.h>
+#include <linux/init.h>
+#include <linux/serial_8250.h>
+
+#include <asm/bootinfo.h>
+
+#include <loongson.h>
+#include <machine.h>
+
+#define PORT(int)                       \
+{                                                               \
+        .irq            = int,                                  \
+        .uartclk        = 1843200,                              \
+        .iotype         = UPIO_PORT,                            \
+        .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,    \
+        .regshift       = 0,                                    \
+}
+
+#define PORT_M(int)                             \
+{                                                               \
+        .irq            = MIPS_CPU_IRQ_BASE + (int),            \
+        .uartclk        = 3686400,                              \
+        .iotype         = UPIO_MEM,                             \
+        .membase        = (void __iomem *)NULL,                 \
+        .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,    \
+        .regshift       = 0,                                    \
+}
+
+static struct plat_serial8250_port uart8250_data[][2] = {
+        [MACH_LOONGSON_UNKNOWN]         {},
+        [MACH_LEMOTE_FL2E]              {PORT(4), {} },
+        [MACH_LEMOTE_FL2F]              {PORT(3), {} },
+        [MACH_LEMOTE_ML2F7]             {PORT_M(3), {} },
+        [MACH_LEMOTE_YL2F89]            {PORT_M(3), {} },
+        [MACH_DEXXON_GDIUM2F10]         {PORT_M(3), {} },
+        [MACH_LEMOTE_NAS]               {PORT_M(3), {} },
+        [MACH_LEMOTE_LL2F]              {PORT(3), {} },
+        [MACH_LOONGSON_END]             {},
+};
+
+static struct platform_device uart8250_device = {
+        .name = "serial8250",
+        .id = PLAT8250_DEV_PLATFORM,
+};
+
+static int __init serial_init(void)
+{
+        unsigned char iotype;
+
+        iotype = uart8250_data[mips_machtype][0].iotype;
+
+        if (UPIO_MEM == iotype)
+                uart8250_data[mips_machtype][0].membase =
+                        (void __iomem *)_loongson_uart_base;
+        else if (UPIO_PORT == iotype)
+                uart8250_data[mips_machtype][0].iobase =
+                    loongson_uart_base - LOONGSON_PCIIO_BASE;
+
+        uart8250_device.dev.platform_data = uart8250_data[mips_machtype];
+
+        return platform_device_register(&uart8250_device);
+}
+
+device_initcall(serial_init);
diff --git a/arch/mips/loongson/common/time.c b/arch/mips/loongson/common/time.c
index 6e08c8270abe..35f0b66a94f5 100644
--- a/arch/mips/loongson/common/time.c
+++ b/arch/mips/loongson/common/time.c
@@ -14,11 +14,14 @@
 #include <asm/time.h>
 
 #include <loongson.h>
+#include <cs5536/cs5536_mfgpt.h>
 
 void __init plat_time_init(void)
 {
         /* setup mips r4k timer */
         mips_hpt_frequency = cpu_clock_freq / 2;
+
+        setup_mfgpt0_timer();
 }
 
 void read_persistent_clock(struct timespec *ts)
diff --git a/arch/mips/loongson/common/uart_base.c b/arch/mips/loongson/common/uart_base.c
new file mode 100644
index 000000000000..78ff66ae749e
--- /dev/null
+++ b/arch/mips/loongson/common/uart_base.c
@@ -0,0 +1,45 @@
+/*
+ * Copyright (C) 2009 Lemote Inc.
+ * Author: Wu Zhangjin, wuzj@lemote.com
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/module.h>
+#include <asm/bootinfo.h>
+
+#include <loongson.h>
+
+/* ioremapped */
+unsigned long _loongson_uart_base;
+EXPORT_SYMBOL(_loongson_uart_base);
+/* raw */
+unsigned long loongson_uart_base;
+EXPORT_SYMBOL(loongson_uart_base);
+
+void prom_init_loongson_uart_base(void)
+{
+        switch (mips_machtype) {
+        case MACH_LEMOTE_FL2E:
+                loongson_uart_base = LOONGSON_PCIIO_BASE + 0x3f8;
+                break;
+        case MACH_LEMOTE_FL2F:
+        case MACH_LEMOTE_LL2F:
+                loongson_uart_base = LOONGSON_PCIIO_BASE + 0x2f8;
+                break;
+        case MACH_LEMOTE_ML2F7:
+        case MACH_LEMOTE_YL2F89:
+        case MACH_DEXXON_GDIUM2F10:
+        case MACH_LEMOTE_NAS:
+        default:
+                /* The CPU provided serial port */
+                loongson_uart_base = LOONGSON_LIO1_BASE + 0x3f8;
+                break;
+        }
+
+        _loongson_uart_base =
+                (unsigned long)ioremap_nocache(loongson_uart_base, 8);
+}
diff --git a/arch/mips/loongson/fuloong-2e/irq.c b/arch/mips/loongson/fuloong-2e/irq.c
index 7888cf69424a..320e9379bdd7 100644
--- a/arch/mips/loongson/fuloong-2e/irq.c
+++ b/arch/mips/loongson/fuloong-2e/irq.c
@@ -47,8 +47,8 @@ static struct irqaction cascade_irqaction = {
 void __init set_irq_trigger_mode(void)
 {
         /* most bonito irq should be level triggered */
-        BONITO_INTEDGE = BONITO_ICU_SYSTEMERR | BONITO_ICU_MASTERERR |
-            BONITO_ICU_RETRYERR | BONITO_ICU_MBOXES;
+        LOONGSON_INTEDGE = LOONGSON_ICU_SYSTEMERR | LOONGSON_ICU_MASTERERR |
+            LOONGSON_ICU_RETRYERR | LOONGSON_ICU_MBOXES;
 }
 
 void __init mach_init_irq(void)
diff --git a/arch/mips/loongson/fuloong-2e/reset.c b/arch/mips/loongson/fuloong-2e/reset.c
index 677fe186db95..fc16c677d476 100644
--- a/arch/mips/loongson/fuloong-2e/reset.c
+++ b/arch/mips/loongson/fuloong-2e/reset.c
@@ -14,8 +14,8 @@
 
 void mach_prepare_reboot(void)
 {
-        BONITO_BONGENCFG &= ~(1 << 2);
-        BONITO_BONGENCFG |= (1 << 2);
+        LOONGSON_GENCFG &= ~(1 << 2);
+        LOONGSON_GENCFG |= (1 << 2);
 }
 
 void mach_prepare_shutdown(void)
diff --git a/arch/mips/loongson/lemote-2f/Makefile b/arch/mips/loongson/lemote-2f/Makefile
new file mode 100644
index 000000000000..4d84b27dc41b
--- /dev/null
+++ b/arch/mips/loongson/lemote-2f/Makefile
@@ -0,0 +1,11 @@
+#
+# Makefile for lemote loongson2f family machines
+#
+
+obj-y += irq.o reset.o ec_kb3310b.o
+
+#
+# Suspend Support
+#
+
+obj-$(CONFIG_LOONGSON_SUSPEND) += pm.o
diff --git a/arch/mips/loongson/lemote-2f/ec_kb3310b.c b/arch/mips/loongson/lemote-2f/ec_kb3310b.c
new file mode 100644
index 000000000000..4d84111a2cd4
--- /dev/null
+++ b/arch/mips/loongson/lemote-2f/ec_kb3310b.c
@@ -0,0 +1,130 @@
+/*
+ * Basic KB3310B Embedded Controller support for the YeeLoong 2F netbook
+ *
+ *  Copyright (C) 2008 Lemote Inc.
+ *  Author: liujl <liujl@lemote.com>, 2008-04-20
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <linux/module.h>
+#include <linux/spinlock.h>
+#include <linux/delay.h>
+
+#include "ec_kb3310b.h"
+
+static DEFINE_SPINLOCK(index_access_lock);
+static DEFINE_SPINLOCK(port_access_lock);
+
+unsigned char ec_read(unsigned short addr)
+{
+        unsigned char value;
+        unsigned long flags;
+
+        spin_lock_irqsave(&index_access_lock, flags);
+        outb((addr & 0xff00) >> 8, EC_IO_PORT_HIGH);
+        outb((addr & 0x00ff), EC_IO_PORT_LOW);
+        value = inb(EC_IO_PORT_DATA);
+        spin_unlock_irqrestore(&index_access_lock, flags);
+
+        return value;
+}
+EXPORT_SYMBOL_GPL(ec_read);
+
+void ec_write(unsigned short addr, unsigned char val)
+{
+        unsigned long flags;
+
+        spin_lock_irqsave(&index_access_lock, flags);
+        outb((addr & 0xff00) >> 8, EC_IO_PORT_HIGH);
+        outb((addr & 0x00ff), EC_IO_PORT_LOW);
+        outb(val, EC_IO_PORT_DATA);
+        /*  flush the write action */
+        inb(EC_IO_PORT_DATA);
+        spin_unlock_irqrestore(&index_access_lock, flags);
+
+        return;
+}
+EXPORT_SYMBOL_GPL(ec_write);
+
+/*
+ * This function is used for EC command writes and corresponding status queries.
+ */
+int ec_query_seq(unsigned char cmd)
+{
+        int timeout;
+        unsigned char status;
+        unsigned long flags;
+        int ret = 0;
+
+        spin_lock_irqsave(&port_access_lock, flags);
+
+        /* make chip goto reset mode */
+        udelay(EC_REG_DELAY);
+        outb(cmd, EC_CMD_PORT);
+        udelay(EC_REG_DELAY);
+
+        /* check if the command is received by ec */
+        timeout = EC_CMD_TIMEOUT;
+        status = inb(EC_STS_PORT);
+        while (timeout-- && (status & (1 << 1))) {
+                status = inb(EC_STS_PORT);
+                udelay(EC_REG_DELAY);
+        }
+
+        if (timeout <= 0) {
+                printk(KERN_ERR "%s: deadable error : timeout...\n", __func__);
+                ret = -EINVAL;
+        } else
+                printk(KERN_INFO
+                           "(%x/%d)ec issued command %d status : 0x%x\n",
+                           timeout, EC_CMD_TIMEOUT - timeout, cmd, status);
+
+        spin_unlock_irqrestore(&port_access_lock, flags);
+
+        return ret;
+}
+EXPORT_SYMBOL_GPL(ec_query_seq);
+
+/*
+ * Send query command to EC to get the proper event number
+ */
+int ec_query_event_num(void)
+{
+        return ec_query_seq(CMD_GET_EVENT_NUM);
+}
+EXPORT_SYMBOL(ec_query_event_num);
+
+/*
+ * Get event number from EC
+ *
+ * NOTE: This routine must follow the query_event_num function in the
+ * interrupt.
+ */
+int ec_get_event_num(void)
+{
+        int timeout = 100;
+        unsigned char value;
+        unsigned char status;
+
+        udelay(EC_REG_DELAY);
+        status = inb(EC_STS_PORT);
+        udelay(EC_REG_DELAY);
+        while (timeout-- && !(status & (1 << 0))) {
+                status = inb(EC_STS_PORT);
+                udelay(EC_REG_DELAY);
+        }
+        if (timeout <= 0) {
+                pr_info("%s: get event number timeout.\n", __func__);
+
+                return -EINVAL;
+        }
+        value = inb(EC_DAT_PORT);
+        udelay(EC_REG_DELAY);
+
+        return value;
+}
+EXPORT_SYMBOL(ec_get_event_num);
diff --git a/arch/mips/loongson/lemote-2f/ec_kb3310b.h b/arch/mips/loongson/lemote-2f/ec_kb3310b.h
new file mode 100644
index 000000000000..1595a21b315b
--- /dev/null
+++ b/arch/mips/loongson/lemote-2f/ec_kb3310b.h
@@ -0,0 +1,188 @@
+/*
+ * KB3310B Embedded Controller
+ *
+ *  Copyright (C) 2008 Lemote Inc.
+ *  Author: liujl <liujl@lemote.com>, 2008-03-14
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef _EC_KB3310B_H
+#define _EC_KB3310B_H
+
+extern unsigned char ec_read(unsigned short addr);
+extern void ec_write(unsigned short addr, unsigned char val);
+extern int ec_query_seq(unsigned char cmd);
+extern int ec_query_event_num(void);
+extern int ec_get_event_num(void);
+
+typedef int (*sci_handler) (int status);
+extern sci_handler yeeloong_report_lid_status;
+
+#define SCI_IRQ_NUM 0x0A
+
+/*
+ * The following registers are determined by the EC index configuration.
+ * 1, fill the PORT_HIGH as EC register high part.
+ * 2, fill the PORT_LOW as EC register low part.
+ * 3, fill the PORT_DATA as EC register write data or get the data from it.
+ */
+#define EC_IO_PORT_HIGH 0x0381
+#define EC_IO_PORT_LOW  0x0382
+#define EC_IO_PORT_DATA 0x0383
+
+/*
+ * EC delay time is 500us for register and status access
+ */
+#define EC_REG_DELAY    500     /* unit : us */
+#define EC_CMD_TIMEOUT  0x1000
+
+/*
+ * EC access port for SCI communication
+ */
+#define EC_CMD_PORT             0x66
+#define EC_STS_PORT             0x66
+#define EC_DAT_PORT             0x62
+#define CMD_INIT_IDLE_MODE      0xdd
+#define CMD_EXIT_IDLE_MODE      0xdf
+#define CMD_INIT_RESET_MODE     0xd8
+#define CMD_REBOOT_SYSTEM       0x8c
+#define CMD_GET_EVENT_NUM       0x84
+#define CMD_PROGRAM_PIECE       0xda
+
+/* temperature & fan registers */
+#define REG_TEMPERATURE_VALUE   0xF458
+#define REG_FAN_AUTO_MAN_SWITCH 0xF459
+#define BIT_FAN_AUTO            0
+#define BIT_FAN_MANUAL          1
+#define REG_FAN_CONTROL         0xF4D2
+#define BIT_FAN_CONTROL_ON      (1 << 0)
+#define BIT_FAN_CONTROL_OFF     (0 << 0)
+#define REG_FAN_STATUS          0xF4DA
+#define BIT_FAN_STATUS_ON       (1 << 0)
+#define BIT_FAN_STATUS_OFF      (0 << 0)
+#define REG_FAN_SPEED_HIGH      0xFE22
+#define REG_FAN_SPEED_LOW       0xFE23
+#define REG_FAN_SPEED_LEVEL     0xF4CC
+/* fan speed divider */
+#define FAN_SPEED_DIVIDER       480000  /* (60*1000*1000/62.5/2)*/
+
+/* battery registers */
+#define REG_BAT_DESIGN_CAP_HIGH         0xF77D
+#define REG_BAT_DESIGN_CAP_LOW          0xF77E
+#define REG_BAT_FULLCHG_CAP_HIGH        0xF780
+#define REG_BAT_FULLCHG_CAP_LOW         0xF781
+#define REG_BAT_DESIGN_VOL_HIGH         0xF782
+#define REG_BAT_DESIGN_VOL_LOW          0xF783
+#define REG_BAT_CURRENT_HIGH            0xF784
+#define REG_BAT_CURRENT_LOW             0xF785
+#define REG_BAT_VOLTAGE_HIGH            0xF786
+#define REG_BAT_VOLTAGE_LOW             0xF787
+#define REG_BAT_TEMPERATURE_HIGH        0xF788
+#define REG_BAT_TEMPERATURE_LOW         0xF789
+#define REG_BAT_RELATIVE_CAP_HIGH       0xF492
+#define REG_BAT_RELATIVE_CAP_LOW        0xF493
+#define REG_BAT_VENDOR                  0xF4C4
+#define FLAG_BAT_VENDOR_SANYO           0x01
+#define FLAG_BAT_VENDOR_SIMPLO          0x02
+#define REG_BAT_CELL_COUNT              0xF4C6
+#define FLAG_BAT_CELL_3S1P              0x03
+#define FLAG_BAT_CELL_3S2P              0x06
+#define REG_BAT_CHARGE                  0xF4A2
+#define FLAG_BAT_CHARGE_DISCHARGE       0x01
+#define FLAG_BAT_CHARGE_CHARGE          0x02
+#define FLAG_BAT_CHARGE_ACPOWER         0x00
+#define REG_BAT_STATUS                  0xF4B0
+#define BIT_BAT_STATUS_LOW              (1 << 5)
+#define BIT_BAT_STATUS_DESTROY          (1 << 2)
+#define BIT_BAT_STATUS_FULL             (1 << 1)
+#define BIT_BAT_STATUS_IN               (1 << 0)
+#define REG_BAT_CHARGE_STATUS           0xF4B1
+#define BIT_BAT_CHARGE_STATUS_OVERTEMP  (1 << 2)
+#define BIT_BAT_CHARGE_STATUS_PRECHG    (1 << 1)
+#define REG_BAT_STATE                   0xF482
+#define BIT_BAT_STATE_CHARGING          (1 << 1)
+#define BIT_BAT_STATE_DISCHARGING       (1 << 0)
+#define REG_BAT_POWER                   0xF440
+#define BIT_BAT_POWER_S3                (1 << 2)
+#define BIT_BAT_POWER_ON                (1 << 1)
+#define BIT_BAT_POWER_ACIN              (1 << 0)
+
+/* other registers */
+/* Audio: rd/wr */
+#define REG_AUDIO_VOLUME        0xF46C
+#define REG_AUDIO_MUTE          0xF4E7
+#define REG_AUDIO_BEEP          0xF4D0
+/* USB port power or not: rd/wr */
+#define REG_USB0_FLAG           0xF461
+#define REG_USB1_FLAG           0xF462
+#define REG_USB2_FLAG           0xF463
+#define BIT_USB_FLAG_ON         1
+#define BIT_USB_FLAG_OFF        0
+/* LID */
+#define REG_LID_DETECT          0xF4BD
+#define BIT_LID_DETECT_ON       1
+#define BIT_LID_DETECT_OFF      0
+/* CRT */
+#define REG_CRT_DETECT          0xF4AD
+#define BIT_CRT_DETECT_PLUG     1
+#define BIT_CRT_DETECT_UNPLUG   0
+/* LCD backlight brightness adjust: 9 levels */
+#define REG_DISPLAY_BRIGHTNESS  0xF4F5
+/* Black screen Status */
+#define BIT_DISPLAY_LCD_ON      1
+#define BIT_DISPLAY_LCD_OFF     0
+/* LCD backlight control: off/restore */
+#define REG_BACKLIGHT_CTRL      0xF7BD
+#define BIT_BACKLIGHT_ON        1
+#define BIT_BACKLIGHT_OFF       0
+/* Reset the machine auto-clear: rd/wr */
+#define REG_RESET               0xF4EC
+#define BIT_RESET_ON            1
+/* Light the led: rd/wr */
+#define REG_LED                 0xF4C8
+#define BIT_LED_RED_POWER       (1 << 0)
+#define BIT_LED_ORANGE_POWER    (1 << 1)
+#define BIT_LED_GREEN_CHARGE    (1 << 2)
+#define BIT_LED_RED_CHARGE      (1 << 3)
+#define BIT_LED_NUMLOCK         (1 << 4)
+/* Test led mode, all led on/off */
+#define REG_LED_TEST            0xF4C2
+#define BIT_LED_TEST_IN         1
+#define BIT_LED_TEST_OUT        0
+/* Camera on/off */
+#define REG_CAMERA_STATUS       0xF46A
+#define BIT_CAMERA_STATUS_ON    1
+#define BIT_CAMERA_STATUS_OFF   0
+#define REG_CAMERA_CONTROL      0xF7B7
+#define BIT_CAMERA_CONTROL_OFF  0
+#define BIT_CAMERA_CONTROL_ON   1
+/* Wlan Status */
+#define REG_WLAN                0xF4FA
+#define BIT_WLAN_ON             1
+#define BIT_WLAN_OFF            0
+#define REG_DISPLAY_LCD         0xF79F
+
+/* SCI Event Number from EC */
+enum {
+        EVENT_LID = 0x23,       /*  LID open/close */
+        EVENT_DISPLAY_TOGGLE,   /*  Fn+F3 for display switch */
+        EVENT_SLEEP,            /*  Fn+F1 for entering sleep mode */
+        EVENT_OVERTEMP,         /*  Over-temperature happened */
+        EVENT_CRT_DETECT,       /*  CRT is connected */
+        EVENT_CAMERA,           /*  Camera on/off */
+        EVENT_USB_OC2,          /*  USB2 Over Current occurred */
+        EVENT_USB_OC0,          /*  USB0 Over Current occurred */
+        EVENT_BLACK_SCREEN,     /*  Turn on/off backlight */
+        EVENT_AUDIO_MUTE,       /*  Mute on/off */
+        EVENT_DISPLAY_BRIGHTNESS,/* LCD backlight brightness adjust */
+        EVENT_AC_BAT,           /*  AC & Battery relative issue */
+        EVENT_AUDIO_VOLUME,     /*  Volume adjust */
+        EVENT_WLAN,             /*  Wlan on/off */
+        EVENT_END
+};
+
+#endif /* !_EC_KB3310B_H */
diff --git a/arch/mips/loongson/lemote-2f/irq.c b/arch/mips/loongson/lemote-2f/irq.c
new file mode 100644
index 000000000000..77d32f9cf31e
--- /dev/null
+++ b/arch/mips/loongson/lemote-2f/irq.c
@@ -0,0 +1,134 @@
+/*
+ * Copyright (C) 2007 Lemote Inc.
+ * Author: Fuxin Zhang, zhangfx@lemote.com
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ */
+
+#include <linux/interrupt.h>
+#include <linux/module.h>
+
+#include <asm/irq_cpu.h>
+#include <asm/i8259.h>
+#include <asm/mipsregs.h>
+
+#include <loongson.h>
+#include <machine.h>
+
+#define LOONGSON_TIMER_IRQ      (MIPS_CPU_IRQ_BASE + 7) /* cpu timer */
+#define LOONGSON_PERFCNT_IRQ    (MIPS_CPU_IRQ_BASE + 6) /* cpu perf counter */
+#define LOONGSON_NORTH_BRIDGE_IRQ       (MIPS_CPU_IRQ_BASE + 6) /* bonito */
+#define LOONGSON_UART_IRQ       (MIPS_CPU_IRQ_BASE + 3) /* cpu serial port */
+#define LOONGSON_SOUTH_BRIDGE_IRQ       (MIPS_CPU_IRQ_BASE + 2) /* i8259 */
+
+#define LOONGSON_INT_BIT_INT0           (1 << 11)
+#define LOONGSON_INT_BIT_INT1           (1 << 12)
+
+/*
+ * The generic i8259_irq() make the kernel hang on booting.  Since we cannot
+ * get the irq via the IRR directly, we access the ISR instead.
+ */
+int mach_i8259_irq(void)
+{
+        int irq, isr;
+
+        irq = -1;
+
+        if ((LOONGSON_INTISR & LOONGSON_INTEN) & LOONGSON_INT_BIT_INT0) {
+                spin_lock(&i8259A_lock);
+                isr = inb(PIC_MASTER_CMD) &
+                        ~inb(PIC_MASTER_IMR) & ~(1 << PIC_CASCADE_IR);
+                if (!isr)
+                        isr = (inb(PIC_SLAVE_CMD) & ~inb(PIC_SLAVE_IMR)) << 8;
+                irq = ffs(isr) - 1;
+                if (unlikely(irq == 7)) {
+                        /*
+                         * This may be a spurious interrupt.
+                         *
+                         * Read the interrupt status register (ISR). If the most
+                         * significant bit is not set then there is no valid
+                         * interrupt.
+                         */
+                        outb(0x0B, PIC_MASTER_ISR);     /* ISR register */
+                        if (~inb(PIC_MASTER_ISR) & 0x80)
+                                irq = -1;
+                }
+                spin_unlock(&i8259A_lock);
+        }
+
+        return irq;
+}
+EXPORT_SYMBOL(mach_i8259_irq);
+
+static void i8259_irqdispatch(void)
+{
+        int irq;
+
+        irq = mach_i8259_irq();
+        if (irq >= 0)
+                do_IRQ(irq);
+        else
+                spurious_interrupt();
+}
+
+void mach_irq_dispatch(unsigned int pending)
+{
+        if (pending & CAUSEF_IP7)
+                do_IRQ(LOONGSON_TIMER_IRQ);
+        else if (pending & CAUSEF_IP6) {        /* North Bridge, Perf counter */
+#ifdef CONFIG_OPROFILE
+                do_IRQ(LOONGSON2_PERFCNT_IRQ);
+#endif
+                bonito_irqdispatch();
+        } else if (pending & CAUSEF_IP3)        /* CPU UART */
+                do_IRQ(LOONGSON_UART_IRQ);
+        else if (pending & CAUSEF_IP2)  /* South Bridge */
+                i8259_irqdispatch();
+        else
+                spurious_interrupt();
+}
+
+void __init set_irq_trigger_mode(void)
+{
+        /* setup cs5536 as high level trigger */
+        LOONGSON_INTPOL = LOONGSON_INT_BIT_INT0 | LOONGSON_INT_BIT_INT1;
+        LOONGSON_INTEDGE &= ~(LOONGSON_INT_BIT_INT0 | LOONGSON_INT_BIT_INT1);
+}
+
+static irqreturn_t ip6_action(int cpl, void *dev_id)
+{
+        return IRQ_HANDLED;
+}
+
+struct irqaction ip6_irqaction = {
+        .handler = ip6_action,
+        .name = "cascade",
+        .flags = IRQF_SHARED,
+};
+
+struct irqaction cascade_irqaction = {
+        .handler = no_action,
+        .name = "cascade",
+};
+
+void __init mach_init_irq(void)
+{
+        /* init all controller
+         *   0-15         ------> i8259 interrupt
+         *   16-23        ------> mips cpu interrupt
+         *   32-63        ------> bonito irq
+         */
+
+        /* Sets the first-level interrupt dispatcher. */
+        mips_cpu_irq_init();
+        init_i8259_irqs();
+        bonito_irq_init();
+
+        /* setup north bridge irq (bonito) */
+        setup_irq(LOONGSON_NORTH_BRIDGE_IRQ, &ip6_irqaction);
+        /* setup source bridge irq (i8259) */
+        setup_irq(LOONGSON_SOUTH_BRIDGE_IRQ, &cascade_irqaction);
+}
diff --git a/arch/mips/loongson/lemote-2f/pm.c b/arch/mips/loongson/lemote-2f/pm.c
new file mode 100644
index 000000000000..d7af2e616592
--- /dev/null
+++ b/arch/mips/loongson/lemote-2f/pm.c
@@ -0,0 +1,149 @@
+/*
+ *  Lemote loongson2f family machines' specific suspend support
+ *
+ *  Copyright (C) 2009 Lemote Inc.
+ *  Author: Wu Zhangjin <wuzj@lemote.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <linux/suspend.h>
+#include <linux/interrupt.h>
+#include <linux/pm.h>
+#include <linux/i8042.h>
+#include <linux/module.h>
+
+#include <asm/i8259.h>
+#include <asm/mipsregs.h>
+#include <asm/bootinfo.h>
+
+#include <loongson.h>
+
+#include <cs5536/cs5536_mfgpt.h>
+#include "ec_kb3310b.h"
+
+#define I8042_KBD_IRQ           1
+#define I8042_CTR_KBDINT        0x01
+#define I8042_CTR_KBDDIS        0x10
+
+static unsigned char i8042_ctr;
+
+static int i8042_enable_kbd_port(void)
+{
+        if (i8042_command(&i8042_ctr, I8042_CMD_CTL_RCTR)) {
+                pr_err("i8042.c: Can't read CTR while enabling i8042 kbd port."
+                       "\n");
+                return -EIO;
+        }
+
+        i8042_ctr &= ~I8042_CTR_KBDDIS;
+        i8042_ctr |= I8042_CTR_KBDINT;
+
+        if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) {
+                i8042_ctr &= ~I8042_CTR_KBDINT;
+                i8042_ctr |= I8042_CTR_KBDDIS;
+                pr_err("i8042.c: Failed to enable KBD port.\n");
+
+                return -EIO;
+        }
+
+        return 0;
+}
+
+void setup_wakeup_events(void)
+{
+        int irq_mask;
+
+        switch (mips_machtype) {
+        case MACH_LEMOTE_ML2F7:
+        case MACH_LEMOTE_YL2F89:
+                /* open the keyboard irq in i8259A */
+                outb((0xff & ~(1 << I8042_KBD_IRQ)), PIC_MASTER_IMR);
+                irq_mask = inb(PIC_MASTER_IMR);
+
+                /* enable keyboard port */
+                i8042_enable_kbd_port();
+
+                /* Wakeup CPU via SCI lid open event */
+                outb(irq_mask & ~(1 << PIC_CASCADE_IR), PIC_MASTER_IMR);
+                inb(PIC_MASTER_IMR);
+                outb(0xff & ~(1 << (SCI_IRQ_NUM - 8)), PIC_SLAVE_IMR);
+                inb(PIC_SLAVE_IMR);
+
+                break;
+
+        default:
+                break;
+        }
+}
+
+static struct delayed_work lid_task;
+static int initialized;
+/* yeeloong_report_lid_status will be implemented in yeeloong_laptop.c */
+sci_handler yeeloong_report_lid_status;
+EXPORT_SYMBOL(yeeloong_report_lid_status);
+static void yeeloong_lid_update_task(struct work_struct *work)
+{
+        if (yeeloong_report_lid_status)
+                yeeloong_report_lid_status(BIT_LID_DETECT_ON);
+}
+
+int wakeup_loongson(void)
+{
+        int irq;
+
+        /* query the interrupt number */
+        irq = mach_i8259_irq();
+        if (irq < 0)
+                return 0;
+
+        printk(KERN_INFO "%s: irq = %d\n", __func__, irq);
+
+        if (irq == I8042_KBD_IRQ)
+                return 1;
+        else if (irq == SCI_IRQ_NUM) {
+                int ret, sci_event;
+                /* query the event number */
+                ret = ec_query_seq(CMD_GET_EVENT_NUM);
+                if (ret < 0)
+                        return 0;
+                sci_event = ec_get_event_num();
+                if (sci_event < 0)
+                        return 0;
+                if (sci_event == EVENT_LID) {
+                        int lid_status;
+                        /* check the LID status */
+                        lid_status = ec_read(REG_LID_DETECT);
+                        /* wakeup cpu when people open the LID */
+                        if (lid_status == BIT_LID_DETECT_ON) {
+                                /* If we call it directly here, the WARNING
+                                 * will be sent out by getnstimeofday
+                                 * via "WARN_ON(timekeeping_suspended);"
+                                 * because we can not schedule in suspend mode.
+                                 */
+                                if (initialized == 0) {
+                                        INIT_DELAYED_WORK(&lid_task,
+                                                yeeloong_lid_update_task);
+                                        initialized = 1;
+                                }
+                                schedule_delayed_work(&lid_task, 1);
+                                return 1;
+                        }
+                }
+        }
+
+        return 0;
+}
+
+void __weak mach_suspend(void)
+{
+        disable_mfgpt0_counter();
+}
+
+void __weak mach_resume(void)
+{
+        enable_mfgpt0_counter();
+}
diff --git a/arch/mips/loongson/lemote-2f/reset.c b/arch/mips/loongson/lemote-2f/reset.c
new file mode 100644
index 000000000000..51d1a60d5349
--- /dev/null
+++ b/arch/mips/loongson/lemote-2f/reset.c
@@ -0,0 +1,159 @@
+/* Board-specific reboot/shutdown routines
+ *
+ * Copyright (c) 2009 Philippe Vachon <philippe@cowpig.ca>
+ *
+ * Copyright (C) 2009 Lemote Inc.
+ * Author: Wu Zhangjin, wuzj@lemote.com
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/io.h>
+#include <linux/delay.h>
+#include <linux/types.h>
+
+#include <asm/bootinfo.h>
+
+#include <loongson.h>
+
+#include <cs5536/cs5536.h>
+#include "ec_kb3310b.h"
+
+static void reset_cpu(void)
+{
+        /*
+         * reset cpu to full speed, this is needed when enabling cpu frequency
+         * scalling
+         */
+        LOONGSON_CHIPCFG0 |= 0x7;
+}
+
+/* reset support for fuloong2f */
+
+static void fl2f_reboot(void)
+{
+        reset_cpu();
+
+        /* send a reset signal to south bridge.
+         *
+         * NOTE: if enable "Power Management" in kernel, rtl8169 will not reset
+         * normally with this reset operation and it will not work in PMON, but
+         * you can type halt command and then reboot, seems the hardware reset
+         * logic not work normally.
+         */
+        {
+                u32 hi, lo;
+                _rdmsr(DIVIL_MSR_REG(DIVIL_SOFT_RESET), &hi, &lo);
+                lo |= 0x00000001;
+                _wrmsr(DIVIL_MSR_REG(DIVIL_SOFT_RESET), hi, lo);
+        }
+}
+
+static void fl2f_shutdown(void)
+{
+        u32 hi, lo, val;
+        int gpio_base;
+
+        /* get gpio base */
+        _rdmsr(DIVIL_MSR_REG(DIVIL_LBAR_GPIO), &hi, &lo);
+        gpio_base = lo & 0xff00;
+
+        /* make cs5536 gpio13 output enable */
+        val = inl(gpio_base + GPIOL_OUT_EN);
+        val &= ~(1 << (16 + 13));
+        val |= (1 << 13);
+        outl(val, gpio_base + GPIOL_OUT_EN);
+        mmiowb();
+        /* make cs5536 gpio13 output low level voltage. */
+        val = inl(gpio_base + GPIOL_OUT_VAL) & ~(1 << (13));
+        val |= (1 << (16 + 13));
+        outl(val, gpio_base + GPIOL_OUT_VAL);
+        mmiowb();
+}
+
+/* reset support for yeeloong2f and mengloong2f notebook */
+
+void ml2f_reboot(void)
+{
+        reset_cpu();
+
+        /* sending an reset signal to EC(embedded controller) */
+        ec_write(REG_RESET, BIT_RESET_ON);
+}
+
+#define yl2f89_reboot ml2f_reboot
+
+/* menglong(7inches) laptop has different shutdown logic from 8.9inches */
+#define EC_SHUTDOWN_IO_PORT_HIGH 0xff2d
+#define EC_SHUTDOWN_IO_PORT_LOW  0xff2e
+#define EC_SHUTDOWN_IO_PORT_DATA 0xff2f
+#define REG_SHUTDOWN_HIGH        0xFC
+#define REG_SHUTDOWN_LOW         0x29
+#define BIT_SHUTDOWN_ON          (1 << 1)
+
+static void ml2f_shutdown(void)
+{
+        u8 val;
+        u64 i;
+
+        outb(REG_SHUTDOWN_HIGH, EC_SHUTDOWN_IO_PORT_HIGH);
+        outb(REG_SHUTDOWN_LOW, EC_SHUTDOWN_IO_PORT_LOW);
+        mmiowb();
+        val = inb(EC_SHUTDOWN_IO_PORT_DATA);
+        outb(val & (~BIT_SHUTDOWN_ON), EC_SHUTDOWN_IO_PORT_DATA);
+        mmiowb();
+        /* need enough wait here... how many microseconds needs? */
+        for (i = 0; i < 0x10000; i++)
+                delay();
+        outb(val | BIT_SHUTDOWN_ON, EC_SHUTDOWN_IO_PORT_DATA);
+        mmiowb();
+}
+
+static void yl2f89_shutdown(void)
+{
+        /* cpu-gpio0 output low */
+        LOONGSON_GPIODATA &= ~0x00000001;
+        /* cpu-gpio0 as output */
+        LOONGSON_GPIOIE &= ~0x00000001;
+}
+
+void mach_prepare_reboot(void)
+{
+        switch (mips_machtype) {
+        case MACH_LEMOTE_FL2F:
+        case MACH_LEMOTE_NAS:
+        case MACH_LEMOTE_LL2F:
+                fl2f_reboot();
+                break;
+        case MACH_LEMOTE_ML2F7:
+                ml2f_reboot();
+                break;
+        case MACH_LEMOTE_YL2F89:
+                yl2f89_reboot();
+                break;
+        default:
+                break;
+        }
+}
+
+void mach_prepare_shutdown(void)
+{
+        switch (mips_machtype) {
+        case MACH_LEMOTE_FL2F:
+        case MACH_LEMOTE_NAS:
+        case MACH_LEMOTE_LL2F:
+                fl2f_shutdown();
+                break;
+        case MACH_LEMOTE_ML2F7:
+                ml2f_shutdown();
+                break;
+        case MACH_LEMOTE_YL2F89:
+                yl2f89_shutdown();
+                break;
+        default:
+                break;
+        }
+}
diff --git a/arch/mips/math-emu/cp1emu.c b/arch/mips/math-emu/cp1emu.c
index 454b53924490..8f2f8e9d8b21 100644
--- a/arch/mips/math-emu/cp1emu.c
+++ b/arch/mips/math-emu/cp1emu.c
@@ -35,6 +35,7 @@
  * better performance by compiling with -msoft-float!
  */
 #include <linux/sched.h>
+#include <linux/module.h>
 #include <linux/debugfs.h>
 
 #include <asm/inst.h>
@@ -68,7 +69,9 @@ static int fpux_emu(struct pt_regs *,
 
 /* Further private data for which no space exists in mips_fpu_struct */
 
-struct mips_fpu_emulator_stats fpuemustats;
+#ifdef CONFIG_DEBUG_FS
+DEFINE_PER_CPU(struct mips_fpu_emulator_stats, fpuemustats);
+#endif
 
 /* Control registers */
 
@@ -209,7 +212,7 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx)
         unsigned int cond;
 
         if (get_user(ir, (mips_instruction __user *) xcp->cp0_epc)) {
-                fpuemustats.errors++;
+                MIPS_FPU_EMU_INC_STATS(errors);
                 return SIGBUS;
         }
 
@@ -240,7 +243,7 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx)
                         return SIGILL;
                 }
                 if (get_user(ir, (mips_instruction __user *) emulpc)) {
-                        fpuemustats.errors++;
+                        MIPS_FPU_EMU_INC_STATS(errors);
                         return SIGBUS;
                 }
                 /* __compute_return_epc() will have updated cp0_epc */
@@ -253,16 +256,16 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx)
         }
 
       emul:
-        fpuemustats.emulated++;
+        MIPS_FPU_EMU_INC_STATS(emulated);
         switch (MIPSInst_OPCODE(ir)) {
         case ldc1_op:{
                 u64 __user *va = (u64 __user *) (xcp->regs[MIPSInst_RS(ir)] +
                         MIPSInst_SIMM(ir));
                 u64 val;
 
-                fpuemustats.loads++;
+                MIPS_FPU_EMU_INC_STATS(loads);
                 if (get_user(val, va)) {
-                        fpuemustats.errors++;
+                        MIPS_FPU_EMU_INC_STATS(errors);
                         return SIGBUS;
                 }
                 DITOREG(val, MIPSInst_RT(ir));
@@ -274,10 +277,10 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx)
                         MIPSInst_SIMM(ir));
                 u64 val;
 
-                fpuemustats.stores++;
+                MIPS_FPU_EMU_INC_STATS(stores);
                 DIFROMREG(val, MIPSInst_RT(ir));
                 if (put_user(val, va)) {
-                        fpuemustats.errors++;
+                        MIPS_FPU_EMU_INC_STATS(errors);
                         return SIGBUS;
                 }
                 break;
@@ -288,9 +291,9 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx)
                         MIPSInst_SIMM(ir));
                 u32 val;
 
-                fpuemustats.loads++;
+                MIPS_FPU_EMU_INC_STATS(loads);
                 if (get_user(val, va)) {
-                        fpuemustats.errors++;
+                        MIPS_FPU_EMU_INC_STATS(errors);
                         return SIGBUS;
                 }
                 SITOREG(val, MIPSInst_RT(ir));
@@ -302,10 +305,10 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx)
                         MIPSInst_SIMM(ir));
                 u32 val;
 
-                fpuemustats.stores++;
+                MIPS_FPU_EMU_INC_STATS(stores);
                 SIFROMREG(val, MIPSInst_RT(ir));
                 if (put_user(val, va)) {
-                        fpuemustats.errors++;
+                        MIPS_FPU_EMU_INC_STATS(errors);
                         return SIGBUS;
                 }
                 break;
@@ -429,7 +432,7 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx)
 
                                 if (get_user(ir,
                                     (mips_instruction __user *) xcp->cp0_epc)) {
-                                        fpuemustats.errors++;
+                                        MIPS_FPU_EMU_INC_STATS(errors);
                                         return SIGBUS;
                                 }
 
@@ -595,7 +598,7 @@ static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
 {
         unsigned rcsr = 0;      /* resulting csr */
 
-        fpuemustats.cp1xops++;
+        MIPS_FPU_EMU_INC_STATS(cp1xops);
 
         switch (MIPSInst_FMA_FFMT(ir)) {
         case s_fmt:{            /* 0 */
@@ -610,9 +613,9 @@ static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
                         va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
                                 xcp->regs[MIPSInst_FT(ir)]);
 
-                        fpuemustats.loads++;
+                        MIPS_FPU_EMU_INC_STATS(loads);
                         if (get_user(val, va)) {
-                                fpuemustats.errors++;
+                                MIPS_FPU_EMU_INC_STATS(errors);
                                 return SIGBUS;
                         }
                         SITOREG(val, MIPSInst_FD(ir));
@@ -622,11 +625,11 @@ static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
                         va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
                                 xcp->regs[MIPSInst_FT(ir)]);
 
-                        fpuemustats.stores++;
+                        MIPS_FPU_EMU_INC_STATS(stores);
 
                         SIFROMREG(val, MIPSInst_FS(ir));
                         if (put_user(val, va)) {
-                                fpuemustats.errors++;
+                                MIPS_FPU_EMU_INC_STATS(errors);
                                 return SIGBUS;
                         }
                         break;
@@ -687,9 +690,9 @@ static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
                         va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
                                 xcp->regs[MIPSInst_FT(ir)]);
 
-                        fpuemustats.loads++;
+                        MIPS_FPU_EMU_INC_STATS(loads);
                         if (get_user(val, va)) {
-                                fpuemustats.errors++;
+                                MIPS_FPU_EMU_INC_STATS(errors);
                                 return SIGBUS;
                         }
                         DITOREG(val, MIPSInst_FD(ir));
@@ -699,10 +702,10 @@ static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
                         va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
                                 xcp->regs[MIPSInst_FT(ir)]);
 
-                        fpuemustats.stores++;
+                        MIPS_FPU_EMU_INC_STATS(stores);
                         DIFROMREG(val, MIPSInst_FS(ir));
                         if (put_user(val, va)) {
-                                fpuemustats.errors++;
+                                MIPS_FPU_EMU_INC_STATS(errors);
                                 return SIGBUS;
                         }
                         break;
@@ -769,7 +772,7 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
 #endif
         } rv;                   /* resulting value */
 
-        fpuemustats.cp1ops++;
+        MIPS_FPU_EMU_INC_STATS(cp1ops);
         switch (rfmt = (MIPSInst_FFMT(ir) & 0xf)) {
         case s_fmt:{            /* 0 */
                 union {
@@ -1240,7 +1243,7 @@ int fpu_emulator_cop1Handler(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
                 prevepc = xcp->cp0_epc;
 
                 if (get_user(insn, (mips_instruction __user *) xcp->cp0_epc)) {
-                        fpuemustats.errors++;
+                        MIPS_FPU_EMU_INC_STATS(errors);
                         return SIGBUS;
                 }
                 if (insn == 0)
@@ -1276,33 +1279,50 @@ int fpu_emulator_cop1Handler(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
 }
 
 #ifdef CONFIG_DEBUG_FS
+
+static int fpuemu_stat_get(void *data, u64 *val)
+{
+        int cpu;
+        unsigned long sum = 0;
+        for_each_online_cpu(cpu) {
+                struct mips_fpu_emulator_stats *ps;
+                local_t *pv;
+                ps = &per_cpu(fpuemustats, cpu);
+                pv = (void *)ps + (unsigned long)data;
+                sum += local_read(pv);
+        }
+        *val = sum;
+        return 0;
+}
+DEFINE_SIMPLE_ATTRIBUTE(fops_fpuemu_stat, fpuemu_stat_get, NULL, "%llu\n");
+
 extern struct dentry *mips_debugfs_dir;
 static int __init debugfs_fpuemu(void)
 {
         struct dentry *d, *dir;
-        int i;
-        static struct {
-                const char *name;
-                unsigned int *v;
-        } vars[] __initdata = {
-                { "emulated", &fpuemustats.emulated },
-                { "loads",    &fpuemustats.loads },
-                { "stores",   &fpuemustats.stores },
-                { "cp1ops",   &fpuemustats.cp1ops },
-                { "cp1xops",  &fpuemustats.cp1xops },
-                { "errors",   &fpuemustats.errors },
-        };
 
         if (!mips_debugfs_dir)
                 return -ENODEV;
         dir = debugfs_create_dir("fpuemustats", mips_debugfs_dir);
         if (!dir)
                 return -ENOMEM;
-        for (i = 0; i < ARRAY_SIZE(vars); i++) {
-                d = debugfs_create_u32(vars[i].name, S_IRUGO, dir, vars[i].v);
-                if (!d)
-                        return -ENOMEM;
-        }
+
+#define FPU_STAT_CREATE(M)                                              \
+        do {                                                            \
+                d = debugfs_create_file(#M , S_IRUGO, dir,              \
+                        (void *)offsetof(struct mips_fpu_emulator_stats, M), \
+                        &fops_fpuemu_stat);                             \
+                if (!d)                                                 \
+                        return -ENOMEM;                                 \
+        } while (0)
+
+        FPU_STAT_CREATE(emulated);
+        FPU_STAT_CREATE(loads);
+        FPU_STAT_CREATE(stores);
+        FPU_STAT_CREATE(cp1ops);
+        FPU_STAT_CREATE(cp1xops);
+        FPU_STAT_CREATE(errors);
+
         return 0;
 }
 __initcall(debugfs_fpuemu);
diff --git a/arch/mips/math-emu/dsemul.c b/arch/mips/math-emu/dsemul.c
index df7b9d928efc..36d975ae08f8 100644
--- a/arch/mips/math-emu/dsemul.c
+++ b/arch/mips/math-emu/dsemul.c
@@ -98,7 +98,7 @@ int mips_dsemul(struct pt_regs *regs, mips_instruction ir, unsigned long cpc)
         err |= __put_user(cpc, &fr->epc);
 
         if (unlikely(err)) {
-                fpuemustats.errors++;
+                MIPS_FPU_EMU_INC_STATS(errors);
                 return SIGBUS;
         }
 
@@ -136,7 +136,7 @@ int do_dsemulret(struct pt_regs *xcp)
         err |= __get_user(cookie, &fr->cookie);
 
         if (unlikely(err || (insn != BREAK_MATH) || (cookie != BD_COOKIE))) {
-                fpuemustats.errors++;
+                MIPS_FPU_EMU_INC_STATS(errors);
                 return 0;
         }
 
diff --git a/arch/mips/mipssim/Makefile b/arch/mips/mipssim/Makefile
index 57f43c1c7882..41b96571315e 100644
--- a/arch/mips/mipssim/Makefile
+++ b/arch/mips/mipssim/Makefile
@@ -17,8 +17,7 @@
 # 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
 #
 
-obj-y := sim_platform.o sim_setup.o sim_mem.o sim_time.o sim_int.o \
-         sim_cmdline.o
+obj-y := sim_platform.o sim_setup.o sim_mem.o sim_time.o sim_int.o
 
 obj-$(CONFIG_EARLY_PRINTK) += sim_console.o
 obj-$(CONFIG_MIPS_MT_SMTC) += sim_smtc.o
diff --git a/arch/mips/mipssim/sim_setup.c b/arch/mips/mipssim/sim_setup.c
index 2877675c5f0d..0824f6af4777 100644
--- a/arch/mips/mipssim/sim_setup.c
+++ b/arch/mips/mipssim/sim_setup.c
@@ -61,7 +61,6 @@ void __init prom_init(void)
         set_io_port_base(0xbfd00000);
 
         pr_info("\nLINUX started...\n");
-        prom_init_cmdline();
         prom_meminit();
 
 #ifdef CONFIG_MIPS_MT_SMP
diff --git a/arch/mips/mm/cache.c b/arch/mips/mm/cache.c
index 694d51f523d1..102b2dfa542a 100644
--- a/arch/mips/mm/cache.c
+++ b/arch/mips/mm/cache.c
@@ -194,7 +194,7 @@ void __devinit cpu_cache_init(void)
 
 int __weak __uncached_access(struct file *file, unsigned long addr)
 {
-        if (file->f_flags & O_SYNC)
+        if (file->f_flags & O_DSYNC)
                 return 1;
 
         return addr >= __pa(high_memory);
diff --git a/arch/mips/mm/cerr-sb1.c b/arch/mips/mm/cerr-sb1.c
index 1bd1f18ac23c..3571090ba178 100644
--- a/arch/mips/mm/cerr-sb1.c
+++ b/arch/mips/mm/cerr-sb1.c
@@ -567,13 +567,10 @@ static uint32_t extract_dc(unsigned short addr, int data)
                                 datalo = ((unsigned long long)datalohi << 32) | datalolo;
                                 ecc = dc_ecc(datalo);
                                 if (ecc != datahi) {
-                                        int bits = 0;
+                                        int bits;
                                         bad_ecc |= 1 << (3-offset);
                                         ecc ^= datahi;
-                                        while (ecc) {
-                                                if (ecc & 1) bits++;
-                                                ecc >>= 1;
-                                        }
+                                        bits = hweight8(ecc);
                                         res |= (bits == 1) ? CP0_CERRD_DATA_SBE : CP0_CERRD_DATA_DBE;
                                 }
                                 printk("  %02X-%016llX", datahi, datalo);
diff --git a/arch/mips/mm/init.c b/arch/mips/mm/init.c
index 8d1f4f363049..9e8d00389eef 100644
--- a/arch/mips/mm/init.c
+++ b/arch/mips/mm/init.c
@@ -462,7 +462,9 @@ void __init_refok free_initmem(void)
                         __pa_symbol(&__init_end));
 }
 
+#ifndef CONFIG_MIPS_PGD_C0_CONTEXT
 unsigned long pgd_current[NR_CPUS];
+#endif
 /*
  * On 64-bit we've got three-level pagetables with a slightly
  * different layout ...
diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c
index bb1719a55d22..3d0baa4a842d 100644
--- a/arch/mips/mm/tlbex.c
+++ b/arch/mips/mm/tlbex.c
@@ -160,6 +160,12 @@ static u32 tlb_handler[128] __cpuinitdata;
 static struct uasm_label labels[128] __cpuinitdata;
 static struct uasm_reloc relocs[128] __cpuinitdata;
 
+#ifndef CONFIG_MIPS_PGD_C0_CONTEXT
+/*
+ * CONFIG_MIPS_PGD_C0_CONTEXT implies 64 bit and lack of pgd_current,
+ * we cannot do r3000 under these circumstances.
+ */
+
 /*
  * The R3000 TLB handler is simple.
  */
@@ -199,6 +205,7 @@ static void __cpuinit build_r3000_tlb_refill_handler(void)
 
         dump_handler((u32 *)ebase, 32);
 }
+#endif /* CONFIG_MIPS_PGD_C0_CONTEXT */
 
 /*
  * The R4000 TLB handler is much more complicated. We have two
@@ -497,8 +504,9 @@ static void __cpuinit
 build_get_pmde64(u32 **p, struct uasm_label **l, struct uasm_reloc **r,
                  unsigned int tmp, unsigned int ptr)
 {
+#ifndef CONFIG_MIPS_PGD_C0_CONTEXT
         long pgdc = (long)pgd_current;
-
+#endif
         /*
          * The vmalloc handling is not in the hotpath.
          */
@@ -506,7 +514,15 @@ build_get_pmde64(u32 **p, struct uasm_label **l, struct uasm_reloc **r,
         uasm_il_bltz(p, r, tmp, label_vmalloc);
         /* No uasm_i_nop needed here, since the next insn doesn't touch TMP. */
 
-#ifdef CONFIG_SMP
+#ifdef CONFIG_MIPS_PGD_C0_CONTEXT
+        /*
+         * &pgd << 11 stored in CONTEXT [23..63].
+         */
+        UASM_i_MFC0(p, ptr, C0_CONTEXT);
+        uasm_i_dins(p, ptr, 0, 0, 23); /* Clear lower 23 bits of context. */
+        uasm_i_ori(p, ptr, ptr, 0x540); /* 1 0  1 0 1  << 6  xkphys cached */
+        uasm_i_drotr(p, ptr, ptr, 11);
+#elif defined(CONFIG_SMP)
 # ifdef  CONFIG_MIPS_MT_SMTC
         /*
          * SMTC uses TCBind value as "CPU" index
@@ -520,7 +536,7 @@ build_get_pmde64(u32 **p, struct uasm_label **l, struct uasm_reloc **r,
          */
         uasm_i_dmfc0(p, ptr, C0_CONTEXT);
         uasm_i_dsrl(p, ptr, ptr, 23);
-#endif
+# endif
         UASM_i_LA_mostly(p, tmp, pgdc);
         uasm_i_daddu(p, ptr, ptr, tmp);
         uasm_i_dmfc0(p, tmp, C0_BADVADDR);
@@ -1033,6 +1049,7 @@ build_pte_modifiable(u32 **p, struct uasm_reloc **r,
         iPTE_LW(p, pte, ptr);
 }
 
+#ifndef CONFIG_MIPS_PGD_C0_CONTEXT
 /*
  * R3000 style TLB load/store/modify handlers.
  */
@@ -1184,6 +1201,7 @@ static void __cpuinit build_r3000_tlb_modify_handler(void)
 
         dump_handler(handle_tlbm, ARRAY_SIZE(handle_tlbm));
 }
+#endif /* CONFIG_MIPS_PGD_C0_CONTEXT */
 
 /*
  * R4000 style TLB load/store/modify handlers.
@@ -1400,6 +1418,7 @@ void __cpuinit build_tlb_refill_handler(void)
         case CPU_TX3912:
         case CPU_TX3922:
         case CPU_TX3927:
+#ifndef CONFIG_MIPS_PGD_C0_CONTEXT
                 build_r3000_tlb_refill_handler();
                 if (!run_once) {
                         build_r3000_tlb_load_handler();
@@ -1407,6 +1426,9 @@ void __cpuinit build_tlb_refill_handler(void)
                         build_r3000_tlb_modify_handler();
                         run_once++;
                 }
+#else
+                panic("No R3000 TLB refill handler");
+#endif
                 break;
 
         case CPU_R6000:
diff --git a/arch/mips/mm/uasm.c b/arch/mips/mm/uasm.c
index f467199676a8..0a165c5179a1 100644
--- a/arch/mips/mm/uasm.c
+++ b/arch/mips/mm/uasm.c
@@ -60,11 +60,11 @@ enum opcode {
         insn_beql, insn_bgez, insn_bgezl, insn_bltz, insn_bltzl,
         insn_bne, insn_cache, insn_daddu, insn_daddiu, insn_dmfc0,
         insn_dmtc0, insn_dsll, insn_dsll32, insn_dsra, insn_dsrl,
-        insn_dsrl32, insn_dsubu, insn_eret, insn_j, insn_jal, insn_jr,
-        insn_ld, insn_ll, insn_lld, insn_lui, insn_lw, insn_mfc0,
+        insn_dsrl32, insn_drotr, insn_dsubu, insn_eret, insn_j, insn_jal,
+        insn_jr, insn_ld, insn_ll, insn_lld, insn_lui, insn_lw, insn_mfc0,
         insn_mtc0, insn_ori, insn_pref, insn_rfe, insn_sc, insn_scd,
         insn_sd, insn_sll, insn_sra, insn_srl, insn_subu, insn_sw,
-        insn_tlbp, insn_tlbwi, insn_tlbwr, insn_xor, insn_xori
+        insn_tlbp, insn_tlbwi, insn_tlbwr, insn_xor, insn_xori, insn_dins
 };
 
 struct insn {
@@ -104,6 +104,7 @@ static struct insn insn_table[] __cpuinitdata = {
         { insn_dsra, M(spec_op, 0, 0, 0, 0, dsra_op), RT | RD | RE },
         { insn_dsrl, M(spec_op, 0, 0, 0, 0, dsrl_op), RT | RD | RE },
         { insn_dsrl32, M(spec_op, 0, 0, 0, 0, dsrl32_op), RT | RD | RE },
+        { insn_drotr, M(spec_op, 1, 0, 0, 0, dsrl_op), RT | RD | RE },
         { insn_dsubu, M(spec_op, 0, 0, 0, 0, dsubu_op), RS | RT | RD },
         { insn_eret,  M(cop0_op, cop_op, 0, 0, 0, eret_op),  0 },
         { insn_j,  M(j_op, 0, 0, 0, 0, 0),  JIMM },
@@ -132,6 +133,7 @@ static struct insn insn_table[] __cpuinitdata = {
         { insn_tlbwr,  M(cop0_op, cop_op, 0, 0, 0, tlbwr_op),  0 },
         { insn_xor,  M(spec_op, 0, 0, 0, 0, xor_op),  RS | RT | RD },
         { insn_xori,  M(xori_op, 0, 0, 0, 0, 0),  RS | RT | UIMM },
+        { insn_dins, M(spec3_op, 0, 0, 0, 0, dins_op), RS | RT | RD | RE },
         { insn_invalid, 0, 0 }
 };
 
@@ -304,6 +306,12 @@ Ip_u2u1s3(op)						\
         build_insn(buf, insn##op, b, a, c);             \
 }
 
+#define I_u2u1msbu3(op)                                 \
+Ip_u2u1msbu3(op)                                        \
+{                                                       \
+        build_insn(buf, insn##op, b, a, c+d-1, c);      \
+}
+
 #define I_u1u2(op)                                      \
 Ip_u1u2(op)                                             \
 {                                                       \
@@ -349,6 +357,7 @@ I_u2u1u3(_dsll32)
 I_u2u1u3(_dsra)
 I_u2u1u3(_dsrl)
 I_u2u1u3(_dsrl32)
+I_u2u1u3(_drotr)
 I_u3u1u2(_dsubu)
 I_0(_eret)
 I_u1(_j)
@@ -377,6 +386,7 @@ I_0(_tlbwi)
 I_0(_tlbwr)
 I_u3u1u2(_xor)
 I_u2u1u3(_xori)
+I_u2u1msbu3(_dins);
 
 /* Handle labels. */
 void __cpuinit uasm_build_label(struct uasm_label **lab, u32 *addr, int lid)
diff --git a/arch/mips/mm/uasm.h b/arch/mips/mm/uasm.h
index c6d1e3dd82d4..3d153edaa51e 100644
--- a/arch/mips/mm/uasm.h
+++ b/arch/mips/mm/uasm.h
@@ -34,6 +34,11 @@ uasm_i##op(u32 **buf, unsigned int a, signed int b, unsigned int c)
 void __cpuinit                                                          \
 uasm_i##op(u32 **buf, unsigned int a, unsigned int b, signed int c)
 
+#define Ip_u2u1msbu3(op)                                                \
+void __cpuinit                                                          \
+uasm_i##op(u32 **buf, unsigned int a, unsigned int b, unsigned int c,   \
+           unsigned int d)
+
 #define Ip_u1u2(op)                                                     \
 void __cpuinit uasm_i##op(u32 **buf, unsigned int a, unsigned int b)
 
@@ -65,6 +70,7 @@ Ip_u2u1u3(_dsll32);
 Ip_u2u1u3(_dsra);
 Ip_u2u1u3(_dsrl);
 Ip_u2u1u3(_dsrl32);
+Ip_u2u1u3(_drotr);
 Ip_u3u1u2(_dsubu);
 Ip_0(_eret);
 Ip_u1(_j);
@@ -93,6 +99,7 @@ Ip_0(_tlbwi);
 Ip_0(_tlbwr);
 Ip_u3u1u2(_xor);
 Ip_u2u1u3(_xori);
+Ip_u2u1msbu3(_dins);
 
 /* Handle labels. */
 struct uasm_label {
diff --git a/arch/mips/mti-malta/malta-memory.c b/arch/mips/mti-malta/malta-memory.c
index 9035c64bc5ed..b27419c84919 100644
--- a/arch/mips/mti-malta/malta-memory.c
+++ b/arch/mips/mti-malta/malta-memory.c
@@ -55,7 +55,7 @@ static struct prom_pmemblock * __init prom_getmdesc(void)
         char *memsize_str;
         unsigned int memsize;
         char *ptr;
-        static char cmdline[CL_SIZE] __initdata;
+        static char cmdline[COMMAND_LINE_SIZE] __initdata;
 
         /* otherwise look in the environment */
         memsize_str = prom_getenv("memsize");
diff --git a/arch/mips/nxp/pnx833x/common/interrupts.c b/arch/mips/nxp/pnx833x/common/interrupts.c
index 30533ba200e2..3a467c04f811 100644
--- a/arch/mips/nxp/pnx833x/common/interrupts.c
+++ b/arch/mips/nxp/pnx833x/common/interrupts.c
@@ -295,7 +295,7 @@ static int pnx833x_set_type_gpio_irq(unsigned int irq, unsigned int flow_type)
 }
 
 static struct irq_chip pnx833x_pic_irq_type = {
-        .typename = "PNX-PIC",
+        .name = "PNX-PIC",
         .startup = pnx833x_startup_pic_irq,
         .shutdown = pnx833x_shutdown_pic_irq,
         .enable = pnx833x_enable_pic_irq,
@@ -305,7 +305,7 @@ static struct irq_chip pnx833x_pic_irq_type = {
 };
 
 static struct irq_chip pnx833x_gpio_irq_type = {
-        .typename = "PNX-GPIO",
+        .name = "PNX-GPIO",
         .startup = pnx833x_startup_gpio_irq,
         .shutdown = pnx833x_disable_gpio_irq,
         .enable = pnx833x_enable_gpio_irq,
diff --git a/arch/mips/oprofile/op_model_loongson2.c b/arch/mips/oprofile/op_model_loongson2.c
index 575cd1473475..475ff46712ab 100644
--- a/arch/mips/oprofile/op_model_loongson2.c
+++ b/arch/mips/oprofile/op_model_loongson2.c
@@ -1,7 +1,7 @@
 /*
  * Loongson2 performance counter driver for oprofile
  *
- * Copyright (C) 2009 Lemote Inc. & Insititute of Computing Technology
+ * Copyright (C) 2009 Lemote Inc.
  * Author: Yanhua <yanh@lemote.com>
  * Author: Wu Zhangjin <wuzj@lemote.com>
  *
@@ -125,6 +125,9 @@ static irqreturn_t loongson2_perfcount_handler(int irq, void *dev_id)
          */
 
         /* Check whether the irq belongs to me */
+        enabled = read_c0_perfcnt() & LOONGSON2_PERFCNT_INT_EN;
+        if (!enabled)
+                return IRQ_NONE;
         enabled = reg.cnt1_enabled | reg.cnt2_enabled;
         if (!enabled)
                 return IRQ_NONE;
diff --git a/arch/mips/pci/Makefile b/arch/mips/pci/Makefile
index 91bfe73a7f60..c9209ca6c8e7 100644
--- a/arch/mips/pci/Makefile
+++ b/arch/mips/pci/Makefile
@@ -22,13 +22,13 @@ obj-$(CONFIG_BCM63XX)		+= pci-bcm63xx.o fixup-bcm63xx.o \
 #
 # These are still pretty much in the old state, watch, go blind.
 #
-obj-$(CONFIG_BASLER_EXCITE)     += ops-titan.o pci-excite.o fixup-excite.o
 obj-$(CONFIG_LASAT)             += pci-lasat.o
 obj-$(CONFIG_MIPS_COBALT)       += fixup-cobalt.o
 obj-$(CONFIG_SOC_AU1500)        += fixup-au1000.o ops-au1000.o
 obj-$(CONFIG_SOC_AU1550)        += fixup-au1000.o ops-au1000.o
 obj-$(CONFIG_SOC_PNX8550)       += fixup-pnx8550.o ops-pnx8550.o
-obj-$(CONFIG_LEMOTE_FULOONG2E)  += fixup-fuloong2e.o ops-bonito64.o
+obj-$(CONFIG_LEMOTE_FULOONG2E)  += fixup-fuloong2e.o ops-loongson2.o
+obj-$(CONFIG_LEMOTE_MACH2F)     += fixup-lemote2f.o ops-loongson2.o
 obj-$(CONFIG_MIPS_MALTA)        += fixup-malta.o
 obj-$(CONFIG_PMC_MSP7120_GW)    += fixup-pmcmsp.o ops-pmcmsp.o
 obj-$(CONFIG_PMC_MSP7120_EVAL)  += fixup-pmcmsp.o ops-pmcmsp.o
diff --git a/arch/mips/pci/fixup-excite.c b/arch/mips/pci/fixup-excite.c
deleted file mode 100644
index cd64d9f177c4..000000000000
--- a/arch/mips/pci/fixup-excite.c
+++ /dev/null
@@ -1,36 +0,0 @@
-/*
- *  Copyright (C) 2004 by Basler Vision Technologies AG
- *  Author: Thomas Koeller <thomas.koeller@baslerweb.com>
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License
- *  along with this program; if not, write to the Free Software
- *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/pci.h>
-#include <excite.h>
-
-int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
-{
-        if (pin == 0)
-                return -1;
-
-        return USB_IRQ;         /* USB controller is the only PCI device */
-}
-
-/* Do platform specific device initialization at pci_enable_device() time */
-int pcibios_plat_dev_init(struct pci_dev *dev)
-{
-        return 0;
-}
diff --git a/arch/mips/pci/fixup-fuloong2e.c b/arch/mips/pci/fixup-fuloong2e.c
index 0c4c7a81213f..4f6d8da07f93 100644
--- a/arch/mips/pci/fixup-fuloong2e.c
+++ b/arch/mips/pci/fixup-fuloong2e.c
@@ -13,7 +13,8 @@
  */
 #include <linux/init.h>
 #include <linux/pci.h>
-#include <asm/mips-boards/bonito64.h>
+
+#include <loongson.h>
 
 /* South bridge slot number is set by the pci probe process */
 static u8 sb_slot = 5;
@@ -35,7 +36,7 @@ int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
                         break;
                 }
         } else {
-                irq = BONITO_IRQ_BASE + 25 + pin;
+                irq = LOONGSON_IRQ_BASE + 25 + pin;
         }
         return irq;
 
diff --git a/arch/mips/pci/fixup-lemote2f.c b/arch/mips/pci/fixup-lemote2f.c
new file mode 100644
index 000000000000..caf2edeb02f0
--- /dev/null
+++ b/arch/mips/pci/fixup-lemote2f.c
@@ -0,0 +1,160 @@
+/*
+ * Copyright (C) 2008 Lemote Technology
+ * Copyright (C) 2004 ICT CAS
+ * Author: Li xiaoyu, lixy@ict.ac.cn
+ *
+ * Copyright (C) 2007 Lemote, Inc.
+ * Author: Fuxin Zhang, zhangfx@lemote.com
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ */
+#include <linux/init.h>
+#include <linux/pci.h>
+
+#include <loongson.h>
+#include <cs5536/cs5536.h>
+#include <cs5536/cs5536_pci.h>
+
+/* PCI interrupt pins
+ *
+ * These should not be changed, or you should consider loongson2f interrupt
+ * register and your pci card dispatch
+ */
+
+#define PCIA            4
+#define PCIB            5
+#define PCIC            6
+#define PCID            7
+
+/* all the pci device has the PCIA pin, check the datasheet. */
+static char irq_tab[][5] __initdata = {
+        /*      INTA    INTB    INTC    INTD */
+        {0, 0, 0, 0, 0},        /*  11: Unused */
+        {0, 0, 0, 0, 0},        /*  12: Unused */
+        {0, 0, 0, 0, 0},        /*  13: Unused */
+        {0, 0, 0, 0, 0},        /*  14: Unused */
+        {0, 0, 0, 0, 0},        /*  15: Unused */
+        {0, 0, 0, 0, 0},        /*  16: Unused */
+        {0, PCIA, 0, 0, 0},     /*  17: RTL8110-0 */
+        {0, PCIB, 0, 0, 0},     /*  18: RTL8110-1 */
+        {0, PCIC, 0, 0, 0},     /*  19: SiI3114 */
+        {0, PCID, 0, 0, 0},     /*  20: 3-ports nec usb */
+        {0, PCIA, PCIB, PCIC, PCID},    /*  21: PCI-SLOT */
+        {0, 0, 0, 0, 0},        /*  22: Unused */
+        {0, 0, 0, 0, 0},        /*  23: Unused */
+        {0, 0, 0, 0, 0},        /*  24: Unused */
+        {0, 0, 0, 0, 0},        /*  25: Unused */
+        {0, 0, 0, 0, 0},        /*  26: Unused */
+        {0, 0, 0, 0, 0},        /*  27: Unused */
+};
+
+int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
+{
+        int virq;
+
+        if ((PCI_SLOT(dev->devfn) != PCI_IDSEL_CS5536)
+            && (PCI_SLOT(dev->devfn) < 32)) {
+                virq = irq_tab[slot][pin];
+                printk(KERN_INFO "slot: %d, pin: %d, irq: %d\n", slot, pin,
+                       virq + LOONGSON_IRQ_BASE);
+                if (virq != 0)
+                        return LOONGSON_IRQ_BASE + virq;
+                else
+                        return 0;
+        } else if (PCI_SLOT(dev->devfn) == PCI_IDSEL_CS5536) {  /*  cs5536 */
+                switch (PCI_FUNC(dev->devfn)) {
+                case 2:
+                        pci_write_config_byte(dev, PCI_INTERRUPT_LINE,
+                                              CS5536_IDE_INTR);
+                        return CS5536_IDE_INTR; /*  for IDE */
+                case 3:
+                        pci_write_config_byte(dev, PCI_INTERRUPT_LINE,
+                                              CS5536_ACC_INTR);
+                        return CS5536_ACC_INTR; /*  for AUDIO */
+                case 4: /*  for OHCI */
+                case 5: /*  for EHCI */
+                case 6: /*  for UDC */
+                case 7: /*  for OTG */
+                        pci_write_config_byte(dev, PCI_INTERRUPT_LINE,
+                                              CS5536_USB_INTR);
+                        return CS5536_USB_INTR;
+                }
+                return dev->irq;
+        } else {
+                printk(KERN_INFO " strange pci slot number.\n");
+                return 0;
+        }
+}
+
+/* Do platform specific device initialization at pci_enable_device() time */
+int pcibios_plat_dev_init(struct pci_dev *dev)
+{
+        return 0;
+}
+
+/* CS5536 SPEC. fixup */
+static void __init loongson_cs5536_isa_fixup(struct pci_dev *pdev)
+{
+        /* the uart1 and uart2 interrupt in PIC is enabled as default */
+        pci_write_config_dword(pdev, PCI_UART1_INT_REG, 1);
+        pci_write_config_dword(pdev, PCI_UART2_INT_REG, 1);
+}
+
+static void __init loongson_cs5536_ide_fixup(struct pci_dev *pdev)
+{
+        /* setting the mutex pin as IDE function */
+        pci_write_config_dword(pdev, PCI_IDE_CFG_REG,
+                               CS5536_IDE_FLASH_SIGNATURE);
+}
+
+static void __init loongson_cs5536_acc_fixup(struct pci_dev *pdev)
+{
+        /* enable the AUDIO interrupt in PIC  */
+        pci_write_config_dword(pdev, PCI_ACC_INT_REG, 1);
+
+        pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xc0);
+}
+
+static void __init loongson_cs5536_ohci_fixup(struct pci_dev *pdev)
+{
+        /* enable the OHCI interrupt in PIC */
+        /* THE OHCI, EHCI, UDC, OTG are shared with interrupt in PIC */
+        pci_write_config_dword(pdev, PCI_OHCI_INT_REG, 1);
+}
+
+static void __init loongson_cs5536_ehci_fixup(struct pci_dev *pdev)
+{
+        u32 hi, lo;
+
+        /* Serial short detect enable */
+        _rdmsr(USB_MSR_REG(USB_CONFIG), &hi, &lo);
+        _wrmsr(USB_MSR_REG(USB_CONFIG), (1 << 1) | (1 << 2) | (1 << 3), lo);
+
+        /* setting the USB2.0 micro frame length */
+        pci_write_config_dword(pdev, PCI_EHCI_FLADJ_REG, 0x2000);
+}
+
+static void __init loongson_nec_fixup(struct pci_dev *pdev)
+{
+        unsigned int val;
+
+        pci_read_config_dword(pdev, 0xe0, &val);
+        /* Only 2 port be used */
+        pci_write_config_dword(pdev, 0xe0, (val & ~3) | 0x2);
+}
+
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_ISA,
+                         loongson_cs5536_isa_fixup);
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_OHC,
+                         loongson_cs5536_ohci_fixup);
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_EHC,
+                         loongson_cs5536_ehci_fixup);
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_AUDIO,
+                         loongson_cs5536_acc_fixup);
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_IDE,
+                         loongson_cs5536_ide_fixup);
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_USB,
+                         loongson_nec_fixup);
diff --git a/arch/mips/pci/ops-bonito64.c b/arch/mips/pci/ops-bonito64.c
index 54e55e7a2431..1b3e03f20c54 100644
--- a/arch/mips/pci/ops-bonito64.c
+++ b/arch/mips/pci/ops-bonito64.c
@@ -29,13 +29,8 @@
 #define PCI_ACCESS_READ  0
 #define PCI_ACCESS_WRITE 1
 
-#ifdef CONFIG_LEMOTE_FULOONG2E
-#define CFG_SPACE_REG(offset) (void *)CKSEG1ADDR(BONITO_PCICFG_BASE | (offset))
-#define ID_SEL_BEGIN 11
-#else
 #define CFG_SPACE_REG(offset) (void *)CKSEG1ADDR(_pcictrl_bonito_pcicfg + (offset))
 #define ID_SEL_BEGIN 10
-#endif
 #define MAX_DEV_NUM (31 - ID_SEL_BEGIN)
 
 
@@ -77,10 +72,8 @@ static int bonito64_pcibios_config_access(unsigned char access_type,
         addrp = CFG_SPACE_REG(addr & 0xffff);
         if (access_type == PCI_ACCESS_WRITE) {
                 writel(cpu_to_le32(*data), addrp);
-#ifndef CONFIG_LEMOTE_FULOONG2E
                 /* Wait till done */
                 while (BONITO_PCIMSTAT & 0xF);
-#endif
         } else {
                 *data = le32_to_cpu(readl(addrp));
         }
diff --git a/arch/mips/pci/ops-loongson2.c b/arch/mips/pci/ops-loongson2.c
new file mode 100644
index 000000000000..aa5d3da27212
--- /dev/null
+++ b/arch/mips/pci/ops-loongson2.c
@@ -0,0 +1,208 @@
+/*
+ * fuloong2e specific PCI support.
+ *
+ * Copyright (C) 1999, 2000, 2004  MIPS Technologies, Inc.
+ *      All rights reserved.
+ *      Authors: Carsten Langgaard <carstenl@mips.com>
+ *               Maciej W. Rozycki <macro@mips.com>
+ *
+ * Copyright (C) 2009 Lemote Inc.
+ * Author: Wu Zhangjin <wuzj@lemote.com>
+ *
+ *  This program is free software; you can distribute it and/or modify it
+ *  under the terms of the GNU General Public License (Version 2) as
+ *  published by the Free Software Foundation.
+ */
+#include <linux/types.h>
+#include <linux/pci.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+
+#include <loongson.h>
+
+#ifdef CONFIG_CS5536
+#include <cs5536/cs5536_pci.h>
+#include <cs5536/cs5536.h>
+#endif
+
+#define PCI_ACCESS_READ  0
+#define PCI_ACCESS_WRITE 1
+
+#define CFG_SPACE_REG(offset) \
+        (void *)CKSEG1ADDR(LOONGSON_PCICFG_BASE | (offset))
+#define ID_SEL_BEGIN 11
+#define MAX_DEV_NUM (31 - ID_SEL_BEGIN)
+
+
+static int loongson_pcibios_config_access(unsigned char access_type,
+                                      struct pci_bus *bus,
+                                      unsigned int devfn, int where,
+                                      u32 *data)
+{
+        u32 busnum = bus->number;
+        u32 addr, type;
+        u32 dummy;
+        void *addrp;
+        int device = PCI_SLOT(devfn);
+        int function = PCI_FUNC(devfn);
+        int reg = where & ~3;
+
+        if (busnum == 0) {
+                /* board-specific part,currently,only fuloong2f,yeeloong2f
+                 * use CS5536, fuloong2e use via686b, gdium has no
+                 * south bridge
+                 */
+#ifdef CONFIG_CS5536
+                /* cs5536_pci_conf_read4/write4() will call _rdmsr/_wrmsr() to
+                 * access the regsters PCI_MSR_ADDR, PCI_MSR_DATA_LO,
+                 * PCI_MSR_DATA_HI, which is bigger than PCI_MSR_CTRL, so, it
+                 * will not go this branch, but the others. so, no calling dead
+                 * loop here.
+                 */
+                if ((PCI_IDSEL_CS5536 == device) && (reg < PCI_MSR_CTRL)) {
+                        switch (access_type) {
+                        case PCI_ACCESS_READ:
+                                *data = cs5536_pci_conf_read4(function, reg);
+                                break;
+                        case PCI_ACCESS_WRITE:
+                                cs5536_pci_conf_write4(function, reg, *data);
+                                break;
+                        }
+                        return 0;
+                }
+#endif
+                /* Type 0 configuration for onboard PCI bus */
+                if (device > MAX_DEV_NUM)
+                        return -1;
+
+                addr = (1 << (device + ID_SEL_BEGIN)) | (function << 8) | reg;
+                type = 0;
+        } else {
+                /* Type 1 configuration for offboard PCI bus */
+                addr = (busnum << 16) | (device << 11) | (function << 8) | reg;
+                type = 0x10000;
+        }
+
+        /* Clear aborts */
+        LOONGSON_PCICMD |= LOONGSON_PCICMD_MABORT_CLR | \
+                                LOONGSON_PCICMD_MTABORT_CLR;
+
+        LOONGSON_PCIMAP_CFG = (addr >> 16) | type;
+
+        /* Flush Bonito register block */
+        dummy = LOONGSON_PCIMAP_CFG;
+        mmiowb();
+
+        addrp = CFG_SPACE_REG(addr & 0xffff);
+        if (access_type == PCI_ACCESS_WRITE)
+                writel(cpu_to_le32(*data), addrp);
+        else
+                *data = le32_to_cpu(readl(addrp));
+
+        /* Detect Master/Target abort */
+        if (LOONGSON_PCICMD & (LOONGSON_PCICMD_MABORT_CLR |
+                             LOONGSON_PCICMD_MTABORT_CLR)) {
+                /* Error occurred */
+
+                /* Clear bits */
+                LOONGSON_PCICMD |= (LOONGSON_PCICMD_MABORT_CLR |
+                                  LOONGSON_PCICMD_MTABORT_CLR);
+
+                return -1;
+        }
+
+        return 0;
+
+}
+
+
+/*
+ * We can't address 8 and 16 bit words directly.  Instead we have to
+ * read/write a 32bit word and mask/modify the data we actually want.
+ */
+static int loongson_pcibios_read(struct pci_bus *bus, unsigned int devfn,
+                             int where, int size, u32 *val)
+{
+        u32 data = 0;
+
+        if ((size == 2) && (where & 1))
+                return PCIBIOS_BAD_REGISTER_NUMBER;
+        else if ((size == 4) && (where & 3))
+                return PCIBIOS_BAD_REGISTER_NUMBER;
+
+        if (loongson_pcibios_config_access(PCI_ACCESS_READ, bus, devfn, where,
+                                       &data))
+                return -1;
+
+        if (size == 1)
+                *val = (data >> ((where & 3) << 3)) & 0xff;
+        else if (size == 2)
+                *val = (data >> ((where & 3) << 3)) & 0xffff;
+        else
+                *val = data;
+
+        return PCIBIOS_SUCCESSFUL;
+}
+
+static int loongson_pcibios_write(struct pci_bus *bus, unsigned int devfn,
+                              int where, int size, u32 val)
+{
+        u32 data = 0;
+
+        if ((size == 2) && (where & 1))
+                return PCIBIOS_BAD_REGISTER_NUMBER;
+        else if ((size == 4) && (where & 3))
+                return PCIBIOS_BAD_REGISTER_NUMBER;
+
+        if (size == 4)
+                data = val;
+        else {
+                if (loongson_pcibios_config_access(PCI_ACCESS_READ, bus, devfn,
+                                        where, &data))
+                        return -1;
+
+                if (size == 1)
+                        data = (data & ~(0xff << ((where & 3) << 3))) |
+                                (val << ((where & 3) << 3));
+                else if (size == 2)
+                        data = (data & ~(0xffff << ((where & 3) << 3))) |
+                                (val << ((where & 3) << 3));
+        }
+
+        if (loongson_pcibios_config_access(PCI_ACCESS_WRITE, bus, devfn, where,
+                                       &data))
+                return -1;
+
+        return PCIBIOS_SUCCESSFUL;
+}
+
+struct pci_ops loongson_pci_ops = {
+        .read = loongson_pcibios_read,
+        .write = loongson_pcibios_write
+};
+
+#ifdef CONFIG_CS5536
+void _rdmsr(u32 msr, u32 *hi, u32 *lo)
+{
+        struct pci_bus bus = {
+                .number = PCI_BUS_CS5536
+        };
+        u32 devfn = PCI_DEVFN(PCI_IDSEL_CS5536, 0);
+        loongson_pcibios_write(&bus, devfn, PCI_MSR_ADDR, 4, msr);
+        loongson_pcibios_read(&bus, devfn, PCI_MSR_DATA_LO, 4, lo);
+        loongson_pcibios_read(&bus, devfn, PCI_MSR_DATA_HI, 4, hi);
+}
+EXPORT_SYMBOL(_rdmsr);
+
+void _wrmsr(u32 msr, u32 hi, u32 lo)
+{
+        struct pci_bus bus = {
+                .number = PCI_BUS_CS5536
+        };
+        u32 devfn = PCI_DEVFN(PCI_IDSEL_CS5536, 0);
+        loongson_pcibios_write(&bus, devfn, PCI_MSR_ADDR, 4, msr);
+        loongson_pcibios_write(&bus, devfn, PCI_MSR_DATA_LO, 4, lo);
+        loongson_pcibios_write(&bus, devfn, PCI_MSR_DATA_HI, 4, hi);
+}
+EXPORT_SYMBOL(_wrmsr);
+#endif
diff --git a/arch/mips/pci/pci-excite.c b/arch/mips/pci/pci-excite.c
deleted file mode 100644
index 8a56876afcc6..000000000000
--- a/arch/mips/pci/pci-excite.c
+++ /dev/null
@@ -1,149 +0,0 @@
-/*
- *  Copyright (C) 2004 by Basler Vision Technologies AG
- *  Author: Thomas Koeller <thomas.koeller@baslerweb.com>
- *  Based on the PMC-Sierra Yosemite board support by Ralf Baechle.
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License
- *  along with this program; if not, write to the Free Software
- *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <linux/types.h>
-#include <linux/pci.h>
-#include <linux/bitops.h>
-#include <asm/rm9k-ocd.h>
-#include <excite.h>
-
-
-extern struct pci_ops titan_pci_ops;
-
-
-static struct resource
-        mem_resource =  {
-                .name   = "PCI memory",
-                .start  = EXCITE_PHYS_PCI_MEM,
-                .end    = EXCITE_PHYS_PCI_MEM + EXCITE_SIZE_PCI_MEM - 1,
-                .flags  = IORESOURCE_MEM
-        },
-        io_resource = {
-                .name   = "PCI I/O",
-                .start  = EXCITE_PHYS_PCI_IO,
-                .end    = EXCITE_PHYS_PCI_IO + EXCITE_SIZE_PCI_IO - 1,
-                .flags  = IORESOURCE_IO
-        };
-
-
-static struct pci_controller bx_controller = {
-        .pci_ops        = &titan_pci_ops,
-        .mem_resource   = &mem_resource,
-        .mem_offset     = 0x00000000UL,
-        .io_resource    = &io_resource,
-        .io_offset      = 0x00000000UL
-};
-
-
-static char
-        iopage_failed[] __initdata   = "Cannot allocate PCI I/O page",
-        modebits_no_pci[] __initdata = "PCI is not configured in mode bits";
-
-#define RM9000x2_OCD_HTSC       0x0604
-#define RM9000x2_OCD_HTBHL      0x060c
-#define RM9000x2_OCD_PCIHRST    0x078c
-
-#define RM9K_OCD_MODEBIT1       0x00d4 /* (MODEBIT1) Mode Bit 1 */
-#define RM9K_OCD_CPHDCR         0x00f4 /* CPU-PCI/HT Data Control. */
-
-#define PCISC_FB2B              0x00000200
-#define PCISC_MWICG             0x00000010
-#define PCISC_EMC               0x00000004
-#define PCISC_ERMA              0x00000002
-
-
-
-static int __init basler_excite_pci_setup(void)
-{
-        const unsigned int fullbars = memsize / (256 << 20);
-        unsigned int i;
-
-        /* Check modebits to see if PCI is really enabled. */
-        if (!((ocd_readl(RM9K_OCD_MODEBIT1) >> (47-32)) & 0x1))
-                panic(modebits_no_pci);
-
-        if (NULL == request_mem_region(EXCITE_PHYS_PCI_IO, EXCITE_SIZE_PCI_IO,
-                                       "Memory-mapped PCI I/O page"))
-                panic(iopage_failed);
-
-        /* Enable PCI 0 as master for config cycles */
-        ocd_writel(PCISC_EMC | PCISC_ERMA, RM9000x2_OCD_HTSC);
-
-
-        /* Set up latency timer */
-        ocd_writel(0x8008, RM9000x2_OCD_HTBHL);
-
-        /*  Setup host IO and Memory space */
-        ocd_writel((EXCITE_PHYS_PCI_IO >> 4) | 1, LKB7);
-        ocd_writel(((EXCITE_SIZE_PCI_IO >> 4) & 0x7fffff00) - 0x100, LKM7);
-        ocd_writel((EXCITE_PHYS_PCI_MEM >> 4) | 1, LKB8);
-        ocd_writel(((EXCITE_SIZE_PCI_MEM >> 4) & 0x7fffff00) - 0x100, LKM8);
-
-        /* Set up PCI BARs to map all installed memory */
-        for (i = 0; i < 6; i++) {
-                const unsigned int bar = 0x610 + i * 4;
-
-                if (i < fullbars) {
-                        ocd_writel(0x10000000 * i, bar);
-                        ocd_writel(0x01000000 * i, bar + 0x140);
-                        ocd_writel(0x0ffff029, bar + 0x100);
-                        continue;
-                }
-
-                if (i == fullbars) {
-                        int o;
-                        u32 mask;
-
-                        const unsigned long rem = memsize - i * 0x10000000;
-                        if (!rem) {
-                                ocd_writel(0x00000000, bar + 0x100);
-                                continue;
-                        }
-
-                        o = ffs(rem) - 1;
-                        if (rem & ~(0x1 << o))
-                                o++;
-                        mask = ((0x1 << o) & 0x0ffff000) - 0x1000;
-                        ocd_writel(0x10000000 * i, bar);
-                        ocd_writel(0x01000000 * i, bar + 0x140);
-                        ocd_writel(0x00000029 | mask, bar + 0x100);
-                        continue;
-                }
-
-                ocd_writel(0x00000000, bar + 0x100);
-        }
-
-        /* Finally, enable the PCI interrupt */
-#if USB_IRQ > 7
-        set_c0_intcontrol(1 << USB_IRQ);
-#else
-        set_c0_status(1 << (USB_IRQ + 8));
-#endif
-
-        ioport_resource.start = EXCITE_PHYS_PCI_IO;
-        ioport_resource.end = EXCITE_PHYS_PCI_IO + EXCITE_SIZE_PCI_IO - 1;
-        set_io_port_base((unsigned long) ioremap_nocache(EXCITE_PHYS_PCI_IO, EXCITE_SIZE_PCI_IO));
-        register_pci_controller(&bx_controller);
-        return 0;
-}
-
-
-arch_initcall(basler_excite_pci_setup);
diff --git a/arch/mips/powertv/Kconfig b/arch/mips/powertv/Kconfig
new file mode 100644
index 000000000000..ff0e7e3e6954
--- /dev/null
+++ b/arch/mips/powertv/Kconfig
@@ -0,0 +1,21 @@
+source "arch/mips/powertv/asic/Kconfig"
+
+config BOOTLOADER_DRIVER
+        bool "PowerTV Bootloader Driver Support"
+        default n
+        depends on POWERTV
+        help
+          Use this option if you want to load bootloader driver.
+
+config BOOTLOADER_FAMILY
+        string "POWERTV Bootloader Family string"
+        default "85"
+        depends on POWERTV && !BOOTLOADER_DRIVER
+        help
+          This value should be specified when the bootloader driver is disabled
+          and must be exactly two characters long. Families supported are:
+            R1 - RNG-100  R2 - RNG-200
+            A1 - Class A  B1 - Class B
+            E1 - Class E  F1 - Class F
+            44 - 45xx     46 - 46xx
+            85 - 85xx     86 - 86xx
diff --git a/arch/mips/powertv/Makefile b/arch/mips/powertv/Makefile
new file mode 100644
index 000000000000..2c516718affe
--- /dev/null
+++ b/arch/mips/powertv/Makefile
@@ -0,0 +1,28 @@
+#
+# Carsten Langgaard, carstenl@mips.com
+# Copyright (C) 1999,2000 MIPS Technologies, Inc.  All rights reserved.
+#
+# Carsten Langgaard, carstenl@mips.com
+# Copyright (C) 2000 MIPS Technologies, Inc.  All rights reserved.
+# Portions copyright (C)  2009 Cisco Systems, Inc.
+#
+# This program is free software; you can distribute it and/or modify it
+# under the terms of the GNU General Public License (Version 2) as
+# published by the Free Software Foundation.
+#
+# This program is distributed in the hope it will be useful, but WITHOUT
+# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+# FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+# for more details.
+#
+# You should have received a copy of the GNU General Public License along
+# with this program; if not, write to the Free Software Foundation, Inc.,
+# 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
+#
+# Makefile for the Cisco PowerTV-specific kernel interface routines
+# under Linux.
+#
+
+obj-y += cmdline.o init.o memory.o reset.o time.o powertv_setup.o asic/ pci/
+
+EXTRA_CFLAGS += -Wall -Werror
diff --git a/arch/mips/powertv/asic/Kconfig b/arch/mips/powertv/asic/Kconfig
new file mode 100644
index 000000000000..2016bfe94d66
--- /dev/null
+++ b/arch/mips/powertv/asic/Kconfig
@@ -0,0 +1,28 @@
+config MIN_RUNTIME_RESOURCES
+        bool "Support for minimum runtime resources"
+        default n
+        depends on POWERTV
+        help
+          Enables support for minimizing the number of (SA asic) runtime
+          resources that are preallocated by the kernel.
+
+config MIN_RUNTIME_DOCSIS
+        bool "Support for minimum DOCSIS resource"
+        default y
+        depends on MIN_RUNTIME_RESOURCES
+        help
+          Enables support for the preallocated DOCSIS resource.
+
+config MIN_RUNTIME_PMEM
+        bool "Support for minimum PMEM resource"
+        default y
+        depends on MIN_RUNTIME_RESOURCES
+        help
+          Enables support for the preallocated Memory resource.
+
+config MIN_RUNTIME_TFTP
+        bool "Support for minimum TFTP resource"
+        default y
+        depends on MIN_RUNTIME_RESOURCES
+        help
+          Enables support for the preallocated TFTP resource.
diff --git a/arch/mips/powertv/asic/Makefile b/arch/mips/powertv/asic/Makefile
new file mode 100644
index 000000000000..bebfdcff0443
--- /dev/null
+++ b/arch/mips/powertv/asic/Makefile
@@ -0,0 +1,23 @@
+#
+# Copyright (C) 2009  Scientific-Atlanta, Inc.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+#
+
+obj-y += asic-calliope.o asic-cronus.o asic-zeus.o asic_devices.o asic_int.o \
+         irq_asic.o prealloc-calliope.o prealloc-cronus.o \
+         prealloc-cronuslite.o prealloc-zeus.o
+
+EXTRA_CFLAGS += -Wall -Werror
diff --git a/arch/mips/powertv/asic/asic-calliope.c b/arch/mips/powertv/asic/asic-calliope.c
new file mode 100644
index 000000000000..03d3884c6270
--- /dev/null
+++ b/arch/mips/powertv/asic/asic-calliope.c
@@ -0,0 +1,98 @@
+/*
+ * Locations of devices in the Calliope ASIC.
+ *
+ * Copyright (C) 2005-2009 Scientific-Atlanta, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ *
+ * Author:       Ken Eppinett
+ *               David Schleef <ds@schleef.org>
+ *
+ * Description:  Defines the platform resources for the SA settop.
+ */
+
+#include <asm/mach-powertv/asic.h>
+
+const struct register_map calliope_register_map = {
+        .eic_slow0_strt_add = 0x800000,
+        .eic_cfg_bits = 0x800038,
+        .eic_ready_status = 0x80004c,
+
+        .chipver3 = 0xA00800,
+        .chipver2 = 0xA00804,
+        .chipver1 = 0xA00808,
+        .chipver0 = 0xA0080c,
+
+        /* The registers of IRBlaster */
+        .uart1_intstat = 0xA01800,
+        .uart1_inten = 0xA01804,
+        .uart1_config1 = 0xA01808,
+        .uart1_config2 = 0xA0180C,
+        .uart1_divisorhi = 0xA01810,
+        .uart1_divisorlo = 0xA01814,
+        .uart1_data = 0xA01818,
+        .uart1_status = 0xA0181C,
+
+        .int_stat_3 = 0xA02800,
+        .int_stat_2 = 0xA02804,
+        .int_stat_1 = 0xA02808,
+        .int_stat_0 = 0xA0280c,
+        .int_config = 0xA02810,
+        .int_int_scan = 0xA02818,
+        .ien_int_3 = 0xA02830,
+        .ien_int_2 = 0xA02834,
+        .ien_int_1 = 0xA02838,
+        .ien_int_0 = 0xA0283c,
+        .int_level_3_3 = 0xA02880,
+        .int_level_3_2 = 0xA02884,
+        .int_level_3_1 = 0xA02888,
+        .int_level_3_0 = 0xA0288c,
+        .int_level_2_3 = 0xA02890,
+        .int_level_2_2 = 0xA02894,
+        .int_level_2_1 = 0xA02898,
+        .int_level_2_0 = 0xA0289c,
+        .int_level_1_3 = 0xA028a0,
+        .int_level_1_2 = 0xA028a4,
+        .int_level_1_1 = 0xA028a8,
+        .int_level_1_0 = 0xA028ac,
+        .int_level_0_3 = 0xA028b0,
+        .int_level_0_2 = 0xA028b4,
+        .int_level_0_1 = 0xA028b8,
+        .int_level_0_0 = 0xA028bc,
+        .int_docsis_en = 0xA028F4,
+
+        .mips_pll_setup = 0x980000,
+        .usb_fs = 0x980030,             /* -default 72800028- */
+        .test_bus = 0x9800CC,
+        .crt_spare = 0x9800d4,
+        .usb2_ohci_int_mask = 0x9A000c,
+        .usb2_strap = 0x9A0014,
+        .ehci_hcapbase = 0x9BFE00,
+        .ohci_hc_revision = 0x9BFC00,
+        .bcm1_bs_lmi_steer = 0x9E0004,
+        .usb2_control = 0x9E0054,
+        .usb2_stbus_obc = 0x9BFF00,
+        .usb2_stbus_mess_size = 0x9BFF04,
+        .usb2_stbus_chunk_size = 0x9BFF08,
+
+        .pcie_regs = 0x000000,          /* -doesn't exist- */
+        .tim_ch = 0xA02C10,
+        .tim_cl = 0xA02C14,
+        .gpio_dout = 0xA02c20,
+        .gpio_din = 0xA02c24,
+        .gpio_dir = 0xA02c2C,
+        .watchdog = 0xA02c30,
+        .front_panel = 0x000000,        /* -not used- */
+};
diff --git a/arch/mips/powertv/asic/asic-cronus.c b/arch/mips/powertv/asic/asic-cronus.c
new file mode 100644
index 000000000000..5f4589c9f83d
--- /dev/null
+++ b/arch/mips/powertv/asic/asic-cronus.c
@@ -0,0 +1,98 @@
+/*
+ * Locations of devices in the Cronus ASIC
+ *
+ * Copyright (C) 2005-2009 Scientific-Atlanta, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ *
+ * Author:       Ken Eppinett
+ *               David Schleef <ds@schleef.org>
+ *
+ * Description:  Defines the platform resources for the SA settop.
+ */
+
+#include <asm/mach-powertv/asic.h>
+
+const struct register_map cronus_register_map = {
+        .eic_slow0_strt_add = 0x000000,
+        .eic_cfg_bits = 0x000038,
+        .eic_ready_status = 0x00004C,
+
+        .chipver3 = 0x2A0800,
+        .chipver2 = 0x2A0804,
+        .chipver1 = 0x2A0808,
+        .chipver0 = 0x2A080C,
+
+        /* The registers of IRBlaster */
+        .uart1_intstat = 0x2A1800,
+        .uart1_inten = 0x2A1804,
+        .uart1_config1 = 0x2A1808,
+        .uart1_config2 = 0x2A180C,
+        .uart1_divisorhi = 0x2A1810,
+        .uart1_divisorlo = 0x2A1814,
+        .uart1_data = 0x2A1818,
+        .uart1_status = 0x2A181C,
+
+        .int_stat_3 = 0x2A2800,
+        .int_stat_2 = 0x2A2804,
+        .int_stat_1 = 0x2A2808,
+        .int_stat_0 = 0x2A280C,
+        .int_config = 0x2A2810,
+        .int_int_scan = 0x2A2818,
+        .ien_int_3 = 0x2A2830,
+        .ien_int_2 = 0x2A2834,
+        .ien_int_1 = 0x2A2838,
+        .ien_int_0 = 0x2A283C,
+        .int_level_3_3 = 0x2A2880,
+        .int_level_3_2 = 0x2A2884,
+        .int_level_3_1 = 0x2A2888,
+        .int_level_3_0 = 0x2A288C,
+        .int_level_2_3 = 0x2A2890,
+        .int_level_2_2 = 0x2A2894,
+        .int_level_2_1 = 0x2A2898,
+        .int_level_2_0 = 0x2A289C,
+        .int_level_1_3 = 0x2A28A0,
+        .int_level_1_2 = 0x2A28A4,
+        .int_level_1_1 = 0x2A28A8,
+        .int_level_1_0 = 0x2A28AC,
+        .int_level_0_3 = 0x2A28B0,
+        .int_level_0_2 = 0x2A28B4,
+        .int_level_0_1 = 0x2A28B8,
+        .int_level_0_0 = 0x2A28BC,
+        .int_docsis_en = 0x2A28F4,
+
+        .mips_pll_setup = 0x1C0000,
+        .usb_fs = 0x1C0018,
+        .test_bus = 0x1C00CC,
+        .crt_spare = 0x1c00d4,
+        .usb2_ohci_int_mask = 0x20000C,
+        .usb2_strap = 0x200014,
+        .ehci_hcapbase = 0x21FE00,
+        .ohci_hc_revision = 0x1E0000,
+        .bcm1_bs_lmi_steer = 0x2E0008,
+        .usb2_control = 0x2E004C,
+        .usb2_stbus_obc = 0x21FF00,
+        .usb2_stbus_mess_size = 0x21FF04,
+        .usb2_stbus_chunk_size = 0x21FF08,
+
+        .pcie_regs = 0x220000,
+        .tim_ch = 0x2A2C10,
+        .tim_cl = 0x2A2C14,
+        .gpio_dout = 0x2A2C20,
+        .gpio_din = 0x2A2C24,
+        .gpio_dir = 0x2A2C2C,
+        .watchdog = 0x2A2C30,
+        .front_panel = 0x2A3800,
+};
diff --git a/arch/mips/powertv/asic/asic-zeus.c b/arch/mips/powertv/asic/asic-zeus.c
new file mode 100644
index 000000000000..1469daab920e
--- /dev/null
+++ b/arch/mips/powertv/asic/asic-zeus.c
@@ -0,0 +1,98 @@
+/*
+ * Locations of devices in the Zeus ASIC
+ *
+ * Copyright (C) 2005-2009 Scientific-Atlanta, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ *
+ * Author:       Ken Eppinett
+ *               David Schleef <ds@schleef.org>
+ *
+ * Description:  Defines the platform resources for the SA settop.
+ */
+
+#include <asm/mach-powertv/asic.h>
+
+const struct register_map zeus_register_map = {
+        .eic_slow0_strt_add = 0x000000,
+        .eic_cfg_bits = 0x000038,
+        .eic_ready_status = 0x00004c,
+
+        .chipver3 = 0x280800,
+        .chipver2 = 0x280804,
+        .chipver1 = 0x280808,
+        .chipver0 = 0x28080c,
+
+        /* The registers of IRBlaster */
+        .uart1_intstat = 0x281800,
+        .uart1_inten = 0x281804,
+        .uart1_config1 = 0x281808,
+        .uart1_config2 = 0x28180C,
+        .uart1_divisorhi = 0x281810,
+        .uart1_divisorlo = 0x281814,
+        .uart1_data = 0x281818,
+        .uart1_status = 0x28181C,
+
+        .int_stat_3 = 0x282800,
+        .int_stat_2 = 0x282804,
+        .int_stat_1 = 0x282808,
+        .int_stat_0 = 0x28280c,
+        .int_config = 0x282810,
+        .int_int_scan = 0x282818,
+        .ien_int_3 = 0x282830,
+        .ien_int_2 = 0x282834,
+        .ien_int_1 = 0x282838,
+        .ien_int_0 = 0x28283c,
+        .int_level_3_3 = 0x282880,
+        .int_level_3_2 = 0x282884,
+        .int_level_3_1 = 0x282888,
+        .int_level_3_0 = 0x28288c,
+        .int_level_2_3 = 0x282890,
+        .int_level_2_2 = 0x282894,
+        .int_level_2_1 = 0x282898,
+        .int_level_2_0 = 0x28289c,
+        .int_level_1_3 = 0x2828a0,
+        .int_level_1_2 = 0x2828a4,
+        .int_level_1_1 = 0x2828a8,
+        .int_level_1_0 = 0x2828ac,
+        .int_level_0_3 = 0x2828b0,
+        .int_level_0_2 = 0x2828b4,
+        .int_level_0_1 = 0x2828b8,
+        .int_level_0_0 = 0x2828bc,
+        .int_docsis_en = 0x2828F4,
+
+        .mips_pll_setup = 0x1a0000,
+        .usb_fs = 0x1a0018,
+        .test_bus = 0x1a0238,
+        .crt_spare = 0x1a0090,
+        .usb2_ohci_int_mask = 0x1e000c,
+        .usb2_strap = 0x1e0014,
+        .ehci_hcapbase = 0x1FFE00,
+        .ohci_hc_revision = 0x1FFC00,
+        .bcm1_bs_lmi_steer = 0x2C0008,
+        .usb2_control = 0x2c01a0,
+        .usb2_stbus_obc = 0x1FFF00,
+        .usb2_stbus_mess_size = 0x1FFF04,
+        .usb2_stbus_chunk_size = 0x1FFF08,
+
+        .pcie_regs = 0x200000,
+        .tim_ch = 0x282C10,
+        .tim_cl = 0x282C14,
+        .gpio_dout = 0x282c20,
+        .gpio_din = 0x282c24,
+        .gpio_dir = 0x282c2C,
+        .watchdog = 0x282c30,
+        .front_panel = 0x283800,
+};
diff --git a/arch/mips/powertv/asic/asic_devices.c b/arch/mips/powertv/asic/asic_devices.c
new file mode 100644
index 000000000000..bae82880b6b5
--- /dev/null
+++ b/arch/mips/powertv/asic/asic_devices.c
@@ -0,0 +1,787 @@
+/*
+ *                   ASIC Device List Intialization
+ *
+ * Description:  Defines the platform resources for the SA settop.
+ *
+ * Copyright (C) 2005-2009 Scientific-Atlanta, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ *
+ * Author:       Ken Eppinett
+ *               David Schleef <ds@schleef.org>
+ *
+ * Description:  Defines the platform resources for the SA settop.
+ *
+ * NOTE: The bootloader allocates persistent memory at an address which is
+ * 16 MiB below the end of the highest address in KSEG0. All fixed
+ * address memory reservations must avoid this region.
+ */
+
+#include <linux/device.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/resource.h>
+#include <linux/serial_reg.h>
+#include <linux/io.h>
+#include <linux/bootmem.h>
+#include <linux/mm.h>
+#include <linux/platform_device.h>
+#include <linux/module.h>
+#include <asm/page.h>
+#include <linux/swap.h>
+#include <linux/highmem.h>
+#include <linux/dma-mapping.h>
+
+#include <asm/mach-powertv/asic.h>
+#include <asm/mach-powertv/asic_regs.h>
+#include <asm/mach-powertv/interrupts.h>
+
+#ifdef CONFIG_BOOTLOADER_DRIVER
+#include <asm/mach-powertv/kbldr.h>
+#endif
+#include <asm/bootinfo.h>
+
+#define BOOTLDRFAMILY(byte1, byte0) (((byte1) << 8) | (byte0))
+
+/*
+ * Forward Prototypes
+ */
+static void pmem_setup_resource(void);
+
+/*
+ * Global Variables
+ */
+enum asic_type asic;
+
+unsigned int platform_features;
+unsigned int platform_family;
+const struct register_map  *register_map;
+EXPORT_SYMBOL(register_map);                    /* Exported for testing */
+unsigned long asic_phy_base;
+unsigned long asic_base;
+EXPORT_SYMBOL(asic_base);                       /* Exported for testing */
+struct resource *gp_resources;
+static bool usb_configured;
+
+/*
+ * Don't recommend to use it directly, it is usually used by kernel internally.
+ * Portable code should be using interfaces such as ioremp, dma_map_single, etc.
+ */
+unsigned long phys_to_bus_offset;
+EXPORT_SYMBOL(phys_to_bus_offset);
+
+/*
+ *
+ * IO Resource Definition
+ *
+ */
+
+struct resource asic_resource = {
+        .name  = "ASIC Resource",
+        .start = 0,
+        .end   = ASIC_IO_SIZE,
+        .flags = IORESOURCE_MEM,
+};
+
+/*
+ *
+ * USB Host Resource Definition
+ *
+ */
+
+static struct resource ehci_resources[] = {
+        {
+                .parent = &asic_resource,
+                .start  = 0,
+                .end    = 0xff,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .start  = irq_usbehci,
+                .end    = irq_usbehci,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static u64 ehci_dmamask = DMA_BIT_MASK(32);
+
+static struct platform_device ehci_device = {
+        .name = "powertv-ehci",
+        .id = 0,
+        .num_resources = 2,
+        .resource = ehci_resources,
+        .dev = {
+                .dma_mask = &ehci_dmamask,
+                .coherent_dma_mask = DMA_BIT_MASK(32),
+        },
+};
+
+static struct resource ohci_resources[] = {
+        {
+                .parent = &asic_resource,
+                .start  = 0,
+                .end    = 0xff,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .start  = irq_usbohci,
+                .end    = irq_usbohci,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static u64 ohci_dmamask = DMA_BIT_MASK(32);
+
+static struct platform_device ohci_device = {
+        .name = "powertv-ohci",
+        .id = 0,
+        .num_resources = 2,
+        .resource = ohci_resources,
+        .dev = {
+                .dma_mask = &ohci_dmamask,
+                .coherent_dma_mask = DMA_BIT_MASK(32),
+        },
+};
+
+static struct platform_device *platform_devices[] = {
+        &ehci_device,
+        &ohci_device,
+};
+
+/*
+ *
+ * Platform Configuration and Device Initialization
+ *
+ */
+static void __init fs_update(int pe, int md, int sdiv, int disable_div_by_3)
+{
+        int en_prg, byp, pwr, nsb, val;
+        int sout;
+
+        sout = 1;
+        en_prg = 1;
+        byp = 0;
+        nsb = 1;
+        pwr = 1;
+
+        val = ((sdiv << 29) | (md << 24) | (pe<<8) | (sout<<3) | (byp<<2) |
+                (nsb<<1) | (disable_div_by_3<<5));
+
+        asic_write(val, usb_fs);
+        asic_write(val | (en_prg<<4), usb_fs);
+        asic_write(val | (en_prg<<4) | pwr, usb_fs);
+}
+
+/*
+ * Allow override of bootloader-specified model
+ */
+static char __initdata cmdline[COMMAND_LINE_SIZE];
+
+#define FORCEFAMILY_PARAM       "forcefamily"
+
+static __init int check_forcefamily(unsigned char forced_family[2])
+{
+        const char *p;
+
+        forced_family[0] = '\0';
+        forced_family[1] = '\0';
+
+        /* Check the command line for a forcefamily directive */
+        strncpy(cmdline, arcs_cmdline, COMMAND_LINE_SIZE - 1);
+        p = strstr(cmdline, FORCEFAMILY_PARAM);
+        if (p && (p != cmdline) && (*(p - 1) != ' '))
+                p = strstr(p, " " FORCEFAMILY_PARAM "=");
+
+        if (p) {
+                p += strlen(FORCEFAMILY_PARAM "=");
+
+                if (*p == '\0' || *(p + 1) == '\0' ||
+                        (*(p + 2) != '\0' && *(p + 2) != ' '))
+                        pr_err(FORCEFAMILY_PARAM " must be exactly two "
+                                "characters long, ignoring value\n");
+
+                else {
+                        forced_family[0] = *p;
+                        forced_family[1] = *(p + 1);
+                }
+        }
+
+        return 0;
+}
+
+/*
+ * platform_set_family - determine major platform family type.
+ *
+ * Returns family type; -1 if none
+ * Returns the family type; -1 if none
+ *
+ */
+static __init noinline void platform_set_family(void)
+{
+#define BOOTLDRFAMILY(byte1, byte0) (((byte1) << 8) | (byte0))
+
+        unsigned char forced_family[2];
+        unsigned short bootldr_family;
+
+        check_forcefamily(forced_family);
+
+        if (forced_family[0] != '\0' && forced_family[1] != '\0')
+                bootldr_family = BOOTLDRFAMILY(forced_family[0],
+                        forced_family[1]);
+        else {
+
+#ifdef CONFIG_BOOTLOADER_DRIVER
+                bootldr_family = (unsigned short) kbldr_GetSWFamily();
+#else
+#if defined(CONFIG_BOOTLOADER_FAMILY)
+                bootldr_family = (unsigned short) BOOTLDRFAMILY(
+                        CONFIG_BOOTLOADER_FAMILY[0],
+                        CONFIG_BOOTLOADER_FAMILY[1]);
+#else
+#error "Unknown Bootloader Family"
+#endif
+#endif
+        }
+
+        pr_info("Bootloader Family = 0x%04X\n", bootldr_family);
+
+        switch (bootldr_family) {
+        case BOOTLDRFAMILY('R', '1'):
+                platform_family = FAMILY_1500;
+                break;
+        case BOOTLDRFAMILY('4', '4'):
+                platform_family = FAMILY_4500;
+                break;
+        case BOOTLDRFAMILY('4', '6'):
+                platform_family = FAMILY_4600;
+                break;
+        case BOOTLDRFAMILY('A', '1'):
+                platform_family = FAMILY_4600VZA;
+                break;
+        case BOOTLDRFAMILY('8', '5'):
+                platform_family = FAMILY_8500;
+                break;
+        case BOOTLDRFAMILY('R', '2'):
+                platform_family = FAMILY_8500RNG;
+                break;
+        case BOOTLDRFAMILY('8', '6'):
+                platform_family = FAMILY_8600;
+                break;
+        case BOOTLDRFAMILY('B', '1'):
+                platform_family = FAMILY_8600VZB;
+                break;
+        case BOOTLDRFAMILY('E', '1'):
+                platform_family = FAMILY_1500VZE;
+                break;
+        case BOOTLDRFAMILY('F', '1'):
+                platform_family = FAMILY_1500VZF;
+                break;
+        default:
+                platform_family = -1;
+        }
+}
+
+unsigned int platform_get_family(void)
+{
+        return platform_family;
+}
+EXPORT_SYMBOL(platform_get_family);
+
+/*
+ * \brief usb_eye_configure() for optimizing the USB eye on Calliope.
+ *
+ * \param     unsigned int value saved to the register.
+ *
+ * \return    none
+ *
+ */
+static void __init usb_eye_configure(unsigned int value)
+{
+        asic_write(asic_read(crt_spare) | value, crt_spare);
+}
+
+/*
+ * platform_get_asic - determine the ASIC type.
+ *
+ * \param     none
+ *
+ * \return    ASIC type; ASIC_UNKNOWN if none
+ *
+ */
+enum asic_type platform_get_asic(void)
+{
+        return asic;
+}
+EXPORT_SYMBOL(platform_get_asic);
+
+/*
+ * platform_configure_usb - usb configuration based on platform type.
+ * @bcm1_usb2_ctl:      value for the BCM1_USB2_CTL register, which is
+ *                      quirky
+ */
+static void __init platform_configure_usb(void)
+{
+        u32 bcm1_usb2_ctl;
+
+        if (usb_configured)
+                return;
+
+        switch (asic) {
+        case ASIC_ZEUS:
+                fs_update(0x0000, 0x11, 0x02, 0);
+                bcm1_usb2_ctl = 0x803;
+                break;
+
+        case ASIC_CRONUS:
+        case ASIC_CRONUSLITE:
+                fs_update(0x0000, 0x11, 0x02, 0);
+                bcm1_usb2_ctl = 0x803;
+                break;
+
+        case ASIC_CALLIOPE:
+                fs_update(0x0000, 0x11, 0x02, 1);
+
+                switch (platform_family) {
+                case FAMILY_1500VZE:
+                        break;
+
+                case FAMILY_1500VZF:
+                        usb_eye_configure(0x003c0000);
+                        break;
+
+                default:
+                        usb_eye_configure(0x00300000);
+                        break;
+                }
+
+                bcm1_usb2_ctl = 0x803;
+                break;
+
+        default:
+                pr_err("Unknown ASIC type: %d\n", asic);
+                break;
+        }
+
+        /* turn on USB power */
+        asic_write(0, usb2_strap);
+        /* Enable all OHCI interrupts */
+        asic_write(bcm1_usb2_ctl, usb2_control);
+        /* USB2_STBUS_OBC store32/load32 */
+        asic_write(3, usb2_stbus_obc);
+        /* USB2_STBUS_MESS_SIZE 2 packets */
+        asic_write(1, usb2_stbus_mess_size);
+        /* USB2_STBUS_CHUNK_SIZE 2 packets */
+        asic_write(1, usb2_stbus_chunk_size);
+
+        usb_configured = true;
+}
+
+/*
+ * Set up the USB EHCI interface
+ */
+void platform_configure_usb_ehci()
+{
+        platform_configure_usb();
+}
+
+/*
+ * Set up the USB OHCI interface
+ */
+void platform_configure_usb_ohci()
+{
+        platform_configure_usb();
+}
+
+/*
+ * Shut the USB EHCI interface down--currently a NOP
+ */
+void platform_unconfigure_usb_ehci()
+{
+}
+
+/*
+ * Shut the USB OHCI interface down--currently a NOP
+ */
+void platform_unconfigure_usb_ohci()
+{
+}
+
+/**
+ * configure_platform - configuration based on platform type.
+ */
+void __init configure_platform(void)
+{
+        platform_set_family();
+
+        switch (platform_family) {
+        case FAMILY_1500:
+        case FAMILY_1500VZE:
+        case FAMILY_1500VZF:
+                platform_features = FFS_CAPABLE;
+                asic = ASIC_CALLIOPE;
+                asic_phy_base = CALLIOPE_IO_BASE;
+                register_map = &calliope_register_map;
+                asic_base = (unsigned long)ioremap_nocache(asic_phy_base,
+                        ASIC_IO_SIZE);
+
+                if (platform_family == FAMILY_1500VZE) {
+                        gp_resources = non_dvr_vze_calliope_resources;
+                        pr_info("Platform: 1500/Vz Class E - "
+                                "CALLIOPE, NON_DVR_CAPABLE\n");
+                } else if (platform_family == FAMILY_1500VZF) {
+                        gp_resources = non_dvr_vzf_calliope_resources;
+                        pr_info("Platform: 1500/Vz Class F - "
+                                "CALLIOPE, NON_DVR_CAPABLE\n");
+                } else {
+                        gp_resources = non_dvr_calliope_resources;
+                        pr_info("Platform: 1500/RNG100 - CALLIOPE, "
+                                "NON_DVR_CAPABLE\n");
+                }
+                break;
+
+        case FAMILY_4500:
+                platform_features = FFS_CAPABLE | PCIE_CAPABLE |
+                        DISPLAY_CAPABLE;
+                asic = ASIC_ZEUS;
+                asic_phy_base = ZEUS_IO_BASE;
+                register_map = &zeus_register_map;
+                asic_base = (unsigned long)ioremap_nocache(asic_phy_base,
+                        ASIC_IO_SIZE);
+                gp_resources = non_dvr_zeus_resources;
+
+                pr_info("Platform: 4500 - ZEUS, NON_DVR_CAPABLE\n");
+                break;
+
+        case FAMILY_4600:
+        {
+                unsigned int chipversion = 0;
+
+                /* The settop has PCIE but it isn't used, so don't advertise
+                 * it*/
+                platform_features = FFS_CAPABLE | DISPLAY_CAPABLE;
+                asic_phy_base = CRONUS_IO_BASE;   /* same as Cronus */
+                register_map = &cronus_register_map;   /* same as Cronus */
+                asic_base = (unsigned long)ioremap_nocache(asic_phy_base,
+                        ASIC_IO_SIZE);
+                gp_resources = non_dvr_cronuslite_resources;
+
+                /* ASIC version will determine if this is a real CronusLite or
+                 * Castrati(Cronus) */
+                chipversion  = asic_read(chipver3) << 24;
+                chipversion |= asic_read(chipver2) << 16;
+                chipversion |= asic_read(chipver1) << 8;
+                chipversion |= asic_read(chipver0);
+
+                if ((chipversion == CRONUS_10) || (chipversion == CRONUS_11))
+                        asic = ASIC_CRONUS;
+                else
+                        asic = ASIC_CRONUSLITE;
+
+                pr_info("Platform: 4600 - %s, NON_DVR_CAPABLE, "
+                        "chipversion=0x%08X\n",
+                        (asic == ASIC_CRONUS) ? "CRONUS" : "CRONUS LITE",
+                        chipversion);
+                break;
+        }
+        case FAMILY_4600VZA:
+                platform_features = FFS_CAPABLE | DISPLAY_CAPABLE;
+                asic = ASIC_CRONUS;
+                asic_phy_base = CRONUS_IO_BASE;
+                register_map = &cronus_register_map;
+                asic_base = (unsigned long)ioremap_nocache(asic_phy_base,
+                        ASIC_IO_SIZE);
+                gp_resources = non_dvr_cronus_resources;
+
+                pr_info("Platform: Vz Class A - CRONUS, NON_DVR_CAPABLE\n");
+                break;
+
+        case FAMILY_8500:
+        case FAMILY_8500RNG:
+                platform_features = DVR_CAPABLE | PCIE_CAPABLE |
+                        DISPLAY_CAPABLE;
+                asic = ASIC_ZEUS;
+                asic_phy_base = ZEUS_IO_BASE;
+                register_map = &zeus_register_map;
+                asic_base = (unsigned long)ioremap_nocache(asic_phy_base,
+                        ASIC_IO_SIZE);
+                gp_resources = dvr_zeus_resources;
+
+                pr_info("Platform: 8500/RNG200 - ZEUS, DVR_CAPABLE\n");
+                break;
+
+        case FAMILY_8600:
+        case FAMILY_8600VZB:
+                platform_features = DVR_CAPABLE | PCIE_CAPABLE |
+                        DISPLAY_CAPABLE;
+                asic = ASIC_CRONUS;
+                asic_phy_base = CRONUS_IO_BASE;
+                register_map = &cronus_register_map;
+                asic_base = (unsigned long)ioremap_nocache(asic_phy_base,
+                        ASIC_IO_SIZE);
+                gp_resources = dvr_cronus_resources;
+
+                pr_info("Platform: 8600/Vz Class B - CRONUS, "
+                        "DVR_CAPABLE\n");
+                break;
+
+        default:
+                pr_crit("Platform:  UNKNOWN PLATFORM\n");
+                break;
+        }
+
+        switch (asic) {
+        case ASIC_ZEUS:
+                phys_to_bus_offset = 0x30000000;
+                break;
+        case ASIC_CALLIOPE:
+                phys_to_bus_offset = 0x10000000;
+                break;
+        case ASIC_CRONUSLITE:
+                /* Fall through */
+        case ASIC_CRONUS:
+                /*
+                 * TODO: We suppose 0x10000000 aliases into 0x20000000-
+                 * 0x2XXXXXXX. If 0x10000000 aliases into 0x60000000-
+                 * 0x6XXXXXXX, the offset should be 0x50000000, not 0x10000000.
+                 */
+                phys_to_bus_offset = 0x10000000;
+                break;
+        default:
+                phys_to_bus_offset = 0x00000000;
+                break;
+        }
+}
+
+/**
+ * platform_devices_init - sets up USB device resourse.
+ */
+static int __init platform_devices_init(void)
+{
+        pr_notice("%s: ----- Initializing USB resources -----\n", __func__);
+
+        asic_resource.start = asic_phy_base;
+        asic_resource.end += asic_resource.start;
+
+        ehci_resources[0].start = asic_reg_phys_addr(ehci_hcapbase);
+        ehci_resources[0].end += ehci_resources[0].start;
+
+        ohci_resources[0].start = asic_reg_phys_addr(ohci_hc_revision);
+        ohci_resources[0].end += ohci_resources[0].start;
+
+        set_io_port_base(0);
+
+        platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
+
+        return 0;
+}
+
+arch_initcall(platform_devices_init);
+
+/*
+ *
+ * BOOTMEM ALLOCATION
+ *
+ */
+/*
+ * Allocates/reserves the Platform memory resources early in the boot process.
+ * This ignores any resources that are designated IORESOURCE_IO
+ */
+void __init platform_alloc_bootmem(void)
+{
+        int i;
+        int total = 0;
+
+        /* Get persistent memory data from command line before allocating
+         * resources. This need to happen before normal command line parsing
+         * has been done */
+        pmem_setup_resource();
+
+        /* Loop through looking for resources that want a particular address */
+        for (i = 0; gp_resources[i].flags != 0; i++) {
+                int size = gp_resources[i].end - gp_resources[i].start + 1;
+                if ((gp_resources[i].start != 0) &&
+                        ((gp_resources[i].flags & IORESOURCE_MEM) != 0)) {
+                        reserve_bootmem(bus_to_phys(gp_resources[i].start),
+                                size, 0);
+                        total += gp_resources[i].end -
+                                gp_resources[i].start + 1;
+                        pr_info("reserve resource %s at %08x (%u bytes)\n",
+                                gp_resources[i].name, gp_resources[i].start,
+                                gp_resources[i].end -
+                                        gp_resources[i].start + 1);
+                }
+        }
+
+        /* Loop through assigning addresses for those that are left */
+        for (i = 0; gp_resources[i].flags != 0; i++) {
+                int size = gp_resources[i].end - gp_resources[i].start + 1;
+                if ((gp_resources[i].start == 0) &&
+                        ((gp_resources[i].flags & IORESOURCE_MEM) != 0)) {
+                        void *mem = alloc_bootmem_pages(size);
+
+                        if (mem == NULL)
+                                pr_err("Unable to allocate bootmem pages "
+                                        "for %s\n", gp_resources[i].name);
+
+                        else {
+                                gp_resources[i].start =
+                                        phys_to_bus(virt_to_phys(mem));
+                                gp_resources[i].end =
+                                        gp_resources[i].start + size - 1;
+                                total += size;
+                                pr_info("allocate resource %s at %08x "
+                                                "(%u bytes)\n",
+                                        gp_resources[i].name,
+                                        gp_resources[i].start, size);
+                        }
+                }
+        }
+
+        pr_info("Total Platform driver memory allocation: 0x%08x\n", total);
+
+        /* indicate resources that are platform I/O related */
+        for (i = 0; gp_resources[i].flags != 0; i++) {
+                if ((gp_resources[i].start != 0) &&
+                        ((gp_resources[i].flags & IORESOURCE_IO) != 0)) {
+                        pr_info("reserved platform resource %s at %08x\n",
+                                gp_resources[i].name, gp_resources[i].start);
+                }
+        }
+}
+
+/*
+ *
+ * PERSISTENT MEMORY (PMEM) CONFIGURATION
+ *
+ */
+static unsigned long pmemaddr __initdata;
+
+static int __init early_param_pmemaddr(char *p)
+{
+        pmemaddr = (unsigned long)simple_strtoul(p, NULL, 0);
+        return 0;
+}
+early_param("pmemaddr", early_param_pmemaddr);
+
+static long pmemlen __initdata;
+
+static int __init early_param_pmemlen(char *p)
+{
+/* TODO: we can use this code when and if the bootloader ever changes this */
+#if 0
+        pmemlen = (unsigned long)simple_strtoul(p, NULL, 0);
+#else
+        pmemlen = 0x20000;
+#endif
+        return 0;
+}
+early_param("pmemlen", early_param_pmemlen);
+
+/*
+ * Set up persistent memory. If we were given values, we patch the array of
+ * resources. Otherwise, persistent memory may be allocated anywhere at all.
+ */
+static void __init pmem_setup_resource(void)
+{
+        struct resource *resource;
+        resource = asic_resource_get("DiagPersistentMemory");
+
+        if (resource && pmemaddr && pmemlen) {
+                /* The address provided by bootloader is in kseg0. Convert to
+                 * a bus address. */
+                resource->start = phys_to_bus(pmemaddr - 0x80000000);
+                resource->end = resource->start + pmemlen - 1;
+
+                pr_info("persistent memory: start=0x%x  end=0x%x\n",
+                        resource->start, resource->end);
+        }
+}
+
+/*
+ *
+ * RESOURCE ACCESS FUNCTIONS
+ *
+ */
+
+/**
+ * asic_resource_get - retrieves parameters for a platform resource.
+ * @name:       string to match resource
+ *
+ * Returns a pointer to a struct resource corresponding to the given name.
+ *
+ * CANNOT BE NAMED platform_resource_get, which would be the obvious choice,
+ * as this function name is already declared
+ */
+struct resource *asic_resource_get(const char *name)
+{
+        int i;
+
+        for (i = 0; gp_resources[i].flags != 0; i++) {
+                if (strcmp(gp_resources[i].name, name) == 0)
+                        return &gp_resources[i];
+        }
+
+        return NULL;
+}
+EXPORT_SYMBOL(asic_resource_get);
+
+/**
+ * platform_release_memory - release pre-allocated memory
+ * @ptr:        pointer to memory to release
+ * @size:       size of resource
+ *
+ * This must only be called for memory allocated or reserved via the boot
+ * memory allocator.
+ */
+void platform_release_memory(void *ptr, int size)
+{
+        unsigned long addr;
+        unsigned long end;
+
+        addr = ((unsigned long)ptr + (PAGE_SIZE - 1)) & PAGE_MASK;
+        end = ((unsigned long)ptr + size) & PAGE_MASK;
+
+        for (; addr < end; addr += PAGE_SIZE) {
+                ClearPageReserved(virt_to_page(__va(addr)));
+                init_page_count(virt_to_page(__va(addr)));
+                free_page((unsigned long)__va(addr));
+        }
+}
+EXPORT_SYMBOL(platform_release_memory);
+
+/*
+ *
+ * FEATURE AVAILABILITY FUNCTIONS
+ *
+ */
+int platform_supports_dvr(void)
+{
+        return (platform_features & DVR_CAPABLE) != 0;
+}
+
+int platform_supports_ffs(void)
+{
+        return (platform_features & FFS_CAPABLE) != 0;
+}
+
+int platform_supports_pcie(void)
+{
+        return (platform_features & PCIE_CAPABLE) != 0;
+}
+
+int platform_supports_display(void)
+{
+        return (platform_features & DISPLAY_CAPABLE) != 0;
+}
diff --git a/arch/mips/powertv/asic/asic_int.c b/arch/mips/powertv/asic/asic_int.c
new file mode 100644
index 000000000000..80b2eed21ac3
--- /dev/null
+++ b/arch/mips/powertv/asic/asic_int.c
@@ -0,0 +1,125 @@
+/*
+ * Carsten Langgaard, carstenl@mips.com
+ * Copyright (C) 2000, 2001, 2004 MIPS Technologies, Inc.
+ * Copyright (C) 2001 Ralf Baechle
+ * Portions copyright (C) 2009  Cisco Systems, Inc.
+ *
+ *  This program is free software; you can distribute it and/or modify it
+ *  under the terms of the GNU General Public License (Version 2) as
+ *  published by the Free Software Foundation.
+ *
+ *  This program is distributed in the hope it will be useful, but WITHOUT
+ *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ *  for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
+ *
+ * Routines for generic manipulation of the interrupts found on the PowerTV
+ * platform.
+ *
+ * The interrupt controller is located in the South Bridge a PIIX4 device
+ * with two internal 82C95 interrupt controllers.
+ */
+#include <linux/init.h>
+#include <linux/irq.h>
+#include <linux/sched.h>
+#include <linux/slab.h>
+#include <linux/interrupt.h>
+#include <linux/kernel_stat.h>
+#include <linux/kernel.h>
+#include <linux/random.h>
+
+#include <asm/irq_cpu.h>
+#include <linux/io.h>
+#include <asm/irq_regs.h>
+#include <asm/mips-boards/generic.h>
+
+#include <asm/mach-powertv/asic_regs.h>
+
+static DEFINE_SPINLOCK(asic_irq_lock);
+
+static inline int get_int(void)
+{
+        unsigned long flags;
+        int irq;
+
+        spin_lock_irqsave(&asic_irq_lock, flags);
+
+        irq = (asic_read(int_int_scan) >> 4) - 1;
+
+        if (irq == 0 || irq >= NR_IRQS)
+                irq = -1;
+
+        spin_unlock_irqrestore(&asic_irq_lock, flags);
+
+        return irq;
+}
+
+static void asic_irqdispatch(void)
+{
+        int irq;
+
+        irq = get_int();
+        if (irq < 0)
+                return;  /* interrupt has already been cleared */
+
+        do_IRQ(irq);
+}
+
+static inline int clz(unsigned long x)
+{
+        __asm__(
+        "       .set    push                                    \n"
+        "       .set    mips32                                  \n"
+        "       clz     %0, %1                                  \n"
+        "       .set    pop                                     \n"
+        : "=r" (x)
+        : "r" (x));
+
+        return x;
+}
+
+/*
+ * Version of ffs that only looks at bits 12..15.
+ */
+static inline unsigned int irq_ffs(unsigned int pending)
+{
+        return fls(pending) - 1 + CAUSEB_IP;
+}
+
+/*
+ * TODO: check how it works under EIC mode.
+ */
+asmlinkage void plat_irq_dispatch(void)
+{
+        unsigned int pending = read_c0_cause() & read_c0_status() & ST0_IM;
+        int irq;
+
+        irq = irq_ffs(pending);
+
+        if (irq == CAUSEF_IP3)
+                asic_irqdispatch();
+        else if (irq >= 0)
+                do_IRQ(irq);
+        else
+                spurious_interrupt();
+}
+
+void __init arch_init_irq(void)
+{
+        int i;
+
+        asic_irq_init();
+
+        /*
+         * Initialize interrupt exception vectors.
+         */
+        if (cpu_has_veic || cpu_has_vint) {
+                int nvec = cpu_has_veic ? 64 : 8;
+                for (i = 0; i < nvec; i++)
+                        set_vi_handler(i, asic_irqdispatch);
+        }
+}
diff --git a/arch/mips/powertv/asic/irq_asic.c b/arch/mips/powertv/asic/irq_asic.c
new file mode 100644
index 000000000000..b54d24499b06
--- /dev/null
+++ b/arch/mips/powertv/asic/irq_asic.c
@@ -0,0 +1,116 @@
+/*
+ * Portions copyright (C) 2005-2009 Scientific Atlanta
+ * Portions copyright (C) 2009 Cisco Systems, Inc.
+ *
+ * Modified from arch/mips/kernel/irq-rm7000.c:
+ * Copyright (C) 2003 Ralf Baechle
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/kernel.h>
+
+#include <asm/irq_cpu.h>
+#include <asm/mipsregs.h>
+#include <asm/system.h>
+
+#include <asm/mach-powertv/asic_regs.h>
+
+static inline void unmask_asic_irq(unsigned int irq)
+{
+        unsigned long enable_bit;
+
+        enable_bit = (1 << (irq & 0x1f));
+
+        switch (irq >> 5) {
+        case 0:
+                asic_write(asic_read(ien_int_0) | enable_bit, ien_int_0);
+                break;
+        case 1:
+                asic_write(asic_read(ien_int_1) | enable_bit, ien_int_1);
+                break;
+        case 2:
+                asic_write(asic_read(ien_int_2) | enable_bit, ien_int_2);
+                break;
+        case 3:
+                asic_write(asic_read(ien_int_3) | enable_bit, ien_int_3);
+                break;
+        default:
+                BUG();
+        }
+}
+
+static inline void mask_asic_irq(unsigned int irq)
+{
+        unsigned long disable_mask;
+
+        disable_mask = ~(1 << (irq & 0x1f));
+
+        switch (irq >> 5) {
+        case 0:
+                asic_write(asic_read(ien_int_0) & disable_mask, ien_int_0);
+                break;
+        case 1:
+                asic_write(asic_read(ien_int_1) & disable_mask, ien_int_1);
+                break;
+        case 2:
+                asic_write(asic_read(ien_int_2) & disable_mask, ien_int_2);
+                break;
+        case 3:
+                asic_write(asic_read(ien_int_3) & disable_mask, ien_int_3);
+                break;
+        default:
+                BUG();
+        }
+}
+
+static struct irq_chip asic_irq_chip = {
+        .name = "ASIC Level",
+        .ack = mask_asic_irq,
+        .mask = mask_asic_irq,
+        .mask_ack = mask_asic_irq,
+        .unmask = unmask_asic_irq,
+        .eoi = unmask_asic_irq,
+};
+
+void __init asic_irq_init(void)
+{
+        int i;
+
+        /* set priority to 0 */
+        write_c0_status(read_c0_status() & ~(0x0000fc00));
+
+        asic_write(0, ien_int_0);
+        asic_write(0, ien_int_1);
+        asic_write(0, ien_int_2);
+        asic_write(0, ien_int_3);
+
+        asic_write(0x0fffffff, int_level_3_3);
+        asic_write(0xffffffff, int_level_3_2);
+        asic_write(0xffffffff, int_level_3_1);
+        asic_write(0xffffffff, int_level_3_0);
+        asic_write(0xffffffff, int_level_2_3);
+        asic_write(0xffffffff, int_level_2_2);
+        asic_write(0xffffffff, int_level_2_1);
+        asic_write(0xffffffff, int_level_2_0);
+        asic_write(0xffffffff, int_level_1_3);
+        asic_write(0xffffffff, int_level_1_2);
+        asic_write(0xffffffff, int_level_1_1);
+        asic_write(0xffffffff, int_level_1_0);
+        asic_write(0xffffffff, int_level_0_3);
+        asic_write(0xffffffff, int_level_0_2);
+        asic_write(0xffffffff, int_level_0_1);
+        asic_write(0xffffffff, int_level_0_0);
+
+        asic_write(0xf, int_int_scan);
+
+        /*
+         * Initialize interrupt handlers.
+         */
+        for (i = 0; i < NR_IRQS; i++)
+                set_irq_chip_and_handler(i, &asic_irq_chip, handle_level_irq);
+}
diff --git a/arch/mips/powertv/asic/prealloc-calliope.c b/arch/mips/powertv/asic/prealloc-calliope.c
new file mode 100644
index 000000000000..cd5b76a1c951
--- /dev/null
+++ b/arch/mips/powertv/asic/prealloc-calliope.c
@@ -0,0 +1,620 @@
+/*
+ * Memory pre-allocations for Calliope boxes.
+ *
+ * Copyright (C) 2005-2009 Scientific-Atlanta, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ *
+ * Author:       Ken Eppinett
+ *               David Schleef <ds@schleef.org>
+ */
+
+#include <linux/init.h>
+#include <asm/mach-powertv/asic.h>
+
+/*
+ * NON_DVR_CAPABLE CALLIOPE RESOURCES
+ */
+struct resource non_dvr_calliope_resources[] __initdata =
+{
+        /*
+         * VIDEO / LX1
+         */
+        {
+                .name   = "ST231aImage",        /* Delta-Mu 1 image and ram */
+                .start  = 0x24000000,
+                .end    = 0x24200000 - 1,       /*2MiB */
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .name   = "ST231aMonitor",   /*8KiB block ST231a monitor */
+                .start  = 0x24200000,
+                .end    = 0x24202000 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .name   = "MediaMemory1",
+                .start  = 0x24202000,
+                .end    = 0x26700000 - 1, /*~36.9MiB (32MiB - (2MiB + 8KiB)) */
+                .flags  = IORESOURCE_MEM,
+        },
+        /*
+         * Sysaudio Driver
+         */
+        {
+                .name   = "DSP_Image_Buff",
+                .start  = 0x00000000,
+                .end    = 0x000FFFFF,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .name   = "ADSC_CPU_PCM_Buff",
+                .start  = 0x00000000,
+                .end    = 0x00009FFF,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .name   = "ADSC_AUX_Buff",
+                .start  = 0x00000000,
+                .end    = 0x00003FFF,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .name   = "ADSC_Main_Buff",
+                .start  = 0x00000000,
+                .end    = 0x00003FFF,
+                .flags  = IORESOURCE_MEM,
+        },
+        /*
+         * STAVEM driver/STAPI
+         */
+        {
+                .name   = "AVMEMPartition0",
+                .start  = 0x00000000,
+                .end    = 0x00600000 - 1,       /* 6 MB total */
+                .flags  = IORESOURCE_MEM,
+        },
+        /*
+         * DOCSIS Subsystem
+         */
+        {
+                .name   = "Docsis",
+                .start  = 0x22000000,
+                .end    = 0x22700000 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        /*
+         * GHW HAL Driver
+         */
+        {
+                .name   = "GraphicsHeap",
+                .start  = 0x22700000,
+                .end    = 0x23500000 - 1,       /* 14 MB total */
+                .flags  = IORESOURCE_MEM,
+        },
+        /*
+         * multi com buffer area
+         */
+        {
+                .name   = "MulticomSHM",
+                .start  = 0x23700000,
+                .end    = 0x23720000 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        /*
+         * DMA Ring buffer (don't need recording buffers)
+         */
+        {
+                .name   = "BMM_Buffer",
+                .start  = 0x00000000,
+                .end    = 0x000AA000 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        /*
+         * Display bins buffer for unit0
+         */
+        {
+                .name   = "DisplayBins0",
+                .start  = 0x00000000,
+                .end    = 0x00000FFF,           /* 4 KB total */
+                .flags  = IORESOURCE_MEM,
+        },
+        /*
+         *
+         * AVFS: player HAL memory
+         *
+         *
+         */
+        {
+                .name   = "AvfsDmaMem",
+                .start  = 0x00000000,
+                .end    = 0x002c4c00 - 1,       /* 945K * 3 for playback */
+                .flags  = IORESOURCE_MEM,
+        },
+        /*
+         * PMEM
+         */
+        {
+                .name   = "DiagPersistentMemory",
+                .start  = 0x00000000,
+                .end    = 0x10000 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        /*
+         * Smartcard
+         */
+        {
+                .name   = "SmartCardInfo",
+                .start  = 0x00000000,
+                .end    = 0x2800 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        /*
+         * NAND Flash
+         */
+        {
+                .name   = "NandFlash",
+                .start  = NAND_FLASH_BASE,
+                .end    = NAND_FLASH_BASE + 0x400 - 1,
+                .flags  = IORESOURCE_IO,
+        },
+        /*
+         * Synopsys GMAC Memory Region
+         */
+        {
+                .name   = "GMAC",
+                .start  = 0x00000000,
+                .end    = 0x00010000 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        /*
+         * Add other resources here
+         *
+         */
+        { },
+};
+
+struct resource non_dvr_vz_calliope_resources[] __initdata =
+{
+        /*
+         * VIDEO / LX1
+         */
+        {
+                .name   = "ST231aImage",        /* Delta-Mu 1 image and ram */
+                .start  = 0x24000000,
+                .end    = 0x24200000 - 1, /*2 Meg */
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .name   = "ST231aMonitor",      /* 8k block ST231a monitor */
+                .start  = 0x24200000,
+                .end    = 0x24202000 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .name   = "MediaMemory1",
+                .start  = 0x22202000,
+                .end    = 0x22C20B85 - 1,       /* 10.12 Meg */
+                .flags  = IORESOURCE_MEM,
+        },
+        /*
+         * Sysaudio Driver
+         */
+        {
+                .name   = "DSP_Image_Buff",
+                .start  = 0x00000000,
+                .end    = 0x000FFFFF,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .name   = "ADSC_CPU_PCM_Buff",
+                .start  = 0x00000000,
+                .end    = 0x00009FFF,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .name   = "ADSC_AUX_Buff",
+                .start  = 0x00000000,
+                .end    = 0x00003FFF,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .name   = "ADSC_Main_Buff",
+                .start  = 0x00000000,
+                .end    = 0x00003FFF,
+                .flags  = IORESOURCE_MEM,
+        },
+        /*
+         * STAVEM driver/STAPI
+         */
+        {
+                .name   = "AVMEMPartition0",
+                .start  = 0x20300000,
+                .end    = 0x20620000-1,  /*3.125 MB total */
+                .flags  = IORESOURCE_MEM,
+        },
+        /*
+         * GHW HAL Driver
+         */
+        {
+                .name   = "GraphicsHeap",
+                .start  = 0x20100000,
+                .end    = 0x20300000 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        /*
+         * multi com buffer area
+         */
+        {
+                .name   = "MulticomSHM",
+                .start  = 0x23900000,
+                .end    = 0x23920000 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        /*
+         * DMA Ring buffer
+         */
+        {
+                .name   = "BMM_Buffer",
+                .start  = 0x00000000,
+                .end    = 0x000AA000 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        /*
+         * Display bins buffer for unit0
+         */
+        {
+                .name   = "DisplayBins0",
+                .start  = 0x00000000,
+                .end    = 0x00000FFF,
+                .flags  = IORESOURCE_MEM,
+        },
+        /*
+         * PMEM
+         */
+        {
+                .name   = "DiagPersistentMemory",
+                .start  = 0x00000000,
+                .end    = 0x10000 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        /*
+         * Smartcard
+         */
+        {
+                .name   = "SmartCardInfo",
+                .start  = 0x00000000,
+                .end    = 0x2800 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        /*
+         * NAND Flash
+         */
+        {
+                .name   = "NandFlash",
+                .start  = NAND_FLASH_BASE,
+                .end    = NAND_FLASH_BASE+0x400 - 1,
+                .flags  = IORESOURCE_IO,
+        },
+        /*
+         * Synopsys GMAC Memory Region
+         */
+        {
+                .name   = "GMAC",
+                .start  = 0x00000000,
+                .end    = 0x00010000 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        /*
+         * Add other resources here
+         */
+        { },
+};
+
+struct resource non_dvr_vze_calliope_resources[] __initdata =
+{
+        /*
+         * VIDEO / LX1
+         */
+        {
+                .name   = "ST231aImage",        /* Delta-Mu 1 image and ram */
+                .start  = 0x22000000,
+                .end    = 0x22200000 - 1,       /*2  Meg */
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .name   = "ST231aMonitor",      /* 8k block ST231a monitor */
+                .start  = 0x22200000,
+                .end    = 0x22202000 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .name   = "MediaMemory1",
+                .start  = 0x22202000,
+                .end    = 0x22C20B85 - 1,       /* 10.12 Meg */
+                .flags  = IORESOURCE_MEM,
+        },
+        /*
+         * Sysaudio Driver
+         */
+        {
+                .name   = "DSP_Image_Buff",
+                .start  = 0x00000000,
+                .end    = 0x000FFFFF,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .name   = "ADSC_CPU_PCM_Buff",
+                .start  = 0x00000000,
+                .end    = 0x00009FFF,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .name   = "ADSC_AUX_Buff",
+                .start  = 0x00000000,
+                .end    = 0x00003FFF,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .name   = "ADSC_Main_Buff",
+                .start  = 0x00000000,
+                .end    = 0x00003FFF,
+                .flags  = IORESOURCE_MEM,
+        },
+        /*
+         * STAVEM driver/STAPI
+         */
+        {
+                .name   = "AVMEMPartition0",
+                .start  = 0x20396000,
+                .end    = 0x206B6000 - 1,               /* 3.125 MB total */
+                .flags  = IORESOURCE_MEM,
+        },
+        /*
+         * GHW HAL Driver
+         */
+        {
+                .name   = "GraphicsHeap",
+                .start  = 0x20100000,
+                .end    = 0x20396000 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        /*
+         * multi com buffer area
+         */
+        {
+                .name   = "MulticomSHM",
+                .start  = 0x206B6000,
+                .end    = 0x206D6000 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        /*
+         * DMA Ring buffer
+         */
+        {
+                .name   = "BMM_Buffer",
+                .start  = 0x00000000,
+                .end    = 0x000AA000 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        /*
+         * Display bins buffer for unit0
+         */
+        {
+                .name   = "DisplayBins0",
+                .start  = 0x00000000,
+                .end    = 0x00000FFF,
+                .flags  = IORESOURCE_MEM,
+        },
+        /*
+         * PMEM
+         */
+        {
+                .name   = "DiagPersistentMemory",
+                .start  = 0x00000000,
+                .end    = 0x10000 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        /*
+         * Smartcard
+         */
+        {
+                .name   = "SmartCardInfo",
+                .start  = 0x00000000,
+                .end    = 0x2800 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        /*
+         * NAND Flash
+         */
+        {
+                .name   = "NandFlash",
+                .start  = NAND_FLASH_BASE,
+                .end    = NAND_FLASH_BASE+0x400 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        /*
+         * Synopsys GMAC Memory Region
+         */
+        {
+                .name   = "GMAC",
+                .start  = 0x00000000,
+                .end    = 0x00010000 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        /*
+         * Add other resources here
+         */
+        { },
+};
+
+struct resource non_dvr_vzf_calliope_resources[] __initdata =
+{
+        /*
+         * VIDEO / LX1
+         */
+        {
+                .name   = "ST231aImage",        /*Delta-Mu 1 image and ram */
+                .start  = 0x24000000,
+                .end    = 0x24200000 - 1,       /*2MiB */
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .name   = "ST231aMonitor",      /*8KiB block ST231a monitor */
+                .start  = 0x24200000,
+                .end    = 0x24202000 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .name   = "MediaMemory1",
+                .start  = 0x24202000,
+                /* ~19.4 (21.5MiB - (2MiB + 8KiB)) */
+                .end    = 0x25580000 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        /*
+         * Sysaudio Driver
+         */
+        {
+                .name   = "DSP_Image_Buff",
+                .start  = 0x00000000,
+                .end    = 0x000FFFFF,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .name   = "ADSC_CPU_PCM_Buff",
+                .start  = 0x00000000,
+                .end    = 0x00009FFF,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .name   = "ADSC_AUX_Buff",
+                .start  = 0x00000000,
+                .end    = 0x00003FFF,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .name   = "ADSC_Main_Buff",
+                .start  = 0x00000000,
+                .end    = 0x00003FFF,
+                .flags  = IORESOURCE_MEM,
+        },
+        /*
+         * STAVEM driver/STAPI
+         */
+        {
+                .name   = "AVMEMPartition0",
+                .start  = 0x00000000,
+                .end    = 0x00480000 - 1,  /* 4.5 MB total */
+                .flags  = IORESOURCE_MEM,
+        },
+        /*
+         * GHW HAL Driver
+         */
+        {
+                .name   = "GraphicsHeap",
+                .start  = 0x22700000,
+                .end    = 0x23500000 - 1, /* 14 MB total */
+                .flags  = IORESOURCE_MEM,
+        },
+        /*
+         * multi com buffer area
+         */
+        {
+                .name   = "MulticomSHM",
+                .start  = 0x23700000,
+                .end    = 0x23720000 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        /*
+         * DMA Ring buffer (don't need recording buffers)
+         */
+        {
+                .name   = "BMM_Buffer",
+                .start  = 0x00000000,
+                .end    = 0x000AA000 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        /*
+         * Display bins buffer for unit0
+         */
+        {
+                .name   = "DisplayBins0",
+                .start  = 0x00000000,
+                .end    = 0x00000FFF,  /* 4 KB total */
+                .flags  = IORESOURCE_MEM,
+        },
+        /*
+         * Display bins buffer for unit1
+         */
+        {
+                .name   = "DisplayBins1",
+                .start  = 0x00000000,
+                .end    = 0x00000FFF,  /* 4 KB total */
+                .flags  = IORESOURCE_MEM,
+        },
+        /*
+         *
+         * AVFS: player HAL memory
+         *
+         *
+         */
+        {
+                .name   = "AvfsDmaMem",
+                .start  = 0x00000000,
+                .end    = 0x002c4c00 - 1,  /* 945K * 3 for playback */
+                .flags  = IORESOURCE_MEM,
+        },
+        /*
+         * PMEM
+         */
+        {
+                .name   = "DiagPersistentMemory",
+                .start  = 0x00000000,
+                .end    = 0x10000 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        /*
+         * Smartcard
+         */
+        {
+                .name   = "SmartCardInfo",
+                .start  = 0x00000000,
+                .end    = 0x2800 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        /*
+         * NAND Flash
+         */
+        {
+                .name   = "NandFlash",
+                .start  = NAND_FLASH_BASE,
+                .end    = NAND_FLASH_BASE + 0x400 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        /*
+         * Synopsys GMAC Memory Region
+         */
+        {
+                .name   = "GMAC",
+                .start  = 0x00000000,
+                .end    = 0x00010000 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        /*
+         * Add other resources here
+         */
+        { },
+};
diff --git a/arch/mips/powertv/asic/prealloc-cronus.c b/arch/mips/powertv/asic/prealloc-cronus.c
new file mode 100644
index 000000000000..45a5c3ea718c
--- /dev/null
+++ b/arch/mips/powertv/asic/prealloc-cronus.c
@@ -0,0 +1,608 @@
+/*
+ * Memory pre-allocations for Cronus boxes.
+ *
+ * Copyright (C) 2005-2009 Scientific-Atlanta, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ *
+ * Author:       Ken Eppinett
+ *               David Schleef <ds@schleef.org>
+ */
+
+#include <linux/init.h>
+#include <asm/mach-powertv/asic.h>
+
+/*
+ * DVR_CAPABLE CRONUS RESOURCES
+ */
+struct resource dvr_cronus_resources[] __initdata =
+{
+        /*
+         *
+         * VIDEO1 / LX1
+         *
+         */
+        {
+                .name   = "ST231aImage",        /* Delta-Mu 1 image and ram */
+                .start  = 0x24000000,
+                .end    = 0x241FFFFF,           /* 2MiB */
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .name   = "ST231aMonitor",      /* 8KiB block ST231a monitor */
+                .start  = 0x24200000,
+                .end    = 0x24201FFF,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .name   = "MediaMemory1",
+                .start  = 0x24202000,
+                .end    = 0x25FFFFFF, /*~29.9MiB (32MiB - (2MiB + 8KiB)) */
+                .flags  = IORESOURCE_MEM,
+        },
+        /*
+         *
+         * VIDEO2 / LX2
+         *
+         */
+        {
+                .name   = "ST231bImage",        /* Delta-Mu 2 image and ram */
+                .start  = 0x60000000,
+                .end    = 0x601FFFFF,           /* 2MiB */
+                .flags  = IORESOURCE_IO,
+        },
+        {
+                .name   = "ST231bMonitor",      /* 8KiB block ST231b monitor */
+                .start  = 0x60200000,
+                .end    = 0x60201FFF,
+                .flags  = IORESOURCE_IO,
+        },
+        {
+                .name   = "MediaMemory2",
+                .start  = 0x60202000,
+                .end    = 0x61FFFFFF, /*~29.9MiB (32MiB - (2MiB + 8KiB)) */
+                .flags  = IORESOURCE_IO,
+        },
+        /*
+         *
+         * Sysaudio Driver
+         *
+         * This driver requires:
+         *
+         * Arbitrary Based Buffers:
+         *  DSP_Image_Buff - DSP code and data images (1MB)
+         *  ADSC_CPU_PCM_Buff - ADSC CPU PCM buffer (40KB)
+         *  ADSC_AUX_Buff - ADSC AUX buffer (16KB)
+         *  ADSC_Main_Buff - ADSC Main buffer (16KB)
+         *
+         */
+        {
+                .name   = "DSP_Image_Buff",
+                .start  = 0x00000000,
+                .end    = 0x000FFFFF,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .name   = "ADSC_CPU_PCM_Buff",
+                .start  = 0x00000000,
+                .end    = 0x00009FFF,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .name   = "ADSC_AUX_Buff",
+                .start  = 0x00000000,
+                .end    = 0x00003FFF,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .name   = "ADSC_Main_Buff",
+                .start  = 0x00000000,
+                .end    = 0x00003FFF,
+                .flags  = IORESOURCE_MEM,
+        },
+        /*
+         *
+         * STAVEM driver/STAPI
+         *
+         * This driver requires:
+         *
+         * Arbitrary Based Buffers:
+         *  This memory area is used for allocating buffers for Video decoding
+         *  purposes.  Allocation/De-allocation within this buffer is managed
+         *  by the STAVMEM driver of the STAPI.  They could be Decimated
+         *  Picture Buffers, Intermediate Buffers, as deemed necessary for
+         *  video decoding purposes, for any video decoders on Zeus.
+         *
+         */
+        {
+                .name   = "AVMEMPartition0",
+                .start  = 0x63580000,
+                .end    = 0x64180000 - 1,  /* 12 MB total */
+                .flags  = IORESOURCE_IO,
+        },
+        /*
+         *
+         * DOCSIS Subsystem
+         *
+         * This driver requires:
+         *
+         * Arbitrary Based Buffers:
+         *  Docsis -
+         *
+         */
+        {
+                .name   = "Docsis",
+                .start  = 0x62000000,
+                .end    = 0x62700000 - 1,       /* 7 MB total */
+                .flags  = IORESOURCE_IO,
+        },
+        /*
+         *
+         * GHW HAL Driver
+         *
+         * This driver requires:
+         *
+         * Arbitrary Based Buffers:
+         *  GraphicsHeap - PowerTV Graphics Heap
+         *
+         */
+        {
+                .name   = "GraphicsHeap",
+                .start  = 0x62700000,
+                .end    = 0x63500000 - 1,       /* 14 MB total */
+                .flags  = IORESOURCE_IO,
+        },
+        /*
+         *
+         * multi com buffer area
+         *
+         * This driver requires:
+         *
+         * Arbitrary Based Buffers:
+         *  Docsis -
+         *
+         */
+        {
+                .name   = "MulticomSHM",
+                .start  = 0x26000000,
+                .end    = 0x26020000 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        /*
+         *
+         * DMA Ring buffer
+         *
+         * This driver requires:
+         *
+         * Arbitrary Based Buffers:
+         *  Docsis -
+         *
+         */
+        {
+                .name   = "BMM_Buffer",
+                .start  = 0x00000000,
+                .end    = 0x00280000 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        /*
+         *
+         * Display bins buffer for unit0
+         *
+         * This driver requires:
+         *
+         * Arbitrary Based Buffers:
+         *  Display Bins for unit0
+         *
+         */
+        {
+                .name   = "DisplayBins0",
+                .start  = 0x00000000,
+                .end    = 0x00000FFF,           /* 4 KB total */
+                .flags  = IORESOURCE_MEM,
+        },
+        /*
+         *
+         * Display bins buffer
+         *
+         * This driver requires:
+         *
+         * Arbitrary Based Buffers:
+         *  Display Bins for unit1
+         *
+         */
+        {
+                .name   = "DisplayBins1",
+                .start  = 0x64AD4000,
+                .end    = 0x64AD5000 - 1,  /* 4 KB total */
+                .flags  = IORESOURCE_IO,
+        },
+        /*
+         *
+         * ITFS
+         *
+         * This driver requires:
+         *
+         * Arbitrary Based Buffers:
+         *  Docsis -
+         *
+         */
+        {
+                .name   = "ITFS",
+                .start  = 0x64180000,
+                /* 815,104 bytes each for 2 ITFS partitions. */
+                .end    = 0x6430DFFF,
+                .flags  = IORESOURCE_IO,
+        },
+        /*
+         *
+         * AVFS
+         *
+         * This driver requires:
+         *
+         * Arbitrary Based Buffers:
+         *  Docsis -
+         *
+         */
+        {
+                .name   = "AvfsDmaMem",
+                .start  = 0x6430E000,
+                /* (945K * 8) = (128K *3) 5 playbacks / 3 server */
+                .end    = 0x64AD0000 - 1,
+                .flags  = IORESOURCE_IO,
+        },
+        {
+                .name   = "AvfsFileSys",
+                .start  = 0x64AD0000,
+                .end    = 0x64AD1000 - 1,  /* 4K */
+                .flags  = IORESOURCE_IO,
+        },
+        /*
+         *
+         * PMEM
+         *
+         * This driver requires:
+         *
+         * Arbitrary Based Buffers:
+         *  Persistent memory for diagnostics.
+         *
+         */
+        {
+                .name   = "DiagPersistentMemory",
+                .start  = 0x00000000,
+                .end    = 0x10000 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        /*
+         *
+         * Smartcard
+         *
+         * This driver requires:
+         *
+         * Arbitrary Based Buffers:
+         *  Read and write buffers for Internal/External cards
+         *
+         */
+        {
+                .name   = "SmartCardInfo",
+                .start  = 0x64AD1000,
+                .end    = 0x64AD3800 - 1,
+                .flags  = IORESOURCE_IO,
+        },
+        /*
+         *
+         * KAVNET
+         *    NP Reset Vector - must be of the form xxCxxxxx
+         *         NP Image - must be video bank 1
+         *         NP IPC - must be video bank 2
+         */
+        {
+                .name   = "NP_Reset_Vector",
+                .start  = 0x27c00000,
+                .end    = 0x27c01000 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .name   = "NP_Image",
+                .start  = 0x27020000,
+                .end    = 0x27060000 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .name   = "NP_IPC",
+                .start  = 0x63500000,
+                .end    = 0x63580000 - 1,
+                .flags  = IORESOURCE_IO,
+        },
+        /*
+         * Add other resources here
+         */
+        { },
+};
+
+/*
+ * NON_DVR_CAPABLE CRONUS RESOURCES
+ */
+struct resource non_dvr_cronus_resources[] __initdata =
+{
+        /*
+         *
+         * VIDEO1 / LX1
+         *
+         */
+        {
+                .name   = "ST231aImage",        /* Delta-Mu 1 image and ram */
+                .start  = 0x24000000,
+                .end    = 0x241FFFFF,           /* 2MiB */
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .name   = "ST231aMonitor",      /* 8KiB block ST231a monitor */
+                .start  = 0x24200000,
+                .end    = 0x24201FFF,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .name   = "MediaMemory1",
+                .start  = 0x24202000,
+                .end    = 0x25FFFFFF, /*~29.9MiB (32MiB - (2MiB + 8KiB)) */
+                .flags  = IORESOURCE_MEM,
+        },
+        /*
+         *
+         * VIDEO2 / LX2
+         *
+         */
+        {
+                .name   = "ST231bImage",        /* Delta-Mu 2 image and ram */
+                .start  = 0x60000000,
+                .end    = 0x601FFFFF,           /* 2MiB */
+                .flags  = IORESOURCE_IO,
+        },
+        {
+                .name   = "ST231bMonitor",      /* 8KiB block ST231b monitor */
+                .start  = 0x60200000,
+                .end    = 0x60201FFF,
+                .flags  = IORESOURCE_IO,
+        },
+        {
+                .name   = "MediaMemory2",
+                .start  = 0x60202000,
+                .end    = 0x61FFFFFF, /*~29.9MiB (32MiB - (2MiB + 8KiB)) */
+                .flags  = IORESOURCE_IO,
+        },
+        /*
+         *
+         * Sysaudio Driver
+         *
+         * This driver requires:
+         *
+         * Arbitrary Based Buffers:
+         *  DSP_Image_Buff - DSP code and data images (1MB)
+         *  ADSC_CPU_PCM_Buff - ADSC CPU PCM buffer (40KB)
+         *  ADSC_AUX_Buff - ADSC AUX buffer (16KB)
+         *  ADSC_Main_Buff - ADSC Main buffer (16KB)
+         *
+         */
+        {
+                .name   = "DSP_Image_Buff",
+                .start  = 0x00000000,
+                .end    = 0x000FFFFF,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .name   = "ADSC_CPU_PCM_Buff",
+                .start  = 0x00000000,
+                .end    = 0x00009FFF,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .name   = "ADSC_AUX_Buff",
+                .start  = 0x00000000,
+                .end    = 0x00003FFF,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .name   = "ADSC_Main_Buff",
+                .start  = 0x00000000,
+                .end    = 0x00003FFF,
+                .flags  = IORESOURCE_MEM,
+        },
+        /*
+         *
+         * STAVEM driver/STAPI
+         *
+         * This driver requires:
+         *
+         * Arbitrary Based Buffers:
+         *  This memory area is used for allocating buffers for Video decoding
+         *  purposes.  Allocation/De-allocation within this buffer is managed
+         *  by the STAVMEM driver of the STAPI.  They could be Decimated
+         *  Picture Buffers, Intermediate Buffers, as deemed necessary for
+         *  video decoding purposes, for any video decoders on Zeus.
+         *
+         */
+        {
+                .name   = "AVMEMPartition0",
+                .start  = 0x63580000,
+                .end    = 0x64180000 - 1,  /* 12 MB total */
+                .flags  = IORESOURCE_IO,
+        },
+        /*
+         *
+         * DOCSIS Subsystem
+         *
+         * This driver requires:
+         *
+         * Arbitrary Based Buffers:
+         *  Docsis -
+         *
+         */
+        {
+                .name   = "Docsis",
+                .start  = 0x62000000,
+                .end    = 0x62700000 - 1,       /* 7 MB total */
+                .flags  = IORESOURCE_IO,
+        },
+        /*
+         *
+         * GHW HAL Driver
+         *
+         * This driver requires:
+         *
+         * Arbitrary Based Buffers:
+         *  GraphicsHeap - PowerTV Graphics Heap
+         *
+         */
+        {
+                .name   = "GraphicsHeap",
+                .start  = 0x62700000,
+                .end    = 0x63500000 - 1,       /* 14 MB total */
+                .flags  = IORESOURCE_IO,
+        },
+        /*
+         *
+         * multi com buffer area
+         *
+         * This driver requires:
+         *
+         * Arbitrary Based Buffers:
+         *  Docsis -
+         *
+         */
+        {
+                .name   = "MulticomSHM",
+                .start  = 0x26000000,
+                .end    = 0x26020000 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        /*
+         *
+         * DMA Ring buffer
+         *
+         * This driver requires:
+         *
+         * Arbitrary Based Buffers:
+         *  Docsis -
+         *
+         */
+        {
+                .name   = "BMM_Buffer",
+                .start  = 0x00000000,
+                .end    = 0x000AA000 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        /*
+         *
+         * Display bins buffer for unit0
+         *
+         * This driver requires:
+         *
+         * Arbitrary Based Buffers:
+         *  Display Bins for unit0
+         *
+         */
+        {
+                .name   = "DisplayBins0",
+                .start  = 0x00000000,
+                .end    = 0x00000FFF,           /* 4 KB total */
+                .flags  = IORESOURCE_MEM,
+        },
+        /*
+         *
+         * Display bins buffer
+         *
+         * This driver requires:
+         *
+         * Arbitrary Based Buffers:
+         *  Display Bins for unit1
+         *
+         */
+        {
+                .name   = "DisplayBins1",
+                .start  = 0x64AD4000,
+                .end    = 0x64AD5000 - 1,  /* 4 KB total */
+                .flags  = IORESOURCE_IO,
+        },
+        /*
+         *
+         * AVFS: player HAL memory
+         *
+         *
+         */
+        {
+                .name   = "AvfsDmaMem",
+                .start  = 0x6430E000,
+                .end    = 0x645D2C00 - 1,  /* 945K * 3 for playback */
+                .flags  = IORESOURCE_IO,
+        },
+        /*
+         *
+         * PMEM
+         *
+         * This driver requires:
+         *
+         * Arbitrary Based Buffers:
+         *  Persistent memory for diagnostics.
+         *
+         */
+        {
+                .name   = "DiagPersistentMemory",
+                .start  = 0x00000000,
+                .end    = 0x10000 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        /*
+         *
+         * Smartcard
+         *
+         * This driver requires:
+         *
+         * Arbitrary Based Buffers:
+         *  Read and write buffers for Internal/External cards
+         *
+         */
+        {
+                .name   = "SmartCardInfo",
+                .start  = 0x64AD1000,
+                .end    = 0x64AD3800 - 1,
+                .flags  = IORESOURCE_IO,
+        },
+        /*
+         *
+         * KAVNET
+         *    NP Reset Vector - must be of the form xxCxxxxx
+         *         NP Image - must be video bank 1
+         *         NP IPC - must be video bank 2
+         */
+        {
+                .name   = "NP_Reset_Vector",
+                .start  = 0x27c00000,
+                .end    = 0x27c01000 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .name   = "NP_Image",
+                .start  = 0x27020000,
+                .end    = 0x27060000 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .name   = "NP_IPC",
+                .start  = 0x63500000,
+                .end    = 0x63580000 - 1,
+                .flags  = IORESOURCE_IO,
+        },
+        { },
+};
diff --git a/arch/mips/powertv/asic/prealloc-cronuslite.c b/arch/mips/powertv/asic/prealloc-cronuslite.c
new file mode 100644
index 000000000000..23a905613c04
--- /dev/null
+++ b/arch/mips/powertv/asic/prealloc-cronuslite.c
@@ -0,0 +1,290 @@
+/*
+ * Memory pre-allocations for Cronus Lite boxes.
+ *
+ * Copyright (C) 2005-2009 Scientific-Atlanta, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ *
+ * Author:       Ken Eppinett
+ *               David Schleef <ds@schleef.org>
+ */
+
+#include <linux/init.h>
+#include <asm/mach-powertv/asic.h>
+
+/*
+ * NON_DVR_CAPABLE CRONUSLITE RESOURCES
+ */
+struct resource non_dvr_cronuslite_resources[] __initdata =
+{
+        /*
+         *
+         * VIDEO2 / LX2
+         *
+         */
+        {
+                .name   = "ST231aImage",        /* Delta-Mu 2 image and ram */
+                .start  = 0x60000000,
+                .end    = 0x601FFFFF,           /* 2MiB */
+                .flags  = IORESOURCE_IO,
+        },
+        {
+                .name   = "ST231aMonitor",      /* 8KiB block ST231b monitor */
+                .start  = 0x60200000,
+                .end    = 0x60201FFF,
+                .flags  = IORESOURCE_IO,
+        },
+        {
+                .name   = "MediaMemory1",
+                .start  = 0x60202000,
+                .end    = 0x61FFFFFF, /*~29.9MiB (32MiB - (2MiB + 8KiB)) */
+                .flags  = IORESOURCE_IO,
+        },
+        /*
+         *
+         * Sysaudio Driver
+         *
+         * This driver requires:
+         *
+         * Arbitrary Based Buffers:
+         *  DSP_Image_Buff - DSP code and data images (1MB)
+         *  ADSC_CPU_PCM_Buff - ADSC CPU PCM buffer (40KB)
+         *  ADSC_AUX_Buff - ADSC AUX buffer (16KB)
+         *  ADSC_Main_Buff - ADSC Main buffer (16KB)
+         *
+         */
+        {
+                .name   = "DSP_Image_Buff",
+                .start  = 0x00000000,
+                .end    = 0x000FFFFF,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .name   = "ADSC_CPU_PCM_Buff",
+                .start  = 0x00000000,
+                .end    = 0x00009FFF,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .name   = "ADSC_AUX_Buff",
+                .start  = 0x00000000,
+                .end    = 0x00003FFF,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .name   = "ADSC_Main_Buff",
+                .start  = 0x00000000,
+                .end    = 0x00003FFF,
+                .flags  = IORESOURCE_MEM,
+        },
+        /*
+         *
+         * STAVEM driver/STAPI
+         *
+         * This driver requires:
+         *
+         * Arbitrary Based Buffers:
+         *  This memory area is used for allocating buffers for Video decoding
+         *  purposes.  Allocation/De-allocation within this buffer is managed
+         *  by the STAVMEM driver of the STAPI.  They could be Decimated
+         *  Picture Buffers, Intermediate Buffers, as deemed necessary for
+         *  video decoding purposes, for any video decoders on Zeus.
+         *
+         */
+        {
+                .name   = "AVMEMPartition0",
+                .start  = 0x63580000,
+                .end    = 0x63B80000 - 1,  /* 6 MB total */
+                .flags  = IORESOURCE_IO,
+        },
+        /*
+         *
+         * DOCSIS Subsystem
+         *
+         * This driver requires:
+         *
+         * Arbitrary Based Buffers:
+         *  Docsis -
+         *
+         */
+        {
+                .name   = "Docsis",
+                .start  = 0x62000000,
+                .end    = 0x62700000 - 1,       /* 7 MB total */
+                .flags  = IORESOURCE_IO,
+        },
+        /*
+         *
+         * GHW HAL Driver
+         *
+         * This driver requires:
+         *
+         * Arbitrary Based Buffers:
+         *  GraphicsHeap - PowerTV Graphics Heap
+         *
+         */
+        {
+                .name   = "GraphicsHeap",
+                .start  = 0x62700000,
+                .end    = 0x63500000 - 1,       /* 14 MB total */
+                .flags  = IORESOURCE_IO,
+        },
+        /*
+         *
+         * multi com buffer area
+         *
+         * This driver requires:
+         *
+         * Arbitrary Based Buffers:
+         *  Docsis -
+         *
+         */
+        {
+                .name   = "MulticomSHM",
+                .start  = 0x26000000,
+                .end    = 0x26020000 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        /*
+         *
+         * DMA Ring buffer
+         *
+         * This driver requires:
+         *
+         * Arbitrary Based Buffers:
+         *  Docsis -
+         *
+         */
+        {
+                .name   = "BMM_Buffer",
+                .start  = 0x00000000,
+                .end    = 0x000AA000 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        /*
+         *
+         * Display bins buffer for unit0
+         *
+         * This driver requires:
+         *
+         * Arbitrary Based Buffers:
+         *  Display Bins for unit0
+         *
+         */
+        {
+                .name   = "DisplayBins0",
+                .start  = 0x00000000,
+                .end    = 0x00000FFF,           /* 4 KB total */
+                .flags  = IORESOURCE_MEM,
+        },
+        /*
+         *
+         * Display bins buffer
+         *
+         * This driver requires:
+         *
+         * Arbitrary Based Buffers:
+         *  Display Bins for unit1
+         *
+         */
+        {
+                .name   = "DisplayBins1",
+                .start  = 0x63B83000,
+                .end    = 0x63B84000 - 1,  /* 4 KB total */
+                .flags  = IORESOURCE_IO,
+        },
+        /*
+         *
+         * AVFS: player HAL memory
+         *
+         *
+         */
+        {
+                .name   = "AvfsDmaMem",
+                .start  = 0x63B84000,
+                .end    = 0x63E48C00 - 1,  /* 945K * 3 for playback */
+                .flags  = IORESOURCE_IO,
+        },
+        /*
+         *
+         * PMEM
+         *
+         * This driver requires:
+         *
+         * Arbitrary Based Buffers:
+         *  Persistent memory for diagnostics.
+         *
+         */
+        {
+                .name   = "DiagPersistentMemory",
+                .start  = 0x00000000,
+                .end    = 0x10000 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        /*
+         *
+         * Smartcard
+         *
+         * This driver requires:
+         *
+         * Arbitrary Based Buffers:
+         *  Read and write buffers for Internal/External cards
+         *
+         */
+        {
+                .name   = "SmartCardInfo",
+                .start  = 0x63B80000,
+                .end    = 0x63B82800 - 1,
+                .flags  = IORESOURCE_IO,
+        },
+        /*
+         *
+         * KAVNET
+         *    NP Reset Vector - must be of the form xxCxxxxx
+         *         NP Image - must be video bank 1
+         *         NP IPC - must be video bank 2
+         */
+        {
+                .name   = "NP_Reset_Vector",
+                .start  = 0x27c00000,
+                .end    = 0x27c01000 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .name   = "NP_Image",
+                .start  = 0x27020000,
+                .end    = 0x27060000 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .name   = "NP_IPC",
+                .start  = 0x63500000,
+                .end    = 0x63580000 - 1,
+                .flags  = IORESOURCE_IO,
+        },
+        /*
+         * NAND Flash
+         */
+        {
+                .name   = "NandFlash",
+                .start  = NAND_FLASH_BASE,
+                .end    = NAND_FLASH_BASE + 0x400 - 1,
+                .flags  = IORESOURCE_IO,
+        },
+        /*
+         * Add other resources here
+         */
+        { },
+};
diff --git a/arch/mips/powertv/asic/prealloc-zeus.c b/arch/mips/powertv/asic/prealloc-zeus.c
new file mode 100644
index 000000000000..018d4514dbe3
--- /dev/null
+++ b/arch/mips/powertv/asic/prealloc-zeus.c
@@ -0,0 +1,459 @@
+/*
+ * Memory pre-allocations for Zeus boxes.
+ *
+ * Copyright (C) 2005-2009 Scientific-Atlanta, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ *
+ * Author:       Ken Eppinett
+ *               David Schleef <ds@schleef.org>
+ */
+
+#include <linux/init.h>
+#include <asm/mach-powertv/asic.h>
+
+/*
+ * DVR_CAPABLE RESOURCES
+ */
+struct resource dvr_zeus_resources[] __initdata =
+{
+        /*
+         *
+         * VIDEO1 / LX1
+         *
+         */
+        {
+                .name   = "ST231aImage",        /* Delta-Mu 1 image and ram */
+                .start  = 0x20000000,
+                .end    = 0x201FFFFF,           /* 2MiB */
+                .flags  = IORESOURCE_IO,
+        },
+        {
+                .name   = "ST231aMonitor",      /* 8KiB block ST231a monitor */
+                .start  = 0x20200000,
+                .end    = 0x20201FFF,
+                .flags  = IORESOURCE_IO,
+        },
+        {
+                .name   = "MediaMemory1",
+                .start  = 0x20202000,
+                .end    = 0x21FFFFFF, /*~29.9MiB (32MiB - (2MiB + 8KiB)) */
+                .flags  = IORESOURCE_IO,
+        },
+        /*
+         *
+         * VIDEO2 / LX2
+         *
+         */
+        {
+                .name   = "ST231bImage",        /* Delta-Mu 2 image and ram */
+                .start  = 0x30000000,
+                .end    = 0x301FFFFF,           /* 2MiB */
+                .flags  = IORESOURCE_IO,
+        },
+        {
+                .name   = "ST231bMonitor",      /* 8KiB block ST231b monitor */
+                .start  = 0x30200000,
+                .end    = 0x30201FFF,
+                .flags  = IORESOURCE_IO,
+        },
+        {
+                .name   = "MediaMemory2",
+                .start  = 0x30202000,
+                .end    = 0x31FFFFFF, /*~29.9MiB (32MiB - (2MiB + 8KiB)) */
+                .flags  = IORESOURCE_IO,
+        },
+        /*
+         *
+         * Sysaudio Driver
+         *
+         * This driver requires:
+         *
+         * Arbitrary Based Buffers:
+         *  DSP_Image_Buff - DSP code and data images (1MB)
+         *  ADSC_CPU_PCM_Buff - ADSC CPU PCM buffer (40KB)
+         *  ADSC_AUX_Buff - ADSC AUX buffer (16KB)
+         *  ADSC_Main_Buff - ADSC Main buffer (16KB)
+         *
+         */
+        {
+                .name   = "DSP_Image_Buff",
+                .start  = 0x00000000,
+                .end    = 0x000FFFFF,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .name   = "ADSC_CPU_PCM_Buff",
+                .start  = 0x00000000,
+                .end    = 0x00009FFF,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .name   = "ADSC_AUX_Buff",
+                .start  = 0x00000000,
+                .end    = 0x00003FFF,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .name   = "ADSC_Main_Buff",
+                .start  = 0x00000000,
+                .end    = 0x00003FFF,
+                .flags  = IORESOURCE_MEM,
+        },
+        /*
+         *
+         * STAVEM driver/STAPI
+         *
+         * This driver requires:
+         *
+         * Arbitrary Based Buffers:
+         *  This memory area is used for allocating buffers for Video decoding
+         *  purposes.  Allocation/De-allocation within this buffer is managed
+         *  by the STAVMEM driver of the STAPI.  They could be Decimated
+         *  Picture Buffers, Intermediate Buffers, as deemed necessary for
+         *  video decoding purposes, for any video decoders on Zeus.
+         *
+         */
+        {
+                .name   = "AVMEMPartition0",
+                .start  = 0x00000000,
+                .end    = 0x00c00000 - 1,       /* 12 MB total */
+                .flags  = IORESOURCE_MEM,
+        },
+        /*
+         *
+         * DOCSIS Subsystem
+         *
+         * This driver requires:
+         *
+         * Arbitrary Based Buffers:
+         *  Docsis -
+         *
+         */
+        {
+                .name   = "Docsis",
+                .start  = 0x40100000,
+                .end    = 0x407fffff,
+                .flags  = IORESOURCE_MEM,
+        },
+        /*
+         *
+         * GHW HAL Driver
+         *
+         * This driver requires:
+         *
+         * Arbitrary Based Buffers:
+         *  GraphicsHeap - PowerTV Graphics Heap
+         *
+         */
+        {
+                .name   = "GraphicsHeap",
+                .start  = 0x46900000,
+                .end    = 0x47700000 - 1,       /* 14 MB total */
+                .flags  = IORESOURCE_MEM,
+        },
+        /*
+         *
+         * multi com buffer area
+         *
+         * This driver requires:
+         *
+         * Arbitrary Based Buffers:
+         *  Docsis -
+         *
+         */
+        {
+                .name   = "MulticomSHM",
+                .start  = 0x47900000,
+                .end    = 0x47920000 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        /*
+         *
+         * DMA Ring buffer
+         *
+         * This driver requires:
+         *
+         * Arbitrary Based Buffers:
+         *  Docsis -
+         *
+         */
+        {
+                .name   = "BMM_Buffer",
+                .start  = 0x00000000,
+                .end    = 0x00280000 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        /*
+         *
+         * Display bins buffer for unit0
+         *
+         * This driver requires:
+         *
+         * Arbitrary Based Buffers:
+         *  Display Bins for unit0
+         *
+         */
+        {
+                .name   = "DisplayBins0",
+                .start  = 0x00000000,
+                .end    = 0x00000FFF,   /* 4 KB total */
+                .flags  = IORESOURCE_MEM,
+        },
+        /*
+         *
+         * Display bins buffer
+         *
+         * This driver requires:
+         *
+         * Arbitrary Based Buffers:
+         *  Display Bins for unit1
+         *
+         */
+        {
+                .name   = "DisplayBins1",
+                .start  = 0x00000000,
+                .end    = 0x00000FFF,   /* 4 KB total */
+                .flags  = IORESOURCE_MEM,
+        },
+        /*
+         *
+         * ITFS
+         *
+         * This driver requires:
+         *
+         * Arbitrary Based Buffers:
+         *  Docsis -
+         *
+         */
+        {
+                .name   = "ITFS",
+                .start  = 0x00000000,
+                /* 815,104 bytes each for 2 ITFS partitions. */
+                .end    = 0x0018DFFF,
+                .flags  = IORESOURCE_MEM,
+        },
+        /*
+         *
+         * AVFS
+         *
+         * This driver requires:
+         *
+         * Arbitrary Based Buffers:
+         *  Docsis -
+         *
+         */
+        {
+                .name   = "AvfsDmaMem",
+                .start  = 0x00000000,
+                /* (945K * 8) = (128K * 3) 5 playbacks / 3 server */
+                .end    = 0x007c2000 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .name   = "AvfsFileSys",
+                .start  = 0x00000000,
+                .end    = 0x00001000 - 1,  /* 4K */
+                .flags  = IORESOURCE_MEM,
+        },
+        /*
+         *
+         * PMEM
+         *
+         * This driver requires:
+         *
+         * Arbitrary Based Buffers:
+         *  Persistent memory for diagnostics.
+         *
+         */
+        {
+                .name   = "DiagPersistentMemory",
+                .start  = 0x00000000,
+                .end    = 0x10000 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        /*
+         *
+         * Smartcard
+         *
+         * This driver requires:
+         *
+         * Arbitrary Based Buffers:
+         *  Read and write buffers for Internal/External cards
+         *
+         */
+        {
+                .name   = "SmartCardInfo",
+                .start  = 0x00000000,
+                .end    = 0x2800 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        /*
+         * Add other resources here
+         */
+        { },
+};
+
+/*
+ * NON_DVR_CAPABLE ZEUS RESOURCES
+ */
+struct resource non_dvr_zeus_resources[] __initdata =
+{
+        /*
+         * VIDEO1 / LX1
+         */
+        {
+                .name   = "ST231aImage",        /* Delta-Mu 1 image and ram */
+                .start  = 0x20000000,
+                .end    = 0x201FFFFF,           /* 2MiB */
+                .flags  = IORESOURCE_IO,
+        },
+        {
+                .name   = "ST231aMonitor",      /* 8KiB block ST231a monitor */
+                .start  = 0x20200000,
+                .end    = 0x20201FFF,
+                .flags  = IORESOURCE_IO,
+        },
+        {
+                .name   = "MediaMemory1",
+                .start  = 0x20202000,
+                .end    = 0x21FFFFFF, /*~29.9MiB (32MiB - (2MiB + 8KiB)) */
+                .flags  = IORESOURCE_IO,
+        },
+        /*
+         * Sysaudio Driver
+         */
+        {
+                .name   = "DSP_Image_Buff",
+                .start  = 0x00000000,
+                .end    = 0x000FFFFF,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .name   = "ADSC_CPU_PCM_Buff",
+                .start  = 0x00000000,
+                .end    = 0x00009FFF,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .name   = "ADSC_AUX_Buff",
+                .start  = 0x00000000,
+                .end    = 0x00003FFF,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .name   = "ADSC_Main_Buff",
+                .start  = 0x00000000,
+                .end    = 0x00003FFF,
+                .flags  = IORESOURCE_MEM,
+        },
+        /*
+         * STAVEM driver/STAPI
+         */
+        {
+                .name   = "AVMEMPartition0",
+                .start  = 0x00000000,
+                .end    = 0x00600000 - 1,       /* 6 MB total */
+                .flags  = IORESOURCE_MEM,
+        },
+        /*
+         * DOCSIS Subsystem
+         */
+        {
+                .name   = "Docsis",
+                .start  = 0x40100000,
+                .end    = 0x407fffff,
+                .flags  = IORESOURCE_MEM,
+        },
+        /*
+         * GHW HAL Driver
+         */
+        {
+                .name   = "GraphicsHeap",
+                .start  = 0x46900000,
+                .end    = 0x47700000 - 1,       /* 14 MB total */
+                .flags  = IORESOURCE_MEM,
+        },
+        /*
+         * multi com buffer area
+         */
+        {
+                .name   = "MulticomSHM",
+                .start  = 0x47900000,
+                .end    = 0x47920000 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        /*
+         * DMA Ring buffer
+         */
+        {
+                .name   = "BMM_Buffer",
+                .start  = 0x00000000,
+                .end    = 0x00280000 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        /*
+         * Display bins buffer for unit0
+         */
+        {
+                .name   = "DisplayBins0",
+                .start  = 0x00000000,
+                .end    = 0x00000FFF,           /* 4 KB total */
+                .flags  = IORESOURCE_MEM,
+        },
+        /*
+         *
+         * AVFS: player HAL memory
+         *
+         *
+         */
+        {
+                .name   = "AvfsDmaMem",
+                .start  = 0x00000000,
+                .end    = 0x002c4c00 - 1,       /* 945K * 3 for playback */
+                .flags  = IORESOURCE_MEM,
+        },
+        /*
+         * PMEM
+         */
+        {
+                .name   = "DiagPersistentMemory",
+                .start  = 0x00000000,
+                .end    = 0x10000 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        /*
+         * Smartcard
+         */
+        {
+                .name   = "SmartCardInfo",
+                .start  = 0x00000000,
+                .end    = 0x2800 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        /*
+         * NAND Flash
+         */
+        {
+                .name   = "NandFlash",
+                .start  = NAND_FLASH_BASE,
+                .end    = NAND_FLASH_BASE + 0x400 - 1,
+                .flags  = IORESOURCE_IO,
+        },
+        /*
+         * Add other resources here
+         */
+        { },
+};
diff --git a/arch/mips/powertv/cmdline.c b/arch/mips/powertv/cmdline.c
new file mode 100644
index 000000000000..98d73cb0d452
--- /dev/null
+++ b/arch/mips/powertv/cmdline.c
@@ -0,0 +1,52 @@
+/*
+ * Carsten Langgaard, carstenl@mips.com
+ * Copyright (C) 1999,2000 MIPS Technologies, Inc.  All rights reserved.
+ * Portions copyright (C) 2009 Cisco Systems, Inc.
+ *
+ * This program is free software; you can distribute it and/or modify it
+ * under the terms of the GNU General Public License (Version 2) as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ * for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
+ *
+ * Kernel command line creation using the prom monitor (YAMON) argc/argv.
+ */
+#include <linux/init.h>
+#include <linux/string.h>
+
+#include <asm/bootinfo.h>
+
+#include "init.h"
+
+/*
+ * YAMON (32-bit PROM) pass arguments and environment as 32-bit pointer.
+ * This macro take care of sign extension.
+ */
+#define prom_argv(index) ((char *)(long)_prom_argv[(index)])
+
+char * __init prom_getcmdline(void)
+{
+        return &(arcs_cmdline[0]);
+}
+
+void  __init prom_init_cmdline(void)
+{
+        int len;
+
+        if (prom_argc != 1)
+                return;
+
+        len = strlen(arcs_cmdline);
+
+        arcs_cmdline[len] = ' ';
+
+        strlcpy(arcs_cmdline + len + 1, (char *)_prom_argv,
+                COMMAND_LINE_SIZE - len - 1);
+}
diff --git a/arch/mips/powertv/init.c b/arch/mips/powertv/init.c
new file mode 100644
index 000000000000..5f4e4c304e48
--- /dev/null
+++ b/arch/mips/powertv/init.c
@@ -0,0 +1,128 @@
+/*
+ * Copyright (C) 1999, 2000, 2004, 2005  MIPS Technologies, Inc.
+ *      All rights reserved.
+ *      Authors: Carsten Langgaard <carstenl@mips.com>
+ *               Maciej W. Rozycki <macro@mips.com>
+ * Portions copyright (C) 2009 Cisco Systems, Inc.
+ *
+ *  This program is free software; you can distribute it and/or modify it
+ *  under the terms of the GNU General Public License (Version 2) as
+ *  published by the Free Software Foundation.
+ *
+ *  This program is distributed in the hope it will be useful, but WITHOUT
+ *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ *  for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
+ *
+ * PROM library initialisation code.
+ */
+#include <linux/init.h>
+#include <linux/string.h>
+#include <linux/kernel.h>
+
+#include <asm/bootinfo.h>
+#include <linux/io.h>
+#include <asm/system.h>
+#include <asm/cacheflush.h>
+#include <asm/traps.h>
+
+#include <asm/mips-boards/prom.h>
+#include <asm/mips-boards/generic.h>
+#include <asm/mach-powertv/asic.h>
+
+#include "init.h"
+
+int prom_argc;
+int *_prom_argv, *_prom_envp;
+unsigned long _prom_memsize;
+
+/*
+ * YAMON (32-bit PROM) pass arguments and environment as 32-bit pointer.
+ * This macro take care of sign extension, if running in 64-bit mode.
+ */
+#define prom_envp(index) ((char *)(long)_prom_envp[(index)])
+
+char *prom_getenv(char *envname)
+{
+        char *result = NULL;
+
+        if (_prom_envp != NULL) {
+                /*
+                 * Return a pointer to the given environment variable.
+                 * In 64-bit mode: we're using 64-bit pointers, but all pointers
+                 * in the PROM structures are only 32-bit, so we need some
+                 * workarounds, if we are running in 64-bit mode.
+                 */
+                int i, index = 0;
+
+                i = strlen(envname);
+
+                while (prom_envp(index)) {
+                        if (strncmp(envname, prom_envp(index), i) == 0) {
+                                result = prom_envp(index + 1);
+                                break;
+                        }
+                        index += 2;
+                }
+        }
+
+        return result;
+}
+
+/* TODO: Verify on linux-mips mailing list that the following two  */
+/* functions are correct                                           */
+/* TODO: Copy NMI and EJTAG exception vectors to memory from the   */
+/* BootROM exception vectors. Flush their cache entries. test it.  */
+
+static void __init mips_nmi_setup(void)
+{
+        void *base;
+#if defined(CONFIG_CPU_MIPS32_R1)
+        base = cpu_has_veic ?
+                (void *)(CAC_BASE + 0xa80) :
+                (void *)(CAC_BASE + 0x380);
+#elif defined(CONFIG_CPU_MIPS32_R2)
+        base = (void *)0xbfc00000;
+#else
+#error NMI exception handler address not defined
+#endif
+}
+
+static void __init mips_ejtag_setup(void)
+{
+        void *base;
+
+#if defined(CONFIG_CPU_MIPS32_R1)
+        base = cpu_has_veic ?
+                (void *)(CAC_BASE + 0xa00) :
+                (void *)(CAC_BASE + 0x300);
+#elif defined(CONFIG_CPU_MIPS32_R2)
+        base = (void *)0xbfc00480;
+#else
+#error EJTAG exception handler address not defined
+#endif
+}
+
+void __init prom_init(void)
+{
+        prom_argc = fw_arg0;
+        _prom_argv = (int *) fw_arg1;
+        _prom_envp = (int *) fw_arg2;
+        _prom_memsize = (unsigned long) fw_arg3;
+
+        board_nmi_handler_setup = mips_nmi_setup;
+        board_ejtag_handler_setup = mips_ejtag_setup;
+
+        pr_info("\nLINUX started...\n");
+        prom_init_cmdline();
+        configure_platform();
+        prom_meminit();
+
+#ifndef CONFIG_BOOTLOADER_DRIVER
+        pr_info("\nBootloader driver isn't loaded...\n");
+#endif
+}
diff --git a/arch/mips/powertv/init.h b/arch/mips/powertv/init.h
new file mode 100644
index 000000000000..7af6bf25008c
--- /dev/null
+++ b/arch/mips/powertv/init.h
@@ -0,0 +1,28 @@
+/*
+ * Definitions from powertv init.c file
+ *
+ * Copyright (C) 2009  Cisco Systems, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ *
+ * Author: David VomLehn
+ */
+
+#ifndef _POWERTV_INIT_H
+#define _POWERTV_INIT_H
+extern int prom_argc;
+extern int *_prom_argv;
+extern unsigned long _prom_memsize;
+#endif
diff --git a/arch/mips/powertv/memory.c b/arch/mips/powertv/memory.c
new file mode 100644
index 000000000000..28d06605fff6
--- /dev/null
+++ b/arch/mips/powertv/memory.c
@@ -0,0 +1,186 @@
+/*
+ * Carsten Langgaard, carstenl@mips.com
+ * Copyright (C) 1999,2000 MIPS Technologies, Inc.  All rights reserved.
+ * Portions copyright (C) 2009 Cisco Systems, Inc.
+ *
+ *  This program is free software; you can distribute it and/or modify it
+ *  under the terms of the GNU General Public License (Version 2) as
+ *  published by the Free Software Foundation.
+ *
+ *  This program is distributed in the hope it will be useful, but WITHOUT
+ *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ *  for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
+ *
+ * Apparently originally from arch/mips/malta-memory.c. Modified to work
+ * with the PowerTV bootloader.
+ */
+#include <linux/init.h>
+#include <linux/mm.h>
+#include <linux/bootmem.h>
+#include <linux/pfn.h>
+#include <linux/string.h>
+
+#include <asm/bootinfo.h>
+#include <asm/page.h>
+#include <asm/sections.h>
+
+#include <asm/mips-boards/prom.h>
+
+#include "init.h"
+
+/* Memory constants */
+#define KIBIBYTE(n)             ((n) * 1024)    /* Number of kibibytes */
+#define MEBIBYTE(n)             ((n) * KIBIBYTE(1024)) /* Number of mebibytes */
+#define DEFAULT_MEMSIZE         MEBIBYTE(256)   /* If no memsize provided */
+#define LOW_MEM_MAX             MEBIBYTE(252)   /* Max usable low mem */
+#define RES_BOOTLDR_MEMSIZE     MEBIBYTE(1)     /* Memory reserved for bldr */
+#define BOOT_MEM_SIZE           KIBIBYTE(256)   /* Memory reserved for bldr */
+#define PHYS_MEM_START          0x10000000      /* Start of physical memory */
+
+unsigned long ptv_memsize;
+
+char __initdata cmdline[COMMAND_LINE_SIZE];
+
+void __init prom_meminit(void)
+{
+        char *memsize_str;
+        unsigned long memsize = 0;
+        unsigned int physend;
+        char *ptr;
+        int low_mem;
+        int high_mem;
+
+        /* Check the command line first for a memsize directive */
+        strcpy(cmdline, arcs_cmdline);
+        ptr = strstr(cmdline, "memsize=");
+        if (ptr && (ptr != cmdline) && (*(ptr - 1) != ' '))
+                ptr = strstr(ptr, " memsize=");
+
+        if (ptr) {
+                memsize = memparse(ptr + 8, &ptr);
+        } else {
+                /* otherwise look in the environment */
+                memsize_str = prom_getenv("memsize");
+
+                if (memsize_str != NULL) {
+                        pr_info("prom memsize = %s\n", memsize_str);
+                        memsize = simple_strtol(memsize_str, NULL, 0);
+                }
+
+                if (memsize == 0) {
+                        if (_prom_memsize != 0) {
+                                memsize = _prom_memsize;
+                                pr_info("_prom_memsize = 0x%lx\n", memsize);
+                                /* add in memory that the bootloader doesn't
+                                 * report */
+                                memsize += BOOT_MEM_SIZE;
+                        } else {
+                                memsize = DEFAULT_MEMSIZE;
+                                pr_info("Memsize not passed by bootloader, "
+                                        "defaulting to 0x%lx\n", memsize);
+                        }
+                }
+        }
+
+        /* Store memsize for diagnostic purposes */
+        ptv_memsize = memsize;
+
+        physend = PFN_ALIGN(&_end) - 0x80000000;
+        if (memsize > LOW_MEM_MAX) {
+                low_mem = LOW_MEM_MAX;
+                high_mem = memsize - low_mem;
+        } else {
+                low_mem = memsize;
+                high_mem = 0;
+        }
+
+/*
+ * TODO: We will use the hard code for memory configuration until
+ * the bootloader releases their device tree to us.
+ */
+        /*
+         * Add the memory reserved for use by the bootloader to the
+         * memory map.
+         */
+        add_memory_region(PHYS_MEM_START, RES_BOOTLDR_MEMSIZE,
+                BOOT_MEM_RESERVED);
+#ifdef CONFIG_HIGHMEM_256_128
+        /*
+         * Add memory in low for general use by the kernel and its friends
+         * (like drivers, applications, etc).
+         */
+        add_memory_region(PHYS_MEM_START + RES_BOOTLDR_MEMSIZE,
+                LOW_MEM_MAX - RES_BOOTLDR_MEMSIZE, BOOT_MEM_RAM);
+        /*
+         * Add the memory reserved for reset vector.
+         */
+        add_memory_region(0x1fc00000, MEBIBYTE(4), BOOT_MEM_RESERVED);
+        /*
+         * Add the memory reserved.
+         */
+        add_memory_region(0x20000000, MEBIBYTE(1024 + 75), BOOT_MEM_RESERVED);
+        /*
+         * Add memory in high for general use by the kernel and its friends
+         * (like drivers, applications, etc).
+         *
+         * 75MB is reserved for devices which are using the memory in high.
+         */
+        add_memory_region(0x60000000 + MEBIBYTE(75), MEBIBYTE(128 - 75),
+                BOOT_MEM_RAM);
+#elif defined CONFIG_HIGHMEM_128_128
+        /*
+         * Add memory in low for general use by the kernel and its friends
+         * (like drivers, applications, etc).
+         */
+        add_memory_region(PHYS_MEM_START + RES_BOOTLDR_MEMSIZE,
+                MEBIBYTE(128) - RES_BOOTLDR_MEMSIZE, BOOT_MEM_RAM);
+        /*
+         * Add the memory reserved.
+         */
+        add_memory_region(PHYS_MEM_START + MEBIBYTE(128),
+                MEBIBYTE(128 + 1024 + 75), BOOT_MEM_RESERVED);
+        /*
+         * Add memory in high for general use by the kernel and its friends
+         * (like drivers, applications, etc).
+         *
+         * 75MB is reserved for devices which are using the memory in high.
+         */
+        add_memory_region(0x60000000 + MEBIBYTE(75), MEBIBYTE(128 - 75),
+                BOOT_MEM_RAM);
+#else
+        /* Add low memory regions for either:
+         *   - no-highmemory configuration case -OR-
+         *   - highmemory "HIGHMEM_LOWBANK_ONLY" case
+         */
+        /*
+         * Add memory for general use by the kernel and its friends
+         * (like drivers, applications, etc).
+         */
+        add_memory_region(PHYS_MEM_START + RES_BOOTLDR_MEMSIZE,
+                low_mem - RES_BOOTLDR_MEMSIZE, BOOT_MEM_RAM);
+        /*
+         * Add the memory reserved for reset vector.
+         */
+        add_memory_region(0x1fc00000, MEBIBYTE(4), BOOT_MEM_RESERVED);
+#endif
+}
+
+void __init prom_free_prom_memory(void)
+{
+        unsigned long addr;
+        int i;
+
+        for (i = 0; i < boot_mem_map.nr_map; i++) {
+                if (boot_mem_map.map[i].type != BOOT_MEM_ROM_DATA)
+                        continue;
+
+                addr = boot_mem_map.map[i].addr;
+                free_init_pages("prom memory",
+                                addr, addr + boot_mem_map.map[i].size);
+        }
+}
diff --git a/arch/mips/powertv/pci/Makefile b/arch/mips/powertv/pci/Makefile
new file mode 100644
index 000000000000..f5c62462fc9d
--- /dev/null
+++ b/arch/mips/powertv/pci/Makefile
@@ -0,0 +1,21 @@
+#
+# Copyright (C) 2009  Scientific-Atlanta, Inc.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+#
+
+obj-$(CONFIG_PCI)       += fixup-powertv.o
+
+EXTRA_CFLAGS += -Wall -Werror
diff --git a/arch/mips/powertv/pci/fixup-powertv.c b/arch/mips/powertv/pci/fixup-powertv.c
new file mode 100644
index 000000000000..726bc2e824b3
--- /dev/null
+++ b/arch/mips/powertv/pci/fixup-powertv.c
@@ -0,0 +1,36 @@
+#include <linux/init.h>
+#include <linux/pci.h>
+#include <asm/mach-powertv/interrupts.h>
+#include "powertv-pci.h"
+
+int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
+{
+        return asic_pcie_map_irq(dev, slot, pin);
+}
+
+/* Do platform specific device initialization at pci_enable_device() time */
+int pcibios_plat_dev_init(struct pci_dev *dev)
+{
+        return 0;
+}
+
+/*
+ * asic_pcie_map_irq
+ *
+ * Parameters:
+ * *dev - pointer to a pci_dev structure  (not used)
+ * slot - slot number  (not used)
+ * pin - pin number  (not used)
+ *
+ * Return Value:
+ * Returns: IRQ number (always the PCI Express IRQ number)
+ *
+ * Description:
+ * asic_pcie_map_irq will return the IRQ number of the PCI Express interrupt.
+ *
+ */
+int asic_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
+{
+        return irq_pciexp;
+}
+EXPORT_SYMBOL(asic_pcie_map_irq);
diff --git a/arch/mips/powertv/pci/powertv-pci.h b/arch/mips/powertv/pci/powertv-pci.h
new file mode 100644
index 000000000000..1b5886bbd759
--- /dev/null
+++ b/arch/mips/powertv/pci/powertv-pci.h
@@ -0,0 +1,31 @@
+/*
+ *                              powertv-pci.c
+ *
+ * Copyright (C) 2009  Cisco Systems, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ */
+/*
+ * Local definitions for the powertv PCI code
+ */
+
+#ifndef _POWERTV_PCI_POWERTV_PCI_H_
+#define _POWERTV_PCI_POWERTV_PCI_H_
+extern int asic_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin);
+extern int asic_pcie_init(void);
+extern int asic_pcie_init(void);
+
+extern int log_level;
+#endif
diff --git a/arch/mips/powertv/powertv-clock.h b/arch/mips/powertv/powertv-clock.h
new file mode 100644
index 000000000000..d94c54311485
--- /dev/null
+++ b/arch/mips/powertv/powertv-clock.h
@@ -0,0 +1,26 @@
+/*
+ * Copyright (C) 2009  Cisco Systems, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ *
+ * Author: David VomLehn
+ */
+
+#ifndef _POWERTV_POWERTV_CLOCK_H
+#define _POWERTV_POWERTV_CLOCK_H
+extern int powertv_clockevent_init(void);
+extern void powertv_clocksource_init(void);
+extern unsigned int mips_get_pll_freq(void);
+#endif
diff --git a/arch/mips/powertv/powertv_setup.c b/arch/mips/powertv/powertv_setup.c
new file mode 100644
index 000000000000..bd8ebf128f29
--- /dev/null
+++ b/arch/mips/powertv/powertv_setup.c
@@ -0,0 +1,351 @@
+/*
+ * Carsten Langgaard, carstenl@mips.com
+ * Copyright (C) 2000 MIPS Technologies, Inc.  All rights reserved.
+ * Portions copyright (C) 2009 Cisco Systems, Inc.
+ *
+ *  This program is free software; you can distribute it and/or modify it
+ *  under the terms of the GNU General Public License (Version 2) as
+ *  published by the Free Software Foundation.
+ *
+ *  This program is distributed in the hope it will be useful, but WITHOUT
+ *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ *  for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
+ */
+#include <linux/init.h>
+#include <linux/sched.h>
+#include <linux/ioport.h>
+#include <linux/pci.h>
+#include <linux/screen_info.h>
+#include <linux/notifier.h>
+#include <linux/etherdevice.h>
+#include <linux/if_ether.h>
+#include <linux/ctype.h>
+
+#include <linux/cpu.h>
+#include <asm/bootinfo.h>
+#include <asm/irq.h>
+#include <asm/mips-boards/generic.h>
+#include <asm/mips-boards/prom.h>
+#include <asm/dma.h>
+#include <linux/time.h>
+#include <asm/traps.h>
+#include <asm/asm-offsets.h>
+#include "reset.h"
+
+#define VAL(n)          STR(n)
+
+/*
+ * Macros for loading addresses and storing registers:
+ * PTR_LA       Load the address into a register
+ * LONG_S       Store the full width of the given register.
+ * LONG_L       Load the full width of the given register
+ * PTR_ADDIU    Add a constant value to a register used as a pointer
+ * REG_SIZE     Number of 8-bit bytes in a full width register
+ */
+#ifdef CONFIG_64BIT
+#warning TODO: 64-bit code needs to be verified
+#define PTR_LA          "dla    "
+#define LONG_S          "sd     "
+#define LONG_L          "ld     "
+#define PTR_ADDIU       "daddiu "
+#define REG_SIZE        "8"             /* In bytes */
+#endif
+
+#ifdef CONFIG_32BIT
+#define PTR_LA          "la     "
+#define LONG_S          "sw     "
+#define LONG_L          "lw     "
+#define PTR_ADDIU       "addiu  "
+#define REG_SIZE        "4"             /* In bytes */
+#endif
+
+static struct pt_regs die_regs;
+static bool have_die_regs;
+
+static void register_panic_notifier(void);
+static int panic_handler(struct notifier_block *notifier_block,
+        unsigned long event, void *cause_string);
+
+const char *get_system_type(void)
+{
+        return "PowerTV";
+}
+
+void __init plat_mem_setup(void)
+{
+        panic_on_oops = 1;
+        register_panic_notifier();
+
+#if 0
+        mips_pcibios_init();
+#endif
+        mips_reboot_setup();
+}
+
+/*
+ * Install a panic notifier for platform-specific diagnostics
+ */
+static void register_panic_notifier()
+{
+        static struct notifier_block panic_notifier = {
+                .notifier_call = panic_handler,
+                .next = NULL,
+                .priority       = INT_MAX
+        };
+        atomic_notifier_chain_register(&panic_notifier_list, &panic_notifier);
+}
+
+static int panic_handler(struct notifier_block *notifier_block,
+        unsigned long event, void *cause_string)
+{
+        struct pt_regs  my_regs;
+
+        /* Save all of the registers */
+        {
+                unsigned long   at, v0, v1; /* Must be on the stack */
+
+                /* Start by saving $at and v0 on the stack. We use $at
+                 * ourselves, but it looks like the compiler may use v0 or v1
+                 * to load the address of the pt_regs structure. We'll come
+                 * back later to store the registers in the pt_regs
+                 * structure. */
+                __asm__ __volatile__ (
+                        ".set   noat\n"
+                        LONG_S          "$at, %[at]\n"
+                        LONG_S          "$2, %[v0]\n"
+                        LONG_S          "$3, %[v1]\n"
+                :
+                        [at] "=m" (at),
+                        [v0] "=m" (v0),
+                        [v1] "=m" (v1)
+                :
+                :       "at"
+                );
+
+                __asm__ __volatile__ (
+                        ".set   noat\n"
+                        "move           $at, %[pt_regs]\n"
+
+                        /* Argument registers */
+                        LONG_S          "$4, " VAL(PT_R4) "($at)\n"
+                        LONG_S          "$5, " VAL(PT_R5) "($at)\n"
+                        LONG_S          "$6, " VAL(PT_R6) "($at)\n"
+                        LONG_S          "$7, " VAL(PT_R7) "($at)\n"
+
+                        /* Temporary regs */
+                        LONG_S          "$8, " VAL(PT_R8) "($at)\n"
+                        LONG_S          "$9, " VAL(PT_R9) "($at)\n"
+                        LONG_S          "$10, " VAL(PT_R10) "($at)\n"
+                        LONG_S          "$11, " VAL(PT_R11) "($at)\n"
+                        LONG_S          "$12, " VAL(PT_R12) "($at)\n"
+                        LONG_S          "$13, " VAL(PT_R13) "($at)\n"
+                        LONG_S          "$14, " VAL(PT_R14) "($at)\n"
+                        LONG_S          "$15, " VAL(PT_R15) "($at)\n"
+
+                        /* "Saved" registers */
+                        LONG_S          "$16, " VAL(PT_R16) "($at)\n"
+                        LONG_S          "$17, " VAL(PT_R17) "($at)\n"
+                        LONG_S          "$18, " VAL(PT_R18) "($at)\n"
+                        LONG_S          "$19, " VAL(PT_R19) "($at)\n"
+                        LONG_S          "$20, " VAL(PT_R20) "($at)\n"
+                        LONG_S          "$21, " VAL(PT_R21) "($at)\n"
+                        LONG_S          "$22, " VAL(PT_R22) "($at)\n"
+                        LONG_S          "$23, " VAL(PT_R23) "($at)\n"
+
+                        /* Add'l temp regs */
+                        LONG_S          "$24, " VAL(PT_R24) "($at)\n"
+                        LONG_S          "$25, " VAL(PT_R25) "($at)\n"
+
+                        /* Kernel temp regs */
+                        LONG_S          "$26, " VAL(PT_R26) "($at)\n"
+                        LONG_S          "$27, " VAL(PT_R27) "($at)\n"
+
+                        /* Global pointer, stack pointer, frame pointer and
+                         * return address */
+                        LONG_S          "$gp, " VAL(PT_R28) "($at)\n"
+                        LONG_S          "$sp, " VAL(PT_R29) "($at)\n"
+                        LONG_S          "$fp, " VAL(PT_R30) "($at)\n"
+                        LONG_S          "$ra, " VAL(PT_R31) "($at)\n"
+
+                        /* Now we can get the $at and v0 registers back and
+                         * store them */
+                        LONG_L          "$8, %[at]\n"
+                        LONG_S          "$8, " VAL(PT_R1) "($at)\n"
+                        LONG_L          "$8, %[v0]\n"
+                        LONG_S          "$8, " VAL(PT_R2) "($at)\n"
+                        LONG_L          "$8, %[v1]\n"
+                        LONG_S          "$8, " VAL(PT_R3) "($at)\n"
+                :
+                :
+                        [at] "m" (at),
+                        [v0] "m" (v0),
+                        [v1] "m" (v1),
+                        [pt_regs] "r" (&my_regs)
+                :       "at", "t0"
+                );
+
+                /* Set the current EPC value to be the current location in this
+                 * function */
+                __asm__ __volatile__ (
+                        ".set   noat\n"
+                "1:\n"
+                        PTR_LA          "$at, 1b\n"
+                        LONG_S          "$at, %[cp0_epc]\n"
+                :
+                        [cp0_epc] "=m" (my_regs.cp0_epc)
+                :
+                :       "at"
+                );
+
+                my_regs.cp0_cause = read_c0_cause();
+                my_regs.cp0_status = read_c0_status();
+        }
+
+#ifdef CONFIG_DIAGNOSTICS
+        failure_report((char *) cause_string,
+                have_die_regs ? &die_regs : &my_regs);
+        have_die_regs = false;
+#else
+        pr_crit("I'm feeling a bit sleepy. hmmmmm... perhaps a nap would... "
+                "zzzz... \n");
+#endif
+
+        return NOTIFY_DONE;
+}
+
+/**
+ * Platform-specific handling of oops
+ * @str:        Pointer to the oops string
+ * @regs:       Pointer to the oops registers
+ * All we do here is to save the registers for subsequent printing through
+ * the panic notifier.
+ */
+void platform_die(const char *str, const struct pt_regs *regs)
+{
+        /* If we already have saved registers, don't overwrite them as they
+         * they apply to the initial fault */
+
+        if (!have_die_regs) {
+                have_die_regs = true;
+                die_regs = *regs;
+        }
+}
+
+/* Information about the RF MAC address, if one was supplied on the
+ * command line. */
+static bool have_rfmac;
+static u8 rfmac[ETH_ALEN];
+
+static int rfmac_param(char *p)
+{
+        u8      *q;
+        bool    is_high_nibble;
+        int     c;
+
+        /* Skip a leading "0x", if present */
+        if (*p == '0' && *(p+1) == 'x')
+                p += 2;
+
+        q = rfmac;
+        is_high_nibble = true;
+
+        for (c = (unsigned char) *p++;
+                isxdigit(c) && q - rfmac < ETH_ALEN;
+                c = (unsigned char) *p++) {
+                int     nibble;
+
+                nibble = (isdigit(c) ? (c - '0') :
+                        (isupper(c) ? c - 'A' + 10 : c - 'a' + 10));
+
+                if (is_high_nibble)
+                        *q = nibble << 4;
+                else
+                        *q++ |= nibble;
+
+                is_high_nibble = !is_high_nibble;
+        }
+
+        /* If we parsed all the way to the end of the parameter value and
+         * parsed all ETH_ALEN bytes, we have a usable RF MAC address */
+        have_rfmac = (c == '\0' && q - rfmac == ETH_ALEN);
+
+        return 0;
+}
+
+early_param("rfmac", rfmac_param);
+
+/*
+ * Generate an Ethernet MAC address that has a good chance of being unique.
+ * @addr:       Pointer to six-byte array containing the Ethernet address
+ * Generates an Ethernet MAC address that is highly likely to be unique for
+ * this particular system on a network with other systems of the same type.
+ *
+ * The problem we are solving is that, when random_ether_addr() is used to
+ * generate MAC addresses at startup, there isn't much entropy for the random
+ * number generator to use and the addresses it produces are fairly likely to
+ * be the same as those of other identical systems on the same local network.
+ * This is true even for relatively small numbers of systems (for the reason
+ * why, see the Wikipedia entry for "Birthday problem" at:
+ *      http://en.wikipedia.org/wiki/Birthday_problem
+ *
+ * The good news is that we already have a MAC address known to be unique, the
+ * RF MAC address. The bad news is that this address is already in use on the
+ * RF interface. Worse, the obvious trick, taking the RF MAC address and
+ * turning on the locally managed bit, has already been used for other devices.
+ * Still, this does give us something to work with.
+ *
+ * The approach we take is:
+ * 1.   If we can't get the RF MAC Address, just call random_ether_addr.
+ * 2.   Use the 24-bit NIC-specific bits of the RF MAC address as the last 24
+ *      bits of the new address. This is very likely to be unique, except for
+ *      the current box.
+ * 3.   To avoid using addresses already on the current box, we set the top
+ *      six bits of the address with a value different from any currently
+ *      registered Scientific Atlanta organizationally unique identifyer
+ *      (OUI). This avoids duplication with any addresses on the system that
+ *      were generated from valid Scientific Atlanta-registered address by
+ *      simply flipping the locally managed bit.
+ * 4.   We aren't generating a multicast address, so we leave the multicast
+ *      bit off. Since we aren't using a registered address, we have to set
+ *      the locally managed bit.
+ * 5.   We then randomly generate the remaining 16-bits. This does two
+ *      things:
+ *      a.      It allows us to call this function for more than one device
+ *              in this system
+ *      b.      It ensures that things will probably still work even if
+ *              some device on the device network has a locally managed
+ *              address that matches the top six bits from step 2.
+ */
+void platform_random_ether_addr(u8 addr[ETH_ALEN])
+{
+        const int num_random_bytes = 2;
+        const unsigned char non_sciatl_oui_bits = 0xc0u;
+        const unsigned char mac_addr_locally_managed = (1 << 1);
+
+        if (!have_rfmac) {
+                pr_warning("rfmac not available on command line; "
+                        "generating random MAC address\n");
+                random_ether_addr(addr);
+        }
+
+        else {
+                int     i;
+
+                /* Set the first byte to something that won't match a Scientific
+                 * Atlanta OUI, is locally managed, and isn't a multicast
+                 * address */
+                addr[0] = non_sciatl_oui_bits | mac_addr_locally_managed;
+
+                /* Get some bytes of random address information */
+                get_random_bytes(&addr[1], num_random_bytes);
+
+                /* Copy over the NIC-specific bits of the RF MAC address */
+                for (i = 1 + num_random_bytes; i < ETH_ALEN; i++)
+                        addr[i] = rfmac[i];
+        }
+}
diff --git a/arch/mips/powertv/reset.c b/arch/mips/powertv/reset.c
new file mode 100644
index 000000000000..494c652c984b
--- /dev/null
+++ b/arch/mips/powertv/reset.c
@@ -0,0 +1,65 @@
+/*
+ * Carsten Langgaard, carstenl@mips.com
+ * Copyright (C) 1999,2000 MIPS Technologies, Inc.  All rights reserved.
+ * Portions copyright (C) 2009 Cisco Systems, Inc.
+ *
+ *  This program is free software; you can distribute it and/or modify it
+ *  under the terms of the GNU General Public License (Version 2) as
+ *  published by the Free Software Foundation.
+ *
+ *  This program is distributed in the hope it will be useful, but WITHOUT
+ *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ *  for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
+ */
+#include <linux/pm.h>
+
+#include <linux/io.h>
+#include <asm/reboot.h>                 /* Not included by linux/reboot.h */
+
+#ifdef CONFIG_BOOTLOADER_DRIVER
+#include <asm/mach-powertv/kbldr.h>
+#endif
+
+#include <asm/mach-powertv/asic_regs.h>
+#include "reset.h"
+
+static void mips_machine_restart(char *command);
+static void mips_machine_halt(void);
+
+static void mips_machine_restart(char *command)
+{
+#ifdef CONFIG_BOOTLOADER_DRIVER
+        /*
+         * Call the bootloader's reset function to ensure
+         * that persistent data is flushed before hard reset
+         */
+        kbldr_SetCauseAndReset();
+#else
+        writel(0x1, asic_reg_addr(watchdog));
+#endif
+}
+
+static void mips_machine_halt(void)
+{
+#ifdef CONFIG_BOOTLOADER_DRIVER
+        /*
+         * Call the bootloader's reset function to ensure
+         * that persistent data is flushed before hard reset
+         */
+        kbldr_SetCauseAndReset();
+#else
+        writel(0x1, asic_reg_addr(watchdog));
+#endif
+}
+
+void mips_reboot_setup(void)
+{
+        _machine_restart = mips_machine_restart;
+        _machine_halt = mips_machine_halt;
+        pm_power_off = mips_machine_halt;
+}
diff --git a/arch/mips/powertv/reset.h b/arch/mips/powertv/reset.h
new file mode 100644
index 000000000000..888fd09e2620
--- /dev/null
+++ b/arch/mips/powertv/reset.h
@@ -0,0 +1,26 @@
+/*
+ * Definitions from powertv reset.c file
+ *
+ * Copyright (C) 2009  Cisco Systems, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ *
+ * Author: David VomLehn
+ */
+
+#ifndef _POWERTV_POWERTV_RESET_H
+#define _POWERTV_POWERTV_RESET_H
+extern void mips_reboot_setup(void);
+#endif
diff --git a/arch/mips/mipssim/sim_cmdline.c b/arch/mips/powertv/time.c
index 74240e1ce5a5..1e0a5ef4c8c7 100644
--- a/arch/mips/mipssim/sim_cmdline.c
+++ b/arch/mips/powertv/time.c
@@ -1,5 +1,7 @@
 /*
- * Copyright (C) 2005 MIPS Technologies, Inc.  All rights reserved.
+ * Carsten Langgaard, carstenl@mips.com
+ * Copyright (C) 1999,2000 MIPS Technologies, Inc.  All rights reserved.
+ * Portions copyright (C) 2009 Cisco Systems, Inc.
  *
  *  This program is free software; you can distribute it and/or modify it
  *  under the terms of the GNU General Public License (Version 2) as
@@ -14,19 +16,22 @@
  *  with this program; if not, write to the Free Software Foundation, Inc.,
  *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
  *
+ * Setting up the clock on the MIPS boards.
  */
+
 #include <linux/init.h>
-#include <linux/string.h>
-#include <asm/bootinfo.h>
+#include <asm/mach-powertv/interrupts.h>
+#include <asm/time.h>
 
-extern char arcs_cmdline[];
+#include "powertv-clock.h"
 
-char * __init prom_getcmdline(void)
+unsigned int __cpuinit get_c0_compare_int(void)
 {
-        return arcs_cmdline;
+        return irq_mips_timer;
 }
 
-void  __init prom_init_cmdline(void)
+void __init plat_time_init(void)
 {
-        /* XXX: Get boot line from environment? */
+        powertv_clocksource_init();
+        r4k_clockevent_init();
 }
diff --git a/arch/mips/rb532/prom.c b/arch/mips/rb532/prom.c
index ad5bd1097974..d7c26d00cfef 100644
--- a/arch/mips/rb532/prom.c
+++ b/arch/mips/rb532/prom.c
@@ -69,7 +69,7 @@ static inline unsigned long tag2ul(char *arg, const char *tag)
 
 void __init prom_setup_cmdline(void)
 {
-        static char cmd_line[CL_SIZE] __initdata;
+        static char cmd_line[COMMAND_LINE_SIZE] __initdata;
         char *cp, *board;
         int prom_argc;
         char **prom_argv, **prom_envp;
@@ -115,7 +115,7 @@ void __init prom_setup_cmdline(void)
                 strcpy(cp, arcs_cmdline);
                 cp += strlen(arcs_cmdline);
         }
-        cmd_line[CL_SIZE-1] = '\0';
+        cmd_line[COMMAND_LINE_SIZE - 1] = '\0';
 
         strcpy(arcs_cmdline, cmd_line);
 }
diff --git a/arch/mips/sgi-ip22/ip22-eisa.c b/arch/mips/sgi-ip22/ip22-eisa.c
index 1617241d2737..da44ccb20829 100644
--- a/arch/mips/sgi-ip22/ip22-eisa.c
+++ b/arch/mips/sgi-ip22/ip22-eisa.c
@@ -50,9 +50,9 @@
 
 static char __init *decode_eisa_sig(unsigned long addr)
 {
-        static char sig_str[EISA_SIG_LEN];
+        static char sig_str[EISA_SIG_LEN] __initdata;
         u8 sig[4];
-        u16 rev;
+        u16 rev;
         int i;
 
         for (i = 0; i < 4; i++) {
diff --git a/arch/mips/sgi-ip22/ip22-int.c b/arch/mips/sgi-ip22/ip22-int.c
index 0ecd5fe9486e..383f11d7f442 100644
--- a/arch/mips/sgi-ip22/ip22-int.c
+++ b/arch/mips/sgi-ip22/ip22-int.c
@@ -13,6 +13,7 @@
 #include <linux/init.h>
 #include <linux/kernel_stat.h>
 #include <linux/interrupt.h>
+#include <linux/ftrace.h>
 
 #include <asm/irq_cpu.h>
 #include <asm/sgi/hpc3.h>
@@ -150,7 +151,7 @@ static void indy_local1_irqdispatch(void)
 
 extern void ip22_be_interrupt(int irq);
 
-static void indy_buserror_irq(void)
+static void __irq_entry indy_buserror_irq(void)
 {
         int irq = SGI_BUSERR_IRQ;
 
diff --git a/arch/mips/sgi-ip22/ip22-setup.c b/arch/mips/sgi-ip22/ip22-setup.c
index b9a931358e23..5deeb68b6c9c 100644
--- a/arch/mips/sgi-ip22/ip22-setup.c
+++ b/arch/mips/sgi-ip22/ip22-setup.c
@@ -67,7 +67,7 @@ void __init plat_mem_setup(void)
         cserial = ArcGetEnvironmentVariable("ConsoleOut");
 
         if ((ctype && *ctype == 'd') || (cserial && *cserial == 's')) {
-                static char options[8];
+                static char options[8] __initdata;
                 char *baud = ArcGetEnvironmentVariable("dbaud");
                 if (baud)
                         strcpy(options, baud);
diff --git a/arch/mips/sgi-ip22/ip22-time.c b/arch/mips/sgi-ip22/ip22-time.c
index c8f7d2328b24..603fc91c1030 100644
--- a/arch/mips/sgi-ip22/ip22-time.c
+++ b/arch/mips/sgi-ip22/ip22-time.c
@@ -16,6 +16,7 @@
 #include <linux/interrupt.h>
 #include <linux/kernel_stat.h>
 #include <linux/time.h>
+#include <linux/ftrace.h>
 
 #include <asm/cpu.h>
 #include <asm/mipsregs.h>
@@ -115,7 +116,7 @@ __init void plat_time_init(void)
 }
 
 /* Generic SGI handler for (spurious) 8254 interrupts */
-void indy_8254timer_irq(void)
+void __irq_entry indy_8254timer_irq(void)
 {
         int irq = SGI_8254_0_IRQ;
         ULONG cnt;
diff --git a/arch/mips/sgi-ip32/ip32-setup.c b/arch/mips/sgi-ip32/ip32-setup.c
index c5a5d4a31b4b..3abd1465ec02 100644
--- a/arch/mips/sgi-ip32/ip32-setup.c
+++ b/arch/mips/sgi-ip32/ip32-setup.c
@@ -90,7 +90,7 @@ void __init plat_mem_setup(void)
         {
                 char* con = ArcGetEnvironmentVariable("console");
                 if (con && *con == 'd') {
-                        static char options[8];
+                        static char options[8] __initdata;
                         char *baud = ArcGetEnvironmentVariable("dbaud");
                         if (baud)
                                 strcpy(options, baud);
diff --git a/arch/mips/sibyte/common/cfe.c b/arch/mips/sibyte/common/cfe.c
index eb5396cf81bb..6343011e9902 100644
--- a/arch/mips/sibyte/common/cfe.c
+++ b/arch/mips/sibyte/common/cfe.c
@@ -287,7 +287,7 @@ void __init prom_init(void)
          * boot console
          */
         cfe_cons_handle = cfe_getstdhandle(CFE_STDHANDLE_CONSOLE);
-        if (cfe_getenv("LINUX_CMDLINE", arcs_cmdline, CL_SIZE) < 0) {
+        if (cfe_getenv("LINUX_CMDLINE", arcs_cmdline, COMMAND_LINE_SIZE) < 0) {
                 if (argc >= 0) {
                         /* The loader should have set the command line */
                         /* too early for panic to do any good */
@@ -318,7 +318,7 @@ void __init prom_init(void)
 #endif /* CONFIG_BLK_DEV_INITRD */
 
         /* Not sure this is needed, but it's the safe way. */
-        arcs_cmdline[CL_SIZE-1] = 0;
+        arcs_cmdline[COMMAND_LINE_SIZE-1] = 0;
 
         prom_meminit();
 
diff --git a/arch/mips/sni/a20r.c b/arch/mips/sni/a20r.c
index 7dd76fb3b645..e6980892834a 100644
--- a/arch/mips/sni/a20r.c
+++ b/arch/mips/sni/a20r.c
@@ -188,7 +188,7 @@ static void end_a20r_irq(unsigned int irq)
 }
 
 static struct irq_chip a20r_irq_type = {
-        .typename       = "A20R",
+        .name           = "A20R",
         .ack            = mask_a20r_irq,
         .mask           = mask_a20r_irq,
         .mask_ack       = mask_a20r_irq,
diff --git a/arch/mips/sni/pcimt.c b/arch/mips/sni/pcimt.c
index 74e6c67982fb..51e62bbaa23b 100644
--- a/arch/mips/sni/pcimt.c
+++ b/arch/mips/sni/pcimt.c
@@ -214,7 +214,7 @@ static void end_pcimt_irq(unsigned int irq)
 }
 
 static struct irq_chip pcimt_irq_type = {
-        .typename = "PCIMT",
+        .name = "PCIMT",
         .ack = disable_pcimt_irq,
         .mask = disable_pcimt_irq,
         .mask_ack = disable_pcimt_irq,
diff --git a/arch/mips/sni/pcit.c b/arch/mips/sni/pcit.c
index 071a9573ac7f..f4699d35858b 100644
--- a/arch/mips/sni/pcit.c
+++ b/arch/mips/sni/pcit.c
@@ -176,7 +176,7 @@ void end_pcit_irq(unsigned int irq)
 }
 
 static struct irq_chip pcit_irq_type = {
-        .typename = "PCIT",
+        .name = "PCIT",
         .ack = disable_pcit_irq,
         .mask = disable_pcit_irq,
         .mask_ack = disable_pcit_irq,
diff --git a/arch/mips/sni/rm200.c b/arch/mips/sni/rm200.c
index 5e687819cbc2..46f00691f448 100644
--- a/arch/mips/sni/rm200.c
+++ b/arch/mips/sni/rm200.c
@@ -449,7 +449,7 @@ void end_rm200_irq(unsigned int irq)
 }
 
 static struct irq_chip rm200_irq_type = {
-        .typename = "RM200",
+        .name = "RM200",
         .ack = disable_rm200_irq,
         .mask = disable_rm200_irq,
         .mask_ack = disable_rm200_irq,
diff --git a/arch/mips/sni/setup.c b/arch/mips/sni/setup.c
index a49272ce7ef5..d16b462154c3 100644
--- a/arch/mips/sni/setup.c
+++ b/arch/mips/sni/setup.c
@@ -60,7 +60,7 @@ static void __init sni_console_setup(void)
         char *cdev;
         char *baud;
         int port;
-        static char options[8];
+        static char options[8] __initdata;
 
         cdev = prom_getenv("console_dev");
         if (strncmp(cdev, "tty", 3) == 0) {
diff --git a/arch/mips/txx9/generic/setup.c b/arch/mips/txx9/generic/setup.c
index d66802edebb2..06e801c7e258 100644
--- a/arch/mips/txx9/generic/setup.c
+++ b/arch/mips/txx9/generic/setup.c
@@ -160,7 +160,7 @@ static void __init prom_init_cmdline(void)
         int argc;
         int *argv32;
         int i;                  /* Always ignore the "-c" at argv[0] */
-        static char builtin[CL_SIZE] __initdata;
+        static char builtin[COMMAND_LINE_SIZE] __initdata;
 
         if (fw_arg0 >= CKSEG0 || fw_arg1 < CKSEG0) {
                 /*
@@ -315,7 +315,7 @@ static inline void txx9_cache_fixup(void)
 
 static void __init preprocess_cmdline(void)
 {
-        static char cmdline[CL_SIZE] __initdata;
+        static char cmdline[COMMAND_LINE_SIZE] __initdata;
         char *s;
 
         strcpy(cmdline, arcs_cmdline);
diff --git a/arch/mips/vr41xx/common/icu.c b/arch/mips/vr41xx/common/icu.c
index 6d39e222b170..6153b6a05ccf 100644
--- a/arch/mips/vr41xx/common/icu.c
+++ b/arch/mips/vr41xx/common/icu.c
@@ -159,9 +159,9 @@ void vr41xx_enable_piuint(uint16_t mask)
 
         if (current_cpu_type() == CPU_VR4111 ||
             current_cpu_type() == CPU_VR4121) {
-                spin_lock_irqsave(&desc->lock, flags);
+                raw_spin_lock_irqsave(&desc->lock, flags);
                 icu1_set(MPIUINTREG, mask);
-                spin_unlock_irqrestore(&desc->lock, flags);
+                raw_spin_unlock_irqrestore(&desc->lock, flags);
         }
 }
 
@@ -174,9 +174,9 @@ void vr41xx_disable_piuint(uint16_t mask)
 
         if (current_cpu_type() == CPU_VR4111 ||
             current_cpu_type() == CPU_VR4121) {
-                spin_lock_irqsave(&desc->lock, flags);
+                raw_spin_lock_irqsave(&desc->lock, flags);
                 icu1_clear(MPIUINTREG, mask);
-                spin_unlock_irqrestore(&desc->lock, flags);
+                raw_spin_unlock_irqrestore(&desc->lock, flags);
         }
 }
 
@@ -189,9 +189,9 @@ void vr41xx_enable_aiuint(uint16_t mask)
 
         if (current_cpu_type() == CPU_VR4111 ||
             current_cpu_type() == CPU_VR4121) {
-                spin_lock_irqsave(&desc->lock, flags);
+                raw_spin_lock_irqsave(&desc->lock, flags);
                 icu1_set(MAIUINTREG, mask);
-                spin_unlock_irqrestore(&desc->lock, flags);
+                raw_spin_unlock_irqrestore(&desc->lock, flags);
         }
 }
 
@@ -204,9 +204,9 @@ void vr41xx_disable_aiuint(uint16_t mask)
 
         if (current_cpu_type() == CPU_VR4111 ||
             current_cpu_type() == CPU_VR4121) {
-                spin_lock_irqsave(&desc->lock, flags);
+                raw_spin_lock_irqsave(&desc->lock, flags);
                 icu1_clear(MAIUINTREG, mask);
-                spin_unlock_irqrestore(&desc->lock, flags);
+                raw_spin_unlock_irqrestore(&desc->lock, flags);
         }
 }
 
@@ -219,9 +219,9 @@ void vr41xx_enable_kiuint(uint16_t mask)
 
         if (current_cpu_type() == CPU_VR4111 ||
             current_cpu_type() == CPU_VR4121) {
-                spin_lock_irqsave(&desc->lock, flags);
+                raw_spin_lock_irqsave(&desc->lock, flags);
                 icu1_set(MKIUINTREG, mask);
-                spin_unlock_irqrestore(&desc->lock, flags);
+                raw_spin_unlock_irqrestore(&desc->lock, flags);
         }
 }
 
@@ -234,9 +234,9 @@ void vr41xx_disable_kiuint(uint16_t mask)
 
         if (current_cpu_type() == CPU_VR4111 ||
             current_cpu_type() == CPU_VR4121) {
-                spin_lock_irqsave(&desc->lock, flags);
+                raw_spin_lock_irqsave(&desc->lock, flags);
                 icu1_clear(MKIUINTREG, mask);
-                spin_unlock_irqrestore(&desc->lock, flags);
+                raw_spin_unlock_irqrestore(&desc->lock, flags);
         }
 }
 
@@ -247,9 +247,9 @@ void vr41xx_enable_macint(uint16_t mask)
         struct irq_desc *desc = irq_desc + ETHERNET_IRQ;
         unsigned long flags;
 
-        spin_lock_irqsave(&desc->lock, flags);
+        raw_spin_lock_irqsave(&desc->lock, flags);
         icu1_set(MMACINTREG, mask);
-        spin_unlock_irqrestore(&desc->lock, flags);
+        raw_spin_unlock_irqrestore(&desc->lock, flags);
 }
 
 EXPORT_SYMBOL(vr41xx_enable_macint);
@@ -259,9 +259,9 @@ void vr41xx_disable_macint(uint16_t mask)
         struct irq_desc *desc = irq_desc + ETHERNET_IRQ;
         unsigned long flags;
 
-        spin_lock_irqsave(&desc->lock, flags);
+        raw_spin_lock_irqsave(&desc->lock, flags);
         icu1_clear(MMACINTREG, mask);
-        spin_unlock_irqrestore(&desc->lock, flags);
+        raw_spin_unlock_irqrestore(&desc->lock, flags);
 }
 
 EXPORT_SYMBOL(vr41xx_disable_macint);
@@ -271,9 +271,9 @@ void vr41xx_enable_dsiuint(uint16_t mask)
         struct irq_desc *desc = irq_desc + DSIU_IRQ;
         unsigned long flags;
 
-        spin_lock_irqsave(&desc->lock, flags);
+        raw_spin_lock_irqsave(&desc->lock, flags);
         icu1_set(MDSIUINTREG, mask);
-        spin_unlock_irqrestore(&desc->lock, flags);
+        raw_spin_unlock_irqrestore(&desc->lock, flags);
 }
 
 EXPORT_SYMBOL(vr41xx_enable_dsiuint);
@@ -283,9 +283,9 @@ void vr41xx_disable_dsiuint(uint16_t mask)
         struct irq_desc *desc = irq_desc + DSIU_IRQ;
         unsigned long flags;
 
-        spin_lock_irqsave(&desc->lock, flags);
+        raw_spin_lock_irqsave(&desc->lock, flags);
         icu1_clear(MDSIUINTREG, mask);
-        spin_unlock_irqrestore(&desc->lock, flags);
+        raw_spin_unlock_irqrestore(&desc->lock, flags);
 }
 
 EXPORT_SYMBOL(vr41xx_disable_dsiuint);
@@ -295,9 +295,9 @@ void vr41xx_enable_firint(uint16_t mask)
         struct irq_desc *desc = irq_desc + FIR_IRQ;
         unsigned long flags;
 
-        spin_lock_irqsave(&desc->lock, flags);
+        raw_spin_lock_irqsave(&desc->lock, flags);
         icu2_set(MFIRINTREG, mask);
-        spin_unlock_irqrestore(&desc->lock, flags);
+        raw_spin_unlock_irqrestore(&desc->lock, flags);
 }
 
 EXPORT_SYMBOL(vr41xx_enable_firint);
@@ -307,9 +307,9 @@ void vr41xx_disable_firint(uint16_t mask)
         struct irq_desc *desc = irq_desc + FIR_IRQ;
         unsigned long flags;
 
-        spin_lock_irqsave(&desc->lock, flags);
+        raw_spin_lock_irqsave(&desc->lock, flags);
         icu2_clear(MFIRINTREG, mask);
-        spin_unlock_irqrestore(&desc->lock, flags);
+        raw_spin_unlock_irqrestore(&desc->lock, flags);
 }
 
 EXPORT_SYMBOL(vr41xx_disable_firint);
@@ -322,9 +322,9 @@ void vr41xx_enable_pciint(void)
         if (current_cpu_type() == CPU_VR4122 ||
             current_cpu_type() == CPU_VR4131 ||
             current_cpu_type() == CPU_VR4133) {
-                spin_lock_irqsave(&desc->lock, flags);
+                raw_spin_lock_irqsave(&desc->lock, flags);
                 icu2_write(MPCIINTREG, PCIINT0);
-                spin_unlock_irqrestore(&desc->lock, flags);
+                raw_spin_unlock_irqrestore(&desc->lock, flags);
         }
 }
 
@@ -338,9 +338,9 @@ void vr41xx_disable_pciint(void)
         if (current_cpu_type() == CPU_VR4122 ||
             current_cpu_type() == CPU_VR4131 ||
             current_cpu_type() == CPU_VR4133) {
-                spin_lock_irqsave(&desc->lock, flags);
+                raw_spin_lock_irqsave(&desc->lock, flags);
                 icu2_write(MPCIINTREG, 0);
-                spin_unlock_irqrestore(&desc->lock, flags);
+                raw_spin_unlock_irqrestore(&desc->lock, flags);
         }
 }
 
@@ -354,9 +354,9 @@ void vr41xx_enable_scuint(void)
         if (current_cpu_type() == CPU_VR4122 ||
             current_cpu_type() == CPU_VR4131 ||
             current_cpu_type() == CPU_VR4133) {
-                spin_lock_irqsave(&desc->lock, flags);
+                raw_spin_lock_irqsave(&desc->lock, flags);
                 icu2_write(MSCUINTREG, SCUINT0);
-                spin_unlock_irqrestore(&desc->lock, flags);
+                raw_spin_unlock_irqrestore(&desc->lock, flags);
         }
 }
 
@@ -370,9 +370,9 @@ void vr41xx_disable_scuint(void)
         if (current_cpu_type() == CPU_VR4122 ||
             current_cpu_type() == CPU_VR4131 ||
             current_cpu_type() == CPU_VR4133) {
-                spin_lock_irqsave(&desc->lock, flags);
+                raw_spin_lock_irqsave(&desc->lock, flags);
                 icu2_write(MSCUINTREG, 0);
-                spin_unlock_irqrestore(&desc->lock, flags);
+                raw_spin_unlock_irqrestore(&desc->lock, flags);
         }
 }
 
@@ -386,9 +386,9 @@ void vr41xx_enable_csiint(uint16_t mask)
         if (current_cpu_type() == CPU_VR4122 ||
             current_cpu_type() == CPU_VR4131 ||
             current_cpu_type() == CPU_VR4133) {
-                spin_lock_irqsave(&desc->lock, flags);
+                raw_spin_lock_irqsave(&desc->lock, flags);
                 icu2_set(MCSIINTREG, mask);
-                spin_unlock_irqrestore(&desc->lock, flags);
+                raw_spin_unlock_irqrestore(&desc->lock, flags);
         }
 }
 
@@ -402,9 +402,9 @@ void vr41xx_disable_csiint(uint16_t mask)
         if (current_cpu_type() == CPU_VR4122 ||
             current_cpu_type() == CPU_VR4131 ||
             current_cpu_type() == CPU_VR4133) {
-                spin_lock_irqsave(&desc->lock, flags);
+                raw_spin_lock_irqsave(&desc->lock, flags);
                 icu2_clear(MCSIINTREG, mask);
-                spin_unlock_irqrestore(&desc->lock, flags);
+                raw_spin_unlock_irqrestore(&desc->lock, flags);
         }
 }
 
@@ -418,9 +418,9 @@ void vr41xx_enable_bcuint(void)
         if (current_cpu_type() == CPU_VR4122 ||
             current_cpu_type() == CPU_VR4131 ||
             current_cpu_type() == CPU_VR4133) {
-                spin_lock_irqsave(&desc->lock, flags);
+                raw_spin_lock_irqsave(&desc->lock, flags);
                 icu2_write(MBCUINTREG, BCUINTR);
-                spin_unlock_irqrestore(&desc->lock, flags);
+                raw_spin_unlock_irqrestore(&desc->lock, flags);
         }
 }
 
@@ -434,9 +434,9 @@ void vr41xx_disable_bcuint(void)
         if (current_cpu_type() == CPU_VR4122 ||
             current_cpu_type() == CPU_VR4131 ||
             current_cpu_type() == CPU_VR4133) {
-                spin_lock_irqsave(&desc->lock, flags);
+                raw_spin_lock_irqsave(&desc->lock, flags);
                 icu2_write(MBCUINTREG, 0);
-                spin_unlock_irqrestore(&desc->lock, flags);
+                raw_spin_unlock_irqrestore(&desc->lock, flags);
         }
 }
 
@@ -486,7 +486,7 @@ static inline int set_sysint1_assign(unsigned int irq, unsigned char assign)
 
         pin = SYSINT1_IRQ_TO_PIN(irq);
 
-        spin_lock_irq(&desc->lock);
+        raw_spin_lock_irq(&desc->lock);
 
         intassign0 = icu1_read(INTASSIGN0);
         intassign1 = icu1_read(INTASSIGN1);
@@ -525,7 +525,7 @@ static inline int set_sysint1_assign(unsigned int irq, unsigned char assign)
                 intassign1 |= (uint16_t)assign << 9;
                 break;
         default:
-                spin_unlock_irq(&desc->lock);
+                raw_spin_unlock_irq(&desc->lock);
                 return -EINVAL;
         }
 
@@ -533,7 +533,7 @@ static inline int set_sysint1_assign(unsigned int irq, unsigned char assign)
         icu1_write(INTASSIGN0, intassign0);
         icu1_write(INTASSIGN1, intassign1);
 
-        spin_unlock_irq(&desc->lock);
+        raw_spin_unlock_irq(&desc->lock);
 
         return 0;
 }
@@ -546,7 +546,7 @@ static inline int set_sysint2_assign(unsigned int irq, unsigned char assign)
 
         pin = SYSINT2_IRQ_TO_PIN(irq);
 
-        spin_lock_irq(&desc->lock);
+        raw_spin_lock_irq(&desc->lock);
 
         intassign2 = icu1_read(INTASSIGN2);
         intassign3 = icu1_read(INTASSIGN3);
@@ -593,7 +593,7 @@ static inline int set_sysint2_assign(unsigned int irq, unsigned char assign)
                 intassign3 |= (uint16_t)assign << 12;
                 break;
         default:
-                spin_unlock_irq(&desc->lock);
+                raw_spin_unlock_irq(&desc->lock);
                 return -EINVAL;
         }
 
@@ -601,7 +601,7 @@ static inline int set_sysint2_assign(unsigned int irq, unsigned char assign)
         icu1_write(INTASSIGN2, intassign2);
         icu1_write(INTASSIGN3, intassign3);
 
-        spin_unlock_irq(&desc->lock);
+        raw_spin_unlock_irq(&desc->lock);
 
         return 0;
 }
diff --git a/arch/mn10300/include/asm/asm-offsets.h b/arch/mn10300/include/asm/asm-offsets.h
new file mode 100644
index 000000000000..d370ee36a182
--- /dev/null
+++ b/arch/mn10300/include/asm/asm-offsets.h
@@ -0,0 +1 @@
+#include <generated/asm-offsets.h>
diff --git a/arch/mn10300/include/asm/elf.h b/arch/mn10300/include/asm/elf.h
index 75a70aa9fd6f..e5fa97cd9a14 100644
--- a/arch/mn10300/include/asm/elf.h
+++ b/arch/mn10300/include/asm/elf.h
@@ -77,7 +77,6 @@ do {									\
         _ur->a1   = 0;  _ur->a0   = 0;  _ur->d1   = 0;  _ur->d0   = 0;  \
 } while (0)
 
-#define USE_ELF_CORE_DUMP
 #define CORE_DUMP_USE_REGSET
 #define ELF_EXEC_PAGESIZE       4096
 
diff --git a/arch/mn10300/include/asm/mman.h b/arch/mn10300/include/asm/mman.h
index 8eebf89f5ab1..db5c53da73ce 100644
--- a/arch/mn10300/include/asm/mman.h
+++ b/arch/mn10300/include/asm/mman.h
@@ -1 +1,6 @@
 #include <asm-generic/mman.h>
+
+#define MIN_MAP_ADDR    PAGE_SIZE       /* minimum fixed mmap address */
+
+#define arch_mmap_check(addr, len, flags) \
+        (((flags) & MAP_FIXED && (addr) < MIN_MAP_ADDR) ? -EINVAL : 0)
diff --git a/arch/mn10300/kernel/entry.S b/arch/mn10300/kernel/entry.S
index a94e7ea3faa6..c9ee6c009d79 100644
--- a/arch/mn10300/kernel/entry.S
+++ b/arch/mn10300/kernel/entry.S
@@ -578,7 +578,7 @@ ENTRY(sys_call_table)
         .long sys_ni_syscall    /* reserved for streams2 */
         .long sys_vfork         /* 190 */
         .long sys_getrlimit
-        .long sys_mmap2
+        .long sys_mmap_pgoff
         .long sys_truncate64
         .long sys_ftruncate64
         .long sys_stat64        /* 195 */
diff --git a/arch/mn10300/kernel/irq.c b/arch/mn10300/kernel/irq.c
index 4c3c58ef5cda..e2d5ed891f37 100644
--- a/arch/mn10300/kernel/irq.c
+++ b/arch/mn10300/kernel/irq.c
@@ -215,7 +215,7 @@ int show_interrupts(struct seq_file *p, void *v)
 
                 /* display information rows, one per active CPU */
         case 1 ... NR_IRQS - 1:
-                spin_lock_irqsave(&irq_desc[i].lock, flags);
+                raw_spin_lock_irqsave(&irq_desc[i].lock, flags);
 
                 action = irq_desc[i].action;
                 if (action) {
@@ -235,7 +235,7 @@ int show_interrupts(struct seq_file *p, void *v)
                         seq_putc(p, '\n');
                 }
 
-                spin_unlock_irqrestore(&irq_desc[i].lock, flags);
+                raw_spin_unlock_irqrestore(&irq_desc[i].lock, flags);
                 break;
 
                 /* polish off with NMI and error counters */
diff --git a/arch/mn10300/kernel/kprobes.c b/arch/mn10300/kernel/kprobes.c
index dacafab00eb2..67e6389d625a 100644
--- a/arch/mn10300/kernel/kprobes.c
+++ b/arch/mn10300/kernel/kprobes.c
@@ -31,13 +31,13 @@ const int kretprobe_blacklist_size = ARRAY_SIZE(kretprobe_blacklist);
 #define KPROBE_HIT_ACTIVE       0x00000001
 #define KPROBE_HIT_SS           0x00000002
 
-static struct kprobe *current_kprobe;
-static unsigned long current_kprobe_orig_pc;
-static unsigned long current_kprobe_next_pc;
-static int current_kprobe_ss_flags;
+static struct kprobe *cur_kprobe;
+static unsigned long cur_kprobe_orig_pc;
+static unsigned long cur_kprobe_next_pc;
+static int cur_kprobe_ss_flags;
 static unsigned long kprobe_status;
-static kprobe_opcode_t current_kprobe_ss_buf[MAX_INSN_SIZE + 2];
-static unsigned long current_kprobe_bp_addr;
+static kprobe_opcode_t cur_kprobe_ss_buf[MAX_INSN_SIZE + 2];
+static unsigned long cur_kprobe_bp_addr;
 
 DEFINE_PER_CPU(struct kprobe *, current_kprobe) = NULL;
 
@@ -399,26 +399,25 @@ void __kprobes prepare_singlestep(struct kprobe *p, struct pt_regs *regs)
 {
         unsigned long nextpc;
 
-        current_kprobe_orig_pc = regs->pc;
-        memcpy(current_kprobe_ss_buf, &p->ainsn.insn[0], MAX_INSN_SIZE);
-        regs->pc = (unsigned long) current_kprobe_ss_buf;
+        cur_kprobe_orig_pc = regs->pc;
+        memcpy(cur_kprobe_ss_buf, &p->ainsn.insn[0], MAX_INSN_SIZE);
+        regs->pc = (unsigned long) cur_kprobe_ss_buf;
 
-        nextpc = find_nextpc(regs, &current_kprobe_ss_flags);
-        if (current_kprobe_ss_flags & SINGLESTEP_PCREL)
-                current_kprobe_next_pc =
-                        current_kprobe_orig_pc + (nextpc - regs->pc);
+        nextpc = find_nextpc(regs, &cur_kprobe_ss_flags);
+        if (cur_kprobe_ss_flags & SINGLESTEP_PCREL)
+                cur_kprobe_next_pc = cur_kprobe_orig_pc + (nextpc - regs->pc);
         else
-                current_kprobe_next_pc = nextpc;
+                cur_kprobe_next_pc = nextpc;
 
         /* branching instructions need special handling */
-        if (current_kprobe_ss_flags & SINGLESTEP_BRANCH)
+        if (cur_kprobe_ss_flags & SINGLESTEP_BRANCH)
                 nextpc = singlestep_branch_setup(regs);
 
-        current_kprobe_bp_addr = nextpc;
+        cur_kprobe_bp_addr = nextpc;
 
         *(u8 *) nextpc = BREAKPOINT_INSTRUCTION;
-        mn10300_dcache_flush_range2((unsigned) current_kprobe_ss_buf,
-                                    sizeof(current_kprobe_ss_buf));
+        mn10300_dcache_flush_range2((unsigned) cur_kprobe_ss_buf,
+                                    sizeof(cur_kprobe_ss_buf));
         mn10300_icache_inv();
 }
 
@@ -440,7 +439,7 @@ static inline int __kprobes kprobe_handler(struct pt_regs *regs)
                         disarm_kprobe(p, regs);
                         ret = 1;
                 } else {
-                        p = current_kprobe;
+                        p = cur_kprobe;
                         if (p->break_handler && p->break_handler(p, regs))
                                 goto ss_probe;
                 }
@@ -464,7 +463,7 @@ static inline int __kprobes kprobe_handler(struct pt_regs *regs)
         }
 
         kprobe_status = KPROBE_HIT_ACTIVE;
-        current_kprobe = p;
+        cur_kprobe = p;
         if (p->pre_handler(p, regs)) {
                 /* handler has already set things up, so skip ss setup */
                 return 1;
@@ -491,8 +490,8 @@ no_kprobe:
 static void __kprobes resume_execution(struct kprobe *p, struct pt_regs *regs)
 {
         /* we may need to fixup regs/stack after singlestepping a call insn */
-        if (current_kprobe_ss_flags & SINGLESTEP_BRANCH) {
-                regs->pc = current_kprobe_orig_pc;
+        if (cur_kprobe_ss_flags & SINGLESTEP_BRANCH) {
+                regs->pc = cur_kprobe_orig_pc;
                 switch (p->ainsn.insn[0]) {
                 case 0xcd:      /* CALL (d16,PC) */
                         *(unsigned *) regs->sp = regs->mdr = regs->pc + 5;
@@ -523,8 +522,8 @@ static void __kprobes resume_execution(struct kprobe *p, struct pt_regs *regs)
                 }
         }
 
-        regs->pc = current_kprobe_next_pc;
-        current_kprobe_bp_addr = 0;
+        regs->pc = cur_kprobe_next_pc;
+        cur_kprobe_bp_addr = 0;
 }
 
 static inline int __kprobes post_kprobe_handler(struct pt_regs *regs)
@@ -532,10 +531,10 @@ static inline int __kprobes post_kprobe_handler(struct pt_regs *regs)
         if (!kprobe_running())
                 return 0;
 
-        if (current_kprobe->post_handler)
-                current_kprobe->post_handler(current_kprobe, regs, 0);
+        if (cur_kprobe->post_handler)
+                cur_kprobe->post_handler(cur_kprobe, regs, 0);
 
-        resume_execution(current_kprobe, regs);
+        resume_execution(cur_kprobe, regs);
         reset_current_kprobe();
         preempt_enable_no_resched();
         return 1;
@@ -545,12 +544,12 @@ static inline int __kprobes post_kprobe_handler(struct pt_regs *regs)
 static inline
 int __kprobes kprobe_fault_handler(struct pt_regs *regs, int trapnr)
 {
-        if (current_kprobe->fault_handler &&
-            current_kprobe->fault_handler(current_kprobe, regs, trapnr))
+        if (cur_kprobe->fault_handler &&
+            cur_kprobe->fault_handler(cur_kprobe, regs, trapnr))
                 return 1;
 
         if (kprobe_status & KPROBE_HIT_SS) {
-                resume_execution(current_kprobe, regs);
+                resume_execution(cur_kprobe, regs);
                 reset_current_kprobe();
                 preempt_enable_no_resched();
         }
@@ -567,7 +566,7 @@ int __kprobes kprobe_exceptions_notify(struct notifier_block *self,
 
         switch (val) {
         case DIE_BREAKPOINT:
-                if (current_kprobe_bp_addr != args->regs->pc) {
+                if (cur_kprobe_bp_addr != args->regs->pc) {
                         if (kprobe_handler(args->regs))
                                 return NOTIFY_STOP;
                 } else {
diff --git a/arch/mn10300/kernel/sys_mn10300.c b/arch/mn10300/kernel/sys_mn10300.c
index 8ca5af00334c..17cc6ce04e84 100644
--- a/arch/mn10300/kernel/sys_mn10300.c
+++ b/arch/mn10300/kernel/sys_mn10300.c
@@ -23,47 +23,13 @@
 
 #include <asm/uaccess.h>
 
-#define MIN_MAP_ADDR    PAGE_SIZE       /* minimum fixed mmap address */
-
-/*
- * memory mapping syscall
- */
-asmlinkage long sys_mmap2(unsigned long addr, unsigned long len,
-                          unsigned long prot, unsigned long flags,
-                          unsigned long fd, unsigned long pgoff)
-{
-        struct file *file = NULL;
-        long error = -EINVAL;
-
-        flags &= ~(MAP_EXECUTABLE | MAP_DENYWRITE);
-
-        if (flags & MAP_FIXED && addr < MIN_MAP_ADDR)
-                goto out;
-
-        error = -EBADF;
-        if (!(flags & MAP_ANONYMOUS)) {
-                file = fget(fd);
-                if (!file)
-                        goto out;
-        }
-
-        down_write(&current->mm->mmap_sem);
-        error = do_mmap_pgoff(file, addr, len, prot, flags, pgoff);
-        up_write(&current->mm->mmap_sem);
-
-        if (file)
-                fput(file);
-out:
-        return error;
-}
-
 asmlinkage long old_mmap(unsigned long addr, unsigned long len,
                          unsigned long prot, unsigned long flags,
                          unsigned long fd, unsigned long offset)
 {
         if (offset & ~PAGE_MASK)
                 return -EINVAL;
-        return sys_mmap2(addr, len, prot, flags, fd, offset >> PAGE_SHIFT);
+        return sys_mmap_pgoff(addr, len, prot, flags, fd, offset >> PAGE_SHIFT);
 }
 
 struct sel_arg_struct {
diff --git a/arch/parisc/hpux/sys_hpux.c b/arch/parisc/hpux/sys_hpux.c
index 18072e03a019..92343bd35fa3 100644
--- a/arch/parisc/hpux/sys_hpux.c
+++ b/arch/parisc/hpux/sys_hpux.c
@@ -445,12 +445,7 @@ done:
 
 int hpux_pipe(int *kstack_fildes)
 {
-        int error;
-
-        lock_kernel();
-        error = do_pipe_flags(kstack_fildes, 0);
-        unlock_kernel();
-        return error;
+        return do_pipe_flags(kstack_fildes, 0);
 }
 
 /* lies - says it works, but it really didn't lock anything */
diff --git a/arch/parisc/include/asm/asm-offsets.h b/arch/parisc/include/asm/asm-offsets.h
new file mode 100644
index 000000000000..d370ee36a182
--- /dev/null
+++ b/arch/parisc/include/asm/asm-offsets.h
@@ -0,0 +1 @@
+#include <generated/asm-offsets.h>
diff --git a/arch/parisc/include/asm/atomic.h b/arch/parisc/include/asm/atomic.h
index 8bc9e96699b2..716634d1f546 100644
--- a/arch/parisc/include/asm/atomic.h
+++ b/arch/parisc/include/asm/atomic.h
@@ -27,19 +27,19 @@
 #  define ATOMIC_HASH_SIZE 4
 #  define ATOMIC_HASH(a) (&(__atomic_hash[ (((unsigned long) (a))/L1_CACHE_BYTES) & (ATOMIC_HASH_SIZE-1) ]))
 
-extern raw_spinlock_t __atomic_hash[ATOMIC_HASH_SIZE] __lock_aligned;
+extern arch_spinlock_t __atomic_hash[ATOMIC_HASH_SIZE] __lock_aligned;
 
 /* Can't use raw_spin_lock_irq because of #include problems, so
  * this is the substitute */
 #define _atomic_spin_lock_irqsave(l,f) do {     \
-        raw_spinlock_t *s = ATOMIC_HASH(l);             \
+        arch_spinlock_t *s = ATOMIC_HASH(l);            \
         local_irq_save(f);                      \
-        __raw_spin_lock(s);                     \
+        arch_spin_lock(s);                      \
 } while(0)
 
 #define _atomic_spin_unlock_irqrestore(l,f) do {        \
-        raw_spinlock_t *s = ATOMIC_HASH(l);                     \
-        __raw_spin_unlock(s);                           \
+        arch_spinlock_t *s = ATOMIC_HASH(l);                    \
+        arch_spin_unlock(s);                            \
         local_irq_restore(f);                           \
 } while(0)
 
diff --git a/arch/parisc/include/asm/bug.h b/arch/parisc/include/asm/bug.h
index 8cfc553fc837..75e46c557a16 100644
--- a/arch/parisc/include/asm/bug.h
+++ b/arch/parisc/include/asm/bug.h
@@ -32,14 +32,14 @@
                              "\t.popsection"                            \
                              : : "i" (__FILE__), "i" (__LINE__),        \
                              "i" (0), "i" (sizeof(struct bug_entry)) ); \
-                for(;;) ;                                               \
+                unreachable();                                          \
         } while(0)
 
 #else
 #define BUG()                                                           \
         do {                                                            \
                 asm volatile(PARISC_BUG_BREAK_ASM : : );                \
-                for(;;) ;                                               \
+                unreachable();                                          \
         } while(0)
 #endif
 
diff --git a/arch/parisc/include/asm/elf.h b/arch/parisc/include/asm/elf.h
index 9c802eb4be84..19f6cb1a4a1c 100644
--- a/arch/parisc/include/asm/elf.h
+++ b/arch/parisc/include/asm/elf.h
@@ -328,7 +328,6 @@ struct pt_regs;	/* forward declaration... */
    such function.  */
 #define ELF_PLAT_INIT(_r, load_addr)       _r->gr[23] = 0
 
-#define USE_ELF_CORE_DUMP
 #define ELF_EXEC_PAGESIZE       4096
 
 /* This is the location that an ET_DYN program is loaded if exec'ed.  Typical
diff --git a/arch/parisc/include/asm/fcntl.h b/arch/parisc/include/asm/fcntl.h
index 1e1c824764ee..f357fc693c89 100644
--- a/arch/parisc/include/asm/fcntl.h
+++ b/arch/parisc/include/asm/fcntl.h
@@ -1,14 +1,13 @@
 #ifndef _PARISC_FCNTL_H
 #define _PARISC_FCNTL_H
 
-/* open/fcntl - O_SYNC is only implemented on blocks devices and on files
-   located on an ext2 file system */
 #define O_APPEND        000000010
 #define O_BLKSEEK       000000100 /* HPUX only */
 #define O_CREAT         000000400 /* not fcntl */
 #define O_EXCL          000002000 /* not fcntl */
 #define O_LARGEFILE     000004000
-#define O_SYNC          000100000
+#define __O_SYNC        000100000
+#define O_SYNC          (__O_SYNC|O_DSYNC)
 #define O_NONBLOCK      000200004 /* HPUX has separate NDELAY & NONBLOCK */
 #define O_NOCTTY        000400000 /* not fcntl */
 #define O_DSYNC         001000000 /* HPUX only */
diff --git a/arch/parisc/include/asm/ftrace.h b/arch/parisc/include/asm/ftrace.h
index 2fa05dd6aeee..72c0fafaa039 100644
--- a/arch/parisc/include/asm/ftrace.h
+++ b/arch/parisc/include/asm/ftrace.h
@@ -20,6 +20,20 @@ struct ftrace_ret_stack {
  * Defined in entry.S
  */
 extern void return_to_handler(void);
+
+
+extern unsigned long return_address(unsigned int);
+
+#define HAVE_ARCH_CALLER_ADDR
+
+#define CALLER_ADDR0 ((unsigned long)__builtin_return_address(0))
+#define CALLER_ADDR1 return_address(1)
+#define CALLER_ADDR2 return_address(2)
+#define CALLER_ADDR3 return_address(3)
+#define CALLER_ADDR4 return_address(4)
+#define CALLER_ADDR5 return_address(5)
+#define CALLER_ADDR6 return_address(6)
+
 #endif /* __ASSEMBLY__ */
 
 #endif /* _ASM_PARISC_FTRACE_H */
diff --git a/arch/parisc/include/asm/spinlock.h b/arch/parisc/include/asm/spinlock.h
index fae03e136fa8..74036f436a3b 100644
--- a/arch/parisc/include/asm/spinlock.h
+++ b/arch/parisc/include/asm/spinlock.h
@@ -5,17 +5,17 @@
 #include <asm/processor.h>
 #include <asm/spinlock_types.h>
 
-static inline int __raw_spin_is_locked(raw_spinlock_t *x)
+static inline int arch_spin_is_locked(arch_spinlock_t *x)
 {
         volatile unsigned int *a = __ldcw_align(x);
         return *a == 0;
 }
 
-#define __raw_spin_lock(lock) __raw_spin_lock_flags(lock, 0)
-#define __raw_spin_unlock_wait(x) \
-                do { cpu_relax(); } while (__raw_spin_is_locked(x))
+#define arch_spin_lock(lock) arch_spin_lock_flags(lock, 0)
+#define arch_spin_unlock_wait(x) \
+                do { cpu_relax(); } while (arch_spin_is_locked(x))
 
-static inline void __raw_spin_lock_flags(raw_spinlock_t *x,
+static inline void arch_spin_lock_flags(arch_spinlock_t *x,
                                          unsigned long flags)
 {
         volatile unsigned int *a;
@@ -33,7 +33,7 @@ static inline void __raw_spin_lock_flags(raw_spinlock_t *x,
         mb();
 }
 
-static inline void __raw_spin_unlock(raw_spinlock_t *x)
+static inline void arch_spin_unlock(arch_spinlock_t *x)
 {
         volatile unsigned int *a;
         mb();
@@ -42,7 +42,7 @@ static inline void __raw_spin_unlock(raw_spinlock_t *x)
         mb();
 }
 
-static inline int __raw_spin_trylock(raw_spinlock_t *x)
+static inline int arch_spin_trylock(arch_spinlock_t *x)
 {
         volatile unsigned int *a;
         int ret;
@@ -69,38 +69,38 @@ static inline int __raw_spin_trylock(raw_spinlock_t *x)
 
 /* Note that we have to ensure interrupts are disabled in case we're
  * interrupted by some other code that wants to grab the same read lock */
-static  __inline__ void __raw_read_lock(raw_rwlock_t *rw)
+static  __inline__ void arch_read_lock(arch_rwlock_t *rw)
 {
         unsigned long flags;
         local_irq_save(flags);
-        __raw_spin_lock_flags(&rw->lock, flags);
+        arch_spin_lock_flags(&rw->lock, flags);
         rw->counter++;
-        __raw_spin_unlock(&rw->lock);
+        arch_spin_unlock(&rw->lock);
         local_irq_restore(flags);
 }
 
 /* Note that we have to ensure interrupts are disabled in case we're
  * interrupted by some other code that wants to grab the same read lock */
-static  __inline__ void __raw_read_unlock(raw_rwlock_t *rw)
+static  __inline__ void arch_read_unlock(arch_rwlock_t *rw)
 {
         unsigned long flags;
         local_irq_save(flags);
-        __raw_spin_lock_flags(&rw->lock, flags);
+        arch_spin_lock_flags(&rw->lock, flags);
         rw->counter--;
-        __raw_spin_unlock(&rw->lock);
+        arch_spin_unlock(&rw->lock);
         local_irq_restore(flags);
 }
 
 /* Note that we have to ensure interrupts are disabled in case we're
  * interrupted by some other code that wants to grab the same read lock */
-static __inline__ int __raw_read_trylock(raw_rwlock_t *rw)
+static __inline__ int arch_read_trylock(arch_rwlock_t *rw)
 {
         unsigned long flags;
  retry:
         local_irq_save(flags);
-        if (__raw_spin_trylock(&rw->lock)) {
+        if (arch_spin_trylock(&rw->lock)) {
                 rw->counter++;
-                __raw_spin_unlock(&rw->lock);
+                arch_spin_unlock(&rw->lock);
                 local_irq_restore(flags);
                 return 1;
         }
@@ -111,7 +111,7 @@ static __inline__ int __raw_read_trylock(raw_rwlock_t *rw)
                 return 0;
 
         /* Wait until we have a realistic chance at the lock */
-        while (__raw_spin_is_locked(&rw->lock) && rw->counter >= 0)
+        while (arch_spin_is_locked(&rw->lock) && rw->counter >= 0)
                 cpu_relax();
 
         goto retry;
@@ -119,15 +119,15 @@ static __inline__ int __raw_read_trylock(raw_rwlock_t *rw)
 
 /* Note that we have to ensure interrupts are disabled in case we're
  * interrupted by some other code that wants to read_trylock() this lock */
-static __inline__ void __raw_write_lock(raw_rwlock_t *rw)
+static __inline__ void arch_write_lock(arch_rwlock_t *rw)
 {
         unsigned long flags;
 retry:
         local_irq_save(flags);
-        __raw_spin_lock_flags(&rw->lock, flags);
+        arch_spin_lock_flags(&rw->lock, flags);
 
         if (rw->counter != 0) {
-                __raw_spin_unlock(&rw->lock);
+                arch_spin_unlock(&rw->lock);
                 local_irq_restore(flags);
 
                 while (rw->counter != 0)
@@ -141,27 +141,27 @@ retry:
         local_irq_restore(flags);
 }
 
-static __inline__ void __raw_write_unlock(raw_rwlock_t *rw)
+static __inline__ void arch_write_unlock(arch_rwlock_t *rw)
 {
         rw->counter = 0;
-        __raw_spin_unlock(&rw->lock);
+        arch_spin_unlock(&rw->lock);
 }
 
 /* Note that we have to ensure interrupts are disabled in case we're
  * interrupted by some other code that wants to read_trylock() this lock */
-static __inline__ int __raw_write_trylock(raw_rwlock_t *rw)
+static __inline__ int arch_write_trylock(arch_rwlock_t *rw)
 {
         unsigned long flags;
         int result = 0;
 
         local_irq_save(flags);
-        if (__raw_spin_trylock(&rw->lock)) {
+        if (arch_spin_trylock(&rw->lock)) {
                 if (rw->counter == 0) {
                         rw->counter = -1;
                         result = 1;
                 } else {
                         /* Read-locked.  Oh well. */
-                        __raw_spin_unlock(&rw->lock);
+                        arch_spin_unlock(&rw->lock);
                 }
         }
         local_irq_restore(flags);
@@ -173,7 +173,7 @@ static __inline__ int __raw_write_trylock(raw_rwlock_t *rw)
  * read_can_lock - would read_trylock() succeed?
  * @lock: the rwlock in question.
  */
-static __inline__ int __raw_read_can_lock(raw_rwlock_t *rw)
+static __inline__ int arch_read_can_lock(arch_rwlock_t *rw)
 {
         return rw->counter >= 0;
 }
@@ -182,16 +182,16 @@ static __inline__ int __raw_read_can_lock(raw_rwlock_t *rw)
  * write_can_lock - would write_trylock() succeed?
  * @lock: the rwlock in question.
  */
-static __inline__ int __raw_write_can_lock(raw_rwlock_t *rw)
+static __inline__ int arch_write_can_lock(arch_rwlock_t *rw)
 {
         return !rw->counter;
 }
 
-#define __raw_read_lock_flags(lock, flags) __raw_read_lock(lock)
-#define __raw_write_lock_flags(lock, flags) __raw_write_lock(lock)
+#define arch_read_lock_flags(lock, flags) arch_read_lock(lock)
+#define arch_write_lock_flags(lock, flags) arch_write_lock(lock)
 
-#define _raw_spin_relax(lock)   cpu_relax()
-#define _raw_read_relax(lock)   cpu_relax()
-#define _raw_write_relax(lock)  cpu_relax()
+#define arch_spin_relax(lock)   cpu_relax()
+#define arch_read_relax(lock)   cpu_relax()
+#define arch_write_relax(lock)  cpu_relax()
 
 #endif /* __ASM_SPINLOCK_H */
diff --git a/arch/parisc/include/asm/spinlock_types.h b/arch/parisc/include/asm/spinlock_types.h
index 3f72f47cf4b2..8c373aa28a86 100644
--- a/arch/parisc/include/asm/spinlock_types.h
+++ b/arch/parisc/include/asm/spinlock_types.h
@@ -4,18 +4,18 @@
 typedef struct {
 #ifdef CONFIG_PA20
         volatile unsigned int slock;
-# define __RAW_SPIN_LOCK_UNLOCKED { 1 }
+# define __ARCH_SPIN_LOCK_UNLOCKED { 1 }
 #else
         volatile unsigned int lock[4];
-# define __RAW_SPIN_LOCK_UNLOCKED       { { 1, 1, 1, 1 } }
+# define __ARCH_SPIN_LOCK_UNLOCKED      { { 1, 1, 1, 1 } }
 #endif
-} raw_spinlock_t;
+} arch_spinlock_t;
 
 typedef struct {
-        raw_spinlock_t lock;
+        arch_spinlock_t lock;
         volatile int counter;
-} raw_rwlock_t;
+} arch_rwlock_t;
 
-#define __RAW_RW_LOCK_UNLOCKED          { __RAW_SPIN_LOCK_UNLOCKED, 0 }
+#define __ARCH_RW_LOCK_UNLOCKED         { __ARCH_SPIN_LOCK_UNLOCKED, 0 }
 
 #endif
diff --git a/arch/parisc/kernel/asm-offsets.c b/arch/parisc/kernel/asm-offsets.c
index fcd3c707bf12..ec787b411e9a 100644
--- a/arch/parisc/kernel/asm-offsets.c
+++ b/arch/parisc/kernel/asm-offsets.c
@@ -244,9 +244,6 @@ int main(void)
         DEFINE(THREAD_SZ, sizeof(struct thread_info));
         DEFINE(THREAD_SZ_ALGN, align(sizeof(struct thread_info), 64));
         BLANK();
-        DEFINE(IRQSTAT_SIRQ_PEND, offsetof(irq_cpustat_t, __softirq_pending));
-        DEFINE(IRQSTAT_SZ, sizeof(irq_cpustat_t));
-        BLANK();
         DEFINE(ICACHE_BASE, offsetof(struct pdc_cache_info, ic_base));
         DEFINE(ICACHE_STRIDE, offsetof(struct pdc_cache_info, ic_stride));
         DEFINE(ICACHE_COUNT, offsetof(struct pdc_cache_info, ic_count));
diff --git a/arch/parisc/kernel/irq.c b/arch/parisc/kernel/irq.c
index 2e7610cb33d5..efbcee5d2220 100644
--- a/arch/parisc/kernel/irq.c
+++ b/arch/parisc/kernel/irq.c
@@ -145,7 +145,7 @@ static int cpu_set_affinity_irq(unsigned int irq, const struct cpumask *dest)
 #endif
 
 static struct irq_chip cpu_interrupt_type = {
-        .typename       = "CPU",
+        .name           = "CPU",
         .startup        = cpu_startup_irq,
         .shutdown       = cpu_disable_irq,
         .enable         = cpu_enable_irq,
@@ -180,7 +180,7 @@ int show_interrupts(struct seq_file *p, void *v)
         if (i < NR_IRQS) {
                 struct irqaction *action;
 
-                spin_lock_irqsave(&irq_desc[i].lock, flags);
+                raw_spin_lock_irqsave(&irq_desc[i].lock, flags);
                 action = irq_desc[i].action;
                 if (!action)
                         goto skip;
@@ -192,7 +192,7 @@ int show_interrupts(struct seq_file *p, void *v)
                 seq_printf(p, "%10u ", kstat_irqs(i));
 #endif
 
-                seq_printf(p, " %14s", irq_desc[i].chip->typename);
+                seq_printf(p, " %14s", irq_desc[i].chip->name);
 #ifndef PARISC_IRQ_CR16_COUNTS
                 seq_printf(p, "  %s", action->name);
 
@@ -224,7 +224,7 @@ int show_interrupts(struct seq_file *p, void *v)
 
                 seq_putc(p, '\n');
  skip:
-                spin_unlock_irqrestore(&irq_desc[i].lock, flags);
+                raw_spin_unlock_irqrestore(&irq_desc[i].lock, flags);
         }
 
         return 0;
diff --git a/arch/parisc/kernel/signal.c b/arch/parisc/kernel/signal.c
index e8467e4aa8d1..fb37ac52e46c 100644
--- a/arch/parisc/kernel/signal.c
+++ b/arch/parisc/kernel/signal.c
@@ -26,7 +26,6 @@
 #include <linux/stddef.h>
 #include <linux/compat.h>
 #include <linux/elf.h>
-#include <linux/tracehook.h>
 #include <asm/ucontext.h>
 #include <asm/rt_sigframe.h>
 #include <asm/uaccess.h>
diff --git a/arch/parisc/kernel/smp.c b/arch/parisc/kernel/smp.c
index 1fd0f0cec037..3f2fce8ce6b6 100644
--- a/arch/parisc/kernel/smp.c
+++ b/arch/parisc/kernel/smp.c
@@ -60,8 +60,6 @@ static int smp_debug_lvl = 0;
 #define smp_debug(lvl, ...)     do { } while(0)
 #endif /* DEBUG_SMP */
 
-DEFINE_SPINLOCK(smp_lock);
-
 volatile struct task_struct *smp_init_current_idle_task;
 
 /* track which CPU is booting */
@@ -69,7 +67,7 @@ static volatile int cpu_now_booting __cpuinitdata;
 
 static int parisc_max_cpus __cpuinitdata = 1;
 
-DEFINE_PER_CPU(spinlock_t, ipi_lock) = SPIN_LOCK_UNLOCKED;
+static DEFINE_PER_CPU(spinlock_t, ipi_lock);
 
 enum ipi_message_type {
         IPI_NOP=0,
@@ -438,6 +436,11 @@ void __init smp_prepare_boot_cpu(void)
 */
 void __init smp_prepare_cpus(unsigned int max_cpus)
 {
+        int cpu;
+
+        for_each_possible_cpu(cpu)
+                spin_lock_init(&per_cpu(ipi_lock, cpu));
+
         init_cpu_present(cpumask_of(0));
 
         parisc_max_cpus = max_cpus;
diff --git a/arch/parisc/kernel/sys_parisc.c b/arch/parisc/kernel/sys_parisc.c
index 71b31957c8f1..9147391afb03 100644
--- a/arch/parisc/kernel/sys_parisc.c
+++ b/arch/parisc/kernel/sys_parisc.c
@@ -110,37 +110,14 @@ unsigned long arch_get_unmapped_area(struct file *filp, unsigned long addr,
         return addr;
 }
 
-static unsigned long do_mmap2(unsigned long addr, unsigned long len,
-        unsigned long prot, unsigned long flags, unsigned long fd,
-        unsigned long pgoff)
-{
-        struct file * file = NULL;
-        unsigned long error = -EBADF;
-        if (!(flags & MAP_ANONYMOUS)) {
-                file = fget(fd);
-                if (!file)
-                        goto out;
-        }
-
-        flags &= ~(MAP_EXECUTABLE | MAP_DENYWRITE);
-
-        down_write(&current->mm->mmap_sem);
-        error = do_mmap_pgoff(file, addr, len, prot, flags, pgoff);
-        up_write(&current->mm->mmap_sem);
-
-        if (file != NULL)
-                fput(file);
-out:
-        return error;
-}
-
 asmlinkage unsigned long sys_mmap2(unsigned long addr, unsigned long len,
         unsigned long prot, unsigned long flags, unsigned long fd,
         unsigned long pgoff)
 {
         /* Make sure the shift for mmap2 is constant (12), no matter what PAGE_SIZE
            we have. */
-        return do_mmap2(addr, len, prot, flags, fd, pgoff >> (PAGE_SHIFT - 12));
+        return sys_mmap_pgoff(addr, len, prot, flags, fd,
+                              pgoff >> (PAGE_SHIFT - 12));
 }
 
 asmlinkage unsigned long sys_mmap(unsigned long addr, unsigned long len,
@@ -148,7 +125,8 @@ asmlinkage unsigned long sys_mmap(unsigned long addr, unsigned long len,
                 unsigned long offset)
 {
         if (!(offset & ~PAGE_MASK)) {
-                return do_mmap2(addr, len, prot, flags, fd, offset >> PAGE_SHIFT);
+                return sys_mmap_pgoff(addr, len, prot, flags, fd,
+                                        offset >> PAGE_SHIFT);
         } else {
                 return -EINVAL;
         }
diff --git a/arch/parisc/kernel/sys_parisc32.c b/arch/parisc/kernel/sys_parisc32.c
index 76d23ec8dfaa..9779ece2b070 100644
--- a/arch/parisc/kernel/sys_parisc32.c
+++ b/arch/parisc/kernel/sys_parisc32.c
@@ -26,13 +26,7 @@
 #include <linux/shm.h>
 #include <linux/slab.h>
 #include <linux/uio.h>
-#include <linux/nfs_fs.h>
 #include <linux/ncp_fs.h>
-#include <linux/sunrpc/svc.h>
-#include <linux/nfsd/nfsd.h>
-#include <linux/nfsd/cache.h>
-#include <linux/nfsd/xdr.h>
-#include <linux/nfsd/syscall.h>
 #include <linux/poll.h>
 #include <linux/personality.h>
 #include <linux/stat.h>
diff --git a/arch/parisc/kernel/unwind.c b/arch/parisc/kernel/unwind.c
index a36799e85693..d58eac1a8288 100644
--- a/arch/parisc/kernel/unwind.c
+++ b/arch/parisc/kernel/unwind.c
@@ -13,6 +13,7 @@
 #include <linux/sched.h>
 #include <linux/slab.h>
 #include <linux/kallsyms.h>
+#include <linux/sort.h>
 
 #include <asm/uaccess.h>
 #include <asm/assembly.h>
@@ -115,24 +116,18 @@ unwind_table_init(struct unwind_table *table, const char *name,
         }
 }
 
+static int cmp_unwind_table_entry(const void *a, const void *b)
+{
+        return ((const struct unwind_table_entry *)a)->region_start
+             - ((const struct unwind_table_entry *)b)->region_start;
+}
+
 static void
 unwind_table_sort(struct unwind_table_entry *start,
                   struct unwind_table_entry *finish)
 {
-        struct unwind_table_entry el, *p, *q;
-
-        for (p = start + 1; p < finish; ++p) {
-                if (p[0].region_start < p[-1].region_start) {
-                        el = *p;
-                        q = p;
-                        do {
-                                q[0] = q[-1];
-                                --q;
-                        } while (q > start && 
-                                 el.region_start < q[-1].region_start);
-                        *q = el;
-                }
-        }
+        sort(start, finish - start, sizeof(struct unwind_table_entry),
+             cmp_unwind_table_entry, NULL);
 }
 
 struct unwind_table *
@@ -417,3 +412,30 @@ int unwind_to_user(struct unwind_frame_info *info)
 
         return ret;
 }
+
+unsigned long return_address(unsigned int level)
+{
+        struct unwind_frame_info info;
+        struct pt_regs r;
+        unsigned long sp;
+
+        /* initialize unwind info */
+        asm volatile ("copy %%r30, %0" : "=r"(sp));
+        memset(&r, 0, sizeof(struct pt_regs));
+        r.iaoq[0] = (unsigned long) current_text_addr();
+        r.gr[2] = (unsigned long) __builtin_return_address(0);
+        r.gr[30] = sp;
+        unwind_frame_init(&info, current, &r);
+
+        /* unwind stack */
+        ++level;
+        do {
+                if (unwind_once(&info) < 0 || info.ip == 0)
+                        return 0;
+                if (!__kernel_text_address(info.ip)) {
+                        return 0;
+                }
+        } while (info.ip && level--);
+
+        return info.ip;
+}
diff --git a/arch/parisc/lib/bitops.c b/arch/parisc/lib/bitops.c
index e3eb739fab19..353963d42059 100644
--- a/arch/parisc/lib/bitops.c
+++ b/arch/parisc/lib/bitops.c
@@ -12,8 +12,8 @@
 #include <asm/atomic.h>
 
 #ifdef CONFIG_SMP
-raw_spinlock_t __atomic_hash[ATOMIC_HASH_SIZE] __lock_aligned = {
-        [0 ... (ATOMIC_HASH_SIZE-1)]  = __RAW_SPIN_LOCK_UNLOCKED
+arch_spinlock_t __atomic_hash[ATOMIC_HASH_SIZE] __lock_aligned = {
+        [0 ... (ATOMIC_HASH_SIZE-1)]  = __ARCH_SPIN_LOCK_UNLOCKED
 };
 #endif
 
diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
index 2ba14e77296c..ba3948c70072 100644
--- a/arch/powerpc/Kconfig
+++ b/arch/powerpc/Kconfig
@@ -56,6 +56,16 @@ config IRQ_PER_CPU
         bool
         default y
 
+config NR_IRQS
+        int "Number of virtual interrupt numbers"
+        range 32 512
+        default "512"
+        help
+          This defines the number of virtual interrupt numbers the kernel
+          can manage. Virtual interrupt numbers are what you see in
+          /proc/interrupts. If you configure your system to have too few,
+          drivers will fail to load or worse - handle with care.
+
 config STACKTRACE_SUPPORT
         bool
         default y
@@ -199,24 +209,14 @@ config DEFAULT_UIMAGE
 config REDBOOT
         bool
 
-config HIBERNATE_32
-        bool
-        depends on (PPC_PMAC && !SMP) || BROKEN
-        default y
-
-config HIBERNATE_64
-        bool
-        depends on BROKEN || (PPC_PMAC64 && EXPERIMENTAL)
-        default y
-
 config ARCH_HIBERNATION_POSSIBLE
         bool
-        depends on (PPC64 && HIBERNATE_64) || (PPC32 && HIBERNATE_32)
         default y
 
 config ARCH_SUSPEND_POSSIBLE
         def_bool y
-        depends on ADB_PMU || PPC_EFIKA || PPC_LITE5200 || PPC_83xx
+        depends on ADB_PMU || PPC_EFIKA || PPC_LITE5200 || PPC_83xx || \
+                   PPC_85xx || PPC_86xx
 
 config PPC_DCR_NATIVE
         bool
@@ -320,6 +320,10 @@ config HOTPLUG_CPU
 
           Say N if you are unsure.
 
+config ARCH_CPU_PROBE_RELEASE
+        def_bool y
+        depends on HOTPLUG_CPU
+
 config ARCH_ENABLE_MEMORY_HOTPLUG
         def_bool y
 
@@ -378,6 +382,19 @@ config IRQ_ALL_CPUS
           CPU.  Generally saying Y is safe, although some problems have been
           reported with SMP Power Macintoshes with this option enabled.
 
+config SPARSE_IRQ
+        bool "Support sparse irq numbering"
+        default y
+        help
+          This enables support for sparse irqs. This is useful for distro
+          kernels that want to define a high CONFIG_NR_CPUS value but still
+          want to have low kernel memory footprint on smaller machines.
+
+          ( Sparse IRQs can also be beneficial on NUMA boxes, as they spread
+            out the irq_desc[] array in a more NUMA-friendly way. )
+
+          If you don't know what to do here, say Y.
+
 config NUMA
         bool "NUMA support"
         depends on PPC64
@@ -652,6 +669,14 @@ config FSL_PCI
         select PPC_INDIRECT_PCI
         select PCI_QUIRKS
 
+config FSL_PMC
+        bool
+        default y
+        depends on SUSPEND && (PPC_85xx || PPC_86xx)
+        help
+          Freescale MPC85xx/MPC86xx power management controller support
+          (suspend/resume). For MPC83xx see platforms/83xx/suspend.c
+
 config 4xx_SOC
         bool
 
@@ -679,7 +704,7 @@ config PPC_PCI_CHOICE
 config PCI
         bool "PCI support" if PPC_PCI_CHOICE
         default y if !40x && !CPM2 && !8xx && !PPC_83xx \
-                && !PPC_85xx && !PPC_86xx
+                && !PPC_85xx && !PPC_86xx && !GAMECUBE_COMMON
         default PCI_PERMEDIA if !4xx && !CPM2 && !8xx
         default PCI_QSPAN if !4xx && !CPM2 && 8xx
         select ARCH_SUPPORTS_MSI
diff --git a/arch/powerpc/Kconfig.debug b/arch/powerpc/Kconfig.debug
index bf3382f1904d..5cdd7ed9a12e 100644
--- a/arch/powerpc/Kconfig.debug
+++ b/arch/powerpc/Kconfig.debug
@@ -254,6 +254,14 @@ config PPC_EARLY_DEBUG_CPM
           using a CPM-based serial port.  This assumes that the bootwrapper
           has run, and set up the CPM in a particular way.
 
+config PPC_EARLY_DEBUG_USBGECKO
+        bool "Early debugging through the USB Gecko adapter"
+        depends on GAMECUBE_COMMON
+        select USBGECKO_UDBG
+        help
+          Select this to enable early debugging for Nintendo GameCube/Wii
+          consoles via an external USB Gecko adapter.
+
 endchoice
 
 config PPC_EARLY_DEBUG_44x_PHYSLOW
diff --git a/arch/powerpc/boot/Makefile b/arch/powerpc/boot/Makefile
index 7bfc8ad87798..bb2465bcb327 100644
--- a/arch/powerpc/boot/Makefile
+++ b/arch/powerpc/boot/Makefile
@@ -66,7 +66,7 @@ src-wlib := string.S crt0.S crtsavres.S stdio.c main.c \
                 gunzip_util.c elf_util.c $(zlib) devtree.c oflib.c ofconsole.c \
                 4xx.c ebony.c mv64x60.c mpsc.c mv64x60_i2c.c cuboot.c bamboo.c \
                 cpm-serial.c stdlib.c mpc52xx-psc.c planetcore.c uartlite.c \
-                fsl-soc.c mpc8xx.c pq2.c
+                fsl-soc.c mpc8xx.c pq2.c ugecon.c
 src-plat := of.c cuboot-52xx.c cuboot-824x.c cuboot-83xx.c cuboot-85xx.c holly.c \
                 cuboot-ebony.c cuboot-hotfoot.c treeboot-ebony.c prpmc2800.c \
                 ps3-head.S ps3-hvcall.S ps3.c treeboot-bamboo.c cuboot-8xx.c \
@@ -76,7 +76,8 @@ src-plat := of.c cuboot-52xx.c cuboot-824x.c cuboot-83xx.c cuboot-85xx.c holly.c
                 cuboot-katmai.c cuboot-rainier.c redboot-8xx.c ep8248e.c \
                 cuboot-warp.c cuboot-85xx-cpm2.c cuboot-yosemite.c simpleboot.c \
                 virtex405-head.S virtex.c redboot-83xx.c cuboot-sam440ep.c \
-                cuboot-acadia.c cuboot-amigaone.c cuboot-kilauea.c
+                cuboot-acadia.c cuboot-amigaone.c cuboot-kilauea.c \
+                gamecube-head.S gamecube.c wii-head.S wii.c
 src-boot := $(src-wlib) $(src-plat) empty.c
 
 src-boot := $(addprefix $(obj)/, $(src-boot))
@@ -254,6 +255,8 @@ image-$(CONFIG_KSI8560)			+= cuImage.ksi8560
 image-$(CONFIG_STORCENTER)              += cuImage.storcenter
 image-$(CONFIG_MPC7448HPC2)             += cuImage.mpc7448hpc2
 image-$(CONFIG_PPC_C2K)                 += cuImage.c2k
+image-$(CONFIG_GAMECUBE)                += dtbImage.gamecube
+image-$(CONFIG_WII)                     += dtbImage.wii
 
 # Board port in arch/powerpc/platform/amigaone/Kconfig
 image-$(CONFIG_AMIGAONE)                += cuImage.amigaone
diff --git a/arch/powerpc/boot/dts/canyonlands.dts b/arch/powerpc/boot/dts/canyonlands.dts
index c920170b7dfe..cd56bb5b347b 100644
--- a/arch/powerpc/boot/dts/canyonlands.dts
+++ b/arch/powerpc/boot/dts/canyonlands.dts
@@ -352,6 +352,7 @@
                                 max-frame-size = <9000>;
                                 rx-fifo-size = <4096>;
                                 tx-fifo-size = <2048>;
+                                rx-fifo-size-gige = <16384>;
                                 phy-mode = "rgmii";
                                 phy-map = <0x00000000>;
                                 rgmii-device = <&RGMII0>;
@@ -381,6 +382,7 @@
                                 max-frame-size = <9000>;
                                 rx-fifo-size = <4096>;
                                 tx-fifo-size = <2048>;
+                                rx-fifo-size-gige = <16384>;
                                 phy-mode = "rgmii";
                                 phy-map = <0x00000000>;
                                 rgmii-device = <&RGMII0>;
diff --git a/arch/powerpc/boot/dts/eiger.dts b/arch/powerpc/boot/dts/eiger.dts
index c4a934f2e886..48bcf7187924 100644
--- a/arch/powerpc/boot/dts/eiger.dts
+++ b/arch/powerpc/boot/dts/eiger.dts
@@ -316,6 +316,7 @@
                                 max-frame-size = <9000>;
                                 rx-fifo-size = <4096>;
                                 tx-fifo-size = <2048>;
+                                rx-fifo-size-gige = <16384>;
                                 phy-mode = "rgmii";
                                 phy-map = <0x00000000>;
                                 rgmii-device = <&RGMII0>;
@@ -345,6 +346,7 @@
                                 max-frame-size = <9000>;
                                 rx-fifo-size = <4096>;
                                 tx-fifo-size = <2048>;
+                                rx-fifo-size-gige = <16384>;
                                 phy-mode = "rgmii";
                                 phy-map = <0x00000000>;
                                 rgmii-device = <&RGMII0>;
@@ -375,6 +377,8 @@
                                 max-frame-size = <9000>;
                                 rx-fifo-size = <4096>;
                                 tx-fifo-size = <2048>;
+                                rx-fifo-size-gige = <16384>;
+                                tx-fifo-size-gige = <16384>; /* emac2&3 only */
                                 phy-mode = "rgmii";
                                 phy-map = <0x00000000>;
                                 rgmii-device = <&RGMII1>;
@@ -403,6 +407,8 @@
                                 max-frame-size = <9000>;
                                 rx-fifo-size = <4096>;
                                 tx-fifo-size = <2048>;
+                                rx-fifo-size-gige = <16384>;
+                                tx-fifo-size-gige = <16384>; /* emac2&3 only */
                                 phy-mode = "rgmii";
                                 phy-map = <0x00000000>;
                                 rgmii-device = <&RGMII1>;
diff --git a/arch/powerpc/boot/dts/gamecube.dts b/arch/powerpc/boot/dts/gamecube.dts
new file mode 100644
index 000000000000..ef3be0e58b02
--- /dev/null
+++ b/arch/powerpc/boot/dts/gamecube.dts
@@ -0,0 +1,114 @@
+/*
+ * arch/powerpc/boot/dts/gamecube.dts
+ *
+ * Nintendo GameCube platform device tree source
+ * Copyright (C) 2007-2009 The GameCube Linux Team
+ * Copyright (C) 2007,2008,2009 Albert Herranz
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ */
+
+/dts-v1/;
+
+/ {
+        model = "nintendo,gamecube";
+        compatible = "nintendo,gamecube";
+        #address-cells = <1>;
+        #size-cells = <1>;
+
+        chosen {
+                bootargs = "root=/dev/gcnsda2 rootwait udbg-immortal";
+        };
+
+        memory {
+                device_type = "memory";
+                reg = <0x00000000 0x01800000>;
+        };
+
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                PowerPC,gekko@0 {
+                        device_type = "cpu";
+                        reg = <0>;
+                        clock-frequency = <486000000>; /* 486MHz */
+                        bus-frequency = <162000000>; /* 162MHz core-to-bus 3x */
+                        timebase-frequency = <40500000>; /* 162MHz / 4 */
+                        i-cache-line-size = <32>;
+                        d-cache-line-size = <32>;
+                        i-cache-size = <32768>;
+                        d-cache-size = <32768>;
+                };
+        };
+
+        /* devices contained int the flipper chipset */
+        flipper {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "nintendo,flipper";
+                ranges = <0x0c000000 0x0c000000 0x00010000>;
+                interrupt-parent = <&PIC>;
+
+                video@0c002000 {
+                        compatible = "nintendo,flipper-vi";
+                        reg = <0x0c002000 0x100>;
+                        interrupts = <8>;
+                };
+
+                processor-interface@0c003000 {
+                        compatible = "nintendo,flipper-pi";
+                        reg = <0x0c003000 0x100>;
+
+                        PIC: pic {
+                                #interrupt-cells = <1>;
+                                compatible = "nintendo,flipper-pic";
+                                interrupt-controller;
+                        };
+                };
+
+                dsp@0c005000 {
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        compatible = "nintendo,flipper-dsp";
+                        reg = <0x0c005000 0x200>;
+                        interrupts = <6>;
+
+                        memory@0 {
+                                compatible = "nintendo,flipper-aram";
+                                reg = <0 0x1000000>;    /* 16MB */
+                        };
+                };
+
+                disk@0c006000 {
+                        compatible = "nintendo,flipper-di";
+                        reg = <0x0c006000 0x40>;
+                        interrupts = <2>;
+                };
+
+                audio@0c006c00 {
+                        compatible = "nintendo,flipper-ai";
+                        reg = <0x0c006c00 0x20>;
+                        interrupts = <6>;
+                };
+
+                gamepad-controller@0c006400 {
+                        compatible = "nintendo,flipper-si";
+                        reg = <0x0c006400 0x100>;
+                        interrupts = <3>;
+                };
+
+                /* External Interface bus */
+                exi@0c006800 {
+                        compatible = "nintendo,flipper-exi";
+                        reg = <0x0c006800 0x40>;
+                        virtual-reg = <0x0c006800>;
+                        interrupts = <4>;
+                };
+        };
+};
+
diff --git a/arch/powerpc/boot/dts/gef_ppc9a.dts b/arch/powerpc/boot/dts/gef_ppc9a.dts
index 910944edd886..c86114e93f1e 100644
--- a/arch/powerpc/boot/dts/gef_ppc9a.dts
+++ b/arch/powerpc/boot/dts/gef_ppc9a.dts
@@ -118,6 +118,12 @@
                         };
                 };
 
+                nvram@3,0 {
+                        device_type = "nvram";
+                        compatible = "simtek,stk14ca8";
+                        reg = <0x3 0x0 0x20000>;
+                };
+
                 fpga@4,0 {
                         compatible = "gef,ppc9a-fpga-regs";
                         reg = <0x4 0x0 0x40>;
diff --git a/arch/powerpc/boot/dts/gef_sbc310.dts b/arch/powerpc/boot/dts/gef_sbc310.dts
index 2107d3c7cfe1..820c2b355ab1 100644
--- a/arch/powerpc/boot/dts/gef_sbc310.dts
+++ b/arch/powerpc/boot/dts/gef_sbc310.dts
@@ -115,6 +115,12 @@
                         };
                 };
 
+                nvram@3,0 {
+                        device_type = "nvram";
+                        compatible = "simtek,stk14ca8";
+                        reg = <0x3 0x0 0x20000>;
+                };
+
                 fpga@4,0 {
                         compatible = "gef,fpga-regs";
                         reg = <0x4 0x0 0x40>;
diff --git a/arch/powerpc/boot/dts/gef_sbc610.dts b/arch/powerpc/boot/dts/gef_sbc610.dts
index 35a63183eecc..30911adefc8e 100644
--- a/arch/powerpc/boot/dts/gef_sbc610.dts
+++ b/arch/powerpc/boot/dts/gef_sbc610.dts
@@ -84,6 +84,12 @@
                           6 0 0xfd000000 0x00800000     // IO FPGA (8-bit)
                           7 0 0xfd800000 0x00800000>;   // IO FPGA (32-bit)
 
+                nvram@3,0 {
+                        device_type = "nvram";
+                        compatible = "simtek,stk14ca8";
+                        reg = <0x3 0x0 0x20000>;
+                };
+
                 fpga@4,0 {
                         compatible = "gef,fpga-regs";
                         reg = <0x4 0x0 0x40>;
diff --git a/arch/powerpc/boot/dts/glacier.dts b/arch/powerpc/boot/dts/glacier.dts
index f3787a27f634..f6f618939293 100644
--- a/arch/powerpc/boot/dts/glacier.dts
+++ b/arch/powerpc/boot/dts/glacier.dts
@@ -292,6 +292,7 @@
                                 max-frame-size = <9000>;
                                 rx-fifo-size = <4096>;
                                 tx-fifo-size = <2048>;
+                                rx-fifo-size-gige = <16384>;
                                 phy-mode = "rgmii";
                                 phy-map = <0x00000000>;
                                 rgmii-device = <&RGMII0>;
@@ -321,6 +322,7 @@
                                 max-frame-size = <9000>;
                                 rx-fifo-size = <4096>;
                                 tx-fifo-size = <2048>;
+                                rx-fifo-size-gige = <16384>;
                                 phy-mode = "rgmii";
                                 phy-map = <0x00000000>;
                                 rgmii-device = <&RGMII0>;
@@ -351,6 +353,8 @@
                                 max-frame-size = <9000>;
                                 rx-fifo-size = <4096>;
                                 tx-fifo-size = <2048>;
+                                rx-fifo-size-gige = <16384>;
+                                tx-fifo-size-gige = <16384>; /* emac2&3 only */
                                 phy-mode = "rgmii";
                                 phy-map = <0x00000000>;
                                 rgmii-device = <&RGMII1>;
@@ -379,6 +383,8 @@
                                 max-frame-size = <9000>;
                                 rx-fifo-size = <4096>;
                                 tx-fifo-size = <2048>;
+                                rx-fifo-size-gige = <16384>;
+                                tx-fifo-size-gige = <16384>; /* emac2&3 only */
                                 phy-mode = "rgmii";
                                 phy-map = <0x00000000>;
                                 rgmii-device = <&RGMII1>;
diff --git a/arch/powerpc/boot/dts/haleakala.dts b/arch/powerpc/boot/dts/haleakala.dts
index 5b2a4947bf82..2b256694eca6 100644
--- a/arch/powerpc/boot/dts/haleakala.dts
+++ b/arch/powerpc/boot/dts/haleakala.dts
@@ -226,6 +226,8 @@
                                 max-frame-size = <9000>;
                                 rx-fifo-size = <4096>;
                                 tx-fifo-size = <2048>;
+                                rx-fifo-size-gige = <16384>;
+                                tx-fifo-size-gige = <16384>;
                                 phy-mode = "rgmii";
                                 phy-map = <0x00000000>;
                                 rgmii-device = <&RGMII0>;
diff --git a/arch/powerpc/boot/dts/katmai.dts b/arch/powerpc/boot/dts/katmai.dts
index 077819bc3cbd..51eb6ed5da2d 100644
--- a/arch/powerpc/boot/dts/katmai.dts
+++ b/arch/powerpc/boot/dts/katmai.dts
@@ -16,7 +16,7 @@
 
 / {
         #address-cells = <2>;
-        #size-cells = <1>;
+        #size-cells = <2>;
         model = "amcc,katmai";
         compatible = "amcc,katmai";
         dcr-parent = <&{/cpus/cpu@0}>;
@@ -49,7 +49,7 @@
 
         memory {
                 device_type = "memory";
-                reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by zImage */
+                reg = <0x0 0x00000000 0x0 0x00000000>; /* Filled in by U-Boot */
         };
 
         UIC0: interrupt-controller0 {
@@ -112,7 +112,15 @@
                 compatible = "ibm,plb-440spe", "ibm,plb-440gp", "ibm,plb4";
                 #address-cells = <2>;
                 #size-cells = <1>;
-                ranges;
+                /*        addr-child     addr-parent    size */
+                ranges = <0x4 0xe0000000 0x4 0xe0000000 0x20000000
+                          0xc 0x00000000 0xc 0x00000000 0x20000000
+                          0xd 0x00000000 0xd 0x00000000 0x80000000
+                          0xd 0x80000000 0xd 0x80000000 0x80000000
+                          0xe 0x00000000 0xe 0x00000000 0x80000000
+                          0xe 0x80000000 0xe 0x80000000 0x80000000
+                          0xf 0x00000000 0xf 0x00000000 0x80000000
+                          0xf 0x80000000 0xf 0x80000000 0x80000000>;
                 clock-frequency = <0>; /* Filled in by zImage */
 
                 SDRAM0: sdram {
@@ -245,8 +253,8 @@
                         ranges = <0x02000000 0x00000000 0x80000000 0x0000000d 0x80000000 0x00000000 0x80000000
                                   0x01000000 0x00000000 0x00000000 0x0000000c 0x08000000 0x00000000 0x00010000>;
 
-                        /* Inbound 2GB range starting at 0 */
-                        dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
+                        /* Inbound 4GB range starting at 0 */
+                        dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x1 0x00000000>;
 
                         /* This drives busses 0 to 0xf */
                         bus-range = <0x0 0xf>;
@@ -289,10 +297,10 @@
                         ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x00000000 0x00000000 0x80000000
                                   0x01000000 0x00000000 0x00000000 0x0000000f 0x80000000 0x00000000 0x00010000>;
 
-                        /* Inbound 2GB range starting at 0 */
-                        dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
+                        /* Inbound 4GB range starting at 0 */
+                        dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x1 0x00000000>;
 
-                        /* This drives busses 10 to 0x1f */
+                        /* This drives busses 0x10 to 0x1f */
                         bus-range = <0x10 0x1f>;
 
                         /* Legacy interrupts (note the weird polarity, the bridge seems
@@ -330,10 +338,10 @@
                         ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x80000000 0x00000000 0x80000000
                                   0x01000000 0x00000000 0x00000000 0x0000000f 0x80010000 0x00000000 0x00010000>;
 
-                        /* Inbound 2GB range starting at 0 */
-                        dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
+                        /* Inbound 4GB range starting at 0 */
+                        dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x1 0x00000000>;
 
-                        /* This drives busses 10 to 0x1f */
+                        /* This drives busses 0x20 to 0x2f */
                         bus-range = <0x20 0x2f>;
 
                         /* Legacy interrupts (note the weird polarity, the bridge seems
@@ -371,10 +379,10 @@
                         ranges = <0x02000000 0x00000000 0x80000000 0x0000000f 0x00000000 0x00000000 0x80000000
                                   0x01000000 0x00000000 0x00000000 0x0000000f 0x80020000 0x00000000 0x00010000>;
 
-                        /* Inbound 2GB range starting at 0 */
-                        dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
+                        /* Inbound 4GB range starting at 0 */
+                        dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x1 0x00000000>;
 
-                        /* This drives busses 10 to 0x1f */
+                        /* This drives busses 0x30 to 0x3f */
                         bus-range = <0x30 0x3f>;
 
                         /* Legacy interrupts (note the weird polarity, the bridge seems
diff --git a/arch/powerpc/boot/dts/kilauea.dts b/arch/powerpc/boot/dts/kilauea.dts
index c46561456ede..083e68eeaca4 100644
--- a/arch/powerpc/boot/dts/kilauea.dts
+++ b/arch/powerpc/boot/dts/kilauea.dts
@@ -272,6 +272,8 @@
                                 max-frame-size = <9000>;
                                 rx-fifo-size = <4096>;
                                 tx-fifo-size = <2048>;
+                                rx-fifo-size-gige = <16384>;
+                                tx-fifo-size-gige = <16384>;
                                 phy-mode = "rgmii";
                                 phy-map = <0x00000000>;
                                 rgmii-device = <&RGMII0>;
@@ -300,6 +302,8 @@
                                 max-frame-size = <9000>;
                                 rx-fifo-size = <4096>;
                                 tx-fifo-size = <2048>;
+                                rx-fifo-size-gige = <16384>;
+                                tx-fifo-size-gige = <16384>;
                                 phy-mode = "rgmii";
                                 phy-map = <0x00000000>;
                                 rgmii-device = <&RGMII0>;
diff --git a/arch/powerpc/boot/dts/kmeter1.dts b/arch/powerpc/boot/dts/kmeter1.dts
index 167044f7de1d..65b8b4f27efe 100644
--- a/arch/powerpc/boot/dts/kmeter1.dts
+++ b/arch/powerpc/boot/dts/kmeter1.dts
@@ -59,6 +59,13 @@
                 reg = <0xe0000000 0x00000200>;
                 bus-frequency = <0>;    /* Filled in by U-Boot */
 
+                pmc: power@b00 {
+                        compatible = "fsl,mpc8360-pmc", "fsl,mpc8349-pmc";
+                        reg = <0xb00 0x100 0xa00 0x100>;
+                        interrupts = <80 0x8>;
+                        interrupt-parent = <&ipic>;
+                };
+
                 i2c@3000 {
                         #address-cells = <1>;
                         #size-cells = <0>;
diff --git a/arch/powerpc/boot/dts/makalu.dts b/arch/powerpc/boot/dts/makalu.dts
index ffc246e72670..63d48b632c84 100644
--- a/arch/powerpc/boot/dts/makalu.dts
+++ b/arch/powerpc/boot/dts/makalu.dts
@@ -227,6 +227,8 @@
                                 max-frame-size = <9000>;
                                 rx-fifo-size = <4096>;
                                 tx-fifo-size = <2048>;
+                                rx-fifo-size-gige = <16384>;
+                                tx-fifo-size-gige = <16384>;
                                 phy-mode = "rgmii";
                                 phy-map = <0x0000003f>; /* Start at 6 */
                                 rgmii-device = <&RGMII0>;
@@ -255,6 +257,8 @@
                                 max-frame-size = <9000>;
                                 rx-fifo-size = <4096>;
                                 tx-fifo-size = <2048>;
+                                rx-fifo-size-gige = <16384>;
+                                tx-fifo-size-gige = <16384>;
                                 phy-mode = "rgmii";
                                 phy-map = <0x00000000>;
                                 rgmii-device = <&RGMII0>;
diff --git a/arch/powerpc/boot/dts/mpc832x_mds.dts b/arch/powerpc/boot/dts/mpc832x_mds.dts
index 436c9c671dd9..05ad8c98e527 100644
--- a/arch/powerpc/boot/dts/mpc832x_mds.dts
+++ b/arch/powerpc/boot/dts/mpc832x_mds.dts
@@ -79,6 +79,13 @@
                         reg = <0x200 0x100>;
                 };
 
+                pmc: power@b00 {
+                        compatible = "fsl,mpc8323-pmc", "fsl,mpc8349-pmc";
+                        reg = <0xb00 0x100 0xa00 0x100>;
+                        interrupts = <80 0x8>;
+                        interrupt-parent = <&ipic>;
+                };
+
                 i2c@3000 {
                         #address-cells = <1>;
                         #size-cells = <0>;
@@ -163,6 +170,7 @@
                         fsl,channel-fifo-len = <24>;
                         fsl,exec-units-mask = <0x4c>;
                         fsl,descriptor-types-mask = <0x0122003f>;
+                        sleep = <&pmc 0x03000000>;
                 };
 
                 ipic: pic@700 {
@@ -428,5 +436,6 @@
                        0xe0008300 0x8>;         /* config space access registers */
                 compatible = "fsl,mpc8349-pci";
                 device_type = "pci";
+                sleep = <&pmc 0x00010000>;
         };
 };
diff --git a/arch/powerpc/boot/dts/mpc832x_rdb.dts b/arch/powerpc/boot/dts/mpc832x_rdb.dts
index 9a0952f74b81..f4fadb23ad6f 100644
--- a/arch/powerpc/boot/dts/mpc832x_rdb.dts
+++ b/arch/powerpc/boot/dts/mpc832x_rdb.dts
@@ -62,6 +62,13 @@
                         reg = <0x200 0x100>;
                 };
 
+                pmc: power@b00 {
+                        compatible = "fsl,mpc8323-pmc", "fsl,mpc8349-pmc";
+                        reg = <0xb00 0x100 0xa00 0x100>;
+                        interrupts = <80 0x8>;
+                        interrupt-parent = <&ipic>;
+                };
+
                 i2c@3000 {
                         #address-cells = <1>;
                         #size-cells = <0>;
@@ -141,6 +148,7 @@
                         fsl,channel-fifo-len = <24>;
                         fsl,exec-units-mask = <0x4c>;
                         fsl,descriptor-types-mask = <0x0122003f>;
+                        sleep = <&pmc 0x03000000>;
                 };
 
                 ipic:pic@700 {
@@ -360,5 +368,6 @@
                        0xe0008300 0x8>;         /* config space access registers */
                 compatible = "fsl,mpc8349-pci";
                 device_type = "pci";
+                sleep = <&pmc 0x00010000>;
         };
 };
diff --git a/arch/powerpc/boot/dts/mpc836x_mds.dts b/arch/powerpc/boot/dts/mpc836x_mds.dts
index 39ff4c829caf..45cfa1c50a2a 100644
--- a/arch/powerpc/boot/dts/mpc836x_mds.dts
+++ b/arch/powerpc/boot/dts/mpc836x_mds.dts
@@ -99,6 +99,13 @@
                         reg = <0x200 0x100>;
                 };
 
+                pmc: power@b00 {
+                        compatible = "fsl,mpc8360-pmc", "fsl,mpc8349-pmc";
+                        reg = <0xb00 0x100 0xa00 0x100>;
+                        interrupts = <80 0x8>;
+                        interrupt-parent = <&ipic>;
+                };
+
                 i2c@3000 {
                         #address-cells = <1>;
                         #size-cells = <0>;
@@ -194,6 +201,7 @@
                         fsl,channel-fifo-len = <24>;
                         fsl,exec-units-mask = <0x7e>;
                         fsl,descriptor-types-mask = <0x01010ebf>;
+                        sleep = <&pmc 0x03000000>;
                 };
 
                 ipic: pic@700 {
@@ -470,5 +478,6 @@
                        0xe0008300 0x8>;         /* config space access registers */
                 compatible = "fsl,mpc8349-pci";
                 device_type = "pci";
+                sleep = <&pmc 0x00010000>;
         };
 };
diff --git a/arch/powerpc/boot/dts/mpc836x_rdk.dts b/arch/powerpc/boot/dts/mpc836x_rdk.dts
index 6315d6fcc58a..bdf4459677b1 100644
--- a/arch/powerpc/boot/dts/mpc836x_rdk.dts
+++ b/arch/powerpc/boot/dts/mpc836x_rdk.dts
@@ -71,6 +71,13 @@
                         reg = <0x200 0x100>;
                 };
 
+                pmc: power@b00 {
+                        compatible = "fsl,mpc8360-pmc", "fsl,mpc8349-pmc";
+                        reg = <0xb00 0x100 0xa00 0x100>;
+                        interrupts = <80 0x8>;
+                        interrupt-parent = <&ipic>;
+                };
+
                 i2c@3000 {
                         #address-cells = <1>;
                         #size-cells = <0>;
@@ -161,6 +168,7 @@
                         fsl,channel-fifo-len = <24>;
                         fsl,exec-units-mask = <0x7e>;
                         fsl,descriptor-types-mask = <0x01010ebf>;
+                        sleep = <&pmc 0x03000000>;
                 };
 
                 ipic: interrupt-controller@700 {
@@ -455,6 +463,7 @@
                                  0xa800 0 0 2 &ipic 20 8
                                  0xa800 0 0 3 &ipic 21 8
                                  0xa800 0 0 4 &ipic 18 8>;
+                sleep = <&pmc 0x00010000>;
                 /* filled by u-boot */
                 bus-range = <0 0>;
                 clock-frequency = <0>;
diff --git a/arch/powerpc/boot/dts/mpc8568mds.dts b/arch/powerpc/boot/dts/mpc8568mds.dts
index 00c2bbda7013..6d892ba74e55 100644
--- a/arch/powerpc/boot/dts/mpc8568mds.dts
+++ b/arch/powerpc/boot/dts/mpc8568mds.dts
@@ -40,6 +40,8 @@
                         i-cache-line-size = <32>;       // 32 bytes
                         d-cache-size = <0x8000>;                // L1, 32K
                         i-cache-size = <0x8000>;                // L1, 32K
+                        sleep = <&pmc 0x00008000        // core
+                                 &pmc 0x00004000>;      // timebase
                         timebase-frequency = <0>;
                         bus-frequency = <0>;
                         clock-frequency = <0>;
@@ -94,31 +96,41 @@
                         interrupts = <16 2>;
                 };
 
-                i2c@3000 {
+                i2c-sleep-nexus {
                         #address-cells = <1>;
-                        #size-cells = <0>;
-                        cell-index = <0>;
-                        compatible = "fsl-i2c";
-                        reg = <0x3000 0x100>;
-                        interrupts = <43 2>;
-                        interrupt-parent = <&mpic>;
-                        dfsrr;
+                        #size-cells = <1>;
+                        compatible = "simple-bus";
+                        sleep = <&pmc 0x00000004>;
+                        ranges;
 
-                        rtc@68 {
-                                compatible = "dallas,ds1374";
-                                reg = <0x68>;
+                        i2c@3000 {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                cell-index = <0>;
+                                compatible = "fsl-i2c";
+                                reg = <0x3000 0x100>;
+                                interrupts = <43 2>;
+                                interrupt-parent = <&mpic>;
+                                dfsrr;
+
+                                rtc@68 {
+                                        compatible = "dallas,ds1374";
+                                        reg = <0x68>;
+                                        interrupts = <3 1>;
+                                        interrupt-parent = <&mpic>;
+                                };
                         };
-                };
 
-                i2c@3100 {
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                        cell-index = <1>;
-                        compatible = "fsl-i2c";
-                        reg = <0x3100 0x100>;
-                        interrupts = <43 2>;
-                        interrupt-parent = <&mpic>;
-                        dfsrr;
+                        i2c@3100 {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                cell-index = <1>;
+                                compatible = "fsl-i2c";
+                                reg = <0x3100 0x100>;
+                                interrupts = <43 2>;
+                                interrupt-parent = <&mpic>;
+                                dfsrr;
+                        };
                 };
 
                 dma@21300 {
@@ -128,6 +140,8 @@
                         reg = <0x21300 0x4>;
                         ranges = <0x0 0x21100 0x200>;
                         cell-index = <0>;
+                        sleep = <&pmc 0x00000400>;
+
                         dma-channel@0 {
                                 compatible = "fsl,mpc8568-dma-channel",
                                                 "fsl,eloplus-dma-channel";
@@ -176,6 +190,7 @@
                         interrupt-parent = <&mpic>;
                         tbi-handle = <&tbi0>;
                         phy-handle = <&phy2>;
+                        sleep = <&pmc 0x00000080>;
 
                         mdio@520 {
                                 #address-cells = <1>;
@@ -228,6 +243,7 @@
                         interrupt-parent = <&mpic>;
                         tbi-handle = <&tbi1>;
                         phy-handle = <&phy3>;
+                        sleep = <&pmc 0x00000040>;
 
                         mdio@520 {
                                 #address-cells = <1>;
@@ -242,30 +258,47 @@
                         };
                 };
 
-                serial0: serial@4500 {
-                        cell-index = <0>;
-                        device_type = "serial";
-                        compatible = "ns16550";
-                        reg = <0x4500 0x100>;
-                        clock-frequency = <0>;
-                        interrupts = <42 2>;
-                        interrupt-parent = <&mpic>;
+                duart-sleep-nexus {
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        compatible = "simple-bus";
+                        sleep = <&pmc 0x00000002>;
+                        ranges;
+
+                        serial0: serial@4500 {
+                                cell-index = <0>;
+                                device_type = "serial";
+                                compatible = "ns16550";
+                                reg = <0x4500 0x100>;
+                                clock-frequency = <0>;
+                                interrupts = <42 2>;
+                                interrupt-parent = <&mpic>;
+                        };
+
+                        serial1: serial@4600 {
+                                cell-index = <1>;
+                                device_type = "serial";
+                                compatible = "ns16550";
+                                reg = <0x4600 0x100>;
+                                clock-frequency = <0>;
+                                interrupts = <42 2>;
+                                interrupt-parent = <&mpic>;
+                        };
                 };
 
-                global-utilities@e0000 {        //global utilities block
-                        compatible = "fsl,mpc8548-guts";
+                global-utilities@e0000 {
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        compatible = "fsl,mpc8568-guts", "fsl,mpc8548-guts";
                         reg = <0xe0000 0x1000>;
+                        ranges = <0 0xe0000 0x1000>;
                         fsl,has-rstcr;
-                };
 
-                serial1: serial@4600 {
-                        cell-index = <1>;
-                        device_type = "serial";
-                        compatible = "ns16550";
-                        reg = <0x4600 0x100>;
-                        clock-frequency = <0>;
-                        interrupts = <42 2>;
-                        interrupt-parent = <&mpic>;
+                        pmc: power@70 {
+                                compatible = "fsl,mpc8568-pmc",
+                                             "fsl,mpc8548-pmc";
+                                reg = <0x70 0x20>;
+                        };
                 };
 
                 crypto@30000 {
@@ -277,6 +310,7 @@
                         fsl,channel-fifo-len = <24>;
                         fsl,exec-units-mask = <0xfe>;
                         fsl,descriptor-types-mask = <0x12b0ebf>;
+                        sleep = <&pmc 0x01000000>;
                 };
 
                 mpic: pic@40000 {
@@ -376,6 +410,7 @@
                 compatible = "fsl,qe";
                 ranges = <0x0 0xe0080000 0x40000>;
                 reg = <0xe0080000 0x480>;
+                sleep = <&pmc 0x00000800>;
                 brg-frequency = <0>;
                 bus-frequency = <396000000>;
                 fsl,qe-num-riscs = <2>;
@@ -509,6 +544,7 @@
                 bus-range = <0 255>;
                 ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000
                           0x1000000 0x0 0x0 0xe2000000 0x0 0x800000>;
+                sleep = <&pmc 0x80000000>;
                 clock-frequency = <66666666>;
                 #interrupt-cells = <1>;
                 #size-cells = <2>;
@@ -534,6 +570,7 @@
                 bus-range = <0 255>;
                 ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
                           0x1000000 0x0 0x0 0xe2800000 0x0 0x800000>;
+                sleep = <&pmc 0x20000000>;
                 clock-frequency = <33333333>;
                 #interrupt-cells = <1>;
                 #size-cells = <2>;
@@ -570,5 +607,7 @@
                               55 2 /* msg2_tx   */
                               56 2 /* msg2_rx   */>;
                 interrupt-parent = <&mpic>;
+                sleep = <&pmc 0x00080000   /* controller */
+                         &pmc 0x00040000>; /* message unit */
         };
 };
diff --git a/arch/powerpc/boot/dts/mpc8569mds.dts b/arch/powerpc/boot/dts/mpc8569mds.dts
index 1e3ec8f059bf..795eb362fcf9 100644
--- a/arch/powerpc/boot/dts/mpc8569mds.dts
+++ b/arch/powerpc/boot/dts/mpc8569mds.dts
@@ -41,6 +41,8 @@
                         i-cache-line-size = <32>;       // 32 bytes
                         d-cache-size = <0x8000>;                // L1, 32K
                         i-cache-size = <0x8000>;                // L1, 32K
+                        sleep = <&pmc 0x00008000        // core
+                                 &pmc 0x00004000>;      // timebase
                         timebase-frequency = <0>;
                         bus-frequency = <0>;
                         clock-frequency = <0>;
@@ -59,6 +61,7 @@
                 reg = <0xe0005000 0x1000>;
                 interrupts = <19 2>;
                 interrupt-parent = <&mpic>;
+                sleep = <&pmc 0x08000000>;
 
                 ranges = <0x0 0x0 0xfe000000 0x02000000
                           0x1 0x0 0xf8000000 0x00008000
@@ -158,51 +161,69 @@
                         interrupts = <18 2>;
                 };
 
-                i2c@3000 {
+                i2c-sleep-nexus {
                         #address-cells = <1>;
-                        #size-cells = <0>;
-                        cell-index = <0>;
-                        compatible = "fsl-i2c";
-                        reg = <0x3000 0x100>;
-                        interrupts = <43 2>;
-                        interrupt-parent = <&mpic>;
-                        dfsrr;
+                        #size-cells = <1>;
+                        compatible = "simple-bus";
+                        sleep = <&pmc 0x00000004>;
+                        ranges;
+
+                        i2c@3000 {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                cell-index = <0>;
+                                compatible = "fsl-i2c";
+                                reg = <0x3000 0x100>;
+                                interrupts = <43 2>;
+                                interrupt-parent = <&mpic>;
+                                dfsrr;
+
+                                rtc@68 {
+                                        compatible = "dallas,ds1374";
+                                        reg = <0x68>;
+                                        interrupts = <3 1>;
+                                        interrupt-parent = <&mpic>;
+                                };
+                        };
 
-                        rtc@68 {
-                                compatible = "dallas,ds1374";
-                                reg = <0x68>;
+                        i2c@3100 {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                cell-index = <1>;
+                                compatible = "fsl-i2c";
+                                reg = <0x3100 0x100>;
+                                interrupts = <43 2>;
+                                interrupt-parent = <&mpic>;
+                                dfsrr;
                         };
                 };
 
-                i2c@3100 {
+                duart-sleep-nexus {
                         #address-cells = <1>;
-                        #size-cells = <0>;
-                        cell-index = <1>;
-                        compatible = "fsl-i2c";
-                        reg = <0x3100 0x100>;
-                        interrupts = <43 2>;
-                        interrupt-parent = <&mpic>;
-                        dfsrr;
-                };
+                        #size-cells = <1>;
+                        compatible = "simple-bus";
+                        sleep = <&pmc 0x00000002>;
+                        ranges;
 
-                serial0: serial@4500 {
-                        cell-index = <0>;
-                        device_type = "serial";
-                        compatible = "ns16550";
-                        reg = <0x4500 0x100>;
-                        clock-frequency = <0>;
-                        interrupts = <42 2>;
-                        interrupt-parent = <&mpic>;
-                };
+                        serial0: serial@4500 {
+                                cell-index = <0>;
+                                device_type = "serial";
+                                compatible = "ns16550";
+                                reg = <0x4500 0x100>;
+                                clock-frequency = <0>;
+                                interrupts = <42 2>;
+                                interrupt-parent = <&mpic>;
+                        };
 
-                serial1: serial@4600 {
-                        cell-index = <1>;
-                        device_type = "serial";
-                        compatible = "ns16550";
-                        reg = <0x4600 0x100>;
-                        clock-frequency = <0>;
-                        interrupts = <42 2>;
-                        interrupt-parent = <&mpic>;
+                        serial1: serial@4600 {
+                                cell-index = <1>;
+                                device_type = "serial";
+                                compatible = "ns16550";
+                                reg = <0x4600 0x100>;
+                                clock-frequency = <0>;
+                                interrupts = <42 2>;
+                                interrupt-parent = <&mpic>;
+                        };
                 };
 
                 L2: l2-cache-controller@20000 {
@@ -260,6 +281,7 @@
                         reg = <0x2e000 0x1000>;
                         interrupts = <72 0x8>;
                         interrupt-parent = <&mpic>;
+                        sleep = <&pmc 0x00200000>;
                         /* Filled in by U-Boot */
                         clock-frequency = <0>;
                         status = "disabled";
@@ -276,6 +298,7 @@
                         fsl,channel-fifo-len = <24>;
                         fsl,exec-units-mask = <0xbfe>;
                         fsl,descriptor-types-mask = <0x3ab0ebf>;
+                        sleep = <&pmc 0x01000000>;
                 };
 
                 mpic: pic@40000 {
@@ -304,9 +327,18 @@
                 };
 
                 global-utilities@e0000 {
-                        compatible = "fsl,mpc8569-guts";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        compatible = "fsl,mpc8569-guts", "fsl,mpc8548-guts";
                         reg = <0xe0000 0x1000>;
+                        ranges = <0 0xe0000 0x1000>;
                         fsl,has-rstcr;
+
+                        pmc: power@70 {
+                                compatible = "fsl,mpc8569-pmc",
+                                             "fsl,mpc8548-pmc";
+                                reg = <0x70 0x20>;
+                        };
                 };
 
                 par_io@e0100 {
@@ -422,6 +454,7 @@
                 compatible = "fsl,qe";
                 ranges = <0x0 0xe0080000 0x40000>;
                 reg = <0xe0080000 0x480>;
+                sleep = <&pmc 0x00000800>;
                 brg-frequency = <0>;
                 bus-frequency = <0>;
                 fsl,qe-num-riscs = <4>;
@@ -684,6 +717,7 @@
                 bus-range = <0 255>;
                 ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
                           0x1000000 0x0 0x00000000 0xe2800000 0x0 0x00800000>;
+                sleep = <&pmc 0x20000000>;
                 clock-frequency = <33333333>;
                 pcie@0 {
                         reg = <0x0 0x0 0x0 0x0 0x0>;
@@ -714,5 +748,6 @@
                               55 2 /* msg2_tx   */
                               56 2 /* msg2_rx   */>;
                 interrupt-parent = <&mpic>;
+                sleep = <&pmc 0x00080000>;
         };
 };
diff --git a/arch/powerpc/boot/dts/mpc8610_hpcd.dts b/arch/powerpc/boot/dts/mpc8610_hpcd.dts
index f468d215f716..9535ce68caae 100644
--- a/arch/powerpc/boot/dts/mpc8610_hpcd.dts
+++ b/arch/powerpc/boot/dts/mpc8610_hpcd.dts
@@ -35,6 +35,8 @@
                         i-cache-line-size = <32>;
                         d-cache-size = <32768>;         // L1
                         i-cache-size = <32768>;         // L1
+                        sleep = <&pmc 0x00008000 0      // core
+                                 &pmc 0x00004000 0>;    // timebase
                         timebase-frequency = <0>;       // From uboot
                         bus-frequency = <0>;            // From uboot
                         clock-frequency = <0>;          // From uboot
@@ -60,6 +62,7 @@
                           5 0 0xe8480000 0x00008000
                           6 0 0xe84c0000 0x00008000
                           3 0 0xe8000000 0x00000020>;
+                sleep = <&pmc 0x08000000 0>;
 
                 flash@0,0 {
                         compatible = "cfi-flash";
@@ -105,6 +108,8 @@
                         compatible = "fsl,fpga-pixis";
                         reg = <3 0 0x20>;
                         ranges = <0 3 0 0x20>;
+                        interrupt-parent = <&mpic>;
+                        interrupts = <8 8>;
 
                         sdcsr_pio: gpio-controller@a {
                                 #gpio-cells = <2>;
@@ -163,6 +168,7 @@
                         reg = <0x3100 0x100>;
                         interrupts = <43 2>;
                         interrupt-parent = <&mpic>;
+                        sleep = <&pmc 0x00000004 0>;
                         dfsrr;
                 };
 
@@ -174,6 +180,7 @@
                         clock-frequency = <0>;
                         interrupts = <42 2>;
                         interrupt-parent = <&mpic>;
+                        sleep = <&pmc 0x00000002 0>;
                 };
 
                 serial1: serial@4600 {
@@ -184,6 +191,7 @@
                         clock-frequency = <0>;
                         interrupts = <42 2>;
                         interrupt-parent = <&mpic>;
+                        sleep = <&pmc 0x00000008 0>;
                 };
 
                 spi@7000 {
@@ -196,6 +204,7 @@
                         interrupt-parent = <&mpic>;
                         mode = "cpu";
                         gpios = <&sdcsr_pio 7 0>;
+                        sleep = <&pmc 0x00000800 0>;
 
                         mmc-slot@0 {
                                 compatible = "fsl,mpc8610hpcd-mmc-slot",
@@ -213,6 +222,7 @@
                         reg = <0x2c000 100>;
                         interrupts = <72 2>;
                         interrupt-parent = <&mpic>;
+                        sleep = <&pmc 0x04000000 0>;
                 };
 
                 mpic: interrupt-controller@40000 {
@@ -241,9 +251,18 @@
                 };
 
                 global-utilities@e0000 {
+                        #address-cells = <1>;
+                        #size-cells = <1>;
                         compatible = "fsl,mpc8610-guts";
                         reg = <0xe0000 0x1000>;
+                        ranges = <0 0xe0000 0x1000>;
                         fsl,has-rstcr;
+
+                        pmc: power@70 {
+                                compatible = "fsl,mpc8610-pmc",
+                                             "fsl,mpc8641d-pmc";
+                                reg = <0x70 0x20>;
+                        };
                 };
 
                 wdt@e4000 {
@@ -262,6 +281,7 @@
                         fsl,playback-dma = <&dma00>;
                         fsl,capture-dma = <&dma01>;
                         fsl,fifo-depth = <8>;
+                        sleep = <&pmc 0 0x08000000>;
                 };
 
                 ssi@16100 {
@@ -271,6 +291,7 @@
                         interrupt-parent = <&mpic>;
                         interrupts = <63 2>;
                         fsl,fifo-depth = <8>;
+                        sleep = <&pmc 0 0x04000000>;
                 };
 
                 dma@21300 {
@@ -280,6 +301,7 @@
                         cell-index = <0>;
                         reg = <0x21300 0x4>; /* DMA general status register */
                         ranges = <0x0 0x21100 0x200>;
+                        sleep = <&pmc 0x00000400 0>;
 
                         dma00: dma-channel@0 {
                                 compatible = "fsl,mpc8610-dma-channel",
@@ -322,6 +344,7 @@
                         cell-index = <1>;
                         reg = <0xc300 0x4>; /* DMA general status register */
                         ranges = <0x0 0xc100 0x200>;
+                        sleep = <&pmc 0x00000200 0>;
 
                         dma-channel@0 {
                                 compatible = "fsl,mpc8610-dma-channel",
@@ -369,6 +392,7 @@
                 bus-range = <0 0>;
                 ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x10000000
                           0x01000000 0x0 0x00000000 0xe1000000 0x0 0x00100000>;
+                sleep = <&pmc 0x80000000 0>;
                 clock-frequency = <33333333>;
                 interrupt-parent = <&mpic>;
                 interrupts = <24 2>;
@@ -398,6 +422,7 @@
                 bus-range = <1 3>;
                 ranges = <0x02000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
                           0x01000000 0x0 0x00000000 0xe3000000 0x0 0x00100000>;
+                sleep = <&pmc 0x40000000 0>;
                 clock-frequency = <33333333>;
                 interrupt-parent = <&mpic>;
                 interrupts = <26 2>;
@@ -474,6 +499,7 @@
                                  0x0000 0 0 4 &mpic 7 1>;
                 interrupt-parent = <&mpic>;
                 interrupts = <25 2>;
+                sleep = <&pmc 0x20000000 0>;
                 clock-frequency = <33333333>;
         };
 };
diff --git a/arch/powerpc/boot/dts/p1020rdb.dts b/arch/powerpc/boot/dts/p1020rdb.dts
new file mode 100644
index 000000000000..df5269093af8
--- /dev/null
+++ b/arch/powerpc/boot/dts/p1020rdb.dts
@@ -0,0 +1,477 @@
+/*
+ * P1020 RDB Device Tree Source
+ *
+ * Copyright 2009 Freescale Semiconductor Inc.
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+/dts-v1/;
+/ {
+        model = "fsl,P1020";
+        compatible = "fsl,P1020RDB";
+        #address-cells = <2>;
+        #size-cells = <2>;
+
+        aliases {
+                serial0 = &serial0;
+                serial1 = &serial1;
+                pci0 = &pci0;
+                pci1 = &pci1;
+        };
+
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                PowerPC,P1020@0 {
+                        device_type = "cpu";
+                        reg = <0x0>;
+                        next-level-cache = <&L2>;
+                };
+
+                PowerPC,P1020@1 {
+                        device_type = "cpu";
+                        reg = <0x1>;
+                        next-level-cache = <&L2>;
+                };
+        };
+
+        memory {
+                device_type = "memory";
+        };
+
+        localbus@ffe05000 {
+                #address-cells = <2>;
+                #size-cells = <1>;
+                compatible = "fsl,p1020-elbc", "fsl,elbc", "simple-bus";
+                reg = <0 0xffe05000 0 0x1000>;
+                interrupts = <19 2>;
+                interrupt-parent = <&mpic>;
+
+                /* NOR, NAND Flashes and Vitesse 5 port L2 switch */
+                ranges = <0x0 0x0 0x0 0xef000000 0x01000000
+                          0x1 0x0 0x0 0xffa00000 0x00040000
+                          0x2 0x0 0x0 0xffb00000 0x00020000>;
+
+                nor@0,0 {
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        compatible = "cfi-flash";
+                        reg = <0x0 0x0 0x1000000>;
+                        bank-width = <2>;
+                        device-width = <1>;
+
+                        partition@0 {
+                                /* This location must not be altered  */
+                                /* 256KB for Vitesse 7385 Switch firmware */
+                                reg = <0x0 0x00040000>;
+                                label = "NOR (RO) Vitesse-7385 Firmware";
+                                read-only;
+                        };
+
+                        partition@40000 {
+                                /* 256KB for DTB Image */
+                                reg = <0x00040000 0x00040000>;
+                                label = "NOR (RO) DTB Image";
+                                read-only;
+                        };
+
+                        partition@80000 {
+                                /* 3.5 MB for Linux Kernel Image */
+                                reg = <0x00080000 0x00380000>;
+                                label = "NOR (RO) Linux Kernel Image";
+                                read-only;
+                        };
+
+                        partition@400000 {
+                                /* 11MB for JFFS2 based Root file System */
+                                reg = <0x00400000 0x00b00000>;
+                                label = "NOR (RW) JFFS2 Root File System";
+                        };
+
+                        partition@f00000 {
+                                /* This location must not be altered  */
+                                /* 512KB for u-boot Bootloader Image */
+                                /* 512KB for u-boot Environment Variables */
+                                reg = <0x00f00000 0x00100000>;
+                                label = "NOR (RO) U-Boot Image";
+                                read-only;
+                        };
+                };
+
+                nand@1,0 {
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        compatible = "fsl,p1020-fcm-nand",
+                                     "fsl,elbc-fcm-nand";
+                        reg = <0x1 0x0 0x40000>;
+
+                        partition@0 {
+                                /* This location must not be altered  */
+                                /* 1MB for u-boot Bootloader Image */
+                                reg = <0x0 0x00100000>;
+                                label = "NAND (RO) U-Boot Image";
+                                read-only;
+                        };
+
+                        partition@100000 {
+                                /* 1MB for DTB Image */
+                                reg = <0x00100000 0x00100000>;
+                                label = "NAND (RO) DTB Image";
+                                read-only;
+                        };
+
+                        partition@200000 {
+                                /* 4MB for Linux Kernel Image */
+                                reg = <0x00200000 0x00400000>;
+                                label = "NAND (RO) Linux Kernel Image";
+                                read-only;
+                        };
+
+                        partition@600000 {
+                                /* 4MB for Compressed Root file System Image */
+                                reg = <0x00600000 0x00400000>;
+                                label = "NAND (RO) Compressed RFS Image";
+                                read-only;
+                        };
+
+                        partition@a00000 {
+                                /* 7MB for JFFS2 based Root file System */
+                                reg = <0x00a00000 0x00700000>;
+                                label = "NAND (RW) JFFS2 Root File System";
+                        };
+
+                        partition@1100000 {
+                                /* 15MB for JFFS2 based Root file System */
+                                reg = <0x01100000 0x00f00000>;
+                                label = "NAND (RW) Writable User area";
+                        };
+                };
+
+                L2switch@2,0 {
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        compatible = "vitesse-7385";
+                        reg = <0x2 0x0 0x20000>;
+                };
+
+        };
+
+        soc@ffe00000 {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                device_type = "soc";
+                compatible = "fsl,p1020-immr", "simple-bus";
+                ranges = <0x0  0x0 0xffe00000 0x100000>;
+                bus-frequency = <0>;            // Filled out by uboot.
+
+                ecm-law@0 {
+                        compatible = "fsl,ecm-law";
+                        reg = <0x0 0x1000>;
+                        fsl,num-laws = <12>;
+                };
+
+                ecm@1000 {
+                        compatible = "fsl,p1020-ecm", "fsl,ecm";
+                        reg = <0x1000 0x1000>;
+                        interrupts = <16 2>;
+                        interrupt-parent = <&mpic>;
+                };
+
+                memory-controller@2000 {
+                        compatible = "fsl,p1020-memory-controller";
+                        reg = <0x2000 0x1000>;
+                        interrupt-parent = <&mpic>;
+                        interrupts = <16 2>;
+                };
+
+                i2c@3000 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        cell-index = <0>;
+                        compatible = "fsl-i2c";
+                        reg = <0x3000 0x100>;
+                        interrupts = <43 2>;
+                        interrupt-parent = <&mpic>;
+                        dfsrr;
+                        rtc@68 {
+                                compatible = "dallas,ds1339";
+                                reg = <0x68>;
+                        };
+                };
+
+                i2c@3100 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        cell-index = <1>;
+                        compatible = "fsl-i2c";
+                        reg = <0x3100 0x100>;
+                        interrupts = <43 2>;
+                        interrupt-parent = <&mpic>;
+                        dfsrr;
+                };
+
+                serial0: serial@4500 {
+                        cell-index = <0>;
+                        device_type = "serial";
+                        compatible = "ns16550";
+                        reg = <0x4500 0x100>;
+                        clock-frequency = <0>;
+                        interrupts = <42 2>;
+                        interrupt-parent = <&mpic>;
+                };
+
+                serial1: serial@4600 {
+                        cell-index = <1>;
+                        device_type = "serial";
+                        compatible = "ns16550";
+                        reg = <0x4600 0x100>;
+                        clock-frequency = <0>;
+                        interrupts = <42 2>;
+                        interrupt-parent = <&mpic>;
+                };
+
+                spi@7000 {
+                        cell-index = <0>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "fsl,espi";
+                        reg = <0x7000 0x1000>;
+                        interrupts = <59 0x2>;
+                        interrupt-parent = <&mpic>;
+                        mode = "cpu";
+
+                        fsl_m25p80@0 {
+                                #address-cells = <1>;
+                                #size-cells = <1>;
+                                compatible = "fsl,espi-flash";
+                                reg = <0>;
+                                linux,modalias = "fsl_m25p80";
+                                modal = "s25sl128b";
+                                spi-max-frequency = <50000000>;
+                                mode = <0>;
+
+                                partition@0 {
+                                        /* 512KB for u-boot Bootloader Image */
+                                        reg = <0x0 0x00080000>;
+                                        label = "SPI (RO) U-Boot Image";
+                                        read-only;
+                                };
+
+                                partition@80000 {
+                                        /* 512KB for DTB Image */
+                                        reg = <0x00080000 0x00080000>;
+                                        label = "SPI (RO) DTB Image";
+                                        read-only;
+                                };
+
+                                partition@100000 {
+                                        /* 4MB for Linux Kernel Image */
+                                        reg = <0x00100000 0x00400000>;
+                                        label = "SPI (RO) Linux Kernel Image";
+                                        read-only;
+                                };
+
+                                partition@500000 {
+                                        /* 4MB for Compressed RFS Image */
+                                        reg = <0x00500000 0x00400000>;
+                                        label = "SPI (RO) Compressed RFS Image";
+                                        read-only;
+                                };
+
+                                partition@900000 {
+                                        /* 7MB for JFFS2 based RFS */
+                                        reg = <0x00900000 0x00700000>;
+                                        label = "SPI (RW) JFFS2 RFS";
+                                };
+                        };
+                };
+
+                gpio: gpio-controller@f000 {
+                        #gpio-cells = <2>;
+                        compatible = "fsl,mpc8572-gpio";
+                        reg = <0xf000 0x100>;
+                        interrupts = <47 0x2>;
+                        interrupt-parent = <&mpic>;
+                        gpio-controller;
+                };
+
+                L2: l2-cache-controller@20000 {
+                        compatible = "fsl,p1020-l2-cache-controller";
+                        reg = <0x20000 0x1000>;
+                        cache-line-size = <32>; // 32 bytes
+                        cache-size = <0x40000>; // L2,256K
+                        interrupt-parent = <&mpic>;
+                        interrupts = <16 2>;
+                };
+
+                dma@21300 {
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        compatible = "fsl,eloplus-dma";
+                        reg = <0x21300 0x4>;
+                        ranges = <0x0 0x21100 0x200>;
+                        cell-index = <0>;
+                        dma-channel@0 {
+                                compatible = "fsl,eloplus-dma-channel";
+                                reg = <0x0 0x80>;
+                                cell-index = <0>;
+                                interrupt-parent = <&mpic>;
+                                interrupts = <20 2>;
+                        };
+                        dma-channel@80 {
+                                compatible = "fsl,eloplus-dma-channel";
+                                reg = <0x80 0x80>;
+                                cell-index = <1>;
+                                interrupt-parent = <&mpic>;
+                                interrupts = <21 2>;
+                        };
+                        dma-channel@100 {
+                                compatible = "fsl,eloplus-dma-channel";
+                                reg = <0x100 0x80>;
+                                cell-index = <2>;
+                                interrupt-parent = <&mpic>;
+                                interrupts = <22 2>;
+                        };
+                        dma-channel@180 {
+                                compatible = "fsl,eloplus-dma-channel";
+                                reg = <0x180 0x80>;
+                                cell-index = <3>;
+                                interrupt-parent = <&mpic>;
+                                interrupts = <23 2>;
+                        };
+                };
+
+                usb@22000 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "fsl-usb2-dr";
+                        reg = <0x22000 0x1000>;
+                        interrupt-parent = <&mpic>;
+                        interrupts = <28 0x2>;
+                        phy_type = "ulpi";
+                };
+
+                usb@23000 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "fsl-usb2-dr";
+                        reg = <0x23000 0x1000>;
+                        interrupt-parent = <&mpic>;
+                        interrupts = <46 0x2>;
+                        phy_type = "ulpi";
+                };
+
+                sdhci@2e000 {
+                        compatible = "fsl,p1020-esdhc", "fsl,esdhc";
+                        reg = <0x2e000 0x1000>;
+                        interrupts = <72 0x2>;
+                        interrupt-parent = <&mpic>;
+                        /* Filled in by U-Boot */
+                        clock-frequency = <0>;
+                };
+
+                crypto@30000 {
+                        compatible = "fsl,sec3.1", "fsl,sec3.0", "fsl,sec2.4",
+                                     "fsl,sec2.2", "fsl,sec2.1", "fsl,sec2.0";
+                        reg = <0x30000 0x10000>;
+                        interrupts = <45 2 58 2>;
+                        interrupt-parent = <&mpic>;
+                        fsl,num-channels = <4>;
+                        fsl,channel-fifo-len = <24>;
+                        fsl,exec-units-mask = <0xbfe>;
+                        fsl,descriptor-types-mask = <0x3ab0ebf>;
+                };
+
+                mpic: pic@40000 {
+                        interrupt-controller;
+                        #address-cells = <0>;
+                        #interrupt-cells = <2>;
+                        reg = <0x40000 0x40000>;
+                        compatible = "chrp,open-pic";
+                        device_type = "open-pic";
+                };
+
+                msi@41600 {
+                        compatible = "fsl,p1020-msi", "fsl,mpic-msi";
+                        reg = <0x41600 0x80>;
+                        msi-available-ranges = <0 0x100>;
+                        interrupts = <
+                                0xe0 0
+                                0xe1 0
+                                0xe2 0
+                                0xe3 0
+                                0xe4 0
+                                0xe5 0
+                                0xe6 0
+                                0xe7 0>;
+                        interrupt-parent = <&mpic>;
+                };
+
+                global-utilities@e0000 {        //global utilities block
+                        compatible = "fsl,p1020-guts";
+                        reg = <0xe0000 0x1000>;
+                        fsl,has-rstcr;
+                };
+        };
+
+        pci0: pcie@ffe09000 {
+                compatible = "fsl,mpc8548-pcie";
+                device_type = "pci";
+                #interrupt-cells = <1>;
+                #size-cells = <2>;
+                #address-cells = <3>;
+                reg = <0 0xffe09000 0 0x1000>;
+                bus-range = <0 255>;
+                ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
+                          0x1000000 0x0 0x00000000 0 0xffc30000 0x0 0x10000>;
+                clock-frequency = <33333333>;
+                interrupt-parent = <&mpic>;
+                interrupts = <16 2>;
+                pcie@0 {
+                        reg = <0x0 0x0 0x0 0x0 0x0>;
+                        #size-cells = <2>;
+                        #address-cells = <3>;
+                        device_type = "pci";
+                        ranges = <0x2000000 0x0 0xa0000000
+                                  0x2000000 0x0 0xa0000000
+                                  0x0 0x20000000
+
+                                  0x1000000 0x0 0x0
+                                  0x1000000 0x0 0x0
+                                  0x0 0x100000>;
+                };
+        };
+
+        pci1: pcie@ffe0a000 {
+                compatible = "fsl,mpc8548-pcie";
+                device_type = "pci";
+                #interrupt-cells = <1>;
+                #size-cells = <2>;
+                #address-cells = <3>;
+                reg = <0 0xffe0a000 0 0x1000>;
+                bus-range = <0 255>;
+                ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x20000000
+                          0x1000000 0x0 0x00000000 0 0xffc20000 0x0 0x10000>;
+                clock-frequency = <33333333>;
+                interrupt-parent = <&mpic>;
+                interrupts = <16 2>;
+                pcie@0 {
+                        reg = <0x0 0x0 0x0 0x0 0x0>;
+                        #size-cells = <2>;
+                        #address-cells = <3>;
+                        device_type = "pci";
+                        ranges = <0x2000000 0x0 0xc0000000
+                                  0x2000000 0x0 0xc0000000
+                                  0x0 0x20000000
+
+                                  0x1000000 0x0 0x0
+                                  0x1000000 0x0 0x0
+                                  0x0 0x100000>;
+                };
+        };
+};
diff --git a/arch/powerpc/boot/dts/p2020rdb_camp_core0.dts b/arch/powerpc/boot/dts/p2020rdb_camp_core0.dts
new file mode 100644
index 000000000000..0fe93d0c8b2e
--- /dev/null
+++ b/arch/powerpc/boot/dts/p2020rdb_camp_core0.dts
@@ -0,0 +1,363 @@
+/*
+ * P2020 RDB  Core0 Device Tree Source in CAMP mode.
+ *
+ * In CAMP mode, each core needs to have its own dts. Only mpic and L2 cache
+ * can be shared, all the other devices must be assigned to one core only.
+ * This dts file allows core0 to have memory, l2, i2c, spi, gpio, dma1, usb,
+ * eth1, eth2, sdhc, crypto, global-util, pci0.
+ *
+ * Copyright 2009 Freescale Semiconductor Inc.
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+/dts-v1/;
+/ {
+        model = "fsl,P2020";
+        compatible = "fsl,P2020RDB", "fsl,MPC85XXRDB-CAMP";
+        #address-cells = <2>;
+        #size-cells = <2>;
+
+        aliases {
+                ethernet1 = &enet1;
+                ethernet2 = &enet2;
+                serial0 = &serial0;
+                pci0 = &pci0;
+        };
+
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                PowerPC,P2020@0 {
+                        device_type = "cpu";
+                        reg = <0x0>;
+                        next-level-cache = <&L2>;
+                };
+        };
+
+        memory {
+                device_type = "memory";
+        };
+
+        soc@ffe00000 {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                device_type = "soc";
+                compatible = "fsl,p2020-immr", "simple-bus";
+                ranges = <0x0  0x0 0xffe00000 0x100000>;
+                bus-frequency = <0>;            // Filled out by uboot.
+
+                ecm-law@0 {
+                        compatible = "fsl,ecm-law";
+                        reg = <0x0 0x1000>;
+                        fsl,num-laws = <12>;
+                };
+
+                ecm@1000 {
+                        compatible = "fsl,p2020-ecm", "fsl,ecm";
+                        reg = <0x1000 0x1000>;
+                        interrupts = <17 2>;
+                        interrupt-parent = <&mpic>;
+                };
+
+                memory-controller@2000 {
+                        compatible = "fsl,p2020-memory-controller";
+                        reg = <0x2000 0x1000>;
+                        interrupt-parent = <&mpic>;
+                        interrupts = <18 2>;
+                };
+
+                i2c@3000 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        cell-index = <0>;
+                        compatible = "fsl-i2c";
+                        reg = <0x3000 0x100>;
+                        interrupts = <43 2>;
+                        interrupt-parent = <&mpic>;
+                        dfsrr;
+                        rtc@68 {
+                                compatible = "dallas,ds1339";
+                                reg = <0x68>;
+                        };
+                };
+
+                i2c@3100 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        cell-index = <1>;
+                        compatible = "fsl-i2c";
+                        reg = <0x3100 0x100>;
+                        interrupts = <43 2>;
+                        interrupt-parent = <&mpic>;
+                        dfsrr;
+                };
+
+                serial0: serial@4500 {
+                        cell-index = <0>;
+                        device_type = "serial";
+                        compatible = "ns16550";
+                        reg = <0x4500 0x100>;
+                        clock-frequency = <0>;
+                };
+
+                spi@7000 {
+                        cell-index = <0>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "fsl,espi";
+                        reg = <0x7000 0x1000>;
+                        interrupts = <59 0x2>;
+                        interrupt-parent = <&mpic>;
+                        mode = "cpu";
+
+                        fsl_m25p80@0 {
+                                #address-cells = <1>;
+                                #size-cells = <1>;
+                                compatible = "fsl,espi-flash";
+                                reg = <0>;
+                                linux,modalias = "fsl_m25p80";
+                                modal = "s25sl128b";
+                                spi-max-frequency = <50000000>;
+                                mode = <0>;
+
+                                partition@0 {
+                                        /* 512KB for u-boot Bootloader Image */
+                                        reg = <0x0 0x00080000>;
+                                        label = "SPI (RO) U-Boot Image";
+                                        read-only;
+                                };
+
+                                partition@80000 {
+                                        /* 512KB for DTB Image */
+                                        reg = <0x00080000 0x00080000>;
+                                        label = "SPI (RO) DTB Image";
+                                        read-only;
+                                };
+
+                                partition@100000 {
+                                        /* 4MB for Linux Kernel Image */
+                                        reg = <0x00100000 0x00400000>;
+                                        label = "SPI (RO) Linux Kernel Image";
+                                        read-only;
+                                };
+
+                                partition@500000 {
+                                        /* 4MB for Compressed RFS Image */
+                                        reg = <0x00500000 0x00400000>;
+                                        label = "SPI (RO) Compressed RFS Image";
+                                        read-only;
+                                };
+
+                                partition@900000 {
+                                        /* 7MB for JFFS2 based RFS */
+                                        reg = <0x00900000 0x00700000>;
+                                        label = "SPI (RW) JFFS2 RFS";
+                                };
+                        };
+                };
+
+                gpio: gpio-controller@f000 {
+                        #gpio-cells = <2>;
+                        compatible = "fsl,mpc8572-gpio";
+                        reg = <0xf000 0x100>;
+                        interrupts = <47 0x2>;
+                        interrupt-parent = <&mpic>;
+                        gpio-controller;
+                };
+
+                L2: l2-cache-controller@20000 {
+                        compatible = "fsl,p2020-l2-cache-controller";
+                        reg = <0x20000 0x1000>;
+                        cache-line-size = <32>; // 32 bytes
+                        cache-size = <0x80000>; // L2,512K
+                        interrupt-parent = <&mpic>;
+                        interrupts = <16 2>;
+                };
+
+                dma@21300 {
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        compatible = "fsl,eloplus-dma";
+                        reg = <0x21300 0x4>;
+                        ranges = <0x0 0x21100 0x200>;
+                        cell-index = <0>;
+                        dma-channel@0 {
+                                compatible = "fsl,eloplus-dma-channel";
+                                reg = <0x0 0x80>;
+                                cell-index = <0>;
+                                interrupt-parent = <&mpic>;
+                                interrupts = <20 2>;
+                        };
+                        dma-channel@80 {
+                                compatible = "fsl,eloplus-dma-channel";
+                                reg = <0x80 0x80>;
+                                cell-index = <1>;
+                                interrupt-parent = <&mpic>;
+                                interrupts = <21 2>;
+                        };
+                        dma-channel@100 {
+                                compatible = "fsl,eloplus-dma-channel";
+                                reg = <0x100 0x80>;
+                                cell-index = <2>;
+                                interrupt-parent = <&mpic>;
+                                interrupts = <22 2>;
+                        };
+                        dma-channel@180 {
+                                compatible = "fsl,eloplus-dma-channel";
+                                reg = <0x180 0x80>;
+                                cell-index = <3>;
+                                interrupt-parent = <&mpic>;
+                                interrupts = <23 2>;
+                        };
+                };
+
+                usb@22000 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "fsl-usb2-dr";
+                        reg = <0x22000 0x1000>;
+                        interrupt-parent = <&mpic>;
+                        interrupts = <28 0x2>;
+                        phy_type = "ulpi";
+                };
+
+                mdio@24520 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "fsl,gianfar-mdio";
+                        reg = <0x24520 0x20>;
+
+                        phy0: ethernet-phy@0 {
+                                interrupt-parent = <&mpic>;
+                                interrupts = <3 1>;
+                                reg = <0x0>;
+                        };
+                        phy1: ethernet-phy@1 {
+                                interrupt-parent = <&mpic>;
+                                interrupts = <3 1>;
+                                reg = <0x1>;
+                        };
+                };
+
+                mdio@25520 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "fsl,gianfar-tbi";
+                        reg = <0x26520 0x20>;
+
+                        tbi0: tbi-phy@11 {
+                                reg = <0x11>;
+                                device_type = "tbi-phy";
+                        };
+                };
+
+                enet1: ethernet@25000 {
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        cell-index = <1>;
+                        device_type = "network";
+                        model = "eTSEC";
+                        compatible = "gianfar";
+                        reg = <0x25000 0x1000>;
+                        ranges = <0x0 0x25000 0x1000>;
+                        local-mac-address = [ 00 00 00 00 00 00 ];
+                        interrupts = <35 2 36 2 40 2>;
+                        interrupt-parent = <&mpic>;
+                        tbi-handle = <&tbi0>;
+                        phy-handle = <&phy0>;
+                        phy-connection-type = "sgmii";
+
+                };
+
+                enet2: ethernet@26000 {
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        cell-index = <2>;
+                        device_type = "network";
+                        model = "eTSEC";
+                        compatible = "gianfar";
+                        reg = <0x26000 0x1000>;
+                        ranges = <0x0 0x26000 0x1000>;
+                        local-mac-address = [ 00 00 00 00 00 00 ];
+                        interrupts = <31 2 32 2 33 2>;
+                        interrupt-parent = <&mpic>;
+                        phy-handle = <&phy1>;
+                        phy-connection-type = "rgmii-id";
+                };
+
+                sdhci@2e000 {
+                        compatible = "fsl,p2020-esdhc", "fsl,esdhc";
+                        reg = <0x2e000 0x1000>;
+                        interrupts = <72 0x2>;
+                        interrupt-parent = <&mpic>;
+                        /* Filled in by U-Boot */
+                        clock-frequency = <0>;
+                };
+
+                crypto@30000 {
+                        compatible = "fsl,sec3.1", "fsl,sec3.0", "fsl,sec2.4",
+                                     "fsl,sec2.2", "fsl,sec2.1", "fsl,sec2.0";
+                        reg = <0x30000 0x10000>;
+                        interrupts = <45 2 58 2>;
+                        interrupt-parent = <&mpic>;
+                        fsl,num-channels = <4>;
+                        fsl,channel-fifo-len = <24>;
+                        fsl,exec-units-mask = <0xbfe>;
+                        fsl,descriptor-types-mask = <0x3ab0ebf>;
+                };
+
+                mpic: pic@40000 {
+                        interrupt-controller;
+                        #address-cells = <0>;
+                        #interrupt-cells = <2>;
+                        reg = <0x40000 0x40000>;
+                        compatible = "chrp,open-pic";
+                        device_type = "open-pic";
+                        protected-sources = <
+                        42 76 77 78 79 /* serial1 , dma2 */
+                        29 30 34 26 /* enet0, pci1 */
+                        0xe0 0xe1 0xe2 0xe3 /* msi */
+                        0xe4 0xe5 0xe6 0xe7
+                        >;
+                };
+
+                global-utilities@e0000 {
+                        compatible = "fsl,p2020-guts";
+                        reg = <0xe0000 0x1000>;
+                        fsl,has-rstcr;
+                };
+        };
+
+        pci0: pcie@ffe09000 {
+                compatible = "fsl,mpc8548-pcie";
+                device_type = "pci";
+                #interrupt-cells = <1>;
+                #size-cells = <2>;
+                #address-cells = <3>;
+                reg = <0 0xffe09000 0 0x1000>;
+                bus-range = <0 255>;
+                ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
+                          0x1000000 0x0 0x00000000 0 0xffc30000 0x0 0x10000>;
+                clock-frequency = <33333333>;
+                interrupt-parent = <&mpic>;
+                interrupts = <25 2>;
+                pcie@0 {
+                        reg = <0x0 0x0 0x0 0x0 0x0>;
+                        #size-cells = <2>;
+                        #address-cells = <3>;
+                        device_type = "pci";
+                        ranges = <0x2000000 0x0 0xa0000000
+                                  0x2000000 0x0 0xa0000000
+                                  0x0 0x20000000
+
+                                  0x1000000 0x0 0x0
+                                  0x1000000 0x0 0x0
+                                  0x0 0x100000>;
+                };
+        };
+};
diff --git a/arch/powerpc/boot/dts/p2020rdb_camp_core1.dts b/arch/powerpc/boot/dts/p2020rdb_camp_core1.dts
new file mode 100644
index 000000000000..e95a51285328
--- /dev/null
+++ b/arch/powerpc/boot/dts/p2020rdb_camp_core1.dts
@@ -0,0 +1,184 @@
+/*
+ * P2020 RDB Core1 Device Tree Source in CAMP mode.
+ *
+ * In CAMP mode, each core needs to have its own dts. Only mpic and L2 cache
+ * can be shared, all the other devices must be assigned to one core only.
+ * This dts allows core1 to have l2, dma2, eth0, pci1, msi.
+ *
+ * Please note to add "-b 1" for core1's dts compiling.
+ *
+ * Copyright 2009 Freescale Semiconductor Inc.
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+/dts-v1/;
+/ {
+        model = "fsl,P2020";
+        compatible = "fsl,P2020RDB", "fsl,MPC85XXRDB-CAMP";
+        #address-cells = <2>;
+        #size-cells = <2>;
+
+        aliases {
+                ethernet0 = &enet0;
+                serial0 = &serial0;
+                pci1 = &pci1;
+        };
+
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                PowerPC,P2020@1 {
+                        device_type = "cpu";
+                        reg = <0x1>;
+                        next-level-cache = <&L2>;
+                };
+        };
+
+        memory {
+                device_type = "memory";
+        };
+
+        soc@ffe00000 {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                device_type = "soc";
+                compatible = "fsl,p2020-immr", "simple-bus";
+                ranges = <0x0  0x0 0xffe00000 0x100000>;
+                bus-frequency = <0>;            // Filled out by uboot.
+
+                serial0: serial@4600 {
+                        cell-index = <1>;
+                        device_type = "serial";
+                        compatible = "ns16550";
+                        reg = <0x4600 0x100>;
+                        clock-frequency = <0>;
+                };
+
+                dma@c300 {
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        compatible = "fsl,eloplus-dma";
+                        reg = <0xc300 0x4>;
+                        ranges = <0x0 0xc100 0x200>;
+                        cell-index = <1>;
+                        dma-channel@0 {
+                                compatible = "fsl,eloplus-dma-channel";
+                                reg = <0x0 0x80>;
+                                cell-index = <0>;
+                                interrupt-parent = <&mpic>;
+                                interrupts = <76 2>;
+                        };
+                        dma-channel@80 {
+                                compatible = "fsl,eloplus-dma-channel";
+                                reg = <0x80 0x80>;
+                                cell-index = <1>;
+                                interrupt-parent = <&mpic>;
+                                interrupts = <77 2>;
+                        };
+                        dma-channel@100 {
+                                compatible = "fsl,eloplus-dma-channel";
+                                reg = <0x100 0x80>;
+                                cell-index = <2>;
+                                interrupt-parent = <&mpic>;
+                                interrupts = <78 2>;
+                        };
+                        dma-channel@180 {
+                                compatible = "fsl,eloplus-dma-channel";
+                                reg = <0x180 0x80>;
+                                cell-index = <3>;
+                                interrupt-parent = <&mpic>;
+                                interrupts = <79 2>;
+                        };
+                };
+
+                L2: l2-cache-controller@20000 {
+                        compatible = "fsl,p2020-l2-cache-controller";
+                        reg = <0x20000 0x1000>;
+                        cache-line-size = <32>; // 32 bytes
+                        cache-size = <0x80000>; // L2,512K
+                        interrupt-parent = <&mpic>;
+                };
+
+
+                enet0: ethernet@24000 {
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        cell-index = <0>;
+                        device_type = "network";
+                        model = "eTSEC";
+                        compatible = "gianfar";
+                        reg = <0x24000 0x1000>;
+                        ranges = <0x0 0x24000 0x1000>;
+                        local-mac-address = [ 00 00 00 00 00 00 ];
+                        interrupts = <29 2 30 2 34 2>;
+                        interrupt-parent = <&mpic>;
+                        fixed-link = <1 1 1000 0 0>;
+                        phy-connection-type = "rgmii-id";
+
+                };
+
+                mpic: pic@40000 {
+                        interrupt-controller;
+                        #address-cells = <0>;
+                        #interrupt-cells = <2>;
+                        reg = <0x40000 0x40000>;
+                        compatible = "chrp,open-pic";
+                        device_type = "open-pic";
+                        protected-sources = <
+                        17 18 43 42 59 47 /*ecm, mem, i2c, serial0, spi,gpio */
+                        16 20 21 22 23 28       /* L2, dma1, USB */
+                        03 35 36 40 31 32 33    /* mdio, enet1, enet2 */
+                        72 45 58 25             /* sdhci, crypto , pci */
+                        >;
+                };
+
+                msi@41600 {
+                        compatible = "fsl,p2020-msi", "fsl,mpic-msi";
+                        reg = <0x41600 0x80>;
+                        msi-available-ranges = <0 0x100>;
+                        interrupts = <
+                                0xe0 0
+                                0xe1 0
+                                0xe2 0
+                                0xe3 0
+                                0xe4 0
+                                0xe5 0
+                                0xe6 0
+                                0xe7 0>;
+                        interrupt-parent = <&mpic>;
+                };
+        };
+
+        pci1: pcie@ffe0a000 {
+                compatible = "fsl,mpc8548-pcie";
+                device_type = "pci";
+                #interrupt-cells = <1>;
+                #size-cells = <2>;
+                #address-cells = <3>;
+                reg = <0 0xffe0a000 0 0x1000>;
+                bus-range = <0 255>;
+                ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x20000000
+                          0x1000000 0x0 0x00000000 0 0xffc20000 0x0 0x10000>;
+                clock-frequency = <33333333>;
+                interrupt-parent = <&mpic>;
+                interrupts = <26 2>;
+                pcie@0 {
+                        reg = <0x0 0x0 0x0 0x0 0x0>;
+                        #size-cells = <2>;
+                        #address-cells = <3>;
+                        device_type = "pci";
+                        ranges = <0x2000000 0x0 0xc0000000
+                                  0x2000000 0x0 0xc0000000
+                                  0x0 0x20000000
+
+                                  0x1000000 0x0 0x0
+                                  0x1000000 0x0 0x0
+                                  0x0 0x100000>;
+                };
+        };
+};
diff --git a/arch/powerpc/boot/dts/p4080ds.dts b/arch/powerpc/boot/dts/p4080ds.dts
new file mode 100644
index 000000000000..6b29eab05362
--- /dev/null
+++ b/arch/powerpc/boot/dts/p4080ds.dts
@@ -0,0 +1,554 @@
+/*
+ * P4080DS Device Tree Source
+ *
+ * Copyright 2009 Freescale Semiconductor Inc.
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+/dts-v1/;
+
+/ {
+        model = "fsl,P4080DS";
+        compatible = "fsl,P4080DS";
+        #address-cells = <2>;
+        #size-cells = <2>;
+
+        aliases {
+                ccsr = &soc;
+
+                serial0 = &serial0;
+                serial1 = &serial1;
+                serial2 = &serial2;
+                serial3 = &serial3;
+                pci0 = &pci0;
+                pci1 = &pci1;
+                pci2 = &pci2;
+                usb0 = &usb0;
+                usb1 = &usb1;
+                dma0 = &dma0;
+                dma1 = &dma1;
+                sdhc = &sdhc;
+
+                rio0 = &rapidio0;
+        };
+
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                cpu0: PowerPC,4080@0 {
+                        device_type = "cpu";
+                        reg = <0>;
+                        next-level-cache = <&L2_0>;
+                        L2_0: l2-cache {
+                        };
+                };
+                cpu1: PowerPC,4080@1 {
+                        device_type = "cpu";
+                        reg = <1>;
+                        next-level-cache = <&L2_1>;
+                        L2_1: l2-cache {
+                        };
+                };
+                cpu2: PowerPC,4080@2 {
+                        device_type = "cpu";
+                        reg = <2>;
+                        next-level-cache = <&L2_2>;
+                        L2_2: l2-cache {
+                        };
+                };
+                cpu3: PowerPC,4080@3 {
+                        device_type = "cpu";
+                        reg = <3>;
+                        next-level-cache = <&L2_3>;
+                        L2_3: l2-cache {
+                        };
+                };
+                cpu4: PowerPC,4080@4 {
+                        device_type = "cpu";
+                        reg = <4>;
+                        next-level-cache = <&L2_4>;
+                        L2_4: l2-cache {
+                        };
+                };
+                cpu5: PowerPC,4080@5 {
+                        device_type = "cpu";
+                        reg = <5>;
+                        next-level-cache = <&L2_5>;
+                        L2_5: l2-cache {
+                        };
+                };
+                cpu6: PowerPC,4080@6 {
+                        device_type = "cpu";
+                        reg = <6>;
+                        next-level-cache = <&L2_6>;
+                        L2_6: l2-cache {
+                        };
+                };
+                cpu7: PowerPC,4080@7 {
+                        device_type = "cpu";
+                        reg = <7>;
+                        next-level-cache = <&L2_7>;
+                        L2_7: l2-cache {
+                        };
+                };
+        };
+
+        memory {
+                device_type = "memory";
+        };
+
+        soc: soc@ffe000000 {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                device_type = "soc";
+                compatible = "simple-bus";
+                ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
+                reg = <0xf 0xfe000000 0 0x00001000>;
+
+                corenet-law@0 {
+                        compatible = "fsl,corenet-law";
+                        reg = <0x0 0x1000>;
+                        fsl,num-laws = <32>;
+                };
+
+                memory-controller@8000 {
+                        compatible = "fsl,p4080-memory-controller";
+                        reg = <0x8000 0x1000>;
+                        interrupt-parent = <&mpic>;
+                        interrupts = <0x12 2>;
+                };
+
+                memory-controller@9000 {
+                        compatible = "fsl,p4080-memory-controller";
+                        reg = <0x9000 0x1000>;
+                        interrupt-parent = <&mpic>;
+                        interrupts = <0x12 2>;
+                };
+
+                corenet-cf@18000 {
+                        compatible = "fsl,corenet-cf";
+                        reg = <0x18000 0x1000>;
+                        fsl,ccf-num-csdids = <32>;
+                        fsl,ccf-num-snoopids = <32>;
+                };
+
+                iommu@20000 {
+                        compatible = "fsl,p4080-pamu";
+                        reg = <0x20000 0x10000>;
+                        interrupts = <24 2>;
+                        interrupt-parent = <&mpic>;
+                };
+
+                mpic: pic@40000 {
+                        interrupt-controller;
+                        #address-cells = <0>;
+                        #interrupt-cells = <2>;
+                        reg = <0x40000 0x40000>;
+                        compatible = "chrp,open-pic";
+                        device_type = "open-pic";
+                };
+
+                dma0: dma@100300 {
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        compatible = "fsl,p4080-dma", "fsl,eloplus-dma";
+                        reg = <0x100300 0x4>;
+                        ranges = <0x0 0x100100 0x200>;
+                        cell-index = <0>;
+                        dma-channel@0 {
+                                compatible = "fsl,p4080-dma-channel",
+                                                "fsl,eloplus-dma-channel";
+                                reg = <0x0 0x80>;
+                                cell-index = <0>;
+                                interrupt-parent = <&mpic>;
+                                interrupts = <28 2>;
+                        };
+                        dma-channel@80 {
+                                compatible = "fsl,p4080-dma-channel",
+                                                "fsl,eloplus-dma-channel";
+                                reg = <0x80 0x80>;
+                                cell-index = <1>;
+                                interrupt-parent = <&mpic>;
+                                interrupts = <29 2>;
+                        };
+                        dma-channel@100 {
+                                compatible = "fsl,p4080-dma-channel",
+                                                "fsl,eloplus-dma-channel";
+                                reg = <0x100 0x80>;
+                                cell-index = <2>;
+                                interrupt-parent = <&mpic>;
+                                interrupts = <30 2>;
+                        };
+                        dma-channel@180 {
+                                compatible = "fsl,p4080-dma-channel",
+                                                "fsl,eloplus-dma-channel";
+                                reg = <0x180 0x80>;
+                                cell-index = <3>;
+                                interrupt-parent = <&mpic>;
+                                interrupts = <31 2>;
+                        };
+                };
+
+                dma1: dma@101300 {
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        compatible = "fsl,p4080-dma", "fsl,eloplus-dma";
+                        reg = <0x101300 0x4>;
+                        ranges = <0x0 0x101100 0x200>;
+                        cell-index = <1>;
+                        dma-channel@0 {
+                                compatible = "fsl,p4080-dma-channel",
+                                                "fsl,eloplus-dma-channel";
+                                reg = <0x0 0x80>;
+                                cell-index = <0>;
+                                interrupt-parent = <&mpic>;
+                                interrupts = <32 2>;
+                        };
+                        dma-channel@80 {
+                                compatible = "fsl,p4080-dma-channel",
+                                                "fsl,eloplus-dma-channel";
+                                reg = <0x80 0x80>;
+                                cell-index = <1>;
+                                interrupt-parent = <&mpic>;
+                                interrupts = <33 2>;
+                        };
+                        dma-channel@100 {
+                                compatible = "fsl,p4080-dma-channel",
+                                                "fsl,eloplus-dma-channel";
+                                reg = <0x100 0x80>;
+                                cell-index = <2>;
+                                interrupt-parent = <&mpic>;
+                                interrupts = <34 2>;
+                        };
+                        dma-channel@180 {
+                                compatible = "fsl,p4080-dma-channel",
+                                                "fsl,eloplus-dma-channel";
+                                reg = <0x180 0x80>;
+                                cell-index = <3>;
+                                interrupt-parent = <&mpic>;
+                                interrupts = <35 2>;
+                        };
+                };
+
+                spi@110000 {
+                        cell-index = <0>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "fsl,espi";
+                        reg = <0x110000 0x1000>;
+                        interrupts = <53 0x2>;
+                        interrupt-parent = <&mpic>;
+                        espi,num-ss-bits = <4>;
+                        mode = "cpu";
+
+                        fsl_m25p80@0 {
+                                #address-cells = <1>;
+                                #size-cells = <1>;
+                                compatible = "fsl,espi-flash";
+                                reg = <0>;
+                                linux,modalias = "fsl_m25p80";
+                                spi-max-frequency = <40000000>; /* input clock */
+                                partition@u-boot {
+                                        label = "u-boot";
+                                        reg = <0x00000000 0x00100000>;
+                                        read-only;
+                                };
+                                partition@kernel {
+                                        label = "kernel";
+                                        reg = <0x00100000 0x00500000>;
+                                        read-only;
+                                };
+                                partition@dtb {
+                                        label = "dtb";
+                                        reg = <0x00600000 0x00100000>;
+                                        read-only;
+                                };
+                                partition@fs {
+                                        label = "file system";
+                                        reg = <0x00700000 0x00900000>;
+                                };
+                        };
+                };
+
+                sdhc: sdhc@114000 {
+                        compatible = "fsl,p4080-esdhc", "fsl,esdhc";
+                        reg = <0x114000 0x1000>;
+                        interrupts = <48 2>;
+                        interrupt-parent = <&mpic>;
+                };
+
+                i2c@118000 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        cell-index = <0>;
+                        compatible = "fsl-i2c";
+                        reg = <0x118000 0x100>;
+                        interrupts = <38 2>;
+                        interrupt-parent = <&mpic>;
+                        dfsrr;
+                };
+
+                i2c@118100 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        cell-index = <1>;
+                        compatible = "fsl-i2c";
+                        reg = <0x118100 0x100>;
+                        interrupts = <38 2>;
+                        interrupt-parent = <&mpic>;
+                        dfsrr;
+                        eeprom@51 {
+                                compatible = "at24,24c256";
+                                reg = <0x51>;
+                        };
+                        eeprom@52 {
+                                compatible = "at24,24c256";
+                                reg = <0x52>;
+                        };
+                        rtc@68 {
+                                compatible = "dallas,ds3232";
+                                reg = <0x68>;
+                                interrupts = <0 0x1>;
+                                interrupt-parent = <&mpic>;
+                        };
+                };
+
+                i2c@119000 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        cell-index = <2>;
+                        compatible = "fsl-i2c";
+                        reg = <0x119000 0x100>;
+                        interrupts = <39 2>;
+                        interrupt-parent = <&mpic>;
+                        dfsrr;
+                };
+
+                i2c@119100 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        cell-index = <3>;
+                        compatible = "fsl-i2c";
+                        reg = <0x119100 0x100>;
+                        interrupts = <39 2>;
+                        interrupt-parent = <&mpic>;
+                        dfsrr;
+                };
+
+                serial0: serial@11c500 {
+                        cell-index = <0>;
+                        device_type = "serial";
+                        compatible = "ns16550";
+                        reg = <0x11c500 0x100>;
+                        clock-frequency = <0>;
+                        interrupts = <36 2>;
+                        interrupt-parent = <&mpic>;
+                };
+
+                serial1: serial@11c600 {
+                        cell-index = <1>;
+                        device_type = "serial";
+                        compatible = "ns16550";
+                        reg = <0x11c600 0x100>;
+                        clock-frequency = <0>;
+                        interrupts = <36 2>;
+                        interrupt-parent = <&mpic>;
+                };
+
+                serial2: serial@11d500 {
+                        cell-index = <2>;
+                        device_type = "serial";
+                        compatible = "ns16550";
+                        reg = <0x11d500 0x100>;
+                        clock-frequency = <0>;
+                        interrupts = <37 2>;
+                        interrupt-parent = <&mpic>;
+                };
+
+                serial3: serial@11d600 {
+                        cell-index = <3>;
+                        device_type = "serial";
+                        compatible = "ns16550";
+                        reg = <0x11d600 0x100>;
+                        clock-frequency = <0>;
+                        interrupts = <37 2>;
+                        interrupt-parent = <&mpic>;
+                };
+
+                gpio0: gpio@130000 {
+                        compatible = "fsl,p4080-gpio";
+                        reg = <0x130000 0x1000>;
+                        interrupts = <55 2>;
+                        interrupt-parent = <&mpic>;
+                        #gpio-cells = <2>;
+                        gpio-controller;
+                };
+
+                usb0: usb@210000 {
+                        compatible = "fsl,p4080-usb2-mph",
+                                        "fsl,mpc85xx-usb2-mph", "fsl-usb2-mph";
+                        reg = <0x210000 0x1000>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        interrupt-parent = <&mpic>;
+                        interrupts = <44 0x2>;
+                        phy_type = "ulpi";
+                };
+
+                usb1: usb@211000 {
+                        compatible = "fsl,p4080-usb2-dr",
+                                        "fsl,mpc85xx-usb2-dr", "fsl-usb2-dr";
+                        reg = <0x211000 0x1000>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        interrupt-parent = <&mpic>;
+                        interrupts = <45 0x2>;
+                        dr_mode = "host";
+                        phy_type = "ulpi";
+                };
+        };
+
+        rapidio0: rapidio@ffe0c0000 {
+                #address-cells = <2>;
+                #size-cells = <2>;
+                compatible = "fsl,rapidio-delta";
+                reg = <0xf 0xfe0c0000 0 0x20000>;
+                ranges = <0 0 0xf 0xf5000000 0 0x01000000>;
+                interrupt-parent = <&mpic>;
+                /* err_irq bell_outb_irq bell_inb_irq
+                        msg1_tx_irq msg1_rx_irq msg2_tx_irq msg2_rx_irq */
+                interrupts = <16 2 56 2 57 2 60 2 61 2 62 2 63 2>;
+        };
+
+        localbus@ffe124000 {
+                compatible = "fsl,p4080-elbc", "fsl,elbc", "simple-bus";
+                reg = <0xf 0xfe124000 0 0x1000>;
+                interrupts = <25 2>;
+                #address-cells = <2>;
+                #size-cells = <1>;
+
+                ranges = <0 0 0xf 0xe8000000 0x08000000>;
+
+                flash@0,0 {
+                        compatible = "cfi-flash";
+                        reg = <0 0 0x08000000>;
+                        bank-width = <2>;
+                        device-width = <2>;
+                };
+        };
+
+        pci0: pcie@ffe200000 {
+                compatible = "fsl,p4080-pcie";
+                device_type = "pci";
+                #interrupt-cells = <1>;
+                #size-cells = <2>;
+                #address-cells = <3>;
+                reg = <0xf 0xfe200000 0 0x1000>;
+                bus-range = <0x0 0xff>;
+                ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000
+                          0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>;
+                clock-frequency = <0x1fca055>;
+                interrupt-parent = <&mpic>;
+                interrupts = <16 2>;
+
+                interrupt-map-mask = <0xf800 0 0 7>;
+                interrupt-map = <
+                        /* IDSEL 0x0 */
+                        0000 0 0 1 &mpic 40 1
+                        0000 0 0 2 &mpic 1 1
+                        0000 0 0 3 &mpic 2 1
+                        0000 0 0 4 &mpic 3 1
+                        >;
+                pcie@0 {
+                        reg = <0 0 0 0 0>;
+                        #size-cells = <2>;
+                        #address-cells = <3>;
+                        device_type = "pci";
+                        ranges = <0x02000000 0 0xe0000000
+                                  0x02000000 0 0xe0000000
+                                  0 0x20000000
+
+                                  0x01000000 0 0x00000000
+                                  0x01000000 0 0x00000000
+                                  0 0x00010000>;
+                };
+        };
+
+        pci1: pcie@ffe201000 {
+                compatible = "fsl,p4080-pcie";
+                device_type = "pci";
+                #interrupt-cells = <1>;
+                #size-cells = <2>;
+                #address-cells = <3>;
+                reg = <0xf 0xfe201000 0 0x1000>;
+                bus-range = <0 0xff>;
+                ranges = <0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000
+                          0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>;
+                clock-frequency = <0x1fca055>;
+                interrupt-parent = <&mpic>;
+                interrupts = <16 2>;
+                interrupt-map-mask = <0xf800 0 0 7>;
+                interrupt-map = <
+                        /* IDSEL 0x0 */
+                        0000 0 0 1 &mpic 41 1
+                        0000 0 0 2 &mpic 5 1
+                        0000 0 0 3 &mpic 6 1
+                        0000 0 0 4 &mpic 7 1
+                        >;
+                pcie@0 {
+                        reg = <0 0 0 0 0>;
+                        #size-cells = <2>;
+                        #address-cells = <3>;
+                        device_type = "pci";
+                        ranges = <0x02000000 0 0xe0000000
+                                  0x02000000 0 0xe0000000
+                                  0 0x20000000
+
+                                  0x01000000 0 0x00000000
+                                  0x01000000 0 0x00000000
+                                  0 0x00010000>;
+                };
+        };
+
+        pci2: pcie@ffe202000 {
+                compatible = "fsl,p4080-pcie";
+                device_type = "pci";
+                #interrupt-cells = <1>;
+                #size-cells = <2>;
+                #address-cells = <3>;
+                reg = <0xf 0xfe202000 0 0x1000>;
+                bus-range = <0x0 0xff>;
+                ranges = <0x02000000 0 0xe0000000 0xc 0x40000000 0 0x20000000
+                          0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>;
+                clock-frequency = <0x1fca055>;
+                interrupt-parent = <&mpic>;
+                interrupts = <16 2>;
+                interrupt-map-mask = <0xf800 0 0 7>;
+                interrupt-map = <
+                        /* IDSEL 0x0 */
+                        0000 0 0 1 &mpic 42 1
+                        0000 0 0 2 &mpic 9 1
+                        0000 0 0 3 &mpic 10 1
+                        0000 0 0 4 &mpic 11 1
+                        >;
+                pcie@0 {
+                        reg = <0 0 0 0 0>;
+                        #size-cells = <2>;
+                        #address-cells = <3>;
+                        device_type = "pci";
+                        ranges = <0x02000000 0 0xe0000000
+                                  0x02000000 0 0xe0000000
+                                  0 0x20000000
+
+                                  0x01000000 0 0x00000000
+                                  0x01000000 0 0x00000000
+                                  0 0x00010000>;
+                };
+        };
+
+};
diff --git a/arch/powerpc/boot/dts/redwood.dts b/arch/powerpc/boot/dts/redwood.dts
index ad402c488741..d2af32e2bf7a 100644
--- a/arch/powerpc/boot/dts/redwood.dts
+++ b/arch/powerpc/boot/dts/redwood.dts
@@ -226,6 +226,7 @@
                                 max-frame-size = <9000>;
                                 rx-fifo-size = <4096>;
                                 tx-fifo-size = <2048>;
+                                rx-fifo-size-gige = <16384>;
                                 phy-mode = "rgmii";
                                 phy-map = <0x00000000>;
                                 rgmii-device = <&RGMII0>;
diff --git a/arch/powerpc/boot/dts/wii.dts b/arch/powerpc/boot/dts/wii.dts
new file mode 100644
index 000000000000..77528c9a8dbd
--- /dev/null
+++ b/arch/powerpc/boot/dts/wii.dts
@@ -0,0 +1,218 @@
+/*
+ * arch/powerpc/boot/dts/wii.dts
+ *
+ * Nintendo Wii platform device tree source
+ * Copyright (C) 2008-2009 The GameCube Linux Team
+ * Copyright (C) 2008,2009 Albert Herranz
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ */
+
+/dts-v1/;
+
+/*
+ * This is commented-out for now.
+ * Until a later patch is merged, the kernel can use only the first
+ * contiguous RAM range and will BUG() if the memreserve is outside
+ * that range.
+ */
+/*/memreserve/ 0x10000000 0x0004000;*/  /* DSP RAM */
+
+/ {
+        model = "nintendo,wii";
+        compatible = "nintendo,wii";
+        #address-cells = <1>;
+        #size-cells = <1>;
+
+        chosen {
+                bootargs = "root=/dev/mmcblk0p2 rootwait udbg-immortal";
+        };
+
+        memory {
+                device_type = "memory";
+                reg = <0x00000000 0x01800000    /* MEM1 24MB 1T-SRAM */
+                       0x10000000 0x04000000>;  /* MEM2 64MB GDDR3 */
+        };
+
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                PowerPC,broadway@0 {
+                        device_type = "cpu";
+                        reg = <0>;
+                        clock-frequency = <729000000>; /* 729MHz */
+                        bus-frequency = <243000000>; /* 243MHz core-to-bus 3x */
+                        timebase-frequency = <60750000>; /* 243MHz / 4 */
+                        i-cache-line-size = <32>;
+                        d-cache-line-size = <32>;
+                        i-cache-size = <32768>;
+                        d-cache-size = <32768>;
+                };
+        };
+
+        /* devices contained in the hollywood chipset */
+        hollywood {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "nintendo,hollywood";
+                ranges = <0x0c000000 0x0c000000 0x01000000
+                          0x0d000000 0x0d000000 0x00800000
+                          0x0d800000 0x0d800000 0x00800000>;
+                interrupt-parent = <&PIC0>;
+
+                video@0c002000 {
+                        compatible = "nintendo,hollywood-vi",
+                                        "nintendo,flipper-vi";
+                        reg = <0x0c002000 0x100>;
+                        interrupts = <8>;
+                };
+
+                processor-interface@0c003000 {
+                        compatible = "nintendo,hollywood-pi",
+                                        "nintendo,flipper-pi";
+                        reg = <0x0c003000 0x100>;
+
+                        PIC0: pic0 {
+                                #interrupt-cells = <1>;
+                                compatible = "nintendo,flipper-pic";
+                                interrupt-controller;
+                        };
+                };
+
+                dsp@0c005000 {
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        compatible = "nintendo,hollywood-dsp",
+                                        "nintendo,flipper-dsp";
+                        reg = <0x0c005000 0x200>;
+                        interrupts = <6>;
+                };
+
+                gamepad-controller@0d006400 {
+                        compatible = "nintendo,hollywood-si",
+                                        "nintendo,flipper-si";
+                        reg = <0x0d006400 0x100>;
+                        interrupts = <3>;
+                };
+
+                audio@0c006c00 {
+                        compatible = "nintendo,hollywood-ai",
+                                        "nintendo,flipper-ai";
+                        reg = <0x0d006c00 0x20>;
+                        interrupts = <6>;
+                };
+
+                /* External Interface bus */
+                exi@0d006800 {
+                        compatible = "nintendo,hollywood-exi",
+                                        "nintendo,flipper-exi";
+                        reg = <0x0d006800 0x40>;
+                        virtual-reg = <0x0d006800>;
+                        interrupts = <4>;
+                };
+
+                usb@0d040000 {
+                        compatible = "nintendo,hollywood-usb-ehci",
+                                        "usb-ehci";
+                        reg = <0x0d040000 0x100>;
+                        interrupts = <4>;
+                        interrupt-parent = <&PIC1>;
+                };
+
+                usb@0d050000 {
+                        compatible = "nintendo,hollywood-usb-ohci",
+                                        "usb-ohci";
+                        reg = <0x0d050000 0x100>;
+                        interrupts = <5>;
+                        interrupt-parent = <&PIC1>;
+                };
+
+                usb@0d060000 {
+                        compatible = "nintendo,hollywood-usb-ohci",
+                                        "usb-ohci";
+                        reg = <0x0d060000 0x100>;
+                        interrupts = <6>;
+                        interrupt-parent = <&PIC1>;
+                };
+
+                sd@0d070000 {
+                        compatible = "nintendo,hollywood-sdhci",
+                                        "sdhci";
+                        reg = <0x0d070000 0x200>;
+                        interrupts = <7>;
+                        interrupt-parent = <&PIC1>;
+                };
+
+                sdio@0d080000 {
+                        compatible = "nintendo,hollywood-sdhci",
+                                        "sdhci";
+                        reg = <0x0d080000 0x200>;
+                        interrupts = <8>;
+                        interrupt-parent = <&PIC1>;
+                };
+
+                ipc@0d000000 {
+                        compatible = "nintendo,hollywood-ipc";
+                        reg = <0x0d000000 0x10>;
+                        interrupts = <30>;
+                        interrupt-parent = <&PIC1>;
+                };
+
+                PIC1: pic1@0d800030 {
+                        #interrupt-cells = <1>;
+                        compatible = "nintendo,hollywood-pic";
+                        reg = <0x0d800030 0x10>;
+                        interrupt-controller;
+                        interrupts = <14>;
+                };
+
+                GPIO: gpio@0d8000c0 {
+                        #gpio-cells = <2>;
+                        compatible = "nintendo,hollywood-gpio";
+                        reg = <0x0d8000c0 0x40>;
+                        gpio-controller;
+
+                        /*
+                         * This is commented out while a standard binding
+                         * for i2c over gpio is defined.
+                         */
+                        /*
+                        i2c-video {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                compatible = "i2c-gpio";
+
+                                gpios = <&GPIO 15 0
+                                         &GPIO 14 0>;
+                                clock-frequency = <250000>;
+                                no-clock-stretching;
+                                scl-is-open-drain;
+                                sda-is-open-drain;
+                                sda-enforce-dir;
+
+                                AVE: audio-video-encoder@70 {
+                                        compatible = "nintendo,wii-audio-video-encoder";
+                                        reg = <0x70>;
+                                };
+                        };
+                        */
+                };
+
+                control@0d800100 {
+                        compatible = "nintendo,hollywood-control";
+                        reg = <0x0d800100 0x300>;
+                };
+
+                disk@0d806000 {
+                        compatible = "nintendo,hollywood-di";
+                        reg = <0x0d806000 0x40>;
+                        interrupts = <2>;
+                };
+        };
+};
+
diff --git a/arch/powerpc/boot/dts/yosemite.dts b/arch/powerpc/boot/dts/yosemite.dts
index 1fa3cb4c4ebb..64923245f0e5 100644
--- a/arch/powerpc/boot/dts/yosemite.dts
+++ b/arch/powerpc/boot/dts/yosemite.dts
@@ -282,20 +282,10 @@
                         /* Inbound 2GB range starting at 0 */
                         dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
 
-                        /* Bamboo has all 4 IRQ pins tied together per slot */
                         interrupt-map-mask = <0xf800 0x0 0x0 0x0>;
                         interrupt-map = <
-                                /* IDSEL 1 */
-                                0x800 0x0 0x0 0x0 &UIC0 0x1c 0x8
-
-                                /* IDSEL 2 */
-                                0x1000 0x0 0x0 0x0 &UIC0 0x1b 0x8
-
-                                /* IDSEL 3 */
-                                0x1800 0x0 0x0 0x0 &UIC0 0x1a 0x8
-
-                                /* IDSEL 4 */
-                                0x2000 0x0 0x0 0x0 &UIC0 0x19 0x8
+                                /* IDSEL 12 */
+                                0x6000 0x0 0x0 0x0 &UIC0 0x19 0x8
                         >;
                 };
         };
diff --git a/arch/powerpc/boot/gamecube-head.S b/arch/powerpc/boot/gamecube-head.S
new file mode 100644
index 000000000000..65a9b2a3bf33
--- /dev/null
+++ b/arch/powerpc/boot/gamecube-head.S
@@ -0,0 +1,111 @@
+/*
+ * arch/powerpc/boot/gamecube-head.S
+ *
+ * Nintendo GameCube bootwrapper entry.
+ * Copyright (C) 2004-2009 The GameCube Linux Team
+ * Copyright (C) 2008,2009 Albert Herranz
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ */
+
+#include "ppc_asm.h"
+
+/*
+ * The entry code does no assumptions regarding:
+ * - if the data and instruction caches are enabled or not
+ * - if the MMU is enabled or not
+ *
+ * We enable the caches if not already enabled, enable the MMU with an
+ * identity mapping scheme and jump to the start code.
+ */
+
+        .text
+
+        .globl _zimage_start
+_zimage_start:
+
+        /* turn the MMU off */
+        mfmsr   9
+        rlwinm  9, 9, 0, ~((1<<4)|(1<<5)) /* MSR_DR|MSR_IR */
+        bcl     20, 31, 1f
+1:
+        mflr    8
+        clrlwi  8, 8, 3         /* convert to a real address */
+        addi    8, 8, _mmu_off - 1b
+        mtsrr0  8
+        mtsrr1  9
+        rfi
+_mmu_off:
+        /* MMU disabled */
+
+        /* setup BATs */
+        isync
+        li      8, 0
+        mtspr   0x210, 8        /* IBAT0U */
+        mtspr   0x212, 8        /* IBAT1U */
+        mtspr   0x214, 8        /* IBAT2U */
+        mtspr   0x216, 8        /* IBAT3U */
+        mtspr   0x218, 8        /* DBAT0U */
+        mtspr   0x21a, 8        /* DBAT1U */
+        mtspr   0x21c, 8        /* DBAT2U */
+        mtspr   0x21e, 8        /* DBAT3U */
+
+        li      8, 0x01ff       /* first 16MiB */
+        li      9, 0x0002       /* rw */
+        mtspr   0x211, 9        /* IBAT0L */
+        mtspr   0x210, 8        /* IBAT0U */
+        mtspr   0x219, 9        /* DBAT0L */
+        mtspr   0x218, 8        /* DBAT0U */
+
+        lis     8, 0x0c00       /* I/O mem */
+        ori     8, 8, 0x3ff     /* 32MiB */
+        lis     9, 0x0c00
+        ori     9, 9, 0x002a    /* uncached, guarded, rw */
+        mtspr   0x21b, 9        /* DBAT1L */
+        mtspr   0x21a, 8        /* DBAT1U */
+
+        lis     8, 0x0100       /* next 8MiB */
+        ori     8, 8, 0x00ff    /* 8MiB */
+        lis     9, 0x0100
+        ori     9, 9, 0x0002    /* rw */
+        mtspr   0x215, 9        /* IBAT2L */
+        mtspr   0x214, 8        /* IBAT2U */
+        mtspr   0x21d, 9        /* DBAT2L */
+        mtspr   0x21c, 8        /* DBAT2U */
+
+        /* enable and invalidate the caches if not already enabled */
+        mfspr   8, 0x3f0        /* HID0 */
+        andi.   0, 8, (1<<15)           /* HID0_ICE */
+        bne     1f
+        ori     8, 8, (1<<15)|(1<<11)   /* HID0_ICE|HID0_ICFI*/
+1:
+        andi.   0, 8, (1<<14)           /* HID0_DCE */
+        bne     1f
+        ori     8, 8, (1<<14)|(1<<10)   /* HID0_DCE|HID0_DCFI*/
+1:
+        mtspr   0x3f0, 8        /* HID0 */
+        isync
+
+        /* initialize arguments */
+        li      3, 0
+        li      4, 0
+        li      5, 0
+
+        /* turn the MMU on */
+        bcl     20, 31, 1f
+1:
+        mflr    8
+        addi    8, 8, _mmu_on - 1b
+        mfmsr   9
+        ori     9, 9, (1<<4)|(1<<5) /* MSR_DR|MSR_IR */
+        mtsrr0  8
+        mtsrr1  9
+        sync
+        rfi
+_mmu_on:
+        b _zimage_start_lib
+
diff --git a/arch/powerpc/boot/gamecube.c b/arch/powerpc/boot/gamecube.c
new file mode 100644
index 000000000000..28ae7057be5e
--- /dev/null
+++ b/arch/powerpc/boot/gamecube.c
@@ -0,0 +1,35 @@
+/*
+ * arch/powerpc/boot/gamecube.c
+ *
+ * Nintendo GameCube bootwrapper support
+ * Copyright (C) 2004-2009 The GameCube Linux Team
+ * Copyright (C) 2008,2009 Albert Herranz
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ */
+
+#include <stddef.h>
+#include "stdio.h"
+#include "types.h"
+#include "io.h"
+#include "ops.h"
+
+#include "ugecon.h"
+
+BSS_STACK(8192);
+
+void platform_init(unsigned long r3, unsigned long r4, unsigned long r5)
+{
+        u32 heapsize = 16*1024*1024 - (u32)_end;
+
+        simple_alloc_init(_end, heapsize, 32, 64);
+        fdt_init(_dtb_start);
+
+        if (ug_probe())
+                console_ops.write = ug_console_write;
+}
+
diff --git a/arch/powerpc/boot/ugecon.c b/arch/powerpc/boot/ugecon.c
new file mode 100644
index 000000000000..50609ea6ddf8
--- /dev/null
+++ b/arch/powerpc/boot/ugecon.c
@@ -0,0 +1,147 @@
+/*
+ * arch/powerpc/boot/ugecon.c
+ *
+ * USB Gecko bootwrapper console.
+ * Copyright (C) 2008-2009 The GameCube Linux Team
+ * Copyright (C) 2008,2009 Albert Herranz
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ */
+
+#include <stddef.h>
+#include "stdio.h"
+#include "types.h"
+#include "io.h"
+#include "ops.h"
+
+
+#define EXI_CLK_32MHZ           5
+
+#define EXI_CSR                 0x00
+#define   EXI_CSR_CLKMASK       (0x7<<4)
+#define     EXI_CSR_CLK_32MHZ   (EXI_CLK_32MHZ<<4)
+#define   EXI_CSR_CSMASK        (0x7<<7)
+#define     EXI_CSR_CS_0        (0x1<<7)  /* Chip Select 001 */
+
+#define EXI_CR                  0x0c
+#define   EXI_CR_TSTART         (1<<0)
+#define   EXI_CR_WRITE          (1<<2)
+#define   EXI_CR_READ_WRITE     (2<<2)
+#define   EXI_CR_TLEN(len)      (((len)-1)<<4)
+
+#define EXI_DATA                0x10
+
+
+/* virtual address base for input/output, retrieved from device tree */
+static void *ug_io_base;
+
+
+static u32 ug_io_transaction(u32 in)
+{
+        u32 *csr_reg = ug_io_base + EXI_CSR;
+        u32 *data_reg = ug_io_base + EXI_DATA;
+        u32 *cr_reg = ug_io_base + EXI_CR;
+        u32 csr, data, cr;
+
+        /* select */
+        csr = EXI_CSR_CLK_32MHZ | EXI_CSR_CS_0;
+        out_be32(csr_reg, csr);
+
+        /* read/write */
+        data = in;
+        out_be32(data_reg, data);
+        cr = EXI_CR_TLEN(2) | EXI_CR_READ_WRITE | EXI_CR_TSTART;
+        out_be32(cr_reg, cr);
+
+        while (in_be32(cr_reg) & EXI_CR_TSTART)
+                barrier();
+
+        /* deselect */
+        out_be32(csr_reg, 0);
+
+        data = in_be32(data_reg);
+        return data;
+}
+
+static int ug_is_txfifo_ready(void)
+{
+        return ug_io_transaction(0xc0000000) & 0x04000000;
+}
+
+static void ug_raw_putc(char ch)
+{
+        ug_io_transaction(0xb0000000 | (ch << 20));
+}
+
+static void ug_putc(char ch)
+{
+        int count = 16;
+
+        if (!ug_io_base)
+                return;
+
+        while (!ug_is_txfifo_ready() && count--)
+                barrier();
+        if (count)
+                ug_raw_putc(ch);
+}
+
+void ug_console_write(const char *buf, int len)
+{
+        char *b = (char *)buf;
+
+        while (len--) {
+                if (*b == '\n')
+                        ug_putc('\r');
+                ug_putc(*b++);
+        }
+}
+
+static int ug_is_adapter_present(void)
+{
+        if (!ug_io_base)
+                return 0;
+        return ug_io_transaction(0x90000000) == 0x04700000;
+}
+
+static void *ug_grab_exi_io_base(void)
+{
+        u32 v;
+        void *devp;
+
+        devp = find_node_by_compatible(NULL, "nintendo,flipper-exi");
+        if (devp == NULL)
+                goto err_out;
+        if (getprop(devp, "virtual-reg", &v, sizeof(v)) != sizeof(v))
+                goto err_out;
+
+        return (void *)v;
+
+err_out:
+        return NULL;
+}
+
+void *ug_probe(void)
+{
+        void *exi_io_base;
+        int i;
+
+        exi_io_base = ug_grab_exi_io_base();
+        if (!exi_io_base)
+                return NULL;
+
+        /* look for a usbgecko on memcard slots A and B */
+        for (i = 0; i < 2; i++) {
+                ug_io_base = exi_io_base + 0x14 * i;
+                if (ug_is_adapter_present())
+                        break;
+        }
+        if (i == 2)
+                ug_io_base = NULL;
+        return ug_io_base;
+}
+
diff --git a/arch/powerpc/boot/ugecon.h b/arch/powerpc/boot/ugecon.h
new file mode 100644
index 000000000000..43737539169b
--- /dev/null
+++ b/arch/powerpc/boot/ugecon.h
@@ -0,0 +1,24 @@
+/*
+ * arch/powerpc/boot/ugecon.h
+ *
+ * USB Gecko early bootwrapper console.
+ * Copyright (C) 2008-2009 The GameCube Linux Team
+ * Copyright (C) 2008,2009 Albert Herranz
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ */
+
+#ifndef __UGECON_H
+#define __UGECON_H
+
+extern void *ug_probe(void);
+
+extern void ug_putc(char ch);
+extern void ug_console_write(const char *buf, int len);
+
+#endif /* __UGECON_H */
+
diff --git a/arch/powerpc/boot/wii-head.S b/arch/powerpc/boot/wii-head.S
new file mode 100644
index 000000000000..edd79b836fcf
--- /dev/null
+++ b/arch/powerpc/boot/wii-head.S
@@ -0,0 +1,142 @@
+/*
+ * arch/powerpc/boot/wii-head.S
+ *
+ * Nintendo Wii bootwrapper entry.
+ * Copyright (C) 2008-2009 The GameCube Linux Team
+ * Copyright (C) 2008,2009 Albert Herranz
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ */
+
+#include "ppc_asm.h"
+
+/*
+ * The entry code does no assumptions regarding:
+ * - if the data and instruction caches are enabled or not
+ * - if the MMU is enabled or not
+ * - if the high BATs are enabled or not
+ *
+ * We enable the high BATs, enable the caches if not already enabled,
+ * enable the MMU with an identity mapping scheme and jump to the start code.
+ */
+
+        .text
+
+        .globl _zimage_start
+_zimage_start:
+
+        /* turn the MMU off */
+        mfmsr   9
+        rlwinm  9, 9, 0, ~((1<<4)|(1<<5)) /* MSR_DR|MSR_IR */
+        bcl     20, 31, 1f
+1:
+        mflr    8
+        clrlwi  8, 8, 3         /* convert to a real address */
+        addi    8, 8, _mmu_off - 1b
+        mtsrr0  8
+        mtsrr1  9
+        rfi
+_mmu_off:
+        /* MMU disabled */
+
+        /* setup BATs */
+        isync
+        li      8, 0
+        mtspr   0x210, 8        /* IBAT0U */
+        mtspr   0x212, 8        /* IBAT1U */
+        mtspr   0x214, 8        /* IBAT2U */
+        mtspr   0x216, 8        /* IBAT3U */
+        mtspr   0x218, 8        /* DBAT0U */
+        mtspr   0x21a, 8        /* DBAT1U */
+        mtspr   0x21c, 8        /* DBAT2U */
+        mtspr   0x21e, 8        /* DBAT3U */
+
+        mtspr   0x230, 8        /* IBAT4U */
+        mtspr   0x232, 8        /* IBAT5U */
+        mtspr   0x234, 8        /* IBAT6U */
+        mtspr   0x236, 8        /* IBAT7U */
+        mtspr   0x238, 8        /* DBAT4U */
+        mtspr   0x23a, 8        /* DBAT5U */
+        mtspr   0x23c, 8        /* DBAT6U */
+        mtspr   0x23e, 8        /* DBAT7U */
+
+        li      8, 0x01ff       /* first 16MiB */
+        li      9, 0x0002       /* rw */
+        mtspr   0x211, 9        /* IBAT0L */
+        mtspr   0x210, 8        /* IBAT0U */
+        mtspr   0x219, 9        /* DBAT0L */
+        mtspr   0x218, 8        /* DBAT0U */
+
+        lis     8, 0x0c00       /* I/O mem */
+        ori     8, 8, 0x3ff     /* 32MiB */
+        lis     9, 0x0c00
+        ori     9, 9, 0x002a    /* uncached, guarded, rw */
+        mtspr   0x21b, 9        /* DBAT1L */
+        mtspr   0x21a, 8        /* DBAT1U */
+
+        lis     8, 0x0100       /* next 8MiB */
+        ori     8, 8, 0x00ff    /* 8MiB */
+        lis     9, 0x0100
+        ori     9, 9, 0x0002    /* rw */
+        mtspr   0x215, 9        /* IBAT2L */
+        mtspr   0x214, 8        /* IBAT2U */
+        mtspr   0x21d, 9        /* DBAT2L */
+        mtspr   0x21c, 8        /* DBAT2U */
+
+        lis     8, 0x1000       /* MEM2 */
+        ori     8, 8, 0x07ff    /* 64MiB */
+        lis     9, 0x1000
+        ori     9, 9, 0x0002    /* rw */
+        mtspr   0x216, 8        /* IBAT3U */
+        mtspr   0x217, 9        /* IBAT3L */
+        mtspr   0x21e, 8        /* DBAT3U */
+        mtspr   0x21f, 9        /* DBAT3L */
+
+        /* enable the high BATs */
+        mfspr   8, 0x3f3        /* HID4 */
+        oris    8, 8, 0x0200
+        mtspr   0x3f3, 8        /* HID4 */
+
+        /* enable and invalidate the caches if not already enabled */
+        mfspr   8, 0x3f0        /* HID0 */
+        andi.   0, 8, (1<<15)           /* HID0_ICE */
+        bne     1f
+        ori     8, 8, (1<<15)|(1<<11)   /* HID0_ICE|HID0_ICFI*/
+1:
+        andi.   0, 8, (1<<14)           /* HID0_DCE */
+        bne     1f
+        ori     8, 8, (1<<14)|(1<<10)   /* HID0_DCE|HID0_DCFI*/
+1:
+        mtspr   0x3f0, 8        /* HID0 */
+        isync
+
+        /* initialize arguments */
+        li      3, 0
+        li      4, 0
+        li      5, 0
+
+        /* turn the MMU on */
+        bcl     20, 31, 1f
+1:
+        mflr    8
+        addi    8, 8, _mmu_on - 1b
+        mfmsr   9
+        ori     9, 9, (1<<4)|(1<<5) /* MSR_DR|MSR_IR */
+        mtsrr0  8
+        mtsrr1  9
+        sync
+        rfi
+_mmu_on:
+        /* turn on the front blue led (aka: yay! we got here!) */
+        lis     8, 0x0d00
+        ori     8, 8, 0x00c0
+        lwz     9, 0(8)
+        ori     9, 9, 0x20
+        stw     9, 0(8)
+
+        b _zimage_start_lib
+
diff --git a/arch/powerpc/boot/wii.c b/arch/powerpc/boot/wii.c
new file mode 100644
index 000000000000..2ebaec0344dd
--- /dev/null
+++ b/arch/powerpc/boot/wii.c
@@ -0,0 +1,158 @@
+/*
+ * arch/powerpc/boot/wii.c
+ *
+ * Nintendo Wii bootwrapper support
+ * Copyright (C) 2008-2009 The GameCube Linux Team
+ * Copyright (C) 2008,2009 Albert Herranz
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ */
+
+#include <stddef.h>
+#include "stdio.h"
+#include "types.h"
+#include "io.h"
+#include "ops.h"
+
+#include "ugecon.h"
+
+BSS_STACK(8192);
+
+#define HW_REG(x)               ((void *)(x))
+
+#define EXI_CTRL                HW_REG(0x0d800070)
+#define EXI_CTRL_ENABLE         (1<<0)
+
+#define MEM2_TOP                (0x10000000 + 64*1024*1024)
+#define FIRMWARE_DEFAULT_SIZE   (12*1024*1024)
+
+
+struct mipc_infohdr {
+        char magic[3];
+        u8 version;
+        u32 mem2_boundary;
+        u32 ipc_in;
+        size_t ipc_in_size;
+        u32 ipc_out;
+        size_t ipc_out_size;
+};
+
+static int mipc_check_address(u32 pa)
+{
+        /* only MEM2 addresses */
+        if (pa < 0x10000000 || pa > 0x14000000)
+                return -EINVAL;
+        return 0;
+}
+
+static struct mipc_infohdr *mipc_get_infohdr(void)
+{
+        struct mipc_infohdr **hdrp, *hdr;
+
+        /* 'mini' header pointer is the last word of MEM2 memory */
+        hdrp = (struct mipc_infohdr **)0x13fffffc;
+        if (mipc_check_address((u32)hdrp)) {
+                printf("mini: invalid hdrp %08X\n", (u32)hdrp);
+                hdr = NULL;
+                goto out;
+        }
+
+        hdr = *hdrp;
+        if (mipc_check_address((u32)hdr)) {
+                printf("mini: invalid hdr %08X\n", (u32)hdr);
+                hdr = NULL;
+                goto out;
+        }
+        if (memcmp(hdr->magic, "IPC", 3)) {
+                printf("mini: invalid magic\n");
+                hdr = NULL;
+                goto out;
+        }
+
+out:
+        return hdr;
+}
+
+static int mipc_get_mem2_boundary(u32 *mem2_boundary)
+{
+        struct mipc_infohdr *hdr;
+        int error;
+
+        hdr = mipc_get_infohdr();
+        if (!hdr) {
+                error = -1;
+                goto out;
+        }
+
+        if (mipc_check_address(hdr->mem2_boundary)) {
+                printf("mini: invalid mem2_boundary %08X\n",
+                       hdr->mem2_boundary);
+                error = -EINVAL;
+                goto out;
+        }
+        *mem2_boundary = hdr->mem2_boundary;
+        error = 0;
+out:
+        return error;
+
+}
+
+static void platform_fixups(void)
+{
+        void *mem;
+        u32 reg[4];
+        u32 mem2_boundary;
+        int len;
+        int error;
+
+        mem = finddevice("/memory");
+        if (!mem)
+                fatal("Can't find memory node\n");
+
+        /* two ranges of (address, size) words */
+        len = getprop(mem, "reg", reg, sizeof(reg));
+        if (len != sizeof(reg)) {
+                /* nothing to do */
+                goto out;
+        }
+
+        /* retrieve MEM2 boundary from 'mini' */
+        error = mipc_get_mem2_boundary(&mem2_boundary);
+        if (error) {
+                /* if that fails use a sane value */
+                mem2_boundary = MEM2_TOP - FIRMWARE_DEFAULT_SIZE;
+        }
+
+        if (mem2_boundary > reg[2] && mem2_boundary < reg[2] + reg[3]) {
+                reg[3] = mem2_boundary - reg[2];
+                printf("top of MEM2 @ %08X\n", reg[2] + reg[3]);
+                setprop(mem, "reg", reg, sizeof(reg));
+        }
+
+out:
+        return;
+}
+
+void platform_init(unsigned long r3, unsigned long r4, unsigned long r5)
+{
+        u32 heapsize = 24*1024*1024 - (u32)_end;
+
+        simple_alloc_init(_end, heapsize, 32, 64);
+        fdt_init(_dtb_start);
+
+        /*
+         * 'mini' boots the Broadway processor with EXI disabled.
+         * We need it enabled before probing for the USB Gecko.
+         */
+        out_be32(EXI_CTRL, in_be32(EXI_CTRL) | EXI_CTRL_ENABLE);
+
+        if (ug_probe())
+                console_ops.write = ug_console_write;
+
+        platform_ops.fixups = platform_fixups;
+}
+
diff --git a/arch/powerpc/boot/wrapper b/arch/powerpc/boot/wrapper
index ac9e9a58b2b0..390512ae7f86 100755
--- a/arch/powerpc/boot/wrapper
+++ b/arch/powerpc/boot/wrapper
@@ -230,6 +230,10 @@ xpedite52*)
     link_address='0x1400000'
     platformo=$object/cuboot-85xx.o
     ;;
+gamecube|wii)
+    link_address='0x600000'
+    platformo="$object/$platform-head.o $object/$platform.o"
+    ;;
 esac
 
 vmz="$tmpdir/`basename \"$kernel\"`.$ext"
diff --git a/arch/powerpc/configs/86xx/gef_ppc9a_defconfig b/arch/powerpc/configs/86xx/gef_ppc9a_defconfig
index 28980738776c..6cd2cd65c2cd 100644
--- a/arch/powerpc/configs/86xx/gef_ppc9a_defconfig
+++ b/arch/powerpc/configs/86xx/gef_ppc9a_defconfig
@@ -218,7 +218,7 @@ CONFIG_MPIC=y
 # CONFIG_MPIC_WEIRD is not set
 # CONFIG_PPC_I8259 is not set
 # CONFIG_PPC_RTAS is not set
-# CONFIG_MMIO_NVRAM is not set
+CONFIG_MMIO_NVRAM=y
 # CONFIG_PPC_MPC106 is not set
 # CONFIG_PPC_970_NAP is not set
 # CONFIG_PPC_INDIRECT_IO is not set
diff --git a/arch/powerpc/configs/86xx/gef_sbc310_defconfig b/arch/powerpc/configs/86xx/gef_sbc310_defconfig
index e199d1cacbaf..a6a3768f7304 100644
--- a/arch/powerpc/configs/86xx/gef_sbc310_defconfig
+++ b/arch/powerpc/configs/86xx/gef_sbc310_defconfig
@@ -218,7 +218,7 @@ CONFIG_MPIC=y
 # CONFIG_MPIC_WEIRD is not set
 # CONFIG_PPC_I8259 is not set
 # CONFIG_PPC_RTAS is not set
-# CONFIG_MMIO_NVRAM is not set
+CONFIG_MMIO_NVRAM=y
 # CONFIG_PPC_MPC106 is not set
 # CONFIG_PPC_970_NAP is not set
 # CONFIG_PPC_INDIRECT_IO is not set
diff --git a/arch/powerpc/configs/86xx/gef_sbc610_defconfig b/arch/powerpc/configs/86xx/gef_sbc610_defconfig
index 3b0fbfb28efd..1975d41e0763 100644
--- a/arch/powerpc/configs/86xx/gef_sbc610_defconfig
+++ b/arch/powerpc/configs/86xx/gef_sbc610_defconfig
@@ -219,7 +219,7 @@ CONFIG_MPIC=y
 # CONFIG_MPIC_WEIRD is not set
 # CONFIG_PPC_I8259 is not set
 # CONFIG_PPC_RTAS is not set
-# CONFIG_MMIO_NVRAM is not set
+CONFIG_MMIO_NVRAM=y
 # CONFIG_PPC_MPC106 is not set
 # CONFIG_PPC_970_NAP is not set
 # CONFIG_PPC_INDIRECT_IO is not set
@@ -1124,7 +1124,7 @@ CONFIG_UNIX98_PTYS=y
 # CONFIG_IPMI_HANDLER is not set
 CONFIG_HW_RANDOM=y
 # CONFIG_HW_RANDOM_TIMERIOMEM is not set
-# CONFIG_NVRAM is not set
+CONFIG_NVRAM=y
 # CONFIG_R3964 is not set
 # CONFIG_APPLICOM is not set
 # CONFIG_RAW_DRIVER is not set
diff --git a/arch/powerpc/configs/gamecube_defconfig b/arch/powerpc/configs/gamecube_defconfig
new file mode 100644
index 000000000000..942e1193e9e4
--- /dev/null
+++ b/arch/powerpc/configs/gamecube_defconfig
@@ -0,0 +1,1061 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.32-rc8
+# Sun Nov 22 21:07:30 2009
+#
+# CONFIG_PPC64 is not set
+
+#
+# Processor support
+#
+CONFIG_PPC_BOOK3S_32=y
+# CONFIG_PPC_85xx is not set
+# CONFIG_PPC_8xx is not set
+# CONFIG_40x is not set
+# CONFIG_44x is not set
+# CONFIG_E200 is not set
+CONFIG_PPC_BOOK3S=y
+CONFIG_6xx=y
+CONFIG_PPC_FPU=y
+# CONFIG_ALTIVEC is not set
+CONFIG_PPC_STD_MMU=y
+CONFIG_PPC_STD_MMU_32=y
+# CONFIG_PPC_MM_SLICES is not set
+CONFIG_PPC_HAVE_PMU_SUPPORT=y
+CONFIG_PPC_PERF_CTRS=y
+# CONFIG_SMP is not set
+CONFIG_NOT_COHERENT_CACHE=y
+CONFIG_PPC32=y
+CONFIG_WORD_SIZE=32
+# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set
+CONFIG_MMU=y
+CONFIG_GENERIC_CMOS_UPDATE=y
+CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_TIME_VSYSCALL=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
+# CONFIG_HAVE_SETUP_PER_CPU_AREA is not set
+# CONFIG_NEED_PER_CPU_EMBED_FIRST_CHUNK is not set
+CONFIG_IRQ_PER_CPU=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_HAVE_LATENCYTOP_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_RWSEM_XCHGADD_ALGORITHM=y
+CONFIG_ARCH_HAS_ILOG2_U32=y
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_FIND_NEXT_BIT=y
+# CONFIG_ARCH_NO_VIRT_TO_BUS is not set
+CONFIG_PPC=y
+CONFIG_EARLY_PRINTK=y
+CONFIG_GENERIC_NVRAM=y
+CONFIG_SCHED_OMIT_FRAME_POINTER=y
+CONFIG_ARCH_MAY_HAVE_PC_FDC=y
+CONFIG_PPC_OF=y
+CONFIG_OF=y
+# CONFIG_PPC_UDBG_16550 is not set
+# CONFIG_GENERIC_TBSYNC is not set
+CONFIG_AUDIT_ARCH=y
+CONFIG_GENERIC_BUG=y
+CONFIG_DTC=y
+# CONFIG_DEFAULT_UIMAGE is not set
+# CONFIG_PPC_DCR_NATIVE is not set
+# CONFIG_PPC_DCR_MMIO is not set
+CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+CONFIG_CONSTRUCTORS=y
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_LOCK_KERNEL=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION="-gcn"
+CONFIG_LOCALVERSION_AUTO=y
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+# CONFIG_POSIX_MQUEUE is not set
+# CONFIG_BSD_PROCESS_ACCT is not set
+# CONFIG_TASKSTATS is not set
+# CONFIG_AUDIT is not set
+
+#
+# RCU Subsystem
+#
+CONFIG_TREE_RCU=y
+# CONFIG_TREE_PREEMPT_RCU is not set
+# CONFIG_RCU_TRACE is not set
+CONFIG_RCU_FANOUT=32
+# CONFIG_RCU_FANOUT_EXACT is not set
+# CONFIG_TREE_RCU_TRACE is not set
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_GROUP_SCHED=y
+CONFIG_FAIR_GROUP_SCHED=y
+# CONFIG_RT_GROUP_SCHED is not set
+CONFIG_USER_SCHED=y
+# CONFIG_CGROUP_SCHED is not set
+# CONFIG_CGROUPS is not set
+CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SYSFS_DEPRECATED_V2=y
+# CONFIG_RELAY is not set
+# CONFIG_NAMESPACES is not set
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_RD_GZIP=y
+# CONFIG_RD_BZIP2 is not set
+# CONFIG_RD_LZMA is not set
+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+CONFIG_SYSCTL=y
+CONFIG_ANON_INODES=y
+CONFIG_EMBEDDED=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_KALLSYMS=y
+CONFIG_KALLSYMS_ALL=y
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+# CONFIG_ELF_CORE is not set
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_AIO=y
+CONFIG_HAVE_PERF_EVENTS=y
+
+#
+# Kernel Performance Events And Counters
+#
+CONFIG_PERF_EVENTS=y
+CONFIG_EVENT_PROFILE=y
+CONFIG_PERF_COUNTERS=y
+# CONFIG_DEBUG_PERF_USE_VMALLOC is not set
+# CONFIG_VM_EVENT_COUNTERS is not set
+CONFIG_COMPAT_BRK=y
+CONFIG_SLAB=y
+# CONFIG_SLUB is not set
+# CONFIG_SLOB is not set
+# CONFIG_PROFILING is not set
+CONFIG_TRACEPOINTS=y
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_KPROBES is not set
+CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
+CONFIG_HAVE_IOREMAP_PROT=y
+CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_KRETPROBES=y
+CONFIG_HAVE_ARCH_TRACEHOOK=y
+CONFIG_HAVE_DMA_ATTRS=y
+CONFIG_HAVE_DMA_API_DEBUG=y
+
+#
+# GCOV-based kernel profiling
+#
+# CONFIG_GCOV_KERNEL is not set
+CONFIG_SLOW_WORK=y
+# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+# CONFIG_MODULE_FORCE_LOAD is not set
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODULE_FORCE_UNLOAD is not set
+# CONFIG_MODVERSIONS is not set
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+CONFIG_BLOCK=y
+CONFIG_LBDAF=y
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_BLK_DEV_INTEGRITY is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+CONFIG_DEFAULT_AS=y
+# CONFIG_DEFAULT_DEADLINE is not set
+# CONFIG_DEFAULT_CFQ is not set
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="anticipatory"
+# CONFIG_FREEZER is not set
+
+#
+# Platform support
+#
+# CONFIG_PPC_CHRP is not set
+# CONFIG_MPC5121_ADS is not set
+# CONFIG_MPC5121_GENERIC is not set
+# CONFIG_PPC_MPC52xx is not set
+# CONFIG_PPC_PMAC is not set
+# CONFIG_PPC_CELL is not set
+# CONFIG_PPC_CELL_NATIVE is not set
+# CONFIG_PPC_82xx is not set
+# CONFIG_PQ2ADS is not set
+# CONFIG_PPC_83xx is not set
+# CONFIG_PPC_86xx is not set
+CONFIG_EMBEDDED6xx=y
+# CONFIG_LINKSTATION is not set
+# CONFIG_STORCENTER is not set
+# CONFIG_MPC7448HPC2 is not set
+# CONFIG_PPC_HOLLY is not set
+# CONFIG_PPC_PRPMC2800 is not set
+# CONFIG_PPC_C2K is not set
+CONFIG_GAMECUBE_COMMON=y
+CONFIG_USBGECKO_UDBG=y
+CONFIG_FLIPPER_PIC=y
+CONFIG_GAMECUBE=y
+# CONFIG_WII is not set
+# CONFIG_AMIGAONE is not set
+# CONFIG_PPC_OF_BOOT_TRAMPOLINE is not set
+# CONFIG_IPIC is not set
+# CONFIG_MPIC is not set
+# CONFIG_MPIC_WEIRD is not set
+# CONFIG_PPC_I8259 is not set
+# CONFIG_PPC_RTAS is not set
+# CONFIG_MMIO_NVRAM is not set
+# CONFIG_PPC_MPC106 is not set
+# CONFIG_PPC_970_NAP is not set
+# CONFIG_PPC_INDIRECT_IO is not set
+# CONFIG_GENERIC_IOMAP is not set
+# CONFIG_CPU_FREQ is not set
+# CONFIG_TAU is not set
+# CONFIG_FSL_ULI1575 is not set
+# CONFIG_SIMPLE_GPIO is not set
+
+#
+# Kernel options
+#
+# CONFIG_HIGHMEM is not set
+# CONFIG_NO_HZ is not set
+# CONFIG_HIGH_RES_TIMERS is not set
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+# CONFIG_HZ_100 is not set
+CONFIG_HZ_250=y
+# CONFIG_HZ_300 is not set
+# CONFIG_HZ_1000 is not set
+CONFIG_HZ=250
+# CONFIG_SCHED_HRTICK is not set
+# CONFIG_PREEMPT_NONE is not set
+# CONFIG_PREEMPT_VOLUNTARY is not set
+CONFIG_PREEMPT=y
+CONFIG_BINFMT_ELF=y
+# CONFIG_HAVE_AOUT is not set
+CONFIG_BINFMT_MISC=m
+# CONFIG_IOMMU_HELPER is not set
+# CONFIG_SWIOTLB is not set
+CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y
+CONFIG_ARCH_HAS_WALK_MEMORY=y
+CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y
+CONFIG_KEXEC=y
+# CONFIG_CRASH_DUMP is not set
+CONFIG_MAX_ACTIVE_REGIONS=32
+CONFIG_ARCH_FLATMEM_ENABLE=y
+CONFIG_ARCH_POPULATES_NODE_MAP=y
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_SPLIT_PTLOCK_CPUS=4
+# CONFIG_MIGRATION is not set
+# CONFIG_PHYS_ADDR_T_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=1
+CONFIG_BOUNCE=y
+CONFIG_VIRT_TO_BUS=y
+CONFIG_HAVE_MLOCK=y
+CONFIG_HAVE_MLOCKED_PAGE_BIT=y
+# CONFIG_KSM is not set
+CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
+CONFIG_PPC_4K_PAGES=y
+# CONFIG_PPC_16K_PAGES is not set
+# CONFIG_PPC_64K_PAGES is not set
+# CONFIG_PPC_256K_PAGES is not set
+CONFIG_FORCE_MAX_ZONEORDER=11
+CONFIG_PROC_DEVICETREE=y
+# CONFIG_CMDLINE_BOOL is not set
+CONFIG_EXTRA_TARGETS=""
+# CONFIG_PM is not set
+# CONFIG_SECCOMP is not set
+CONFIG_ISA_DMA_API=y
+
+#
+# Bus options
+#
+CONFIG_ZONE_DMA=y
+CONFIG_GENERIC_ISA_DMA=y
+# CONFIG_PCI is not set
+# CONFIG_PCI_DOMAINS is not set
+# CONFIG_PCI_SYSCALL is not set
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+# CONFIG_PCCARD is not set
+# CONFIG_HAS_RAPIDIO is not set
+
+#
+# Advanced setup
+#
+CONFIG_ADVANCED_OPTIONS=y
+# CONFIG_LOWMEM_SIZE_BOOL is not set
+CONFIG_LOWMEM_SIZE=0x30000000
+# CONFIG_PAGE_OFFSET_BOOL is not set
+CONFIG_PAGE_OFFSET=0xc0000000
+# CONFIG_KERNEL_START_BOOL is not set
+CONFIG_KERNEL_START=0xc0000000
+CONFIG_PHYSICAL_START=0x00000000
+# CONFIG_TASK_SIZE_BOOL is not set
+CONFIG_TASK_SIZE=0xc0000000
+# CONFIG_CONSISTENT_SIZE_BOOL is not set
+CONFIG_CONSISTENT_SIZE=0x00200000
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+# CONFIG_PACKET_MMAP is not set
+CONFIG_UNIX=y
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+# CONFIG_IP_MULTICAST is not set
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+# CONFIG_IP_PNP_BOOTP is not set
+CONFIG_IP_PNP_RARP=y
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
+# CONFIG_INET_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_LRO is not set
+# CONFIG_INET_DIAG is not set
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+# CONFIG_IPV6 is not set
+# CONFIG_NETWORK_SECMARK is not set
+# CONFIG_NETFILTER is not set
+# CONFIG_IP_DCCP is not set
+# CONFIG_IP_SCTP is not set
+# CONFIG_RDS is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_NET_DSA is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_PHONET is not set
+# CONFIG_IEEE802154 is not set
+# CONFIG_NET_SCHED is not set
+# CONFIG_DCB is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_NET_DROP_MONITOR is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+# CONFIG_AF_RXRPC is not set
+# CONFIG_WIRELESS is not set
+# CONFIG_WIMAX is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+# CONFIG_DEVTMPFS is not set
+# CONFIG_STANDALONE is not set
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+# CONFIG_FW_LOADER is not set
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
+# CONFIG_SYS_HYPERVISOR is not set
+# CONFIG_CONNECTOR is not set
+# CONFIG_MTD is not set
+CONFIG_OF_DEVICE=y
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_FD is not set
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=y
+# CONFIG_BLK_DEV_CRYPTOLOOP is not set
+CONFIG_BLK_DEV_NBD=m
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=2
+CONFIG_BLK_DEV_RAM_SIZE=4096
+# CONFIG_BLK_DEV_XIP is not set
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+# CONFIG_BLK_DEV_HD is not set
+CONFIG_MISC_DEVICES=y
+# CONFIG_ENCLOSURE_SERVICES is not set
+# CONFIG_C2PORT is not set
+
+#
+# EEPROM support
+#
+# CONFIG_EEPROM_93CX6 is not set
+CONFIG_HAVE_IDE=y
+# CONFIG_IDE is not set
+
+#
+# SCSI device support
+#
+# CONFIG_RAID_ATTRS is not set
+# CONFIG_SCSI is not set
+# CONFIG_SCSI_DMA is not set
+# CONFIG_SCSI_NETLINK is not set
+# CONFIG_ATA is not set
+# CONFIG_MD is not set
+# CONFIG_MACINTOSH_DRIVERS is not set
+CONFIG_NETDEVICES=y
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_VETH is not set
+# CONFIG_PHYLIB is not set
+CONFIG_NET_ETHERNET=y
+# CONFIG_MII is not set
+# CONFIG_ETHOC is not set
+# CONFIG_DNET is not set
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
+# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
+# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
+# CONFIG_B44 is not set
+# CONFIG_KS8842 is not set
+# CONFIG_KS8851_MLL is not set
+# CONFIG_XILINX_EMACLITE is not set
+# CONFIG_NETDEV_1000 is not set
+# CONFIG_NETDEV_10000 is not set
+# CONFIG_WLAN is not set
+
+#
+# Enable WiMAX (Networking options) to see the WiMAX drivers
+#
+# CONFIG_WAN is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_ISDN is not set
+# CONFIG_PHONE is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+CONFIG_INPUT_FF_MEMLESS=m
+# CONFIG_INPUT_POLLDEV is not set
+
+#
+# Userland interfaces
+#
+# CONFIG_INPUT_MOUSEDEV is not set
+CONFIG_INPUT_JOYDEV=y
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input Device Drivers
+#
+CONFIG_INPUT_KEYBOARD=y
+# CONFIG_KEYBOARD_ATKBD is not set
+# CONFIG_KEYBOARD_LKKBD is not set
+# CONFIG_KEYBOARD_NEWTON is not set
+# CONFIG_KEYBOARD_OPENCORES is not set
+# CONFIG_KEYBOARD_STOWAWAY is not set
+# CONFIG_KEYBOARD_SUNKBD is not set
+# CONFIG_KEYBOARD_XTKBD is not set
+# CONFIG_INPUT_MOUSE is not set
+CONFIG_INPUT_JOYSTICK=y
+# CONFIG_JOYSTICK_ANALOG is not set
+# CONFIG_JOYSTICK_A3D is not set
+# CONFIG_JOYSTICK_ADI is not set
+# CONFIG_JOYSTICK_COBRA is not set
+# CONFIG_JOYSTICK_GF2K is not set
+# CONFIG_JOYSTICK_GRIP is not set
+# CONFIG_JOYSTICK_GRIP_MP is not set
+# CONFIG_JOYSTICK_GUILLEMOT is not set
+# CONFIG_JOYSTICK_INTERACT is not set
+# CONFIG_JOYSTICK_SIDEWINDER is not set
+# CONFIG_JOYSTICK_TMDC is not set
+# CONFIG_JOYSTICK_IFORCE is not set
+# CONFIG_JOYSTICK_WARRIOR is not set
+# CONFIG_JOYSTICK_MAGELLAN is not set
+# CONFIG_JOYSTICK_SPACEORB is not set
+# CONFIG_JOYSTICK_SPACEBALL is not set
+# CONFIG_JOYSTICK_STINGER is not set
+# CONFIG_JOYSTICK_TWIDJOY is not set
+# CONFIG_JOYSTICK_ZHENHUA is not set
+# CONFIG_JOYSTICK_JOYDUMP is not set
+# CONFIG_INPUT_TABLET is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+# CONFIG_INPUT_MISC is not set
+
+#
+# Hardware I/O ports
+#
+CONFIG_SERIO=y
+# CONFIG_SERIO_I8042 is not set
+# CONFIG_SERIO_SERPORT is not set
+# CONFIG_SERIO_LIBPS2 is not set
+# CONFIG_SERIO_RAW is not set
+# CONFIG_SERIO_XILINX_XPS_PS2 is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+# CONFIG_VT_HW_CONSOLE_BINDING is not set
+# CONFIG_DEVKMEM is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+# CONFIG_SERIAL_8250 is not set
+
+#
+# Non-8250 serial port support
+#
+# CONFIG_SERIAL_UARTLITE is not set
+CONFIG_UNIX98_PTYS=y
+# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
+CONFIG_LEGACY_PTYS=y
+CONFIG_LEGACY_PTY_COUNT=64
+# CONFIG_HVC_UDBG is not set
+# CONFIG_IPMI_HANDLER is not set
+# CONFIG_HW_RANDOM is not set
+# CONFIG_NVRAM is not set
+# CONFIG_R3964 is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+# CONFIG_I2C is not set
+# CONFIG_SPI is not set
+
+#
+# PPS support
+#
+# CONFIG_PPS is not set
+CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
+# CONFIG_GPIOLIB is not set
+# CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
+# CONFIG_HWMON is not set
+# CONFIG_THERMAL is not set
+# CONFIG_WATCHDOG is not set
+CONFIG_SSB_POSSIBLE=y
+
+#
+# Sonics Silicon Backplane
+#
+# CONFIG_SSB is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_CORE is not set
+# CONFIG_MFD_SM501 is not set
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_MFD_TMIO is not set
+# CONFIG_REGULATOR is not set
+# CONFIG_MEDIA_SUPPORT is not set
+
+#
+# Graphics support
+#
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+CONFIG_FB=y
+# CONFIG_FIRMWARE_EDID is not set
+# CONFIG_FB_DDC is not set
+# CONFIG_FB_BOOT_VESA_SUPPORT is not set
+# CONFIG_FB_CFB_FILLRECT is not set
+# CONFIG_FB_CFB_COPYAREA is not set
+# CONFIG_FB_CFB_IMAGEBLIT is not set
+# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
+# CONFIG_FB_SYS_FILLRECT is not set
+# CONFIG_FB_SYS_COPYAREA is not set
+# CONFIG_FB_SYS_IMAGEBLIT is not set
+# CONFIG_FB_FOREIGN_ENDIAN is not set
+# CONFIG_FB_SYS_FOPS is not set
+# CONFIG_FB_SVGALIB is not set
+# CONFIG_FB_MACMODES is not set
+# CONFIG_FB_BACKLIGHT is not set
+# CONFIG_FB_MODE_HELPERS is not set
+# CONFIG_FB_TILEBLITTING is not set
+
+#
+# Frame buffer hardware drivers
+#
+# CONFIG_FB_OF is not set
+# CONFIG_FB_VGA16 is not set
+# CONFIG_FB_S1D13XXX is not set
+# CONFIG_FB_IBM_GXT4500 is not set
+# CONFIG_FB_VIRTUAL is not set
+# CONFIG_FB_METRONOME is not set
+# CONFIG_FB_MB862XX is not set
+# CONFIG_FB_BROADSHEET is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+
+#
+# Console display driver support
+#
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_DUMMY_CONSOLE=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
+# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
+# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
+# CONFIG_FONTS is not set
+CONFIG_FONT_8x8=y
+CONFIG_FONT_8x16=y
+CONFIG_LOGO=y
+# CONFIG_LOGO_LINUX_MONO is not set
+# CONFIG_LOGO_LINUX_VGA16 is not set
+# CONFIG_LOGO_LINUX_CLUT224 is not set
+CONFIG_SOUND=y
+CONFIG_SOUND_OSS_CORE=y
+CONFIG_SOUND_OSS_CORE_PRECLAIM=y
+CONFIG_SND=y
+CONFIG_SND_TIMER=y
+CONFIG_SND_PCM=y
+CONFIG_SND_SEQUENCER=y
+# CONFIG_SND_SEQ_DUMMY is not set
+CONFIG_SND_OSSEMUL=y
+CONFIG_SND_MIXER_OSS=y
+CONFIG_SND_PCM_OSS=y
+CONFIG_SND_PCM_OSS_PLUGINS=y
+CONFIG_SND_SEQUENCER_OSS=y
+# CONFIG_SND_DYNAMIC_MINORS is not set
+CONFIG_SND_SUPPORT_OLD_API=y
+# CONFIG_SND_VERBOSE_PROCFS is not set
+# CONFIG_SND_VERBOSE_PRINTK is not set
+# CONFIG_SND_DEBUG is not set
+# CONFIG_SND_RAWMIDI_SEQ is not set
+# CONFIG_SND_OPL3_LIB_SEQ is not set
+# CONFIG_SND_OPL4_LIB_SEQ is not set
+# CONFIG_SND_SBAWE_SEQ is not set
+# CONFIG_SND_EMU10K1_SEQ is not set
+CONFIG_SND_DRIVERS=y
+# CONFIG_SND_DUMMY is not set
+# CONFIG_SND_VIRMIDI is not set
+# CONFIG_SND_MTPAV is not set
+# CONFIG_SND_SERIAL_U16550 is not set
+# CONFIG_SND_MPU401 is not set
+CONFIG_SND_PPC=y
+# CONFIG_SND_SOC is not set
+# CONFIG_SOUND_PRIME is not set
+CONFIG_HID_SUPPORT=y
+CONFIG_HID=y
+# CONFIG_HIDRAW is not set
+# CONFIG_HID_PID is not set
+
+#
+# Special HID drivers
+#
+# CONFIG_USB_SUPPORT is not set
+# CONFIG_MMC is not set
+# CONFIG_MEMSTICK is not set
+# CONFIG_NEW_LEDS is not set
+# CONFIG_ACCESSIBILITY is not set
+# CONFIG_EDAC is not set
+CONFIG_RTC_LIB=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_HCTOSYS=y
+CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
+# CONFIG_RTC_DEBUG is not set
+
+#
+# RTC interfaces
+#
+CONFIG_RTC_INTF_SYSFS=y
+CONFIG_RTC_INTF_PROC=y
+CONFIG_RTC_INTF_DEV=y
+# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
+# CONFIG_RTC_DRV_TEST is not set
+
+#
+# SPI RTC drivers
+#
+
+#
+# Platform RTC drivers
+#
+# CONFIG_RTC_DRV_CMOS is not set
+# CONFIG_RTC_DRV_DS1286 is not set
+# CONFIG_RTC_DRV_DS1511 is not set
+# CONFIG_RTC_DRV_DS1553 is not set
+# CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_STK17TA8 is not set
+# CONFIG_RTC_DRV_M48T86 is not set
+# CONFIG_RTC_DRV_M48T35 is not set
+# CONFIG_RTC_DRV_M48T59 is not set
+# CONFIG_RTC_DRV_BQ4802 is not set
+# CONFIG_RTC_DRV_V3020 is not set
+
+#
+# on-CPU RTC drivers
+#
+CONFIG_RTC_DRV_GENERIC=y
+# CONFIG_DMADEVICES is not set
+# CONFIG_AUXDISPLAY is not set
+# CONFIG_UIO is not set
+
+#
+# TI VLYNQ
+#
+# CONFIG_STAGING is not set
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+# CONFIG_EXT2_FS_XATTR is not set
+# CONFIG_EXT2_FS_XIP is not set
+CONFIG_EXT3_FS=y
+# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
+# CONFIG_EXT3_FS_XATTR is not set
+# CONFIG_EXT4_FS is not set
+CONFIG_JBD=y
+# CONFIG_JBD_DEBUG is not set
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+# CONFIG_FS_POSIX_ACL is not set
+# CONFIG_XFS_FS is not set
+# CONFIG_GFS2_FS is not set
+# CONFIG_OCFS2_FS is not set
+# CONFIG_BTRFS_FS is not set
+# CONFIG_NILFS2_FS is not set
+CONFIG_FILE_LOCKING=y
+CONFIG_FSNOTIFY=y
+CONFIG_DNOTIFY=y
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_FUSE_FS is not set
+
+#
+# Caches
+#
+# CONFIG_FSCACHE is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+CONFIG_ISO9660_FS=y
+CONFIG_JOLIET=y
+# CONFIG_ZISOFS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_KCORE=y
+CONFIG_PROC_SYSCTL=y
+# CONFIG_PROC_PAGE_MONITOR is not set
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_HUGETLB_PAGE is not set
+# CONFIG_CONFIGFS_FS is not set
+CONFIG_MISC_FILESYSTEMS=y
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+# CONFIG_CRAMFS is not set
+# CONFIG_SQUASHFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_OMFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+# CONFIG_NFS_V3_ACL is not set
+# CONFIG_NFS_V4 is not set
+CONFIG_ROOT_NFS=y
+# CONFIG_NFSD is not set
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=y
+# CONFIG_RPCSEC_GSS_KRB5 is not set
+# CONFIG_RPCSEC_GSS_SPKM3 is not set
+# CONFIG_SMB_FS is not set
+CONFIG_CIFS=y
+# CONFIG_CIFS_STATS is not set
+# CONFIG_CIFS_WEAK_PW_HASH is not set
+# CONFIG_CIFS_XATTR is not set
+# CONFIG_CIFS_DEBUG2 is not set
+# CONFIG_CIFS_EXPERIMENTAL is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="iso8859-1"
+CONFIG_NLS_CODEPAGE_437=y
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+# CONFIG_NLS_ASCII is not set
+CONFIG_NLS_ISO8859_1=y
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+# CONFIG_NLS_UTF8 is not set
+# CONFIG_DLM is not set
+CONFIG_BINARY_PRINTF=y
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+CONFIG_GENERIC_FIND_LAST_BIT=y
+CONFIG_CRC_CCITT=y
+# CONFIG_CRC16 is not set
+# CONFIG_CRC_T10DIF is not set
+# CONFIG_CRC_ITU_T is not set
+CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
+# CONFIG_LIBCRC32C is not set
+CONFIG_ZLIB_INFLATE=y
+CONFIG_DECOMPRESS_GZIP=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
+CONFIG_HAVE_LMB=y
+CONFIG_NLATTR=y
+CONFIG_GENERIC_ATOMIC64=y
+
+#
+# Kernel hacking
+#
+CONFIG_PRINTK_TIME=y
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_FRAME_WARN=1024
+# CONFIG_MAGIC_SYSRQ is not set
+# CONFIG_STRIP_ASM_SYMS is not set
+# CONFIG_UNUSED_SYMBOLS is not set
+CONFIG_DEBUG_FS=y
+# CONFIG_HEADERS_CHECK is not set
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_SHIRQ is not set
+CONFIG_DETECT_SOFTLOCKUP=y
+# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
+CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
+# CONFIG_DETECT_HUNG_TASK is not set
+CONFIG_SCHED_DEBUG=y
+CONFIG_SCHEDSTATS=y
+# CONFIG_TIMER_STATS is not set
+# CONFIG_DEBUG_OBJECTS is not set
+# CONFIG_DEBUG_SLAB is not set
+# CONFIG_DEBUG_KMEMLEAK is not set
+CONFIG_DEBUG_PREEMPT=y
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_RT_MUTEX_TESTER is not set
+CONFIG_DEBUG_SPINLOCK=y
+CONFIG_DEBUG_MUTEXES=y
+# CONFIG_DEBUG_LOCK_ALLOC is not set
+# CONFIG_PROVE_LOCKING is not set
+# CONFIG_LOCK_STAT is not set
+CONFIG_DEBUG_SPINLOCK_SLEEP=y
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+CONFIG_STACKTRACE=y
+# CONFIG_DEBUG_KOBJECT is not set
+CONFIG_DEBUG_BUGVERBOSE=y
+# CONFIG_DEBUG_INFO is not set
+# CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_WRITECOUNT is not set
+# CONFIG_DEBUG_MEMORY_INIT is not set
+# CONFIG_DEBUG_LIST is not set
+# CONFIG_DEBUG_SG is not set
+# CONFIG_DEBUG_NOTIFIERS is not set
+# CONFIG_DEBUG_CREDENTIALS is not set
+# CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_RCU_CPU_STALL_DETECTOR is not set
+# CONFIG_BACKTRACE_SELF_TEST is not set
+# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
+# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
+# CONFIG_FAULT_INJECTION is not set
+CONFIG_LATENCYTOP=y
+CONFIG_SYSCTL_SYSCALL_CHECK=y
+# CONFIG_DEBUG_PAGEALLOC is not set
+CONFIG_NOP_TRACER=y
+CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
+CONFIG_HAVE_DYNAMIC_FTRACE=y
+CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
+CONFIG_TRACER_MAX_TRACE=y
+CONFIG_RING_BUFFER=y
+CONFIG_EVENT_TRACING=y
+CONFIG_CONTEXT_SWITCH_TRACER=y
+CONFIG_TRACING=y
+CONFIG_GENERIC_TRACER=y
+CONFIG_TRACING_SUPPORT=y
+CONFIG_FTRACE=y
+# CONFIG_FUNCTION_TRACER is not set
+# CONFIG_IRQSOFF_TRACER is not set
+# CONFIG_PREEMPT_TRACER is not set
+CONFIG_SCHED_TRACER=y
+CONFIG_BOOT_TRACER=y
+CONFIG_BRANCH_PROFILE_NONE=y
+# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set
+# CONFIG_PROFILE_ALL_BRANCHES is not set
+# CONFIG_STACK_TRACER is not set
+# CONFIG_KMEMTRACE is not set
+# CONFIG_WORKQUEUE_TRACER is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_FTRACE_STARTUP_TEST is not set
+# CONFIG_RING_BUFFER_BENCHMARK is not set
+# CONFIG_DYNAMIC_DEBUG is not set
+CONFIG_DMA_API_DEBUG=y
+# CONFIG_SAMPLES is not set
+CONFIG_HAVE_ARCH_KGDB=y
+# CONFIG_KGDB is not set
+# CONFIG_PPC_DISABLE_WERROR is not set
+CONFIG_PPC_WERROR=y
+CONFIG_PRINT_STACK_DEPTH=64
+# CONFIG_DEBUG_STACKOVERFLOW is not set
+# CONFIG_DEBUG_STACK_USAGE is not set
+# CONFIG_PPC_EMULATED_STATS is not set
+# CONFIG_CODE_PATCHING_SELFTEST is not set
+# CONFIG_FTR_FIXUP_SELFTEST is not set
+# CONFIG_MSI_BITMAP_SELFTEST is not set
+# CONFIG_XMON is not set
+# CONFIG_IRQSTACKS is not set
+# CONFIG_VIRQ_DEBUG is not set
+# CONFIG_BDI_SWITCH is not set
+# CONFIG_BOOTX_TEXT is not set
+CONFIG_PPC_EARLY_DEBUG=y
+# CONFIG_PPC_EARLY_DEBUG_LPAR is not set
+# CONFIG_PPC_EARLY_DEBUG_G5 is not set
+# CONFIG_PPC_EARLY_DEBUG_RTAS_PANEL is not set
+# CONFIG_PPC_EARLY_DEBUG_RTAS_CONSOLE is not set
+# CONFIG_PPC_EARLY_DEBUG_MAPLE is not set
+# CONFIG_PPC_EARLY_DEBUG_ISERIES is not set
+# CONFIG_PPC_EARLY_DEBUG_PAS_REALMODE is not set
+# CONFIG_PPC_EARLY_DEBUG_BEAT is not set
+# CONFIG_PPC_EARLY_DEBUG_44x is not set
+# CONFIG_PPC_EARLY_DEBUG_40x is not set
+# CONFIG_PPC_EARLY_DEBUG_CPM is not set
+CONFIG_PPC_EARLY_DEBUG_USBGECKO=y
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITYFS is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+# CONFIG_CRYPTO is not set
+# CONFIG_PPC_CLOCK is not set
+# CONFIG_VIRTUALIZATION is not set
diff --git a/arch/powerpc/configs/wii_defconfig b/arch/powerpc/configs/wii_defconfig
new file mode 100644
index 000000000000..c386828c639a
--- /dev/null
+++ b/arch/powerpc/configs/wii_defconfig
@@ -0,0 +1,1406 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.32-rc8
+# Sun Nov 22 20:37:21 2009
+#
+# CONFIG_PPC64 is not set
+
+#
+# Processor support
+#
+CONFIG_PPC_BOOK3S_32=y
+# CONFIG_PPC_85xx is not set
+# CONFIG_PPC_8xx is not set
+# CONFIG_40x is not set
+# CONFIG_44x is not set
+# CONFIG_E200 is not set
+CONFIG_PPC_BOOK3S=y
+CONFIG_6xx=y
+CONFIG_PPC_FPU=y
+# CONFIG_ALTIVEC is not set
+CONFIG_PPC_STD_MMU=y
+CONFIG_PPC_STD_MMU_32=y
+# CONFIG_PPC_MM_SLICES is not set
+CONFIG_PPC_HAVE_PMU_SUPPORT=y
+CONFIG_PPC_PERF_CTRS=y
+# CONFIG_SMP is not set
+CONFIG_NOT_COHERENT_CACHE=y
+CONFIG_PPC32=y
+CONFIG_WORD_SIZE=32
+# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set
+CONFIG_MMU=y
+CONFIG_GENERIC_CMOS_UPDATE=y
+CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_TIME_VSYSCALL=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
+# CONFIG_HAVE_SETUP_PER_CPU_AREA is not set
+# CONFIG_NEED_PER_CPU_EMBED_FIRST_CHUNK is not set
+CONFIG_IRQ_PER_CPU=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_HAVE_LATENCYTOP_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_RWSEM_XCHGADD_ALGORITHM=y
+CONFIG_ARCH_HAS_ILOG2_U32=y
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_FIND_NEXT_BIT=y
+CONFIG_GENERIC_GPIO=y
+# CONFIG_ARCH_NO_VIRT_TO_BUS is not set
+CONFIG_PPC=y
+CONFIG_EARLY_PRINTK=y
+CONFIG_GENERIC_NVRAM=y
+CONFIG_SCHED_OMIT_FRAME_POINTER=y
+CONFIG_ARCH_MAY_HAVE_PC_FDC=y
+CONFIG_PPC_OF=y
+CONFIG_OF=y
+# CONFIG_PPC_UDBG_16550 is not set
+# CONFIG_GENERIC_TBSYNC is not set
+CONFIG_AUDIT_ARCH=y
+CONFIG_GENERIC_BUG=y
+CONFIG_DTC=y
+# CONFIG_DEFAULT_UIMAGE is not set
+# CONFIG_PPC_DCR_NATIVE is not set
+# CONFIG_PPC_DCR_MMIO is not set
+CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+CONFIG_CONSTRUCTORS=y
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_LOCK_KERNEL=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION="-wii"
+# CONFIG_LOCALVERSION_AUTO is not set
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+# CONFIG_POSIX_MQUEUE is not set
+# CONFIG_BSD_PROCESS_ACCT is not set
+# CONFIG_TASKSTATS is not set
+# CONFIG_AUDIT is not set
+
+#
+# RCU Subsystem
+#
+CONFIG_TREE_RCU=y
+# CONFIG_TREE_PREEMPT_RCU is not set
+# CONFIG_RCU_TRACE is not set
+CONFIG_RCU_FANOUT=32
+# CONFIG_RCU_FANOUT_EXACT is not set
+# CONFIG_TREE_RCU_TRACE is not set
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_GROUP_SCHED=y
+CONFIG_FAIR_GROUP_SCHED=y
+# CONFIG_RT_GROUP_SCHED is not set
+CONFIG_USER_SCHED=y
+# CONFIG_CGROUP_SCHED is not set
+# CONFIG_CGROUPS is not set
+CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SYSFS_DEPRECATED_V2=y
+CONFIG_RELAY=y
+# CONFIG_NAMESPACES is not set
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_RD_GZIP=y
+# CONFIG_RD_BZIP2 is not set
+# CONFIG_RD_LZMA is not set
+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+CONFIG_SYSCTL=y
+CONFIG_ANON_INODES=y
+CONFIG_EMBEDDED=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_KALLSYMS=y
+CONFIG_KALLSYMS_ALL=y
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+# CONFIG_ELF_CORE is not set
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_AIO=y
+CONFIG_HAVE_PERF_EVENTS=y
+
+#
+# Kernel Performance Events And Counters
+#
+CONFIG_PERF_EVENTS=y
+CONFIG_EVENT_PROFILE=y
+CONFIG_PERF_COUNTERS=y
+# CONFIG_DEBUG_PERF_USE_VMALLOC is not set
+# CONFIG_VM_EVENT_COUNTERS is not set
+CONFIG_COMPAT_BRK=y
+CONFIG_SLAB=y
+# CONFIG_SLUB is not set
+# CONFIG_SLOB is not set
+# CONFIG_PROFILING is not set
+CONFIG_TRACEPOINTS=y
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_KPROBES is not set
+CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
+CONFIG_HAVE_IOREMAP_PROT=y
+CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_KRETPROBES=y
+CONFIG_HAVE_ARCH_TRACEHOOK=y
+CONFIG_HAVE_DMA_ATTRS=y
+CONFIG_HAVE_DMA_API_DEBUG=y
+
+#
+# GCOV-based kernel profiling
+#
+# CONFIG_GCOV_KERNEL is not set
+CONFIG_SLOW_WORK=y
+# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+# CONFIG_MODULE_FORCE_LOAD is not set
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODULE_FORCE_UNLOAD is not set
+# CONFIG_MODVERSIONS is not set
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+CONFIG_BLOCK=y
+CONFIG_LBDAF=y
+CONFIG_BLK_DEV_BSG=y
+# CONFIG_BLK_DEV_INTEGRITY is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+CONFIG_DEFAULT_AS=y
+# CONFIG_DEFAULT_DEADLINE is not set
+# CONFIG_DEFAULT_CFQ is not set
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="anticipatory"
+# CONFIG_FREEZER is not set
+
+#
+# Platform support
+#
+# CONFIG_PPC_CHRP is not set
+# CONFIG_MPC5121_ADS is not set
+# CONFIG_MPC5121_GENERIC is not set
+# CONFIG_PPC_MPC52xx is not set
+# CONFIG_PPC_PMAC is not set
+# CONFIG_PPC_CELL is not set
+# CONFIG_PPC_CELL_NATIVE is not set
+# CONFIG_PPC_82xx is not set
+# CONFIG_PQ2ADS is not set
+# CONFIG_PPC_83xx is not set
+# CONFIG_PPC_86xx is not set
+CONFIG_EMBEDDED6xx=y
+# CONFIG_LINKSTATION is not set
+# CONFIG_STORCENTER is not set
+# CONFIG_MPC7448HPC2 is not set
+# CONFIG_PPC_HOLLY is not set
+# CONFIG_PPC_PRPMC2800 is not set
+# CONFIG_PPC_C2K is not set
+CONFIG_GAMECUBE_COMMON=y
+CONFIG_USBGECKO_UDBG=y
+CONFIG_FLIPPER_PIC=y
+# CONFIG_GAMECUBE is not set
+CONFIG_HLWD_PIC=y
+CONFIG_STARLET_MINI=y
+CONFIG_WII=y
+# CONFIG_AMIGAONE is not set
+# CONFIG_PPC_OF_BOOT_TRAMPOLINE is not set
+# CONFIG_IPIC is not set
+# CONFIG_MPIC is not set
+# CONFIG_MPIC_WEIRD is not set
+# CONFIG_PPC_I8259 is not set
+# CONFIG_PPC_RTAS is not set
+# CONFIG_MMIO_NVRAM is not set
+# CONFIG_PPC_MPC106 is not set
+# CONFIG_PPC_970_NAP is not set
+# CONFIG_PPC_INDIRECT_IO is not set
+# CONFIG_GENERIC_IOMAP is not set
+# CONFIG_CPU_FREQ is not set
+# CONFIG_TAU is not set
+# CONFIG_FSL_ULI1575 is not set
+# CONFIG_SIMPLE_GPIO is not set
+
+#
+# Kernel options
+#
+# CONFIG_HIGHMEM is not set
+# CONFIG_NO_HZ is not set
+# CONFIG_HIGH_RES_TIMERS is not set
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+# CONFIG_HZ_100 is not set
+CONFIG_HZ_250=y
+# CONFIG_HZ_300 is not set
+# CONFIG_HZ_1000 is not set
+CONFIG_HZ=250
+# CONFIG_SCHED_HRTICK is not set
+# CONFIG_PREEMPT_NONE is not set
+# CONFIG_PREEMPT_VOLUNTARY is not set
+CONFIG_PREEMPT=y
+CONFIG_BINFMT_ELF=y
+# CONFIG_HAVE_AOUT is not set
+CONFIG_BINFMT_MISC=m
+# CONFIG_IOMMU_HELPER is not set
+# CONFIG_SWIOTLB is not set
+CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y
+CONFIG_ARCH_HAS_WALK_MEMORY=y
+CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y
+CONFIG_KEXEC=y
+# CONFIG_CRASH_DUMP is not set
+CONFIG_MAX_ACTIVE_REGIONS=32
+CONFIG_ARCH_FLATMEM_ENABLE=y
+CONFIG_ARCH_POPULATES_NODE_MAP=y
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_SPLIT_PTLOCK_CPUS=4
+# CONFIG_MIGRATION is not set
+# CONFIG_PHYS_ADDR_T_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=1
+CONFIG_BOUNCE=y
+CONFIG_VIRT_TO_BUS=y
+CONFIG_HAVE_MLOCK=y
+CONFIG_HAVE_MLOCKED_PAGE_BIT=y
+# CONFIG_KSM is not set
+CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
+CONFIG_PPC_4K_PAGES=y
+# CONFIG_PPC_16K_PAGES is not set
+# CONFIG_PPC_64K_PAGES is not set
+# CONFIG_PPC_256K_PAGES is not set
+CONFIG_FORCE_MAX_ZONEORDER=11
+CONFIG_PROC_DEVICETREE=y
+# CONFIG_CMDLINE_BOOL is not set
+CONFIG_EXTRA_TARGETS=""
+# CONFIG_PM is not set
+# CONFIG_SECCOMP is not set
+CONFIG_ISA_DMA_API=y
+
+#
+# Bus options
+#
+CONFIG_ZONE_DMA=y
+CONFIG_GENERIC_ISA_DMA=y
+# CONFIG_PCI is not set
+# CONFIG_PCI_DOMAINS is not set
+# CONFIG_PCI_SYSCALL is not set
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+# CONFIG_PCCARD is not set
+# CONFIG_HAS_RAPIDIO is not set
+
+#
+# Advanced setup
+#
+CONFIG_ADVANCED_OPTIONS=y
+# CONFIG_LOWMEM_SIZE_BOOL is not set
+CONFIG_LOWMEM_SIZE=0x30000000
+# CONFIG_PAGE_OFFSET_BOOL is not set
+CONFIG_PAGE_OFFSET=0xc0000000
+# CONFIG_KERNEL_START_BOOL is not set
+CONFIG_KERNEL_START=0xc0000000
+CONFIG_PHYSICAL_START=0x00000000
+# CONFIG_TASK_SIZE_BOOL is not set
+CONFIG_TASK_SIZE=0xc0000000
+# CONFIG_CONSISTENT_SIZE_BOOL is not set
+CONFIG_CONSISTENT_SIZE=0x00200000
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+# CONFIG_PACKET_MMAP is not set
+CONFIG_UNIX=y
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+# CONFIG_IP_MULTICAST is not set
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+# CONFIG_IP_PNP_BOOTP is not set
+CONFIG_IP_PNP_RARP=y
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
+# CONFIG_INET_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_LRO is not set
+# CONFIG_INET_DIAG is not set
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+# CONFIG_IPV6 is not set
+# CONFIG_NETWORK_SECMARK is not set
+# CONFIG_NETFILTER is not set
+# CONFIG_IP_DCCP is not set
+# CONFIG_IP_SCTP is not set
+# CONFIG_RDS is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_NET_DSA is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_PHONET is not set
+# CONFIG_IEEE802154 is not set
+# CONFIG_NET_SCHED is not set
+# CONFIG_DCB is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_NET_DROP_MONITOR is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
+# CONFIG_IRDA is not set
+CONFIG_BT=y
+CONFIG_BT_L2CAP=y
+# CONFIG_BT_SCO is not set
+CONFIG_BT_RFCOMM=y
+# CONFIG_BT_RFCOMM_TTY is not set
+CONFIG_BT_BNEP=y
+CONFIG_BT_BNEP_MC_FILTER=y
+# CONFIG_BT_BNEP_PROTO_FILTER is not set
+CONFIG_BT_HIDP=y
+
+#
+# Bluetooth device drivers
+#
+# CONFIG_BT_HCIBTSDIO is not set
+# CONFIG_BT_HCIUART is not set
+# CONFIG_BT_HCIVHCI is not set
+# CONFIG_BT_MRVL is not set
+# CONFIG_AF_RXRPC is not set
+CONFIG_WIRELESS=y
+CONFIG_CFG80211=y
+# CONFIG_NL80211_TESTMODE is not set
+# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set
+# CONFIG_CFG80211_REG_DEBUG is not set
+CONFIG_CFG80211_DEFAULT_PS=y
+CONFIG_CFG80211_DEFAULT_PS_VALUE=1
+# CONFIG_CFG80211_DEBUGFS is not set
+CONFIG_WIRELESS_OLD_REGULATORY=y
+CONFIG_WIRELESS_EXT=y
+CONFIG_WIRELESS_EXT_SYSFS=y
+# CONFIG_LIB80211 is not set
+CONFIG_MAC80211=y
+# CONFIG_MAC80211_RC_PID is not set
+CONFIG_MAC80211_RC_MINSTREL=y
+# CONFIG_MAC80211_RC_DEFAULT_PID is not set
+CONFIG_MAC80211_RC_DEFAULT_MINSTREL=y
+CONFIG_MAC80211_RC_DEFAULT="minstrel"
+# CONFIG_MAC80211_MESH is not set
+# CONFIG_MAC80211_LEDS is not set
+# CONFIG_MAC80211_DEBUGFS is not set
+# CONFIG_MAC80211_DEBUG_MENU is not set
+# CONFIG_WIMAX is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+# CONFIG_DEVTMPFS is not set
+# CONFIG_STANDALONE is not set
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+CONFIG_FW_LOADER=y
+# CONFIG_FIRMWARE_IN_KERNEL is not set
+CONFIG_EXTRA_FIRMWARE=""
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
+# CONFIG_SYS_HYPERVISOR is not set
+# CONFIG_CONNECTOR is not set
+# CONFIG_MTD is not set
+CONFIG_OF_DEVICE=y
+CONFIG_OF_GPIO=y
+CONFIG_OF_I2C=y
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_FD is not set
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=y
+# CONFIG_BLK_DEV_CRYPTOLOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=2
+CONFIG_BLK_DEV_RAM_SIZE=4096
+# CONFIG_BLK_DEV_XIP is not set
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+# CONFIG_BLK_DEV_HD is not set
+CONFIG_MISC_DEVICES=y
+# CONFIG_ICS932S401 is not set
+# CONFIG_ENCLOSURE_SERVICES is not set
+# CONFIG_ISL29003 is not set
+# CONFIG_C2PORT is not set
+
+#
+# EEPROM support
+#
+# CONFIG_EEPROM_AT24 is not set
+# CONFIG_EEPROM_LEGACY is not set
+# CONFIG_EEPROM_MAX6875 is not set
+# CONFIG_EEPROM_93CX6 is not set
+CONFIG_HAVE_IDE=y
+# CONFIG_IDE is not set
+
+#
+# SCSI device support
+#
+# CONFIG_RAID_ATTRS is not set
+CONFIG_SCSI=y
+CONFIG_SCSI_DMA=y
+# CONFIG_SCSI_TGT is not set
+# CONFIG_SCSI_NETLINK is not set
+CONFIG_SCSI_PROC_FS=y
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+# CONFIG_BLK_DEV_SR is not set
+# CONFIG_CHR_DEV_SG is not set
+# CONFIG_CHR_DEV_SCH is not set
+CONFIG_SCSI_MULTI_LUN=y
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+# CONFIG_SCSI_SCAN_ASYNC is not set
+CONFIG_SCSI_WAIT_SCAN=m
+
+#
+# SCSI Transports
+#
+# CONFIG_SCSI_SPI_ATTRS is not set
+# CONFIG_SCSI_FC_ATTRS is not set
+# CONFIG_SCSI_ISCSI_ATTRS is not set
+# CONFIG_SCSI_SAS_ATTRS is not set
+# CONFIG_SCSI_SAS_LIBSAS is not set
+# CONFIG_SCSI_SRP_ATTRS is not set
+CONFIG_SCSI_LOWLEVEL=y
+# CONFIG_ISCSI_TCP is not set
+# CONFIG_LIBFC is not set
+# CONFIG_LIBFCOE is not set
+# CONFIG_SCSI_DEBUG is not set
+# CONFIG_SCSI_DH is not set
+# CONFIG_SCSI_OSD_INITIATOR is not set
+# CONFIG_ATA is not set
+# CONFIG_MD is not set
+# CONFIG_MACINTOSH_DRIVERS is not set
+CONFIG_NETDEVICES=y
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_VETH is not set
+# CONFIG_PHYLIB is not set
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
+# CONFIG_ETHOC is not set
+# CONFIG_DNET is not set
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
+# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
+# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
+# CONFIG_B44 is not set
+# CONFIG_KS8842 is not set
+# CONFIG_KS8851_MLL is not set
+# CONFIG_XILINX_EMACLITE is not set
+# CONFIG_NETDEV_1000 is not set
+# CONFIG_NETDEV_10000 is not set
+CONFIG_WLAN=y
+# CONFIG_WLAN_PRE80211 is not set
+CONFIG_WLAN_80211=y
+# CONFIG_LIBERTAS is not set
+# CONFIG_LIBERTAS_THINFIRM is not set
+# CONFIG_MAC80211_HWSIM is not set
+# CONFIG_P54_COMMON is not set
+# CONFIG_ATH_COMMON is not set
+# CONFIG_HOSTAP is not set
+CONFIG_B43=y
+CONFIG_B43_SDIO=y
+CONFIG_B43_PIO=y
+# CONFIG_B43_PHY_LP is not set
+CONFIG_B43_DEBUG=y
+# CONFIG_B43_FORCE_PIO is not set
+# CONFIG_B43LEGACY is not set
+# CONFIG_RT2X00 is not set
+# CONFIG_WL12XX is not set
+# CONFIG_IWM is not set
+
+#
+# Enable WiMAX (Networking options) to see the WiMAX drivers
+#
+# CONFIG_WAN is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_ISDN is not set
+# CONFIG_PHONE is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+CONFIG_INPUT_FF_MEMLESS=m
+# CONFIG_INPUT_POLLDEV is not set
+
+#
+# Userland interfaces
+#
+CONFIG_INPUT_MOUSEDEV=y
+# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=640
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=480
+CONFIG_INPUT_JOYDEV=y
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input Device Drivers
+#
+CONFIG_INPUT_KEYBOARD=y
+# CONFIG_KEYBOARD_ADP5588 is not set
+# CONFIG_KEYBOARD_ATKBD is not set
+# CONFIG_QT2160 is not set
+# CONFIG_KEYBOARD_LKKBD is not set
+# CONFIG_KEYBOARD_GPIO is not set
+# CONFIG_KEYBOARD_MATRIX is not set
+# CONFIG_KEYBOARD_MAX7359 is not set
+# CONFIG_KEYBOARD_NEWTON is not set
+# CONFIG_KEYBOARD_OPENCORES is not set
+# CONFIG_KEYBOARD_STOWAWAY is not set
+# CONFIG_KEYBOARD_SUNKBD is not set
+# CONFIG_KEYBOARD_XTKBD is not set
+CONFIG_INPUT_MOUSE=y
+# CONFIG_MOUSE_PS2 is not set
+# CONFIG_MOUSE_SERIAL is not set
+# CONFIG_MOUSE_VSXXXAA is not set
+# CONFIG_MOUSE_GPIO is not set
+# CONFIG_MOUSE_SYNAPTICS_I2C is not set
+CONFIG_INPUT_JOYSTICK=y
+# CONFIG_JOYSTICK_ANALOG is not set
+# CONFIG_JOYSTICK_A3D is not set
+# CONFIG_JOYSTICK_ADI is not set
+# CONFIG_JOYSTICK_COBRA is not set
+# CONFIG_JOYSTICK_GF2K is not set
+# CONFIG_JOYSTICK_GRIP is not set
+# CONFIG_JOYSTICK_GRIP_MP is not set
+# CONFIG_JOYSTICK_GUILLEMOT is not set
+# CONFIG_JOYSTICK_INTERACT is not set
+# CONFIG_JOYSTICK_SIDEWINDER is not set
+# CONFIG_JOYSTICK_TMDC is not set
+# CONFIG_JOYSTICK_IFORCE is not set
+# CONFIG_JOYSTICK_WARRIOR is not set
+# CONFIG_JOYSTICK_MAGELLAN is not set
+# CONFIG_JOYSTICK_SPACEORB is not set
+# CONFIG_JOYSTICK_SPACEBALL is not set
+# CONFIG_JOYSTICK_STINGER is not set
+# CONFIG_JOYSTICK_TWIDJOY is not set
+# CONFIG_JOYSTICK_ZHENHUA is not set
+# CONFIG_JOYSTICK_JOYDUMP is not set
+# CONFIG_INPUT_TABLET is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+CONFIG_INPUT_MISC=y
+CONFIG_INPUT_UINPUT=y
+# CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set
+
+#
+# Hardware I/O ports
+#
+CONFIG_SERIO=y
+# CONFIG_SERIO_I8042 is not set
+# CONFIG_SERIO_SERPORT is not set
+# CONFIG_SERIO_LIBPS2 is not set
+# CONFIG_SERIO_RAW is not set
+# CONFIG_SERIO_XILINX_XPS_PS2 is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+# CONFIG_VT_HW_CONSOLE_BINDING is not set
+# CONFIG_DEVKMEM is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+# CONFIG_SERIAL_8250 is not set
+
+#
+# Non-8250 serial port support
+#
+# CONFIG_SERIAL_UARTLITE is not set
+CONFIG_UNIX98_PTYS=y
+# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
+CONFIG_LEGACY_PTYS=y
+CONFIG_LEGACY_PTY_COUNT=64
+# CONFIG_HVC_UDBG is not set
+# CONFIG_IPMI_HANDLER is not set
+# CONFIG_HW_RANDOM is not set
+CONFIG_NVRAM=y
+# CONFIG_R3964 is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_COMPAT=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_HELPER_AUTO=y
+CONFIG_I2C_ALGOBIT=y
+
+#
+# I2C Hardware Bus support
+#
+
+#
+# I2C system bus drivers (mostly embedded / system-on-chip)
+#
+CONFIG_I2C_GPIO=y
+# CONFIG_I2C_MPC is not set
+# CONFIG_I2C_OCORES is not set
+# CONFIG_I2C_SIMTEC is not set
+
+#
+# External I2C/SMBus adapter drivers
+#
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_TAOS_EVM is not set
+
+#
+# Other I2C/SMBus bus drivers
+#
+# CONFIG_I2C_PCA_PLATFORM is not set
+# CONFIG_I2C_STUB is not set
+
+#
+# Miscellaneous I2C Chip support
+#
+# CONFIG_DS1682 is not set
+# CONFIG_SENSORS_TSL2550 is not set
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+# CONFIG_I2C_DEBUG_CHIP is not set
+# CONFIG_SPI is not set
+
+#
+# PPS support
+#
+# CONFIG_PPS is not set
+CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
+CONFIG_GPIOLIB=y
+# CONFIG_DEBUG_GPIO is not set
+CONFIG_GPIO_SYSFS=y
+
+#
+# Memory mapped GPIO expanders:
+#
+# CONFIG_GPIO_XILINX is not set
+
+#
+# I2C GPIO expanders:
+#
+# CONFIG_GPIO_MAX732X is not set
+# CONFIG_GPIO_PCA953X is not set
+# CONFIG_GPIO_PCF857X is not set
+
+#
+# PCI GPIO expanders:
+#
+
+#
+# SPI GPIO expanders:
+#
+
+#
+# AC97 GPIO expanders:
+#
+# CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
+# CONFIG_HWMON is not set
+# CONFIG_THERMAL is not set
+# CONFIG_WATCHDOG is not set
+CONFIG_SSB_POSSIBLE=y
+
+#
+# Sonics Silicon Backplane
+#
+CONFIG_SSB=y
+CONFIG_SSB_BLOCKIO=y
+CONFIG_SSB_SDIOHOST_POSSIBLE=y
+CONFIG_SSB_SDIOHOST=y
+# CONFIG_SSB_SILENT is not set
+CONFIG_SSB_DEBUG=y
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_CORE is not set
+# CONFIG_MFD_SM501 is not set
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_TPS65010 is not set
+# CONFIG_TWL4030_CORE is not set
+# CONFIG_MFD_TMIO is not set
+# CONFIG_PMIC_DA903X is not set
+# CONFIG_MFD_WM8400 is not set
+# CONFIG_MFD_WM831X is not set
+# CONFIG_MFD_WM8350_I2C is not set
+# CONFIG_MFD_PCF50633 is not set
+# CONFIG_AB3100_CORE is not set
+# CONFIG_REGULATOR is not set
+# CONFIG_MEDIA_SUPPORT is not set
+
+#
+# Graphics support
+#
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+CONFIG_FB=y
+# CONFIG_FIRMWARE_EDID is not set
+# CONFIG_FB_DDC is not set
+# CONFIG_FB_BOOT_VESA_SUPPORT is not set
+# CONFIG_FB_CFB_FILLRECT is not set
+# CONFIG_FB_CFB_COPYAREA is not set
+# CONFIG_FB_CFB_IMAGEBLIT is not set
+# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
+# CONFIG_FB_SYS_FILLRECT is not set
+# CONFIG_FB_SYS_COPYAREA is not set
+# CONFIG_FB_SYS_IMAGEBLIT is not set
+# CONFIG_FB_FOREIGN_ENDIAN is not set
+# CONFIG_FB_SYS_FOPS is not set
+# CONFIG_FB_SVGALIB is not set
+# CONFIG_FB_MACMODES is not set
+# CONFIG_FB_BACKLIGHT is not set
+# CONFIG_FB_MODE_HELPERS is not set
+# CONFIG_FB_TILEBLITTING is not set
+
+#
+# Frame buffer hardware drivers
+#
+# CONFIG_FB_OF is not set
+# CONFIG_FB_VGA16 is not set
+# CONFIG_FB_S1D13XXX is not set
+# CONFIG_FB_IBM_GXT4500 is not set
+# CONFIG_FB_VIRTUAL is not set
+# CONFIG_FB_METRONOME is not set
+# CONFIG_FB_MB862XX is not set
+# CONFIG_FB_BROADSHEET is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+
+#
+# Console display driver support
+#
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_DUMMY_CONSOLE=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
+# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
+# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
+# CONFIG_FONTS is not set
+CONFIG_FONT_8x8=y
+CONFIG_FONT_8x16=y
+# CONFIG_LOGO is not set
+CONFIG_SOUND=y
+CONFIG_SOUND_OSS_CORE=y
+CONFIG_SOUND_OSS_CORE_PRECLAIM=y
+CONFIG_SND=y
+CONFIG_SND_TIMER=y
+CONFIG_SND_PCM=y
+CONFIG_SND_SEQUENCER=y
+# CONFIG_SND_SEQ_DUMMY is not set
+CONFIG_SND_OSSEMUL=y
+CONFIG_SND_MIXER_OSS=y
+CONFIG_SND_PCM_OSS=y
+CONFIG_SND_PCM_OSS_PLUGINS=y
+CONFIG_SND_SEQUENCER_OSS=y
+# CONFIG_SND_DYNAMIC_MINORS is not set
+CONFIG_SND_SUPPORT_OLD_API=y
+# CONFIG_SND_VERBOSE_PROCFS is not set
+# CONFIG_SND_VERBOSE_PRINTK is not set
+# CONFIG_SND_DEBUG is not set
+# CONFIG_SND_RAWMIDI_SEQ is not set
+# CONFIG_SND_OPL3_LIB_SEQ is not set
+# CONFIG_SND_OPL4_LIB_SEQ is not set
+# CONFIG_SND_SBAWE_SEQ is not set
+# CONFIG_SND_EMU10K1_SEQ is not set
+CONFIG_SND_DRIVERS=y
+# CONFIG_SND_DUMMY is not set
+# CONFIG_SND_VIRMIDI is not set
+# CONFIG_SND_MTPAV is not set
+# CONFIG_SND_SERIAL_U16550 is not set
+# CONFIG_SND_MPU401 is not set
+CONFIG_SND_PPC=y
+# CONFIG_SND_SOC is not set
+# CONFIG_SOUND_PRIME is not set
+CONFIG_HID_SUPPORT=y
+CONFIG_HID=y
+# CONFIG_HIDRAW is not set
+# CONFIG_HID_PID is not set
+
+#
+# Special HID drivers
+#
+CONFIG_HID_APPLE=m
+CONFIG_HID_WACOM=m
+CONFIG_USB_SUPPORT=y
+# CONFIG_USB_ARCH_HAS_HCD is not set
+# CONFIG_USB_ARCH_HAS_OHCI is not set
+# CONFIG_USB_ARCH_HAS_EHCI is not set
+# CONFIG_USB_OTG_WHITELIST is not set
+# CONFIG_USB_OTG_BLACKLIST_HUB is not set
+
+#
+# Enable Host or Gadget support to see Inventra options
+#
+
+#
+# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
+#
+# CONFIG_USB_GADGET is not set
+
+#
+# OTG and related infrastructure
+#
+CONFIG_MMC=y
+# CONFIG_MMC_DEBUG is not set
+# CONFIG_MMC_UNSAFE_RESUME is not set
+
+#
+# MMC/SD/SDIO Card Drivers
+#
+CONFIG_MMC_BLOCK=y
+CONFIG_MMC_BLOCK_BOUNCE=y
+# CONFIG_SDIO_UART is not set
+# CONFIG_MMC_TEST is not set
+
+#
+# MMC/SD/SDIO Host Controller Drivers
+#
+CONFIG_MMC_SDHCI=y
+# CONFIG_MMC_SDHCI_OF is not set
+# CONFIG_MMC_SDHCI_PLTFM is not set
+# CONFIG_MMC_WBSD is not set
+# CONFIG_MMC_AT91 is not set
+# CONFIG_MMC_ATMELMCI is not set
+# CONFIG_MEMSTICK is not set
+# CONFIG_NEW_LEDS is not set
+# CONFIG_ACCESSIBILITY is not set
+# CONFIG_EDAC is not set
+CONFIG_RTC_LIB=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_HCTOSYS=y
+CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
+# CONFIG_RTC_DEBUG is not set
+
+#
+# RTC interfaces
+#
+CONFIG_RTC_INTF_SYSFS=y
+CONFIG_RTC_INTF_PROC=y
+CONFIG_RTC_INTF_DEV=y
+# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
+# CONFIG_RTC_DRV_TEST is not set
+
+#
+# I2C RTC drivers
+#
+# CONFIG_RTC_DRV_DS1307 is not set
+# CONFIG_RTC_DRV_DS1374 is not set
+# CONFIG_RTC_DRV_DS1672 is not set
+# CONFIG_RTC_DRV_MAX6900 is not set
+# CONFIG_RTC_DRV_RS5C372 is not set
+# CONFIG_RTC_DRV_ISL1208 is not set
+# CONFIG_RTC_DRV_X1205 is not set
+# CONFIG_RTC_DRV_PCF8563 is not set
+# CONFIG_RTC_DRV_PCF8583 is not set
+# CONFIG_RTC_DRV_M41T80 is not set
+# CONFIG_RTC_DRV_S35390A is not set
+# CONFIG_RTC_DRV_FM3130 is not set
+# CONFIG_RTC_DRV_RX8581 is not set
+# CONFIG_RTC_DRV_RX8025 is not set
+
+#
+# SPI RTC drivers
+#
+
+#
+# Platform RTC drivers
+#
+# CONFIG_RTC_DRV_CMOS is not set
+# CONFIG_RTC_DRV_DS1286 is not set
+# CONFIG_RTC_DRV_DS1511 is not set
+# CONFIG_RTC_DRV_DS1553 is not set
+# CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_STK17TA8 is not set
+# CONFIG_RTC_DRV_M48T86 is not set
+# CONFIG_RTC_DRV_M48T35 is not set
+# CONFIG_RTC_DRV_M48T59 is not set
+# CONFIG_RTC_DRV_BQ4802 is not set
+# CONFIG_RTC_DRV_V3020 is not set
+
+#
+# on-CPU RTC drivers
+#
+CONFIG_RTC_DRV_GENERIC=y
+# CONFIG_DMADEVICES is not set
+# CONFIG_AUXDISPLAY is not set
+# CONFIG_UIO is not set
+
+#
+# TI VLYNQ
+#
+# CONFIG_STAGING is not set
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+# CONFIG_EXT2_FS_XATTR is not set
+# CONFIG_EXT2_FS_XIP is not set
+CONFIG_EXT3_FS=y
+# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
+# CONFIG_EXT3_FS_XATTR is not set
+# CONFIG_EXT4_FS is not set
+CONFIG_JBD=y
+# CONFIG_JBD_DEBUG is not set
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+# CONFIG_FS_POSIX_ACL is not set
+# CONFIG_XFS_FS is not set
+# CONFIG_GFS2_FS is not set
+# CONFIG_OCFS2_FS is not set
+# CONFIG_BTRFS_FS is not set
+# CONFIG_NILFS2_FS is not set
+CONFIG_FILE_LOCKING=y
+CONFIG_FSNOTIFY=y
+CONFIG_DNOTIFY=y
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+CONFIG_FUSE_FS=m
+# CONFIG_CUSE is not set
+
+#
+# Caches
+#
+# CONFIG_FSCACHE is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+CONFIG_ISO9660_FS=y
+CONFIG_JOLIET=y
+# CONFIG_ZISOFS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_KCORE=y
+CONFIG_PROC_SYSCTL=y
+# CONFIG_PROC_PAGE_MONITOR is not set
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_HUGETLB_PAGE is not set
+# CONFIG_CONFIGFS_FS is not set
+CONFIG_MISC_FILESYSTEMS=y
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+# CONFIG_CRAMFS is not set
+# CONFIG_SQUASHFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_OMFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+# CONFIG_NFS_V3_ACL is not set
+# CONFIG_NFS_V4 is not set
+CONFIG_ROOT_NFS=y
+# CONFIG_NFSD is not set
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=y
+# CONFIG_RPCSEC_GSS_KRB5 is not set
+# CONFIG_RPCSEC_GSS_SPKM3 is not set
+# CONFIG_SMB_FS is not set
+CONFIG_CIFS=m
+# CONFIG_CIFS_STATS is not set
+# CONFIG_CIFS_WEAK_PW_HASH is not set
+# CONFIG_CIFS_XATTR is not set
+# CONFIG_CIFS_DEBUG2 is not set
+# CONFIG_CIFS_EXPERIMENTAL is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="iso8859-1"
+CONFIG_NLS_CODEPAGE_437=y
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+# CONFIG_NLS_ASCII is not set
+CONFIG_NLS_ISO8859_1=y
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+# CONFIG_NLS_UTF8 is not set
+# CONFIG_DLM is not set
+CONFIG_BINARY_PRINTF=y
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+CONFIG_GENERIC_FIND_LAST_BIT=y
+CONFIG_CRC_CCITT=y
+CONFIG_CRC16=y
+# CONFIG_CRC_T10DIF is not set
+# CONFIG_CRC_ITU_T is not set
+CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
+# CONFIG_LIBCRC32C is not set
+CONFIG_ZLIB_INFLATE=y
+CONFIG_DECOMPRESS_GZIP=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
+CONFIG_HAVE_LMB=y
+CONFIG_NLATTR=y
+CONFIG_GENERIC_ATOMIC64=y
+
+#
+# Kernel hacking
+#
+CONFIG_PRINTK_TIME=y
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_FRAME_WARN=1024
+CONFIG_MAGIC_SYSRQ=y
+# CONFIG_STRIP_ASM_SYMS is not set
+# CONFIG_UNUSED_SYMBOLS is not set
+CONFIG_DEBUG_FS=y
+# CONFIG_HEADERS_CHECK is not set
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_SHIRQ is not set
+CONFIG_DETECT_SOFTLOCKUP=y
+# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
+CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
+# CONFIG_DETECT_HUNG_TASK is not set
+CONFIG_SCHED_DEBUG=y
+CONFIG_SCHEDSTATS=y
+# CONFIG_TIMER_STATS is not set
+# CONFIG_DEBUG_OBJECTS is not set
+# CONFIG_DEBUG_SLAB is not set
+# CONFIG_DEBUG_KMEMLEAK is not set
+CONFIG_DEBUG_PREEMPT=y
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_RT_MUTEX_TESTER is not set
+CONFIG_DEBUG_SPINLOCK=y
+CONFIG_DEBUG_MUTEXES=y
+# CONFIG_DEBUG_LOCK_ALLOC is not set
+# CONFIG_PROVE_LOCKING is not set
+# CONFIG_LOCK_STAT is not set
+CONFIG_DEBUG_SPINLOCK_SLEEP=y
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+CONFIG_STACKTRACE=y
+# CONFIG_DEBUG_KOBJECT is not set
+CONFIG_DEBUG_BUGVERBOSE=y
+# CONFIG_DEBUG_INFO is not set
+# CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_WRITECOUNT is not set
+# CONFIG_DEBUG_MEMORY_INIT is not set
+# CONFIG_DEBUG_LIST is not set
+# CONFIG_DEBUG_SG is not set
+# CONFIG_DEBUG_NOTIFIERS is not set
+# CONFIG_DEBUG_CREDENTIALS is not set
+# CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_RCU_CPU_STALL_DETECTOR is not set
+# CONFIG_BACKTRACE_SELF_TEST is not set
+# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
+# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
+# CONFIG_FAULT_INJECTION is not set
+CONFIG_LATENCYTOP=y
+CONFIG_SYSCTL_SYSCALL_CHECK=y
+# CONFIG_DEBUG_PAGEALLOC is not set
+CONFIG_NOP_TRACER=y
+CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
+CONFIG_HAVE_DYNAMIC_FTRACE=y
+CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
+CONFIG_TRACER_MAX_TRACE=y
+CONFIG_RING_BUFFER=y
+CONFIG_EVENT_TRACING=y
+CONFIG_CONTEXT_SWITCH_TRACER=y
+CONFIG_TRACING=y
+CONFIG_GENERIC_TRACER=y
+CONFIG_TRACING_SUPPORT=y
+CONFIG_FTRACE=y
+# CONFIG_FUNCTION_TRACER is not set
+# CONFIG_IRQSOFF_TRACER is not set
+# CONFIG_PREEMPT_TRACER is not set
+CONFIG_SCHED_TRACER=y
+CONFIG_BOOT_TRACER=y
+CONFIG_BRANCH_PROFILE_NONE=y
+# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set
+# CONFIG_PROFILE_ALL_BRANCHES is not set
+# CONFIG_STACK_TRACER is not set
+# CONFIG_KMEMTRACE is not set
+# CONFIG_WORKQUEUE_TRACER is not set
+CONFIG_BLK_DEV_IO_TRACE=y
+# CONFIG_FTRACE_STARTUP_TEST is not set
+# CONFIG_RING_BUFFER_BENCHMARK is not set
+# CONFIG_DYNAMIC_DEBUG is not set
+CONFIG_DMA_API_DEBUG=y
+# CONFIG_SAMPLES is not set
+CONFIG_HAVE_ARCH_KGDB=y
+# CONFIG_KGDB is not set
+# CONFIG_PPC_DISABLE_WERROR is not set
+CONFIG_PPC_WERROR=y
+CONFIG_PRINT_STACK_DEPTH=64
+# CONFIG_DEBUG_STACKOVERFLOW is not set
+# CONFIG_DEBUG_STACK_USAGE is not set
+# CONFIG_PPC_EMULATED_STATS is not set
+# CONFIG_CODE_PATCHING_SELFTEST is not set
+# CONFIG_FTR_FIXUP_SELFTEST is not set
+# CONFIG_MSI_BITMAP_SELFTEST is not set
+# CONFIG_XMON is not set
+# CONFIG_IRQSTACKS is not set
+# CONFIG_VIRQ_DEBUG is not set
+# CONFIG_BDI_SWITCH is not set
+# CONFIG_BOOTX_TEXT is not set
+CONFIG_PPC_EARLY_DEBUG=y
+# CONFIG_PPC_EARLY_DEBUG_LPAR is not set
+# CONFIG_PPC_EARLY_DEBUG_G5 is not set
+# CONFIG_PPC_EARLY_DEBUG_RTAS_PANEL is not set
+# CONFIG_PPC_EARLY_DEBUG_RTAS_CONSOLE is not set
+# CONFIG_PPC_EARLY_DEBUG_MAPLE is not set
+# CONFIG_PPC_EARLY_DEBUG_ISERIES is not set
+# CONFIG_PPC_EARLY_DEBUG_PAS_REALMODE is not set
+# CONFIG_PPC_EARLY_DEBUG_BEAT is not set
+# CONFIG_PPC_EARLY_DEBUG_44x is not set
+# CONFIG_PPC_EARLY_DEBUG_40x is not set
+# CONFIG_PPC_EARLY_DEBUG_CPM is not set
+CONFIG_PPC_EARLY_DEBUG_USBGECKO=y
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITYFS is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+CONFIG_CRYPTO=y
+
+#
+# Crypto core or helper
+#
+CONFIG_CRYPTO_ALGAPI=y
+CONFIG_CRYPTO_ALGAPI2=y
+CONFIG_CRYPTO_AEAD2=y
+CONFIG_CRYPTO_BLKCIPHER=y
+CONFIG_CRYPTO_BLKCIPHER2=y
+CONFIG_CRYPTO_HASH2=y
+CONFIG_CRYPTO_RNG2=y
+CONFIG_CRYPTO_PCOMP=y
+CONFIG_CRYPTO_MANAGER=y
+CONFIG_CRYPTO_MANAGER2=y
+# CONFIG_CRYPTO_GF128MUL is not set
+# CONFIG_CRYPTO_NULL is not set
+CONFIG_CRYPTO_WORKQUEUE=y
+# CONFIG_CRYPTO_CRYPTD is not set
+# CONFIG_CRYPTO_AUTHENC is not set
+# CONFIG_CRYPTO_TEST is not set
+
+#
+# Authenticated Encryption with Associated Data
+#
+# CONFIG_CRYPTO_CCM is not set
+# CONFIG_CRYPTO_GCM is not set
+# CONFIG_CRYPTO_SEQIV is not set
+
+#
+# Block modes
+#
+# CONFIG_CRYPTO_CBC is not set
+# CONFIG_CRYPTO_CTR is not set
+# CONFIG_CRYPTO_CTS is not set
+CONFIG_CRYPTO_ECB=y
+# CONFIG_CRYPTO_LRW is not set
+# CONFIG_CRYPTO_PCBC is not set
+# CONFIG_CRYPTO_XTS is not set
+
+#
+# Hash modes
+#
+# CONFIG_CRYPTO_HMAC is not set
+# CONFIG_CRYPTO_XCBC is not set
+# CONFIG_CRYPTO_VMAC is not set
+
+#
+# Digest
+#
+# CONFIG_CRYPTO_CRC32C is not set
+# CONFIG_CRYPTO_GHASH is not set
+# CONFIG_CRYPTO_MD4 is not set
+# CONFIG_CRYPTO_MD5 is not set
+# CONFIG_CRYPTO_MICHAEL_MIC is not set
+# CONFIG_CRYPTO_RMD128 is not set
+# CONFIG_CRYPTO_RMD160 is not set
+# CONFIG_CRYPTO_RMD256 is not set
+# CONFIG_CRYPTO_RMD320 is not set
+# CONFIG_CRYPTO_SHA1 is not set
+# CONFIG_CRYPTO_SHA256 is not set
+# CONFIG_CRYPTO_SHA512 is not set
+# CONFIG_CRYPTO_TGR192 is not set
+# CONFIG_CRYPTO_WP512 is not set
+
+#
+# Ciphers
+#
+CONFIG_CRYPTO_AES=y
+# CONFIG_CRYPTO_ANUBIS is not set
+CONFIG_CRYPTO_ARC4=y
+# CONFIG_CRYPTO_BLOWFISH is not set
+# CONFIG_CRYPTO_CAMELLIA is not set
+# CONFIG_CRYPTO_CAST5 is not set
+# CONFIG_CRYPTO_CAST6 is not set
+# CONFIG_CRYPTO_DES is not set
+# CONFIG_CRYPTO_FCRYPT is not set
+# CONFIG_CRYPTO_KHAZAD is not set
+# CONFIG_CRYPTO_SALSA20 is not set
+# CONFIG_CRYPTO_SEED is not set
+# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_TEA is not set
+# CONFIG_CRYPTO_TWOFISH is not set
+
+#
+# Compression
+#
+# CONFIG_CRYPTO_DEFLATE is not set
+# CONFIG_CRYPTO_ZLIB is not set
+# CONFIG_CRYPTO_LZO is not set
+
+#
+# Random Number Generation
+#
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
+# CONFIG_CRYPTO_HW is not set
+# CONFIG_PPC_CLOCK is not set
+# CONFIG_VIRTUALIZATION is not set
diff --git a/arch/powerpc/include/asm/asm-offsets.h b/arch/powerpc/include/asm/asm-offsets.h
new file mode 100644
index 000000000000..d370ee36a182
--- /dev/null
+++ b/arch/powerpc/include/asm/asm-offsets.h
@@ -0,0 +1 @@
+#include <generated/asm-offsets.h>
diff --git a/arch/powerpc/include/asm/async_tx.h b/arch/powerpc/include/asm/async_tx.h
new file mode 100644
index 000000000000..8b2dc55d01ab
--- /dev/null
+++ b/arch/powerpc/include/asm/async_tx.h
@@ -0,0 +1,47 @@
+/*
+ * Copyright (C) 2008-2009 DENX Software Engineering.
+ *
+ * Author: Yuri Tikhonov <yur@emcraft.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the Free
+ * Software Foundation; either version 2 of the License, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc., 59
+ * Temple Place - Suite 330, Boston, MA  02111-1307, USA.
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called COPYING.
+ */
+#ifndef _ASM_POWERPC_ASYNC_TX_H_
+#define _ASM_POWERPC_ASYNC_TX_H_
+
+#if defined(CONFIG_440SPe) || defined(CONFIG_440SP)
+extern struct dma_chan *
+ppc440spe_async_tx_find_best_channel(enum dma_transaction_type cap,
+        struct page **dst_lst, int dst_cnt, struct page **src_lst,
+        int src_cnt, size_t src_sz);
+
+#define async_tx_find_channel(dep, cap, dst_lst, dst_cnt, src_lst, \
+                              src_cnt, src_sz) \
+        ppc440spe_async_tx_find_best_channel(cap, dst_lst, dst_cnt, src_lst, \
+                                             src_cnt, src_sz)
+#else
+
+#define async_tx_find_channel(dep, type, dst, dst_count, src, src_count, len) \
+        __async_tx_find_channel(dep, type)
+
+struct dma_chan *
+__async_tx_find_channel(struct async_submit_ctl *submit,
+                        enum dma_transaction_type tx_type);
+
+#endif
+
+#endif
diff --git a/arch/powerpc/include/asm/cpm.h b/arch/powerpc/include/asm/cpm.h
index 24d79e3abd8e..0835eb977ba9 100644
--- a/arch/powerpc/include/asm/cpm.h
+++ b/arch/powerpc/include/asm/cpm.h
@@ -3,8 +3,47 @@
 
 #include <linux/compiler.h>
 #include <linux/types.h>
+#include <linux/errno.h>
 #include <linux/of.h>
 
+/*
+ * USB Controller pram common to QE and CPM.
+ */
+struct usb_ctlr {
+        u8      usb_usmod;
+        u8      usb_usadr;
+        u8      usb_uscom;
+        u8      res1[1];
+        __be16  usb_usep[4];
+        u8      res2[4];
+        __be16  usb_usber;
+        u8      res3[2];
+        __be16  usb_usbmr;
+        u8      res4[1];
+        u8      usb_usbs;
+        /* Fields down below are QE-only */
+        __be16  usb_ussft;
+        u8      res5[2];
+        __be16  usb_usfrn;
+        u8      res6[0x22];
+} __attribute__ ((packed));
+
+/*
+ * Function code bits, usually generic to devices.
+ */
+#ifdef CONFIG_CPM1
+#define CPMFCR_GBL      ((u_char)0x00)  /* Flag doesn't exist in CPM1 */
+#define CPMFCR_TC2      ((u_char)0x00)  /* Flag doesn't exist in CPM1 */
+#define CPMFCR_DTB      ((u_char)0x00)  /* Flag doesn't exist in CPM1 */
+#define CPMFCR_BDB      ((u_char)0x00)  /* Flag doesn't exist in CPM1 */
+#else
+#define CPMFCR_GBL      ((u_char)0x20)  /* Set memory snooping */
+#define CPMFCR_TC2      ((u_char)0x04)  /* Transfer code 2 value */
+#define CPMFCR_DTB      ((u_char)0x02)  /* Use local bus for data when set */
+#define CPMFCR_BDB      ((u_char)0x01)  /* Use local bus for BD when set */
+#endif
+#define CPMFCR_EB       ((u_char)0x10)  /* Set big endian byte order */
+
 /* Opcodes common to CPM1 and CPM2
 */
 #define CPM_CR_INIT_TRX         ((ushort)0x0000)
@@ -93,13 +132,56 @@ typedef struct cpm_buf_desc {
 #define BD_I2C_START            (0x0400)
 
 int cpm_muram_init(void);
+
+#if defined(CONFIG_CPM) || defined(CONFIG_QUICC_ENGINE)
 unsigned long cpm_muram_alloc(unsigned long size, unsigned long align);
 int cpm_muram_free(unsigned long offset);
 unsigned long cpm_muram_alloc_fixed(unsigned long offset, unsigned long size);
 void __iomem *cpm_muram_addr(unsigned long offset);
 unsigned long cpm_muram_offset(void __iomem *addr);
 dma_addr_t cpm_muram_dma(void __iomem *addr);
+#else
+static inline unsigned long cpm_muram_alloc(unsigned long size,
+                                            unsigned long align)
+{
+        return -ENOSYS;
+}
+
+static inline int cpm_muram_free(unsigned long offset)
+{
+        return -ENOSYS;
+}
+
+static inline unsigned long cpm_muram_alloc_fixed(unsigned long offset,
+                                                  unsigned long size)
+{
+        return -ENOSYS;
+}
+
+static inline void __iomem *cpm_muram_addr(unsigned long offset)
+{
+        return NULL;
+}
+
+static inline unsigned long cpm_muram_offset(void __iomem *addr)
+{
+        return -ENOSYS;
+}
+
+static inline dma_addr_t cpm_muram_dma(void __iomem *addr)
+{
+        return 0;
+}
+#endif /* defined(CONFIG_CPM) || defined(CONFIG_QUICC_ENGINE) */
+
+#ifdef CONFIG_CPM
 int cpm_command(u32 command, u8 opcode);
+#else
+static inline int cpm_command(u32 command, u8 opcode)
+{
+        return -ENOSYS;
+}
+#endif /* CONFIG_CPM */
 
 int cpm2_gpiochip_add32(struct device_node *np);
 
diff --git a/arch/powerpc/include/asm/cpm1.h b/arch/powerpc/include/asm/cpm1.h
index 7685ffde8821..81b01192f440 100644
--- a/arch/powerpc/include/asm/cpm1.h
+++ b/arch/powerpc/include/asm/cpm1.h
@@ -478,51 +478,6 @@ typedef struct iic {
         char    res2[2];        /* Reserved */
 } iic_t;
 
-/* SPI parameter RAM.
-*/
-typedef struct spi {
-        ushort  spi_rbase;      /* Rx Buffer descriptor base address */
-        ushort  spi_tbase;      /* Tx Buffer descriptor base address */
-        u_char  spi_rfcr;       /* Rx function code */
-        u_char  spi_tfcr;       /* Tx function code */
-        ushort  spi_mrblr;      /* Max receive buffer length */
-        uint    spi_rstate;     /* Internal */
-        uint    spi_rdp;        /* Internal */
-        ushort  spi_rbptr;      /* Internal */
-        ushort  spi_rbc;        /* Internal */
-        uint    spi_rxtmp;      /* Internal */
-        uint    spi_tstate;     /* Internal */
-        uint    spi_tdp;        /* Internal */
-        ushort  spi_tbptr;      /* Internal */
-        ushort  spi_tbc;        /* Internal */
-        uint    spi_txtmp;      /* Internal */
-        uint    spi_res;
-        ushort  spi_rpbase;     /* Relocation pointer */
-        ushort  spi_res2;
-} spi_t;
-
-/* SPI Mode register.
-*/
-#define SPMODE_LOOP     ((ushort)0x4000)        /* Loopback */
-#define SPMODE_CI       ((ushort)0x2000)        /* Clock Invert */
-#define SPMODE_CP       ((ushort)0x1000)        /* Clock Phase */
-#define SPMODE_DIV16    ((ushort)0x0800)        /* BRG/16 mode */
-#define SPMODE_REV      ((ushort)0x0400)        /* Reversed Data */
-#define SPMODE_MSTR     ((ushort)0x0200)        /* SPI Master */
-#define SPMODE_EN       ((ushort)0x0100)        /* Enable */
-#define SPMODE_LENMSK   ((ushort)0x00f0)        /* character length */
-#define SPMODE_LEN4     ((ushort)0x0030)        /*  4 bits per char */
-#define SPMODE_LEN8     ((ushort)0x0070)        /*  8 bits per char */
-#define SPMODE_LEN16    ((ushort)0x00f0)        /* 16 bits per char */
-#define SPMODE_PMMSK    ((ushort)0x000f)        /* prescale modulus */
-
-/* SPIE fields */
-#define SPIE_MME        0x20
-#define SPIE_TXE        0x10
-#define SPIE_BSY        0x04
-#define SPIE_TXB        0x02
-#define SPIE_RXB        0x01
-
 /*
  * RISC Controller Configuration Register definitons
  */
diff --git a/arch/powerpc/include/asm/cpm2.h b/arch/powerpc/include/asm/cpm2.h
index 990ff191da8b..f42e9baf3a4e 100644
--- a/arch/powerpc/include/asm/cpm2.h
+++ b/arch/powerpc/include/asm/cpm2.h
@@ -124,14 +124,6 @@ static inline void cpm2_fastbrg(uint brg, uint rate, int div16)
         __cpm2_setbrg(brg, rate, CPM2_BRG_INT_CLK, div16, CPM_BRG_EXTC_INT);
 }
 
-/* Function code bits, usually generic to devices.
-*/
-#define CPMFCR_GBL      ((u_char)0x20)  /* Set memory snooping */
-#define CPMFCR_EB       ((u_char)0x10)  /* Set big endian byte order */
-#define CPMFCR_TC2      ((u_char)0x04)  /* Transfer code 2 value */
-#define CPMFCR_DTB      ((u_char)0x02)  /* Use local bus for data when set */
-#define CPMFCR_BDB      ((u_char)0x01)  /* Use local bus for BD when set */
-
 /* Parameter RAM offsets from the base.
 */
 #define PROFF_SCC1              ((uint)0x8000)
@@ -654,45 +646,6 @@ typedef struct iic {
         uint    iic_txtmp;      /* Internal */
 } iic_t;
 
-/* SPI parameter RAM.
-*/
-typedef struct spi {
-        ushort  spi_rbase;      /* Rx Buffer descriptor base address */
-        ushort  spi_tbase;      /* Tx Buffer descriptor base address */
-        u_char  spi_rfcr;       /* Rx function code */
-        u_char  spi_tfcr;       /* Tx function code */
-        ushort  spi_mrblr;      /* Max receive buffer length */
-        uint    spi_rstate;     /* Internal */
-        uint    spi_rdp;        /* Internal */
-        ushort  spi_rbptr;      /* Internal */
-        ushort  spi_rbc;        /* Internal */
-        uint    spi_rxtmp;      /* Internal */
-        uint    spi_tstate;     /* Internal */
-        uint    spi_tdp;        /* Internal */
-        ushort  spi_tbptr;      /* Internal */
-        ushort  spi_tbc;        /* Internal */
-        uint    spi_txtmp;      /* Internal */
-        uint    spi_res;        /* Tx temp. */
-        uint    spi_res1[4];    /* SDMA temp. */
-} spi_t;
-
-/* SPI Mode register.
-*/
-#define SPMODE_LOOP     ((ushort)0x4000)        /* Loopback */
-#define SPMODE_CI       ((ushort)0x2000)        /* Clock Invert */
-#define SPMODE_CP       ((ushort)0x1000)        /* Clock Phase */
-#define SPMODE_DIV16    ((ushort)0x0800)        /* BRG/16 mode */
-#define SPMODE_REV      ((ushort)0x0400)        /* Reversed Data */
-#define SPMODE_MSTR     ((ushort)0x0200)        /* SPI Master */
-#define SPMODE_EN       ((ushort)0x0100)        /* Enable */
-#define SPMODE_LENMSK   ((ushort)0x00f0)        /* character length */
-#define SPMODE_PMMSK    ((ushort)0x000f)        /* prescale modulus */
-
-#define SPMODE_LEN(x)   ((((x)-1)&0xF)<<4)
-#define SPMODE_PM(x)    ((x) &0xF)
-
-#define SPI_EB          ((u_char)0x10)          /* big endian byte order */
-
 /* IDMA parameter RAM
 */
 typedef struct idma {
diff --git a/arch/powerpc/include/asm/dcr-regs.h b/arch/powerpc/include/asm/dcr-regs.h
index 828e3aa1f2fc..380274de429f 100644
--- a/arch/powerpc/include/asm/dcr-regs.h
+++ b/arch/powerpc/include/asm/dcr-regs.h
@@ -157,4 +157,27 @@
 #define  L2C_SNP_SSR_32G        0x0000f000
 #define  L2C_SNP_ESR            0x00000800
 
+/*
+ * DCR register offsets for 440SP/440SPe I2O/DMA controller.
+ * The base address is configured in the device tree.
+ */
+#define DCRN_I2O0_IBAL          0x006
+#define DCRN_I2O0_IBAH          0x007
+#define I2O_REG_ENABLE          0x00000001      /* Enable I2O/DMA access */
+
+/* 440SP/440SPe Software Reset DCR */
+#define DCRN_SDR0_SRST          0x0200
+#define DCRN_SDR0_SRST_I2ODMA   (0x80000000 >> 15)      /* Reset I2O/DMA */
+
+/* 440SP/440SPe Memory Queue DCR offsets */
+#define DCRN_MQ0_XORBA          0x04
+#define DCRN_MQ0_CF2H           0x06
+#define DCRN_MQ0_CFBHL          0x0f
+#define DCRN_MQ0_BAUH           0x10
+
+/* HB/LL Paths Configuration Register */
+#define MQ0_CFBHL_TPLM          28
+#define MQ0_CFBHL_HBCL          23
+#define MQ0_CFBHL_POLY          15
+
 #endif /* __DCR_REGS_H__ */
diff --git a/arch/powerpc/include/asm/dma-mapping.h b/arch/powerpc/include/asm/dma-mapping.h
index e281daebddca..80a973bb9e71 100644
--- a/arch/powerpc/include/asm/dma-mapping.h
+++ b/arch/powerpc/include/asm/dma-mapping.h
@@ -197,7 +197,7 @@ static inline bool dma_capable(struct device *dev, dma_addr_t addr, size_t size)
         if (!dev->dma_mask)
                 return 0;
 
-        return addr + size <= *dev->dma_mask;
+        return addr + size - 1 <= *dev->dma_mask;
 }
 
 static inline dma_addr_t phys_to_dma(struct device *dev, phys_addr_t paddr)
diff --git a/arch/powerpc/include/asm/elf.h b/arch/powerpc/include/asm/elf.h
index 014a624f4c8e..17828ad411eb 100644
--- a/arch/powerpc/include/asm/elf.h
+++ b/arch/powerpc/include/asm/elf.h
@@ -170,7 +170,6 @@ typedef elf_fpreg_t elf_vsrreghalf_t32[ELF_NVSRHALFREG];
 #define elf_check_arch(x) ((x)->e_machine == ELF_ARCH)
 #define compat_elf_check_arch(x)        ((x)->e_machine == EM_PPC)
 
-#define USE_ELF_CORE_DUMP
 #define CORE_DUMP_USE_REGSET
 #define ELF_EXEC_PAGESIZE       PAGE_SIZE
 
diff --git a/arch/powerpc/include/asm/exception-64s.h b/arch/powerpc/include/asm/exception-64s.h
index a98653b26231..57c400071995 100644
--- a/arch/powerpc/include/asm/exception-64s.h
+++ b/arch/powerpc/include/asm/exception-64s.h
@@ -147,6 +147,7 @@
         .globl label##_pSeries;                         \
 label##_pSeries:                                        \
         HMT_MEDIUM;                                     \
+        DO_KVM  n;                                      \
         mtspr   SPRN_SPRG_SCRATCH0,r13;         /* save r13 */  \
         EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, label##_common)
 
@@ -170,6 +171,7 @@ label##_pSeries:					\
         .globl label##_pSeries;                                         \
 label##_pSeries:                                                        \
         HMT_MEDIUM;                                                     \
+        DO_KVM  n;                                                      \
         mtspr   SPRN_SPRG_SCRATCH0,r13; /* save r13 */                  \
         mfspr   r13,SPRN_SPRG_PACA;     /* get paca address into r13 */ \
         std     r9,PACA_EXGEN+EX_R9(r13);       /* save r9, r10 */      \
diff --git a/arch/powerpc/include/asm/fixmap.h b/arch/powerpc/include/asm/fixmap.h
index f1f4e23a84e9..5c2c0233175e 100644
--- a/arch/powerpc/include/asm/fixmap.h
+++ b/arch/powerpc/include/asm/fixmap.h
@@ -44,6 +44,9 @@
  */
 enum fixed_addresses {
         FIX_HOLE,
+        /* reserve the top 128K for early debugging purposes */
+        FIX_EARLY_DEBUG_TOP = FIX_HOLE,
+        FIX_EARLY_DEBUG_BASE = FIX_EARLY_DEBUG_TOP+((128*1024)/PAGE_SIZE)-1,
 #ifdef CONFIG_HIGHMEM
         FIX_KMAP_BEGIN, /* reserved pte's for temporary kernel mappings */
         FIX_KMAP_END = FIX_KMAP_BEGIN+(KM_TYPE_NR*NR_CPUS)-1,
diff --git a/arch/powerpc/include/asm/hugetlb.h b/arch/powerpc/include/asm/hugetlb.h
index b1dafb6a9743..5856a66ab404 100644
--- a/arch/powerpc/include/asm/hugetlb.h
+++ b/arch/powerpc/include/asm/hugetlb.h
@@ -3,6 +3,10 @@
 
 #include <asm/page.h>
 
+pte_t *huge_pte_offset_and_shift(struct mm_struct *mm,
+                                 unsigned long addr, unsigned *shift);
+
+void flush_dcache_icache_hugepage(struct page *page);
 
 int is_hugepage_only_range(struct mm_struct *mm, unsigned long addr,
                            unsigned long len);
@@ -11,12 +15,6 @@ void hugetlb_free_pgd_range(struct mmu_gather *tlb, unsigned long addr,
                             unsigned long end, unsigned long floor,
                             unsigned long ceiling);
 
-void set_huge_pte_at(struct mm_struct *mm, unsigned long addr,
-                     pte_t *ptep, pte_t pte);
-
-pte_t huge_ptep_get_and_clear(struct mm_struct *mm, unsigned long addr,
-                              pte_t *ptep);
-
 /*
  * The version of vma_mmu_pagesize() in arch/powerpc/mm/hugetlbpage.c needs
  * to override the version in mm/hugetlb.c
@@ -42,9 +40,26 @@ static inline void hugetlb_prefault_arch_hook(struct mm_struct *mm)
 {
 }
 
+
+static inline void set_huge_pte_at(struct mm_struct *mm, unsigned long addr,
+                                   pte_t *ptep, pte_t pte)
+{
+        set_pte_at(mm, addr, ptep, pte);
+}
+
+static inline pte_t huge_ptep_get_and_clear(struct mm_struct *mm,
+                                            unsigned long addr, pte_t *ptep)
+{
+        unsigned long old = pte_update(mm, addr, ptep, ~0UL, 1);
+        return __pte(old);
+}
+
 static inline void huge_ptep_clear_flush(struct vm_area_struct *vma,
                                          unsigned long addr, pte_t *ptep)
 {
+        pte_t pte;
+        pte = huge_ptep_get_and_clear(vma->vm_mm, addr, ptep);
+        flush_tlb_page(vma, addr);
 }
 
 static inline int huge_pte_none(pte_t pte)
diff --git a/arch/powerpc/include/asm/hvcall.h b/arch/powerpc/include/asm/hvcall.h
index c27caac47ad1..f0275818b95c 100644
--- a/arch/powerpc/include/asm/hvcall.h
+++ b/arch/powerpc/include/asm/hvcall.h
@@ -212,6 +212,19 @@
 #define H_QUERY_INT_STATE       0x1E4
 #define H_POLL_PENDING          0x1D8
 #define H_ILLAN_ATTRIBUTES      0x244
+#define H_MODIFY_HEA_QP         0x250
+#define H_QUERY_HEA_QP          0x254
+#define H_QUERY_HEA             0x258
+#define H_QUERY_HEA_PORT        0x25C
+#define H_MODIFY_HEA_PORT       0x260
+#define H_REG_BCMC              0x264
+#define H_DEREG_BCMC            0x268
+#define H_REGISTER_HEA_RPAGES   0x26C
+#define H_DISABLE_AND_GET_HEA   0x270
+#define H_GET_HEA_INFO          0x274
+#define H_ALLOC_HEA_RESOURCE    0x278
+#define H_ADD_CONN              0x284
+#define H_DEL_CONN              0x288
 #define H_JOIN                  0x298
 #define H_VASI_STATE            0x2A4
 #define H_ENABLE_CRQ            0x2B0
diff --git a/arch/powerpc/include/asm/hw_irq.h b/arch/powerpc/include/asm/hw_irq.h
index abbc2aaaced5..9f4c9d4f5803 100644
--- a/arch/powerpc/include/asm/hw_irq.h
+++ b/arch/powerpc/include/asm/hw_irq.h
@@ -64,11 +64,6 @@ extern void iseries_handle_interrupts(void);
                 get_paca()->hard_enabled = 0;   \
         } while(0)
 
-static inline int irqs_disabled_flags(unsigned long flags)
-{
-        return flags == 0;
-}
-
 #else
 
 #if defined(CONFIG_BOOKE)
diff --git a/arch/powerpc/include/asm/immap_cpm2.h b/arch/powerpc/include/asm/immap_cpm2.h
index d4f069bf0e57..7c64fda5357b 100644
--- a/arch/powerpc/include/asm/immap_cpm2.h
+++ b/arch/powerpc/include/asm/immap_cpm2.h
@@ -549,7 +549,7 @@ typedef struct comm_proc {
 
 /* USB Controller.
 */
-typedef struct usb_ctlr {
+typedef struct cpm_usb_ctlr {
         u8      usb_usmod;
         u8      usb_usadr;
         u8      usb_uscom;
diff --git a/arch/powerpc/include/asm/immap_qe.h b/arch/powerpc/include/asm/immap_qe.h
index c346d0bcd230..4e10f508570a 100644
--- a/arch/powerpc/include/asm/immap_qe.h
+++ b/arch/powerpc/include/asm/immap_qe.h
@@ -210,7 +210,7 @@ struct sir {
 } __attribute__ ((packed));
 
 /* USB Controller */
-struct usb_ctlr {
+struct qe_usb_ctlr {
         u8      usb_usmod;
         u8      usb_usadr;
         u8      usb_uscom;
@@ -229,7 +229,7 @@ struct usb_ctlr {
 } __attribute__ ((packed));
 
 /* MCC */
-struct mcc {
+struct qe_mcc {
         __be32  mcce;           /* MCC event register */
         __be32  mccm;           /* MCC mask register */
         __be32  mccf;           /* MCC configuration register */
@@ -431,9 +431,9 @@ struct qe_immap {
         struct qe_mux           qmx;            /* QE Multiplexer */
         struct qe_timers        qet;            /* QE Timers */
         struct spi              spi[0x2];       /* spi */
-        struct mcc              mcc;            /* mcc */
+        struct qe_mcc           mcc;            /* mcc */
         struct qe_brg           brg;            /* brg */
-        struct usb_ctlr         usb;            /* USB */
+        struct qe_usb_ctlr      usb;            /* USB */
         struct si1              si1;            /* SI */
         u8                      res11[0x800];
         struct sir              sir;            /* SI Routing Tables */
diff --git a/arch/powerpc/include/asm/irq.h b/arch/powerpc/include/asm/irq.h
index bbcd1aaf3dfd..e054baef1845 100644
--- a/arch/powerpc/include/asm/irq.h
+++ b/arch/powerpc/include/asm/irq.h
@@ -17,8 +17,6 @@
 #include <asm/atomic.h>
 
 
-#define get_irq_desc(irq) (&irq_desc[(irq)])
-
 /* Define a way to iterate across irqs. */
 #define for_each_irq(i) \
         for ((i) = 0; (i) < NR_IRQS; ++(i))
@@ -34,12 +32,15 @@ extern atomic_t ppc_n_lost_interrupts;
  */
 #define NO_IRQ_IGNORE           ((unsigned int)-1)
 
-/* Total number of virq in the platform (make it a CONFIG_* option ? */
-#define NR_IRQS         512
+/* Total number of virq in the platform */
+#define NR_IRQS         CONFIG_NR_IRQS
 
 /* Number of irqs reserved for the legacy controller */
 #define NUM_ISA_INTERRUPTS      16
 
+/* Same thing, used by the generic IRQ code */
+#define NR_IRQS_LEGACY          NUM_ISA_INTERRUPTS
+
 /* This type is the placeholder for a hardware interrupt number. It has to
  * be big enough to enclose whatever representation is used by a given
  * platform.
@@ -99,7 +100,7 @@ struct irq_host_ops {
          * interrupt controller has for that line)
          */
         int (*xlate)(struct irq_host *h, struct device_node *ctrler,
-                     u32 *intspec, unsigned int intsize,
+                     const u32 *intspec, unsigned int intsize,
                      irq_hw_number_t *out_hwirq, unsigned int *out_type);
 };
 
@@ -313,7 +314,7 @@ extern void irq_free_virt(unsigned int virq, unsigned int count);
  * of the of_irq_map_*() functions.
  */
 extern unsigned int irq_create_of_mapping(struct device_node *controller,
-                                          u32 *intspec, unsigned int intsize);
+                                          const u32 *intspec, unsigned int intsize);
 
 /**
  * irq_of_parse_and_map - Parse and Map an interrupt into linux virq space
diff --git a/arch/powerpc/include/asm/kvm.h b/arch/powerpc/include/asm/kvm.h
index bb2de6aa5ce0..81f3b0b5601e 100644
--- a/arch/powerpc/include/asm/kvm.h
+++ b/arch/powerpc/include/asm/kvm.h
@@ -46,6 +46,24 @@ struct kvm_regs {
 };
 
 struct kvm_sregs {
+        __u32 pvr;
+        union {
+                struct {
+                        __u64 sdr1;
+                        struct {
+                                struct {
+                                        __u64 slbe;
+                                        __u64 slbv;
+                                } slb[64];
+                        } ppc64;
+                        struct {
+                                __u32 sr[16];
+                                __u64 ibat[8]; 
+                                __u64 dbat[8]; 
+                        } ppc32;
+                } s;
+                __u8 pad[1020];
+        } u;
 };
 
 struct kvm_fpu {
diff --git a/arch/powerpc/include/asm/kvm_asm.h b/arch/powerpc/include/asm/kvm_asm.h
index 56bfae59837f..af2abe74f544 100644
--- a/arch/powerpc/include/asm/kvm_asm.h
+++ b/arch/powerpc/include/asm/kvm_asm.h
@@ -49,6 +49,46 @@
 #define BOOKE_INTERRUPT_SPE_FP_ROUND 34
 #define BOOKE_INTERRUPT_PERFORMANCE_MONITOR 35
 
+/* book3s */
+
+#define BOOK3S_INTERRUPT_SYSTEM_RESET   0x100
+#define BOOK3S_INTERRUPT_MACHINE_CHECK  0x200
+#define BOOK3S_INTERRUPT_DATA_STORAGE   0x300
+#define BOOK3S_INTERRUPT_DATA_SEGMENT   0x380
+#define BOOK3S_INTERRUPT_INST_STORAGE   0x400
+#define BOOK3S_INTERRUPT_INST_SEGMENT   0x480
+#define BOOK3S_INTERRUPT_EXTERNAL       0x500
+#define BOOK3S_INTERRUPT_ALIGNMENT      0x600
+#define BOOK3S_INTERRUPT_PROGRAM        0x700
+#define BOOK3S_INTERRUPT_FP_UNAVAIL     0x800
+#define BOOK3S_INTERRUPT_DECREMENTER    0x900
+#define BOOK3S_INTERRUPT_SYSCALL        0xc00
+#define BOOK3S_INTERRUPT_TRACE          0xd00
+#define BOOK3S_INTERRUPT_PERFMON        0xf00
+#define BOOK3S_INTERRUPT_ALTIVEC        0xf20
+#define BOOK3S_INTERRUPT_VSX            0xf40
+
+#define BOOK3S_IRQPRIO_SYSTEM_RESET             0
+#define BOOK3S_IRQPRIO_DATA_SEGMENT             1
+#define BOOK3S_IRQPRIO_INST_SEGMENT             2
+#define BOOK3S_IRQPRIO_DATA_STORAGE             3
+#define BOOK3S_IRQPRIO_INST_STORAGE             4
+#define BOOK3S_IRQPRIO_ALIGNMENT                5
+#define BOOK3S_IRQPRIO_PROGRAM                  6
+#define BOOK3S_IRQPRIO_FP_UNAVAIL               7
+#define BOOK3S_IRQPRIO_ALTIVEC                  8
+#define BOOK3S_IRQPRIO_VSX                      9
+#define BOOK3S_IRQPRIO_SYSCALL                  10
+#define BOOK3S_IRQPRIO_MACHINE_CHECK            11
+#define BOOK3S_IRQPRIO_DEBUG                    12
+#define BOOK3S_IRQPRIO_EXTERNAL                 13
+#define BOOK3S_IRQPRIO_DECREMENTER              14
+#define BOOK3S_IRQPRIO_PERFORMANCE_MONITOR      15
+#define BOOK3S_IRQPRIO_MAX                      16
+
+#define BOOK3S_HFLAG_DCBZ32                     0x1
+#define BOOK3S_HFLAG_SLB                        0x2
+
 #define RESUME_FLAG_NV          (1<<0)  /* Reload guest nonvolatile state? */
 #define RESUME_FLAG_HOST        (1<<1)  /* Resume host? */
 
diff --git a/arch/powerpc/include/asm/kvm_book3s.h b/arch/powerpc/include/asm/kvm_book3s.h
new file mode 100644
index 000000000000..74b7369770d0
--- /dev/null
+++ b/arch/powerpc/include/asm/kvm_book3s.h
@@ -0,0 +1,139 @@
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ *
+ * Copyright SUSE Linux Products GmbH 2009
+ *
+ * Authors: Alexander Graf <agraf@suse.de>
+ */
+
+#ifndef __ASM_KVM_BOOK3S_H__
+#define __ASM_KVM_BOOK3S_H__
+
+#include <linux/types.h>
+#include <linux/kvm_host.h>
+#include <asm/kvm_ppc.h>
+
+struct kvmppc_slb {
+        u64 esid;
+        u64 vsid;
+        u64 orige;
+        u64 origv;
+        bool valid;
+        bool Ks;
+        bool Kp;
+        bool nx;
+        bool large;
+        bool class;
+};
+
+struct kvmppc_sr {
+        u32 raw;
+        u32 vsid;
+        bool Ks;
+        bool Kp;
+        bool nx;
+};
+
+struct kvmppc_bat {
+        u64 raw;
+        u32 bepi;
+        u32 bepi_mask;
+        bool vs;
+        bool vp;
+        u32 brpn;
+        u8 wimg;
+        u8 pp;
+};
+
+struct kvmppc_sid_map {
+        u64 guest_vsid;
+        u64 guest_esid;
+        u64 host_vsid;
+        bool valid;
+};
+
+#define SID_MAP_BITS    9
+#define SID_MAP_NUM     (1 << SID_MAP_BITS)
+#define SID_MAP_MASK    (SID_MAP_NUM - 1)
+
+struct kvmppc_vcpu_book3s {
+        struct kvm_vcpu vcpu;
+        struct kvmppc_sid_map sid_map[SID_MAP_NUM];
+        struct kvmppc_slb slb[64];
+        struct {
+                u64 esid;
+                u64 vsid;
+        } slb_shadow[64];
+        u8 slb_shadow_max;
+        struct kvmppc_sr sr[16];
+        struct kvmppc_bat ibat[8];
+        struct kvmppc_bat dbat[8];
+        u64 hid[6];
+        int slb_nr;
+        u64 sdr1;
+        u64 dsisr;
+        u64 hior;
+        u64 msr_mask;
+        u64 vsid_first;
+        u64 vsid_next;
+        u64 vsid_max;
+        int context_id;
+};
+
+#define CONTEXT_HOST            0
+#define CONTEXT_GUEST           1
+#define CONTEXT_GUEST_END       2
+
+#define VSID_REAL       0xfffffffffff00000
+#define VSID_REAL_DR    0xffffffffffe00000
+#define VSID_REAL_IR    0xffffffffffd00000
+#define VSID_BAT        0xffffffffffc00000
+#define VSID_PR         0x8000000000000000
+
+extern void kvmppc_mmu_pte_flush(struct kvm_vcpu *vcpu, u64 ea, u64 ea_mask);
+extern void kvmppc_mmu_pte_vflush(struct kvm_vcpu *vcpu, u64 vp, u64 vp_mask);
+extern void kvmppc_mmu_pte_pflush(struct kvm_vcpu *vcpu, u64 pa_start, u64 pa_end);
+extern void kvmppc_set_msr(struct kvm_vcpu *vcpu, u64 new_msr);
+extern void kvmppc_mmu_book3s_64_init(struct kvm_vcpu *vcpu);
+extern void kvmppc_mmu_book3s_32_init(struct kvm_vcpu *vcpu);
+extern int kvmppc_mmu_map_page(struct kvm_vcpu *vcpu, struct kvmppc_pte *pte);
+extern int kvmppc_mmu_map_segment(struct kvm_vcpu *vcpu, ulong eaddr);
+extern void kvmppc_mmu_flush_segments(struct kvm_vcpu *vcpu);
+extern struct kvmppc_pte *kvmppc_mmu_find_pte(struct kvm_vcpu *vcpu, u64 ea, bool data);
+extern int kvmppc_ld(struct kvm_vcpu *vcpu, ulong eaddr, int size, void *ptr, bool data);
+extern int kvmppc_st(struct kvm_vcpu *vcpu, ulong eaddr, int size, void *ptr);
+extern void kvmppc_book3s_queue_irqprio(struct kvm_vcpu *vcpu, unsigned int vec);
+extern void kvmppc_set_bat(struct kvm_vcpu *vcpu, struct kvmppc_bat *bat,
+                           bool upper, u32 val);
+
+extern u32 kvmppc_trampoline_lowmem;
+extern u32 kvmppc_trampoline_enter;
+
+static inline struct kvmppc_vcpu_book3s *to_book3s(struct kvm_vcpu *vcpu)
+{
+        return container_of(vcpu, struct kvmppc_vcpu_book3s, vcpu);
+}
+
+static inline ulong dsisr(void)
+{
+        ulong r;
+        asm ( "mfdsisr %0 " : "=r" (r) );
+        return r;
+}
+
+extern void kvm_return_point(void);
+
+#define INS_DCBZ                        0x7c0007ec
+
+#endif /* __ASM_KVM_BOOK3S_H__ */
diff --git a/arch/powerpc/include/asm/kvm_book3s_64_asm.h b/arch/powerpc/include/asm/kvm_book3s_64_asm.h
new file mode 100644
index 000000000000..2e06ee8184ef
--- /dev/null
+++ b/arch/powerpc/include/asm/kvm_book3s_64_asm.h
@@ -0,0 +1,58 @@
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ *
+ * Copyright SUSE Linux Products GmbH 2009
+ *
+ * Authors: Alexander Graf <agraf@suse.de>
+ */
+
+#ifndef __ASM_KVM_BOOK3S_ASM_H__
+#define __ASM_KVM_BOOK3S_ASM_H__
+
+#ifdef CONFIG_KVM_BOOK3S_64_HANDLER
+
+#include <asm/kvm_asm.h>
+
+.macro DO_KVM intno
+        .if (\intno == BOOK3S_INTERRUPT_SYSTEM_RESET) || \
+            (\intno == BOOK3S_INTERRUPT_MACHINE_CHECK) || \
+            (\intno == BOOK3S_INTERRUPT_DATA_STORAGE) || \
+            (\intno == BOOK3S_INTERRUPT_INST_STORAGE) || \
+            (\intno == BOOK3S_INTERRUPT_DATA_SEGMENT) || \
+            (\intno == BOOK3S_INTERRUPT_INST_SEGMENT) || \
+            (\intno == BOOK3S_INTERRUPT_EXTERNAL) || \
+            (\intno == BOOK3S_INTERRUPT_ALIGNMENT) || \
+            (\intno == BOOK3S_INTERRUPT_PROGRAM) || \
+            (\intno == BOOK3S_INTERRUPT_FP_UNAVAIL) || \
+            (\intno == BOOK3S_INTERRUPT_DECREMENTER) || \
+            (\intno == BOOK3S_INTERRUPT_SYSCALL) || \
+            (\intno == BOOK3S_INTERRUPT_TRACE) || \
+            (\intno == BOOK3S_INTERRUPT_PERFMON) || \
+            (\intno == BOOK3S_INTERRUPT_ALTIVEC) || \
+            (\intno == BOOK3S_INTERRUPT_VSX)
+
+        b       kvmppc_trampoline_\intno
+kvmppc_resume_\intno:
+
+        .endif
+.endm
+
+#else
+
+.macro DO_KVM intno
+.endm
+
+#endif /* CONFIG_KVM_BOOK3S_64_HANDLER */
+
+#endif /* __ASM_KVM_BOOK3S_ASM_H__ */
diff --git a/arch/powerpc/include/asm/kvm_host.h b/arch/powerpc/include/asm/kvm_host.h
index c9c930ed11d7..1201f62d0d73 100644
--- a/arch/powerpc/include/asm/kvm_host.h
+++ b/arch/powerpc/include/asm/kvm_host.h
@@ -21,7 +21,8 @@
 #define __POWERPC_KVM_HOST_H__
 
 #include <linux/mutex.h>
-#include <linux/timer.h>
+#include <linux/hrtimer.h>
+#include <linux/interrupt.h>
 #include <linux/types.h>
 #include <linux/kvm_types.h>
 #include <asm/kvm_asm.h>
@@ -37,6 +38,8 @@
 #define KVM_NR_PAGE_SIZES       1
 #define KVM_PAGES_PER_HPAGE(x)  (1UL<<31)
 
+#define HPTEG_CACHE_NUM 1024
+
 struct kvm;
 struct kvm_run;
 struct kvm_vcpu;
@@ -63,6 +66,17 @@ struct kvm_vcpu_stat {
         u32 dec_exits;
         u32 ext_intr_exits;
         u32 halt_wakeup;
+#ifdef CONFIG_PPC64
+        u32 pf_storage;
+        u32 pf_instruc;
+        u32 sp_storage;
+        u32 sp_instruc;
+        u32 queue_intr;
+        u32 ld;
+        u32 ld_slow;
+        u32 st;
+        u32 st_slow;
+#endif
 };
 
 enum kvm_exit_types {
@@ -109,9 +123,53 @@ struct kvmppc_exit_timing {
 struct kvm_arch {
 };
 
+struct kvmppc_pte {
+        u64 eaddr;
+        u64 vpage;
+        u64 raddr;
+        bool may_read;
+        bool may_write;
+        bool may_execute;
+};
+
+struct kvmppc_mmu {
+        /* book3s_64 only */
+        void (*slbmte)(struct kvm_vcpu *vcpu, u64 rb, u64 rs);
+        u64  (*slbmfee)(struct kvm_vcpu *vcpu, u64 slb_nr);
+        u64  (*slbmfev)(struct kvm_vcpu *vcpu, u64 slb_nr);
+        void (*slbie)(struct kvm_vcpu *vcpu, u64 slb_nr);
+        void (*slbia)(struct kvm_vcpu *vcpu);
+        /* book3s */
+        void (*mtsrin)(struct kvm_vcpu *vcpu, u32 srnum, ulong value);
+        u32  (*mfsrin)(struct kvm_vcpu *vcpu, u32 srnum);
+        int  (*xlate)(struct kvm_vcpu *vcpu, gva_t eaddr, struct kvmppc_pte *pte, bool data);
+        void (*reset_msr)(struct kvm_vcpu *vcpu);
+        void (*tlbie)(struct kvm_vcpu *vcpu, ulong addr, bool large);
+        int  (*esid_to_vsid)(struct kvm_vcpu *vcpu, u64 esid, u64 *vsid);
+        u64  (*ea_to_vp)(struct kvm_vcpu *vcpu, gva_t eaddr, bool data);
+        bool (*is_dcbz32)(struct kvm_vcpu *vcpu);
+};
+
+struct hpte_cache {
+        u64 host_va;
+        u64 pfn;
+        ulong slot;
+        struct kvmppc_pte pte;
+};
+
 struct kvm_vcpu_arch {
-        u32 host_stack;
+        ulong host_stack;
         u32 host_pid;
+#ifdef CONFIG_PPC64
+        ulong host_msr;
+        ulong host_r2;
+        void *host_retip;
+        ulong trampoline_lowmem;
+        ulong trampoline_enter;
+        ulong highmem_handler;
+        ulong host_paca_phys;
+        struct kvmppc_mmu mmu;
+#endif
 
         u64 fpr[32];
         ulong gpr[32];
@@ -123,6 +181,10 @@ struct kvm_vcpu_arch {
         ulong xer;
 
         ulong msr;
+#ifdef CONFIG_PPC64
+        ulong shadow_msr;
+        ulong hflags;
+#endif
         u32 mmucr;
         ulong sprg0;
         ulong sprg1;
@@ -149,6 +211,7 @@ struct kvm_vcpu_arch {
         u32 ivor[64];
         ulong ivpr;
         u32 pir;
+        u32 pvr;
 
         u32 shadow_pid;
         u32 pid;
@@ -174,6 +237,9 @@ struct kvm_vcpu_arch {
 #endif
 
         u32 last_inst;
+#ifdef CONFIG_PPC64
+        ulong fault_dsisr;
+#endif
         ulong fault_dear;
         ulong fault_esr;
         gpa_t paddr_accessed;
@@ -185,8 +251,15 @@ struct kvm_vcpu_arch {
 
         u32 cpr0_cfgaddr; /* holds the last set cpr0_cfgaddr */
 
-        struct timer_list dec_timer;
+        struct hrtimer dec_timer;
+        struct tasklet_struct tasklet;
+        u64 dec_jiffies;
         unsigned long pending_exceptions;
+
+#ifdef CONFIG_PPC64
+        struct hpte_cache hpte_cache[HPTEG_CACHE_NUM];
+        int hpte_cache_offset;
+#endif
 };
 
 #endif /* __POWERPC_KVM_HOST_H__ */
diff --git a/arch/powerpc/include/asm/kvm_ppc.h b/arch/powerpc/include/asm/kvm_ppc.h
index 2c6ee349df5e..269ee46ab028 100644
--- a/arch/powerpc/include/asm/kvm_ppc.h
+++ b/arch/powerpc/include/asm/kvm_ppc.h
@@ -39,6 +39,7 @@ enum emulation_result {
 extern int __kvmppc_vcpu_run(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu);
 extern char kvmppc_handlers_start[];
 extern unsigned long kvmppc_handler_len;
+extern void kvmppc_handler_highmem(void);
 
 extern void kvmppc_dump_vcpu(struct kvm_vcpu *vcpu);
 extern int kvmppc_handle_load(struct kvm_run *run, struct kvm_vcpu *vcpu,
diff --git a/arch/powerpc/include/asm/lppaca.h b/arch/powerpc/include/asm/lppaca.h
index f78f65c38f05..14b592dfb4e8 100644
--- a/arch/powerpc/include/asm/lppaca.h
+++ b/arch/powerpc/include/asm/lppaca.h
@@ -100,7 +100,14 @@ struct lppaca {
         // Used to pass parms from the OS to PLIC for SetAsrAndRfid
         u64     saved_gpr3;             // Saved GPR3                   x20-x27
         u64     saved_gpr4;             // Saved GPR4                   x28-x2F
-        u64     saved_gpr5;             // Saved GPR5                   x30-x37
+        union {
+                u64     saved_gpr5;     /* Saved GPR5               x30-x37 */
+                struct {
+                        u8      cede_latency_hint;  /*                  x30 */
+                        u8      reserved[7];        /*              x31-x36 */
+                } fields;
+        } gpr5_dword;
+
 
         u8      dtl_enable_mask;        // Dispatch Trace Log mask      x38-x38
         u8      donate_dedicated_cpu;   // Donate dedicated CPU cycles  x39-x39
diff --git a/arch/powerpc/include/asm/machdep.h b/arch/powerpc/include/asm/machdep.h
index 9efa2be78331..9f0fc9e6ce0d 100644
--- a/arch/powerpc/include/asm/machdep.h
+++ b/arch/powerpc/include/asm/machdep.h
@@ -266,6 +266,11 @@ struct machdep_calls {
         void (*suspend_disable_irqs)(void);
         void (*suspend_enable_irqs)(void);
 #endif
+
+#ifdef CONFIG_ARCH_CPU_PROBE_RELEASE
+        ssize_t (*cpu_probe)(const char *, size_t);
+        ssize_t (*cpu_release)(const char *, size_t);
+#endif
 };
 
 extern void e500_idle(void);
diff --git a/arch/powerpc/include/asm/macio.h b/arch/powerpc/include/asm/macio.h
index 079c06eae446..a062c57696d0 100644
--- a/arch/powerpc/include/asm/macio.h
+++ b/arch/powerpc/include/asm/macio.h
@@ -39,6 +39,7 @@ struct macio_dev
         struct macio_bus        *bus;           /* macio bus this device is on */
         struct macio_dev        *media_bay;     /* Device is part of a media bay */
         struct of_device        ofdev;
+        struct device_dma_parameters dma_parms; /* ide needs that */
         int                     n_resources;
         struct resource         resource[MACIO_DEV_COUNT_RESOURCES];
         int                     n_interrupts;
@@ -78,6 +79,8 @@ static inline unsigned long macio_resource_len(struct macio_dev *dev, int resour
         return res->end - res->start + 1;
 }
 
+extern int macio_enable_devres(struct macio_dev *dev);
+
 extern int macio_request_resource(struct macio_dev *dev, int resource_no, const char *name);
 extern void macio_release_resource(struct macio_dev *dev, int resource_no);
 extern int macio_request_resources(struct macio_dev *dev, const char *name);
@@ -131,6 +134,9 @@ struct macio_driver
         int     (*resume)(struct macio_dev* dev);
         int     (*shutdown)(struct macio_dev* dev);
 
+#ifdef CONFIG_PMAC_MEDIABAY
+        void    (*mediabay_event)(struct macio_dev* dev, int mb_state);
+#endif
         struct device_driver    driver;
 };
 #define to_macio_driver(drv) container_of(drv,struct macio_driver, driver)
diff --git a/arch/powerpc/include/asm/mediabay.h b/arch/powerpc/include/asm/mediabay.h
index b2efb3325808..11037a4133ee 100644
--- a/arch/powerpc/include/asm/mediabay.h
+++ b/arch/powerpc/include/asm/mediabay.h
@@ -17,26 +17,31 @@
 #define MB_POWER        6       /* media bay contains a Power device (???) */
 #define MB_NO           7       /* media bay contains nothing */
 
-/* Number of bays in the machine or 0 */
-extern int media_bay_count;
+struct macio_dev;
 
-#ifdef CONFIG_BLK_DEV_IDE_PMAC
-#include <linux/ide.h>
+#ifdef CONFIG_PMAC_MEDIABAY
 
-int check_media_bay_by_base(unsigned long base, int what);
-/* called by IDE PMAC host driver to register IDE controller for media bay */
-int media_bay_set_ide_infos(struct device_node *which_bay, unsigned long base,
-                            int irq, ide_hwif_t *hwif);
+/* Check the content type of the bay, returns MB_NO if the bay is still
+ * transitionning
+ */
+extern int check_media_bay(struct macio_dev *bay);
 
-int check_media_bay(struct device_node *which_bay, int what);
+/* The ATA driver uses the calls below to temporarily hold on the
+ * media bay callbacks while initializing the interface
+ */
+extern void lock_media_bay(struct macio_dev *bay);
+extern void unlock_media_bay(struct macio_dev *bay);
 
 #else
 
-static inline int check_media_bay(struct device_node *which_bay, int what)
+static inline int check_media_bay(struct macio_dev *bay)
 {
-        return -ENODEV;
+        return MB_NO;
 }
 
+static inline void lock_media_bay(struct macio_dev *bay) { }
+static inline void unlock_media_bay(struct macio_dev *bay) { }
+
 #endif
 
 #endif /* __KERNEL__ */
diff --git a/arch/powerpc/include/asm/mmu-hash64.h b/arch/powerpc/include/asm/mmu-hash64.h
index bebe31c2e907..2102b214a87c 100644
--- a/arch/powerpc/include/asm/mmu-hash64.h
+++ b/arch/powerpc/include/asm/mmu-hash64.h
@@ -173,14 +173,6 @@ extern unsigned long tce_alloc_start, tce_alloc_end;
  */
 extern int mmu_ci_restrictions;
 
-#ifdef CONFIG_HUGETLB_PAGE
-/*
- * The page size indexes of the huge pages for use by hugetlbfs
- */
-extern unsigned int mmu_huge_psizes[MMU_PAGE_COUNT];
-
-#endif /* CONFIG_HUGETLB_PAGE */
-
 /*
  * This function sets the AVPN and L fields of the HPTE  appropriately
  * for the page size
@@ -253,10 +245,11 @@ extern int __hash_page_64K(unsigned long ea, unsigned long access,
                            unsigned long vsid, pte_t *ptep, unsigned long trap,
                            unsigned int local, int ssize);
 struct mm_struct;
+unsigned int hash_page_do_lazy_icache(unsigned int pp, pte_t pte, int trap);
 extern int hash_page(unsigned long ea, unsigned long access, unsigned long trap);
-extern int hash_huge_page(struct mm_struct *mm, unsigned long access,
-                          unsigned long ea, unsigned long vsid, int local,
-                          unsigned long trap);
+int __hash_page_huge(unsigned long ea, unsigned long access, unsigned long vsid,
+                     pte_t *ptep, unsigned long trap, int local, int ssize,
+                     unsigned int shift, unsigned int mmu_psize);
 
 extern int htab_bolt_mapping(unsigned long vstart, unsigned long vend,
                              unsigned long pstart, unsigned long prot,
@@ -380,6 +373,38 @@ extern void slb_set_size(u16 size);
 
 #ifndef __ASSEMBLY__
 
+#ifdef CONFIG_PPC_SUBPAGE_PROT
+/*
+ * For the sub-page protection option, we extend the PGD with one of
+ * these.  Basically we have a 3-level tree, with the top level being
+ * the protptrs array.  To optimize speed and memory consumption when
+ * only addresses < 4GB are being protected, pointers to the first
+ * four pages of sub-page protection words are stored in the low_prot
+ * array.
+ * Each page of sub-page protection words protects 1GB (4 bytes
+ * protects 64k).  For the 3-level tree, each page of pointers then
+ * protects 8TB.
+ */
+struct subpage_prot_table {
+        unsigned long maxaddr;  /* only addresses < this are protected */
+        unsigned int **protptrs[2];
+        unsigned int *low_prot[4];
+};
+
+#define SBP_L1_BITS             (PAGE_SHIFT - 2)
+#define SBP_L2_BITS             (PAGE_SHIFT - 3)
+#define SBP_L1_COUNT            (1 << SBP_L1_BITS)
+#define SBP_L2_COUNT            (1 << SBP_L2_BITS)
+#define SBP_L2_SHIFT            (PAGE_SHIFT + SBP_L1_BITS)
+#define SBP_L3_SHIFT            (SBP_L2_SHIFT + SBP_L2_BITS)
+
+extern void subpage_prot_free(struct mm_struct *mm);
+extern void subpage_prot_init_new_context(struct mm_struct *mm);
+#else
+static inline void subpage_prot_free(struct mm_struct *mm) {}
+static inline void subpage_prot_init_new_context(struct mm_struct *mm) { }
+#endif /* CONFIG_PPC_SUBPAGE_PROT */
+
 typedef unsigned long mm_context_id_t;
 
 typedef struct {
@@ -393,6 +418,9 @@ typedef struct {
         u16 sllp;               /* SLB page size encoding */
 #endif
         unsigned long vdso_base;
+#ifdef CONFIG_PPC_SUBPAGE_PROT
+        struct subpage_prot_table spt;
+#endif /* CONFIG_PPC_SUBPAGE_PROT */
 } mm_context_t;
 
 
diff --git a/arch/powerpc/include/asm/mmu_context.h b/arch/powerpc/include/asm/mmu_context.h
index b34e94d94435..26383e0778aa 100644
--- a/arch/powerpc/include/asm/mmu_context.h
+++ b/arch/powerpc/include/asm/mmu_context.h
@@ -23,6 +23,8 @@ extern void switch_slb(struct task_struct *tsk, struct mm_struct *mm);
 extern void set_context(unsigned long id, pgd_t *pgd);
 
 #ifdef CONFIG_PPC_BOOK3S_64
+extern int __init_new_context(void);
+extern void __destroy_context(int context_id);
 static inline void mmu_context_init(void) { }
 #else
 extern void mmu_context_init(void);
diff --git a/arch/powerpc/include/asm/module.h b/arch/powerpc/include/asm/module.h
index 08454880a2c0..0192a4ee2bc2 100644
--- a/arch/powerpc/include/asm/module.h
+++ b/arch/powerpc/include/asm/module.h
@@ -87,5 +87,10 @@ struct exception_table_entry;
 void sort_ex_table(struct exception_table_entry *start,
                    struct exception_table_entry *finish);
 
+#ifdef CONFIG_MODVERSIONS
+#define ARCH_RELOCATES_KCRCTAB
+
+extern const unsigned long reloc_start[];
+#endif
 #endif /* __KERNEL__ */
 #endif  /* _ASM_POWERPC_MODULE_H */
diff --git a/arch/powerpc/include/asm/mpc52xx.h b/arch/powerpc/include/asm/mpc52xx.h
index 1b4f697abbdd..b664ce79a172 100644
--- a/arch/powerpc/include/asm/mpc52xx.h
+++ b/arch/powerpc/include/asm/mpc52xx.h
@@ -276,6 +276,53 @@ extern int mpc52xx_set_psc_clkdiv(int psc_id, int clkdiv);
 extern unsigned int mpc52xx_get_xtal_freq(struct device_node *node);
 extern void mpc52xx_restart(char *cmd);
 
+/* mpc52xx_gpt.c */
+struct mpc52xx_gpt_priv;
+extern struct mpc52xx_gpt_priv *mpc52xx_gpt_from_irq(int irq);
+extern int mpc52xx_gpt_start_timer(struct mpc52xx_gpt_priv *gpt, u64 period,
+                            int continuous);
+extern u64 mpc52xx_gpt_timer_period(struct mpc52xx_gpt_priv *gpt);
+extern int mpc52xx_gpt_stop_timer(struct mpc52xx_gpt_priv *gpt);
+
+/* mpc52xx_lpbfifo.c */
+#define MPC52XX_LPBFIFO_FLAG_READ               (0)
+#define MPC52XX_LPBFIFO_FLAG_WRITE              (1<<0)
+#define MPC52XX_LPBFIFO_FLAG_NO_INCREMENT       (1<<1)
+#define MPC52XX_LPBFIFO_FLAG_NO_DMA             (1<<2)
+#define MPC52XX_LPBFIFO_FLAG_POLL_DMA           (1<<3)
+
+struct mpc52xx_lpbfifo_request {
+        struct list_head list;
+
+        /* localplus bus address */
+        unsigned int cs;
+        size_t offset;
+
+        /* Memory address */
+        void *data;
+        phys_addr_t data_phys;
+
+        /* Details of transfer */
+        size_t size;
+        size_t pos;     /* current position of transfer */
+        int flags;
+
+        /* What to do when finished */
+        void (*callback)(struct mpc52xx_lpbfifo_request *);
+
+        void *priv;             /* Driver private data */
+
+        /* statistics */
+        int irq_count;
+        int irq_ticks;
+        u8 last_byte;
+        int buffer_not_done_cnt;
+};
+
+extern int mpc52xx_lpbfifo_submit(struct mpc52xx_lpbfifo_request *req);
+extern void mpc52xx_lpbfifo_abort(struct mpc52xx_lpbfifo_request *req);
+extern void mpc52xx_lpbfifo_poll(void);
+
 /* mpc52xx_pic.c */
 extern void mpc52xx_init_irq(void);
 extern unsigned int mpc52xx_get_irq(void);
diff --git a/arch/powerpc/include/asm/nvram.h b/arch/powerpc/include/asm/nvram.h
index 6c587eddee59..850b72f27445 100644
--- a/arch/powerpc/include/asm/nvram.h
+++ b/arch/powerpc/include/asm/nvram.h
@@ -73,7 +73,6 @@ extern int nvram_write_error_log(char * buff, int length,
 extern int nvram_read_error_log(char * buff, int length,
                                          unsigned int * err_type, unsigned int *err_seq);
 extern int nvram_clear_error_log(void);
-extern struct nvram_partition *nvram_find_partition(int sig, const char *name);
 
 extern int pSeries_nvram_init(void);
 
diff --git a/arch/powerpc/include/asm/pSeries_reconfig.h b/arch/powerpc/include/asm/pSeries_reconfig.h
index e482e5352e69..d4b4bfa26fb3 100644
--- a/arch/powerpc/include/asm/pSeries_reconfig.h
+++ b/arch/powerpc/include/asm/pSeries_reconfig.h
@@ -17,6 +17,7 @@
 #ifdef CONFIG_PPC_PSERIES
 extern int pSeries_reconfig_notifier_register(struct notifier_block *);
 extern void pSeries_reconfig_notifier_unregister(struct notifier_block *);
+extern struct blocking_notifier_head pSeries_reconfig_chain;
 #else /* !CONFIG_PPC_PSERIES */
 static inline int pSeries_reconfig_notifier_register(struct notifier_block *nb)
 {
diff --git a/arch/powerpc/include/asm/paca.h b/arch/powerpc/include/asm/paca.h
index 7d8514ceceae..5e9b4ef71415 100644
--- a/arch/powerpc/include/asm/paca.h
+++ b/arch/powerpc/include/asm/paca.h
@@ -129,6 +129,15 @@ struct paca_struct {
         u64 system_time;                /* accumulated system TB ticks */
         u64 startpurr;                  /* PURR/TB value snapshot */
         u64 startspurr;                 /* SPURR value snapshot */
+
+#ifdef CONFIG_KVM_BOOK3S_64_HANDLER
+        struct  {
+                u64     esid;
+                u64     vsid;
+        } kvm_slb[64];                  /* guest SLB */
+        u8 kvm_slb_max;                 /* highest used guest slb entry */
+        u8 kvm_in_guest;                /* are we inside the guest? */
+#endif
 };
 
 extern struct paca_struct paca[];
diff --git a/arch/powerpc/include/asm/page.h b/arch/powerpc/include/asm/page.h
index ff24254990e1..e96d52a516ba 100644
--- a/arch/powerpc/include/asm/page.h
+++ b/arch/powerpc/include/asm/page.h
@@ -229,6 +229,20 @@ typedef unsigned long pgprot_t;
 
 #endif
 
+typedef struct { signed long pd; } hugepd_t;
+#define HUGEPD_SHIFT_MASK     0x3f
+
+#ifdef CONFIG_HUGETLB_PAGE
+static inline int hugepd_ok(hugepd_t hpd)
+{
+        return (hpd.pd > 0);
+}
+
+#define is_hugepd(pdep)               (hugepd_ok(*((hugepd_t *)(pdep))))
+#else /* CONFIG_HUGETLB_PAGE */
+#define is_hugepd(pdep)                 0
+#endif /* CONFIG_HUGETLB_PAGE */
+
 struct page;
 extern void clear_user_page(void *page, unsigned long vaddr, struct page *pg);
 extern void copy_user_page(void *to, void *from, unsigned long vaddr,
diff --git a/arch/powerpc/include/asm/page_64.h b/arch/powerpc/include/asm/page_64.h
index 3f17b83f55a1..bfc4e027e2ad 100644
--- a/arch/powerpc/include/asm/page_64.h
+++ b/arch/powerpc/include/asm/page_64.h
@@ -90,7 +90,7 @@ extern unsigned int HPAGE_SHIFT;
 #define HPAGE_SIZE              ((1UL) << HPAGE_SHIFT)
 #define HPAGE_MASK              (~(HPAGE_SIZE - 1))
 #define HUGETLB_PAGE_ORDER      (HPAGE_SHIFT - PAGE_SHIFT)
-#define HUGE_MAX_HSTATE         3
+#define HUGE_MAX_HSTATE         (MMU_PAGE_COUNT-1)
 
 #endif /* __ASSEMBLY__ */
 
diff --git a/arch/powerpc/include/asm/pgalloc-32.h b/arch/powerpc/include/asm/pgalloc-32.h
index c9500d666a1d..580cf73b96e8 100644
--- a/arch/powerpc/include/asm/pgalloc-32.h
+++ b/arch/powerpc/include/asm/pgalloc-32.h
@@ -3,7 +3,8 @@
 
 #include <linux/threads.h>
 
-#define PTE_NONCACHE_NUM        0  /* dummy for now to share code w/ppc64 */
+/* For 32-bit, all levels of page tables are just drawn from get_free_page() */
+#define MAX_PGTABLE_INDEX_SIZE  0
 
 extern void __bad_pte(pmd_t *pmd);
 
@@ -36,11 +37,10 @@ extern void pgd_free(struct mm_struct *mm, pgd_t *pgd);
 extern pte_t *pte_alloc_one_kernel(struct mm_struct *mm, unsigned long addr);
 extern pgtable_t pte_alloc_one(struct mm_struct *mm, unsigned long addr);
 
-static inline void pgtable_free(pgtable_free_t pgf)
+static inline void pgtable_free(void *table, unsigned index_size)
 {
-        void *p = (void *)(pgf.val & ~PGF_CACHENUM_MASK);
-
-        free_page((unsigned long)p);
+        BUG_ON(index_size); /* 32-bit doesn't use this */
+        free_page((unsigned long)table);
 }
 
 #define check_pgt_cache()       do { } while (0)
diff --git a/arch/powerpc/include/asm/pgalloc-64.h b/arch/powerpc/include/asm/pgalloc-64.h
index e6f069c4f713..605f5c5398d1 100644
--- a/arch/powerpc/include/asm/pgalloc-64.h
+++ b/arch/powerpc/include/asm/pgalloc-64.h
@@ -11,27 +11,34 @@
 #include <linux/cpumask.h>
 #include <linux/percpu.h>
 
-#ifndef CONFIG_PPC_SUBPAGE_PROT
-static inline void subpage_prot_free(pgd_t *pgd) {}
-#endif
+/*
+ * Functions that deal with pagetables that could be at any level of
+ * the table need to be passed an "index_size" so they know how to
+ * handle allocation.  For PTE pages (which are linked to a struct
+ * page for now, and drawn from the main get_free_pages() pool), the
+ * allocation size will be (2^index_size * sizeof(pointer)) and
+ * allocations are drawn from the kmem_cache in PGT_CACHE(index_size).
+ *
+ * The maximum index size needs to be big enough to allow any
+ * pagetable sizes we need, but small enough to fit in the low bits of
+ * any page table pointer.  In other words all pagetables, even tiny
+ * ones, must be aligned to allow at least enough low 0 bits to
+ * contain this value.  This value is also used as a mask, so it must
+ * be one less than a power of two.
+ */
+#define MAX_PGTABLE_INDEX_SIZE  0xf
 
 extern struct kmem_cache *pgtable_cache[];
-
-#define PGD_CACHE_NUM           0
-#define PUD_CACHE_NUM           1
-#define PMD_CACHE_NUM           1
-#define HUGEPTE_CACHE_NUM       2
-#define PTE_NONCACHE_NUM        7  /* from GFP rather than kmem_cache */
+#define PGT_CACHE(shift) (pgtable_cache[(shift)-1])
 
 static inline pgd_t *pgd_alloc(struct mm_struct *mm)
 {
-        return kmem_cache_alloc(pgtable_cache[PGD_CACHE_NUM], GFP_KERNEL);
+        return kmem_cache_alloc(PGT_CACHE(PGD_INDEX_SIZE), GFP_KERNEL);
 }
 
 static inline void pgd_free(struct mm_struct *mm, pgd_t *pgd)
 {
-        subpage_prot_free(pgd);
-        kmem_cache_free(pgtable_cache[PGD_CACHE_NUM], pgd);
+        kmem_cache_free(PGT_CACHE(PGD_INDEX_SIZE), pgd);
 }
 
 #ifndef CONFIG_PPC_64K_PAGES
@@ -40,13 +47,13 @@ static inline void pgd_free(struct mm_struct *mm, pgd_t *pgd)
 
 static inline pud_t *pud_alloc_one(struct mm_struct *mm, unsigned long addr)
 {
-        return kmem_cache_alloc(pgtable_cache[PUD_CACHE_NUM],
+        return kmem_cache_alloc(PGT_CACHE(PUD_INDEX_SIZE),
                                 GFP_KERNEL|__GFP_REPEAT);
 }
 
 static inline void pud_free(struct mm_struct *mm, pud_t *pud)
 {
-        kmem_cache_free(pgtable_cache[PUD_CACHE_NUM], pud);
+        kmem_cache_free(PGT_CACHE(PUD_INDEX_SIZE), pud);
 }
 
 static inline void pud_populate(struct mm_struct *mm, pud_t *pud, pmd_t *pmd)
@@ -78,13 +85,13 @@ static inline void pmd_populate_kernel(struct mm_struct *mm, pmd_t *pmd,
 
 static inline pmd_t *pmd_alloc_one(struct mm_struct *mm, unsigned long addr)
 {
-        return kmem_cache_alloc(pgtable_cache[PMD_CACHE_NUM],
+        return kmem_cache_alloc(PGT_CACHE(PMD_INDEX_SIZE),
                                 GFP_KERNEL|__GFP_REPEAT);
 }
 
 static inline void pmd_free(struct mm_struct *mm, pmd_t *pmd)
 {
-        kmem_cache_free(pgtable_cache[PMD_CACHE_NUM], pmd);
+        kmem_cache_free(PGT_CACHE(PMD_INDEX_SIZE), pmd);
 }
 
 static inline pte_t *pte_alloc_one_kernel(struct mm_struct *mm,
@@ -107,24 +114,22 @@ static inline pgtable_t pte_alloc_one(struct mm_struct *mm,
         return page;
 }
 
-static inline void pgtable_free(pgtable_free_t pgf)
+static inline void pgtable_free(void *table, unsigned index_size)
 {
-        void *p = (void *)(pgf.val & ~PGF_CACHENUM_MASK);
-        int cachenum = pgf.val & PGF_CACHENUM_MASK;
-
-        if (cachenum == PTE_NONCACHE_NUM)
-                free_page((unsigned long)p);
-        else
-                kmem_cache_free(pgtable_cache[cachenum], p);
+        if (!index_size)
+                free_page((unsigned long)table);
+        else {
+                BUG_ON(index_size > MAX_PGTABLE_INDEX_SIZE);
+                kmem_cache_free(PGT_CACHE(index_size), table);
+        }
 }
 
-#define __pmd_free_tlb(tlb, pmd,addr)                 \
-        pgtable_free_tlb(tlb, pgtable_free_cache(pmd, \
-                PMD_CACHE_NUM, PMD_TABLE_SIZE-1))
+#define __pmd_free_tlb(tlb, pmd, addr)                \
+        pgtable_free_tlb(tlb, pmd, PMD_INDEX_SIZE)
 #ifndef CONFIG_PPC_64K_PAGES
 #define __pud_free_tlb(tlb, pud, addr)                \
-        pgtable_free_tlb(tlb, pgtable_free_cache(pud, \
-                PUD_CACHE_NUM, PUD_TABLE_SIZE-1))
+        pgtable_free_tlb(tlb, pud, PUD_INDEX_SIZE)
+
 #endif /* CONFIG_PPC_64K_PAGES */
 
 #define check_pgt_cache()       do { } while (0)
diff --git a/arch/powerpc/include/asm/pgalloc.h b/arch/powerpc/include/asm/pgalloc.h
index f2e812de7c3c..abe8532bd14e 100644
--- a/arch/powerpc/include/asm/pgalloc.h
+++ b/arch/powerpc/include/asm/pgalloc.h
@@ -24,25 +24,6 @@ static inline void pte_free(struct mm_struct *mm, pgtable_t ptepage)
         __free_page(ptepage);
 }
 
-typedef struct pgtable_free {
-        unsigned long val;
-} pgtable_free_t;
-
-/* This needs to be big enough to allow for MMU_PAGE_COUNT + 2 to be stored
- * and small enough to fit in the low bits of any naturally aligned page
- * table cache entry. Arbitrarily set to 0x1f, that should give us some
- * room to grow
- */
-#define PGF_CACHENUM_MASK       0x1f
-
-static inline pgtable_free_t pgtable_free_cache(void *p, int cachenum,
-                                                unsigned long mask)
-{
-        BUG_ON(cachenum > PGF_CACHENUM_MASK);
-
-        return (pgtable_free_t){.val = ((unsigned long) p & ~mask) | cachenum};
-}
-
 #ifdef CONFIG_PPC64
 #include <asm/pgalloc-64.h>
 #else
@@ -50,12 +31,12 @@ static inline pgtable_free_t pgtable_free_cache(void *p, int cachenum,
 #endif
 
 #ifdef CONFIG_SMP
-extern void pgtable_free_tlb(struct mmu_gather *tlb, pgtable_free_t pgf);
+extern void pgtable_free_tlb(struct mmu_gather *tlb, void *table, unsigned shift);
 extern void pte_free_finish(void);
 #else /* CONFIG_SMP */
-static inline void pgtable_free_tlb(struct mmu_gather *tlb, pgtable_free_t pgf)
+static inline void pgtable_free_tlb(struct mmu_gather *tlb, void *table, unsigned shift)
 {
-        pgtable_free(pgf);
+        pgtable_free(table, shift);
 }
 static inline void pte_free_finish(void) { }
 #endif /* !CONFIG_SMP */
@@ -63,12 +44,9 @@ static inline void pte_free_finish(void) { }
 static inline void __pte_free_tlb(struct mmu_gather *tlb, struct page *ptepage,
                                   unsigned long address)
 {
-        pgtable_free_t pgf = pgtable_free_cache(page_address(ptepage),
-                                                PTE_NONCACHE_NUM,
-                                                PTE_TABLE_SIZE-1);
         tlb_flush_pgtable(tlb, address);
         pgtable_page_dtor(ptepage);
-        pgtable_free_tlb(tlb, pgf);
+        pgtable_free_tlb(tlb, page_address(ptepage), 0);
 }
 
 #endif /* __KERNEL__ */
diff --git a/arch/powerpc/include/asm/pgtable-ppc64.h b/arch/powerpc/include/asm/pgtable-ppc64.h
index 806abe7a3fa5..49865045d56f 100644
--- a/arch/powerpc/include/asm/pgtable-ppc64.h
+++ b/arch/powerpc/include/asm/pgtable-ppc64.h
@@ -354,6 +354,7 @@ static inline void __ptep_set_access_flags(pte_t *ptep, pte_t entry)
 #define pgoff_to_pte(off)       ((pte_t) {((off) << PTE_RPN_SHIFT)|_PAGE_FILE})
 #define PTE_FILE_MAX_BITS       (BITS_PER_LONG - PTE_RPN_SHIFT)
 
+void pgtable_cache_add(unsigned shift, void (*ctor)(void *));
 void pgtable_cache_init(void);
 
 /*
@@ -378,7 +379,18 @@ void pgtable_cache_init(void);
         return pt;
 }
 
-pte_t *huge_pte_offset(struct mm_struct *mm, unsigned long address);
+#ifdef CONFIG_HUGETLB_PAGE
+pte_t *find_linux_pte_or_hugepte(pgd_t *pgdir, unsigned long ea,
+                                 unsigned *shift);
+#else
+static inline pte_t *find_linux_pte_or_hugepte(pgd_t *pgdir, unsigned long ea,
+                                               unsigned *shift)
+{
+        if (shift)
+                *shift = 0;
+        return find_linux_pte(pgdir, ea);
+}
+#endif /* !CONFIG_HUGETLB_PAGE */
 
 #endif /* __ASSEMBLY__ */
 
diff --git a/arch/powerpc/include/asm/pgtable.h b/arch/powerpc/include/asm/pgtable.h
index 2a5da069714e..21207e54825b 100644
--- a/arch/powerpc/include/asm/pgtable.h
+++ b/arch/powerpc/include/asm/pgtable.h
@@ -211,6 +211,9 @@ extern void paging_init(void);
  */
 extern void update_mmu_cache(struct vm_area_struct *, unsigned long, pte_t);
 
+extern int gup_hugepd(hugepd_t *hugepd, unsigned pdshift, unsigned long addr,
+                      unsigned long end, int write, struct page **pages, int *nr);
+
 #endif /* __ASSEMBLY__ */
 
 #endif /* __KERNEL__ */
diff --git a/arch/powerpc/include/asm/pte-8xx.h b/arch/powerpc/include/asm/pte-8xx.h
index dd5ea95fe61e..d44826e4ff97 100644
--- a/arch/powerpc/include/asm/pte-8xx.h
+++ b/arch/powerpc/include/asm/pte-8xx.h
@@ -33,21 +33,21 @@
 #define _PAGE_NO_CACHE  0x0002  /* I: cache inhibit */
 #define _PAGE_SHARED    0x0004  /* No ASID (context) compare */
 #define _PAGE_SPECIAL   0x0008  /* SW entry, forced to 0 by the TLB miss */
+#define _PAGE_DIRTY     0x0100  /* C: page changed */
 
-/* These five software bits must be masked out when the entry is loaded
- * into the TLB.
+/* These 4 software bits must be masked out when the entry is loaded
+ * into the TLB, 1 SW bit left(0x0080).
  */
 #define _PAGE_GUARDED   0x0010  /* software: guarded access */
-#define _PAGE_DIRTY     0x0020  /* software: page changed */
-#define _PAGE_RW        0x0040  /* software: user write access allowed */
-#define _PAGE_ACCESSED  0x0080  /* software: page referenced */
+#define _PAGE_ACCESSED  0x0020  /* software: page referenced */
+#define _PAGE_WRITETHRU 0x0040  /* software: caching is write through */
 
 /* Setting any bits in the nibble with the follow two controls will
  * require a TLB exception handler change.  It is assumed unused bits
  * are always zero.
  */
-#define _PAGE_HWWRITE   0x0100  /* h/w write enable: never set in Linux PTE */
-#define _PAGE_USER      0x0800  /* One of the PP bits, the other is USER&~RW */
+#define _PAGE_RW        0x0400  /* lsb PP bits, inverted in HW */
+#define _PAGE_USER      0x0800  /* msb PP bits */
 
 #define _PMD_PRESENT    0x0001
 #define _PMD_BAD        0x0ff0
diff --git a/arch/powerpc/include/asm/pte-hash64-64k.h b/arch/powerpc/include/asm/pte-hash64-64k.h
index 82b72207c51c..c4490f9c67c4 100644
--- a/arch/powerpc/include/asm/pte-hash64-64k.h
+++ b/arch/powerpc/include/asm/pte-hash64-64k.h
@@ -76,41 +76,4 @@
         remap_pfn_range((vma), (addr), (pfn), PAGE_SIZE,                \
                         __pgprot(pgprot_val((prot)) | _PAGE_4K_PFN))
 
-
-#ifdef CONFIG_PPC_SUBPAGE_PROT
-/*
- * For the sub-page protection option, we extend the PGD with one of
- * these.  Basically we have a 3-level tree, with the top level being
- * the protptrs array.  To optimize speed and memory consumption when
- * only addresses < 4GB are being protected, pointers to the first
- * four pages of sub-page protection words are stored in the low_prot
- * array.
- * Each page of sub-page protection words protects 1GB (4 bytes
- * protects 64k).  For the 3-level tree, each page of pointers then
- * protects 8TB.
- */
-struct subpage_prot_table {
-        unsigned long maxaddr;  /* only addresses < this are protected */
-        unsigned int **protptrs[2];
-        unsigned int *low_prot[4];
-};
-
-#undef PGD_TABLE_SIZE
-#define PGD_TABLE_SIZE          ((sizeof(pgd_t) << PGD_INDEX_SIZE) + \
-                                 sizeof(struct subpage_prot_table))
-
-#define SBP_L1_BITS             (PAGE_SHIFT - 2)
-#define SBP_L2_BITS             (PAGE_SHIFT - 3)
-#define SBP_L1_COUNT            (1 << SBP_L1_BITS)
-#define SBP_L2_COUNT            (1 << SBP_L2_BITS)
-#define SBP_L2_SHIFT            (PAGE_SHIFT + SBP_L1_BITS)
-#define SBP_L3_SHIFT            (SBP_L2_SHIFT + SBP_L2_BITS)
-
-extern void subpage_prot_free(pgd_t *pgd);
-
-static inline struct subpage_prot_table *pgd_subpage_prot(pgd_t *pgd)
-{
-        return (struct subpage_prot_table *)(pgd + PTRS_PER_PGD);
-}
-#endif /* CONFIG_PPC_SUBPAGE_PROT */
 #endif  /* __ASSEMBLY__ */
diff --git a/arch/powerpc/include/asm/ptrace.h b/arch/powerpc/include/asm/ptrace.h
index 8c341490cfc5..cbd759e3cd78 100644
--- a/arch/powerpc/include/asm/ptrace.h
+++ b/arch/powerpc/include/asm/ptrace.h
@@ -140,6 +140,8 @@ extern void user_enable_single_step(struct task_struct *);
 extern void user_enable_block_step(struct task_struct *);
 extern void user_disable_single_step(struct task_struct *);
 
+#define ARCH_HAS_USER_SINGLE_STEP_INFO
+
 #endif /* __ASSEMBLY__ */
 
 #endif /* __KERNEL__ */
diff --git a/arch/powerpc/include/asm/qe.h b/arch/powerpc/include/asm/qe.h
index f388f0ab193f..0947b36e534c 100644
--- a/arch/powerpc/include/asm/qe.h
+++ b/arch/powerpc/include/asm/qe.h
@@ -87,7 +87,7 @@ extern spinlock_t cmxgcr_lock;
 
 /* Export QE common operations */
 #ifdef CONFIG_QUICC_ENGINE
-extern void __init qe_reset(void);
+extern void qe_reset(void);
 #else
 static inline void qe_reset(void) {}
 #endif
@@ -145,8 +145,17 @@ static inline void qe_pin_set_gpio(struct qe_pin *qe_pin) {}
 static inline void qe_pin_set_dedicated(struct qe_pin *pin) {}
 #endif /* CONFIG_QE_GPIO */
 
-/* QE internal API */
+#ifdef CONFIG_QUICC_ENGINE
 int qe_issue_cmd(u32 cmd, u32 device, u8 mcn_protocol, u32 cmd_input);
+#else
+static inline int qe_issue_cmd(u32 cmd, u32 device, u8 mcn_protocol,
+                               u32 cmd_input)
+{
+        return -ENOSYS;
+}
+#endif /* CONFIG_QUICC_ENGINE */
+
+/* QE internal API */
 enum qe_clock qe_clock_source(const char *source);
 unsigned int qe_get_brg_clk(void);
 int qe_setbrg(enum qe_clock brg, unsigned int rate, unsigned int multiplier);
@@ -154,7 +163,28 @@ int qe_get_snum(void);
 void qe_put_snum(u8 snum);
 unsigned int qe_get_num_of_risc(void);
 unsigned int qe_get_num_of_snums(void);
-int qe_alive_during_sleep(void);
+
+static inline int qe_alive_during_sleep(void)
+{
+        /*
+         * MPC8568E reference manual says:
+         *
+         * "...power down sequence waits for all I/O interfaces to become idle.
+         *  In some applications this may happen eventually without actively
+         *  shutting down interfaces, but most likely, software will have to
+         *  take steps to shut down the eTSEC, QUICC Engine Block, and PCI
+         *  interfaces before issuing the command (either the write to the core
+         *  MSR[WE] as described above or writing to POWMGTCSR) to put the
+         *  device into sleep state."
+         *
+         * MPC8569E reference manual has a similar paragraph.
+         */
+#ifdef CONFIG_PPC_85xx
+        return 0;
+#else
+        return 1;
+#endif
+}
 
 /* we actually use cpm_muram implementation, define this for convenience */
 #define qe_muram_init cpm_muram_init
@@ -210,8 +240,15 @@ struct qe_firmware_info {
         u64 extended_modes;     /* Extended modes */
 };
 
+#ifdef CONFIG_QUICC_ENGINE
 /* Upload a firmware to the QE */
 int qe_upload_firmware(const struct qe_firmware *firmware);
+#else
+static inline int qe_upload_firmware(const struct qe_firmware *firmware)
+{
+        return -ENOSYS;
+}
+#endif /* CONFIG_QUICC_ENGINE */
 
 /* Obtain information on the uploaded firmware */
 struct qe_firmware_info *qe_get_firmware_info(void);
diff --git a/arch/powerpc/include/asm/rtas.h b/arch/powerpc/include/asm/rtas.h
index 168fce726201..20de73c36682 100644
--- a/arch/powerpc/include/asm/rtas.h
+++ b/arch/powerpc/include/asm/rtas.h
@@ -58,7 +58,7 @@ struct rtas_t {
         unsigned long entry;            /* physical address pointer */
         unsigned long base;             /* physical address pointer */
         unsigned long size;
-        raw_spinlock_t lock;
+        arch_spinlock_t lock;
         struct rtas_args args;
         struct device_node *dev;        /* virtual address pointer */
 };
diff --git a/arch/powerpc/include/asm/smp.h b/arch/powerpc/include/asm/smp.h
index d9ea8d39c342..1d3b270d3083 100644
--- a/arch/powerpc/include/asm/smp.h
+++ b/arch/powerpc/include/asm/smp.h
@@ -37,7 +37,7 @@ extern void cpu_die(void);
 extern void smp_send_debugger_break(int cpu);
 extern void smp_message_recv(int);
 
-DECLARE_PER_CPU(unsigned int, pvr);
+DECLARE_PER_CPU(unsigned int, cpu_pvr);
 
 #ifdef CONFIG_HOTPLUG_CPU
 extern void fixup_irqs(cpumask_t map);
diff --git a/arch/powerpc/include/asm/spinlock.h b/arch/powerpc/include/asm/spinlock.h
index 198266cf9e2d..764094cff681 100644
--- a/arch/powerpc/include/asm/spinlock.h
+++ b/arch/powerpc/include/asm/spinlock.h
@@ -28,7 +28,7 @@
 #include <asm/asm-compat.h>
 #include <asm/synch.h>
 
-#define __raw_spin_is_locked(x)         ((x)->slock != 0)
+#define arch_spin_is_locked(x)          ((x)->slock != 0)
 
 #ifdef CONFIG_PPC64
 /* use 0x800000yy when locked, where yy == CPU number */
@@ -54,7 +54,7 @@
  * This returns the old value in the lock, so we succeeded
  * in getting the lock if the return value is 0.
  */
-static inline unsigned long arch_spin_trylock(raw_spinlock_t *lock)
+static inline unsigned long __arch_spin_trylock(arch_spinlock_t *lock)
 {
         unsigned long tmp, token;
 
@@ -73,10 +73,10 @@ static inline unsigned long arch_spin_trylock(raw_spinlock_t *lock)
         return tmp;
 }
 
-static inline int __raw_spin_trylock(raw_spinlock_t *lock)
+static inline int arch_spin_trylock(arch_spinlock_t *lock)
 {
         CLEAR_IO_SYNC;
-        return arch_spin_trylock(lock) == 0;
+        return __arch_spin_trylock(lock) == 0;
 }
 
 /*
@@ -96,19 +96,19 @@ static inline int __raw_spin_trylock(raw_spinlock_t *lock)
 #if defined(CONFIG_PPC_SPLPAR) || defined(CONFIG_PPC_ISERIES)
 /* We only yield to the hypervisor if we are in shared processor mode */
 #define SHARED_PROCESSOR (get_lppaca()->shared_proc)
-extern void __spin_yield(raw_spinlock_t *lock);
-extern void __rw_yield(raw_rwlock_t *lock);
+extern void __spin_yield(arch_spinlock_t *lock);
+extern void __rw_yield(arch_rwlock_t *lock);
 #else /* SPLPAR || ISERIES */
 #define __spin_yield(x) barrier()
 #define __rw_yield(x)   barrier()
 #define SHARED_PROCESSOR        0
 #endif
 
-static inline void __raw_spin_lock(raw_spinlock_t *lock)
+static inline void arch_spin_lock(arch_spinlock_t *lock)
 {
         CLEAR_IO_SYNC;
         while (1) {
-                if (likely(arch_spin_trylock(lock) == 0))
+                if (likely(__arch_spin_trylock(lock) == 0))
                         break;
                 do {
                         HMT_low();
@@ -120,13 +120,13 @@ static inline void __raw_spin_lock(raw_spinlock_t *lock)
 }
 
 static inline
-void __raw_spin_lock_flags(raw_spinlock_t *lock, unsigned long flags)
+void arch_spin_lock_flags(arch_spinlock_t *lock, unsigned long flags)
 {
         unsigned long flags_dis;
 
         CLEAR_IO_SYNC;
         while (1) {
-                if (likely(arch_spin_trylock(lock) == 0))
+                if (likely(__arch_spin_trylock(lock) == 0))
                         break;
                 local_save_flags(flags_dis);
                 local_irq_restore(flags);
@@ -140,19 +140,19 @@ void __raw_spin_lock_flags(raw_spinlock_t *lock, unsigned long flags)
         }
 }
 
-static inline void __raw_spin_unlock(raw_spinlock_t *lock)
+static inline void arch_spin_unlock(arch_spinlock_t *lock)
 {
         SYNC_IO;
-        __asm__ __volatile__("# __raw_spin_unlock\n\t"
+        __asm__ __volatile__("# arch_spin_unlock\n\t"
                                 LWSYNC_ON_SMP: : :"memory");
         lock->slock = 0;
 }
 
 #ifdef CONFIG_PPC64
-extern void __raw_spin_unlock_wait(raw_spinlock_t *lock);
+extern void arch_spin_unlock_wait(arch_spinlock_t *lock);
 #else
-#define __raw_spin_unlock_wait(lock) \
-        do { while (__raw_spin_is_locked(lock)) cpu_relax(); } while (0)
+#define arch_spin_unlock_wait(lock) \
+        do { while (arch_spin_is_locked(lock)) cpu_relax(); } while (0)
 #endif
 
 /*
@@ -166,8 +166,8 @@ extern void __raw_spin_unlock_wait(raw_spinlock_t *lock);
  * read-locks.
  */
 
-#define __raw_read_can_lock(rw)         ((rw)->lock >= 0)
-#define __raw_write_can_lock(rw)        (!(rw)->lock)
+#define arch_read_can_lock(rw)          ((rw)->lock >= 0)
+#define arch_write_can_lock(rw) (!(rw)->lock)
 
 #ifdef CONFIG_PPC64
 #define __DO_SIGN_EXTEND        "extsw  %0,%0\n"
@@ -181,7 +181,7 @@ extern void __raw_spin_unlock_wait(raw_spinlock_t *lock);
  * This returns the old value in the lock + 1,
  * so we got a read lock if the return value is > 0.
  */
-static inline long arch_read_trylock(raw_rwlock_t *rw)
+static inline long __arch_read_trylock(arch_rwlock_t *rw)
 {
         long tmp;
 
@@ -205,7 +205,7 @@ static inline long arch_read_trylock(raw_rwlock_t *rw)
  * This returns the old value in the lock,
  * so we got the write lock if the return value is 0.
  */
-static inline long arch_write_trylock(raw_rwlock_t *rw)
+static inline long __arch_write_trylock(arch_rwlock_t *rw)
 {
         long tmp, token;
 
@@ -225,10 +225,10 @@ static inline long arch_write_trylock(raw_rwlock_t *rw)
         return tmp;
 }
 
-static inline void __raw_read_lock(raw_rwlock_t *rw)
+static inline void arch_read_lock(arch_rwlock_t *rw)
 {
         while (1) {
-                if (likely(arch_read_trylock(rw) > 0))
+                if (likely(__arch_read_trylock(rw) > 0))
                         break;
                 do {
                         HMT_low();
@@ -239,10 +239,10 @@ static inline void __raw_read_lock(raw_rwlock_t *rw)
         }
 }
 
-static inline void __raw_write_lock(raw_rwlock_t *rw)
+static inline void arch_write_lock(arch_rwlock_t *rw)
 {
         while (1) {
-                if (likely(arch_write_trylock(rw) == 0))
+                if (likely(__arch_write_trylock(rw) == 0))
                         break;
                 do {
                         HMT_low();
@@ -253,17 +253,17 @@ static inline void __raw_write_lock(raw_rwlock_t *rw)
         }
 }
 
-static inline int __raw_read_trylock(raw_rwlock_t *rw)
+static inline int arch_read_trylock(arch_rwlock_t *rw)
 {
-        return arch_read_trylock(rw) > 0;
+        return __arch_read_trylock(rw) > 0;
 }
 
-static inline int __raw_write_trylock(raw_rwlock_t *rw)
+static inline int arch_write_trylock(arch_rwlock_t *rw)
 {
-        return arch_write_trylock(rw) == 0;
+        return __arch_write_trylock(rw) == 0;
 }
 
-static inline void __raw_read_unlock(raw_rwlock_t *rw)
+static inline void arch_read_unlock(arch_rwlock_t *rw)
 {
         long tmp;
 
@@ -280,19 +280,19 @@ static inline void __raw_read_unlock(raw_rwlock_t *rw)
         : "cr0", "xer", "memory");
 }
 
-static inline void __raw_write_unlock(raw_rwlock_t *rw)
+static inline void arch_write_unlock(arch_rwlock_t *rw)
 {
         __asm__ __volatile__("# write_unlock\n\t"
                                 LWSYNC_ON_SMP: : :"memory");
         rw->lock = 0;
 }
 
-#define __raw_read_lock_flags(lock, flags) __raw_read_lock(lock)
-#define __raw_write_lock_flags(lock, flags) __raw_write_lock(lock)
+#define arch_read_lock_flags(lock, flags) arch_read_lock(lock)
+#define arch_write_lock_flags(lock, flags) arch_write_lock(lock)
 
-#define _raw_spin_relax(lock)   __spin_yield(lock)
-#define _raw_read_relax(lock)   __rw_yield(lock)
-#define _raw_write_relax(lock)  __rw_yield(lock)
+#define arch_spin_relax(lock)   __spin_yield(lock)
+#define arch_read_relax(lock)   __rw_yield(lock)
+#define arch_write_relax(lock)  __rw_yield(lock)
 
 #endif /* __KERNEL__ */
 #endif /* __ASM_SPINLOCK_H */
diff --git a/arch/powerpc/include/asm/spinlock_types.h b/arch/powerpc/include/asm/spinlock_types.h
index 74236c9f05b1..2351adc4fdc4 100644
--- a/arch/powerpc/include/asm/spinlock_types.h
+++ b/arch/powerpc/include/asm/spinlock_types.h
@@ -7,14 +7,14 @@
 
 typedef struct {
         volatile unsigned int slock;
-} raw_spinlock_t;
+} arch_spinlock_t;
 
-#define __RAW_SPIN_LOCK_UNLOCKED        { 0 }
+#define __ARCH_SPIN_LOCK_UNLOCKED       { 0 }
 
 typedef struct {
         volatile signed int lock;
-} raw_rwlock_t;
+} arch_rwlock_t;
 
-#define __RAW_RW_LOCK_UNLOCKED          { 0 }
+#define __ARCH_RW_LOCK_UNLOCKED         { 0 }
 
 #endif
diff --git a/arch/powerpc/include/asm/systbl.h b/arch/powerpc/include/asm/systbl.h
index c7d671a7d9a1..07d2d19ab5e9 100644
--- a/arch/powerpc/include/asm/systbl.h
+++ b/arch/powerpc/include/asm/systbl.h
@@ -145,7 +145,7 @@ SYSCALL_SPU(setfsuid)
 SYSCALL_SPU(setfsgid)
 SYSCALL_SPU(llseek)
 COMPAT_SYS_SPU(getdents)
-SYSX_SPU(sys_select,ppc32_select,ppc_select)
+SYSX_SPU(sys_select,ppc32_select,sys_select)
 SYSCALL_SPU(flock)
 SYSCALL_SPU(msync)
 COMPAT_SYS_SPU(readv)
diff --git a/arch/powerpc/include/asm/udbg.h b/arch/powerpc/include/asm/udbg.h
index cd21e5e6b04f..11ae699135ba 100644
--- a/arch/powerpc/include/asm/udbg.h
+++ b/arch/powerpc/include/asm/udbg.h
@@ -51,6 +51,7 @@ extern void __init udbg_init_btext(void);
 extern void __init udbg_init_44x_as1(void);
 extern void __init udbg_init_40x_realmode(void);
 extern void __init udbg_init_cpm(void);
+extern void __init udbg_init_usbgecko(void);
 
 #endif /* __KERNEL__ */
 #endif /* _ASM_POWERPC_UDBG_H */
diff --git a/arch/powerpc/kernel/Makefile b/arch/powerpc/kernel/Makefile
index b23664a0b86c..c002b0410219 100644
--- a/arch/powerpc/kernel/Makefile
+++ b/arch/powerpc/kernel/Makefile
@@ -42,10 +42,11 @@ obj-$(CONFIG_ALTIVEC)		+= vecemu.o
 obj-$(CONFIG_PPC_970_NAP)       += idle_power4.o
 obj-$(CONFIG_PPC_OF)            += of_device.o of_platform.o prom_parse.o
 obj-$(CONFIG_PPC_CLOCK)         += clock.o
-procfs-$(CONFIG_PPC64)          := proc_ppc64.o
+procfs-y                        := proc_powerpc.o
 obj-$(CONFIG_PROC_FS)           += $(procfs-y)
 rtaspci-$(CONFIG_PPC64)-$(CONFIG_PCI)   := rtas_pci.o
 obj-$(CONFIG_PPC_RTAS)          += rtas.o rtas-rtc.o $(rtaspci-y-y)
+obj-$(CONFIG_PPC_RTAS_DAEMON)   += rtasd.o
 obj-$(CONFIG_RTAS_FLASH)        += rtas_flash.o
 obj-$(CONFIG_RTAS_PROC)         += rtas-proc.o
 obj-$(CONFIG_LPARCFG)           += lparcfg.o
diff --git a/arch/powerpc/kernel/asm-offsets.c b/arch/powerpc/kernel/asm-offsets.c
index 0812b0f414bb..a6c2b63227b3 100644
--- a/arch/powerpc/kernel/asm-offsets.c
+++ b/arch/powerpc/kernel/asm-offsets.c
@@ -190,6 +190,11 @@ int main(void)
         DEFINE(PACA_SYSTEM_TIME, offsetof(struct paca_struct, system_time));
         DEFINE(PACA_DATA_OFFSET, offsetof(struct paca_struct, data_offset));
         DEFINE(PACA_TRAP_SAVE, offsetof(struct paca_struct, trap_save));
+#ifdef CONFIG_KVM_BOOK3S_64_HANDLER
+        DEFINE(PACA_KVM_IN_GUEST, offsetof(struct paca_struct, kvm_in_guest));
+        DEFINE(PACA_KVM_SLB, offsetof(struct paca_struct, kvm_slb));
+        DEFINE(PACA_KVM_SLB_MAX, offsetof(struct paca_struct, kvm_slb_max));
+#endif
 #endif /* CONFIG_PPC64 */
 
         /* RTAS */
@@ -398,14 +403,24 @@ int main(void)
         DEFINE(VCPU_LAST_INST, offsetof(struct kvm_vcpu, arch.last_inst));
         DEFINE(VCPU_FAULT_DEAR, offsetof(struct kvm_vcpu, arch.fault_dear));
         DEFINE(VCPU_FAULT_ESR, offsetof(struct kvm_vcpu, arch.fault_esr));
+
+        /* book3s_64 */
+#ifdef CONFIG_PPC64
+        DEFINE(VCPU_FAULT_DSISR, offsetof(struct kvm_vcpu, arch.fault_dsisr));
+        DEFINE(VCPU_HOST_RETIP, offsetof(struct kvm_vcpu, arch.host_retip));
+        DEFINE(VCPU_HOST_R2, offsetof(struct kvm_vcpu, arch.host_r2));
+        DEFINE(VCPU_HOST_MSR, offsetof(struct kvm_vcpu, arch.host_msr));
+        DEFINE(VCPU_SHADOW_MSR, offsetof(struct kvm_vcpu, arch.shadow_msr));
+        DEFINE(VCPU_TRAMPOLINE_LOWMEM, offsetof(struct kvm_vcpu, arch.trampoline_lowmem));
+        DEFINE(VCPU_TRAMPOLINE_ENTER, offsetof(struct kvm_vcpu, arch.trampoline_enter));
+        DEFINE(VCPU_HIGHMEM_HANDLER, offsetof(struct kvm_vcpu, arch.highmem_handler));
+        DEFINE(VCPU_HFLAGS, offsetof(struct kvm_vcpu, arch.hflags));
+#endif
 #endif
 #ifdef CONFIG_44x
         DEFINE(PGD_T_LOG2, PGD_T_LOG2);
         DEFINE(PTE_T_LOG2, PTE_T_LOG2);
 #endif
-#ifdef CONFIG_FSL_BOOKE
-        DEFINE(TLBCAM_SIZE, sizeof(struct tlbcam));
-#endif
 
 #ifdef CONFIG_KVM_EXIT_TIMING
         DEFINE(VCPU_TIMING_EXIT_TBU, offsetof(struct kvm_vcpu,
diff --git a/arch/powerpc/kernel/cputable.c b/arch/powerpc/kernel/cputable.c
index 03c862b6a9c4..2fc82bac3bbc 100644
--- a/arch/powerpc/kernel/cputable.c
+++ b/arch/powerpc/kernel/cputable.c
@@ -697,9 +697,9 @@ static struct cpu_spec __initdata cpu_specs[] = {
                 .machine_check          = machine_check_generic,
                 .platform               = "ppc750",
         },
-        {       /* 750CL */
-                .pvr_mask               = 0xfffff0f0,
-                .pvr_value              = 0x00087010,
+        {       /* 750CL (and "Broadway") */
+                .pvr_mask               = 0xfffff0e0,
+                .pvr_value              = 0x00087000,
                 .cpu_name               = "750CL",
                 .cpu_features           = CPU_FTRS_750CL,
                 .cpu_user_features      = COMMON_USER | PPC_FEATURE_PPC_LE,
diff --git a/arch/powerpc/kernel/crash.c b/arch/powerpc/kernel/crash.c
index 0a8439aafdd1..6f4613dd05ef 100644
--- a/arch/powerpc/kernel/crash.c
+++ b/arch/powerpc/kernel/crash.c
@@ -373,7 +373,7 @@ void default_machine_crash_shutdown(struct pt_regs *regs)
         hard_irq_disable();
 
         for_each_irq(i) {
-                struct irq_desc *desc = irq_desc + i;
+                struct irq_desc *desc = irq_to_desc(i);
 
                 if (desc->status & IRQ_INPROGRESS)
                         desc->chip->eoi(i);
diff --git a/arch/powerpc/kernel/dma-swiotlb.c b/arch/powerpc/kernel/dma-swiotlb.c
index e96cbbd9b449..59c928564a03 100644
--- a/arch/powerpc/kernel/dma-swiotlb.c
+++ b/arch/powerpc/kernel/dma-swiotlb.c
@@ -21,7 +21,6 @@
 #include <asm/dma.h>
 #include <asm/abs_addr.h>
 
-int swiotlb __read_mostly;
 unsigned int ppc_swiotlb_enable;
 
 /*
diff --git a/arch/powerpc/kernel/exceptions-64s.S b/arch/powerpc/kernel/exceptions-64s.S
index c7eb4e0eb86c..e3be98ffe2a7 100644
--- a/arch/powerpc/kernel/exceptions-64s.S
+++ b/arch/powerpc/kernel/exceptions-64s.S
@@ -41,6 +41,7 @@ __start_interrupts:
         . = 0x200
 _machine_check_pSeries:
         HMT_MEDIUM
+        DO_KVM  0x200
         mtspr   SPRN_SPRG_SCRATCH0,r13          /* save r13 */
         EXCEPTION_PROLOG_PSERIES(PACA_EXMC, machine_check_common)
 
@@ -48,6 +49,7 @@ _machine_check_pSeries:
         .globl data_access_pSeries
 data_access_pSeries:
         HMT_MEDIUM
+        DO_KVM  0x300
         mtspr   SPRN_SPRG_SCRATCH0,r13
 BEGIN_FTR_SECTION
         mfspr   r13,SPRN_SPRG_PACA
@@ -77,6 +79,7 @@ ALT_FTR_SECTION_END_IFCLR(CPU_FTR_SLB)
         .globl data_access_slb_pSeries
 data_access_slb_pSeries:
         HMT_MEDIUM
+        DO_KVM  0x380
         mtspr   SPRN_SPRG_SCRATCH0,r13
         mfspr   r13,SPRN_SPRG_PACA              /* get paca address into r13 */
         std     r3,PACA_EXSLB+EX_R3(r13)
@@ -115,6 +118,7 @@ data_access_slb_pSeries:
         .globl instruction_access_slb_pSeries
 instruction_access_slb_pSeries:
         HMT_MEDIUM
+        DO_KVM  0x480
         mtspr   SPRN_SPRG_SCRATCH0,r13
         mfspr   r13,SPRN_SPRG_PACA              /* get paca address into r13 */
         std     r3,PACA_EXSLB+EX_R3(r13)
@@ -154,6 +158,7 @@ instruction_access_slb_pSeries:
         .globl  system_call_pSeries
 system_call_pSeries:
         HMT_MEDIUM
+        DO_KVM  0xc00
 BEGIN_FTR_SECTION
         cmpdi   r0,0x1ebe
         beq-    1f
@@ -187,14 +192,17 @@ END_FTR_SECTION_IFSET(CPU_FTR_REAL_LE)
          */
 performance_monitor_pSeries_1:
         . = 0xf00
+        DO_KVM  0xf00
         b       performance_monitor_pSeries
 
 altivec_unavailable_pSeries_1:
         . = 0xf20
+        DO_KVM  0xf20
         b       altivec_unavailable_pSeries
 
 vsx_unavailable_pSeries_1:
         . = 0xf40
+        DO_KVM  0xf40
         b       vsx_unavailable_pSeries
 
 #ifdef CONFIG_CBE_RAS
diff --git a/arch/powerpc/kernel/head_32.S b/arch/powerpc/kernel/head_32.S
index 829c3fe7c5a2..e025e89fe93e 100644
--- a/arch/powerpc/kernel/head_32.S
+++ b/arch/powerpc/kernel/head_32.S
@@ -164,6 +164,9 @@ __after_mmu_off:
 #ifdef CONFIG_PPC_EARLY_DEBUG_CPM
         bl      setup_cpm_bat
 #endif
+#ifdef CONFIG_PPC_EARLY_DEBUG_USBGECKO
+        bl      setup_usbgecko_bat
+#endif
 
 /*
  * Call setup_cpu for CPU 0 and initialize 6xx Idle
@@ -1203,6 +1206,28 @@ setup_cpm_bat:
         blr
 #endif
 
+#ifdef CONFIG_PPC_EARLY_DEBUG_USBGECKO
+setup_usbgecko_bat:
+        /* prepare a BAT for early io */
+#if defined(CONFIG_GAMECUBE)
+        lis     r8, 0x0c00
+#elif defined(CONFIG_WII)
+        lis     r8, 0x0d00
+#else
+#error Invalid platform for USB Gecko based early debugging.
+#endif
+        /*
+         * The virtual address used must match the virtual address
+         * associated to the fixmap entry FIX_EARLY_DEBUG_BASE.
+         */
+        lis     r11, 0xfffe     /* top 128K */
+        ori     r8, r8, 0x002a  /* uncached, guarded ,rw */
+        ori     r11, r11, 0x2   /* 128K, Vs=1, Vp=0 */
+        mtspr   SPRN_DBAT1L, r8
+        mtspr   SPRN_DBAT1U, r11
+        blr
+#endif
+
 #ifdef CONFIG_8260
 /* Jump into the system reset for the rom.
  * We first disable the MMU, and then jump to the ROM reset address.
diff --git a/arch/powerpc/kernel/head_64.S b/arch/powerpc/kernel/head_64.S
index c38afdb45d7b..925807488022 100644
--- a/arch/powerpc/kernel/head_64.S
+++ b/arch/powerpc/kernel/head_64.S
@@ -37,6 +37,7 @@
 #include <asm/firmware.h>
 #include <asm/page_64.h>
 #include <asm/irqflags.h>
+#include <asm/kvm_book3s_64_asm.h>
 
 /* The physical memory is layed out such that the secondary processor
  * spin code sits at 0x0000...0x00ff. On server, the vectors follow
@@ -165,6 +166,12 @@ exception_marker:
 #include "exceptions-64s.S"
 #endif
 
+/* KVM trampoline code needs to be close to the interrupt handlers */
+
+#ifdef CONFIG_KVM_BOOK3S_64_HANDLER
+#include "../kvm/book3s_64_rmhandlers.S"
+#endif
+
 _GLOBAL(generic_secondary_thread_init)
         mr      r24,r3
 
diff --git a/arch/powerpc/kernel/head_8xx.S b/arch/powerpc/kernel/head_8xx.S
index 6ded19d01891..678f98cd5e64 100644
--- a/arch/powerpc/kernel/head_8xx.S
+++ b/arch/powerpc/kernel/head_8xx.S
@@ -206,6 +206,8 @@ MachineCheck:
         EXCEPTION_PROLOG
         mfspr r4,SPRN_DAR
         stw r4,_DAR(r11)
+        li r5,0x00f0
+        mtspr SPRN_DAR,r5       /* Tag DAR, to be used in DTLB Error */
         mfspr r5,SPRN_DSISR
         stw r5,_DSISR(r11)
         addi r3,r1,STACK_FRAME_OVERHEAD
@@ -222,6 +224,8 @@ DataAccess:
         stw     r10,_DSISR(r11)
         mr      r5,r10
         mfspr   r4,SPRN_DAR
+        li      r10,0x00f0
+        mtspr   SPRN_DAR,r10    /* Tag DAR, to be used in DTLB Error */
         EXC_XFER_EE_LITE(0x300, handle_page_fault)
 
 /* Instruction access exception.
@@ -244,6 +248,8 @@ Alignment:
         EXCEPTION_PROLOG
         mfspr   r4,SPRN_DAR
         stw     r4,_DAR(r11)
+        li      r5,0x00f0
+        mtspr   SPRN_DAR,r5     /* Tag DAR, to be used in DTLB Error */
         mfspr   r5,SPRN_DSISR
         stw     r5,_DSISR(r11)
         addi    r3,r1,STACK_FRAME_OVERHEAD
@@ -333,26 +339,20 @@ InstructionTLBMiss:
         mfspr   r11, SPRN_MD_TWC        /* ....and get the pte address */
         lwz     r10, 0(r11)     /* Get the pte */
 
-#ifdef CONFIG_SWAP
-        /* do not set the _PAGE_ACCESSED bit of a non-present page */
-        andi.   r11, r10, _PAGE_PRESENT
-        beq     4f
-        ori     r10, r10, _PAGE_ACCESSED
-        mfspr   r11, SPRN_MD_TWC        /* get the pte address again */
-        stw     r10, 0(r11)
-4:
-#else
-        ori     r10, r10, _PAGE_ACCESSED
-        stw     r10, 0(r11)
-#endif
+        andi.   r11, r10, _PAGE_ACCESSED | _PAGE_PRESENT
+        cmpwi   cr0, r11, _PAGE_ACCESSED | _PAGE_PRESENT
+        bne-    cr0, 2f
+
+        /* Clear PP lsb, 0x400 */
+        rlwinm  r10, r10, 0, 22, 20
 
         /* The Linux PTE won't go exactly into the MMU TLB.
-         * Software indicator bits 21, 22 and 28 must be clear.
+         * Software indicator bits 22 and 28 must be clear.
          * Software indicator bits 24, 25, 26, and 27 must be
          * set.  All other Linux PTE bits control the behavior
          * of the MMU.
          */
-2:      li      r11, 0x00f0
+        li      r11, 0x00f0
         rlwimi  r10, r11, 0, 24, 28     /* Set 24-27, clear 28 */
         DO_8xx_CPU6(0x2d80, r3)
         mtspr   SPRN_MI_RPN, r10        /* Update TLB entry */
@@ -365,6 +365,22 @@ InstructionTLBMiss:
         lwz     r3, 8(r0)
 #endif
         rfi
+2:
+        mfspr   r11, SPRN_SRR1
+        /* clear all error bits as TLB Miss
+         * sets a few unconditionally
+        */
+        rlwinm  r11, r11, 0, 0xffff
+        mtspr   SPRN_SRR1, r11
+
+        mfspr   r10, SPRN_M_TW  /* Restore registers */
+        lwz     r11, 0(r0)
+        mtcr    r11
+        lwz     r11, 4(r0)
+#ifdef CONFIG_8xx_CPU6
+        lwz     r3, 8(r0)
+#endif
+        b       InstructionAccess
 
         . = 0x1200
 DataStoreTLBMiss:
@@ -406,29 +422,45 @@ DataStoreTLBMiss:
          * above.
          */
         rlwimi  r11, r10, 0, 27, 27
+        /* Insert the WriteThru flag into the TWC from the Linux PTE.
+         * It is bit 25 in the Linux PTE and bit 30 in the TWC
+         */
+        rlwimi  r11, r10, 32-5, 30, 30
         DO_8xx_CPU6(0x3b80, r3)
         mtspr   SPRN_MD_TWC, r11
 
-#ifdef CONFIG_SWAP
-        /* do not set the _PAGE_ACCESSED bit of a non-present page */
-        andi.   r11, r10, _PAGE_PRESENT
-        beq     4f
-        ori     r10, r10, _PAGE_ACCESSED
-4:
-        /* and update pte in table */
-#else
-        ori     r10, r10, _PAGE_ACCESSED
-#endif
-        mfspr   r11, SPRN_MD_TWC        /* get the pte address again */
-        stw     r10, 0(r11)
+        /* Both _PAGE_ACCESSED and _PAGE_PRESENT has to be set.
+         * We also need to know if the insn is a load/store, so:
+         * Clear _PAGE_PRESENT and load that which will
+         * trap into DTLB Error with store bit set accordinly.
+         */
+        /* PRESENT=0x1, ACCESSED=0x20
+         * r11 = ((r10 & PRESENT) & ((r10 & ACCESSED) >> 5));
+         * r10 = (r10 & ~PRESENT) | r11;
+         */
+        rlwinm  r11, r10, 32-5, _PAGE_PRESENT
+        and     r11, r11, r10
+        rlwimi  r10, r11, 0, _PAGE_PRESENT
+
+        /* Honour kernel RO, User NA */
+        /* 0x200 == Extended encoding, bit 22 */
+        /* r11 =  (r10 & _PAGE_USER) >> 2 */
+        rlwinm  r11, r10, 32-2, 0x200
+        or      r10, r11, r10
+        /* r11 =  (r10 & _PAGE_RW) >> 1 */
+        rlwinm  r11, r10, 32-1, 0x200
+        or      r10, r11, r10
+        /* invert RW and 0x200 bits */
+        xori    r10, r10, _PAGE_RW | 0x200
 
         /* The Linux PTE won't go exactly into the MMU TLB.
-         * Software indicator bits 21, 22 and 28 must be clear.
+         * Software indicator bits 22 and 28 must be clear.
          * Software indicator bits 24, 25, 26, and 27 must be
          * set.  All other Linux PTE bits control the behavior
          * of the MMU.
          */
 2:      li      r11, 0x00f0
+        mtspr   SPRN_DAR,r11    /* Tag DAR */
         rlwimi  r10, r11, 0, 24, 28     /* Set 24-27, clear 28 */
         DO_8xx_CPU6(0x3d80, r3)
         mtspr   SPRN_MD_RPN, r10        /* Update TLB entry */
@@ -469,97 +501,10 @@ DataTLBError:
         stw     r10, 0(r0)
         stw     r11, 4(r0)
 
-        /* First, make sure this was a store operation.
-        */
-        mfspr   r10, SPRN_DSISR
-        andis.  r11, r10, 0x0200        /* If set, indicates store op */
-        beq     2f
-
-        /* The EA of a data TLB miss is automatically stored in the MD_EPN
-         * register.  The EA of a data TLB error is automatically stored in
-         * the DAR, but not the MD_EPN register.  We must copy the 20 most
-         * significant bits of the EA from the DAR to MD_EPN before we
-         * start walking the page tables.  We also need to copy the CASID
-         * value from the M_CASID register.
-         * Addendum:  The EA of a data TLB error is _supposed_ to be stored
-         * in DAR, but it seems that this doesn't happen in some cases, such
-         * as when the error is due to a dcbi instruction to a page with a
-         * TLB that doesn't have the changed bit set.  In such cases, there
-         * does not appear to be any way  to recover the EA of the error
-         * since it is neither in DAR nor MD_EPN.  As a workaround, the
-         * _PAGE_HWWRITE bit is set for all kernel data pages when the PTEs
-         * are initialized in mapin_ram().  This will avoid the problem,
-         * assuming we only use the dcbi instruction on kernel addresses.
-         */
         mfspr   r10, SPRN_DAR
-        rlwinm  r11, r10, 0, 0, 19
-        ori     r11, r11, MD_EVALID
-        mfspr   r10, SPRN_M_CASID
-        rlwimi  r11, r10, 0, 28, 31
-        DO_8xx_CPU6(0x3780, r3)
-        mtspr   SPRN_MD_EPN, r11
-
-        mfspr   r10, SPRN_M_TWB /* Get level 1 table entry address */
-
-        /* If we are faulting a kernel address, we have to use the
-         * kernel page tables.
-         */
-        andi.   r11, r10, 0x0800
-        beq     3f
-        lis     r11, swapper_pg_dir@h
-        ori     r11, r11, swapper_pg_dir@l
-        rlwimi  r10, r11, 0, 2, 19
-3:
-        lwz     r11, 0(r10)     /* Get the level 1 entry */
-        rlwinm. r10, r11,0,0,19 /* Extract page descriptor page address */
-        beq     2f              /* If zero, bail */
-
-        /* We have a pte table, so fetch the pte from the table.
-         */
-        ori     r11, r11, 1             /* Set valid bit in physical L2 page */
-        DO_8xx_CPU6(0x3b80, r3)
-        mtspr   SPRN_MD_TWC, r11                /* Load pte table base address */
-        mfspr   r11, SPRN_MD_TWC                /* ....and get the pte address */
-        lwz     r10, 0(r11)             /* Get the pte */
-
-        andi.   r11, r10, _PAGE_RW      /* Is it writeable? */
-        beq     2f                      /* Bail out if not */
-
-        /* Update 'changed', among others.
-        */
-#ifdef CONFIG_SWAP
-        ori     r10, r10, _PAGE_DIRTY|_PAGE_HWWRITE
-        /* do not set the _PAGE_ACCESSED bit of a non-present page */
-        andi.   r11, r10, _PAGE_PRESENT
-        beq     4f
-        ori     r10, r10, _PAGE_ACCESSED
-4:
-#else
-        ori     r10, r10, _PAGE_DIRTY|_PAGE_ACCESSED|_PAGE_HWWRITE
-#endif
-        mfspr   r11, SPRN_MD_TWC                /* Get pte address again */
-        stw     r10, 0(r11)             /* and update pte in table */
-
-        /* The Linux PTE won't go exactly into the MMU TLB.
-         * Software indicator bits 21, 22 and 28 must be clear.
-         * Software indicator bits 24, 25, 26, and 27 must be
-         * set.  All other Linux PTE bits control the behavior
-         * of the MMU.
-         */
-        li      r11, 0x00f0
-        rlwimi  r10, r11, 0, 24, 28     /* Set 24-27, clear 28 */
-        DO_8xx_CPU6(0x3d80, r3)
-        mtspr   SPRN_MD_RPN, r10        /* Update TLB entry */
-
-        mfspr   r10, SPRN_M_TW  /* Restore registers */
-        lwz     r11, 0(r0)
-        mtcr    r11
-        lwz     r11, 4(r0)
-#ifdef CONFIG_8xx_CPU6
-        lwz     r3, 8(r0)
-#endif
-        rfi
-2:
+        cmpwi   cr0, r10, 0x00f0
+        beq-    FixupDAR        /* must be a buggy dcbX, icbi insn. */
+DARFixed:/* Return from dcbx instruction bug workaround, r10 holds value of DAR */
         mfspr   r10, SPRN_M_TW  /* Restore registers */
         lwz     r11, 0(r0)
         mtcr    r11
@@ -588,6 +533,140 @@ DataTLBError:
 
         . = 0x2000
 
+/* This is the procedure to calculate the data EA for buggy dcbx,dcbi instructions
+ * by decoding the registers used by the dcbx instruction and adding them.
+ * DAR is set to the calculated address and r10 also holds the EA on exit.
+ */
+ /* define if you don't want to use self modifying code */
+#define NO_SELF_MODIFYING_CODE
+FixupDAR:/* Entry point for dcbx workaround. */
+        /* fetch instruction from memory. */
+        mfspr   r10, SPRN_SRR0
+        DO_8xx_CPU6(0x3780, r3)
+        mtspr   SPRN_MD_EPN, r10
+        mfspr   r11, SPRN_M_TWB /* Get level 1 table entry address */
+        cmplwi  cr0, r11, 0x0800
+        blt-    3f              /* Branch if user space */
+        lis     r11, (swapper_pg_dir-PAGE_OFFSET)@h
+        ori     r11, r11, (swapper_pg_dir-PAGE_OFFSET)@l
+        rlwimi  r11, r10, 32-20, 0xffc /* r11 = r11&~0xffc|(r10>>20)&0xffc */
+3:      lwz     r11, 0(r11)     /* Get the level 1 entry */
+        DO_8xx_CPU6(0x3b80, r3)
+        mtspr   SPRN_MD_TWC, r11        /* Load pte table base address */
+        mfspr   r11, SPRN_MD_TWC        /* ....and get the pte address */
+        lwz     r11, 0(r11)     /* Get the pte */
+        /* concat physical page address(r11) and page offset(r10) */
+        rlwimi  r11, r10, 0, 20, 31
+        lwz     r11,0(r11)
+/* Check if it really is a dcbx instruction. */
+/* dcbt and dcbtst does not generate DTLB Misses/Errors,
+ * no need to include them here */
+        srwi    r10, r11, 26    /* check if major OP code is 31 */
+        cmpwi   cr0, r10, 31
+        bne-    141f
+        rlwinm  r10, r11, 0, 21, 30
+        cmpwi   cr0, r10, 2028  /* Is dcbz? */
+        beq+    142f
+        cmpwi   cr0, r10, 940   /* Is dcbi? */
+        beq+    142f
+        cmpwi   cr0, r10, 108   /* Is dcbst? */
+        beq+    144f            /* Fix up store bit! */
+        cmpwi   cr0, r10, 172   /* Is dcbf? */
+        beq+    142f
+        cmpwi   cr0, r10, 1964  /* Is icbi? */
+        beq+    142f
+141:    mfspr   r10, SPRN_DAR   /* r10 must hold DAR at exit */
+        b       DARFixed        /* Nope, go back to normal TLB processing */
+
+144:    mfspr   r10, SPRN_DSISR
+        rlwinm  r10, r10,0,7,5  /* Clear store bit for buggy dcbst insn */
+        mtspr   SPRN_DSISR, r10
+142:    /* continue, it was a dcbx, dcbi instruction. */
+#ifdef CONFIG_8xx_CPU6
+        lwz     r3, 8(r0)       /* restore r3 from memory */
+#endif
+#ifndef NO_SELF_MODIFYING_CODE
+        andis.  r10,r11,0x1f    /* test if reg RA is r0 */
+        li      r10,modified_instr@l
+        dcbtst  r0,r10          /* touch for store */
+        rlwinm  r11,r11,0,0,20  /* Zero lower 10 bits */
+        oris    r11,r11,640     /* Transform instr. to a "add r10,RA,RB" */
+        ori     r11,r11,532
+        stw     r11,0(r10)      /* store add/and instruction */
+        dcbf    0,r10           /* flush new instr. to memory. */
+        icbi    0,r10           /* invalidate instr. cache line */
+        lwz     r11, 4(r0)      /* restore r11 from memory */
+        mfspr   r10, SPRN_M_TW  /* restore r10 from M_TW */
+        isync                   /* Wait until new instr is loaded from memory */
+modified_instr:
+        .space  4               /* this is where the add instr. is stored */
+        bne+    143f
+        subf    r10,r0,r10      /* r10=r10-r0, only if reg RA is r0 */
+143:    mtdar   r10             /* store faulting EA in DAR */
+        b       DARFixed        /* Go back to normal TLB handling */
+#else
+        mfctr   r10
+        mtdar   r10                     /* save ctr reg in DAR */
+        rlwinm  r10, r11, 24, 24, 28    /* offset into jump table for reg RB */
+        addi    r10, r10, 150f@l        /* add start of table */
+        mtctr   r10                     /* load ctr with jump address */
+        xor     r10, r10, r10           /* sum starts at zero */
+        bctr                            /* jump into table */
+150:
+        add     r10, r10, r0    ;b      151f
+        add     r10, r10, r1    ;b      151f
+        add     r10, r10, r2    ;b      151f
+        add     r10, r10, r3    ;b      151f
+        add     r10, r10, r4    ;b      151f
+        add     r10, r10, r5    ;b      151f
+        add     r10, r10, r6    ;b      151f
+        add     r10, r10, r7    ;b      151f
+        add     r10, r10, r8    ;b      151f
+        add     r10, r10, r9    ;b      151f
+        mtctr   r11     ;b      154f    /* r10 needs special handling */
+        mtctr   r11     ;b      153f    /* r11 needs special handling */
+        add     r10, r10, r12   ;b      151f
+        add     r10, r10, r13   ;b      151f
+        add     r10, r10, r14   ;b      151f
+        add     r10, r10, r15   ;b      151f
+        add     r10, r10, r16   ;b      151f
+        add     r10, r10, r17   ;b      151f
+        add     r10, r10, r18   ;b      151f
+        add     r10, r10, r19   ;b      151f
+        add     r10, r10, r20   ;b      151f
+        add     r10, r10, r21   ;b      151f
+        add     r10, r10, r22   ;b      151f
+        add     r10, r10, r23   ;b      151f
+        add     r10, r10, r24   ;b      151f
+        add     r10, r10, r25   ;b      151f
+        add     r10, r10, r26   ;b      151f
+        add     r10, r10, r27   ;b      151f
+        add     r10, r10, r28   ;b      151f
+        add     r10, r10, r29   ;b      151f
+        add     r10, r10, r30   ;b      151f
+        add     r10, r10, r31
+151:
+        rlwinm. r11,r11,19,24,28        /* offset into jump table for reg RA */
+        beq     152f                    /* if reg RA is zero, don't add it */
+        addi    r11, r11, 150b@l        /* add start of table */
+        mtctr   r11                     /* load ctr with jump address */
+        rlwinm  r11,r11,0,16,10         /* make sure we don't execute this more than once */
+        bctr                            /* jump into table */
+152:
+        mfdar   r11
+        mtctr   r11                     /* restore ctr reg from DAR */
+        mtdar   r10                     /* save fault EA to DAR */
+        b       DARFixed                /* Go back to normal TLB handling */
+
+        /* special handling for r10,r11 since these are modified already */
+153:    lwz     r11, 4(r0)      /* load r11 from memory */
+        b       155f
+154:    mfspr   r11, SPRN_M_TW  /* load r10 from M_TW */
+155:    add     r10, r10, r11   /* add it */
+        mfctr   r11             /* restore r11 */
+        b       151b
+#endif
+
         .globl  giveup_fpu
 giveup_fpu:
         blr
diff --git a/arch/powerpc/kernel/head_fsl_booke.S b/arch/powerpc/kernel/head_fsl_booke.S
index 975788ca05d2..7f4bd7f3b6af 100644
--- a/arch/powerpc/kernel/head_fsl_booke.S
+++ b/arch/powerpc/kernel/head_fsl_booke.S
@@ -944,28 +944,6 @@ _GLOBAL(__setup_e500mc_ivors)
         blr
 
 /*
- * extern void loadcam_entry(unsigned int index)
- *
- * Load TLBCAM[index] entry in to the L2 CAM MMU
- */
-_GLOBAL(loadcam_entry)
-        lis     r4,TLBCAM@ha
-        addi    r4,r4,TLBCAM@l
-        mulli   r5,r3,TLBCAM_SIZE
-        add     r3,r5,r4
-        lwz     r4,0(r3)
-        mtspr   SPRN_MAS0,r4
-        lwz     r4,4(r3)
-        mtspr   SPRN_MAS1,r4
-        lwz     r4,8(r3)
-        mtspr   SPRN_MAS2,r4
-        lwz     r4,12(r3)
-        mtspr   SPRN_MAS3,r4
-        tlbwe
-        isync
-        blr
-
-/*
  * extern void giveup_altivec(struct task_struct *prev)
  *
  * The e500 core does not have an AltiVec unit.
diff --git a/arch/powerpc/kernel/io.c b/arch/powerpc/kernel/io.c
index 1882bf419fa6..8dc7547c2377 100644
--- a/arch/powerpc/kernel/io.c
+++ b/arch/powerpc/kernel/io.c
@@ -161,7 +161,7 @@ void _memcpy_fromio(void *dest, const volatile void __iomem *src,
                 dest++;
                 n--;
         }
-        while(n > 4) {
+        while(n >= 4) {
                 *((u32 *)dest) = *((volatile u32 *)vsrc);
                 eieio();
                 vsrc += 4;
@@ -190,7 +190,7 @@ void _memcpy_toio(volatile void __iomem *dest, const void *src, unsigned long n)
                 vdest++;
                 n--;
         }
-        while(n > 4) {
+        while(n >= 4) {
                 *((volatile u32 *)vdest) = *((volatile u32 *)src);
                 src += 4;
                 vdest += 4;
diff --git a/arch/powerpc/kernel/iommu.c b/arch/powerpc/kernel/iommu.c
index fd51578e29dd..5547ae6e6b0b 100644
--- a/arch/powerpc/kernel/iommu.c
+++ b/arch/powerpc/kernel/iommu.c
@@ -30,7 +30,7 @@
 #include <linux/spinlock.h>
 #include <linux/string.h>
 #include <linux/dma-mapping.h>
-#include <linux/bitops.h>
+#include <linux/bitmap.h>
 #include <linux/iommu-helper.h>
 #include <linux/crash_dump.h>
 #include <asm/io.h>
@@ -251,7 +251,7 @@ static void __iommu_free(struct iommu_table *tbl, dma_addr_t dma_addr,
         }
 
         ppc_md.tce_free(tbl, entry, npages);
-        iommu_area_free(tbl->it_map, free_entry, npages);
+        bitmap_clear(tbl->it_map, free_entry, npages);
 }
 
 static void iommu_free(struct iommu_table *tbl, dma_addr_t dma_addr,
diff --git a/arch/powerpc/kernel/irq.c b/arch/powerpc/kernel/irq.c
index 02a334662cc0..9040330b0530 100644
--- a/arch/powerpc/kernel/irq.c
+++ b/arch/powerpc/kernel/irq.c
@@ -87,7 +87,10 @@ extern int tau_interrupts(int);
 #endif /* CONFIG_PPC32 */
 
 #ifdef CONFIG_PPC64
+
+#ifndef CONFIG_SPARSE_IRQ
 EXPORT_SYMBOL(irq_desc);
+#endif
 
 int distribute_irqs = 1;
 
@@ -189,33 +192,7 @@ int show_interrupts(struct seq_file *p, void *v)
                 for_each_online_cpu(j)
                         seq_printf(p, "CPU%d       ", j);
                 seq_putc(p, '\n');
-        }
-
-        if (i < NR_IRQS) {
-                desc = get_irq_desc(i);
-                spin_lock_irqsave(&desc->lock, flags);
-                action = desc->action;
-                if (!action || !action->handler)
-                        goto skip;
-                seq_printf(p, "%3d: ", i);
-#ifdef CONFIG_SMP
-                for_each_online_cpu(j)
-                        seq_printf(p, "%10u ", kstat_irqs_cpu(i, j));
-#else
-                seq_printf(p, "%10u ", kstat_irqs(i));
-#endif /* CONFIG_SMP */
-                if (desc->chip)
-                        seq_printf(p, " %s ", desc->chip->typename);
-                else
-                        seq_puts(p, "  None      ");
-                seq_printf(p, "%s", (desc->status & IRQ_LEVEL) ? "Level " : "Edge  ");
-                seq_printf(p, "    %s", action->name);
-                for (action = action->next; action; action = action->next)
-                        seq_printf(p, ", %s", action->name);
-                seq_putc(p, '\n');
-skip:
-                spin_unlock_irqrestore(&desc->lock, flags);
-        } else if (i == NR_IRQS) {
+        } else if (i == nr_irqs) {
 #if defined(CONFIG_PPC32) && defined(CONFIG_TAU_INT)
                 if (tau_initialized){
                         seq_puts(p, "TAU: ");
@@ -225,30 +202,68 @@ skip:
                 }
 #endif /* CONFIG_PPC32 && CONFIG_TAU_INT*/
                 seq_printf(p, "BAD: %10u\n", ppc_spurious_interrupts);
+
+                return 0;
         }
+
+        desc = irq_to_desc(i);
+        if (!desc)
+                return 0;
+
+        raw_spin_lock_irqsave(&desc->lock, flags);
+
+        action = desc->action;
+        if (!action || !action->handler)
+                goto skip;
+
+        seq_printf(p, "%3d: ", i);
+#ifdef CONFIG_SMP
+        for_each_online_cpu(j)
+                seq_printf(p, "%10u ", kstat_irqs_cpu(i, j));
+#else
+        seq_printf(p, "%10u ", kstat_irqs(i));
+#endif /* CONFIG_SMP */
+
+        if (desc->chip)
+                seq_printf(p, " %s ", desc->chip->name);
+        else
+                seq_puts(p, "  None      ");
+
+        seq_printf(p, "%s", (desc->status & IRQ_LEVEL) ? "Level " : "Edge  ");
+        seq_printf(p, "    %s", action->name);
+
+        for (action = action->next; action; action = action->next)
+                seq_printf(p, ", %s", action->name);
+        seq_putc(p, '\n');
+
+skip:
+        raw_spin_unlock_irqrestore(&desc->lock, flags);
+
         return 0;
 }
 
 #ifdef CONFIG_HOTPLUG_CPU
 void fixup_irqs(cpumask_t map)
 {
+        struct irq_desc *desc;
         unsigned int irq;
         static int warned;
 
         for_each_irq(irq) {
                 cpumask_t mask;
 
-                if (irq_desc[irq].status & IRQ_PER_CPU)
+                desc = irq_to_desc(irq);
+                if (desc && desc->status & IRQ_PER_CPU)
                         continue;
 
-                cpumask_and(&mask, irq_desc[irq].affinity, &map);
+                cpumask_and(&mask, desc->affinity, &map);
                 if (any_online_cpu(mask) == NR_CPUS) {
                         printk("Breaking affinity for irq %i\n", irq);
                         mask = map;
                 }
-                if (irq_desc[irq].chip->set_affinity)
-                        irq_desc[irq].chip->set_affinity(irq, &mask);
-                else if (irq_desc[irq].action && !(warned++))
+                if (desc->chip->set_affinity)
+                        desc->chip->set_affinity(irq, &mask);
+                else if (desc->action && !(warned++))
                         printk("Cannot set affinity for irq %i\n", irq);
         }
 
@@ -275,7 +290,7 @@ static inline void handle_one_irq(unsigned int irq)
                 return;
         }
 
-        desc = irq_desc + irq;
+        desc = irq_to_desc(irq);
         saved_sp_limit = current->thread.ksp_limit;
 
         irqtp->task = curtp->task;
@@ -541,7 +556,7 @@ struct irq_host *irq_alloc_host(struct device_node *of_node,
                         smp_wmb();
 
                         /* Clear norequest flags */
-                        get_irq_desc(i)->status &= ~IRQ_NOREQUEST;
+                        irq_to_desc(i)->status &= ~IRQ_NOREQUEST;
 
                         /* Legacy flags are left to default at this point,
                          * one can then use irq_create_mapping() to
@@ -607,8 +622,16 @@ void irq_set_virq_count(unsigned int count)
 static int irq_setup_virq(struct irq_host *host, unsigned int virq,
                             irq_hw_number_t hwirq)
 {
+        struct irq_desc *desc;
+
+        desc = irq_to_desc_alloc_node(virq, 0);
+        if (!desc) {
+                pr_debug("irq: -> allocating desc failed\n");
+                goto error;
+        }
+
         /* Clear IRQ_NOREQUEST flag */
-        get_irq_desc(virq)->status &= ~IRQ_NOREQUEST;
+        desc->status &= ~IRQ_NOREQUEST;
 
         /* map it */
         smp_wmb();
@@ -617,11 +640,14 @@ static int irq_setup_virq(struct irq_host *host, unsigned int virq,
 
         if (host->ops->map(host, virq, hwirq)) {
                 pr_debug("irq: -> mapping failed, freeing\n");
-                irq_free_virt(virq, 1);
-                return -1;
+                goto error;
         }
 
         return 0;
+
+error:
+        irq_free_virt(virq, 1);
+        return -1;
 }
 
 unsigned int irq_create_direct_mapping(struct irq_host *host)
@@ -705,7 +731,7 @@ unsigned int irq_create_mapping(struct irq_host *host,
 EXPORT_SYMBOL_GPL(irq_create_mapping);
 
 unsigned int irq_create_of_mapping(struct device_node *controller,
-                                   u32 *intspec, unsigned int intsize)
+                                   const u32 *intspec, unsigned int intsize)
 {
         struct irq_host *host;
         irq_hw_number_t hwirq;
@@ -738,7 +764,7 @@ unsigned int irq_create_of_mapping(struct device_node *controller,
 
         /* Set type if specified and different than the current one */
         if (type != IRQ_TYPE_NONE &&
-            type != (get_irq_desc(virq)->status & IRQF_TRIGGER_MASK))
+            type != (irq_to_desc(virq)->status & IRQF_TRIGGER_MASK))
                 set_irq_type(virq, type);
         return virq;
 }
@@ -810,7 +836,7 @@ void irq_dispose_mapping(unsigned int virq)
         irq_map[virq].hwirq = host->inval_irq;
 
         /* Set some flags */
-        get_irq_desc(virq)->status |= IRQ_NOREQUEST;
+        irq_to_desc(virq)->status |= IRQ_NOREQUEST;
 
         /* Free it */
         irq_free_virt(virq, 1);
@@ -1002,12 +1028,24 @@ void irq_free_virt(unsigned int virq, unsigned int count)
         spin_unlock_irqrestore(&irq_big_lock, flags);
 }
 
-void irq_early_init(void)
+int arch_early_irq_init(void)
 {
-        unsigned int i;
+        struct irq_desc *desc;
+        int i;
+
+        for (i = 0; i < NR_IRQS; i++) {
+                desc = irq_to_desc(i);
+                if (desc)
+                        desc->status |= IRQ_NOREQUEST;
+        }
 
-        for (i = 0; i < NR_IRQS; i++)
-                get_irq_desc(i)->status |= IRQ_NOREQUEST;
+        return 0;
+}
+
+int arch_init_chip_data(struct irq_desc *desc, int node)
+{
+        desc->status |= IRQ_NOREQUEST;
+        return 0;
 }
 
 /* We need to create the radix trees late */
@@ -1069,16 +1107,19 @@ static int virq_debug_show(struct seq_file *m, void *private)
         seq_printf(m, "%-5s  %-7s  %-15s  %s\n", "virq", "hwirq",
                       "chip name", "host name");
 
-        for (i = 1; i < NR_IRQS; i++) {
-                desc = get_irq_desc(i);
-                spin_lock_irqsave(&desc->lock, flags);
+        for (i = 1; i < nr_irqs; i++) {
+                desc = irq_to_desc(i);
+                if (!desc)
+                        continue;
+
+                raw_spin_lock_irqsave(&desc->lock, flags);
 
                 if (desc->action && desc->action->handler) {
                         seq_printf(m, "%5d  ", i);
                         seq_printf(m, "0x%05lx  ", virq_to_hw(i));
 
-                        if (desc->chip && desc->chip->typename)
-                                p = desc->chip->typename;
+                        if (desc->chip && desc->chip->name)
+                                p = desc->chip->name;
                         else
                                 p = none;
                         seq_printf(m, "%-15s  ", p);
@@ -1090,7 +1131,7 @@ static int virq_debug_show(struct seq_file *m, void *private)
                         seq_printf(m, "%s\n", p);
                 }
 
-                spin_unlock_irqrestore(&desc->lock, flags);
+                raw_spin_unlock_irqrestore(&desc->lock, flags);
         }
 
         return 0;
diff --git a/arch/powerpc/kernel/lparcfg.c b/arch/powerpc/kernel/lparcfg.c
index ed0ac4e4b8d8..79a00bb9c64c 100644
--- a/arch/powerpc/kernel/lparcfg.c
+++ b/arch/powerpc/kernel/lparcfg.c
@@ -781,9 +781,9 @@ static int __init lparcfg_init(void)
                         !firmware_has_feature(FW_FEATURE_ISERIES))
                 mode |= S_IWUSR;
 
-        ent = proc_create("ppc64/lparcfg", mode, NULL, &lparcfg_fops);
+        ent = proc_create("powerpc/lparcfg", mode, NULL, &lparcfg_fops);
         if (!ent) {
-                printk(KERN_ERR "Failed to create ppc64/lparcfg\n");
+                printk(KERN_ERR "Failed to create powerpc/lparcfg\n");
                 return -EIO;
         }
 
diff --git a/arch/powerpc/kernel/misc_32.S b/arch/powerpc/kernel/misc_32.S
index da9c0c4c10f3..8649f536f8df 100644
--- a/arch/powerpc/kernel/misc_32.S
+++ b/arch/powerpc/kernel/misc_32.S
@@ -502,15 +502,7 @@ _GLOBAL(clear_pages)
         li      r0,PAGE_SIZE/L1_CACHE_BYTES
         slw     r0,r0,r4
         mtctr   r0
-#ifdef CONFIG_8xx
-        li      r4, 0
-1:      stw     r4, 0(r3)
-        stw     r4, 4(r3)
-        stw     r4, 8(r3)
-        stw     r4, 12(r3)
-#else
 1:      dcbz    0,r3
-#endif
         addi    r3,r3,L1_CACHE_BYTES
         bdnz    1b
         blr
@@ -535,15 +527,6 @@ _GLOBAL(copy_page)
         addi    r3,r3,-4
         addi    r4,r4,-4
 
-#ifdef CONFIG_8xx
-        /* don't use prefetch on 8xx */
-        li      r0,4096/L1_CACHE_BYTES
-        mtctr   r0
-1:      COPY_16_BYTES
-        bdnz    1b
-        blr
-
-#else   /* not 8xx, we can prefetch */
         li      r5,4
 
 #if MAX_COPY_PREFETCH > 1
@@ -584,7 +567,6 @@ _GLOBAL(copy_page)
         li      r0,MAX_COPY_PREFETCH
         li      r11,4
         b       2b
-#endif  /* CONFIG_8xx */
 
 /*
  * void atomic_clear_mask(atomic_t mask, atomic_t *addr)
diff --git a/arch/powerpc/kernel/nvram_64.c b/arch/powerpc/kernel/nvram_64.c
index 0ed31f220482..ad461e735aec 100644
--- a/arch/powerpc/kernel/nvram_64.c
+++ b/arch/powerpc/kernel/nvram_64.c
@@ -139,8 +139,8 @@ out:
 
 }
 
-static int dev_nvram_ioctl(struct inode *inode, struct file *file,
-        unsigned int cmd, unsigned long arg)
+static long dev_nvram_ioctl(struct file *file, unsigned int cmd,
+                            unsigned long arg)
 {
         switch(cmd) {
 #ifdef CONFIG_PPC_PMAC
@@ -169,11 +169,11 @@ static int dev_nvram_ioctl(struct inode *inode, struct file *file,
 }
 
 const struct file_operations nvram_fops = {
-        .owner =        THIS_MODULE,
-        .llseek =       dev_nvram_llseek,
-        .read =         dev_nvram_read,
-        .write =        dev_nvram_write,
-        .ioctl =        dev_nvram_ioctl,
+        .owner          = THIS_MODULE,
+        .llseek         = dev_nvram_llseek,
+        .read           = dev_nvram_read,
+        .write          = dev_nvram_write,
+        .unlocked_ioctl = dev_nvram_ioctl,
 };
 
 static struct miscdevice nvram_dev = {
@@ -184,7 +184,7 @@ static struct miscdevice nvram_dev = {
 
 
 #ifdef DEBUG_NVRAM
-static void nvram_print_partitions(char * label)
+static void __init nvram_print_partitions(char * label)
 {
         struct list_head * p;
         struct nvram_partition * tmp_part;
@@ -202,7 +202,7 @@ static void nvram_print_partitions(char * label)
 #endif
 
 
-static int nvram_write_header(struct nvram_partition * part)
+static int __init nvram_write_header(struct nvram_partition * part)
 {
         loff_t tmp_index;
         int rc;
@@ -214,7 +214,7 @@ static int nvram_write_header(struct nvram_partition * part)
 }
 
 
-static unsigned char nvram_checksum(struct nvram_header *p)
+static unsigned char __init nvram_checksum(struct nvram_header *p)
 {
         unsigned int c_sum, c_sum2;
         unsigned short *sp = (unsigned short *)p->name; /* assume 6 shorts */
@@ -228,32 +228,7 @@ static unsigned char nvram_checksum(struct nvram_header *p)
         return c_sum;
 }
 
-
-/*
- * Find an nvram partition, sig can be 0 for any
- * partition or name can be NULL for any name, else
- * tries to match both
- */
-struct nvram_partition *nvram_find_partition(int sig, const char *name)
-{
-        struct nvram_partition * part;
-        struct list_head * p;
-
-        list_for_each(p, &nvram_part->partition) {
-                part = list_entry(p, struct nvram_partition, partition);
-
-                if (sig && part->header.signature != sig)
-                        continue;
-                if (name && 0 != strncmp(name, part->header.name, 12))
-                        continue;
-                return part; 
-        }
-        return NULL;
-}
-EXPORT_SYMBOL(nvram_find_partition);
-
-
-static int nvram_remove_os_partition(void)
+static int __init nvram_remove_os_partition(void)
 {
         struct list_head *i;
         struct list_head *j;
@@ -319,7 +294,7 @@ static int nvram_remove_os_partition(void)
  * Will create a partition starting at the first free
  * space found if space has enough room.
  */
-static int nvram_create_os_partition(void)
+static int __init nvram_create_os_partition(void)
 {
         struct nvram_partition *part;
         struct nvram_partition *new_part;
@@ -422,7 +397,7 @@ static int nvram_create_os_partition(void)
  * 5.) If the max chunk cannot be allocated then try finding a chunk
  * that will satisfy the minum needed (NVRAM_MIN_REQ).
  */
-static int nvram_setup_partition(void)
+static int __init nvram_setup_partition(void)
 {
         struct list_head * p;
         struct nvram_partition * part;
@@ -480,7 +455,7 @@ static int nvram_setup_partition(void)
 }
 
 
-static int nvram_scan_partitions(void)
+static int __init nvram_scan_partitions(void)
 {
         loff_t cur_index = 0;
         struct nvram_header phead;
@@ -706,6 +681,9 @@ int nvram_clear_error_log(void)
         int clear_word = ERR_FLAG_ALREADY_LOGGED;
         int rc;
 
+        if (nvram_error_log_index == -1)
+                return -1;
+
         tmp_index = nvram_error_log_index;
         
         rc = ppc_md.nvram_write((char *)&clear_word, sizeof(int), &tmp_index);
diff --git a/arch/powerpc/kernel/perf_callchain.c b/arch/powerpc/kernel/perf_callchain.c
index 0a03cf70d247..a3c11cac3d71 100644
--- a/arch/powerpc/kernel/perf_callchain.c
+++ b/arch/powerpc/kernel/perf_callchain.c
@@ -119,13 +119,6 @@ static void perf_callchain_kernel(struct pt_regs *regs,
 }
 
 #ifdef CONFIG_PPC64
-
-#ifdef CONFIG_HUGETLB_PAGE
-#define is_huge_psize(pagesize) (HPAGE_SHIFT && mmu_huge_psizes[pagesize])
-#else
-#define is_huge_psize(pagesize) 0
-#endif
-
 /*
  * On 64-bit we don't want to invoke hash_page on user addresses from
  * interrupt context, so if the access faults, we read the page tables
@@ -135,7 +128,7 @@ static int read_user_stack_slow(void __user *ptr, void *ret, int nb)
 {
         pgd_t *pgdir;
         pte_t *ptep, pte;
-        int pagesize;
+        unsigned shift;
         unsigned long addr = (unsigned long) ptr;
         unsigned long offset;
         unsigned long pfn;
@@ -145,17 +138,14 @@ static int read_user_stack_slow(void __user *ptr, void *ret, int nb)
         if (!pgdir)
                 return -EFAULT;
 
-        pagesize = get_slice_psize(current->mm, addr);
+        ptep = find_linux_pte_or_hugepte(pgdir, addr, &shift);
+        if (!shift)
+                shift = PAGE_SHIFT;
 
         /* align address to page boundary */
-        offset = addr & ((1ul << mmu_psize_defs[pagesize].shift) - 1);
+        offset = addr & ((1UL << shift) - 1);
         addr -= offset;
 
-        if (is_huge_psize(pagesize))
-                ptep = huge_pte_offset(current->mm, addr);
-        else
-                ptep = find_linux_pte(pgdir, addr);
-
         if (ptep == NULL)
                 return -EFAULT;
         pte = *ptep;
@@ -497,11 +487,11 @@ static void perf_callchain_user_32(struct pt_regs *regs,
  * Since we can't get PMU interrupts inside a PMU interrupt handler,
  * we don't need separate irq and nmi entries here.
  */
-static DEFINE_PER_CPU(struct perf_callchain_entry, callchain);
+static DEFINE_PER_CPU(struct perf_callchain_entry, cpu_perf_callchain);
 
 struct perf_callchain_entry *perf_callchain(struct pt_regs *regs)
 {
-        struct perf_callchain_entry *entry = &__get_cpu_var(callchain);
+        struct perf_callchain_entry *entry = &__get_cpu_var(cpu_perf_callchain);
 
         entry->nr = 0;
 
diff --git a/arch/powerpc/kernel/ppc_ksyms.c b/arch/powerpc/kernel/ppc_ksyms.c
index c8b27bb4dbde..425451453e96 100644
--- a/arch/powerpc/kernel/ppc_ksyms.c
+++ b/arch/powerpc/kernel/ppc_ksyms.c
@@ -96,8 +96,6 @@ EXPORT_SYMBOL(copy_4K_page);
 EXPORT_SYMBOL(isa_io_base);
 EXPORT_SYMBOL(isa_mem_base);
 EXPORT_SYMBOL(pci_dram_offset);
-EXPORT_SYMBOL(pci_alloc_consistent);
-EXPORT_SYMBOL(pci_free_consistent);
 #endif /* CONFIG_PCI */
 
 EXPORT_SYMBOL(start_thread);
@@ -162,7 +160,6 @@ EXPORT_SYMBOL(screen_info);
 
 #ifdef CONFIG_PPC32
 EXPORT_SYMBOL(timer_interrupt);
-EXPORT_SYMBOL(irq_desc);
 EXPORT_SYMBOL(tb_ticks_per_jiffy);
 EXPORT_SYMBOL(cacheable_memcpy);
 EXPORT_SYMBOL(cacheable_memzero);
diff --git a/arch/powerpc/kernel/proc_ppc64.c b/arch/powerpc/kernel/proc_powerpc.c
index c647ddef40dc..1ed3b8d7981e 100644
--- a/arch/powerpc/kernel/proc_ppc64.c
+++ b/arch/powerpc/kernel/proc_powerpc.c
@@ -28,55 +28,7 @@
 #include <asm/uaccess.h>
 #include <asm/prom.h>
 
-static loff_t  page_map_seek( struct file *file, loff_t off, int whence);
-static ssize_t page_map_read( struct file *file, char __user *buf, size_t nbytes,
-                              loff_t *ppos);
-static int     page_map_mmap( struct file *file, struct vm_area_struct *vma );
-
-static const struct file_operations page_map_fops = {
-        .llseek = page_map_seek,
-        .read   = page_map_read,
-        .mmap   = page_map_mmap
-};
-
-/*
- * Create the ppc64 and ppc64/rtas directories early. This allows us to
- * assume that they have been previously created in drivers.
- */
-static int __init proc_ppc64_create(void)
-{
-        struct proc_dir_entry *root;
-
-        root = proc_mkdir("ppc64", NULL);
-        if (!root)
-                return 1;
-
-        if (!of_find_node_by_path("/rtas"))
-                return 0;
-
-        if (!proc_mkdir("rtas", root))
-                return 1;
-
-        if (!proc_symlink("rtas", NULL, "ppc64/rtas"))
-                return 1;
-
-        return 0;
-}
-core_initcall(proc_ppc64_create);
-
-static int __init proc_ppc64_init(void)
-{
-        struct proc_dir_entry *pde;
-
-        pde = proc_create_data("ppc64/systemcfg", S_IFREG|S_IRUGO, NULL,
-                               &page_map_fops, vdso_data);
-        if (!pde)
-                return 1;
-        pde->size = PAGE_SIZE;
-
-        return 0;
-}
-__initcall(proc_ppc64_init);
+#ifdef CONFIG_PPC64
 
 static loff_t page_map_seek( struct file *file, loff_t off, int whence)
 {
@@ -120,3 +72,55 @@ static int page_map_mmap( struct file *file, struct vm_area_struct *vma )
         return 0;
 }
 
+static const struct file_operations page_map_fops = {
+        .llseek = page_map_seek,
+        .read   = page_map_read,
+        .mmap   = page_map_mmap
+};
+
+
+static int __init proc_ppc64_init(void)
+{
+        struct proc_dir_entry *pde;
+
+        pde = proc_create_data("powerpc/systemcfg", S_IFREG|S_IRUGO, NULL,
+                               &page_map_fops, vdso_data);
+        if (!pde)
+                return 1;
+        pde->size = PAGE_SIZE;
+
+        return 0;
+}
+__initcall(proc_ppc64_init);
+
+#endif /* CONFIG_PPC64 */
+
+/*
+ * Create the ppc64 and ppc64/rtas directories early. This allows us to
+ * assume that they have been previously created in drivers.
+ */
+static int __init proc_ppc64_create(void)
+{
+        struct proc_dir_entry *root;
+
+        root = proc_mkdir("powerpc", NULL);
+        if (!root)
+                return 1;
+
+#ifdef CONFIG_PPC64
+        if (!proc_symlink("ppc64", NULL, "powerpc"))
+                pr_err("Failed to create link /proc/ppc64 -> /proc/powerpc\n");
+#endif
+
+        if (!of_find_node_by_path("/rtas"))
+                return 0;
+
+        if (!proc_mkdir("rtas", root))
+                return 1;
+
+        if (!proc_symlink("rtas", NULL, "powerpc/rtas"))
+                return 1;
+
+        return 0;
+}
+core_initcall(proc_ppc64_create);
diff --git a/arch/powerpc/kernel/rtas.c b/arch/powerpc/kernel/rtas.c
index bf90361bb70f..fd0d29493fd6 100644
--- a/arch/powerpc/kernel/rtas.c
+++ b/arch/powerpc/kernel/rtas.c
@@ -42,7 +42,7 @@
 #include <asm/mmu.h>
 
 struct rtas_t rtas = {
-        .lock = __RAW_SPIN_LOCK_UNLOCKED
+        .lock = __ARCH_SPIN_LOCK_UNLOCKED
 };
 EXPORT_SYMBOL(rtas);
 
@@ -80,13 +80,13 @@ static unsigned long lock_rtas(void)
 
         local_irq_save(flags);
         preempt_disable();
-        __raw_spin_lock_flags(&rtas.lock, flags);
+        arch_spin_lock_flags(&rtas.lock, flags);
         return flags;
 }
 
 static void unlock_rtas(unsigned long flags)
 {
-        __raw_spin_unlock(&rtas.lock);
+        arch_spin_unlock(&rtas.lock);
         local_irq_restore(flags);
         preempt_enable();
 }
@@ -978,7 +978,7 @@ int __init early_init_dt_scan_rtas(unsigned long node,
         return 1;
 }
 
-static raw_spinlock_t timebase_lock;
+static arch_spinlock_t timebase_lock;
 static u64 timebase = 0;
 
 void __cpuinit rtas_give_timebase(void)
@@ -987,10 +987,10 @@ void __cpuinit rtas_give_timebase(void)
 
         local_irq_save(flags);
         hard_irq_disable();
-        __raw_spin_lock(&timebase_lock);
+        arch_spin_lock(&timebase_lock);
         rtas_call(rtas_token("freeze-time-base"), 0, 1, NULL);
         timebase = get_tb();
-        __raw_spin_unlock(&timebase_lock);
+        arch_spin_unlock(&timebase_lock);
 
         while (timebase)
                 barrier();
@@ -1002,8 +1002,8 @@ void __cpuinit rtas_take_timebase(void)
 {
         while (!timebase)
                 barrier();
-        __raw_spin_lock(&timebase_lock);
+        arch_spin_lock(&timebase_lock);
         set_tb(timebase >> 32, timebase & 0xffffffff);
         timebase = 0;
-        __raw_spin_unlock(&timebase_lock);
+        arch_spin_unlock(&timebase_lock);
 }
diff --git a/arch/powerpc/kernel/rtas_flash.c b/arch/powerpc/kernel/rtas_flash.c
index 13011a96a977..a85117d5c9a4 100644
--- a/arch/powerpc/kernel/rtas_flash.c
+++ b/arch/powerpc/kernel/rtas_flash.c
@@ -6,7 +6,7 @@
  *      as published by the Free Software Foundation; either version
  *      2 of the License, or (at your option) any later version.
  *
- * /proc/ppc64/rtas/firmware_flash interface
+ * /proc/powerpc/rtas/firmware_flash interface
  *
  * This file implements a firmware_flash interface to pump a firmware
  * image into the kernel.  At reboot time rtas_restart() will see the
@@ -740,7 +740,7 @@ static int __init rtas_flash_init(void)
                 return 1;
         }
 
-        firmware_flash_pde = create_flash_pde("ppc64/rtas/"
+        firmware_flash_pde = create_flash_pde("powerpc/rtas/"
                                               FIRMWARE_FLASH_NAME,
                                               &rtas_flash_operations);
         if (firmware_flash_pde == NULL) {
@@ -754,7 +754,7 @@ static int __init rtas_flash_init(void)
         if (rc != 0)
                 goto cleanup;
 
-        firmware_update_pde = create_flash_pde("ppc64/rtas/"
+        firmware_update_pde = create_flash_pde("powerpc/rtas/"
                                                FIRMWARE_UPDATE_NAME,
                                                &rtas_flash_operations);
         if (firmware_update_pde == NULL) {
@@ -768,7 +768,7 @@ static int __init rtas_flash_init(void)
         if (rc != 0)
                 goto cleanup;
 
-        validate_pde = create_flash_pde("ppc64/rtas/" VALIDATE_FLASH_NAME,
+        validate_pde = create_flash_pde("powerpc/rtas/" VALIDATE_FLASH_NAME,
                                         &validate_flash_operations);
         if (validate_pde == NULL) {
                 rc = -ENOMEM;
@@ -781,7 +781,7 @@ static int __init rtas_flash_init(void)
         if (rc != 0)
                 goto cleanup;
 
-        manage_pde = create_flash_pde("ppc64/rtas/" MANAGE_FLASH_NAME,
+        manage_pde = create_flash_pde("powerpc/rtas/" MANAGE_FLASH_NAME,
                                       &manage_flash_operations);
         if (manage_pde == NULL) {
                 rc = -ENOMEM;
diff --git a/arch/powerpc/platforms/pseries/rtasd.c b/arch/powerpc/kernel/rtasd.c
index b3cbac855924..2e4832ab2108 100644
--- a/arch/powerpc/platforms/pseries/rtasd.c
+++ b/arch/powerpc/kernel/rtasd.c
@@ -39,6 +39,7 @@ static unsigned long rtas_log_start;
 static unsigned long rtas_log_size;
 
 static int surveillance_timeout = -1;
+
 static unsigned int rtas_error_log_max;
 static unsigned int rtas_error_log_buffer_max;
 
@@ -213,9 +214,11 @@ void pSeries_log_error(char *buf, unsigned int err_type, int fatal)
                 return;
         }
 
+#ifdef CONFIG_PPC64
         /* Write error to NVRAM */
         if (logging_enabled && !(err_type & ERR_FLAG_BOOT))
                 nvram_write_error_log(buf, len, err_type, error_log_cnt);
+#endif /* CONFIG_PPC64 */
 
         /*
          * rtas errors can occur during boot, and we do want to capture
@@ -264,7 +267,6 @@ void pSeries_log_error(char *buf, unsigned int err_type, int fatal)
 
 }
 
-
 static int rtas_log_open(struct inode * inode, struct file * file)
 {
         return 0;
@@ -300,6 +302,7 @@ static ssize_t rtas_log_read(struct file * file, char __user * buf,
                 return -ENOMEM;
 
         spin_lock_irqsave(&rtasd_log_lock, s);
+
         /* if it's 0, then we know we got the last one (the one in NVRAM) */
         while (rtas_log_size == 0) {
                 if (file->f_flags & O_NONBLOCK) {
@@ -313,7 +316,9 @@ static ssize_t rtas_log_read(struct file * file, char __user * buf,
                         error = -ENODATA;
                         goto out;
                 }
+#ifdef CONFIG_PPC64
                 nvram_clear_error_log();
+#endif /* CONFIG_PPC64 */
 
                 spin_unlock_irqrestore(&rtasd_log_lock, s);
                 error = wait_event_interruptible(rtas_log_wait, rtas_log_size);
@@ -427,14 +432,11 @@ static void rtas_event_scan(struct work_struct *w)
         put_online_cpus();
 }
 
-static void start_event_scan(void)
+#ifdef CONFIG_PPC64
+static void retreive_nvram_error_log(void)
 {
-        unsigned int err_type;
-        int rc;
-
-        printk(KERN_DEBUG "RTAS daemon started\n");
-        pr_debug("rtasd: will sleep for %d milliseconds\n",
-                 (30000 / rtas_event_scan_rate));
+        unsigned int err_type ;
+        int rc ;
 
         /* See if we have any error stored in NVRAM */
         memset(logdata, 0, rtas_error_log_max);
@@ -442,12 +444,26 @@ static void start_event_scan(void)
                                   &err_type, &error_log_cnt);
         /* We can use rtas_log_buf now */
         logging_enabled = 1;
-
         if (!rc) {
                 if (err_type != ERR_FLAG_ALREADY_LOGGED) {
                         pSeries_log_error(logdata, err_type | ERR_FLAG_BOOT, 0);
                 }
         }
+}
+#else /* CONFIG_PPC64 */
+static void retreive_nvram_error_log(void)
+{
+}
+#endif /* CONFIG_PPC64 */
+
+static void start_event_scan(void)
+{
+        printk(KERN_DEBUG "RTAS daemon started\n");
+        pr_debug("rtasd: will sleep for %d milliseconds\n",
+                 (30000 / rtas_event_scan_rate));
+
+        /* Retreive errors from nvram if any */
+        retreive_nvram_error_log();
 
         schedule_delayed_work_on(first_cpu(cpu_online_map), &event_scan_work,
                                  event_scan_delay);
@@ -457,13 +473,13 @@ static int __init rtas_init(void)
 {
         struct proc_dir_entry *entry;
 
-        if (!machine_is(pseries))
+        if (!machine_is(pseries) && !machine_is(chrp))
                 return 0;
 
         /* No RTAS */
         event_scan = rtas_token("event-scan");
         if (event_scan == RTAS_UNKNOWN_SERVICE) {
-                printk(KERN_DEBUG "rtasd: no event-scan on system\n");
+                printk(KERN_INFO "rtasd: No event-scan on system\n");
                 return -ENODEV;
         }
 
@@ -483,7 +499,7 @@ static int __init rtas_init(void)
                 return -ENOMEM;
         }
 
-        entry = proc_create("ppc64/rtas/error_log", S_IRUSR, NULL,
+        entry = proc_create("powerpc/rtas/error_log", S_IRUSR, NULL,
                             &proc_rtas_log_operations);
         if (!entry)
                 printk(KERN_ERR "Failed to create error_log proc entry\n");
@@ -492,11 +508,16 @@ static int __init rtas_init(void)
 
         return 0;
 }
+__initcall(rtas_init);
 
 static int __init surveillance_setup(char *str)
 {
         int i;
 
+        /* We only do surveillance on pseries */
+        if (!machine_is(pseries))
+                return 0;
+
         if (get_option(&str,&i)) {
                 if (i >= 0 && i <= 255)
                         surveillance_timeout = i;
@@ -504,6 +525,7 @@ static int __init surveillance_setup(char *str)
 
         return 1;
 }
+__setup("surveillance=", surveillance_setup);
 
 static int __init rtasmsgs_setup(char *str)
 {
@@ -514,6 +536,4 @@ static int __init rtasmsgs_setup(char *str)
 
         return 1;
 }
-__initcall(rtas_init);
-__setup("surveillance=", surveillance_setup);
 __setup("rtasmsgs=", rtasmsgs_setup);
diff --git a/arch/powerpc/kernel/setup-common.c b/arch/powerpc/kernel/setup-common.c
index 845c72ab7357..03dd6a248198 100644
--- a/arch/powerpc/kernel/setup-common.c
+++ b/arch/powerpc/kernel/setup-common.c
@@ -157,7 +157,7 @@ extern u32 cpu_temp_both(unsigned long cpu);
 #endif /* CONFIG_TAU */
 
 #ifdef CONFIG_SMP
-DEFINE_PER_CPU(unsigned int, pvr);
+DEFINE_PER_CPU(unsigned int, cpu_pvr);
 #endif
 
 static int show_cpuinfo(struct seq_file *m, void *v)
@@ -209,7 +209,7 @@ static int show_cpuinfo(struct seq_file *m, void *v)
         }
 
 #ifdef CONFIG_SMP
-        pvr = per_cpu(pvr, cpu_id);
+        pvr = per_cpu(cpu_pvr, cpu_id);
 #else
         pvr = mfspr(SPRN_PVR);
 #endif
diff --git a/arch/powerpc/kernel/setup_64.c b/arch/powerpc/kernel/setup_64.c
index df2c9e932b37..6568406b2a30 100644
--- a/arch/powerpc/kernel/setup_64.c
+++ b/arch/powerpc/kernel/setup_64.c
@@ -356,11 +356,6 @@ void __init setup_system(void)
          */
         initialize_cache_info();
 
-        /*
-         * Initialize irq remapping subsystem
-         */
-        irq_early_init();
-
 #ifdef CONFIG_PPC_RTAS
         /*
          * Initialize RTAS if available
diff --git a/arch/powerpc/kernel/smp.c b/arch/powerpc/kernel/smp.c
index 9b86a74d2815..a521fb8a40ee 100644
--- a/arch/powerpc/kernel/smp.c
+++ b/arch/powerpc/kernel/smp.c
@@ -218,6 +218,9 @@ void crash_send_ipi(void (*crash_ipi_callback)(struct pt_regs *))
 
 static void stop_this_cpu(void *dummy)
 {
+        /* Remove this CPU */
+        set_cpu_online(smp_processor_id(), false);
+
         local_irq_disable();
         while (1)
                 ;
@@ -232,7 +235,7 @@ struct thread_info *current_set[NR_CPUS];
 
 static void __devinit smp_store_cpu_info(int id)
 {
-        per_cpu(pvr, id) = mfspr(SPRN_PVR);
+        per_cpu(cpu_pvr, id) = mfspr(SPRN_PVR);
 }
 
 static void __init smp_create_idle(unsigned int cpu)
diff --git a/arch/powerpc/kernel/syscalls.c b/arch/powerpc/kernel/syscalls.c
index c04832c4a02e..3370e62e43d4 100644
--- a/arch/powerpc/kernel/syscalls.c
+++ b/arch/powerpc/kernel/syscalls.c
@@ -140,7 +140,6 @@ static inline unsigned long do_mmap2(unsigned long addr, size_t len,
                         unsigned long prot, unsigned long flags,
                         unsigned long fd, unsigned long off, int shift)
 {
-        struct file * file = NULL;
         unsigned long ret = -EINVAL;
 
         if (!arch_validate_prot(prot))
@@ -151,20 +150,8 @@ static inline unsigned long do_mmap2(unsigned long addr, size_t len,
                         goto out;
                 off >>= shift;
         }
-                
-        ret = -EBADF;
-        if (!(flags & MAP_ANONYMOUS)) {
-                if (!(file = fget(fd)))
-                        goto out;
-        }
-
-        flags &= ~(MAP_EXECUTABLE | MAP_DENYWRITE);
 
-        down_write(&current->mm->mmap_sem);
-        ret = do_mmap_pgoff(file, addr, len, prot, flags, off);
-        up_write(&current->mm->mmap_sem);
-        if (file)
-                fput(file);
+        ret = sys_mmap_pgoff(addr, len, prot, flags, fd, off);
 out:
         return ret;
 }
diff --git a/arch/powerpc/kernel/sysfs.c b/arch/powerpc/kernel/sysfs.c
index 956ab33fd73f..e235e52dc4fe 100644
--- a/arch/powerpc/kernel/sysfs.c
+++ b/arch/powerpc/kernel/sysfs.c
@@ -461,6 +461,25 @@ static void unregister_cpu_online(unsigned int cpu)
 
         cacheinfo_cpu_offline(cpu);
 }
+
+#ifdef CONFIG_ARCH_CPU_PROBE_RELEASE
+ssize_t arch_cpu_probe(const char *buf, size_t count)
+{
+        if (ppc_md.cpu_probe)
+                return ppc_md.cpu_probe(buf, count);
+
+        return -EINVAL;
+}
+
+ssize_t arch_cpu_release(const char *buf, size_t count)
+{
+        if (ppc_md.cpu_release)
+                return ppc_md.cpu_release(buf, count);
+
+        return -EINVAL;
+}
+#endif /* CONFIG_ARCH_CPU_PROBE_RELEASE */
+
 #endif /* CONFIG_HOTPLUG_CPU */
 
 static int __cpuinit sysfs_cpu_notify(struct notifier_block *self,
diff --git a/arch/powerpc/kernel/time.c b/arch/powerpc/kernel/time.c
index 674800b242d6..9ba2cc88591d 100644
--- a/arch/powerpc/kernel/time.c
+++ b/arch/powerpc/kernel/time.c
@@ -269,6 +269,7 @@ void account_system_vtime(struct task_struct *tsk)
         per_cpu(cputime_scaled_last_delta, smp_processor_id()) = deltascaled;
         local_irq_restore(flags);
 }
+EXPORT_SYMBOL_GPL(account_system_vtime);
 
 /*
  * Transfer the user and system times accumulated in the paca
diff --git a/arch/powerpc/kernel/traps.c b/arch/powerpc/kernel/traps.c
index 9d1f9354d6ca..d069ff8a7e03 100644
--- a/arch/powerpc/kernel/traps.c
+++ b/arch/powerpc/kernel/traps.c
@@ -174,6 +174,15 @@ int die(const char *str, struct pt_regs *regs, long err)
         return 0;
 }
 
+void user_single_step_siginfo(struct task_struct *tsk,
+                                struct pt_regs *regs, siginfo_t *info)
+{
+        memset(info, 0, sizeof(*info));
+        info->si_signo = SIGTRAP;
+        info->si_code = TRAP_TRACE;
+        info->si_addr = (void __user *)regs->nip;
+}
+
 void _exception(int signr, struct pt_regs *regs, int code, unsigned long addr)
 {
         siginfo_t info;
@@ -198,28 +207,6 @@ void _exception(int signr, struct pt_regs *regs, int code, unsigned long addr)
         info.si_code = code;
         info.si_addr = (void __user *) addr;
         force_sig_info(signr, &info, current);
-
-        /*
-         * Init gets no signals that it doesn't have a handler for.
-         * That's all very well, but if it has caused a synchronous
-         * exception and we ignore the resulting signal, it will just
-         * generate the same exception over and over again and we get
-         * nowhere.  Better to kill it and let the kernel panic.
-         */
-        if (is_global_init(current)) {
-                __sighandler_t handler;
-
-                spin_lock_irq(&current->sighand->siglock);
-                handler = current->sighand->action[signr-1].sa.sa_handler;
-                spin_unlock_irq(&current->sighand->siglock);
-                if (handler == SIG_DFL) {
-                        /* init has generated a synchronous exception
-                           and it doesn't have a handler for the signal */
-                        printk(KERN_CRIT "init has generated signal %d "
-                               "but has no handler for it\n", signr);
-                        do_exit(signr);
-                }
-        }
 }
 
 #ifdef CONFIG_PPC64
diff --git a/arch/powerpc/kernel/udbg.c b/arch/powerpc/kernel/udbg.c
index fc9af47e2128..e39cad83c884 100644
--- a/arch/powerpc/kernel/udbg.c
+++ b/arch/powerpc/kernel/udbg.c
@@ -60,6 +60,8 @@ void __init udbg_early_init(void)
         udbg_init_40x_realmode();
 #elif defined(CONFIG_PPC_EARLY_DEBUG_CPM)
         udbg_init_cpm();
+#elif defined(CONFIG_PPC_EARLY_DEBUG_USBGECKO)
+        udbg_init_usbgecko();
 #endif
 
 #ifdef CONFIG_PPC_EARLY_DEBUG
diff --git a/arch/powerpc/kernel/vector.S b/arch/powerpc/kernel/vector.S
index 67b6916f0e94..fe460482fa68 100644
--- a/arch/powerpc/kernel/vector.S
+++ b/arch/powerpc/kernel/vector.S
@@ -58,7 +58,7 @@ _GLOBAL(load_up_altivec)
          * all 1's
          */
         mfspr   r4,SPRN_VRSAVE
-        cmpdi   0,r4,0
+        cmpwi   0,r4,0
         bne+    1f
         li      r4,-1
         mtspr   SPRN_VRSAVE,r4
diff --git a/arch/powerpc/kernel/vmlinux.lds.S b/arch/powerpc/kernel/vmlinux.lds.S
index 27735a7ac12b..dcd01c82e701 100644
--- a/arch/powerpc/kernel/vmlinux.lds.S
+++ b/arch/powerpc/kernel/vmlinux.lds.S
@@ -38,6 +38,9 @@ jiffies = jiffies_64 + 4;
 #endif
 SECTIONS
 {
+        . = 0;
+        reloc_start = .;
+
         . = KERNELBASE;
 
 /*
diff --git a/arch/powerpc/kvm/Kconfig b/arch/powerpc/kvm/Kconfig
index c29926846613..07703f72330e 100644
--- a/arch/powerpc/kvm/Kconfig
+++ b/arch/powerpc/kvm/Kconfig
@@ -21,6 +21,23 @@ config KVM
         select PREEMPT_NOTIFIERS
         select ANON_INODES
 
+config KVM_BOOK3S_64_HANDLER
+        bool
+
+config KVM_BOOK3S_64
+        tristate "KVM support for PowerPC book3s_64 processors"
+        depends on EXPERIMENTAL && PPC64
+        select KVM
+        select KVM_BOOK3S_64_HANDLER
+        ---help---
+          Support running unmodified book3s_64 and book3s_32 guest kernels
+          in virtual machines on book3s_64 host processors.
+
+          This module provides access to the hardware capabilities through
+          a character device node named /dev/kvm.
+
+          If unsure, say N.
+
 config KVM_440
         bool "KVM support for PowerPC 440 processors"
         depends on EXPERIMENTAL && 44x
diff --git a/arch/powerpc/kvm/Makefile b/arch/powerpc/kvm/Makefile
index 37655fe19f2f..56484d652377 100644
--- a/arch/powerpc/kvm/Makefile
+++ b/arch/powerpc/kvm/Makefile
@@ -12,26 +12,45 @@ CFLAGS_44x_tlb.o  := -I.
 CFLAGS_e500_tlb.o := -I.
 CFLAGS_emulate.o  := -I.
 
-kvm-objs := $(common-objs-y) powerpc.o emulate.o
+common-objs-y += powerpc.o emulate.o
 obj-$(CONFIG_KVM_EXIT_TIMING) += timing.o
-obj-$(CONFIG_KVM) += kvm.o
+obj-$(CONFIG_KVM_BOOK3S_64_HANDLER) += book3s_64_exports.o
 
 AFLAGS_booke_interrupts.o := -I$(obj)
 
 kvm-440-objs := \
+        $(common-objs-y) \
         booke.o \
         booke_emulate.o \
         booke_interrupts.o \
         44x.o \
         44x_tlb.o \
         44x_emulate.o
-obj-$(CONFIG_KVM_440) += kvm-440.o
+kvm-objs-$(CONFIG_KVM_440) := $(kvm-440-objs)
 
 kvm-e500-objs := \
+        $(common-objs-y) \
         booke.o \
         booke_emulate.o \
         booke_interrupts.o \
         e500.o \
         e500_tlb.o \
         e500_emulate.o
-obj-$(CONFIG_KVM_E500) += kvm-e500.o
+kvm-objs-$(CONFIG_KVM_E500) := $(kvm-e500-objs)
+
+kvm-book3s_64-objs := \
+        $(common-objs-y) \
+        book3s.o \
+        book3s_64_emulate.o \
+        book3s_64_interrupts.o \
+        book3s_64_mmu_host.o \
+        book3s_64_mmu.o \
+        book3s_32_mmu.o
+kvm-objs-$(CONFIG_KVM_BOOK3S_64) := $(kvm-book3s_64-objs)
+
+kvm-objs := $(kvm-objs-m) $(kvm-objs-y)
+
+obj-$(CONFIG_KVM_440) += kvm.o
+obj-$(CONFIG_KVM_E500) += kvm.o
+obj-$(CONFIG_KVM_BOOK3S_64) += kvm.o
+
diff --git a/arch/powerpc/kvm/book3s.c b/arch/powerpc/kvm/book3s.c
new file mode 100644
index 000000000000..3e294bd9b8c6
--- /dev/null
+++ b/arch/powerpc/kvm/book3s.c
@@ -0,0 +1,974 @@
+/*
+ * Copyright (C) 2009. SUSE Linux Products GmbH. All rights reserved.
+ *
+ * Authors:
+ *    Alexander Graf <agraf@suse.de>
+ *    Kevin Wolf <mail@kevin-wolf.de>
+ *
+ * Description:
+ * This file is derived from arch/powerpc/kvm/44x.c,
+ * by Hollis Blanchard <hollisb@us.ibm.com>.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, version 2, as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kvm_host.h>
+#include <linux/err.h>
+
+#include <asm/reg.h>
+#include <asm/cputable.h>
+#include <asm/cacheflush.h>
+#include <asm/tlbflush.h>
+#include <asm/uaccess.h>
+#include <asm/io.h>
+#include <asm/kvm_ppc.h>
+#include <asm/kvm_book3s.h>
+#include <asm/mmu_context.h>
+#include <linux/sched.h>
+#include <linux/vmalloc.h>
+
+#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
+
+/* #define EXIT_DEBUG */
+/* #define EXIT_DEBUG_SIMPLE */
+
+/* Without AGGRESSIVE_DEC we only fire off a DEC interrupt when DEC turns 0.
+ * When set, we retrigger a DEC interrupt after that if DEC <= 0.
+ * PPC32 Linux runs faster without AGGRESSIVE_DEC, PPC64 Linux requires it. */
+
+/* #define AGGRESSIVE_DEC */
+
+struct kvm_stats_debugfs_item debugfs_entries[] = {
+        { "exits",       VCPU_STAT(sum_exits) },
+        { "mmio",        VCPU_STAT(mmio_exits) },
+        { "sig",         VCPU_STAT(signal_exits) },
+        { "sysc",        VCPU_STAT(syscall_exits) },
+        { "inst_emu",    VCPU_STAT(emulated_inst_exits) },
+        { "dec",         VCPU_STAT(dec_exits) },
+        { "ext_intr",    VCPU_STAT(ext_intr_exits) },
+        { "queue_intr",  VCPU_STAT(queue_intr) },
+        { "halt_wakeup", VCPU_STAT(halt_wakeup) },
+        { "pf_storage",  VCPU_STAT(pf_storage) },
+        { "sp_storage",  VCPU_STAT(sp_storage) },
+        { "pf_instruc",  VCPU_STAT(pf_instruc) },
+        { "sp_instruc",  VCPU_STAT(sp_instruc) },
+        { "ld",          VCPU_STAT(ld) },
+        { "ld_slow",     VCPU_STAT(ld_slow) },
+        { "st",          VCPU_STAT(st) },
+        { "st_slow",     VCPU_STAT(st_slow) },
+        { NULL }
+};
+
+void kvmppc_core_load_host_debugstate(struct kvm_vcpu *vcpu)
+{
+}
+
+void kvmppc_core_load_guest_debugstate(struct kvm_vcpu *vcpu)
+{
+}
+
+void kvmppc_core_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
+{
+        memcpy(get_paca()->kvm_slb, to_book3s(vcpu)->slb_shadow, sizeof(get_paca()->kvm_slb));
+        get_paca()->kvm_slb_max = to_book3s(vcpu)->slb_shadow_max;
+}
+
+void kvmppc_core_vcpu_put(struct kvm_vcpu *vcpu)
+{
+        memcpy(to_book3s(vcpu)->slb_shadow, get_paca()->kvm_slb, sizeof(get_paca()->kvm_slb));
+        to_book3s(vcpu)->slb_shadow_max = get_paca()->kvm_slb_max;
+}
+
+#if defined(AGGRESSIVE_DEC) || defined(EXIT_DEBUG)
+static u32 kvmppc_get_dec(struct kvm_vcpu *vcpu)
+{
+        u64 jd = mftb() - vcpu->arch.dec_jiffies;
+        return vcpu->arch.dec - jd;
+}
+#endif
+
+void kvmppc_set_msr(struct kvm_vcpu *vcpu, u64 msr)
+{
+        ulong old_msr = vcpu->arch.msr;
+
+#ifdef EXIT_DEBUG
+        printk(KERN_INFO "KVM: Set MSR to 0x%llx\n", msr);
+#endif
+        msr &= to_book3s(vcpu)->msr_mask;
+        vcpu->arch.msr = msr;
+        vcpu->arch.shadow_msr = msr | MSR_USER32;
+        vcpu->arch.shadow_msr &= ( MSR_VEC | MSR_VSX | MSR_FP | MSR_FE0 |
+                                   MSR_USER64 | MSR_SE | MSR_BE | MSR_DE |
+                                   MSR_FE1);
+
+        if (msr & (MSR_WE|MSR_POW)) {
+                if (!vcpu->arch.pending_exceptions) {
+                        kvm_vcpu_block(vcpu);
+                        vcpu->stat.halt_wakeup++;
+                }
+        }
+
+        if (((vcpu->arch.msr & (MSR_IR|MSR_DR)) != (old_msr & (MSR_IR|MSR_DR))) ||
+            (vcpu->arch.msr & MSR_PR) != (old_msr & MSR_PR)) {
+                kvmppc_mmu_flush_segments(vcpu);
+                kvmppc_mmu_map_segment(vcpu, vcpu->arch.pc);
+        }
+}
+
+void kvmppc_inject_interrupt(struct kvm_vcpu *vcpu, int vec, u64 flags)
+{
+        vcpu->arch.srr0 = vcpu->arch.pc;
+        vcpu->arch.srr1 = vcpu->arch.msr | flags;
+        vcpu->arch.pc = to_book3s(vcpu)->hior + vec;
+        vcpu->arch.mmu.reset_msr(vcpu);
+}
+
+void kvmppc_book3s_queue_irqprio(struct kvm_vcpu *vcpu, unsigned int vec)
+{
+        unsigned int prio;
+
+        vcpu->stat.queue_intr++;
+        switch (vec) {
+        case 0x100: prio = BOOK3S_IRQPRIO_SYSTEM_RESET;         break;
+        case 0x200: prio = BOOK3S_IRQPRIO_MACHINE_CHECK;        break;
+        case 0x300: prio = BOOK3S_IRQPRIO_DATA_STORAGE;         break;
+        case 0x380: prio = BOOK3S_IRQPRIO_DATA_SEGMENT;         break;
+        case 0x400: prio = BOOK3S_IRQPRIO_INST_STORAGE;         break;
+        case 0x480: prio = BOOK3S_IRQPRIO_INST_SEGMENT;         break;
+        case 0x500: prio = BOOK3S_IRQPRIO_EXTERNAL;             break;
+        case 0x600: prio = BOOK3S_IRQPRIO_ALIGNMENT;            break;
+        case 0x700: prio = BOOK3S_IRQPRIO_PROGRAM;              break;
+        case 0x800: prio = BOOK3S_IRQPRIO_FP_UNAVAIL;           break;
+        case 0x900: prio = BOOK3S_IRQPRIO_DECREMENTER;          break;
+        case 0xc00: prio = BOOK3S_IRQPRIO_SYSCALL;              break;
+        case 0xd00: prio = BOOK3S_IRQPRIO_DEBUG;                break;
+        case 0xf20: prio = BOOK3S_IRQPRIO_ALTIVEC;              break;
+        case 0xf40: prio = BOOK3S_IRQPRIO_VSX;                  break;
+        default:    prio = BOOK3S_IRQPRIO_MAX;                  break;
+        }
+
+        set_bit(prio, &vcpu->arch.pending_exceptions);
+#ifdef EXIT_DEBUG
+        printk(KERN_INFO "Queueing interrupt %x\n", vec);
+#endif
+}
+
+
+void kvmppc_core_queue_program(struct kvm_vcpu *vcpu)
+{
+        kvmppc_book3s_queue_irqprio(vcpu, BOOK3S_INTERRUPT_PROGRAM);
+}
+
+void kvmppc_core_queue_dec(struct kvm_vcpu *vcpu)
+{
+        kvmppc_book3s_queue_irqprio(vcpu, BOOK3S_INTERRUPT_DECREMENTER);
+}
+
+int kvmppc_core_pending_dec(struct kvm_vcpu *vcpu)
+{
+        return test_bit(BOOK3S_INTERRUPT_DECREMENTER >> 7, &vcpu->arch.pending_exceptions);
+}
+
+void kvmppc_core_queue_external(struct kvm_vcpu *vcpu,
+                                struct kvm_interrupt *irq)
+{
+        kvmppc_book3s_queue_irqprio(vcpu, BOOK3S_INTERRUPT_EXTERNAL);
+}
+
+int kvmppc_book3s_irqprio_deliver(struct kvm_vcpu *vcpu, unsigned int priority)
+{
+        int deliver = 1;
+        int vec = 0;
+
+        switch (priority) {
+        case BOOK3S_IRQPRIO_DECREMENTER:
+                deliver = vcpu->arch.msr & MSR_EE;
+                vec = BOOK3S_INTERRUPT_DECREMENTER;
+                break;
+        case BOOK3S_IRQPRIO_EXTERNAL:
+                deliver = vcpu->arch.msr & MSR_EE;
+                vec = BOOK3S_INTERRUPT_EXTERNAL;
+                break;
+        case BOOK3S_IRQPRIO_SYSTEM_RESET:
+                vec = BOOK3S_INTERRUPT_SYSTEM_RESET;
+                break;
+        case BOOK3S_IRQPRIO_MACHINE_CHECK:
+                vec = BOOK3S_INTERRUPT_MACHINE_CHECK;
+                break;
+        case BOOK3S_IRQPRIO_DATA_STORAGE:
+                vec = BOOK3S_INTERRUPT_DATA_STORAGE;
+                break;
+        case BOOK3S_IRQPRIO_INST_STORAGE:
+                vec = BOOK3S_INTERRUPT_INST_STORAGE;
+                break;
+        case BOOK3S_IRQPRIO_DATA_SEGMENT:
+                vec = BOOK3S_INTERRUPT_DATA_SEGMENT;
+                break;
+        case BOOK3S_IRQPRIO_INST_SEGMENT:
+                vec = BOOK3S_INTERRUPT_INST_SEGMENT;
+                break;
+        case BOOK3S_IRQPRIO_ALIGNMENT:
+                vec = BOOK3S_INTERRUPT_ALIGNMENT;
+                break;
+        case BOOK3S_IRQPRIO_PROGRAM:
+                vec = BOOK3S_INTERRUPT_PROGRAM;
+                break;
+        case BOOK3S_IRQPRIO_VSX:
+                vec = BOOK3S_INTERRUPT_VSX;
+                break;
+        case BOOK3S_IRQPRIO_ALTIVEC:
+                vec = BOOK3S_INTERRUPT_ALTIVEC;
+                break;
+        case BOOK3S_IRQPRIO_FP_UNAVAIL:
+                vec = BOOK3S_INTERRUPT_FP_UNAVAIL;
+                break;
+        case BOOK3S_IRQPRIO_SYSCALL:
+                vec = BOOK3S_INTERRUPT_SYSCALL;
+                break;
+        case BOOK3S_IRQPRIO_DEBUG:
+                vec = BOOK3S_INTERRUPT_TRACE;
+                break;
+        case BOOK3S_IRQPRIO_PERFORMANCE_MONITOR:
+                vec = BOOK3S_INTERRUPT_PERFMON;
+                break;
+        default:
+                deliver = 0;
+                printk(KERN_ERR "KVM: Unknown interrupt: 0x%x\n", priority);
+                break;
+        }
+
+#if 0
+        printk(KERN_INFO "Deliver interrupt 0x%x? %x\n", vec, deliver);
+#endif
+
+        if (deliver)
+                kvmppc_inject_interrupt(vcpu, vec, 0ULL);
+
+        return deliver;
+}
+
+void kvmppc_core_deliver_interrupts(struct kvm_vcpu *vcpu)
+{
+        unsigned long *pending = &vcpu->arch.pending_exceptions;
+        unsigned int priority;
+
+        /* XXX be more clever here - no need to mftb() on every entry */
+        /* Issue DEC again if it's still active */
+#ifdef AGGRESSIVE_DEC
+        if (vcpu->arch.msr & MSR_EE)
+                if (kvmppc_get_dec(vcpu) & 0x80000000)
+                        kvmppc_core_queue_dec(vcpu);
+#endif
+
+#ifdef EXIT_DEBUG
+        if (vcpu->arch.pending_exceptions)
+                printk(KERN_EMERG "KVM: Check pending: %lx\n", vcpu->arch.pending_exceptions);
+#endif
+        priority = __ffs(*pending);
+        while (priority <= (sizeof(unsigned int) * 8)) {
+                if (kvmppc_book3s_irqprio_deliver(vcpu, priority)) {
+                        clear_bit(priority, &vcpu->arch.pending_exceptions);
+                        break;
+                }
+
+                priority = find_next_bit(pending,
+                                         BITS_PER_BYTE * sizeof(*pending),
+                                         priority + 1);
+        }
+}
+
+void kvmppc_set_pvr(struct kvm_vcpu *vcpu, u32 pvr)
+{
+        vcpu->arch.hflags &= ~BOOK3S_HFLAG_SLB;
+        vcpu->arch.pvr = pvr;
+        if ((pvr >= 0x330000) && (pvr < 0x70330000)) {
+                kvmppc_mmu_book3s_64_init(vcpu);
+                to_book3s(vcpu)->hior = 0xfff00000;
+                to_book3s(vcpu)->msr_mask = 0xffffffffffffffffULL;
+        } else {
+                kvmppc_mmu_book3s_32_init(vcpu);
+                to_book3s(vcpu)->hior = 0;
+                to_book3s(vcpu)->msr_mask = 0xffffffffULL;
+        }
+
+        /* If we are in hypervisor level on 970, we can tell the CPU to
+         * treat DCBZ as 32 bytes store */
+        vcpu->arch.hflags &= ~BOOK3S_HFLAG_DCBZ32;
+        if (vcpu->arch.mmu.is_dcbz32(vcpu) && (mfmsr() & MSR_HV) &&
+            !strcmp(cur_cpu_spec->platform, "ppc970"))
+                vcpu->arch.hflags |= BOOK3S_HFLAG_DCBZ32;
+
+}
+
+/* Book3s_32 CPUs always have 32 bytes cache line size, which Linux assumes. To
+ * make Book3s_32 Linux work on Book3s_64, we have to make sure we trap dcbz to
+ * emulate 32 bytes dcbz length.
+ *
+ * The Book3s_64 inventors also realized this case and implemented a special bit
+ * in the HID5 register, which is a hypervisor ressource. Thus we can't use it.
+ *
+ * My approach here is to patch the dcbz instruction on executing pages.
+ */
+static void kvmppc_patch_dcbz(struct kvm_vcpu *vcpu, struct kvmppc_pte *pte)
+{
+        bool touched = false;
+        hva_t hpage;
+        u32 *page;
+        int i;
+
+        hpage = gfn_to_hva(vcpu->kvm, pte->raddr >> PAGE_SHIFT);
+        if (kvm_is_error_hva(hpage))
+                return;
+
+        hpage |= pte->raddr & ~PAGE_MASK;
+        hpage &= ~0xFFFULL;
+
+        page = vmalloc(HW_PAGE_SIZE);
+
+        if (copy_from_user(page, (void __user *)hpage, HW_PAGE_SIZE))
+                goto out;
+
+        for (i=0; i < HW_PAGE_SIZE / 4; i++)
+                if ((page[i] & 0xff0007ff) == INS_DCBZ) {
+                        page[i] &= 0xfffffff7; // reserved instruction, so we trap
+                        touched = true;
+                }
+
+        if (touched)
+                copy_to_user((void __user *)hpage, page, HW_PAGE_SIZE);
+
+out:
+        vfree(page);
+}
+
+static int kvmppc_xlate(struct kvm_vcpu *vcpu, ulong eaddr, bool data,
+                         struct kvmppc_pte *pte)
+{
+        int relocated = (vcpu->arch.msr & (data ? MSR_DR : MSR_IR));
+        int r;
+
+        if (relocated) {
+                r = vcpu->arch.mmu.xlate(vcpu, eaddr, pte, data);
+        } else {
+                pte->eaddr = eaddr;
+                pte->raddr = eaddr & 0xffffffff;
+                pte->vpage = eaddr >> 12;
+                switch (vcpu->arch.msr & (MSR_DR|MSR_IR)) {
+                case 0:
+                        pte->vpage |= VSID_REAL;
+                case MSR_DR:
+                        pte->vpage |= VSID_REAL_DR;
+                case MSR_IR:
+                        pte->vpage |= VSID_REAL_IR;
+                }
+                pte->may_read = true;
+                pte->may_write = true;
+                pte->may_execute = true;
+                r = 0;
+        }
+
+        return r;
+}
+
+static hva_t kvmppc_bad_hva(void)
+{
+        return PAGE_OFFSET;
+}
+
+static hva_t kvmppc_pte_to_hva(struct kvm_vcpu *vcpu, struct kvmppc_pte *pte,
+                               bool read)
+{
+        hva_t hpage;
+
+        if (read && !pte->may_read)
+                goto err;
+
+        if (!read && !pte->may_write)
+                goto err;
+
+        hpage = gfn_to_hva(vcpu->kvm, pte->raddr >> PAGE_SHIFT);
+        if (kvm_is_error_hva(hpage))
+                goto err;
+
+        return hpage | (pte->raddr & ~PAGE_MASK);
+err:
+        return kvmppc_bad_hva();
+}
+
+int kvmppc_st(struct kvm_vcpu *vcpu, ulong eaddr, int size, void *ptr)
+{
+        struct kvmppc_pte pte;
+        hva_t hva = eaddr;
+
+        vcpu->stat.st++;
+
+        if (kvmppc_xlate(vcpu, eaddr, false, &pte))
+                goto err;
+
+        hva = kvmppc_pte_to_hva(vcpu, &pte, false);
+        if (kvm_is_error_hva(hva))
+                goto err;
+
+        if (copy_to_user((void __user *)hva, ptr, size)) {
+                printk(KERN_INFO "kvmppc_st at 0x%lx failed\n", hva);
+                goto err;
+        }
+
+        return 0;
+
+err:
+        return -ENOENT;
+}
+
+int kvmppc_ld(struct kvm_vcpu *vcpu, ulong eaddr, int size, void *ptr,
+                      bool data)
+{
+        struct kvmppc_pte pte;
+        hva_t hva = eaddr;
+
+        vcpu->stat.ld++;
+
+        if (kvmppc_xlate(vcpu, eaddr, data, &pte))
+                goto err;
+
+        hva = kvmppc_pte_to_hva(vcpu, &pte, true);
+        if (kvm_is_error_hva(hva))
+                goto err;
+
+        if (copy_from_user(ptr, (void __user *)hva, size)) {
+                printk(KERN_INFO "kvmppc_ld at 0x%lx failed\n", hva);
+                goto err;
+        }
+
+        return 0;
+
+err:
+        return -ENOENT;
+}
+
+static int kvmppc_visible_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
+{
+        return kvm_is_visible_gfn(vcpu->kvm, gfn);
+}
+
+int kvmppc_handle_pagefault(struct kvm_run *run, struct kvm_vcpu *vcpu,
+                            ulong eaddr, int vec)
+{
+        bool data = (vec == BOOK3S_INTERRUPT_DATA_STORAGE);
+        int r = RESUME_GUEST;
+        int relocated;
+        int page_found = 0;
+        struct kvmppc_pte pte;
+        bool is_mmio = false;
+
+        if ( vec == BOOK3S_INTERRUPT_DATA_STORAGE ) {
+                relocated = (vcpu->arch.msr & MSR_DR);
+        } else {
+                relocated = (vcpu->arch.msr & MSR_IR);
+        }
+
+        /* Resolve real address if translation turned on */
+        if (relocated) {
+                page_found = vcpu->arch.mmu.xlate(vcpu, eaddr, &pte, data);
+        } else {
+                pte.may_execute = true;
+                pte.may_read = true;
+                pte.may_write = true;
+                pte.raddr = eaddr & 0xffffffff;
+                pte.eaddr = eaddr;
+                pte.vpage = eaddr >> 12;
+                switch (vcpu->arch.msr & (MSR_DR|MSR_IR)) {
+                case 0:
+                        pte.vpage |= VSID_REAL;
+                case MSR_DR:
+                        pte.vpage |= VSID_REAL_DR;
+                case MSR_IR:
+                        pte.vpage |= VSID_REAL_IR;
+                }
+        }
+
+        if (vcpu->arch.mmu.is_dcbz32(vcpu) &&
+           (!(vcpu->arch.hflags & BOOK3S_HFLAG_DCBZ32))) {
+                /*
+                 * If we do the dcbz hack, we have to NX on every execution,
+                 * so we can patch the executing code. This renders our guest
+                 * NX-less.
+                 */
+                pte.may_execute = !data;
+        }
+
+        if (page_found == -ENOENT) {
+                /* Page not found in guest PTE entries */
+                vcpu->arch.dear = vcpu->arch.fault_dear;
+                to_book3s(vcpu)->dsisr = vcpu->arch.fault_dsisr;
+                vcpu->arch.msr |= (vcpu->arch.shadow_msr & 0x00000000f8000000ULL);
+                kvmppc_book3s_queue_irqprio(vcpu, vec);
+        } else if (page_found == -EPERM) {
+                /* Storage protection */
+                vcpu->arch.dear = vcpu->arch.fault_dear;
+                to_book3s(vcpu)->dsisr = vcpu->arch.fault_dsisr & ~DSISR_NOHPTE;
+                to_book3s(vcpu)->dsisr |= DSISR_PROTFAULT;
+                vcpu->arch.msr |= (vcpu->arch.shadow_msr & 0x00000000f8000000ULL);
+                kvmppc_book3s_queue_irqprio(vcpu, vec);
+        } else if (page_found == -EINVAL) {
+                /* Page not found in guest SLB */
+                vcpu->arch.dear = vcpu->arch.fault_dear;
+                kvmppc_book3s_queue_irqprio(vcpu, vec + 0x80);
+        } else if (!is_mmio &&
+                   kvmppc_visible_gfn(vcpu, pte.raddr >> PAGE_SHIFT)) {
+                /* The guest's PTE is not mapped yet. Map on the host */
+                kvmppc_mmu_map_page(vcpu, &pte);
+                if (data)
+                        vcpu->stat.sp_storage++;
+                else if (vcpu->arch.mmu.is_dcbz32(vcpu) &&
+                        (!(vcpu->arch.hflags & BOOK3S_HFLAG_DCBZ32)))
+                        kvmppc_patch_dcbz(vcpu, &pte);
+        } else {
+                /* MMIO */
+                vcpu->stat.mmio_exits++;
+                vcpu->arch.paddr_accessed = pte.raddr;
+                r = kvmppc_emulate_mmio(run, vcpu);
+                if ( r == RESUME_HOST_NV )
+                        r = RESUME_HOST;
+                if ( r == RESUME_GUEST_NV )
+                        r = RESUME_GUEST;
+        }
+
+        return r;
+}
+
+int kvmppc_handle_exit(struct kvm_run *run, struct kvm_vcpu *vcpu,
+                       unsigned int exit_nr)
+{
+        int r = RESUME_HOST;
+
+        vcpu->stat.sum_exits++;
+
+        run->exit_reason = KVM_EXIT_UNKNOWN;
+        run->ready_for_interrupt_injection = 1;
+#ifdef EXIT_DEBUG
+        printk(KERN_EMERG "exit_nr=0x%x | pc=0x%lx | dar=0x%lx | dec=0x%x | msr=0x%lx\n",
+                exit_nr, vcpu->arch.pc, vcpu->arch.fault_dear,
+                kvmppc_get_dec(vcpu), vcpu->arch.msr);
+#elif defined (EXIT_DEBUG_SIMPLE)
+        if ((exit_nr != 0x900) && (exit_nr != 0x500))
+                printk(KERN_EMERG "exit_nr=0x%x | pc=0x%lx | dar=0x%lx | msr=0x%lx\n",
+                        exit_nr, vcpu->arch.pc, vcpu->arch.fault_dear,
+                        vcpu->arch.msr);
+#endif
+        kvm_resched(vcpu);
+        switch (exit_nr) {
+        case BOOK3S_INTERRUPT_INST_STORAGE:
+                vcpu->stat.pf_instruc++;
+                /* only care about PTEG not found errors, but leave NX alone */
+                if (vcpu->arch.shadow_msr & 0x40000000) {
+                        r = kvmppc_handle_pagefault(run, vcpu, vcpu->arch.pc, exit_nr);
+                        vcpu->stat.sp_instruc++;
+                } else if (vcpu->arch.mmu.is_dcbz32(vcpu) &&
+                          (!(vcpu->arch.hflags & BOOK3S_HFLAG_DCBZ32))) {
+                        /*
+                         * XXX If we do the dcbz hack we use the NX bit to flush&patch the page,
+                         *     so we can't use the NX bit inside the guest. Let's cross our fingers,
+                         *     that no guest that needs the dcbz hack does NX.
+                         */
+                        kvmppc_mmu_pte_flush(vcpu, vcpu->arch.pc, ~0xFFFULL);
+                } else {
+                        vcpu->arch.msr |= (vcpu->arch.shadow_msr & 0x58000000);
+                        kvmppc_book3s_queue_irqprio(vcpu, exit_nr);
+                        kvmppc_mmu_pte_flush(vcpu, vcpu->arch.pc, ~0xFFFULL);
+                        r = RESUME_GUEST;
+                }
+                break;
+        case BOOK3S_INTERRUPT_DATA_STORAGE:
+                vcpu->stat.pf_storage++;
+                /* The only case we need to handle is missing shadow PTEs */
+                if (vcpu->arch.fault_dsisr & DSISR_NOHPTE) {
+                        r = kvmppc_handle_pagefault(run, vcpu, vcpu->arch.fault_dear, exit_nr);
+                } else {
+                        vcpu->arch.dear = vcpu->arch.fault_dear;
+                        to_book3s(vcpu)->dsisr = vcpu->arch.fault_dsisr;
+                        kvmppc_book3s_queue_irqprio(vcpu, exit_nr);
+                        kvmppc_mmu_pte_flush(vcpu, vcpu->arch.dear, ~0xFFFULL);
+                        r = RESUME_GUEST;
+                }
+                break;
+        case BOOK3S_INTERRUPT_DATA_SEGMENT:
+                if (kvmppc_mmu_map_segment(vcpu, vcpu->arch.fault_dear) < 0) {
+                        vcpu->arch.dear = vcpu->arch.fault_dear;
+                        kvmppc_book3s_queue_irqprio(vcpu,
+                                BOOK3S_INTERRUPT_DATA_SEGMENT);
+                }
+                r = RESUME_GUEST;
+                break;
+        case BOOK3S_INTERRUPT_INST_SEGMENT:
+                if (kvmppc_mmu_map_segment(vcpu, vcpu->arch.pc) < 0) {
+                        kvmppc_book3s_queue_irqprio(vcpu,
+                                BOOK3S_INTERRUPT_INST_SEGMENT);
+                }
+                r = RESUME_GUEST;
+                break;
+        /* We're good on these - the host merely wanted to get our attention */
+        case BOOK3S_INTERRUPT_DECREMENTER:
+                vcpu->stat.dec_exits++;
+                r = RESUME_GUEST;
+                break;
+        case BOOK3S_INTERRUPT_EXTERNAL:
+                vcpu->stat.ext_intr_exits++;
+                r = RESUME_GUEST;
+                break;
+        case BOOK3S_INTERRUPT_PROGRAM:
+        {
+                enum emulation_result er;
+
+                if (vcpu->arch.msr & MSR_PR) {
+#ifdef EXIT_DEBUG
+                        printk(KERN_INFO "Userspace triggered 0x700 exception at 0x%lx (0x%x)\n", vcpu->arch.pc, vcpu->arch.last_inst);
+#endif
+                        if ((vcpu->arch.last_inst & 0xff0007ff) !=
+                            (INS_DCBZ & 0xfffffff7)) {
+                                kvmppc_book3s_queue_irqprio(vcpu, exit_nr);
+                                r = RESUME_GUEST;
+                                break;
+                        }
+                }
+
+                vcpu->stat.emulated_inst_exits++;
+                er = kvmppc_emulate_instruction(run, vcpu);
+                switch (er) {
+                case EMULATE_DONE:
+                        r = RESUME_GUEST;
+                        break;
+                case EMULATE_FAIL:
+                        printk(KERN_CRIT "%s: emulation at %lx failed (%08x)\n",
+                               __func__, vcpu->arch.pc, vcpu->arch.last_inst);
+                        kvmppc_book3s_queue_irqprio(vcpu, exit_nr);
+                        r = RESUME_GUEST;
+                        break;
+                default:
+                        BUG();
+                }
+                break;
+        }
+        case BOOK3S_INTERRUPT_SYSCALL:
+#ifdef EXIT_DEBUG
+                printk(KERN_INFO "Syscall Nr %d\n", (int)vcpu->arch.gpr[0]);
+#endif
+                vcpu->stat.syscall_exits++;
+                kvmppc_book3s_queue_irqprio(vcpu, exit_nr);
+                r = RESUME_GUEST;
+                break;
+        case BOOK3S_INTERRUPT_MACHINE_CHECK:
+        case BOOK3S_INTERRUPT_FP_UNAVAIL:
+        case BOOK3S_INTERRUPT_TRACE:
+        case BOOK3S_INTERRUPT_ALTIVEC:
+        case BOOK3S_INTERRUPT_VSX:
+                kvmppc_book3s_queue_irqprio(vcpu, exit_nr);
+                r = RESUME_GUEST;
+                break;
+        default:
+                /* Ugh - bork here! What did we get? */
+                printk(KERN_EMERG "exit_nr=0x%x | pc=0x%lx | msr=0x%lx\n", exit_nr, vcpu->arch.pc, vcpu->arch.shadow_msr);
+                r = RESUME_HOST;
+                BUG();
+                break;
+        }
+
+
+        if (!(r & RESUME_HOST)) {
+                /* To avoid clobbering exit_reason, only check for signals if
+                 * we aren't already exiting to userspace for some other
+                 * reason. */
+                if (signal_pending(current)) {
+#ifdef EXIT_DEBUG
+                        printk(KERN_EMERG "KVM: Going back to host\n");
+#endif
+                        vcpu->stat.signal_exits++;
+                        run->exit_reason = KVM_EXIT_INTR;
+                        r = -EINTR;
+                } else {
+                        /* In case an interrupt came in that was triggered
+                         * from userspace (like DEC), we need to check what
+                         * to inject now! */
+                        kvmppc_core_deliver_interrupts(vcpu);
+                }
+        }
+
+#ifdef EXIT_DEBUG
+        printk(KERN_EMERG "KVM exit: vcpu=0x%p pc=0x%lx r=0x%x\n", vcpu, vcpu->arch.pc, r);
+#endif
+
+        return r;
+}
+
+int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
+{
+        return 0;
+}
+
+int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
+{
+        int i;
+
+        regs->pc = vcpu->arch.pc;
+        regs->cr = vcpu->arch.cr;
+        regs->ctr = vcpu->arch.ctr;
+        regs->lr = vcpu->arch.lr;
+        regs->xer = vcpu->arch.xer;
+        regs->msr = vcpu->arch.msr;
+        regs->srr0 = vcpu->arch.srr0;
+        regs->srr1 = vcpu->arch.srr1;
+        regs->pid = vcpu->arch.pid;
+        regs->sprg0 = vcpu->arch.sprg0;
+        regs->sprg1 = vcpu->arch.sprg1;
+        regs->sprg2 = vcpu->arch.sprg2;
+        regs->sprg3 = vcpu->arch.sprg3;
+        regs->sprg5 = vcpu->arch.sprg4;
+        regs->sprg6 = vcpu->arch.sprg5;
+        regs->sprg7 = vcpu->arch.sprg6;
+
+        for (i = 0; i < ARRAY_SIZE(regs->gpr); i++)
+                regs->gpr[i] = vcpu->arch.gpr[i];
+
+        return 0;
+}
+
+int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
+{
+        int i;
+
+        vcpu->arch.pc = regs->pc;
+        vcpu->arch.cr = regs->cr;
+        vcpu->arch.ctr = regs->ctr;
+        vcpu->arch.lr = regs->lr;
+        vcpu->arch.xer = regs->xer;
+        kvmppc_set_msr(vcpu, regs->msr);
+        vcpu->arch.srr0 = regs->srr0;
+        vcpu->arch.srr1 = regs->srr1;
+        vcpu->arch.sprg0 = regs->sprg0;
+        vcpu->arch.sprg1 = regs->sprg1;
+        vcpu->arch.sprg2 = regs->sprg2;
+        vcpu->arch.sprg3 = regs->sprg3;
+        vcpu->arch.sprg5 = regs->sprg4;
+        vcpu->arch.sprg6 = regs->sprg5;
+        vcpu->arch.sprg7 = regs->sprg6;
+
+        for (i = 0; i < ARRAY_SIZE(vcpu->arch.gpr); i++)
+                vcpu->arch.gpr[i] = regs->gpr[i];
+
+        return 0;
+}
+
+int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
+                                  struct kvm_sregs *sregs)
+{
+        struct kvmppc_vcpu_book3s *vcpu3s = to_book3s(vcpu);
+        int i;
+
+        sregs->pvr = vcpu->arch.pvr;
+
+        sregs->u.s.sdr1 = to_book3s(vcpu)->sdr1;
+        if (vcpu->arch.hflags & BOOK3S_HFLAG_SLB) {
+                for (i = 0; i < 64; i++) {
+                        sregs->u.s.ppc64.slb[i].slbe = vcpu3s->slb[i].orige | i;
+                        sregs->u.s.ppc64.slb[i].slbv = vcpu3s->slb[i].origv;
+                }
+        } else {
+                for (i = 0; i < 16; i++) {
+                        sregs->u.s.ppc32.sr[i] = vcpu3s->sr[i].raw;
+                        sregs->u.s.ppc32.sr[i] = vcpu3s->sr[i].raw;
+                }
+                for (i = 0; i < 8; i++) {
+                        sregs->u.s.ppc32.ibat[i] = vcpu3s->ibat[i].raw;
+                        sregs->u.s.ppc32.dbat[i] = vcpu3s->dbat[i].raw;
+                }
+        }
+        return 0;
+}
+
+int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
+                                  struct kvm_sregs *sregs)
+{
+        struct kvmppc_vcpu_book3s *vcpu3s = to_book3s(vcpu);
+        int i;
+
+        kvmppc_set_pvr(vcpu, sregs->pvr);
+
+        vcpu3s->sdr1 = sregs->u.s.sdr1;
+        if (vcpu->arch.hflags & BOOK3S_HFLAG_SLB) {
+                for (i = 0; i < 64; i++) {
+                        vcpu->arch.mmu.slbmte(vcpu, sregs->u.s.ppc64.slb[i].slbv,
+                                                    sregs->u.s.ppc64.slb[i].slbe);
+                }
+        } else {
+                for (i = 0; i < 16; i++) {
+                        vcpu->arch.mmu.mtsrin(vcpu, i, sregs->u.s.ppc32.sr[i]);
+                }
+                for (i = 0; i < 8; i++) {
+                        kvmppc_set_bat(vcpu, &(vcpu3s->ibat[i]), false,
+                                       (u32)sregs->u.s.ppc32.ibat[i]);
+                        kvmppc_set_bat(vcpu, &(vcpu3s->ibat[i]), true,
+                                       (u32)(sregs->u.s.ppc32.ibat[i] >> 32));
+                        kvmppc_set_bat(vcpu, &(vcpu3s->dbat[i]), false,
+                                       (u32)sregs->u.s.ppc32.dbat[i]);
+                        kvmppc_set_bat(vcpu, &(vcpu3s->dbat[i]), true,
+                                       (u32)(sregs->u.s.ppc32.dbat[i] >> 32));
+                }
+        }
+
+        /* Flush the MMU after messing with the segments */
+        kvmppc_mmu_pte_flush(vcpu, 0, 0);
+        return 0;
+}
+
+int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
+{
+        return -ENOTSUPP;
+}
+
+int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
+{
+        return -ENOTSUPP;
+}
+
+int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
+                                  struct kvm_translation *tr)
+{
+        return 0;
+}
+
+/*
+ * Get (and clear) the dirty memory log for a memory slot.
+ */
+int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm,
+                                      struct kvm_dirty_log *log)
+{
+        struct kvm_memory_slot *memslot;
+        struct kvm_vcpu *vcpu;
+        ulong ga, ga_end;
+        int is_dirty = 0;
+        int r, n;
+
+        down_write(&kvm->slots_lock);
+
+        r = kvm_get_dirty_log(kvm, log, &is_dirty);
+        if (r)
+                goto out;
+
+        /* If nothing is dirty, don't bother messing with page tables. */
+        if (is_dirty) {
+                memslot = &kvm->memslots[log->slot];
+
+                ga = memslot->base_gfn << PAGE_SHIFT;
+                ga_end = ga + (memslot->npages << PAGE_SHIFT);
+
+                kvm_for_each_vcpu(n, vcpu, kvm)
+                        kvmppc_mmu_pte_pflush(vcpu, ga, ga_end);
+
+                n = ALIGN(memslot->npages, BITS_PER_LONG) / 8;
+                memset(memslot->dirty_bitmap, 0, n);
+        }
+
+        r = 0;
+out:
+        up_write(&kvm->slots_lock);
+        return r;
+}
+
+int kvmppc_core_check_processor_compat(void)
+{
+        return 0;
+}
+
+struct kvm_vcpu *kvmppc_core_vcpu_create(struct kvm *kvm, unsigned int id)
+{
+        struct kvmppc_vcpu_book3s *vcpu_book3s;
+        struct kvm_vcpu *vcpu;
+        int err;
+
+        vcpu_book3s = (struct kvmppc_vcpu_book3s *)__get_free_pages( GFP_KERNEL | __GFP_ZERO,
+                        get_order(sizeof(struct kvmppc_vcpu_book3s)));
+        if (!vcpu_book3s) {
+                err = -ENOMEM;
+                goto out;
+        }
+
+        vcpu = &vcpu_book3s->vcpu;
+        err = kvm_vcpu_init(vcpu, kvm, id);
+        if (err)
+                goto free_vcpu;
+
+        vcpu->arch.host_retip = kvm_return_point;
+        vcpu->arch.host_msr = mfmsr();
+        /* default to book3s_64 (970fx) */
+        vcpu->arch.pvr = 0x3C0301;
+        kvmppc_set_pvr(vcpu, vcpu->arch.pvr);
+        vcpu_book3s->slb_nr = 64;
+
+        /* remember where some real-mode handlers are */
+        vcpu->arch.trampoline_lowmem = kvmppc_trampoline_lowmem;
+        vcpu->arch.trampoline_enter = kvmppc_trampoline_enter;
+        vcpu->arch.highmem_handler = (ulong)kvmppc_handler_highmem;
+
+        vcpu->arch.shadow_msr = MSR_USER64;
+
+        err = __init_new_context();
+        if (err < 0)
+                goto free_vcpu;
+        vcpu_book3s->context_id = err;
+
+        vcpu_book3s->vsid_max = ((vcpu_book3s->context_id + 1) << USER_ESID_BITS) - 1;
+        vcpu_book3s->vsid_first = vcpu_book3s->context_id << USER_ESID_BITS;
+        vcpu_book3s->vsid_next = vcpu_book3s->vsid_first;
+
+        return vcpu;
+
+free_vcpu:
+        free_pages((long)vcpu_book3s, get_order(sizeof(struct kvmppc_vcpu_book3s)));
+out:
+        return ERR_PTR(err);
+}
+
+void kvmppc_core_vcpu_free(struct kvm_vcpu *vcpu)
+{
+        struct kvmppc_vcpu_book3s *vcpu_book3s = to_book3s(vcpu);
+
+        __destroy_context(vcpu_book3s->context_id);
+        kvm_vcpu_uninit(vcpu);
+        free_pages((long)vcpu_book3s, get_order(sizeof(struct kvmppc_vcpu_book3s)));
+}
+
+extern int __kvmppc_vcpu_entry(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu);
+int __kvmppc_vcpu_run(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu)
+{
+        int ret;
+
+        /* No need to go into the guest when all we do is going out */
+        if (signal_pending(current)) {
+                kvm_run->exit_reason = KVM_EXIT_INTR;
+                return -EINTR;
+        }
+
+        /* XXX we get called with irq disabled - change that! */
+        local_irq_enable();
+
+        ret = __kvmppc_vcpu_entry(kvm_run, vcpu);
+
+        local_irq_disable();
+
+        return ret;
+}
+
+static int kvmppc_book3s_init(void)
+{
+        return kvm_init(NULL, sizeof(struct kvmppc_vcpu_book3s), THIS_MODULE);
+}
+
+static void kvmppc_book3s_exit(void)
+{
+        kvm_exit();
+}
+
+module_init(kvmppc_book3s_init);
+module_exit(kvmppc_book3s_exit);
diff --git a/arch/powerpc/kvm/book3s_32_mmu.c b/arch/powerpc/kvm/book3s_32_mmu.c
new file mode 100644
index 000000000000..faf99f20d993
--- /dev/null
+++ b/arch/powerpc/kvm/book3s_32_mmu.c
@@ -0,0 +1,372 @@
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ *
+ * Copyright SUSE Linux Products GmbH 2009
+ *
+ * Authors: Alexander Graf <agraf@suse.de>
+ */
+
+#include <linux/types.h>
+#include <linux/string.h>
+#include <linux/kvm.h>
+#include <linux/kvm_host.h>
+#include <linux/highmem.h>
+
+#include <asm/tlbflush.h>
+#include <asm/kvm_ppc.h>
+#include <asm/kvm_book3s.h>
+
+/* #define DEBUG_MMU */
+/* #define DEBUG_MMU_PTE */
+/* #define DEBUG_MMU_PTE_IP 0xfff14c40 */
+
+#ifdef DEBUG_MMU
+#define dprintk(X...) printk(KERN_INFO X)
+#else
+#define dprintk(X...) do { } while(0)
+#endif
+
+#ifdef DEBUG_PTE
+#define dprintk_pte(X...) printk(KERN_INFO X)
+#else
+#define dprintk_pte(X...) do { } while(0)
+#endif
+
+#define PTEG_FLAG_ACCESSED      0x00000100
+#define PTEG_FLAG_DIRTY         0x00000080
+
+static inline bool check_debug_ip(struct kvm_vcpu *vcpu)
+{
+#ifdef DEBUG_MMU_PTE_IP
+        return vcpu->arch.pc == DEBUG_MMU_PTE_IP;
+#else
+        return true;
+#endif
+}
+
+static int kvmppc_mmu_book3s_32_xlate_bat(struct kvm_vcpu *vcpu, gva_t eaddr,
+                                          struct kvmppc_pte *pte, bool data);
+
+static struct kvmppc_sr *find_sr(struct kvmppc_vcpu_book3s *vcpu_book3s, gva_t eaddr)
+{
+        return &vcpu_book3s->sr[(eaddr >> 28) & 0xf];
+}
+
+static u64 kvmppc_mmu_book3s_32_ea_to_vp(struct kvm_vcpu *vcpu, gva_t eaddr,
+                                         bool data)
+{
+        struct kvmppc_sr *sre = find_sr(to_book3s(vcpu), eaddr);
+        struct kvmppc_pte pte;
+
+        if (!kvmppc_mmu_book3s_32_xlate_bat(vcpu, eaddr, &pte, data))
+                return pte.vpage;
+
+        return (((u64)eaddr >> 12) & 0xffff) | (((u64)sre->vsid) << 16);
+}
+
+static void kvmppc_mmu_book3s_32_reset_msr(struct kvm_vcpu *vcpu)
+{
+        kvmppc_set_msr(vcpu, 0);
+}
+
+static hva_t kvmppc_mmu_book3s_32_get_pteg(struct kvmppc_vcpu_book3s *vcpu_book3s,
+                                      struct kvmppc_sr *sre, gva_t eaddr,
+                                      bool primary)
+{
+        u32 page, hash, pteg, htabmask;
+        hva_t r;
+
+        page = (eaddr & 0x0FFFFFFF) >> 12;
+        htabmask = ((vcpu_book3s->sdr1 & 0x1FF) << 16) | 0xFFC0;
+
+        hash = ((sre->vsid ^ page) << 6);
+        if (!primary)
+                hash = ~hash;
+        hash &= htabmask;
+
+        pteg = (vcpu_book3s->sdr1 & 0xffff0000) | hash;
+
+        dprintk("MMU: pc=0x%lx eaddr=0x%lx sdr1=0x%llx pteg=0x%x vsid=0x%x\n",
+                vcpu_book3s->vcpu.arch.pc, eaddr, vcpu_book3s->sdr1, pteg,
+                sre->vsid);
+
+        r = gfn_to_hva(vcpu_book3s->vcpu.kvm, pteg >> PAGE_SHIFT);
+        if (kvm_is_error_hva(r))
+                return r;
+        return r | (pteg & ~PAGE_MASK);
+}
+
+static u32 kvmppc_mmu_book3s_32_get_ptem(struct kvmppc_sr *sre, gva_t eaddr,
+                                    bool primary)
+{
+        return ((eaddr & 0x0fffffff) >> 22) | (sre->vsid << 7) |
+               (primary ? 0 : 0x40) | 0x80000000;
+}
+
+static int kvmppc_mmu_book3s_32_xlate_bat(struct kvm_vcpu *vcpu, gva_t eaddr,
+                                          struct kvmppc_pte *pte, bool data)
+{
+        struct kvmppc_vcpu_book3s *vcpu_book3s = to_book3s(vcpu);
+        struct kvmppc_bat *bat;
+        int i;
+
+        for (i = 0; i < 8; i++) {
+                if (data)
+                        bat = &vcpu_book3s->dbat[i];
+                else
+                        bat = &vcpu_book3s->ibat[i];
+
+                if (vcpu->arch.msr & MSR_PR) {
+                        if (!bat->vp)
+                                continue;
+                } else {
+                        if (!bat->vs)
+                                continue;
+                }
+
+                if (check_debug_ip(vcpu))
+                {
+                        dprintk_pte("%cBAT %02d: 0x%lx - 0x%x (0x%x)\n",
+                                    data ? 'd' : 'i', i, eaddr, bat->bepi,
+                                    bat->bepi_mask);
+                }
+                if ((eaddr & bat->bepi_mask) == bat->bepi) {
+                        pte->raddr = bat->brpn | (eaddr & ~bat->bepi_mask);
+                        pte->vpage = (eaddr >> 12) | VSID_BAT;
+                        pte->may_read = bat->pp;
+                        pte->may_write = bat->pp > 1;
+                        pte->may_execute = true;
+                        if (!pte->may_read) {
+                                printk(KERN_INFO "BAT is not readable!\n");
+                                continue;
+                        }
+                        if (!pte->may_write) {
+                                /* let's treat r/o BATs as not-readable for now */
+                                dprintk_pte("BAT is read-only!\n");
+                                continue;
+                        }
+
+                        return 0;
+                }
+        }
+
+        return -ENOENT;
+}
+
+static int kvmppc_mmu_book3s_32_xlate_pte(struct kvm_vcpu *vcpu, gva_t eaddr,
+                                     struct kvmppc_pte *pte, bool data,
+                                     bool primary)
+{
+        struct kvmppc_vcpu_book3s *vcpu_book3s = to_book3s(vcpu);
+        struct kvmppc_sr *sre;
+        hva_t ptegp;
+        u32 pteg[16];
+        u64 ptem = 0;
+        int i;
+        int found = 0;
+
+        sre = find_sr(vcpu_book3s, eaddr);
+
+        dprintk_pte("SR 0x%lx: vsid=0x%x, raw=0x%x\n", eaddr >> 28,
+                    sre->vsid, sre->raw);
+
+        pte->vpage = kvmppc_mmu_book3s_32_ea_to_vp(vcpu, eaddr, data);
+
+        ptegp = kvmppc_mmu_book3s_32_get_pteg(vcpu_book3s, sre, eaddr, primary);
+        if (kvm_is_error_hva(ptegp)) {
+                printk(KERN_INFO "KVM: Invalid PTEG!\n");
+                goto no_page_found;
+        }
+
+        ptem = kvmppc_mmu_book3s_32_get_ptem(sre, eaddr, primary);
+
+        if(copy_from_user(pteg, (void __user *)ptegp, sizeof(pteg))) {
+                printk(KERN_ERR "KVM: Can't copy data from 0x%lx!\n", ptegp);
+                goto no_page_found;
+        }
+
+        for (i=0; i<16; i+=2) {
+                if (ptem == pteg[i]) {
+                        u8 pp;
+
+                        pte->raddr = (pteg[i+1] & ~(0xFFFULL)) | (eaddr & 0xFFF);
+                        pp = pteg[i+1] & 3;
+
+                        if ((sre->Kp &&  (vcpu->arch.msr & MSR_PR)) ||
+                            (sre->Ks && !(vcpu->arch.msr & MSR_PR)))
+                                pp |= 4;
+
+                        pte->may_write = false;
+                        pte->may_read = false;
+                        pte->may_execute = true;
+                        switch (pp) {
+                                case 0:
+                                case 1:
+                                case 2:
+                                case 6:
+                                        pte->may_write = true;
+                                case 3:
+                                case 5:
+                                case 7:
+                                        pte->may_read = true;
+                                        break;
+                        }
+
+                        if ( !pte->may_read )
+                                continue;
+
+                        dprintk_pte("MMU: Found PTE -> %x %x - %x\n",
+                                    pteg[i], pteg[i+1], pp);
+                        found = 1;
+                        break;
+                }
+        }
+
+        /* Update PTE C and A bits, so the guest's swapper knows we used the
+           page */
+        if (found) {
+                u32 oldpte = pteg[i+1];
+
+                if (pte->may_read)
+                        pteg[i+1] |= PTEG_FLAG_ACCESSED;
+                if (pte->may_write)
+                        pteg[i+1] |= PTEG_FLAG_DIRTY;
+                else
+                        dprintk_pte("KVM: Mapping read-only page!\n");
+
+                /* Write back into the PTEG */
+                if (pteg[i+1] != oldpte)
+                        copy_to_user((void __user *)ptegp, pteg, sizeof(pteg));
+
+                return 0;
+        }
+
+no_page_found:
+
+        if (check_debug_ip(vcpu)) {
+                dprintk_pte("KVM MMU: No PTE found (sdr1=0x%llx ptegp=0x%lx)\n",
+                            to_book3s(vcpu)->sdr1, ptegp);
+                for (i=0; i<16; i+=2) {
+                        dprintk_pte("   %02d: 0x%x - 0x%x (0x%llx)\n",
+                                    i, pteg[i], pteg[i+1], ptem);
+                }
+        }
+
+        return -ENOENT;
+}
+
+static int kvmppc_mmu_book3s_32_xlate(struct kvm_vcpu *vcpu, gva_t eaddr,
+                                      struct kvmppc_pte *pte, bool data)
+{
+        int r;
+
+        pte->eaddr = eaddr;
+        r = kvmppc_mmu_book3s_32_xlate_bat(vcpu, eaddr, pte, data);
+        if (r < 0)
+               r = kvmppc_mmu_book3s_32_xlate_pte(vcpu, eaddr, pte, data, true);
+        if (r < 0)
+               r = kvmppc_mmu_book3s_32_xlate_pte(vcpu, eaddr, pte, data, false);
+
+        return r;
+}
+
+
+static u32 kvmppc_mmu_book3s_32_mfsrin(struct kvm_vcpu *vcpu, u32 srnum)
+{
+        return to_book3s(vcpu)->sr[srnum].raw;
+}
+
+static void kvmppc_mmu_book3s_32_mtsrin(struct kvm_vcpu *vcpu, u32 srnum,
+                                        ulong value)
+{
+        struct kvmppc_sr *sre;
+
+        sre = &to_book3s(vcpu)->sr[srnum];
+
+        /* Flush any left-over shadows from the previous SR */
+
+        /* XXX Not necessary? */
+        /* kvmppc_mmu_pte_flush(vcpu, ((u64)sre->vsid) << 28, 0xf0000000ULL); */
+
+        /* And then put in the new SR */
+        sre->raw = value;
+        sre->vsid = (value & 0x0fffffff);
+        sre->Ks = (value & 0x40000000) ? true : false;
+        sre->Kp = (value & 0x20000000) ? true : false;
+        sre->nx = (value & 0x10000000) ? true : false;
+
+        /* Map the new segment */
+        kvmppc_mmu_map_segment(vcpu, srnum << SID_SHIFT);
+}
+
+static void kvmppc_mmu_book3s_32_tlbie(struct kvm_vcpu *vcpu, ulong ea, bool large)
+{
+        kvmppc_mmu_pte_flush(vcpu, ea, ~0xFFFULL);
+}
+
+static int kvmppc_mmu_book3s_32_esid_to_vsid(struct kvm_vcpu *vcpu, u64 esid,
+                                             u64 *vsid)
+{
+        /* In case we only have one of MSR_IR or MSR_DR set, let's put
+           that in the real-mode context (and hope RM doesn't access
+           high memory) */
+        switch (vcpu->arch.msr & (MSR_DR|MSR_IR)) {
+        case 0:
+                *vsid = (VSID_REAL >> 16) | esid;
+                break;
+        case MSR_IR:
+                *vsid = (VSID_REAL_IR >> 16) | esid;
+                break;
+        case MSR_DR:
+                *vsid = (VSID_REAL_DR >> 16) | esid;
+                break;
+        case MSR_DR|MSR_IR:
+        {
+                ulong ea;
+                ea = esid << SID_SHIFT;
+                *vsid = find_sr(to_book3s(vcpu), ea)->vsid;
+                break;
+        }
+        default:
+                BUG();
+        }
+
+        return 0;
+}
+
+static bool kvmppc_mmu_book3s_32_is_dcbz32(struct kvm_vcpu *vcpu)
+{
+        return true;
+}
+
+
+void kvmppc_mmu_book3s_32_init(struct kvm_vcpu *vcpu)
+{
+        struct kvmppc_mmu *mmu = &vcpu->arch.mmu;
+
+        mmu->mtsrin = kvmppc_mmu_book3s_32_mtsrin;
+        mmu->mfsrin = kvmppc_mmu_book3s_32_mfsrin;
+        mmu->xlate = kvmppc_mmu_book3s_32_xlate;
+        mmu->reset_msr = kvmppc_mmu_book3s_32_reset_msr;
+        mmu->tlbie = kvmppc_mmu_book3s_32_tlbie;
+        mmu->esid_to_vsid = kvmppc_mmu_book3s_32_esid_to_vsid;
+        mmu->ea_to_vp = kvmppc_mmu_book3s_32_ea_to_vp;
+        mmu->is_dcbz32 = kvmppc_mmu_book3s_32_is_dcbz32;
+
+        mmu->slbmte = NULL;
+        mmu->slbmfee = NULL;
+        mmu->slbmfev = NULL;
+        mmu->slbie = NULL;
+        mmu->slbia = NULL;
+}
diff --git a/arch/powerpc/kvm/book3s_64_emulate.c b/arch/powerpc/kvm/book3s_64_emulate.c
new file mode 100644
index 000000000000..1027eac6d474
--- /dev/null
+++ b/arch/powerpc/kvm/book3s_64_emulate.c
@@ -0,0 +1,345 @@
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ *
+ * Copyright SUSE Linux Products GmbH 2009
+ *
+ * Authors: Alexander Graf <agraf@suse.de>
+ */
+
+#include <asm/kvm_ppc.h>
+#include <asm/disassemble.h>
+#include <asm/kvm_book3s.h>
+#include <asm/reg.h>
+
+#define OP_19_XOP_RFID          18
+#define OP_19_XOP_RFI           50
+
+#define OP_31_XOP_MFMSR         83
+#define OP_31_XOP_MTMSR         146
+#define OP_31_XOP_MTMSRD        178
+#define OP_31_XOP_MTSRIN        242
+#define OP_31_XOP_TLBIEL        274
+#define OP_31_XOP_TLBIE         306
+#define OP_31_XOP_SLBMTE        402
+#define OP_31_XOP_SLBIE         434
+#define OP_31_XOP_SLBIA         498
+#define OP_31_XOP_MFSRIN        659
+#define OP_31_XOP_SLBMFEV       851
+#define OP_31_XOP_EIOIO         854
+#define OP_31_XOP_SLBMFEE       915
+
+/* DCBZ is actually 1014, but we patch it to 1010 so we get a trap */
+#define OP_31_XOP_DCBZ          1010
+
+int kvmppc_core_emulate_op(struct kvm_run *run, struct kvm_vcpu *vcpu,
+                           unsigned int inst, int *advance)
+{
+        int emulated = EMULATE_DONE;
+
+        switch (get_op(inst)) {
+        case 19:
+                switch (get_xop(inst)) {
+                case OP_19_XOP_RFID:
+                case OP_19_XOP_RFI:
+                        vcpu->arch.pc = vcpu->arch.srr0;
+                        kvmppc_set_msr(vcpu, vcpu->arch.srr1);
+                        *advance = 0;
+                        break;
+
+                default:
+                        emulated = EMULATE_FAIL;
+                        break;
+                }
+                break;
+        case 31:
+                switch (get_xop(inst)) {
+                case OP_31_XOP_MFMSR:
+                        vcpu->arch.gpr[get_rt(inst)] = vcpu->arch.msr;
+                        break;
+                case OP_31_XOP_MTMSRD:
+                {
+                        ulong rs = vcpu->arch.gpr[get_rs(inst)];
+                        if (inst & 0x10000) {
+                                vcpu->arch.msr &= ~(MSR_RI | MSR_EE);
+                                vcpu->arch.msr |= rs & (MSR_RI | MSR_EE);
+                        } else
+                                kvmppc_set_msr(vcpu, rs);
+                        break;
+                }
+                case OP_31_XOP_MTMSR:
+                        kvmppc_set_msr(vcpu, vcpu->arch.gpr[get_rs(inst)]);
+                        break;
+                case OP_31_XOP_MFSRIN:
+                {
+                        int srnum;
+
+                        srnum = (vcpu->arch.gpr[get_rb(inst)] >> 28) & 0xf;
+                        if (vcpu->arch.mmu.mfsrin) {
+                                u32 sr;
+                                sr = vcpu->arch.mmu.mfsrin(vcpu, srnum);
+                                vcpu->arch.gpr[get_rt(inst)] = sr;
+                        }
+                        break;
+                }
+                case OP_31_XOP_MTSRIN:
+                        vcpu->arch.mmu.mtsrin(vcpu,
+                                (vcpu->arch.gpr[get_rb(inst)] >> 28) & 0xf,
+                                vcpu->arch.gpr[get_rs(inst)]);
+                        break;
+                case OP_31_XOP_TLBIE:
+                case OP_31_XOP_TLBIEL:
+                {
+                        bool large = (inst & 0x00200000) ? true : false;
+                        ulong addr = vcpu->arch.gpr[get_rb(inst)];
+                        vcpu->arch.mmu.tlbie(vcpu, addr, large);
+                        break;
+                }
+                case OP_31_XOP_EIOIO:
+                        break;
+                case OP_31_XOP_SLBMTE:
+                        if (!vcpu->arch.mmu.slbmte)
+                                return EMULATE_FAIL;
+
+                        vcpu->arch.mmu.slbmte(vcpu, vcpu->arch.gpr[get_rs(inst)],
+                                                vcpu->arch.gpr[get_rb(inst)]);
+                        break;
+                case OP_31_XOP_SLBIE:
+                        if (!vcpu->arch.mmu.slbie)
+                                return EMULATE_FAIL;
+
+                        vcpu->arch.mmu.slbie(vcpu, vcpu->arch.gpr[get_rb(inst)]);
+                        break;
+                case OP_31_XOP_SLBIA:
+                        if (!vcpu->arch.mmu.slbia)
+                                return EMULATE_FAIL;
+
+                        vcpu->arch.mmu.slbia(vcpu);
+                        break;
+                case OP_31_XOP_SLBMFEE:
+                        if (!vcpu->arch.mmu.slbmfee) {
+                                emulated = EMULATE_FAIL;
+                        } else {
+                                ulong t, rb;
+
+                                rb = vcpu->arch.gpr[get_rb(inst)];
+                                t = vcpu->arch.mmu.slbmfee(vcpu, rb);
+                                vcpu->arch.gpr[get_rt(inst)] = t;
+                        }
+                        break;
+                case OP_31_XOP_SLBMFEV:
+                        if (!vcpu->arch.mmu.slbmfev) {
+                                emulated = EMULATE_FAIL;
+                        } else {
+                                ulong t, rb;
+
+                                rb = vcpu->arch.gpr[get_rb(inst)];
+                                t = vcpu->arch.mmu.slbmfev(vcpu, rb);
+                                vcpu->arch.gpr[get_rt(inst)] = t;
+                        }
+                        break;
+                case OP_31_XOP_DCBZ:
+                {
+                        ulong rb =  vcpu->arch.gpr[get_rb(inst)];
+                        ulong ra = 0;
+                        ulong addr;
+                        u32 zeros[8] = { 0, 0, 0, 0, 0, 0, 0, 0 };
+
+                        if (get_ra(inst))
+                                ra = vcpu->arch.gpr[get_ra(inst)];
+
+                        addr = (ra + rb) & ~31ULL;
+                        if (!(vcpu->arch.msr & MSR_SF))
+                                addr &= 0xffffffff;
+
+                        if (kvmppc_st(vcpu, addr, 32, zeros)) {
+                                vcpu->arch.dear = addr;
+                                vcpu->arch.fault_dear = addr;
+                                to_book3s(vcpu)->dsisr = DSISR_PROTFAULT |
+                                                      DSISR_ISSTORE;
+                                kvmppc_book3s_queue_irqprio(vcpu,
+                                        BOOK3S_INTERRUPT_DATA_STORAGE);
+                                kvmppc_mmu_pte_flush(vcpu, addr, ~0xFFFULL);
+                        }
+
+                        break;
+                }
+                default:
+                        emulated = EMULATE_FAIL;
+                }
+                break;
+        default:
+                emulated = EMULATE_FAIL;
+        }
+
+        return emulated;
+}
+
+void kvmppc_set_bat(struct kvm_vcpu *vcpu, struct kvmppc_bat *bat, bool upper,
+                    u32 val)
+{
+        if (upper) {
+                /* Upper BAT */
+                u32 bl = (val >> 2) & 0x7ff;
+                bat->bepi_mask = (~bl << 17);
+                bat->bepi = val & 0xfffe0000;
+                bat->vs = (val & 2) ? 1 : 0;
+                bat->vp = (val & 1) ? 1 : 0;
+                bat->raw = (bat->raw & 0xffffffff00000000ULL) | val;
+        } else {
+                /* Lower BAT */
+                bat->brpn = val & 0xfffe0000;
+                bat->wimg = (val >> 3) & 0xf;
+                bat->pp = val & 3;
+                bat->raw = (bat->raw & 0x00000000ffffffffULL) | ((u64)val << 32);
+        }
+}
+
+static void kvmppc_write_bat(struct kvm_vcpu *vcpu, int sprn, u32 val)
+{
+        struct kvmppc_vcpu_book3s *vcpu_book3s = to_book3s(vcpu);
+        struct kvmppc_bat *bat;
+
+        switch (sprn) {
+        case SPRN_IBAT0U ... SPRN_IBAT3L:
+                bat = &vcpu_book3s->ibat[(sprn - SPRN_IBAT0U) / 2];
+                break;
+        case SPRN_IBAT4U ... SPRN_IBAT7L:
+                bat = &vcpu_book3s->ibat[(sprn - SPRN_IBAT4U) / 2];
+                break;
+        case SPRN_DBAT0U ... SPRN_DBAT3L:
+                bat = &vcpu_book3s->dbat[(sprn - SPRN_DBAT0U) / 2];
+                break;
+        case SPRN_DBAT4U ... SPRN_DBAT7L:
+                bat = &vcpu_book3s->dbat[(sprn - SPRN_DBAT4U) / 2];
+                break;
+        default:
+                BUG();
+        }
+
+        kvmppc_set_bat(vcpu, bat, !(sprn % 2), val);
+}
+
+int kvmppc_core_emulate_mtspr(struct kvm_vcpu *vcpu, int sprn, int rs)
+{
+        int emulated = EMULATE_DONE;
+
+        switch (sprn) {
+        case SPRN_SDR1:
+                to_book3s(vcpu)->sdr1 = vcpu->arch.gpr[rs];
+                break;
+        case SPRN_DSISR:
+                to_book3s(vcpu)->dsisr = vcpu->arch.gpr[rs];
+                break;
+        case SPRN_DAR:
+                vcpu->arch.dear = vcpu->arch.gpr[rs];
+                break;
+        case SPRN_HIOR:
+                to_book3s(vcpu)->hior = vcpu->arch.gpr[rs];
+                break;
+        case SPRN_IBAT0U ... SPRN_IBAT3L:
+        case SPRN_IBAT4U ... SPRN_IBAT7L:
+        case SPRN_DBAT0U ... SPRN_DBAT3L:
+        case SPRN_DBAT4U ... SPRN_DBAT7L:
+                kvmppc_write_bat(vcpu, sprn, (u32)vcpu->arch.gpr[rs]);
+                /* BAT writes happen so rarely that we're ok to flush
+                 * everything here */
+                kvmppc_mmu_pte_flush(vcpu, 0, 0);
+                break;
+        case SPRN_HID0:
+                to_book3s(vcpu)->hid[0] = vcpu->arch.gpr[rs];
+                break;
+        case SPRN_HID1:
+                to_book3s(vcpu)->hid[1] = vcpu->arch.gpr[rs];
+                break;
+        case SPRN_HID2:
+                to_book3s(vcpu)->hid[2] = vcpu->arch.gpr[rs];
+                break;
+        case SPRN_HID4:
+                to_book3s(vcpu)->hid[4] = vcpu->arch.gpr[rs];
+                break;
+        case SPRN_HID5:
+                to_book3s(vcpu)->hid[5] = vcpu->arch.gpr[rs];
+                /* guest HID5 set can change is_dcbz32 */
+                if (vcpu->arch.mmu.is_dcbz32(vcpu) &&
+                    (mfmsr() & MSR_HV))
+                        vcpu->arch.hflags |= BOOK3S_HFLAG_DCBZ32;
+                break;
+        case SPRN_ICTC:
+        case SPRN_THRM1:
+        case SPRN_THRM2:
+        case SPRN_THRM3:
+        case SPRN_CTRLF:
+        case SPRN_CTRLT:
+                break;
+        default:
+                printk(KERN_INFO "KVM: invalid SPR write: %d\n", sprn);
+#ifndef DEBUG_SPR
+                emulated = EMULATE_FAIL;
+#endif
+                break;
+        }
+
+        return emulated;
+}
+
+int kvmppc_core_emulate_mfspr(struct kvm_vcpu *vcpu, int sprn, int rt)
+{
+        int emulated = EMULATE_DONE;
+
+        switch (sprn) {
+        case SPRN_SDR1:
+                vcpu->arch.gpr[rt] = to_book3s(vcpu)->sdr1;
+                break;
+        case SPRN_DSISR:
+                vcpu->arch.gpr[rt] = to_book3s(vcpu)->dsisr;
+                break;
+        case SPRN_DAR:
+                vcpu->arch.gpr[rt] = vcpu->arch.dear;
+                break;
+        case SPRN_HIOR:
+                vcpu->arch.gpr[rt] = to_book3s(vcpu)->hior;
+                break;
+        case SPRN_HID0:
+                vcpu->arch.gpr[rt] = to_book3s(vcpu)->hid[0];
+                break;
+        case SPRN_HID1:
+                vcpu->arch.gpr[rt] = to_book3s(vcpu)->hid[1];
+                break;
+        case SPRN_HID2:
+                vcpu->arch.gpr[rt] = to_book3s(vcpu)->hid[2];
+                break;
+        case SPRN_HID4:
+                vcpu->arch.gpr[rt] = to_book3s(vcpu)->hid[4];
+                break;
+        case SPRN_HID5:
+                vcpu->arch.gpr[rt] = to_book3s(vcpu)->hid[5];
+                break;
+        case SPRN_THRM1:
+        case SPRN_THRM2:
+        case SPRN_THRM3:
+        case SPRN_CTRLF:
+        case SPRN_CTRLT:
+                vcpu->arch.gpr[rt] = 0;
+                break;
+        default:
+                printk(KERN_INFO "KVM: invalid SPR read: %d\n", sprn);
+#ifndef DEBUG_SPR
+                emulated = EMULATE_FAIL;
+#endif
+                break;
+        }
+
+        return emulated;
+}
+
diff --git a/arch/powerpc/kvm/book3s_64_exports.c b/arch/powerpc/kvm/book3s_64_exports.c
new file mode 100644
index 000000000000..5b2db38ed86c
--- /dev/null
+++ b/arch/powerpc/kvm/book3s_64_exports.c
@@ -0,0 +1,24 @@
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ *
+ * Copyright SUSE Linux Products GmbH 2009
+ *
+ * Authors: Alexander Graf <agraf@suse.de>
+ */
+
+#include <linux/module.h>
+#include <asm/kvm_book3s.h>
+
+EXPORT_SYMBOL_GPL(kvmppc_trampoline_enter);
+EXPORT_SYMBOL_GPL(kvmppc_trampoline_lowmem);
diff --git a/arch/powerpc/kvm/book3s_64_interrupts.S b/arch/powerpc/kvm/book3s_64_interrupts.S
new file mode 100644
index 000000000000..7b55d8094c8b
--- /dev/null
+++ b/arch/powerpc/kvm/book3s_64_interrupts.S
@@ -0,0 +1,392 @@
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ *
+ * Copyright SUSE Linux Products GmbH 2009
+ *
+ * Authors: Alexander Graf <agraf@suse.de>
+ */
+
+#include <asm/ppc_asm.h>
+#include <asm/kvm_asm.h>
+#include <asm/reg.h>
+#include <asm/page.h>
+#include <asm/asm-offsets.h>
+#include <asm/exception-64s.h>
+
+#define KVMPPC_HANDLE_EXIT .kvmppc_handle_exit
+#define ULONG_SIZE 8
+#define VCPU_GPR(n)     (VCPU_GPRS + (n * ULONG_SIZE))
+
+.macro mfpaca tmp_reg, src_reg, offset, vcpu_reg
+        ld      \tmp_reg, (PACA_EXMC+\offset)(r13)
+        std     \tmp_reg, VCPU_GPR(\src_reg)(\vcpu_reg)
+.endm
+
+.macro DISABLE_INTERRUPTS
+       mfmsr   r0
+       rldicl  r0,r0,48,1
+       rotldi  r0,r0,16
+       mtmsrd  r0,1
+.endm
+
+/*****************************************************************************
+ *                                                                           *
+ *     Guest entry / exit code that is in kernel module memory (highmem)     *
+ *                                                                           *
+ ****************************************************************************/
+
+/* Registers:
+ *  r3: kvm_run pointer
+ *  r4: vcpu pointer
+ */
+_GLOBAL(__kvmppc_vcpu_entry)
+
+kvm_start_entry:
+        /* Write correct stack frame */
+        mflr    r0
+        std     r0,16(r1)
+
+        /* Save host state to the stack */
+        stdu    r1, -SWITCH_FRAME_SIZE(r1)
+
+        /* Save r3 (kvm_run) and r4 (vcpu) */
+        SAVE_2GPRS(3, r1)
+
+        /* Save non-volatile registers (r14 - r31) */
+        SAVE_NVGPRS(r1)
+
+        /* Save LR */
+        mflr    r14
+        std     r14, _LINK(r1)
+
+/* XXX optimize non-volatile loading away */
+kvm_start_lightweight:
+
+        DISABLE_INTERRUPTS
+
+        /* Save R1/R2 in the PACA */
+        std     r1, PACAR1(r13)
+        std     r2, (PACA_EXMC+EX_SRR0)(r13)
+        ld      r3, VCPU_HIGHMEM_HANDLER(r4)
+        std     r3, PACASAVEDMSR(r13)
+
+        /* Load non-volatile guest state from the vcpu */
+        ld      r14, VCPU_GPR(r14)(r4)
+        ld      r15, VCPU_GPR(r15)(r4)
+        ld      r16, VCPU_GPR(r16)(r4)
+        ld      r17, VCPU_GPR(r17)(r4)
+        ld      r18, VCPU_GPR(r18)(r4)
+        ld      r19, VCPU_GPR(r19)(r4)
+        ld      r20, VCPU_GPR(r20)(r4)
+        ld      r21, VCPU_GPR(r21)(r4)
+        ld      r22, VCPU_GPR(r22)(r4)
+        ld      r23, VCPU_GPR(r23)(r4)
+        ld      r24, VCPU_GPR(r24)(r4)
+        ld      r25, VCPU_GPR(r25)(r4)
+        ld      r26, VCPU_GPR(r26)(r4)
+        ld      r27, VCPU_GPR(r27)(r4)
+        ld      r28, VCPU_GPR(r28)(r4)
+        ld      r29, VCPU_GPR(r29)(r4)
+        ld      r30, VCPU_GPR(r30)(r4)
+        ld      r31, VCPU_GPR(r31)(r4)
+
+        ld      r9, VCPU_PC(r4)                 /* r9 = vcpu->arch.pc */
+        ld      r10, VCPU_SHADOW_MSR(r4)        /* r10 = vcpu->arch.shadow_msr */
+
+        ld      r3, VCPU_TRAMPOLINE_ENTER(r4)
+        mtsrr0  r3
+
+        LOAD_REG_IMMEDIATE(r3, MSR_KERNEL & ~(MSR_IR | MSR_DR))
+        mtsrr1  r3
+
+        /* Load guest state in the respective registers */
+        lwz     r3, VCPU_CR(r4)         /* r3 = vcpu->arch.cr */
+        stw     r3, (PACA_EXMC + EX_CCR)(r13)
+
+        ld      r3, VCPU_CTR(r4)        /* r3 = vcpu->arch.ctr */
+        mtctr   r3                      /* CTR = r3 */
+
+        ld      r3, VCPU_LR(r4)         /* r3 = vcpu->arch.lr */
+        mtlr    r3                      /* LR = r3 */
+
+        ld      r3, VCPU_XER(r4)        /* r3 = vcpu->arch.xer */
+        std     r3, (PACA_EXMC + EX_R3)(r13)
+
+        /* Some guests may need to have dcbz set to 32 byte length.
+         *
+         * Usually we ensure that by patching the guest's instructions
+         * to trap on dcbz and emulate it in the hypervisor.
+         *
+         * If we can, we should tell the CPU to use 32 byte dcbz though,
+         * because that's a lot faster.
+         */
+
+        ld      r3, VCPU_HFLAGS(r4)
+        rldicl. r3, r3, 0, 63           /* CR = ((r3 & 1) == 0) */
+        beq     no_dcbz32_on
+
+        mfspr   r3,SPRN_HID5
+        ori     r3, r3, 0x80            /* XXX HID5_dcbz32 = 0x80 */
+        mtspr   SPRN_HID5,r3
+
+no_dcbz32_on:
+        /*      Load guest GPRs */
+
+        ld      r3, VCPU_GPR(r9)(r4)
+        std     r3, (PACA_EXMC + EX_R9)(r13)
+        ld      r3, VCPU_GPR(r10)(r4)
+        std     r3, (PACA_EXMC + EX_R10)(r13)
+        ld      r3, VCPU_GPR(r11)(r4)
+        std     r3, (PACA_EXMC + EX_R11)(r13)
+        ld      r3, VCPU_GPR(r12)(r4)
+        std     r3, (PACA_EXMC + EX_R12)(r13)
+        ld      r3, VCPU_GPR(r13)(r4)
+        std     r3, (PACA_EXMC + EX_R13)(r13)
+
+        ld      r0, VCPU_GPR(r0)(r4)
+        ld      r1, VCPU_GPR(r1)(r4)
+        ld      r2, VCPU_GPR(r2)(r4)
+        ld      r3, VCPU_GPR(r3)(r4)
+        ld      r5, VCPU_GPR(r5)(r4)
+        ld      r6, VCPU_GPR(r6)(r4)
+        ld      r7, VCPU_GPR(r7)(r4)
+        ld      r8, VCPU_GPR(r8)(r4)
+        ld      r4, VCPU_GPR(r4)(r4)
+
+        /* This sets the Magic value for the trampoline */
+
+        li      r11, 1
+        stb     r11, PACA_KVM_IN_GUEST(r13)
+
+        /* Jump to SLB patching handlder and into our guest */
+        RFI
+
+/*
+ * This is the handler in module memory. It gets jumped at from the
+ * lowmem trampoline code, so it's basically the guest exit code.
+ *
+ */
+
+.global kvmppc_handler_highmem
+kvmppc_handler_highmem:
+
+        /*
+         * Register usage at this point:
+         *
+         * R00   = guest R13
+         * R01   = host R1
+         * R02   = host R2
+         * R10   = guest PC
+         * R11   = guest MSR
+         * R12   = exit handler id
+         * R13   = PACA
+         * PACA.exmc.R9    = guest R1
+         * PACA.exmc.R10   = guest R10
+         * PACA.exmc.R11   = guest R11
+         * PACA.exmc.R12   = guest R12
+         * PACA.exmc.R13   = guest R2
+         * PACA.exmc.DAR   = guest DAR
+         * PACA.exmc.DSISR = guest DSISR
+         * PACA.exmc.LR    = guest instruction
+         * PACA.exmc.CCR   = guest CR
+         * PACA.exmc.SRR0  = guest R0
+         *
+         */
+
+        std     r3, (PACA_EXMC+EX_R3)(r13)
+
+        /* save the exit id in R3 */
+        mr      r3, r12
+
+        /* R12 = vcpu */
+        ld      r12, GPR4(r1)
+
+        /* Now save the guest state */
+
+        std     r0, VCPU_GPR(r13)(r12)
+        std     r4, VCPU_GPR(r4)(r12)
+        std     r5, VCPU_GPR(r5)(r12)
+        std     r6, VCPU_GPR(r6)(r12)
+        std     r7, VCPU_GPR(r7)(r12)
+        std     r8, VCPU_GPR(r8)(r12)
+        std     r9, VCPU_GPR(r9)(r12)
+
+        /* get registers from PACA */
+        mfpaca  r5, r0, EX_SRR0, r12
+        mfpaca  r5, r3, EX_R3, r12
+        mfpaca  r5, r1, EX_R9, r12
+        mfpaca  r5, r10, EX_R10, r12
+        mfpaca  r5, r11, EX_R11, r12
+        mfpaca  r5, r12, EX_R12, r12
+        mfpaca  r5, r2, EX_R13, r12
+
+        lwz     r5, (PACA_EXMC+EX_LR)(r13)
+        stw     r5, VCPU_LAST_INST(r12)
+
+        lwz     r5, (PACA_EXMC+EX_CCR)(r13)
+        stw     r5, VCPU_CR(r12)
+
+        ld      r5, VCPU_HFLAGS(r12)
+        rldicl. r5, r5, 0, 63           /* CR = ((r5 & 1) == 0) */
+        beq     no_dcbz32_off
+
+        mfspr   r5,SPRN_HID5
+        rldimi  r5,r5,6,56
+        mtspr   SPRN_HID5,r5
+
+no_dcbz32_off:
+
+        /* XXX maybe skip on lightweight? */
+        std     r14, VCPU_GPR(r14)(r12)
+        std     r15, VCPU_GPR(r15)(r12)
+        std     r16, VCPU_GPR(r16)(r12)
+        std     r17, VCPU_GPR(r17)(r12)
+        std     r18, VCPU_GPR(r18)(r12)
+        std     r19, VCPU_GPR(r19)(r12)
+        std     r20, VCPU_GPR(r20)(r12)
+        std     r21, VCPU_GPR(r21)(r12)
+        std     r22, VCPU_GPR(r22)(r12)
+        std     r23, VCPU_GPR(r23)(r12)
+        std     r24, VCPU_GPR(r24)(r12)
+        std     r25, VCPU_GPR(r25)(r12)
+        std     r26, VCPU_GPR(r26)(r12)
+        std     r27, VCPU_GPR(r27)(r12)
+        std     r28, VCPU_GPR(r28)(r12)
+        std     r29, VCPU_GPR(r29)(r12)
+        std     r30, VCPU_GPR(r30)(r12)
+        std     r31, VCPU_GPR(r31)(r12)
+
+        /* Restore non-volatile host registers (r14 - r31) */
+        REST_NVGPRS(r1)
+
+        /* Save guest PC (R10) */
+        std     r10, VCPU_PC(r12)
+
+        /* Save guest msr (R11) */
+        std     r11, VCPU_SHADOW_MSR(r12)
+
+        /* Save guest CTR (in R12) */
+        mfctr   r5
+        std     r5, VCPU_CTR(r12)
+
+        /* Save guest LR */
+        mflr    r5
+        std     r5, VCPU_LR(r12)
+
+        /* Save guest XER */
+        mfxer   r5
+        std     r5, VCPU_XER(r12)
+
+        /* Save guest DAR */
+        ld      r5, (PACA_EXMC+EX_DAR)(r13)
+        std     r5, VCPU_FAULT_DEAR(r12)
+
+        /* Save guest DSISR */
+        lwz     r5, (PACA_EXMC+EX_DSISR)(r13)
+        std     r5, VCPU_FAULT_DSISR(r12)
+
+        /* Restore host msr -> SRR1 */
+        ld      r7, VCPU_HOST_MSR(r12)
+        mtsrr1  r7
+
+        /* Restore host IP -> SRR0 */
+        ld      r6, VCPU_HOST_RETIP(r12)
+        mtsrr0  r6
+
+        /*
+         * For some interrupts, we need to call the real Linux
+         * handler, so it can do work for us. This has to happen
+         * as if the interrupt arrived from the kernel though,
+         * so let's fake it here where most state is restored.
+         *
+         * Call Linux for hardware interrupts/decrementer
+         * r3 = address of interrupt handler (exit reason)
+         */
+
+        cmpwi   r3, BOOK3S_INTERRUPT_EXTERNAL
+        beq     call_linux_handler
+        cmpwi   r3, BOOK3S_INTERRUPT_DECREMENTER
+        beq     call_linux_handler
+
+        /* Back to Interruptable Mode! (goto kvm_return_point) */
+        RFI
+
+call_linux_handler:
+
+        /*
+         * If we land here we need to jump back to the handler we
+         * came from.
+         *
+         * We have a page that we can access from real mode, so let's
+         * jump back to that and use it as a trampoline to get back into the
+         * interrupt handler!
+         *
+         * R3 still contains the exit code,
+         * R6 VCPU_HOST_RETIP and
+         * R7 VCPU_HOST_MSR
+         */
+
+        mtlr    r3
+
+        ld      r5, VCPU_TRAMPOLINE_LOWMEM(r12)
+        mtsrr0  r5
+        LOAD_REG_IMMEDIATE(r5, MSR_KERNEL & ~(MSR_IR | MSR_DR))
+        mtsrr1  r5
+
+        RFI
+
+.global kvm_return_point
+kvm_return_point:
+
+        /* Jump back to lightweight entry if we're supposed to */
+        /* go back into the guest */
+        mr      r5, r3
+        /* Restore r3 (kvm_run) and r4 (vcpu) */
+        REST_2GPRS(3, r1)
+        bl      KVMPPC_HANDLE_EXIT
+
+#if 0 /* XXX get lightweight exits back */
+        cmpwi   r3, RESUME_GUEST
+        bne     kvm_exit_heavyweight
+
+        /* put VCPU and KVM_RUN back into place and roll again! */
+        REST_2GPRS(3, r1)
+        b       kvm_start_lightweight
+
+kvm_exit_heavyweight:
+        /* Restore non-volatile host registers */
+        ld      r14, _LINK(r1)
+        mtlr    r14
+        REST_NVGPRS(r1)
+
+        addi    r1, r1, SWITCH_FRAME_SIZE
+#else
+        ld      r4, _LINK(r1)
+        mtlr    r4
+
+        cmpwi   r3, RESUME_GUEST
+        bne     kvm_exit_heavyweight
+
+        REST_2GPRS(3, r1)
+
+        addi    r1, r1, SWITCH_FRAME_SIZE
+
+        b       kvm_start_entry
+
+kvm_exit_heavyweight:
+
+        addi    r1, r1, SWITCH_FRAME_SIZE
+#endif
+
+        blr
diff --git a/arch/powerpc/kvm/book3s_64_mmu.c b/arch/powerpc/kvm/book3s_64_mmu.c
new file mode 100644
index 000000000000..5598f88f142e
--- /dev/null
+++ b/arch/powerpc/kvm/book3s_64_mmu.c
@@ -0,0 +1,478 @@
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ *
+ * Copyright SUSE Linux Products GmbH 2009
+ *
+ * Authors: Alexander Graf <agraf@suse.de>
+ */
+
+#include <linux/types.h>
+#include <linux/string.h>
+#include <linux/kvm.h>
+#include <linux/kvm_host.h>
+#include <linux/highmem.h>
+
+#include <asm/tlbflush.h>
+#include <asm/kvm_ppc.h>
+#include <asm/kvm_book3s.h>
+
+/* #define DEBUG_MMU */
+
+#ifdef DEBUG_MMU
+#define dprintk(X...) printk(KERN_INFO X)
+#else
+#define dprintk(X...) do { } while(0)
+#endif
+
+static void kvmppc_mmu_book3s_64_reset_msr(struct kvm_vcpu *vcpu)
+{
+        kvmppc_set_msr(vcpu, MSR_SF);
+}
+
+static struct kvmppc_slb *kvmppc_mmu_book3s_64_find_slbe(
+                                struct kvmppc_vcpu_book3s *vcpu_book3s,
+                                gva_t eaddr)
+{
+        int i;
+        u64 esid = GET_ESID(eaddr);
+        u64 esid_1t = GET_ESID_1T(eaddr);
+
+        for (i = 0; i < vcpu_book3s->slb_nr; i++) {
+                u64 cmp_esid = esid;
+
+                if (!vcpu_book3s->slb[i].valid)
+                        continue;
+
+                if (vcpu_book3s->slb[i].large)
+                        cmp_esid = esid_1t;
+
+                if (vcpu_book3s->slb[i].esid == cmp_esid)
+                        return &vcpu_book3s->slb[i];
+        }
+
+        dprintk("KVM: No SLB entry found for 0x%lx [%llx | %llx]\n",
+                eaddr, esid, esid_1t);
+        for (i = 0; i < vcpu_book3s->slb_nr; i++) {
+            if (vcpu_book3s->slb[i].vsid)
+                dprintk("  %d: %c%c %llx %llx\n", i,
+                        vcpu_book3s->slb[i].valid ? 'v' : ' ',
+                        vcpu_book3s->slb[i].large ? 'l' : ' ',
+                        vcpu_book3s->slb[i].esid,
+                        vcpu_book3s->slb[i].vsid);
+        }
+
+        return NULL;
+}
+
+static u64 kvmppc_mmu_book3s_64_ea_to_vp(struct kvm_vcpu *vcpu, gva_t eaddr,
+                                         bool data)
+{
+        struct kvmppc_slb *slb;
+
+        slb = kvmppc_mmu_book3s_64_find_slbe(to_book3s(vcpu), eaddr);
+        if (!slb)
+                return 0;
+
+        if (slb->large)
+                return (((u64)eaddr >> 12) & 0xfffffff) |
+                       (((u64)slb->vsid) << 28);
+
+        return (((u64)eaddr >> 12) & 0xffff) | (((u64)slb->vsid) << 16);
+}
+
+static int kvmppc_mmu_book3s_64_get_pagesize(struct kvmppc_slb *slbe)
+{
+        return slbe->large ? 24 : 12;
+}
+
+static u32 kvmppc_mmu_book3s_64_get_page(struct kvmppc_slb *slbe, gva_t eaddr)
+{
+        int p = kvmppc_mmu_book3s_64_get_pagesize(slbe);
+        return ((eaddr & 0xfffffff) >> p);
+}
+
+static hva_t kvmppc_mmu_book3s_64_get_pteg(
+                                struct kvmppc_vcpu_book3s *vcpu_book3s,
+                                struct kvmppc_slb *slbe, gva_t eaddr,
+                                bool second)
+{
+        u64 hash, pteg, htabsize;
+        u32 page;
+        hva_t r;
+
+        page = kvmppc_mmu_book3s_64_get_page(slbe, eaddr);
+        htabsize = ((1 << ((vcpu_book3s->sdr1 & 0x1f) + 11)) - 1);
+
+        hash = slbe->vsid ^ page;
+        if (second)
+                hash = ~hash;
+        hash &= ((1ULL << 39ULL) - 1ULL);
+        hash &= htabsize;
+        hash <<= 7ULL;
+
+        pteg = vcpu_book3s->sdr1 & 0xfffffffffffc0000ULL;
+        pteg |= hash;
+
+        dprintk("MMU: page=0x%x sdr1=0x%llx pteg=0x%llx vsid=0x%llx\n",
+                page, vcpu_book3s->sdr1, pteg, slbe->vsid);
+
+        r = gfn_to_hva(vcpu_book3s->vcpu.kvm, pteg >> PAGE_SHIFT);
+        if (kvm_is_error_hva(r))
+                return r;
+        return r | (pteg & ~PAGE_MASK);
+}
+
+static u64 kvmppc_mmu_book3s_64_get_avpn(struct kvmppc_slb *slbe, gva_t eaddr)
+{
+        int p = kvmppc_mmu_book3s_64_get_pagesize(slbe);
+        u64 avpn;
+
+        avpn = kvmppc_mmu_book3s_64_get_page(slbe, eaddr);
+        avpn |= slbe->vsid << (28 - p);
+
+        if (p < 24)
+                avpn >>= ((80 - p) - 56) - 8;
+        else
+                avpn <<= 8;
+
+        return avpn;
+}
+
+static int kvmppc_mmu_book3s_64_xlate(struct kvm_vcpu *vcpu, gva_t eaddr,
+                                struct kvmppc_pte *gpte, bool data)
+{
+        struct kvmppc_vcpu_book3s *vcpu_book3s = to_book3s(vcpu);
+        struct kvmppc_slb *slbe;
+        hva_t ptegp;
+        u64 pteg[16];
+        u64 avpn = 0;
+        int i;
+        u8 key = 0;
+        bool found = false;
+        bool perm_err = false;
+        int second = 0;
+
+        slbe = kvmppc_mmu_book3s_64_find_slbe(vcpu_book3s, eaddr);
+        if (!slbe)
+                goto no_seg_found;
+
+do_second:
+        ptegp = kvmppc_mmu_book3s_64_get_pteg(vcpu_book3s, slbe, eaddr, second);
+        if (kvm_is_error_hva(ptegp))
+                goto no_page_found;
+
+        avpn = kvmppc_mmu_book3s_64_get_avpn(slbe, eaddr);
+
+        if(copy_from_user(pteg, (void __user *)ptegp, sizeof(pteg))) {
+                printk(KERN_ERR "KVM can't copy data from 0x%lx!\n", ptegp);
+                goto no_page_found;
+        }
+
+        if ((vcpu->arch.msr & MSR_PR) && slbe->Kp)
+                key = 4;
+        else if (!(vcpu->arch.msr & MSR_PR) && slbe->Ks)
+                key = 4;
+
+        for (i=0; i<16; i+=2) {
+                u64 v = pteg[i];
+                u64 r = pteg[i+1];
+
+                /* Valid check */
+                if (!(v & HPTE_V_VALID))
+                        continue;
+                /* Hash check */
+                if ((v & HPTE_V_SECONDARY) != second)
+                        continue;
+
+                /* AVPN compare */
+                if (HPTE_V_AVPN_VAL(avpn) == HPTE_V_AVPN_VAL(v)) {
+                        u8 pp = (r & HPTE_R_PP) | key;
+                        int eaddr_mask = 0xFFF;
+
+                        gpte->eaddr = eaddr;
+                        gpte->vpage = kvmppc_mmu_book3s_64_ea_to_vp(vcpu,
+                                                                    eaddr,
+                                                                    data);
+                        if (slbe->large)
+                                eaddr_mask = 0xFFFFFF;
+                        gpte->raddr = (r & HPTE_R_RPN) | (eaddr & eaddr_mask);
+                        gpte->may_execute = ((r & HPTE_R_N) ? false : true);
+                        gpte->may_read = false;
+                        gpte->may_write = false;
+
+                        switch (pp) {
+                        case 0:
+                        case 1:
+                        case 2:
+                        case 6:
+                                gpte->may_write = true;
+                                /* fall through */
+                        case 3:
+                        case 5:
+                        case 7:
+                                gpte->may_read = true;
+                                break;
+                        }
+
+                        if (!gpte->may_read) {
+                                perm_err = true;
+                                continue;
+                        }
+
+                        dprintk("KVM MMU: Translated 0x%lx [0x%llx] -> 0x%llx "
+                                "-> 0x%llx\n",
+                                eaddr, avpn, gpte->vpage, gpte->raddr);
+                        found = true;
+                        break;
+                }
+        }
+
+        /* Update PTE R and C bits, so the guest's swapper knows we used the
+         * page */
+        if (found) {
+                u32 oldr = pteg[i+1];
+
+                if (gpte->may_read) {
+                        /* Set the accessed flag */
+                        pteg[i+1] |= HPTE_R_R;
+                }
+                if (gpte->may_write) {
+                        /* Set the dirty flag */
+                        pteg[i+1] |= HPTE_R_C;
+                } else {
+                        dprintk("KVM: Mapping read-only page!\n");
+                }
+
+                /* Write back into the PTEG */
+                if (pteg[i+1] != oldr)
+                        copy_to_user((void __user *)ptegp, pteg, sizeof(pteg));
+
+                return 0;
+        } else {
+                dprintk("KVM MMU: No PTE found (ea=0x%lx sdr1=0x%llx "
+                        "ptegp=0x%lx)\n",
+                        eaddr, to_book3s(vcpu)->sdr1, ptegp);
+                for (i = 0; i < 16; i += 2)
+                        dprintk("   %02d: 0x%llx - 0x%llx (0x%llx)\n",
+                                i, pteg[i], pteg[i+1], avpn);
+
+                if (!second) {
+                        second = HPTE_V_SECONDARY;
+                        goto do_second;
+                }
+        }
+
+
+no_page_found:
+
+
+        if (perm_err)
+                return -EPERM;
+
+        return -ENOENT;
+
+no_seg_found:
+
+        dprintk("KVM MMU: Trigger segment fault\n");
+        return -EINVAL;
+}
+
+static void kvmppc_mmu_book3s_64_slbmte(struct kvm_vcpu *vcpu, u64 rs, u64 rb)
+{
+        struct kvmppc_vcpu_book3s *vcpu_book3s;
+        u64 esid, esid_1t;
+        int slb_nr;
+        struct kvmppc_slb *slbe;
+
+        dprintk("KVM MMU: slbmte(0x%llx, 0x%llx)\n", rs, rb);
+
+        vcpu_book3s = to_book3s(vcpu);
+
+        esid = GET_ESID(rb);
+        esid_1t = GET_ESID_1T(rb);
+        slb_nr = rb & 0xfff;
+
+        if (slb_nr > vcpu_book3s->slb_nr)
+                return;
+
+        slbe = &vcpu_book3s->slb[slb_nr];
+
+        slbe->large = (rs & SLB_VSID_L) ? 1 : 0;
+        slbe->esid  = slbe->large ? esid_1t : esid;
+        slbe->vsid  = rs >> 12;
+        slbe->valid = (rb & SLB_ESID_V) ? 1 : 0;
+        slbe->Ks    = (rs & SLB_VSID_KS) ? 1 : 0;
+        slbe->Kp    = (rs & SLB_VSID_KP) ? 1 : 0;
+        slbe->nx    = (rs & SLB_VSID_N) ? 1 : 0;
+        slbe->class = (rs & SLB_VSID_C) ? 1 : 0;
+
+        slbe->orige = rb & (ESID_MASK | SLB_ESID_V);
+        slbe->origv = rs;
+
+        /* Map the new segment */
+        kvmppc_mmu_map_segment(vcpu, esid << SID_SHIFT);
+}
+
+static u64 kvmppc_mmu_book3s_64_slbmfee(struct kvm_vcpu *vcpu, u64 slb_nr)
+{
+        struct kvmppc_vcpu_book3s *vcpu_book3s = to_book3s(vcpu);
+        struct kvmppc_slb *slbe;
+
+        if (slb_nr > vcpu_book3s->slb_nr)
+                return 0;
+
+        slbe = &vcpu_book3s->slb[slb_nr];
+
+        return slbe->orige;
+}
+
+static u64 kvmppc_mmu_book3s_64_slbmfev(struct kvm_vcpu *vcpu, u64 slb_nr)
+{
+        struct kvmppc_vcpu_book3s *vcpu_book3s = to_book3s(vcpu);
+        struct kvmppc_slb *slbe;
+
+        if (slb_nr > vcpu_book3s->slb_nr)
+                return 0;
+
+        slbe = &vcpu_book3s->slb[slb_nr];
+
+        return slbe->origv;
+}
+
+static void kvmppc_mmu_book3s_64_slbie(struct kvm_vcpu *vcpu, u64 ea)
+{
+        struct kvmppc_vcpu_book3s *vcpu_book3s = to_book3s(vcpu);
+        struct kvmppc_slb *slbe;
+
+        dprintk("KVM MMU: slbie(0x%llx)\n", ea);
+
+        slbe = kvmppc_mmu_book3s_64_find_slbe(vcpu_book3s, ea);
+
+        if (!slbe)
+                return;
+
+        dprintk("KVM MMU: slbie(0x%llx, 0x%llx)\n", ea, slbe->esid);
+
+        slbe->valid = false;
+
+        kvmppc_mmu_map_segment(vcpu, ea);
+}
+
+static void kvmppc_mmu_book3s_64_slbia(struct kvm_vcpu *vcpu)
+{
+        struct kvmppc_vcpu_book3s *vcpu_book3s = to_book3s(vcpu);
+        int i;
+
+        dprintk("KVM MMU: slbia()\n");
+
+        for (i = 1; i < vcpu_book3s->slb_nr; i++)
+                vcpu_book3s->slb[i].valid = false;
+
+        if (vcpu->arch.msr & MSR_IR) {
+                kvmppc_mmu_flush_segments(vcpu);
+                kvmppc_mmu_map_segment(vcpu, vcpu->arch.pc);
+        }
+}
+
+static void kvmppc_mmu_book3s_64_mtsrin(struct kvm_vcpu *vcpu, u32 srnum,
+                                        ulong value)
+{
+        u64 rb = 0, rs = 0;
+
+        /* ESID = srnum */
+        rb |= (srnum & 0xf) << 28;
+        /* Set the valid bit */
+        rb |= 1 << 27;
+        /* Index = ESID */
+        rb |= srnum;
+
+        /* VSID = VSID */
+        rs |= (value & 0xfffffff) << 12;
+        /* flags = flags */
+        rs |= ((value >> 27) & 0xf) << 9;
+
+        kvmppc_mmu_book3s_64_slbmte(vcpu, rs, rb);
+}
+
+static void kvmppc_mmu_book3s_64_tlbie(struct kvm_vcpu *vcpu, ulong va,
+                                       bool large)
+{
+        u64 mask = 0xFFFFFFFFFULL;
+
+        dprintk("KVM MMU: tlbie(0x%lx)\n", va);
+
+        if (large)
+                mask = 0xFFFFFF000ULL;
+        kvmppc_mmu_pte_vflush(vcpu, va >> 12, mask);
+}
+
+static int kvmppc_mmu_book3s_64_esid_to_vsid(struct kvm_vcpu *vcpu, u64 esid,
+                                             u64 *vsid)
+{
+        switch (vcpu->arch.msr & (MSR_DR|MSR_IR)) {
+        case 0:
+                *vsid = (VSID_REAL >> 16) | esid;
+                break;
+        case MSR_IR:
+                *vsid = (VSID_REAL_IR >> 16) | esid;
+                break;
+        case MSR_DR:
+                *vsid = (VSID_REAL_DR >> 16) | esid;
+                break;
+        case MSR_DR|MSR_IR:
+        {
+                ulong ea;
+                struct kvmppc_slb *slb;
+                ea = esid << SID_SHIFT;
+                slb = kvmppc_mmu_book3s_64_find_slbe(to_book3s(vcpu), ea);
+                if (slb)
+                        *vsid = slb->vsid;
+                else
+                        return -ENOENT;
+
+                break;
+        }
+        default:
+                BUG();
+                break;
+        }
+
+        return 0;
+}
+
+static bool kvmppc_mmu_book3s_64_is_dcbz32(struct kvm_vcpu *vcpu)
+{
+        return (to_book3s(vcpu)->hid[5] & 0x80);
+}
+
+void kvmppc_mmu_book3s_64_init(struct kvm_vcpu *vcpu)
+{
+        struct kvmppc_mmu *mmu = &vcpu->arch.mmu;
+
+        mmu->mfsrin = NULL;
+        mmu->mtsrin = kvmppc_mmu_book3s_64_mtsrin;
+        mmu->slbmte = kvmppc_mmu_book3s_64_slbmte;
+        mmu->slbmfee = kvmppc_mmu_book3s_64_slbmfee;
+        mmu->slbmfev = kvmppc_mmu_book3s_64_slbmfev;
+        mmu->slbie = kvmppc_mmu_book3s_64_slbie;
+        mmu->slbia = kvmppc_mmu_book3s_64_slbia;
+        mmu->xlate = kvmppc_mmu_book3s_64_xlate;
+        mmu->reset_msr = kvmppc_mmu_book3s_64_reset_msr;
+        mmu->tlbie = kvmppc_mmu_book3s_64_tlbie;
+        mmu->esid_to_vsid = kvmppc_mmu_book3s_64_esid_to_vsid;
+        mmu->ea_to_vp = kvmppc_mmu_book3s_64_ea_to_vp;
+        mmu->is_dcbz32 = kvmppc_mmu_book3s_64_is_dcbz32;
+
+        vcpu->arch.hflags |= BOOK3S_HFLAG_SLB;
+}
diff --git a/arch/powerpc/kvm/book3s_64_mmu_host.c b/arch/powerpc/kvm/book3s_64_mmu_host.c
new file mode 100644
index 000000000000..f2899b297ffd
--- /dev/null
+++ b/arch/powerpc/kvm/book3s_64_mmu_host.c
@@ -0,0 +1,408 @@
+/*
+ * Copyright (C) 2009 SUSE Linux Products GmbH. All rights reserved.
+ *
+ * Authors:
+ *     Alexander Graf <agraf@suse.de>
+ *     Kevin Wolf <mail@kevin-wolf.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+#include <linux/kvm_host.h>
+
+#include <asm/kvm_ppc.h>
+#include <asm/kvm_book3s.h>
+#include <asm/mmu-hash64.h>
+#include <asm/machdep.h>
+#include <asm/mmu_context.h>
+#include <asm/hw_irq.h>
+
+#define PTE_SIZE 12
+#define VSID_ALL 0
+
+/* #define DEBUG_MMU */
+/* #define DEBUG_SLB */
+
+#ifdef DEBUG_MMU
+#define dprintk_mmu(a, ...) printk(KERN_INFO a, __VA_ARGS__)
+#else
+#define dprintk_mmu(a, ...) do { } while(0)
+#endif
+
+#ifdef DEBUG_SLB
+#define dprintk_slb(a, ...) printk(KERN_INFO a, __VA_ARGS__)
+#else
+#define dprintk_slb(a, ...) do { } while(0)
+#endif
+
+static void invalidate_pte(struct hpte_cache *pte)
+{
+        dprintk_mmu("KVM: Flushing SPT %d: 0x%llx (0x%llx) -> 0x%llx\n",
+                    i, pte->pte.eaddr, pte->pte.vpage, pte->host_va);
+
+        ppc_md.hpte_invalidate(pte->slot, pte->host_va,
+                               MMU_PAGE_4K, MMU_SEGSIZE_256M,
+                               false);
+        pte->host_va = 0;
+        kvm_release_pfn_dirty(pte->pfn);
+}
+
+void kvmppc_mmu_pte_flush(struct kvm_vcpu *vcpu, u64 guest_ea, u64 ea_mask)
+{
+        int i;
+
+        dprintk_mmu("KVM: Flushing %d Shadow PTEs: 0x%llx & 0x%llx\n",
+                    vcpu->arch.hpte_cache_offset, guest_ea, ea_mask);
+        BUG_ON(vcpu->arch.hpte_cache_offset > HPTEG_CACHE_NUM);
+
+        guest_ea &= ea_mask;
+        for (i = 0; i < vcpu->arch.hpte_cache_offset; i++) {
+                struct hpte_cache *pte;
+
+                pte = &vcpu->arch.hpte_cache[i];
+                if (!pte->host_va)
+                        continue;
+
+                if ((pte->pte.eaddr & ea_mask) == guest_ea) {
+                        invalidate_pte(pte);
+                }
+        }
+
+        /* Doing a complete flush -> start from scratch */
+        if (!ea_mask)
+                vcpu->arch.hpte_cache_offset = 0;
+}
+
+void kvmppc_mmu_pte_vflush(struct kvm_vcpu *vcpu, u64 guest_vp, u64 vp_mask)
+{
+        int i;
+
+        dprintk_mmu("KVM: Flushing %d Shadow vPTEs: 0x%llx & 0x%llx\n",
+                    vcpu->arch.hpte_cache_offset, guest_vp, vp_mask);
+        BUG_ON(vcpu->arch.hpte_cache_offset > HPTEG_CACHE_NUM);
+
+        guest_vp &= vp_mask;
+        for (i = 0; i < vcpu->arch.hpte_cache_offset; i++) {
+                struct hpte_cache *pte;
+
+                pte = &vcpu->arch.hpte_cache[i];
+                if (!pte->host_va)
+                        continue;
+
+                if ((pte->pte.vpage & vp_mask) == guest_vp) {
+                        invalidate_pte(pte);
+                }
+        }
+}
+
+void kvmppc_mmu_pte_pflush(struct kvm_vcpu *vcpu, u64 pa_start, u64 pa_end)
+{
+        int i;
+
+        dprintk_mmu("KVM: Flushing %d Shadow pPTEs: 0x%llx & 0x%llx\n",
+                    vcpu->arch.hpte_cache_offset, guest_pa, pa_mask);
+        BUG_ON(vcpu->arch.hpte_cache_offset > HPTEG_CACHE_NUM);
+
+        for (i = 0; i < vcpu->arch.hpte_cache_offset; i++) {
+                struct hpte_cache *pte;
+
+                pte = &vcpu->arch.hpte_cache[i];
+                if (!pte->host_va)
+                        continue;
+
+                if ((pte->pte.raddr >= pa_start) &&
+                    (pte->pte.raddr < pa_end)) {
+                        invalidate_pte(pte);
+                }
+        }
+}
+
+struct kvmppc_pte *kvmppc_mmu_find_pte(struct kvm_vcpu *vcpu, u64 ea, bool data)
+{
+        int i;
+        u64 guest_vp;
+
+        guest_vp = vcpu->arch.mmu.ea_to_vp(vcpu, ea, false);
+        for (i=0; i<vcpu->arch.hpte_cache_offset; i++) {
+                struct hpte_cache *pte;
+
+                pte = &vcpu->arch.hpte_cache[i];
+                if (!pte->host_va)
+                        continue;
+
+                if (pte->pte.vpage == guest_vp)
+                        return &pte->pte;
+        }
+
+        return NULL;
+}
+
+static int kvmppc_mmu_hpte_cache_next(struct kvm_vcpu *vcpu)
+{
+        if (vcpu->arch.hpte_cache_offset == HPTEG_CACHE_NUM)
+                kvmppc_mmu_pte_flush(vcpu, 0, 0);
+
+        return vcpu->arch.hpte_cache_offset++;
+}
+
+/* We keep 512 gvsid->hvsid entries, mapping the guest ones to the array using
+ * a hash, so we don't waste cycles on looping */
+static u16 kvmppc_sid_hash(struct kvm_vcpu *vcpu, u64 gvsid)
+{
+        return (u16)(((gvsid >> (SID_MAP_BITS * 7)) & SID_MAP_MASK) ^
+                     ((gvsid >> (SID_MAP_BITS * 6)) & SID_MAP_MASK) ^
+                     ((gvsid >> (SID_MAP_BITS * 5)) & SID_MAP_MASK) ^
+                     ((gvsid >> (SID_MAP_BITS * 4)) & SID_MAP_MASK) ^
+                     ((gvsid >> (SID_MAP_BITS * 3)) & SID_MAP_MASK) ^
+                     ((gvsid >> (SID_MAP_BITS * 2)) & SID_MAP_MASK) ^
+                     ((gvsid >> (SID_MAP_BITS * 1)) & SID_MAP_MASK) ^
+                     ((gvsid >> (SID_MAP_BITS * 0)) & SID_MAP_MASK));
+}
+
+
+static struct kvmppc_sid_map *find_sid_vsid(struct kvm_vcpu *vcpu, u64 gvsid)
+{
+        struct kvmppc_sid_map *map;
+        u16 sid_map_mask;
+
+        if (vcpu->arch.msr & MSR_PR)
+                gvsid |= VSID_PR;
+
+        sid_map_mask = kvmppc_sid_hash(vcpu, gvsid);
+        map = &to_book3s(vcpu)->sid_map[sid_map_mask];
+        if (map->guest_vsid == gvsid) {
+                dprintk_slb("SLB: Searching 0x%llx -> 0x%llx\n",
+                            gvsid, map->host_vsid);
+                return map;
+        }
+
+        map = &to_book3s(vcpu)->sid_map[SID_MAP_MASK - sid_map_mask];
+        if (map->guest_vsid == gvsid) {
+                dprintk_slb("SLB: Searching 0x%llx -> 0x%llx\n",
+                            gvsid, map->host_vsid);
+                return map;
+        }
+
+        dprintk_slb("SLB: Searching 0x%llx -> not found\n", gvsid);
+        return NULL;
+}
+
+int kvmppc_mmu_map_page(struct kvm_vcpu *vcpu, struct kvmppc_pte *orig_pte)
+{
+        pfn_t hpaddr;
+        ulong hash, hpteg, va;
+        u64 vsid;
+        int ret;
+        int rflags = 0x192;
+        int vflags = 0;
+        int attempt = 0;
+        struct kvmppc_sid_map *map;
+
+        /* Get host physical address for gpa */
+        hpaddr = gfn_to_pfn(vcpu->kvm, orig_pte->raddr >> PAGE_SHIFT);
+        if (kvm_is_error_hva(hpaddr)) {
+                printk(KERN_INFO "Couldn't get guest page for gfn %llx!\n", orig_pte->eaddr);
+                return -EINVAL;
+        }
+        hpaddr <<= PAGE_SHIFT;
+#if PAGE_SHIFT == 12
+#elif PAGE_SHIFT == 16
+        hpaddr |= orig_pte->raddr & 0xf000;
+#else
+#error Unknown page size
+#endif
+
+        /* and write the mapping ea -> hpa into the pt */
+        vcpu->arch.mmu.esid_to_vsid(vcpu, orig_pte->eaddr >> SID_SHIFT, &vsid);
+        map = find_sid_vsid(vcpu, vsid);
+        if (!map) {
+                kvmppc_mmu_map_segment(vcpu, orig_pte->eaddr);
+                map = find_sid_vsid(vcpu, vsid);
+        }
+        BUG_ON(!map);
+
+        vsid = map->host_vsid;
+        va = hpt_va(orig_pte->eaddr, vsid, MMU_SEGSIZE_256M);
+
+        if (!orig_pte->may_write)
+                rflags |= HPTE_R_PP;
+        else
+                mark_page_dirty(vcpu->kvm, orig_pte->raddr >> PAGE_SHIFT);
+
+        if (!orig_pte->may_execute)
+                rflags |= HPTE_R_N;
+
+        hash = hpt_hash(va, PTE_SIZE, MMU_SEGSIZE_256M);
+
+map_again:
+        hpteg = ((hash & htab_hash_mask) * HPTES_PER_GROUP);
+
+        /* In case we tried normal mapping already, let's nuke old entries */
+        if (attempt > 1)
+                if (ppc_md.hpte_remove(hpteg) < 0)
+                        return -1;
+
+        ret = ppc_md.hpte_insert(hpteg, va, hpaddr, rflags, vflags, MMU_PAGE_4K, MMU_SEGSIZE_256M);
+
+        if (ret < 0) {
+                /* If we couldn't map a primary PTE, try a secondary */
+#ifdef USE_SECONDARY
+                hash = ~hash;
+                attempt++;
+                if (attempt % 2)
+                        vflags = HPTE_V_SECONDARY;
+                else
+                        vflags = 0;
+#else
+                attempt = 2;
+#endif
+                goto map_again;
+        } else {
+                int hpte_id = kvmppc_mmu_hpte_cache_next(vcpu);
+                struct hpte_cache *pte = &vcpu->arch.hpte_cache[hpte_id];
+
+                dprintk_mmu("KVM: %c%c Map 0x%llx: [%lx] 0x%lx (0x%llx) -> %lx\n",
+                            ((rflags & HPTE_R_PP) == 3) ? '-' : 'w',
+                            (rflags & HPTE_R_N) ? '-' : 'x',
+                            orig_pte->eaddr, hpteg, va, orig_pte->vpage, hpaddr);
+
+                pte->slot = hpteg + (ret & 7);
+                pte->host_va = va;
+                pte->pte = *orig_pte;
+                pte->pfn = hpaddr >> PAGE_SHIFT;
+        }
+
+        return 0;
+}
+
+static struct kvmppc_sid_map *create_sid_map(struct kvm_vcpu *vcpu, u64 gvsid)
+{
+        struct kvmppc_sid_map *map;
+        struct kvmppc_vcpu_book3s *vcpu_book3s = to_book3s(vcpu);
+        u16 sid_map_mask;
+        static int backwards_map = 0;
+
+        if (vcpu->arch.msr & MSR_PR)
+                gvsid |= VSID_PR;
+
+        /* We might get collisions that trap in preceding order, so let's
+           map them differently */
+
+        sid_map_mask = kvmppc_sid_hash(vcpu, gvsid);
+        if (backwards_map)
+                sid_map_mask = SID_MAP_MASK - sid_map_mask;
+
+        map = &to_book3s(vcpu)->sid_map[sid_map_mask];
+
+        /* Make sure we're taking the other map next time */
+        backwards_map = !backwards_map;
+
+        /* Uh-oh ... out of mappings. Let's flush! */
+        if (vcpu_book3s->vsid_next == vcpu_book3s->vsid_max) {
+                vcpu_book3s->vsid_next = vcpu_book3s->vsid_first;
+                memset(vcpu_book3s->sid_map, 0,
+                       sizeof(struct kvmppc_sid_map) * SID_MAP_NUM);
+                kvmppc_mmu_pte_flush(vcpu, 0, 0);
+                kvmppc_mmu_flush_segments(vcpu);
+        }
+        map->host_vsid = vcpu_book3s->vsid_next++;
+
+        map->guest_vsid = gvsid;
+        map->valid = true;
+
+        return map;
+}
+
+static int kvmppc_mmu_next_segment(struct kvm_vcpu *vcpu, ulong esid)
+{
+        int i;
+        int max_slb_size = 64;
+        int found_inval = -1;
+        int r;
+
+        if (!get_paca()->kvm_slb_max)
+                get_paca()->kvm_slb_max = 1;
+
+        /* Are we overwriting? */
+        for (i = 1; i < get_paca()->kvm_slb_max; i++) {
+                if (!(get_paca()->kvm_slb[i].esid & SLB_ESID_V))
+                        found_inval = i;
+                else if ((get_paca()->kvm_slb[i].esid & ESID_MASK) == esid)
+                        return i;
+        }
+
+        /* Found a spare entry that was invalidated before */
+        if (found_inval > 0)
+                return found_inval;
+
+        /* No spare invalid entry, so create one */
+
+        if (mmu_slb_size < 64)
+                max_slb_size = mmu_slb_size;
+
+        /* Overflowing -> purge */
+        if ((get_paca()->kvm_slb_max) == max_slb_size)
+                kvmppc_mmu_flush_segments(vcpu);
+
+        r = get_paca()->kvm_slb_max;
+        get_paca()->kvm_slb_max++;
+
+        return r;
+}
+
+int kvmppc_mmu_map_segment(struct kvm_vcpu *vcpu, ulong eaddr)
+{
+        u64 esid = eaddr >> SID_SHIFT;
+        u64 slb_esid = (eaddr & ESID_MASK) | SLB_ESID_V;
+        u64 slb_vsid = SLB_VSID_USER;
+        u64 gvsid;
+        int slb_index;
+        struct kvmppc_sid_map *map;
+
+        slb_index = kvmppc_mmu_next_segment(vcpu, eaddr & ESID_MASK);
+
+        if (vcpu->arch.mmu.esid_to_vsid(vcpu, esid, &gvsid)) {
+                /* Invalidate an entry */
+                get_paca()->kvm_slb[slb_index].esid = 0;
+                return -ENOENT;
+        }
+
+        map = find_sid_vsid(vcpu, gvsid);
+        if (!map)
+                map = create_sid_map(vcpu, gvsid);
+
+        map->guest_esid = esid;
+
+        slb_vsid |= (map->host_vsid << 12);
+        slb_vsid &= ~SLB_VSID_KP;
+        slb_esid |= slb_index;
+
+        get_paca()->kvm_slb[slb_index].esid = slb_esid;
+        get_paca()->kvm_slb[slb_index].vsid = slb_vsid;
+
+        dprintk_slb("slbmte %#llx, %#llx\n", slb_vsid, slb_esid);
+
+        return 0;
+}
+
+void kvmppc_mmu_flush_segments(struct kvm_vcpu *vcpu)
+{
+        get_paca()->kvm_slb_max = 1;
+        get_paca()->kvm_slb[0].esid = 0;
+}
+
+void kvmppc_mmu_destroy(struct kvm_vcpu *vcpu)
+{
+        kvmppc_mmu_pte_flush(vcpu, 0, 0);
+}
diff --git a/arch/powerpc/kvm/book3s_64_rmhandlers.S b/arch/powerpc/kvm/book3s_64_rmhandlers.S
new file mode 100644
index 000000000000..fb7dd2e9ac88
--- /dev/null
+++ b/arch/powerpc/kvm/book3s_64_rmhandlers.S
@@ -0,0 +1,131 @@
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ *
+ * Copyright SUSE Linux Products GmbH 2009
+ *
+ * Authors: Alexander Graf <agraf@suse.de>
+ */
+
+#include <asm/ppc_asm.h>
+#include <asm/kvm_asm.h>
+#include <asm/reg.h>
+#include <asm/page.h>
+#include <asm/asm-offsets.h>
+#include <asm/exception-64s.h>
+
+/*****************************************************************************
+ *                                                                           *
+ *        Real Mode handlers that need to be in low physical memory          *
+ *                                                                           *
+ ****************************************************************************/
+
+
+.macro INTERRUPT_TRAMPOLINE intno
+
+.global kvmppc_trampoline_\intno
+kvmppc_trampoline_\intno:
+
+        mtspr   SPRN_SPRG_SCRATCH0, r13         /* Save r13 */
+
+        /*
+         * First thing to do is to find out if we're coming
+         * from a KVM guest or a Linux process.
+         *
+         * To distinguish, we check a magic byte in the PACA
+         */
+        mfspr   r13, SPRN_SPRG_PACA             /* r13 = PACA */
+        std     r12, (PACA_EXMC + EX_R12)(r13)
+        mfcr    r12
+        stw     r12, (PACA_EXMC + EX_CCR)(r13)
+        lbz     r12, PACA_KVM_IN_GUEST(r13)
+        cmpwi   r12, 0
+        bne     ..kvmppc_handler_hasmagic_\intno
+        /* No KVM guest? Then jump back to the Linux handler! */
+        lwz     r12, (PACA_EXMC + EX_CCR)(r13)
+        mtcr    r12
+        ld      r12, (PACA_EXMC + EX_R12)(r13)
+        mfspr   r13, SPRN_SPRG_SCRATCH0         /* r13 = original r13 */
+        b       kvmppc_resume_\intno            /* Get back original handler */
+
+        /* Now we know we're handling a KVM guest */
+..kvmppc_handler_hasmagic_\intno:
+        /* Unset guest state */
+        li      r12, 0
+        stb     r12, PACA_KVM_IN_GUEST(r13)
+
+        std     r1, (PACA_EXMC+EX_R9)(r13)
+        std     r10, (PACA_EXMC+EX_R10)(r13)
+        std     r11, (PACA_EXMC+EX_R11)(r13)
+        std     r2, (PACA_EXMC+EX_R13)(r13)
+
+        mfsrr0  r10
+        mfsrr1  r11
+
+        /* Restore R1/R2 so we can handle faults */
+        ld      r1, PACAR1(r13)
+        ld      r2, (PACA_EXMC+EX_SRR0)(r13)
+
+        /* Let's store which interrupt we're handling */
+        li      r12, \intno
+
+        /* Jump into the SLB exit code that goes to the highmem handler */
+        b       kvmppc_handler_trampoline_exit
+
+.endm
+
+INTERRUPT_TRAMPOLINE    BOOK3S_INTERRUPT_SYSTEM_RESET
+INTERRUPT_TRAMPOLINE    BOOK3S_INTERRUPT_MACHINE_CHECK
+INTERRUPT_TRAMPOLINE    BOOK3S_INTERRUPT_DATA_STORAGE
+INTERRUPT_TRAMPOLINE    BOOK3S_INTERRUPT_DATA_SEGMENT
+INTERRUPT_TRAMPOLINE    BOOK3S_INTERRUPT_INST_STORAGE
+INTERRUPT_TRAMPOLINE    BOOK3S_INTERRUPT_INST_SEGMENT
+INTERRUPT_TRAMPOLINE    BOOK3S_INTERRUPT_EXTERNAL
+INTERRUPT_TRAMPOLINE    BOOK3S_INTERRUPT_ALIGNMENT
+INTERRUPT_TRAMPOLINE    BOOK3S_INTERRUPT_PROGRAM
+INTERRUPT_TRAMPOLINE    BOOK3S_INTERRUPT_FP_UNAVAIL
+INTERRUPT_TRAMPOLINE    BOOK3S_INTERRUPT_DECREMENTER
+INTERRUPT_TRAMPOLINE    BOOK3S_INTERRUPT_SYSCALL
+INTERRUPT_TRAMPOLINE    BOOK3S_INTERRUPT_TRACE
+INTERRUPT_TRAMPOLINE    BOOK3S_INTERRUPT_PERFMON
+INTERRUPT_TRAMPOLINE    BOOK3S_INTERRUPT_ALTIVEC
+INTERRUPT_TRAMPOLINE    BOOK3S_INTERRUPT_VSX
+
+/*
+ * This trampoline brings us back to a real mode handler
+ *
+ * Input Registers:
+ *
+ * R6 = SRR0
+ * R7 = SRR1
+ * LR = real-mode IP
+ *
+ */
+.global kvmppc_handler_lowmem_trampoline
+kvmppc_handler_lowmem_trampoline:
+
+        mtsrr0  r6
+        mtsrr1  r7
+        blr
+kvmppc_handler_lowmem_trampoline_end:
+
+.global kvmppc_trampoline_lowmem
+kvmppc_trampoline_lowmem:
+        .long kvmppc_handler_lowmem_trampoline - _stext
+
+.global kvmppc_trampoline_enter
+kvmppc_trampoline_enter:
+        .long kvmppc_handler_trampoline_enter - _stext
+
+#include "book3s_64_slb.S"
+
diff --git a/arch/powerpc/kvm/book3s_64_slb.S b/arch/powerpc/kvm/book3s_64_slb.S
new file mode 100644
index 000000000000..ecd237a03fd0
--- /dev/null
+++ b/arch/powerpc/kvm/book3s_64_slb.S
@@ -0,0 +1,262 @@
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ *
+ * Copyright SUSE Linux Products GmbH 2009
+ *
+ * Authors: Alexander Graf <agraf@suse.de>
+ */
+
+#define SHADOW_SLB_ESID(num)    (SLBSHADOW_SAVEAREA + (num * 0x10))
+#define SHADOW_SLB_VSID(num)    (SLBSHADOW_SAVEAREA + (num * 0x10) + 0x8)
+#define UNBOLT_SLB_ENTRY(num) \
+        ld      r9, SHADOW_SLB_ESID(num)(r12); \
+        /* Invalid? Skip. */; \
+        rldicl. r0, r9, 37, 63; \
+        beq     slb_entry_skip_ ## num; \
+        xoris   r9, r9, SLB_ESID_V@h; \
+        std     r9, SHADOW_SLB_ESID(num)(r12); \
+  slb_entry_skip_ ## num:
+
+#define REBOLT_SLB_ENTRY(num) \
+        ld      r10, SHADOW_SLB_ESID(num)(r11); \
+        cmpdi   r10, 0; \
+        beq     slb_exit_skip_1; \
+        oris    r10, r10, SLB_ESID_V@h; \
+        ld      r9, SHADOW_SLB_VSID(num)(r11); \
+        slbmte  r9, r10; \
+        std     r10, SHADOW_SLB_ESID(num)(r11); \
+slb_exit_skip_ ## num:
+
+/******************************************************************************
+ *                                                                            *
+ *                               Entry code                                   *
+ *                                                                            *
+ *****************************************************************************/
+
+.global kvmppc_handler_trampoline_enter
+kvmppc_handler_trampoline_enter:
+
+        /* Required state:
+         *
+         * MSR = ~IR|DR
+         * R13 = PACA
+         * R9 = guest IP
+         * R10 = guest MSR
+         * R11 = free
+         * R12 = free
+         * PACA[PACA_EXMC + EX_R9] = guest R9
+         * PACA[PACA_EXMC + EX_R10] = guest R10
+         * PACA[PACA_EXMC + EX_R11] = guest R11
+         * PACA[PACA_EXMC + EX_R12] = guest R12
+         * PACA[PACA_EXMC + EX_R13] = guest R13
+         * PACA[PACA_EXMC + EX_CCR] = guest CR
+         * PACA[PACA_EXMC + EX_R3] = guest XER
+         */
+
+        mtsrr0  r9
+        mtsrr1  r10
+
+        mtspr   SPRN_SPRG_SCRATCH0, r0
+
+        /* Remove LPAR shadow entries */
+
+#if SLB_NUM_BOLTED == 3
+
+        ld      r12, PACA_SLBSHADOWPTR(r13)
+
+        /* Save off the first entry so we can slbie it later */
+        ld      r10, SHADOW_SLB_ESID(0)(r12)
+        ld      r11, SHADOW_SLB_VSID(0)(r12)
+
+        /* Remove bolted entries */
+        UNBOLT_SLB_ENTRY(0)
+        UNBOLT_SLB_ENTRY(1)
+        UNBOLT_SLB_ENTRY(2)
+        
+#else
+#error unknown number of bolted entries
+#endif
+
+        /* Flush SLB */
+
+        slbia
+
+        /* r0 = esid & ESID_MASK */
+        rldicr  r10, r10, 0, 35
+        /* r0 |= CLASS_BIT(VSID) */
+        rldic   r12, r11, 56 - 36, 36
+        or      r10, r10, r12
+        slbie   r10
+
+        isync
+
+        /* Fill SLB with our shadow */
+
+        lbz     r12, PACA_KVM_SLB_MAX(r13)
+        mulli   r12, r12, 16
+        addi    r12, r12, PACA_KVM_SLB
+        add     r12, r12, r13
+
+        /* for (r11 = kvm_slb; r11 < kvm_slb + kvm_slb_size; r11+=slb_entry) */
+        li      r11, PACA_KVM_SLB
+        add     r11, r11, r13
+
+slb_loop_enter:
+
+        ld      r10, 0(r11)
+
+        rldicl. r0, r10, 37, 63
+        beq     slb_loop_enter_skip
+
+        ld      r9, 8(r11)
+        slbmte  r9, r10
+
+slb_loop_enter_skip:
+        addi    r11, r11, 16
+        cmpd    cr0, r11, r12
+        blt     slb_loop_enter
+
+slb_do_enter:
+
+        /* Enter guest */
+
+        mfspr   r0, SPRN_SPRG_SCRATCH0
+
+        ld      r9, (PACA_EXMC+EX_R9)(r13)
+        ld      r10, (PACA_EXMC+EX_R10)(r13)
+        ld      r12, (PACA_EXMC+EX_R12)(r13)
+
+        lwz     r11, (PACA_EXMC+EX_CCR)(r13)
+        mtcr    r11
+
+        ld      r11, (PACA_EXMC+EX_R3)(r13)
+        mtxer   r11
+
+        ld      r11, (PACA_EXMC+EX_R11)(r13)
+        ld      r13, (PACA_EXMC+EX_R13)(r13)
+
+        RFI
+kvmppc_handler_trampoline_enter_end:
+
+
+
+/******************************************************************************
+ *                                                                            *
+ *                               Exit code                                    *
+ *                                                                            *
+ *****************************************************************************/
+
+.global kvmppc_handler_trampoline_exit
+kvmppc_handler_trampoline_exit:
+
+        /* Register usage at this point:
+         *
+         * SPRG_SCRATCH0 = guest R13
+         * R01           = host R1
+         * R02           = host R2
+         * R10           = guest PC
+         * R11           = guest MSR
+         * R12           = exit handler id
+         * R13           = PACA
+         * PACA.exmc.CCR  = guest CR
+         * PACA.exmc.R9  = guest R1
+         * PACA.exmc.R10 = guest R10
+         * PACA.exmc.R11 = guest R11
+         * PACA.exmc.R12 = guest R12
+         * PACA.exmc.R13 = guest R2
+         *
+         */
+
+        /* Save registers */
+
+        std     r0, (PACA_EXMC+EX_SRR0)(r13)
+        std     r9, (PACA_EXMC+EX_R3)(r13)
+        std     r10, (PACA_EXMC+EX_LR)(r13)
+        std     r11, (PACA_EXMC+EX_DAR)(r13)
+
+        /*
+         * In order for us to easily get the last instruction,
+         * we got the #vmexit at, we exploit the fact that the
+         * virtual layout is still the same here, so we can just
+         * ld from the guest's PC address
+         */
+
+        /* We only load the last instruction when it's safe */
+        cmpwi   r12, BOOK3S_INTERRUPT_DATA_STORAGE
+        beq     ld_last_inst
+        cmpwi   r12, BOOK3S_INTERRUPT_PROGRAM
+        beq     ld_last_inst
+
+        b       no_ld_last_inst
+
+ld_last_inst:
+        /* Save off the guest instruction we're at */
+        /*    1) enable paging for data */
+        mfmsr   r9
+        ori     r11, r9, MSR_DR                 /* Enable paging for data */
+        mtmsr   r11
+        /*    2) fetch the instruction */
+        lwz     r0, 0(r10)
+        /*    3) disable paging again */
+        mtmsr   r9
+
+no_ld_last_inst:
+
+        /* Restore bolted entries from the shadow and fix it along the way */
+
+        /* We don't store anything in entry 0, so we don't need to take care of it */
+        slbia
+        isync
+
+#if SLB_NUM_BOLTED == 3
+
+        ld      r11, PACA_SLBSHADOWPTR(r13)
+
+        REBOLT_SLB_ENTRY(0)
+        REBOLT_SLB_ENTRY(1)
+        REBOLT_SLB_ENTRY(2)
+        
+#else
+#error unknown number of bolted entries
+#endif
+
+slb_do_exit:
+
+        /* Restore registers */
+
+        ld      r11, (PACA_EXMC+EX_DAR)(r13)
+        ld      r10, (PACA_EXMC+EX_LR)(r13)
+        ld      r9, (PACA_EXMC+EX_R3)(r13)
+
+        /* Save last inst */
+        stw     r0, (PACA_EXMC+EX_LR)(r13)
+
+        /* Save DAR and DSISR before going to paged mode */
+        mfdar   r0
+        std     r0, (PACA_EXMC+EX_DAR)(r13)
+        mfdsisr r0
+        stw     r0, (PACA_EXMC+EX_DSISR)(r13)
+
+        /* RFI into the highmem handler */
+        mfmsr   r0
+        ori     r0, r0, MSR_IR|MSR_DR|MSR_RI    /* Enable paging */
+        mtsrr1  r0
+        ld      r0, PACASAVEDMSR(r13)           /* Highmem handler address */
+        mtsrr0  r0
+
+        mfspr   r0, SPRN_SPRG_SCRATCH0
+
+        RFI
+kvmppc_handler_trampoline_exit_end:
+
diff --git a/arch/powerpc/kvm/booke.c b/arch/powerpc/kvm/booke.c
index e7bf4d029484..06f5a9ecc42c 100644
--- a/arch/powerpc/kvm/booke.c
+++ b/arch/powerpc/kvm/booke.c
@@ -520,6 +520,11 @@ int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
         return kvmppc_core_vcpu_translate(vcpu, tr);
 }
 
+int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
+{
+        return -ENOTSUPP;
+}
+
 int __init kvmppc_booke_init(void)
 {
         unsigned long ivor[16];
diff --git a/arch/powerpc/kvm/emulate.c b/arch/powerpc/kvm/emulate.c
index 7737146af3fb..4a9ac6640fad 100644
--- a/arch/powerpc/kvm/emulate.c
+++ b/arch/powerpc/kvm/emulate.c
@@ -18,7 +18,7 @@
  */
 
 #include <linux/jiffies.h>
-#include <linux/timer.h>
+#include <linux/hrtimer.h>
 #include <linux/types.h>
 #include <linux/string.h>
 #include <linux/kvm_host.h>
@@ -32,6 +32,7 @@
 #include "trace.h"
 
 #define OP_TRAP 3
+#define OP_TRAP_64 2
 
 #define OP_31_XOP_LWZX      23
 #define OP_31_XOP_LBZX      87
@@ -64,19 +65,45 @@
 #define OP_STH  44
 #define OP_STHU 45
 
+#ifdef CONFIG_PPC64
+static int kvmppc_dec_enabled(struct kvm_vcpu *vcpu)
+{
+        return 1;
+}
+#else
+static int kvmppc_dec_enabled(struct kvm_vcpu *vcpu)
+{
+        return vcpu->arch.tcr & TCR_DIE;
+}
+#endif
+
 void kvmppc_emulate_dec(struct kvm_vcpu *vcpu)
 {
-        if (vcpu->arch.tcr & TCR_DIE) {
+        unsigned long dec_nsec;
+
+        pr_debug("mtDEC: %x\n", vcpu->arch.dec);
+#ifdef CONFIG_PPC64
+        /* POWER4+ triggers a dec interrupt if the value is < 0 */
+        if (vcpu->arch.dec & 0x80000000) {
+                hrtimer_try_to_cancel(&vcpu->arch.dec_timer);
+                kvmppc_core_queue_dec(vcpu);
+                return;
+        }
+#endif
+        if (kvmppc_dec_enabled(vcpu)) {
                 /* The decrementer ticks at the same rate as the timebase, so
                  * that's how we convert the guest DEC value to the number of
                  * host ticks. */
-                unsigned long nr_jiffies;
 
-                nr_jiffies = vcpu->arch.dec / tb_ticks_per_jiffy;
-                mod_timer(&vcpu->arch.dec_timer,
-                          get_jiffies_64() + nr_jiffies);
+                hrtimer_try_to_cancel(&vcpu->arch.dec_timer);
+                dec_nsec = vcpu->arch.dec;
+                dec_nsec *= 1000;
+                dec_nsec /= tb_ticks_per_usec;
+                hrtimer_start(&vcpu->arch.dec_timer, ktime_set(0, dec_nsec),
+                              HRTIMER_MODE_REL);
+                vcpu->arch.dec_jiffies = get_tb();
         } else {
-                del_timer(&vcpu->arch.dec_timer);
+                hrtimer_try_to_cancel(&vcpu->arch.dec_timer);
         }
 }
 
@@ -111,9 +138,15 @@ int kvmppc_emulate_instruction(struct kvm_run *run, struct kvm_vcpu *vcpu)
         /* this default type might be overwritten by subcategories */
         kvmppc_set_exit_type(vcpu, EMULATED_INST_EXITS);
 
+        pr_debug(KERN_INFO "Emulating opcode %d / %d\n", get_op(inst), get_xop(inst));
+
         switch (get_op(inst)) {
         case OP_TRAP:
+#ifdef CONFIG_PPC64
+        case OP_TRAP_64:
+#else
                 vcpu->arch.esr |= ESR_PTR;
+#endif
                 kvmppc_core_queue_program(vcpu);
                 advance = 0;
                 break;
@@ -188,17 +221,19 @@ int kvmppc_emulate_instruction(struct kvm_run *run, struct kvm_vcpu *vcpu)
                         case SPRN_SRR1:
                                 vcpu->arch.gpr[rt] = vcpu->arch.srr1; break;
                         case SPRN_PVR:
-                                vcpu->arch.gpr[rt] = mfspr(SPRN_PVR); break;
+                                vcpu->arch.gpr[rt] = vcpu->arch.pvr; break;
                         case SPRN_PIR:
-                                vcpu->arch.gpr[rt] = mfspr(SPRN_PIR); break;
+                                vcpu->arch.gpr[rt] = vcpu->vcpu_id; break;
+                        case SPRN_MSSSR0:
+                                vcpu->arch.gpr[rt] = 0; break;
 
                         /* Note: mftb and TBRL/TBWL are user-accessible, so
                          * the guest can always access the real TB anyways.
                          * In fact, we probably will never see these traps. */
                         case SPRN_TBWL:
-                                vcpu->arch.gpr[rt] = mftbl(); break;
+                                vcpu->arch.gpr[rt] = get_tb() >> 32; break;
                         case SPRN_TBWU:
-                                vcpu->arch.gpr[rt] = mftbu(); break;
+                                vcpu->arch.gpr[rt] = get_tb(); break;
 
                         case SPRN_SPRG0:
                                 vcpu->arch.gpr[rt] = vcpu->arch.sprg0; break;
@@ -211,6 +246,13 @@ int kvmppc_emulate_instruction(struct kvm_run *run, struct kvm_vcpu *vcpu)
                         /* Note: SPRG4-7 are user-readable, so we don't get
                          * a trap. */
 
+                        case SPRN_DEC:
+                        {
+                                u64 jd = get_tb() - vcpu->arch.dec_jiffies;
+                                vcpu->arch.gpr[rt] = vcpu->arch.dec - jd;
+                                pr_debug(KERN_INFO "mfDEC: %x - %llx = %lx\n", vcpu->arch.dec, jd, vcpu->arch.gpr[rt]);
+                                break;
+                        }
                         default:
                                 emulated = kvmppc_core_emulate_mfspr(vcpu, sprn, rt);
                                 if (emulated == EMULATE_FAIL) {
@@ -260,6 +302,8 @@ int kvmppc_emulate_instruction(struct kvm_run *run, struct kvm_vcpu *vcpu)
                         case SPRN_TBWL: break;
                         case SPRN_TBWU: break;
 
+                        case SPRN_MSSSR0: break;
+
                         case SPRN_DEC:
                                 vcpu->arch.dec = vcpu->arch.gpr[rs];
                                 kvmppc_emulate_dec(vcpu);
diff --git a/arch/powerpc/kvm/powerpc.c b/arch/powerpc/kvm/powerpc.c
index 5902bbc2411e..f06cf93b178e 100644
--- a/arch/powerpc/kvm/powerpc.c
+++ b/arch/powerpc/kvm/powerpc.c
@@ -23,6 +23,7 @@
 #include <linux/kvm_host.h>
 #include <linux/module.h>
 #include <linux/vmalloc.h>
+#include <linux/hrtimer.h>
 #include <linux/fs.h>
 #include <asm/cputable.h>
 #include <asm/uaccess.h>
@@ -144,6 +145,9 @@ int kvm_dev_ioctl_check_extension(long ext)
         int r;
 
         switch (ext) {
+        case KVM_CAP_PPC_SEGSTATE:
+                r = 1;
+                break;
         case KVM_CAP_COALESCED_MMIO:
                 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
                 break;
@@ -209,10 +213,25 @@ static void kvmppc_decrementer_func(unsigned long data)
         }
 }
 
+/*
+ * low level hrtimer wake routine. Because this runs in hardirq context
+ * we schedule a tasklet to do the real work.
+ */
+enum hrtimer_restart kvmppc_decrementer_wakeup(struct hrtimer *timer)
+{
+        struct kvm_vcpu *vcpu;
+
+        vcpu = container_of(timer, struct kvm_vcpu, arch.dec_timer);
+        tasklet_schedule(&vcpu->arch.tasklet);
+
+        return HRTIMER_NORESTART;
+}
+
 int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
 {
-        setup_timer(&vcpu->arch.dec_timer, kvmppc_decrementer_func,
-                    (unsigned long)vcpu);
+        hrtimer_init(&vcpu->arch.dec_timer, CLOCK_REALTIME, HRTIMER_MODE_ABS);
+        tasklet_init(&vcpu->arch.tasklet, kvmppc_decrementer_func, (ulong)vcpu);
+        vcpu->arch.dec_timer.function = kvmppc_decrementer_wakeup;
 
         return 0;
 }
@@ -410,11 +429,6 @@ out:
         return r;
 }
 
-int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
-{
-        return -ENOTSUPP;
-}
-
 long kvm_arch_vm_ioctl(struct file *filp,
                        unsigned int ioctl, unsigned long arg)
 {
diff --git a/arch/powerpc/kvm/timing.c b/arch/powerpc/kvm/timing.c
index 2aa371e30079..70378551c0cc 100644
--- a/arch/powerpc/kvm/timing.c
+++ b/arch/powerpc/kvm/timing.c
@@ -23,6 +23,7 @@
 #include <linux/seq_file.h>
 #include <linux/debugfs.h>
 #include <linux/uaccess.h>
+#include <linux/module.h>
 
 #include <asm/time.h>
 #include <asm-generic/div64.h>
diff --git a/arch/powerpc/kvm/trace.h b/arch/powerpc/kvm/trace.h
index 67f219de0455..a8e840018052 100644
--- a/arch/powerpc/kvm/trace.h
+++ b/arch/powerpc/kvm/trace.h
@@ -12,8 +12,8 @@
  * Tracepoint for guest mode entry.
  */
 TRACE_EVENT(kvm_ppc_instr,
-        TP_PROTO(unsigned int inst, unsigned long pc, unsigned int emulate),
-        TP_ARGS(inst, pc, emulate),
+        TP_PROTO(unsigned int inst, unsigned long _pc, unsigned int emulate),
+        TP_ARGS(inst, _pc, emulate),
 
         TP_STRUCT__entry(
                 __field(        unsigned int,   inst            )
@@ -23,7 +23,7 @@ TRACE_EVENT(kvm_ppc_instr,
 
         TP_fast_assign(
                 __entry->inst           = inst;
-                __entry->pc             = pc;
+                __entry->pc             = _pc;
                 __entry->emulate        = emulate;
         ),
 
diff --git a/arch/powerpc/lib/copy_32.S b/arch/powerpc/lib/copy_32.S
index c657de59abca..74a7f4130b4c 100644
--- a/arch/powerpc/lib/copy_32.S
+++ b/arch/powerpc/lib/copy_32.S
@@ -98,20 +98,7 @@ _GLOBAL(cacheable_memzero)
         bdnz    4b
 3:      mtctr   r9
         li      r7,4
-#if !defined(CONFIG_8xx)
 10:     dcbz    r7,r6
-#else
-10:     stw     r4, 4(r6)
-        stw     r4, 8(r6)
-        stw     r4, 12(r6)
-        stw     r4, 16(r6)
-#if CACHE_LINE_SIZE >= 32
-        stw     r4, 20(r6)
-        stw     r4, 24(r6)
-        stw     r4, 28(r6)
-        stw     r4, 32(r6)
-#endif /* CACHE_LINE_SIZE */
-#endif
         addi    r6,r6,CACHELINE_BYTES
         bdnz    10b
         clrlwi  r5,r8,32-LG_CACHELINE_BYTES
@@ -200,9 +187,7 @@ _GLOBAL(cacheable_memcpy)
         mtctr   r0
         beq     63f
 53:
-#if !defined(CONFIG_8xx)
         dcbz    r11,r6
-#endif
         COPY_16_BYTES
 #if L1_CACHE_BYTES >= 32
         COPY_16_BYTES
@@ -356,14 +341,6 @@ _GLOBAL(__copy_tofrom_user)
         li      r11,4
         beq     63f
 
-#ifdef CONFIG_8xx
-        /* Don't use prefetch on 8xx */
-        mtctr   r0
-        li      r0,0
-53:     COPY_16_BYTES_WITHEX(0)
-        bdnz    53b
-
-#else /* not CONFIG_8xx */
         /* Here we decide how far ahead to prefetch the source */
         li      r3,4
         cmpwi   r0,1
@@ -416,7 +393,6 @@ _GLOBAL(__copy_tofrom_user)
         li      r3,4
         li      r7,0
         bne     114b
-#endif /* CONFIG_8xx */
 
 63:     srwi.   r0,r5,2
         mtctr   r0
diff --git a/arch/powerpc/lib/locks.c b/arch/powerpc/lib/locks.c
index 79d0fa3a470d..58e14fba11b1 100644
--- a/arch/powerpc/lib/locks.c
+++ b/arch/powerpc/lib/locks.c
@@ -25,7 +25,7 @@
 #include <asm/smp.h>
 #include <asm/firmware.h>
 
-void __spin_yield(raw_spinlock_t *lock)
+void __spin_yield(arch_spinlock_t *lock)
 {
         unsigned int lock_value, holder_cpu, yield_count;
 
@@ -55,7 +55,7 @@ void __spin_yield(raw_spinlock_t *lock)
  * This turns out to be the same for read and write locks, since
  * we only know the holder if it is write-locked.
  */
-void __rw_yield(raw_rwlock_t *rw)
+void __rw_yield(arch_rwlock_t *rw)
 {
         int lock_value;
         unsigned int holder_cpu, yield_count;
@@ -82,7 +82,7 @@ void __rw_yield(raw_rwlock_t *rw)
 }
 #endif
 
-void __raw_spin_unlock_wait(raw_spinlock_t *lock)
+void arch_spin_unlock_wait(arch_spinlock_t *lock)
 {
         while (lock->slock) {
                 HMT_low();
@@ -92,4 +92,4 @@ void __raw_spin_unlock_wait(raw_spinlock_t *lock)
         HMT_medium();
 }
 
-EXPORT_SYMBOL(__raw_spin_unlock_wait);
+EXPORT_SYMBOL(arch_spin_unlock_wait);
diff --git a/arch/powerpc/mm/40x_mmu.c b/arch/powerpc/mm/40x_mmu.c
index f5e7b9ce63dd..08dfa8e6d86f 100644
--- a/arch/powerpc/mm/40x_mmu.c
+++ b/arch/powerpc/mm/40x_mmu.c
@@ -91,7 +91,7 @@ void __init MMU_init_hw(void)
 #define LARGE_PAGE_SIZE_16M     (1<<24)
 #define LARGE_PAGE_SIZE_4M      (1<<22)
 
-unsigned long __init mmu_mapin_ram(void)
+unsigned long __init mmu_mapin_ram(unsigned long top)
 {
         unsigned long v, s, mapped;
         phys_addr_t p;
diff --git a/arch/powerpc/mm/44x_mmu.c b/arch/powerpc/mm/44x_mmu.c
index 98052ac96580..3986264b0993 100644
--- a/arch/powerpc/mm/44x_mmu.c
+++ b/arch/powerpc/mm/44x_mmu.c
@@ -88,7 +88,7 @@ void __init MMU_init_hw(void)
         flush_instruction_cache();
 }
 
-unsigned long __init mmu_mapin_ram(void)
+unsigned long __init mmu_mapin_ram(unsigned long top)
 {
         unsigned long addr;
 
diff --git a/arch/powerpc/mm/Makefile b/arch/powerpc/mm/Makefile
index 6fb8fc8d2fea..ce68708bbad5 100644
--- a/arch/powerpc/mm/Makefile
+++ b/arch/powerpc/mm/Makefile
@@ -28,7 +28,10 @@ obj-$(CONFIG_44x)		+= 44x_mmu.o
 obj-$(CONFIG_FSL_BOOKE)         += fsl_booke_mmu.o
 obj-$(CONFIG_NEED_MULTIPLE_NODES) += numa.o
 obj-$(CONFIG_PPC_MM_SLICES)     += slice.o
-obj-$(CONFIG_HUGETLB_PAGE)      += hugetlbpage.o
+ifeq ($(CONFIG_HUGETLB_PAGE),y)
+obj-y                           += hugetlbpage.o
+obj-$(CONFIG_PPC_STD_MMU_64)    += hugetlbpage-hash64.o
+endif
 obj-$(CONFIG_PPC_SUBPAGE_PROT)  += subpage-prot.o
 obj-$(CONFIG_NOT_COHERENT_CACHE) += dma-noncoherent.o
 obj-$(CONFIG_HIGHMEM)           += highmem.o
diff --git a/arch/powerpc/mm/fault.c b/arch/powerpc/mm/fault.c
index e7dae82c1285..26fb6b990b0a 100644
--- a/arch/powerpc/mm/fault.c
+++ b/arch/powerpc/mm/fault.c
@@ -40,7 +40,7 @@
 #include <asm/uaccess.h>
 #include <asm/tlbflush.h>
 #include <asm/siginfo.h>
-
+#include <mm/mmu_decl.h>
 
 #ifdef CONFIG_KPROBES
 static inline int notify_page_fault(struct pt_regs *regs)
@@ -246,6 +246,12 @@ good_area:
                 goto bad_area;
 #endif /* CONFIG_6xx */
 #if defined(CONFIG_8xx)
+        /* 8xx sometimes need to load a invalid/non-present TLBs.
+         * These must be invalidated separately as linux mm don't.
+         */
+        if (error_code & 0x40000000) /* no translation? */
+                _tlbil_va(address, 0, 0, 0);
+
         /* The MPC8xx seems to always set 0x80000000, which is
          * "undefined".  Of those that can be set, this is the only
          * one which seems bad.
diff --git a/arch/powerpc/mm/fsl_booke_mmu.c b/arch/powerpc/mm/fsl_booke_mmu.c
index dc93e95b256e..c5394728bf2e 100644
--- a/arch/powerpc/mm/fsl_booke_mmu.c
+++ b/arch/powerpc/mm/fsl_booke_mmu.c
@@ -54,26 +54,35 @@
 
 #include "mmu_decl.h"
 
-extern void loadcam_entry(unsigned int index);
 unsigned int tlbcam_index;
-static unsigned long cam[CONFIG_LOWMEM_CAM_NUM];
 
-#define NUM_TLBCAMS     (16)
+#define NUM_TLBCAMS     (64)
 
 #if defined(CONFIG_LOWMEM_CAM_NUM_BOOL) && (CONFIG_LOWMEM_CAM_NUM >= NUM_TLBCAMS)
 #error "LOWMEM_CAM_NUM must be less than NUM_TLBCAMS"
 #endif
 
-struct tlbcam TLBCAM[NUM_TLBCAMS];
+struct tlbcam {
+        u32     MAS0;
+        u32     MAS1;
+        unsigned long   MAS2;
+        u32     MAS3;
+        u32     MAS7;
+} TLBCAM[NUM_TLBCAMS];
 
 struct tlbcamrange {
-        unsigned long start;
+        unsigned long start;
         unsigned long limit;
         phys_addr_t phys;
 } tlbcam_addrs[NUM_TLBCAMS];
 
 extern unsigned int tlbcam_index;
 
+unsigned long tlbcam_sz(int idx)
+{
+        return tlbcam_addrs[idx].limit - tlbcam_addrs[idx].start + 1;
+}
+
 /*
  * Return PA for this VA if it is mapped by a CAM, or 0
  */
@@ -94,23 +103,36 @@ unsigned long p_mapped_by_tlbcam(phys_addr_t pa)
         int b;
         for (b = 0; b < tlbcam_index; ++b)
                 if (pa >= tlbcam_addrs[b].phys
-                    && pa < (tlbcam_addrs[b].limit-tlbcam_addrs[b].start)
+                        && pa < (tlbcam_addrs[b].limit-tlbcam_addrs[b].start)
                               +tlbcam_addrs[b].phys)
                         return tlbcam_addrs[b].start+(pa-tlbcam_addrs[b].phys);
         return 0;
 }
 
+void loadcam_entry(int idx)
+{
+        mtspr(SPRN_MAS0, TLBCAM[idx].MAS0);
+        mtspr(SPRN_MAS1, TLBCAM[idx].MAS1);
+        mtspr(SPRN_MAS2, TLBCAM[idx].MAS2);
+        mtspr(SPRN_MAS3, TLBCAM[idx].MAS3);
+
+        if (cur_cpu_spec->cpu_features & MMU_FTR_BIG_PHYS)
+                mtspr(SPRN_MAS7, TLBCAM[idx].MAS7);
+
+        asm volatile("isync;tlbwe;isync" : : : "memory");
+}
+
 /*
  * Set up one of the I/D BAT (block address translation) register pairs.
  * The parameters are not checked; in particular size must be a power
  * of 4 between 4k and 256M.
  */
-void settlbcam(int index, unsigned long virt, phys_addr_t phys,
-                unsigned int size, int flags, unsigned int pid)
+static void settlbcam(int index, unsigned long virt, phys_addr_t phys,
+                unsigned long size, unsigned long flags, unsigned int pid)
 {
         unsigned int tsize, lz;
 
-        asm ("cntlzw %0,%1" : "=r" (lz) : "r" (size));
+        asm (PPC_CNTLZL "%0,%1" : "=r" (lz) : "r" (size));
         tsize = 21 - lz;
 
 #ifdef CONFIG_SMP
@@ -128,8 +150,10 @@ void settlbcam(int index, unsigned long virt, phys_addr_t phys,
         TLBCAM[index].MAS2 |= (flags & _PAGE_GUARDED) ? MAS2_G : 0;
         TLBCAM[index].MAS2 |= (flags & _PAGE_ENDIAN) ? MAS2_E : 0;
 
-        TLBCAM[index].MAS3 = (phys & PAGE_MASK) | MAS3_SX | MAS3_SR;
+        TLBCAM[index].MAS3 = (phys & MAS3_RPN) | MAS3_SX | MAS3_SR;
         TLBCAM[index].MAS3 |= ((flags & _PAGE_RW) ? MAS3_SW : 0);
+        if (cur_cpu_spec->cpu_features & MMU_FTR_BIG_PHYS)
+                TLBCAM[index].MAS7 = (u64)phys >> 32;
 
 #ifndef CONFIG_KGDB /* want user access for breakpoints */
         if (flags & _PAGE_USER) {
@@ -148,27 +172,44 @@ void settlbcam(int index, unsigned long virt, phys_addr_t phys,
         loadcam_entry(index);
 }
 
-void invalidate_tlbcam_entry(int index)
-{
-        TLBCAM[index].MAS0 = MAS0_TLBSEL(1) | MAS0_ESEL(index);
-        TLBCAM[index].MAS1 = ~MAS1_VALID;
-
-        loadcam_entry(index);
-}
-
-unsigned long __init mmu_mapin_ram(void)
+unsigned long map_mem_in_cams(unsigned long ram, int max_cam_idx)
 {
+        int i;
         unsigned long virt = PAGE_OFFSET;
         phys_addr_t phys = memstart_addr;
+        unsigned long amount_mapped = 0;
+        unsigned long max_cam = (mfspr(SPRN_TLB1CFG) >> 16) & 0xf;
+
+        /* Convert (4^max) kB to (2^max) bytes */
+        max_cam = max_cam * 2 + 10;
 
-        while (tlbcam_index < ARRAY_SIZE(cam) && cam[tlbcam_index]) {
-                settlbcam(tlbcam_index, virt, phys, cam[tlbcam_index], PAGE_KERNEL_X, 0);
-                virt += cam[tlbcam_index];
-                phys += cam[tlbcam_index];
-                tlbcam_index++;
+        /* Calculate CAM values */
+        for (i = 0; ram && i < max_cam_idx; i++) {
+                unsigned int camsize = __ilog2(ram) & ~1U;
+                unsigned int align = __ffs(virt | phys) & ~1U;
+                unsigned long cam_sz;
+
+                if (camsize > align)
+                        camsize = align;
+                if (camsize > max_cam)
+                        camsize = max_cam;
+
+                cam_sz = 1UL << camsize;
+                settlbcam(i, virt, phys, cam_sz, PAGE_KERNEL_X, 0);
+
+                ram -= cam_sz;
+                amount_mapped += cam_sz;
+                virt += cam_sz;
+                phys += cam_sz;
         }
+        tlbcam_index = i;
 
-        return virt - PAGE_OFFSET;
+        return amount_mapped;
+}
+
+unsigned long __init mmu_mapin_ram(unsigned long top)
+{
+        return tlbcam_addrs[tlbcam_index - 1].limit - PAGE_OFFSET + 1;
 }
 
 /*
@@ -179,46 +220,21 @@ void __init MMU_init_hw(void)
         flush_instruction_cache();
 }
 
-void __init
-adjust_total_lowmem(void)
+void __init adjust_total_lowmem(void)
 {
-        phys_addr_t ram;
-        unsigned int max_cam = (mfspr(SPRN_TLB1CFG) >> 16) & 0xff;
-        char buf[ARRAY_SIZE(cam) * 5 + 1], *p = buf;
+        unsigned long ram;
         int i;
-        unsigned long virt = PAGE_OFFSET & 0xffffffffUL;
-        unsigned long phys = memstart_addr & 0xffffffffUL;
-
-        /* Convert (4^max) kB to (2^max) bytes */
-        max_cam = max_cam * 2 + 10;
 
         /* adjust lowmem size to __max_low_memory */
         ram = min((phys_addr_t)__max_low_memory, (phys_addr_t)total_lowmem);
 
-        /* Calculate CAM values */
-        __max_low_memory = 0;
-        for (i = 0; ram && i < ARRAY_SIZE(cam); i++) {
-                unsigned int camsize = __ilog2(ram) & ~1U;
-                unsigned int align = __ffs(virt | phys) & ~1U;
-
-                if (camsize > align)
-                        camsize = align;
-                if (camsize > max_cam)
-                        camsize = max_cam;
-
-                cam[i] = 1UL << camsize;
-                ram -= cam[i];
-                __max_low_memory += cam[i];
-                virt += cam[i];
-                phys += cam[i];
+        __max_low_memory = map_mem_in_cams(ram, CONFIG_LOWMEM_CAM_NUM);
 
-                p += sprintf(p, "%lu/", cam[i] >> 20);
-        }
-        for (; i < ARRAY_SIZE(cam); i++)
-                p += sprintf(p, "0/");
-        p[-1] = '\0';
-
-        pr_info("Memory CAM mapping: %s Mb, residual: %dMb\n", buf,
+        pr_info("Memory CAM mapping: ");
+        for (i = 0; i < tlbcam_index - 1; i++)
+                pr_cont("%lu/", tlbcam_sz(i) >> 20);
+        pr_cont("%lu Mb, residual: %dMb\n", tlbcam_sz(tlbcam_index - 1) >> 20,
                 (unsigned int)((total_lowmem - __max_low_memory) >> 20));
+
         __initial_memory_limit_addr = memstart_addr + __max_low_memory;
 }
diff --git a/arch/powerpc/mm/gup.c b/arch/powerpc/mm/gup.c
index bc122a120bf0..d7efdbf640c7 100644
--- a/arch/powerpc/mm/gup.c
+++ b/arch/powerpc/mm/gup.c
@@ -55,57 +55,6 @@ static noinline int gup_pte_range(pmd_t pmd, unsigned long addr,
         return 1;
 }
 
-#ifdef CONFIG_HUGETLB_PAGE
-static noinline int gup_huge_pte(pte_t *ptep, struct hstate *hstate,
-                                 unsigned long *addr, unsigned long end,
-                                 int write, struct page **pages, int *nr)
-{
-        unsigned long mask;
-        unsigned long pte_end;
-        struct page *head, *page;
-        pte_t pte;
-        int refs;
-
-        pte_end = (*addr + huge_page_size(hstate)) & huge_page_mask(hstate);
-        if (pte_end < end)
-                end = pte_end;
-
-        pte = *ptep;
-        mask = _PAGE_PRESENT|_PAGE_USER;
-        if (write)
-                mask |= _PAGE_RW;
-        if ((pte_val(pte) & mask) != mask)
-                return 0;
-        /* hugepages are never "special" */
-        VM_BUG_ON(!pfn_valid(pte_pfn(pte)));
-
-        refs = 0;
-        head = pte_page(pte);
-        page = head + ((*addr & ~huge_page_mask(hstate)) >> PAGE_SHIFT);
-        do {
-                VM_BUG_ON(compound_head(page) != head);
-                pages[*nr] = page;
-                (*nr)++;
-                page++;
-                refs++;
-        } while (*addr += PAGE_SIZE, *addr != end);
-
-        if (!page_cache_add_speculative(head, refs)) {
-                *nr -= refs;
-                return 0;
-        }
-        if (unlikely(pte_val(pte) != pte_val(*ptep))) {
-                /* Could be optimized better */
-                while (*nr) {
-                        put_page(page);
-                        (*nr)--;
-                }
-        }
-
-        return 1;
-}
-#endif /* CONFIG_HUGETLB_PAGE */
-
 static int gup_pmd_range(pud_t pud, unsigned long addr, unsigned long end,
                 int write, struct page **pages, int *nr)
 {
@@ -119,7 +68,11 @@ static int gup_pmd_range(pud_t pud, unsigned long addr, unsigned long end,
                 next = pmd_addr_end(addr, end);
                 if (pmd_none(pmd))
                         return 0;
-                if (!gup_pte_range(pmd, addr, next, write, pages, nr))
+                if (is_hugepd(pmdp)) {
+                        if (!gup_hugepd((hugepd_t *)pmdp, PMD_SHIFT,
+                                        addr, next, write, pages, nr))
+                                return 0;
+                } else if (!gup_pte_range(pmd, addr, next, write, pages, nr))
                         return 0;
         } while (pmdp++, addr = next, addr != end);
 
@@ -139,7 +92,11 @@ static int gup_pud_range(pgd_t pgd, unsigned long addr, unsigned long end,
                 next = pud_addr_end(addr, end);
                 if (pud_none(pud))
                         return 0;
-                if (!gup_pmd_range(pud, addr, next, write, pages, nr))
+                if (is_hugepd(pudp)) {
+                        if (!gup_hugepd((hugepd_t *)pudp, PUD_SHIFT,
+                                        addr, next, write, pages, nr))
+                                return 0;
+                } else if (!gup_pmd_range(pud, addr, next, write, pages, nr))
                         return 0;
         } while (pudp++, addr = next, addr != end);
 
@@ -154,10 +111,6 @@ int get_user_pages_fast(unsigned long start, int nr_pages, int write,
         unsigned long next;
         pgd_t *pgdp;
         int nr = 0;
-#ifdef CONFIG_PPC64
-        unsigned int shift;
-        int psize;
-#endif
 
         pr_devel("%s(%lx,%x,%s)\n", __func__, start, nr_pages, write ? "write" : "read");
 
@@ -172,25 +125,6 @@ int get_user_pages_fast(unsigned long start, int nr_pages, int write,
 
         pr_devel("  aligned: %lx .. %lx\n", start, end);
 
-#ifdef CONFIG_HUGETLB_PAGE
-        /* We bail out on slice boundary crossing when hugetlb is
-         * enabled in order to not have to deal with two different
-         * page table formats
-         */
-        if (addr < SLICE_LOW_TOP) {
-                if (end > SLICE_LOW_TOP)
-                        goto slow_irqon;
-
-                if (unlikely(GET_LOW_SLICE_INDEX(addr) !=
-                             GET_LOW_SLICE_INDEX(end - 1)))
-                        goto slow_irqon;
-        } else {
-                if (unlikely(GET_HIGH_SLICE_INDEX(addr) !=
-                             GET_HIGH_SLICE_INDEX(end - 1)))
-                        goto slow_irqon;
-        }
-#endif /* CONFIG_HUGETLB_PAGE */
-
         /*
          * XXX: batch / limit 'nr', to avoid large irq off latency
          * needs some instrumenting to determine the common sizes used by
@@ -210,54 +144,23 @@ int get_user_pages_fast(unsigned long start, int nr_pages, int write,
          */
         local_irq_disable();
 
-#ifdef CONFIG_PPC64
-        /* Those bits are related to hugetlbfs implementation and only exist
-         * on 64-bit for now
-         */
-        psize = get_slice_psize(mm, addr);
-        shift = mmu_psize_defs[psize].shift;
-#endif /* CONFIG_PPC64 */
-
-#ifdef CONFIG_HUGETLB_PAGE
-        if (unlikely(mmu_huge_psizes[psize])) {
-                pte_t *ptep;
-                unsigned long a = addr;
-                unsigned long sz = ((1UL) << shift);
-                struct hstate *hstate = size_to_hstate(sz);
-
-                BUG_ON(!hstate);
-                /*
-                 * XXX: could be optimized to avoid hstate
-                 * lookup entirely (just use shift)
-                 */
-
-                do {
-                        VM_BUG_ON(shift != mmu_psize_defs[get_slice_psize(mm, a)].shift);
-                        ptep = huge_pte_offset(mm, a);
-                        pr_devel(" %016lx: huge ptep %p\n", a, ptep);
-                        if (!ptep || !gup_huge_pte(ptep, hstate, &a, end, write, pages,
-                                                   &nr))
-                                goto slow;
-                } while (a != end);
-        } else
-#endif /* CONFIG_HUGETLB_PAGE */
-        {
-                pgdp = pgd_offset(mm, addr);
-                do {
-                        pgd_t pgd = *pgdp;
-
-#ifdef CONFIG_PPC64
-                        VM_BUG_ON(shift != mmu_psize_defs[get_slice_psize(mm, addr)].shift);
-#endif
-                        pr_devel("  %016lx: normal pgd %p\n", addr,
-                                 (void *)pgd_val(pgd));
-                        next = pgd_addr_end(addr, end);
-                        if (pgd_none(pgd))
-                                goto slow;
-                        if (!gup_pud_range(pgd, addr, next, write, pages, &nr))
+        pgdp = pgd_offset(mm, addr);
+        do {
+                pgd_t pgd = *pgdp;
+
+                pr_devel("  %016lx: normal pgd %p\n", addr,
+                         (void *)pgd_val(pgd));
+                next = pgd_addr_end(addr, end);
+                if (pgd_none(pgd))
+                        goto slow;
+                if (is_hugepd(pgdp)) {
+                        if (!gup_hugepd((hugepd_t *)pgdp, PGDIR_SHIFT,
+                                        addr, next, write, pages, &nr))
                                 goto slow;
-                } while (pgdp++, addr = next, addr != end);
-        }
+                } else if (!gup_pud_range(pgd, addr, next, write, pages, &nr))
+                        goto slow;
+        } while (pgdp++, addr = next, addr != end);
+
         local_irq_enable();
 
         VM_BUG_ON(nr != (end - start) >> PAGE_SHIFT);
diff --git a/arch/powerpc/mm/hash_utils_64.c b/arch/powerpc/mm/hash_utils_64.c
index 1ade7eb6ae00..50f867d657df 100644
--- a/arch/powerpc/mm/hash_utils_64.c
+++ b/arch/powerpc/mm/hash_utils_64.c
@@ -92,6 +92,7 @@ struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT];
 struct hash_pte *htab_address;
 unsigned long htab_size_bytes;
 unsigned long htab_hash_mask;
+EXPORT_SYMBOL_GPL(htab_hash_mask);
 int mmu_linear_psize = MMU_PAGE_4K;
 int mmu_virtual_psize = MMU_PAGE_4K;
 int mmu_vmalloc_psize = MMU_PAGE_4K;
@@ -102,6 +103,7 @@ int mmu_io_psize = MMU_PAGE_4K;
 int mmu_kernel_ssize = MMU_SEGSIZE_256M;
 int mmu_highuser_ssize = MMU_SEGSIZE_256M;
 u16 mmu_slb_size = 64;
+EXPORT_SYMBOL_GPL(mmu_slb_size);
 #ifdef CONFIG_HUGETLB_PAGE
 unsigned int HPAGE_SHIFT;
 #endif
@@ -481,16 +483,6 @@ static void __init htab_init_page_sizes(void)
 #ifdef CONFIG_HUGETLB_PAGE
         /* Reserve 16G huge page memory sections for huge pages */
         of_scan_flat_dt(htab_dt_scan_hugepage_blocks, NULL);
-
-/* Set default large page size. Currently, we pick 16M or 1M depending
-         * on what is available
-         */
-        if (mmu_psize_defs[MMU_PAGE_16M].shift)
-                HPAGE_SHIFT = mmu_psize_defs[MMU_PAGE_16M].shift;
-        /* With 4k/4level pagetables, we can't (for now) cope with a
-         * huge page size < PMD_SIZE */
-        else if (mmu_psize_defs[MMU_PAGE_1M].shift)
-                HPAGE_SHIFT = mmu_psize_defs[MMU_PAGE_1M].shift;
 #endif /* CONFIG_HUGETLB_PAGE */
 }
 
@@ -785,7 +777,7 @@ unsigned int hash_page_do_lazy_icache(unsigned int pp, pte_t pte, int trap)
         /* page is dirty */
         if (!test_bit(PG_arch_1, &page->flags) && !PageReserved(page)) {
                 if (trap == 0x400) {
-                        __flush_dcache_icache(page_address(page));
+                        flush_dcache_icache_page(page);
                         set_bit(PG_arch_1, &page->flags);
                 } else
                         pp |= HPTE_R_N;
@@ -843,9 +835,9 @@ void demote_segment_4k(struct mm_struct *mm, unsigned long addr)
  * Result is 0: full permissions, _PAGE_RW: read-only,
  * _PAGE_USER or _PAGE_USER|_PAGE_RW: no access.
  */
-static int subpage_protection(pgd_t *pgdir, unsigned long ea)
+static int subpage_protection(struct mm_struct *mm, unsigned long ea)
 {
-        struct subpage_prot_table *spt = pgd_subpage_prot(pgdir);
+        struct subpage_prot_table *spt = &mm->context.spt;
         u32 spp = 0;
         u32 **sbpm, *sbpp;
 
@@ -873,7 +865,7 @@ static int subpage_protection(pgd_t *pgdir, unsigned long ea)
 }
 
 #else /* CONFIG_PPC_SUBPAGE_PROT */
-static inline int subpage_protection(pgd_t *pgdir, unsigned long ea)
+static inline int subpage_protection(struct mm_struct *mm, unsigned long ea)
 {
         return 0;
 }
@@ -891,6 +883,7 @@ int hash_page(unsigned long ea, unsigned long access, unsigned long trap)
         unsigned long vsid;
         struct mm_struct *mm;
         pte_t *ptep;
+        unsigned hugeshift;
         const struct cpumask *tmp;
         int rc, user_region = 0, local = 0;
         int psize, ssize;
@@ -943,30 +936,31 @@ int hash_page(unsigned long ea, unsigned long access, unsigned long trap)
         if (user_region && cpumask_equal(mm_cpumask(mm), tmp))
                 local = 1;
 
-#ifdef CONFIG_HUGETLB_PAGE
-        /* Handle hugepage regions */
-        if (HPAGE_SHIFT && mmu_huge_psizes[psize]) {
-                DBG_LOW(" -> huge page !\n");
-                return hash_huge_page(mm, access, ea, vsid, local, trap);
-        }
-#endif /* CONFIG_HUGETLB_PAGE */
-
 #ifndef CONFIG_PPC_64K_PAGES
-        /* If we use 4K pages and our psize is not 4K, then we are hitting
-         * a special driver mapping, we need to align the address before
-         * we fetch the PTE
+        /* If we use 4K pages and our psize is not 4K, then we might
+         * be hitting a special driver mapping, and need to align the
+         * address before we fetch the PTE.
+         *
+         * It could also be a hugepage mapping, in which case this is
+         * not necessary, but it's not harmful, either.
          */
         if (psize != MMU_PAGE_4K)
                 ea &= ~((1ul << mmu_psize_defs[psize].shift) - 1);
 #endif /* CONFIG_PPC_64K_PAGES */
 
         /* Get PTE and page size from page tables */
-        ptep = find_linux_pte(pgdir, ea);
+        ptep = find_linux_pte_or_hugepte(pgdir, ea, &hugeshift);
         if (ptep == NULL || !pte_present(*ptep)) {
                 DBG_LOW(" no PTE !\n");
                 return 1;
         }
 
+#ifdef CONFIG_HUGETLB_PAGE
+        if (hugeshift)
+                return __hash_page_huge(ea, access, vsid, ptep, trap, local,
+                                        ssize, hugeshift, psize);
+#endif /* CONFIG_HUGETLB_PAGE */
+
 #ifndef CONFIG_PPC_64K_PAGES
         DBG_LOW(" i-pte: %016lx\n", pte_val(*ptep));
 #else
diff --git a/arch/powerpc/mm/hugetlbpage-hash64.c b/arch/powerpc/mm/hugetlbpage-hash64.c
new file mode 100644
index 000000000000..199539882f92
--- /dev/null
+++ b/arch/powerpc/mm/hugetlbpage-hash64.c
@@ -0,0 +1,139 @@
+/*
+ * PPC64 Huge TLB Page Support for hash based MMUs (POWER4 and later)
+ *
+ * Copyright (C) 2003 David Gibson, IBM Corporation.
+ *
+ * Based on the IA-32 version:
+ * Copyright (C) 2002, Rohit Seth <rohit.seth@intel.com>
+ */
+
+#include <linux/mm.h>
+#include <linux/hugetlb.h>
+#include <asm/pgtable.h>
+#include <asm/pgalloc.h>
+#include <asm/cacheflush.h>
+#include <asm/machdep.h>
+
+int __hash_page_huge(unsigned long ea, unsigned long access, unsigned long vsid,
+                     pte_t *ptep, unsigned long trap, int local, int ssize,
+                     unsigned int shift, unsigned int mmu_psize)
+{
+        unsigned long old_pte, new_pte;
+        unsigned long va, rflags, pa, sz;
+        long slot;
+        int err = 1;
+
+        BUG_ON(shift != mmu_psize_defs[mmu_psize].shift);
+
+        /* Search the Linux page table for a match with va */
+        va = hpt_va(ea, vsid, ssize);
+
+        /*
+         * Check the user's access rights to the page.  If access should be
+         * prevented then send the problem up to do_page_fault.
+         */
+        if (unlikely(access & ~pte_val(*ptep)))
+                goto out;
+        /*
+         * At this point, we have a pte (old_pte) which can be used to build
+         * or update an HPTE. There are 2 cases:
+         *
+         * 1. There is a valid (present) pte with no associated HPTE (this is
+         *      the most common case)
+         * 2. There is a valid (present) pte with an associated HPTE. The
+         *      current values of the pp bits in the HPTE prevent access
+         *      because we are doing software DIRTY bit management and the
+         *      page is currently not DIRTY.
+         */
+
+
+        do {
+                old_pte = pte_val(*ptep);
+                if (old_pte & _PAGE_BUSY)
+                        goto out;
+                new_pte = old_pte | _PAGE_BUSY | _PAGE_ACCESSED;
+        } while(old_pte != __cmpxchg_u64((unsigned long *)ptep,
+                                         old_pte, new_pte));
+
+        rflags = 0x2 | (!(new_pte & _PAGE_RW));
+        /* _PAGE_EXEC -> HW_NO_EXEC since it's inverted */
+        rflags |= ((new_pte & _PAGE_EXEC) ? 0 : HPTE_R_N);
+        sz = ((1UL) << shift);
+        if (!cpu_has_feature(CPU_FTR_COHERENT_ICACHE))
+                /* No CPU has hugepages but lacks no execute, so we
+                 * don't need to worry about that case */
+                rflags = hash_page_do_lazy_icache(rflags, __pte(old_pte), trap);
+
+        /* Check if pte already has an hpte (case 2) */
+        if (unlikely(old_pte & _PAGE_HASHPTE)) {
+                /* There MIGHT be an HPTE for this pte */
+                unsigned long hash, slot;
+
+                hash = hpt_hash(va, shift, ssize);
+                if (old_pte & _PAGE_F_SECOND)
+                        hash = ~hash;
+                slot = (hash & htab_hash_mask) * HPTES_PER_GROUP;
+                slot += (old_pte & _PAGE_F_GIX) >> 12;
+
+                if (ppc_md.hpte_updatepp(slot, rflags, va, mmu_psize,
+                                         ssize, local) == -1)
+                        old_pte &= ~_PAGE_HPTEFLAGS;
+        }
+
+        if (likely(!(old_pte & _PAGE_HASHPTE))) {
+                unsigned long hash = hpt_hash(va, shift, ssize);
+                unsigned long hpte_group;
+
+                pa = pte_pfn(__pte(old_pte)) << PAGE_SHIFT;
+
+repeat:
+                hpte_group = ((hash & htab_hash_mask) *
+                              HPTES_PER_GROUP) & ~0x7UL;
+
+                /* clear HPTE slot informations in new PTE */
+#ifdef CONFIG_PPC_64K_PAGES
+                new_pte = (new_pte & ~_PAGE_HPTEFLAGS) | _PAGE_HPTE_SUB0;
+#else
+                new_pte = (new_pte & ~_PAGE_HPTEFLAGS) | _PAGE_HASHPTE;
+#endif
+                /* Add in WIMG bits */
+                rflags |= (new_pte & (_PAGE_WRITETHRU | _PAGE_NO_CACHE |
+                                      _PAGE_COHERENT | _PAGE_GUARDED));
+
+                /* Insert into the hash table, primary slot */
+                slot = ppc_md.hpte_insert(hpte_group, va, pa, rflags, 0,
+                                          mmu_psize, ssize);
+
+                /* Primary is full, try the secondary */
+                if (unlikely(slot == -1)) {
+                        hpte_group = ((~hash & htab_hash_mask) *
+                                      HPTES_PER_GROUP) & ~0x7UL;
+                        slot = ppc_md.hpte_insert(hpte_group, va, pa, rflags,
+                                                  HPTE_V_SECONDARY,
+                                                  mmu_psize, ssize);
+                        if (slot == -1) {
+                                if (mftb() & 0x1)
+                                        hpte_group = ((hash & htab_hash_mask) *
+                                                      HPTES_PER_GROUP)&~0x7UL;
+
+                                ppc_md.hpte_remove(hpte_group);
+                                goto repeat;
+                        }
+                }
+
+                if (unlikely(slot == -2))
+                        panic("hash_huge_page: pte_insert failed\n");
+
+                new_pte |= (slot << 12) & (_PAGE_F_SECOND | _PAGE_F_GIX);
+        }
+
+        /*
+         * No need to use ldarx/stdcx here
+         */
+        *ptep = __pte(new_pte & ~_PAGE_BUSY);
+
+        err = 0;
+
+ out:
+        return err;
+}
diff --git a/arch/powerpc/mm/hugetlbpage.c b/arch/powerpc/mm/hugetlbpage.c
index 90df6ffe3a43..123f7070238a 100644
--- a/arch/powerpc/mm/hugetlbpage.c
+++ b/arch/powerpc/mm/hugetlbpage.c
@@ -7,29 +7,17 @@
  * Copyright (C) 2002, Rohit Seth <rohit.seth@intel.com>
  */
 
-#include <linux/init.h>
-#include <linux/fs.h>
 #include <linux/mm.h>
+#include <linux/io.h>
 #include <linux/hugetlb.h>
-#include <linux/pagemap.h>
-#include <linux/slab.h>
-#include <linux/err.h>
-#include <linux/sysctl.h>
-#include <asm/mman.h>
+#include <asm/pgtable.h>
 #include <asm/pgalloc.h>
 #include <asm/tlb.h>
-#include <asm/tlbflush.h>
-#include <asm/mmu_context.h>
-#include <asm/machdep.h>
-#include <asm/cputable.h>
-#include <asm/spu.h>
 
 #define PAGE_SHIFT_64K  16
 #define PAGE_SHIFT_16M  24
 #define PAGE_SHIFT_16G  34
 
-#define NUM_LOW_AREAS   (0x100000000UL >> SID_SHIFT)
-#define NUM_HIGH_AREAS  (PGTABLE_RANGE >> HTLB_AREA_SHIFT)
 #define MAX_NUMBER_GPAGES       1024
 
 /* Tracks the 16G pages after the device tree is scanned and before the
@@ -37,53 +25,17 @@
 static unsigned long gpage_freearray[MAX_NUMBER_GPAGES];
 static unsigned nr_gpages;
 
-/* Array of valid huge page sizes - non-zero value(hugepte_shift) is
- * stored for the huge page sizes that are valid.
- */
-unsigned int mmu_huge_psizes[MMU_PAGE_COUNT] = { }; /* initialize all to 0 */
-
-#define hugepte_shift                   mmu_huge_psizes
-#define PTRS_PER_HUGEPTE(psize)         (1 << hugepte_shift[psize])
-#define HUGEPTE_TABLE_SIZE(psize)       (sizeof(pte_t) << hugepte_shift[psize])
-
-#define HUGEPD_SHIFT(psize)             (mmu_psize_to_shift(psize) \
-                                                + hugepte_shift[psize])
-#define HUGEPD_SIZE(psize)              (1UL << HUGEPD_SHIFT(psize))
-#define HUGEPD_MASK(psize)              (~(HUGEPD_SIZE(psize)-1))
-
-/* Subtract one from array size because we don't need a cache for 4K since
- * is not a huge page size */
-#define HUGE_PGTABLE_INDEX(psize)       (HUGEPTE_CACHE_NUM + psize - 1)
-#define HUGEPTE_CACHE_NAME(psize)       (huge_pgtable_cache_name[psize])
-
-static const char *huge_pgtable_cache_name[MMU_PAGE_COUNT] = {
-        [MMU_PAGE_64K]  = "hugepte_cache_64K",
-        [MMU_PAGE_1M]   = "hugepte_cache_1M",
-        [MMU_PAGE_16M]  = "hugepte_cache_16M",
-        [MMU_PAGE_16G]  = "hugepte_cache_16G",
-};
-
 /* Flag to mark huge PD pointers.  This means pmd_bad() and pud_bad()
  * will choke on pointers to hugepte tables, which is handy for
  * catching screwups early. */
-#define HUGEPD_OK       0x1
-
-typedef struct { unsigned long pd; } hugepd_t;
-
-#define hugepd_none(hpd)        ((hpd).pd == 0)
 
 static inline int shift_to_mmu_psize(unsigned int shift)
 {
-        switch (shift) {
-#ifndef CONFIG_PPC_64K_PAGES
-        case PAGE_SHIFT_64K:
-            return MMU_PAGE_64K;
-#endif
-        case PAGE_SHIFT_16M:
-            return MMU_PAGE_16M;
-        case PAGE_SHIFT_16G:
-            return MMU_PAGE_16G;
-        }
+        int psize;
+
+        for (psize = 0; psize < MMU_PAGE_COUNT; ++psize)
+                if (mmu_psize_defs[psize].shift == shift)
+                        return psize;
         return -1;
 }
 
@@ -94,71 +46,126 @@ static inline unsigned int mmu_psize_to_shift(unsigned int mmu_psize)
         BUG();
 }
 
+#define hugepd_none(hpd)        ((hpd).pd == 0)
+
 static inline pte_t *hugepd_page(hugepd_t hpd)
 {
-        BUG_ON(!(hpd.pd & HUGEPD_OK));
-        return (pte_t *)(hpd.pd & ~HUGEPD_OK);
+        BUG_ON(!hugepd_ok(hpd));
+        return (pte_t *)((hpd.pd & ~HUGEPD_SHIFT_MASK) | 0xc000000000000000);
+}
+
+static inline unsigned int hugepd_shift(hugepd_t hpd)
+{
+        return hpd.pd & HUGEPD_SHIFT_MASK;
 }
 
-static inline pte_t *hugepte_offset(hugepd_t *hpdp, unsigned long addr,
-                                    struct hstate *hstate)
+static inline pte_t *hugepte_offset(hugepd_t *hpdp, unsigned long addr, unsigned pdshift)
 {
-        unsigned int shift = huge_page_shift(hstate);
-        int psize = shift_to_mmu_psize(shift);
-        unsigned long idx = ((addr >> shift) & (PTRS_PER_HUGEPTE(psize)-1));
+        unsigned long idx = (addr & ((1UL << pdshift) - 1)) >> hugepd_shift(*hpdp);
         pte_t *dir = hugepd_page(*hpdp);
 
         return dir + idx;
 }
 
+pte_t *find_linux_pte_or_hugepte(pgd_t *pgdir, unsigned long ea, unsigned *shift)
+{
+        pgd_t *pg;
+        pud_t *pu;
+        pmd_t *pm;
+        hugepd_t *hpdp = NULL;
+        unsigned pdshift = PGDIR_SHIFT;
+
+        if (shift)
+                *shift = 0;
+
+        pg = pgdir + pgd_index(ea);
+        if (is_hugepd(pg)) {
+                hpdp = (hugepd_t *)pg;
+        } else if (!pgd_none(*pg)) {
+                pdshift = PUD_SHIFT;
+                pu = pud_offset(pg, ea);
+                if (is_hugepd(pu))
+                        hpdp = (hugepd_t *)pu;
+                else if (!pud_none(*pu)) {
+                        pdshift = PMD_SHIFT;
+                        pm = pmd_offset(pu, ea);
+                        if (is_hugepd(pm))
+                                hpdp = (hugepd_t *)pm;
+                        else if (!pmd_none(*pm)) {
+                                return pte_offset_map(pm, ea);
+                        }
+                }
+        }
+
+        if (!hpdp)
+                return NULL;
+
+        if (shift)
+                *shift = hugepd_shift(*hpdp);
+        return hugepte_offset(hpdp, ea, pdshift);
+}
+
+pte_t *huge_pte_offset(struct mm_struct *mm, unsigned long addr)
+{
+        return find_linux_pte_or_hugepte(mm->pgd, addr, NULL);
+}
+
 static int __hugepte_alloc(struct mm_struct *mm, hugepd_t *hpdp,
-                           unsigned long address, unsigned int psize)
+                           unsigned long address, unsigned pdshift, unsigned pshift)
 {
-        pte_t *new = kmem_cache_zalloc(pgtable_cache[HUGE_PGTABLE_INDEX(psize)],
-                                      GFP_KERNEL|__GFP_REPEAT);
+        pte_t *new = kmem_cache_zalloc(PGT_CACHE(pdshift - pshift),
+                                       GFP_KERNEL|__GFP_REPEAT);
+
+        BUG_ON(pshift > HUGEPD_SHIFT_MASK);
+        BUG_ON((unsigned long)new & HUGEPD_SHIFT_MASK);
 
         if (! new)
                 return -ENOMEM;
 
         spin_lock(&mm->page_table_lock);
         if (!hugepd_none(*hpdp))
-                kmem_cache_free(pgtable_cache[HUGE_PGTABLE_INDEX(psize)], new);
+                kmem_cache_free(PGT_CACHE(pdshift - pshift), new);
         else
-                hpdp->pd = (unsigned long)new | HUGEPD_OK;
+                hpdp->pd = ((unsigned long)new & ~0x8000000000000000) | pshift;
         spin_unlock(&mm->page_table_lock);
         return 0;
 }
 
-
-static pud_t *hpud_offset(pgd_t *pgd, unsigned long addr, struct hstate *hstate)
-{
-        if (huge_page_shift(hstate) < PUD_SHIFT)
-                return pud_offset(pgd, addr);
-        else
-                return (pud_t *) pgd;
-}
-static pud_t *hpud_alloc(struct mm_struct *mm, pgd_t *pgd, unsigned long addr,
-                         struct hstate *hstate)
+pte_t *huge_pte_alloc(struct mm_struct *mm, unsigned long addr, unsigned long sz)
 {
-        if (huge_page_shift(hstate) < PUD_SHIFT)
-                return pud_alloc(mm, pgd, addr);
-        else
-                return (pud_t *) pgd;
-}
-static pmd_t *hpmd_offset(pud_t *pud, unsigned long addr, struct hstate *hstate)
-{
-        if (huge_page_shift(hstate) < PMD_SHIFT)
-                return pmd_offset(pud, addr);
-        else
-                return (pmd_t *) pud;
-}
-static pmd_t *hpmd_alloc(struct mm_struct *mm, pud_t *pud, unsigned long addr,
-                         struct hstate *hstate)
-{
-        if (huge_page_shift(hstate) < PMD_SHIFT)
-                return pmd_alloc(mm, pud, addr);
-        else
-                return (pmd_t *) pud;
+        pgd_t *pg;
+        pud_t *pu;
+        pmd_t *pm;
+        hugepd_t *hpdp = NULL;
+        unsigned pshift = __ffs(sz);
+        unsigned pdshift = PGDIR_SHIFT;
+
+        addr &= ~(sz-1);
+
+        pg = pgd_offset(mm, addr);
+        if (pshift >= PUD_SHIFT) {
+                hpdp = (hugepd_t *)pg;
+        } else {
+                pdshift = PUD_SHIFT;
+                pu = pud_alloc(mm, pg, addr);
+                if (pshift >= PMD_SHIFT) {
+                        hpdp = (hugepd_t *)pu;
+                } else {
+                        pdshift = PMD_SHIFT;
+                        pm = pmd_alloc(mm, pu, addr);
+                        hpdp = (hugepd_t *)pm;
+                }
+        }
+
+        if (!hpdp)
+                return NULL;
+
+        BUG_ON(!hugepd_none(*hpdp) && !hugepd_ok(*hpdp));
+
+        if (hugepd_none(*hpdp) && __hugepte_alloc(mm, hpdp, addr, pdshift, pshift))
+                return NULL;
+
+        return hugepte_offset(hpdp, addr, pdshift);
 }
 
 /* Build list of addresses of gigantic pages.  This function is used in early
@@ -192,94 +199,38 @@ int alloc_bootmem_huge_page(struct hstate *hstate)
         return 1;
 }
 
-
-/* Modelled after find_linux_pte() */
-pte_t *huge_pte_offset(struct mm_struct *mm, unsigned long addr)
-{
-        pgd_t *pg;
-        pud_t *pu;
-        pmd_t *pm;
-
-        unsigned int psize;
-        unsigned int shift;
-        unsigned long sz;
-        struct hstate *hstate;
-        psize = get_slice_psize(mm, addr);
-        shift = mmu_psize_to_shift(psize);
-        sz = ((1UL) << shift);
-        hstate = size_to_hstate(sz);
-
-        addr &= hstate->mask;
-
-        pg = pgd_offset(mm, addr);
-        if (!pgd_none(*pg)) {
-                pu = hpud_offset(pg, addr, hstate);
-                if (!pud_none(*pu)) {
-                        pm = hpmd_offset(pu, addr, hstate);
-                        if (!pmd_none(*pm))
-                                return hugepte_offset((hugepd_t *)pm, addr,
-                                                      hstate);
-                }
-        }
-
-        return NULL;
-}
-
-pte_t *huge_pte_alloc(struct mm_struct *mm,
-                        unsigned long addr, unsigned long sz)
-{
-        pgd_t *pg;
-        pud_t *pu;
-        pmd_t *pm;
-        hugepd_t *hpdp = NULL;
-        struct hstate *hstate;
-        unsigned int psize;
-        hstate = size_to_hstate(sz);
-
-        psize = get_slice_psize(mm, addr);
-        BUG_ON(!mmu_huge_psizes[psize]);
-
-        addr &= hstate->mask;
-
-        pg = pgd_offset(mm, addr);
-        pu = hpud_alloc(mm, pg, addr, hstate);
-
-        if (pu) {
-                pm = hpmd_alloc(mm, pu, addr, hstate);
-                if (pm)
-                        hpdp = (hugepd_t *)pm;
-        }
-
-        if (! hpdp)
-                return NULL;
-
-        if (hugepd_none(*hpdp) && __hugepte_alloc(mm, hpdp, addr, psize))
-                return NULL;
-
-        return hugepte_offset(hpdp, addr, hstate);
-}
-
 int huge_pmd_unshare(struct mm_struct *mm, unsigned long *addr, pte_t *ptep)
 {
         return 0;
 }
 
-static void free_hugepte_range(struct mmu_gather *tlb, hugepd_t *hpdp,
-                               unsigned int psize)
+static void free_hugepd_range(struct mmu_gather *tlb, hugepd_t *hpdp, int pdshift,
+                              unsigned long start, unsigned long end,
+                              unsigned long floor, unsigned long ceiling)
 {
         pte_t *hugepte = hugepd_page(*hpdp);
+        unsigned shift = hugepd_shift(*hpdp);
+        unsigned long pdmask = ~((1UL << pdshift) - 1);
+
+        start &= pdmask;
+        if (start < floor)
+                return;
+        if (ceiling) {
+                ceiling &= pdmask;
+                if (! ceiling)
+                        return;
+        }
+        if (end - 1 > ceiling - 1)
+                return;
 
         hpdp->pd = 0;
         tlb->need_flush = 1;
-        pgtable_free_tlb(tlb, pgtable_free_cache(hugepte,
-                                                 HUGEPTE_CACHE_NUM+psize-1,
-                                                 PGF_CACHENUM_MASK));
+        pgtable_free_tlb(tlb, hugepte, pdshift - shift);
 }
 
 static void hugetlb_free_pmd_range(struct mmu_gather *tlb, pud_t *pud,
                                    unsigned long addr, unsigned long end,
-                                   unsigned long floor, unsigned long ceiling,
-                                   unsigned int psize)
+                                   unsigned long floor, unsigned long ceiling)
 {
         pmd_t *pmd;
         unsigned long next;
@@ -291,7 +242,8 @@ static void hugetlb_free_pmd_range(struct mmu_gather *tlb, pud_t *pud,
                 next = pmd_addr_end(addr, end);
                 if (pmd_none(*pmd))
                         continue;
-                free_hugepte_range(tlb, (hugepd_t *)pmd, psize);
+                free_hugepd_range(tlb, (hugepd_t *)pmd, PMD_SHIFT,
+                                  addr, next, floor, ceiling);
         } while (pmd++, addr = next, addr != end);
 
         start &= PUD_MASK;
@@ -317,23 +269,19 @@ static void hugetlb_free_pud_range(struct mmu_gather *tlb, pgd_t *pgd,
         pud_t *pud;
         unsigned long next;
         unsigned long start;
-        unsigned int shift;
-        unsigned int psize = get_slice_psize(tlb->mm, addr);
-        shift = mmu_psize_to_shift(psize);
 
         start = addr;
         pud = pud_offset(pgd, addr);
         do {
                 next = pud_addr_end(addr, end);
-                if (shift < PMD_SHIFT) {
+                if (!is_hugepd(pud)) {
                         if (pud_none_or_clear_bad(pud))
                                 continue;
                         hugetlb_free_pmd_range(tlb, pud, addr, next, floor,
-                                               ceiling, psize);
+                                               ceiling);
                 } else {
-                        if (pud_none(*pud))
-                                continue;
-                        free_hugepte_range(tlb, (hugepd_t *)pud, psize);
+                        free_hugepd_range(tlb, (hugepd_t *)pud, PUD_SHIFT,
+                                          addr, next, floor, ceiling);
                 }
         } while (pud++, addr = next, addr != end);
 
@@ -364,121 +312,56 @@ void hugetlb_free_pgd_range(struct mmu_gather *tlb,
 {
         pgd_t *pgd;
         unsigned long next;
-        unsigned long start;
 
         /*
-         * Comments below take from the normal free_pgd_range().  They
-         * apply here too.  The tests against HUGEPD_MASK below are
-         * essential, because we *don't* test for this at the bottom
-         * level.  Without them we'll attempt to free a hugepte table
-         * when we unmap just part of it, even if there are other
-         * active mappings using it.
-         *
-         * The next few lines have given us lots of grief...
-         *
-         * Why are we testing HUGEPD* at this top level?  Because
-         * often there will be no work to do at all, and we'd prefer
-         * not to go all the way down to the bottom just to discover
-         * that.
-         *
-         * Why all these "- 1"s?  Because 0 represents both the bottom
-         * of the address space and the top of it (using -1 for the
-         * top wouldn't help much: the masks would do the wrong thing).
-         * The rule is that addr 0 and floor 0 refer to the bottom of
-         * the address space, but end 0 and ceiling 0 refer to the top
-         * Comparisons need to use "end - 1" and "ceiling - 1" (though
-         * that end 0 case should be mythical).
+         * Because there are a number of different possible pagetable
+         * layouts for hugepage ranges, we limit knowledge of how
+         * things should be laid out to the allocation path
+         * (huge_pte_alloc(), above).  Everything else works out the
+         * structure as it goes from information in the hugepd
+         * pointers.  That means that we can't here use the
+         * optimization used in the normal page free_pgd_range(), of
+         * checking whether we're actually covering a large enough
+         * range to have to do anything at the top level of the walk
+         * instead of at the bottom.
          *
-         * Wherever addr is brought up or ceiling brought down, we
-         * must be careful to reject "the opposite 0" before it
-         * confuses the subsequent tests.  But what about where end is
-         * brought down by HUGEPD_SIZE below? no, end can't go down to
-         * 0 there.
-         *
-         * Whereas we round start (addr) and ceiling down, by different
-         * masks at different levels, in order to test whether a table
-         * now has no other vmas using it, so can be freed, we don't
-         * bother to round floor or end up - the tests don't need that.
+         * To make sense of this, you should probably go read the big
+         * block comment at the top of the normal free_pgd_range(),
+         * too.
          */
-        unsigned int psize = get_slice_psize(tlb->mm, addr);
-
-        addr &= HUGEPD_MASK(psize);
-        if (addr < floor) {
-                addr += HUGEPD_SIZE(psize);
-                if (!addr)
-                        return;
-        }
-        if (ceiling) {
-                ceiling &= HUGEPD_MASK(psize);
-                if (!ceiling)
-                        return;
-        }
-        if (end - 1 > ceiling - 1)
-                end -= HUGEPD_SIZE(psize);
-        if (addr > end - 1)
-                return;
 
-        start = addr;
         pgd = pgd_offset(tlb->mm, addr);
         do {
-                psize = get_slice_psize(tlb->mm, addr);
-                BUG_ON(!mmu_huge_psizes[psize]);
                 next = pgd_addr_end(addr, end);
-                if (mmu_psize_to_shift(psize) < PUD_SHIFT) {
+                if (!is_hugepd(pgd)) {
                         if (pgd_none_or_clear_bad(pgd))
                                 continue;
                         hugetlb_free_pud_range(tlb, pgd, addr, next, floor, ceiling);
                 } else {
-                        if (pgd_none(*pgd))
-                                continue;
-                        free_hugepte_range(tlb, (hugepd_t *)pgd, psize);
+                        free_hugepd_range(tlb, (hugepd_t *)pgd, PGDIR_SHIFT,
+                                          addr, next, floor, ceiling);
                 }
         } while (pgd++, addr = next, addr != end);
 }
 
-void set_huge_pte_at(struct mm_struct *mm, unsigned long addr,
-                     pte_t *ptep, pte_t pte)
-{
-        if (pte_present(*ptep)) {
-                /* We open-code pte_clear because we need to pass the right
-                 * argument to hpte_need_flush (huge / !huge). Might not be
-                 * necessary anymore if we make hpte_need_flush() get the
-                 * page size from the slices
-                 */
-                unsigned int psize = get_slice_psize(mm, addr);
-                unsigned int shift = mmu_psize_to_shift(psize);
-                unsigned long sz = ((1UL) << shift);
-                struct hstate *hstate = size_to_hstate(sz);
-                pte_update(mm, addr & hstate->mask, ptep, ~0UL, 1);
-        }
-        *ptep = __pte(pte_val(pte) & ~_PAGE_HPTEFLAGS);
-}
-
-pte_t huge_ptep_get_and_clear(struct mm_struct *mm, unsigned long addr,
-                              pte_t *ptep)
-{
-        unsigned long old = pte_update(mm, addr, ptep, ~0UL, 1);
-        return __pte(old);
-}
-
 struct page *
 follow_huge_addr(struct mm_struct *mm, unsigned long address, int write)
 {
         pte_t *ptep;
         struct page *page;
-        unsigned int mmu_psize = get_slice_psize(mm, address);
+        unsigned shift;
+        unsigned long mask;
+
+        ptep = find_linux_pte_or_hugepte(mm->pgd, address, &shift);
 
         /* Verify it is a huge page else bail. */
-        if (!mmu_huge_psizes[mmu_psize])
+        if (!ptep || !shift)
                 return ERR_PTR(-EINVAL);
 
-        ptep = huge_pte_offset(mm, address);
+        mask = (1UL << shift) - 1;
         page = pte_page(*ptep);
-        if (page) {
-                unsigned int shift = mmu_psize_to_shift(mmu_psize);
-                unsigned long sz = ((1UL) << shift);
-                page += (address % sz) / PAGE_SIZE;
-        }
+        if (page)
+                page += (address & mask) / PAGE_SIZE;
 
         return page;
 }
@@ -501,6 +384,82 @@ follow_huge_pmd(struct mm_struct *mm, unsigned long address,
         return NULL;
 }
 
+static noinline int gup_hugepte(pte_t *ptep, unsigned long sz, unsigned long addr,
+                       unsigned long end, int write, struct page **pages, int *nr)
+{
+        unsigned long mask;
+        unsigned long pte_end;
+        struct page *head, *page;
+        pte_t pte;
+        int refs;
+
+        pte_end = (addr + sz) & ~(sz-1);
+        if (pte_end < end)
+                end = pte_end;
+
+        pte = *ptep;
+        mask = _PAGE_PRESENT | _PAGE_USER;
+        if (write)
+                mask |= _PAGE_RW;
+
+        if ((pte_val(pte) & mask) != mask)
+                return 0;
+
+        /* hugepages are never "special" */
+        VM_BUG_ON(!pfn_valid(pte_pfn(pte)));
+
+        refs = 0;
+        head = pte_page(pte);
+
+        page = head + ((addr & (sz-1)) >> PAGE_SHIFT);
+        do {
+                VM_BUG_ON(compound_head(page) != head);
+                pages[*nr] = page;
+                (*nr)++;
+                page++;
+                refs++;
+        } while (addr += PAGE_SIZE, addr != end);
+
+        if (!page_cache_add_speculative(head, refs)) {
+                *nr -= refs;
+                return 0;
+        }
+
+        if (unlikely(pte_val(pte) != pte_val(*ptep))) {
+                /* Could be optimized better */
+                while (*nr) {
+                        put_page(page);
+                        (*nr)--;
+                }
+        }
+
+        return 1;
+}
+
+static unsigned long hugepte_addr_end(unsigned long addr, unsigned long end,
+                                      unsigned long sz)
+{
+        unsigned long __boundary = (addr + sz) & ~(sz-1);
+        return (__boundary - 1 < end - 1) ? __boundary : end;
+}
+
+int gup_hugepd(hugepd_t *hugepd, unsigned pdshift,
+               unsigned long addr, unsigned long end,
+               int write, struct page **pages, int *nr)
+{
+        pte_t *ptep;
+        unsigned long sz = 1UL << hugepd_shift(*hugepd);
+        unsigned long next;
+
+        ptep = hugepte_offset(hugepd, addr, pdshift);
+        do {
+                next = hugepte_addr_end(addr, end, sz);
+                if (!gup_hugepte(ptep, sz, addr, end, write, pages, nr))
+                        return 0;
+        } while (ptep++, addr = next, addr != end);
+
+        return 1;
+}
 
 unsigned long hugetlb_get_unmapped_area(struct file *file, unsigned long addr,
                                         unsigned long len, unsigned long pgoff,
@@ -509,8 +468,6 @@ unsigned long hugetlb_get_unmapped_area(struct file *file, unsigned long addr,
         struct hstate *hstate = hstate_file(file);
         int mmu_psize = shift_to_mmu_psize(huge_page_shift(hstate));
 
-        if (!mmu_huge_psizes[mmu_psize])
-                return -EINVAL;
         return slice_get_unmapped_area(addr, len, flags, mmu_psize, 1, 0);
 }
 
@@ -521,229 +478,46 @@ unsigned long vma_mmu_pagesize(struct vm_area_struct *vma)
         return 1UL << mmu_psize_to_shift(psize);
 }
 
-/*
- * Called by asm hashtable.S for doing lazy icache flush
- */
-static unsigned int hash_huge_page_do_lazy_icache(unsigned long rflags,
-                                        pte_t pte, int trap, unsigned long sz)
+static int __init add_huge_page_size(unsigned long long size)
 {
-        struct page *page;
-        int i;
-
-        if (!pfn_valid(pte_pfn(pte)))
-                return rflags;
-
-        page = pte_page(pte);
-
-        /* page is dirty */
-        if (!test_bit(PG_arch_1, &page->flags) && !PageReserved(page)) {
-                if (trap == 0x400) {
-                        for (i = 0; i < (sz / PAGE_SIZE); i++)
-                                __flush_dcache_icache(page_address(page+i));
-                        set_bit(PG_arch_1, &page->flags);
-                } else {
-                        rflags |= HPTE_R_N;
-                }
-        }
-        return rflags;
-}
+        int shift = __ffs(size);
+        int mmu_psize;
 
-int hash_huge_page(struct mm_struct *mm, unsigned long access,
-                   unsigned long ea, unsigned long vsid, int local,
-                   unsigned long trap)
-{
-        pte_t *ptep;
-        unsigned long old_pte, new_pte;
-        unsigned long va, rflags, pa, sz;
-        long slot;
-        int err = 1;
-        int ssize = user_segment_size(ea);
-        unsigned int mmu_psize;
-        int shift;
-        mmu_psize = get_slice_psize(mm, ea);
-
-        if (!mmu_huge_psizes[mmu_psize])
-                goto out;
-        ptep = huge_pte_offset(mm, ea);
-
-        /* Search the Linux page table for a match with va */
-        va = hpt_va(ea, vsid, ssize);
+        /* Check that it is a page size supported by the hardware and
+         * that it fits within pagetable and slice limits. */
+        if (!is_power_of_2(size)
+            || (shift > SLICE_HIGH_SHIFT) || (shift <= PAGE_SHIFT))
+                return -EINVAL;
 
-        /*
-         * If no pte found or not present, send the problem up to
-         * do_page_fault
-         */
-        if (unlikely(!ptep || pte_none(*ptep)))
-                goto out;
+        if ((mmu_psize = shift_to_mmu_psize(shift)) < 0)
+                return -EINVAL;
 
-        /* 
-         * Check the user's access rights to the page.  If access should be
-         * prevented then send the problem up to do_page_fault.
+#ifdef CONFIG_SPU_FS_64K_LS
+        /* Disable support for 64K huge pages when 64K SPU local store
+         * support is enabled as the current implementation conflicts.
          */
-        if (unlikely(access & ~pte_val(*ptep)))
-                goto out;
-        /*
-         * At this point, we have a pte (old_pte) which can be used to build
-         * or update an HPTE. There are 2 cases:
-         *
-         * 1. There is a valid (present) pte with no associated HPTE (this is 
-         *      the most common case)
-         * 2. There is a valid (present) pte with an associated HPTE. The
-         *      current values of the pp bits in the HPTE prevent access
-         *      because we are doing software DIRTY bit management and the
-         *      page is currently not DIRTY. 
-         */
-
-
-        do {
-                old_pte = pte_val(*ptep);
-                if (old_pte & _PAGE_BUSY)
-                        goto out;
-                new_pte = old_pte | _PAGE_BUSY | _PAGE_ACCESSED;
-        } while(old_pte != __cmpxchg_u64((unsigned long *)ptep,
-                                         old_pte, new_pte));
-
-        rflags = 0x2 | (!(new_pte & _PAGE_RW));
-        /* _PAGE_EXEC -> HW_NO_EXEC since it's inverted */
-        rflags |= ((new_pte & _PAGE_EXEC) ? 0 : HPTE_R_N);
-        shift = mmu_psize_to_shift(mmu_psize);
-        sz = ((1UL) << shift);
-        if (!cpu_has_feature(CPU_FTR_COHERENT_ICACHE))
-                /* No CPU has hugepages but lacks no execute, so we
-                 * don't need to worry about that case */
-                rflags = hash_huge_page_do_lazy_icache(rflags, __pte(old_pte),
-                                                       trap, sz);
-
-        /* Check if pte already has an hpte (case 2) */
-        if (unlikely(old_pte & _PAGE_HASHPTE)) {
-                /* There MIGHT be an HPTE for this pte */
-                unsigned long hash, slot;
-
-                hash = hpt_hash(va, shift, ssize);
-                if (old_pte & _PAGE_F_SECOND)
-                        hash = ~hash;
-                slot = (hash & htab_hash_mask) * HPTES_PER_GROUP;
-                slot += (old_pte & _PAGE_F_GIX) >> 12;
-
-                if (ppc_md.hpte_updatepp(slot, rflags, va, mmu_psize,
-                                         ssize, local) == -1)
-                        old_pte &= ~_PAGE_HPTEFLAGS;
-        }
-
-        if (likely(!(old_pte & _PAGE_HASHPTE))) {
-                unsigned long hash = hpt_hash(va, shift, ssize);
-                unsigned long hpte_group;
-
-                pa = pte_pfn(__pte(old_pte)) << PAGE_SHIFT;
-
-repeat:
-                hpte_group = ((hash & htab_hash_mask) *
-                              HPTES_PER_GROUP) & ~0x7UL;
-
-                /* clear HPTE slot informations in new PTE */
-#ifdef CONFIG_PPC_64K_PAGES
-                new_pte = (new_pte & ~_PAGE_HPTEFLAGS) | _PAGE_HPTE_SUB0;
-#else
-                new_pte = (new_pte & ~_PAGE_HPTEFLAGS) | _PAGE_HASHPTE;
-#endif
-                /* Add in WIMG bits */
-                rflags |= (new_pte & (_PAGE_WRITETHRU | _PAGE_NO_CACHE |
-                                      _PAGE_COHERENT | _PAGE_GUARDED));
-
-                /* Insert into the hash table, primary slot */
-                slot = ppc_md.hpte_insert(hpte_group, va, pa, rflags, 0,
-                                          mmu_psize, ssize);
-
-                /* Primary is full, try the secondary */
-                if (unlikely(slot == -1)) {
-                        hpte_group = ((~hash & htab_hash_mask) *
-                                      HPTES_PER_GROUP) & ~0x7UL; 
-                        slot = ppc_md.hpte_insert(hpte_group, va, pa, rflags,
-                                                  HPTE_V_SECONDARY,
-                                                  mmu_psize, ssize);
-                        if (slot == -1) {
-                                if (mftb() & 0x1)
-                                        hpte_group = ((hash & htab_hash_mask) *
-                                                      HPTES_PER_GROUP)&~0x7UL;
-
-                                ppc_md.hpte_remove(hpte_group);
-                                goto repeat;
-                        }
-                }
-
-                if (unlikely(slot == -2))
-                        panic("hash_huge_page: pte_insert failed\n");
-
-                new_pte |= (slot << 12) & (_PAGE_F_SECOND | _PAGE_F_GIX);
-        }
+        if (shift == PAGE_SHIFT_64K)
+                return -EINVAL;
+#endif /* CONFIG_SPU_FS_64K_LS */
 
-        /*
-         * No need to use ldarx/stdcx here
-         */
-        *ptep = __pte(new_pte & ~_PAGE_BUSY);
+        BUG_ON(mmu_psize_defs[mmu_psize].shift != shift);
 
-        err = 0;
+        /* Return if huge page size has already been setup */
+        if (size_to_hstate(size))
+                return 0;
 
- out:
-        return err;
-}
+        hugetlb_add_hstate(shift - PAGE_SHIFT);
 
-static void __init set_huge_psize(int psize)
-{
-        /* Check that it is a page size supported by the hardware and
-         * that it fits within pagetable limits. */
-        if (mmu_psize_defs[psize].shift &&
-                mmu_psize_defs[psize].shift < SID_SHIFT_1T &&
-                (mmu_psize_defs[psize].shift > MIN_HUGEPTE_SHIFT ||
-                 mmu_psize_defs[psize].shift == PAGE_SHIFT_64K ||
-                 mmu_psize_defs[psize].shift == PAGE_SHIFT_16G)) {
-                /* Return if huge page size has already been setup or is the
-                 * same as the base page size. */
-                if (mmu_huge_psizes[psize] ||
-                   mmu_psize_defs[psize].shift == PAGE_SHIFT)
-                        return;
-                if (WARN_ON(HUGEPTE_CACHE_NAME(psize) == NULL))
-                        return;
-                hugetlb_add_hstate(mmu_psize_defs[psize].shift - PAGE_SHIFT);
-
-                switch (mmu_psize_defs[psize].shift) {
-                case PAGE_SHIFT_64K:
-                    /* We only allow 64k hpages with 4k base page,
-                     * which was checked above, and always put them
-                     * at the PMD */
-                    hugepte_shift[psize] = PMD_SHIFT;
-                    break;
-                case PAGE_SHIFT_16M:
-                    /* 16M pages can be at two different levels
-                     * of pagestables based on base page size */
-                    if (PAGE_SHIFT == PAGE_SHIFT_64K)
-                            hugepte_shift[psize] = PMD_SHIFT;
-                    else /* 4k base page */
-                            hugepte_shift[psize] = PUD_SHIFT;
-                    break;
-                case PAGE_SHIFT_16G:
-                    /* 16G pages are always at PGD level */
-                    hugepte_shift[psize] = PGDIR_SHIFT;
-                    break;
-                }
-                hugepte_shift[psize] -= mmu_psize_defs[psize].shift;
-        } else
-                hugepte_shift[psize] = 0;
+        return 0;
 }
 
 static int __init hugepage_setup_sz(char *str)
 {
         unsigned long long size;
-        int mmu_psize;
-        int shift;
 
         size = memparse(str, &str);
 
-        shift = __ffs(size);
-        mmu_psize = shift_to_mmu_psize(shift);
-        if (mmu_psize >= 0 && mmu_psize_defs[mmu_psize].shift)
-                set_huge_psize(mmu_psize);
-        else
+        if (add_huge_page_size(size) != 0)
                 printk(KERN_WARNING "Invalid huge page size specified(%llu)\n", size);
 
         return 1;
@@ -752,41 +526,55 @@ __setup("hugepagesz=", hugepage_setup_sz);
 
 static int __init hugetlbpage_init(void)
 {
-        unsigned int psize;
+        int psize;
 
         if (!cpu_has_feature(CPU_FTR_16M_PAGE))
                 return -ENODEV;
 
-        /* Add supported huge page sizes.  Need to change HUGE_MAX_HSTATE
-         * and adjust PTE_NONCACHE_NUM if the number of supported huge page
-         * sizes changes.
-         */
-        set_huge_psize(MMU_PAGE_16M);
-        set_huge_psize(MMU_PAGE_16G);
+        for (psize = 0; psize < MMU_PAGE_COUNT; ++psize) {
+                unsigned shift;
+                unsigned pdshift;
 
-        /* Temporarily disable support for 64K huge pages when 64K SPU local
-         * store support is enabled as the current implementation conflicts.
-         */
-#ifndef CONFIG_SPU_FS_64K_LS
-        set_huge_psize(MMU_PAGE_64K);
-#endif
+                if (!mmu_psize_defs[psize].shift)
+                        continue;
 
-        for (psize = 0; psize < MMU_PAGE_COUNT; ++psize) {
-                if (mmu_huge_psizes[psize]) {
-                        pgtable_cache[HUGE_PGTABLE_INDEX(psize)] =
-                                kmem_cache_create(
-                                        HUGEPTE_CACHE_NAME(psize),
-                                        HUGEPTE_TABLE_SIZE(psize),
-                                        HUGEPTE_TABLE_SIZE(psize),
-                                        0,
-                                        NULL);
-                        if (!pgtable_cache[HUGE_PGTABLE_INDEX(psize)])
-                                panic("hugetlbpage_init(): could not create %s"\
-                                      "\n", HUGEPTE_CACHE_NAME(psize));
-                }
+                shift = mmu_psize_to_shift(psize);
+
+                if (add_huge_page_size(1ULL << shift) < 0)
+                        continue;
+
+                if (shift < PMD_SHIFT)
+                        pdshift = PMD_SHIFT;
+                else if (shift < PUD_SHIFT)
+                        pdshift = PUD_SHIFT;
+                else
+                        pdshift = PGDIR_SHIFT;
+
+                pgtable_cache_add(pdshift - shift, NULL);
+                if (!PGT_CACHE(pdshift - shift))
+                        panic("hugetlbpage_init(): could not create "
+                              "pgtable cache for %d bit pagesize\n", shift);
         }
 
+        /* Set default large page size. Currently, we pick 16M or 1M
+         * depending on what is available
+         */
+        if (mmu_psize_defs[MMU_PAGE_16M].shift)
+                HPAGE_SHIFT = mmu_psize_defs[MMU_PAGE_16M].shift;
+        else if (mmu_psize_defs[MMU_PAGE_1M].shift)
+                HPAGE_SHIFT = mmu_psize_defs[MMU_PAGE_1M].shift;
+
         return 0;
 }
 
 module_init(hugetlbpage_init);
+
+void flush_dcache_icache_hugepage(struct page *page)
+{
+        int i;
+
+        BUG_ON(!PageCompound(page));
+
+        for (i = 0; i < (1UL << compound_order(page)); i++)
+                __flush_dcache_icache(page_address(page+i));
+}
diff --git a/arch/powerpc/mm/init_32.c b/arch/powerpc/mm/init_32.c
index 9ddcfb4dc139..4ec900af332f 100644
--- a/arch/powerpc/mm/init_32.c
+++ b/arch/powerpc/mm/init_32.c
@@ -82,6 +82,11 @@ extern struct task_struct *current_set[NR_CPUS];
 int __map_without_bats;
 int __map_without_ltlbs;
 
+/*
+ * This tells the system to allow ioremapping memory marked as reserved.
+ */
+int __allow_ioremap_reserved;
+
 /* max amount of low RAM to map in */
 unsigned long __max_low_memory = MAX_LOW_MEM;
 
@@ -131,9 +136,13 @@ void __init MMU_init(void)
         MMU_setup();
 
         if (lmb.memory.cnt > 1) {
+#ifndef CONFIG_WII
                 lmb.memory.cnt = 1;
                 lmb_analyze();
                 printk(KERN_WARNING "Only using first contiguous memory region");
+#else
+                wii_memory_fixups();
+#endif
         }
 
         total_lowmem = total_memory = lmb_end_of_DRAM() - memstart_addr;
diff --git a/arch/powerpc/mm/init_64.c b/arch/powerpc/mm/init_64.c
index 335c578b9cc3..776f28d02b6b 100644
--- a/arch/powerpc/mm/init_64.c
+++ b/arch/powerpc/mm/init_64.c
@@ -41,6 +41,7 @@
 #include <linux/module.h>
 #include <linux/poison.h>
 #include <linux/lmb.h>
+#include <linux/hugetlb.h>
 
 #include <asm/pgalloc.h>
 #include <asm/page.h>
@@ -119,30 +120,63 @@ static void pmd_ctor(void *addr)
         memset(addr, 0, PMD_TABLE_SIZE);
 }
 
-static const unsigned int pgtable_cache_size[2] = {
-        PGD_TABLE_SIZE, PMD_TABLE_SIZE
-};
-static const char *pgtable_cache_name[ARRAY_SIZE(pgtable_cache_size)] = {
-#ifdef CONFIG_PPC_64K_PAGES
-        "pgd_cache", "pmd_cache",
-#else
-        "pgd_cache", "pud_pmd_cache",
-#endif /* CONFIG_PPC_64K_PAGES */
-};
-
-#ifdef CONFIG_HUGETLB_PAGE
-/* Hugepages need an extra cache per hugepagesize, initialized in
- * hugetlbpage.c.  We can't put into the tables above, because HPAGE_SHIFT
- * is not compile time constant. */
-struct kmem_cache *pgtable_cache[ARRAY_SIZE(pgtable_cache_size)+MMU_PAGE_COUNT];
-#else
-struct kmem_cache *pgtable_cache[ARRAY_SIZE(pgtable_cache_size)];
-#endif
+struct kmem_cache *pgtable_cache[MAX_PGTABLE_INDEX_SIZE];
+
+/*
+ * Create a kmem_cache() for pagetables.  This is not used for PTE
+ * pages - they're linked to struct page, come from the normal free
+ * pages pool and have a different entry size (see real_pte_t) to
+ * everything else.  Caches created by this function are used for all
+ * the higher level pagetables, and for hugepage pagetables.
+ */
+void pgtable_cache_add(unsigned shift, void (*ctor)(void *))
+{
+        char *name;
+        unsigned long table_size = sizeof(void *) << shift;
+        unsigned long align = table_size;
+
+        /* When batching pgtable pointers for RCU freeing, we store
+         * the index size in the low bits.  Table alignment must be
+         * big enough to fit it.
+         *
+         * Likewise, hugeapge pagetable pointers contain a (different)
+         * shift value in the low bits.  All tables must be aligned so
+         * as to leave enough 0 bits in the address to contain it. */
+        unsigned long minalign = max(MAX_PGTABLE_INDEX_SIZE + 1,
+                                     HUGEPD_SHIFT_MASK + 1);
+        struct kmem_cache *new;
+
+        /* It would be nice if this was a BUILD_BUG_ON(), but at the
+         * moment, gcc doesn't seem to recognize is_power_of_2 as a
+         * constant expression, so so much for that. */
+        BUG_ON(!is_power_of_2(minalign));
+        BUG_ON((shift < 1) || (shift > MAX_PGTABLE_INDEX_SIZE));
+
+        if (PGT_CACHE(shift))
+                return; /* Already have a cache of this size */
+
+        align = max_t(unsigned long, align, minalign);
+        name = kasprintf(GFP_KERNEL, "pgtable-2^%d", shift);
+        new = kmem_cache_create(name, table_size, align, 0, ctor);
+        PGT_CACHE(shift) = new;
+
+        pr_debug("Allocated pgtable cache for order %d\n", shift);
+}
+
 
 void pgtable_cache_init(void)
 {
-        pgtable_cache[0] = kmem_cache_create(pgtable_cache_name[0], PGD_TABLE_SIZE, PGD_TABLE_SIZE, SLAB_PANIC, pgd_ctor);
-        pgtable_cache[1] = kmem_cache_create(pgtable_cache_name[1], PMD_TABLE_SIZE, PMD_TABLE_SIZE, SLAB_PANIC, pmd_ctor);
+        pgtable_cache_add(PGD_INDEX_SIZE, pgd_ctor);
+        pgtable_cache_add(PMD_INDEX_SIZE, pmd_ctor);
+        if (!PGT_CACHE(PGD_INDEX_SIZE) || !PGT_CACHE(PMD_INDEX_SIZE))
+                panic("Couldn't allocate pgtable caches");
+
+        /* In all current configs, when the PUD index exists it's the
+         * same size as either the pgd or pmd index.  Verify that the
+         * initialization above has also created a PUD cache.  This
+         * will need re-examiniation if we add new possibilities for
+         * the pagetable layout. */
+        BUG_ON(PUD_INDEX_SIZE && !PGT_CACHE(PUD_INDEX_SIZE));
 }
 
 #ifdef CONFIG_SPARSEMEM_VMEMMAP
diff --git a/arch/powerpc/mm/mem.c b/arch/powerpc/mm/mem.c
index 59736317bf0e..b9b152558f9c 100644
--- a/arch/powerpc/mm/mem.c
+++ b/arch/powerpc/mm/mem.c
@@ -32,6 +32,7 @@
 #include <linux/pagemap.h>
 #include <linux/suspend.h>
 #include <linux/lmb.h>
+#include <linux/hugetlb.h>
 
 #include <asm/pgalloc.h>
 #include <asm/prom.h>
@@ -417,18 +418,26 @@ EXPORT_SYMBOL(flush_dcache_page);
 
 void flush_dcache_icache_page(struct page *page)
 {
+#ifdef CONFIG_HUGETLB_PAGE
+        if (PageCompound(page)) {
+                flush_dcache_icache_hugepage(page);
+                return;
+        }
+#endif
 #ifdef CONFIG_BOOKE
-        void *start = kmap_atomic(page, KM_PPC_SYNC_ICACHE);
-        __flush_dcache_icache(start);
-        kunmap_atomic(start, KM_PPC_SYNC_ICACHE);
+        {
+                void *start = kmap_atomic(page, KM_PPC_SYNC_ICACHE);
+                __flush_dcache_icache(start);
+                kunmap_atomic(start, KM_PPC_SYNC_ICACHE);
+        }
 #elif defined(CONFIG_8xx) || defined(CONFIG_PPC64)
         /* On 8xx there is no need to kmap since highmem is not supported */
         __flush_dcache_icache(page_address(page)); 
 #else
         __flush_dcache_icache_phys(page_to_pfn(page) << PAGE_SHIFT);
 #endif
-
 }
+
 void clear_user_page(void *page, unsigned long vaddr, struct page *pg)
 {
         clear_page(page);
diff --git a/arch/powerpc/mm/mmu_context_hash64.c b/arch/powerpc/mm/mmu_context_hash64.c
index dbeb86ac90cd..b910d37aea1a 100644
--- a/arch/powerpc/mm/mmu_context_hash64.c
+++ b/arch/powerpc/mm/mmu_context_hash64.c
@@ -18,6 +18,7 @@
 #include <linux/mm.h>
 #include <linux/spinlock.h>
 #include <linux/idr.h>
+#include <linux/module.h>
 
 #include <asm/mmu_context.h>
 
@@ -32,7 +33,7 @@ static DEFINE_IDR(mmu_context_idr);
 #define NO_CONTEXT      0
 #define MAX_CONTEXT     ((1UL << 19) - 1)
 
-int init_new_context(struct task_struct *tsk, struct mm_struct *mm)
+int __init_new_context(void)
 {
         int index;
         int err;
@@ -57,22 +58,41 @@ again:
                 return -ENOMEM;
         }
 
+        return index;
+}
+EXPORT_SYMBOL_GPL(__init_new_context);
+
+int init_new_context(struct task_struct *tsk, struct mm_struct *mm)
+{
+        int index;
+
+        index = __init_new_context();
+        if (index < 0)
+                return index;
+
         /* The old code would re-promote on fork, we don't do that
          * when using slices as it could cause problem promoting slices
          * that have been forced down to 4K
          */
         if (slice_mm_new_context(mm))
                 slice_set_user_psize(mm, mmu_virtual_psize);
+        subpage_prot_init_new_context(mm);
         mm->context.id = index;
 
         return 0;
 }
 
-void destroy_context(struct mm_struct *mm)
+void __destroy_context(int context_id)
 {
         spin_lock(&mmu_context_lock);
-        idr_remove(&mmu_context_idr, mm->context.id);
+        idr_remove(&mmu_context_idr, context_id);
         spin_unlock(&mmu_context_lock);
+}
+EXPORT_SYMBOL_GPL(__destroy_context);
 
+void destroy_context(struct mm_struct *mm)
+{
+        __destroy_context(mm->context.id);
+        subpage_prot_free(mm);
         mm->context.id = NO_CONTEXT;
 }
diff --git a/arch/powerpc/mm/mmu_decl.h b/arch/powerpc/mm/mmu_decl.h
index d2e5321d5ea6..d49a77503e19 100644
--- a/arch/powerpc/mm/mmu_decl.h
+++ b/arch/powerpc/mm/mmu_decl.h
@@ -98,23 +98,13 @@ extern void _tlbia(void);
 
 #ifdef CONFIG_PPC32
 
-struct tlbcam {
-        u32     MAS0;
-        u32     MAS1;
-        u32     MAS2;
-        u32     MAS3;
-        u32     MAS7;
-};
-
 extern void mapin_ram(void);
 extern int map_page(unsigned long va, phys_addr_t pa, int flags);
 extern void setbat(int index, unsigned long virt, phys_addr_t phys,
                    unsigned int size, int flags);
-extern void settlbcam(int index, unsigned long virt, phys_addr_t phys,
-                      unsigned int size, int flags, unsigned int pid);
-extern void invalidate_tlbcam_entry(int index);
 
 extern int __map_without_bats;
+extern int __allow_ioremap_reserved;
 extern unsigned long ioremap_base;
 extern unsigned int rtas_data, rtas_size;
 
@@ -136,24 +126,32 @@ extern phys_addr_t total_lowmem;
 extern phys_addr_t memstart_addr;
 extern phys_addr_t lowmem_end_addr;
 
+#ifdef CONFIG_WII
+extern unsigned long wii_hole_start;
+extern unsigned long wii_hole_size;
+
+extern unsigned long wii_mmu_mapin_mem2(unsigned long top);
+extern void wii_memory_fixups(void);
+#endif
+
 /* ...and now those things that may be slightly different between processor
  * architectures.  -- Dan
  */
 #if defined(CONFIG_8xx)
 #define MMU_init_hw()           do { } while(0)
-#define mmu_mapin_ram()         (0UL)
+#define mmu_mapin_ram(top)      (0UL)
 
 #elif defined(CONFIG_4xx)
 extern void MMU_init_hw(void);
-extern unsigned long mmu_mapin_ram(void);
+extern unsigned long mmu_mapin_ram(unsigned long top);
 
 #elif defined(CONFIG_FSL_BOOKE)
 extern void MMU_init_hw(void);
-extern unsigned long mmu_mapin_ram(void);
+extern unsigned long mmu_mapin_ram(unsigned long top);
 extern void adjust_total_lowmem(void);
 
 #elif defined(CONFIG_PPC32)
 /* anything 32-bit except 4xx or 8xx */
 extern void MMU_init_hw(void);
-extern unsigned long mmu_mapin_ram(void);
+extern unsigned long mmu_mapin_ram(unsigned long top);
 #endif
diff --git a/arch/powerpc/mm/pgtable.c b/arch/powerpc/mm/pgtable.c
index 53040931de32..99df697c601a 100644
--- a/arch/powerpc/mm/pgtable.c
+++ b/arch/powerpc/mm/pgtable.c
@@ -49,12 +49,12 @@ struct pte_freelist_batch
 {
         struct rcu_head rcu;
         unsigned int    index;
-        pgtable_free_t  tables[0];
+        unsigned long   tables[0];
 };
 
 #define PTE_FREELIST_SIZE \
         ((PAGE_SIZE - sizeof(struct pte_freelist_batch)) \
-          / sizeof(pgtable_free_t))
+          / sizeof(unsigned long))
 
 static void pte_free_smp_sync(void *arg)
 {
@@ -64,13 +64,13 @@ static void pte_free_smp_sync(void *arg)
 /* This is only called when we are critically out of memory
  * (and fail to get a page in pte_free_tlb).
  */
-static void pgtable_free_now(pgtable_free_t pgf)
+static void pgtable_free_now(void *table, unsigned shift)
 {
         pte_freelist_forced_free++;
 
         smp_call_function(pte_free_smp_sync, NULL, 1);
 
-        pgtable_free(pgf);
+        pgtable_free(table, shift);
 }
 
 static void pte_free_rcu_callback(struct rcu_head *head)
@@ -79,8 +79,12 @@ static void pte_free_rcu_callback(struct rcu_head *head)
                 container_of(head, struct pte_freelist_batch, rcu);
         unsigned int i;
 
-        for (i = 0; i < batch->index; i++)
-                pgtable_free(batch->tables[i]);
+        for (i = 0; i < batch->index; i++) {
+                void *table = (void *)(batch->tables[i] & ~MAX_PGTABLE_INDEX_SIZE);
+                unsigned shift = batch->tables[i] & MAX_PGTABLE_INDEX_SIZE;
+
+                pgtable_free(table, shift);
+        }
 
         free_page((unsigned long)batch);
 }
@@ -91,25 +95,28 @@ static void pte_free_submit(struct pte_freelist_batch *batch)
         call_rcu(&batch->rcu, pte_free_rcu_callback);
 }
 
-void pgtable_free_tlb(struct mmu_gather *tlb, pgtable_free_t pgf)
+void pgtable_free_tlb(struct mmu_gather *tlb, void *table, unsigned shift)
 {
         /* This is safe since tlb_gather_mmu has disabled preemption */
         struct pte_freelist_batch **batchp = &__get_cpu_var(pte_freelist_cur);
+        unsigned long pgf;
 
         if (atomic_read(&tlb->mm->mm_users) < 2 ||
             cpumask_equal(mm_cpumask(tlb->mm), cpumask_of(smp_processor_id()))){
-                pgtable_free(pgf);
+                pgtable_free(table, shift);
                 return;
         }
 
         if (*batchp == NULL) {
                 *batchp = (struct pte_freelist_batch *)__get_free_page(GFP_ATOMIC);
                 if (*batchp == NULL) {
-                        pgtable_free_now(pgf);
+                        pgtable_free_now(table, shift);
                         return;
                 }
                 (*batchp)->index = 0;
         }
+        BUG_ON(shift > MAX_PGTABLE_INDEX_SIZE);
+        pgf = (unsigned long)table | shift;
         (*batchp)->tables[(*batchp)->index++] = pgf;
         if ((*batchp)->index == PTE_FREELIST_SIZE) {
                 pte_free_submit(*batchp);
diff --git a/arch/powerpc/mm/pgtable_32.c b/arch/powerpc/mm/pgtable_32.c
index cb96cb2e17cc..177e4038b43c 100644
--- a/arch/powerpc/mm/pgtable_32.c
+++ b/arch/powerpc/mm/pgtable_32.c
@@ -26,6 +26,7 @@
 #include <linux/vmalloc.h>
 #include <linux/init.h>
 #include <linux/highmem.h>
+#include <linux/lmb.h>
 
 #include <asm/pgtable.h>
 #include <asm/pgalloc.h>
@@ -191,7 +192,8 @@ __ioremap_caller(phys_addr_t addr, unsigned long size, unsigned long flags,
          * Don't allow anybody to remap normal RAM that we're using.
          * mem_init() sets high_memory so only do the check after that.
          */
-        if (mem_init_done && (p < virt_to_phys(high_memory))) {
+        if (mem_init_done && (p < virt_to_phys(high_memory)) &&
+            !(__allow_ioremap_reserved && lmb_is_region_reserved(p, size))) {
                 printk("__ioremap(): phys addr 0x%llx is RAM lr %p\n",
                        (unsigned long long)p, __builtin_return_address(0));
                 return NULL;
@@ -283,18 +285,18 @@ int map_page(unsigned long va, phys_addr_t pa, int flags)
 }
 
 /*
- * Map in a big chunk of physical memory starting at PAGE_OFFSET.
+ * Map in a chunk of physical memory starting at start.
  */
-void __init mapin_ram(void)
+void __init __mapin_ram_chunk(unsigned long offset, unsigned long top)
 {
         unsigned long v, s, f;
         phys_addr_t p;
         int ktext;
 
-        s = mmu_mapin_ram();
+        s = offset;
         v = PAGE_OFFSET + s;
         p = memstart_addr + s;
-        for (; s < total_lowmem; s += PAGE_SIZE) {
+        for (; s < top; s += PAGE_SIZE) {
                 ktext = ((char *) v >= _stext && (char *) v < etext);
                 f = ktext ? PAGE_KERNEL_TEXT : PAGE_KERNEL;
                 map_page(v, p, f);
@@ -307,6 +309,30 @@ void __init mapin_ram(void)
         }
 }
 
+void __init mapin_ram(void)
+{
+        unsigned long s, top;
+
+#ifndef CONFIG_WII
+        top = total_lowmem;
+        s = mmu_mapin_ram(top);
+        __mapin_ram_chunk(s, top);
+#else
+        if (!wii_hole_size) {
+                s = mmu_mapin_ram(total_lowmem);
+                __mapin_ram_chunk(s, total_lowmem);
+        } else {
+                top = wii_hole_start;
+                s = mmu_mapin_ram(top);
+                __mapin_ram_chunk(s, top);
+
+                top = lmb_end_of_DRAM();
+                s = wii_mmu_mapin_mem2(top);
+                __mapin_ram_chunk(s, top);
+        }
+#endif
+}
+
 /* Scan the real Linux page tables and return a PTE pointer for
  * a virtual address in a context.
  * Returns true (1) if PTE was found, zero otherwise.  The pointer to
diff --git a/arch/powerpc/mm/ppc_mmu_32.c b/arch/powerpc/mm/ppc_mmu_32.c
index 2d2a87e10154..f11c2cdcb0fe 100644
--- a/arch/powerpc/mm/ppc_mmu_32.c
+++ b/arch/powerpc/mm/ppc_mmu_32.c
@@ -72,7 +72,7 @@ unsigned long p_mapped_by_bats(phys_addr_t pa)
         return 0;
 }
 
-unsigned long __init mmu_mapin_ram(void)
+unsigned long __init mmu_mapin_ram(unsigned long top)
 {
         unsigned long tot, bl, done;
         unsigned long max_size = (256<<20);
@@ -86,7 +86,7 @@ unsigned long __init mmu_mapin_ram(void)
 
         /* Make sure we don't map a block larger than the
            smallest alignment of the physical address. */
-        tot = total_lowmem;
+        tot = top;
         for (bl = 128<<10; bl < max_size; bl <<= 1) {
                 if (bl * 2 > tot)
                         break;
diff --git a/arch/powerpc/mm/subpage-prot.c b/arch/powerpc/mm/subpage-prot.c
index 4cafc0c33d0a..a040b81e93bd 100644
--- a/arch/powerpc/mm/subpage-prot.c
+++ b/arch/powerpc/mm/subpage-prot.c
@@ -24,9 +24,9 @@
  * Also makes sure that the subpage_prot_table structure is
  * reinitialized for the next user.
  */
-void subpage_prot_free(pgd_t *pgd)
+void subpage_prot_free(struct mm_struct *mm)
 {
-        struct subpage_prot_table *spt = pgd_subpage_prot(pgd);
+        struct subpage_prot_table *spt = &mm->context.spt;
         unsigned long i, j, addr;
         u32 **p;
 
@@ -51,6 +51,13 @@ void subpage_prot_free(pgd_t *pgd)
         spt->maxaddr = 0;
 }
 
+void subpage_prot_init_new_context(struct mm_struct *mm)
+{
+        struct subpage_prot_table *spt = &mm->context.spt;
+
+        memset(spt, 0, sizeof(*spt));
+}
+
 static void hpte_flush_range(struct mm_struct *mm, unsigned long addr,
                              int npages)
 {
@@ -87,7 +94,7 @@ static void hpte_flush_range(struct mm_struct *mm, unsigned long addr,
 static void subpage_prot_clear(unsigned long addr, unsigned long len)
 {
         struct mm_struct *mm = current->mm;
-        struct subpage_prot_table *spt = pgd_subpage_prot(mm->pgd);
+        struct subpage_prot_table *spt = &mm->context.spt;
         u32 **spm, *spp;
         int i, nw;
         unsigned long next, limit;
@@ -136,7 +143,7 @@ static void subpage_prot_clear(unsigned long addr, unsigned long len)
 long sys_subpage_prot(unsigned long addr, unsigned long len, u32 __user *map)
 {
         struct mm_struct *mm = current->mm;
-        struct subpage_prot_table *spt = pgd_subpage_prot(mm->pgd);
+        struct subpage_prot_table *spt = &mm->context.spt;
         u32 **spm, *spp;
         int i, nw;
         unsigned long next, limit;
diff --git a/arch/powerpc/mm/tlb_hash64.c b/arch/powerpc/mm/tlb_hash64.c
index 2b2f35f6985e..282d9306361f 100644
--- a/arch/powerpc/mm/tlb_hash64.c
+++ b/arch/powerpc/mm/tlb_hash64.c
@@ -53,11 +53,6 @@ void hpte_need_flush(struct mm_struct *mm, unsigned long addr,
 
         i = batch->index;
 
-        /* We mask the address for the base page size. Huge pages will
-         * have applied their own masking already
-         */
-        addr &= PAGE_MASK;
-
         /* Get page size (maybe move back to caller).
          *
          * NOTE: when using special 64K mappings in 4K environment like
@@ -75,6 +70,9 @@ void hpte_need_flush(struct mm_struct *mm, unsigned long addr,
         } else
                 psize = pte_pagesize_index(mm, addr, pte);
 
+        /* Mask the address for the correct page size */
+        addr &= ~((1UL << mmu_psize_defs[psize].shift) - 1);
+
         /* Build full vaddr */
         if (!is_kernel_addr(addr)) {
                 ssize = user_segment_size(addr);
diff --git a/arch/powerpc/platforms/512x/mpc5121_ads_cpld.c b/arch/powerpc/platforms/512x/mpc5121_ads_cpld.c
index a6ce80566625..da9b20a63769 100644
--- a/arch/powerpc/platforms/512x/mpc5121_ads_cpld.c
+++ b/arch/powerpc/platforms/512x/mpc5121_ads_cpld.c
@@ -79,7 +79,7 @@ cpld_unmask_irq(unsigned int irq)
 }
 
 static struct irq_chip cpld_pic = {
-        .typename = " CPLD PIC ",
+        .name = " CPLD PIC ",
         .mask = cpld_mask_irq,
         .ack = cpld_mask_irq,
         .unmask = cpld_unmask_irq,
@@ -132,7 +132,7 @@ static int
 cpld_pic_host_map(struct irq_host *h, unsigned int virq,
                              irq_hw_number_t hw)
 {
-        get_irq_desc(virq)->status |= IRQ_LEVEL;
+        irq_to_desc(virq)->status |= IRQ_LEVEL;
         set_irq_chip_and_handler(virq, &cpld_pic, handle_level_irq);
         return 0;
 }
diff --git a/arch/powerpc/platforms/52xx/Kconfig b/arch/powerpc/platforms/52xx/Kconfig
index 8b8e9560a315..47ea1be1481b 100644
--- a/arch/powerpc/platforms/52xx/Kconfig
+++ b/arch/powerpc/platforms/52xx/Kconfig
@@ -62,3 +62,8 @@ config PPC_MPC5200_GPIO
         select GENERIC_GPIO
         help
           Enable gpiolib support for mpc5200 based boards
+
+config PPC_MPC5200_LPBFIFO
+        tristate "MPC5200 LocalPlus bus FIFO driver"
+        depends on PPC_MPC52xx
+        select PPC_BESTCOMM_GEN_BD
diff --git a/arch/powerpc/platforms/52xx/Makefile b/arch/powerpc/platforms/52xx/Makefile
index bfd4f52cf3dd..2bc8cd0c5cfc 100644
--- a/arch/powerpc/platforms/52xx/Makefile
+++ b/arch/powerpc/platforms/52xx/Makefile
@@ -15,3 +15,4 @@ ifeq ($(CONFIG_PPC_LITE5200),y)
 endif
 
 obj-$(CONFIG_PPC_MPC5200_GPIO)  += mpc52xx_gpio.o
+obj-$(CONFIG_PPC_MPC5200_LPBFIFO)       += mpc52xx_lpbfifo.o
diff --git a/arch/powerpc/platforms/52xx/efika.c b/arch/powerpc/platforms/52xx/efika.c
index bcc69e1f77c1..45c0cb9b67e6 100644
--- a/arch/powerpc/platforms/52xx/efika.c
+++ b/arch/powerpc/platforms/52xx/efika.c
@@ -10,7 +10,7 @@
  */
 
 #include <linux/init.h>
-#include <linux/utsrelease.h>
+#include <generated/utsrelease.h>
 #include <linux/pci.h>
 #include <linux/of.h>
 #include <asm/prom.h>
diff --git a/arch/powerpc/platforms/52xx/media5200.c b/arch/powerpc/platforms/52xx/media5200.c
index 68e4f1696d14..0bac3a3dbecf 100644
--- a/arch/powerpc/platforms/52xx/media5200.c
+++ b/arch/powerpc/platforms/52xx/media5200.c
@@ -74,7 +74,7 @@ static void media5200_irq_mask(unsigned int virq)
 }
 
 static struct irq_chip media5200_irq_chip = {
-        .typename = "Media5200 FPGA",
+        .name = "Media5200 FPGA",
         .unmask = media5200_irq_unmask,
         .mask = media5200_irq_mask,
         .mask_ack = media5200_irq_mask,
@@ -86,9 +86,9 @@ void media5200_irq_cascade(unsigned int virq, struct irq_desc *desc)
         u32 status, enable;
 
         /* Mask off the cascaded IRQ */
-        spin_lock(&desc->lock);
+        raw_spin_lock(&desc->lock);
         desc->chip->mask(virq);
-        spin_unlock(&desc->lock);
+        raw_spin_unlock(&desc->lock);
 
         /* Ask the FPGA for IRQ status.  If 'val' is 0, then no irqs
          * are pending.  'ffs()' is 1 based */
@@ -104,17 +104,17 @@ void media5200_irq_cascade(unsigned int virq, struct irq_desc *desc)
         }
 
         /* Processing done; can reenable the cascade now */
-        spin_lock(&desc->lock);
+        raw_spin_lock(&desc->lock);
         desc->chip->ack(virq);
         if (!(desc->status & IRQ_DISABLED))
                 desc->chip->unmask(virq);
-        spin_unlock(&desc->lock);
+        raw_spin_unlock(&desc->lock);
 }
 
 static int media5200_irq_map(struct irq_host *h, unsigned int virq,
                              irq_hw_number_t hw)
 {
-        struct irq_desc *desc = get_irq_desc(virq);
+        struct irq_desc *desc = irq_to_desc(virq);
 
         pr_debug("%s: h=%p, virq=%i, hwirq=%i\n", __func__, h, virq, (int)hw);
         set_irq_chip_data(virq, &media5200_irq);
@@ -127,7 +127,7 @@ static int media5200_irq_map(struct irq_host *h, unsigned int virq,
 }
 
 static int media5200_irq_xlate(struct irq_host *h, struct device_node *ct,
-                                 u32 *intspec, unsigned int intsize,
+                                 const u32 *intspec, unsigned int intsize,
                                  irq_hw_number_t *out_hwirq,
                                  unsigned int *out_flags)
 {
diff --git a/arch/powerpc/platforms/52xx/mpc52xx_gpt.c b/arch/powerpc/platforms/52xx/mpc52xx_gpt.c
index bfbcd418e690..6f8ebe1085b3 100644
--- a/arch/powerpc/platforms/52xx/mpc52xx_gpt.c
+++ b/arch/powerpc/platforms/52xx/mpc52xx_gpt.c
@@ -16,8 +16,14 @@
  * output signals or measure input signals.
  *
  * This driver supports the GPIO and IRQ controller functions of the GPT
- * device.  Timer functions are not yet supported, nor is the watchdog
- * timer.
+ * device.  Timer functions are not yet supported.
+ *
+ * The timer gpt0 can be used as watchdog (wdt).  If the wdt mode is used,
+ * this prevents the use of any gpt0 gpt function (i.e. they will fail with
+ * -EBUSY).  Thus, the safety wdt function always has precedence over the gpt
+ * function.  If the kernel has been compiled with CONFIG_WATCHDOG_NOWAYOUT,
+ * this means that gpt0 is locked in wdt mode until the next reboot - this
+ * may be a requirement in safety applications.
  *
  * To use the GPIO function, the following two properties must be added
  * to the device tree node for the gpt device (typically in the .dts file
@@ -46,17 +52,24 @@
  * the output mode.  This driver does not change the output mode setting.
  */
 
+#include <linux/device.h>
 #include <linux/irq.h>
 #include <linux/interrupt.h>
 #include <linux/io.h>
+#include <linux/list.h>
+#include <linux/mutex.h>
 #include <linux/of.h>
 #include <linux/of_platform.h>
 #include <linux/of_gpio.h>
 #include <linux/kernel.h>
+#include <linux/watchdog.h>
+#include <linux/miscdevice.h>
+#include <linux/uaccess.h>
+#include <asm/div64.h>
 #include <asm/mpc52xx.h>
 
 MODULE_DESCRIPTION("Freescale MPC52xx gpt driver");
-MODULE_AUTHOR("Sascha Hauer, Grant Likely");
+MODULE_AUTHOR("Sascha Hauer, Grant Likely, Albrecht Dreß");
 MODULE_LICENSE("GPL");
 
 /**
@@ -66,18 +79,27 @@ MODULE_LICENSE("GPL");
  * @lock: spinlock to coordinate between different functions.
  * @of_gc: of_gpio_chip instance structure; used when GPIO is enabled
  * @irqhost: Pointer to irq_host instance; used when IRQ mode is supported
+ * @wdt_mode: only relevant for gpt0: bit 0 (MPC52xx_GPT_CAN_WDT) indicates
+ *   if the gpt may be used as wdt, bit 1 (MPC52xx_GPT_IS_WDT) indicates
+ *   if the timer is actively used as wdt which blocks gpt functions
  */
 struct mpc52xx_gpt_priv {
+        struct list_head list;          /* List of all GPT devices */
         struct device *dev;
         struct mpc52xx_gpt __iomem *regs;
         spinlock_t lock;
         struct irq_host *irqhost;
+        u32 ipb_freq;
+        u8 wdt_mode;
 
 #if defined(CONFIG_GPIOLIB)
         struct of_gpio_chip of_gc;
 #endif
 };
 
+LIST_HEAD(mpc52xx_gpt_list);
+DEFINE_MUTEX(mpc52xx_gpt_list_mutex);
+
 #define MPC52xx_GPT_MODE_MS_MASK        (0x07)
 #define MPC52xx_GPT_MODE_MS_IC          (0x01)
 #define MPC52xx_GPT_MODE_MS_OC          (0x02)
@@ -88,15 +110,25 @@ struct mpc52xx_gpt_priv {
 #define MPC52xx_GPT_MODE_GPIO_OUT_LOW   (0x20)
 #define MPC52xx_GPT_MODE_GPIO_OUT_HIGH  (0x30)
 
+#define MPC52xx_GPT_MODE_COUNTER_ENABLE (0x1000)
+#define MPC52xx_GPT_MODE_CONTINUOUS     (0x0400)
+#define MPC52xx_GPT_MODE_OPEN_DRAIN     (0x0200)
 #define MPC52xx_GPT_MODE_IRQ_EN         (0x0100)
+#define MPC52xx_GPT_MODE_WDT_EN         (0x8000)
 
 #define MPC52xx_GPT_MODE_ICT_MASK       (0x030000)
 #define MPC52xx_GPT_MODE_ICT_RISING     (0x010000)
 #define MPC52xx_GPT_MODE_ICT_FALLING    (0x020000)
 #define MPC52xx_GPT_MODE_ICT_TOGGLE     (0x030000)
 
+#define MPC52xx_GPT_MODE_WDT_PING       (0xa5)
+
 #define MPC52xx_GPT_STATUS_IRQMASK      (0x000f)
 
+#define MPC52xx_GPT_CAN_WDT             (1 << 0)
+#define MPC52xx_GPT_IS_WDT              (1 << 1)
+
+
 /* ---------------------------------------------------------------------
  * Cascaded interrupt controller hooks
  */
@@ -149,7 +181,7 @@ static int mpc52xx_gpt_irq_set_type(unsigned int virq, unsigned int flow_type)
 }
 
 static struct irq_chip mpc52xx_gpt_irq_chip = {
-        .typename = "MPC52xx GPT",
+        .name = "MPC52xx GPT",
         .unmask = mpc52xx_gpt_irq_unmask,
         .mask = mpc52xx_gpt_irq_mask,
         .ack = mpc52xx_gpt_irq_ack,
@@ -182,7 +214,7 @@ static int mpc52xx_gpt_irq_map(struct irq_host *h, unsigned int virq,
 }
 
 static int mpc52xx_gpt_irq_xlate(struct irq_host *h, struct device_node *ct,
-                                 u32 *intspec, unsigned int intsize,
+                                 const u32 *intspec, unsigned int intsize,
                                  irq_hw_number_t *out_hwirq,
                                  unsigned int *out_flags)
 {
@@ -190,7 +222,7 @@ static int mpc52xx_gpt_irq_xlate(struct irq_host *h, struct device_node *ct,
 
         dev_dbg(gpt->dev, "%s: flags=%i\n", __func__, intspec[0]);
 
-        if ((intsize < 1) || (intspec[0] < 1) || (intspec[0] > 3)) {
+        if ((intsize < 1) || (intspec[0] > 3)) {
                 dev_err(gpt->dev, "bad irq specifier in %s\n", ct->full_name);
                 return -EINVAL;
         }
@@ -211,13 +243,11 @@ mpc52xx_gpt_irq_setup(struct mpc52xx_gpt_priv *gpt, struct device_node *node)
 {
         int cascade_virq;
         unsigned long flags;
-
-        /* Only setup cascaded IRQ if device tree claims the GPT is
-         * an interrupt controller */
-        if (!of_find_property(node, "interrupt-controller", NULL))
-                return;
+        u32 mode;
 
         cascade_virq = irq_of_parse_and_map(node, 0);
+        if (!cascade_virq)
+                return;
 
         gpt->irqhost = irq_alloc_host(node, IRQ_HOST_MAP_LINEAR, 1,
                                       &mpc52xx_gpt_irq_ops, -1);
@@ -227,14 +257,16 @@ mpc52xx_gpt_irq_setup(struct mpc52xx_gpt_priv *gpt, struct device_node *node)
         }
 
         gpt->irqhost->host_data = gpt;
-
         set_irq_data(cascade_virq, gpt);
         set_irq_chained_handler(cascade_virq, mpc52xx_gpt_irq_cascade);
 
-        /* Set to Input Capture mode */
+        /* If the GPT is currently disabled, then change it to be in Input
+         * Capture mode.  If the mode is non-zero, then the pin could be
+         * already in use for something. */
         spin_lock_irqsave(&gpt->lock, flags);
-        clrsetbits_be32(&gpt->regs->mode, MPC52xx_GPT_MODE_MS_MASK,
-                        MPC52xx_GPT_MODE_MS_IC);
+        mode = in_be32(&gpt->regs->mode);
+        if ((mode & MPC52xx_GPT_MODE_MS_MASK) == 0)
+                out_be32(&gpt->regs->mode, mode | MPC52xx_GPT_MODE_MS_IC);
         spin_unlock_irqrestore(&gpt->lock, flags);
 
         dev_dbg(gpt->dev, "%s() complete. virq=%i\n", __func__, cascade_virq);
@@ -335,6 +367,354 @@ static void
 mpc52xx_gpt_gpio_setup(struct mpc52xx_gpt_priv *p, struct device_node *np) { }
 #endif /* defined(CONFIG_GPIOLIB) */
 
+/***********************************************************************
+ * Timer API
+ */
+
+/**
+ * mpc52xx_gpt_from_irq - Return the GPT device associated with an IRQ number
+ * @irq: irq of timer.
+ */
+struct mpc52xx_gpt_priv *mpc52xx_gpt_from_irq(int irq)
+{
+        struct mpc52xx_gpt_priv *gpt;
+        struct list_head *pos;
+
+        /* Iterate over the list of timers looking for a matching device */
+        mutex_lock(&mpc52xx_gpt_list_mutex);
+        list_for_each(pos, &mpc52xx_gpt_list) {
+                gpt = container_of(pos, struct mpc52xx_gpt_priv, list);
+                if (gpt->irqhost && irq == irq_linear_revmap(gpt->irqhost, 0)) {
+                        mutex_unlock(&mpc52xx_gpt_list_mutex);
+                        return gpt;
+                }
+        }
+        mutex_unlock(&mpc52xx_gpt_list_mutex);
+
+        return NULL;
+}
+EXPORT_SYMBOL(mpc52xx_gpt_from_irq);
+
+static int mpc52xx_gpt_do_start(struct mpc52xx_gpt_priv *gpt, u64 period,
+                                int continuous, int as_wdt)
+{
+        u32 clear, set;
+        u64 clocks;
+        u32 prescale;
+        unsigned long flags;
+
+        clear = MPC52xx_GPT_MODE_MS_MASK | MPC52xx_GPT_MODE_CONTINUOUS;
+        set = MPC52xx_GPT_MODE_MS_GPIO | MPC52xx_GPT_MODE_COUNTER_ENABLE;
+        if (as_wdt) {
+                clear |= MPC52xx_GPT_MODE_IRQ_EN;
+                set |= MPC52xx_GPT_MODE_WDT_EN;
+        } else if (continuous)
+                set |= MPC52xx_GPT_MODE_CONTINUOUS;
+
+        /* Determine the number of clocks in the requested period.  64 bit
+         * arithmatic is done here to preserve the precision until the value
+         * is scaled back down into the u32 range.  Period is in 'ns', bus
+         * frequency is in Hz. */
+        clocks = period * (u64)gpt->ipb_freq;
+        do_div(clocks, 1000000000); /* Scale it down to ns range */
+
+        /* This device cannot handle a clock count greater than 32 bits */
+        if (clocks > 0xffffffff)
+                return -EINVAL;
+
+        /* Calculate the prescaler and count values from the clocks value.
+         * 'clocks' is the number of clock ticks in the period.  The timer
+         * has 16 bit precision and a 16 bit prescaler.  Prescaler is
+         * calculated by integer dividing the clocks by 0x10000 (shifting
+         * down 16 bits) to obtain the smallest possible divisor for clocks
+         * to get a 16 bit count value.
+         *
+         * Note: the prescale register is '1' based, not '0' based.  ie. a
+         * value of '1' means divide the clock by one.  0xffff divides the
+         * clock by 0xffff.  '0x0000' does not divide by zero, but wraps
+         * around and divides by 0x10000.  That is why prescale must be
+         * a u32 variable, not a u16, for this calculation. */
+        prescale = (clocks >> 16) + 1;
+        do_div(clocks, prescale);
+        if (clocks > 0xffff) {
+                pr_err("calculation error; prescale:%x clocks:%llx\n",
+                       prescale, clocks);
+                return -EINVAL;
+        }
+
+        /* Set and enable the timer, reject an attempt to use a wdt as gpt */
+        spin_lock_irqsave(&gpt->lock, flags);
+        if (as_wdt)
+                gpt->wdt_mode |= MPC52xx_GPT_IS_WDT;
+        else if ((gpt->wdt_mode & MPC52xx_GPT_IS_WDT) != 0) {
+                spin_unlock_irqrestore(&gpt->lock, flags);
+                return -EBUSY;
+        }
+        out_be32(&gpt->regs->count, prescale << 16 | clocks);
+        clrsetbits_be32(&gpt->regs->mode, clear, set);
+        spin_unlock_irqrestore(&gpt->lock, flags);
+
+        return 0;
+}
+
+/**
+ * mpc52xx_gpt_start_timer - Set and enable the GPT timer
+ * @gpt: Pointer to gpt private data structure
+ * @period: period of timer in ns; max. ~130s @ 33MHz IPB clock
+ * @continuous: set to 1 to make timer continuous free running
+ *
+ * An interrupt will be generated every time the timer fires
+ */
+int mpc52xx_gpt_start_timer(struct mpc52xx_gpt_priv *gpt, u64 period,
+                            int continuous)
+{
+        return mpc52xx_gpt_do_start(gpt, period, continuous, 0);
+}
+EXPORT_SYMBOL(mpc52xx_gpt_start_timer);
+
+/**
+ * mpc52xx_gpt_stop_timer - Stop a gpt
+ * @gpt: Pointer to gpt private data structure
+ *
+ * Returns an error if attempting to stop a wdt
+ */
+int mpc52xx_gpt_stop_timer(struct mpc52xx_gpt_priv *gpt)
+{
+        unsigned long flags;
+
+        /* reject the operation if the timer is used as watchdog (gpt 0 only) */
+        spin_lock_irqsave(&gpt->lock, flags);
+        if ((gpt->wdt_mode & MPC52xx_GPT_IS_WDT) != 0) {
+                spin_unlock_irqrestore(&gpt->lock, flags);
+                return -EBUSY;
+        }
+
+        clrbits32(&gpt->regs->mode, MPC52xx_GPT_MODE_COUNTER_ENABLE);
+        spin_unlock_irqrestore(&gpt->lock, flags);
+        return 0;
+}
+EXPORT_SYMBOL(mpc52xx_gpt_stop_timer);
+
+/**
+ * mpc52xx_gpt_timer_period - Read the timer period
+ * @gpt: Pointer to gpt private data structure
+ *
+ * Returns the timer period in ns
+ */
+u64 mpc52xx_gpt_timer_period(struct mpc52xx_gpt_priv *gpt)
+{
+        u64 period;
+        u64 prescale;
+        unsigned long flags;
+
+        spin_lock_irqsave(&gpt->lock, flags);
+        period = in_be32(&gpt->regs->count);
+        spin_unlock_irqrestore(&gpt->lock, flags);
+
+        prescale = period >> 16;
+        period &= 0xffff;
+        if (prescale == 0)
+                prescale = 0x10000;
+        period = period * prescale * 1000000000ULL;
+        do_div(period, (u64)gpt->ipb_freq);
+        return period;
+}
+EXPORT_SYMBOL(mpc52xx_gpt_timer_period);
+
+#if defined(CONFIG_MPC5200_WDT)
+/***********************************************************************
+ * Watchdog API for gpt0
+ */
+
+#define WDT_IDENTITY        "mpc52xx watchdog on GPT0"
+
+/* wdt_is_active stores wether or not the /dev/watchdog device is opened */
+static unsigned long wdt_is_active;
+
+/* wdt-capable gpt */
+static struct mpc52xx_gpt_priv *mpc52xx_gpt_wdt;
+
+/* low-level wdt functions */
+static inline void mpc52xx_gpt_wdt_ping(struct mpc52xx_gpt_priv *gpt_wdt)
+{
+        unsigned long flags;
+
+        spin_lock_irqsave(&gpt_wdt->lock, flags);
+        out_8((u8 *) &gpt_wdt->regs->mode, MPC52xx_GPT_MODE_WDT_PING);
+        spin_unlock_irqrestore(&gpt_wdt->lock, flags);
+}
+
+/* wdt misc device api */
+static ssize_t mpc52xx_wdt_write(struct file *file, const char __user *data,
+                                 size_t len, loff_t *ppos)
+{
+        struct mpc52xx_gpt_priv *gpt_wdt = file->private_data;
+        mpc52xx_gpt_wdt_ping(gpt_wdt);
+        return 0;
+}
+
+static struct watchdog_info mpc5200_wdt_info = {
+        .options        = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING,
+        .identity       = WDT_IDENTITY,
+};
+
+static long mpc52xx_wdt_ioctl(struct file *file, unsigned int cmd,
+                              unsigned long arg)
+{
+        struct mpc52xx_gpt_priv *gpt_wdt = file->private_data;
+        int __user *data = (int __user *)arg;
+        int timeout;
+        u64 real_timeout;
+        int ret = 0;
+
+        switch (cmd) {
+        case WDIOC_GETSUPPORT:
+                ret = copy_to_user(data, &mpc5200_wdt_info,
+                                   sizeof(mpc5200_wdt_info));
+                if (ret)
+                        ret = -EFAULT;
+                break;
+
+        case WDIOC_GETSTATUS:
+        case WDIOC_GETBOOTSTATUS:
+                ret = put_user(0, data);
+                break;
+
+        case WDIOC_KEEPALIVE:
+                mpc52xx_gpt_wdt_ping(gpt_wdt);
+                break;
+
+        case WDIOC_SETTIMEOUT:
+                ret = get_user(timeout, data);
+                if (ret)
+                        break;
+                real_timeout = (u64) timeout * 1000000000ULL;
+                ret = mpc52xx_gpt_do_start(gpt_wdt, real_timeout, 0, 1);
+                if (ret)
+                        break;
+                /* fall through and return the timeout */
+
+        case WDIOC_GETTIMEOUT:
+                /* we need to round here as to avoid e.g. the following
+                 * situation:
+                 * - timeout requested is 1 second;
+                 * - real timeout @33MHz is 999997090ns
+                 * - the int divide by 10^9 will return 0.
+                 */
+                real_timeout =
+                        mpc52xx_gpt_timer_period(gpt_wdt) + 500000000ULL;
+                do_div(real_timeout, 1000000000ULL);
+                timeout = (int) real_timeout;
+                ret = put_user(timeout, data);
+                break;
+
+        default:
+                ret = -ENOTTY;
+        }
+        return ret;
+}
+
+static int mpc52xx_wdt_open(struct inode *inode, struct file *file)
+{
+        int ret;
+
+        /* sanity check */
+        if (!mpc52xx_gpt_wdt)
+                return -ENODEV;
+
+        /* /dev/watchdog can only be opened once */
+        if (test_and_set_bit(0, &wdt_is_active))
+                return -EBUSY;
+
+        /* Set and activate the watchdog with 30 seconds timeout */
+        ret = mpc52xx_gpt_do_start(mpc52xx_gpt_wdt, 30ULL * 1000000000ULL,
+                                   0, 1);
+        if (ret) {
+                clear_bit(0, &wdt_is_active);
+                return ret;
+        }
+
+        file->private_data = mpc52xx_gpt_wdt;
+        return nonseekable_open(inode, file);
+}
+
+static int mpc52xx_wdt_release(struct inode *inode, struct file *file)
+{
+        /* note: releasing the wdt in NOWAYOUT-mode does not stop it */
+#if !defined(CONFIG_WATCHDOG_NOWAYOUT)
+        struct mpc52xx_gpt_priv *gpt_wdt = file->private_data;
+        unsigned long flags;
+
+        spin_lock_irqsave(&gpt_wdt->lock, flags);
+        clrbits32(&gpt_wdt->regs->mode,
+                  MPC52xx_GPT_MODE_COUNTER_ENABLE | MPC52xx_GPT_MODE_WDT_EN);
+        gpt_wdt->wdt_mode &= ~MPC52xx_GPT_IS_WDT;
+        spin_unlock_irqrestore(&gpt_wdt->lock, flags);
+#endif
+        clear_bit(0, &wdt_is_active);
+        return 0;
+}
+
+
+static const struct file_operations mpc52xx_wdt_fops = {
+        .owner          = THIS_MODULE,
+        .llseek         = no_llseek,
+        .write          = mpc52xx_wdt_write,
+        .unlocked_ioctl = mpc52xx_wdt_ioctl,
+        .open           = mpc52xx_wdt_open,
+        .release        = mpc52xx_wdt_release,
+};
+
+static struct miscdevice mpc52xx_wdt_miscdev = {
+        .minor          = WATCHDOG_MINOR,
+        .name           = "watchdog",
+        .fops           = &mpc52xx_wdt_fops,
+};
+
+static int __devinit mpc52xx_gpt_wdt_init(void)
+{
+        int err;
+
+        /* try to register the watchdog misc device */
+        err = misc_register(&mpc52xx_wdt_miscdev);
+        if (err)
+                pr_err("%s: cannot register watchdog device\n", WDT_IDENTITY);
+        else
+                pr_info("%s: watchdog device registered\n", WDT_IDENTITY);
+        return err;
+}
+
+static int mpc52xx_gpt_wdt_setup(struct mpc52xx_gpt_priv *gpt,
+                                 const u32 *period)
+{
+        u64 real_timeout;
+
+        /* remember the gpt for the wdt operation */
+        mpc52xx_gpt_wdt = gpt;
+
+        /* configure the wdt if the device tree contained a timeout */
+        if (!period || *period == 0)
+                return 0;
+
+        real_timeout = (u64) *period * 1000000000ULL;
+        if (mpc52xx_gpt_do_start(gpt, real_timeout, 0, 1))
+                dev_warn(gpt->dev, "starting as wdt failed\n");
+        else
+                dev_info(gpt->dev, "watchdog set to %us timeout\n", *period);
+        return 0;
+}
+
+#else
+
+static int __devinit mpc52xx_gpt_wdt_init(void)
+{
+        return 0;
+}
+
+#define mpc52xx_gpt_wdt_setup(x, y)             (0)
+
+#endif  /*  CONFIG_MPC5200_WDT  */
+
 /* ---------------------------------------------------------------------
  * of_platform bus binding code
  */
@@ -349,6 +729,7 @@ static int __devinit mpc52xx_gpt_probe(struct of_device *ofdev,
 
         spin_lock_init(&gpt->lock);
         gpt->dev = &ofdev->dev;
+        gpt->ipb_freq = mpc5xxx_get_bus_frequency(ofdev->node);
         gpt->regs = of_iomap(ofdev->node, 0);
         if (!gpt->regs) {
                 kfree(gpt);
@@ -360,6 +741,26 @@ static int __devinit mpc52xx_gpt_probe(struct of_device *ofdev,
         mpc52xx_gpt_gpio_setup(gpt, ofdev->node);
         mpc52xx_gpt_irq_setup(gpt, ofdev->node);
 
+        mutex_lock(&mpc52xx_gpt_list_mutex);
+        list_add(&gpt->list, &mpc52xx_gpt_list);
+        mutex_unlock(&mpc52xx_gpt_list_mutex);
+
+        /* check if this device could be a watchdog */
+        if (of_get_property(ofdev->node, "fsl,has-wdt", NULL) ||
+            of_get_property(ofdev->node, "has-wdt", NULL)) {
+                const u32 *on_boot_wdt;
+
+                gpt->wdt_mode = MPC52xx_GPT_CAN_WDT;
+                on_boot_wdt = of_get_property(ofdev->node, "fsl,wdt-on-boot",
+                                              NULL);
+                if (on_boot_wdt) {
+                        dev_info(gpt->dev, "used as watchdog\n");
+                        gpt->wdt_mode |= MPC52xx_GPT_IS_WDT;
+                } else
+                        dev_info(gpt->dev, "can function as watchdog\n");
+                mpc52xx_gpt_wdt_setup(gpt, on_boot_wdt);
+        }
+
         return 0;
 }
 
@@ -394,3 +795,4 @@ static int __init mpc52xx_gpt_init(void)
 
 /* Make sure GPIOs and IRQs get set up before anyone tries to use them */
 subsys_initcall(mpc52xx_gpt_init);
+device_initcall(mpc52xx_gpt_wdt_init);
diff --git a/arch/powerpc/platforms/52xx/mpc52xx_lpbfifo.c b/arch/powerpc/platforms/52xx/mpc52xx_lpbfifo.c
new file mode 100644
index 000000000000..929d017535a3
--- /dev/null
+++ b/arch/powerpc/platforms/52xx/mpc52xx_lpbfifo.c
@@ -0,0 +1,560 @@
+/*
+ * LocalPlus Bus FIFO driver for the Freescale MPC52xx.
+ *
+ * Copyright (C) 2009 Secret Lab Technologies Ltd.
+ *
+ * This file is released under the GPLv2
+ *
+ * Todo:
+ * - Add support for multiple requests to be queued.
+ */
+
+#include <linux/interrupt.h>
+#include <linux/kernel.h>
+#include <linux/of.h>
+#include <linux/of_platform.h>
+#include <linux/spinlock.h>
+#include <asm/io.h>
+#include <asm/prom.h>
+#include <asm/mpc52xx.h>
+#include <asm/time.h>
+
+#include <sysdev/bestcomm/bestcomm.h>
+#include <sysdev/bestcomm/bestcomm_priv.h>
+#include <sysdev/bestcomm/gen_bd.h>
+
+MODULE_AUTHOR("Grant Likely <grant.likely@secretlab.ca>");
+MODULE_DESCRIPTION("MPC5200 LocalPlus FIFO device driver");
+MODULE_LICENSE("GPL");
+
+#define LPBFIFO_REG_PACKET_SIZE         (0x00)
+#define LPBFIFO_REG_START_ADDRESS       (0x04)
+#define LPBFIFO_REG_CONTROL             (0x08)
+#define LPBFIFO_REG_ENABLE              (0x0C)
+#define LPBFIFO_REG_BYTES_DONE_STATUS   (0x14)
+#define LPBFIFO_REG_FIFO_DATA           (0x40)
+#define LPBFIFO_REG_FIFO_STATUS         (0x44)
+#define LPBFIFO_REG_FIFO_CONTROL        (0x48)
+#define LPBFIFO_REG_FIFO_ALARM          (0x4C)
+
+struct mpc52xx_lpbfifo {
+        struct device *dev;
+        phys_addr_t regs_phys;
+        void __iomem *regs;
+        int irq;
+        spinlock_t lock;
+
+        struct bcom_task *bcom_tx_task;
+        struct bcom_task *bcom_rx_task;
+        struct bcom_task *bcom_cur_task;
+
+        /* Current state data */
+        struct mpc52xx_lpbfifo_request *req;
+        int dma_irqs_enabled;
+};
+
+/* The MPC5200 has only one fifo, so only need one instance structure */
+static struct mpc52xx_lpbfifo lpbfifo;
+
+/**
+ * mpc52xx_lpbfifo_kick - Trigger the next block of data to be transfered
+ */
+static void mpc52xx_lpbfifo_kick(struct mpc52xx_lpbfifo_request *req)
+{
+        size_t transfer_size = req->size - req->pos;
+        struct bcom_bd *bd;
+        void __iomem *reg;
+        u32 *data;
+        int i;
+        int bit_fields;
+        int dma = !(req->flags & MPC52XX_LPBFIFO_FLAG_NO_DMA);
+        int write = req->flags & MPC52XX_LPBFIFO_FLAG_WRITE;
+        int poll_dma = req->flags & MPC52XX_LPBFIFO_FLAG_POLL_DMA;
+
+        /* Set and clear the reset bits; is good practice in User Manual */
+        out_be32(lpbfifo.regs + LPBFIFO_REG_ENABLE, 0x01010000);
+
+        /* set master enable bit */
+        out_be32(lpbfifo.regs + LPBFIFO_REG_ENABLE, 0x00000001);
+        if (!dma) {
+                /* While the FIFO can be setup for transfer sizes as large as
+                 * 16M-1, the FIFO itself is only 512 bytes deep and it does
+                 * not generate interrupts for FIFO full events (only transfer
+                 * complete will raise an IRQ).  Therefore when not using
+                 * Bestcomm to drive the FIFO it needs to either be polled, or
+                 * transfers need to constrained to the size of the fifo.
+                 *
+                 * This driver restricts the size of the transfer
+                 */
+                if (transfer_size > 512)
+                        transfer_size = 512;
+
+                /* Load the FIFO with data */
+                if (write) {
+                        reg = lpbfifo.regs + LPBFIFO_REG_FIFO_DATA;
+                        data = req->data + req->pos;
+                        for (i = 0; i < transfer_size; i += 4)
+                                out_be32(reg, *data++);
+                }
+
+                /* Unmask both error and completion irqs */
+                out_be32(lpbfifo.regs + LPBFIFO_REG_ENABLE, 0x00000301);
+        } else {
+                /* Choose the correct direction
+                 *
+                 * Configure the watermarks so DMA will always complete correctly.
+                 * It may be worth experimenting with the ALARM value to see if
+                 * there is a performance impacit.  However, if it is wrong there
+                 * is a risk of DMA not transferring the last chunk of data
+                 */
+                if (write) {
+                        out_be32(lpbfifo.regs + LPBFIFO_REG_FIFO_ALARM, 0x1e4);
+                        out_8(lpbfifo.regs + LPBFIFO_REG_FIFO_CONTROL, 7);
+                        lpbfifo.bcom_cur_task = lpbfifo.bcom_tx_task;
+                } else {
+                        out_be32(lpbfifo.regs + LPBFIFO_REG_FIFO_ALARM, 0x1ff);
+                        out_8(lpbfifo.regs + LPBFIFO_REG_FIFO_CONTROL, 0);
+                        lpbfifo.bcom_cur_task = lpbfifo.bcom_rx_task;
+
+                        if (poll_dma) {
+                                if (lpbfifo.dma_irqs_enabled) {
+                                        disable_irq(bcom_get_task_irq(lpbfifo.bcom_rx_task));
+                                        lpbfifo.dma_irqs_enabled = 0;
+                                }
+                        } else {
+                                if (!lpbfifo.dma_irqs_enabled) {
+                                        enable_irq(bcom_get_task_irq(lpbfifo.bcom_rx_task));
+                                        lpbfifo.dma_irqs_enabled = 1;
+                                }
+                        }
+                }
+
+                bd = bcom_prepare_next_buffer(lpbfifo.bcom_cur_task);
+                bd->status = transfer_size;
+                if (!write) {
+                        /*
+                         * In the DMA read case, the DMA doesn't complete,
+                         * possibly due to incorrect watermarks in the ALARM
+                         * and CONTROL regs. For now instead of trying to
+                         * determine the right watermarks that will make this
+                         * work, just increase the number of bytes the FIFO is
+                         * expecting.
+                         *
+                         * When submitting another operation, the FIFO will get
+                         * reset, so the condition of the FIFO waiting for a
+                         * non-existent 4 bytes will get cleared.
+                         */
+                        transfer_size += 4; /* BLECH! */
+                }
+                bd->data[0] = req->data_phys + req->pos;
+                bcom_submit_next_buffer(lpbfifo.bcom_cur_task, NULL);
+
+                /* error irq & master enabled bit */
+                bit_fields = 0x00000201;
+
+                /* Unmask irqs */
+                if (write && (!poll_dma))
+                        bit_fields |= 0x00000100; /* completion irq too */
+                out_be32(lpbfifo.regs + LPBFIFO_REG_ENABLE, bit_fields);
+        }
+
+        /* Set transfer size, width, chip select and READ mode */
+        out_be32(lpbfifo.regs + LPBFIFO_REG_START_ADDRESS,
+                 req->offset + req->pos);
+        out_be32(lpbfifo.regs + LPBFIFO_REG_PACKET_SIZE, transfer_size);
+
+        bit_fields = req->cs << 24 | 0x000008;
+        if (!write)
+                bit_fields |= 0x010000; /* read mode */
+        out_be32(lpbfifo.regs + LPBFIFO_REG_CONTROL, bit_fields);
+
+        /* Kick it off */
+        out_8(lpbfifo.regs + LPBFIFO_REG_PACKET_SIZE, 0x01);
+        if (dma)
+                bcom_enable(lpbfifo.bcom_cur_task);
+}
+
+/**
+ * mpc52xx_lpbfifo_irq - IRQ handler for LPB FIFO
+ *
+ * On transmit, the dma completion irq triggers before the fifo completion
+ * triggers.  Handle the dma completion here instead of the LPB FIFO Bestcomm
+ * task completion irq becuase everyting is not really done until the LPB FIFO
+ * completion irq triggers.
+ *
+ * In other words:
+ * For DMA, on receive, the "Fat Lady" is the bestcom completion irq. on
+ * transmit, the fifo completion irq is the "Fat Lady". The opera (or in this
+ * case the DMA/FIFO operation) is not finished until the "Fat Lady" sings.
+ *
+ * Reasons for entering this routine:
+ * 1) PIO mode rx and tx completion irq
+ * 2) DMA interrupt mode tx completion irq
+ * 3) DMA polled mode tx
+ *
+ * Exit conditions:
+ * 1) Transfer aborted
+ * 2) FIFO complete without DMA; more data to do
+ * 3) FIFO complete without DMA; all data transfered
+ * 4) FIFO complete using DMA
+ *
+ * Condition 1 can occur regardless of whether or not DMA is used.
+ * It requires executing the callback to report the error and exiting
+ * immediately.
+ *
+ * Condition 2 requires programming the FIFO with the next block of data
+ *
+ * Condition 3 requires executing the callback to report completion
+ *
+ * Condition 4 means the same as 3, except that we also retrieve the bcom
+ * buffer so DMA doesn't get clogged up.
+ *
+ * To make things trickier, the spinlock must be dropped before
+ * executing the callback, otherwise we could end up with a deadlock
+ * or nested spinlock condition.  The out path is non-trivial, so
+ * extra fiddling is done to make sure all paths lead to the same
+ * outbound code.
+ */
+static irqreturn_t mpc52xx_lpbfifo_irq(int irq, void *dev_id)
+{
+        struct mpc52xx_lpbfifo_request *req;
+        u32 status = in_8(lpbfifo.regs + LPBFIFO_REG_BYTES_DONE_STATUS);
+        void __iomem *reg;
+        u32 *data;
+        int count, i;
+        int do_callback = 0;
+        u32 ts;
+        unsigned long flags;
+        int dma, write, poll_dma;
+
+        spin_lock_irqsave(&lpbfifo.lock, flags);
+        ts = get_tbl();
+
+        req = lpbfifo.req;
+        if (!req) {
+                spin_unlock_irqrestore(&lpbfifo.lock, flags);
+                pr_err("bogus LPBFIFO IRQ\n");
+                return IRQ_HANDLED;
+        }
+
+        dma = !(req->flags & MPC52XX_LPBFIFO_FLAG_NO_DMA);
+        write = req->flags & MPC52XX_LPBFIFO_FLAG_WRITE;
+        poll_dma = req->flags & MPC52XX_LPBFIFO_FLAG_POLL_DMA;
+
+        if (dma && !write) {
+                spin_unlock_irqrestore(&lpbfifo.lock, flags);
+                pr_err("bogus LPBFIFO IRQ (dma and not writting)\n");
+                return IRQ_HANDLED;
+        }
+
+        if ((status & 0x01) == 0) {
+                goto out;
+        }
+
+        /* check abort bit */
+        if (status & 0x10) {
+                out_be32(lpbfifo.regs + LPBFIFO_REG_ENABLE, 0x01010000);
+                do_callback = 1;
+                goto out;
+        }
+
+        /* Read result from hardware */
+        count = in_be32(lpbfifo.regs + LPBFIFO_REG_BYTES_DONE_STATUS);
+        count &= 0x00ffffff;
+
+        if (!dma && !write) {
+                /* copy the data out of the FIFO */
+                reg = lpbfifo.regs + LPBFIFO_REG_FIFO_DATA;
+                data = req->data + req->pos;
+                for (i = 0; i < count; i += 4)
+                        *data++ = in_be32(reg);
+        }
+
+        /* Update transfer position and count */
+        req->pos += count;
+
+        /* Decide what to do next */
+        if (req->size - req->pos)
+                mpc52xx_lpbfifo_kick(req); /* more work to do */
+        else
+                do_callback = 1;
+
+ out:
+        /* Clear the IRQ */
+        out_8(lpbfifo.regs + LPBFIFO_REG_BYTES_DONE_STATUS, 0x01);
+
+        if (dma && (status & 0x11)) {
+                /*
+                 * Count the DMA as complete only when the FIFO completion
+                 * status or abort bits are set.
+                 *
+                 * (status & 0x01) should always be the case except sometimes
+                 * when using polled DMA.
+                 *
+                 * (status & 0x10) {transfer aborted}: This case needs more
+                 * testing.
+                 */
+                bcom_retrieve_buffer(lpbfifo.bcom_cur_task, &status, NULL);
+        }
+        req->last_byte = ((u8 *)req->data)[req->size - 1];
+
+        /* When the do_callback flag is set; it means the transfer is finished
+         * so set the FIFO as idle */
+        if (do_callback)
+                lpbfifo.req = NULL;
+
+        if (irq != 0) /* don't increment on polled case */
+                req->irq_count++;
+
+        req->irq_ticks += get_tbl() - ts;
+        spin_unlock_irqrestore(&lpbfifo.lock, flags);
+
+        /* Spinlock is released; it is now safe to call the callback */
+        if (do_callback && req->callback)
+                req->callback(req);
+
+        return IRQ_HANDLED;
+}
+
+/**
+ * mpc52xx_lpbfifo_bcom_irq - IRQ handler for LPB FIFO Bestcomm task
+ *
+ * Only used when receiving data.
+ */
+static irqreturn_t mpc52xx_lpbfifo_bcom_irq(int irq, void *dev_id)
+{
+        struct mpc52xx_lpbfifo_request *req;
+        unsigned long flags;
+        u32 status;
+        u32 ts;
+
+        spin_lock_irqsave(&lpbfifo.lock, flags);
+        ts = get_tbl();
+
+        req = lpbfifo.req;
+        if (!req || (req->flags & MPC52XX_LPBFIFO_FLAG_NO_DMA)) {
+                spin_unlock_irqrestore(&lpbfifo.lock, flags);
+                return IRQ_HANDLED;
+        }
+
+        if (irq != 0) /* don't increment on polled case */
+                req->irq_count++;
+
+        if (!bcom_buffer_done(lpbfifo.bcom_cur_task)) {
+                spin_unlock_irqrestore(&lpbfifo.lock, flags);
+
+                req->buffer_not_done_cnt++;
+                if ((req->buffer_not_done_cnt % 1000) == 0)
+                        pr_err("transfer stalled\n");
+
+                return IRQ_HANDLED;
+        }
+
+        bcom_retrieve_buffer(lpbfifo.bcom_cur_task, &status, NULL);
+
+        req->last_byte = ((u8 *)req->data)[req->size - 1];
+
+        req->pos = status & 0x00ffffff;
+
+        /* Mark the FIFO as idle */
+        lpbfifo.req = NULL;
+
+        /* Release the lock before calling out to the callback. */
+        req->irq_ticks += get_tbl() - ts;
+        spin_unlock_irqrestore(&lpbfifo.lock, flags);
+
+        if (req->callback)
+                req->callback(req);
+
+        return IRQ_HANDLED;
+}
+
+/**
+ * mpc52xx_lpbfifo_bcom_poll - Poll for DMA completion
+ */
+void mpc52xx_lpbfifo_poll(void)
+{
+        struct mpc52xx_lpbfifo_request *req = lpbfifo.req;
+        int dma = !(req->flags & MPC52XX_LPBFIFO_FLAG_NO_DMA);
+        int write = req->flags & MPC52XX_LPBFIFO_FLAG_WRITE;
+
+        /*
+         * For more information, see comments on the "Fat Lady" 
+         */
+        if (dma && write)
+                mpc52xx_lpbfifo_irq(0, NULL);
+        else 
+                mpc52xx_lpbfifo_bcom_irq(0, NULL);
+}
+EXPORT_SYMBOL(mpc52xx_lpbfifo_poll);
+
+/**
+ * mpc52xx_lpbfifo_submit - Submit an LPB FIFO transfer request.
+ * @req: Pointer to request structure
+ */
+int mpc52xx_lpbfifo_submit(struct mpc52xx_lpbfifo_request *req)
+{
+        unsigned long flags;
+
+        if (!lpbfifo.regs)
+                return -ENODEV;
+
+        spin_lock_irqsave(&lpbfifo.lock, flags);
+
+        /* If the req pointer is already set, then a transfer is in progress */
+        if (lpbfifo.req) {
+                spin_unlock_irqrestore(&lpbfifo.lock, flags);
+                return -EBUSY;
+        }
+
+        /* Setup the transfer */
+        lpbfifo.req = req;
+        req->irq_count = 0;
+        req->irq_ticks = 0;
+        req->buffer_not_done_cnt = 0;
+        req->pos = 0;
+
+        mpc52xx_lpbfifo_kick(req);
+        spin_unlock_irqrestore(&lpbfifo.lock, flags);
+        return 0;
+}
+EXPORT_SYMBOL(mpc52xx_lpbfifo_submit);
+
+void mpc52xx_lpbfifo_abort(struct mpc52xx_lpbfifo_request *req)
+{
+        unsigned long flags;
+
+        spin_lock_irqsave(&lpbfifo.lock, flags);
+        if (lpbfifo.req == req) {
+                /* Put it into reset and clear the state */
+                bcom_gen_bd_rx_reset(lpbfifo.bcom_rx_task);
+                bcom_gen_bd_tx_reset(lpbfifo.bcom_tx_task);
+                out_be32(lpbfifo.regs + LPBFIFO_REG_ENABLE, 0x01010000);
+                lpbfifo.req = NULL;
+        }
+        spin_unlock_irqrestore(&lpbfifo.lock, flags);
+}
+EXPORT_SYMBOL(mpc52xx_lpbfifo_abort);
+
+static int __devinit
+mpc52xx_lpbfifo_probe(struct of_device *op, const struct of_device_id *match)
+{
+        struct resource res;
+        int rc = -ENOMEM;
+
+        if (lpbfifo.dev != NULL)
+                return -ENOSPC;
+
+        lpbfifo.irq = irq_of_parse_and_map(op->node, 0);
+        if (!lpbfifo.irq)
+                return -ENODEV;
+
+        if (of_address_to_resource(op->node, 0, &res))
+                return -ENODEV;
+        lpbfifo.regs_phys = res.start;
+        lpbfifo.regs = of_iomap(op->node, 0);
+        if (!lpbfifo.regs)
+                return -ENOMEM;
+
+        spin_lock_init(&lpbfifo.lock);
+
+        /* Put FIFO into reset */
+        out_be32(lpbfifo.regs + LPBFIFO_REG_ENABLE, 0x01010000);
+
+        /* Register the interrupt handler */
+        rc = request_irq(lpbfifo.irq, mpc52xx_lpbfifo_irq, 0,
+                         "mpc52xx-lpbfifo", &lpbfifo);
+        if (rc)
+                goto err_irq;
+
+        /* Request the Bestcomm receive (fifo --> memory) task and IRQ */
+        lpbfifo.bcom_rx_task =
+                bcom_gen_bd_rx_init(2, res.start + LPBFIFO_REG_FIFO_DATA,
+                                    BCOM_INITIATOR_SCLPC, BCOM_IPR_SCLPC,
+                                    16*1024*1024);
+        if (!lpbfifo.bcom_rx_task)
+                goto err_bcom_rx;
+
+        rc = request_irq(bcom_get_task_irq(lpbfifo.bcom_rx_task),
+                         mpc52xx_lpbfifo_bcom_irq, 0,
+                         "mpc52xx-lpbfifo-rx", &lpbfifo);
+        if (rc)
+                goto err_bcom_rx_irq;
+
+        /* Request the Bestcomm transmit (memory --> fifo) task and IRQ */
+        lpbfifo.bcom_tx_task =
+                bcom_gen_bd_tx_init(2, res.start + LPBFIFO_REG_FIFO_DATA,
+                                    BCOM_INITIATOR_SCLPC, BCOM_IPR_SCLPC);
+        if (!lpbfifo.bcom_tx_task)
+                goto err_bcom_tx;
+
+        lpbfifo.dev = &op->dev;
+        return 0;
+
+ err_bcom_tx:
+        free_irq(bcom_get_task_irq(lpbfifo.bcom_rx_task), &lpbfifo);
+ err_bcom_rx_irq:
+        bcom_gen_bd_rx_release(lpbfifo.bcom_rx_task);
+ err_bcom_rx:
+ err_irq:
+        iounmap(lpbfifo.regs);
+        lpbfifo.regs = NULL;
+
+        dev_err(&op->dev, "mpc52xx_lpbfifo_probe() failed\n");
+        return -ENODEV;
+}
+
+
+static int __devexit mpc52xx_lpbfifo_remove(struct of_device *op)
+{
+        if (lpbfifo.dev != &op->dev)
+                return 0;
+
+        /* Put FIFO in reset */
+        out_be32(lpbfifo.regs + LPBFIFO_REG_ENABLE, 0x01010000);
+
+        /* Release the bestcomm transmit task */
+        free_irq(bcom_get_task_irq(lpbfifo.bcom_tx_task), &lpbfifo);
+        bcom_gen_bd_tx_release(lpbfifo.bcom_tx_task);
+        
+        /* Release the bestcomm receive task */
+        free_irq(bcom_get_task_irq(lpbfifo.bcom_rx_task), &lpbfifo);
+        bcom_gen_bd_rx_release(lpbfifo.bcom_rx_task);
+
+        free_irq(lpbfifo.irq, &lpbfifo);
+        iounmap(lpbfifo.regs);
+        lpbfifo.regs = NULL;
+        lpbfifo.dev = NULL;
+
+        return 0;
+}
+
+static struct of_device_id mpc52xx_lpbfifo_match[] __devinitconst = {
+        { .compatible = "fsl,mpc5200-lpbfifo", },
+        {},
+};
+
+static struct of_platform_driver mpc52xx_lpbfifo_driver = {
+        .owner = THIS_MODULE,
+        .name = "mpc52xx-lpbfifo",
+        .match_table = mpc52xx_lpbfifo_match,
+        .probe = mpc52xx_lpbfifo_probe,
+        .remove = __devexit_p(mpc52xx_lpbfifo_remove),
+};
+
+/***********************************************************************
+ * Module init/exit
+ */
+static int __init mpc52xx_lpbfifo_init(void)
+{
+        pr_debug("Registering LocalPlus bus FIFO driver\n");
+        return of_register_platform_driver(&mpc52xx_lpbfifo_driver);
+}
+module_init(mpc52xx_lpbfifo_init);
+
+static void __exit mpc52xx_lpbfifo_exit(void)
+{
+        pr_debug("Unregistering LocalPlus bus FIFO driver\n");
+        of_unregister_platform_driver(&mpc52xx_lpbfifo_driver);
+}
+module_exit(mpc52xx_lpbfifo_exit);
diff --git a/arch/powerpc/platforms/52xx/mpc52xx_pic.c b/arch/powerpc/platforms/52xx/mpc52xx_pic.c
index 480f806fd0a9..4bf4bf7b063e 100644
--- a/arch/powerpc/platforms/52xx/mpc52xx_pic.c
+++ b/arch/powerpc/platforms/52xx/mpc52xx_pic.c
@@ -220,7 +220,7 @@ static int mpc52xx_extirq_set_type(unsigned int virq, unsigned int flow_type)
 }
 
 static struct irq_chip mpc52xx_extirq_irqchip = {
-        .typename = "MPC52xx External",
+        .name = "MPC52xx External",
         .mask = mpc52xx_extirq_mask,
         .unmask = mpc52xx_extirq_unmask,
         .ack = mpc52xx_extirq_ack,
@@ -258,7 +258,7 @@ static void mpc52xx_main_unmask(unsigned int virq)
 }
 
 static struct irq_chip mpc52xx_main_irqchip = {
-        .typename = "MPC52xx Main",
+        .name = "MPC52xx Main",
         .mask = mpc52xx_main_mask,
         .mask_ack = mpc52xx_main_mask,
         .unmask = mpc52xx_main_unmask,
@@ -291,7 +291,7 @@ static void mpc52xx_periph_unmask(unsigned int virq)
 }
 
 static struct irq_chip mpc52xx_periph_irqchip = {
-        .typename = "MPC52xx Peripherals",
+        .name = "MPC52xx Peripherals",
         .mask = mpc52xx_periph_mask,
         .mask_ack = mpc52xx_periph_mask,
         .unmask = mpc52xx_periph_unmask,
@@ -335,7 +335,7 @@ static void mpc52xx_sdma_ack(unsigned int virq)
 }
 
 static struct irq_chip mpc52xx_sdma_irqchip = {
-        .typename = "MPC52xx SDMA",
+        .name = "MPC52xx SDMA",
         .mask = mpc52xx_sdma_mask,
         .unmask = mpc52xx_sdma_unmask,
         .ack = mpc52xx_sdma_ack,
@@ -355,7 +355,7 @@ static int mpc52xx_is_extirq(int l1, int l2)
  * mpc52xx_irqhost_xlate - translate virq# from device tree interrupts property
  */
 static int mpc52xx_irqhost_xlate(struct irq_host *h, struct device_node *ct,
-                                 u32 *intspec, unsigned int intsize,
+                                 const u32 *intspec, unsigned int intsize,
                                  irq_hw_number_t *out_hwirq,
                                  unsigned int *out_flags)
 {
diff --git a/arch/powerpc/platforms/82xx/pq2ads-pci-pic.c b/arch/powerpc/platforms/82xx/pq2ads-pci-pic.c
index 7ee979f323d1..9d962d7c72c1 100644
--- a/arch/powerpc/platforms/82xx/pq2ads-pci-pic.c
+++ b/arch/powerpc/platforms/82xx/pq2ads-pci-pic.c
@@ -69,7 +69,6 @@ static void pq2ads_pci_unmask_irq(unsigned int virq)
 }
 
 static struct irq_chip pq2ads_pci_ic = {
-        .typename = "PQ2 ADS PCI",
         .name = "PQ2 ADS PCI",
         .end = pq2ads_pci_unmask_irq,
         .mask = pq2ads_pci_mask_irq,
@@ -107,7 +106,7 @@ static void pq2ads_pci_irq_demux(unsigned int irq, struct irq_desc *desc)
 static int pci_pic_host_map(struct irq_host *h, unsigned int virq,
                             irq_hw_number_t hw)
 {
-        get_irq_desc(virq)->status |= IRQ_LEVEL;
+        irq_to_desc(virq)->status |= IRQ_LEVEL;
         set_irq_chip_data(virq, h->host_data);
         set_irq_chip_and_handler(virq, &pq2ads_pci_ic, handle_level_irq);
         return 0;
diff --git a/arch/powerpc/platforms/83xx/mpc832x_rdb.c b/arch/powerpc/platforms/83xx/mpc832x_rdb.c
index 567ded7c3b9b..17f99745f0e4 100644
--- a/arch/powerpc/platforms/83xx/mpc832x_rdb.c
+++ b/arch/powerpc/platforms/83xx/mpc832x_rdb.c
@@ -74,7 +74,7 @@ static int __init of_fsl_spi_probe(char *type, char *compatible, u32 sysclk,
 
                 prop = of_get_property(np, "mode", NULL);
                 if (prop && !strcmp(prop, "cpu-qe"))
-                        pdata.qe_mode = 1;
+                        pdata.flags = SPI_QE_CPU_MODE;
 
                 for (j = 0; j < num_board_infos; j++) {
                         if (board_infos[j].bus_num == pdata.bus_num)
diff --git a/arch/powerpc/platforms/83xx/suspend.c b/arch/powerpc/platforms/83xx/suspend.c
index 08e65fc8b98c..d306f07b9aa1 100644
--- a/arch/powerpc/platforms/83xx/suspend.c
+++ b/arch/powerpc/platforms/83xx/suspend.c
@@ -96,6 +96,7 @@ int fsl_deep_sleep(void)
 {
         return deep_sleeping;
 }
+EXPORT_SYMBOL(fsl_deep_sleep);
 
 static int mpc83xx_change_state(void)
 {
diff --git a/arch/powerpc/platforms/85xx/Kconfig b/arch/powerpc/platforms/85xx/Kconfig
index d3a975e8fd3e..d95121894eb7 100644
--- a/arch/powerpc/platforms/85xx/Kconfig
+++ b/arch/powerpc/platforms/85xx/Kconfig
@@ -1,6 +1,7 @@
-menuconfig MPC85xx
-        bool "Machine Type"
-        depends on PPC_85xx
+menuconfig FSL_SOC_BOOKE
+        bool "Freescale Book-E Machine Type"
+        depends on PPC_85xx || PPC_BOOK3E
+        select FSL_SOC
         select PPC_UDBG_16550
         select MPIC
         select PPC_PCI_CHOICE
@@ -8,7 +9,7 @@ menuconfig MPC85xx
         select SERIAL_8250_SHARE_IRQ if SERIAL_8250
         default y
 
-if MPC85xx
+if FSL_SOC_BOOKE
 
 config MPC8540_ADS
         bool "Freescale MPC8540 ADS"
@@ -144,7 +145,19 @@ config SBC8560
         help
           This option enables support for the Wind River SBC8560 board
 
-endif # MPC85xx
+config P4080_DS
+        bool "Freescale P4080 DS"
+        select DEFAULT_UIMAGE
+        select PPC_FSL_BOOK3E
+        select PPC_E500MC
+        select PHYS_64BIT
+        select SWIOTLB
+        select MPC8xxx_GPIO
+        select HAS_RAPIDIO
+        help
+          This option enables support for the P4080 DS board
+
+endif # FSL_SOC_BOOKE
 
 config TQM85xx
         bool
diff --git a/arch/powerpc/platforms/85xx/Makefile b/arch/powerpc/platforms/85xx/Makefile
index 9098aea0cf32..387c128f2c8c 100644
--- a/arch/powerpc/platforms/85xx/Makefile
+++ b/arch/powerpc/platforms/85xx/Makefile
@@ -10,6 +10,7 @@ obj-$(CONFIG_MPC8536_DS)  += mpc8536_ds.o
 obj-$(CONFIG_MPC85xx_DS)  += mpc85xx_ds.o
 obj-$(CONFIG_MPC85xx_MDS) += mpc85xx_mds.o
 obj-$(CONFIG_MPC85xx_RDB) += mpc85xx_rdb.o
+obj-$(CONFIG_P4080_DS)    += p4080_ds.o corenet_ds.o
 obj-$(CONFIG_STX_GP3)     += stx_gp3.o
 obj-$(CONFIG_TQM85xx)     += tqm85xx.o
 obj-$(CONFIG_SBC8560)     += sbc8560.o
diff --git a/arch/powerpc/platforms/85xx/corenet_ds.c b/arch/powerpc/platforms/85xx/corenet_ds.c
new file mode 100644
index 000000000000..534c2ecc89d9
--- /dev/null
+++ b/arch/powerpc/platforms/85xx/corenet_ds.c
@@ -0,0 +1,125 @@
+/*
+ * Corenet based SoC DS Setup
+ *
+ * Maintained by Kumar Gala (see MAINTAINERS for contact information)
+ *
+ * Copyright 2009 Freescale Semiconductor Inc.
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/kernel.h>
+#include <linux/pci.h>
+#include <linux/kdev_t.h>
+#include <linux/delay.h>
+#include <linux/interrupt.h>
+#include <linux/lmb.h>
+
+#include <asm/system.h>
+#include <asm/time.h>
+#include <asm/machdep.h>
+#include <asm/pci-bridge.h>
+#include <mm/mmu_decl.h>
+#include <asm/prom.h>
+#include <asm/udbg.h>
+#include <asm/mpic.h>
+
+#include <linux/of_platform.h>
+#include <sysdev/fsl_soc.h>
+#include <sysdev/fsl_pci.h>
+
+void __init corenet_ds_pic_init(void)
+{
+        struct mpic *mpic;
+        struct resource r;
+        struct device_node *np = NULL;
+        unsigned int flags = MPIC_PRIMARY | MPIC_BIG_ENDIAN |
+                                MPIC_BROKEN_FRR_NIRQS | MPIC_SINGLE_DEST_CPU;
+
+        np = of_find_node_by_type(np, "open-pic");
+
+        if (np == NULL) {
+                printk(KERN_ERR "Could not find open-pic node\n");
+                return;
+        }
+
+        if (of_address_to_resource(np, 0, &r)) {
+                printk(KERN_ERR "Failed to map mpic register space\n");
+                of_node_put(np);
+                return;
+        }
+
+        if (ppc_md.get_irq == mpic_get_coreint_irq)
+                flags |= MPIC_ENABLE_COREINT;
+
+        mpic = mpic_alloc(np, r.start, flags, 0, 256, " OpenPIC  ");
+        BUG_ON(mpic == NULL);
+
+        mpic_init(mpic);
+}
+
+#ifdef CONFIG_PCI
+static int primary_phb_addr;
+#endif
+
+/*
+ * Setup the architecture
+ */
+#ifdef CONFIG_SMP
+void __init mpc85xx_smp_init(void);
+#endif
+
+void __init corenet_ds_setup_arch(void)
+{
+#ifdef CONFIG_PCI
+        struct device_node *np;
+        struct pci_controller *hose;
+#endif
+        dma_addr_t max = 0xffffffff;
+
+#ifdef CONFIG_SMP
+        mpc85xx_smp_init();
+#endif
+
+#ifdef CONFIG_PCI
+        for_each_compatible_node(np, "pci", "fsl,p4080-pcie") {
+                struct resource rsrc;
+                of_address_to_resource(np, 0, &rsrc);
+                if ((rsrc.start & 0xfffff) == primary_phb_addr)
+                        fsl_add_bridge(np, 1);
+                else
+                        fsl_add_bridge(np, 0);
+
+                hose = pci_find_hose_for_OF_device(np);
+                max = min(max, hose->dma_window_base_cur +
+                                hose->dma_window_size);
+        }
+#endif
+
+#ifdef CONFIG_SWIOTLB
+        if (lmb_end_of_DRAM() > max) {
+                ppc_swiotlb_enable = 1;
+                set_pci_dma_ops(&swiotlb_dma_ops);
+                ppc_md.pci_dma_dev_setup = pci_dma_dev_setup_swiotlb;
+        }
+#endif
+        pr_info("%s board from Freescale Semiconductor\n", ppc_md.name);
+}
+
+static const struct of_device_id of_device_ids[] __devinitconst = {
+        {
+                .compatible     = "simple-bus"
+        },
+        {
+                .compatible     = "fsl,rapidio-delta",
+        },
+        {}
+};
+
+int __init corenet_ds_publish_devices(void)
+{
+        return of_platform_bus_probe(NULL, of_device_ids, NULL);
+}
diff --git a/arch/powerpc/platforms/85xx/corenet_ds.h b/arch/powerpc/platforms/85xx/corenet_ds.h
new file mode 100644
index 000000000000..ddd700b23031
--- /dev/null
+++ b/arch/powerpc/platforms/85xx/corenet_ds.h
@@ -0,0 +1,19 @@
+/*
+ * Corenet based SoC DS Setup
+ *
+ * Copyright 2009 Freescale Semiconductor Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef CORENET_DS_H
+#define CORENET_DS_H
+
+extern void __init corenet_ds_pic_init(void);
+extern void __init corenet_ds_setup_arch(void);
+extern int __init corenet_ds_publish_devices(void);
+
+#endif
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_mds.c b/arch/powerpc/platforms/85xx/mpc85xx_mds.c
index 3909d57b86e3..c5028a2e5a58 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_mds.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_mds.c
@@ -301,6 +301,7 @@ static struct of_device_id mpc85xx_ids[] = {
         { .compatible = "fsl,qe", },
         { .compatible = "gianfar", },
         { .compatible = "fsl,rapidio-delta", },
+        { .compatible = "fsl,mpc8548-guts", },
         {},
 };
 
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_rdb.c b/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
index c8468de4acf6..088f30b0c088 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
@@ -44,6 +44,7 @@ void __init mpc85xx_rdb_pic_init(void)
         struct mpic *mpic;
         struct resource r;
         struct device_node *np;
+        unsigned long root = of_get_flat_dt_root();
 
         np = of_find_node_by_type(NULL, "open-pic");
         if (np == NULL) {
@@ -57,11 +58,18 @@ void __init mpc85xx_rdb_pic_init(void)
                 return;
         }
 
-        mpic = mpic_alloc(np, r.start,
+        if (of_flat_dt_is_compatible(root, "fsl,85XXRDB-CAMP")) {
+                mpic = mpic_alloc(np, r.start,
+                        MPIC_PRIMARY |
+                        MPIC_BIG_ENDIAN | MPIC_BROKEN_FRR_NIRQS,
+                        0, 256, " OpenPIC  ");
+        } else {
+                mpic = mpic_alloc(np, r.start,
                   MPIC_PRIMARY | MPIC_WANTS_RESET |
                   MPIC_BIG_ENDIAN | MPIC_BROKEN_FRR_NIRQS |
                   MPIC_SINGLE_DEST_CPU,
                   0, 256, " OpenPIC  ");
+        }
 
         BUG_ON(mpic == NULL);
         of_node_put(np);
@@ -113,6 +121,7 @@ static int __init mpc85xxrdb_publish_devices(void)
         return of_platform_bus_probe(NULL, mpc85xxrdb_ids, NULL);
 }
 machine_device_initcall(p2020_rdb, mpc85xxrdb_publish_devices);
+machine_device_initcall(p1020_rdb, mpc85xxrdb_publish_devices);
 
 /*
  * Called very early, device-tree isn't unflattened
@@ -126,6 +135,15 @@ static int __init p2020_rdb_probe(void)
         return 0;
 }
 
+static int __init p1020_rdb_probe(void)
+{
+        unsigned long root = of_get_flat_dt_root();
+
+        if (of_flat_dt_is_compatible(root, "fsl,P1020RDB"))
+                return 1;
+        return 0;
+}
+
 define_machine(p2020_rdb) {
         .name                   = "P2020 RDB",
         .probe                  = p2020_rdb_probe,
@@ -139,3 +157,17 @@ define_machine(p2020_rdb) {
         .calibrate_decr         = generic_calibrate_decr,
         .progress               = udbg_progress,
 };
+
+define_machine(p1020_rdb) {
+        .name                   = "P1020 RDB",
+        .probe                  = p1020_rdb_probe,
+        .setup_arch             = mpc85xx_rdb_setup_arch,
+        .init_IRQ               = mpc85xx_rdb_pic_init,
+#ifdef CONFIG_PCI
+        .pcibios_fixup_bus      = fsl_pcibios_fixup_bus,
+#endif
+        .get_irq                = mpic_get_irq,
+        .restart                = fsl_rstcr_restart,
+        .calibrate_decr         = generic_calibrate_decr,
+        .progress               = udbg_progress,
+};
diff --git a/arch/powerpc/platforms/85xx/p4080_ds.c b/arch/powerpc/platforms/85xx/p4080_ds.c
new file mode 100644
index 000000000000..84170460497b
--- /dev/null
+++ b/arch/powerpc/platforms/85xx/p4080_ds.c
@@ -0,0 +1,74 @@
+/*
+ * P4080 DS Setup
+ *
+ * Maintained by Kumar Gala (see MAINTAINERS for contact information)
+ *
+ * Copyright 2009 Freescale Semiconductor Inc.
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/kernel.h>
+#include <linux/pci.h>
+#include <linux/kdev_t.h>
+#include <linux/delay.h>
+#include <linux/interrupt.h>
+
+#include <asm/system.h>
+#include <asm/time.h>
+#include <asm/machdep.h>
+#include <asm/pci-bridge.h>
+#include <mm/mmu_decl.h>
+#include <asm/prom.h>
+#include <asm/udbg.h>
+#include <asm/mpic.h>
+
+#include <linux/of_platform.h>
+#include <sysdev/fsl_soc.h>
+#include <sysdev/fsl_pci.h>
+
+#include "corenet_ds.h"
+
+#ifdef CONFIG_PCI
+static int primary_phb_addr;
+#endif
+
+/*
+ * Called very early, device-tree isn't unflattened
+ */
+static int __init p4080_ds_probe(void)
+{
+        unsigned long root = of_get_flat_dt_root();
+
+        if (of_flat_dt_is_compatible(root, "fsl,P4080DS")) {
+#ifdef CONFIG_PCI
+                /* treat PCIe1 as primary,
+                 * shouldn't matter as we have no ISA on the board
+                 */
+                primary_phb_addr = 0x0000;
+#endif
+                return 1;
+        } else {
+                return 0;
+        }
+}
+
+define_machine(p4080_ds) {
+        .name                   = "P4080 DS",
+        .probe                  = p4080_ds_probe,
+        .setup_arch             = corenet_ds_setup_arch,
+        .init_IRQ               = corenet_ds_pic_init,
+#ifdef CONFIG_PCI
+        .pcibios_fixup_bus      = fsl_pcibios_fixup_bus,
+#endif
+        .get_irq                = mpic_get_coreint_irq,
+        .restart                = fsl_rstcr_restart,
+        .calibrate_decr         = generic_calibrate_decr,
+        .progress               = udbg_progress,
+};
+
+machine_device_initcall(p4080_ds, corenet_ds_publish_devices);
+machine_arch_initcall(p4080_ds, swiotlb_setup_bus_notifier);
diff --git a/arch/powerpc/platforms/85xx/socrates_fpga_pic.c b/arch/powerpc/platforms/85xx/socrates_fpga_pic.c
index 60edf63d0157..e5da5f62b24a 100644
--- a/arch/powerpc/platforms/85xx/socrates_fpga_pic.c
+++ b/arch/powerpc/platforms/85xx/socrates_fpga_pic.c
@@ -232,7 +232,7 @@ static int socrates_fpga_pic_set_type(unsigned int virq,
 }
 
 static struct irq_chip socrates_fpga_pic_chip = {
-        .typename       = " FPGA-PIC ",
+        .name           = " FPGA-PIC ",
         .ack            = socrates_fpga_pic_ack,
         .mask           = socrates_fpga_pic_mask,
         .mask_ack       = socrates_fpga_pic_mask_ack,
@@ -245,7 +245,7 @@ static int socrates_fpga_pic_host_map(struct irq_host *h, unsigned int virq,
                 irq_hw_number_t hwirq)
 {
         /* All interrupts are LEVEL sensitive */
-        get_irq_desc(virq)->status |= IRQ_LEVEL;
+        irq_to_desc(virq)->status |= IRQ_LEVEL;
         set_irq_chip_and_handler(virq, &socrates_fpga_pic_chip,
                         handle_fasteoi_irq);
 
@@ -253,7 +253,7 @@ static int socrates_fpga_pic_host_map(struct irq_host *h, unsigned int virq,
 }
 
 static int socrates_fpga_pic_host_xlate(struct irq_host *h,
-                struct device_node *ct, u32 *intspec, unsigned int intsize,
+                struct device_node *ct, const u32 *intspec, unsigned int intsize,
                 irq_hw_number_t *out_hwirq, unsigned int *out_flags)
 {
         struct socrates_fpga_irq_info *fpga_irq = &fpga_irqs[intspec[0]];
diff --git a/arch/powerpc/platforms/86xx/Kconfig b/arch/powerpc/platforms/86xx/Kconfig
index 9c7b64a3402b..2bbfd530d6d8 100644
--- a/arch/powerpc/platforms/86xx/Kconfig
+++ b/arch/powerpc/platforms/86xx/Kconfig
@@ -35,6 +35,7 @@ config MPC8610_HPCD
 config GEF_PPC9A
         bool "GE Fanuc PPC9A"
         select DEFAULT_UIMAGE
+        select MMIO_NVRAM
         select GENERIC_GPIO
         select ARCH_REQUIRE_GPIOLIB
         help
@@ -43,6 +44,7 @@ config GEF_PPC9A
 config GEF_SBC310
         bool "GE Fanuc SBC310"
         select DEFAULT_UIMAGE
+        select MMIO_NVRAM
         select GENERIC_GPIO
         select ARCH_REQUIRE_GPIOLIB
         help
@@ -51,6 +53,7 @@ config GEF_SBC310
 config GEF_SBC610
         bool "GE Fanuc SBC610"
         select DEFAULT_UIMAGE
+        select MMIO_NVRAM
         select GENERIC_GPIO
         select ARCH_REQUIRE_GPIOLIB
         select HAS_RAPIDIO
diff --git a/arch/powerpc/platforms/86xx/gef_pic.c b/arch/powerpc/platforms/86xx/gef_pic.c
index 50d0a2b63809..0110a8736d33 100644
--- a/arch/powerpc/platforms/86xx/gef_pic.c
+++ b/arch/powerpc/platforms/86xx/gef_pic.c
@@ -149,7 +149,7 @@ static void gef_pic_unmask(unsigned int virq)
 }
 
 static struct irq_chip gef_pic_chip = {
-        .typename       = "gefp",
+        .name           = "gefp",
         .mask           = gef_pic_mask,
         .mask_ack       = gef_pic_mask_ack,
         .unmask         = gef_pic_unmask,
@@ -163,14 +163,14 @@ static int gef_pic_host_map(struct irq_host *h, unsigned int virq,
                           irq_hw_number_t hwirq)
 {
         /* All interrupts are LEVEL sensitive */
-        get_irq_desc(virq)->status |= IRQ_LEVEL;
+        irq_to_desc(virq)->status |= IRQ_LEVEL;
         set_irq_chip_and_handler(virq, &gef_pic_chip, handle_level_irq);
 
         return 0;
 }
 
 static int gef_pic_host_xlate(struct irq_host *h, struct device_node *ct,
-                            u32 *intspec, unsigned int intsize,
+                            const u32 *intspec, unsigned int intsize,
                             irq_hw_number_t *out_hwirq, unsigned int *out_flags)
 {
 
diff --git a/arch/powerpc/platforms/86xx/gef_ppc9a.c b/arch/powerpc/platforms/86xx/gef_ppc9a.c
index 287f7bd17dd9..a792e5d85813 100644
--- a/arch/powerpc/platforms/86xx/gef_ppc9a.c
+++ b/arch/powerpc/platforms/86xx/gef_ppc9a.c
@@ -33,6 +33,7 @@
 #include <asm/udbg.h>
 
 #include <asm/mpic.h>
+#include <asm/nvram.h>
 
 #include <sysdev/fsl_pci.h>
 #include <sysdev/fsl_soc.h>
@@ -95,6 +96,10 @@ static void __init gef_ppc9a_setup_arch(void)
                         printk(KERN_WARNING "Unable to map board registers\n");
                 of_node_put(regs);
         }
+
+#if defined(CONFIG_MMIO_NVRAM)
+        mmio_nvram_init();
+#endif
 }
 
 /* Return the PCB revision */
diff --git a/arch/powerpc/platforms/86xx/gef_sbc310.c b/arch/powerpc/platforms/86xx/gef_sbc310.c
index 90754e752bd8..6a1a613836c2 100644
--- a/arch/powerpc/platforms/86xx/gef_sbc310.c
+++ b/arch/powerpc/platforms/86xx/gef_sbc310.c
@@ -33,6 +33,7 @@
 #include <asm/udbg.h>
 
 #include <asm/mpic.h>
+#include <asm/nvram.h>
 
 #include <sysdev/fsl_pci.h>
 #include <sysdev/fsl_soc.h>
@@ -95,6 +96,10 @@ static void __init gef_sbc310_setup_arch(void)
                         printk(KERN_WARNING "Unable to map board registers\n");
                 of_node_put(regs);
         }
+
+#if defined(CONFIG_MMIO_NVRAM)
+        mmio_nvram_init();
+#endif
 }
 
 /* Return the PCB revision */
diff --git a/arch/powerpc/platforms/86xx/gef_sbc610.c b/arch/powerpc/platforms/86xx/gef_sbc610.c
index 72b31a6010a0..e10688a0fc4e 100644
--- a/arch/powerpc/platforms/86xx/gef_sbc610.c
+++ b/arch/powerpc/platforms/86xx/gef_sbc610.c
@@ -33,6 +33,7 @@
 #include <asm/udbg.h>
 
 #include <asm/mpic.h>
+#include <asm/nvram.h>
 
 #include <sysdev/fsl_pci.h>
 #include <sysdev/fsl_soc.h>
@@ -95,6 +96,10 @@ static void __init gef_sbc610_setup_arch(void)
                         printk(KERN_WARNING "Unable to map board registers\n");
                 of_node_put(regs);
         }
+
+#if defined(CONFIG_MMIO_NVRAM)
+        mmio_nvram_init();
+#endif
 }
 
 /* Return the PCB revision */
diff --git a/arch/powerpc/platforms/86xx/mpc8610_hpcd.c b/arch/powerpc/platforms/86xx/mpc8610_hpcd.c
index 627908a4cd77..5abe137f6309 100644
--- a/arch/powerpc/platforms/86xx/mpc8610_hpcd.c
+++ b/arch/powerpc/platforms/86xx/mpc8610_hpcd.c
@@ -19,6 +19,7 @@
 #include <linux/stddef.h>
 #include <linux/kernel.h>
 #include <linux/pci.h>
+#include <linux/interrupt.h>
 #include <linux/kdev_t.h>
 #include <linux/delay.h>
 #include <linux/seq_file.h>
@@ -41,10 +42,46 @@
 
 #include "mpc86xx.h"
 
+static struct device_node *pixis_node;
 static unsigned char *pixis_bdcfg0, *pixis_arch;
 
+#ifdef CONFIG_SUSPEND
+static irqreturn_t mpc8610_sw9_irq(int irq, void *data)
+{
+        pr_debug("%s: PIXIS' event (sw9/wakeup) IRQ handled\n", __func__);
+        return IRQ_HANDLED;
+}
+
+static void __init mpc8610_suspend_init(void)
+{
+        int irq;
+        int ret;
+
+        if (!pixis_node)
+                return;
+
+        irq = irq_of_parse_and_map(pixis_node, 0);
+        if (!irq) {
+                pr_err("%s: can't map pixis event IRQ.\n", __func__);
+                return;
+        }
+
+        ret = request_irq(irq, mpc8610_sw9_irq, 0, "sw9/wakeup", NULL);
+        if (ret) {
+                pr_err("%s: can't request pixis event IRQ: %d\n",
+                       __func__, ret);
+                irq_dispose_mapping(irq);
+        }
+
+        enable_irq_wake(irq);
+}
+#else
+static inline void mpc8610_suspend_init(void) { }
+#endif /* CONFIG_SUSPEND */
+
 static struct of_device_id __initdata mpc8610_ids[] = {
         { .compatible = "fsl,mpc8610-immr", },
+        { .compatible = "fsl,mpc8610-guts", },
         { .compatible = "simple-bus", },
         { .compatible = "gianfar", },
         {}
@@ -55,6 +92,9 @@ static int __init mpc8610_declare_of_platform_devices(void)
         /* Firstly, register PIXIS GPIOs. */
         simple_gpiochip_init("fsl,fpga-pixis-gpio-bank");
 
+        /* Enable wakeup on PIXIS' event IRQ. */
+        mpc8610_suspend_init();
+
         /* Without this call, the SSI device driver won't get probed. */
         of_platform_bus_probe(NULL, mpc8610_ids, NULL);
 
@@ -250,10 +290,10 @@ static void __init mpc86xx_hpcd_setup_arch(void)
         diu_ops.set_sysfs_monitor_port  = mpc8610hpcd_set_sysfs_monitor_port;
 #endif
 
-        np = of_find_compatible_node(NULL, NULL, "fsl,fpga-pixis");
-        if (np) {
-                of_address_to_resource(np, 0, &r);
-                of_node_put(np);
+        pixis_node = of_find_compatible_node(NULL, NULL, "fsl,fpga-pixis");
+        if (pixis_node) {
+                of_address_to_resource(pixis_node, 0, &r);
+                of_node_put(pixis_node);
                 pixis = ioremap(r.start, 32);
                 if (!pixis) {
                         printk(KERN_ERR "Err: can't map FPGA cfg register!\n");
diff --git a/arch/powerpc/platforms/8xx/m8xx_setup.c b/arch/powerpc/platforms/8xx/m8xx_setup.c
index 385acfc48397..242954c4293f 100644
--- a/arch/powerpc/platforms/8xx/m8xx_setup.c
+++ b/arch/powerpc/platforms/8xx/m8xx_setup.c
@@ -222,7 +222,7 @@ static void cpm_cascade(unsigned int irq, struct irq_desc *desc)
         int cascade_irq;
 
         if ((cascade_irq = cpm_get_irq()) >= 0) {
-                struct irq_desc *cdesc = irq_desc + cascade_irq;
+                struct irq_desc *cdesc = irq_to_desc(cascade_irq);
 
                 generic_handle_irq(cascade_irq);
                 cdesc->chip->eoi(cascade_irq);
diff --git a/arch/powerpc/platforms/Kconfig b/arch/powerpc/platforms/Kconfig
index 04a8061045c4..d1663db7810f 100644
--- a/arch/powerpc/platforms/Kconfig
+++ b/arch/powerpc/platforms/Kconfig
@@ -86,6 +86,11 @@ config RTAS_ERROR_LOGGING
         depends on PPC_RTAS
         default n
 
+config PPC_RTAS_DAEMON
+        bool
+        depends on PPC_RTAS
+        default n
+
 config RTAS_PROC
         bool "Proc interface to RTAS"
         depends on PPC_RTAS
@@ -255,7 +260,7 @@ config QE_GPIO
 
 config CPM2
         bool "Enable support for the CPM2 (Communications Processor Module)"
-        depends on MPC85xx || 8260
+        depends on (FSL_SOC_BOOKE && PPC32) || 8260
         select CPM
         select PPC_LIB_RHEAP
         select PPC_PCI_CHOICE
@@ -300,7 +305,7 @@ source "arch/powerpc/sysdev/bestcomm/Kconfig"
 
 config MPC8xxx_GPIO
         bool "MPC8xxx GPIO support"
-        depends on PPC_MPC831x || PPC_MPC834x || PPC_MPC837x || PPC_85xx || PPC_86xx
+        depends on PPC_MPC831x || PPC_MPC834x || PPC_MPC837x || FSL_SOC_BOOKE || PPC_86xx
         select GENERIC_GPIO
         select ARCH_REQUIRE_GPIOLIB
         help
diff --git a/arch/powerpc/platforms/Kconfig.cputype b/arch/powerpc/platforms/Kconfig.cputype
index e382cae678b8..fa0f690d3867 100644
--- a/arch/powerpc/platforms/Kconfig.cputype
+++ b/arch/powerpc/platforms/Kconfig.cputype
@@ -28,8 +28,6 @@ config PPC_BOOK3S_32
 config PPC_85xx
         bool "Freescale 85xx"
         select E500
-        select FSL_SOC
-        select MPC85xx
 
 config PPC_8xx
         bool "Freescale 8xx"
@@ -138,6 +136,14 @@ config PPC_FPU
         bool
         default y if PPC64
 
+config FSL_EMB_PERFMON
+        bool "Freescale Embedded Perfmon"
+        depends on E500 || PPC_83xx
+        help
+          This is the Performance Monitor support found on the e500 core
+          and some e300 cores (c3 and c4).  Select this only if your
+          core supports the Embedded Performance Monitor APU
+
 config 4xx
         bool
         depends on 40x || 44x
@@ -153,13 +159,6 @@ config FSL_BOOKE
         depends on E200 || E500
         default y
 
-config FSL_EMB_PERFMON
-        bool "Freescale Embedded Perfmon"
-        depends on E500 || PPC_83xx
-        help
-          This is the Performance Monitor support found on the e500 core
-          and some e300 cores (c3 and c4).  Select this only if your
-          core supports the Embedded Performance Monitor APU
 
 config PTE_64BIT
         bool
@@ -312,7 +311,7 @@ config NR_CPUS
 
 config NOT_COHERENT_CACHE
         bool
-        depends on 4xx || 8xx || E200 || PPC_MPC512x
+        depends on 4xx || 8xx || E200 || PPC_MPC512x || GAMECUBE_COMMON
         default y
 
 config CHECK_CACHE_COHERENCY
diff --git a/arch/powerpc/platforms/Makefile b/arch/powerpc/platforms/Makefile
index a6812ee00100..fdb9f0b0d7a8 100644
--- a/arch/powerpc/platforms/Makefile
+++ b/arch/powerpc/platforms/Makefile
@@ -12,7 +12,7 @@ obj-$(CONFIG_PPC_MPC52xx)	+= 52xx/
 obj-$(CONFIG_PPC_8xx)           += 8xx/
 obj-$(CONFIG_PPC_82xx)          += 82xx/
 obj-$(CONFIG_PPC_83xx)          += 83xx/
-obj-$(CONFIG_PPC_85xx)          += 85xx/
+obj-$(CONFIG_FSL_SOC_BOOKE)     += 85xx/
 obj-$(CONFIG_PPC_86xx)          += 86xx/
 obj-$(CONFIG_PPC_PSERIES)       += pseries/
 obj-$(CONFIG_PPC_ISERIES)       += iseries/
diff --git a/arch/powerpc/platforms/amigaone/setup.c b/arch/powerpc/platforms/amigaone/setup.c
index 9290a7a442d0..fb4eb0df054c 100644
--- a/arch/powerpc/platforms/amigaone/setup.c
+++ b/arch/powerpc/platforms/amigaone/setup.c
@@ -14,7 +14,7 @@
 
 #include <linux/kernel.h>
 #include <linux/seq_file.h>
-#include <linux/utsrelease.h>
+#include <generated/utsrelease.h>
 
 #include <asm/machdep.h>
 #include <asm/cputable.h>
diff --git a/arch/powerpc/platforms/cell/axon_msi.c b/arch/powerpc/platforms/cell/axon_msi.c
index a86c34b3bb84..96fe896f6df3 100644
--- a/arch/powerpc/platforms/cell/axon_msi.c
+++ b/arch/powerpc/platforms/cell/axon_msi.c
@@ -312,7 +312,7 @@ static struct irq_chip msic_irq_chip = {
         .mask           = mask_msi_irq,
         .unmask         = unmask_msi_irq,
         .shutdown       = unmask_msi_irq,
-        .typename       = "AXON-MSI",
+        .name           = "AXON-MSI",
 };
 
 static int msic_host_map(struct irq_host *h, unsigned int virq,
diff --git a/arch/powerpc/platforms/cell/beat_interrupt.c b/arch/powerpc/platforms/cell/beat_interrupt.c
index 72254848a228..36052a9ebcda 100644
--- a/arch/powerpc/platforms/cell/beat_interrupt.c
+++ b/arch/powerpc/platforms/cell/beat_interrupt.c
@@ -110,7 +110,7 @@ static void beatic_end_irq(unsigned int irq_plug)
 }
 
 static struct irq_chip beatic_pic = {
-        .typename = " CELL-BEAT ",
+        .name = " CELL-BEAT ",
         .unmask = beatic_unmask_irq,
         .mask = beatic_mask_irq,
         .eoi = beatic_end_irq,
@@ -136,7 +136,7 @@ static void beatic_pic_host_unmap(struct irq_host *h, unsigned int virq)
 static int beatic_pic_host_map(struct irq_host *h, unsigned int virq,
                                irq_hw_number_t hw)
 {
-        struct irq_desc *desc = get_irq_desc(virq);
+        struct irq_desc *desc = irq_to_desc(virq);
         int64_t err;
 
         err = beat_construct_and_connect_irq_plug(virq, hw);
@@ -166,11 +166,11 @@ static void beatic_pic_host_remap(struct irq_host *h, unsigned int virq,
  * Note: We have only 1 entry to translate.
  */
 static int beatic_pic_host_xlate(struct irq_host *h, struct device_node *ct,
-                                 u32 *intspec, unsigned int intsize,
+                                 const u32 *intspec, unsigned int intsize,
                                  irq_hw_number_t *out_hwirq,
                                  unsigned int *out_flags)
 {
-        u64 *intspec2 = (u64 *)intspec;
+        const u64 *intspec2 = (const u64 *)intspec;
 
         *out_hwirq = *intspec2;
         *out_flags |= IRQ_TYPE_LEVEL_LOW;
diff --git a/arch/powerpc/platforms/cell/interrupt.c b/arch/powerpc/platforms/cell/interrupt.c
index 882e47080e74..6829cf7e2bda 100644
--- a/arch/powerpc/platforms/cell/interrupt.c
+++ b/arch/powerpc/platforms/cell/interrupt.c
@@ -54,7 +54,7 @@ struct iic {
         struct device_node *node;
 };
 
-static DEFINE_PER_CPU(struct iic, iic);
+static DEFINE_PER_CPU(struct iic, cpu_iic);
 #define IIC_NODE_COUNT  2
 static struct irq_host *iic_host;
 
@@ -82,13 +82,13 @@ static void iic_unmask(unsigned int irq)
 
 static void iic_eoi(unsigned int irq)
 {
-        struct iic *iic = &__get_cpu_var(iic);
+        struct iic *iic = &__get_cpu_var(cpu_iic);
         out_be64(&iic->regs->prio, iic->eoi_stack[--iic->eoi_ptr]);
         BUG_ON(iic->eoi_ptr < 0);
 }
 
 static struct irq_chip iic_chip = {
-        .typename = " CELL-IIC ",
+        .name = " CELL-IIC ",
         .mask = iic_mask,
         .unmask = iic_unmask,
         .eoi = iic_eoi,
@@ -133,7 +133,7 @@ static void iic_ioexc_cascade(unsigned int irq, struct irq_desc *desc)
 
 
 static struct irq_chip iic_ioexc_chip = {
-        .typename = " CELL-IOEX",
+        .name = " CELL-IOEX",
         .mask = iic_mask,
         .unmask = iic_unmask,
         .eoi = iic_ioexc_eoi,
@@ -146,7 +146,7 @@ static unsigned int iic_get_irq(void)
         struct iic *iic;
         unsigned int virq;
 
-        iic = &__get_cpu_var(iic);
+        iic = &__get_cpu_var(cpu_iic);
         *(unsigned long *) &pending =
                 in_be64((u64 __iomem *) &iic->regs->pending_destr);
         if (!(pending.flags & CBE_IIC_IRQ_VALID))
@@ -161,12 +161,12 @@ static unsigned int iic_get_irq(void)
 
 void iic_setup_cpu(void)
 {
-        out_be64(&__get_cpu_var(iic).regs->prio, 0xff);
+        out_be64(&__get_cpu_var(cpu_iic).regs->prio, 0xff);
 }
 
 u8 iic_get_target_id(int cpu)
 {
-        return per_cpu(iic, cpu).target_id;
+        return per_cpu(cpu_iic, cpu).target_id;
 }
 
 EXPORT_SYMBOL_GPL(iic_get_target_id);
@@ -181,7 +181,7 @@ static inline int iic_ipi_to_irq(int ipi)
 
 void iic_cause_IPI(int cpu, int mesg)
 {
-        out_be64(&per_cpu(iic, cpu).regs->generate, (0xf - mesg) << 4);
+        out_be64(&per_cpu(cpu_iic, cpu).regs->generate, (0xf - mesg) << 4);
 }
 
 struct irq_host *iic_get_irq_host(int node)
@@ -237,7 +237,7 @@ extern int noirqdebug;
 
 static void handle_iic_irq(unsigned int irq, struct irq_desc *desc)
 {
-        spin_lock(&desc->lock);
+        raw_spin_lock(&desc->lock);
 
         desc->status &= ~(IRQ_REPLAY | IRQ_WAITING);
 
@@ -265,18 +265,18 @@ static void handle_iic_irq(unsigned int irq, struct irq_desc *desc)
                         goto out_eoi;
 
                 desc->status &= ~IRQ_PENDING;
-                spin_unlock(&desc->lock);
+                raw_spin_unlock(&desc->lock);
                 action_ret = handle_IRQ_event(irq, action);
                 if (!noirqdebug)
                         note_interrupt(irq, desc, action_ret);
-                spin_lock(&desc->lock);
+                raw_spin_lock(&desc->lock);
 
         } while ((desc->status & (IRQ_PENDING | IRQ_DISABLED)) == IRQ_PENDING);
 
         desc->status &= ~IRQ_INPROGRESS;
 out_eoi:
         desc->chip->eoi(irq);
-        spin_unlock(&desc->lock);
+        raw_spin_unlock(&desc->lock);
 }
 
 static int iic_host_map(struct irq_host *h, unsigned int virq,
@@ -297,7 +297,7 @@ static int iic_host_map(struct irq_host *h, unsigned int virq,
 }
 
 static int iic_host_xlate(struct irq_host *h, struct device_node *ct,
-                           u32 *intspec, unsigned int intsize,
+                           const u32 *intspec, unsigned int intsize,
                            irq_hw_number_t *out_hwirq, unsigned int *out_flags)
 
 {
@@ -348,7 +348,7 @@ static void __init init_one_iic(unsigned int hw_cpu, unsigned long addr,
         /* XXX FIXME: should locate the linux CPU number from the HW cpu
          * number properly. We are lucky for now
          */
-        struct iic *iic = &per_cpu(iic, hw_cpu);
+        struct iic *iic = &per_cpu(cpu_iic, hw_cpu);
 
         iic->regs = ioremap(addr, sizeof(struct cbe_iic_thread_regs));
         BUG_ON(iic->regs == NULL);
diff --git a/arch/powerpc/platforms/cell/spider-pic.c b/arch/powerpc/platforms/cell/spider-pic.c
index 4e5655624ae8..01244f254a11 100644
--- a/arch/powerpc/platforms/cell/spider-pic.c
+++ b/arch/powerpc/platforms/cell/spider-pic.c
@@ -102,7 +102,7 @@ static void spider_ack_irq(unsigned int virq)
 
         /* Reset edge detection logic if necessary
          */
-        if (get_irq_desc(virq)->status & IRQ_LEVEL)
+        if (irq_to_desc(virq)->status & IRQ_LEVEL)
                 return;
 
         /* Only interrupts 47 to 50 can be set to edge */
@@ -119,7 +119,7 @@ static int spider_set_irq_type(unsigned int virq, unsigned int type)
         struct spider_pic *pic = spider_virq_to_pic(virq);
         unsigned int hw = irq_map[virq].hwirq;
         void __iomem *cfg = spider_get_irq_config(pic, hw);
-        struct irq_desc *desc = get_irq_desc(virq);
+        struct irq_desc *desc = irq_to_desc(virq);
         u32 old_mask;
         u32 ic;
 
@@ -168,7 +168,7 @@ static int spider_set_irq_type(unsigned int virq, unsigned int type)
 }
 
 static struct irq_chip spider_pic = {
-        .typename = " SPIDER   ",
+        .name = " SPIDER   ",
         .unmask = spider_unmask_irq,
         .mask = spider_mask_irq,
         .ack = spider_ack_irq,
@@ -187,7 +187,7 @@ static int spider_host_map(struct irq_host *h, unsigned int virq,
 }
 
 static int spider_host_xlate(struct irq_host *h, struct device_node *ct,
-                           u32 *intspec, unsigned int intsize,
+                           const u32 *intspec, unsigned int intsize,
                            irq_hw_number_t *out_hwirq, unsigned int *out_flags)
 
 {
diff --git a/arch/powerpc/platforms/cell/spufs/Makefile b/arch/powerpc/platforms/cell/spufs/Makefile
index b93f877ba504..b9d5d678aa44 100644
--- a/arch/powerpc/platforms/cell/spufs/Makefile
+++ b/arch/powerpc/platforms/cell/spufs/Makefile
@@ -13,10 +13,8 @@ SPU_CC		:= $(SPU_CROSS)gcc
 SPU_AS          := $(SPU_CROSS)gcc
 SPU_LD          := $(SPU_CROSS)ld
 SPU_OBJCOPY     := $(SPU_CROSS)objcopy
-SPU_CFLAGS      := -O2 -Wall -I$(srctree)/include \
-                   -I$(objtree)/include2 -D__KERNEL__
-SPU_AFLAGS      := -c -D__ASSEMBLY__ -I$(srctree)/include \
-                   -I$(objtree)/include2 -D__KERNEL__
+SPU_CFLAGS      := -O2 -Wall -I$(srctree)/include -D__KERNEL__
+SPU_AFLAGS      := -c -D__ASSEMBLY__ -I$(srctree)/include -D__KERNEL__
 SPU_LDFLAGS     := -N -Ttext=0x0
 
 $(obj)/switch.o: $(obj)/spu_save_dump.h $(obj)/spu_restore_dump.h
diff --git a/arch/powerpc/platforms/cell/spufs/file.c b/arch/powerpc/platforms/cell/spufs/file.c
index 884e8bcec499..64a4c2d85f7c 100644
--- a/arch/powerpc/platforms/cell/spufs/file.c
+++ b/arch/powerpc/platforms/cell/spufs/file.c
@@ -2494,7 +2494,7 @@ static ssize_t spufs_switch_log_read(struct file *file, char __user *buf,
         struct spu_context *ctx = SPUFS_I(inode)->i_ctx;
         int error = 0, cnt = 0;
 
-        if (!buf || len < 0)
+        if (!buf)
                 return -EINVAL;
 
         error = spu_acquire(ctx);
diff --git a/arch/powerpc/platforms/chrp/Kconfig b/arch/powerpc/platforms/chrp/Kconfig
index 37d438bd5b7a..bc0b0efdc5fe 100644
--- a/arch/powerpc/platforms/chrp/Kconfig
+++ b/arch/powerpc/platforms/chrp/Kconfig
@@ -5,6 +5,8 @@ config PPC_CHRP
         select PPC_I8259
         select PPC_INDIRECT_PCI
         select PPC_RTAS
+        select PPC_RTAS_DAEMON
+        select RTAS_ERROR_LOGGING
         select PPC_MPC106
         select PPC_UDBG_16550
         select PPC_NATIVE
diff --git a/arch/powerpc/platforms/chrp/setup.c b/arch/powerpc/platforms/chrp/setup.c
index cd4ad9aea760..8f41685d8f42 100644
--- a/arch/powerpc/platforms/chrp/setup.c
+++ b/arch/powerpc/platforms/chrp/setup.c
@@ -23,7 +23,7 @@
 #include <linux/reboot.h>
 #include <linux/init.h>
 #include <linux/pci.h>
-#include <linux/utsrelease.h>
+#include <generated/utsrelease.h>
 #include <linux/adb.h>
 #include <linux/module.h>
 #include <linux/delay.h>
@@ -364,19 +364,6 @@ void __init chrp_setup_arch(void)
         if (ppc_md.progress) ppc_md.progress("Linux/PPC "UTS_RELEASE"\n", 0x0);
 }
 
-void
-chrp_event_scan(unsigned long unused)
-{
-        unsigned char log[1024];
-        int ret = 0;
-
-        /* XXX: we should loop until the hardware says no more error logs -- Cort */
-        rtas_call(rtas_token("event-scan"), 4, 1, &ret, 0xffffffff, 0,
-                  __pa(log), 1024);
-        mod_timer(&__get_cpu_var(heartbeat_timer),
-                  jiffies + event_scan_interval);
-}
-
 static void chrp_8259_cascade(unsigned int irq, struct irq_desc *desc)
 {
         unsigned int cascade_irq = i8259_irq();
@@ -568,9 +555,6 @@ void __init chrp_init_IRQ(void)
 void __init
 chrp_init2(void)
 {
-        struct device_node *device;
-        const unsigned int *p = NULL;
-
 #ifdef CONFIG_NVRAM
         chrp_nvram_init();
 #endif
@@ -582,40 +566,6 @@ chrp_init2(void)
         request_region(0x80,0x10,"dma page reg");
         request_region(0xc0,0x20,"dma2");
 
-        /* Get the event scan rate for the rtas so we know how
-         * often it expects a heartbeat. -- Cort
-         */
-        device = of_find_node_by_name(NULL, "rtas");
-        if (device)
-                p = of_get_property(device, "rtas-event-scan-rate", NULL);
-        if (p && *p) {
-                /*
-                 * Arrange to call chrp_event_scan at least *p times
-                 * per minute.  We use 59 rather than 60 here so that
-                 * the rate will be slightly higher than the minimum.
-                 * This all assumes we don't do hotplug CPU on any
-                 * machine that needs the event scans done.
-                 */
-                unsigned long interval, offset;
-                int cpu, ncpus;
-                struct timer_list *timer;
-
-                interval = HZ * 59 / *p;
-                offset = HZ;
-                ncpus = num_online_cpus();
-                event_scan_interval = ncpus * interval;
-                for (cpu = 0; cpu < ncpus; ++cpu) {
-                        timer = &per_cpu(heartbeat_timer, cpu);
-                        setup_timer(timer, chrp_event_scan, 0);
-                        timer->expires = jiffies + offset;
-                        add_timer_on(timer, cpu);
-                        offset += interval;
-                }
-                printk("RTAS Event Scan Rate: %u (%lu jiffies)\n",
-                       *p, interval);
-        }
-        of_node_put(device);
-
         if (ppc_md.progress)
                 ppc_md.progress("  Have fun!    ", 0x7777);
 }
diff --git a/arch/powerpc/platforms/embedded6xx/Kconfig b/arch/powerpc/platforms/embedded6xx/Kconfig
index 291ac9d8cbee..524d971a1478 100644
--- a/arch/powerpc/platforms/embedded6xx/Kconfig
+++ b/arch/powerpc/platforms/embedded6xx/Kconfig
@@ -90,3 +90,36 @@ config MPC10X_OPENPIC
 config MPC10X_STORE_GATHERING
         bool "Enable MPC10x store gathering"
         depends on MPC10X_BRIDGE
+
+config GAMECUBE_COMMON
+        bool
+
+config USBGECKO_UDBG
+        bool "USB Gecko udbg console for the Nintendo GameCube/Wii"
+        depends on GAMECUBE_COMMON
+        help
+          If you say yes to this option, support will be included for the
+          USB Gecko adapter as an udbg console.
+          The USB Gecko is a EXI to USB Serial converter that can be plugged
+          into a memcard slot in the Nintendo GameCube/Wii.
+
+          This driver bypasses the EXI layer completely.
+
+          If in doubt, say N here.
+
+config GAMECUBE
+        bool "Nintendo-GameCube"
+        depends on EMBEDDED6xx
+        select GAMECUBE_COMMON
+        help
+          Select GAMECUBE if configuring for the Nintendo GameCube.
+          More information at: <http://gc-linux.sourceforge.net/>
+
+config WII
+        bool "Nintendo-Wii"
+        depends on EMBEDDED6xx
+        select GAMECUBE_COMMON
+        help
+          Select WII if configuring for the Nintendo Wii.
+          More information at: <http://gc-linux.sourceforge.net/>
+
diff --git a/arch/powerpc/platforms/embedded6xx/Makefile b/arch/powerpc/platforms/embedded6xx/Makefile
index 0773c08bd444..66c23e423f40 100644
--- a/arch/powerpc/platforms/embedded6xx/Makefile
+++ b/arch/powerpc/platforms/embedded6xx/Makefile
@@ -7,3 +7,7 @@ obj-$(CONFIG_STORCENTER)	+= storcenter.o
 obj-$(CONFIG_PPC_HOLLY)         += holly.o
 obj-$(CONFIG_PPC_PRPMC2800)     += prpmc2800.o
 obj-$(CONFIG_PPC_C2K)           += c2k.o
+obj-$(CONFIG_USBGECKO_UDBG)     += usbgecko_udbg.o
+obj-$(CONFIG_GAMECUBE_COMMON)   += flipper-pic.o
+obj-$(CONFIG_GAMECUBE)          += gamecube.o
+obj-$(CONFIG_WII)               += wii.o hlwd-pic.o
diff --git a/arch/powerpc/platforms/embedded6xx/flipper-pic.c b/arch/powerpc/platforms/embedded6xx/flipper-pic.c
new file mode 100644
index 000000000000..d5963285e3be
--- /dev/null
+++ b/arch/powerpc/platforms/embedded6xx/flipper-pic.c
@@ -0,0 +1,263 @@
+/*
+ * arch/powerpc/platforms/embedded6xx/flipper-pic.c
+ *
+ * Nintendo GameCube/Wii "Flipper" interrupt controller support.
+ * Copyright (C) 2004-2009 The GameCube Linux Team
+ * Copyright (C) 2007,2008,2009 Albert Herranz
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ */
+#define DRV_MODULE_NAME "flipper-pic"
+#define pr_fmt(fmt) DRV_MODULE_NAME ": " fmt
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/irq.h>
+#include <linux/of.h>
+#include <asm/io.h>
+
+#include "flipper-pic.h"
+
+#define FLIPPER_NR_IRQS         32
+
+/*
+ * Each interrupt has a corresponding bit in both
+ * the Interrupt Cause (ICR) and Interrupt Mask (IMR) registers.
+ *
+ * Enabling/disabling an interrupt line involves setting/clearing
+ * the corresponding bit in IMR.
+ * Except for the RSW interrupt, all interrupts get deasserted automatically
+ * when the source deasserts the interrupt.
+ */
+#define FLIPPER_ICR             0x00
+#define FLIPPER_ICR_RSS         (1<<16) /* reset switch state */
+
+#define FLIPPER_IMR             0x04
+
+#define FLIPPER_RESET           0x24
+
+
+/*
+ * IRQ chip hooks.
+ *
+ */
+
+static void flipper_pic_mask_and_ack(unsigned int virq)
+{
+        int irq = virq_to_hw(virq);
+        void __iomem *io_base = get_irq_chip_data(virq);
+        u32 mask = 1 << irq;
+
+        clrbits32(io_base + FLIPPER_IMR, mask);
+        /* this is at least needed for RSW */
+        out_be32(io_base + FLIPPER_ICR, mask);
+}
+
+static void flipper_pic_ack(unsigned int virq)
+{
+        int irq = virq_to_hw(virq);
+        void __iomem *io_base = get_irq_chip_data(virq);
+
+        /* this is at least needed for RSW */
+        out_be32(io_base + FLIPPER_ICR, 1 << irq);
+}
+
+static void flipper_pic_mask(unsigned int virq)
+{
+        int irq = virq_to_hw(virq);
+        void __iomem *io_base = get_irq_chip_data(virq);
+
+        clrbits32(io_base + FLIPPER_IMR, 1 << irq);
+}
+
+static void flipper_pic_unmask(unsigned int virq)
+{
+        int irq = virq_to_hw(virq);
+        void __iomem *io_base = get_irq_chip_data(virq);
+
+        setbits32(io_base + FLIPPER_IMR, 1 << irq);
+}
+
+
+static struct irq_chip flipper_pic = {
+        .name           = "flipper-pic",
+        .ack            = flipper_pic_ack,
+        .mask_ack       = flipper_pic_mask_and_ack,
+        .mask           = flipper_pic_mask,
+        .unmask         = flipper_pic_unmask,
+};
+
+/*
+ * IRQ host hooks.
+ *
+ */
+
+static struct irq_host *flipper_irq_host;
+
+static int flipper_pic_map(struct irq_host *h, unsigned int virq,
+                           irq_hw_number_t hwirq)
+{
+        set_irq_chip_data(virq, h->host_data);
+        get_irq_desc(virq)->status |= IRQ_LEVEL;
+        set_irq_chip_and_handler(virq, &flipper_pic, handle_level_irq);
+        return 0;
+}
+
+static void flipper_pic_unmap(struct irq_host *h, unsigned int irq)
+{
+        set_irq_chip_data(irq, NULL);
+        set_irq_chip(irq, NULL);
+}
+
+static int flipper_pic_match(struct irq_host *h, struct device_node *np)
+{
+        return 1;
+}
+
+
+static struct irq_host_ops flipper_irq_host_ops = {
+        .map = flipper_pic_map,
+        .unmap = flipper_pic_unmap,
+        .match = flipper_pic_match,
+};
+
+/*
+ * Platform hooks.
+ *
+ */
+
+static void __flipper_quiesce(void __iomem *io_base)
+{
+        /* mask and ack all IRQs */
+        out_be32(io_base + FLIPPER_IMR, 0x00000000);
+        out_be32(io_base + FLIPPER_ICR, 0xffffffff);
+}
+
+struct irq_host * __init flipper_pic_init(struct device_node *np)
+{
+        struct device_node *pi;
+        struct irq_host *irq_host = NULL;
+        struct resource res;
+        void __iomem *io_base;
+        int retval;
+
+        pi = of_get_parent(np);
+        if (!pi) {
+                pr_err("no parent found\n");
+                goto out;
+        }
+        if (!of_device_is_compatible(pi, "nintendo,flipper-pi")) {
+                pr_err("unexpected parent compatible\n");
+                goto out;
+        }
+
+        retval = of_address_to_resource(pi, 0, &res);
+        if (retval) {
+                pr_err("no io memory range found\n");
+                goto out;
+        }
+        io_base = ioremap(res.start, resource_size(&res));
+
+        pr_info("controller at 0x%08x mapped to 0x%p\n", res.start, io_base);
+
+        __flipper_quiesce(io_base);
+
+        irq_host = irq_alloc_host(np, IRQ_HOST_MAP_LINEAR, FLIPPER_NR_IRQS,
+                                  &flipper_irq_host_ops, -1);
+        if (!irq_host) {
+                pr_err("failed to allocate irq_host\n");
+                return NULL;
+        }
+
+        irq_host->host_data = io_base;
+
+out:
+        return irq_host;
+}
+
+unsigned int flipper_pic_get_irq(void)
+{
+        void __iomem *io_base = flipper_irq_host->host_data;
+        int irq;
+        u32 irq_status;
+
+        irq_status = in_be32(io_base + FLIPPER_ICR) &
+                     in_be32(io_base + FLIPPER_IMR);
+        if (irq_status == 0)
+                return NO_IRQ;  /* no more IRQs pending */
+
+        irq = __ffs(irq_status);
+        return irq_linear_revmap(flipper_irq_host, irq);
+}
+
+/*
+ * Probe function.
+ *
+ */
+
+void __init flipper_pic_probe(void)
+{
+        struct device_node *np;
+
+        np = of_find_compatible_node(NULL, NULL, "nintendo,flipper-pic");
+        BUG_ON(!np);
+
+        flipper_irq_host = flipper_pic_init(np);
+        BUG_ON(!flipper_irq_host);
+
+        irq_set_default_host(flipper_irq_host);
+
+        of_node_put(np);
+}
+
+/*
+ * Misc functions related to the flipper chipset.
+ *
+ */
+
+/**
+ * flipper_quiesce() - quiesce flipper irq controller
+ *
+ * Mask and ack all interrupt sources.
+ *
+ */
+void flipper_quiesce(void)
+{
+        void __iomem *io_base = flipper_irq_host->host_data;
+
+        __flipper_quiesce(io_base);
+}
+
+/*
+ * Resets the platform.
+ */
+void flipper_platform_reset(void)
+{
+        void __iomem *io_base;
+
+        if (flipper_irq_host && flipper_irq_host->host_data) {
+                io_base = flipper_irq_host->host_data;
+                out_8(io_base + FLIPPER_RESET, 0x00);
+        }
+}
+
+/*
+ * Returns non-zero if the reset button is pressed.
+ */
+int flipper_is_reset_button_pressed(void)
+{
+        void __iomem *io_base;
+        u32 icr;
+
+        if (flipper_irq_host && flipper_irq_host->host_data) {
+                io_base = flipper_irq_host->host_data;
+                icr = in_be32(io_base + FLIPPER_ICR);
+                return !(icr & FLIPPER_ICR_RSS);
+        }
+        return 0;
+}
+
diff --git a/arch/powerpc/platforms/embedded6xx/flipper-pic.h b/arch/powerpc/platforms/embedded6xx/flipper-pic.h
new file mode 100644
index 000000000000..e339186b5663
--- /dev/null
+++ b/arch/powerpc/platforms/embedded6xx/flipper-pic.h
@@ -0,0 +1,25 @@
+/*
+ * arch/powerpc/platforms/embedded6xx/flipper-pic.h
+ *
+ * Nintendo GameCube/Wii "Flipper" interrupt controller support.
+ * Copyright (C) 2004-2009 The GameCube Linux Team
+ * Copyright (C) 2007,2008,2009 Albert Herranz
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ */
+
+#ifndef __FLIPPER_PIC_H
+#define __FLIPPER_PIC_H
+
+unsigned int flipper_pic_get_irq(void);
+void __init flipper_pic_probe(void);
+
+void flipper_quiesce(void);
+void flipper_platform_reset(void);
+int flipper_is_reset_button_pressed(void);
+
+#endif
diff --git a/arch/powerpc/platforms/embedded6xx/gamecube.c b/arch/powerpc/platforms/embedded6xx/gamecube.c
new file mode 100644
index 000000000000..1106fd99627f
--- /dev/null
+++ b/arch/powerpc/platforms/embedded6xx/gamecube.c
@@ -0,0 +1,118 @@
+/*
+ * arch/powerpc/platforms/embedded6xx/gamecube.c
+ *
+ * Nintendo GameCube board-specific support
+ * Copyright (C) 2004-2009 The GameCube Linux Team
+ * Copyright (C) 2007,2008,2009 Albert Herranz
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/irq.h>
+#include <linux/kexec.h>
+#include <linux/seq_file.h>
+#include <linux/of_platform.h>
+
+#include <asm/io.h>
+#include <asm/machdep.h>
+#include <asm/prom.h>
+#include <asm/time.h>
+#include <asm/udbg.h>
+
+#include "flipper-pic.h"
+#include "usbgecko_udbg.h"
+
+
+static void gamecube_spin(void)
+{
+        /* spin until power button pressed */
+        for (;;)
+                cpu_relax();
+}
+
+static void gamecube_restart(char *cmd)
+{
+        local_irq_disable();
+        flipper_platform_reset();
+        gamecube_spin();
+}
+
+static void gamecube_power_off(void)
+{
+        local_irq_disable();
+        gamecube_spin();
+}
+
+static void gamecube_halt(void)
+{
+        gamecube_restart(NULL);
+}
+
+static void __init gamecube_init_early(void)
+{
+        ug_udbg_init();
+}
+
+static int __init gamecube_probe(void)
+{
+        unsigned long dt_root;
+
+        dt_root = of_get_flat_dt_root();
+        if (!of_flat_dt_is_compatible(dt_root, "nintendo,gamecube"))
+                return 0;
+
+        return 1;
+}
+
+static void gamecube_shutdown(void)
+{
+        flipper_quiesce();
+}
+
+#ifdef CONFIG_KEXEC
+static int gamecube_kexec_prepare(struct kimage *image)
+{
+        return 0;
+}
+#endif /* CONFIG_KEXEC */
+
+
+define_machine(gamecube) {
+        .name                   = "gamecube",
+        .probe                  = gamecube_probe,
+        .init_early             = gamecube_init_early,
+        .restart                = gamecube_restart,
+        .power_off              = gamecube_power_off,
+        .halt                   = gamecube_halt,
+        .init_IRQ               = flipper_pic_probe,
+        .get_irq                = flipper_pic_get_irq,
+        .calibrate_decr         = generic_calibrate_decr,
+        .progress               = udbg_progress,
+        .machine_shutdown       = gamecube_shutdown,
+#ifdef CONFIG_KEXEC
+        .machine_kexec_prepare  = gamecube_kexec_prepare,
+#endif
+};
+
+
+static struct of_device_id gamecube_of_bus[] = {
+        { .compatible = "nintendo,flipper", },
+        { },
+};
+
+static int __init gamecube_device_probe(void)
+{
+        if (!machine_is(gamecube))
+                return 0;
+
+        of_platform_bus_probe(NULL, gamecube_of_bus, NULL);
+        return 0;
+}
+device_initcall(gamecube_device_probe);
+
diff --git a/arch/powerpc/platforms/embedded6xx/hlwd-pic.c b/arch/powerpc/platforms/embedded6xx/hlwd-pic.c
new file mode 100644
index 000000000000..dd20bff33207
--- /dev/null
+++ b/arch/powerpc/platforms/embedded6xx/hlwd-pic.c
@@ -0,0 +1,241 @@
+/*
+ * arch/powerpc/platforms/embedded6xx/hlwd-pic.c
+ *
+ * Nintendo Wii "Hollywood" interrupt controller support.
+ * Copyright (C) 2009 The GameCube Linux Team
+ * Copyright (C) 2009 Albert Herranz
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ */
+#define DRV_MODULE_NAME "hlwd-pic"
+#define pr_fmt(fmt) DRV_MODULE_NAME ": " fmt
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/irq.h>
+#include <linux/of.h>
+#include <asm/io.h>
+
+#include "hlwd-pic.h"
+
+#define HLWD_NR_IRQS    32
+
+/*
+ * Each interrupt has a corresponding bit in both
+ * the Interrupt Cause (ICR) and Interrupt Mask (IMR) registers.
+ *
+ * Enabling/disabling an interrupt line involves asserting/clearing
+ * the corresponding bit in IMR. ACK'ing a request simply involves
+ * asserting the corresponding bit in ICR.
+ */
+#define HW_BROADWAY_ICR         0x00
+#define HW_BROADWAY_IMR         0x04
+
+
+/*
+ * IRQ chip hooks.
+ *
+ */
+
+static void hlwd_pic_mask_and_ack(unsigned int virq)
+{
+        int irq = virq_to_hw(virq);
+        void __iomem *io_base = get_irq_chip_data(virq);
+        u32 mask = 1 << irq;
+
+        clrbits32(io_base + HW_BROADWAY_IMR, mask);
+        out_be32(io_base + HW_BROADWAY_ICR, mask);
+}
+
+static void hlwd_pic_ack(unsigned int virq)
+{
+        int irq = virq_to_hw(virq);
+        void __iomem *io_base = get_irq_chip_data(virq);
+
+        out_be32(io_base + HW_BROADWAY_ICR, 1 << irq);
+}
+
+static void hlwd_pic_mask(unsigned int virq)
+{
+        int irq = virq_to_hw(virq);
+        void __iomem *io_base = get_irq_chip_data(virq);
+
+        clrbits32(io_base + HW_BROADWAY_IMR, 1 << irq);
+}
+
+static void hlwd_pic_unmask(unsigned int virq)
+{
+        int irq = virq_to_hw(virq);
+        void __iomem *io_base = get_irq_chip_data(virq);
+
+        setbits32(io_base + HW_BROADWAY_IMR, 1 << irq);
+}
+
+
+static struct irq_chip hlwd_pic = {
+        .name           = "hlwd-pic",
+        .ack            = hlwd_pic_ack,
+        .mask_ack       = hlwd_pic_mask_and_ack,
+        .mask           = hlwd_pic_mask,
+        .unmask         = hlwd_pic_unmask,
+};
+
+/*
+ * IRQ host hooks.
+ *
+ */
+
+static struct irq_host *hlwd_irq_host;
+
+static int hlwd_pic_map(struct irq_host *h, unsigned int virq,
+                           irq_hw_number_t hwirq)
+{
+        set_irq_chip_data(virq, h->host_data);
+        get_irq_desc(virq)->status |= IRQ_LEVEL;
+        set_irq_chip_and_handler(virq, &hlwd_pic, handle_level_irq);
+        return 0;
+}
+
+static void hlwd_pic_unmap(struct irq_host *h, unsigned int irq)
+{
+        set_irq_chip_data(irq, NULL);
+        set_irq_chip(irq, NULL);
+}
+
+static struct irq_host_ops hlwd_irq_host_ops = {
+        .map = hlwd_pic_map,
+        .unmap = hlwd_pic_unmap,
+};
+
+static unsigned int __hlwd_pic_get_irq(struct irq_host *h)
+{
+        void __iomem *io_base = h->host_data;
+        int irq;
+        u32 irq_status;
+
+        irq_status = in_be32(io_base + HW_BROADWAY_ICR) &
+                     in_be32(io_base + HW_BROADWAY_IMR);
+        if (irq_status == 0)
+                return NO_IRQ;  /* no more IRQs pending */
+
+        irq = __ffs(irq_status);
+        return irq_linear_revmap(h, irq);
+}
+
+static void hlwd_pic_irq_cascade(unsigned int cascade_virq,
+                                      struct irq_desc *desc)
+{
+        struct irq_host *irq_host = get_irq_data(cascade_virq);
+        unsigned int virq;
+
+        spin_lock(&desc->lock);
+        desc->chip->mask(cascade_virq); /* IRQ_LEVEL */
+        spin_unlock(&desc->lock);
+
+        virq = __hlwd_pic_get_irq(irq_host);
+        if (virq != NO_IRQ)
+                generic_handle_irq(virq);
+        else
+                pr_err("spurious interrupt!\n");
+
+        spin_lock(&desc->lock);
+        desc->chip->ack(cascade_virq); /* IRQ_LEVEL */
+        if (!(desc->status & IRQ_DISABLED) && desc->chip->unmask)
+                desc->chip->unmask(cascade_virq);
+        spin_unlock(&desc->lock);
+}
+
+/*
+ * Platform hooks.
+ *
+ */
+
+static void __hlwd_quiesce(void __iomem *io_base)
+{
+        /* mask and ack all IRQs */
+        out_be32(io_base + HW_BROADWAY_IMR, 0);
+        out_be32(io_base + HW_BROADWAY_ICR, 0xffffffff);
+}
+
+struct irq_host *hlwd_pic_init(struct device_node *np)
+{
+        struct irq_host *irq_host;
+        struct resource res;
+        void __iomem *io_base;
+        int retval;
+
+        retval = of_address_to_resource(np, 0, &res);
+        if (retval) {
+                pr_err("no io memory range found\n");
+                return NULL;
+        }
+        io_base = ioremap(res.start, resource_size(&res));
+        if (!io_base) {
+                pr_err("ioremap failed\n");
+                return NULL;
+        }
+
+        pr_info("controller at 0x%08x mapped to 0x%p\n", res.start, io_base);
+
+        __hlwd_quiesce(io_base);
+
+        irq_host = irq_alloc_host(np, IRQ_HOST_MAP_LINEAR, HLWD_NR_IRQS,
+                                  &hlwd_irq_host_ops, -1);
+        if (!irq_host) {
+                pr_err("failed to allocate irq_host\n");
+                return NULL;
+        }
+        irq_host->host_data = io_base;
+
+        return irq_host;
+}
+
+unsigned int hlwd_pic_get_irq(void)
+{
+        return __hlwd_pic_get_irq(hlwd_irq_host);
+}
+
+/*
+ * Probe function.
+ *
+ */
+
+void hlwd_pic_probe(void)
+{
+        struct irq_host *host;
+        struct device_node *np;
+        const u32 *interrupts;
+        int cascade_virq;
+
+        for_each_compatible_node(np, NULL, "nintendo,hollywood-pic") {
+                interrupts = of_get_property(np, "interrupts", NULL);
+                if (interrupts) {
+                        host = hlwd_pic_init(np);
+                        BUG_ON(!host);
+                        cascade_virq = irq_of_parse_and_map(np, 0);
+                        set_irq_data(cascade_virq, host);
+                        set_irq_chained_handler(cascade_virq,
+                                                hlwd_pic_irq_cascade);
+                        hlwd_irq_host = host;
+                        break;
+                }
+        }
+}
+
+/**
+ * hlwd_quiesce() - quiesce hollywood irq controller
+ *
+ * Mask and ack all interrupt sources.
+ *
+ */
+void hlwd_quiesce(void)
+{
+        void __iomem *io_base = hlwd_irq_host->host_data;
+
+        __hlwd_quiesce(io_base);
+}
+
diff --git a/arch/powerpc/platforms/embedded6xx/hlwd-pic.h b/arch/powerpc/platforms/embedded6xx/hlwd-pic.h
new file mode 100644
index 000000000000..d2e5a092761e
--- /dev/null
+++ b/arch/powerpc/platforms/embedded6xx/hlwd-pic.h
@@ -0,0 +1,22 @@
+/*
+ * arch/powerpc/platforms/embedded6xx/hlwd-pic.h
+ *
+ * Nintendo Wii "Hollywood" interrupt controller support.
+ * Copyright (C) 2009 The GameCube Linux Team
+ * Copyright (C) 2009 Albert Herranz
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ */
+
+#ifndef __HLWD_PIC_H
+#define __HLWD_PIC_H
+
+extern unsigned int hlwd_pic_get_irq(void);
+extern void hlwd_pic_probe(void);
+extern void hlwd_quiesce(void);
+
+#endif
diff --git a/arch/powerpc/platforms/embedded6xx/usbgecko_udbg.c b/arch/powerpc/platforms/embedded6xx/usbgecko_udbg.c
new file mode 100644
index 000000000000..edc956cc8b13
--- /dev/null
+++ b/arch/powerpc/platforms/embedded6xx/usbgecko_udbg.c
@@ -0,0 +1,328 @@
+/*
+ * arch/powerpc/platforms/embedded6xx/usbgecko_udbg.c
+ *
+ * udbg serial input/output routines for the USB Gecko adapter.
+ * Copyright (C) 2008-2009 The GameCube Linux Team
+ * Copyright (C) 2008,2009 Albert Herranz
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ */
+
+#include <mm/mmu_decl.h>
+
+#include <asm/io.h>
+#include <asm/prom.h>
+#include <asm/udbg.h>
+#include <asm/fixmap.h>
+
+#include "usbgecko_udbg.h"
+
+
+#define EXI_CLK_32MHZ           5
+
+#define EXI_CSR                 0x00
+#define   EXI_CSR_CLKMASK       (0x7<<4)
+#define     EXI_CSR_CLK_32MHZ   (EXI_CLK_32MHZ<<4)
+#define   EXI_CSR_CSMASK        (0x7<<7)
+#define     EXI_CSR_CS_0        (0x1<<7)  /* Chip Select 001 */
+
+#define EXI_CR                  0x0c
+#define   EXI_CR_TSTART         (1<<0)
+#define   EXI_CR_WRITE          (1<<2)
+#define   EXI_CR_READ_WRITE     (2<<2)
+#define   EXI_CR_TLEN(len)      (((len)-1)<<4)
+
+#define EXI_DATA                0x10
+
+#define UG_READ_ATTEMPTS        100
+#define UG_WRITE_ATTEMPTS       100
+
+
+static void __iomem *ug_io_base;
+
+/*
+ * Performs one input/output transaction between the exi host and the usbgecko.
+ */
+static u32 ug_io_transaction(u32 in)
+{
+        u32 __iomem *csr_reg = ug_io_base + EXI_CSR;
+        u32 __iomem *data_reg = ug_io_base + EXI_DATA;
+        u32 __iomem *cr_reg = ug_io_base + EXI_CR;
+        u32 csr, data, cr;
+
+        /* select */
+        csr = EXI_CSR_CLK_32MHZ | EXI_CSR_CS_0;
+        out_be32(csr_reg, csr);
+
+        /* read/write */
+        data = in;
+        out_be32(data_reg, data);
+        cr = EXI_CR_TLEN(2) | EXI_CR_READ_WRITE | EXI_CR_TSTART;
+        out_be32(cr_reg, cr);
+
+        while (in_be32(cr_reg) & EXI_CR_TSTART)
+                barrier();
+
+        /* deselect */
+        out_be32(csr_reg, 0);
+
+        /* result */
+        data = in_be32(data_reg);
+
+        return data;
+}
+
+/*
+ * Returns true if an usbgecko adapter is found.
+ */
+static int ug_is_adapter_present(void)
+{
+        if (!ug_io_base)
+                return 0;
+
+        return ug_io_transaction(0x90000000) == 0x04700000;
+}
+
+/*
+ * Returns true if the TX fifo is ready for transmission.
+ */
+static int ug_is_txfifo_ready(void)
+{
+        return ug_io_transaction(0xc0000000) & 0x04000000;
+}
+
+/*
+ * Tries to transmit a character.
+ * If the TX fifo is not ready the result is undefined.
+ */
+static void ug_raw_putc(char ch)
+{
+        ug_io_transaction(0xb0000000 | (ch << 20));
+}
+
+/*
+ * Transmits a character.
+ * It silently fails if the TX fifo is not ready after a number of retries.
+ */
+static void ug_putc(char ch)
+{
+        int count = UG_WRITE_ATTEMPTS;
+
+        if (!ug_io_base)
+                return;
+
+        if (ch == '\n')
+                ug_putc('\r');
+
+        while (!ug_is_txfifo_ready() && count--)
+                barrier();
+        if (count)
+                ug_raw_putc(ch);
+}
+
+/*
+ * Returns true if the RX fifo is ready for transmission.
+ */
+static int ug_is_rxfifo_ready(void)
+{
+        return ug_io_transaction(0xd0000000) & 0x04000000;
+}
+
+/*
+ * Tries to receive a character.
+ * If a character is unavailable the function returns -1.
+ */
+static int ug_raw_getc(void)
+{
+        u32 data = ug_io_transaction(0xa0000000);
+        if (data & 0x08000000)
+                return (data >> 16) & 0xff;
+        else
+                return -1;
+}
+
+/*
+ * Receives a character.
+ * It fails if the RX fifo is not ready after a number of retries.
+ */
+static int ug_getc(void)
+{
+        int count = UG_READ_ATTEMPTS;
+
+        if (!ug_io_base)
+                return -1;
+
+        while (!ug_is_rxfifo_ready() && count--)
+                barrier();
+        return ug_raw_getc();
+}
+
+/*
+ * udbg functions.
+ *
+ */
+
+/*
+ * Transmits a character.
+ */
+void ug_udbg_putc(char ch)
+{
+        ug_putc(ch);
+}
+
+/*
+ * Receives a character. Waits until a character is available.
+ */
+static int ug_udbg_getc(void)
+{
+        int ch;
+
+        while ((ch = ug_getc()) == -1)
+                barrier();
+        return ch;
+}
+
+/*
+ * Receives a character. If a character is not available, returns -1.
+ */
+static int ug_udbg_getc_poll(void)
+{
+        if (!ug_is_rxfifo_ready())
+                return -1;
+        return ug_getc();
+}
+
+/*
+ * Retrieves and prepares the virtual address needed to access the hardware.
+ */
+static void __iomem *ug_udbg_setup_exi_io_base(struct device_node *np)
+{
+        void __iomem *exi_io_base = NULL;
+        phys_addr_t paddr;
+        const unsigned int *reg;
+
+        reg = of_get_property(np, "reg", NULL);
+        if (reg) {
+                paddr = of_translate_address(np, reg);
+                if (paddr)
+                        exi_io_base = ioremap(paddr, reg[1]);
+        }
+        return exi_io_base;
+}
+
+/*
+ * Checks if a USB Gecko adapter is inserted in any memory card slot.
+ */
+static void __iomem *ug_udbg_probe(void __iomem *exi_io_base)
+{
+        int i;
+
+        /* look for a usbgecko on memcard slots A and B */
+        for (i = 0; i < 2; i++) {
+                ug_io_base = exi_io_base + 0x14 * i;
+                if (ug_is_adapter_present())
+                        break;
+        }
+        if (i == 2)
+                ug_io_base = NULL;
+        return ug_io_base;
+
+}
+
+/*
+ * USB Gecko udbg support initialization.
+ */
+void __init ug_udbg_init(void)
+{
+        struct device_node *np;
+        void __iomem *exi_io_base;
+
+        if (ug_io_base)
+                udbg_printf("%s: early -> final\n", __func__);
+
+        np = of_find_compatible_node(NULL, NULL, "nintendo,flipper-exi");
+        if (!np) {
+                udbg_printf("%s: EXI node not found\n", __func__);
+                goto done;
+        }
+
+        exi_io_base = ug_udbg_setup_exi_io_base(np);
+        if (!exi_io_base) {
+                udbg_printf("%s: failed to setup EXI io base\n", __func__);
+                goto done;
+        }
+
+        if (!ug_udbg_probe(exi_io_base)) {
+                udbg_printf("usbgecko_udbg: not found\n");
+                iounmap(exi_io_base);
+        } else {
+                udbg_putc = ug_udbg_putc;
+                udbg_getc = ug_udbg_getc;
+                udbg_getc_poll = ug_udbg_getc_poll;
+                udbg_printf("usbgecko_udbg: ready\n");
+        }
+
+done:
+        if (np)
+                of_node_put(np);
+        return;
+}
+
+#ifdef CONFIG_PPC_EARLY_DEBUG_USBGECKO
+
+static phys_addr_t __init ug_early_grab_io_addr(void)
+{
+#if defined(CONFIG_GAMECUBE)
+        return 0x0c000000;
+#elif defined(CONFIG_WII)
+        return 0x0d000000;
+#else
+#error Invalid platform for USB Gecko based early debugging.
+#endif
+}
+
+/*
+ * USB Gecko early debug support initialization for udbg.
+ */
+void __init udbg_init_usbgecko(void)
+{
+        void __iomem *early_debug_area;
+        void __iomem *exi_io_base;
+
+        /*
+         * At this point we have a BAT already setup that enables I/O
+         * to the EXI hardware.
+         *
+         * The BAT uses a virtual address range reserved at the fixmap.
+         * This must match the virtual address configured in
+         * head_32.S:setup_usbgecko_bat().
+         */
+        early_debug_area = (void __iomem *)__fix_to_virt(FIX_EARLY_DEBUG_BASE);
+        exi_io_base = early_debug_area + 0x00006800;
+
+        /* try to detect a USB Gecko */
+        if (!ug_udbg_probe(exi_io_base))
+                return;
+
+        /* we found a USB Gecko, load udbg hooks */
+        udbg_putc = ug_udbg_putc;
+        udbg_getc = ug_udbg_getc;
+        udbg_getc_poll = ug_udbg_getc_poll;
+
+        /*
+         * Prepare again the same BAT for MMU_init.
+         * This allows udbg I/O to continue working after the MMU is
+         * turned on for real.
+         * It is safe to continue using the same virtual address as it is
+         * a reserved fixmap area.
+         */
+        setbat(1, (unsigned long)early_debug_area,
+               ug_early_grab_io_addr(), 128*1024, PAGE_KERNEL_NCG);
+}
+
+#endif /* CONFIG_PPC_EARLY_DEBUG_USBGECKO */
+
diff --git a/arch/powerpc/platforms/embedded6xx/usbgecko_udbg.h b/arch/powerpc/platforms/embedded6xx/usbgecko_udbg.h
new file mode 100644
index 000000000000..bb6cde4ad764
--- /dev/null
+++ b/arch/powerpc/platforms/embedded6xx/usbgecko_udbg.h
@@ -0,0 +1,32 @@
+/*
+ * arch/powerpc/platforms/embedded6xx/usbgecko_udbg.h
+ *
+ * udbg serial input/output routines for the USB Gecko adapter.
+ * Copyright (C) 2008-2009 The GameCube Linux Team
+ * Copyright (C) 2008,2009 Albert Herranz
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ */
+
+#ifndef __USBGECKO_UDBG_H
+#define __USBGECKO_UDBG_H
+
+#ifdef CONFIG_USBGECKO_UDBG
+
+extern void __init ug_udbg_init(void);
+
+#else
+
+static inline void __init ug_udbg_init(void)
+{
+}
+
+#endif /* CONFIG_USBGECKO_UDBG */
+
+void __init udbg_init_usbgecko(void);
+
+#endif /* __USBGECKO_UDBG_H */
diff --git a/arch/powerpc/platforms/embedded6xx/wii.c b/arch/powerpc/platforms/embedded6xx/wii.c
new file mode 100644
index 000000000000..57e5b608fa1a
--- /dev/null
+++ b/arch/powerpc/platforms/embedded6xx/wii.c
@@ -0,0 +1,268 @@
+/*
+ * arch/powerpc/platforms/embedded6xx/wii.c
+ *
+ * Nintendo Wii board-specific support
+ * Copyright (C) 2008-2009 The GameCube Linux Team
+ * Copyright (C) 2008,2009 Albert Herranz
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ */
+#define DRV_MODULE_NAME "wii"
+#define pr_fmt(fmt) DRV_MODULE_NAME ": " fmt
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/irq.h>
+#include <linux/seq_file.h>
+#include <linux/kexec.h>
+#include <linux/of_platform.h>
+#include <linux/lmb.h>
+#include <mm/mmu_decl.h>
+
+#include <asm/io.h>
+#include <asm/machdep.h>
+#include <asm/prom.h>
+#include <asm/time.h>
+#include <asm/udbg.h>
+
+#include "flipper-pic.h"
+#include "hlwd-pic.h"
+#include "usbgecko_udbg.h"
+
+/* control block */
+#define HW_CTRL_COMPATIBLE      "nintendo,hollywood-control"
+
+#define HW_CTRL_RESETS          0x94
+#define HW_CTRL_RESETS_SYS      (1<<0)
+
+/* gpio */
+#define HW_GPIO_COMPATIBLE      "nintendo,hollywood-gpio"
+
+#define HW_GPIO_BASE(idx)       (idx * 0x20)
+#define HW_GPIO_OUT(idx)        (HW_GPIO_BASE(idx) + 0)
+#define HW_GPIO_DIR(idx)        (HW_GPIO_BASE(idx) + 4)
+
+#define HW_GPIO_SHUTDOWN        (1<<1)
+#define HW_GPIO_SLOT_LED        (1<<5)
+#define HW_GPIO_SENSOR_BAR      (1<<8)
+
+
+static void __iomem *hw_ctrl;
+static void __iomem *hw_gpio;
+
+unsigned long wii_hole_start;
+unsigned long wii_hole_size;
+
+
+static int __init page_aligned(unsigned long x)
+{
+        return !(x & (PAGE_SIZE-1));
+}
+
+void __init wii_memory_fixups(void)
+{
+        struct lmb_property *p = lmb.memory.region;
+
+        /*
+         * This is part of a workaround to allow the use of two
+         * discontiguous RAM ranges on the Wii, even if this is
+         * currently unsupported on 32-bit PowerPC Linux.
+         *
+         * We coealesce the two memory ranges of the Wii into a
+         * single range, then create a reservation for the "hole"
+         * between both ranges.
+         */
+
+        BUG_ON(lmb.memory.cnt != 2);
+        BUG_ON(!page_aligned(p[0].base) || !page_aligned(p[1].base));
+
+        p[0].size = _ALIGN_DOWN(p[0].size, PAGE_SIZE);
+        p[1].size = _ALIGN_DOWN(p[1].size, PAGE_SIZE);
+
+        wii_hole_start = p[0].base + p[0].size;
+        wii_hole_size = p[1].base - wii_hole_start;
+
+        pr_info("MEM1: <%08llx %08llx>\n", p[0].base, p[0].size);
+        pr_info("HOLE: <%08lx %08lx>\n", wii_hole_start, wii_hole_size);
+        pr_info("MEM2: <%08llx %08llx>\n", p[1].base, p[1].size);
+
+        p[0].size += wii_hole_size + p[1].size;
+
+        lmb.memory.cnt = 1;
+        lmb_analyze();
+
+        /* reserve the hole */
+        lmb_reserve(wii_hole_start, wii_hole_size);
+
+        /* allow ioremapping the address space in the hole */
+        __allow_ioremap_reserved = 1;
+}
+
+unsigned long __init wii_mmu_mapin_mem2(unsigned long top)
+{
+        unsigned long delta, size, bl;
+        unsigned long max_size = (256<<20);
+
+        /* MEM2 64MB@0x10000000 */
+        delta = wii_hole_start + wii_hole_size;
+        size = top - delta;
+        for (bl = 128<<10; bl < max_size; bl <<= 1) {
+                if (bl * 2 > size)
+                        break;
+        }
+        setbat(4, PAGE_OFFSET+delta, delta, bl, PAGE_KERNEL_X);
+        return delta + bl;
+}
+
+static void wii_spin(void)
+{
+        local_irq_disable();
+        for (;;)
+                cpu_relax();
+}
+
+static void __iomem *wii_ioremap_hw_regs(char *name, char *compatible)
+{
+        void __iomem *hw_regs = NULL;
+        struct device_node *np;
+        struct resource res;
+        int error = -ENODEV;
+
+        np = of_find_compatible_node(NULL, NULL, compatible);
+        if (!np) {
+                pr_err("no compatible node found for %s\n", compatible);
+                goto out;
+        }
+        error = of_address_to_resource(np, 0, &res);
+        if (error) {
+                pr_err("no valid reg found for %s\n", np->name);
+                goto out_put;
+        }
+
+        hw_regs = ioremap(res.start, resource_size(&res));
+        if (hw_regs) {
+                pr_info("%s at 0x%08x mapped to 0x%p\n", name,
+                        res.start, hw_regs);
+        }
+
+out_put:
+        of_node_put(np);
+out:
+        return hw_regs;
+}
+
+static void __init wii_setup_arch(void)
+{
+        hw_ctrl = wii_ioremap_hw_regs("hw_ctrl", HW_CTRL_COMPATIBLE);
+        hw_gpio = wii_ioremap_hw_regs("hw_gpio", HW_GPIO_COMPATIBLE);
+        if (hw_gpio) {
+                /* turn off the front blue led and IR light */
+                clrbits32(hw_gpio + HW_GPIO_OUT(0),
+                          HW_GPIO_SLOT_LED | HW_GPIO_SENSOR_BAR);
+        }
+}
+
+static void wii_restart(char *cmd)
+{
+        local_irq_disable();
+
+        if (hw_ctrl) {
+                /* clear the system reset pin to cause a reset */
+                clrbits32(hw_ctrl + HW_CTRL_RESETS, HW_CTRL_RESETS_SYS);
+        }
+        wii_spin();
+}
+
+static void wii_power_off(void)
+{
+        local_irq_disable();
+
+        if (hw_gpio) {
+                /* make sure that the poweroff GPIO is configured as output */
+                setbits32(hw_gpio + HW_GPIO_DIR(1), HW_GPIO_SHUTDOWN);
+
+                /* drive the poweroff GPIO high */
+                setbits32(hw_gpio + HW_GPIO_OUT(1), HW_GPIO_SHUTDOWN);
+        }
+        wii_spin();
+}
+
+static void wii_halt(void)
+{
+        if (ppc_md.restart)
+                ppc_md.restart(NULL);
+        wii_spin();
+}
+
+static void __init wii_init_early(void)
+{
+        ug_udbg_init();
+}
+
+static void __init wii_pic_probe(void)
+{
+        flipper_pic_probe();
+        hlwd_pic_probe();
+}
+
+static int __init wii_probe(void)
+{
+        unsigned long dt_root;
+
+        dt_root = of_get_flat_dt_root();
+        if (!of_flat_dt_is_compatible(dt_root, "nintendo,wii"))
+                return 0;
+
+        return 1;
+}
+
+static void wii_shutdown(void)
+{
+        hlwd_quiesce();
+        flipper_quiesce();
+}
+
+#ifdef CONFIG_KEXEC
+static int wii_machine_kexec_prepare(struct kimage *image)
+{
+        return 0;
+}
+#endif /* CONFIG_KEXEC */
+
+define_machine(wii) {
+        .name                   = "wii",
+        .probe                  = wii_probe,
+        .init_early             = wii_init_early,
+        .setup_arch             = wii_setup_arch,
+        .restart                = wii_restart,
+        .power_off              = wii_power_off,
+        .halt                   = wii_halt,
+        .init_IRQ               = wii_pic_probe,
+        .get_irq                = flipper_pic_get_irq,
+        .calibrate_decr         = generic_calibrate_decr,
+        .progress               = udbg_progress,
+        .machine_shutdown       = wii_shutdown,
+#ifdef CONFIG_KEXEC
+        .machine_kexec_prepare  = wii_machine_kexec_prepare,
+#endif
+};
+
+static struct of_device_id wii_of_bus[] = {
+        { .compatible = "nintendo,hollywood", },
+        { },
+};
+
+static int __init wii_device_probe(void)
+{
+        if (!machine_is(wii))
+                return 0;
+
+        of_platform_bus_probe(NULL, wii_of_bus, NULL);
+        return 0;
+}
+device_initcall(wii_device_probe);
+
diff --git a/arch/powerpc/platforms/iseries/htab.c b/arch/powerpc/platforms/iseries/htab.c
index f99c6c4b6985..3ae66ab9d5e7 100644
--- a/arch/powerpc/platforms/iseries/htab.c
+++ b/arch/powerpc/platforms/iseries/htab.c
@@ -19,8 +19,7 @@
 
 #include "call_hpt.h"
 
-static spinlock_t iSeries_hlocks[64] __cacheline_aligned_in_smp =
-        { [0 ... 63] = SPIN_LOCK_UNLOCKED};
+static spinlock_t iSeries_hlocks[64] __cacheline_aligned_in_smp;
 
 /*
  * Very primitive algorithm for picking up a lock
@@ -245,6 +244,11 @@ static void iSeries_hpte_invalidate(unsigned long slot, unsigned long va,
 
 void __init hpte_init_iSeries(void)
 {
+        int i;
+
+        for (i = 0; i < ARRAY_SIZE(iSeries_hlocks); i++)
+                spin_lock_init(&iSeries_hlocks[i]);
+
         ppc_md.hpte_invalidate  = iSeries_hpte_invalidate;
         ppc_md.hpte_updatepp    = iSeries_hpte_updatepp;
         ppc_md.hpte_updateboltedpp = iSeries_hpte_updateboltedpp;
diff --git a/arch/powerpc/platforms/iseries/irq.c b/arch/powerpc/platforms/iseries/irq.c
index 94f444758836..86c4b29eea89 100644
--- a/arch/powerpc/platforms/iseries/irq.c
+++ b/arch/powerpc/platforms/iseries/irq.c
@@ -214,12 +214,12 @@ void __init iSeries_activate_IRQs()
         unsigned long flags;
 
         for_each_irq (irq) {
-                struct irq_desc *desc = get_irq_desc(irq);
+                struct irq_desc *desc = irq_to_desc(irq);
 
                 if (desc && desc->chip && desc->chip->startup) {
-                        spin_lock_irqsave(&desc->lock, flags);
+                        raw_spin_lock_irqsave(&desc->lock, flags);
                         desc->chip->startup(irq);
-                        spin_unlock_irqrestore(&desc->lock, flags);
+                        raw_spin_unlock_irqrestore(&desc->lock, flags);
                 }
         }
 }
@@ -273,7 +273,7 @@ static void iseries_end_IRQ(unsigned int irq)
 }
 
 static struct irq_chip iseries_pic = {
-        .typename       = "iSeries irq controller",
+        .name   = "iSeries irq controller",
         .startup        = iseries_startup_IRQ,
         .shutdown       = iseries_shutdown_IRQ,
         .unmask         = iseries_enable_IRQ,
diff --git a/arch/powerpc/platforms/pasemi/setup.c b/arch/powerpc/platforms/pasemi/setup.c
index a4619347aa7e..242f8095c2df 100644
--- a/arch/powerpc/platforms/pasemi/setup.c
+++ b/arch/powerpc/platforms/pasemi/setup.c
@@ -71,7 +71,7 @@ static void pas_restart(char *cmd)
 }
 
 #ifdef CONFIG_SMP
-static raw_spinlock_t timebase_lock;
+static arch_spinlock_t timebase_lock;
 static unsigned long timebase;
 
 static void __devinit pas_give_timebase(void)
@@ -80,11 +80,11 @@ static void __devinit pas_give_timebase(void)
 
         local_irq_save(flags);
         hard_irq_disable();
-        __raw_spin_lock(&timebase_lock);
+        arch_spin_lock(&timebase_lock);
         mtspr(SPRN_TBCTL, TBCTL_FREEZE);
         isync();
         timebase = get_tb();
-        __raw_spin_unlock(&timebase_lock);
+        arch_spin_unlock(&timebase_lock);
 
         while (timebase)
                 barrier();
@@ -97,10 +97,10 @@ static void __devinit pas_take_timebase(void)
         while (!timebase)
                 smp_rmb();
 
-        __raw_spin_lock(&timebase_lock);
+        arch_spin_lock(&timebase_lock);
         set_tb(timebase >> 32, timebase & 0xffffffff);
         timebase = 0;
-        __raw_spin_unlock(&timebase_lock);
+        arch_spin_unlock(&timebase_lock);
 }
 
 struct smp_ops_t pas_smp_ops = {
diff --git a/arch/powerpc/platforms/powermac/bootx_init.c b/arch/powerpc/platforms/powermac/bootx_init.c
index cf660916ae0b..9dd789a7370d 100644
--- a/arch/powerpc/platforms/powermac/bootx_init.c
+++ b/arch/powerpc/platforms/powermac/bootx_init.c
@@ -12,7 +12,7 @@
 #include <linux/kernel.h>
 #include <linux/string.h>
 #include <linux/init.h>
-#include <linux/utsrelease.h>
+#include <generated/utsrelease.h>
 #include <asm/sections.h>
 #include <asm/prom.h>
 #include <asm/page.h>
diff --git a/arch/powerpc/platforms/powermac/pic.c b/arch/powerpc/platforms/powermac/pic.c
index d212006a5b3c..09e827296276 100644
--- a/arch/powerpc/platforms/powermac/pic.c
+++ b/arch/powerpc/platforms/powermac/pic.c
@@ -152,12 +152,12 @@ static unsigned int pmac_startup_irq(unsigned int virq)
         unsigned long bit = 1UL << (src & 0x1f);
         int i = src >> 5;
 
-        spin_lock_irqsave(&pmac_pic_lock, flags);
-        if ((irq_desc[virq].status & IRQ_LEVEL) == 0)
+        spin_lock_irqsave(&pmac_pic_lock, flags);
+        if ((irq_to_desc(virq)->status & IRQ_LEVEL) == 0)
                 out_le32(&pmac_irq_hw[i]->ack, bit);
         __set_bit(src, ppc_cached_irq_mask);
         __pmac_set_irq_mask(src, 0);
-        spin_unlock_irqrestore(&pmac_pic_lock, flags);
+        spin_unlock_irqrestore(&pmac_pic_lock, flags);
 
         return 0;
 }
@@ -195,7 +195,7 @@ static int pmac_retrigger(unsigned int virq)
 }
 
 static struct irq_chip pmac_pic = {
-        .typename       = " PMAC-PIC ",
+        .name           = " PMAC-PIC ",
         .startup        = pmac_startup_irq,
         .mask           = pmac_mask_irq,
         .ack            = pmac_ack_irq,
@@ -285,7 +285,7 @@ static int pmac_pic_host_match(struct irq_host *h, struct device_node *node)
 static int pmac_pic_host_map(struct irq_host *h, unsigned int virq,
                              irq_hw_number_t hw)
 {
-        struct irq_desc *desc = get_irq_desc(virq);
+        struct irq_desc *desc = irq_to_desc(virq);
         int level;
 
         if (hw >= max_irqs)
@@ -303,7 +303,7 @@ static int pmac_pic_host_map(struct irq_host *h, unsigned int virq,
 }
 
 static int pmac_pic_host_xlate(struct irq_host *h, struct device_node *ct,
-                               u32 *intspec, unsigned int intsize,
+                               const u32 *intspec, unsigned int intsize,
                                irq_hw_number_t *out_hwirq,
                                unsigned int *out_flags)
 
diff --git a/arch/powerpc/platforms/ps3/interrupt.c b/arch/powerpc/platforms/ps3/interrupt.c
index 8ec5ccf76b19..59d9712d7364 100644
--- a/arch/powerpc/platforms/ps3/interrupt.c
+++ b/arch/powerpc/platforms/ps3/interrupt.c
@@ -152,7 +152,7 @@ static void ps3_chip_eoi(unsigned int virq)
  */
 
 static struct irq_chip ps3_irq_chip = {
-        .typename = "ps3",
+        .name = "ps3",
         .mask = ps3_chip_mask,
         .unmask = ps3_chip_unmask,
         .eoi = ps3_chip_eoi,
diff --git a/arch/powerpc/platforms/ps3/mm.c b/arch/powerpc/platforms/ps3/mm.c
index 189a25b80735..e81b028a2a48 100644
--- a/arch/powerpc/platforms/ps3/mm.c
+++ b/arch/powerpc/platforms/ps3/mm.c
@@ -34,7 +34,7 @@
 #if defined(DEBUG)
 #define DBG udbg_printf
 #else
-#define DBG pr_debug
+#define DBG pr_devel
 #endif
 
 enum {
diff --git a/arch/powerpc/platforms/pseries/Kconfig b/arch/powerpc/platforms/pseries/Kconfig
index f0e6f28427bd..27554c807fd5 100644
--- a/arch/powerpc/platforms/pseries/Kconfig
+++ b/arch/powerpc/platforms/pseries/Kconfig
@@ -4,6 +4,7 @@ config PPC_PSERIES
         select MPIC
         select PPC_I8259
         select PPC_RTAS
+        select PPC_RTAS_DAEMON
         select RTAS_ERROR_LOGGING
         select PPC_UDBG_16550
         select PPC_NATIVE
@@ -59,7 +60,7 @@ config PPC_SMLPAR
 
 config CMM
         tristate "Collaborative memory management"
-        depends on PPC_SMLPAR && !CRASH_DUMP
+        depends on PPC_SMLPAR
         default y
         help
           Select this option, if you want to enable the kernel interface
diff --git a/arch/powerpc/platforms/pseries/Makefile b/arch/powerpc/platforms/pseries/Makefile
index 790c0b872d4f..0ff5174ae4f5 100644
--- a/arch/powerpc/platforms/pseries/Makefile
+++ b/arch/powerpc/platforms/pseries/Makefile
@@ -7,8 +7,8 @@ EXTRA_CFLAGS		+= -DDEBUG
 endif
 
 obj-y                   := lpar.o hvCall.o nvram.o reconfig.o \
-                           setup.o iommu.o ras.o rtasd.o \
-                           firmware.o power.o
+                           setup.o iommu.o ras.o \
+                           firmware.o power.o dlpar.o
 obj-$(CONFIG_SMP)       += smp.o
 obj-$(CONFIG_XICS)      += xics.o
 obj-$(CONFIG_SCANLOG)   += scanlog.o
diff --git a/arch/powerpc/platforms/pseries/cmm.c b/arch/powerpc/platforms/pseries/cmm.c
index 6567439fe78d..bcdcf0ccc8d7 100644
--- a/arch/powerpc/platforms/pseries/cmm.c
+++ b/arch/powerpc/platforms/pseries/cmm.c
@@ -229,8 +229,9 @@ static void cmm_get_mpp(void)
 {
         int rc;
         struct hvcall_mpp_data mpp_data;
-        unsigned long active_pages_target;
-        signed long page_loan_request;
+        signed long active_pages_target, page_loan_request, target;
+        signed long total_pages = totalram_pages + loaned_pages;
+        signed long min_mem_pages = (min_mem_mb * 1024 * 1024) / PAGE_SIZE;
 
         rc = h_get_mpp(&mpp_data);
 
@@ -238,17 +239,25 @@ static void cmm_get_mpp(void)
                 return;
 
         page_loan_request = div_s64((s64)mpp_data.loan_request, PAGE_SIZE);
-        loaned_pages_target = page_loan_request + loaned_pages;
-        if (loaned_pages_target > oom_freed_pages)
-                loaned_pages_target -= oom_freed_pages;
+        target = page_loan_request + (signed long)loaned_pages;
+
+        if (target < 0 || total_pages < min_mem_pages)
+                target = 0;
+
+        if (target > oom_freed_pages)
+                target -= oom_freed_pages;
         else
-                loaned_pages_target = 0;
+                target = 0;
+
+        active_pages_target = total_pages - target;
+
+        if (min_mem_pages > active_pages_target)
+                target = total_pages - min_mem_pages;
 
-        active_pages_target = totalram_pages + loaned_pages - loaned_pages_target;
+        if (target < 0)
+                target = 0;
 
-        if ((min_mem_mb * 1024 * 1024) > (active_pages_target * PAGE_SIZE))
-                loaned_pages_target = totalram_pages + loaned_pages -
-                        ((min_mem_mb * 1024 * 1024) / PAGE_SIZE);
+        loaned_pages_target = target;
 
         cmm_dbg("delta = %ld, loaned = %lu, target = %lu, oom = %lu, totalram = %lu\n",
                 page_loan_request, loaned_pages, loaned_pages_target,
diff --git a/arch/powerpc/platforms/pseries/dlpar.c b/arch/powerpc/platforms/pseries/dlpar.c
new file mode 100644
index 000000000000..12df9e8812a9
--- /dev/null
+++ b/arch/powerpc/platforms/pseries/dlpar.c
@@ -0,0 +1,558 @@
+/*
+ * Support for dynamic reconfiguration for PCI, Memory, and CPU
+ * Hotplug and Dynamic Logical Partitioning on RPA platforms.
+ *
+ * Copyright (C) 2009 Nathan Fontenot
+ * Copyright (C) 2009 IBM Corporation
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License version
+ * 2 as published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/kref.h>
+#include <linux/notifier.h>
+#include <linux/proc_fs.h>
+#include <linux/spinlock.h>
+#include <linux/cpu.h>
+#include "offline_states.h"
+
+#include <asm/prom.h>
+#include <asm/machdep.h>
+#include <asm/uaccess.h>
+#include <asm/rtas.h>
+#include <asm/pSeries_reconfig.h>
+
+struct cc_workarea {
+        u32     drc_index;
+        u32     zero;
+        u32     name_offset;
+        u32     prop_length;
+        u32     prop_offset;
+};
+
+static void dlpar_free_cc_property(struct property *prop)
+{
+        kfree(prop->name);
+        kfree(prop->value);
+        kfree(prop);
+}
+
+static struct property *dlpar_parse_cc_property(struct cc_workarea *ccwa)
+{
+        struct property *prop;
+        char *name;
+        char *value;
+
+        prop = kzalloc(sizeof(*prop), GFP_KERNEL);
+        if (!prop)
+                return NULL;
+
+        name = (char *)ccwa + ccwa->name_offset;
+        prop->name = kstrdup(name, GFP_KERNEL);
+
+        prop->length = ccwa->prop_length;
+        value = (char *)ccwa + ccwa->prop_offset;
+        prop->value = kzalloc(prop->length, GFP_KERNEL);
+        if (!prop->value) {
+                dlpar_free_cc_property(prop);
+                return NULL;
+        }
+
+        memcpy(prop->value, value, prop->length);
+        return prop;
+}
+
+static struct device_node *dlpar_parse_cc_node(struct cc_workarea *ccwa)
+{
+        struct device_node *dn;
+        char *name;
+
+        dn = kzalloc(sizeof(*dn), GFP_KERNEL);
+        if (!dn)
+                return NULL;
+
+        /* The configure connector reported name does not contain a
+         * preceeding '/', so we allocate a buffer large enough to
+         * prepend this to the full_name.
+         */
+        name = (char *)ccwa + ccwa->name_offset;
+        dn->full_name = kmalloc(strlen(name) + 2, GFP_KERNEL);
+        if (!dn->full_name) {
+                kfree(dn);
+                return NULL;
+        }
+
+        sprintf(dn->full_name, "/%s", name);
+        return dn;
+}
+
+static void dlpar_free_one_cc_node(struct device_node *dn)
+{
+        struct property *prop;
+
+        while (dn->properties) {
+                prop = dn->properties;
+                dn->properties = prop->next;
+                dlpar_free_cc_property(prop);
+        }
+
+        kfree(dn->full_name);
+        kfree(dn);
+}
+
+static void dlpar_free_cc_nodes(struct device_node *dn)
+{
+        if (dn->child)
+                dlpar_free_cc_nodes(dn->child);
+
+        if (dn->sibling)
+                dlpar_free_cc_nodes(dn->sibling);
+
+        dlpar_free_one_cc_node(dn);
+}
+
+#define NEXT_SIBLING    1
+#define NEXT_CHILD      2
+#define NEXT_PROPERTY   3
+#define PREV_PARENT     4
+#define MORE_MEMORY     5
+#define CALL_AGAIN      -2
+#define ERR_CFG_USE     -9003
+
+struct device_node *dlpar_configure_connector(u32 drc_index)
+{
+        struct device_node *dn;
+        struct device_node *first_dn = NULL;
+        struct device_node *last_dn = NULL;
+        struct property *property;
+        struct property *last_property = NULL;
+        struct cc_workarea *ccwa;
+        int cc_token;
+        int rc;
+
+        cc_token = rtas_token("ibm,configure-connector");
+        if (cc_token == RTAS_UNKNOWN_SERVICE)
+                return NULL;
+
+        spin_lock(&rtas_data_buf_lock);
+        ccwa = (struct cc_workarea *)&rtas_data_buf[0];
+        ccwa->drc_index = drc_index;
+        ccwa->zero = 0;
+
+        rc = rtas_call(cc_token, 2, 1, NULL, rtas_data_buf, NULL);
+        while (rc) {
+                switch (rc) {
+                case NEXT_SIBLING:
+                        dn = dlpar_parse_cc_node(ccwa);
+                        if (!dn)
+                                goto cc_error;
+
+                        dn->parent = last_dn->parent;
+                        last_dn->sibling = dn;
+                        last_dn = dn;
+                        break;
+
+                case NEXT_CHILD:
+                        dn = dlpar_parse_cc_node(ccwa);
+                        if (!dn)
+                                goto cc_error;
+
+                        if (!first_dn)
+                                first_dn = dn;
+                        else {
+                                dn->parent = last_dn;
+                                if (last_dn)
+                                        last_dn->child = dn;
+                        }
+
+                        last_dn = dn;
+                        break;
+
+                case NEXT_PROPERTY:
+                        property = dlpar_parse_cc_property(ccwa);
+                        if (!property)
+                                goto cc_error;
+
+                        if (!last_dn->properties)
+                                last_dn->properties = property;
+                        else
+                                last_property->next = property;
+
+                        last_property = property;
+                        break;
+
+                case PREV_PARENT:
+                        last_dn = last_dn->parent;
+                        break;
+
+                case CALL_AGAIN:
+                        break;
+
+                case MORE_MEMORY:
+                case ERR_CFG_USE:
+                default:
+                        printk(KERN_ERR "Unexpected Error (%d) "
+                               "returned from configure-connector\n", rc);
+                        goto cc_error;
+                }
+
+                rc = rtas_call(cc_token, 2, 1, NULL, rtas_data_buf, NULL);
+        }
+
+        spin_unlock(&rtas_data_buf_lock);
+        return first_dn;
+
+cc_error:
+        if (first_dn)
+                dlpar_free_cc_nodes(first_dn);
+        spin_unlock(&rtas_data_buf_lock);
+        return NULL;
+}
+
+static struct device_node *derive_parent(const char *path)
+{
+        struct device_node *parent;
+        char *last_slash;
+
+        last_slash = strrchr(path, '/');
+        if (last_slash == path) {
+                parent = of_find_node_by_path("/");
+        } else {
+                char *parent_path;
+                int parent_path_len = last_slash - path + 1;
+                parent_path = kmalloc(parent_path_len, GFP_KERNEL);
+                if (!parent_path)
+                        return NULL;
+
+                strlcpy(parent_path, path, parent_path_len);
+                parent = of_find_node_by_path(parent_path);
+                kfree(parent_path);
+        }
+
+        return parent;
+}
+
+int dlpar_attach_node(struct device_node *dn)
+{
+        struct proc_dir_entry *ent;
+        int rc;
+
+        of_node_set_flag(dn, OF_DYNAMIC);
+        kref_init(&dn->kref);
+        dn->parent = derive_parent(dn->full_name);
+        if (!dn->parent)
+                return -ENOMEM;
+
+        rc = blocking_notifier_call_chain(&pSeries_reconfig_chain,
+                                          PSERIES_RECONFIG_ADD, dn);
+        if (rc == NOTIFY_BAD) {
+                printk(KERN_ERR "Failed to add device node %s\n",
+                       dn->full_name);
+                return -ENOMEM; /* For now, safe to assume kmalloc failure */
+        }
+
+        of_attach_node(dn);
+
+#ifdef CONFIG_PROC_DEVICETREE
+        ent = proc_mkdir(strrchr(dn->full_name, '/') + 1, dn->parent->pde);
+        if (ent)
+                proc_device_tree_add_node(dn, ent);
+#endif
+
+        of_node_put(dn->parent);
+        return 0;
+}
+
+int dlpar_detach_node(struct device_node *dn)
+{
+        struct device_node *parent = dn->parent;
+        struct property *prop = dn->properties;
+
+#ifdef CONFIG_PROC_DEVICETREE
+        while (prop) {
+                remove_proc_entry(prop->name, dn->pde);
+                prop = prop->next;
+        }
+
+        if (dn->pde)
+                remove_proc_entry(dn->pde->name, parent->pde);
+#endif
+
+        blocking_notifier_call_chain(&pSeries_reconfig_chain,
+                            PSERIES_RECONFIG_REMOVE, dn);
+        of_detach_node(dn);
+        of_node_put(dn); /* Must decrement the refcount */
+
+        return 0;
+}
+
+#define DR_ENTITY_SENSE         9003
+#define DR_ENTITY_PRESENT       1
+#define DR_ENTITY_UNUSABLE      2
+#define ALLOCATION_STATE        9003
+#define ALLOC_UNUSABLE          0
+#define ALLOC_USABLE            1
+#define ISOLATION_STATE         9001
+#define ISOLATE                 0
+#define UNISOLATE               1
+
+int dlpar_acquire_drc(u32 drc_index)
+{
+        int dr_status, rc;
+
+        rc = rtas_call(rtas_token("get-sensor-state"), 2, 2, &dr_status,
+                       DR_ENTITY_SENSE, drc_index);
+        if (rc || dr_status != DR_ENTITY_UNUSABLE)
+                return -1;
+
+        rc = rtas_set_indicator(ALLOCATION_STATE, drc_index, ALLOC_USABLE);
+        if (rc)
+                return rc;
+
+        rc = rtas_set_indicator(ISOLATION_STATE, drc_index, UNISOLATE);
+        if (rc) {
+                rtas_set_indicator(ALLOCATION_STATE, drc_index, ALLOC_UNUSABLE);
+                return rc;
+        }
+
+        return 0;
+}
+
+int dlpar_release_drc(u32 drc_index)
+{
+        int dr_status, rc;
+
+        rc = rtas_call(rtas_token("get-sensor-state"), 2, 2, &dr_status,
+                       DR_ENTITY_SENSE, drc_index);
+        if (rc || dr_status != DR_ENTITY_PRESENT)
+                return -1;
+
+        rc = rtas_set_indicator(ISOLATION_STATE, drc_index, ISOLATE);
+        if (rc)
+                return rc;
+
+        rc = rtas_set_indicator(ALLOCATION_STATE, drc_index, ALLOC_UNUSABLE);
+        if (rc) {
+                rtas_set_indicator(ISOLATION_STATE, drc_index, UNISOLATE);
+                return rc;
+        }
+
+        return 0;
+}
+
+#ifdef CONFIG_ARCH_CPU_PROBE_RELEASE
+
+static DEFINE_MUTEX(pseries_cpu_hotplug_mutex);
+
+void cpu_hotplug_driver_lock()
+{
+        mutex_lock(&pseries_cpu_hotplug_mutex);
+}
+
+void cpu_hotplug_driver_unlock()
+{
+        mutex_unlock(&pseries_cpu_hotplug_mutex);
+}
+
+static int dlpar_online_cpu(struct device_node *dn)
+{
+        int rc = 0;
+        unsigned int cpu;
+        int len, nthreads, i;
+        const u32 *intserv;
+
+        intserv = of_get_property(dn, "ibm,ppc-interrupt-server#s", &len);
+        if (!intserv)
+                return -EINVAL;
+
+        nthreads = len / sizeof(u32);
+
+        cpu_maps_update_begin();
+        for (i = 0; i < nthreads; i++) {
+                for_each_present_cpu(cpu) {
+                        if (get_hard_smp_processor_id(cpu) != intserv[i])
+                                continue;
+                        BUG_ON(get_cpu_current_state(cpu)
+                                        != CPU_STATE_OFFLINE);
+                        cpu_maps_update_done();
+                        rc = cpu_up(cpu);
+                        if (rc)
+                                goto out;
+                        cpu_maps_update_begin();
+
+                        break;
+                }
+                if (cpu == num_possible_cpus())
+                        printk(KERN_WARNING "Could not find cpu to online "
+                               "with physical id 0x%x\n", intserv[i]);
+        }
+        cpu_maps_update_done();
+
+out:
+        return rc;
+
+}
+
+static ssize_t dlpar_cpu_probe(const char *buf, size_t count)
+{
+        struct device_node *dn;
+        unsigned long drc_index;
+        char *cpu_name;
+        int rc;
+
+        cpu_hotplug_driver_lock();
+        rc = strict_strtoul(buf, 0, &drc_index);
+        if (rc) {
+                rc = -EINVAL;
+                goto out;
+        }
+
+        dn = dlpar_configure_connector(drc_index);
+        if (!dn) {
+                rc = -EINVAL;
+                goto out;
+        }
+
+        /* configure-connector reports cpus as living in the base
+         * directory of the device tree.  CPUs actually live in the
+         * cpus directory so we need to fixup the full_name.
+         */
+        cpu_name = kzalloc(strlen(dn->full_name) + strlen("/cpus") + 1,
+                           GFP_KERNEL);
+        if (!cpu_name) {
+                dlpar_free_cc_nodes(dn);
+                rc = -ENOMEM;
+                goto out;
+        }
+
+        sprintf(cpu_name, "/cpus%s", dn->full_name);
+        kfree(dn->full_name);
+        dn->full_name = cpu_name;
+
+        rc = dlpar_acquire_drc(drc_index);
+        if (rc) {
+                dlpar_free_cc_nodes(dn);
+                rc = -EINVAL;
+                goto out;
+        }
+
+        rc = dlpar_attach_node(dn);
+        if (rc) {
+                dlpar_release_drc(drc_index);
+                dlpar_free_cc_nodes(dn);
+        }
+
+        rc = dlpar_online_cpu(dn);
+out:
+        cpu_hotplug_driver_unlock();
+
+        return rc ? rc : count;
+}
+
+static int dlpar_offline_cpu(struct device_node *dn)
+{
+        int rc = 0;
+        unsigned int cpu;
+        int len, nthreads, i;
+        const u32 *intserv;
+
+        intserv = of_get_property(dn, "ibm,ppc-interrupt-server#s", &len);
+        if (!intserv)
+                return -EINVAL;
+
+        nthreads = len / sizeof(u32);
+
+        cpu_maps_update_begin();
+        for (i = 0; i < nthreads; i++) {
+                for_each_present_cpu(cpu) {
+                        if (get_hard_smp_processor_id(cpu) != intserv[i])
+                                continue;
+
+                        if (get_cpu_current_state(cpu) == CPU_STATE_OFFLINE)
+                                break;
+
+                        if (get_cpu_current_state(cpu) == CPU_STATE_ONLINE) {
+                                cpu_maps_update_done();
+                                rc = cpu_down(cpu);
+                                if (rc)
+                                        goto out;
+                                cpu_maps_update_begin();
+                                break;
+
+                        }
+
+                        /*
+                         * The cpu is in CPU_STATE_INACTIVE.
+                         * Upgrade it's state to CPU_STATE_OFFLINE.
+                         */
+                        set_preferred_offline_state(cpu, CPU_STATE_OFFLINE);
+                        BUG_ON(plpar_hcall_norets(H_PROD, intserv[i])
+                                                                != H_SUCCESS);
+                        __cpu_die(cpu);
+                        break;
+                }
+                if (cpu == num_possible_cpus())
+                        printk(KERN_WARNING "Could not find cpu to offline "
+                               "with physical id 0x%x\n", intserv[i]);
+        }
+        cpu_maps_update_done();
+
+out:
+        return rc;
+
+}
+
+static ssize_t dlpar_cpu_release(const char *buf, size_t count)
+{
+        struct device_node *dn;
+        const u32 *drc_index;
+        int rc;
+
+        dn = of_find_node_by_path(buf);
+        if (!dn)
+                return -EINVAL;
+
+        drc_index = of_get_property(dn, "ibm,my-drc-index", NULL);
+        if (!drc_index) {
+                of_node_put(dn);
+                return -EINVAL;
+        }
+
+        cpu_hotplug_driver_lock();
+        rc = dlpar_offline_cpu(dn);
+        if (rc) {
+                of_node_put(dn);
+                rc = -EINVAL;
+                goto out;
+        }
+
+        rc = dlpar_release_drc(*drc_index);
+        if (rc) {
+                of_node_put(dn);
+                goto out;
+        }
+
+        rc = dlpar_detach_node(dn);
+        if (rc) {
+                dlpar_acquire_drc(*drc_index);
+                goto out;
+        }
+
+        of_node_put(dn);
+out:
+        cpu_hotplug_driver_unlock();
+        return rc ? rc : count;
+}
+
+static int __init pseries_dlpar_init(void)
+{
+        ppc_md.cpu_probe = dlpar_cpu_probe;
+        ppc_md.cpu_release = dlpar_cpu_release;
+
+        return 0;
+}
+machine_device_initcall(pseries, pseries_dlpar_init);
+
+#endif /* CONFIG_ARCH_CPU_PROBE_RELEASE */
diff --git a/arch/powerpc/platforms/pseries/dtl.c b/arch/powerpc/platforms/pseries/dtl.c
index 937a544a236d..c5f3116b6ca5 100644
--- a/arch/powerpc/platforms/pseries/dtl.c
+++ b/arch/powerpc/platforms/pseries/dtl.c
@@ -54,7 +54,7 @@ struct dtl {
         int                     buf_entries;
         u64                     last_idx;
 };
-static DEFINE_PER_CPU(struct dtl, dtl);
+static DEFINE_PER_CPU(struct dtl, cpu_dtl);
 
 /*
  * Dispatch trace log event mask:
@@ -261,7 +261,7 @@ static int dtl_init(void)
 
         /* set up the per-cpu log structures */
         for_each_possible_cpu(i) {
-                struct dtl *dtl = &per_cpu(dtl, i);
+                struct dtl *dtl = &per_cpu(cpu_dtl, i);
                 dtl->cpu = i;
 
                 rc = dtl_setup_file(dtl);
diff --git a/arch/powerpc/platforms/pseries/eeh_driver.c b/arch/powerpc/platforms/pseries/eeh_driver.c
index 0e8db6771252..ef8e45448480 100644
--- a/arch/powerpc/platforms/pseries/eeh_driver.c
+++ b/arch/powerpc/platforms/pseries/eeh_driver.c
@@ -63,22 +63,6 @@ static void print_device_node_tree(struct pci_dn *pdn, int dent)
 }
 #endif
 
-/** 
- * irq_in_use - return true if this irq is being used 
- */
-static int irq_in_use(unsigned int irq)
-{
-        int rc = 0;
-        unsigned long flags;
-   struct irq_desc *desc = irq_desc + irq;
-
-        spin_lock_irqsave(&desc->lock, flags);
-        if (desc->action)
-                rc = 1;
-        spin_unlock_irqrestore(&desc->lock, flags);
-        return rc;
-}
-
 /**
  * eeh_disable_irq - disable interrupt for the recovering device
  */
@@ -93,7 +77,7 @@ static void eeh_disable_irq(struct pci_dev *dev)
         if (dev->msi_enabled || dev->msix_enabled)
                 return;
 
-        if (!irq_in_use(dev->irq))
+        if (!irq_has_action(dev->irq))
                 return;
 
         PCI_DN(dn)->eeh_mode |= EEH_MODE_IRQ_DISABLED;
diff --git a/arch/powerpc/platforms/pseries/hotplug-cpu.c b/arch/powerpc/platforms/pseries/hotplug-cpu.c
index ebff6d9a4e39..6ea4698d9176 100644
--- a/arch/powerpc/platforms/pseries/hotplug-cpu.c
+++ b/arch/powerpc/platforms/pseries/hotplug-cpu.c
@@ -30,6 +30,7 @@
 #include <asm/pSeries_reconfig.h>
 #include "xics.h"
 #include "plpar_wrappers.h"
+#include "offline_states.h"
 
 /* This version can't take the spinlock, because it never returns */
 static struct rtas_args rtas_stop_self_args = {
@@ -39,6 +40,55 @@ static struct rtas_args rtas_stop_self_args = {
         .rets = &rtas_stop_self_args.args[0],
 };
 
+static DEFINE_PER_CPU(enum cpu_state_vals, preferred_offline_state) =
+                                                        CPU_STATE_OFFLINE;
+static DEFINE_PER_CPU(enum cpu_state_vals, current_state) = CPU_STATE_OFFLINE;
+
+static enum cpu_state_vals default_offline_state = CPU_STATE_OFFLINE;
+
+static int cede_offline_enabled __read_mostly = 1;
+
+/*
+ * Enable/disable cede_offline when available.
+ */
+static int __init setup_cede_offline(char *str)
+{
+        if (!strcmp(str, "off"))
+                cede_offline_enabled = 0;
+        else if (!strcmp(str, "on"))
+                cede_offline_enabled = 1;
+        else
+                return 0;
+        return 1;
+}
+
+__setup("cede_offline=", setup_cede_offline);
+
+enum cpu_state_vals get_cpu_current_state(int cpu)
+{
+        return per_cpu(current_state, cpu);
+}
+
+void set_cpu_current_state(int cpu, enum cpu_state_vals state)
+{
+        per_cpu(current_state, cpu) = state;
+}
+
+enum cpu_state_vals get_preferred_offline_state(int cpu)
+{
+        return per_cpu(preferred_offline_state, cpu);
+}
+
+void set_preferred_offline_state(int cpu, enum cpu_state_vals state)
+{
+        per_cpu(preferred_offline_state, cpu) = state;
+}
+
+void set_default_offline_state(int cpu)
+{
+        per_cpu(preferred_offline_state, cpu) = default_offline_state;
+}
+
 static void rtas_stop_self(void)
 {
         struct rtas_args *args = &rtas_stop_self_args;
@@ -56,11 +106,61 @@ static void rtas_stop_self(void)
 
 static void pseries_mach_cpu_die(void)
 {
+        unsigned int cpu = smp_processor_id();
+        unsigned int hwcpu = hard_smp_processor_id();
+        u8 cede_latency_hint = 0;
+
         local_irq_disable();
         idle_task_exit();
         xics_teardown_cpu();
-        unregister_slb_shadow(hard_smp_processor_id(), __pa(get_slb_shadow()));
-        rtas_stop_self();
+
+        if (get_preferred_offline_state(cpu) == CPU_STATE_INACTIVE) {
+                set_cpu_current_state(cpu, CPU_STATE_INACTIVE);
+                cede_latency_hint = 2;
+
+                get_lppaca()->idle = 1;
+                if (!get_lppaca()->shared_proc)
+                        get_lppaca()->donate_dedicated_cpu = 1;
+
+                printk(KERN_INFO
+                        "cpu %u (hwid %u) ceding for offline with hint %d\n",
+                        cpu, hwcpu, cede_latency_hint);
+                while (get_preferred_offline_state(cpu) == CPU_STATE_INACTIVE) {
+                        extended_cede_processor(cede_latency_hint);
+                        printk(KERN_INFO "cpu %u (hwid %u) returned from cede.\n",
+                                cpu, hwcpu);
+                        printk(KERN_INFO
+                        "Decrementer value = %x Timebase value = %llx\n",
+                        get_dec(), get_tb());
+                }
+
+                printk(KERN_INFO "cpu %u (hwid %u) got prodded to go online\n",
+                        cpu, hwcpu);
+
+                if (!get_lppaca()->shared_proc)
+                        get_lppaca()->donate_dedicated_cpu = 0;
+                get_lppaca()->idle = 0;
+        }
+
+        if (get_preferred_offline_state(cpu) == CPU_STATE_ONLINE) {
+                unregister_slb_shadow(hwcpu, __pa(get_slb_shadow()));
+
+                /*
+                 * NOTE: Calling start_secondary() here for now to
+                 * start new context.
+                 * However, need to do it cleanly by resetting the
+                 * stack pointer.
+                 */
+                start_secondary();
+
+        } else if (get_preferred_offline_state(cpu) == CPU_STATE_OFFLINE) {
+
+                set_cpu_current_state(cpu, CPU_STATE_OFFLINE);
+                unregister_slb_shadow(hard_smp_processor_id(),
+                                        __pa(get_slb_shadow()));
+                rtas_stop_self();
+        }
+
         /* Should never get here... */
         BUG();
         for(;;);
@@ -106,18 +206,43 @@ static int pseries_cpu_disable(void)
         return 0;
 }
 
+/*
+ * pseries_cpu_die: Wait for the cpu to die.
+ * @cpu: logical processor id of the CPU whose death we're awaiting.
+ *
+ * This function is called from the context of the thread which is performing
+ * the cpu-offline. Here we wait for long enough to allow the cpu in question
+ * to self-destroy so that the cpu-offline thread can send the CPU_DEAD
+ * notifications.
+ *
+ * OTOH, pseries_mach_cpu_die() is called by the @cpu when it wants to
+ * self-destruct.
+ */
 static void pseries_cpu_die(unsigned int cpu)
 {
         int tries;
-        int cpu_status;
+        int cpu_status = 1;
         unsigned int pcpu = get_hard_smp_processor_id(cpu);
 
-        for (tries = 0; tries < 25; tries++) {
-                cpu_status = query_cpu_stopped(pcpu);
-                if (cpu_status == 0 || cpu_status == -1)
-                        break;
-                cpu_relax();
+        if (get_preferred_offline_state(cpu) == CPU_STATE_INACTIVE) {
+                cpu_status = 1;
+                for (tries = 0; tries < 1000; tries++) {
+                        if (get_cpu_current_state(cpu) == CPU_STATE_INACTIVE) {
+                                cpu_status = 0;
+                                break;
+                        }
+                        cpu_relax();
+                }
+        } else if (get_preferred_offline_state(cpu) == CPU_STATE_OFFLINE) {
+
+                for (tries = 0; tries < 25; tries++) {
+                        cpu_status = query_cpu_stopped(pcpu);
+                        if (cpu_status == 0 || cpu_status == -1)
+                                break;
+                        cpu_relax();
+                }
         }
+
         if (cpu_status != 0) {
                 printk("Querying DEAD? cpu %i (%i) shows %i\n",
                        cpu, pcpu, cpu_status);
@@ -252,10 +377,41 @@ static struct notifier_block pseries_smp_nb = {
         .notifier_call = pseries_smp_notifier,
 };
 
+#define MAX_CEDE_LATENCY_LEVELS         4
+#define CEDE_LATENCY_PARAM_LENGTH       10
+#define CEDE_LATENCY_PARAM_MAX_LENGTH   \
+        (MAX_CEDE_LATENCY_LEVELS * CEDE_LATENCY_PARAM_LENGTH * sizeof(char))
+#define CEDE_LATENCY_TOKEN              45
+
+static char cede_parameters[CEDE_LATENCY_PARAM_MAX_LENGTH];
+
+static int parse_cede_parameters(void)
+{
+        int call_status;
+
+        memset(cede_parameters, 0, CEDE_LATENCY_PARAM_MAX_LENGTH);
+        call_status = rtas_call(rtas_token("ibm,get-system-parameter"), 3, 1,
+                                NULL,
+                                CEDE_LATENCY_TOKEN,
+                                __pa(cede_parameters),
+                                CEDE_LATENCY_PARAM_MAX_LENGTH);
+
+        if (call_status != 0)
+                printk(KERN_INFO "CEDE_LATENCY: \
+                        %s %s Error calling get-system-parameter(0x%x)\n",
+                        __FILE__, __func__, call_status);
+        else
+                printk(KERN_INFO "CEDE_LATENCY: \
+                        get-system-parameter successful.\n");
+
+        return call_status;
+}
+
 static int __init pseries_cpu_hotplug_init(void)
 {
         struct device_node *np;
         const char *typep;
+        int cpu;
 
         for_each_node_by_name(np, "interrupt-controller") {
                 typep = of_get_property(np, "compatible", NULL);
@@ -283,8 +439,16 @@ static int __init pseries_cpu_hotplug_init(void)
         smp_ops->cpu_die = pseries_cpu_die;
 
         /* Processors can be added/removed only on LPAR */
-        if (firmware_has_feature(FW_FEATURE_LPAR))
+        if (firmware_has_feature(FW_FEATURE_LPAR)) {
                 pSeries_reconfig_notifier_register(&pseries_smp_nb);
+                cpu_maps_update_begin();
+                if (cede_offline_enabled && parse_cede_parameters() == 0) {
+                        default_offline_state = CPU_STATE_INACTIVE;
+                        for_each_online_cpu(cpu)
+                                set_default_offline_state(cpu);
+                }
+                cpu_maps_update_done();
+        }
 
         return 0;
 }
diff --git a/arch/powerpc/platforms/pseries/offline_states.h b/arch/powerpc/platforms/pseries/offline_states.h
new file mode 100644
index 000000000000..22574e0d9d91
--- /dev/null
+++ b/arch/powerpc/platforms/pseries/offline_states.h
@@ -0,0 +1,18 @@
+#ifndef _OFFLINE_STATES_H_
+#define _OFFLINE_STATES_H_
+
+/* Cpu offline states go here */
+enum cpu_state_vals {
+        CPU_STATE_OFFLINE,
+        CPU_STATE_INACTIVE,
+        CPU_STATE_ONLINE,
+        CPU_MAX_OFFLINE_STATES
+};
+
+extern enum cpu_state_vals get_cpu_current_state(int cpu);
+extern void set_cpu_current_state(int cpu, enum cpu_state_vals state);
+extern enum cpu_state_vals get_preferred_offline_state(int cpu);
+extern void set_preferred_offline_state(int cpu, enum cpu_state_vals state);
+extern void set_default_offline_state(int cpu);
+extern int start_secondary(void);
+#endif
diff --git a/arch/powerpc/platforms/pseries/plpar_wrappers.h b/arch/powerpc/platforms/pseries/plpar_wrappers.h
index a24a6b2333b2..0603c91538ae 100644
--- a/arch/powerpc/platforms/pseries/plpar_wrappers.h
+++ b/arch/powerpc/platforms/pseries/plpar_wrappers.h
@@ -9,11 +9,33 @@ static inline long poll_pending(void)
         return plpar_hcall_norets(H_POLL_PENDING);
 }
 
+static inline u8 get_cede_latency_hint(void)
+{
+        return get_lppaca()->gpr5_dword.fields.cede_latency_hint;
+}
+
+static inline void set_cede_latency_hint(u8 latency_hint)
+{
+        get_lppaca()->gpr5_dword.fields.cede_latency_hint = latency_hint;
+}
+
 static inline long cede_processor(void)
 {
         return plpar_hcall_norets(H_CEDE);
 }
 
+static inline long extended_cede_processor(unsigned long latency_hint)
+{
+        long rc;
+        u8 old_latency_hint = get_cede_latency_hint();
+
+        set_cede_latency_hint(latency_hint);
+        rc = cede_processor();
+        set_cede_latency_hint(old_latency_hint);
+
+        return rc;
+}
+
 static inline long vpa_call(unsigned long flags, unsigned long cpu,
                 unsigned long vpa)
 {
diff --git a/arch/powerpc/platforms/pseries/reconfig.c b/arch/powerpc/platforms/pseries/reconfig.c
index 2e2bbe120b90..a2305d29bbbd 100644
--- a/arch/powerpc/platforms/pseries/reconfig.c
+++ b/arch/powerpc/platforms/pseries/reconfig.c
@@ -96,7 +96,7 @@ static struct device_node *derive_parent(const char *path)
         return parent;
 }
 
-static BLOCKING_NOTIFIER_HEAD(pSeries_reconfig_chain);
+BLOCKING_NOTIFIER_HEAD(pSeries_reconfig_chain);
 
 int pSeries_reconfig_notifier_register(struct notifier_block *nb)
 {
@@ -184,7 +184,7 @@ static int pSeries_reconfig_remove_node(struct device_node *np)
 }
 
 /*
- * /proc/ppc64/ofdt - yucky binary interface for adding and removing
+ * /proc/powerpc/ofdt - yucky binary interface for adding and removing
  * OF device nodes.  Should be deprecated as soon as we get an
  * in-kernel wrapper for the RTAS ibm,configure-connector call.
  */
@@ -543,7 +543,7 @@ static const struct file_operations ofdt_fops = {
         .write = ofdt_write
 };
 
-/* create /proc/ppc64/ofdt write-only by root */
+/* create /proc/powerpc/ofdt write-only by root */
 static int proc_ppc64_create_ofdt(void)
 {
         struct proc_dir_entry *ent;
@@ -551,7 +551,7 @@ static int proc_ppc64_create_ofdt(void)
         if (!machine_is(pseries))
                 return 0;
 
-        ent = proc_create("ppc64/ofdt", S_IWUSR, NULL, &ofdt_fops);
+        ent = proc_create("powerpc/ofdt", S_IWUSR, NULL, &ofdt_fops);
         if (ent)
                 ent->size = 0;
 
diff --git a/arch/powerpc/platforms/pseries/scanlog.c b/arch/powerpc/platforms/pseries/scanlog.c
index 417eca79df69..1b45c458f952 100644
--- a/arch/powerpc/platforms/pseries/scanlog.c
+++ b/arch/powerpc/platforms/pseries/scanlog.c
@@ -13,7 +13,7 @@
  * of this data using this driver.  A dump exists if the device-tree
  * /chosen/ibm,scan-log-data property exists.
  *
- * This driver exports /proc/ppc64/scan-log-dump which can be read.
+ * This driver exports /proc/powerpc/scan-log-dump which can be read.
  * The driver supports only sequential reads.
  *
  * The driver looks at a write to the driver for the single word "reset".
@@ -186,7 +186,7 @@ static int __init scanlog_init(void)
         if (!data)
                 goto err;
 
-        ent = proc_create_data("ppc64/rtas/scan-log-dump", S_IRUSR, NULL,
+        ent = proc_create_data("powerpc/rtas/scan-log-dump", S_IRUSR, NULL,
                                &scanlog_fops, data);
         if (!ent)
                 goto err;
diff --git a/arch/powerpc/platforms/pseries/smp.c b/arch/powerpc/platforms/pseries/smp.c
index 440000cc7130..8868c012268a 100644
--- a/arch/powerpc/platforms/pseries/smp.c
+++ b/arch/powerpc/platforms/pseries/smp.c
@@ -48,6 +48,7 @@
 #include "plpar_wrappers.h"
 #include "pseries.h"
 #include "xics.h"
+#include "offline_states.h"
 
 
 /*
@@ -84,6 +85,9 @@ static inline int __devinit smp_startup_cpu(unsigned int lcpu)
         /* Fixup atomic count: it exited inside IRQ handler. */
         task_thread_info(paca[lcpu].__current)->preempt_count   = 0;
 
+        if (get_cpu_current_state(lcpu) == CPU_STATE_INACTIVE)
+                goto out;
+
         /* 
          * If the RTAS start-cpu token does not exist then presume the
          * cpu is already spinning.
@@ -98,6 +102,7 @@ static inline int __devinit smp_startup_cpu(unsigned int lcpu)
                 return 0;
         }
 
+out:
         return 1;
 }
 
@@ -111,12 +116,16 @@ static void __devinit smp_xics_setup_cpu(int cpu)
                 vpa_init(cpu);
 
         cpu_clear(cpu, of_spin_map);
+        set_cpu_current_state(cpu, CPU_STATE_ONLINE);
+        set_default_offline_state(cpu);
 
 }
 #endif /* CONFIG_XICS */
 
 static void __devinit smp_pSeries_kick_cpu(int nr)
 {
+        long rc;
+        unsigned long hcpuid;
         BUG_ON(nr < 0 || nr >= NR_CPUS);
 
         if (!smp_startup_cpu(nr))
@@ -128,6 +137,16 @@ static void __devinit smp_pSeries_kick_cpu(int nr)
          * the processor will continue on to secondary_start
          */
         paca[nr].cpu_start = 1;
+
+        set_preferred_offline_state(nr, CPU_STATE_ONLINE);
+
+        if (get_cpu_current_state(nr) == CPU_STATE_INACTIVE) {
+                hcpuid = get_hard_smp_processor_id(nr);
+                rc = plpar_hcall_norets(H_PROD, hcpuid);
+                if (rc != H_SUCCESS)
+                        panic("Error: Prod to wake up processor %d Ret= %ld\n",
+                                nr, rc);
+        }
 }
 
 static int smp_pSeries_cpu_bootable(unsigned int nr)
diff --git a/arch/powerpc/platforms/pseries/xics.c b/arch/powerpc/platforms/pseries/xics.c
index b9bf0eedccf2..b9b9e11609ec 100644
--- a/arch/powerpc/platforms/pseries/xics.c
+++ b/arch/powerpc/platforms/pseries/xics.c
@@ -20,6 +20,7 @@
 #include <linux/cpu.h>
 #include <linux/msi.h>
 #include <linux/of.h>
+#include <linux/percpu.h>
 
 #include <asm/firmware.h>
 #include <asm/io.h>
@@ -46,6 +47,12 @@ static struct irq_host *xics_host;
  */
 #define IPI_PRIORITY            4
 
+/* The least favored priority */
+#define LOWEST_PRIORITY         0xFF
+
+/* The number of priorities defined above */
+#define MAX_NUM_PRIORITIES      3
+
 static unsigned int default_server = 0xFF;
 static unsigned int default_distrib_server = 0;
 static unsigned int interrupt_server_size = 8;
@@ -56,6 +63,12 @@ static int ibm_set_xive;
 static int ibm_int_on;
 static int ibm_int_off;
 
+struct xics_cppr {
+        unsigned char stack[MAX_NUM_PRIORITIES];
+        int index;
+};
+
+static DEFINE_PER_CPU(struct xics_cppr, xics_cppr);
 
 /* Direct hardware low level accessors */
 
@@ -157,7 +170,7 @@ static int get_irq_server(unsigned int virq, unsigned int strict_check)
         cpumask_t cpumask;
         cpumask_t tmp = CPU_MASK_NONE;
 
-        cpumask_copy(&cpumask, irq_desc[virq].affinity);
+        cpumask_copy(&cpumask, irq_to_desc(virq)->affinity);
         if (!distribute_irqs)
                 return default_server;
 
@@ -284,6 +297,19 @@ static inline unsigned int xics_xirr_vector(unsigned int xirr)
         return xirr & 0x00ffffff;
 }
 
+static void push_cppr(unsigned int vec)
+{
+        struct xics_cppr *os_cppr = &__get_cpu_var(xics_cppr);
+
+        if (WARN_ON(os_cppr->index >= MAX_NUM_PRIORITIES - 1))
+                return;
+
+        if (vec == XICS_IPI)
+                os_cppr->stack[++os_cppr->index] = IPI_PRIORITY;
+        else
+                os_cppr->stack[++os_cppr->index] = DEFAULT_PRIORITY;
+}
+
 static unsigned int xics_get_irq_direct(void)
 {
         unsigned int xirr = direct_xirr_info_get();
@@ -294,8 +320,10 @@ static unsigned int xics_get_irq_direct(void)
                 return NO_IRQ;
 
         irq = irq_radix_revmap_lookup(xics_host, vec);
-        if (likely(irq != NO_IRQ))
+        if (likely(irq != NO_IRQ)) {
+                push_cppr(vec);
                 return irq;
+        }
 
         /* We don't have a linux mapping, so have rtas mask it. */
         xics_mask_unknown_vec(vec);
@@ -315,8 +343,10 @@ static unsigned int xics_get_irq_lpar(void)
                 return NO_IRQ;
 
         irq = irq_radix_revmap_lookup(xics_host, vec);
-        if (likely(irq != NO_IRQ))
+        if (likely(irq != NO_IRQ)) {
+                push_cppr(vec);
                 return irq;
+        }
 
         /* We don't have a linux mapping, so have RTAS mask it. */
         xics_mask_unknown_vec(vec);
@@ -326,12 +356,22 @@ static unsigned int xics_get_irq_lpar(void)
         return NO_IRQ;
 }
 
+static unsigned char pop_cppr(void)
+{
+        struct xics_cppr *os_cppr = &__get_cpu_var(xics_cppr);
+
+        if (WARN_ON(os_cppr->index < 1))
+                return LOWEST_PRIORITY;
+
+        return os_cppr->stack[--os_cppr->index];
+}
+
 static void xics_eoi_direct(unsigned int virq)
 {
         unsigned int irq = (unsigned int)irq_map[virq].hwirq;
 
         iosync();
-        direct_xirr_info_set((0xff << 24) | irq);
+        direct_xirr_info_set((pop_cppr() << 24) | irq);
 }
 
 static void xics_eoi_lpar(unsigned int virq)
@@ -339,7 +379,7 @@ static void xics_eoi_lpar(unsigned int virq)
         unsigned int irq = (unsigned int)irq_map[virq].hwirq;
 
         iosync();
-        lpar_xirr_info_set((0xff << 24) | irq);
+        lpar_xirr_info_set((pop_cppr() << 24) | irq);
 }
 
 static int xics_set_affinity(unsigned int virq, const struct cpumask *cpumask)
@@ -388,7 +428,7 @@ static int xics_set_affinity(unsigned int virq, const struct cpumask *cpumask)
 }
 
 static struct irq_chip xics_pic_direct = {
-        .typename = " XICS     ",
+        .name = " XICS     ",
         .startup = xics_startup,
         .mask = xics_mask_irq,
         .unmask = xics_unmask_irq,
@@ -397,7 +437,7 @@ static struct irq_chip xics_pic_direct = {
 };
 
 static struct irq_chip xics_pic_lpar = {
-        .typename = " XICS     ",
+        .name = " XICS     ",
         .startup = xics_startup,
         .mask = xics_mask_irq,
         .unmask = xics_unmask_irq,
@@ -428,13 +468,13 @@ static int xics_host_map(struct irq_host *h, unsigned int virq,
         /* Insert the interrupt mapping into the radix tree for fast lookup */
         irq_radix_revmap_insert(xics_host, virq, hw);
 
-        get_irq_desc(virq)->status |= IRQ_LEVEL;
+        irq_to_desc(virq)->status |= IRQ_LEVEL;
         set_irq_chip_and_handler(virq, xics_irq_chip, handle_fasteoi_irq);
         return 0;
 }
 
 static int xics_host_xlate(struct irq_host *h, struct device_node *ct,
-                           u32 *intspec, unsigned int intsize,
+                           const u32 *intspec, unsigned int intsize,
                            irq_hw_number_t *out_hwirq, unsigned int *out_flags)
 
 {
@@ -746,6 +786,12 @@ void __init xics_init_IRQ(void)
 
 static void xics_set_cpu_priority(unsigned char cppr)
 {
+        struct xics_cppr *os_cppr = &__get_cpu_var(xics_cppr);
+
+        BUG_ON(os_cppr->index != 0);
+
+        os_cppr->stack[os_cppr->index] = cppr;
+
         if (firmware_has_feature(FW_FEATURE_LPAR))
                 lpar_cppr_info(cppr);
         else
@@ -772,7 +818,7 @@ static void xics_set_cpu_giq(unsigned int gserver, unsigned int join)
 
 void xics_setup_cpu(void)
 {
-        xics_set_cpu_priority(0xff);
+        xics_set_cpu_priority(LOWEST_PRIORITY);
 
         xics_set_cpu_giq(default_distrib_server, 1);
 }
@@ -852,7 +898,7 @@ void xics_migrate_irqs_away(void)
                 /* We need to get IPIs still. */
                 if (irq == XICS_IPI || irq == XICS_IRQ_SPURIOUS)
                         continue;
-                desc = get_irq_desc(virq);
+                desc = irq_to_desc(virq);
 
                 /* We only need to migrate enabled IRQS */
                 if (desc == NULL || desc->chip == NULL
@@ -860,7 +906,7 @@ void xics_migrate_irqs_away(void)
                     || desc->chip->set_affinity == NULL)
                         continue;
 
-                spin_lock_irqsave(&desc->lock, flags);
+                raw_spin_lock_irqsave(&desc->lock, flags);
 
                 status = rtas_call(ibm_get_xive, 1, 3, xics_status, irq);
                 if (status) {
@@ -881,10 +927,10 @@ void xics_migrate_irqs_away(void)
                        virq, cpu);
 
                 /* Reset affinity to all cpus */
-                cpumask_setall(irq_desc[virq].affinity);
+                cpumask_setall(irq_to_desc(virq)->affinity);
                 desc->chip->set_affinity(virq, cpu_all_mask);
 unlock:
-                spin_unlock_irqrestore(&desc->lock, flags);
+                raw_spin_unlock_irqrestore(&desc->lock, flags);
         }
 }
 #endif
diff --git a/arch/powerpc/sysdev/Makefile b/arch/powerpc/sysdev/Makefile
index 9d4b17462f13..5642924fb9fb 100644
--- a/arch/powerpc/sysdev/Makefile
+++ b/arch/powerpc/sysdev/Makefile
@@ -16,6 +16,7 @@ obj-$(CONFIG_U3_DART)		+= dart_iommu.o
 obj-$(CONFIG_MMIO_NVRAM)        += mmio_nvram.o
 obj-$(CONFIG_FSL_SOC)           += fsl_soc.o
 obj-$(CONFIG_FSL_PCI)           += fsl_pci.o $(fsl-msi-obj-y)
+obj-$(CONFIG_FSL_PMC)           += fsl_pmc.o
 obj-$(CONFIG_FSL_LBC)           += fsl_lbc.o
 obj-$(CONFIG_FSL_GTM)           += fsl_gtm.o
 obj-$(CONFIG_MPC8xxx_GPIO)      += mpc8xxx_gpio.o
diff --git a/arch/powerpc/sysdev/cpm1.c b/arch/powerpc/sysdev/cpm1.c
index 82424cd7e128..a4b41dbde128 100644
--- a/arch/powerpc/sysdev/cpm1.c
+++ b/arch/powerpc/sysdev/cpm1.c
@@ -77,7 +77,7 @@ static void cpm_end_irq(unsigned int irq)
 }
 
 static struct irq_chip cpm_pic = {
-        .typename = " CPM PIC ",
+        .name = " CPM PIC ",
         .mask = cpm_mask_irq,
         .unmask = cpm_unmask_irq,
         .eoi = cpm_end_irq,
@@ -102,7 +102,7 @@ static int cpm_pic_host_map(struct irq_host *h, unsigned int virq,
 {
         pr_debug("cpm_pic_host_map(%d, 0x%lx)\n", virq, hw);
 
-        get_irq_desc(virq)->status |= IRQ_LEVEL;
+        irq_to_desc(virq)->status |= IRQ_LEVEL;
         set_irq_chip_and_handler(virq, &cpm_pic, handle_fasteoi_irq);
         return 0;
 }
diff --git a/arch/powerpc/sysdev/cpm2_pic.c b/arch/powerpc/sysdev/cpm2_pic.c
index 78f1f7cca0a0..971483f0dfac 100644
--- a/arch/powerpc/sysdev/cpm2_pic.c
+++ b/arch/powerpc/sysdev/cpm2_pic.c
@@ -115,11 +115,13 @@ static void cpm2_ack(unsigned int virq)
 
 static void cpm2_end_irq(unsigned int virq)
 {
+        struct irq_desc *desc;
         int     bit, word;
         unsigned int irq_nr = virq_to_hw(virq);
 
-        if (!(irq_desc[irq_nr].status & (IRQ_DISABLED|IRQ_INPROGRESS))
-                        && irq_desc[irq_nr].action) {
+        desc = irq_to_desc(irq_nr);
+        if (!(desc->status & (IRQ_DISABLED|IRQ_INPROGRESS))
+                        && desc->action) {
 
                 bit = irq_to_siubit[irq_nr];
                 word = irq_to_siureg[irq_nr];
@@ -138,7 +140,7 @@ static void cpm2_end_irq(unsigned int virq)
 static int cpm2_set_irq_type(unsigned int virq, unsigned int flow_type)
 {
         unsigned int src = virq_to_hw(virq);
-        struct irq_desc *desc = get_irq_desc(virq);
+        struct irq_desc *desc = irq_to_desc(virq);
         unsigned int vold, vnew, edibit;
 
         if (flow_type == IRQ_TYPE_NONE)
@@ -182,7 +184,7 @@ static int cpm2_set_irq_type(unsigned int virq, unsigned int flow_type)
 }
 
 static struct irq_chip cpm2_pic = {
-        .typename = " CPM2 SIU ",
+        .name = " CPM2 SIU ",
         .mask = cpm2_mask_irq,
         .unmask = cpm2_unmask_irq,
         .ack = cpm2_ack,
@@ -210,13 +212,13 @@ static int cpm2_pic_host_map(struct irq_host *h, unsigned int virq,
 {
         pr_debug("cpm2_pic_host_map(%d, 0x%lx)\n", virq, hw);
 
-        get_irq_desc(virq)->status |= IRQ_LEVEL;
+        irq_to_desc(virq)->status |= IRQ_LEVEL;
         set_irq_chip_and_handler(virq, &cpm2_pic, handle_level_irq);
         return 0;
 }
 
 static int cpm2_pic_host_xlate(struct irq_host *h, struct device_node *ct,
-                            u32 *intspec, unsigned int intsize,
+                            const u32 *intspec, unsigned int intsize,
                             irq_hw_number_t *out_hwirq, unsigned int *out_flags)
 {
         *out_hwirq = intspec[0];
diff --git a/arch/powerpc/sysdev/cpm_common.c b/arch/powerpc/sysdev/cpm_common.c
index e4b6d66d93de..9de72c96e6d1 100644
--- a/arch/powerpc/sysdev/cpm_common.c
+++ b/arch/powerpc/sysdev/cpm_common.c
@@ -72,7 +72,7 @@ static phys_addr_t muram_pbase;
 /* Max address size we deal with */
 #define OF_MAX_ADDR_CELLS       4
 
-int __init cpm_muram_init(void)
+int cpm_muram_init(void)
 {
         struct device_node *np;
         struct resource r;
@@ -81,6 +81,9 @@ int __init cpm_muram_init(void)
         int i = 0;
         int ret = 0;
 
+        if (muram_pbase)
+                return 0;
+
         spin_lock_init(&cpm_muram_lock);
         /* initialize the info header */
         rh_init(&cpm_muram_info, 1,
diff --git a/arch/powerpc/sysdev/fsl_msi.c b/arch/powerpc/sysdev/fsl_msi.c
index da38a1ff97bb..c6e11b077108 100644
--- a/arch/powerpc/sysdev/fsl_msi.c
+++ b/arch/powerpc/sysdev/fsl_msi.c
@@ -47,7 +47,7 @@ static struct irq_chip fsl_msi_chip = {
         .mask           = mask_msi_irq,
         .unmask         = unmask_msi_irq,
         .ack            = fsl_msi_end_irq,
-        .typename       = " FSL-MSI  ",
+        .name   = " FSL-MSI  ",
 };
 
 static int fsl_msi_host_map(struct irq_host *h, unsigned int virq,
@@ -55,7 +55,7 @@ static int fsl_msi_host_map(struct irq_host *h, unsigned int virq,
 {
         struct irq_chip *chip = &fsl_msi_chip;
 
-        get_irq_desc(virq)->status |= IRQ_TYPE_EDGE_FALLING;
+        irq_to_desc(virq)->status |= IRQ_TYPE_EDGE_FALLING;
 
         set_irq_chip_and_handler(virq, chip, handle_edge_irq);
 
@@ -173,7 +173,7 @@ static void fsl_msi_cascade(unsigned int irq, struct irq_desc *desc)
         u32 intr_index;
         u32 have_shift = 0;
 
-        spin_lock(&desc->lock);
+        raw_spin_lock(&desc->lock);
         if ((msi_data->feature &  FSL_PIC_IP_MASK) == FSL_PIC_IP_IPIC) {
                 if (desc->chip->mask_ack)
                         desc->chip->mask_ack(irq);
@@ -225,7 +225,7 @@ static void fsl_msi_cascade(unsigned int irq, struct irq_desc *desc)
                 break;
         }
 unlock:
-        spin_unlock(&desc->lock);
+        raw_spin_unlock(&desc->lock);
 }
 
 static int __devinit fsl_of_msi_probe(struct of_device *dev,
diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c
index ae88b1448018..4e3a3e345ab3 100644
--- a/arch/powerpc/sysdev/fsl_pci.c
+++ b/arch/powerpc/sysdev/fsl_pci.c
@@ -56,7 +56,7 @@ static int __init fsl_pcie_check_link(struct pci_controller *hose)
         return 0;
 }
 
-#if defined(CONFIG_PPC_85xx) || defined(CONFIG_PPC_86xx)
+#if defined(CONFIG_FSL_SOC_BOOKE) || defined(CONFIG_PPC_86xx)
 static int __init setup_one_atmu(struct ccsr_pci __iomem *pci,
         unsigned int index, const struct resource *res,
         resource_size_t offset)
@@ -392,9 +392,23 @@ DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8536, quirk_fsl_pcie_header);
 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8641, quirk_fsl_pcie_header);
 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8641D, quirk_fsl_pcie_header);
 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8610, quirk_fsl_pcie_header);
+DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P1011E, quirk_fsl_pcie_header);
+DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P1011, quirk_fsl_pcie_header);
+DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P1013E, quirk_fsl_pcie_header);
+DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P1013, quirk_fsl_pcie_header);
+DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P1020E, quirk_fsl_pcie_header);
+DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P1020, quirk_fsl_pcie_header);
+DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P1022E, quirk_fsl_pcie_header);
+DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P1022, quirk_fsl_pcie_header);
+DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P2010E, quirk_fsl_pcie_header);
+DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P2010, quirk_fsl_pcie_header);
 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P2020E, quirk_fsl_pcie_header);
 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P2020, quirk_fsl_pcie_header);
-#endif /* CONFIG_PPC_85xx || CONFIG_PPC_86xx */
+DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P4040E, quirk_fsl_pcie_header);
+DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P4040, quirk_fsl_pcie_header);
+DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P4080E, quirk_fsl_pcie_header);
+DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P4080, quirk_fsl_pcie_header);
+#endif /* CONFIG_FSL_SOC_BOOKE || CONFIG_PPC_86xx */
 
 #if defined(CONFIG_PPC_83xx) || defined(CONFIG_PPC_MPC512x)
 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8314E, quirk_fsl_pcie_header);
diff --git a/arch/powerpc/sysdev/fsl_pmc.c b/arch/powerpc/sysdev/fsl_pmc.c
new file mode 100644
index 000000000000..a7635a993dca
--- /dev/null
+++ b/arch/powerpc/sysdev/fsl_pmc.c
@@ -0,0 +1,88 @@
+/*
+ * Suspend/resume support
+ *
+ * Copyright 2009  MontaVista Software, Inc.
+ *
+ * Author: Anton Vorontsov <avorontsov@ru.mvista.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <linux/init.h>
+#include <linux/types.h>
+#include <linux/errno.h>
+#include <linux/suspend.h>
+#include <linux/delay.h>
+#include <linux/device.h>
+#include <linux/of_platform.h>
+
+struct pmc_regs {
+        __be32 devdisr;
+        __be32 devdisr2;
+        __be32 :32;
+        __be32 :32;
+        __be32 pmcsr;
+#define PMCSR_SLP       (1 << 17)
+};
+
+static struct device *pmc_dev;
+static struct pmc_regs __iomem *pmc_regs;
+
+static int pmc_suspend_enter(suspend_state_t state)
+{
+        int ret;
+
+        setbits32(&pmc_regs->pmcsr, PMCSR_SLP);
+        /* At this point, the CPU is asleep. */
+
+        /* Upon resume, wait for SLP bit to be clear. */
+        ret = spin_event_timeout((in_be32(&pmc_regs->pmcsr) & PMCSR_SLP) == 0,
+                                 10000, 10) ? 0 : -ETIMEDOUT;
+        if (ret)
+                dev_err(pmc_dev, "tired waiting for SLP bit to clear\n");
+        return ret;
+}
+
+static int pmc_suspend_valid(suspend_state_t state)
+{
+        if (state != PM_SUSPEND_STANDBY)
+                return 0;
+        return 1;
+}
+
+static struct platform_suspend_ops pmc_suspend_ops = {
+        .valid = pmc_suspend_valid,
+        .enter = pmc_suspend_enter,
+};
+
+static int pmc_probe(struct of_device *ofdev, const struct of_device_id *id)
+{
+        pmc_regs = of_iomap(ofdev->node, 0);
+        if (!pmc_regs)
+                return -ENOMEM;
+
+        pmc_dev = &ofdev->dev;
+        suspend_set_ops(&pmc_suspend_ops);
+        return 0;
+}
+
+static const struct of_device_id pmc_ids[] = {
+        { .compatible = "fsl,mpc8548-pmc", },
+        { .compatible = "fsl,mpc8641d-pmc", },
+        { },
+};
+
+static struct of_platform_driver pmc_driver = {
+        .driver.name = "fsl-pmc",
+        .match_table = pmc_ids,
+        .probe = pmc_probe,
+};
+
+static int __init pmc_init(void)
+{
+        return of_register_platform_driver(&pmc_driver);
+}
+device_initcall(pmc_init);
diff --git a/arch/powerpc/sysdev/fsl_soc.c b/arch/powerpc/sysdev/fsl_soc.c
index adca4affcf1f..b91f7acdda6f 100644
--- a/arch/powerpc/sysdev/fsl_soc.c
+++ b/arch/powerpc/sysdev/fsl_soc.c
@@ -372,7 +372,7 @@ err:
 
 arch_initcall(fsl_usb_of_init);
 
-#if defined(CONFIG_PPC_85xx) || defined(CONFIG_PPC_86xx)
+#if defined(CONFIG_FSL_SOC_BOOKE) || defined(CONFIG_PPC_86xx)
 static __be32 __iomem *rstcr;
 
 static int __init setup_rstcr(void)
diff --git a/arch/powerpc/sysdev/i8259.c b/arch/powerpc/sysdev/i8259.c
index a96584ab33dd..0a55db8a5a29 100644
--- a/arch/powerpc/sysdev/i8259.c
+++ b/arch/powerpc/sysdev/i8259.c
@@ -135,7 +135,7 @@ static void i8259_unmask_irq(unsigned int irq_nr)
 }
 
 static struct irq_chip i8259_pic = {
-        .typename       = " i8259    ",
+        .name           = " i8259    ",
         .mask           = i8259_mask_irq,
         .disable        = i8259_mask_irq,
         .unmask         = i8259_unmask_irq,
@@ -175,12 +175,12 @@ static int i8259_host_map(struct irq_host *h, unsigned int virq,
 
         /* We block the internal cascade */
         if (hw == 2)
-                get_irq_desc(virq)->status |= IRQ_NOREQUEST;
+                irq_to_desc(virq)->status |= IRQ_NOREQUEST;
 
         /* We use the level handler only for now, we might want to
          * be more cautious here but that works for now
          */
-        get_irq_desc(virq)->status |= IRQ_LEVEL;
+        irq_to_desc(virq)->status |= IRQ_LEVEL;
         set_irq_chip_and_handler(virq, &i8259_pic, handle_level_irq);
         return 0;
 }
@@ -198,7 +198,7 @@ static void i8259_host_unmap(struct irq_host *h, unsigned int virq)
 }
 
 static int i8259_host_xlate(struct irq_host *h, struct device_node *ct,
-                            u32 *intspec, unsigned int intsize,
+                            const u32 *intspec, unsigned int intsize,
                             irq_hw_number_t *out_hwirq, unsigned int *out_flags)
 {
         static unsigned char map_isa_senses[4] = {
diff --git a/arch/powerpc/sysdev/ipic.c b/arch/powerpc/sysdev/ipic.c
index cb7689c4bfbd..28cdddd2f89e 100644
--- a/arch/powerpc/sysdev/ipic.c
+++ b/arch/powerpc/sysdev/ipic.c
@@ -605,7 +605,7 @@ static int ipic_set_irq_type(unsigned int virq, unsigned int flow_type)
 {
         struct ipic *ipic = ipic_from_irq(virq);
         unsigned int src = ipic_irq_to_hw(virq);
-        struct irq_desc *desc = get_irq_desc(virq);
+        struct irq_desc *desc = irq_to_desc(virq);
         unsigned int vold, vnew, edibit;
 
         if (flow_type == IRQ_TYPE_NONE)
@@ -660,7 +660,7 @@ static int ipic_set_irq_type(unsigned int virq, unsigned int flow_type)
 
 /* level interrupts and edge interrupts have different ack operations */
 static struct irq_chip ipic_level_irq_chip = {
-        .typename       = " IPIC  ",
+        .name           = " IPIC  ",
         .unmask         = ipic_unmask_irq,
         .mask           = ipic_mask_irq,
         .mask_ack       = ipic_mask_irq,
@@ -668,7 +668,7 @@ static struct irq_chip ipic_level_irq_chip = {
 };
 
 static struct irq_chip ipic_edge_irq_chip = {
-        .typename       = " IPIC  ",
+        .name           = " IPIC  ",
         .unmask         = ipic_unmask_irq,
         .mask           = ipic_mask_irq,
         .mask_ack       = ipic_mask_irq_and_ack,
@@ -697,7 +697,7 @@ static int ipic_host_map(struct irq_host *h, unsigned int virq,
 }
 
 static int ipic_host_xlate(struct irq_host *h, struct device_node *ct,
-                           u32 *intspec, unsigned int intsize,
+                           const u32 *intspec, unsigned int intsize,
                            irq_hw_number_t *out_hwirq, unsigned int *out_flags)
 
 {
diff --git a/arch/powerpc/sysdev/mpc8xx_pic.c b/arch/powerpc/sysdev/mpc8xx_pic.c
index 5d2d5522ef41..69bd6f4dff83 100644
--- a/arch/powerpc/sysdev/mpc8xx_pic.c
+++ b/arch/powerpc/sysdev/mpc8xx_pic.c
@@ -72,7 +72,7 @@ static void mpc8xx_end_irq(unsigned int virq)
 
 static int mpc8xx_set_irq_type(unsigned int virq, unsigned int flow_type)
 {
-        struct irq_desc *desc = get_irq_desc(virq);
+        struct irq_desc *desc = irq_to_desc(virq);
 
         desc->status &= ~(IRQ_TYPE_SENSE_MASK | IRQ_LEVEL);
         desc->status |= flow_type & IRQ_TYPE_SENSE_MASK;
@@ -94,7 +94,7 @@ static int mpc8xx_set_irq_type(unsigned int virq, unsigned int flow_type)
 }
 
 static struct irq_chip mpc8xx_pic = {
-        .typename = " MPC8XX SIU ",
+        .name = " MPC8XX SIU ",
         .unmask = mpc8xx_unmask_irq,
         .mask = mpc8xx_mask_irq,
         .ack = mpc8xx_ack,
@@ -130,7 +130,7 @@ static int mpc8xx_pic_host_map(struct irq_host *h, unsigned int virq,
 
 
 static int mpc8xx_pic_host_xlate(struct irq_host *h, struct device_node *ct,
-                            u32 *intspec, unsigned int intsize,
+                            const u32 *intspec, unsigned int intsize,
                             irq_hw_number_t *out_hwirq, unsigned int *out_flags)
 {
         static unsigned char map_pic_senses[4] = {
diff --git a/arch/powerpc/sysdev/mpic.c b/arch/powerpc/sysdev/mpic.c
index 30c44e6b0413..aa9d06e5925b 100644
--- a/arch/powerpc/sysdev/mpic.c
+++ b/arch/powerpc/sysdev/mpic.c
@@ -572,7 +572,7 @@ static int irq_choose_cpu(unsigned int virt_irq)
         cpumask_t mask;
         int cpuid;
 
-        cpumask_copy(&mask, irq_desc[virt_irq].affinity);
+        cpumask_copy(&mask, irq_to_desc(virt_irq)->affinity);
         if (cpus_equal(mask, CPU_MASK_ALL)) {
                 static int irq_rover;
                 static DEFINE_SPINLOCK(irq_rover_lock);
@@ -621,7 +621,7 @@ static struct mpic *mpic_find(unsigned int irq)
         if (irq < NUM_ISA_INTERRUPTS)
                 return NULL;
 
-        return irq_desc[irq].chip_data;
+        return irq_to_desc(irq)->chip_data;
 }
 
 /* Determine if the linux irq is an IPI */
@@ -648,14 +648,14 @@ static inline u32 mpic_physmask(u32 cpumask)
 /* Get the mpic structure from the IPI number */
 static inline struct mpic * mpic_from_ipi(unsigned int ipi)
 {
-        return irq_desc[ipi].chip_data;
+        return irq_to_desc(ipi)->chip_data;
 }
 #endif
 
 /* Get the mpic structure from the irq number */
 static inline struct mpic * mpic_from_irq(unsigned int irq)
 {
-        return irq_desc[irq].chip_data;
+        return irq_to_desc(irq)->chip_data;
 }
 
 /* Send an EOI */
@@ -735,7 +735,7 @@ static void mpic_unmask_ht_irq(unsigned int irq)
 
         mpic_unmask_irq(irq);
 
-        if (irq_desc[irq].status & IRQ_LEVEL)
+        if (irq_to_desc(irq)->status & IRQ_LEVEL)
                 mpic_ht_end_irq(mpic, src);
 }
 
@@ -745,7 +745,7 @@ static unsigned int mpic_startup_ht_irq(unsigned int irq)
         unsigned int src = mpic_irq_to_hw(irq);
 
         mpic_unmask_irq(irq);
-        mpic_startup_ht_interrupt(mpic, src, irq_desc[irq].status);
+        mpic_startup_ht_interrupt(mpic, src, irq_to_desc(irq)->status);
 
         return 0;
 }
@@ -755,7 +755,7 @@ static void mpic_shutdown_ht_irq(unsigned int irq)
         struct mpic *mpic = mpic_from_irq(irq);
         unsigned int src = mpic_irq_to_hw(irq);
 
-        mpic_shutdown_ht_interrupt(mpic, src, irq_desc[irq].status);
+        mpic_shutdown_ht_interrupt(mpic, src, irq_to_desc(irq)->status);
         mpic_mask_irq(irq);
 }
 
@@ -772,7 +772,7 @@ static void mpic_end_ht_irq(unsigned int irq)
          * latched another edge interrupt coming in anyway
          */
 
-        if (irq_desc[irq].status & IRQ_LEVEL)
+        if (irq_to_desc(irq)->status & IRQ_LEVEL)
                 mpic_ht_end_irq(mpic, src);
         mpic_eoi(mpic);
 }
@@ -856,7 +856,7 @@ int mpic_set_irq_type(unsigned int virq, unsigned int flow_type)
 {
         struct mpic *mpic = mpic_from_irq(virq);
         unsigned int src = mpic_irq_to_hw(virq);
-        struct irq_desc *desc = get_irq_desc(virq);
+        struct irq_desc *desc = irq_to_desc(virq);
         unsigned int vecpri, vold, vnew;
 
         DBG("mpic: set_irq_type(mpic:@%p,virq:%d,src:0x%x,type:0x%x)\n",
@@ -994,7 +994,7 @@ static int mpic_host_map(struct irq_host *h, unsigned int virq,
 }
 
 static int mpic_host_xlate(struct irq_host *h, struct device_node *ct,
-                           u32 *intspec, unsigned int intsize,
+                           const u32 *intspec, unsigned int intsize,
                            irq_hw_number_t *out_hwirq, unsigned int *out_flags)
 
 {
@@ -1062,19 +1062,19 @@ struct mpic * __init mpic_alloc(struct device_node *node,
         mpic->name = name;
 
         mpic->hc_irq = mpic_irq_chip;
-        mpic->hc_irq.typename = name;
+        mpic->hc_irq.name = name;
         if (flags & MPIC_PRIMARY)
                 mpic->hc_irq.set_affinity = mpic_set_affinity;
 #ifdef CONFIG_MPIC_U3_HT_IRQS
         mpic->hc_ht_irq = mpic_irq_ht_chip;
-        mpic->hc_ht_irq.typename = name;
+        mpic->hc_ht_irq.name = name;
         if (flags & MPIC_PRIMARY)
                 mpic->hc_ht_irq.set_affinity = mpic_set_affinity;
 #endif /* CONFIG_MPIC_U3_HT_IRQS */
 
 #ifdef CONFIG_SMP
         mpic->hc_ipi = mpic_ipi_chip;
-        mpic->hc_ipi.typename = name;
+        mpic->hc_ipi.name = name;
 #endif /* CONFIG_SMP */
 
         mpic->flags = flags;
diff --git a/arch/powerpc/sysdev/mpic_pasemi_msi.c b/arch/powerpc/sysdev/mpic_pasemi_msi.c
index 656cb772b691..0f6ab06f8474 100644
--- a/arch/powerpc/sysdev/mpic_pasemi_msi.c
+++ b/arch/powerpc/sysdev/mpic_pasemi_msi.c
@@ -60,7 +60,7 @@ static struct irq_chip mpic_pasemi_msi_chip = {
         .eoi            = mpic_end_irq,
         .set_type       = mpic_set_irq_type,
         .set_affinity   = mpic_set_affinity,
-        .typename       = "PASEMI-MSI ",
+        .name           = "PASEMI-MSI ",
 };
 
 static int pasemi_msi_check_device(struct pci_dev *pdev, int nvec, int type)
diff --git a/arch/powerpc/sysdev/mpic_u3msi.c b/arch/powerpc/sysdev/mpic_u3msi.c
index 0a8f5a9e87c9..d3caf23e6312 100644
--- a/arch/powerpc/sysdev/mpic_u3msi.c
+++ b/arch/powerpc/sysdev/mpic_u3msi.c
@@ -42,7 +42,7 @@ static struct irq_chip mpic_u3msi_chip = {
         .eoi            = mpic_end_irq,
         .set_type       = mpic_set_irq_type,
         .set_affinity   = mpic_set_affinity,
-        .typename       = "MPIC-U3MSI",
+        .name           = "MPIC-U3MSI",
 };
 
 static u64 read_ht_magic_addr(struct pci_dev *pdev, unsigned int pos)
diff --git a/arch/powerpc/sysdev/mv64x60_pic.c b/arch/powerpc/sysdev/mv64x60_pic.c
index 2aa4ed066db1..485b92477d7c 100644
--- a/arch/powerpc/sysdev/mv64x60_pic.c
+++ b/arch/powerpc/sysdev/mv64x60_pic.c
@@ -213,7 +213,7 @@ static int mv64x60_host_map(struct irq_host *h, unsigned int virq,
 {
         int level1;
 
-        get_irq_desc(virq)->status |= IRQ_LEVEL;
+        irq_to_desc(virq)->status |= IRQ_LEVEL;
 
         level1 = (hwirq & MV64x60_LEVEL1_MASK) >> MV64x60_LEVEL1_OFFSET;
         BUG_ON(level1 > MV64x60_LEVEL1_GPP);
diff --git a/arch/powerpc/sysdev/qe_lib/qe.c b/arch/powerpc/sysdev/qe_lib/qe.c
index 464271bea6c9..149393c02c3f 100644
--- a/arch/powerpc/sysdev/qe_lib/qe.c
+++ b/arch/powerpc/sysdev/qe_lib/qe.c
@@ -27,6 +27,8 @@
 #include <linux/delay.h>
 #include <linux/ioport.h>
 #include <linux/crc32.h>
+#include <linux/mod_devicetable.h>
+#include <linux/of_platform.h>
 #include <asm/irq.h>
 #include <asm/page.h>
 #include <asm/pgtable.h>
@@ -65,19 +67,6 @@ static unsigned int qe_num_of_snum;
 
 static phys_addr_t qebase = -1;
 
-int qe_alive_during_sleep(void)
-{
-        static int ret = -1;
-
-        if (ret != -1)
-                return ret;
-
-        ret = !of_find_compatible_node(NULL, NULL, "fsl,mpc8569-pmc");
-
-        return ret;
-}
-EXPORT_SYMBOL(qe_alive_during_sleep);
-
 phys_addr_t get_qe_base(void)
 {
         struct device_node *qe;
@@ -104,7 +93,7 @@ phys_addr_t get_qe_base(void)
 
 EXPORT_SYMBOL(get_qe_base);
 
-void __init qe_reset(void)
+void qe_reset(void)
 {
         if (qe_immr == NULL)
                 qe_immr = ioremap(get_qe_base(), QE_IMMAP_SIZE);
@@ -330,16 +319,18 @@ EXPORT_SYMBOL(qe_put_snum);
 static int qe_sdma_init(void)
 {
         struct sdma __iomem *sdma = &qe_immr->sdma;
-        unsigned long sdma_buf_offset;
+        static unsigned long sdma_buf_offset = (unsigned long)-ENOMEM;
 
         if (!sdma)
                 return -ENODEV;
 
         /* allocate 2 internal temporary buffers (512 bytes size each) for
          * the SDMA */
-        sdma_buf_offset = qe_muram_alloc(512 * 2, 4096);
-        if (IS_ERR_VALUE(sdma_buf_offset))
-                return -ENOMEM;
+        if (IS_ERR_VALUE(sdma_buf_offset)) {
+                sdma_buf_offset = qe_muram_alloc(512 * 2, 4096);
+                if (IS_ERR_VALUE(sdma_buf_offset))
+                        return -ENOMEM;
+        }
 
         out_be32(&sdma->sdebcr, (u32) sdma_buf_offset & QE_SDEBCR_BA_MASK);
         out_be32(&sdma->sdmr, (QE_SDMR_GLB_1_MSK |
@@ -349,7 +340,7 @@ static int qe_sdma_init(void)
 }
 
 /* The maximum number of RISCs we support */
-#define MAX_QE_RISC     2
+#define MAX_QE_RISC     4
 
 /* Firmware information stored here for qe_get_firmware_info() */
 static struct qe_firmware_info qe_firmware_info;
@@ -658,3 +649,35 @@ unsigned int qe_get_num_of_snums(void)
         return num_of_snums;
 }
 EXPORT_SYMBOL(qe_get_num_of_snums);
+
+#if defined(CONFIG_SUSPEND) && defined(CONFIG_PPC_85xx)
+static int qe_resume(struct of_device *ofdev)
+{
+        if (!qe_alive_during_sleep())
+                qe_reset();
+        return 0;
+}
+
+static int qe_probe(struct of_device *ofdev, const struct of_device_id *id)
+{
+        return 0;
+}
+
+static const struct of_device_id qe_ids[] = {
+        { .compatible = "fsl,qe", },
+        { },
+};
+
+static struct of_platform_driver qe_driver = {
+        .driver.name = "fsl-qe",
+        .match_table = qe_ids,
+        .probe = qe_probe,
+        .resume = qe_resume,
+};
+
+static int __init qe_drv_init(void)
+{
+        return of_register_platform_driver(&qe_driver);
+}
+device_initcall(qe_drv_init);
+#endif /* defined(CONFIG_SUSPEND) && defined(CONFIG_PPC_85xx) */
diff --git a/arch/powerpc/sysdev/qe_lib/qe_ic.c b/arch/powerpc/sysdev/qe_lib/qe_ic.c
index 3faa42e03a85..2acc928d1920 100644
--- a/arch/powerpc/sysdev/qe_lib/qe_ic.c
+++ b/arch/powerpc/sysdev/qe_lib/qe_ic.c
@@ -189,7 +189,7 @@ static inline void qe_ic_write(volatile __be32  __iomem * base, unsigned int reg
 
 static inline struct qe_ic *qe_ic_from_irq(unsigned int virq)
 {
-        return irq_desc[virq].chip_data;
+        return irq_to_desc(virq)->chip_data;
 }
 
 #define virq_to_hw(virq)        ((unsigned int)irq_map[virq].hwirq)
@@ -237,7 +237,7 @@ static void qe_ic_mask_irq(unsigned int virq)
 }
 
 static struct irq_chip qe_ic_irq_chip = {
-        .typename = " QEIC  ",
+        .name = " QEIC  ",
         .unmask = qe_ic_unmask_irq,
         .mask = qe_ic_mask_irq,
         .mask_ack = qe_ic_mask_irq,
@@ -263,7 +263,7 @@ static int qe_ic_host_map(struct irq_host *h, unsigned int virq,
         chip = &qe_ic->hc_irq;
 
         set_irq_chip_data(virq, qe_ic);
-        get_irq_desc(virq)->status |= IRQ_LEVEL;
+        irq_to_desc(virq)->status |= IRQ_LEVEL;
 
         set_irq_chip_and_handler(virq, chip, handle_level_irq);
 
@@ -271,7 +271,7 @@ static int qe_ic_host_map(struct irq_host *h, unsigned int virq,
 }
 
 static int qe_ic_host_xlate(struct irq_host *h, struct device_node *ct,
-                            u32 * intspec, unsigned int intsize,
+                            const u32 * intspec, unsigned int intsize,
                             irq_hw_number_t * out_hwirq,
                             unsigned int *out_flags)
 {
diff --git a/arch/powerpc/sysdev/tsi108_pci.c b/arch/powerpc/sysdev/tsi108_pci.c
index cf244a419e96..595034cfb85a 100644
--- a/arch/powerpc/sysdev/tsi108_pci.c
+++ b/arch/powerpc/sysdev/tsi108_pci.c
@@ -376,7 +376,7 @@ static void tsi108_pci_irq_end(u_int irq)
  */
 
 static struct irq_chip tsi108_pci_irq = {
-        .typename = "tsi108_PCI_int",
+        .name = "tsi108_PCI_int",
         .mask = tsi108_pci_irq_disable,
         .ack = tsi108_pci_irq_ack,
         .end = tsi108_pci_irq_end,
@@ -384,7 +384,7 @@ static struct irq_chip tsi108_pci_irq = {
 };
 
 static int pci_irq_host_xlate(struct irq_host *h, struct device_node *ct,
-                            u32 *intspec, unsigned int intsize,
+                            const u32 *intspec, unsigned int intsize,
                             irq_hw_number_t *out_hwirq, unsigned int *out_flags)
 {
         *out_hwirq = intspec[0];
@@ -398,7 +398,7 @@ static int pci_irq_host_map(struct irq_host *h, unsigned int virq,
         DBG("%s(%d, 0x%lx)\n", __func__, virq, hw);
         if ((virq >= 1) && (virq <= 4)){
                 irq = virq + IRQ_PCI_INTAD_BASE - 1;
-                get_irq_desc(irq)->status |= IRQ_LEVEL;
+                irq_to_desc(irq)->status |= IRQ_LEVEL;
                 set_irq_chip(irq, &tsi108_pci_irq);
         }
         return 0;
diff --git a/arch/powerpc/sysdev/uic.c b/arch/powerpc/sysdev/uic.c
index 466ce9ace127..6f220a913e42 100644
--- a/arch/powerpc/sysdev/uic.c
+++ b/arch/powerpc/sysdev/uic.c
@@ -57,7 +57,7 @@ struct uic {
 
 static void uic_unmask_irq(unsigned int virq)
 {
-        struct irq_desc *desc = get_irq_desc(virq);
+        struct irq_desc *desc = irq_to_desc(virq);
         struct uic *uic = get_irq_chip_data(virq);
         unsigned int src = uic_irq_to_hw(virq);
         unsigned long flags;
@@ -101,7 +101,7 @@ static void uic_ack_irq(unsigned int virq)
 
 static void uic_mask_ack_irq(unsigned int virq)
 {
-        struct irq_desc *desc = get_irq_desc(virq);
+        struct irq_desc *desc = irq_to_desc(virq);
         struct uic *uic = get_irq_chip_data(virq);
         unsigned int src = uic_irq_to_hw(virq);
         unsigned long flags;
@@ -129,7 +129,7 @@ static int uic_set_irq_type(unsigned int virq, unsigned int flow_type)
 {
         struct uic *uic = get_irq_chip_data(virq);
         unsigned int src = uic_irq_to_hw(virq);
-        struct irq_desc *desc = get_irq_desc(virq);
+        struct irq_desc *desc = irq_to_desc(virq);
         unsigned long flags;
         int trigger, polarity;
         u32 tr, pr, mask;
@@ -177,7 +177,7 @@ static int uic_set_irq_type(unsigned int virq, unsigned int flow_type)
 }
 
 static struct irq_chip uic_irq_chip = {
-        .typename       = " UIC  ",
+        .name           = " UIC  ",
         .unmask         = uic_unmask_irq,
         .mask           = uic_mask_irq,
         .mask_ack       = uic_mask_ack_irq,
@@ -202,7 +202,7 @@ static int uic_host_map(struct irq_host *h, unsigned int virq,
 }
 
 static int uic_host_xlate(struct irq_host *h, struct device_node *ct,
-                          u32 *intspec, unsigned int intsize,
+                          const u32 *intspec, unsigned int intsize,
                           irq_hw_number_t *out_hwirq, unsigned int *out_type)
 
 {
@@ -225,12 +225,12 @@ void uic_irq_cascade(unsigned int virq, struct irq_desc *desc)
         int src;
         int subvirq;
 
-        spin_lock(&desc->lock);
+        raw_spin_lock(&desc->lock);
         if (desc->status & IRQ_LEVEL)
                 desc->chip->mask(virq);
         else
                 desc->chip->mask_ack(virq);
-        spin_unlock(&desc->lock);
+        raw_spin_unlock(&desc->lock);
 
         msr = mfdcr(uic->dcrbase + UIC_MSR);
         if (!msr) /* spurious interrupt */
@@ -242,12 +242,12 @@ void uic_irq_cascade(unsigned int virq, struct irq_desc *desc)
         generic_handle_irq(subvirq);
 
 uic_irq_ret:
-        spin_lock(&desc->lock);
+        raw_spin_lock(&desc->lock);
         if (desc->status & IRQ_LEVEL)
                 desc->chip->ack(virq);
         if (!(desc->status & IRQ_DISABLED) && desc->chip->unmask)
                 desc->chip->unmask(virq);
-        spin_unlock(&desc->lock);
+        raw_spin_unlock(&desc->lock);
 }
 
 static struct uic * __init uic_init_one(struct device_node *node)
diff --git a/arch/powerpc/sysdev/xilinx_intc.c b/arch/powerpc/sysdev/xilinx_intc.c
index 40edad520770..1e0ccfaf403e 100644
--- a/arch/powerpc/sysdev/xilinx_intc.c
+++ b/arch/powerpc/sysdev/xilinx_intc.c
@@ -79,7 +79,7 @@ static void xilinx_intc_mask(unsigned int virq)
 
 static int xilinx_intc_set_type(unsigned int virq, unsigned int flow_type)
 {
-        struct irq_desc *desc = get_irq_desc(virq);
+        struct irq_desc *desc = irq_to_desc(virq);
 
         desc->status &= ~(IRQ_TYPE_SENSE_MASK | IRQ_LEVEL);
         desc->status |= flow_type & IRQ_TYPE_SENSE_MASK;
@@ -106,7 +106,7 @@ static void xilinx_intc_level_unmask(unsigned int virq)
 }
 
 static struct irq_chip xilinx_intc_level_irqchip = {
-        .typename = "Xilinx Level INTC",
+        .name = "Xilinx Level INTC",
         .mask = xilinx_intc_mask,
         .mask_ack = xilinx_intc_mask,
         .unmask = xilinx_intc_level_unmask,
@@ -133,7 +133,7 @@ static void xilinx_intc_edge_ack(unsigned int virq)
 }
 
 static struct irq_chip xilinx_intc_edge_irqchip = {
-        .typename = "Xilinx Edge  INTC",
+        .name = "Xilinx Edge  INTC",
         .mask = xilinx_intc_mask,
         .unmask = xilinx_intc_edge_unmask,
         .ack = xilinx_intc_edge_ack,
@@ -148,7 +148,7 @@ static struct irq_chip xilinx_intc_edge_irqchip = {
  * xilinx_intc_xlate - translate virq# from device tree interrupts property
  */
 static int xilinx_intc_xlate(struct irq_host *h, struct device_node *ct,
-                                u32 *intspec, unsigned int intsize,
+                                const u32 *intspec, unsigned int intsize,
                                 irq_hw_number_t *out_hwirq,
                                 unsigned int *out_flags)
 {
diff --git a/arch/powerpc/xmon/xmon.c b/arch/powerpc/xmon/xmon.c
index bdbe96c8a7e4..4e6152c13764 100644
--- a/arch/powerpc/xmon/xmon.c
+++ b/arch/powerpc/xmon/xmon.c
@@ -1641,7 +1641,8 @@ static void super_regs(void)
                                ptrLpPaca->saved_srr0, ptrLpPaca->saved_srr1);
                         printf("    Saved Gpr3=%.16lx  Saved Gpr4=%.16lx \n",
                                ptrLpPaca->saved_gpr3, ptrLpPaca->saved_gpr4);
-                        printf("    Saved Gpr5=%.16lx \n", ptrLpPaca->saved_gpr5);
+                        printf("    Saved Gpr5=%.16lx \n",
+                                ptrLpPaca->gpr5_dword.saved_gpr5);
                 }
 #endif
 
diff --git a/arch/s390/appldata/appldata_base.c b/arch/s390/appldata/appldata_base.c
index 495589950dc7..5c91995b74e4 100644
--- a/arch/s390/appldata/appldata_base.c
+++ b/arch/s390/appldata/appldata_base.c
@@ -551,7 +551,7 @@ static int appldata_thaw(struct device *dev)
         return appldata_restore(dev);
 }
 
-static struct dev_pm_ops appldata_pm_ops = {
+static const struct dev_pm_ops appldata_pm_ops = {
         .freeze         = appldata_freeze,
         .thaw           = appldata_thaw,
         .restore        = appldata_restore,
diff --git a/arch/s390/include/asm/asm-offsets.h b/arch/s390/include/asm/asm-offsets.h
new file mode 100644
index 000000000000..d370ee36a182
--- /dev/null
+++ b/arch/s390/include/asm/asm-offsets.h
@@ -0,0 +1 @@
+#include <generated/asm-offsets.h>
diff --git a/arch/s390/include/asm/elf.h b/arch/s390/include/asm/elf.h
index e885442c1dfe..354d42616c7e 100644
--- a/arch/s390/include/asm/elf.h
+++ b/arch/s390/include/asm/elf.h
@@ -155,7 +155,6 @@ extern unsigned int vdso_enabled;
         } while (0)
 
 #define CORE_DUMP_USE_REGSET
-#define USE_ELF_CORE_DUMP
 #define ELF_EXEC_PAGESIZE       4096
 
 /* This is the location that an ET_DYN program is loaded if exec'ed.  Typical
diff --git a/arch/s390/include/asm/spinlock.h b/arch/s390/include/asm/spinlock.h
index c9af0d19c7ab..a587907d77f3 100644
--- a/arch/s390/include/asm/spinlock.h
+++ b/arch/s390/include/asm/spinlock.h
@@ -52,27 +52,27 @@ _raw_compare_and_swap(volatile unsigned int *lock,
  * (the type definitions are in asm/spinlock_types.h)
  */
 
-#define __raw_spin_is_locked(x) ((x)->owner_cpu != 0)
-#define __raw_spin_unlock_wait(lock) \
-        do { while (__raw_spin_is_locked(lock)) \
-                 _raw_spin_relax(lock); } while (0)
+#define arch_spin_is_locked(x) ((x)->owner_cpu != 0)
+#define arch_spin_unlock_wait(lock) \
+        do { while (arch_spin_is_locked(lock)) \
+                 arch_spin_relax(lock); } while (0)
 
-extern void _raw_spin_lock_wait(raw_spinlock_t *);
-extern void _raw_spin_lock_wait_flags(raw_spinlock_t *, unsigned long flags);
-extern int _raw_spin_trylock_retry(raw_spinlock_t *);
-extern void _raw_spin_relax(raw_spinlock_t *lock);
+extern void arch_spin_lock_wait(arch_spinlock_t *);
+extern void arch_spin_lock_wait_flags(arch_spinlock_t *, unsigned long flags);
+extern int arch_spin_trylock_retry(arch_spinlock_t *);
+extern void arch_spin_relax(arch_spinlock_t *lock);
 
-static inline void __raw_spin_lock(raw_spinlock_t *lp)
+static inline void arch_spin_lock(arch_spinlock_t *lp)
 {
         int old;
 
         old = _raw_compare_and_swap(&lp->owner_cpu, 0, ~smp_processor_id());
         if (likely(old == 0))
                 return;
-        _raw_spin_lock_wait(lp);
+        arch_spin_lock_wait(lp);
 }
 
-static inline void __raw_spin_lock_flags(raw_spinlock_t *lp,
+static inline void arch_spin_lock_flags(arch_spinlock_t *lp,
                                          unsigned long flags)
 {
         int old;
@@ -80,20 +80,20 @@ static inline void __raw_spin_lock_flags(raw_spinlock_t *lp,
         old = _raw_compare_and_swap(&lp->owner_cpu, 0, ~smp_processor_id());
         if (likely(old == 0))
                 return;
-        _raw_spin_lock_wait_flags(lp, flags);
+        arch_spin_lock_wait_flags(lp, flags);
 }
 
-static inline int __raw_spin_trylock(raw_spinlock_t *lp)
+static inline int arch_spin_trylock(arch_spinlock_t *lp)
 {
         int old;
 
         old = _raw_compare_and_swap(&lp->owner_cpu, 0, ~smp_processor_id());
         if (likely(old == 0))
                 return 1;
-        return _raw_spin_trylock_retry(lp);
+        return arch_spin_trylock_retry(lp);
 }
 
-static inline void __raw_spin_unlock(raw_spinlock_t *lp)
+static inline void arch_spin_unlock(arch_spinlock_t *lp)
 {
         _raw_compare_and_swap(&lp->owner_cpu, lp->owner_cpu, 0);
 }
@@ -113,22 +113,22 @@ static inline void __raw_spin_unlock(raw_spinlock_t *lp)
  * read_can_lock - would read_trylock() succeed?
  * @lock: the rwlock in question.
  */
-#define __raw_read_can_lock(x) ((int)(x)->lock >= 0)
+#define arch_read_can_lock(x) ((int)(x)->lock >= 0)
 
 /**
  * write_can_lock - would write_trylock() succeed?
  * @lock: the rwlock in question.
  */
-#define __raw_write_can_lock(x) ((x)->lock == 0)
+#define arch_write_can_lock(x) ((x)->lock == 0)
 
-extern void _raw_read_lock_wait(raw_rwlock_t *lp);
-extern void _raw_read_lock_wait_flags(raw_rwlock_t *lp, unsigned long flags);
-extern int _raw_read_trylock_retry(raw_rwlock_t *lp);
-extern void _raw_write_lock_wait(raw_rwlock_t *lp);
-extern void _raw_write_lock_wait_flags(raw_rwlock_t *lp, unsigned long flags);
-extern int _raw_write_trylock_retry(raw_rwlock_t *lp);
+extern void _raw_read_lock_wait(arch_rwlock_t *lp);
+extern void _raw_read_lock_wait_flags(arch_rwlock_t *lp, unsigned long flags);
+extern int _raw_read_trylock_retry(arch_rwlock_t *lp);
+extern void _raw_write_lock_wait(arch_rwlock_t *lp);
+extern void _raw_write_lock_wait_flags(arch_rwlock_t *lp, unsigned long flags);
+extern int _raw_write_trylock_retry(arch_rwlock_t *lp);
 
-static inline void __raw_read_lock(raw_rwlock_t *rw)
+static inline void arch_read_lock(arch_rwlock_t *rw)
 {
         unsigned int old;
         old = rw->lock & 0x7fffffffU;
@@ -136,7 +136,7 @@ static inline void __raw_read_lock(raw_rwlock_t *rw)
                 _raw_read_lock_wait(rw);
 }
 
-static inline void __raw_read_lock_flags(raw_rwlock_t *rw, unsigned long flags)
+static inline void arch_read_lock_flags(arch_rwlock_t *rw, unsigned long flags)
 {
         unsigned int old;
         old = rw->lock & 0x7fffffffU;
@@ -144,7 +144,7 @@ static inline void __raw_read_lock_flags(raw_rwlock_t *rw, unsigned long flags)
                 _raw_read_lock_wait_flags(rw, flags);
 }
 
-static inline void __raw_read_unlock(raw_rwlock_t *rw)
+static inline void arch_read_unlock(arch_rwlock_t *rw)
 {
         unsigned int old, cmp;
 
@@ -155,24 +155,24 @@ static inline void __raw_read_unlock(raw_rwlock_t *rw)
         } while (cmp != old);
 }
 
-static inline void __raw_write_lock(raw_rwlock_t *rw)
+static inline void arch_write_lock(arch_rwlock_t *rw)
 {
         if (unlikely(_raw_compare_and_swap(&rw->lock, 0, 0x80000000) != 0))
                 _raw_write_lock_wait(rw);
 }
 
-static inline void __raw_write_lock_flags(raw_rwlock_t *rw, unsigned long flags)
+static inline void arch_write_lock_flags(arch_rwlock_t *rw, unsigned long flags)
 {
         if (unlikely(_raw_compare_and_swap(&rw->lock, 0, 0x80000000) != 0))
                 _raw_write_lock_wait_flags(rw, flags);
 }
 
-static inline void __raw_write_unlock(raw_rwlock_t *rw)
+static inline void arch_write_unlock(arch_rwlock_t *rw)
 {
         _raw_compare_and_swap(&rw->lock, 0x80000000, 0);
 }
 
-static inline int __raw_read_trylock(raw_rwlock_t *rw)
+static inline int arch_read_trylock(arch_rwlock_t *rw)
 {
         unsigned int old;
         old = rw->lock & 0x7fffffffU;
@@ -181,14 +181,14 @@ static inline int __raw_read_trylock(raw_rwlock_t *rw)
         return _raw_read_trylock_retry(rw);
 }
 
-static inline int __raw_write_trylock(raw_rwlock_t *rw)
+static inline int arch_write_trylock(arch_rwlock_t *rw)
 {
         if (likely(_raw_compare_and_swap(&rw->lock, 0, 0x80000000) == 0))
                 return 1;
         return _raw_write_trylock_retry(rw);
 }
 
-#define _raw_read_relax(lock)   cpu_relax()
-#define _raw_write_relax(lock)  cpu_relax()
+#define arch_read_relax(lock)   cpu_relax()
+#define arch_write_relax(lock)  cpu_relax()
 
 #endif /* __ASM_SPINLOCK_H */
diff --git a/arch/s390/include/asm/spinlock_types.h b/arch/s390/include/asm/spinlock_types.h
index 654abc40de04..9c76656a0af0 100644
--- a/arch/s390/include/asm/spinlock_types.h
+++ b/arch/s390/include/asm/spinlock_types.h
@@ -7,14 +7,14 @@
 
 typedef struct {
         volatile unsigned int owner_cpu;
-} __attribute__ ((aligned (4))) raw_spinlock_t;
+} __attribute__ ((aligned (4))) arch_spinlock_t;
 
-#define __RAW_SPIN_LOCK_UNLOCKED        { 0 }
+#define __ARCH_SPIN_LOCK_UNLOCKED       { 0 }
 
 typedef struct {
         volatile unsigned int lock;
-} raw_rwlock_t;
+} arch_rwlock_t;
 
-#define __RAW_RW_LOCK_UNLOCKED          { 0 }
+#define __ARCH_RW_LOCK_UNLOCKED         { 0 }
 
 #endif
diff --git a/arch/s390/kernel/compat_linux.c b/arch/s390/kernel/compat_linux.c
index 25c31d681402..22c9e557bb22 100644
--- a/arch/s390/kernel/compat_linux.c
+++ b/arch/s390/kernel/compat_linux.c
@@ -624,38 +624,6 @@ struct mmap_arg_struct_emu31 {
         u32     offset;
 };
 
-/* common code for old and new mmaps */
-static inline long do_mmap2(
-        unsigned long addr, unsigned long len,
-        unsigned long prot, unsigned long flags,
-        unsigned long fd, unsigned long pgoff)
-{
-        struct file * file = NULL;
-        unsigned long error = -EBADF;
-
-        flags &= ~(MAP_EXECUTABLE | MAP_DENYWRITE);
-        if (!(flags & MAP_ANONYMOUS)) {
-                file = fget(fd);
-                if (!file)
-                        goto out;
-        }
-
-        down_write(&current->mm->mmap_sem);
-        error = do_mmap_pgoff(file, addr, len, prot, flags, pgoff);
-        if (!IS_ERR((void *) error) && error + len >= 0x80000000ULL) {
-                /* Result is out of bounds.  */
-                do_munmap(current->mm, addr, len);
-                error = -ENOMEM;
-        }
-        up_write(&current->mm->mmap_sem);
-
-        if (file)
-                fput(file);
-out:    
-        return error;
-}
-
-
 asmlinkage unsigned long
 old32_mmap(struct mmap_arg_struct_emu31 __user *arg)
 {
@@ -669,7 +637,8 @@ old32_mmap(struct mmap_arg_struct_emu31 __user *arg)
         if (a.offset & ~PAGE_MASK)
                 goto out;
 
-        error = do_mmap2(a.addr, a.len, a.prot, a.flags, a.fd, a.offset >> PAGE_SHIFT); 
+        error = sys_mmap_pgoff(a.addr, a.len, a.prot, a.flags, a.fd,
+                               a.offset >> PAGE_SHIFT);
 out:
         return error;
 }
@@ -682,7 +651,7 @@ sys32_mmap2(struct mmap_arg_struct_emu31 __user *arg)
 
         if (copy_from_user(&a, arg, sizeof(a)))
                 goto out;
-        error = do_mmap2(a.addr, a.len, a.prot, a.flags, a.fd, a.offset);
+        error = sys_mmap_pgoff(a.addr, a.len, a.prot, a.flags, a.fd, a.offset);
 out:
         return error;
 }
diff --git a/arch/s390/kernel/debug.c b/arch/s390/kernel/debug.c
index 071c81f179ef..0168472b2fdf 100644
--- a/arch/s390/kernel/debug.c
+++ b/arch/s390/kernel/debug.c
@@ -18,6 +18,7 @@
 #include <linux/errno.h>
 #include <linux/slab.h>
 #include <linux/ctype.h>
+#include <linux/string.h>
 #include <linux/sysctl.h>
 #include <asm/uaccess.h>
 #include <linux/module.h>
@@ -1178,7 +1179,7 @@ debug_get_uint(char *buf)
 {
         int rc;
 
-        for(; isspace(*buf); buf++);
+        buf = skip_spaces(buf);
         rc = simple_strtoul(buf, &buf, 10);
         if(*buf){
                 rc = -EINVAL;
diff --git a/arch/s390/kernel/sys_s390.c b/arch/s390/kernel/sys_s390.c
index e9d94f61d500..86a74c9c9e63 100644
--- a/arch/s390/kernel/sys_s390.c
+++ b/arch/s390/kernel/sys_s390.c
@@ -32,32 +32,6 @@
 #include <asm/uaccess.h>
 #include "entry.h"
 
-/* common code for old and new mmaps */
-static inline long do_mmap2(
-        unsigned long addr, unsigned long len,
-        unsigned long prot, unsigned long flags,
-        unsigned long fd, unsigned long pgoff)
-{
-        long error = -EBADF;
-        struct file * file = NULL;
-
-        flags &= ~(MAP_EXECUTABLE | MAP_DENYWRITE);
-        if (!(flags & MAP_ANONYMOUS)) {
-                file = fget(fd);
-                if (!file)
-                        goto out;
-        }
-
-        down_write(&current->mm->mmap_sem);
-        error = do_mmap_pgoff(file, addr, len, prot, flags, pgoff);
-        up_write(&current->mm->mmap_sem);
-
-        if (file)
-                fput(file);
-out:
-        return error;
-}
-
 /*
  * Perform the select(nd, in, out, ex, tv) and mmap() system
  * calls. Linux for S/390 isn't able to handle more than 5
@@ -81,7 +55,7 @@ SYSCALL_DEFINE1(mmap2, struct mmap_arg_struct __user *, arg)
 
         if (copy_from_user(&a, arg, sizeof(a)))
                 goto out;
-        error = do_mmap2(a.addr, a.len, a.prot, a.flags, a.fd, a.offset);
+        error = sys_mmap_pgoff(a.addr, a.len, a.prot, a.flags, a.fd, a.offset);
 out:
         return error;
 }
@@ -98,7 +72,7 @@ SYSCALL_DEFINE1(s390_old_mmap, struct mmap_arg_struct __user *, arg)
         if (a.offset & ~PAGE_MASK)
                 goto out;
 
-        error = do_mmap2(a.addr, a.len, a.prot, a.flags, a.fd, a.offset >> PAGE_SHIFT);
+        error = sys_mmap_pgoff(a.addr, a.len, a.prot, a.flags, a.fd, a.offset >> PAGE_SHIFT);
 out:
         return error;
 }
diff --git a/arch/s390/lib/spinlock.c b/arch/s390/lib/spinlock.c
index f7e0d30250b7..10754a375668 100644
--- a/arch/s390/lib/spinlock.c
+++ b/arch/s390/lib/spinlock.c
@@ -39,7 +39,7 @@ static inline void _raw_yield_cpu(int cpu)
                 _raw_yield();
 }
 
-void _raw_spin_lock_wait(raw_spinlock_t *lp)
+void arch_spin_lock_wait(arch_spinlock_t *lp)
 {
         int count = spin_retry;
         unsigned int cpu = ~smp_processor_id();
@@ -51,15 +51,15 @@ void _raw_spin_lock_wait(raw_spinlock_t *lp)
                                 _raw_yield_cpu(~owner);
                         count = spin_retry;
                 }
-                if (__raw_spin_is_locked(lp))
+                if (arch_spin_is_locked(lp))
                         continue;
                 if (_raw_compare_and_swap(&lp->owner_cpu, 0, cpu) == 0)
                         return;
         }
 }
-EXPORT_SYMBOL(_raw_spin_lock_wait);
+EXPORT_SYMBOL(arch_spin_lock_wait);
 
-void _raw_spin_lock_wait_flags(raw_spinlock_t *lp, unsigned long flags)
+void arch_spin_lock_wait_flags(arch_spinlock_t *lp, unsigned long flags)
 {
         int count = spin_retry;
         unsigned int cpu = ~smp_processor_id();
@@ -72,7 +72,7 @@ void _raw_spin_lock_wait_flags(raw_spinlock_t *lp, unsigned long flags)
                                 _raw_yield_cpu(~owner);
                         count = spin_retry;
                 }
-                if (__raw_spin_is_locked(lp))
+                if (arch_spin_is_locked(lp))
                         continue;
                 local_irq_disable();
                 if (_raw_compare_and_swap(&lp->owner_cpu, 0, cpu) == 0)
@@ -80,32 +80,32 @@ void _raw_spin_lock_wait_flags(raw_spinlock_t *lp, unsigned long flags)
                 local_irq_restore(flags);
         }
 }
-EXPORT_SYMBOL(_raw_spin_lock_wait_flags);
+EXPORT_SYMBOL(arch_spin_lock_wait_flags);
 
-int _raw_spin_trylock_retry(raw_spinlock_t *lp)
+int arch_spin_trylock_retry(arch_spinlock_t *lp)
 {
         unsigned int cpu = ~smp_processor_id();
         int count;
 
         for (count = spin_retry; count > 0; count--) {
-                if (__raw_spin_is_locked(lp))
+                if (arch_spin_is_locked(lp))
                         continue;
                 if (_raw_compare_and_swap(&lp->owner_cpu, 0, cpu) == 0)
                         return 1;
         }
         return 0;
 }
-EXPORT_SYMBOL(_raw_spin_trylock_retry);
+EXPORT_SYMBOL(arch_spin_trylock_retry);
 
-void _raw_spin_relax(raw_spinlock_t *lock)
+void arch_spin_relax(arch_spinlock_t *lock)
 {
         unsigned int cpu = lock->owner_cpu;
         if (cpu != 0)
                 _raw_yield_cpu(~cpu);
 }
-EXPORT_SYMBOL(_raw_spin_relax);
+EXPORT_SYMBOL(arch_spin_relax);
 
-void _raw_read_lock_wait(raw_rwlock_t *rw)
+void _raw_read_lock_wait(arch_rwlock_t *rw)
 {
         unsigned int old;
         int count = spin_retry;
@@ -115,7 +115,7 @@ void _raw_read_lock_wait(raw_rwlock_t *rw)
                         _raw_yield();
                         count = spin_retry;
                 }
-                if (!__raw_read_can_lock(rw))
+                if (!arch_read_can_lock(rw))
                         continue;
                 old = rw->lock & 0x7fffffffU;
                 if (_raw_compare_and_swap(&rw->lock, old, old + 1) == old)
@@ -124,7 +124,7 @@ void _raw_read_lock_wait(raw_rwlock_t *rw)
 }
 EXPORT_SYMBOL(_raw_read_lock_wait);
 
-void _raw_read_lock_wait_flags(raw_rwlock_t *rw, unsigned long flags)
+void _raw_read_lock_wait_flags(arch_rwlock_t *rw, unsigned long flags)
 {
         unsigned int old;
         int count = spin_retry;
@@ -135,7 +135,7 @@ void _raw_read_lock_wait_flags(raw_rwlock_t *rw, unsigned long flags)
                         _raw_yield();
                         count = spin_retry;
                 }
-                if (!__raw_read_can_lock(rw))
+                if (!arch_read_can_lock(rw))
                         continue;
                 old = rw->lock & 0x7fffffffU;
                 local_irq_disable();
@@ -145,13 +145,13 @@ void _raw_read_lock_wait_flags(raw_rwlock_t *rw, unsigned long flags)
 }
 EXPORT_SYMBOL(_raw_read_lock_wait_flags);
 
-int _raw_read_trylock_retry(raw_rwlock_t *rw)
+int _raw_read_trylock_retry(arch_rwlock_t *rw)
 {
         unsigned int old;
         int count = spin_retry;
 
         while (count-- > 0) {
-                if (!__raw_read_can_lock(rw))
+                if (!arch_read_can_lock(rw))
                         continue;
                 old = rw->lock & 0x7fffffffU;
                 if (_raw_compare_and_swap(&rw->lock, old, old + 1) == old)
@@ -161,7 +161,7 @@ int _raw_read_trylock_retry(raw_rwlock_t *rw)
 }
 EXPORT_SYMBOL(_raw_read_trylock_retry);
 
-void _raw_write_lock_wait(raw_rwlock_t *rw)
+void _raw_write_lock_wait(arch_rwlock_t *rw)
 {
         int count = spin_retry;
 
@@ -170,7 +170,7 @@ void _raw_write_lock_wait(raw_rwlock_t *rw)
                         _raw_yield();
                         count = spin_retry;
                 }
-                if (!__raw_write_can_lock(rw))
+                if (!arch_write_can_lock(rw))
                         continue;
                 if (_raw_compare_and_swap(&rw->lock, 0, 0x80000000) == 0)
                         return;
@@ -178,7 +178,7 @@ void _raw_write_lock_wait(raw_rwlock_t *rw)
 }
 EXPORT_SYMBOL(_raw_write_lock_wait);
 
-void _raw_write_lock_wait_flags(raw_rwlock_t *rw, unsigned long flags)
+void _raw_write_lock_wait_flags(arch_rwlock_t *rw, unsigned long flags)
 {
         int count = spin_retry;
 
@@ -188,7 +188,7 @@ void _raw_write_lock_wait_flags(raw_rwlock_t *rw, unsigned long flags)
                         _raw_yield();
                         count = spin_retry;
                 }
-                if (!__raw_write_can_lock(rw))
+                if (!arch_write_can_lock(rw))
                         continue;
                 local_irq_disable();
                 if (_raw_compare_and_swap(&rw->lock, 0, 0x80000000) == 0)
@@ -197,12 +197,12 @@ void _raw_write_lock_wait_flags(raw_rwlock_t *rw, unsigned long flags)
 }
 EXPORT_SYMBOL(_raw_write_lock_wait_flags);
 
-int _raw_write_trylock_retry(raw_rwlock_t *rw)
+int _raw_write_trylock_retry(arch_rwlock_t *rw)
 {
         int count = spin_retry;
 
         while (count-- > 0) {
-                if (!__raw_write_can_lock(rw))
+                if (!arch_write_can_lock(rw))
                         continue;
                 if (_raw_compare_and_swap(&rw->lock, 0, 0x80000000) == 0)
                         return 1;
diff --git a/arch/score/include/asm/asm-offsets.h b/arch/score/include/asm/asm-offsets.h
new file mode 100644
index 000000000000..d370ee36a182
--- /dev/null
+++ b/arch/score/include/asm/asm-offsets.h
@@ -0,0 +1 @@
+#include <generated/asm-offsets.h>
diff --git a/arch/score/include/asm/cacheflush.h b/arch/score/include/asm/cacheflush.h
index caaba24036e3..1d545d0ce206 100644
--- a/arch/score/include/asm/cacheflush.h
+++ b/arch/score/include/asm/cacheflush.h
@@ -14,10 +14,12 @@ extern void flush_cache_sigtramp(unsigned long addr);
 extern void flush_icache_all(void);
 extern void flush_icache_range(unsigned long start, unsigned long end);
 extern void flush_dcache_range(unsigned long start, unsigned long end);
+extern void flush_dcache_page(struct page *page);
+
+#define PG_dcache_dirty         PG_arch_1
 
 #define flush_cache_dup_mm(mm)                  do {} while (0)
 #define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 0
-#define flush_dcache_page(page)                 do {} while (0)
 #define flush_dcache_mmap_lock(mapping)         do {} while (0)
 #define flush_dcache_mmap_unlock(mapping)       do {} while (0)
 #define flush_cache_vmap(start, end)            do {} while (0)
diff --git a/arch/score/include/asm/delay.h b/arch/score/include/asm/delay.h
index 6726ec199dc0..529e494712a5 100644
--- a/arch/score/include/asm/delay.h
+++ b/arch/score/include/asm/delay.h
@@ -1,6 +1,8 @@
 #ifndef _ASM_SCORE_DELAY_H
 #define _ASM_SCORE_DELAY_H
 
+#include <asm-generic/param.h>
+
 static inline void __delay(unsigned long loops)
 {
         /* 3 cycles per loop. */
diff --git a/arch/score/include/asm/elf.h b/arch/score/include/asm/elf.h
index 43526d9fda93..f478ce94181f 100644
--- a/arch/score/include/asm/elf.h
+++ b/arch/score/include/asm/elf.h
@@ -61,7 +61,6 @@ struct task_struct;
 struct pt_regs;
 
 #define CORE_DUMP_USE_REGSET
-#define USE_ELF_CORE_DUMP
 #define ELF_EXEC_PAGESIZE       PAGE_SIZE
 
 /* This yields a mask that user programs can use to figure out what
diff --git a/arch/score/include/asm/page.h b/arch/score/include/asm/page.h
index d92a5a2d36d4..1e9ade8e77e6 100644
--- a/arch/score/include/asm/page.h
+++ b/arch/score/include/asm/page.h
@@ -74,7 +74,7 @@ extern unsigned long max_pfn;
 #define page_to_bus(page)       (page_to_phys(page))
 #define phys_to_page(paddr)     (pfn_to_page(phys_to_pfn(paddr)))
 
-#define pfn_valid(pfn)          ((pfn) >= min_low_pfn && (pfn) < max_mapnr)
+#define pfn_valid(pfn)          (((pfn) >= min_low_pfn) && ((pfn) < max_low_pfn))
 
 #define ARCH_PFN_OFFSET         (PAGE_OFFSET >> PAGE_SHIFT)
 
diff --git a/arch/score/kernel/setup.c b/arch/score/kernel/setup.c
index 6a2503c75c4e..6f898c057878 100644
--- a/arch/score/kernel/setup.c
+++ b/arch/score/kernel/setup.c
@@ -49,6 +49,7 @@ static void __init bootmem_init(void)
 
         min_low_pfn = PFN_UP(MEMORY_START);
         max_low_pfn = PFN_UP(MEMORY_START + MEMORY_SIZE);
+        max_mapnr = max_low_pfn - min_low_pfn;
 
         /* Initialize the boot-time allocator with low memory only. */
         bootmap_size = init_bootmem_node(NODE_DATA(0), start_pfn,
diff --git a/arch/score/kernel/sys_score.c b/arch/score/kernel/sys_score.c
index 001249469866..856ed68a58e6 100644
--- a/arch/score/kernel/sys_score.c
+++ b/arch/score/kernel/sys_score.c
@@ -36,34 +36,16 @@ asmlinkage long
 sys_mmap2(unsigned long addr, unsigned long len, unsigned long prot,
           unsigned long flags, unsigned long fd, unsigned long pgoff)
 {
-        int error = -EBADF;
-        struct file *file = NULL;
-
-        if (pgoff & (~PAGE_MASK >> 12))
-                return -EINVAL;
-
-        flags &= ~(MAP_EXECUTABLE | MAP_DENYWRITE);
-        if (!(flags & MAP_ANONYMOUS)) {
-                file = fget(fd);
-                if (!file)
-                        return error;
-        }
-
-        down_write(&current->mm->mmap_sem);
-        error = do_mmap_pgoff(file, addr, len, prot, flags, pgoff);
-        up_write(&current->mm->mmap_sem);
-
-        if (file)
-                fput(file);
-
-        return error;
+        return sys_mmap_pgoff(addr, len, prot, flags, fd, pgoff);
 }
 
 asmlinkage long
 sys_mmap(unsigned long addr, unsigned long len, unsigned long prot,
-        unsigned long flags, unsigned long fd, off_t pgoff)
+        unsigned long flags, unsigned long fd, off_t offset)
 {
-        return sys_mmap2(addr, len, prot, flags, fd, pgoff >> PAGE_SHIFT);
+        if (unlikely(offset & ~PAGE_MASK))
+                return -EINVAL;
+        return sys_mmap_pgoff(addr, len, prot, flags, fd, offset >> PAGE_SHIFT);
 }
 
 asmlinkage long
diff --git a/arch/score/mm/cache.c b/arch/score/mm/cache.c
index dbac9d9dfddd..b25e95743600 100644
--- a/arch/score/mm/cache.c
+++ b/arch/score/mm/cache.c
@@ -29,6 +29,7 @@
 #include <linux/mm.h>
 #include <linux/module.h>
 #include <linux/sched.h>
+#include <linux/fs.h>
 
 #include <asm/mmu_context.h>
 
@@ -51,6 +52,27 @@ static void flush_data_cache_page(unsigned long addr)
         }
 }
 
+void flush_dcache_page(struct page *page)
+{
+        struct address_space *mapping = page_mapping(page);
+        unsigned long addr;
+
+        if (PageHighMem(page))
+                return;
+        if (mapping && !mapping_mapped(mapping)) {
+                set_bit(PG_dcache_dirty, &(page)->flags);
+                return;
+        }
+
+        /*
+         * We could delay the flush for the !page_mapping case too.  But that
+         * case is for exec env/arg pages and those are %99 certainly going to
+         * get faulted into the tlb (and thus flushed) anyways.
+         */
+        addr = (unsigned long) page_address(page);
+        flush_data_cache_page(addr);
+}
+
 /* called by update_mmu_cache. */
 void __update_cache(struct vm_area_struct *vma, unsigned long address,
                 pte_t pte)
@@ -63,11 +85,11 @@ void __update_cache(struct vm_area_struct *vma, unsigned long address,
         if (unlikely(!pfn_valid(pfn)))
                 return;
         page = pfn_to_page(pfn);
-        if (page_mapping(page) && test_bit(PG_arch_1, &page->flags)) {
+        if (page_mapping(page) && test_bit(PG_dcache_dirty, &(page)->flags)) {
                 addr = (unsigned long) page_address(page);
                 if (exec)
                         flush_data_cache_page(addr);
-                clear_bit(PG_arch_1, &page->flags);
+                clear_bit(PG_dcache_dirty, &(page)->flags);
         }
 }
 
diff --git a/arch/score/mm/init.c b/arch/score/mm/init.c
index 4e3dcd0c4716..8c15b2c85d5a 100644
--- a/arch/score/mm/init.c
+++ b/arch/score/mm/init.c
@@ -83,7 +83,6 @@ void __init mem_init(void)
         unsigned long codesize, reservedpages, datasize, initsize;
         unsigned long tmp, ram = 0;
 
-        max_mapnr = max_low_pfn;
         high_memory = (void *) __va(max_low_pfn << PAGE_SHIFT);
         totalram_pages += free_all_bootmem();
         totalram_pages -= setup_zero_page();    /* Setup zeroed pages. */
@@ -101,10 +100,6 @@ void __init mem_init(void)
         datasize = (unsigned long) &_edata - (unsigned long) &_etext;
         initsize = (unsigned long) &__init_end - (unsigned long) &__init_begin;
 
-        kclist_add(&kcore_mem, __va(0), max_low_pfn << PAGE_SHIFT);
-        kclist_add(&kcore_vmalloc, (void *) VMALLOC_START,
-                        VMALLOC_END - VMALLOC_START);
-
         printk(KERN_INFO "Memory: %luk/%luk available (%ldk kernel code, "
                         "%ldk reserved, %ldk data, %ldk init, %ldk highmem)\n",
                         (unsigned long) nr_free_pages() << (PAGE_SHIFT-10),
diff --git a/arch/sh/Kconfig.debug b/arch/sh/Kconfig.debug
index 55907af1dc25..12fec72fec5f 100644
--- a/arch/sh/Kconfig.debug
+++ b/arch/sh/Kconfig.debug
@@ -19,50 +19,6 @@ config SH_STANDARD_BIOS
           mask ROM and no flash (WindowsCE machines fall in this category).
           If unsure, say N.
 
-config EARLY_SCIF_CONSOLE
-        bool "Use early SCIF console"
-        help
-          This enables an early console using a fixed SCIF port. This can
-          be used by platforms that are either not running the SH
-          standard BIOS, or do not wish to use the BIOS callbacks for the
-          serial I/O.
-
-config EARLY_SCIF_CONSOLE_PORT
-        hex
-        depends on EARLY_SCIF_CONSOLE
-        default "0xa4400000" if CPU_SUBTYPE_SH7712 || CPU_SUBTYPE_SH7705
-        default "0xa4430000" if CPU_SUBTYPE_SH7720 || CPU_SUBTYPE_SH7721
-        default "0xf8420000" if CPU_SUBTYPE_SH7619
-        default "0xff804000" if CPU_SUBTYPE_MXG
-        default "0xffc30000" if CPU_SUBTYPE_SHX3
-        default "0xffe00000" if CPU_SUBTYPE_SH7780 || CPU_SUBTYPE_SH7763 || \
-                                CPU_SUBTYPE_SH7722 || CPU_SUBTYPE_SH7366 || \
-                                CPU_SUBTYPE_SH7343
-        default "0xfe4c0000" if CPU_SUBTYPE_SH7757
-        default "0xffeb0000" if CPU_SUBTYPE_SH7785
-        default "0xffeb0000" if CPU_SUBTYPE_SH7786
-        default "0xfffe8000" if CPU_SUBTYPE_SH7203
-        default "0xfffe9800" if CPU_SUBTYPE_SH7206 || CPU_SUBTYPE_SH7263
-        default "0xffe80000" if CPU_SH4
-        default "0xa4000150" if CPU_SH3
-        default "0x00000000"
-
-config EARLY_PRINTK
-        bool "Early printk support"
-        depends on SH_STANDARD_BIOS || EARLY_SCIF_CONSOLE
-        help
-          Say Y here to redirect kernel printk messages to the serial port
-          used by the SH-IPL bootloader, starting very early in the boot
-          process and ending when the kernel's serial console is initialised.
-          This option is only useful porting the kernel to a new machine,
-          when the kernel may crash or hang before the serial console is
-          initialised. If unsure, say N.
-
-          On devices that are running SH-IPL and want to keep the port
-          initialization consistent while not using the BIOS callbacks,
-          select both the EARLY_SCIF_CONSOLE and SH_STANDARD_BIOS, using
-          the kernel command line option to toggle back and forth.
-
 config STACK_DEBUG
         bool "Check for stack overflows"
         depends on DEBUG_KERNEL && SUPERH32
diff --git a/arch/sh/Makefile b/arch/sh/Makefile
index ac17c5ac550e..db91925c79d1 100644
--- a/arch/sh/Makefile
+++ b/arch/sh/Makefile
@@ -205,10 +205,7 @@ libs-$(CONFIG_SUPERH64)		:= arch/sh/lib64/ $(libs-y)
 
 BOOT_TARGETS = uImage uImage.bz2 uImage.gz uImage.lzma uImage.srec uImage.bin \
                zImage vmlinux.srec romImage
-PHONY += maketools $(BOOT_TARGETS) FORCE
-
-maketools:  include/linux/version.h FORCE
-        $(Q)$(MAKE) $(build)=arch/sh/tools include/asm-sh/machtypes.h
+PHONY += $(BOOT_TARGETS)
 
 all: $(KBUILD_IMAGE)
 
@@ -217,7 +214,8 @@ $(BOOT_TARGETS): vmlinux
 
 compressed: zImage
 
-archprepare: maketools
+archprepare:
+        $(Q)$(MAKE) $(build)=arch/sh/tools include/generated/machtypes.h
 
 archclean:
         $(Q)$(MAKE) $(clean)=$(boot)
@@ -234,5 +232,3 @@ define archhelp
         @echo '  uImage.bz2                - Kernel-only image for U-Boot (bzip2)'
         @echo '  uImage.lzma               - Kernel-only image for U-Boot (lzma)'
 endef
-
-CLEAN_FILES += include/asm-sh/machtypes.h
diff --git a/arch/sh/boards/mach-ap325rxa/setup.c b/arch/sh/boards/mach-ap325rxa/setup.c
index cf9dc12dfeb1..1f5fa5c44f6d 100644
--- a/arch/sh/boards/mach-ap325rxa/setup.c
+++ b/arch/sh/boards/mach-ap325rxa/setup.c
@@ -316,20 +316,24 @@ static struct soc_camera_platform_info camera_info = {
         .format_name = "UYVY",
         .format_depth = 16,
         .format = {
-                .pixelformat = V4L2_PIX_FMT_UYVY,
+                .code = V4L2_MBUS_FMT_YUYV8_2X8_BE,
                 .colorspace = V4L2_COLORSPACE_SMPTE170M,
+                .field = V4L2_FIELD_NONE,
                 .width = 640,
                 .height = 480,
         },
         .bus_param = SOCAM_PCLK_SAMPLE_RISING | SOCAM_HSYNC_ACTIVE_HIGH |
-        SOCAM_VSYNC_ACTIVE_HIGH | SOCAM_MASTER | SOCAM_DATAWIDTH_8,
+        SOCAM_VSYNC_ACTIVE_HIGH | SOCAM_MASTER | SOCAM_DATAWIDTH_8 |
+        SOCAM_DATA_ACTIVE_HIGH,
         .set_capture = camera_set_capture,
-        .link = {
-                .bus_id         = 0,
-                .add_device     = ap325rxa_camera_add,
-                .del_device     = ap325rxa_camera_del,
-                .module_name    = "soc_camera_platform",
-        },
+};
+
+struct soc_camera_link camera_link = {
+        .bus_id         = 0,
+        .add_device     = ap325rxa_camera_add,
+        .del_device     = ap325rxa_camera_del,
+        .module_name    = "soc_camera_platform",
+        .priv           = &camera_info,
 };
 
 static void dummy_release(struct device *dev)
@@ -347,7 +351,7 @@ static struct platform_device camera_device = {
 static int ap325rxa_camera_add(struct soc_camera_link *icl,
                                struct device *dev)
 {
-        if (icl != &camera_info.link || camera_probe() <= 0)
+        if (icl != &camera_link || camera_probe() <= 0)
                 return -ENODEV;
 
         camera_info.dev = dev;
@@ -357,7 +361,7 @@ static int ap325rxa_camera_add(struct soc_camera_link *icl,
 
 static void ap325rxa_camera_del(struct soc_camera_link *icl)
 {
-        if (icl != &camera_info.link)
+        if (icl != &camera_link)
                 return;
 
         platform_device_unregister(&camera_device);
@@ -470,13 +474,15 @@ static struct ov772x_camera_info ov7725_info = {
         .buswidth       = SOCAM_DATAWIDTH_8,
         .flags          = OV772X_FLAG_VFLIP | OV772X_FLAG_HFLIP,
         .edgectrl       = OV772X_AUTO_EDGECTRL(0xf, 0),
-        .link = {
-                .bus_id         = 0,
-                .power          = ov7725_power,
-                .board_info     = &ap325rxa_i2c_camera[0],
-                .i2c_adapter_id = 0,
-                .module_name    = "ov772x",
-        },
+};
+
+static struct soc_camera_link ov7725_link = {
+        .bus_id         = 0,
+        .power          = ov7725_power,
+        .board_info     = &ap325rxa_i2c_camera[0],
+        .i2c_adapter_id = 0,
+        .module_name    = "ov772x",
+        .priv           = &ov7725_info,
 };
 
 static struct platform_device ap325rxa_camera[] = {
@@ -484,13 +490,13 @@ static struct platform_device ap325rxa_camera[] = {
                 .name   = "soc-camera-pdrv",
                 .id     = 0,
                 .dev    = {
-                        .platform_data = &ov7725_info.link,
+                        .platform_data = &ov7725_link,
                 },
         }, {
                 .name   = "soc-camera-pdrv",
                 .id     = 1,
                 .dev    = {
-                        .platform_data = &camera_info.link,
+                        .platform_data = &camera_link,
                 },
         },
 };
diff --git a/arch/sh/boards/mach-ecovec24/setup.c b/arch/sh/boards/mach-ecovec24/setup.c
index 826e62326d51..194aaca22d47 100644
--- a/arch/sh/boards/mach-ecovec24/setup.c
+++ b/arch/sh/boards/mach-ecovec24/setup.c
@@ -19,11 +19,18 @@
 #include <linux/usb/r8a66597.h>
 #include <linux/i2c.h>
 #include <linux/i2c/tsc2007.h>
+#include <linux/spi/spi.h>
+#include <linux/spi/sh_msiof.h>
+#include <linux/spi/mmc_spi.h>
+#include <linux/mmc/host.h>
 #include <linux/input.h>
 #include <linux/input/sh_keysc.h>
 #include <linux/mfd/sh_mobile_sdhi.h>
 #include <video/sh_mobile_lcdc.h>
+#include <sound/sh_fsi.h>
 #include <media/sh_mobile_ceu.h>
+#include <media/tw9910.h>
+#include <media/mt9t112.h>
 #include <asm/heartbeat.h>
 #include <asm/sh_eth.h>
 #include <asm/clock.h>
@@ -338,6 +345,12 @@ static struct platform_device ceu1_device = {
 };
 
 /* I2C device */
+static struct i2c_board_info i2c0_devices[] = {
+        {
+                I2C_BOARD_INFO("da7210", 0x1a),
+        },
+};
+
 static struct i2c_board_info i2c1_devices[] = {
         {
                 I2C_BOARD_INFO("r2025sd", 0x32),
@@ -421,6 +434,7 @@ static struct i2c_board_info ts_i2c_clients = {
         .irq            = IRQ0,
 };
 
+#ifdef CONFIG_MFD_SH_MOBILE_SDHI
 /* SHDI0 */
 static void sdhi0_set_pwr(struct platform_device *pdev, int state)
 {
@@ -493,6 +507,248 @@ static struct platform_device sdhi1_device = {
         },
 };
 
+#else
+
+static int mmc_spi_get_ro(struct device *dev)
+{
+        return gpio_get_value(GPIO_PTY6);
+}
+
+static int mmc_spi_get_cd(struct device *dev)
+{
+        return !gpio_get_value(GPIO_PTY7);
+}
+
+static void mmc_spi_setpower(struct device *dev, unsigned int maskval)
+{
+        gpio_set_value(GPIO_PTB6, maskval ? 1 : 0);
+}
+
+static struct mmc_spi_platform_data mmc_spi_info = {
+        .get_ro = mmc_spi_get_ro,
+        .get_cd = mmc_spi_get_cd,
+        .caps = MMC_CAP_NEEDS_POLL,
+        .ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34, /* 3.3V only */
+        .setpower = mmc_spi_setpower,
+};
+
+static struct spi_board_info spi_bus[] = {
+        {
+                .modalias       = "mmc_spi",
+                .platform_data  = &mmc_spi_info,
+                .max_speed_hz   = 5000000,
+                .mode           = SPI_MODE_0,
+                .controller_data = (void *) GPIO_PTM4,
+        },
+};
+
+static struct sh_msiof_spi_info msiof0_data = {
+        .num_chipselect = 1,
+};
+
+static struct resource msiof0_resources[] = {
+        [0] = {
+                .name   = "MSIOF0",
+                .start  = 0xa4c40000,
+                .end    = 0xa4c40063,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = 84,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device msiof0_device = {
+        .name           = "spi_sh_msiof",
+        .id             = 0, /* MSIOF0 */
+        .dev = {
+                .platform_data = &msiof0_data,
+        },
+        .num_resources  = ARRAY_SIZE(msiof0_resources),
+        .resource       = msiof0_resources,
+        .archdata = {
+                .hwblk_id = HWBLK_MSIOF0,
+        },
+};
+
+#endif
+
+/* I2C Video/Camera */
+static struct i2c_board_info i2c_camera[] = {
+        {
+                I2C_BOARD_INFO("tw9910", 0x45),
+        },
+        {
+                /* 1st camera */
+                I2C_BOARD_INFO("mt9t112", 0x3c),
+        },
+        {
+                /* 2nd camera */
+                I2C_BOARD_INFO("mt9t112", 0x3c),
+        },
+};
+
+/* tw9910 */
+static int tw9910_power(struct device *dev, int mode)
+{
+        int val = mode ? 0 : 1;
+
+        gpio_set_value(GPIO_PTU2, val);
+        if (mode)
+                mdelay(100);
+
+        return 0;
+}
+
+static struct tw9910_video_info tw9910_info = {
+        .buswidth       = SOCAM_DATAWIDTH_8,
+        .mpout          = TW9910_MPO_FIELD,
+};
+
+static struct soc_camera_link tw9910_link = {
+        .i2c_adapter_id = 0,
+        .bus_id         = 1,
+        .power          = tw9910_power,
+        .board_info     = &i2c_camera[0],
+        .module_name    = "tw9910",
+        .priv           = &tw9910_info,
+};
+
+/* mt9t112 */
+static int mt9t112_power1(struct device *dev, int mode)
+{
+        gpio_set_value(GPIO_PTA3, mode);
+        if (mode)
+                mdelay(100);
+
+        return 0;
+}
+
+static struct mt9t112_camera_info mt9t112_info1 = {
+        .flags = MT9T112_FLAG_PCLK_RISING_EDGE | MT9T112_FLAG_DATAWIDTH_8,
+        .divider = { 0x49, 0x6, 0, 6, 0, 9, 9, 6, 0 }, /* for 24MHz */
+};
+
+static struct soc_camera_link mt9t112_link1 = {
+        .i2c_adapter_id = 0,
+        .power          = mt9t112_power1,
+        .bus_id         = 0,
+        .board_info     = &i2c_camera[1],
+        .module_name    = "mt9t112",
+        .priv           = &mt9t112_info1,
+};
+
+static int mt9t112_power2(struct device *dev, int mode)
+{
+        gpio_set_value(GPIO_PTA4, mode);
+        if (mode)
+                mdelay(100);
+
+        return 0;
+}
+
+static struct mt9t112_camera_info mt9t112_info2 = {
+        .flags = MT9T112_FLAG_PCLK_RISING_EDGE | MT9T112_FLAG_DATAWIDTH_8,
+        .divider = { 0x49, 0x6, 0, 6, 0, 9, 9, 6, 0 }, /* for 24MHz */
+};
+
+static struct soc_camera_link mt9t112_link2 = {
+        .i2c_adapter_id = 1,
+        .power          = mt9t112_power2,
+        .bus_id         = 1,
+        .board_info     = &i2c_camera[2],
+        .module_name    = "mt9t112",
+        .priv           = &mt9t112_info2,
+};
+
+static struct platform_device camera_devices[] = {
+        {
+                .name   = "soc-camera-pdrv",
+                .id     = 0,
+                .dev    = {
+                        .platform_data = &tw9910_link,
+                },
+        },
+        {
+                .name   = "soc-camera-pdrv",
+                .id     = 1,
+                .dev    = {
+                        .platform_data = &mt9t112_link1,
+                },
+        },
+        {
+                .name   = "soc-camera-pdrv",
+                .id     = 2,
+                .dev    = {
+                        .platform_data = &mt9t112_link2,
+                },
+        },
+};
+
+/* FSI */
+/*
+ * FSI-B use external clock which came from da7210.
+ * So, we should change parent of fsi
+ */
+#define FCLKBCR         0xa415000c
+static void fsimck_init(struct clk *clk)
+{
+        u32 status = ctrl_inl(clk->enable_reg);
+
+        /* use external clock */
+        status &= ~0x000000ff;
+        status |= 0x00000080;
+
+        ctrl_outl(status, clk->enable_reg);
+}
+
+static struct clk_ops fsimck_clk_ops = {
+        .init = fsimck_init,
+};
+
+static struct clk fsimckb_clk = {
+        .name           = "fsimckb_clk",
+        .id             = -1,
+        .ops            = &fsimck_clk_ops,
+        .enable_reg     = (void __iomem *)FCLKBCR,
+        .rate           = 0, /* unknown */
+};
+
+struct sh_fsi_platform_info fsi_info = {
+        .portb_flags = SH_FSI_BRS_INV |
+                       SH_FSI_OUT_SLAVE_MODE |
+                       SH_FSI_IN_SLAVE_MODE |
+                       SH_FSI_OFMT(I2S) |
+                       SH_FSI_IFMT(I2S),
+};
+
+static struct resource fsi_resources[] = {
+        [0] = {
+                .name   = "FSI",
+                .start  = 0xFE3C0000,
+                .end    = 0xFE3C021d,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = 108,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device fsi_device = {
+        .name           = "sh_fsi",
+        .id             = 0,
+        .num_resources  = ARRAY_SIZE(fsi_resources),
+        .resource       = fsi_resources,
+        .dev    = {
+                .platform_data  = &fsi_info,
+        },
+        .archdata = {
+                .hwblk_id = HWBLK_SPU, /* FSI needs SPU hwblk */
+        },
+};
+
 static struct platform_device *ecovec_devices[] __initdata = {
         &heartbeat_device,
         &nor_flash_device,
@@ -503,8 +759,16 @@ static struct platform_device *ecovec_devices[] __initdata = {
         &ceu0_device,
         &ceu1_device,
         &keysc_device,
+#ifdef CONFIG_MFD_SH_MOBILE_SDHI
         &sdhi0_device,
         &sdhi1_device,
+#else
+        &msiof0_device,
+#endif
+        &camera_devices[0],
+        &camera_devices[1],
+        &camera_devices[2],
+        &fsi_device,
 };
 
 #define EEPROM_ADDR 0x50
@@ -560,6 +824,8 @@ extern char ecovec24_sdram_leave_end;
 
 static int __init arch_setup(void)
 {
+        struct clk *clk;
+
         /* register board specific self-refresh code */
         sh_mobile_register_self_refresh(SUSP_SH_STANDBY | SUSP_SH_SF,
                                         &ecovec24_sdram_enter_start,
@@ -773,7 +1039,8 @@ static int __init arch_setup(void)
         gpio_direction_input(GPIO_PTR5);
         gpio_direction_input(GPIO_PTR6);
 
-        /* enable SDHI0 (needs DS2.4 set to ON) */
+#ifdef CONFIG_MFD_SH_MOBILE_SDHI
+        /* enable SDHI0 on CN11 (needs DS2.4 set to ON) */
         gpio_request(GPIO_FN_SDHI0CD,  NULL);
         gpio_request(GPIO_FN_SDHI0WP,  NULL);
         gpio_request(GPIO_FN_SDHI0CMD, NULL);
@@ -785,7 +1052,7 @@ static int __init arch_setup(void)
         gpio_request(GPIO_PTB6, NULL);
         gpio_direction_output(GPIO_PTB6, 0);
 
-        /* enable SDHI1 (needs DS2.6,7 set to ON,OFF) */
+        /* enable SDHI1 on CN12 (needs DS2.6,7 set to ON,OFF) */
         gpio_request(GPIO_FN_SDHI1CD,  NULL);
         gpio_request(GPIO_FN_SDHI1WP,  NULL);
         gpio_request(GPIO_FN_SDHI1CMD, NULL);
@@ -799,8 +1066,59 @@ static int __init arch_setup(void)
 
         /* I/O buffer drive ability is high for SDHI1 */
         ctrl_outw((ctrl_inw(IODRIVEA) & ~0x3000) | 0x2000 , IODRIVEA);
+#else
+        /* enable MSIOF0 on CN11 (needs DS2.4 set to OFF) */
+        gpio_request(GPIO_FN_MSIOF0_TXD, NULL);
+        gpio_request(GPIO_FN_MSIOF0_RXD, NULL);
+        gpio_request(GPIO_FN_MSIOF0_TSCK, NULL);
+        gpio_request(GPIO_PTM4, NULL); /* software CS control of TSYNC pin */
+        gpio_direction_output(GPIO_PTM4, 1); /* active low CS */
+        gpio_request(GPIO_PTB6, NULL); /* 3.3V power control */
+        gpio_direction_output(GPIO_PTB6, 0); /* disable power by default */
+        gpio_request(GPIO_PTY6, NULL); /* write protect */
+        gpio_direction_input(GPIO_PTY6);
+        gpio_request(GPIO_PTY7, NULL); /* card detect */
+        gpio_direction_input(GPIO_PTY7);
+
+        spi_register_board_info(spi_bus, ARRAY_SIZE(spi_bus));
+#endif
+
+        /* enable Video */
+        gpio_request(GPIO_PTU2, NULL);
+        gpio_direction_output(GPIO_PTU2, 1);
+
+        /* enable Camera */
+        gpio_request(GPIO_PTA3, NULL);
+        gpio_request(GPIO_PTA4, NULL);
+        gpio_direction_output(GPIO_PTA3, 0);
+        gpio_direction_output(GPIO_PTA4, 0);
+
+        /* enable FSI */
+        gpio_request(GPIO_FN_FSIMCKB,    NULL);
+        gpio_request(GPIO_FN_FSIIBSD,    NULL);
+        gpio_request(GPIO_FN_FSIOBSD,    NULL);
+        gpio_request(GPIO_FN_FSIIBBCK,   NULL);
+        gpio_request(GPIO_FN_FSIIBLRCK,  NULL);
+        gpio_request(GPIO_FN_FSIOBBCK,   NULL);
+        gpio_request(GPIO_FN_FSIOBLRCK,  NULL);
+        gpio_request(GPIO_FN_CLKAUDIOBO, NULL);
+
+        /* change parent of FSI B */
+        clk = clk_get(NULL, "fsib_clk");
+        clk_register(&fsimckb_clk);
+        clk_set_parent(clk, &fsimckb_clk);
+        clk_set_rate(clk, 11000);
+        clk_set_rate(&fsimckb_clk, 11000);
+        clk_put(clk);
+
+        gpio_request(GPIO_PTU0, NULL);
+        gpio_direction_output(GPIO_PTU0, 0);
+        mdelay(20);
 
         /* enable I2C device */
+        i2c_register_board_info(0, i2c0_devices,
+                                ARRAY_SIZE(i2c0_devices));
+
         i2c_register_board_info(1, i2c1_devices,
                                 ARRAY_SIZE(i2c1_devices));
 
diff --git a/arch/sh/boards/mach-kfr2r09/lcd_wqvga.c b/arch/sh/boards/mach-kfr2r09/lcd_wqvga.c
index 8ccb1cc8b589..e9b970846c41 100644
--- a/arch/sh/boards/mach-kfr2r09/lcd_wqvga.c
+++ b/arch/sh/boards/mach-kfr2r09/lcd_wqvga.c
@@ -273,6 +273,12 @@ int kfr2r09_lcd_setup(void *board_data, void *sohandle,
         return 0;
 }
 
+void kfr2r09_lcd_start(void *board_data, void *sohandle,
+                       struct sh_mobile_lcdc_sys_bus_ops *so)
+{
+        write_memory_start(sohandle, so);
+}
+
 #define CTRL_CKSW       0x10
 #define CTRL_C10        0x20
 #define CTRL_CPSW       0x80
diff --git a/arch/sh/boards/mach-kfr2r09/setup.c b/arch/sh/boards/mach-kfr2r09/setup.c
index 87438d6603d6..5d7b5d92475e 100644
--- a/arch/sh/boards/mach-kfr2r09/setup.c
+++ b/arch/sh/boards/mach-kfr2r09/setup.c
@@ -19,6 +19,7 @@
 #include <linux/input/sh_keysc.h>
 #include <linux/i2c.h>
 #include <linux/usb/r8a66597.h>
+#include <media/rj54n1cb0c.h>
 #include <media/soc_camera.h>
 #include <media/sh_mobile_ceu.h>
 #include <video/sh_mobile_lcdc.h>
@@ -149,6 +150,7 @@ static struct sh_mobile_lcdc_info kfr2r09_sh_lcdc_info = {
                 },
                 .board_cfg = {
                         .setup_sys = kfr2r09_lcd_setup,
+                        .start_transfer = kfr2r09_lcd_start,
                         .display_on = kfr2r09_lcd_on,
                         .display_off = kfr2r09_lcd_off,
                 },
@@ -255,6 +257,9 @@ static struct i2c_board_info kfr2r09_i2c_camera = {
 
 static struct clk *camera_clk;
 
+/* set VIO_CKO clock to 25MHz */
+#define CEU_MCLK_FREQ 25000000
+
 #define DRVCRB 0xA405018C
 static int camera_power(struct device *dev, int mode)
 {
@@ -267,8 +272,7 @@ static int camera_power(struct device *dev, int mode)
                 if (IS_ERR(camera_clk))
                         return PTR_ERR(camera_clk);
 
-                /* set VIO_CKO clock to 25MHz */
-                rate = clk_round_rate(camera_clk, 25000000);
+                rate = clk_round_rate(camera_clk, CEU_MCLK_FREQ);
                 ret = clk_set_rate(camera_clk, rate);
                 if (ret < 0)
                         goto eclkrate;
@@ -318,11 +322,17 @@ eclkrate:
         return ret;
 }
 
+static struct rj54n1_pdata rj54n1_priv = {
+        .mclk_freq      = CEU_MCLK_FREQ,
+        .ioctl_high     = false,
+};
+
 static struct soc_camera_link rj54n1_link = {
         .power          = camera_power,
         .board_info     = &kfr2r09_i2c_camera,
         .i2c_adapter_id = 1,
         .module_name    = "rj54n1cb0c",
+        .priv           = &rj54n1_priv,
 };
 
 static struct platform_device kfr2r09_camera = {
diff --git a/arch/sh/boards/mach-migor/setup.c b/arch/sh/boards/mach-migor/setup.c
index 9099b6da9957..507c77be476d 100644
--- a/arch/sh/boards/mach-migor/setup.c
+++ b/arch/sh/boards/mach-migor/setup.c
@@ -432,23 +432,27 @@ static struct i2c_board_info migor_i2c_camera[] = {
 
 static struct ov772x_camera_info ov7725_info = {
         .buswidth       = SOCAM_DATAWIDTH_8,
-        .link = {
-                .power          = ov7725_power,
-                .board_info     = &migor_i2c_camera[0],
-                .i2c_adapter_id = 0,
-                .module_name    = "ov772x",
-        },
+};
+
+static struct soc_camera_link ov7725_link = {
+        .power          = ov7725_power,
+        .board_info     = &migor_i2c_camera[0],
+        .i2c_adapter_id = 0,
+        .module_name    = "ov772x",
+        .priv           = &ov7725_info,
 };
 
 static struct tw9910_video_info tw9910_info = {
         .buswidth       = SOCAM_DATAWIDTH_8,
         .mpout          = TW9910_MPO_FIELD,
-        .link = {
-                .power          = tw9910_power,
-                .board_info     = &migor_i2c_camera[1],
-                .i2c_adapter_id = 0,
-                .module_name    = "tw9910",
-        }
+};
+
+static struct soc_camera_link tw9910_link = {
+        .power          = tw9910_power,
+        .board_info     = &migor_i2c_camera[1],
+        .i2c_adapter_id = 0,
+        .module_name    = "tw9910",
+        .priv           = &tw9910_info,
 };
 
 static struct platform_device migor_camera[] = {
@@ -456,13 +460,13 @@ static struct platform_device migor_camera[] = {
                 .name   = "soc-camera-pdrv",
                 .id     = 0,
                 .dev    = {
-                        .platform_data = &ov7725_info.link,
+                        .platform_data = &ov7725_link,
                 },
         }, {
                 .name   = "soc-camera-pdrv",
                 .id     = 1,
                 .dev    = {
-                        .platform_data = &tw9910_info.link,
+                        .platform_data = &tw9910_link,
                 },
         },
 };
diff --git a/arch/sh/boards/mach-se/7722/irq.c b/arch/sh/boards/mach-se/7722/irq.c
index 4eb31acfafef..b221b6842b0d 100644
--- a/arch/sh/boards/mach-se/7722/irq.c
+++ b/arch/sh/boards/mach-se/7722/irq.c
@@ -57,15 +57,16 @@ static void se7722_irq_demux(unsigned int irq, struct irq_desc *desc)
  */
 void __init init_se7722_IRQ(void)
 {
-        int i;
+        int i, irq;
 
         ctrl_outw(0, IRQ01_MASK);       /* disable all irqs */
         ctrl_outw(0x2000, 0xb03fffec);  /* mrshpc irq enable */
 
         for (i = 0; i < SE7722_FPGA_IRQ_NR; i++) {
-                se7722_fpga_irq[i] = create_irq();
-                if (se7722_fpga_irq[i] < 0)
+                irq = create_irq();
+                if (irq < 0)
                         return;
+                se7722_fpga_irq[i] = irq;
 
                 set_irq_chip_and_handler_name(se7722_fpga_irq[i],
                                               &se7722_irq_chip,
diff --git a/arch/sh/boards/mach-se/7724/setup.c b/arch/sh/boards/mach-se/7724/setup.c
index 4b0f0c0dc2b8..5d0f70b46c97 100644
--- a/arch/sh/boards/mach-se/7724/setup.c
+++ b/arch/sh/boards/mach-se/7724/setup.c
@@ -514,6 +514,13 @@ static struct platform_device *ms7724se_devices[] __initdata = {
         &sdhi1_cn8_device,
 };
 
+/* I2C device */
+static struct i2c_board_info i2c0_devices[] = {
+        {
+                I2C_BOARD_INFO("ak4642", 0x12),
+        },
+};
+
 #define EEPROM_OP   0xBA206000
 #define EEPROM_ADR  0xBA206004
 #define EEPROM_DATA 0xBA20600C
@@ -575,6 +582,16 @@ extern char ms7724se_sdram_enter_end;
 extern char ms7724se_sdram_leave_start;
 extern char ms7724se_sdram_leave_end;
 
+
+static int __init arch_setup(void)
+{
+        /* enable I2C device */
+        i2c_register_board_info(0, i2c0_devices,
+                                ARRAY_SIZE(i2c0_devices));
+        return 0;
+}
+arch_initcall(arch_setup);
+
 static int __init devices_setup(void)
 {
         u16 sw = ctrl_inw(SW4140); /* select camera, monitor */
diff --git a/arch/sh/configs/ecovec24-romimage_defconfig b/arch/sh/configs/ecovec24-romimage_defconfig
index 0774924623cc..46874704e4e7 100644
--- a/arch/sh/configs/ecovec24-romimage_defconfig
+++ b/arch/sh/configs/ecovec24-romimage_defconfig
@@ -203,7 +203,7 @@ CONFIG_MMU=y
 CONFIG_PAGE_OFFSET=0x80000000
 CONFIG_FORCE_MAX_ZONEORDER=11
 CONFIG_MEMORY_START=0x08000000
-CONFIG_MEMORY_SIZE=0x08000000
+CONFIG_MEMORY_SIZE=0x10000000
 CONFIG_29BIT=y
 # CONFIG_X2TLB is not set
 CONFIG_VSYSCALL=y
diff --git a/arch/sh/configs/ecovec24_defconfig b/arch/sh/configs/ecovec24_defconfig
index ac6469718a2c..cad918437ca7 100644
--- a/arch/sh/configs/ecovec24_defconfig
+++ b/arch/sh/configs/ecovec24_defconfig
@@ -204,7 +204,7 @@ CONFIG_MMU=y
 CONFIG_PAGE_OFFSET=0x80000000
 CONFIG_FORCE_MAX_ZONEORDER=11
 CONFIG_MEMORY_START=0x08000000
-CONFIG_MEMORY_SIZE=0x08000000
+CONFIG_MEMORY_SIZE=0x10000000
 CONFIG_29BIT=y
 # CONFIG_X2TLB is not set
 CONFIG_VSYSCALL=y
diff --git a/arch/sh/configs/rts7751r2d1_defconfig b/arch/sh/configs/rts7751r2d1_defconfig
index f521e82cc19e..6f1126b3e487 100644
--- a/arch/sh/configs/rts7751r2d1_defconfig
+++ b/arch/sh/configs/rts7751r2d1_defconfig
@@ -324,7 +324,7 @@ CONFIG_ENTRY_OFFSET=0x00001000
 # CONFIG_UBC_WAKEUP is not set
 CONFIG_CMDLINE_OVERWRITE=y
 # CONFIG_CMDLINE_EXTEND is not set
-CONFIG_CMDLINE="console=tty0 console=ttySC0,115200 root=/dev/sda1 earlyprintk=serial"
+CONFIG_CMDLINE="console=tty0 console=ttySC1,115200 root=/dev/sda1"
 
 #
 # Bus options
diff --git a/arch/sh/configs/rts7751r2dplus_defconfig b/arch/sh/configs/rts7751r2dplus_defconfig
index a156cd1e0617..9215bbb13d6f 100644
--- a/arch/sh/configs/rts7751r2dplus_defconfig
+++ b/arch/sh/configs/rts7751r2dplus_defconfig
@@ -324,7 +324,7 @@ CONFIG_ENTRY_OFFSET=0x00001000
 # CONFIG_UBC_WAKEUP is not set
 CONFIG_CMDLINE_OVERWRITE=y
 # CONFIG_CMDLINE_EXTEND is not set
-CONFIG_CMDLINE="console=tty0 console=ttySC0,115200 root=/dev/sda1 earlyprintk=serial"
+CONFIG_CMDLINE="console=tty0 console=ttySC1,115200 root=/dev/sda1"
 
 #
 # Bus options
diff --git a/arch/sh/drivers/pci/fixups-rts7751r2d.c b/arch/sh/drivers/pci/fixups-rts7751r2d.c
index 052b354236dc..7898f14d6641 100644
--- a/arch/sh/drivers/pci/fixups-rts7751r2d.c
+++ b/arch/sh/drivers/pci/fixups-rts7751r2d.c
@@ -15,7 +15,7 @@
 #include <mach/lboxre2.h>
 #include <mach/r2d.h>
 #include "pci-sh4.h"
-#include <asm/machtypes.h>
+#include <generated/machtypes.h>
 
 #define PCIMCR_MRSET_OFF        0xBFFFFFFF
 #define PCIMCR_RFSH_OFF         0xFFFFFFFB
diff --git a/arch/sh/include/asm/.gitignore b/arch/sh/include/asm/.gitignore
deleted file mode 100644
index 378db779fb6c..000000000000
--- a/arch/sh/include/asm/.gitignore
+++ /dev/null
@@ -1 +0,0 @@
-machtypes.h
diff --git a/arch/sh/include/asm/asm-offsets.h b/arch/sh/include/asm/asm-offsets.h
new file mode 100644
index 000000000000..d370ee36a182
--- /dev/null
+++ b/arch/sh/include/asm/asm-offsets.h
@@ -0,0 +1 @@
+#include <generated/asm-offsets.h>
diff --git a/arch/sh/include/asm/elf.h b/arch/sh/include/asm/elf.h
index ccb1d93bb043..ac04255022b6 100644
--- a/arch/sh/include/asm/elf.h
+++ b/arch/sh/include/asm/elf.h
@@ -114,7 +114,6 @@ typedef struct user_fpu_struct elf_fpregset_t;
  */
 #define CORE_DUMP_USE_REGSET
 
-#define USE_ELF_CORE_DUMP
 #define ELF_FDPIC_CORE_EFLAGS   EF_SH_FDPIC
 #define ELF_EXEC_PAGESIZE       PAGE_SIZE
 
diff --git a/arch/sh/include/asm/io.h b/arch/sh/include/asm/io.h
index 512cd3e9d0ca..026dd659a640 100644
--- a/arch/sh/include/asm/io.h
+++ b/arch/sh/include/asm/io.h
@@ -233,11 +233,17 @@ unsigned long long poke_real_address_q(unsigned long long addr,
  * doesn't exist, so everything must go through page tables.
  */
 #ifdef CONFIG_MMU
-void __iomem *__ioremap(unsigned long offset, unsigned long size,
-                        unsigned long flags);
+void __iomem *__ioremap_caller(unsigned long offset, unsigned long size,
+                               unsigned long flags, void *caller);
 void __iounmap(void __iomem *addr);
 
 static inline void __iomem *
+__ioremap(unsigned long offset, unsigned long size, unsigned long flags)
+{
+        return __ioremap_caller(offset, size, flags, __builtin_return_address(0));
+}
+
+static inline void __iomem *
 __ioremap_mode(unsigned long offset, unsigned long size, unsigned long flags)
 {
 #if defined(CONFIG_SUPERH32) && !defined(CONFIG_PMB_FIXED) && !defined(CONFIG_PMB)
@@ -271,6 +277,7 @@ __ioremap_mode(unsigned long offset, unsigned long size, unsigned long flags)
         return __ioremap(offset, size, flags);
 }
 #else
+#define __ioremap(offset, size, flags)          ((void __iomem *)(offset))
 #define __ioremap_mode(offset, size, flags)     ((void __iomem *)(offset))
 #define __iounmap(addr)                         do { } while (0)
 #endif /* CONFIG_MMU */
diff --git a/arch/sh/include/asm/machvec.h b/arch/sh/include/asm/machvec.h
index 84dd37761f56..9c30955630ff 100644
--- a/arch/sh/include/asm/machvec.h
+++ b/arch/sh/include/asm/machvec.h
@@ -12,7 +12,7 @@
 
 #include <linux/types.h>
 #include <linux/time.h>
-#include <asm/machtypes.h>
+#include <generated/machtypes.h>
 
 struct sh_machine_vector {
         void (*mv_setup)(char **cmdline_p);
diff --git a/arch/sh/include/asm/pgtable_32.h b/arch/sh/include/asm/pgtable_32.h
index b35435516203..5003ee86f67b 100644
--- a/arch/sh/include/asm/pgtable_32.h
+++ b/arch/sh/include/asm/pgtable_32.h
@@ -344,7 +344,8 @@ static inline void set_pte(pte_t *ptep, pte_t pte)
 #define pte_special(pte)        ((pte).pte_low & _PAGE_SPECIAL)
 
 #ifdef CONFIG_X2TLB
-#define pte_write(pte)          ((pte).pte_high & _PAGE_EXT_USER_WRITE)
+#define pte_write(pte) \
+        ((pte).pte_high & (_PAGE_EXT_USER_WRITE | _PAGE_EXT_KERN_WRITE))
 #else
 #define pte_write(pte)          ((pte).pte_low & _PAGE_RW)
 #endif
@@ -358,7 +359,7 @@ static inline pte_t pte_##fn(pte_t pte) { pte.pte_##h op; return pte; }
  * individually toggled (and user permissions are entirely decoupled from
  * kernel permissions), we attempt to couple them a bit more sanely here.
  */
-PTE_BIT_FUNC(high, wrprotect, &= ~_PAGE_EXT_USER_WRITE);
+PTE_BIT_FUNC(high, wrprotect, &= ~(_PAGE_EXT_USER_WRITE | _PAGE_EXT_KERN_WRITE));
 PTE_BIT_FUNC(high, mkwrite, |= _PAGE_EXT_USER_WRITE | _PAGE_EXT_KERN_WRITE);
 PTE_BIT_FUNC(high, mkhuge, |= _PAGE_SZHUGE);
 #else
diff --git a/arch/sh/include/asm/spinlock.h b/arch/sh/include/asm/spinlock.h
index a28c9f0053fd..bdc0f3b6c56a 100644
--- a/arch/sh/include/asm/spinlock.h
+++ b/arch/sh/include/asm/spinlock.h
@@ -23,10 +23,10 @@
  * Your basic SMP spinlocks, allowing only a single CPU anywhere
  */
 
-#define __raw_spin_is_locked(x)         ((x)->lock <= 0)
-#define __raw_spin_lock_flags(lock, flags) __raw_spin_lock(lock)
-#define __raw_spin_unlock_wait(x) \
-        do { while (__raw_spin_is_locked(x)) cpu_relax(); } while (0)
+#define arch_spin_is_locked(x)          ((x)->lock <= 0)
+#define arch_spin_lock_flags(lock, flags) arch_spin_lock(lock)
+#define arch_spin_unlock_wait(x) \
+        do { while (arch_spin_is_locked(x)) cpu_relax(); } while (0)
 
 /*
  * Simple spin lock operations.  There are two variants, one clears IRQ's
@@ -34,14 +34,14 @@
  *
  * We make no fairness assumptions.  They have a cost.
  */
-static inline void __raw_spin_lock(raw_spinlock_t *lock)
+static inline void arch_spin_lock(arch_spinlock_t *lock)
 {
         unsigned long tmp;
         unsigned long oldval;
 
         __asm__ __volatile__ (
                 "1:                                             \n\t"
-                "movli.l        @%2, %0 ! __raw_spin_lock       \n\t"
+                "movli.l        @%2, %0 ! arch_spin_lock        \n\t"
                 "mov            %0, %1                          \n\t"
                 "mov            #0, %0                          \n\t"
                 "movco.l        %0, @%2                         \n\t"
@@ -54,12 +54,12 @@ static inline void __raw_spin_lock(raw_spinlock_t *lock)
         );
 }
 
-static inline void __raw_spin_unlock(raw_spinlock_t *lock)
+static inline void arch_spin_unlock(arch_spinlock_t *lock)
 {
         unsigned long tmp;
 
         __asm__ __volatile__ (
-                "mov            #1, %0 ! __raw_spin_unlock      \n\t"
+                "mov            #1, %0 ! arch_spin_unlock       \n\t"
                 "mov.l          %0, @%1                         \n\t"
                 : "=&z" (tmp)
                 : "r" (&lock->lock)
@@ -67,13 +67,13 @@ static inline void __raw_spin_unlock(raw_spinlock_t *lock)
         );
 }
 
-static inline int __raw_spin_trylock(raw_spinlock_t *lock)
+static inline int arch_spin_trylock(arch_spinlock_t *lock)
 {
         unsigned long tmp, oldval;
 
         __asm__ __volatile__ (
                 "1:                                             \n\t"
-                "movli.l        @%2, %0 ! __raw_spin_trylock    \n\t"
+                "movli.l        @%2, %0 ! arch_spin_trylock     \n\t"
                 "mov            %0, %1                          \n\t"
                 "mov            #0, %0                          \n\t"
                 "movco.l        %0, @%2                         \n\t"
@@ -100,21 +100,21 @@ static inline int __raw_spin_trylock(raw_spinlock_t *lock)
  * read_can_lock - would read_trylock() succeed?
  * @lock: the rwlock in question.
  */
-#define __raw_read_can_lock(x)  ((x)->lock > 0)
+#define arch_read_can_lock(x)   ((x)->lock > 0)
 
 /**
  * write_can_lock - would write_trylock() succeed?
  * @lock: the rwlock in question.
  */
-#define __raw_write_can_lock(x) ((x)->lock == RW_LOCK_BIAS)
+#define arch_write_can_lock(x)  ((x)->lock == RW_LOCK_BIAS)
 
-static inline void __raw_read_lock(raw_rwlock_t *rw)
+static inline void arch_read_lock(arch_rwlock_t *rw)
 {
         unsigned long tmp;
 
         __asm__ __volatile__ (
                 "1:                                             \n\t"
-                "movli.l        @%1, %0 ! __raw_read_lock       \n\t"
+                "movli.l        @%1, %0 ! arch_read_lock        \n\t"
                 "cmp/pl         %0                              \n\t"
                 "bf             1b                              \n\t"
                 "add            #-1, %0                         \n\t"
@@ -126,13 +126,13 @@ static inline void __raw_read_lock(raw_rwlock_t *rw)
         );
 }
 
-static inline void __raw_read_unlock(raw_rwlock_t *rw)
+static inline void arch_read_unlock(arch_rwlock_t *rw)
 {
         unsigned long tmp;
 
         __asm__ __volatile__ (
                 "1:                                             \n\t"
-                "movli.l        @%1, %0 ! __raw_read_unlock     \n\t"
+                "movli.l        @%1, %0 ! arch_read_unlock      \n\t"
                 "add            #1, %0                          \n\t"
                 "movco.l        %0, @%1                         \n\t"
                 "bf             1b                              \n\t"
@@ -142,13 +142,13 @@ static inline void __raw_read_unlock(raw_rwlock_t *rw)
         );
 }
 
-static inline void __raw_write_lock(raw_rwlock_t *rw)
+static inline void arch_write_lock(arch_rwlock_t *rw)
 {
         unsigned long tmp;
 
         __asm__ __volatile__ (
                 "1:                                             \n\t"
-                "movli.l        @%1, %0 ! __raw_write_lock      \n\t"
+                "movli.l        @%1, %0 ! arch_write_lock       \n\t"
                 "cmp/hs         %2, %0                          \n\t"
                 "bf             1b                              \n\t"
                 "sub            %2, %0                          \n\t"
@@ -160,23 +160,23 @@ static inline void __raw_write_lock(raw_rwlock_t *rw)
         );
 }
 
-static inline void __raw_write_unlock(raw_rwlock_t *rw)
+static inline void arch_write_unlock(arch_rwlock_t *rw)
 {
         __asm__ __volatile__ (
-                "mov.l          %1, @%0 ! __raw_write_unlock    \n\t"
+                "mov.l          %1, @%0 ! arch_write_unlock     \n\t"
                 :
                 : "r" (&rw->lock), "r" (RW_LOCK_BIAS)
                 : "t", "memory"
         );
 }
 
-static inline int __raw_read_trylock(raw_rwlock_t *rw)
+static inline int arch_read_trylock(arch_rwlock_t *rw)
 {
         unsigned long tmp, oldval;
 
         __asm__ __volatile__ (
                 "1:                                             \n\t"
-                "movli.l        @%2, %0 ! __raw_read_trylock    \n\t"
+                "movli.l        @%2, %0 ! arch_read_trylock     \n\t"
                 "mov            %0, %1                          \n\t"
                 "cmp/pl         %0                              \n\t"
                 "bf             2f                              \n\t"
@@ -193,13 +193,13 @@ static inline int __raw_read_trylock(raw_rwlock_t *rw)
         return (oldval > 0);
 }
 
-static inline int __raw_write_trylock(raw_rwlock_t *rw)
+static inline int arch_write_trylock(arch_rwlock_t *rw)
 {
         unsigned long tmp, oldval;
 
         __asm__ __volatile__ (
                 "1:                                             \n\t"
-                "movli.l        @%2, %0 ! __raw_write_trylock   \n\t"
+                "movli.l        @%2, %0 ! arch_write_trylock    \n\t"
                 "mov            %0, %1                          \n\t"
                 "cmp/hs         %3, %0                          \n\t"
                 "bf             2f                              \n\t"
@@ -216,11 +216,11 @@ static inline int __raw_write_trylock(raw_rwlock_t *rw)
         return (oldval > (RW_LOCK_BIAS - 1));
 }
 
-#define __raw_read_lock_flags(lock, flags) __raw_read_lock(lock)
-#define __raw_write_lock_flags(lock, flags) __raw_write_lock(lock)
+#define arch_read_lock_flags(lock, flags) arch_read_lock(lock)
+#define arch_write_lock_flags(lock, flags) arch_write_lock(lock)
 
-#define _raw_spin_relax(lock)   cpu_relax()
-#define _raw_read_relax(lock)   cpu_relax()
-#define _raw_write_relax(lock)  cpu_relax()
+#define arch_spin_relax(lock)   cpu_relax()
+#define arch_read_relax(lock)   cpu_relax()
+#define arch_write_relax(lock)  cpu_relax()
 
 #endif /* __ASM_SH_SPINLOCK_H */
diff --git a/arch/sh/include/asm/spinlock_types.h b/arch/sh/include/asm/spinlock_types.h
index b4d244e7b60c..9b7560db06ca 100644
--- a/arch/sh/include/asm/spinlock_types.h
+++ b/arch/sh/include/asm/spinlock_types.h
@@ -7,15 +7,15 @@
 
 typedef struct {
         volatile unsigned int lock;
-} raw_spinlock_t;
+} arch_spinlock_t;
 
-#define __RAW_SPIN_LOCK_UNLOCKED                { 1 }
+#define __ARCH_SPIN_LOCK_UNLOCKED               { 1 }
 
 typedef struct {
         volatile unsigned int lock;
-} raw_rwlock_t;
+} arch_rwlock_t;
 
 #define RW_LOCK_BIAS                    0x01000000
-#define __RAW_RW_LOCK_UNLOCKED          { RW_LOCK_BIAS }
+#define __ARCH_RW_LOCK_UNLOCKED         { RW_LOCK_BIAS }
 
 #endif
diff --git a/arch/sh/include/asm/unistd_32.h b/arch/sh/include/asm/unistd_32.h
index f3fd1b9eb6b1..f18c4f9baf27 100644
--- a/arch/sh/include/asm/unistd_32.h
+++ b/arch/sh/include/asm/unistd_32.h
@@ -345,8 +345,9 @@
 #define __NR_pwritev            334
 #define __NR_rt_tgsigqueueinfo  335
 #define __NR_perf_event_open    336
+#define __NR_recvmmsg           337
 
-#define NR_syscalls 337
+#define NR_syscalls 338
 
 #ifdef __KERNEL__
 
diff --git a/arch/sh/include/asm/unistd_64.h b/arch/sh/include/asm/unistd_64.h
index 343ce8f073ea..3e7645d11130 100644
--- a/arch/sh/include/asm/unistd_64.h
+++ b/arch/sh/include/asm/unistd_64.h
@@ -385,10 +385,11 @@
 #define __NR_pwritev            362
 #define __NR_rt_tgsigqueueinfo  363
 #define __NR_perf_event_open    364
+#define __NR_recvmmsg           365
 
 #ifdef __KERNEL__
 
-#define NR_syscalls 365
+#define NR_syscalls 366
 
 #define __ARCH_WANT_IPC_PARSE_VERSION
 #define __ARCH_WANT_OLD_READDIR
diff --git a/arch/sh/include/mach-kfr2r09/mach/kfr2r09.h b/arch/sh/include/mach-kfr2r09/mach/kfr2r09.h
index 174374e19547..484ef42c2fb5 100644
--- a/arch/sh/include/mach-kfr2r09/mach/kfr2r09.h
+++ b/arch/sh/include/mach-kfr2r09/mach/kfr2r09.h
@@ -8,6 +8,8 @@ void kfr2r09_lcd_on(void *board_data);
 void kfr2r09_lcd_off(void *board_data);
 int kfr2r09_lcd_setup(void *board_data, void *sys_ops_handle,
                       struct sh_mobile_lcdc_sys_bus_ops *sys_ops);
+void kfr2r09_lcd_start(void *board_data, void *sys_ops_handle,
+                       struct sh_mobile_lcdc_sys_bus_ops *sys_ops);
 #else
 static inline void kfr2r09_lcd_on(void *board_data) {}
 static inline void kfr2r09_lcd_off(void *board_data) {}
@@ -16,6 +18,10 @@ static inline int kfr2r09_lcd_setup(void *board_data, void *sys_ops_handle,
 {
         return -ENODEV;
 }
+static inline void kfr2r09_lcd_start(void *board_data, void *sys_ops_handle,
+                                     struct sh_mobile_lcdc_sys_bus_ops *sys_ops)
+{
+}
 #endif
 
 #endif /* __ASM_SH_KFR2R09_H */
diff --git a/arch/sh/kernel/Makefile b/arch/sh/kernel/Makefile
index 0471a3eb25ed..0d587da1ef12 100644
--- a/arch/sh/kernel/Makefile
+++ b/arch/sh/kernel/Makefile
@@ -22,11 +22,10 @@ obj-y	:= debugtraps.o dma-nommu.o dumpstack.o 			\
 obj-y                           += cpu/
 obj-$(CONFIG_VSYSCALL)          += vsyscall/
 obj-$(CONFIG_SMP)               += smp.o
-obj-$(CONFIG_SH_STANDARD_BIOS)  += sh_bios.o
+obj-$(CONFIG_SH_STANDARD_BIOS)  += sh_bios.o early_printk.o
 obj-$(CONFIG_KGDB)              += kgdb.o
 obj-$(CONFIG_SH_CPU_FREQ)       += cpufreq.o
 obj-$(CONFIG_MODULES)           += sh_ksyms_$(BITS).o module.o
-obj-$(CONFIG_EARLY_PRINTK)      += early_printk.o
 obj-$(CONFIG_KEXEC)             += machine_kexec.o relocate_kernel.o
 obj-$(CONFIG_CRASH_DUMP)        += crash_dump.o
 obj-$(CONFIG_STACKTRACE)        += stacktrace.o
diff --git a/arch/sh/kernel/cpu/irq/ipr.c b/arch/sh/kernel/cpu/irq/ipr.c
index c1508a90fc6a..9282d965a1b6 100644
--- a/arch/sh/kernel/cpu/irq/ipr.c
+++ b/arch/sh/kernel/cpu/irq/ipr.c
@@ -17,16 +17,17 @@
  * for more details.
  */
 #include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
 #include <linux/irq.h>
+#include <linux/kernel.h>
 #include <linux/module.h>
-#include <linux/io.h>
-#include <linux/interrupt.h>
 #include <linux/topology.h>
 
 static inline struct ipr_desc *get_ipr_desc(unsigned int irq)
 {
         struct irq_chip *chip = get_irq_chip(irq);
-        return (void *)((char *)chip - offsetof(struct ipr_desc, chip));
+        return container_of(chip, struct ipr_desc, chip);
 }
 
 static void disable_ipr_irq(unsigned int irq)
diff --git a/arch/sh/kernel/cpu/sh2/setup-sh7619.c b/arch/sh/kernel/cpu/sh2/setup-sh7619.c
index 8555c05e8667..114c7cee7184 100644
--- a/arch/sh/kernel/cpu/sh2/setup-sh7619.c
+++ b/arch/sh/kernel/cpu/sh2/setup-sh7619.c
@@ -59,32 +59,48 @@ static struct intc_prio_reg prio_registers[] __initdata = {
 static DECLARE_INTC_DESC(intc_desc, "sh7619", vectors, NULL,
                          NULL, prio_registers, NULL);
 
-static struct plat_sci_port sci_platform_data[] = {
-        {
-                .mapbase        = 0xf8400000,
-                .flags          = UPF_BOOT_AUTOCONF,
-                .type           = PORT_SCIF,
-                .irqs           = { 88, 88, 88, 88 },
-        }, {
-                .mapbase        = 0xf8410000,
-                .flags          = UPF_BOOT_AUTOCONF,
-                .type           = PORT_SCIF,
-                .irqs           = { 92, 92, 92, 92 },
-        }, {
-                .mapbase        = 0xf8420000,
-                .flags          = UPF_BOOT_AUTOCONF,
-                .type           = PORT_SCIF,
-                .irqs           = { 96, 96, 96, 96 },
-        }, {
-                .flags = 0,
-        }
-};
-
-static struct platform_device sci_device = {
+static struct plat_sci_port scif0_platform_data = {
+        .mapbase        = 0xf8400000,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .type           = PORT_SCIF,
+        .irqs           = { 88, 88, 88, 88 },
+};
+
+static struct platform_device scif0_device = {
+        .name           = "sh-sci",
+        .id             = 0,
+        .dev            = {
+                .platform_data  = &scif0_platform_data,
+        },
+};
+
+static struct plat_sci_port scif1_platform_data = {
+        .mapbase        = 0xf8410000,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .type           = PORT_SCIF,
+        .irqs           = { 92, 92, 92, 92 },
+};
+
+static struct platform_device scif1_device = {
+        .name           = "sh-sci",
+        .id             = 1,
+        .dev            = {
+                .platform_data  = &scif1_platform_data,
+        },
+};
+
+static struct plat_sci_port scif2_platform_data = {
+        .mapbase        = 0xf8420000,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .type           = PORT_SCIF,
+        .irqs           = { 96, 96, 96, 96 },
+};
+
+static struct platform_device scif2_device = {
         .name           = "sh-sci",
-        .id             = -1,
+        .id             = 2,
         .dev            = {
-                .platform_data  = sci_platform_data,
+                .platform_data  = &scif2_platform_data,
         },
 };
 
@@ -176,7 +192,9 @@ static struct platform_device cmt1_device = {
 };
 
 static struct platform_device *sh7619_devices[] __initdata = {
-        &sci_device,
+        &scif0_device,
+        &scif1_device,
+        &scif2_device,
         &eth_device,
         &cmt0_device,
         &cmt1_device,
@@ -195,6 +213,9 @@ void __init plat_irq_setup(void)
 }
 
 static struct platform_device *sh7619_early_devices[] __initdata = {
+        &scif0_device,
+        &scif1_device,
+        &scif2_device,
         &cmt0_device,
         &cmt1_device,
 };
diff --git a/arch/sh/kernel/cpu/sh2a/setup-mxg.c b/arch/sh/kernel/cpu/sh2a/setup-mxg.c
index b67376445315..8f669dc9b0da 100644
--- a/arch/sh/kernel/cpu/sh2a/setup-mxg.c
+++ b/arch/sh/kernel/cpu/sh2a/setup-mxg.c
@@ -207,27 +207,23 @@ static struct platform_device mtu2_2_device = {
         .num_resources  = ARRAY_SIZE(mtu2_2_resources),
 };
 
-static struct plat_sci_port sci_platform_data[] = {
-        {
-                .mapbase        = 0xff804000,
-                .flags          = UPF_BOOT_AUTOCONF,
-                .type           = PORT_SCIF,
-                .irqs           = { 220, 220, 220, 220 },
-        }, {
-                .flags = 0,
-        }
+static struct plat_sci_port scif0_platform_data = {
+        .mapbase        = 0xff804000,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .type           = PORT_SCIF,
+        .irqs           = { 220, 220, 220, 220 },
 };
 
-static struct platform_device sci_device = {
+static struct platform_device scif0_device = {
         .name           = "sh-sci",
-        .id             = -1,
+        .id             = 0,
         .dev            = {
-                .platform_data  = sci_platform_data,
+                .platform_data  = &scif0_platform_data,
         },
 };
 
 static struct platform_device *mxg_devices[] __initdata = {
-        &sci_device,
+        &scif0_device,
         &mtu2_0_device,
         &mtu2_1_device,
         &mtu2_2_device,
@@ -246,6 +242,7 @@ void __init plat_irq_setup(void)
 }
 
 static struct platform_device *mxg_early_devices[] __initdata = {
+        &scif0_device,
         &mtu2_0_device,
         &mtu2_1_device,
         &mtu2_2_device,
diff --git a/arch/sh/kernel/cpu/sh2a/setup-sh7201.c b/arch/sh/kernel/cpu/sh2a/setup-sh7201.c
index fbde5b75deb9..4ccfeb59eb1a 100644
--- a/arch/sh/kernel/cpu/sh2a/setup-sh7201.c
+++ b/arch/sh/kernel/cpu/sh2a/setup-sh7201.c
@@ -177,57 +177,123 @@ static struct intc_mask_reg mask_registers[] __initdata = {
 static DECLARE_INTC_DESC(intc_desc, "sh7201", vectors, groups,
                          mask_registers, prio_registers, NULL);
 
-static struct plat_sci_port sci_platform_data[] = {
-        {
-                .mapbase        = 0xfffe8000,
-                .flags          = UPF_BOOT_AUTOCONF,
-                .type           = PORT_SCIF,
-                .irqs           = { 180, 180, 180, 180 }
-        }, {
-                .mapbase        = 0xfffe8800,
-                .flags          = UPF_BOOT_AUTOCONF,
-                .type           = PORT_SCIF,
-                .irqs           = { 184, 184, 184, 184 }
-        }, {
-                .mapbase        = 0xfffe9000,
-                .flags          = UPF_BOOT_AUTOCONF,
-                .type           = PORT_SCIF,
-                .irqs           = { 188, 188, 188, 188 }
-        }, {
-                .mapbase        = 0xfffe9800,
-                .flags          = UPF_BOOT_AUTOCONF,
-                .type           = PORT_SCIF,
-                .irqs           = { 192, 192, 192, 192 }
-        }, {
-                .mapbase        = 0xfffea000,
-                .flags          = UPF_BOOT_AUTOCONF,
-                .type           = PORT_SCIF,
-                .irqs           = { 196, 196, 196, 196 }
-        }, {
-                .mapbase        = 0xfffea800,
-                .flags          = UPF_BOOT_AUTOCONF,
-                .type           = PORT_SCIF,
-                .irqs           = { 200, 200, 200, 200 }
-        }, {
-                .mapbase        = 0xfffeb000,
-                .flags          = UPF_BOOT_AUTOCONF,
-                .type           = PORT_SCIF,
-                .irqs           = { 204, 204, 204, 204 }
-        }, {
-                .mapbase        = 0xfffeb800,
-                .flags          = UPF_BOOT_AUTOCONF,
-                .type           = PORT_SCIF,
-                .irqs           = { 208, 208, 208, 208 }
-        }, {
-                .flags = 0,
-        }
-};
-
-static struct platform_device sci_device = {
+static struct plat_sci_port scif0_platform_data = {
+        .mapbase        = 0xfffe8000,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .type           = PORT_SCIF,
+        .irqs           = { 180, 180, 180, 180 }
+};
+
+static struct platform_device scif0_device = {
         .name           = "sh-sci",
-        .id             = -1,
+        .id             = 0,
+        .dev            = {
+                .platform_data  = &scif0_platform_data,
+        },
+};
+
+static struct plat_sci_port scif1_platform_data = {
+        .mapbase        = 0xfffe8800,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .type           = PORT_SCIF,
+        .irqs           = { 184, 184, 184, 184 }
+};
+
+static struct platform_device scif1_device = {
+        .name           = "sh-sci",
+        .id             = 1,
+        .dev            = {
+                .platform_data  = &scif1_platform_data,
+        },
+};
+
+static struct plat_sci_port scif2_platform_data = {
+        .mapbase        = 0xfffe9000,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .type           = PORT_SCIF,
+        .irqs           = { 188, 188, 188, 188 }
+};
+
+static struct platform_device scif2_device = {
+        .name           = "sh-sci",
+        .id             = 2,
+        .dev            = {
+                .platform_data  = &scif2_platform_data,
+        },
+};
+
+static struct plat_sci_port scif3_platform_data = {
+        .mapbase        = 0xfffe9800,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .type           = PORT_SCIF,
+        .irqs           = { 192, 192, 192, 192 }
+};
+
+static struct platform_device scif3_device = {
+        .name           = "sh-sci",
+        .id             = 3,
+        .dev            = {
+                .platform_data  = &scif3_platform_data,
+        },
+};
+
+static struct plat_sci_port scif4_platform_data = {
+        .mapbase        = 0xfffea000,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .type           = PORT_SCIF,
+        .irqs           = { 196, 196, 196, 196 }
+};
+
+static struct platform_device scif4_device = {
+        .name           = "sh-sci",
+        .id             = 4,
+        .dev            = {
+                .platform_data  = &scif4_platform_data,
+        },
+};
+
+static struct plat_sci_port scif5_platform_data = {
+        .mapbase        = 0xfffea800,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .type           = PORT_SCIF,
+        .irqs           = { 200, 200, 200, 200 }
+};
+
+static struct platform_device scif5_device = {
+        .name           = "sh-sci",
+        .id             = 5,
+        .dev            = {
+                .platform_data  = &scif5_platform_data,
+        },
+};
+
+static struct plat_sci_port scif6_platform_data = {
+        .mapbase        = 0xfffeb000,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .type           = PORT_SCIF,
+        .irqs           = { 204, 204, 204, 204 }
+};
+
+static struct platform_device scif6_device = {
+        .name           = "sh-sci",
+        .id             = 6,
+        .dev            = {
+                .platform_data  = &scif6_platform_data,
+        },
+};
+
+static struct plat_sci_port scif7_platform_data = {
+        .mapbase        = 0xfffeb800,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .type           = PORT_SCIF,
+        .irqs           = { 208, 208, 208, 208 }
+};
+
+static struct platform_device scif7_device = {
+        .name           = "sh-sci",
+        .id             = 7,
         .dev            = {
-                .platform_data  = sci_platform_data,
+                .platform_data  = &scif7_platform_data,
         },
 };
 
@@ -345,7 +411,14 @@ static struct platform_device mtu2_2_device = {
 };
 
 static struct platform_device *sh7201_devices[] __initdata = {
-        &sci_device,
+        &scif0_device,
+        &scif1_device,
+        &scif2_device,
+        &scif3_device,
+        &scif4_device,
+        &scif5_device,
+        &scif6_device,
+        &scif7_device,
         &rtc_device,
         &mtu2_0_device,
         &mtu2_1_device,
@@ -365,6 +438,14 @@ void __init plat_irq_setup(void)
 }
 
 static struct platform_device *sh7201_early_devices[] __initdata = {
+        &scif0_device,
+        &scif1_device,
+        &scif2_device,
+        &scif3_device,
+        &scif4_device,
+        &scif5_device,
+        &scif6_device,
+        &scif7_device,
         &mtu2_0_device,
         &mtu2_1_device,
         &mtu2_2_device,
diff --git a/arch/sh/kernel/cpu/sh2a/setup-sh7203.c b/arch/sh/kernel/cpu/sh2a/setup-sh7203.c
index d3fd536c9a84..3136966cc9b3 100644
--- a/arch/sh/kernel/cpu/sh2a/setup-sh7203.c
+++ b/arch/sh/kernel/cpu/sh2a/setup-sh7203.c
@@ -173,37 +173,63 @@ static struct intc_mask_reg mask_registers[] __initdata = {
 static DECLARE_INTC_DESC(intc_desc, "sh7203", vectors, groups,
                          mask_registers, prio_registers, NULL);
 
-static struct plat_sci_port sci_platform_data[] = {
-        {
-                .mapbase        = 0xfffe8000,
-                .flags          = UPF_BOOT_AUTOCONF,
-                .type           = PORT_SCIF,
-                .irqs           =  { 192, 192, 192, 192 },
-        }, {
-                .mapbase        = 0xfffe8800,
-                .flags          = UPF_BOOT_AUTOCONF,
-                .type           = PORT_SCIF,
-                .irqs           =  { 196, 196, 196, 196 },
-        }, {
-                .mapbase        = 0xfffe9000,
-                .flags          = UPF_BOOT_AUTOCONF,
-                .type           = PORT_SCIF,
-                .irqs           =  { 200, 200, 200, 200 },
-        }, {
-                .mapbase        = 0xfffe9800,
-                .flags          = UPF_BOOT_AUTOCONF,
-                .type           = PORT_SCIF,
-                .irqs           =  { 204, 204, 204, 204 },
-        }, {
-                .flags = 0,
-        }
+static struct plat_sci_port scif0_platform_data = {
+        .mapbase        = 0xfffe8000,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .type           = PORT_SCIF,
+        .irqs           =  { 192, 192, 192, 192 },
 };
 
-static struct platform_device sci_device = {
+static struct platform_device scif0_device = {
         .name           = "sh-sci",
-        .id             = -1,
+        .id             = 0,
+        .dev            = {
+                .platform_data  = &scif0_platform_data,
+        },
+};
+
+static struct plat_sci_port scif1_platform_data = {
+        .mapbase        = 0xfffe8800,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .type           = PORT_SCIF,
+        .irqs           =  { 196, 196, 196, 196 },
+};
+
+static struct platform_device scif1_device = {
+        .name           = "sh-sci",
+        .id             = 1,
+        .dev            = {
+                .platform_data  = &scif1_platform_data,
+        },
+};
+
+static struct plat_sci_port scif2_platform_data = {
+        .mapbase        = 0xfffe9000,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .type           = PORT_SCIF,
+        .irqs           =  { 200, 200, 200, 200 },
+};
+
+static struct platform_device scif2_device = {
+        .name           = "sh-sci",
+        .id             = 2,
+        .dev            = {
+                .platform_data  = &scif2_platform_data,
+        },
+};
+
+static struct plat_sci_port scif3_platform_data = {
+        .mapbase        = 0xfffe9800,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .type           = PORT_SCIF,
+        .irqs           =  { 204, 204, 204, 204 },
+};
+
+static struct platform_device scif3_device = {
+        .name           = "sh-sci",
+        .id             = 3,
         .dev            = {
-                .platform_data  = sci_platform_data,
+                .platform_data  = &scif3_platform_data,
         },
 };
 
@@ -354,7 +380,10 @@ static struct platform_device rtc_device = {
 };
 
 static struct platform_device *sh7203_devices[] __initdata = {
-        &sci_device,
+        &scif0_device,
+        &scif1_device,
+        &scif2_device,
+        &scif3_device,
         &cmt0_device,
         &cmt1_device,
         &mtu2_0_device,
@@ -375,6 +404,10 @@ void __init plat_irq_setup(void)
 }
 
 static struct platform_device *sh7203_early_devices[] __initdata = {
+        &scif0_device,
+        &scif1_device,
+        &scif2_device,
+        &scif3_device,
         &cmt0_device,
         &cmt1_device,
         &mtu2_0_device,
diff --git a/arch/sh/kernel/cpu/sh2a/setup-sh7206.c b/arch/sh/kernel/cpu/sh2a/setup-sh7206.c
index a9ccc5e8d9e9..064873585a8b 100644
--- a/arch/sh/kernel/cpu/sh2a/setup-sh7206.c
+++ b/arch/sh/kernel/cpu/sh2a/setup-sh7206.c
@@ -133,37 +133,63 @@ static struct intc_mask_reg mask_registers[] __initdata = {
 static DECLARE_INTC_DESC(intc_desc, "sh7206", vectors, groups,
                          mask_registers, prio_registers, NULL);
 
-static struct plat_sci_port sci_platform_data[] = {
-        {
-                .mapbase        = 0xfffe8000,
-                .flags          = UPF_BOOT_AUTOCONF,
-                .type           = PORT_SCIF,
-                .irqs           = { 240, 240, 240, 240 },
-        }, {
-                .mapbase        = 0xfffe8800,
-                .flags          = UPF_BOOT_AUTOCONF,
-                .type           = PORT_SCIF,
-                .irqs           = { 244, 244, 244, 244 },
-        }, {
-                .mapbase        = 0xfffe9000,
-                .flags          = UPF_BOOT_AUTOCONF,
-                .type           = PORT_SCIF,
-                .irqs           = { 248, 248, 248, 248 },
-        }, {
-                .mapbase        = 0xfffe9800,
-                .flags          = UPF_BOOT_AUTOCONF,
-                .type           = PORT_SCIF,
-                .irqs           = { 252, 252, 252, 252 },
-        }, {
-                .flags = 0,
-        }
+static struct plat_sci_port scif0_platform_data = {
+        .mapbase        = 0xfffe8000,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .type           = PORT_SCIF,
+        .irqs           = { 240, 240, 240, 240 },
 };
 
-static struct platform_device sci_device = {
+static struct platform_device scif0_device = {
         .name           = "sh-sci",
-        .id             = -1,
+        .id             = 0,
+        .dev            = {
+                .platform_data  = &scif0_platform_data,
+        },
+};
+
+static struct plat_sci_port scif1_platform_data = {
+        .mapbase        = 0xfffe8800,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .type           = PORT_SCIF,
+        .irqs           = { 244, 244, 244, 244 },
+};
+
+static struct platform_device scif1_device = {
+        .name           = "sh-sci",
+        .id             = 1,
+        .dev            = {
+                .platform_data  = &scif1_platform_data,
+        },
+};
+
+static struct plat_sci_port scif2_platform_data = {
+        .mapbase        = 0xfffe9000,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .type           = PORT_SCIF,
+        .irqs           = { 248, 248, 248, 248 },
+};
+
+static struct platform_device scif2_device = {
+        .name           = "sh-sci",
+        .id             = 2,
+        .dev            = {
+                .platform_data  = &scif2_platform_data,
+        },
+};
+
+static struct plat_sci_port scif3_platform_data = {
+        .mapbase        = 0xfffe9800,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .type           = PORT_SCIF,
+        .irqs           = { 252, 252, 252, 252 },
+};
+
+static struct platform_device scif3_device = {
+        .name           = "sh-sci",
+        .id             = 3,
         .dev            = {
-                .platform_data  = sci_platform_data,
+                .platform_data  = &scif3_platform_data,
         },
 };
 
@@ -325,7 +351,10 @@ static struct platform_device mtu2_2_device = {
 };
 
 static struct platform_device *sh7206_devices[] __initdata = {
-        &sci_device,
+        &scif0_device,
+        &scif1_device,
+        &scif2_device,
+        &scif3_device,
         &cmt0_device,
         &cmt1_device,
         &mtu2_0_device,
@@ -346,6 +375,10 @@ void __init plat_irq_setup(void)
 }
 
 static struct platform_device *sh7206_early_devices[] __initdata = {
+        &scif0_device,
+        &scif1_device,
+        &scif2_device,
+        &scif3_device,
         &cmt0_device,
         &cmt1_device,
         &mtu2_0_device,
diff --git a/arch/sh/kernel/cpu/sh3/setup-sh7705.c b/arch/sh/kernel/cpu/sh3/setup-sh7705.c
index c23105983878..7b892d60e3a0 100644
--- a/arch/sh/kernel/cpu/sh3/setup-sh7705.c
+++ b/arch/sh/kernel/cpu/sh3/setup-sh7705.c
@@ -67,27 +67,33 @@ static struct intc_prio_reg prio_registers[] __initdata = {
 static DECLARE_INTC_DESC(intc_desc, "sh7705", vectors, NULL,
                          NULL, prio_registers, NULL);
 
-static struct plat_sci_port sci_platform_data[] = {
-        {
-                .mapbase        = 0xa4410000,
-                .flags          = UPF_BOOT_AUTOCONF,
-                .type           = PORT_SCIF,
-                .irqs           = { 56, 56, 56 },
-        }, {
-                .mapbase        = 0xa4400000,
-                .flags          = UPF_BOOT_AUTOCONF,
-                .type           = PORT_SCIF,
-                .irqs           = { 52, 52, 52 },
-        }, {
-                .flags = 0,
-        }
-};
-
-static struct platform_device sci_device = {
+static struct plat_sci_port scif0_platform_data = {
+        .mapbase        = 0xa4410000,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .type           = PORT_SCIF,
+        .irqs           = { 56, 56, 56 },
+};
+
+static struct platform_device scif0_device = {
         .name           = "sh-sci",
-        .id             = -1,
+        .id             = 0,
+        .dev            = {
+                .platform_data  = &scif0_platform_data,
+        },
+};
+
+static struct plat_sci_port scif1_platform_data = {
+        .mapbase        = 0xa4400000,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .type           = PORT_SCIF,
+        .irqs           = { 52, 52, 52 },
+};
+
+static struct platform_device scif1_device = {
+        .name           = "sh-sci",
+        .id             = 1,
         .dev            = {
-                .platform_data  = sci_platform_data,
+                .platform_data  = &scif1_platform_data,
         },
 };
 
@@ -210,10 +216,11 @@ static struct platform_device tmu2_device = {
 };
 
 static struct platform_device *sh7705_devices[] __initdata = {
+        &scif0_device,
+        &scif1_device,
         &tmu0_device,
         &tmu1_device,
         &tmu2_device,
-        &sci_device,
         &rtc_device,
 };
 
@@ -225,6 +232,8 @@ static int __init sh7705_devices_setup(void)
 arch_initcall(sh7705_devices_setup);
 
 static struct platform_device *sh7705_early_devices[] __initdata = {
+        &scif0_device,
+        &scif1_device,
         &tmu0_device,
         &tmu1_device,
         &tmu2_device,
diff --git a/arch/sh/kernel/cpu/sh3/setup-sh770x.c b/arch/sh/kernel/cpu/sh3/setup-sh770x.c
index 347ab35d0697..bc0c4f68c7c7 100644
--- a/arch/sh/kernel/cpu/sh3/setup-sh770x.c
+++ b/arch/sh/kernel/cpu/sh3/setup-sh770x.c
@@ -106,44 +106,55 @@ static struct platform_device rtc_device = {
         .resource       = rtc_resources,
 };
 
-static struct plat_sci_port sci_platform_data[] = {
-        {
-                .mapbase        = 0xfffffe80,
-                .flags          = UPF_BOOT_AUTOCONF,
-                .type           = PORT_SCI,
-                .irqs           = { 23, 23, 23, 0 },
+static struct plat_sci_port scif0_platform_data = {
+        .mapbase        = 0xfffffe80,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .type           = PORT_SCI,
+        .irqs           = { 23, 23, 23, 0 },
+};
+
+static struct platform_device scif0_device = {
+        .name           = "sh-sci",
+        .id             = 0,
+        .dev            = {
+                .platform_data  = &scif0_platform_data,
         },
+};
 #if defined(CONFIG_CPU_SUBTYPE_SH7706) || \
     defined(CONFIG_CPU_SUBTYPE_SH7707) || \
     defined(CONFIG_CPU_SUBTYPE_SH7709)
-        {
-                .mapbase        = 0xa4000150,
-                .flags          = UPF_BOOT_AUTOCONF,
-                .type           = PORT_SCIF,
-                .irqs           = { 56, 56, 56, 56 },
+static struct plat_sci_port scif1_platform_data = {
+        .mapbase        = 0xa4000150,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .type           = PORT_SCIF,
+        .irqs           = { 56, 56, 56, 56 },
+};
+
+static struct platform_device scif1_device = {
+        .name           = "sh-sci",
+        .id             = 1,
+        .dev            = {
+                .platform_data  = &scif1_platform_data,
         },
+};
 #endif
 #if defined(CONFIG_CPU_SUBTYPE_SH7707) || \
     defined(CONFIG_CPU_SUBTYPE_SH7709)
-        {
-                .mapbase        = 0xa4000140,
-                .flags          = UPF_BOOT_AUTOCONF,
-                .type           = PORT_IRDA,
-                .irqs           = { 52, 52, 52, 52 },
-        },
-#endif
-        {
-                .flags = 0,
-        }
+static struct plat_sci_port scif2_platform_data = {
+        .mapbase        = 0xa4000140,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .type           = PORT_IRDA,
+        .irqs           = { 52, 52, 52, 52 },
 };
 
-static struct platform_device sci_device = {
+static struct platform_device scif2_device = {
         .name           = "sh-sci",
-        .id             = -1,
+        .id             = 2,
         .dev            = {
-                .platform_data  = sci_platform_data,
+                .platform_data  = &scif2_platform_data,
         },
 };
+#endif
 
 static struct sh_timer_config tmu0_platform_data = {
         .name = "TMU0",
@@ -238,10 +249,19 @@ static struct platform_device tmu2_device = {
 };
 
 static struct platform_device *sh770x_devices[] __initdata = {
+        &scif0_device,
+#if defined(CONFIG_CPU_SUBTYPE_SH7706) || \
+    defined(CONFIG_CPU_SUBTYPE_SH7707) || \
+    defined(CONFIG_CPU_SUBTYPE_SH7709)
+        &scif1_device,
+#endif
+#if defined(CONFIG_CPU_SUBTYPE_SH7707) || \
+    defined(CONFIG_CPU_SUBTYPE_SH7709)
+        &scif2_device,
+#endif
         &tmu0_device,
         &tmu1_device,
         &tmu2_device,
-        &sci_device,
         &rtc_device,
 };
 
@@ -253,6 +273,16 @@ static int __init sh770x_devices_setup(void)
 arch_initcall(sh770x_devices_setup);
 
 static struct platform_device *sh770x_early_devices[] __initdata = {
+        &scif0_device,
+#if defined(CONFIG_CPU_SUBTYPE_SH7706) || \
+    defined(CONFIG_CPU_SUBTYPE_SH7707) || \
+    defined(CONFIG_CPU_SUBTYPE_SH7709)
+        &scif1_device,
+#endif
+#if defined(CONFIG_CPU_SUBTYPE_SH7707) || \
+    defined(CONFIG_CPU_SUBTYPE_SH7709)
+        &scif2_device,
+#endif
         &tmu0_device,
         &tmu1_device,
         &tmu2_device,
diff --git a/arch/sh/kernel/cpu/sh3/setup-sh7710.c b/arch/sh/kernel/cpu/sh3/setup-sh7710.c
index 717e90ae1097..0845a3ad006d 100644
--- a/arch/sh/kernel/cpu/sh3/setup-sh7710.c
+++ b/arch/sh/kernel/cpu/sh3/setup-sh7710.c
@@ -96,28 +96,33 @@ static struct platform_device rtc_device = {
         },
 };
 
-static struct plat_sci_port sci_platform_data[] = {
-        {
-                .mapbase        = 0xa4400000,
-                .flags          = UPF_BOOT_AUTOCONF,
-                .type           = PORT_SCIF,
-                .irqs           = { 52, 52, 52, 52 },
-        }, {
-                .mapbase        = 0xa4410000,
-                .flags          = UPF_BOOT_AUTOCONF,
-                .type           = PORT_SCIF,
-                .irqs           = { 56, 56, 56, 56 },
-        }, {
-
-                .flags = 0,
-        }
-};
-
-static struct platform_device sci_device = {
+static struct plat_sci_port scif0_platform_data = {
+        .mapbase        = 0xa4400000,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .type           = PORT_SCIF,
+        .irqs           = { 52, 52, 52, 52 },
+};
+
+static struct platform_device scif0_device = {
         .name           = "sh-sci",
-        .id             = -1,
+        .id             = 0,
+        .dev            = {
+                .platform_data  = &scif0_platform_data,
+        },
+};
+
+static struct plat_sci_port scif1_platform_data = {
+        .mapbase        = 0xa4410000,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .type           = PORT_SCIF,
+        .irqs           = { 56, 56, 56, 56 },
+};
+
+static struct platform_device scif1_device = {
+        .name           = "sh-sci",
+        .id             = 1,
         .dev            = {
-                .platform_data  = sci_platform_data,
+                .platform_data  = &scif1_platform_data,
         },
 };
 
@@ -214,10 +219,11 @@ static struct platform_device tmu2_device = {
 };
 
 static struct platform_device *sh7710_devices[] __initdata = {
+        &scif0_device,
+        &scif1_device,
         &tmu0_device,
         &tmu1_device,
         &tmu2_device,
-        &sci_device,
         &rtc_device,
 };
 
@@ -229,6 +235,8 @@ static int __init sh7710_devices_setup(void)
 arch_initcall(sh7710_devices_setup);
 
 static struct platform_device *sh7710_early_devices[] __initdata = {
+        &scif0_device,
+        &scif1_device,
         &tmu0_device,
         &tmu1_device,
         &tmu2_device,
diff --git a/arch/sh/kernel/cpu/sh3/setup-sh7720.c b/arch/sh/kernel/cpu/sh3/setup-sh7720.c
index 74d8baaf8e96..a718a6231091 100644
--- a/arch/sh/kernel/cpu/sh3/setup-sh7720.c
+++ b/arch/sh/kernel/cpu/sh3/setup-sh7720.c
@@ -48,28 +48,33 @@ static struct platform_device rtc_device = {
         },
 };
 
-static struct plat_sci_port sci_platform_data[] = {
-        {
-                .mapbase        = 0xa4430000,
-                .flags          = UPF_BOOT_AUTOCONF,
-                .type           = PORT_SCIF,
-                .irqs           = { 80, 80, 80, 80 },
-        }, {
-                .mapbase        = 0xa4438000,
-                .flags          = UPF_BOOT_AUTOCONF,
-                .type           = PORT_SCIF,
-                .irqs           = { 81, 81, 81, 81 },
-        }, {
-
-                .flags = 0,
-        }
-};
-
-static struct platform_device sci_device = {
+static struct plat_sci_port scif0_platform_data = {
+        .mapbase        = 0xa4430000,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .type           = PORT_SCIF,
+        .irqs           = { 80, 80, 80, 80 },
+};
+
+static struct platform_device scif0_device = {
         .name           = "sh-sci",
-        .id             = -1,
+        .id             = 0,
+        .dev            = {
+                .platform_data  = &scif0_platform_data,
+        },
+};
+
+static struct plat_sci_port scif1_platform_data = {
+        .mapbase        = 0xa4438000,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .type           = PORT_SCIF,
+        .irqs           = { 81, 81, 81, 81 },
+};
+
+static struct platform_device scif1_device = {
+        .name           = "sh-sci",
+        .id             = 1,
         .dev            = {
-                .platform_data  = sci_platform_data,
+                .platform_data  = &scif1_platform_data,
         },
 };
 
@@ -369,6 +374,8 @@ static struct platform_device tmu2_device = {
 };
 
 static struct platform_device *sh7720_devices[] __initdata = {
+        &scif0_device,
+        &scif1_device,
         &cmt0_device,
         &cmt1_device,
         &cmt2_device,
@@ -378,7 +385,6 @@ static struct platform_device *sh7720_devices[] __initdata = {
         &tmu1_device,
         &tmu2_device,
         &rtc_device,
-        &sci_device,
         &usb_ohci_device,
         &usbf_device,
 };
@@ -391,6 +397,8 @@ static int __init sh7720_devices_setup(void)
 arch_initcall(sh7720_devices_setup);
 
 static struct platform_device *sh7720_early_devices[] __initdata = {
+        &scif0_device,
+        &scif1_device,
         &cmt0_device,
         &cmt1_device,
         &cmt2_device,
diff --git a/arch/sh/kernel/cpu/sh4/setup-sh4-202.c b/arch/sh/kernel/cpu/sh4/setup-sh4-202.c
index de4827df19aa..4b733715cdb5 100644
--- a/arch/sh/kernel/cpu/sh4/setup-sh4-202.c
+++ b/arch/sh/kernel/cpu/sh4/setup-sh4-202.c
@@ -15,22 +15,18 @@
 #include <linux/sh_timer.h>
 #include <linux/io.h>
 
-static struct plat_sci_port sci_platform_data[] = {
-        {
-                .mapbase        = 0xffe80000,
-                .flags          = UPF_BOOT_AUTOCONF,
-                .type           = PORT_SCIF,
-                .irqs           = { 40, 41, 43, 42 },
-        }, {
-                .flags = 0,
-        }
+static struct plat_sci_port scif0_platform_data = {
+        .mapbase        = 0xffe80000,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .type           = PORT_SCIF,
+        .irqs           = { 40, 41, 43, 42 },
 };
 
-static struct platform_device sci_device = {
+static struct platform_device scif0_device = {
         .name           = "sh-sci",
-        .id             = -1,
+        .id             = 0,
         .dev            = {
-                .platform_data  = sci_platform_data,
+                .platform_data  = &scif0_platform_data,
         },
 };
 
@@ -127,7 +123,7 @@ static struct platform_device tmu2_device = {
 };
 
 static struct platform_device *sh4202_devices[] __initdata = {
-        &sci_device,
+        &scif0_device,
         &tmu0_device,
         &tmu1_device,
         &tmu2_device,
@@ -141,6 +137,7 @@ static int __init sh4202_devices_setup(void)
 arch_initcall(sh4202_devices_setup);
 
 static struct platform_device *sh4202_early_devices[] __initdata = {
+        &scif0_device,
         &tmu0_device,
         &tmu1_device,
         &tmu2_device,
diff --git a/arch/sh/kernel/cpu/sh4/setup-sh7750.c b/arch/sh/kernel/cpu/sh4/setup-sh7750.c
index 1b8b122e8f3d..b2a9df1af64c 100644
--- a/arch/sh/kernel/cpu/sh4/setup-sh7750.c
+++ b/arch/sh/kernel/cpu/sh4/setup-sh7750.c
@@ -35,29 +35,33 @@ static struct platform_device rtc_device = {
         .resource       = rtc_resources,
 };
 
-static struct plat_sci_port sci_platform_data[] = {
-        {
-#ifndef CONFIG_SH_RTS7751R2D
-                .mapbase        = 0xffe00000,
-                .flags          = UPF_BOOT_AUTOCONF,
-                .type           = PORT_SCI,
-                .irqs           = { 23, 23, 23, 0 },
-        }, {
-#endif
-                .mapbase        = 0xffe80000,
-                .flags          = UPF_BOOT_AUTOCONF,
-                .type           = PORT_SCIF,
-                .irqs           = { 40, 40, 40, 40 },
-        }, {
-                .flags = 0,
-        }
+static struct plat_sci_port scif0_platform_data = {
+        .mapbase        = 0xffe00000,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .type           = PORT_SCI,
+        .irqs           = { 23, 23, 23, 0 },
 };
 
-static struct platform_device sci_device = {
+static struct platform_device scif0_device = {
         .name           = "sh-sci",
-        .id             = -1,
+        .id             = 0,
+        .dev            = {
+                .platform_data  = &scif0_platform_data,
+        },
+};
+
+static struct plat_sci_port scif1_platform_data = {
+        .mapbase        = 0xffe80000,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .type           = PORT_SCIF,
+        .irqs           = { 40, 40, 40, 40 },
+};
+
+static struct platform_device scif1_device = {
+        .name           = "sh-sci",
+        .id             = 1,
         .dev            = {
-                .platform_data  = sci_platform_data,
+                .platform_data  = &scif1_platform_data,
         },
 };
 
@@ -221,8 +225,9 @@ static struct platform_device tmu4_device = {
 #endif
 
 static struct platform_device *sh7750_devices[] __initdata = {
+        &scif0_device,
+        &scif1_device,
         &rtc_device,
-        &sci_device,
         &tmu0_device,
         &tmu1_device,
         &tmu2_device,
@@ -242,6 +247,8 @@ static int __init sh7750_devices_setup(void)
 arch_initcall(sh7750_devices_setup);
 
 static struct platform_device *sh7750_early_devices[] __initdata = {
+        &scif0_device,
+        &scif1_device,
         &tmu0_device,
         &tmu1_device,
         &tmu2_device,
diff --git a/arch/sh/kernel/cpu/sh4/setup-sh7760.c b/arch/sh/kernel/cpu/sh4/setup-sh7760.c
index 7fbb7be9284c..5b74cc0b43da 100644
--- a/arch/sh/kernel/cpu/sh4/setup-sh7760.c
+++ b/arch/sh/kernel/cpu/sh4/setup-sh7760.c
@@ -126,37 +126,63 @@ static struct intc_vect vectors_irq[] __initdata = {
 static DECLARE_INTC_DESC(intc_desc_irq, "sh7760-irq", vectors_irq, groups,
                          mask_registers, prio_registers, NULL);
 
-static struct plat_sci_port sci_platform_data[] = {
-        {
-                .mapbase        = 0xfe600000,
-                .flags          = UPF_BOOT_AUTOCONF,
-                .type           = PORT_SCIF,
-                .irqs           = { 52, 53, 55, 54 },
-        }, {
-                .mapbase        = 0xfe610000,
-                .flags          = UPF_BOOT_AUTOCONF,
-                .type           = PORT_SCIF,
-                .irqs           = { 72, 73, 75, 74 },
-        }, {
-                .mapbase        = 0xfe620000,
-                .flags          = UPF_BOOT_AUTOCONF,
-                .type           = PORT_SCIF,
-                .irqs           = { 76, 77, 79, 78 },
-        }, {
-                .mapbase        = 0xfe480000,
-                .flags          = UPF_BOOT_AUTOCONF,
-                .type           = PORT_SCI,
-                .irqs           = { 80, 81, 82, 0 },
-        }, {
-                .flags = 0,
-        }
+static struct plat_sci_port scif0_platform_data = {
+        .mapbase        = 0xfe600000,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .type           = PORT_SCIF,
+        .irqs           = { 52, 53, 55, 54 },
+};
+
+static struct platform_device scif0_device = {
+        .name           = "sh-sci",
+        .id             = 0,
+        .dev            = {
+                .platform_data  = &scif0_platform_data,
+        },
+};
+
+static struct plat_sci_port scif1_platform_data = {
+        .mapbase        = 0xfe610000,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .type           = PORT_SCIF,
+        .irqs           = { 72, 73, 75, 74 },
+};
+
+static struct platform_device scif1_device = {
+        .name           = "sh-sci",
+        .id             = 1,
+        .dev            = {
+                .platform_data  = &scif1_platform_data,
+        },
+};
+
+static struct plat_sci_port scif2_platform_data = {
+        .mapbase        = 0xfe620000,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .type           = PORT_SCIF,
+        .irqs           = { 76, 77, 79, 78 },
+};
+
+static struct platform_device scif2_device = {
+        .name           = "sh-sci",
+        .id             = 2,
+        .dev            = {
+                .platform_data  = &scif2_platform_data,
+        },
+};
+
+static struct plat_sci_port scif3_platform_data = {
+        .mapbase        = 0xfe480000,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .type           = PORT_SCI,
+        .irqs           = { 80, 81, 82, 0 },
 };
 
-static struct platform_device sci_device = {
+static struct platform_device scif3_device = {
         .name           = "sh-sci",
-        .id             = -1,
+        .id             = 3,
         .dev            = {
-                .platform_data  = sci_platform_data,
+                .platform_data  = &scif3_platform_data,
         },
 };
 
@@ -254,7 +280,10 @@ static struct platform_device tmu2_device = {
 
 
 static struct platform_device *sh7760_devices[] __initdata = {
-        &sci_device,
+        &scif0_device,
+        &scif1_device,
+        &scif2_device,
+        &scif3_device,
         &tmu0_device,
         &tmu1_device,
         &tmu2_device,
@@ -268,6 +297,10 @@ static int __init sh7760_devices_setup(void)
 arch_initcall(sh7760_devices_setup);
 
 static struct platform_device *sh7760_early_devices[] __initdata = {
+        &scif0_device,
+        &scif1_device,
+        &scif2_device,
+        &scif3_device,
         &tmu0_device,
         &tmu1_device,
         &tmu2_device,
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7343.c b/arch/sh/kernel/cpu/sh4a/setup-sh7343.c
index ac4d5672ec1a..45eb1bfd42c9 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7343.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7343.c
@@ -15,6 +15,71 @@
 #include <linux/sh_timer.h>
 #include <asm/clock.h>
 
+/* Serial */
+static struct plat_sci_port scif0_platform_data = {
+        .mapbase        = 0xffe00000,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .type           = PORT_SCIF,
+        .irqs           = { 80, 80, 80, 80 },
+        .clk            = "scif0",
+};
+
+static struct platform_device scif0_device = {
+        .name           = "sh-sci",
+        .id             = 0,
+        .dev            = {
+                .platform_data  = &scif0_platform_data,
+        },
+};
+
+static struct plat_sci_port scif1_platform_data = {
+        .mapbase        = 0xffe10000,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .type           = PORT_SCIF,
+        .irqs           = { 81, 81, 81, 81 },
+        .clk            = "scif1",
+};
+
+static struct platform_device scif1_device = {
+        .name           = "sh-sci",
+        .id             = 1,
+        .dev            = {
+                .platform_data  = &scif1_platform_data,
+        },
+};
+
+static struct plat_sci_port scif2_platform_data = {
+        .mapbase        = 0xffe20000,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .type           = PORT_SCIF,
+        .irqs           = { 82, 82, 82, 82 },
+        .clk            = "scif2",
+};
+
+static struct platform_device scif2_device = {
+        .name           = "sh-sci",
+        .id             = 2,
+        .dev            = {
+                .platform_data  = &scif2_platform_data,
+        },
+};
+
+static struct plat_sci_port scif3_platform_data = {
+        .mapbase        = 0xffe30000,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .type           = PORT_SCIF,
+        .irqs           = { 83, 83, 83, 83 },
+        .clk            = "scif3",
+};
+
+static struct platform_device scif3_device = {
+        .name           = "sh-sci",
+        .id             = 3,
+        .dev            = {
+                .platform_data  = &scif3_platform_data,
+        },
+};
+
 static struct resource iic0_resources[] = {
         [0] = {
                 .name   = "IIC0",
@@ -265,52 +330,17 @@ static struct platform_device tmu2_device = {
         .num_resources  = ARRAY_SIZE(tmu2_resources),
 };
 
-static struct plat_sci_port sci_platform_data[] = {
-        {
-                .mapbase        = 0xffe00000,
-                .flags          = UPF_BOOT_AUTOCONF,
-                .type           = PORT_SCIF,
-                .irqs           = { 80, 80, 80, 80 },
-                .clk            = "scif0",
-        }, {
-                .mapbase        = 0xffe10000,
-                .flags          = UPF_BOOT_AUTOCONF,
-                .type           = PORT_SCIF,
-                .irqs           = { 81, 81, 81, 81 },
-                .clk            = "scif1",
-        }, {
-                .mapbase        = 0xffe20000,
-                .flags          = UPF_BOOT_AUTOCONF,
-                .type           = PORT_SCIF,
-                .irqs           = { 82, 82, 82, 82 },
-                .clk            = "scif2",
-        }, {
-                .mapbase        = 0xffe30000,
-                .flags          = UPF_BOOT_AUTOCONF,
-                .type           = PORT_SCIF,
-                .irqs           = { 83, 83, 83, 83 },
-                .clk            = "scif3",
-        }, {
-                .flags = 0,
-        }
-};
-
-static struct platform_device sci_device = {
-        .name           = "sh-sci",
-        .id             = -1,
-        .dev            = {
-                .platform_data  = sci_platform_data,
-        },
-};
-
 static struct platform_device *sh7343_devices[] __initdata = {
+        &scif0_device,
+        &scif1_device,
+        &scif2_device,
+        &scif3_device,
         &cmt_device,
         &tmu0_device,
         &tmu1_device,
         &tmu2_device,
         &iic0_device,
         &iic1_device,
-        &sci_device,
         &vpu_device,
         &veu_device,
         &jpu_device,
@@ -328,6 +358,10 @@ static int __init sh7343_devices_setup(void)
 arch_initcall(sh7343_devices_setup);
 
 static struct platform_device *sh7343_early_devices[] __initdata = {
+        &scif0_device,
+        &scif1_device,
+        &scif2_device,
+        &scif3_device,
         &cmt_device,
         &tmu0_device,
         &tmu1_device,
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7366.c b/arch/sh/kernel/cpu/sh4a/setup-sh7366.c
index 4a9010bf4fd3..c494c193e3b6 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7366.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7366.c
@@ -18,6 +18,22 @@
 #include <linux/usb/r8a66597.h>
 #include <asm/clock.h>
 
+static struct plat_sci_port scif0_platform_data = {
+        .mapbase        = 0xffe00000,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .type           = PORT_SCIF,
+        .irqs           = { 80, 80, 80, 80 },
+        .clk            = "scif0",
+};
+
+static struct platform_device scif0_device = {
+        .name           = "sh-sci",
+        .id             = 0,
+        .dev            = {
+                .platform_data  = &scif0_platform_data,
+        },
+};
+
 static struct resource iic_resources[] = {
         [0] = {
                 .name   = "IIC",
@@ -276,33 +292,13 @@ static struct platform_device tmu2_device = {
         .num_resources  = ARRAY_SIZE(tmu2_resources),
 };
 
-static struct plat_sci_port sci_platform_data[] = {
-        {
-                .mapbase        = 0xffe00000,
-                .flags          = UPF_BOOT_AUTOCONF,
-                .type           = PORT_SCIF,
-                .irqs           = { 80, 80, 80, 80 },
-                .clk            = "scif0",
-        }, {
-                .flags = 0,
-        }
-};
-
-static struct platform_device sci_device = {
-        .name           = "sh-sci",
-        .id             = -1,
-        .dev            = {
-                .platform_data  = sci_platform_data,
-        },
-};
-
 static struct platform_device *sh7366_devices[] __initdata = {
+        &scif0_device,
         &cmt_device,
         &tmu0_device,
         &tmu1_device,
         &tmu2_device,
         &iic_device,
-        &sci_device,
         &usb_host_device,
         &vpu_device,
         &veu0_device,
@@ -321,6 +317,7 @@ static int __init sh7366_devices_setup(void)
 arch_initcall(sh7366_devices_setup);
 
 static struct platform_device *sh7366_early_devices[] __initdata = {
+        &scif0_device,
         &cmt_device,
         &tmu0_device,
         &tmu1_device,
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7722.c b/arch/sh/kernel/cpu/sh4a/setup-sh7722.c
index 5491b094cf05..b5335b5e309c 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7722.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7722.c
@@ -20,6 +20,55 @@
 #include <asm/dma-sh.h>
 #include <cpu/sh7722.h>
 
+/* Serial */
+static struct plat_sci_port scif0_platform_data = {
+        .mapbase        = 0xffe00000,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .type           = PORT_SCIF,
+        .irqs           = { 80, 80, 80, 80 },
+        .clk            = "scif0",
+};
+
+static struct platform_device scif0_device = {
+        .name           = "sh-sci",
+        .id             = 0,
+        .dev            = {
+                .platform_data  = &scif0_platform_data,
+        },
+};
+
+static struct plat_sci_port scif1_platform_data = {
+        .mapbase        = 0xffe10000,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .type           = PORT_SCIF,
+        .irqs           = { 81, 81, 81, 81 },
+        .clk            = "scif1",
+};
+
+static struct platform_device scif1_device = {
+        .name           = "sh-sci",
+        .id             = 1,
+        .dev            = {
+                .platform_data  = &scif1_platform_data,
+        },
+};
+
+static struct plat_sci_port scif2_platform_data = {
+        .mapbase        = 0xffe20000,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .type           = PORT_SCIF,
+        .irqs           = { 82, 82, 82, 82 },
+        .clk            = "scif2",
+};
+
+static struct platform_device scif2_device = {
+        .name           = "sh-sci",
+        .id             = 2,
+        .dev            = {
+                .platform_data  = &scif2_platform_data,
+        },
+};
+
 static struct resource rtc_resources[] = {
         [0] = {
                 .start  = 0xa465fec0,
@@ -339,41 +388,6 @@ static struct platform_device tmu2_device = {
         },
 };
 
-static struct plat_sci_port sci_platform_data[] = {
-        {
-                .mapbase        = 0xffe00000,
-                .flags          = UPF_BOOT_AUTOCONF,
-                .type           = PORT_SCIF,
-                .irqs           = { 80, 80, 80, 80 },
-                .clk            = "scif0",
-        },
-        {
-                .mapbase        = 0xffe10000,
-                .flags          = UPF_BOOT_AUTOCONF,
-                .type           = PORT_SCIF,
-                .irqs           = { 81, 81, 81, 81 },
-                .clk            = "scif1",
-        },
-        {
-                .mapbase        = 0xffe20000,
-                .flags          = UPF_BOOT_AUTOCONF,
-                .type           = PORT_SCIF,
-                .irqs           = { 82, 82, 82, 82 },
-                .clk            = "scif2",
-        },
-        {
-                .flags = 0,
-        }
-};
-
-static struct platform_device sci_device = {
-        .name           = "sh-sci",
-        .id             = -1,
-        .dev            = {
-                .platform_data  = sci_platform_data,
-        },
-};
-
 static struct sh_dmae_pdata dma_platform_data = {
         .mode = 0,
 };
@@ -387,6 +401,9 @@ static struct platform_device dma_device = {
 };
 
 static struct platform_device *sh7722_devices[] __initdata = {
+        &scif0_device,
+        &scif1_device,
+        &scif2_device,
         &cmt_device,
         &tmu0_device,
         &tmu1_device,
@@ -394,7 +411,6 @@ static struct platform_device *sh7722_devices[] __initdata = {
         &rtc_device,
         &usbf_device,
         &iic_device,
-        &sci_device,
         &vpu_device,
         &veu_device,
         &jpu_device,
@@ -413,6 +429,9 @@ static int __init sh7722_devices_setup(void)
 arch_initcall(sh7722_devices_setup);
 
 static struct platform_device *sh7722_early_devices[] __initdata = {
+        &scif0_device,
+        &scif1_device,
+        &scif2_device,
         &cmt_device,
         &tmu0_device,
         &tmu1_device,
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7723.c b/arch/sh/kernel/cpu/sh4a/setup-sh7723.c
index 4caa5a7ca86e..772b9265d0e4 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7723.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7723.c
@@ -20,6 +20,103 @@
 #include <asm/mmzone.h>
 #include <cpu/sh7723.h>
 
+/* Serial */
+static struct plat_sci_port scif0_platform_data = {
+        .mapbase        = 0xffe00000,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .type           = PORT_SCIF,
+        .irqs           = { 80, 80, 80, 80 },
+        .clk            = "scif0",
+};
+
+static struct platform_device scif0_device = {
+        .name           = "sh-sci",
+        .id             = 0,
+        .dev            = {
+                .platform_data  = &scif0_platform_data,
+        },
+};
+
+static struct plat_sci_port scif1_platform_data = {
+        .mapbase        = 0xffe10000,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .type           = PORT_SCIF,
+        .irqs           = { 81, 81, 81, 81 },
+        .clk            = "scif1",
+};
+
+static struct platform_device scif1_device = {
+        .name           = "sh-sci",
+        .id             = 1,
+        .dev            = {
+                .platform_data  = &scif1_platform_data,
+        },
+};
+
+static struct plat_sci_port scif2_platform_data = {
+        .mapbase        = 0xffe20000,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .type           = PORT_SCIF,
+        .irqs           = { 82, 82, 82, 82 },
+        .clk            = "scif2",
+};
+
+static struct platform_device scif2_device = {
+        .name           = "sh-sci",
+        .id             = 2,
+        .dev            = {
+                .platform_data  = &scif2_platform_data,
+        },
+};
+
+static struct plat_sci_port scif3_platform_data = {
+        .mapbase        = 0xa4e30000,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .type           = PORT_SCIFA,
+        .irqs           = { 56, 56, 56, 56 },
+        .clk            = "scif3",
+};
+
+static struct platform_device scif3_device = {
+        .name           = "sh-sci",
+        .id             = 3,
+        .dev            = {
+                .platform_data  = &scif3_platform_data,
+        },
+};
+
+static struct plat_sci_port scif4_platform_data = {
+        .mapbase        = 0xa4e40000,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .type           = PORT_SCIFA,
+        .irqs           = { 88, 88, 88, 88 },
+        .clk            = "scif4",
+};
+
+static struct platform_device scif4_device = {
+        .name           = "sh-sci",
+        .id             = 4,
+        .dev            = {
+                .platform_data  = &scif4_platform_data,
+        },
+};
+
+static struct plat_sci_port scif5_platform_data = {
+        .mapbase        = 0xa4e50000,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .type           = PORT_SCIFA,
+        .irqs           = { 109, 109, 109, 109 },
+        .clk            = "scif5",
+};
+
+static struct platform_device scif5_device = {
+        .name           = "sh-sci",
+        .id             = 5,
+        .dev            = {
+                .platform_data  = &scif5_platform_data,
+        },
+};
+
 static struct uio_info vpu_platform_data = {
         .name = "VPU5",
         .version = "0",
@@ -348,56 +445,6 @@ static struct platform_device tmu5_device = {
         },
 };
 
-static struct plat_sci_port sci_platform_data[] = {
-        {
-                .mapbase        = 0xffe00000,
-                .flags          = UPF_BOOT_AUTOCONF,
-                .type           = PORT_SCIF,
-                .irqs           = { 80, 80, 80, 80 },
-                .clk            = "scif0",
-        },{
-                .mapbase        = 0xffe10000,
-                .flags          = UPF_BOOT_AUTOCONF,
-                .type           = PORT_SCIF,
-                .irqs           = { 81, 81, 81, 81 },
-                .clk            = "scif1",
-        },{
-                .mapbase        = 0xffe20000,
-                .flags          = UPF_BOOT_AUTOCONF,
-                .type           = PORT_SCIF,
-                .irqs           = { 82, 82, 82, 82 },
-                .clk            = "scif2",
-        },{
-                .mapbase        = 0xa4e30000,
-                .flags          = UPF_BOOT_AUTOCONF,
-                .type           = PORT_SCIFA,
-                .irqs           = { 56, 56, 56, 56 },
-                .clk            = "scif3",
-        },{
-                .mapbase        = 0xa4e40000,
-                .flags          = UPF_BOOT_AUTOCONF,
-                .type           = PORT_SCIFA,
-                .irqs           = { 88, 88, 88, 88 },
-                .clk            = "scif4",
-        },{
-                .mapbase        = 0xa4e50000,
-                .flags          = UPF_BOOT_AUTOCONF,
-                .type           = PORT_SCIFA,
-                .irqs           = { 109, 109, 109, 109 },
-                .clk            = "scif5",
-        }, {
-                .flags = 0,
-        }
-};
-
-static struct platform_device sci_device = {
-        .name           = "sh-sci",
-        .id             = -1,
-        .dev            = {
-                .platform_data  = sci_platform_data,
-        },
-};
-
 static struct resource rtc_resources[] = {
         [0] = {
                 .start  = 0xa465fec0,
@@ -488,6 +535,12 @@ static struct platform_device iic_device = {
 };
 
 static struct platform_device *sh7723_devices[] __initdata = {
+        &scif0_device,
+        &scif1_device,
+        &scif2_device,
+        &scif3_device,
+        &scif4_device,
+        &scif5_device,
         &cmt_device,
         &tmu0_device,
         &tmu1_device,
@@ -495,7 +548,6 @@ static struct platform_device *sh7723_devices[] __initdata = {
         &tmu3_device,
         &tmu4_device,
         &tmu5_device,
-        &sci_device,
         &rtc_device,
         &iic_device,
         &sh7723_usb_host_device,
@@ -516,6 +568,12 @@ static int __init sh7723_devices_setup(void)
 arch_initcall(sh7723_devices_setup);
 
 static struct platform_device *sh7723_early_devices[] __initdata = {
+        &scif0_device,
+        &scif1_device,
+        &scif2_device,
+        &scif3_device,
+        &scif4_device,
+        &scif5_device,
         &cmt_device,
         &tmu0_device,
         &tmu1_device,
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7724.c b/arch/sh/kernel/cpu/sh4a/setup-sh7724.c
index 845e89c936e7..a52f35117e82 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7724.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7724.c
@@ -27,53 +27,99 @@
 #include <cpu/sh7724.h>
 
 /* Serial */
-static struct plat_sci_port sci_platform_data[] = {
-        {
-                .mapbase        = 0xffe00000,
-                .flags          = UPF_BOOT_AUTOCONF,
-                .type           = PORT_SCIF,
-                .irqs           = { 80, 80, 80, 80 },
-                .clk            = "scif0",
-        }, {
-                .mapbase        = 0xffe10000,
-                .flags          = UPF_BOOT_AUTOCONF,
-                .type           = PORT_SCIF,
-                .irqs           = { 81, 81, 81, 81 },
-                .clk            = "scif1",
-        }, {
-                .mapbase        = 0xffe20000,
-                .flags          = UPF_BOOT_AUTOCONF,
-                .type           = PORT_SCIF,
-                .irqs           = { 82, 82, 82, 82 },
-                .clk            = "scif2",
-        }, {
-                .mapbase        = 0xa4e30000,
-                .flags          = UPF_BOOT_AUTOCONF,
-                .type           = PORT_SCIFA,
-                .irqs           = { 56, 56, 56, 56 },
-                .clk            = "scif3",
-        }, {
-                .mapbase        = 0xa4e40000,
-                .flags          = UPF_BOOT_AUTOCONF,
-                .type           = PORT_SCIFA,
-                .irqs           = { 88, 88, 88, 88 },
-                .clk            = "scif4",
-        }, {
-                .mapbase        = 0xa4e50000,
-                .flags          = UPF_BOOT_AUTOCONF,
-                .type           = PORT_SCIFA,
-                .irqs           = { 109, 109, 109, 109 },
-                .clk            = "scif5",
-        }, {
-                .flags = 0,
-        }
-};
-
-static struct platform_device sci_device = {
+static struct plat_sci_port scif0_platform_data = {
+        .mapbase        = 0xffe00000,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .type           = PORT_SCIF,
+        .irqs           = { 80, 80, 80, 80 },
+        .clk            = "scif0",
+};
+
+static struct platform_device scif0_device = {
         .name           = "sh-sci",
-        .id             = -1,
+        .id             = 0,
+        .dev            = {
+                .platform_data  = &scif0_platform_data,
+        },
+};
+
+static struct plat_sci_port scif1_platform_data = {
+        .mapbase        = 0xffe10000,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .type           = PORT_SCIF,
+        .irqs           = { 81, 81, 81, 81 },
+        .clk            = "scif1",
+};
+
+static struct platform_device scif1_device = {
+        .name           = "sh-sci",
+        .id             = 1,
+        .dev            = {
+                .platform_data  = &scif1_platform_data,
+        },
+};
+
+static struct plat_sci_port scif2_platform_data = {
+        .mapbase        = 0xffe20000,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .type           = PORT_SCIF,
+        .irqs           = { 82, 82, 82, 82 },
+        .clk            = "scif2",
+};
+
+static struct platform_device scif2_device = {
+        .name           = "sh-sci",
+        .id             = 2,
+        .dev            = {
+                .platform_data  = &scif2_platform_data,
+        },
+};
+
+static struct plat_sci_port scif3_platform_data = {
+        .mapbase        = 0xa4e30000,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .type           = PORT_SCIFA,
+        .irqs           = { 56, 56, 56, 56 },
+        .clk            = "scif3",
+};
+
+static struct platform_device scif3_device = {
+        .name           = "sh-sci",
+        .id             = 3,
+        .dev            = {
+                .platform_data  = &scif3_platform_data,
+        },
+};
+
+static struct plat_sci_port scif4_platform_data = {
+        .mapbase        = 0xa4e40000,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .type           = PORT_SCIFA,
+        .irqs           = { 88, 88, 88, 88 },
+        .clk            = "scif4",
+};
+
+static struct platform_device scif4_device = {
+        .name           = "sh-sci",
+        .id             = 4,
+        .dev            = {
+                .platform_data  = &scif4_platform_data,
+        },
+};
+
+static struct plat_sci_port scif5_platform_data = {
+        .mapbase        = 0xa4e50000,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .type           = PORT_SCIFA,
+        .irqs           = { 109, 109, 109, 109 },
+        .clk            = "scif5",
+};
+
+static struct platform_device scif5_device = {
+        .name           = "sh-sci",
+        .id             = 5,
         .dev            = {
-                .platform_data  = sci_platform_data,
+                .platform_data  = &scif5_platform_data,
         },
 };
 
@@ -590,6 +636,12 @@ static struct platform_device spu1_device = {
 };
 
 static struct platform_device *sh7724_devices[] __initdata = {
+        &scif0_device,
+        &scif1_device,
+        &scif2_device,
+        &scif3_device,
+        &scif4_device,
+        &scif5_device,
         &cmt_device,
         &tmu0_device,
         &tmu1_device,
@@ -597,7 +649,6 @@ static struct platform_device *sh7724_devices[] __initdata = {
         &tmu3_device,
         &tmu4_device,
         &tmu5_device,
-        &sci_device,
         &rtc_device,
         &iic0_device,
         &iic1_device,
@@ -624,6 +675,12 @@ static int __init sh7724_devices_setup(void)
 arch_initcall(sh7724_devices_setup);
 
 static struct platform_device *sh7724_early_devices[] __initdata = {
+        &scif0_device,
+        &scif1_device,
+        &scif2_device,
+        &scif3_device,
+        &scif4_device,
+        &scif5_device,
         &cmt_device,
         &tmu0_device,
         &tmu1_device,
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7757.c b/arch/sh/kernel/cpu/sh4a/setup-sh7757.c
index c470e15f2e03..37e32efbbaa7 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7757.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7757.c
@@ -17,6 +17,51 @@
 #include <linux/mm.h>
 #include <linux/sh_timer.h>
 
+static struct plat_sci_port scif2_platform_data = {
+        .mapbase        = 0xfe4b0000,           /* SCIF2 */
+        .flags          = UPF_BOOT_AUTOCONF,
+        .type           = PORT_SCIF,
+        .irqs           = { 40, 40, 40, 40 },
+};
+
+static struct platform_device scif2_device = {
+        .name           = "sh-sci",
+        .id             = 2,
+        .dev            = {
+                .platform_data  = &scif2_platform_data,
+        },
+};
+
+static struct plat_sci_port scif3_platform_data = {
+        .mapbase        = 0xfe4c0000,           /* SCIF3 */
+        .flags          = UPF_BOOT_AUTOCONF,
+        .type           = PORT_SCIF,
+        .irqs           = { 76, 76, 76, 76 },
+};
+
+static struct platform_device scif3_device = {
+        .name           = "sh-sci",
+        .id             = 3,
+        .dev            = {
+                .platform_data  = &scif3_platform_data,
+        },
+};
+
+static struct plat_sci_port scif4_platform_data = {
+        .mapbase        = 0xfe4d0000,           /* SCIF4 */
+        .flags          = UPF_BOOT_AUTOCONF,
+        .type           = PORT_SCIF,
+        .irqs           = { 104, 104, 104, 104 },
+};
+
+static struct platform_device scif4_device = {
+        .name           = "sh-sci",
+        .id             = 4,
+        .dev            = {
+                .platform_data  = &scif4_platform_data,
+        },
+};
+
 static struct sh_timer_config tmu0_platform_data = {
         .name = "TMU0",
         .channel_offset = 0x04,
@@ -79,39 +124,12 @@ static struct platform_device tmu1_device = {
         .num_resources  = ARRAY_SIZE(tmu1_resources),
 };
 
-static struct plat_sci_port sci_platform_data[] = {
-        {
-                .mapbase        = 0xfe4b0000,           /* SCIF2 */
-                .flags          = UPF_BOOT_AUTOCONF,
-                .type           = PORT_SCIF,
-                .irqs           = { 40, 40, 40, 40 },
-        }, {
-                .mapbase        = 0xfe4c0000,           /* SCIF3 */
-                .flags          = UPF_BOOT_AUTOCONF,
-                .type           = PORT_SCIF,
-                .irqs           = { 76, 76, 76, 76 },
-        }, {
-                .mapbase        = 0xfe4d0000,           /* SCIF4 */
-                .flags          = UPF_BOOT_AUTOCONF,
-                .type           = PORT_SCIF,
-                .irqs           = { 104, 104, 104, 104 },
-        }, {
-                .flags = 0,
-        }
-};
-
-static struct platform_device sci_device = {
-        .name           = "sh-sci",
-        .id             = -1,
-        .dev            = {
-                .platform_data  = sci_platform_data,
-        },
-};
-
 static struct platform_device *sh7757_devices[] __initdata = {
+        &scif2_device,
+        &scif3_device,
+        &scif4_device,
         &tmu0_device,
         &tmu1_device,
-        &sci_device,
 };
 
 static int __init sh7757_devices_setup(void)
@@ -121,6 +139,20 @@ static int __init sh7757_devices_setup(void)
 }
 arch_initcall(sh7757_devices_setup);
 
+static struct platform_device *sh7757_early_devices[] __initdata = {
+        &scif2_device,
+        &scif3_device,
+        &scif4_device,
+        &tmu0_device,
+        &tmu1_device,
+};
+
+void __init plat_early_device_setup(void)
+{
+        early_platform_add_devices(sh7757_early_devices,
+                                   ARRAY_SIZE(sh7757_early_devices));
+}
+
 enum {
         UNUSED = 0,
 
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7763.c b/arch/sh/kernel/cpu/sh4a/setup-sh7763.c
index 4659fff6b842..6aba26fec416 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7763.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7763.c
@@ -16,6 +16,51 @@
 #include <linux/io.h>
 #include <linux/serial_sci.h>
 
+static struct plat_sci_port scif0_platform_data = {
+        .mapbase        = 0xffe00000,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .type           = PORT_SCIF,
+        .irqs           = { 40, 40, 40, 40 },
+};
+
+static struct platform_device scif0_device = {
+        .name           = "sh-sci",
+        .id             = 0,
+        .dev            = {
+                .platform_data  = &scif0_platform_data,
+        },
+};
+
+static struct plat_sci_port scif1_platform_data = {
+        .mapbase        = 0xffe08000,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .type           = PORT_SCIF,
+        .irqs           = { 76, 76, 76, 76 },
+};
+
+static struct platform_device scif1_device = {
+        .name           = "sh-sci",
+        .id             = 1,
+        .dev            = {
+                .platform_data  = &scif1_platform_data,
+        },
+};
+
+static struct plat_sci_port scif2_platform_data = {
+        .mapbase        = 0xffe10000,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .type           = PORT_SCIF,
+        .irqs           = { 104, 104, 104, 104 },
+};
+
+static struct platform_device scif2_device = {
+        .name           = "sh-sci",
+        .id             = 2,
+        .dev            = {
+                .platform_data  = &scif2_platform_data,
+        },
+};
+
 static struct resource rtc_resources[] = {
         [0] = {
                 .start  = 0xffe80000,
@@ -36,35 +81,6 @@ static struct platform_device rtc_device = {
         .resource       = rtc_resources,
 };
 
-static struct plat_sci_port sci_platform_data[] = {
-        {
-                .mapbase        = 0xffe00000,
-                .flags          = UPF_BOOT_AUTOCONF,
-                .type           = PORT_SCIF,
-                .irqs           = { 40, 40, 40, 40 },
-        }, {
-                .mapbase        = 0xffe08000,
-                .flags          = UPF_BOOT_AUTOCONF,
-                .type           = PORT_SCIF,
-                .irqs           = { 76, 76, 76, 76 },
-        }, {
-                .mapbase        = 0xffe10000,
-                .flags          = UPF_BOOT_AUTOCONF,
-                .type           = PORT_SCIF,
-                .irqs           = { 104, 104, 104, 104 },
-        }, {
-                .flags = 0,
-        }
-};
-
-static struct platform_device sci_device = {
-        .name           = "sh-sci",
-        .id             = -1,
-        .dev            = {
-                .platform_data  = sci_platform_data,
-        },
-};
-
 static struct resource usb_ohci_resources[] = {
         [0] = {
                 .start  = 0xffec8000,
@@ -297,6 +313,9 @@ static struct platform_device tmu5_device = {
 };
 
 static struct platform_device *sh7763_devices[] __initdata = {
+        &scif0_device,
+        &scif1_device,
+        &scif2_device,
         &tmu0_device,
         &tmu1_device,
         &tmu2_device,
@@ -304,7 +323,6 @@ static struct platform_device *sh7763_devices[] __initdata = {
         &tmu4_device,
         &tmu5_device,
         &rtc_device,
-        &sci_device,
         &usb_ohci_device,
         &usbf_device,
 };
@@ -317,6 +335,9 @@ static int __init sh7763_devices_setup(void)
 arch_initcall(sh7763_devices_setup);
 
 static struct platform_device *sh7763_early_devices[] __initdata = {
+        &scif0_device,
+        &scif1_device,
+        &scif2_device,
         &tmu0_device,
         &tmu1_device,
         &tmu2_device,
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7770.c b/arch/sh/kernel/cpu/sh4a/setup-sh7770.c
index eead08d89d32..c1643bc9590d 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7770.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7770.c
@@ -14,67 +14,153 @@
 #include <linux/sh_timer.h>
 #include <linux/io.h>
 
-static struct plat_sci_port sci_platform_data[] = {
-        {
-                .mapbase        = 0xff923000,
-                .flags          = UPF_BOOT_AUTOCONF,
-                .type           = PORT_SCIF,
-                .irqs           = { 61, 61, 61, 61 },
-        }, {
-                .mapbase        = 0xff924000,
-                .flags          = UPF_BOOT_AUTOCONF,
-                .type           = PORT_SCIF,
-                .irqs           = { 62, 62, 62, 62 },
-        }, {
-                .mapbase        = 0xff925000,
-                .flags          = UPF_BOOT_AUTOCONF,
-                .type           = PORT_SCIF,
-                .irqs           = { 63, 63, 63, 63 },
-        }, {
-                .mapbase        = 0xff926000,
-                .flags          = UPF_BOOT_AUTOCONF,
-                .type           = PORT_SCIF,
-                .irqs           = { 64, 64, 64, 64 },
-        }, {
-                .mapbase        = 0xff927000,
-                .flags          = UPF_BOOT_AUTOCONF,
-                .type           = PORT_SCIF,
-                .irqs           = { 65, 65, 65, 65 },
-        }, {
-                .mapbase        = 0xff928000,
-                .flags          = UPF_BOOT_AUTOCONF,
-                .type           = PORT_SCIF,
-                .irqs           = { 66, 66, 66, 66 },
-        }, {
-                .mapbase        = 0xff929000,
-                .flags          = UPF_BOOT_AUTOCONF,
-                .type           = PORT_SCIF,
-                .irqs           = { 67, 67, 67, 67 },
-        }, {
-                .mapbase        = 0xff92a000,
-                .flags          = UPF_BOOT_AUTOCONF,
-                .type           = PORT_SCIF,
-                .irqs           = { 68, 68, 68, 68 },
-        }, {
-                .mapbase        = 0xff92b000,
-                .flags          = UPF_BOOT_AUTOCONF,
-                .type           = PORT_SCIF,
-                .irqs           = { 69, 69, 69, 69 },
-        }, {
-                .mapbase        = 0xff92c000,
-                .flags          = UPF_BOOT_AUTOCONF,
-                .type           = PORT_SCIF,
-                .irqs           = { 70, 70, 70, 70 },
-        }, {
-                .flags = 0,
-        }
+static struct plat_sci_port scif0_platform_data = {
+        .mapbase        = 0xff923000,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .type           = PORT_SCIF,
+        .irqs           = { 61, 61, 61, 61 },
+};
+
+static struct platform_device scif0_device = {
+        .name           = "sh-sci",
+        .id             = 0,
+        .dev            = {
+                .platform_data  = &scif0_platform_data,
+        },
+};
+
+static struct plat_sci_port scif1_platform_data = {
+        .mapbase        = 0xff924000,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .type           = PORT_SCIF,
+        .irqs           = { 62, 62, 62, 62 },
+};
+
+static struct platform_device scif1_device = {
+        .name           = "sh-sci",
+        .id             = 1,
+        .dev            = {
+                .platform_data  = &scif1_platform_data,
+        },
+};
+
+static struct plat_sci_port scif2_platform_data = {
+        .mapbase        = 0xff925000,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .type           = PORT_SCIF,
+        .irqs           = { 63, 63, 63, 63 },
+};
+
+static struct platform_device scif2_device = {
+        .name           = "sh-sci",
+        .id             = 2,
+        .dev            = {
+                .platform_data  = &scif2_platform_data,
+        },
+};
+
+static struct plat_sci_port scif3_platform_data = {
+        .mapbase        = 0xff926000,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .type           = PORT_SCIF,
+        .irqs           = { 64, 64, 64, 64 },
+};
+
+static struct platform_device scif3_device = {
+        .name           = "sh-sci",
+        .id             = 3,
+        .dev            = {
+                .platform_data  = &scif3_platform_data,
+        },
+};
+
+static struct plat_sci_port scif4_platform_data = {
+        .mapbase        = 0xff927000,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .type           = PORT_SCIF,
+        .irqs           = { 65, 65, 65, 65 },
+};
+
+static struct platform_device scif4_device = {
+        .name           = "sh-sci",
+        .id             = 4,
+        .dev            = {
+                .platform_data  = &scif4_platform_data,
+        },
+};
+
+static struct plat_sci_port scif5_platform_data = {
+        .mapbase        = 0xff928000,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .type           = PORT_SCIF,
+        .irqs           = { 66, 66, 66, 66 },
+};
+
+static struct platform_device scif5_device = {
+        .name           = "sh-sci",
+        .id             = 5,
+        .dev            = {
+                .platform_data  = &scif5_platform_data,
+        },
+};
+
+static struct plat_sci_port scif6_platform_data = {
+        .mapbase        = 0xff929000,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .type           = PORT_SCIF,
+        .irqs           = { 67, 67, 67, 67 },
+};
+
+static struct platform_device scif6_device = {
+        .name           = "sh-sci",
+        .id             = 6,
+        .dev            = {
+                .platform_data  = &scif6_platform_data,
+        },
+};
+
+static struct plat_sci_port scif7_platform_data = {
+        .mapbase        = 0xff92a000,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .type           = PORT_SCIF,
+        .irqs           = { 68, 68, 68, 68 },
+};
+
+static struct platform_device scif7_device = {
+        .name           = "sh-sci",
+        .id             = 7,
+        .dev            = {
+                .platform_data  = &scif7_platform_data,
+        },
+};
+
+static struct plat_sci_port scif8_platform_data = {
+        .mapbase        = 0xff92b000,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .type           = PORT_SCIF,
+        .irqs           = { 69, 69, 69, 69 },
+};
+
+static struct platform_device scif8_device = {
+        .name           = "sh-sci",
+        .id             = 8,
+        .dev            = {
+                .platform_data  = &scif8_platform_data,
+        },
+};
+
+static struct plat_sci_port scif9_platform_data = {
+        .mapbase        = 0xff92c000,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .type           = PORT_SCIF,
+        .irqs           = { 70, 70, 70, 70 },
 };
 
-static struct platform_device sci_device = {
+static struct platform_device scif9_device = {
         .name           = "sh-sci",
-        .id             = -1,
+        .id             = 9,
         .dev            = {
-                .platform_data  = sci_platform_data,
+                .platform_data  = &scif9_platform_data,
         },
 };
 
@@ -351,6 +437,16 @@ static struct platform_device tmu8_device = {
 };
 
 static struct platform_device *sh7770_devices[] __initdata = {
+        &scif0_device,
+        &scif1_device,
+        &scif2_device,
+        &scif3_device,
+        &scif4_device,
+        &scif5_device,
+        &scif6_device,
+        &scif7_device,
+        &scif8_device,
+        &scif9_device,
         &tmu0_device,
         &tmu1_device,
         &tmu2_device,
@@ -360,7 +456,6 @@ static struct platform_device *sh7770_devices[] __initdata = {
         &tmu6_device,
         &tmu7_device,
         &tmu8_device,
-        &sci_device,
 };
 
 static int __init sh7770_devices_setup(void)
@@ -371,6 +466,16 @@ static int __init sh7770_devices_setup(void)
 arch_initcall(sh7770_devices_setup);
 
 static struct platform_device *sh7770_early_devices[] __initdata = {
+        &scif0_device,
+        &scif1_device,
+        &scif2_device,
+        &scif3_device,
+        &scif4_device,
+        &scif5_device,
+        &scif6_device,
+        &scif7_device,
+        &scif8_device,
+        &scif9_device,
         &tmu0_device,
         &tmu1_device,
         &tmu2_device,
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7780.c b/arch/sh/kernel/cpu/sh4a/setup-sh7780.c
index 12ff56f19c5c..c310558490d5 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7780.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7780.c
@@ -15,6 +15,36 @@
 #include <linux/sh_timer.h>
 #include <asm/dma-sh.h>
 
+static struct plat_sci_port scif0_platform_data = {
+        .mapbase        = 0xffe00000,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .type           = PORT_SCIF,
+        .irqs           = { 40, 40, 40, 40 },
+};
+
+static struct platform_device scif0_device = {
+        .name           = "sh-sci",
+        .id             = 0,
+        .dev            = {
+                .platform_data  = &scif0_platform_data,
+        },
+};
+
+static struct plat_sci_port scif1_platform_data = {
+        .mapbase        = 0xffe10000,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .type           = PORT_SCIF,
+        .irqs           = { 76, 76, 76, 76 },
+};
+
+static struct platform_device scif1_device = {
+        .name           = "sh-sci",
+        .id             = 1,
+        .dev            = {
+                .platform_data  = &scif1_platform_data,
+        },
+};
+
 static struct sh_timer_config tmu0_platform_data = {
         .name = "TMU0",
         .channel_offset = 0x04,
@@ -217,30 +247,6 @@ static struct platform_device rtc_device = {
         .resource       = rtc_resources,
 };
 
-static struct plat_sci_port sci_platform_data[] = {
-        {
-                .mapbase        = 0xffe00000,
-                .flags          = UPF_BOOT_AUTOCONF,
-                .type           = PORT_SCIF,
-                .irqs           = { 40, 40, 40, 40 },
-        }, {
-                .mapbase        = 0xffe10000,
-                .flags          = UPF_BOOT_AUTOCONF,
-                .type           = PORT_SCIF,
-                .irqs           = { 76, 76, 76, 76 },
-        }, {
-                .flags = 0,
-        }
-};
-
-static struct platform_device sci_device = {
-        .name           = "sh-sci",
-        .id             = -1,
-        .dev            = {
-                .platform_data  = sci_platform_data,
-        },
-};
-
 static struct sh_dmae_pdata dma_platform_data = {
         .mode = (SHDMA_MIX_IRQ | SHDMA_DMAOR1),
 };
@@ -254,6 +260,8 @@ static struct platform_device dma_device = {
 };
 
 static struct platform_device *sh7780_devices[] __initdata = {
+        &scif0_device,
+        &scif1_device,
         &tmu0_device,
         &tmu1_device,
         &tmu2_device,
@@ -261,7 +269,6 @@ static struct platform_device *sh7780_devices[] __initdata = {
         &tmu4_device,
         &tmu5_device,
         &rtc_device,
-        &sci_device,
         &dma_device,
 };
 
@@ -271,8 +278,9 @@ static int __init sh7780_devices_setup(void)
                                     ARRAY_SIZE(sh7780_devices));
 }
 arch_initcall(sh7780_devices_setup);
-
 static struct platform_device *sh7780_early_devices[] __initdata = {
+        &scif0_device,
+        &scif1_device,
         &tmu0_device,
         &tmu1_device,
         &tmu2_device,
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7785.c b/arch/sh/kernel/cpu/sh4a/setup-sh7785.c
index 7f6c718b6c36..ef26ebda6e8b 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7785.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7785.c
@@ -16,6 +16,102 @@
 #include <linux/sh_timer.h>
 #include <asm/mmzone.h>
 
+static struct plat_sci_port scif0_platform_data = {
+        .mapbase        = 0xffea0000,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .type           = PORT_SCIF,
+        .irqs           = { 40, 40, 40, 40 },
+        .clk            = "scif_fck",
+};
+
+static struct platform_device scif0_device = {
+        .name           = "sh-sci",
+        .id             = 0,
+        .dev            = {
+                .platform_data  = &scif0_platform_data,
+        },
+};
+
+static struct plat_sci_port scif1_platform_data = {
+        .mapbase        = 0xffeb0000,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .type           = PORT_SCIF,
+        .irqs           = { 44, 44, 44, 44 },
+        .clk            = "scif_fck",
+};
+
+static struct platform_device scif1_device = {
+        .name           = "sh-sci",
+        .id             = 1,
+        .dev            = {
+                .platform_data  = &scif1_platform_data,
+        },
+};
+
+static struct plat_sci_port scif2_platform_data = {
+        .mapbase        = 0xffec0000,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .type           = PORT_SCIF,
+        .irqs           = { 60, 60, 60, 60 },
+        .clk            = "scif_fck",
+};
+
+static struct platform_device scif2_device = {
+        .name           = "sh-sci",
+        .id             = 2,
+        .dev            = {
+                .platform_data  = &scif2_platform_data,
+        },
+};
+
+static struct plat_sci_port scif3_platform_data = {
+        .mapbase        = 0xffed0000,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .type           = PORT_SCIF,
+        .irqs           = { 61, 61, 61, 61 },
+        .clk            = "scif_fck",
+};
+
+static struct platform_device scif3_device = {
+        .name           = "sh-sci",
+        .id             = 3,
+        .dev            = {
+                .platform_data  = &scif3_platform_data,
+        },
+};
+
+static struct plat_sci_port scif4_platform_data = {
+        .mapbase        = 0xffee0000,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .type           = PORT_SCIF,
+        .irqs           = { 62, 62, 62, 62 },
+        .clk            = "scif_fck",
+};
+
+static struct platform_device scif4_device = {
+        .name           = "sh-sci",
+        .id             = 4,
+        .dev            = {
+                .platform_data  = &scif4_platform_data,
+        },
+};
+
+static struct plat_sci_port scif5_platform_data = {
+        .mapbase        = 0xffef0000,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .type           = PORT_SCIF,
+        .irqs           = { 63, 63, 63, 63 },
+        .clk            = "scif_fck",
+};
+
+static struct platform_device scif5_device = {
+        .name           = "sh-sci",
+        .id             = 5,
+        .dev            = {
+                .platform_data  = &scif5_platform_data,
+        },
+};
+
 static struct sh_timer_config tmu0_platform_data = {
         .name = "TMU0",
         .channel_offset = 0x04,
@@ -198,64 +294,19 @@ static struct platform_device tmu5_device = {
         .num_resources  = ARRAY_SIZE(tmu5_resources),
 };
 
-static struct plat_sci_port sci_platform_data[] = {
-        {
-                .mapbase        = 0xffea0000,
-                .flags          = UPF_BOOT_AUTOCONF,
-                .type           = PORT_SCIF,
-                .irqs           = { 40, 40, 40, 40 },
-                .clk            = "scif_fck",
-        }, {
-                .mapbase        = 0xffeb0000,
-                .flags          = UPF_BOOT_AUTOCONF,
-                .type           = PORT_SCIF,
-                .irqs           = { 44, 44, 44, 44 },
-                .clk            = "scif_fck",
-        }, {
-                .mapbase        = 0xffec0000,
-                .flags          = UPF_BOOT_AUTOCONF,
-                .type           = PORT_SCIF,
-                .irqs           = { 60, 60, 60, 60 },
-                .clk            = "scif_fck",
-        }, {
-                .mapbase        = 0xffed0000,
-                .flags          = UPF_BOOT_AUTOCONF,
-                .type           = PORT_SCIF,
-                .irqs           = { 61, 61, 61, 61 },
-                .clk            = "scif_fck",
-        }, {
-                .mapbase        = 0xffee0000,
-                .flags          = UPF_BOOT_AUTOCONF,
-                .type           = PORT_SCIF,
-                .irqs           = { 62, 62, 62, 62 },
-                .clk            = "scif_fck",
-        }, {
-                .mapbase        = 0xffef0000,
-                .flags          = UPF_BOOT_AUTOCONF,
-                .type           = PORT_SCIF,
-                .irqs           = { 63, 63, 63, 63 },
-                .clk            = "scif_fck",
-        }, {
-                .flags = 0,
-        }
-};
-
-static struct platform_device sci_device = {
-        .name           = "sh-sci",
-        .id             = -1,
-        .dev            = {
-                .platform_data  = sci_platform_data,
-        },
-};
-
 static struct platform_device *sh7785_devices[] __initdata = {
+        &scif0_device,
+        &scif1_device,
+        &scif2_device,
+        &scif3_device,
+        &scif4_device,
+        &scif5_device,
         &tmu0_device,
         &tmu1_device,
         &tmu2_device,
         &tmu3_device,
         &tmu4_device,
         &tmu5_device,
-        &sci_device,
 };
 
 static int __init sh7785_devices_setup(void)
@@ -266,6 +317,12 @@ static int __init sh7785_devices_setup(void)
 arch_initcall(sh7785_devices_setup);
 
 static struct platform_device *sh7785_early_devices[] __initdata = {
+        &scif0_device,
+        &scif1_device,
+        &scif2_device,
+        &scif3_device,
+        &scif4_device,
+        &scif5_device,
         &tmu0_device,
         &tmu1_device,
         &tmu2_device,
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7786.c b/arch/sh/kernel/cpu/sh4a/setup-sh7786.c
index 0104a8ec5369..71673487ace0 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7786.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7786.c
@@ -23,51 +23,96 @@
 #include <linux/sh_timer.h>
 #include <asm/mmzone.h>
 
-static struct plat_sci_port sci_platform_data[] = {
-        {
-                .mapbase        = 0xffea0000,
-                .flags          = UPF_BOOT_AUTOCONF,
-                .type           = PORT_SCIF,
-                .irqs           = { 40, 41, 43, 42 },
+static struct plat_sci_port scif0_platform_data = {
+        .mapbase        = 0xffea0000,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .type           = PORT_SCIF,
+        .irqs           = { 40, 41, 43, 42 },
+};
+
+static struct platform_device scif0_device = {
+        .name           = "sh-sci",
+        .id             = 0,
+        .dev            = {
+                .platform_data  = &scif0_platform_data,
         },
-        /*
-         * The rest of these all have multiplexed IRQs
-         */
-        {
-                .mapbase        = 0xffeb0000,
-                .flags          = UPF_BOOT_AUTOCONF,
-                .type           = PORT_SCIF,
-                .irqs           = { 44, 44, 44, 44 },
-        }, {
-                .mapbase        = 0xffec0000,
-                .flags          = UPF_BOOT_AUTOCONF,
-                .type           = PORT_SCIF,
-                .irqs           = { 50, 50, 50, 50 },
-        }, {
-                .mapbase        = 0xffed0000,
-                .flags          = UPF_BOOT_AUTOCONF,
-                .type           = PORT_SCIF,
-                .irqs           = { 51, 51, 51, 51 },
-        }, {
-                .mapbase        = 0xffee0000,
-                .flags          = UPF_BOOT_AUTOCONF,
-                .type           = PORT_SCIF,
-                .irqs           = { 52, 52, 52, 52 },
-        }, {
-                .mapbase        = 0xffef0000,
-                .flags          = UPF_BOOT_AUTOCONF,
-                .type           = PORT_SCIF,
-                .irqs           = { 53, 53, 53, 53 },
-        }, {
-                .flags = 0,
-        }
 };
 
-static struct platform_device sci_device = {
+/*
+ * The rest of these all have multiplexed IRQs
+ */
+static struct plat_sci_port scif1_platform_data = {
+        .mapbase        = 0xffeb0000,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .type           = PORT_SCIF,
+        .irqs           = { 44, 44, 44, 44 },
+};
+
+static struct platform_device scif1_device = {
         .name           = "sh-sci",
-        .id             = -1,
+        .id             = 1,
+        .dev            = {
+                .platform_data  = &scif1_platform_data,
+        },
+};
+
+static struct plat_sci_port scif2_platform_data = {
+        .mapbase        = 0xffec0000,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .type           = PORT_SCIF,
+        .irqs           = { 50, 50, 50, 50 },
+};
+
+static struct platform_device scif2_device = {
+        .name           = "sh-sci",
+        .id             = 2,
+        .dev            = {
+                .platform_data  = &scif2_platform_data,
+        },
+};
+
+static struct plat_sci_port scif3_platform_data = {
+        .mapbase        = 0xffed0000,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .type           = PORT_SCIF,
+        .irqs           = { 51, 51, 51, 51 },
+};
+
+static struct platform_device scif3_device = {
+        .name           = "sh-sci",
+        .id             = 3,
+        .dev            = {
+                .platform_data  = &scif3_platform_data,
+        },
+};
+
+static struct plat_sci_port scif4_platform_data = {
+        .mapbase        = 0xffee0000,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .type           = PORT_SCIF,
+        .irqs           = { 52, 52, 52, 52 },
+};
+
+static struct platform_device scif4_device = {
+        .name           = "sh-sci",
+        .id             = 4,
+        .dev            = {
+                .platform_data  = &scif4_platform_data,
+        },
+};
+
+static struct plat_sci_port scif5_platform_data = {
+        .mapbase        = 0xffef0000,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .type           = PORT_SCIF,
+        .irqs           = { 53, 53, 53, 53 },
+};
+
+static struct platform_device scif5_device = {
+        .name           = "sh-sci",
+        .id             = 5,
         .dev            = {
-                .platform_data  = sci_platform_data,
+                .platform_data  = &scif5_platform_data,
         },
 };
 
@@ -459,6 +504,12 @@ static struct platform_device usb_ohci_device = {
 };
 
 static struct platform_device *sh7786_early_devices[] __initdata = {
+        &scif0_device,
+        &scif1_device,
+        &scif2_device,
+        &scif3_device,
+        &scif4_device,
+        &scif5_device,
         &tmu0_device,
         &tmu1_device,
         &tmu2_device,
@@ -474,7 +525,6 @@ static struct platform_device *sh7786_early_devices[] __initdata = {
 };
 
 static struct platform_device *sh7786_devices[] __initdata = {
-        &sci_device,
         &usb_ohci_device,
 };
 
diff --git a/arch/sh/kernel/cpu/sh4a/setup-shx3.c b/arch/sh/kernel/cpu/sh4a/setup-shx3.c
index c7ba9166e18a..780ba17a5599 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-shx3.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-shx3.c
@@ -24,32 +24,48 @@
  * silicon in the first place, we just refuse to deal with the port at
  * all rather than adding infrastructure to hack around it.
  */
-static struct plat_sci_port sci_platform_data[] = {
-        {
-                .mapbase        = 0xffc30000,
-                .flags          = UPF_BOOT_AUTOCONF,
-                .type           = PORT_SCIF,
-                .irqs           = { 40, 41, 43, 42 },
-        }, {
-                .mapbase        = 0xffc40000,
-                .flags          = UPF_BOOT_AUTOCONF,
-                .type           = PORT_SCIF,
-                .irqs           = { 44, 45, 47, 46 },
-        }, {
-                .mapbase        = 0xffc60000,
-                .flags          = UPF_BOOT_AUTOCONF,
-                .type           = PORT_SCIF,
-                .irqs           = { 52, 53, 55, 54 },
-        }, {
-                .flags = 0,
-        }
+static struct plat_sci_port scif0_platform_data = {
+        .mapbase        = 0xffc30000,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .type           = PORT_SCIF,
+        .irqs           = { 40, 41, 43, 42 },
+};
+
+static struct platform_device scif0_device = {
+        .name           = "sh-sci",
+        .id             = 0,
+        .dev            = {
+                .platform_data  = &scif0_platform_data,
+        },
+};
+
+static struct plat_sci_port scif1_platform_data = {
+        .mapbase        = 0xffc40000,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .type           = PORT_SCIF,
+        .irqs           = { 44, 45, 47, 46 },
+};
+
+static struct platform_device scif1_device = {
+        .name           = "sh-sci",
+        .id             = 1,
+        .dev            = {
+                .platform_data  = &scif1_platform_data,
+        },
+};
+
+static struct plat_sci_port scif2_platform_data = {
+        .mapbase        = 0xffc60000,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .type           = PORT_SCIF,
+        .irqs           = { 52, 53, 55, 54 },
 };
 
-static struct platform_device sci_device = {
+static struct platform_device scif2_device = {
         .name           = "sh-sci",
-        .id             = -1,
+        .id             = 2,
         .dev            = {
-                .platform_data  = sci_platform_data,
+                .platform_data  = &scif2_platform_data,
         },
 };
 
@@ -236,6 +252,9 @@ static struct platform_device tmu5_device = {
 };
 
 static struct platform_device *shx3_early_devices[] __initdata = {
+        &scif0_device,
+        &scif1_device,
+        &scif2_device,
         &tmu0_device,
         &tmu1_device,
         &tmu2_device,
@@ -244,21 +263,10 @@ static struct platform_device *shx3_early_devices[] __initdata = {
         &tmu5_device,
 };
 
-static struct platform_device *shx3_devices[] __initdata = {
-        &sci_device,
-};
-
 static int __init shx3_devices_setup(void)
 {
-        int ret;
-
-        ret = platform_add_devices(shx3_early_devices,
+        return platform_add_devices(shx3_early_devices,
                                    ARRAY_SIZE(shx3_early_devices));
-        if (unlikely(ret != 0))
-                return ret;
-
-        return platform_add_devices(shx3_devices,
-                                    ARRAY_SIZE(shx3_devices));
 }
 arch_initcall(shx3_devices_setup);
 
diff --git a/arch/sh/kernel/cpu/sh5/fpu.c b/arch/sh/kernel/cpu/sh5/fpu.c
index dd4f51ffb50e..4648ccee6c4d 100644
--- a/arch/sh/kernel/cpu/sh5/fpu.c
+++ b/arch/sh/kernel/cpu/sh5/fpu.c
@@ -34,7 +34,7 @@ static union sh_fpu_union init_fpuregs = {
         }
 };
 
-void save_fpu(struct task_struct *tsk, struct pt_regs *regs)
+void save_fpu(struct task_struct *tsk)
 {
         asm volatile("fst.p     %0, (0*8), fp0\n\t"
                      "fst.p     %0, (1*8), fp2\n\t"
@@ -153,7 +153,7 @@ do_fpu_state_restore(unsigned long ex, struct pt_regs *regs)
         enable_fpu();
         if (last_task_used_math != NULL)
                 /* Other processes fpu state, save away */
-                save_fpu(last_task_used_math, regs);
+                save_fpu(last_task_used_math);
 
         last_task_used_math = current;
         if (used_math()) {
diff --git a/arch/sh/kernel/cpu/sh5/setup-sh5.c b/arch/sh/kernel/cpu/sh5/setup-sh5.c
index 6a0f82f70032..e7a3c1e4b604 100644
--- a/arch/sh/kernel/cpu/sh5/setup-sh5.c
+++ b/arch/sh/kernel/cpu/sh5/setup-sh5.c
@@ -16,22 +16,18 @@
 #include <linux/sh_timer.h>
 #include <asm/addrspace.h>
 
-static struct plat_sci_port sci_platform_data[] = {
-        {
-                .mapbase        = PHYS_PERIPHERAL_BLOCK + 0x01030000,
-                .flags          = UPF_BOOT_AUTOCONF | UPF_IOREMAP,
-                .type           = PORT_SCIF,
-                .irqs           = { 39, 40, 42, 0 },
-        }, {
-                .flags = 0,
-        }
+static struct plat_sci_port scif0_platform_data = {
+        .mapbase        = PHYS_PERIPHERAL_BLOCK + 0x01030000,
+        .flags          = UPF_BOOT_AUTOCONF | UPF_IOREMAP,
+        .type           = PORT_SCIF,
+        .irqs           = { 39, 40, 42, 0 },
 };
 
-static struct platform_device sci_device = {
+static struct platform_device scif0_device = {
         .name           = "sh-sci",
-        .id             = -1,
+        .id             = 0,
         .dev            = {
-                .platform_data  = sci_platform_data,
+                .platform_data  = &scif0_platform_data,
         },
 };
 
@@ -164,13 +160,13 @@ static struct platform_device tmu2_device = {
 };
 
 static struct platform_device *sh5_early_devices[] __initdata = {
+        &scif0_device,
         &tmu0_device,
         &tmu1_device,
         &tmu2_device,
 };
 
 static struct platform_device *sh5_devices[] __initdata = {
-        &sci_device,
         &rtc_device,
 };
 
diff --git a/arch/sh/kernel/early_printk.c b/arch/sh/kernel/early_printk.c
index 81a46145ffa5..f8bb50c6e050 100644
--- a/arch/sh/kernel/early_printk.c
+++ b/arch/sh/kernel/early_printk.c
@@ -15,7 +15,6 @@
 #include <linux/io.h>
 #include <linux/delay.h>
 
-#ifdef CONFIG_SH_STANDARD_BIOS
 #include <asm/sh_bios.h>
 
 /*
@@ -57,149 +56,8 @@ static struct console bios_console = {
         .flags          = CON_PRINTBUFFER,
         .index          = -1,
 };
-#endif
 
-#ifdef CONFIG_EARLY_SCIF_CONSOLE
-#include <linux/serial_core.h>
-#include "../../../drivers/serial/sh-sci.h"
-
-#if defined(CONFIG_CPU_SUBTYPE_SH7720) || \
-    defined(CONFIG_CPU_SUBTYPE_SH7721)
-#define EPK_SCSMR_VALUE 0x000
-#define EPK_SCBRR_VALUE 0x00C
-#define EPK_FIFO_SIZE 64
-#define EPK_FIFO_BITS (0x7f00 >> 8)
-#else
-#define EPK_FIFO_SIZE 16
-#define EPK_FIFO_BITS (0x1f00 >> 8)
-#endif
-
-static struct uart_port scif_port = {
-        .type           = PORT_SCIF,
-        .mapbase        = CONFIG_EARLY_SCIF_CONSOLE_PORT,
-        .membase        = (char __iomem *)CONFIG_EARLY_SCIF_CONSOLE_PORT,
-};
-
-static void scif_sercon_putc(int c)
-{
-        while (((sci_in(&scif_port, SCFDR) & EPK_FIFO_BITS) >= EPK_FIFO_SIZE))
-                ;
-
-        sci_in(&scif_port, SCxSR);
-        sci_out(&scif_port, SCxSR, 0xf3 & ~(0x20 | 0x40));
-        sci_out(&scif_port, SCxTDR, c);
-
-        while ((sci_in(&scif_port, SCxSR) & 0x40) == 0)
-                ;
-
-        if (c == '\n')
-                scif_sercon_putc('\r');
-}
-
-static void scif_sercon_write(struct console *con, const char *s,
-                              unsigned count)
-{
-        while (count-- > 0)
-                scif_sercon_putc(*s++);
-}
-
-static int __init scif_sercon_setup(struct console *con, char *options)
-{
-        con->cflag = CREAD | HUPCL | CLOCAL | B115200 | CS8;
-
-        return 0;
-}
-
-static struct console scif_console = {
-        .name           = "sercon",
-        .write          = scif_sercon_write,
-        .setup          = scif_sercon_setup,
-        .flags          = CON_PRINTBUFFER,
-        .index          = -1,
-};
-
-#if !defined(CONFIG_SH_STANDARD_BIOS)
-#if defined(CONFIG_CPU_SUBTYPE_SH7720) || \
-    defined(CONFIG_CPU_SUBTYPE_SH7721)
-static void scif_sercon_init(char *s)
-{
-        sci_out(&scif_port, SCSCR, 0x0000);     /* clear TE and RE */
-        sci_out(&scif_port, SCFCR, 0x4006);     /* reset */
-        sci_out(&scif_port, SCSCR, 0x0000);     /* select internal clock */
-        sci_out(&scif_port, SCSMR, EPK_SCSMR_VALUE);
-        sci_out(&scif_port, SCBRR, EPK_SCBRR_VALUE);
-
-        mdelay(1);      /* wait 1-bit time */
-
-        sci_out(&scif_port, SCFCR, 0x0030);     /* TTRG=b'11 */
-        sci_out(&scif_port, SCSCR, 0x0030);     /* TE, RE */
-}
-#elif defined(CONFIG_CPU_SH4) || defined(CONFIG_CPU_SH3)
-#define DEFAULT_BAUD 115200
-/*
- * Simple SCIF init, primarily aimed at SH7750 and other similar SH-4
- * devices that aren't using sh-ipl+g.
- */
-static void scif_sercon_init(char *s)
-{
-        struct uart_port *port = &scif_port;
-        unsigned baud = DEFAULT_BAUD;
-        unsigned int status;
-        char *e;
-
-        if (*s == ',')
-                ++s;
-
-        if (*s) {
-                /* ignore ioport/device name */
-                s += strcspn(s, ",");
-                if (*s == ',')
-                        s++;
-        }
-
-        if (*s) {
-                baud = simple_strtoul(s, &e, 0);
-                if (baud == 0 || s == e)
-                        baud = DEFAULT_BAUD;
-        }
-
-        do {
-                status = sci_in(port, SCxSR);
-        } while (!(status & SCxSR_TEND(port)));
-
-        sci_out(port, SCSCR, 0);         /* TE=0, RE=0 */
-        sci_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST);
-        sci_out(port, SCSMR, 0);
-
-        /* Set baud rate */
-        sci_out(port, SCBRR, (CONFIG_SH_PCLK_FREQ + 16 * baud) /
-                (32 * baud) - 1);
-        udelay((1000000+(baud-1)) / baud); /* Wait one bit interval */
-
-        sci_out(port, SCSPTR, 0);
-        sci_out(port, SCxSR, 0x60);
-        sci_out(port, SCLSR, 0);
-
-        sci_out(port, SCFCR, 0);
-        sci_out(port, SCSCR, 0x30);      /* TE=1, RE=1 */
-}
-#endif /* defined(CONFIG_CPU_SUBTYPE_SH7720) */
-#endif /* !defined(CONFIG_SH_STANDARD_BIOS) */
-#endif /* CONFIG_EARLY_SCIF_CONSOLE */
-
-/*
- * Setup a default console, if more than one is compiled in, rely on the
- * earlyprintk= parsing to give priority.
- */
-static struct console *early_console =
-#ifdef CONFIG_SH_STANDARD_BIOS
-        &bios_console
-#elif defined(CONFIG_EARLY_SCIF_CONSOLE)
-        &scif_console
-#else
-        NULL
-#endif
-        ;
+static struct console *early_console;
 
 static int __init setup_early_printk(char *buf)
 {
@@ -211,21 +69,8 @@ static int __init setup_early_printk(char *buf)
         if (strstr(buf, "keep"))
                 keep_early = 1;
 
-#ifdef CONFIG_SH_STANDARD_BIOS
         if (!strncmp(buf, "bios", 4))
                 early_console = &bios_console;
-#endif
-#if defined(CONFIG_EARLY_SCIF_CONSOLE)
-        if (!strncmp(buf, "serial", 6)) {
-                early_console = &scif_console;
-
-#if !defined(CONFIG_SH_STANDARD_BIOS)
-#if defined(CONFIG_CPU_SH4) || defined(CONFIG_CPU_SH3)
-                scif_sercon_init(buf + 6);
-#endif
-#endif
-        }
-#endif
 
         if (likely(early_console)) {
                 if (keep_early)
diff --git a/arch/sh/kernel/ftrace.c b/arch/sh/kernel/ftrace.c
index b6f41c109beb..a48cdedc73b5 100644
--- a/arch/sh/kernel/ftrace.c
+++ b/arch/sh/kernel/ftrace.c
@@ -401,82 +401,10 @@ void prepare_ftrace_return(unsigned long *parent, unsigned long self_addr)
 #endif /* CONFIG_FUNCTION_GRAPH_TRACER */
 
 #ifdef CONFIG_FTRACE_SYSCALLS
-
-extern unsigned long __start_syscalls_metadata[];
-extern unsigned long __stop_syscalls_metadata[];
 extern unsigned long *sys_call_table;
 
-static struct syscall_metadata **syscalls_metadata;
-
-static struct syscall_metadata *find_syscall_meta(unsigned long *syscall)
-{
-        struct syscall_metadata *start;
-        struct syscall_metadata *stop;
-        char str[KSYM_SYMBOL_LEN];
-
-
-        start = (struct syscall_metadata *)__start_syscalls_metadata;
-        stop = (struct syscall_metadata *)__stop_syscalls_metadata;
-        kallsyms_lookup((unsigned long) syscall, NULL, NULL, NULL, str);
-
-        for ( ; start < stop; start++) {
-                if (start->name && !strcmp(start->name, str))
-                        return start;
-        }
-
-        return NULL;
-}
-
-struct syscall_metadata *syscall_nr_to_meta(int nr)
-{
-        if (!syscalls_metadata || nr >= FTRACE_SYSCALL_MAX || nr < 0)
-                return NULL;
-
-        return syscalls_metadata[nr];
-}
-
-int syscall_name_to_nr(char *name)
-{
-        int i;
-
-        if (!syscalls_metadata)
-                return -1;
-        for (i = 0; i < NR_syscalls; i++)
-                if (syscalls_metadata[i])
-                        if (!strcmp(syscalls_metadata[i]->name, name))
-                                return i;
-        return -1;
-}
-
-void set_syscall_enter_id(int num, int id)
-{
-        syscalls_metadata[num]->enter_id = id;
-}
-
-void set_syscall_exit_id(int num, int id)
-{
-        syscalls_metadata[num]->exit_id = id;
-}
-
-static int __init arch_init_ftrace_syscalls(void)
+unsigned long __init arch_syscall_addr(int nr)
 {
-        int i;
-        struct syscall_metadata *meta;
-        unsigned long **psys_syscall_table = &sys_call_table;
-
-        syscalls_metadata = kzalloc(sizeof(*syscalls_metadata) *
-                                        FTRACE_SYSCALL_MAX, GFP_KERNEL);
-        if (!syscalls_metadata) {
-                WARN_ON(1);
-                return -ENOMEM;
-        }
-
-        for (i = 0; i < FTRACE_SYSCALL_MAX; i++) {
-                meta = find_syscall_meta(psys_syscall_table[i]);
-                syscalls_metadata[i] = meta;
-        }
-
-        return 0;
+        return (unsigned long)sys_call_table[nr];
 }
-arch_initcall(arch_init_ftrace_syscalls);
 #endif /* CONFIG_FTRACE_SYSCALLS */
diff --git a/arch/sh/kernel/irq.c b/arch/sh/kernel/irq.c
index e1913f28f418..d2d41d046657 100644
--- a/arch/sh/kernel/irq.c
+++ b/arch/sh/kernel/irq.c
@@ -76,7 +76,7 @@ int show_interrupts(struct seq_file *p, void *v)
         if (!desc)
                 return 0;
 
-        spin_lock_irqsave(&desc->lock, flags);
+        raw_spin_lock_irqsave(&desc->lock, flags);
         for_each_online_cpu(j)
                 any_count |= kstat_irqs_cpu(i, j);
         action = desc->action;
@@ -97,7 +97,7 @@ int show_interrupts(struct seq_file *p, void *v)
 
         seq_putc(p, '\n');
 out:
-        spin_unlock_irqrestore(&desc->lock, flags);
+        raw_spin_unlock_irqrestore(&desc->lock, flags);
         return 0;
 }
 #endif
diff --git a/arch/sh/kernel/process_64.c b/arch/sh/kernel/process_64.c
index 359b8a2f4d2e..31f80c61b031 100644
--- a/arch/sh/kernel/process_64.c
+++ b/arch/sh/kernel/process_64.c
@@ -404,7 +404,7 @@ int dump_fpu(struct pt_regs *regs, elf_fpregset_t *fpu)
         if (fpvalid) {
                 if (current == last_task_used_math) {
                         enable_fpu();
-                        save_fpu(tsk, regs);
+                        save_fpu(tsk);
                         disable_fpu();
                         last_task_used_math = 0;
                         regs->sr |= SR_FD;
@@ -431,7 +431,7 @@ int copy_thread(unsigned long clone_flags, unsigned long usp,
 #ifdef CONFIG_SH_FPU
         if(last_task_used_math == current) {
                 enable_fpu();
-                save_fpu(current, regs);
+                save_fpu(current);
                 disable_fpu();
                 last_task_used_math = NULL;
                 regs->sr |= SR_FD;
diff --git a/arch/sh/kernel/ptrace_64.c b/arch/sh/kernel/ptrace_64.c
index 952da83903da..873ebdc4f98e 100644
--- a/arch/sh/kernel/ptrace_64.c
+++ b/arch/sh/kernel/ptrace_64.c
@@ -82,7 +82,7 @@ get_fpu_long(struct task_struct *task, unsigned long addr)
 
         if (last_task_used_math == task) {
                 enable_fpu();
-                save_fpu(task, regs);
+                save_fpu(task);
                 disable_fpu();
                 last_task_used_math = 0;
                 regs->sr |= SR_FD;
@@ -118,7 +118,7 @@ put_fpu_long(struct task_struct *task, unsigned long addr, unsigned long data)
                 set_stopped_child_used_math(task);
         } else if (last_task_used_math == task) {
                 enable_fpu();
-                save_fpu(task, regs);
+                save_fpu(task);
                 disable_fpu();
                 last_task_used_math = 0;
                 regs->sr |= SR_FD;
diff --git a/arch/sh/kernel/setup.c b/arch/sh/kernel/setup.c
index 5a947a2567e4..8b0e69792cf4 100644
--- a/arch/sh/kernel/setup.c
+++ b/arch/sh/kernel/setup.c
@@ -423,6 +423,9 @@ void __init setup_arch(char **cmdline_p)
 
         plat_early_device_setup();
 
+        /* Let earlyprintk output early console messages */
+        early_platform_driver_probe("earlyprintk", 1, 1);
+
         sh_mv_setup();
 
         /*
diff --git a/arch/sh/kernel/signal_64.c b/arch/sh/kernel/signal_64.c
index feb3dddd3192..ce76dbdef294 100644
--- a/arch/sh/kernel/signal_64.c
+++ b/arch/sh/kernel/signal_64.c
@@ -314,7 +314,7 @@ setup_sigcontext_fpu(struct pt_regs *regs, struct sigcontext __user *sc)
 
         if (current == last_task_used_math) {
                 enable_fpu();
-                save_fpu(current, regs);
+                save_fpu(current);
                 disable_fpu();
                 last_task_used_math = NULL;
                 regs->sr |= SR_FD;
diff --git a/arch/sh/kernel/sys_sh.c b/arch/sh/kernel/sys_sh.c
index 8aa5d1ceaf14..71399cde03b5 100644
--- a/arch/sh/kernel/sys_sh.c
+++ b/arch/sh/kernel/sys_sh.c
@@ -28,37 +28,13 @@
 #include <asm/cacheflush.h>
 #include <asm/cachectl.h>
 
-static inline long
-do_mmap2(unsigned long addr, unsigned long len, unsigned long prot,
-         unsigned long flags, int fd, unsigned long pgoff)
-{
-        int error = -EBADF;
-        struct file *file = NULL;
-
-        flags &= ~(MAP_EXECUTABLE | MAP_DENYWRITE);
-        if (!(flags & MAP_ANONYMOUS)) {
-                file = fget(fd);
-                if (!file)
-                        goto out;
-        }
-
-        down_write(&current->mm->mmap_sem);
-        error = do_mmap_pgoff(file, addr, len, prot, flags, pgoff);
-        up_write(&current->mm->mmap_sem);
-
-        if (file)
-                fput(file);
-out:
-        return error;
-}
-
 asmlinkage int old_mmap(unsigned long addr, unsigned long len,
         unsigned long prot, unsigned long flags,
         int fd, unsigned long off)
 {
         if (off & ~PAGE_MASK)
                 return -EINVAL;
-        return do_mmap2(addr, len, prot, flags, fd, off>>PAGE_SHIFT);
+        return sys_mmap_pgoff(addr, len, prot, flags, fd, off>>PAGE_SHIFT);
 }
 
 asmlinkage long sys_mmap2(unsigned long addr, unsigned long len,
@@ -74,7 +50,7 @@ asmlinkage long sys_mmap2(unsigned long addr, unsigned long len,
 
         pgoff >>= PAGE_SHIFT - 12;
 
-        return do_mmap2(addr, len, prot, flags, fd, pgoff);
+        return sys_mmap_pgoff(addr, len, prot, flags, fd, pgoff);
 }
 
 /*
diff --git a/arch/sh/kernel/syscalls_32.S b/arch/sh/kernel/syscalls_32.S
index 19fd11dd9871..4bd5a1146956 100644
--- a/arch/sh/kernel/syscalls_32.S
+++ b/arch/sh/kernel/syscalls_32.S
@@ -353,3 +353,4 @@ ENTRY(sys_call_table)
         .long sys_pwritev
         .long sys_rt_tgsigqueueinfo     /* 335 */
         .long sys_perf_event_open
+        .long sys_recvmmsg
diff --git a/arch/sh/kernel/traps_32.c b/arch/sh/kernel/traps_32.c
index 3da5a125d884..86639beac3a2 100644
--- a/arch/sh/kernel/traps_32.c
+++ b/arch/sh/kernel/traps_32.c
@@ -452,12 +452,18 @@ int handle_unaligned_access(insn_size_t instruction, struct pt_regs *regs,
         rm = regs->regs[index];
 
         /* shout about fixups */
-        if (!expected && printk_ratelimit())
-                printk(KERN_NOTICE "Fixing up unaligned %s access "
-                       "in \"%s\" pid=%d pc=0x%p ins=0x%04hx\n",
-                       user_mode(regs) ? "userspace" : "kernel",
-                       current->comm, task_pid_nr(current),
-                       (void *)regs->pc, instruction);
+        if (!expected) {
+                if (user_mode(regs) && (se_usermode & 1) && printk_ratelimit())
+                        pr_notice("Fixing up unaligned userspace access "
+                                  "in \"%s\" pid=%d pc=0x%p ins=0x%04hx\n",
+                                  current->comm, task_pid_nr(current),
+                                  (void *)regs->pc, instruction);
+                else if (se_kernmode_warn && printk_ratelimit())
+                        pr_notice("Fixing up unaligned kernel access "
+                                  "in \"%s\" pid=%d pc=0x%p ins=0x%04hx\n",
+                                  current->comm, task_pid_nr(current),
+                                  (void *)regs->pc, instruction);
+        }
 
         ret = -EFAULT;
         switch (instruction&0xF000) {
diff --git a/arch/sh/kernel/traps_64.c b/arch/sh/kernel/traps_64.c
index 75c0cbe2eda0..d86f5315a0c1 100644
--- a/arch/sh/kernel/traps_64.c
+++ b/arch/sh/kernel/traps_64.c
@@ -600,7 +600,7 @@ static int misaligned_fpu_load(struct pt_regs *regs,
                    indexed by register number. */
                 if (last_task_used_math == current) {
                         enable_fpu();
-                        save_fpu(current, regs);
+                        save_fpu(current);
                         disable_fpu();
                         last_task_used_math = NULL;
                         regs->sr |= SR_FD;
@@ -673,7 +673,7 @@ static int misaligned_fpu_store(struct pt_regs *regs,
                    indexed by register number. */
                 if (last_task_used_math == current) {
                         enable_fpu();
-                        save_fpu(current, regs);
+                        save_fpu(current);
                         disable_fpu();
                         last_task_used_math = NULL;
                         regs->sr |= SR_FD;
diff --git a/arch/sh/mm/cache-sh4.c b/arch/sh/mm/cache-sh4.c
index f36a08bf3d5c..560ddb6bc8a7 100644
--- a/arch/sh/mm/cache-sh4.c
+++ b/arch/sh/mm/cache-sh4.c
@@ -256,8 +256,7 @@ static void sh4_flush_cache_page(void *args)
                 address = (unsigned long)vaddr;
         }
 
-        if (pages_do_alias(address, phys))
-                flush_cache_one(CACHE_OC_ADDRESS_ARRAY |
+        flush_cache_one(CACHE_OC_ADDRESS_ARRAY |
                         (address & shm_align_mask), phys);
 
         if (vma->vm_flags & VM_EXEC)
diff --git a/arch/sh/mm/ioremap_32.c b/arch/sh/mm/ioremap_32.c
index a86eaa9d75a5..2141befb4f91 100644
--- a/arch/sh/mm/ioremap_32.c
+++ b/arch/sh/mm/ioremap_32.c
@@ -33,10 +33,10 @@
  * have to convert them into an offset in a page-aligned mapping, but the
  * caller shouldn't need to know that small detail.
  */
-void __iomem *__ioremap(unsigned long phys_addr, unsigned long size,
-                        unsigned long flags)
+void __iomem *__ioremap_caller(unsigned long phys_addr, unsigned long size,
+                               unsigned long flags, void *caller)
 {
-        struct vm_struct * area;
+        struct vm_struct *area;
         unsigned long offset, last_addr, addr, orig_addr;
         pgprot_t pgprot;
 
@@ -67,7 +67,7 @@ void __iomem *__ioremap(unsigned long phys_addr, unsigned long size,
         /*
          * Ok, go for it..
          */
-        area = get_vm_area(size, VM_IOREMAP);
+        area = get_vm_area_caller(size, VM_IOREMAP, caller);
         if (!area)
                 return NULL;
         area->phys_addr = phys_addr;
@@ -103,7 +103,7 @@ void __iomem *__ioremap(unsigned long phys_addr, unsigned long size,
 
         return (void __iomem *)(offset + (char *)orig_addr);
 }
-EXPORT_SYMBOL(__ioremap);
+EXPORT_SYMBOL(__ioremap_caller);
 
 void __iounmap(void __iomem *addr)
 {
diff --git a/arch/sh/mm/ioremap_64.c b/arch/sh/mm/ioremap_64.c
index b16843d02b76..ef434657d428 100644
--- a/arch/sh/mm/ioremap_64.c
+++ b/arch/sh/mm/ioremap_64.c
@@ -258,15 +258,15 @@ static void shmedia_unmapioaddr(unsigned long vaddr)
         pte_clear(&init_mm, vaddr, ptep);
 }
 
-void __iomem *__ioremap(unsigned long offset, unsigned long size,
-                        unsigned long flags)
+void __iomem *__ioremap_caller(unsigned long offset, unsigned long size,
+                               unsigned long flags, void *caller)
 {
         char name[14];
 
         sprintf(name, "phys_%08x", (u32)offset);
         return shmedia_alloc_io(offset, size, name, flags);
 }
-EXPORT_SYMBOL(__ioremap);
+EXPORT_SYMBOL(__ioremap_caller);
 
 void __iounmap(void __iomem *virtual)
 {
diff --git a/arch/sh/mm/mmap.c b/arch/sh/mm/mmap.c
index d2984fa42d3d..afeb710ec5c3 100644
--- a/arch/sh/mm/mmap.c
+++ b/arch/sh/mm/mmap.c
@@ -54,7 +54,8 @@ unsigned long arch_get_unmapped_area(struct file *filp, unsigned long addr,
                 /* We do not accept a shared mapping if it would violate
                  * cache aliasing constraints.
                  */
-                if ((flags & MAP_SHARED) && (addr & shm_align_mask))
+                if ((flags & MAP_SHARED) &&
+                    ((addr - (pgoff << PAGE_SHIFT)) & shm_align_mask))
                         return -EINVAL;
                 return addr;
         }
diff --git a/arch/sh/mm/numa.c b/arch/sh/mm/numa.c
index 6c524446c0f6..422e92721878 100644
--- a/arch/sh/mm/numa.c
+++ b/arch/sh/mm/numa.c
@@ -28,7 +28,7 @@ void __init setup_memory(void)
 {
         unsigned long free_pfn = PFN_UP(__pa(_end));
         u64 base = min_low_pfn << PAGE_SHIFT;
-        u64 size = (max_low_pfn << PAGE_SHIFT) - min_low_pfn;
+        u64 size = (max_low_pfn << PAGE_SHIFT) - base;
 
         lmb_add(base, size);
 
@@ -38,6 +38,15 @@ void __init setup_memory(void)
                     (__MEMORY_START + CONFIG_ZERO_PAGE_OFFSET));
 
         /*
+         * Reserve physical pages below CONFIG_ZERO_PAGE_OFFSET.
+         */
+        if (CONFIG_ZERO_PAGE_OFFSET != 0)
+                lmb_reserve(__MEMORY_START, CONFIG_ZERO_PAGE_OFFSET);
+
+        lmb_analyze();
+        lmb_dump_all();
+
+        /*
          * Node 0 sets up its pgdat at the first available pfn,
          * and bumps it up before setting up the bootmem allocator.
          */
@@ -71,7 +80,7 @@ void __init setup_bootmem_node(int nid, unsigned long start, unsigned long end)
 
         /* Node-local pgdat */
         NODE_DATA(nid) = __va(lmb_alloc_base(sizeof(struct pglist_data),
-                                             SMP_CACHE_BYTES, end_pfn));
+                                             SMP_CACHE_BYTES, end));
         memset(NODE_DATA(nid), 0, sizeof(struct pglist_data));
 
         NODE_DATA(nid)->bdata = &bootmem_node_data[nid];
@@ -81,7 +90,7 @@ void __init setup_bootmem_node(int nid, unsigned long start, unsigned long end)
         /* Node-local bootmap */
         bootmap_pages = bootmem_bootmap_pages(end_pfn - start_pfn);
         bootmem_paddr = lmb_alloc_base(bootmap_pages << PAGE_SHIFT,
-                                       PAGE_SIZE, end_pfn);
+                                       PAGE_SIZE, end);
         init_bootmem_node(NODE_DATA(nid), bootmem_paddr >> PAGE_SHIFT,
                           start_pfn, end_pfn);
 
diff --git a/arch/sh/tools/Makefile b/arch/sh/tools/Makefile
index 567516b58acc..558a56bcc7cf 100644
--- a/arch/sh/tools/Makefile
+++ b/arch/sh/tools/Makefile
@@ -10,7 +10,7 @@
 # Shamelessly cloned from ARM.
 #
 
-include/asm-sh/machtypes.h: $(src)/gen-mach-types $(src)/mach-types
+include/generated/machtypes.h: $(src)/gen-mach-types $(src)/mach-types
         @echo '  Generating $@'
-        $(Q)if [ ! -d include/asm-sh ]; then mkdir -p include/asm-sh; fi
+        $(Q)mkdir -p $(dir $@)
         $(Q)$(AWK) -f $^ > $@ || { rm -f $@; /bin/false; }
diff --git a/arch/sh/tools/gen-mach-types b/arch/sh/tools/gen-mach-types
index 65161e368353..f5ff7c5d8913 100644
--- a/arch/sh/tools/gen-mach-types
+++ b/arch/sh/tools/gen-mach-types
@@ -1,6 +1,6 @@
 #!/bin/awk
 #
-# Awk script to generate include/asm-sh/machtypes.h
+# Awk script to generate include/generated/machtypes.h
 # Heavily based on arch/arm/tools/gen-mach-types
 #
 BEGIN   { nr = 0 }
diff --git a/arch/sparc/Kconfig b/arch/sparc/Kconfig
index 33ac1a9ac881..108197ac0d56 100644
--- a/arch/sparc/Kconfig
+++ b/arch/sparc/Kconfig
@@ -43,6 +43,7 @@ config SPARC64
         select HAVE_SYSCALL_WRAPPERS
         select HAVE_DYNAMIC_FTRACE
         select HAVE_FTRACE_MCOUNT_RECORD
+        select HAVE_SYSCALL_TRACEPOINTS
         select USE_GENERIC_SMP_HELPERS if SMP
         select RTC_DRV_CMOS
         select RTC_DRV_BQ4802
diff --git a/arch/sparc/Kconfig.debug b/arch/sparc/Kconfig.debug
index 90d5fe223a74..9d3c889718ac 100644
--- a/arch/sparc/Kconfig.debug
+++ b/arch/sparc/Kconfig.debug
@@ -33,4 +33,18 @@ config FRAME_POINTER
         depends on MCOUNT
         default y
 
+config DEBUG_STRICT_USER_COPY_CHECKS
+        bool "Strict copy size checks"
+        depends on DEBUG_KERNEL && !TRACE_BRANCH_PROFILING
+        ---help---
+          Enabling this option turns a certain set of sanity checks for user
+          copy operations into compile time failures.
+
+          The copy_from_user() etc checks are there to help test if there
+          are sufficient security checks on the length argument of
+          the copy operation, by having gcc prove that the argument is
+          within bounds.
+
+          If unsure, or if you run an older (pre 4.4) gcc, say N.
+
 endmenu
diff --git a/arch/sparc/include/asm/asm-offsets.h b/arch/sparc/include/asm/asm-offsets.h
new file mode 100644
index 000000000000..d370ee36a182
--- /dev/null
+++ b/arch/sparc/include/asm/asm-offsets.h
@@ -0,0 +1 @@
+#include <generated/asm-offsets.h>
diff --git a/arch/sparc/include/asm/elf_32.h b/arch/sparc/include/asm/elf_32.h
index 381a1b5256d6..4269ca6ad18a 100644
--- a/arch/sparc/include/asm/elf_32.h
+++ b/arch/sparc/include/asm/elf_32.h
@@ -104,8 +104,6 @@ typedef struct {
 #define ELF_CLASS       ELFCLASS32
 #define ELF_DATA        ELFDATA2MSB
 
-#define USE_ELF_CORE_DUMP
-
 #define ELF_EXEC_PAGESIZE       4096
 
 
diff --git a/arch/sparc/include/asm/elf_64.h b/arch/sparc/include/asm/elf_64.h
index d42e393078c4..ff66bb88537b 100644
--- a/arch/sparc/include/asm/elf_64.h
+++ b/arch/sparc/include/asm/elf_64.h
@@ -152,7 +152,6 @@ typedef struct {
                                          (x)->e_machine == EM_SPARC32PLUS)
 #define compat_start_thread             start_thread32
 
-#define USE_ELF_CORE_DUMP
 #define ELF_EXEC_PAGESIZE       PAGE_SIZE
 
 /* This is the location that an ET_DYN program is loaded if exec'ed.  Typical
diff --git a/arch/sparc/include/asm/fcntl.h b/arch/sparc/include/asm/fcntl.h
index d4d9c9d852c3..38f37b333cc7 100644
--- a/arch/sparc/include/asm/fcntl.h
+++ b/arch/sparc/include/asm/fcntl.h
@@ -1,14 +1,12 @@
 #ifndef _SPARC_FCNTL_H
 #define _SPARC_FCNTL_H
 
-/* open/fcntl - O_SYNC is only implemented on blocks devices and on files
-   located on an ext2 file system */
 #define O_APPEND        0x0008
 #define FASYNC          0x0040  /* fcntl, for BSD compatibility */
 #define O_CREAT         0x0200  /* not fcntl */
 #define O_TRUNC         0x0400  /* not fcntl */
 #define O_EXCL          0x0800  /* not fcntl */
-#define O_SYNC          0x2000
+#define O_DSYNC         0x2000  /* used to be O_SYNC, see below */
 #define O_NONBLOCK      0x4000
 #if defined(__sparc__) && defined(__arch64__)
 #define O_NDELAY        0x0004
@@ -20,6 +18,21 @@
 #define O_DIRECT        0x100000 /* direct disk access hint */
 #define O_NOATIME       0x200000
 #define O_CLOEXEC       0x400000
+/*
+ * Before Linux 2.6.33 only O_DSYNC semantics were implemented, but using
+ * the O_SYNC flag.  We continue to use the existing numerical value
+ * for O_DSYNC semantics now, but using the correct symbolic name for it.
+ * This new value is used to request true Posix O_SYNC semantics.  It is
+ * defined in this strange way to make sure applications compiled against
+ * new headers get at least O_DSYNC semantics on older kernels.
+ *
+ * This has the nice side-effect that we can simply test for O_DSYNC
+ * wherever we do not care if O_DSYNC or O_SYNC is used.
+ *
+ * Note: __O_SYNC must never be used directly.
+ */
+#define __O_SYNC        0x800000
+#define O_SYNC          (__O_SYNC|O_DSYNC)
 
 #define F_GETOWN        5       /*  for sockets. */
 #define F_SETOWN        6       /*  for sockets. */
diff --git a/arch/sparc/include/asm/pci_64.h b/arch/sparc/include/asm/pci_64.h
index b63e51c3c3ee..b0576df6ec83 100644
--- a/arch/sparc/include/asm/pci_64.h
+++ b/arch/sparc/include/asm/pci_64.h
@@ -16,8 +16,6 @@
 
 #define PCI_IRQ_NONE            0xffffffff
 
-#define PCI_CACHE_LINE_BYTES    64
-
 static inline void pcibios_set_master(struct pci_dev *dev)
 {
         /* No special bus mastering setup handling */
diff --git a/arch/sparc/include/asm/spinlock_32.h b/arch/sparc/include/asm/spinlock_32.h
index 857630cff636..7f9b9dba38a6 100644
--- a/arch/sparc/include/asm/spinlock_32.h
+++ b/arch/sparc/include/asm/spinlock_32.h
@@ -10,12 +10,12 @@
 
 #include <asm/psr.h>
 
-#define __raw_spin_is_locked(lock) (*((volatile unsigned char *)(lock)) != 0)
+#define arch_spin_is_locked(lock) (*((volatile unsigned char *)(lock)) != 0)
 
-#define __raw_spin_unlock_wait(lock) \
-        do { while (__raw_spin_is_locked(lock)) cpu_relax(); } while (0)
+#define arch_spin_unlock_wait(lock) \
+        do { while (arch_spin_is_locked(lock)) cpu_relax(); } while (0)
 
-static inline void __raw_spin_lock(raw_spinlock_t *lock)
+static inline void arch_spin_lock(arch_spinlock_t *lock)
 {
         __asm__ __volatile__(
         "\n1:\n\t"
@@ -35,7 +35,7 @@ static inline void __raw_spin_lock(raw_spinlock_t *lock)
         : "g2", "memory", "cc");
 }
 
-static inline int __raw_spin_trylock(raw_spinlock_t *lock)
+static inline int arch_spin_trylock(arch_spinlock_t *lock)
 {
         unsigned int result;
         __asm__ __volatile__("ldstub [%1], %0"
@@ -45,7 +45,7 @@ static inline int __raw_spin_trylock(raw_spinlock_t *lock)
         return (result == 0);
 }
 
-static inline void __raw_spin_unlock(raw_spinlock_t *lock)
+static inline void arch_spin_unlock(arch_spinlock_t *lock)
 {
         __asm__ __volatile__("stb %%g0, [%0]" : : "r" (lock) : "memory");
 }
@@ -65,7 +65,7 @@ static inline void __raw_spin_unlock(raw_spinlock_t *lock)
  * Sort of like atomic_t's on Sparc, but even more clever.
  *
  *      ------------------------------------
- *      | 24-bit counter           | wlock |  raw_rwlock_t
+ *      | 24-bit counter           | wlock |  arch_rwlock_t
  *      ------------------------------------
  *       31                       8 7     0
  *
@@ -76,9 +76,9 @@ static inline void __raw_spin_unlock(raw_spinlock_t *lock)
  *
  * Unfortunately this scheme limits us to ~16,000,000 cpus.
  */
-static inline void arch_read_lock(raw_rwlock_t *rw)
+static inline void __arch_read_lock(arch_rwlock_t *rw)
 {
-        register raw_rwlock_t *lp asm("g1");
+        register arch_rwlock_t *lp asm("g1");
         lp = rw;
         __asm__ __volatile__(
         "mov    %%o7, %%g4\n\t"
@@ -89,16 +89,16 @@ static inline void arch_read_lock(raw_rwlock_t *rw)
         : "g2", "g4", "memory", "cc");
 }
 
-#define __raw_read_lock(lock) \
+#define arch_read_lock(lock) \
 do {    unsigned long flags; \
         local_irq_save(flags); \
-        arch_read_lock(lock); \
+        __arch_read_lock(lock); \
         local_irq_restore(flags); \
 } while(0)
 
-static inline void arch_read_unlock(raw_rwlock_t *rw)
+static inline void __arch_read_unlock(arch_rwlock_t *rw)
 {
-        register raw_rwlock_t *lp asm("g1");
+        register arch_rwlock_t *lp asm("g1");
         lp = rw;
         __asm__ __volatile__(
         "mov    %%o7, %%g4\n\t"
@@ -109,16 +109,16 @@ static inline void arch_read_unlock(raw_rwlock_t *rw)
         : "g2", "g4", "memory", "cc");
 }
 
-#define __raw_read_unlock(lock) \
+#define arch_read_unlock(lock) \
 do {    unsigned long flags; \
         local_irq_save(flags); \
-        arch_read_unlock(lock); \
+        __arch_read_unlock(lock); \
         local_irq_restore(flags); \
 } while(0)
 
-static inline void __raw_write_lock(raw_rwlock_t *rw)
+static inline void arch_write_lock(arch_rwlock_t *rw)
 {
-        register raw_rwlock_t *lp asm("g1");
+        register arch_rwlock_t *lp asm("g1");
         lp = rw;
         __asm__ __volatile__(
         "mov    %%o7, %%g4\n\t"
@@ -130,7 +130,7 @@ static inline void __raw_write_lock(raw_rwlock_t *rw)
         *(volatile __u32 *)&lp->lock = ~0U;
 }
 
-static inline int __raw_write_trylock(raw_rwlock_t *rw)
+static inline int arch_write_trylock(arch_rwlock_t *rw)
 {
         unsigned int val;
 
@@ -150,9 +150,9 @@ static inline int __raw_write_trylock(raw_rwlock_t *rw)
         return (val == 0);
 }
 
-static inline int arch_read_trylock(raw_rwlock_t *rw)
+static inline int __arch_read_trylock(arch_rwlock_t *rw)
 {
-        register raw_rwlock_t *lp asm("g1");
+        register arch_rwlock_t *lp asm("g1");
         register int res asm("o0");
         lp = rw;
         __asm__ __volatile__(
@@ -165,27 +165,27 @@ static inline int arch_read_trylock(raw_rwlock_t *rw)
         return res;
 }
 
-#define __raw_read_trylock(lock) \
+#define arch_read_trylock(lock) \
 ({      unsigned long flags; \
         int res; \
         local_irq_save(flags); \
-        res = arch_read_trylock(lock); \
+        res = __arch_read_trylock(lock); \
         local_irq_restore(flags); \
         res; \
 })
 
-#define __raw_write_unlock(rw)  do { (rw)->lock = 0; } while(0)
+#define arch_write_unlock(rw)   do { (rw)->lock = 0; } while(0)
 
-#define __raw_spin_lock_flags(lock, flags) __raw_spin_lock(lock)
-#define __raw_read_lock_flags(rw, flags)   __raw_read_lock(rw)
-#define __raw_write_lock_flags(rw, flags)  __raw_write_lock(rw)
+#define arch_spin_lock_flags(lock, flags) arch_spin_lock(lock)
+#define arch_read_lock_flags(rw, flags)   arch_read_lock(rw)
+#define arch_write_lock_flags(rw, flags)  arch_write_lock(rw)
 
-#define _raw_spin_relax(lock)   cpu_relax()
-#define _raw_read_relax(lock)   cpu_relax()
-#define _raw_write_relax(lock)  cpu_relax()
+#define arch_spin_relax(lock)   cpu_relax()
+#define arch_read_relax(lock)   cpu_relax()
+#define arch_write_relax(lock)  cpu_relax()
 
-#define __raw_read_can_lock(rw) (!((rw)->lock & 0xff))
-#define __raw_write_can_lock(rw) (!(rw)->lock)
+#define arch_read_can_lock(rw) (!((rw)->lock & 0xff))
+#define arch_write_can_lock(rw) (!(rw)->lock)
 
 #endif /* !(__ASSEMBLY__) */
 
diff --git a/arch/sparc/include/asm/spinlock_64.h b/arch/sparc/include/asm/spinlock_64.h
index 43e514783582..073936a8b275 100644
--- a/arch/sparc/include/asm/spinlock_64.h
+++ b/arch/sparc/include/asm/spinlock_64.h
@@ -21,13 +21,13 @@
  * the spinner sections must be pre-V9 branches.
  */
 
-#define __raw_spin_is_locked(lp)        ((lp)->lock != 0)
+#define arch_spin_is_locked(lp) ((lp)->lock != 0)
 
-#define __raw_spin_unlock_wait(lp)      \
+#define arch_spin_unlock_wait(lp)       \
         do {    rmb();                  \
         } while((lp)->lock)
 
-static inline void __raw_spin_lock(raw_spinlock_t *lock)
+static inline void arch_spin_lock(arch_spinlock_t *lock)
 {
         unsigned long tmp;
 
@@ -46,7 +46,7 @@ static inline void __raw_spin_lock(raw_spinlock_t *lock)
         : "memory");
 }
 
-static inline int __raw_spin_trylock(raw_spinlock_t *lock)
+static inline int arch_spin_trylock(arch_spinlock_t *lock)
 {
         unsigned long result;
 
@@ -59,7 +59,7 @@ static inline int __raw_spin_trylock(raw_spinlock_t *lock)
         return (result == 0UL);
 }
 
-static inline void __raw_spin_unlock(raw_spinlock_t *lock)
+static inline void arch_spin_unlock(arch_spinlock_t *lock)
 {
         __asm__ __volatile__(
 "       stb             %%g0, [%0]"
@@ -68,7 +68,7 @@ static inline void __raw_spin_unlock(raw_spinlock_t *lock)
         : "memory");
 }
 
-static inline void __raw_spin_lock_flags(raw_spinlock_t *lock, unsigned long flags)
+static inline void arch_spin_lock_flags(arch_spinlock_t *lock, unsigned long flags)
 {
         unsigned long tmp1, tmp2;
 
@@ -92,7 +92,7 @@ static inline void __raw_spin_lock_flags(raw_spinlock_t *lock, unsigned long fla
 
 /* Multi-reader locks, these are much saner than the 32-bit Sparc ones... */
 
-static void inline arch_read_lock(raw_rwlock_t *lock)
+static void inline arch_read_lock(arch_rwlock_t *lock)
 {
         unsigned long tmp1, tmp2;
 
@@ -115,7 +115,7 @@ static void inline arch_read_lock(raw_rwlock_t *lock)
         : "memory");
 }
 
-static int inline arch_read_trylock(raw_rwlock_t *lock)
+static int inline arch_read_trylock(arch_rwlock_t *lock)
 {
         int tmp1, tmp2;
 
@@ -136,7 +136,7 @@ static int inline arch_read_trylock(raw_rwlock_t *lock)
         return tmp1;
 }
 
-static void inline arch_read_unlock(raw_rwlock_t *lock)
+static void inline arch_read_unlock(arch_rwlock_t *lock)
 {
         unsigned long tmp1, tmp2;
 
@@ -152,7 +152,7 @@ static void inline arch_read_unlock(raw_rwlock_t *lock)
         : "memory");
 }
 
-static void inline arch_write_lock(raw_rwlock_t *lock)
+static void inline arch_write_lock(arch_rwlock_t *lock)
 {
         unsigned long mask, tmp1, tmp2;
 
@@ -177,7 +177,7 @@ static void inline arch_write_lock(raw_rwlock_t *lock)
         : "memory");
 }
 
-static void inline arch_write_unlock(raw_rwlock_t *lock)
+static void inline arch_write_unlock(arch_rwlock_t *lock)
 {
         __asm__ __volatile__(
 "       stw             %%g0, [%0]"
@@ -186,7 +186,7 @@ static void inline arch_write_unlock(raw_rwlock_t *lock)
         : "memory");
 }
 
-static int inline arch_write_trylock(raw_rwlock_t *lock)
+static int inline arch_write_trylock(arch_rwlock_t *lock)
 {
         unsigned long mask, tmp1, tmp2, result;
 
@@ -210,21 +210,21 @@ static int inline arch_write_trylock(raw_rwlock_t *lock)
         return result;
 }
 
-#define __raw_read_lock(p)      arch_read_lock(p)
-#define __raw_read_lock_flags(p, f) arch_read_lock(p)
-#define __raw_read_trylock(p)   arch_read_trylock(p)
-#define __raw_read_unlock(p)    arch_read_unlock(p)
-#define __raw_write_lock(p)     arch_write_lock(p)
-#define __raw_write_lock_flags(p, f) arch_write_lock(p)
-#define __raw_write_unlock(p)   arch_write_unlock(p)
-#define __raw_write_trylock(p)  arch_write_trylock(p)
-
-#define __raw_read_can_lock(rw)         (!((rw)->lock & 0x80000000UL))
-#define __raw_write_can_lock(rw)        (!(rw)->lock)
-
-#define _raw_spin_relax(lock)   cpu_relax()
-#define _raw_read_relax(lock)   cpu_relax()
-#define _raw_write_relax(lock)  cpu_relax()
+#define arch_read_lock(p)       arch_read_lock(p)
+#define arch_read_lock_flags(p, f) arch_read_lock(p)
+#define arch_read_trylock(p)    arch_read_trylock(p)
+#define arch_read_unlock(p)     arch_read_unlock(p)
+#define arch_write_lock(p)      arch_write_lock(p)
+#define arch_write_lock_flags(p, f) arch_write_lock(p)
+#define arch_write_unlock(p)    arch_write_unlock(p)
+#define arch_write_trylock(p)   arch_write_trylock(p)
+
+#define arch_read_can_lock(rw)          (!((rw)->lock & 0x80000000UL))
+#define arch_write_can_lock(rw) (!(rw)->lock)
+
+#define arch_spin_relax(lock)   cpu_relax()
+#define arch_read_relax(lock)   cpu_relax()
+#define arch_write_relax(lock)  cpu_relax()
 
 #endif /* !(__ASSEMBLY__) */
 
diff --git a/arch/sparc/include/asm/spinlock_types.h b/arch/sparc/include/asm/spinlock_types.h
index 37cbe01c585b..9c454fdeaad8 100644
--- a/arch/sparc/include/asm/spinlock_types.h
+++ b/arch/sparc/include/asm/spinlock_types.h
@@ -7,14 +7,14 @@
 
 typedef struct {
         volatile unsigned char lock;
-} raw_spinlock_t;
+} arch_spinlock_t;
 
-#define __RAW_SPIN_LOCK_UNLOCKED        { 0 }
+#define __ARCH_SPIN_LOCK_UNLOCKED       { 0 }
 
 typedef struct {
         volatile unsigned int lock;
-} raw_rwlock_t;
+} arch_rwlock_t;
 
-#define __RAW_RW_LOCK_UNLOCKED          { 0 }
+#define __ARCH_RW_LOCK_UNLOCKED         { 0 }
 
 #endif
diff --git a/arch/sparc/include/asm/string_32.h b/arch/sparc/include/asm/string_32.h
index 6c5fddb7e6b5..edf196ee4ef8 100644
--- a/arch/sparc/include/asm/string_32.h
+++ b/arch/sparc/include/asm/string_32.h
@@ -16,8 +16,6 @@
 #ifdef __KERNEL__
 
 extern void __memmove(void *,const void *,__kernel_size_t);
-extern __kernel_size_t __memcpy(void *,const void *,__kernel_size_t);
-extern __kernel_size_t __memset(void *,int,__kernel_size_t);
 
 #ifndef EXPORT_SYMTAB_STROPS
 
@@ -32,82 +30,10 @@ extern __kernel_size_t __memset(void *,int,__kernel_size_t);
 })
 
 #define __HAVE_ARCH_MEMCPY
-
-static inline void *__constant_memcpy(void *to, const void *from, __kernel_size_t n)
-{
-        extern void __copy_1page(void *, const void *);
-
-        if(n <= 32) {
-                __builtin_memcpy(to, from, n);
-        } else if (((unsigned int) to & 7) != 0) {
-                /* Destination is not aligned on the double-word boundary */
-                __memcpy(to, from, n);
-        } else {
-                switch(n) {
-                case PAGE_SIZE:
-                        __copy_1page(to, from);
-                        break;
-                default:
-                        __memcpy(to, from, n);
-                        break;
-                }
-        }
-        return to;
-}
-
-static inline void *__nonconstant_memcpy(void *to, const void *from, __kernel_size_t n)
-{
-        __memcpy(to, from, n);
-        return to;
-}
-
-#undef memcpy
-#define memcpy(t, f, n) \
-(__builtin_constant_p(n) ? \
- __constant_memcpy((t),(f),(n)) : \
- __nonconstant_memcpy((t),(f),(n)))
+#define memcpy(t, f, n) __builtin_memcpy(t, f, n)
 
 #define __HAVE_ARCH_MEMSET
-
-static inline void *__constant_c_and_count_memset(void *s, char c, __kernel_size_t count)
-{
-        extern void bzero_1page(void *);
-        extern __kernel_size_t __bzero(void *, __kernel_size_t);
-
-        if(!c) {
-                if(count == PAGE_SIZE)
-                        bzero_1page(s);
-                else
-                        __bzero(s, count);
-        } else {
-                __memset(s, c, count);
-        }
-        return s;
-}
-
-static inline void *__constant_c_memset(void *s, char c, __kernel_size_t count)
-{
-        extern __kernel_size_t __bzero(void *, __kernel_size_t);
-
-        if(!c)
-                __bzero(s, count);
-        else
-                __memset(s, c, count);
-        return s;
-}
-
-static inline void *__nonconstant_memset(void *s, char c, __kernel_size_t count)
-{
-        __memset(s, c, count);
-        return s;
-}
-
-#undef memset
-#define memset(s, c, count) \
-(__builtin_constant_p(c) ? (__builtin_constant_p(count) ? \
-                            __constant_c_and_count_memset((s), (c), (count)) : \
-                            __constant_c_memset((s), (c), (count))) \
-                          : __nonconstant_memset((s), (c), (count)))
+#define memset(s, c, count) __builtin_memset(s, c, count)
 
 #define __HAVE_ARCH_MEMSCAN
 
diff --git a/arch/sparc/include/asm/string_64.h b/arch/sparc/include/asm/string_64.h
index 43161f2d17eb..9623bc213158 100644
--- a/arch/sparc/include/asm/string_64.h
+++ b/arch/sparc/include/asm/string_64.h
@@ -15,8 +15,6 @@
 
 #include <asm/asi.h>
 
-extern void *__memset(void *,int,__kernel_size_t);
-
 #ifndef EXPORT_SYMTAB_STROPS
 
 /* First the mem*() things. */
@@ -24,29 +22,10 @@ extern void *__memset(void *,int,__kernel_size_t);
 extern void *memmove(void *, const void *, __kernel_size_t);
 
 #define __HAVE_ARCH_MEMCPY
-extern void *memcpy(void *, const void *, __kernel_size_t);
+#define memcpy(t, f, n) __builtin_memcpy(t, f, n)
 
 #define __HAVE_ARCH_MEMSET
-extern void *__builtin_memset(void *,int,__kernel_size_t);
-
-static inline void *__constant_memset(void *s, int c, __kernel_size_t count)
-{
-        extern __kernel_size_t __bzero(void *, __kernel_size_t);
-
-        if (!c) {
-                __bzero(s, count);
-                return s;
-        } else
-                return __memset(s, c, count);
-}
-
-#undef memset
-#define memset(s, c, count) \
-((__builtin_constant_p(count) && (count) <= 32) ? \
- __builtin_memset((s), (c), (count)) : \
- (__builtin_constant_p(c) ? \
-  __constant_memset((s), (c), (count)) : \
-  __memset((s), (c), (count))))
+#define memset(s, c, count) __builtin_memset(s, c, count)
 
 #define __HAVE_ARCH_MEMSCAN
 
diff --git a/arch/sparc/include/asm/thread_info_64.h b/arch/sparc/include/asm/thread_info_64.h
index 1b45a7bbe407..7257ebb8f394 100644
--- a/arch/sparc/include/asm/thread_info_64.h
+++ b/arch/sparc/include/asm/thread_info_64.h
@@ -227,6 +227,7 @@ register struct thread_info *current_thread_info_reg asm("g6");
 /* flag bit 8 is available */
 #define TIF_SECCOMP             9       /* secure computing */
 #define TIF_SYSCALL_AUDIT       10      /* syscall auditing active */
+#define TIF_SYSCALL_TRACEPOINT  11      /* syscall tracepoint instrumentation */
 /* flag bit 11 is available */
 /* NOTE: Thread flags >= 12 should be ones we have no interest
  *       in using in assembly, else we can't use the mask as
@@ -246,6 +247,7 @@ register struct thread_info *current_thread_info_reg asm("g6");
 #define _TIF_32BIT              (1<<TIF_32BIT)
 #define _TIF_SECCOMP            (1<<TIF_SECCOMP)
 #define _TIF_SYSCALL_AUDIT      (1<<TIF_SYSCALL_AUDIT)
+#define _TIF_SYSCALL_TRACEPOINT (1<<TIF_SYSCALL_TRACEPOINT)
 #define _TIF_ABI_PENDING        (1<<TIF_ABI_PENDING)
 #define _TIF_POLLING_NRFLAG     (1<<TIF_POLLING_NRFLAG)
 #define _TIF_FREEZE             (1<<TIF_FREEZE)
diff --git a/arch/sparc/include/asm/uaccess_32.h b/arch/sparc/include/asm/uaccess_32.h
index 8303ac481034..489d2ba92bcb 100644
--- a/arch/sparc/include/asm/uaccess_32.h
+++ b/arch/sparc/include/asm/uaccess_32.h
@@ -260,8 +260,23 @@ static inline unsigned long __copy_to_user(void __user *to, const void *from, un
         return __copy_user(to, (__force void __user *) from, n);
 }
 
+extern void copy_from_user_overflow(void)
+#ifdef CONFIG_DEBUG_STRICT_USER_COPY_CHECKS
+        __compiletime_error("copy_from_user() buffer size is not provably correct")
+#else
+        __compiletime_warning("copy_from_user() buffer size is not provably correct")
+#endif
+;
+
 static inline unsigned long copy_from_user(void *to, const void __user *from, unsigned long n)
 {
+        int sz = __compiletime_object_size(to);
+
+        if (unlikely(sz != -1 && sz < n)) {
+                copy_from_user_overflow();
+                return -EFAULT;
+        }
+
         if (n && __access_ok((unsigned long) from, n))
                 return __copy_user((__force void __user *) to, from, n);
         else
diff --git a/arch/sparc/include/asm/uaccess_64.h b/arch/sparc/include/asm/uaccess_64.h
index 9ea271e19c70..dbc141660994 100644
--- a/arch/sparc/include/asm/uaccess_64.h
+++ b/arch/sparc/include/asm/uaccess_64.h
@@ -6,6 +6,7 @@
  */
 
 #ifdef __KERNEL__
+#include <linux/errno.h>
 #include <linux/compiler.h>
 #include <linux/string.h>
 #include <linux/thread_info.h>
@@ -204,6 +205,14 @@ __asm__ __volatile__(							\
 
 extern int __get_user_bad(void);
 
+extern void copy_from_user_overflow(void)
+#ifdef CONFIG_DEBUG_STRICT_USER_COPY_CHECKS
+        __compiletime_error("copy_from_user() buffer size is not provably correct")
+#else
+        __compiletime_warning("copy_from_user() buffer size is not provably correct")
+#endif
+;
+
 extern unsigned long __must_check ___copy_from_user(void *to,
                                                     const void __user *from,
                                                     unsigned long size);
@@ -212,10 +221,16 @@ extern unsigned long copy_from_user_fixup(void *to, const void __user *from,
 static inline unsigned long __must_check
 copy_from_user(void *to, const void __user *from, unsigned long size)
 {
-        unsigned long ret = ___copy_from_user(to, from, size);
-
-        if (unlikely(ret))
-                ret = copy_from_user_fixup(to, from, size);
+        unsigned long ret = (unsigned long) -EFAULT;
+        int sz = __compiletime_object_size(to);
+
+        if (likely(sz == -1 || sz >= size)) {
+                ret = ___copy_from_user(to, from, size);
+                if (unlikely(ret))
+                        ret = copy_from_user_fixup(to, from, size);
+        } else {
+                copy_from_user_overflow();
+        }
         return ret;
 }
 #define __copy_from_user copy_from_user
diff --git a/arch/sparc/include/asm/unistd.h b/arch/sparc/include/asm/unistd.h
index d8d25bd97121..cb4b9bfd0d87 100644
--- a/arch/sparc/include/asm/unistd.h
+++ b/arch/sparc/include/asm/unistd.h
@@ -398,7 +398,7 @@
 #define __NR_perf_event_open    327
 #define __NR_recvmmsg           328
 
-#define NR_SYSCALLS             329
+#define NR_syscalls             329
 
 #ifdef __32bit_syscall_numbers__
 /* Sparc 32-bit only has the "setresuid32", "getresuid32" variants,
diff --git a/arch/sparc/kernel/entry.S b/arch/sparc/kernel/entry.S
index ec9c7bc67d21..1504df8ddf70 100644
--- a/arch/sparc/kernel/entry.S
+++ b/arch/sparc/kernel/entry.S
@@ -1294,7 +1294,7 @@ linux_sparc_syscall:
         sethi   %hi(PSR_SYSCALL), %l4
         or      %l0, %l4, %l0
         /* Direct access to user regs, must faster. */
-        cmp     %g1, NR_SYSCALLS
+        cmp     %g1, NR_syscalls
         bgeu    linux_sparc_ni_syscall
          sll    %g1, 2, %l4
         ld      [%l7 + %l4], %l7
diff --git a/arch/sparc/kernel/ftrace.c b/arch/sparc/kernel/ftrace.c
index d3b1a3076569..29973daa9930 100644
--- a/arch/sparc/kernel/ftrace.c
+++ b/arch/sparc/kernel/ftrace.c
@@ -4,6 +4,7 @@
 #include <linux/percpu.h>
 #include <linux/init.h>
 #include <linux/list.h>
+#include <trace/syscall.h>
 
 #include <asm/ftrace.h>
 
@@ -91,3 +92,13 @@ int __init ftrace_dyn_arch_init(void *data)
 }
 #endif
 
+#ifdef CONFIG_FTRACE_SYSCALLS
+
+extern unsigned int sys_call_table[];
+
+unsigned long __init arch_syscall_addr(int nr)
+{
+        return (unsigned long)sys_call_table[nr];
+}
+
+#endif
diff --git a/arch/sparc/kernel/iommu.c b/arch/sparc/kernel/iommu.c
index 7690cc219ecc..5fad94950e76 100644
--- a/arch/sparc/kernel/iommu.c
+++ b/arch/sparc/kernel/iommu.c
@@ -11,6 +11,7 @@
 #include <linux/dma-mapping.h>
 #include <linux/errno.h>
 #include <linux/iommu-helper.h>
+#include <linux/bitmap.h>
 
 #ifdef CONFIG_PCI
 #include <linux/pci.h>
@@ -169,7 +170,7 @@ void iommu_range_free(struct iommu *iommu, dma_addr_t dma_addr, unsigned long np
 
         entry = (dma_addr - iommu->page_table_map_base) >> IO_PAGE_SHIFT;
 
-        iommu_area_free(arena->map, entry, npages);
+        bitmap_clear(arena->map, entry, npages);
 }
 
 int iommu_table_init(struct iommu *iommu, int tsbsize,
diff --git a/arch/sparc/kernel/irq_64.c b/arch/sparc/kernel/irq_64.c
index ce996f97855f..8d6882bb480a 100644
--- a/arch/sparc/kernel/irq_64.c
+++ b/arch/sparc/kernel/irq_64.c
@@ -176,7 +176,7 @@ int show_interrupts(struct seq_file *p, void *v)
         }
 
         if (i < NR_IRQS) {
-                spin_lock_irqsave(&irq_desc[i].lock, flags);
+                raw_spin_lock_irqsave(&irq_desc[i].lock, flags);
                 action = irq_desc[i].action;
                 if (!action)
                         goto skip;
@@ -195,7 +195,7 @@ int show_interrupts(struct seq_file *p, void *v)
 
                 seq_putc(p, '\n');
 skip:
-                spin_unlock_irqrestore(&irq_desc[i].lock, flags);
+                raw_spin_unlock_irqrestore(&irq_desc[i].lock, flags);
         } else if (i == NR_IRQS) {
                 seq_printf(p, "NMI: ");
                 for_each_online_cpu(j)
@@ -785,14 +785,14 @@ void fixup_irqs(void)
         for (irq = 0; irq < NR_IRQS; irq++) {
                 unsigned long flags;
 
-                spin_lock_irqsave(&irq_desc[irq].lock, flags);
+                raw_spin_lock_irqsave(&irq_desc[irq].lock, flags);
                 if (irq_desc[irq].action &&
                     !(irq_desc[irq].status & IRQ_PER_CPU)) {
                         if (irq_desc[irq].chip->set_affinity)
                                 irq_desc[irq].chip->set_affinity(irq,
                                         irq_desc[irq].affinity);
                 }
-                spin_unlock_irqrestore(&irq_desc[irq].lock, flags);
+                raw_spin_unlock_irqrestore(&irq_desc[irq].lock, flags);
         }
 
         tick_ops->disable_irq();
diff --git a/arch/sparc/kernel/kprobes.c b/arch/sparc/kernel/kprobes.c
index 3bc6527c95af..6716584e48ab 100644
--- a/arch/sparc/kernel/kprobes.c
+++ b/arch/sparc/kernel/kprobes.c
@@ -46,6 +46,9 @@ struct kretprobe_blackpoint kretprobe_blacklist[] = {{NULL, NULL}};
 
 int __kprobes arch_prepare_kprobe(struct kprobe *p)
 {
+        if ((unsigned long) p->addr & 0x3UL)
+                return -EILSEQ;
+
         p->ainsn.insn[0] = *p->addr;
         flushi(&p->ainsn.insn[0]);
 
diff --git a/arch/sparc/kernel/ldc.c b/arch/sparc/kernel/ldc.c
index cb3c72c45aab..df39a0f0d27a 100644
--- a/arch/sparc/kernel/ldc.c
+++ b/arch/sparc/kernel/ldc.c
@@ -14,6 +14,7 @@
 #include <linux/interrupt.h>
 #include <linux/list.h>
 #include <linux/init.h>
+#include <linux/bitmap.h>
 
 #include <asm/hypervisor.h>
 #include <asm/iommu.h>
@@ -1242,13 +1243,13 @@ int ldc_bind(struct ldc_channel *lp, const char *name)
         snprintf(lp->tx_irq_name, LDC_IRQ_NAME_MAX, "%s TX", name);
 
         err = request_irq(lp->cfg.rx_irq, ldc_rx,
-                          IRQF_SAMPLE_RANDOM | IRQF_DISABLED | IRQF_SHARED,
+                          IRQF_SAMPLE_RANDOM | IRQF_DISABLED,
                           lp->rx_irq_name, lp);
         if (err)
                 return err;
 
         err = request_irq(lp->cfg.tx_irq, ldc_tx,
-                          IRQF_SAMPLE_RANDOM | IRQF_DISABLED | IRQF_SHARED,
+                          IRQF_SAMPLE_RANDOM | IRQF_DISABLED,
                           lp->tx_irq_name, lp);
         if (err) {
                 free_irq(lp->cfg.rx_irq, lp);
@@ -1875,7 +1876,7 @@ EXPORT_SYMBOL(ldc_read);
 static long arena_alloc(struct ldc_iommu *iommu, unsigned long npages)
 {
         struct iommu_arena *arena = &iommu->arena;
-        unsigned long n, i, start, end, limit;
+        unsigned long n, start, end, limit;
         int pass;
 
         limit = arena->limit;
@@ -1883,7 +1884,7 @@ static long arena_alloc(struct ldc_iommu *iommu, unsigned long npages)
         pass = 0;
 
 again:
-        n = find_next_zero_bit(arena->map, limit, start);
+        n = bitmap_find_next_zero_area(arena->map, limit, start, npages, 0);
         end = n + npages;
         if (unlikely(end >= limit)) {
                 if (likely(pass < 1)) {
@@ -1896,16 +1897,7 @@ again:
                         return -1;
                 }
         }
-
-        for (i = n; i < end; i++) {
-                if (test_bit(i, arena->map)) {
-                        start = i + 1;
-                        goto again;
-                }
-        }
-
-        for (i = n; i < end; i++)
-                __set_bit(i, arena->map);
+        bitmap_set(arena->map, n, npages);
 
         arena->hint = end;
 
diff --git a/arch/sparc/kernel/mdesc.c b/arch/sparc/kernel/mdesc.c
index 938da19dc065..cdc91d919e93 100644
--- a/arch/sparc/kernel/mdesc.c
+++ b/arch/sparc/kernel/mdesc.c
@@ -10,6 +10,7 @@
 #include <linux/slab.h>
 #include <linux/mm.h>
 #include <linux/miscdevice.h>
+#include <linux/bootmem.h>
 
 #include <asm/cpudata.h>
 #include <asm/hypervisor.h>
@@ -108,25 +109,15 @@ static struct mdesc_handle * __init mdesc_lmb_alloc(unsigned int mdesc_size)
 
 static void mdesc_lmb_free(struct mdesc_handle *hp)
 {
-        unsigned int alloc_size, handle_size = hp->handle_size;
-        unsigned long start, end;
+        unsigned int alloc_size;
+        unsigned long start;
 
         BUG_ON(atomic_read(&hp->refcnt) != 0);
         BUG_ON(!list_empty(&hp->list));
 
-        alloc_size = PAGE_ALIGN(handle_size);
-
-        start = (unsigned long) hp;
-        end = start + alloc_size;
-
-        while (start < end) {
-                struct page *p;
-
-                p = virt_to_page(start);
-                ClearPageReserved(p);
-                __free_page(p);
-                start += PAGE_SIZE;
-        }
+        alloc_size = PAGE_ALIGN(hp->handle_size);
+        start = __pa(hp);
+        free_bootmem_late(start, alloc_size);
 }
 
 static struct mdesc_mem_ops lmb_mdesc_ops = {
diff --git a/arch/sparc/kernel/nmi.c b/arch/sparc/kernel/nmi.c
index b129611590a4..f30f4a1ead23 100644
--- a/arch/sparc/kernel/nmi.c
+++ b/arch/sparc/kernel/nmi.c
@@ -47,7 +47,7 @@ static DEFINE_PER_CPU(short, wd_enabled);
 static int endflag __initdata;
 
 static DEFINE_PER_CPU(unsigned int, last_irq_sum);
-static DEFINE_PER_CPU(local_t, alert_counter);
+static DEFINE_PER_CPU(long, alert_counter);
 static DEFINE_PER_CPU(int, nmi_touch);
 
 void touch_nmi_watchdog(void)
@@ -112,13 +112,13 @@ notrace __kprobes void perfctr_irq(int irq, struct pt_regs *regs)
                 touched = 1;
         }
         if (!touched && __get_cpu_var(last_irq_sum) == sum) {
-                local_inc(&__get_cpu_var(alert_counter));
-                if (local_read(&__get_cpu_var(alert_counter)) == 30 * nmi_hz)
+                __this_cpu_inc(per_cpu_var(alert_counter));
+                if (__this_cpu_read(per_cpu_var(alert_counter)) == 30 * nmi_hz)
                         die_nmi("BUG: NMI Watchdog detected LOCKUP",
                                 regs, panic_on_timeout);
         } else {
                 __get_cpu_var(last_irq_sum) = sum;
-                local_set(&__get_cpu_var(alert_counter), 0);
+                __this_cpu_write(per_cpu_var(alert_counter), 0);
         }
         if (__get_cpu_var(wd_enabled)) {
                 write_pic(picl_value(nmi_hz));
diff --git a/arch/sparc/kernel/of_device_64.c b/arch/sparc/kernel/of_device_64.c
index 881947e59e95..0a6f2d1798d1 100644
--- a/arch/sparc/kernel/of_device_64.c
+++ b/arch/sparc/kernel/of_device_64.c
@@ -104,9 +104,19 @@ static int of_bus_pci_map(u32 *addr, const u32 *range,
         int i;
 
         /* Check address type match */
-        if ((addr[0] ^ range[0]) & 0x03000000)
-                return -EINVAL;
+        if (!((addr[0] ^ range[0]) & 0x03000000))
+                goto type_match;
+
+        /* Special exception, we can map a 64-bit address into
+         * a 32-bit range.
+         */
+        if ((addr[0] & 0x03000000) == 0x03000000 &&
+            (range[0] & 0x03000000) == 0x02000000)
+                goto type_match;
+
+        return -EINVAL;
 
+type_match:
         if (of_out_of_range(addr + 1, range + 1, range + na + pna,
                             na - 1, ns))
                 return -EINVAL;
diff --git a/arch/sparc/kernel/pci.c b/arch/sparc/kernel/pci.c
index c68648662802..539e83f8e087 100644
--- a/arch/sparc/kernel/pci.c
+++ b/arch/sparc/kernel/pci.c
@@ -1064,7 +1064,6 @@ int pci64_dma_supported(struct pci_dev *pdev, u64 device_mask)
 
         return (device_mask & dma_addr_mask) == dma_addr_mask;
 }
-EXPORT_SYMBOL(pci_dma_supported);
 
 void pci_resource_to_user(const struct pci_dev *pdev, int bar,
                           const struct resource *rp, resource_size_t *start,
@@ -1081,3 +1080,10 @@ void pci_resource_to_user(const struct pci_dev *pdev, int bar,
         *start = rp->start - offset;
         *end = rp->end - offset;
 }
+
+static int __init pcibios_init(void)
+{
+        pci_dfl_cache_line_size = 64 >> 2;
+        return 0;
+}
+subsys_initcall(pcibios_init);
diff --git a/arch/sparc/kernel/ptrace_64.c b/arch/sparc/kernel/ptrace_64.c
index 4ae91dc2feb9..2f6524d1a817 100644
--- a/arch/sparc/kernel/ptrace_64.c
+++ b/arch/sparc/kernel/ptrace_64.c
@@ -23,6 +23,7 @@
 #include <linux/signal.h>
 #include <linux/regset.h>
 #include <linux/tracehook.h>
+#include <trace/syscall.h>
 #include <linux/compat.h>
 #include <linux/elf.h>
 
@@ -37,6 +38,9 @@
 #include <asm/cpudata.h>
 #include <asm/cacheflush.h>
 
+#define CREATE_TRACE_POINTS
+#include <trace/events/syscalls.h>
+
 #include "entry.h"
 
 /* #define ALLOW_INIT_TRACING */
@@ -1059,6 +1063,9 @@ asmlinkage int syscall_trace_enter(struct pt_regs *regs)
         if (test_thread_flag(TIF_SYSCALL_TRACE))
                 ret = tracehook_report_syscall_entry(regs);
 
+        if (unlikely(test_thread_flag(TIF_SYSCALL_TRACEPOINT)))
+                trace_sys_enter(regs, regs->u_regs[UREG_G1]);
+
         if (unlikely(current->audit_context) && !ret)
                 audit_syscall_entry((test_thread_flag(TIF_32BIT) ?
                                      AUDIT_ARCH_SPARC :
@@ -1084,6 +1091,9 @@ asmlinkage void syscall_trace_leave(struct pt_regs *regs)
                 audit_syscall_exit(result, regs->u_regs[UREG_I0]);
         }
 
+        if (unlikely(test_thread_flag(TIF_SYSCALL_TRACEPOINT)))
+                trace_sys_exit(regs, regs->u_regs[UREG_G1]);
+
         if (test_thread_flag(TIF_SYSCALL_TRACE))
                 tracehook_report_syscall_exit(regs, 0);
 }
diff --git a/arch/sparc/kernel/sparc_ksyms_64.c b/arch/sparc/kernel/sparc_ksyms_64.c
index 0f26066a08d9..372ad59c4cba 100644
--- a/arch/sparc/kernel/sparc_ksyms_64.c
+++ b/arch/sparc/kernel/sparc_ksyms_64.c
@@ -38,17 +38,5 @@ EXPORT_SYMBOL(sun4v_niagara_setperf);
 EXPORT_SYMBOL(sun4v_niagara2_getperf);
 EXPORT_SYMBOL(sun4v_niagara2_setperf);
 
-#ifdef CONFIG_PCI
-/* inline functions in asm/pci_64.h */
-EXPORT_SYMBOL(pci_alloc_consistent);
-EXPORT_SYMBOL(pci_free_consistent);
-EXPORT_SYMBOL(pci_map_single);
-EXPORT_SYMBOL(pci_unmap_single);
-EXPORT_SYMBOL(pci_map_sg);
-EXPORT_SYMBOL(pci_unmap_sg);
-EXPORT_SYMBOL(pci_dma_sync_single_for_cpu);
-EXPORT_SYMBOL(pci_dma_sync_sg_for_cpu);
-#endif
-
 /* Exporting a symbol from /init/main.c */
 EXPORT_SYMBOL(saved_command_line);
diff --git a/arch/sparc/kernel/sys_sparc32.c b/arch/sparc/kernel/sys_sparc32.c
index 00abe87e5b51..dc0ac197e7e2 100644
--- a/arch/sparc/kernel/sys_sparc32.c
+++ b/arch/sparc/kernel/sys_sparc32.c
@@ -564,28 +564,6 @@ asmlinkage long sparc32_open(const char __user *filename,
         return do_sys_open(AT_FDCWD, filename, flags, mode);
 }
 
-extern unsigned long do_mremap(unsigned long addr,
-        unsigned long old_len, unsigned long new_len,
-        unsigned long flags, unsigned long new_addr);
-                
-asmlinkage unsigned long sys32_mremap(unsigned long addr,
-        unsigned long old_len, unsigned long new_len,
-        unsigned long flags, u32 __new_addr)
-{
-        unsigned long ret = -EINVAL;
-        unsigned long new_addr = __new_addr;
-
-        if (unlikely(sparc_mmap_check(addr, old_len)))
-                goto out;
-        if (unlikely(sparc_mmap_check(new_addr, new_len)))
-                goto out;
-        down_write(&current->mm->mmap_sem);
-        ret = do_mremap(addr, old_len, new_len, flags, new_addr);
-        up_write(&current->mm->mmap_sem);
-out:
-        return ret;       
-}
-
 long sys32_lookup_dcookie(unsigned long cookie_high,
                           unsigned long cookie_low,
                           char __user *buf, size_t len)
diff --git a/arch/sparc/kernel/sys_sparc_32.c b/arch/sparc/kernel/sys_sparc_32.c
index 03035c852a43..3a82e65d8db2 100644
--- a/arch/sparc/kernel/sys_sparc_32.c
+++ b/arch/sparc/kernel/sys_sparc_32.c
@@ -45,7 +45,8 @@ unsigned long arch_get_unmapped_area(struct file *filp, unsigned long addr, unsi
                 /* We do not accept a shared mapping if it would violate
                  * cache aliasing constraints.
                  */
-                if ((flags & MAP_SHARED) && (addr & (SHMLBA - 1)))
+                if ((flags & MAP_SHARED) &&
+                    ((addr - (pgoff << PAGE_SHIFT)) & (SHMLBA - 1)))
                         return -EINVAL;
                 return addr;
         }
@@ -79,15 +80,6 @@ unsigned long arch_get_unmapped_area(struct file *filp, unsigned long addr, unsi
         }
 }
 
-asmlinkage unsigned long sparc_brk(unsigned long brk)
-{
-        if(ARCH_SUN4C) {
-                if ((brk & 0xe0000000) != (current->mm->brk & 0xe0000000))
-                        return current->mm->brk;
-        }
-        return sys_brk(brk);
-}
-
 /*
  * sys_pipe() is the normal C calling standard for creating
  * a pipe. It's not the way unix traditionally does this, though.
@@ -234,31 +226,6 @@ int sparc_mmap_check(unsigned long addr, unsigned long len)
 }
 
 /* Linux version of mmap */
-static unsigned long do_mmap2(unsigned long addr, unsigned long len,
-        unsigned long prot, unsigned long flags, unsigned long fd,
-        unsigned long pgoff)
-{
-        struct file * file = NULL;
-        unsigned long retval = -EBADF;
-
-        if (!(flags & MAP_ANONYMOUS)) {
-                file = fget(fd);
-                if (!file)
-                        goto out;
-        }
-
-        len = PAGE_ALIGN(len);
-        flags &= ~(MAP_EXECUTABLE | MAP_DENYWRITE);
-
-        down_write(&current->mm->mmap_sem);
-        retval = do_mmap_pgoff(file, addr, len, prot, flags, pgoff);
-        up_write(&current->mm->mmap_sem);
-
-        if (file)
-                fput(file);
-out:
-        return retval;
-}
 
 asmlinkage unsigned long sys_mmap2(unsigned long addr, unsigned long len,
         unsigned long prot, unsigned long flags, unsigned long fd,
@@ -266,14 +233,16 @@ asmlinkage unsigned long sys_mmap2(unsigned long addr, unsigned long len,
 {
         /* Make sure the shift for mmap2 is constant (12), no matter what PAGE_SIZE
            we have. */
-        return do_mmap2(addr, len, prot, flags, fd, pgoff >> (PAGE_SHIFT - 12));
+        return sys_mmap_pgoff(addr, len, prot, flags, fd,
+                              pgoff >> (PAGE_SHIFT - 12));
 }
 
 asmlinkage unsigned long sys_mmap(unsigned long addr, unsigned long len,
         unsigned long prot, unsigned long flags, unsigned long fd,
         unsigned long off)
 {
-        return do_mmap2(addr, len, prot, flags, fd, off >> PAGE_SHIFT);
+        /* no alignment check? */
+        return sys_mmap_pgoff(addr, len, prot, flags, fd, off >> PAGE_SHIFT);
 }
 
 long sparc_remap_file_pages(unsigned long start, unsigned long size,
@@ -287,27 +256,6 @@ long sparc_remap_file_pages(unsigned long start, unsigned long size,
                                     (pgoff >> (PAGE_SHIFT - 12)), flags);
 }
 
-extern unsigned long do_mremap(unsigned long addr,
-        unsigned long old_len, unsigned long new_len,
-        unsigned long flags, unsigned long new_addr);
-                
-asmlinkage unsigned long sparc_mremap(unsigned long addr,
-        unsigned long old_len, unsigned long new_len,
-        unsigned long flags, unsigned long new_addr)
-{
-        unsigned long ret = -EINVAL;
-
-        if (unlikely(sparc_mmap_check(addr, old_len)))
-                goto out;
-        if (unlikely(sparc_mmap_check(new_addr, new_len)))
-                goto out;
-        down_write(&current->mm->mmap_sem);
-        ret = do_mremap(addr, old_len, new_len, flags, new_addr);
-        up_write(&current->mm->mmap_sem);
-out:
-        return ret;       
-}
-
 /* we come to here via sys_nis_syscall so it can setup the regs argument */
 asmlinkage unsigned long
 c_sys_nis_syscall (struct pt_regs *regs)
diff --git a/arch/sparc/kernel/sys_sparc_64.c b/arch/sparc/kernel/sys_sparc_64.c
index e2d102447a43..cfa0e19abe3b 100644
--- a/arch/sparc/kernel/sys_sparc_64.c
+++ b/arch/sparc/kernel/sys_sparc_64.c
@@ -317,10 +317,14 @@ bottomup:
 unsigned long get_fb_unmapped_area(struct file *filp, unsigned long orig_addr, unsigned long len, unsigned long pgoff, unsigned long flags)
 {
         unsigned long align_goal, addr = -ENOMEM;
+        unsigned long (*get_area)(struct file *, unsigned long,
+                                  unsigned long, unsigned long, unsigned long);
+
+        get_area = current->mm->get_unmapped_area;
 
         if (flags & MAP_FIXED) {
                 /* Ok, don't mess with it. */
-                return get_unmapped_area(NULL, orig_addr, len, pgoff, flags);
+                return get_area(NULL, orig_addr, len, pgoff, flags);
         }
         flags &= ~MAP_SHARED;
 
@@ -333,7 +337,7 @@ unsigned long get_fb_unmapped_area(struct file *filp, unsigned long orig_addr, u
                 align_goal = (64UL * 1024);
 
         do {
-                addr = get_unmapped_area(NULL, orig_addr, len + (align_goal - PAGE_SIZE), pgoff, flags);
+                addr = get_area(NULL, orig_addr, len + (align_goal - PAGE_SIZE), pgoff, flags);
                 if (!(addr & ~PAGE_MASK)) {
                         addr = (addr + (align_goal - 1UL)) & ~(align_goal - 1UL);
                         break;
@@ -351,7 +355,7 @@ unsigned long get_fb_unmapped_area(struct file *filp, unsigned long orig_addr, u
          * be obtained.
          */
         if (addr & ~PAGE_MASK)
-                addr = get_unmapped_area(NULL, orig_addr, len, pgoff, flags);
+                addr = get_area(NULL, orig_addr, len, pgoff, flags);
 
         return addr;
 }
@@ -399,18 +403,6 @@ void arch_pick_mmap_layout(struct mm_struct *mm)
         }
 }
 
-SYSCALL_DEFINE1(sparc_brk, unsigned long, brk)
-{
-        /* People could try to be nasty and use ta 0x6d in 32bit programs */
-        if (test_thread_flag(TIF_32BIT) && brk >= STACK_TOP32)
-                return current->mm->brk;
-
-        if (unlikely(straddles_64bit_va_hole(current->mm->brk, brk)))
-                return current->mm->brk;
-
-        return sys_brk(brk);
-}
-                                                                
 /*
  * sys_pipe() is the normal C calling standard for creating
  * a pipe. It's not the way unix traditionally does this, though.
@@ -568,23 +560,13 @@ SYSCALL_DEFINE6(mmap, unsigned long, addr, unsigned long, len,
                 unsigned long, prot, unsigned long, flags, unsigned long, fd,
                 unsigned long, off)
 {
-        struct file * file = NULL;
-        unsigned long retval = -EBADF;
-
-        if (!(flags & MAP_ANONYMOUS)) {
-                file = fget(fd);
-                if (!file)
-                        goto out;
-        }
-        flags &= ~(MAP_EXECUTABLE | MAP_DENYWRITE);
-        len = PAGE_ALIGN(len);
+        unsigned long retval = -EINVAL;
 
-        down_write(&current->mm->mmap_sem);
-        retval = do_mmap(file, addr, len, prot, flags, off);
-        up_write(&current->mm->mmap_sem);
-
-        if (file)
-                fput(file);
+        if ((off + PAGE_ALIGN(len)) < off)
+                goto out;
+        if (off & ~PAGE_MASK)
+                goto out;
+        retval = sys_mmap_pgoff(addr, len, prot, flags, fd, off >> PAGE_SHIFT);
 out:
         return retval;
 }
@@ -614,12 +596,6 @@ SYSCALL_DEFINE5(64_mremap, unsigned long, addr,	unsigned long, old_len,
 
         if (test_thread_flag(TIF_32BIT))
                 goto out;
-        if (unlikely(new_len >= VA_EXCLUDE_START))
-                goto out;
-        if (unlikely(sparc_mmap_check(addr, old_len)))
-                goto out;
-        if (unlikely(sparc_mmap_check(new_addr, new_len)))
-                goto out;
 
         down_write(&current->mm->mmap_sem);
         ret = do_mremap(addr, old_len, new_len, flags, new_addr);
diff --git a/arch/sparc/kernel/syscalls.S b/arch/sparc/kernel/syscalls.S
index d150c2aa98d2..dc4a458f74dc 100644
--- a/arch/sparc/kernel/syscalls.S
+++ b/arch/sparc/kernel/syscalls.S
@@ -62,7 +62,7 @@ sys32_rt_sigreturn:
 #endif
         .align  32
 1:      ldx     [%g6 + TI_FLAGS], %l5
-        andcc   %l5, (_TIF_SYSCALL_TRACE|_TIF_SECCOMP|_TIF_SYSCALL_AUDIT), %g0
+        andcc   %l5, (_TIF_SYSCALL_TRACE|_TIF_SECCOMP|_TIF_SYSCALL_AUDIT|_TIF_SYSCALL_TRACEPOINT), %g0
         be,pt   %icc, rtrap
          nop
         call    syscall_trace_leave
@@ -187,7 +187,7 @@ linux_syscall_trace:
         .globl  linux_sparc_syscall32
 linux_sparc_syscall32:
         /* Direct access to user regs, much faster. */
-        cmp     %g1, NR_SYSCALLS                        ! IEU1  Group
+        cmp     %g1, NR_syscalls                        ! IEU1  Group
         bgeu,pn %xcc, linux_sparc_ni_syscall            ! CTI
          srl    %i0, 0, %o0                             ! IEU0
         sll     %g1, 2, %l4                             ! IEU0  Group
@@ -198,7 +198,7 @@ linux_sparc_syscall32:
 
         srl     %i5, 0, %o5                             ! IEU1
         srl     %i2, 0, %o2                             ! IEU0  Group
-        andcc   %l0, (_TIF_SYSCALL_TRACE|_TIF_SECCOMP|_TIF_SYSCALL_AUDIT), %g0
+        andcc   %l0, (_TIF_SYSCALL_TRACE|_TIF_SECCOMP|_TIF_SYSCALL_AUDIT|_TIF_SYSCALL_TRACEPOINT), %g0
         bne,pn  %icc, linux_syscall_trace32             ! CTI
          mov    %i0, %l5                                ! IEU1
         call    %l7                                     ! CTI   Group brk forced
@@ -210,7 +210,7 @@ linux_sparc_syscall32:
         .globl  linux_sparc_syscall
 linux_sparc_syscall:
         /* Direct access to user regs, much faster. */
-        cmp     %g1, NR_SYSCALLS                        ! IEU1  Group
+        cmp     %g1, NR_syscalls                        ! IEU1  Group
         bgeu,pn %xcc, linux_sparc_ni_syscall            ! CTI
          mov    %i0, %o0                                ! IEU0
         sll     %g1, 2, %l4                             ! IEU0  Group
@@ -221,7 +221,7 @@ linux_sparc_syscall:
 
         mov     %i3, %o3                                ! IEU1
         mov     %i4, %o4                                ! IEU0  Group
-        andcc   %l0, (_TIF_SYSCALL_TRACE|_TIF_SECCOMP|_TIF_SYSCALL_AUDIT), %g0
+        andcc   %l0, (_TIF_SYSCALL_TRACE|_TIF_SECCOMP|_TIF_SYSCALL_AUDIT|_TIF_SYSCALL_TRACEPOINT), %g0
         bne,pn  %icc, linux_syscall_trace               ! CTI   Group
          mov    %i0, %l5                                ! IEU0
 2:      call    %l7                                     ! CTI   Group brk forced
@@ -245,7 +245,7 @@ ret_sys_call:
 
         cmp     %o0, -ERESTART_RESTARTBLOCK
         bgeu,pn %xcc, 1f
-         andcc  %l0, (_TIF_SYSCALL_TRACE|_TIF_SECCOMP|_TIF_SYSCALL_AUDIT), %l6
+         andcc  %l0, (_TIF_SYSCALL_TRACE|_TIF_SECCOMP|_TIF_SYSCALL_AUDIT|_TIF_SYSCALL_TRACEPOINT), %l6
 80:
         /* System call success, clear Carry condition code. */
         andn    %g3, %g2, %g3
@@ -260,7 +260,7 @@ ret_sys_call:
         /* System call failure, set Carry condition code.
          * Also, get abs(errno) to return to the process.
          */
-        andcc   %l0, (_TIF_SYSCALL_TRACE|_TIF_SECCOMP|_TIF_SYSCALL_AUDIT), %l6  
+        andcc   %l0, (_TIF_SYSCALL_TRACE|_TIF_SECCOMP|_TIF_SYSCALL_AUDIT|_TIF_SYSCALL_TRACEPOINT), %l6  
         sub     %g0, %o0, %o0
         or      %g3, %g2, %g3
         stx     %o0, [%sp + PTREGS_OFF + PT_V9_I0]
diff --git a/arch/sparc/kernel/systbls.h b/arch/sparc/kernel/systbls.h
index a63c5d2d9849..d2f999ae2b85 100644
--- a/arch/sparc/kernel/systbls.h
+++ b/arch/sparc/kernel/systbls.h
@@ -9,7 +9,6 @@
 struct new_utsname;
 
 extern asmlinkage unsigned long sys_getpagesize(void);
-extern asmlinkage unsigned long sparc_brk(unsigned long brk);
 extern asmlinkage long sparc_pipe(struct pt_regs *regs);
 extern asmlinkage long sys_ipc(unsigned int call, int first,
                                unsigned long second,
diff --git a/arch/sparc/kernel/systbls_32.S b/arch/sparc/kernel/systbls_32.S
index ceb1530f8aa6..801fc8e5a0e8 100644
--- a/arch/sparc/kernel/systbls_32.S
+++ b/arch/sparc/kernel/systbls_32.S
@@ -19,7 +19,7 @@ sys_call_table:
 /*0*/   .long sys_restart_syscall, sys_exit, sys_fork, sys_read, sys_write
 /*5*/   .long sys_open, sys_close, sys_wait4, sys_creat, sys_link
 /*10*/  .long sys_unlink, sunos_execv, sys_chdir, sys_chown16, sys_mknod
-/*15*/  .long sys_chmod, sys_lchown16, sparc_brk, sys_nis_syscall, sys_lseek
+/*15*/  .long sys_chmod, sys_lchown16, sys_brk, sys_nis_syscall, sys_lseek
 /*20*/  .long sys_getpid, sys_capget, sys_capset, sys_setuid16, sys_getuid16
 /*25*/  .long sys_vmsplice, sys_ptrace, sys_alarm, sys_sigaltstack, sys_pause
 /*30*/  .long sys_utime, sys_lchown, sys_fchown, sys_access, sys_nice
@@ -67,7 +67,7 @@ sys_call_table:
 /*235*/ .long sys_fstatfs64, sys_llseek, sys_mlock, sys_munlock, sys_mlockall
 /*240*/ .long sys_munlockall, sys_sched_setparam, sys_sched_getparam, sys_sched_setscheduler, sys_sched_getscheduler
 /*245*/ .long sys_sched_yield, sys_sched_get_priority_max, sys_sched_get_priority_min, sys_sched_rr_get_interval, sys_nanosleep
-/*250*/ .long sparc_mremap, sys_sysctl, sys_getsid, sys_fdatasync, sys_nfsservctl
+/*250*/ .long sys_mremap, sys_sysctl, sys_getsid, sys_fdatasync, sys_nfsservctl
 /*255*/ .long sys_sync_file_range, sys_clock_settime, sys_clock_gettime, sys_clock_getres, sys_clock_nanosleep
 /*260*/ .long sys_sched_getaffinity, sys_sched_setaffinity, sys_timer_settime, sys_timer_gettime, sys_timer_getoverrun
 /*265*/ .long sys_timer_delete, sys_timer_create, sys_nis_syscall, sys_io_setup, sys_io_destroy
diff --git a/arch/sparc/kernel/systbls_64.S b/arch/sparc/kernel/systbls_64.S
index cc8e7862e95a..e575b46bd7a9 100644
--- a/arch/sparc/kernel/systbls_64.S
+++ b/arch/sparc/kernel/systbls_64.S
@@ -21,7 +21,7 @@ sys_call_table32:
 /*0*/   .word sys_restart_syscall, sys32_exit, sys_fork, sys_read, sys_write
 /*5*/   .word sys32_open, sys_close, sys32_wait4, sys32_creat, sys_link
 /*10*/  .word sys_unlink, sunos_execv, sys_chdir, sys_chown16, sys32_mknod
-/*15*/  .word sys_chmod, sys_lchown16, sys_sparc_brk, sys32_perfctr, sys32_lseek
+/*15*/  .word sys_chmod, sys_lchown16, sys_brk, sys32_perfctr, sys32_lseek
 /*20*/  .word sys_getpid, sys_capget, sys_capset, sys_setuid16, sys_getuid16
 /*25*/  .word sys32_vmsplice, compat_sys_ptrace, sys_alarm, sys32_sigaltstack, sys_pause
 /*30*/  .word compat_sys_utime, sys_lchown, sys_fchown, sys32_access, sys32_nice
@@ -68,7 +68,7 @@ sys_call_table32:
         .word compat_sys_fstatfs64, sys_llseek, sys_mlock, sys_munlock, sys32_mlockall
 /*240*/ .word sys_munlockall, sys32_sched_setparam, sys32_sched_getparam, sys32_sched_setscheduler, sys32_sched_getscheduler
         .word sys_sched_yield, sys32_sched_get_priority_max, sys32_sched_get_priority_min, sys32_sched_rr_get_interval, compat_sys_nanosleep
-/*250*/ .word sys32_mremap, compat_sys_sysctl, sys32_getsid, sys_fdatasync, sys32_nfsservctl
+/*250*/ .word sys_mremap, compat_sys_sysctl, sys32_getsid, sys_fdatasync, sys32_nfsservctl
         .word sys32_sync_file_range, compat_sys_clock_settime, compat_sys_clock_gettime, compat_sys_clock_getres, sys32_clock_nanosleep
 /*260*/ .word compat_sys_sched_getaffinity, compat_sys_sched_setaffinity, sys32_timer_settime, compat_sys_timer_gettime, sys_timer_getoverrun
         .word sys_timer_delete, compat_sys_timer_create, sys_ni_syscall, compat_sys_io_setup, sys_io_destroy
@@ -96,7 +96,7 @@ sys_call_table:
 /*0*/   .word sys_restart_syscall, sparc_exit, sys_fork, sys_read, sys_write
 /*5*/   .word sys_open, sys_close, sys_wait4, sys_creat, sys_link
 /*10*/  .word sys_unlink, sys_nis_syscall, sys_chdir, sys_chown, sys_mknod
-/*15*/  .word sys_chmod, sys_lchown, sys_sparc_brk, sys_perfctr, sys_lseek
+/*15*/  .word sys_chmod, sys_lchown, sys_brk, sys_perfctr, sys_lseek
 /*20*/  .word sys_getpid, sys_capget, sys_capset, sys_setuid, sys_getuid
 /*25*/  .word sys_vmsplice, sys_ptrace, sys_alarm, sys_sigaltstack, sys_nis_syscall
 /*30*/  .word sys_utime, sys_nis_syscall, sys_nis_syscall, sys_access, sys_nice
diff --git a/arch/sparc/kernel/time_64.c b/arch/sparc/kernel/time_64.c
index 63f73ae8a892..67e165102885 100644
--- a/arch/sparc/kernel/time_64.c
+++ b/arch/sparc/kernel/time_64.c
@@ -774,26 +774,9 @@ void __devinit setup_sparc64_timer(void)
 static struct clocksource clocksource_tick = {
         .rating         = 100,
         .mask           = CLOCKSOURCE_MASK(64),
-        .shift          = 16,
         .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
 };
 
-static void __init setup_clockevent_multiplier(unsigned long hz)
-{
-        unsigned long mult, shift = 32;
-
-        while (1) {
-                mult = div_sc(hz, NSEC_PER_SEC, shift);
-                if (mult && (mult >> 32UL) == 0UL)
-                        break;
-
-                shift--;
-        }
-
-        sparc64_clockevent.shift = shift;
-        sparc64_clockevent.mult = mult;
-}
-
 static unsigned long tb_ticks_per_usec __read_mostly;
 
 void __delay(unsigned long loops)
@@ -828,9 +811,7 @@ void __init time_init(void)
                 clocksource_hz2mult(freq, SPARC64_NSEC_PER_CYC_SHIFT);
 
         clocksource_tick.name = tick_ops->name;
-        clocksource_tick.mult =
-                clocksource_hz2mult(freq,
-                                    clocksource_tick.shift);
+        clocksource_calc_mult_shift(&clocksource_tick, freq, 4);
         clocksource_tick.read = clocksource_tick_read;
 
         printk("clocksource: mult[%x] shift[%d]\n",
@@ -839,15 +820,14 @@ void __init time_init(void)
         clocksource_register(&clocksource_tick);
 
         sparc64_clockevent.name = tick_ops->name;
-
-        setup_clockevent_multiplier(freq);
+        clockevents_calc_mult_shift(&sparc64_clockevent, freq, 4);
 
         sparc64_clockevent.max_delta_ns =
                 clockevent_delta2ns(0x7fffffffffffffffUL, &sparc64_clockevent);
         sparc64_clockevent.min_delta_ns =
                 clockevent_delta2ns(0xF, &sparc64_clockevent);
 
-        printk("clockevent: mult[%ux] shift[%d]\n",
+        printk("clockevent: mult[%x] shift[%d]\n",
                sparc64_clockevent.mult, sparc64_clockevent.shift);
 
         setup_sparc64_timer();
diff --git a/arch/sparc/kernel/unaligned_32.c b/arch/sparc/kernel/unaligned_32.c
index 6b1e6cde6fff..f8514e291e15 100644
--- a/arch/sparc/kernel/unaligned_32.c
+++ b/arch/sparc/kernel/unaligned_32.c
@@ -17,8 +17,7 @@
 #include <asm/uaccess.h>
 #include <linux/smp.h>
 #include <linux/smp_lock.h>
-
-/* #define DEBUG_MNA */
+#include <linux/perf_event.h>
 
 enum direction {
         load,    /* ld, ldd, ldh, ldsh */
@@ -29,12 +28,6 @@ enum direction {
         invalid,
 };
 
-#ifdef DEBUG_MNA
-static char *dirstrings[] = {
-  "load", "store", "both", "fpload", "fpstore", "invalid"
-};
-#endif
-
 static inline enum direction decode_direction(unsigned int insn)
 {
         unsigned long tmp = (insn >> 21) & 1;
@@ -255,10 +248,7 @@ asmlinkage void kernel_unaligned_trap(struct pt_regs *regs, unsigned int insn)
                 unsigned long addr = compute_effective_address(regs, insn);
                 int err;
 
-#ifdef DEBUG_MNA
-                printk("KMNA: pc=%08lx [dir=%s addr=%08lx size=%d] retpc[%08lx]\n",
-                       regs->pc, dirstrings[dir], addr, size, regs->u_regs[UREG_RETPC]);
-#endif
+                perf_sw_event(PERF_COUNT_SW_ALIGNMENT_FAULTS, 1, 0, regs, addr);
                 switch (dir) {
                 case load:
                         err = do_int_load(fetch_reg_addr(((insn>>25)&0x1f),
@@ -350,6 +340,7 @@ asmlinkage void user_unaligned_trap(struct pt_regs *regs, unsigned int insn)
                 }
 
                 addr = compute_effective_address(regs, insn);
+                perf_sw_event(PERF_COUNT_SW_ALIGNMENT_FAULTS, 1, 0, regs, addr);
                 switch(dir) {
                 case load:
                         err = do_int_load(fetch_reg_addr(((insn>>25)&0x1f),
diff --git a/arch/sparc/kernel/unaligned_64.c b/arch/sparc/kernel/unaligned_64.c
index 379209982a07..378ca82b9ccc 100644
--- a/arch/sparc/kernel/unaligned_64.c
+++ b/arch/sparc/kernel/unaligned_64.c
@@ -20,10 +20,9 @@
 #include <asm/uaccess.h>
 #include <linux/smp.h>
 #include <linux/bitops.h>
+#include <linux/perf_event.h>
 #include <asm/fpumacro.h>
 
-/* #define DEBUG_MNA */
-
 enum direction {
         load,    /* ld, ldd, ldh, ldsh */
         store,   /* st, std, sth, stsh */
@@ -33,12 +32,6 @@ enum direction {
         invalid,
 };
 
-#ifdef DEBUG_MNA
-static char *dirstrings[] = {
-  "load", "store", "both", "fpload", "fpstore", "invalid"
-};
-#endif
-
 static inline enum direction decode_direction(unsigned int insn)
 {
         unsigned long tmp = (insn >> 21) & 1;
@@ -327,12 +320,7 @@ asmlinkage void kernel_unaligned_trap(struct pt_regs *regs, unsigned int insn)
 
                 addr = compute_effective_address(regs, insn,
                                                  ((insn >> 25) & 0x1f));
-#ifdef DEBUG_MNA
-                printk("KMNA: pc=%016lx [dir=%s addr=%016lx size=%d] "
-                       "retpc[%016lx]\n",
-                       regs->tpc, dirstrings[dir], addr, size,
-                       regs->u_regs[UREG_RETPC]);
-#endif
+                perf_sw_event(PERF_COUNT_SW_ALIGNMENT_FAULTS, 1, 0, regs, addr);
                 switch (asi) {
                 case ASI_NL:
                 case ASI_AIUPL:
@@ -399,6 +387,7 @@ int handle_popc(u32 insn, struct pt_regs *regs)
         int ret, i, rd = ((insn >> 25) & 0x1f);
         int from_kernel = (regs->tstate & TSTATE_PRIV) != 0;
                                 
+        perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, 0, regs, 0);
         if (insn & 0x2000) {
                 maybe_flush_windows(0, 0, rd, from_kernel);
                 value = sign_extend_imm13(insn);
@@ -445,6 +434,8 @@ int handle_ldf_stq(u32 insn, struct pt_regs *regs)
         int asi = decode_asi(insn, regs);
         int flag = (freg < 32) ? FPRS_DL : FPRS_DU;
 
+        perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, 0, regs, 0);
+
         save_and_clear_fpu();
         current_thread_info()->xfsr[0] &= ~0x1c000;
         if (freg & 3) {
@@ -566,6 +557,8 @@ void handle_ld_nf(u32 insn, struct pt_regs *regs)
         int from_kernel = (regs->tstate & TSTATE_PRIV) != 0;
         unsigned long *reg;
                                 
+        perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, 0, regs, 0);
+
         maybe_flush_windows(0, 0, rd, from_kernel);
         reg = fetch_reg_addr(rd, regs);
         if (from_kernel || rd < 16) {
@@ -596,6 +589,7 @@ void handle_lddfmna(struct pt_regs *regs, unsigned long sfar, unsigned long sfsr
 
         if (tstate & TSTATE_PRIV)
                 die_if_kernel("lddfmna from kernel", regs);
+        perf_sw_event(PERF_COUNT_SW_ALIGNMENT_FAULTS, 1, 0, regs, sfar);
         if (test_thread_flag(TIF_32BIT))
                 pc = (u32)pc;
         if (get_user(insn, (u32 __user *) pc) != -EFAULT) {
@@ -657,6 +651,7 @@ void handle_stdfmna(struct pt_regs *regs, unsigned long sfar, unsigned long sfsr
 
         if (tstate & TSTATE_PRIV)
                 die_if_kernel("stdfmna from kernel", regs);
+        perf_sw_event(PERF_COUNT_SW_ALIGNMENT_FAULTS, 1, 0, regs, sfar);
         if (test_thread_flag(TIF_32BIT))
                 pc = (u32)pc;
         if (get_user(insn, (u32 __user *) pc) != -EFAULT) {
diff --git a/arch/sparc/kernel/visemul.c b/arch/sparc/kernel/visemul.c
index d231cbd5c526..9dfd2ebcb157 100644
--- a/arch/sparc/kernel/visemul.c
+++ b/arch/sparc/kernel/visemul.c
@@ -5,6 +5,7 @@
 #include <linux/kernel.h>
 #include <linux/errno.h>
 #include <linux/thread_info.h>
+#include <linux/perf_event.h>
 
 #include <asm/ptrace.h>
 #include <asm/pstate.h>
@@ -801,6 +802,8 @@ int vis_emul(struct pt_regs *regs, unsigned int insn)
 
         BUG_ON(regs->tstate & TSTATE_PRIV);
 
+        perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, 0, regs, 0);
+
         if (test_thread_flag(TIF_32BIT))
                 pc = (u32)pc;
 
diff --git a/arch/sparc/lib/Makefile b/arch/sparc/lib/Makefile
index e75faf0e59ae..c4b5e03af115 100644
--- a/arch/sparc/lib/Makefile
+++ b/arch/sparc/lib/Makefile
@@ -44,3 +44,4 @@ obj-y                 += iomap.o
 obj-$(CONFIG_SPARC32) += atomic32.o
 obj-y                 += ksyms.o
 obj-$(CONFIG_SPARC64) += PeeCeeI.o
+obj-y                 += usercopy.o
diff --git a/arch/sparc/lib/bzero.S b/arch/sparc/lib/bzero.S
index b6557297440f..615f401edf69 100644
--- a/arch/sparc/lib/bzero.S
+++ b/arch/sparc/lib/bzero.S
@@ -6,10 +6,6 @@
 
         .text
 
-        .globl  __memset
-        .type   __memset, #function
-__memset:               /* %o0=buf, %o1=pat, %o2=len */
-
         .globl  memset
         .type   memset, #function
 memset:                 /* %o0=buf, %o1=pat, %o2=len */
@@ -83,7 +79,6 @@ __bzero_done:
         retl
          mov            %o3, %o0
         .size           __bzero, .-__bzero
-        .size           __memset, .-__memset
         .size           memset, .-memset
 
 #define EX_ST(x,y)              \
diff --git a/arch/sparc/lib/checksum_32.S b/arch/sparc/lib/checksum_32.S
index 77f228533d47..3632cb34e914 100644
--- a/arch/sparc/lib/checksum_32.S
+++ b/arch/sparc/lib/checksum_32.S
@@ -560,7 +560,7 @@ __csum_partial_copy_end:
          mov    %i0, %o1
         mov     %i1, %o0
 5:
-        call    __memcpy
+        call    memcpy
          mov    %i2, %o2
         tst     %o0
         bne,a   2f
diff --git a/arch/sparc/lib/ksyms.c b/arch/sparc/lib/ksyms.c
index 704b12668388..1b30bb3bfdb1 100644
--- a/arch/sparc/lib/ksyms.c
+++ b/arch/sparc/lib/ksyms.c
@@ -30,7 +30,6 @@ EXPORT_SYMBOL(__memscan_generic);
 EXPORT_SYMBOL(memcmp);
 EXPORT_SYMBOL(memcpy);
 EXPORT_SYMBOL(memset);
-EXPORT_SYMBOL(__memset);
 EXPORT_SYMBOL(memmove);
 EXPORT_SYMBOL(__bzero);
 
@@ -81,7 +80,6 @@ EXPORT_SYMBOL(__csum_partial_copy_sparc_generic);
 
 /* Special internal versions of library functions. */
 EXPORT_SYMBOL(__copy_1page);
-EXPORT_SYMBOL(__memcpy);
 EXPORT_SYMBOL(__memmove);
 EXPORT_SYMBOL(bzero_1page);
 
diff --git a/arch/sparc/lib/mcount.S b/arch/sparc/lib/mcount.S
index 7ce9c65f3592..24b8b12deed2 100644
--- a/arch/sparc/lib/mcount.S
+++ b/arch/sparc/lib/mcount.S
@@ -64,8 +64,9 @@ mcount:
 2:       sethi          %hi(softirq_stack), %g3
         or              %g3, %lo(softirq_stack), %g3
         ldx             [%g3 + %g1], %g7
+        sub             %g7, STACK_BIAS, %g7
         cmp             %sp, %g7
-        bleu,pt         %xcc, 2f
+        bleu,pt         %xcc, 3f
          sethi          %hi(THREAD_SIZE), %g3
         add             %g7, %g3, %g7
         cmp             %sp, %g7
@@ -75,7 +76,7 @@ mcount:
          * again, we are already trying to output the stack overflow
          * message.
          */
-        sethi           %hi(ovstack), %g7               ! cant move to panic stack fast enough
+3:      sethi           %hi(ovstack), %g7               ! cant move to panic stack fast enough
          or             %g7, %lo(ovstack), %g7
         add             %g7, OVSTACKSIZE, %g3
         sub             %g3, STACK_BIAS + 192, %g3
diff --git a/arch/sparc/lib/memcpy.S b/arch/sparc/lib/memcpy.S
index ce10bc869af9..34fe65751737 100644
--- a/arch/sparc/lib/memcpy.S
+++ b/arch/sparc/lib/memcpy.S
@@ -543,9 +543,6 @@ FUNC(memmove)
         b               3f
          add            %o0, 2, %o0
 
-#ifdef __KERNEL__
-FUNC(__memcpy)
-#endif
 FUNC(memcpy)    /* %o0=dst %o1=src %o2=len */
 
         sub             %o0, %o1, %o4
diff --git a/arch/sparc/lib/memset.S b/arch/sparc/lib/memset.S
index 1c37ea892deb..99c017be8719 100644
--- a/arch/sparc/lib/memset.S
+++ b/arch/sparc/lib/memset.S
@@ -60,11 +60,10 @@
         .globl  __bzero_begin
 __bzero_begin:
 
-        .globl  __bzero, __memset, 
+        .globl  __bzero
         .globl  memset
         .globl  __memset_start, __memset_end
 __memset_start:
-__memset:
 memset:
         and     %o1, 0xff, %g3
         sll     %g3, 8, %g2
diff --git a/arch/sparc/lib/usercopy.c b/arch/sparc/lib/usercopy.c
new file mode 100644
index 000000000000..14b363fec8a2
--- /dev/null
+++ b/arch/sparc/lib/usercopy.c
@@ -0,0 +1,8 @@
+#include <linux/module.h>
+#include <linux/bug.h>
+
+void copy_from_user_overflow(void)
+{
+        WARN(1, "Buffer overflow detected!\n");
+}
+EXPORT_SYMBOL(copy_from_user_overflow);
diff --git a/arch/sparc/math-emu/math_32.c b/arch/sparc/math-emu/math_32.c
index e13f65da17df..a3fccde894ec 100644
--- a/arch/sparc/math-emu/math_32.c
+++ b/arch/sparc/math-emu/math_32.c
@@ -67,6 +67,7 @@
 #include <linux/types.h>
 #include <linux/sched.h>
 #include <linux/mm.h>
+#include <linux/perf_event.h>
 #include <asm/uaccess.h>
 
 #include "sfp-util_32.h"
@@ -163,6 +164,8 @@ int do_mathemu(struct pt_regs *regs, struct task_struct *fpt)
         int retcode = 0;                               /* assume all succeed */
         unsigned long insn;
 
+        perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, 0, regs, 0);
+
 #ifdef DEBUG_MATHEMU
         printk("In do_mathemu()... pc is %08lx\n", regs->pc);
         printk("fpqdepth is %ld\n", fpt->thread.fpqdepth);
diff --git a/arch/sparc/math-emu/math_64.c b/arch/sparc/math-emu/math_64.c
index 6863c9bde25c..56d2c44747b8 100644
--- a/arch/sparc/math-emu/math_64.c
+++ b/arch/sparc/math-emu/math_64.c
@@ -11,6 +11,7 @@
 #include <linux/types.h>
 #include <linux/sched.h>
 #include <linux/errno.h>
+#include <linux/perf_event.h>
 
 #include <asm/fpumacro.h>
 #include <asm/ptrace.h>
@@ -183,6 +184,7 @@ int do_mathemu(struct pt_regs *regs, struct fpustate *f)
 
         if (tstate & TSTATE_PRIV)
                 die_if_kernel("unfinished/unimplemented FPop from kernel", regs);
+        perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, 0, regs, 0);
         if (test_thread_flag(TIF_32BIT))
                 pc = (u32)pc;
         if (get_user(insn, (u32 __user *) pc) != -EFAULT) {
diff --git a/arch/sparc/mm/fault_64.c b/arch/sparc/mm/fault_64.c
index 43b0da96a4fb..6081936bf03b 100644
--- a/arch/sparc/mm/fault_64.c
+++ b/arch/sparc/mm/fault_64.c
@@ -31,13 +31,12 @@
 #include <asm/sections.h>
 #include <asm/mmu_context.h>
 
-#ifdef CONFIG_KPROBES
-static inline int notify_page_fault(struct pt_regs *regs)
+static inline __kprobes int notify_page_fault(struct pt_regs *regs)
 {
         int ret = 0;
 
         /* kprobe_running() needs smp_processor_id() */
-        if (!user_mode(regs)) {
+        if (kprobes_built_in() && !user_mode(regs)) {
                 preempt_disable();
                 if (kprobe_running() && kprobe_fault_handler(regs, 0))
                         ret = 1;
@@ -45,12 +44,6 @@ static inline int notify_page_fault(struct pt_regs *regs)
         }
         return ret;
 }
-#else
-static inline int notify_page_fault(struct pt_regs *regs)
-{
-        return 0;
-}
-#endif
 
 static void __kprobes unhandled_fault(unsigned long address,
                                       struct task_struct *tsk,
@@ -73,7 +66,7 @@ static void __kprobes unhandled_fault(unsigned long address,
         die_if_kernel("Oops", regs);
 }
 
-static void bad_kernel_pc(struct pt_regs *regs, unsigned long vaddr)
+static void __kprobes bad_kernel_pc(struct pt_regs *regs, unsigned long vaddr)
 {
         printk(KERN_CRIT "OOPS: Bogus kernel PC [%016lx] in fault handler\n",
                regs->tpc);
@@ -170,8 +163,9 @@ static unsigned int get_fault_insn(struct pt_regs *regs, unsigned int insn)
         return insn;
 }
 
-static void do_kernel_fault(struct pt_regs *regs, int si_code, int fault_code,
-                            unsigned int insn, unsigned long address)
+static void __kprobes do_kernel_fault(struct pt_regs *regs, int si_code,
+                                      int fault_code, unsigned int insn,
+                                      unsigned long address)
 {
         unsigned char asi = ASI_P;
  
@@ -225,7 +219,7 @@ cannot_handle:
         unhandled_fault (address, current, regs);
 }
 
-static void noinline bogus_32bit_fault_tpc(struct pt_regs *regs)
+static void noinline __kprobes bogus_32bit_fault_tpc(struct pt_regs *regs)
 {
         static int times;
 
@@ -237,8 +231,8 @@ static void noinline bogus_32bit_fault_tpc(struct pt_regs *regs)
         show_regs(regs);
 }
 
-static void noinline bogus_32bit_fault_address(struct pt_regs *regs,
-                                               unsigned long addr)
+static void noinline __kprobes bogus_32bit_fault_address(struct pt_regs *regs,
+                                                         unsigned long addr)
 {
         static int times;
 
diff --git a/arch/sparc/mm/sun4c.c b/arch/sparc/mm/sun4c.c
index 2ffacd67c424..a89baf0d875a 100644
--- a/arch/sparc/mm/sun4c.c
+++ b/arch/sparc/mm/sun4c.c
@@ -17,6 +17,7 @@
 #include <linux/fs.h>
 #include <linux/seq_file.h>
 #include <linux/scatterlist.h>
+#include <linux/bitmap.h>
 
 #include <asm/sections.h>
 #include <asm/page.h>
@@ -1021,20 +1022,12 @@ static char *sun4c_lockarea(char *vaddr, unsigned long size)
         npages = (((unsigned long)vaddr & ~PAGE_MASK) +
                   size + (PAGE_SIZE-1)) >> PAGE_SHIFT;
 
-        scan = 0;
         local_irq_save(flags);
-        for (;;) {
-                scan = find_next_zero_bit(sun4c_iobuffer_map,
-                                          iobuffer_map_size, scan);
-                if ((base = scan) + npages > iobuffer_map_size) goto abend;
-                for (;;) {
-                        if (scan >= base + npages) goto found;
-                        if (test_bit(scan, sun4c_iobuffer_map)) break;
-                        scan++;
-                }
-        }
+        base = bitmap_find_next_zero_area(sun4c_iobuffer_map, iobuffer_map_size,
+                                                0, npages, 0);
+        if (base >= iobuffer_map_size)
+                goto abend;
 
-found:
         high = ((base + npages) << PAGE_SHIFT) + sun4c_iobuffer_start;
         high = SUN4C_REAL_PGDIR_ALIGN(high);
         while (high > sun4c_iobuffer_high) {
diff --git a/arch/um/Makefile b/arch/um/Makefile
index fc633dbacf84..fab8121d2b32 100644
--- a/arch/um/Makefile
+++ b/arch/um/Makefile
@@ -149,6 +149,6 @@ $(SHARED_HEADERS)/user_constants.h: $(ARCH_DIR)/sys-$(SUBARCH)/user-offsets.s
 
 $(SHARED_HEADERS)/kern_constants.h:
         $(Q)mkdir -p $(dir $@)
-        $(Q)echo '#include "../../../../include/asm/asm-offsets.h"' >$@
+        $(Q)echo '#include "../../../../include/generated/asm-offsets.h"' >$@
 
 export SUBARCH USER_CFLAGS CFLAGS_NO_HARDENING OS HEADER_ARCH DEV_NULL_PATH
diff --git a/arch/um/drivers/mconsole_kern.c b/arch/um/drivers/mconsole_kern.c
index e14629c87de4..51069245b79a 100644
--- a/arch/um/drivers/mconsole_kern.c
+++ b/arch/um/drivers/mconsole_kern.c
@@ -6,6 +6,7 @@
 
 #include <linux/console.h>
 #include <linux/ctype.h>
+#include <linux/string.h>
 #include <linux/interrupt.h>
 #include <linux/list.h>
 #include <linux/mm.h>
@@ -131,7 +132,7 @@ void mconsole_proc(struct mc_request *req)
         char *ptr = req->request.data, *buf;
 
         ptr += strlen("proc");
-        while (isspace(*ptr)) ptr++;
+        ptr = skip_spaces(ptr);
 
         proc = get_fs_type("proc");
         if (proc == NULL) {
@@ -212,8 +213,7 @@ void mconsole_proc(struct mc_request *req)
         char *ptr = req->request.data;
 
         ptr += strlen("proc");
-        while (isspace(*ptr))
-                ptr++;
+        ptr = skip_spaces(ptr);
         snprintf(path, sizeof(path), "/proc/%s", ptr);
 
         fd = sys_open(path, 0, 0);
@@ -560,8 +560,7 @@ void mconsole_config(struct mc_request *req)
         int err;
 
         ptr += strlen("config");
-        while (isspace(*ptr))
-                ptr++;
+        ptr = skip_spaces(ptr);
         dev = mconsole_find_dev(ptr);
         if (dev == NULL) {
                 mconsole_reply(req, "Bad configuration option", 1, 0);
@@ -588,7 +587,7 @@ void mconsole_remove(struct mc_request *req)
         int err, start, end, n;
 
         ptr += strlen("remove");
-        while (isspace(*ptr)) ptr++;
+        ptr = skip_spaces(ptr);
         dev = mconsole_find_dev(ptr);
         if (dev == NULL) {
                 mconsole_reply(req, "Bad remove option", 1, 0);
@@ -712,7 +711,7 @@ void mconsole_sysrq(struct mc_request *req)
         char *ptr = req->request.data;
 
         ptr += strlen("sysrq");
-        while (isspace(*ptr)) ptr++;
+        ptr = skip_spaces(ptr);
 
         /*
          * With 'b', the system will shut down without a chance to reply,
@@ -757,8 +756,7 @@ void mconsole_stack(struct mc_request *req)
          */
 
         ptr += strlen("stack");
-        while (isspace(*ptr))
-                ptr++;
+        ptr = skip_spaces(ptr);
 
         /*
          * Should really check for multiple pids or reject bad args here
@@ -833,8 +831,8 @@ static int __init mconsole_init(void)
 
 __initcall(mconsole_init);
 
-static int write_proc_mconsole(struct file *file, const char __user *buffer,
-                               unsigned long count, void *data)
+static ssize_t mconsole_proc_write(struct file *file,
+                const char __user *buffer, size_t count, loff_t *pos)
 {
         char *buf;
 
@@ -855,6 +853,11 @@ static int write_proc_mconsole(struct file *file, const char __user *buffer,
         return count;
 }
 
+static const struct file_operations mconsole_proc_fops = {
+        .owner          = THIS_MODULE,
+        .write          = mconsole_proc_write,
+};
+
 static int create_proc_mconsole(void)
 {
         struct proc_dir_entry *ent;
@@ -862,15 +865,12 @@ static int create_proc_mconsole(void)
         if (notify_socket == NULL)
                 return 0;
 
-        ent = create_proc_entry("mconsole", S_IFREG | 0200, NULL);
+        ent = proc_create("mconsole", 0200, NULL, &mconsole_proc_fops);
         if (ent == NULL) {
                 printk(KERN_INFO "create_proc_mconsole : create_proc_entry "
                        "failed\n");
                 return 0;
         }
-
-        ent->read_proc = NULL;
-        ent->write_proc = write_proc_mconsole;
         return 0;
 }
 
diff --git a/arch/um/drivers/ubd_kern.c b/arch/um/drivers/ubd_kern.c
index 635d16d90a80..5ff554677f40 100644
--- a/arch/um/drivers/ubd_kern.c
+++ b/arch/um/drivers/ubd_kern.c
@@ -27,6 +27,7 @@
 #include "linux/init.h"
 #include "linux/cdrom.h"
 #include "linux/proc_fs.h"
+#include "linux/seq_file.h"
 #include "linux/ctype.h"
 #include "linux/capability.h"
 #include "linux/mm.h"
@@ -200,23 +201,25 @@ static void make_proc_ide(void)
         proc_ide = proc_mkdir("ide0", proc_ide_root);
 }
 
-static int proc_ide_read_media(char *page, char **start, off_t off, int count,
-                               int *eof, void *data)
+static int fake_ide_media_proc_show(struct seq_file *m, void *v)
 {
-        int len;
-
-        strcpy(page, "disk\n");
-        len = strlen("disk\n");
-        len -= off;
-        if (len < count){
-                *eof = 1;
-                if (len <= 0) return 0;
-        }
-        else len = count;
-        *start = page + off;
-        return len;
+        seq_puts(m, "disk\n");
+        return 0;
+}
+
+static int fake_ide_media_proc_open(struct inode *inode, struct file *file)
+{
+        return single_open(file, fake_ide_media_proc_show, NULL);
 }
 
+static const struct file_operations fake_ide_media_proc_fops = {
+        .owner          = THIS_MODULE,
+        .open           = fake_ide_media_proc_open,
+        .read           = seq_read,
+        .llseek         = seq_lseek,
+        .release        = single_release,
+};
+
 static void make_ide_entries(const char *dev_name)
 {
         struct proc_dir_entry *dir, *ent;
@@ -227,11 +230,8 @@ static void make_ide_entries(const char *dev_name)
         dir = proc_mkdir(dev_name, proc_ide);
         if(!dir) return;
 
-        ent = create_proc_entry("media", S_IFREG|S_IRUGO, dir);
+        ent = proc_create("media", S_IRUGO, dir, &fake_ide_media_proc_fops);
         if(!ent) return;
-        ent->data = NULL;
-        ent->read_proc = proc_ide_read_media;
-        ent->write_proc = NULL;
         snprintf(name, sizeof(name), "ide0/%s", dev_name);
         proc_symlink(dev_name, proc_ide_root, name);
 }
diff --git a/arch/um/include/asm/asm-offsets.h b/arch/um/include/asm/asm-offsets.h
new file mode 100644
index 000000000000..d370ee36a182
--- /dev/null
+++ b/arch/um/include/asm/asm-offsets.h
@@ -0,0 +1 @@
+#include <generated/asm-offsets.h>
diff --git a/arch/um/kernel/exitcode.c b/arch/um/kernel/exitcode.c
index 6540d2c9fbb7..829df49dee99 100644
--- a/arch/um/kernel/exitcode.c
+++ b/arch/um/kernel/exitcode.c
@@ -6,7 +6,9 @@
 #include <linux/ctype.h>
 #include <linux/init.h>
 #include <linux/kernel.h>
+#include <linux/module.h>
 #include <linux/proc_fs.h>
+#include <linux/seq_file.h>
 #include <linux/types.h>
 #include <asm/uaccess.h>
 
@@ -16,30 +18,26 @@
  */
 int uml_exitcode = 0;
 
-static int read_proc_exitcode(char *page, char **start, off_t off,
-                              int count, int *eof, void *data)
+static int exitcode_proc_show(struct seq_file *m, void *v)
 {
-        int len, val;
+        int val;
 
         /*
          * Save uml_exitcode in a local so that we don't need to guarantee
          * that sprintf accesses it atomically.
          */
         val = uml_exitcode;
-        len = sprintf(page, "%d\n", val);
-        len -= off;
-        if (len <= off+count)
-                *eof = 1;
-        *start = page + off;
-        if (len > count)
-                len = count;
-        if (len < 0)
-                len = 0;
-        return len;
+        seq_printf(m, "%d\n", val);
+        return 0;
+}
+
+static int exitcode_proc_open(struct inode *inode, struct file *file)
+{
+        return single_open(file, exitcode_proc_show, NULL);
 }
 
-static int write_proc_exitcode(struct file *file, const char __user *buffer,
-                               unsigned long count, void *data)
+static ssize_t exitcode_proc_write(struct file *file,
+                const char __user *buffer, size_t count, loff_t *pos)
 {
         char *end, buf[sizeof("nnnnn\0")];
         int tmp;
@@ -55,20 +53,25 @@ static int write_proc_exitcode(struct file *file, const char __user *buffer,
         return count;
 }
 
+static const struct file_operations exitcode_proc_fops = {
+        .owner          = THIS_MODULE,
+        .open           = exitcode_proc_open,
+        .read           = seq_read,
+        .llseek         = seq_lseek,
+        .release        = single_release,
+        .write          = exitcode_proc_write,
+};
+
 static int make_proc_exitcode(void)
 {
         struct proc_dir_entry *ent;
 
-        ent = create_proc_entry("exitcode", 0600, NULL);
+        ent = proc_create("exitcode", 0600, NULL, &exitcode_proc_fops);
         if (ent == NULL) {
                 printk(KERN_WARNING "make_proc_exitcode : Failed to register "
                        "/proc/exitcode\n");
                 return 0;
         }
-
-        ent->read_proc = read_proc_exitcode;
-        ent->write_proc = write_proc_exitcode;
-
         return 0;
 }
 
diff --git a/arch/um/kernel/irq.c b/arch/um/kernel/irq.c
index 039270b9b73b..89474ba0741e 100644
--- a/arch/um/kernel/irq.c
+++ b/arch/um/kernel/irq.c
@@ -34,7 +34,7 @@ int show_interrupts(struct seq_file *p, void *v)
         }
 
         if (i < NR_IRQS) {
-                spin_lock_irqsave(&irq_desc[i].lock, flags);
+                raw_spin_lock_irqsave(&irq_desc[i].lock, flags);
                 action = irq_desc[i].action;
                 if (!action)
                         goto skip;
@@ -53,7 +53,7 @@ int show_interrupts(struct seq_file *p, void *v)
 
                 seq_putc(p, '\n');
 skip:
-                spin_unlock_irqrestore(&irq_desc[i].lock, flags);
+                raw_spin_unlock_irqrestore(&irq_desc[i].lock, flags);
         } else if (i == NR_IRQS)
                 seq_putc(p, '\n');
 
diff --git a/arch/um/kernel/process.c b/arch/um/kernel/process.c
index 4a28a1568d85..2f910a1b7454 100644
--- a/arch/um/kernel/process.c
+++ b/arch/um/kernel/process.c
@@ -9,11 +9,13 @@
 #include <linux/hardirq.h>
 #include <linux/gfp.h>
 #include <linux/mm.h>
+#include <linux/module.h>
 #include <linux/personality.h>
 #include <linux/proc_fs.h>
 #include <linux/ptrace.h>
 #include <linux/random.h>
 #include <linux/sched.h>
+#include <linux/seq_file.h>
 #include <linux/tick.h>
 #include <linux/threads.h>
 #include <asm/current.h>
@@ -336,16 +338,19 @@ int get_using_sysemu(void)
         return atomic_read(&using_sysemu);
 }
 
-static int proc_read_sysemu(char *buf, char **start, off_t offset, int size,int *eof, void *data)
+static int sysemu_proc_show(struct seq_file *m, void *v)
 {
-        if (snprintf(buf, size, "%d\n", get_using_sysemu()) < size)
-                /* No overflow */
-                *eof = 1;
+        seq_printf(m, "%d\n", get_using_sysemu());
+        return 0;
+}
 
-        return strlen(buf);
+static int sysemu_proc_open(struct inode *inode, struct file *file)
+{
+        return single_open(file, sysemu_proc_show, NULL);
 }
 
-static int proc_write_sysemu(struct file *file,const char __user *buf, unsigned long count,void *data)
+static ssize_t sysemu_proc_write(struct file *file, const char __user *buf,
+                                 size_t count, loff_t *pos)
 {
         char tmp[2];
 
@@ -358,13 +363,22 @@ static int proc_write_sysemu(struct file *file,const char __user *buf, unsigned
         return count;
 }
 
+static const struct file_operations sysemu_proc_fops = {
+        .owner          = THIS_MODULE,
+        .open           = sysemu_proc_open,
+        .read           = seq_read,
+        .llseek         = seq_lseek,
+        .release        = single_release,
+        .write          = sysemu_proc_write,
+};
+
 int __init make_proc_sysemu(void)
 {
         struct proc_dir_entry *ent;
         if (!sysemu_supported)
                 return 0;
 
-        ent = create_proc_entry("sysemu", 0600, NULL);
+        ent = proc_create("sysemu", 0600, NULL, &sysemu_proc_fops);
 
         if (ent == NULL)
         {
@@ -372,9 +386,6 @@ int __init make_proc_sysemu(void)
                 return 0;
         }
 
-        ent->read_proc  = proc_read_sysemu;
-        ent->write_proc = proc_write_sysemu;
-
         return 0;
 }
 
diff --git a/arch/um/kernel/syscall.c b/arch/um/kernel/syscall.c
index a4625c7b2bf9..cccab850c27e 100644
--- a/arch/um/kernel/syscall.c
+++ b/arch/um/kernel/syscall.c
@@ -8,6 +8,7 @@
 #include "linux/mm.h"
 #include "linux/sched.h"
 #include "linux/utsname.h"
+#include "linux/syscalls.h"
 #include "asm/current.h"
 #include "asm/mman.h"
 #include "asm/uaccess.h"
@@ -37,31 +38,6 @@ long sys_vfork(void)
         return ret;
 }
 
-/* common code for old and new mmaps */
-long sys_mmap2(unsigned long addr, unsigned long len,
-               unsigned long prot, unsigned long flags,
-               unsigned long fd, unsigned long pgoff)
-{
-        long error = -EBADF;
-        struct file * file = NULL;
-
-        flags &= ~(MAP_EXECUTABLE | MAP_DENYWRITE);
-        if (!(flags & MAP_ANONYMOUS)) {
-                file = fget(fd);
-                if (!file)
-                        goto out;
-        }
-
-        down_write(&current->mm->mmap_sem);
-        error = do_mmap_pgoff(file, addr, len, prot, flags, pgoff);
-        up_write(&current->mm->mmap_sem);
-
-        if (file)
-                fput(file);
- out:
-        return error;
-}
-
 long old_mmap(unsigned long addr, unsigned long len,
               unsigned long prot, unsigned long flags,
               unsigned long fd, unsigned long offset)
@@ -70,7 +46,7 @@ long old_mmap(unsigned long addr, unsigned long len,
         if (offset & ~PAGE_MASK)
                 goto out;
 
-        err = sys_mmap2(addr, len, prot, flags, fd, offset >> PAGE_SHIFT);
+        err = sys_mmap_pgoff(addr, len, prot, flags, fd, offset >> PAGE_SHIFT);
  out:
         return err;
 }
diff --git a/arch/um/sys-i386/asm/elf.h b/arch/um/sys-i386/asm/elf.h
index d0da9d7c5371..770885472ed4 100644
--- a/arch/um/sys-i386/asm/elf.h
+++ b/arch/um/sys-i386/asm/elf.h
@@ -48,7 +48,6 @@ typedef struct user_i387_struct elf_fpregset_t;
         PT_REGS_EAX(regs) = 0; \
 } while (0)
 
-#define USE_ELF_CORE_DUMP
 #define ELF_EXEC_PAGESIZE 4096
 
 #define ELF_ET_DYN_BASE (2 * TASK_SIZE / 3)
diff --git a/arch/um/sys-i386/shared/sysdep/syscalls.h b/arch/um/sys-i386/shared/sysdep/syscalls.h
index 905698197e35..e7787679e317 100644
--- a/arch/um/sys-i386/shared/sysdep/syscalls.h
+++ b/arch/um/sys-i386/shared/sysdep/syscalls.h
@@ -20,7 +20,3 @@ extern syscall_handler_t *sys_call_table[];
 #define EXECUTE_SYSCALL(syscall, regs) \
         ((long (*)(struct syscall_args)) \
          (*sys_call_table[syscall]))(SYSCALL_ARGS(&regs->regs))
-
-extern long sys_mmap2(unsigned long addr, unsigned long len,
-                      unsigned long prot, unsigned long flags,
-                      unsigned long fd, unsigned long pgoff);
diff --git a/arch/um/sys-ppc/asm/elf.h b/arch/um/sys-ppc/asm/elf.h
index af9463cd8ce5..8aacaf56508d 100644
--- a/arch/um/sys-ppc/asm/elf.h
+++ b/arch/um/sys-ppc/asm/elf.h
@@ -17,8 +17,6 @@ extern long elf_aux_hwcap;
 #define ELF_CLASS ELFCLASS32
 #endif
 
-#define USE_ELF_CORE_DUMP
-
 #define R_386_NONE      0
 #define R_386_32        1
 #define R_386_PC32      2
diff --git a/arch/um/sys-x86_64/asm/elf.h b/arch/um/sys-x86_64/asm/elf.h
index 04b9e87c8dad..49655c83efd2 100644
--- a/arch/um/sys-x86_64/asm/elf.h
+++ b/arch/um/sys-x86_64/asm/elf.h
@@ -104,7 +104,6 @@ extern int elf_core_copy_fpregs(struct task_struct *t, elf_fpregset_t *fpu);
         clear_thread_flag(TIF_IA32);
 #endif
 
-#define USE_ELF_CORE_DUMP
 #define ELF_EXEC_PAGESIZE 4096
 
 #define ELF_ET_DYN_BASE (2 * TASK_SIZE / 3)
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index 32a1918e1b88..3b2a5aca4edb 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -2012,18 +2012,9 @@ config SCx200HR_TIMER
           processor goes idle (as is done by the scheduler).  The
           other workaround is idle=poll boot option.
 
-config GEODE_MFGPT_TIMER
-        def_bool y
-        prompt "Geode Multi-Function General Purpose Timer (MFGPT) events"
-        depends on MGEODE_LX && GENERIC_TIME && GENERIC_CLOCKEVENTS
-        ---help---
-          This driver provides a clock event source based on the MFGPT
-          timer(s) in the CS5535 and CS5536 companion chip for the geode.
-          MFGPTs have a better resolution and max interval than the
-          generic PIT, and are suitable for use as high-res timers.
-
 config OLPC
         bool "One Laptop Per Child support"
+        select GPIOLIB
         default n
         ---help---
           Add support for detecting the unique features of the OLPC
diff --git a/arch/x86/Kconfig.debug b/arch/x86/Kconfig.debug
index 731318e5ac1d..bc01e3ebfeb2 100644
--- a/arch/x86/Kconfig.debug
+++ b/arch/x86/Kconfig.debug
@@ -187,8 +187,8 @@ config HAVE_MMIOTRACE_SUPPORT
         def_bool y
 
 config X86_DECODER_SELFTEST
-     bool "x86 instruction decoder selftest"
-     depends on DEBUG_KERNEL
+        bool "x86 instruction decoder selftest"
+        depends on DEBUG_KERNEL && KPROBES
         ---help---
          Perform x86 instruction decoder selftests at build time.
          This option is useful for checking the sanity of x86 instruction
diff --git a/arch/x86/boot/header.S b/arch/x86/boot/header.S
index b31cc54b4641..93e689f4bd86 100644
--- a/arch/x86/boot/header.S
+++ b/arch/x86/boot/header.S
@@ -16,7 +16,7 @@
  */
 
 #include <asm/segment.h>
-#include <linux/utsrelease.h>
+#include <generated/utsrelease.h>
 #include <asm/boot.h>
 #include <asm/e820.h>
 #include <asm/page_types.h>
diff --git a/arch/x86/boot/version.c b/arch/x86/boot/version.c
index 2723d9b5ce43..2b15aa488ffb 100644
--- a/arch/x86/boot/version.c
+++ b/arch/x86/boot/version.c
@@ -13,8 +13,8 @@
  */
 
 #include "boot.h"
-#include <linux/utsrelease.h>
-#include <linux/compile.h>
+#include <generated/utsrelease.h>
+#include <generated/compile.h>
 
 const char kernel_version[] =
         UTS_RELEASE " (" LINUX_COMPILE_BY "@" LINUX_COMPILE_HOST ") "
diff --git a/arch/x86/ia32/ia32entry.S b/arch/x86/ia32/ia32entry.S
index 4eefdca9832b..53147ad85b96 100644
--- a/arch/x86/ia32/ia32entry.S
+++ b/arch/x86/ia32/ia32entry.S
@@ -696,7 +696,7 @@ ia32_sys_call_table:
         .quad quiet_ni_syscall          /* streams2 */
         .quad stub32_vfork            /* 190 */
         .quad compat_sys_getrlimit
-        .quad sys32_mmap2
+        .quad sys_mmap_pgoff
         .quad sys32_truncate64
         .quad sys32_ftruncate64
         .quad sys32_stat64              /* 195 */
diff --git a/arch/x86/ia32/sys_ia32.c b/arch/x86/ia32/sys_ia32.c
index df82c0e48ded..422572c77923 100644
--- a/arch/x86/ia32/sys_ia32.c
+++ b/arch/x86/ia32/sys_ia32.c
@@ -155,9 +155,6 @@ struct mmap_arg_struct {
 asmlinkage long sys32_mmap(struct mmap_arg_struct __user *arg)
 {
         struct mmap_arg_struct a;
-        struct file *file = NULL;
-        unsigned long retval;
-        struct mm_struct *mm ;
 
         if (copy_from_user(&a, arg, sizeof(a)))
                 return -EFAULT;
@@ -165,22 +162,8 @@ asmlinkage long sys32_mmap(struct mmap_arg_struct __user *arg)
         if (a.offset & ~PAGE_MASK)
                 return -EINVAL;
 
-        if (!(a.flags & MAP_ANONYMOUS)) {
-                file = fget(a.fd);
-                if (!file)
-                        return -EBADF;
-        }
-
-        mm = current->mm;
-        down_write(&mm->mmap_sem);
-        retval = do_mmap_pgoff(file, a.addr, a.len, a.prot, a.flags,
+        return sys_mmap_pgoff(a.addr, a.len, a.prot, a.flags, a.fd,
                                a.offset>>PAGE_SHIFT);
-        if (file)
-                fput(file);
-
-        up_write(&mm->mmap_sem);
-
-        return retval;
 }
 
 asmlinkage long sys32_mprotect(unsigned long start, size_t len,
@@ -483,30 +466,6 @@ asmlinkage long sys32_sendfile(int out_fd, int in_fd,
         return ret;
 }
 
-asmlinkage long sys32_mmap2(unsigned long addr, unsigned long len,
-                            unsigned long prot, unsigned long flags,
-                            unsigned long fd, unsigned long pgoff)
-{
-        struct mm_struct *mm = current->mm;
-        unsigned long error;
-        struct file *file = NULL;
-
-        flags &= ~(MAP_EXECUTABLE | MAP_DENYWRITE);
-        if (!(flags & MAP_ANONYMOUS)) {
-                file = fget(fd);
-                if (!file)
-                        return -EBADF;
-        }
-
-        down_write(&mm->mmap_sem);
-        error = do_mmap_pgoff(file, addr, len, prot, flags, pgoff);
-        up_write(&mm->mmap_sem);
-
-        if (file)
-                fput(file);
-        return error;
-}
-
 asmlinkage long sys32_olduname(struct oldold_utsname __user *name)
 {
         char *arch = "x86_64";
diff --git a/arch/x86/include/asm/asm-offsets.h b/arch/x86/include/asm/asm-offsets.h
new file mode 100644
index 000000000000..d370ee36a182
--- /dev/null
+++ b/arch/x86/include/asm/asm-offsets.h
@@ -0,0 +1 @@
+#include <generated/asm-offsets.h>
diff --git a/arch/x86/include/asm/dma-mapping.h b/arch/x86/include/asm/dma-mapping.h
index 0f6c02f3b7d4..ac91eed21061 100644
--- a/arch/x86/include/asm/dma-mapping.h
+++ b/arch/x86/include/asm/dma-mapping.h
@@ -67,7 +67,7 @@ static inline bool dma_capable(struct device *dev, dma_addr_t addr, size_t size)
         if (!dev->dma_mask)
                 return 0;
 
-        return addr + size <= *dev->dma_mask;
+        return addr + size - 1 <= *dev->dma_mask;
 }
 
 static inline dma_addr_t phys_to_dma(struct device *dev, phys_addr_t paddr)
diff --git a/arch/x86/include/asm/elf.h b/arch/x86/include/asm/elf.h
index 8a024babe5e6..b4501ee223ad 100644
--- a/arch/x86/include/asm/elf.h
+++ b/arch/x86/include/asm/elf.h
@@ -239,7 +239,6 @@ extern int force_personality32;
 #endif /* !CONFIG_X86_32 */
 
 #define CORE_DUMP_USE_REGSET
-#define USE_ELF_CORE_DUMP
 #define ELF_EXEC_PAGESIZE       4096
 
 /* This is the location that an ET_DYN program is loaded if exec'ed.  Typical
diff --git a/arch/x86/include/asm/geode.h b/arch/x86/include/asm/geode.h
index ad3c2ed75481..7cd73552a4e8 100644
--- a/arch/x86/include/asm/geode.h
+++ b/arch/x86/include/asm/geode.h
@@ -12,160 +12,7 @@
 
 #include <asm/processor.h>
 #include <linux/io.h>
-
-/* Generic southbridge functions */
-
-#define GEODE_DEV_PMS 0
-#define GEODE_DEV_ACPI 1
-#define GEODE_DEV_GPIO 2
-#define GEODE_DEV_MFGPT 3
-
-extern int geode_get_dev_base(unsigned int dev);
-
-/* Useful macros */
-#define geode_pms_base()        geode_get_dev_base(GEODE_DEV_PMS)
-#define geode_acpi_base()       geode_get_dev_base(GEODE_DEV_ACPI)
-#define geode_gpio_base()       geode_get_dev_base(GEODE_DEV_GPIO)
-#define geode_mfgpt_base()      geode_get_dev_base(GEODE_DEV_MFGPT)
-
-/* MSRS */
-
-#define MSR_GLIU_P2D_RO0        0x10000029
-
-#define MSR_LX_GLD_MSR_CONFIG   0x48002001
-#define MSR_LX_MSR_PADSEL       0x48002011      /* NOT 0x48000011; the data
-                                                 * sheet has the wrong value */
-#define MSR_GLCP_SYS_RSTPLL     0x4C000014
-#define MSR_GLCP_DOTPLL         0x4C000015
-
-#define MSR_LBAR_SMB            0x5140000B
-#define MSR_LBAR_GPIO           0x5140000C
-#define MSR_LBAR_MFGPT          0x5140000D
-#define MSR_LBAR_ACPI           0x5140000E
-#define MSR_LBAR_PMS            0x5140000F
-
-#define MSR_DIVIL_SOFT_RESET    0x51400017
-
-#define MSR_PIC_YSEL_LOW        0x51400020
-#define MSR_PIC_YSEL_HIGH       0x51400021
-#define MSR_PIC_ZSEL_LOW        0x51400022
-#define MSR_PIC_ZSEL_HIGH       0x51400023
-#define MSR_PIC_IRQM_LPC        0x51400025
-
-#define MSR_MFGPT_IRQ           0x51400028
-#define MSR_MFGPT_NR            0x51400029
-#define MSR_MFGPT_SETUP         0x5140002B
-
-#define MSR_LX_SPARE_MSR        0x80000011      /* DC-specific */
-
-#define MSR_GX_GLD_MSR_CONFIG   0xC0002001
-#define MSR_GX_MSR_PADSEL       0xC0002011
-
-/* Resource Sizes */
-
-#define LBAR_GPIO_SIZE          0xFF
-#define LBAR_MFGPT_SIZE         0x40
-#define LBAR_ACPI_SIZE          0x40
-#define LBAR_PMS_SIZE           0x80
-
-/* ACPI registers (PMS block) */
-
-/*
- * PM1_EN is only valid when VSA is enabled for 16 bit reads.
- * When VSA is not enabled, *always* read both PM1_STS and PM1_EN
- * with a 32 bit read at offset 0x0
- */
-
-#define PM1_STS                 0x00
-#define PM1_EN                  0x02
-#define PM1_CNT                 0x08
-#define PM2_CNT                 0x0C
-#define PM_TMR                  0x10
-#define PM_GPE0_STS             0x18
-#define PM_GPE0_EN              0x1C
-
-/* PMC registers (PMS block) */
-
-#define PM_SSD                  0x00
-#define PM_SCXA                 0x04
-#define PM_SCYA                 0x08
-#define PM_OUT_SLPCTL           0x0C
-#define PM_SCLK                 0x10
-#define PM_SED                  0x1
-#define PM_SCXD                 0x18
-#define PM_SCYD                 0x1C
-#define PM_IN_SLPCTL            0x20
-#define PM_WKD                  0x30
-#define PM_WKXD                 0x34
-#define PM_RD                   0x38
-#define PM_WKXA                 0x3C
-#define PM_FSD                  0x40
-#define PM_TSD                  0x44
-#define PM_PSD                  0x48
-#define PM_NWKD                 0x4C
-#define PM_AWKD                 0x50
-#define PM_SSC                  0x54
-
-/* VSA2 magic values */
-
-#define VSA_VRC_INDEX           0xAC1C
-#define VSA_VRC_DATA            0xAC1E
-#define VSA_VR_UNLOCK           0xFC53  /* unlock virtual register */
-#define VSA_VR_SIGNATURE        0x0003
-#define VSA_VR_MEM_SIZE         0x0200
-#define AMD_VSA_SIG             0x4132  /* signature is ascii 'VSA2' */
-#define GSW_VSA_SIG             0x534d  /* General Software signature */
-/* GPIO */
-
-#define GPIO_OUTPUT_VAL         0x00
-#define GPIO_OUTPUT_ENABLE      0x04
-#define GPIO_OUTPUT_OPEN_DRAIN  0x08
-#define GPIO_OUTPUT_INVERT      0x0C
-#define GPIO_OUTPUT_AUX1        0x10
-#define GPIO_OUTPUT_AUX2        0x14
-#define GPIO_PULL_UP            0x18
-#define GPIO_PULL_DOWN          0x1C
-#define GPIO_INPUT_ENABLE       0x20
-#define GPIO_INPUT_INVERT       0x24
-#define GPIO_INPUT_FILTER       0x28
-#define GPIO_INPUT_EVENT_COUNT  0x2C
-#define GPIO_READ_BACK          0x30
-#define GPIO_INPUT_AUX1         0x34
-#define GPIO_EVENTS_ENABLE      0x38
-#define GPIO_LOCK_ENABLE        0x3C
-#define GPIO_POSITIVE_EDGE_EN   0x40
-#define GPIO_NEGATIVE_EDGE_EN   0x44
-#define GPIO_POSITIVE_EDGE_STS  0x48
-#define GPIO_NEGATIVE_EDGE_STS  0x4C
-
-#define GPIO_MAP_X              0xE0
-#define GPIO_MAP_Y              0xE4
-#define GPIO_MAP_Z              0xE8
-#define GPIO_MAP_W              0xEC
-
-static inline u32 geode_gpio(unsigned int nr)
-{
-        BUG_ON(nr > 28);
-        return 1 << nr;
-}
-
-extern void geode_gpio_set(u32, unsigned int);
-extern void geode_gpio_clear(u32, unsigned int);
-extern int geode_gpio_isset(u32, unsigned int);
-extern void geode_gpio_setup_event(unsigned int, int, int);
-extern void geode_gpio_set_irq(unsigned int, unsigned int);
-
-static inline void geode_gpio_event_irq(unsigned int gpio, int pair)
-{
-        geode_gpio_setup_event(gpio, pair, 0);
-}
-
-static inline void geode_gpio_event_pme(unsigned int gpio, int pair)
-{
-        geode_gpio_setup_event(gpio, pair, 1);
-}
-
-/* Specific geode tests */
+#include <linux/cs5535.h>
 
 static inline int is_geode_gx(void)
 {
@@ -186,68 +33,4 @@ static inline int is_geode(void)
         return (is_geode_gx() || is_geode_lx());
 }
 
-#ifdef CONFIG_MGEODE_LX
-extern int geode_has_vsa2(void);
-#else
-static inline int geode_has_vsa2(void)
-{
-        return 0;
-}
-#endif
-
-/* MFGPTs */
-
-#define MFGPT_MAX_TIMERS        8
-#define MFGPT_TIMER_ANY         (-1)
-
-#define MFGPT_DOMAIN_WORKING    1
-#define MFGPT_DOMAIN_STANDBY    2
-#define MFGPT_DOMAIN_ANY        (MFGPT_DOMAIN_WORKING | MFGPT_DOMAIN_STANDBY)
-
-#define MFGPT_CMP1              0
-#define MFGPT_CMP2              1
-
-#define MFGPT_EVENT_IRQ         0
-#define MFGPT_EVENT_NMI         1
-#define MFGPT_EVENT_RESET       3
-
-#define MFGPT_REG_CMP1          0
-#define MFGPT_REG_CMP2          2
-#define MFGPT_REG_COUNTER       4
-#define MFGPT_REG_SETUP         6
-
-#define MFGPT_SETUP_CNTEN       (1 << 15)
-#define MFGPT_SETUP_CMP2        (1 << 14)
-#define MFGPT_SETUP_CMP1        (1 << 13)
-#define MFGPT_SETUP_SETUP       (1 << 12)
-#define MFGPT_SETUP_STOPEN      (1 << 11)
-#define MFGPT_SETUP_EXTEN       (1 << 10)
-#define MFGPT_SETUP_REVEN       (1 << 5)
-#define MFGPT_SETUP_CLKSEL      (1 << 4)
-
-static inline void geode_mfgpt_write(int timer, u16 reg, u16 value)
-{
-        u32 base = geode_get_dev_base(GEODE_DEV_MFGPT);
-        outw(value, base + reg + (timer * 8));
-}
-
-static inline u16 geode_mfgpt_read(int timer, u16 reg)
-{
-        u32 base = geode_get_dev_base(GEODE_DEV_MFGPT);
-        return inw(base + reg + (timer * 8));
-}
-
-extern int geode_mfgpt_toggle_event(int timer, int cmp, int event, int enable);
-extern int geode_mfgpt_set_irq(int timer, int cmp, int *irq, int enable);
-extern int geode_mfgpt_alloc_timer(int timer, int domain);
-
-#define geode_mfgpt_setup_irq(t, c, i) geode_mfgpt_set_irq((t), (c), (i), 1)
-#define geode_mfgpt_release_irq(t, c, i) geode_mfgpt_set_irq((t), (c), (i), 0)
-
-#ifdef CONFIG_GEODE_MFGPT_TIMER
-extern int __init mfgpt_timer_setup(void);
-#else
-static inline int mfgpt_timer_setup(void) { return 0; }
-#endif
-
 #endif /* _ASM_X86_GEODE_H */
diff --git a/arch/x86/include/asm/olpc.h b/arch/x86/include/asm/olpc.h
index 834a30295fab..3a57385d9fa7 100644
--- a/arch/x86/include/asm/olpc.h
+++ b/arch/x86/include/asm/olpc.h
@@ -120,7 +120,7 @@ extern int olpc_ec_mask_unset(uint8_t bits);
 
 /* GPIO assignments */
 
-#define OLPC_GPIO_MIC_AC        geode_gpio(1)
+#define OLPC_GPIO_MIC_AC        1
 #define OLPC_GPIO_DCON_IRQ      geode_gpio(7)
 #define OLPC_GPIO_THRM_ALRM     geode_gpio(10)
 #define OLPC_GPIO_SMB_CLK       geode_gpio(14)
diff --git a/arch/x86/include/asm/paravirt.h b/arch/x86/include/asm/paravirt.h
index efb38994859c..dd59a85a918f 100644
--- a/arch/x86/include/asm/paravirt.h
+++ b/arch/x86/include/asm/paravirt.h
@@ -731,34 +731,34 @@ static inline void __set_fixmap(unsigned /* enum fixed_addresses */ idx,
 
 #if defined(CONFIG_SMP) && defined(CONFIG_PARAVIRT_SPINLOCKS)
 
-static inline int __raw_spin_is_locked(struct raw_spinlock *lock)
+static inline int arch_spin_is_locked(struct arch_spinlock *lock)
 {
         return PVOP_CALL1(int, pv_lock_ops.spin_is_locked, lock);
 }
 
-static inline int __raw_spin_is_contended(struct raw_spinlock *lock)
+static inline int arch_spin_is_contended(struct arch_spinlock *lock)
 {
         return PVOP_CALL1(int, pv_lock_ops.spin_is_contended, lock);
 }
-#define __raw_spin_is_contended __raw_spin_is_contended
+#define arch_spin_is_contended  arch_spin_is_contended
 
-static __always_inline void __raw_spin_lock(struct raw_spinlock *lock)
+static __always_inline void arch_spin_lock(struct arch_spinlock *lock)
 {
         PVOP_VCALL1(pv_lock_ops.spin_lock, lock);
 }
 
-static __always_inline void __raw_spin_lock_flags(struct raw_spinlock *lock,
+static __always_inline void arch_spin_lock_flags(struct arch_spinlock *lock,
                                                   unsigned long flags)
 {
         PVOP_VCALL2(pv_lock_ops.spin_lock_flags, lock, flags);
 }
 
-static __always_inline int __raw_spin_trylock(struct raw_spinlock *lock)
+static __always_inline int arch_spin_trylock(struct arch_spinlock *lock)
 {
         return PVOP_CALL1(int, pv_lock_ops.spin_trylock, lock);
 }
 
-static __always_inline void __raw_spin_unlock(struct raw_spinlock *lock)
+static __always_inline void arch_spin_unlock(struct arch_spinlock *lock)
 {
         PVOP_VCALL1(pv_lock_ops.spin_unlock, lock);
 }
diff --git a/arch/x86/include/asm/paravirt_types.h b/arch/x86/include/asm/paravirt_types.h
index 9357473c8da0..b1e70d51e40c 100644
--- a/arch/x86/include/asm/paravirt_types.h
+++ b/arch/x86/include/asm/paravirt_types.h
@@ -318,14 +318,14 @@ struct pv_mmu_ops {
                            phys_addr_t phys, pgprot_t flags);
 };
 
-struct raw_spinlock;
+struct arch_spinlock;
 struct pv_lock_ops {
-        int (*spin_is_locked)(struct raw_spinlock *lock);
-        int (*spin_is_contended)(struct raw_spinlock *lock);
-        void (*spin_lock)(struct raw_spinlock *lock);
-        void (*spin_lock_flags)(struct raw_spinlock *lock, unsigned long flags);
-        int (*spin_trylock)(struct raw_spinlock *lock);
-        void (*spin_unlock)(struct raw_spinlock *lock);
+        int (*spin_is_locked)(struct arch_spinlock *lock);
+        int (*spin_is_contended)(struct arch_spinlock *lock);
+        void (*spin_lock)(struct arch_spinlock *lock);
+        void (*spin_lock_flags)(struct arch_spinlock *lock, unsigned long flags);
+        int (*spin_trylock)(struct arch_spinlock *lock);
+        void (*spin_unlock)(struct arch_spinlock *lock);
 };
 
 /* This contains all the paravirt structures: we get a convenient
diff --git a/arch/x86/include/asm/pci_x86.h b/arch/x86/include/asm/pci_x86.h
index b399988eee3a..b4bf9a942ed0 100644
--- a/arch/x86/include/asm/pci_x86.h
+++ b/arch/x86/include/asm/pci_x86.h
@@ -118,11 +118,27 @@ extern int __init pcibios_init(void);
 
 /* pci-mmconfig.c */
 
+/* "PCI MMCONFIG %04x [bus %02x-%02x]" */
+#define PCI_MMCFG_RESOURCE_NAME_LEN (22 + 4 + 2 + 2)
+
+struct pci_mmcfg_region {
+        struct list_head list;
+        struct resource res;
+        u64 address;
+        char __iomem *virt;
+        u16 segment;
+        u8 start_bus;
+        u8 end_bus;
+        char name[PCI_MMCFG_RESOURCE_NAME_LEN];
+};
+
 extern int __init pci_mmcfg_arch_init(void);
 extern void __init pci_mmcfg_arch_free(void);
+extern struct pci_mmcfg_region *pci_mmconfig_lookup(int segment, int bus);
+
+extern struct list_head pci_mmcfg_list;
 
-extern struct acpi_mcfg_allocation *pci_mmcfg_config;
-extern int pci_mmcfg_config_num;
+#define PCI_MMCFG_BUS_OFFSET(bus)      ((bus) << 20)
 
 /*
  * AMD Fam10h CPUs are buggy, and cannot access MMIO config space
diff --git a/arch/x86/include/asm/percpu.h b/arch/x86/include/asm/percpu.h
index b65a36defeb7..0c44196b78ac 100644
--- a/arch/x86/include/asm/percpu.h
+++ b/arch/x86/include/asm/percpu.h
@@ -74,31 +74,31 @@ extern void __bad_percpu_size(void);
 
 #define percpu_to_op(op, var, val)                      \
 do {                                                    \
-        typedef typeof(var) T__;                        \
+        typedef typeof(var) pto_T__;                    \
         if (0) {                                        \
-                T__ tmp__;                              \
-                tmp__ = (val);                          \
+                pto_T__ pto_tmp__;                      \
+                pto_tmp__ = (val);                      \
         }                                               \
         switch (sizeof(var)) {                          \
         case 1:                                         \
                 asm(op "b %1,"__percpu_arg(0)           \
                     : "+m" (var)                        \
-                    : "qi" ((T__)(val)));               \
+                    : "qi" ((pto_T__)(val)));           \
                 break;                                  \
         case 2:                                         \
                 asm(op "w %1,"__percpu_arg(0)           \
                     : "+m" (var)                        \
-                    : "ri" ((T__)(val)));               \
+                    : "ri" ((pto_T__)(val)));           \
                 break;                                  \
         case 4:                                         \
                 asm(op "l %1,"__percpu_arg(0)           \
                     : "+m" (var)                        \
-                    : "ri" ((T__)(val)));               \
+                    : "ri" ((pto_T__)(val)));           \
                 break;                                  \
         case 8:                                         \
                 asm(op "q %1,"__percpu_arg(0)           \
                     : "+m" (var)                        \
-                    : "re" ((T__)(val)));               \
+                    : "re" ((pto_T__)(val)));           \
                 break;                                  \
         default: __bad_percpu_size();                   \
         }                                               \
@@ -106,31 +106,31 @@ do {							\
 
 #define percpu_from_op(op, var, constraint)             \
 ({                                                      \
-        typeof(var) ret__;                              \
+        typeof(var) pfo_ret__;                          \
         switch (sizeof(var)) {                          \
         case 1:                                         \
                 asm(op "b "__percpu_arg(1)",%0"         \
-                    : "=q" (ret__)                      \
+                    : "=q" (pfo_ret__)                  \
                     : constraint);                      \
                 break;                                  \
         case 2:                                         \
                 asm(op "w "__percpu_arg(1)",%0"         \
-                    : "=r" (ret__)                      \
+                    : "=r" (pfo_ret__)                  \
                     : constraint);                      \
                 break;                                  \
         case 4:                                         \
                 asm(op "l "__percpu_arg(1)",%0"         \
-                    : "=r" (ret__)                      \
+                    : "=r" (pfo_ret__)                  \
                     : constraint);                      \
                 break;                                  \
         case 8:                                         \
                 asm(op "q "__percpu_arg(1)",%0"         \
-                    : "=r" (ret__)                      \
+                    : "=r" (pfo_ret__)                  \
                     : constraint);                      \
                 break;                                  \
         default: __bad_percpu_size();                   \
         }                                               \
-        ret__;                                          \
+        pfo_ret__;                                      \
 })
 
 /*
@@ -153,6 +153,84 @@ do {							\
 #define percpu_or(var, val)     percpu_to_op("or", per_cpu__##var, val)
 #define percpu_xor(var, val)    percpu_to_op("xor", per_cpu__##var, val)
 
+#define __this_cpu_read_1(pcp)          percpu_from_op("mov", (pcp), "m"(pcp))
+#define __this_cpu_read_2(pcp)          percpu_from_op("mov", (pcp), "m"(pcp))
+#define __this_cpu_read_4(pcp)          percpu_from_op("mov", (pcp), "m"(pcp))
+
+#define __this_cpu_write_1(pcp, val)    percpu_to_op("mov", (pcp), val)
+#define __this_cpu_write_2(pcp, val)    percpu_to_op("mov", (pcp), val)
+#define __this_cpu_write_4(pcp, val)    percpu_to_op("mov", (pcp), val)
+#define __this_cpu_add_1(pcp, val)      percpu_to_op("add", (pcp), val)
+#define __this_cpu_add_2(pcp, val)      percpu_to_op("add", (pcp), val)
+#define __this_cpu_add_4(pcp, val)      percpu_to_op("add", (pcp), val)
+#define __this_cpu_and_1(pcp, val)      percpu_to_op("and", (pcp), val)
+#define __this_cpu_and_2(pcp, val)      percpu_to_op("and", (pcp), val)
+#define __this_cpu_and_4(pcp, val)      percpu_to_op("and", (pcp), val)
+#define __this_cpu_or_1(pcp, val)       percpu_to_op("or", (pcp), val)
+#define __this_cpu_or_2(pcp, val)       percpu_to_op("or", (pcp), val)
+#define __this_cpu_or_4(pcp, val)       percpu_to_op("or", (pcp), val)
+#define __this_cpu_xor_1(pcp, val)      percpu_to_op("xor", (pcp), val)
+#define __this_cpu_xor_2(pcp, val)      percpu_to_op("xor", (pcp), val)
+#define __this_cpu_xor_4(pcp, val)      percpu_to_op("xor", (pcp), val)
+
+#define this_cpu_read_1(pcp)            percpu_from_op("mov", (pcp), "m"(pcp))
+#define this_cpu_read_2(pcp)            percpu_from_op("mov", (pcp), "m"(pcp))
+#define this_cpu_read_4(pcp)            percpu_from_op("mov", (pcp), "m"(pcp))
+#define this_cpu_write_1(pcp, val)      percpu_to_op("mov", (pcp), val)
+#define this_cpu_write_2(pcp, val)      percpu_to_op("mov", (pcp), val)
+#define this_cpu_write_4(pcp, val)      percpu_to_op("mov", (pcp), val)
+#define this_cpu_add_1(pcp, val)        percpu_to_op("add", (pcp), val)
+#define this_cpu_add_2(pcp, val)        percpu_to_op("add", (pcp), val)
+#define this_cpu_add_4(pcp, val)        percpu_to_op("add", (pcp), val)
+#define this_cpu_and_1(pcp, val)        percpu_to_op("and", (pcp), val)
+#define this_cpu_and_2(pcp, val)        percpu_to_op("and", (pcp), val)
+#define this_cpu_and_4(pcp, val)        percpu_to_op("and", (pcp), val)
+#define this_cpu_or_1(pcp, val)         percpu_to_op("or", (pcp), val)
+#define this_cpu_or_2(pcp, val)         percpu_to_op("or", (pcp), val)
+#define this_cpu_or_4(pcp, val)         percpu_to_op("or", (pcp), val)
+#define this_cpu_xor_1(pcp, val)        percpu_to_op("xor", (pcp), val)
+#define this_cpu_xor_2(pcp, val)        percpu_to_op("xor", (pcp), val)
+#define this_cpu_xor_4(pcp, val)        percpu_to_op("xor", (pcp), val)
+
+#define irqsafe_cpu_add_1(pcp, val)     percpu_to_op("add", (pcp), val)
+#define irqsafe_cpu_add_2(pcp, val)     percpu_to_op("add", (pcp), val)
+#define irqsafe_cpu_add_4(pcp, val)     percpu_to_op("add", (pcp), val)
+#define irqsafe_cpu_and_1(pcp, val)     percpu_to_op("and", (pcp), val)
+#define irqsafe_cpu_and_2(pcp, val)     percpu_to_op("and", (pcp), val)
+#define irqsafe_cpu_and_4(pcp, val)     percpu_to_op("and", (pcp), val)
+#define irqsafe_cpu_or_1(pcp, val)      percpu_to_op("or", (pcp), val)
+#define irqsafe_cpu_or_2(pcp, val)      percpu_to_op("or", (pcp), val)
+#define irqsafe_cpu_or_4(pcp, val)      percpu_to_op("or", (pcp), val)
+#define irqsafe_cpu_xor_1(pcp, val)     percpu_to_op("xor", (pcp), val)
+#define irqsafe_cpu_xor_2(pcp, val)     percpu_to_op("xor", (pcp), val)
+#define irqsafe_cpu_xor_4(pcp, val)     percpu_to_op("xor", (pcp), val)
+
+/*
+ * Per cpu atomic 64 bit operations are only available under 64 bit.
+ * 32 bit must fall back to generic operations.
+ */
+#ifdef CONFIG_X86_64
+#define __this_cpu_read_8(pcp)          percpu_from_op("mov", (pcp), "m"(pcp))
+#define __this_cpu_write_8(pcp, val)    percpu_to_op("mov", (pcp), val)
+#define __this_cpu_add_8(pcp, val)      percpu_to_op("add", (pcp), val)
+#define __this_cpu_and_8(pcp, val)      percpu_to_op("and", (pcp), val)
+#define __this_cpu_or_8(pcp, val)       percpu_to_op("or", (pcp), val)
+#define __this_cpu_xor_8(pcp, val)      percpu_to_op("xor", (pcp), val)
+
+#define this_cpu_read_8(pcp)            percpu_from_op("mov", (pcp), "m"(pcp))
+#define this_cpu_write_8(pcp, val)      percpu_to_op("mov", (pcp), val)
+#define this_cpu_add_8(pcp, val)        percpu_to_op("add", (pcp), val)
+#define this_cpu_and_8(pcp, val)        percpu_to_op("and", (pcp), val)
+#define this_cpu_or_8(pcp, val)         percpu_to_op("or", (pcp), val)
+#define this_cpu_xor_8(pcp, val)        percpu_to_op("xor", (pcp), val)
+
+#define irqsafe_cpu_add_8(pcp, val)     percpu_to_op("add", (pcp), val)
+#define irqsafe_cpu_and_8(pcp, val)     percpu_to_op("and", (pcp), val)
+#define irqsafe_cpu_or_8(pcp, val)      percpu_to_op("or", (pcp), val)
+#define irqsafe_cpu_xor_8(pcp, val)     percpu_to_op("xor", (pcp), val)
+
+#endif
+
 /* This is not atomic against other CPUs -- CPU preemption needs to be off */
 #define x86_test_and_clear_bit_percpu(bit, var)                         \
 ({                                                                      \
diff --git a/arch/x86/include/asm/ptrace.h b/arch/x86/include/asm/ptrace.h
index 3d11fd0f44c5..9d369f680321 100644
--- a/arch/x86/include/asm/ptrace.h
+++ b/arch/x86/include/asm/ptrace.h
@@ -292,6 +292,8 @@ extern void user_enable_block_step(struct task_struct *);
 #define arch_has_block_step()   (boot_cpu_data.x86 >= 6)
 #endif
 
+#define ARCH_HAS_USER_SINGLE_STEP_INFO
+
 struct user_desc;
 extern int do_get_thread_area(struct task_struct *p, int idx,
                               struct user_desc __user *info);
diff --git a/arch/x86/include/asm/spinlock.h b/arch/x86/include/asm/spinlock.h
index 4e77853321db..3089f70c0c52 100644
--- a/arch/x86/include/asm/spinlock.h
+++ b/arch/x86/include/asm/spinlock.h
@@ -58,7 +58,7 @@
 #if (NR_CPUS < 256)
 #define TICKET_SHIFT 8
 
-static __always_inline void __ticket_spin_lock(raw_spinlock_t *lock)
+static __always_inline void __ticket_spin_lock(arch_spinlock_t *lock)
 {
         short inc = 0x0100;
 
@@ -77,7 +77,7 @@ static __always_inline void __ticket_spin_lock(raw_spinlock_t *lock)
                 : "memory", "cc");
 }
 
-static __always_inline int __ticket_spin_trylock(raw_spinlock_t *lock)
+static __always_inline int __ticket_spin_trylock(arch_spinlock_t *lock)
 {
         int tmp, new;
 
@@ -96,7 +96,7 @@ static __always_inline int __ticket_spin_trylock(raw_spinlock_t *lock)
         return tmp;
 }
 
-static __always_inline void __ticket_spin_unlock(raw_spinlock_t *lock)
+static __always_inline void __ticket_spin_unlock(arch_spinlock_t *lock)
 {
         asm volatile(UNLOCK_LOCK_PREFIX "incb %0"
                      : "+m" (lock->slock)
@@ -106,7 +106,7 @@ static __always_inline void __ticket_spin_unlock(raw_spinlock_t *lock)
 #else
 #define TICKET_SHIFT 16
 
-static __always_inline void __ticket_spin_lock(raw_spinlock_t *lock)
+static __always_inline void __ticket_spin_lock(arch_spinlock_t *lock)
 {
         int inc = 0x00010000;
         int tmp;
@@ -127,7 +127,7 @@ static __always_inline void __ticket_spin_lock(raw_spinlock_t *lock)
                      : "memory", "cc");
 }
 
-static __always_inline int __ticket_spin_trylock(raw_spinlock_t *lock)
+static __always_inline int __ticket_spin_trylock(arch_spinlock_t *lock)
 {
         int tmp;
         int new;
@@ -149,7 +149,7 @@ static __always_inline int __ticket_spin_trylock(raw_spinlock_t *lock)
         return tmp;
 }
 
-static __always_inline void __ticket_spin_unlock(raw_spinlock_t *lock)
+static __always_inline void __ticket_spin_unlock(arch_spinlock_t *lock)
 {
         asm volatile(UNLOCK_LOCK_PREFIX "incw %0"
                      : "+m" (lock->slock)
@@ -158,14 +158,14 @@ static __always_inline void __ticket_spin_unlock(raw_spinlock_t *lock)
 }
 #endif
 
-static inline int __ticket_spin_is_locked(raw_spinlock_t *lock)
+static inline int __ticket_spin_is_locked(arch_spinlock_t *lock)
 {
         int tmp = ACCESS_ONCE(lock->slock);
 
         return !!(((tmp >> TICKET_SHIFT) ^ tmp) & ((1 << TICKET_SHIFT) - 1));
 }
 
-static inline int __ticket_spin_is_contended(raw_spinlock_t *lock)
+static inline int __ticket_spin_is_contended(arch_spinlock_t *lock)
 {
         int tmp = ACCESS_ONCE(lock->slock);
 
@@ -174,43 +174,43 @@ static inline int __ticket_spin_is_contended(raw_spinlock_t *lock)
 
 #ifndef CONFIG_PARAVIRT_SPINLOCKS
 
-static inline int __raw_spin_is_locked(raw_spinlock_t *lock)
+static inline int arch_spin_is_locked(arch_spinlock_t *lock)
 {
         return __ticket_spin_is_locked(lock);
 }
 
-static inline int __raw_spin_is_contended(raw_spinlock_t *lock)
+static inline int arch_spin_is_contended(arch_spinlock_t *lock)
 {
         return __ticket_spin_is_contended(lock);
 }
-#define __raw_spin_is_contended __raw_spin_is_contended
+#define arch_spin_is_contended  arch_spin_is_contended
 
-static __always_inline void __raw_spin_lock(raw_spinlock_t *lock)
+static __always_inline void arch_spin_lock(arch_spinlock_t *lock)
 {
         __ticket_spin_lock(lock);
 }
 
-static __always_inline int __raw_spin_trylock(raw_spinlock_t *lock)
+static __always_inline int arch_spin_trylock(arch_spinlock_t *lock)
 {
         return __ticket_spin_trylock(lock);
 }
 
-static __always_inline void __raw_spin_unlock(raw_spinlock_t *lock)
+static __always_inline void arch_spin_unlock(arch_spinlock_t *lock)
 {
         __ticket_spin_unlock(lock);
 }
 
-static __always_inline void __raw_spin_lock_flags(raw_spinlock_t *lock,
+static __always_inline void arch_spin_lock_flags(arch_spinlock_t *lock,
                                                   unsigned long flags)
 {
-        __raw_spin_lock(lock);
+        arch_spin_lock(lock);
 }
 
 #endif  /* CONFIG_PARAVIRT_SPINLOCKS */
 
-static inline void __raw_spin_unlock_wait(raw_spinlock_t *lock)
+static inline void arch_spin_unlock_wait(arch_spinlock_t *lock)
 {
-        while (__raw_spin_is_locked(lock))
+        while (arch_spin_is_locked(lock))
                 cpu_relax();
 }
 
@@ -232,7 +232,7 @@ static inline void __raw_spin_unlock_wait(raw_spinlock_t *lock)
  * read_can_lock - would read_trylock() succeed?
  * @lock: the rwlock in question.
  */
-static inline int __raw_read_can_lock(raw_rwlock_t *lock)
+static inline int arch_read_can_lock(arch_rwlock_t *lock)
 {
         return (int)(lock)->lock > 0;
 }
@@ -241,12 +241,12 @@ static inline int __raw_read_can_lock(raw_rwlock_t *lock)
  * write_can_lock - would write_trylock() succeed?
  * @lock: the rwlock in question.
  */
-static inline int __raw_write_can_lock(raw_rwlock_t *lock)
+static inline int arch_write_can_lock(arch_rwlock_t *lock)
 {
         return (lock)->lock == RW_LOCK_BIAS;
 }
 
-static inline void __raw_read_lock(raw_rwlock_t *rw)
+static inline void arch_read_lock(arch_rwlock_t *rw)
 {
         asm volatile(LOCK_PREFIX " subl $1,(%0)\n\t"
                      "jns 1f\n"
@@ -255,7 +255,7 @@ static inline void __raw_read_lock(raw_rwlock_t *rw)
                      ::LOCK_PTR_REG (rw) : "memory");
 }
 
-static inline void __raw_write_lock(raw_rwlock_t *rw)
+static inline void arch_write_lock(arch_rwlock_t *rw)
 {
         asm volatile(LOCK_PREFIX " subl %1,(%0)\n\t"
                      "jz 1f\n"
@@ -264,7 +264,7 @@ static inline void __raw_write_lock(raw_rwlock_t *rw)
                      ::LOCK_PTR_REG (rw), "i" (RW_LOCK_BIAS) : "memory");
 }
 
-static inline int __raw_read_trylock(raw_rwlock_t *lock)
+static inline int arch_read_trylock(arch_rwlock_t *lock)
 {
         atomic_t *count = (atomic_t *)lock;
 
@@ -274,7 +274,7 @@ static inline int __raw_read_trylock(raw_rwlock_t *lock)
         return 0;
 }
 
-static inline int __raw_write_trylock(raw_rwlock_t *lock)
+static inline int arch_write_trylock(arch_rwlock_t *lock)
 {
         atomic_t *count = (atomic_t *)lock;
 
@@ -284,23 +284,23 @@ static inline int __raw_write_trylock(raw_rwlock_t *lock)
         return 0;
 }
 
-static inline void __raw_read_unlock(raw_rwlock_t *rw)
+static inline void arch_read_unlock(arch_rwlock_t *rw)
 {
         asm volatile(LOCK_PREFIX "incl %0" :"+m" (rw->lock) : : "memory");
 }
 
-static inline void __raw_write_unlock(raw_rwlock_t *rw)
+static inline void arch_write_unlock(arch_rwlock_t *rw)
 {
         asm volatile(LOCK_PREFIX "addl %1, %0"
                      : "+m" (rw->lock) : "i" (RW_LOCK_BIAS) : "memory");
 }
 
-#define __raw_read_lock_flags(lock, flags) __raw_read_lock(lock)
-#define __raw_write_lock_flags(lock, flags) __raw_write_lock(lock)
+#define arch_read_lock_flags(lock, flags) arch_read_lock(lock)
+#define arch_write_lock_flags(lock, flags) arch_write_lock(lock)
 
-#define _raw_spin_relax(lock)   cpu_relax()
-#define _raw_read_relax(lock)   cpu_relax()
-#define _raw_write_relax(lock)  cpu_relax()
+#define arch_spin_relax(lock)   cpu_relax()
+#define arch_read_relax(lock)   cpu_relax()
+#define arch_write_relax(lock)  cpu_relax()
 
 /* The {read|write|spin}_lock() on x86 are full memory barriers. */
 static inline void smp_mb__after_lock(void) { }
diff --git a/arch/x86/include/asm/spinlock_types.h b/arch/x86/include/asm/spinlock_types.h
index 845f81c87091..dcb48b2edc11 100644
--- a/arch/x86/include/asm/spinlock_types.h
+++ b/arch/x86/include/asm/spinlock_types.h
@@ -5,16 +5,16 @@
 # error "please don't include this file directly"
 #endif
 
-typedef struct raw_spinlock {
+typedef struct arch_spinlock {
         unsigned int slock;
-} raw_spinlock_t;
+} arch_spinlock_t;
 
-#define __RAW_SPIN_LOCK_UNLOCKED        { 0 }
+#define __ARCH_SPIN_LOCK_UNLOCKED       { 0 }
 
 typedef struct {
         unsigned int lock;
-} raw_rwlock_t;
+} arch_rwlock_t;
 
-#define __RAW_RW_LOCK_UNLOCKED          { RW_LOCK_BIAS }
+#define __ARCH_RW_LOCK_UNLOCKED         { RW_LOCK_BIAS }
 
 #endif /* _ASM_X86_SPINLOCK_TYPES_H */
diff --git a/arch/x86/include/asm/sys_ia32.h b/arch/x86/include/asm/sys_ia32.h
index 9af9decb38c3..d5f69045c100 100644
--- a/arch/x86/include/asm/sys_ia32.h
+++ b/arch/x86/include/asm/sys_ia32.h
@@ -30,7 +30,6 @@ struct mmap_arg_struct;
 asmlinkage long sys32_mmap(struct mmap_arg_struct __user *);
 asmlinkage long sys32_mprotect(unsigned long, size_t, unsigned long);
 
-asmlinkage long sys32_pipe(int __user *);
 struct sigaction32;
 struct old_sigaction32;
 asmlinkage long sys32_rt_sigaction(int, struct sigaction32 __user *,
@@ -57,9 +56,6 @@ asmlinkage long sys32_pwrite(unsigned int, char __user *, u32, u32, u32);
 asmlinkage long sys32_personality(unsigned long);
 asmlinkage long sys32_sendfile(int, int, compat_off_t __user *, s32);
 
-asmlinkage long sys32_mmap2(unsigned long, unsigned long, unsigned long,
-                            unsigned long, unsigned long, unsigned long);
-
 struct oldold_utsname;
 struct old_utsname;
 asmlinkage long sys32_olduname(struct oldold_utsname __user *);
diff --git a/arch/x86/include/asm/syscalls.h b/arch/x86/include/asm/syscalls.h
index b0ce78061708..8868b9420b0e 100644
--- a/arch/x86/include/asm/syscalls.h
+++ b/arch/x86/include/asm/syscalls.h
@@ -56,8 +56,6 @@ struct sel_arg_struct;
 struct oldold_utsname;
 struct old_utsname;
 
-asmlinkage long sys_mmap2(unsigned long, unsigned long, unsigned long,
-                          unsigned long, unsigned long, unsigned long);
 asmlinkage int old_mmap(struct mmap_arg_struct __user *);
 asmlinkage int old_select(struct sel_arg_struct __user *);
 asmlinkage int sys_ipc(uint, int, int, int, void __user *, long);
diff --git a/arch/x86/include/asm/topology.h b/arch/x86/include/asm/topology.h
index 40e37b10c6c0..c5087d796587 100644
--- a/arch/x86/include/asm/topology.h
+++ b/arch/x86/include/asm/topology.h
@@ -35,11 +35,16 @@
 # endif
 #endif
 
-/* Node not present */
-#define NUMA_NO_NODE    (-1)
+/*
+ * to preserve the visibility of NUMA_NO_NODE definition,
+ * moved to there from here.  May be used independent of
+ * CONFIG_NUMA.
+ */
+#include <linux/numa.h>
 
 #ifdef CONFIG_NUMA
 #include <linux/cpumask.h>
+
 #include <asm/mpspec.h>
 
 #ifdef CONFIG_X86_32
diff --git a/arch/x86/include/asm/uv/bios.h b/arch/x86/include/asm/uv/bios.h
index 7ed17ff502b9..2751f3075d8b 100644
--- a/arch/x86/include/asm/uv/bios.h
+++ b/arch/x86/include/asm/uv/bios.h
@@ -76,15 +76,6 @@ union partition_info_u {
         };
 };
 
-union uv_watchlist_u {
-        u64     val;
-        struct {
-                u64     blade   : 16,
-                        size    : 32,
-                        filler  : 16;
-        };
-};
-
 enum uv_memprotect {
         UV_MEMPROT_RESTRICT_ACCESS,
         UV_MEMPROT_ALLOW_AMO,
@@ -100,7 +91,7 @@ extern s64 uv_bios_call_reentrant(enum uv_bios_cmd, u64, u64, u64, u64, u64);
 
 extern s64 uv_bios_get_sn_info(int, int *, long *, long *, long *);
 extern s64 uv_bios_freq_base(u64, u64 *);
-extern int uv_bios_mq_watchlist_alloc(int, unsigned long, unsigned int,
+extern int uv_bios_mq_watchlist_alloc(unsigned long, unsigned int,
                                         unsigned long *);
 extern int uv_bios_mq_watchlist_free(int, int);
 extern s64 uv_bios_change_memprotect(u64, u64, enum uv_memprotect);
diff --git a/arch/x86/include/asm/uv/uv_hub.h b/arch/x86/include/asm/uv/uv_hub.h
index d1414af98559..811bfabc80b7 100644
--- a/arch/x86/include/asm/uv/uv_hub.h
+++ b/arch/x86/include/asm/uv/uv_hub.h
@@ -172,6 +172,8 @@ DECLARE_PER_CPU(struct uv_hub_info_s, __uv_hub_info);
 #define UV_LOCAL_MMR_SIZE               (64UL * 1024 * 1024)
 #define UV_GLOBAL_MMR32_SIZE            (64UL * 1024 * 1024)
 
+#define UV_GLOBAL_GRU_MMR_BASE          0x4000000
+
 #define UV_GLOBAL_MMR32_PNODE_SHIFT     15
 #define UV_GLOBAL_MMR64_PNODE_SHIFT     26
 
@@ -232,6 +234,26 @@ static inline unsigned long uv_gpa(void *v)
         return uv_soc_phys_ram_to_gpa(__pa(v));
 }
 
+/* Top two bits indicate the requested address is in MMR space.  */
+static inline int
+uv_gpa_in_mmr_space(unsigned long gpa)
+{
+        return (gpa >> 62) == 0x3UL;
+}
+
+/* UV global physical address --> socket phys RAM */
+static inline unsigned long uv_gpa_to_soc_phys_ram(unsigned long gpa)
+{
+        unsigned long paddr = gpa & uv_hub_info->gpa_mask;
+        unsigned long remap_base = uv_hub_info->lowmem_remap_base;
+        unsigned long remap_top =  uv_hub_info->lowmem_remap_top;
+
+        if (paddr >= remap_base && paddr < remap_base + remap_top)
+                paddr -= remap_base;
+        return paddr;
+}
+
+
 /* gnode -> pnode */
 static inline unsigned long uv_gpa_to_gnode(unsigned long gpa)
 {
@@ -308,6 +330,15 @@ static inline unsigned long uv_read_global_mmr64(int pnode,
 }
 
 /*
+ * Global MMR space addresses when referenced by the GRU. (GRU does
+ * NOT use socket addressing).
+ */
+static inline unsigned long uv_global_gru_mmr_address(int pnode, unsigned long offset)
+{
+        return UV_GLOBAL_GRU_MMR_BASE | offset | (pnode << uv_hub_info->m_val);
+}
+
+/*
  * Access hub local MMRs. Faster than using global space but only local MMRs
  * are accessible.
  */
@@ -434,6 +465,14 @@ static inline void uv_set_cpu_scir_bits(int cpu, unsigned char value)
         }
 }
 
+static unsigned long uv_hub_ipi_value(int apicid, int vector, int mode)
+{
+        return (1UL << UVH_IPI_INT_SEND_SHFT) |
+                        ((apicid) << UVH_IPI_INT_APIC_ID_SHFT) |
+                        (mode << UVH_IPI_INT_DELIVERY_MODE_SHFT) |
+                        (vector << UVH_IPI_INT_VECTOR_SHFT);
+}
+
 static inline void uv_hub_send_ipi(int pnode, int apicid, int vector)
 {
         unsigned long val;
@@ -442,10 +481,7 @@ static inline void uv_hub_send_ipi(int pnode, int apicid, int vector)
         if (vector == NMI_VECTOR)
                 dmode = dest_NMI;
 
-        val = (1UL << UVH_IPI_INT_SEND_SHFT) |
-                        ((apicid) << UVH_IPI_INT_APIC_ID_SHFT) |
-                        (dmode << UVH_IPI_INT_DELIVERY_MODE_SHFT) |
-                        (vector << UVH_IPI_INT_VECTOR_SHFT);
+        val = uv_hub_ipi_value(apicid, vector, dmode);
         uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
 }
 
diff --git a/arch/x86/include/asm/xen/hypervisor.h b/arch/x86/include/asm/xen/hypervisor.h
index d5b7e90c0edf..396ff4cc8ed4 100644
--- a/arch/x86/include/asm/xen/hypervisor.h
+++ b/arch/x86/include/asm/xen/hypervisor.h
@@ -37,31 +37,4 @@
 extern struct shared_info *HYPERVISOR_shared_info;
 extern struct start_info *xen_start_info;
 
-enum xen_domain_type {
-        XEN_NATIVE,             /* running on bare hardware    */
-        XEN_PV_DOMAIN,          /* running in a PV domain      */
-        XEN_HVM_DOMAIN,         /* running in a Xen hvm domain */
-};
-
-#ifdef CONFIG_XEN
-extern enum xen_domain_type xen_domain_type;
-#else
-#define xen_domain_type         XEN_NATIVE
-#endif
-
-#define xen_domain()            (xen_domain_type != XEN_NATIVE)
-#define xen_pv_domain()         (xen_domain() &&                        \
-                                 xen_domain_type == XEN_PV_DOMAIN)
-#define xen_hvm_domain()        (xen_domain() &&                        \
-                                 xen_domain_type == XEN_HVM_DOMAIN)
-
-#ifdef CONFIG_XEN_DOM0
-#include <xen/interface/xen.h>
-
-#define xen_initial_domain()    (xen_pv_domain() && \
-                                 xen_start_info->flags & SIF_INITDOMAIN)
-#else  /* !CONFIG_XEN_DOM0 */
-#define xen_initial_domain()    (0)
-#endif  /* CONFIG_XEN_DOM0 */
-
 #endif /* _ASM_X86_XEN_HYPERVISOR_H */
diff --git a/arch/x86/kernel/Makefile b/arch/x86/kernel/Makefile
index 4f2e66e29ecc..d87f09bc5a52 100644
--- a/arch/x86/kernel/Makefile
+++ b/arch/x86/kernel/Makefile
@@ -89,7 +89,6 @@ obj-$(CONFIG_EARLY_PRINTK)	+= early_printk.o
 obj-$(CONFIG_HPET_TIMER)        += hpet.o
 
 obj-$(CONFIG_K8_NB)             += k8.o
-obj-$(CONFIG_MGEODE_LX)         += geode_32.o mfgpt_32.o
 obj-$(CONFIG_DEBUG_RODATA_TEST) += test_rodata.o
 obj-$(CONFIG_DEBUG_NX_TEST)     += test_nx.o
 
diff --git a/arch/x86/kernel/acpi/cstate.c b/arch/x86/kernel/acpi/cstate.c
index 59cdfa4686b2..2e837f5080fe 100644
--- a/arch/x86/kernel/acpi/cstate.c
+++ b/arch/x86/kernel/acpi/cstate.c
@@ -48,7 +48,7 @@ void acpi_processor_power_init_bm_check(struct acpi_processor_flags *flags,
          * P4, Core and beyond CPUs
          */
         if (c->x86_vendor == X86_VENDOR_INTEL &&
-            (c->x86 > 0xf || (c->x86 == 6 && c->x86_model >= 14)))
+            (c->x86 > 0xf || (c->x86 == 6 && c->x86_model >= 0x0f)))
                         flags->bm_control = 0;
 }
 EXPORT_SYMBOL(acpi_processor_power_init_bm_check);
diff --git a/arch/x86/kernel/amd_iommu.c b/arch/x86/kernel/amd_iommu.c
index b990b5cc9541..23824fef789c 100644
--- a/arch/x86/kernel/amd_iommu.c
+++ b/arch/x86/kernel/amd_iommu.c
@@ -19,7 +19,7 @@
 
 #include <linux/pci.h>
 #include <linux/gfp.h>
-#include <linux/bitops.h>
+#include <linux/bitmap.h>
 #include <linux/debugfs.h>
 #include <linux/scatterlist.h>
 #include <linux/dma-mapping.h>
@@ -1162,7 +1162,7 @@ static void dma_ops_free_addresses(struct dma_ops_domain *dom,
 
         address = (address % APERTURE_RANGE_SIZE) >> PAGE_SHIFT;
 
-        iommu_area_free(range->bitmap, address, pages);
+        bitmap_clear(range->bitmap, address, pages);
 
 }
 
diff --git a/arch/x86/kernel/amd_iommu_init.c b/arch/x86/kernel/amd_iommu_init.c
index 309a52f96e0b..fb490ce7dd55 100644
--- a/arch/x86/kernel/amd_iommu_init.c
+++ b/arch/x86/kernel/amd_iommu_init.c
@@ -138,6 +138,11 @@ int amd_iommus_present;
 bool amd_iommu_np_cache __read_mostly;
 
 /*
+ * Set to true if ACPI table parsing and hardware intialization went properly
+ */
+static bool amd_iommu_initialized;
+
+/*
  * List of protection domains - used during resume
  */
 LIST_HEAD(amd_iommu_pd_list);
@@ -929,6 +934,8 @@ static int __init init_iommu_all(struct acpi_table_header *table)
         }
         WARN_ON(p != end);
 
+        amd_iommu_initialized = true;
+
         return 0;
 }
 
@@ -1263,6 +1270,9 @@ static int __init amd_iommu_init(void)
         if (acpi_table_parse("IVRS", init_iommu_all) != 0)
                 goto free;
 
+        if (!amd_iommu_initialized)
+                goto free;
+
         if (acpi_table_parse("IVRS", init_memory_definitions) != 0)
                 goto free;
 
@@ -1345,6 +1355,9 @@ void __init amd_iommu_detect(void)
                 iommu_detected = 1;
                 amd_iommu_detected = 1;
                 x86_init.iommu.iommu_init = amd_iommu_init;
+
+                /* Make sure ACS will be enabled */
+                pci_request_acs();
         }
 }
 
diff --git a/arch/x86/kernel/apic/io_apic.c b/arch/x86/kernel/apic/io_apic.c
index 98ced709e829..de00c4619a55 100644
--- a/arch/x86/kernel/apic/io_apic.c
+++ b/arch/x86/kernel/apic/io_apic.c
@@ -2432,7 +2432,7 @@ asmlinkage void smp_irq_move_cleanup_interrupt(void)
                         continue;
 
                 cfg = irq_cfg(irq);
-                spin_lock(&desc->lock);
+                raw_spin_lock(&desc->lock);
 
                 if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain))
                         goto unlock;
@@ -2451,7 +2451,7 @@ asmlinkage void smp_irq_move_cleanup_interrupt(void)
                 }
                 __get_cpu_var(vector_irq)[vector] = -1;
 unlock:
-                spin_unlock(&desc->lock);
+                raw_spin_unlock(&desc->lock);
         }
 
         irq_exit();
diff --git a/arch/x86/kernel/apic/nmi.c b/arch/x86/kernel/apic/nmi.c
index 6389432a9dbf..0159a69396cb 100644
--- a/arch/x86/kernel/apic/nmi.c
+++ b/arch/x86/kernel/apic/nmi.c
@@ -361,7 +361,7 @@ void stop_apic_nmi_watchdog(void *unused)
  */
 
 static DEFINE_PER_CPU(unsigned, last_irq_sum);
-static DEFINE_PER_CPU(local_t, alert_counter);
+static DEFINE_PER_CPU(long, alert_counter);
 static DEFINE_PER_CPU(int, nmi_touch);
 
 void touch_nmi_watchdog(void)
@@ -438,8 +438,8 @@ nmi_watchdog_tick(struct pt_regs *regs, unsigned reason)
                  * Ayiee, looks like this CPU is stuck ...
                  * wait a few IRQs (5 seconds) before doing the oops ...
                  */
-                local_inc(&__get_cpu_var(alert_counter));
-                if (local_read(&__get_cpu_var(alert_counter)) == 5 * nmi_hz)
+                __this_cpu_inc(per_cpu_var(alert_counter));
+                if (__this_cpu_read(per_cpu_var(alert_counter)) == 5 * nmi_hz)
                         /*
                          * die_nmi will return ONLY if NOTIFY_STOP happens..
                          */
@@ -447,7 +447,7 @@ nmi_watchdog_tick(struct pt_regs *regs, unsigned reason)
                                 regs, panic_on_timeout);
         } else {
                 __get_cpu_var(last_irq_sum) = sum;
-                local_set(&__get_cpu_var(alert_counter), 0);
+                __this_cpu_write(per_cpu_var(alert_counter), 0);
         }
 
         /* see if the nmi watchdog went off */
diff --git a/arch/x86/kernel/bios_uv.c b/arch/x86/kernel/bios_uv.c
index 63a88e1f987d..b0206a211b09 100644
--- a/arch/x86/kernel/bios_uv.c
+++ b/arch/x86/kernel/bios_uv.c
@@ -101,21 +101,17 @@ s64 uv_bios_get_sn_info(int fc, int *uvtype, long *partid, long *coher,
 }
 
 int
-uv_bios_mq_watchlist_alloc(int blade, unsigned long addr, unsigned int mq_size,
+uv_bios_mq_watchlist_alloc(unsigned long addr, unsigned int mq_size,
                            unsigned long *intr_mmr_offset)
 {
-        union uv_watchlist_u size_blade;
         u64 watchlist;
         s64 ret;
 
-        size_blade.size = mq_size;
-        size_blade.blade = blade;
-
         /*
          * bios returns watchlist number or negative error number.
          */
         ret = (int)uv_bios_call_irqsave(UV_BIOS_WATCHLIST_ALLOC, addr,
-                        size_blade.val, (u64)intr_mmr_offset,
+                        mq_size, (u64)intr_mmr_offset,
                         (u64)&watchlist, 0);
         if (ret < BIOS_STATUS_SUCCESS)
                 return ret;
diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c
index 0ee9a3254eec..4868e4a951ee 100644
--- a/arch/x86/kernel/cpu/common.c
+++ b/arch/x86/kernel/cpu/common.c
@@ -1095,7 +1095,7 @@ static void clear_all_debug_regs(void)
 
 void __cpuinit cpu_init(void)
 {
-        struct orig_ist *orig_ist;
+        struct orig_ist *oist;
         struct task_struct *me;
         struct tss_struct *t;
         unsigned long v;
@@ -1104,7 +1104,7 @@ void __cpuinit cpu_init(void)
 
         cpu = stack_smp_processor_id();
         t = &per_cpu(init_tss, cpu);
-        orig_ist = &per_cpu(orig_ist, cpu);
+        oist = &per_cpu(orig_ist, cpu);
 
 #ifdef CONFIG_NUMA
         if (cpu != 0 && percpu_read(node_number) == 0 &&
@@ -1145,12 +1145,12 @@ void __cpuinit cpu_init(void)
         /*
          * set up and load the per-CPU TSS
          */
-        if (!orig_ist->ist[0]) {
+        if (!oist->ist[0]) {
                 char *estacks = per_cpu(exception_stacks, cpu);
 
                 for (v = 0; v < N_EXCEPTION_STACKS; v++) {
                         estacks += exception_stack_sizes[v];
-                        orig_ist->ist[v] = t->x86_tss.ist[v] =
+                        oist->ist[v] = t->x86_tss.ist[v] =
                                         (unsigned long)estacks;
                 }
         }
diff --git a/arch/x86/kernel/cpu/cpu_debug.c b/arch/x86/kernel/cpu/cpu_debug.c
index dca325c03999..b368cd862997 100644
--- a/arch/x86/kernel/cpu/cpu_debug.c
+++ b/arch/x86/kernel/cpu/cpu_debug.c
@@ -30,9 +30,9 @@
 #include <asm/apic.h>
 #include <asm/desc.h>
 
-static DEFINE_PER_CPU(struct cpu_cpuX_base [CPU_REG_ALL_BIT], cpu_arr);
-static DEFINE_PER_CPU(struct cpu_private * [MAX_CPU_FILES], priv_arr);
-static DEFINE_PER_CPU(int, cpu_priv_count);
+static DEFINE_PER_CPU(struct cpu_cpuX_base [CPU_REG_ALL_BIT], cpud_arr);
+static DEFINE_PER_CPU(struct cpu_private * [MAX_CPU_FILES], cpud_priv_arr);
+static DEFINE_PER_CPU(int, cpud_priv_count);
 
 static DEFINE_MUTEX(cpu_debug_lock);
 
@@ -531,7 +531,7 @@ static int cpu_create_file(unsigned cpu, unsigned type, unsigned reg,
 
         /* Already intialized */
         if (file == CPU_INDEX_BIT)
-                if (per_cpu(cpu_arr[type].init, cpu))
+                if (per_cpu(cpud_arr[type].init, cpu))
                         return 0;
 
         priv = kzalloc(sizeof(*priv), GFP_KERNEL);
@@ -543,8 +543,8 @@ static int cpu_create_file(unsigned cpu, unsigned type, unsigned reg,
         priv->reg = reg;
         priv->file = file;
         mutex_lock(&cpu_debug_lock);
-        per_cpu(priv_arr[type], cpu) = priv;
-        per_cpu(cpu_priv_count, cpu)++;
+        per_cpu(cpud_priv_arr[type], cpu) = priv;
+        per_cpu(cpud_priv_count, cpu)++;
         mutex_unlock(&cpu_debug_lock);
 
         if (file)
@@ -552,10 +552,10 @@ static int cpu_create_file(unsigned cpu, unsigned type, unsigned reg,
                                     dentry, (void *)priv, &cpu_fops);
         else {
                 debugfs_create_file(cpu_base[type].name, S_IRUGO,
-                                    per_cpu(cpu_arr[type].dentry, cpu),
+                                    per_cpu(cpud_arr[type].dentry, cpu),
                                     (void *)priv, &cpu_fops);
                 mutex_lock(&cpu_debug_lock);
-                per_cpu(cpu_arr[type].init, cpu) = 1;
+                per_cpu(cpud_arr[type].init, cpu) = 1;
                 mutex_unlock(&cpu_debug_lock);
         }
 
@@ -615,7 +615,7 @@ static int cpu_init_allreg(unsigned cpu, struct dentry *dentry)
                 if (!is_typeflag_valid(cpu, cpu_base[type].flag))
                         continue;
                 cpu_dentry = debugfs_create_dir(cpu_base[type].name, dentry);
-                per_cpu(cpu_arr[type].dentry, cpu) = cpu_dentry;
+                per_cpu(cpud_arr[type].dentry, cpu) = cpu_dentry;
 
                 if (type < CPU_TSS_BIT)
                         err = cpu_init_msr(cpu, type, cpu_dentry);
@@ -647,11 +647,11 @@ static int cpu_init_cpu(void)
                 err = cpu_init_allreg(cpu, cpu_dentry);
 
                 pr_info("cpu%d(%d) debug files %d\n",
-                        cpu, nr_cpu_ids, per_cpu(cpu_priv_count, cpu));
-                if (per_cpu(cpu_priv_count, cpu) > MAX_CPU_FILES) {
+                        cpu, nr_cpu_ids, per_cpu(cpud_priv_count, cpu));
+                if (per_cpu(cpud_priv_count, cpu) > MAX_CPU_FILES) {
                         pr_err("Register files count %d exceeds limit %d\n",
-                                per_cpu(cpu_priv_count, cpu), MAX_CPU_FILES);
-                        per_cpu(cpu_priv_count, cpu) = MAX_CPU_FILES;
+                                per_cpu(cpud_priv_count, cpu), MAX_CPU_FILES);
+                        per_cpu(cpud_priv_count, cpu) = MAX_CPU_FILES;
                         err = -ENFILE;
                 }
                 if (err)
@@ -676,8 +676,8 @@ static void __exit cpu_debug_exit(void)
                 debugfs_remove_recursive(cpu_debugfs_dir);
 
         for (cpu = 0; cpu <  nr_cpu_ids; cpu++)
-                for (i = 0; i < per_cpu(cpu_priv_count, cpu); i++)
-                        kfree(per_cpu(priv_arr[i], cpu));
+                for (i = 0; i < per_cpu(cpud_priv_count, cpu); i++)
+                        kfree(per_cpu(cpud_priv_arr[i], cpu));
 }
 
 module_init(cpu_debug_init);
diff --git a/arch/x86/kernel/cpu/cpufreq/acpi-cpufreq.c b/arch/x86/kernel/cpu/cpufreq/acpi-cpufreq.c
index 8b581d3905cb..f28decf8dde3 100644
--- a/arch/x86/kernel/cpu/cpufreq/acpi-cpufreq.c
+++ b/arch/x86/kernel/cpu/cpufreq/acpi-cpufreq.c
@@ -68,9 +68,9 @@ struct acpi_cpufreq_data {
         unsigned int cpu_feature;
 };
 
-static DEFINE_PER_CPU(struct acpi_cpufreq_data *, drv_data);
+static DEFINE_PER_CPU(struct acpi_cpufreq_data *, acfreq_data);
 
-static DEFINE_PER_CPU(struct aperfmperf, old_perf);
+static DEFINE_PER_CPU(struct aperfmperf, acfreq_old_perf);
 
 /* acpi_perf_data is a pointer to percpu data. */
 static struct acpi_processor_performance *acpi_perf_data;
@@ -214,14 +214,14 @@ static u32 get_cur_val(const struct cpumask *mask)
         if (unlikely(cpumask_empty(mask)))
                 return 0;
 
-        switch (per_cpu(drv_data, cpumask_first(mask))->cpu_feature) {
+        switch (per_cpu(acfreq_data, cpumask_first(mask))->cpu_feature) {
         case SYSTEM_INTEL_MSR_CAPABLE:
                 cmd.type = SYSTEM_INTEL_MSR_CAPABLE;
                 cmd.addr.msr.reg = MSR_IA32_PERF_STATUS;
                 break;
         case SYSTEM_IO_CAPABLE:
                 cmd.type = SYSTEM_IO_CAPABLE;
-                perf = per_cpu(drv_data, cpumask_first(mask))->acpi_data;
+                perf = per_cpu(acfreq_data, cpumask_first(mask))->acpi_data;
                 cmd.addr.io.port = perf->control_register.address;
                 cmd.addr.io.bit_width = perf->control_register.bit_width;
                 break;
@@ -268,8 +268,8 @@ static unsigned int get_measured_perf(struct cpufreq_policy *policy,
         if (smp_call_function_single(cpu, read_measured_perf_ctrs, &perf, 1))
                 return 0;
 
-        ratio = calc_aperfmperf_ratio(&per_cpu(old_perf, cpu), &perf);
-        per_cpu(old_perf, cpu) = perf;
+        ratio = calc_aperfmperf_ratio(&per_cpu(acfreq_old_perf, cpu), &perf);
+        per_cpu(acfreq_old_perf, cpu) = perf;
 
         retval = (policy->cpuinfo.max_freq * ratio) >> APERFMPERF_SHIFT;
 
@@ -278,7 +278,7 @@ static unsigned int get_measured_perf(struct cpufreq_policy *policy,
 
 static unsigned int get_cur_freq_on_cpu(unsigned int cpu)
 {
-        struct acpi_cpufreq_data *data = per_cpu(drv_data, cpu);
+        struct acpi_cpufreq_data *data = per_cpu(acfreq_data, cpu);
         unsigned int freq;
         unsigned int cached_freq;
 
@@ -322,7 +322,7 @@ static unsigned int check_freqs(const struct cpumask *mask, unsigned int freq,
 static int acpi_cpufreq_target(struct cpufreq_policy *policy,
                                unsigned int target_freq, unsigned int relation)
 {
-        struct acpi_cpufreq_data *data = per_cpu(drv_data, policy->cpu);
+        struct acpi_cpufreq_data *data = per_cpu(acfreq_data, policy->cpu);
         struct acpi_processor_performance *perf;
         struct cpufreq_freqs freqs;
         struct drv_cmd cmd;
@@ -416,7 +416,7 @@ out:
 
 static int acpi_cpufreq_verify(struct cpufreq_policy *policy)
 {
-        struct acpi_cpufreq_data *data = per_cpu(drv_data, policy->cpu);
+        struct acpi_cpufreq_data *data = per_cpu(acfreq_data, policy->cpu);
 
         dprintk("acpi_cpufreq_verify\n");
 
@@ -574,7 +574,7 @@ static int acpi_cpufreq_cpu_init(struct cpufreq_policy *policy)
                 return -ENOMEM;
 
         data->acpi_data = per_cpu_ptr(acpi_perf_data, cpu);
-        per_cpu(drv_data, cpu) = data;
+        per_cpu(acfreq_data, cpu) = data;
 
         if (cpu_has(c, X86_FEATURE_CONSTANT_TSC))
                 acpi_cpufreq_driver.flags |= CPUFREQ_CONST_LOOPS;
@@ -725,20 +725,20 @@ err_unreg:
         acpi_processor_unregister_performance(perf, cpu);
 err_free:
         kfree(data);
-        per_cpu(drv_data, cpu) = NULL;
+        per_cpu(acfreq_data, cpu) = NULL;
 
         return result;
 }
 
 static int acpi_cpufreq_cpu_exit(struct cpufreq_policy *policy)
 {
-        struct acpi_cpufreq_data *data = per_cpu(drv_data, policy->cpu);
+        struct acpi_cpufreq_data *data = per_cpu(acfreq_data, policy->cpu);
 
         dprintk("acpi_cpufreq_cpu_exit\n");
 
         if (data) {
                 cpufreq_frequency_table_put_attr(policy->cpu);
-                per_cpu(drv_data, policy->cpu) = NULL;
+                per_cpu(acfreq_data, policy->cpu) = NULL;
                 acpi_processor_unregister_performance(data->acpi_data,
                                                       policy->cpu);
                 kfree(data);
@@ -749,7 +749,7 @@ static int acpi_cpufreq_cpu_exit(struct cpufreq_policy *policy)
 
 static int acpi_cpufreq_resume(struct cpufreq_policy *policy)
 {
-        struct acpi_cpufreq_data *data = per_cpu(drv_data, policy->cpu);
+        struct acpi_cpufreq_data *data = per_cpu(acfreq_data, policy->cpu);
 
         dprintk("acpi_cpufreq_resume\n");
 
@@ -764,14 +764,15 @@ static struct freq_attr *acpi_cpufreq_attr[] = {
 };
 
 static struct cpufreq_driver acpi_cpufreq_driver = {
-        .verify = acpi_cpufreq_verify,
-        .target = acpi_cpufreq_target,
-        .init = acpi_cpufreq_cpu_init,
-        .exit = acpi_cpufreq_cpu_exit,
-        .resume = acpi_cpufreq_resume,
-        .name = "acpi-cpufreq",
-        .owner = THIS_MODULE,
-        .attr = acpi_cpufreq_attr,
+        .verify         = acpi_cpufreq_verify,
+        .target         = acpi_cpufreq_target,
+        .bios_limit     = acpi_processor_get_bios_limit,
+        .init           = acpi_cpufreq_cpu_init,
+        .exit           = acpi_cpufreq_cpu_exit,
+        .resume         = acpi_cpufreq_resume,
+        .name           = "acpi-cpufreq",
+        .owner          = THIS_MODULE,
+        .attr           = acpi_cpufreq_attr,
 };
 
 static int __init acpi_cpufreq_init(void)
diff --git a/arch/x86/kernel/cpu/cpufreq/powernow-k6.c b/arch/x86/kernel/cpu/cpufreq/powernow-k6.c
index f10dea409f40..cb01dac267d3 100644
--- a/arch/x86/kernel/cpu/cpufreq/powernow-k6.c
+++ b/arch/x86/kernel/cpu/cpufreq/powernow-k6.c
@@ -164,7 +164,7 @@ static int powernow_k6_cpu_init(struct cpufreq_policy *policy)
         }
 
         /* cpuinfo and default policy values */
-        policy->cpuinfo.transition_latency = CPUFREQ_ETERNAL;
+        policy->cpuinfo.transition_latency = 200000;
         policy->cur = busfreq * max_multiplier;
 
         result = cpufreq_frequency_table_cpuinfo(policy, clock_ratio);
diff --git a/arch/x86/kernel/cpu/cpufreq/powernow-k7.c b/arch/x86/kernel/cpu/cpufreq/powernow-k7.c
index d47c775eb0ab..9a97116f89e5 100644
--- a/arch/x86/kernel/cpu/cpufreq/powernow-k7.c
+++ b/arch/x86/kernel/cpu/cpufreq/powernow-k7.c
@@ -714,14 +714,17 @@ static struct freq_attr *powernow_table_attr[] = {
 };
 
 static struct cpufreq_driver powernow_driver = {
-        .verify = powernow_verify,
-        .target = powernow_target,
-        .get    = powernow_get,
-        .init   = powernow_cpu_init,
-        .exit   = powernow_cpu_exit,
-        .name   = "powernow-k7",
-        .owner  = THIS_MODULE,
-        .attr   = powernow_table_attr,
+        .verify         = powernow_verify,
+        .target         = powernow_target,
+        .get            = powernow_get,
+#ifdef CONFIG_X86_POWERNOW_K7_ACPI
+        .bios_limit     = acpi_processor_get_bios_limit,
+#endif
+        .init           = powernow_cpu_init,
+        .exit           = powernow_cpu_exit,
+        .name           = "powernow-k7",
+        .owner          = THIS_MODULE,
+        .attr           = powernow_table_attr,
 };
 
 static int __init powernow_init(void)
diff --git a/arch/x86/kernel/cpu/cpufreq/powernow-k8.c b/arch/x86/kernel/cpu/cpufreq/powernow-k8.c
index 3f12dabeab52..f125e5c551c0 100644
--- a/arch/x86/kernel/cpu/cpufreq/powernow-k8.c
+++ b/arch/x86/kernel/cpu/cpufreq/powernow-k8.c
@@ -1118,7 +1118,7 @@ static int transition_frequency_pstate(struct powernow_k8_data *data,
 static int powernowk8_target(struct cpufreq_policy *pol,
                 unsigned targfreq, unsigned relation)
 {
-        cpumask_t oldmask;
+        cpumask_var_t oldmask;
         struct powernow_k8_data *data = per_cpu(powernow_data, pol->cpu);
         u32 checkfid;
         u32 checkvid;
@@ -1131,9 +1131,13 @@ static int powernowk8_target(struct cpufreq_policy *pol,
         checkfid = data->currfid;
         checkvid = data->currvid;
 
-        /* only run on specific CPU from here on */
-        oldmask = current->cpus_allowed;
-        set_cpus_allowed_ptr(current, &cpumask_of_cpu(pol->cpu));
+        /* only run on specific CPU from here on. */
+        /* This is poor form: use a workqueue or smp_call_function_single */
+        if (!alloc_cpumask_var(&oldmask, GFP_KERNEL))
+                return -ENOMEM;
+
+        cpumask_copy(oldmask, tsk_cpus_allowed(current));
+        set_cpus_allowed_ptr(current, cpumask_of(pol->cpu));
 
         if (smp_processor_id() != pol->cpu) {
                 printk(KERN_ERR PFX "limiting to cpu %u failed\n", pol->cpu);
@@ -1193,7 +1197,8 @@ static int powernowk8_target(struct cpufreq_policy *pol,
         ret = 0;
 
 err_out:
-        set_cpus_allowed_ptr(current, &oldmask);
+        set_cpus_allowed_ptr(current, oldmask);
+        free_cpumask_var(oldmask);
         return ret;
 }
 
@@ -1393,14 +1398,15 @@ static struct freq_attr *powernow_k8_attr[] = {
 };
 
 static struct cpufreq_driver cpufreq_amd64_driver = {
-        .verify = powernowk8_verify,
-        .target = powernowk8_target,
-        .init = powernowk8_cpu_init,
-        .exit = __devexit_p(powernowk8_cpu_exit),
-        .get = powernowk8_get,
-        .name = "powernow-k8",
-        .owner = THIS_MODULE,
-        .attr = powernow_k8_attr,
+        .verify         = powernowk8_verify,
+        .target         = powernowk8_target,
+        .bios_limit     = acpi_processor_get_bios_limit,
+        .init           = powernowk8_cpu_init,
+        .exit           = __devexit_p(powernowk8_cpu_exit),
+        .get            = powernowk8_get,
+        .name           = "powernow-k8",
+        .owner          = THIS_MODULE,
+        .attr           = powernow_k8_attr,
 };
 
 /* driver entry point for init */
diff --git a/arch/x86/kernel/cpu/cpufreq/speedstep-ich.c b/arch/x86/kernel/cpu/cpufreq/speedstep-ich.c
index 3ae5a7a3a500..2ce8e0b5cc54 100644
--- a/arch/x86/kernel/cpu/cpufreq/speedstep-ich.c
+++ b/arch/x86/kernel/cpu/cpufreq/speedstep-ich.c
@@ -39,7 +39,7 @@ static struct pci_dev *speedstep_chipset_dev;
 
 /* speedstep_processor
  */
-static unsigned int speedstep_processor;
+static enum speedstep_processor speedstep_processor;
 
 static u32 pmbase;
 
diff --git a/arch/x86/kernel/cpu/cpufreq/speedstep-lib.c b/arch/x86/kernel/cpu/cpufreq/speedstep-lib.c
index f4c290b8482f..ad0083abfa23 100644
--- a/arch/x86/kernel/cpu/cpufreq/speedstep-lib.c
+++ b/arch/x86/kernel/cpu/cpufreq/speedstep-lib.c
@@ -34,7 +34,7 @@ static int relaxed_check;
  *                   GET PROCESSOR CORE SPEED IN KHZ                 *
  *********************************************************************/
 
-static unsigned int pentium3_get_frequency(unsigned int processor)
+static unsigned int pentium3_get_frequency(enum speedstep_processor processor)
 {
         /* See table 14 of p3_ds.pdf and table 22 of 29834003.pdf */
         struct {
@@ -227,7 +227,7 @@ static unsigned int pentium4_get_frequency(void)
 
 
 /* Warning: may get called from smp_call_function_single. */
-unsigned int speedstep_get_frequency(unsigned int processor)
+unsigned int speedstep_get_frequency(enum speedstep_processor processor)
 {
         switch (processor) {
         case SPEEDSTEP_CPU_PCORE:
@@ -380,7 +380,7 @@ EXPORT_SYMBOL_GPL(speedstep_detect_processor);
  *                     DETECT SPEEDSTEP SPEEDS                       *
  *********************************************************************/
 
-unsigned int speedstep_get_freqs(unsigned int processor,
+unsigned int speedstep_get_freqs(enum speedstep_processor processor,
                                   unsigned int *low_speed,
                                   unsigned int *high_speed,
                                   unsigned int *transition_latency,
diff --git a/arch/x86/kernel/cpu/cpufreq/speedstep-lib.h b/arch/x86/kernel/cpu/cpufreq/speedstep-lib.h
index 2b6c04e5a304..70d9cea1219d 100644
--- a/arch/x86/kernel/cpu/cpufreq/speedstep-lib.h
+++ b/arch/x86/kernel/cpu/cpufreq/speedstep-lib.h
@@ -11,18 +11,18 @@
 
 
 /* processors */
-
-#define SPEEDSTEP_CPU_PIII_C_EARLY      0x00000001  /* Coppermine core */
-#define SPEEDSTEP_CPU_PIII_C            0x00000002  /* Coppermine core */
-#define SPEEDSTEP_CPU_PIII_T            0x00000003  /* Tualatin core */
-#define SPEEDSTEP_CPU_P4M               0x00000004  /* P4-M  */
-
+enum speedstep_processor {
+        SPEEDSTEP_CPU_PIII_C_EARLY = 0x00000001,  /* Coppermine core */
+        SPEEDSTEP_CPU_PIII_C       = 0x00000002,  /* Coppermine core */
+        SPEEDSTEP_CPU_PIII_T       = 0x00000003,  /* Tualatin core */
+        SPEEDSTEP_CPU_P4M          = 0x00000004,  /* P4-M  */
 /* the following processors are not speedstep-capable and are not auto-detected
  * in speedstep_detect_processor(). However, their speed can be detected using
  * the speedstep_get_frequency() call. */
-#define SPEEDSTEP_CPU_PM                0xFFFFFF03  /* Pentium M  */
-#define SPEEDSTEP_CPU_P4D               0xFFFFFF04  /* desktop P4  */
-#define SPEEDSTEP_CPU_PCORE             0xFFFFFF05  /* Core */
+        SPEEDSTEP_CPU_PM           = 0xFFFFFF03,  /* Pentium M  */
+        SPEEDSTEP_CPU_P4D          = 0xFFFFFF04,  /* desktop P4  */
+        SPEEDSTEP_CPU_PCORE        = 0xFFFFFF05,  /* Core */
+};
 
 /* speedstep states -- only two of them */
 
@@ -31,10 +31,10 @@
 
 
 /* detect a speedstep-capable processor */
-extern unsigned int speedstep_detect_processor (void);
+extern enum speedstep_processor speedstep_detect_processor(void);
 
 /* detect the current speed (in khz) of the processor */
-extern unsigned int speedstep_get_frequency(unsigned int processor);
+extern unsigned int speedstep_get_frequency(enum speedstep_processor processor);
 
 
 /* detect the low and high speeds of the processor. The callback
@@ -42,7 +42,7 @@ extern unsigned int speedstep_get_frequency(unsigned int processor);
  * SPEEDSTEP_LOW; the second argument is zero so that no
  * cpufreq_notify_transition calls are initiated.
  */
-extern unsigned int speedstep_get_freqs(unsigned int processor,
+extern unsigned int speedstep_get_freqs(enum speedstep_processor processor,
         unsigned int *low_speed,
         unsigned int *high_speed,
         unsigned int *transition_latency,
diff --git a/arch/x86/kernel/cpu/cpufreq/speedstep-smi.c b/arch/x86/kernel/cpu/cpufreq/speedstep-smi.c
index befea088e4f5..04d73c114e49 100644
--- a/arch/x86/kernel/cpu/cpufreq/speedstep-smi.c
+++ b/arch/x86/kernel/cpu/cpufreq/speedstep-smi.c
@@ -35,7 +35,7 @@ static int smi_cmd;
 static unsigned int smi_sig;
 
 /* info about the processor */
-static unsigned int speedstep_processor;
+static enum speedstep_processor speedstep_processor;
 
 /*
  * There are only two frequency states for each processor. Values
diff --git a/arch/x86/kernel/cpu/intel_cacheinfo.c b/arch/x86/kernel/cpu/intel_cacheinfo.c
index 63ada177b40c..fc6c8ef92dcc 100644
--- a/arch/x86/kernel/cpu/intel_cacheinfo.c
+++ b/arch/x86/kernel/cpu/intel_cacheinfo.c
@@ -499,8 +499,8 @@ unsigned int __cpuinit init_intel_cacheinfo(struct cpuinfo_x86 *c)
 #ifdef CONFIG_SYSFS
 
 /* pointer to _cpuid4_info array (for each cache leaf) */
-static DEFINE_PER_CPU(struct _cpuid4_info *, cpuid4_info);
-#define CPUID4_INFO_IDX(x, y)   (&((per_cpu(cpuid4_info, x))[y]))
+static DEFINE_PER_CPU(struct _cpuid4_info *, ici_cpuid4_info);
+#define CPUID4_INFO_IDX(x, y)   (&((per_cpu(ici_cpuid4_info, x))[y]))
 
 #ifdef CONFIG_SMP
 static void __cpuinit cache_shared_cpu_map_setup(unsigned int cpu, int index)
@@ -512,7 +512,7 @@ static void __cpuinit cache_shared_cpu_map_setup(unsigned int cpu, int index)
 
         if ((index == 3) && (c->x86_vendor == X86_VENDOR_AMD)) {
                 for_each_cpu(i, c->llc_shared_map) {
-                        if (!per_cpu(cpuid4_info, i))
+                        if (!per_cpu(ici_cpuid4_info, i))
                                 continue;
                         this_leaf = CPUID4_INFO_IDX(i, index);
                         for_each_cpu(sibling, c->llc_shared_map) {
@@ -536,7 +536,7 @@ static void __cpuinit cache_shared_cpu_map_setup(unsigned int cpu, int index)
                             c->apicid >> index_msb) {
                                 cpumask_set_cpu(i,
                                         to_cpumask(this_leaf->shared_cpu_map));
-                                if (i != cpu && per_cpu(cpuid4_info, i))  {
+                                if (i != cpu && per_cpu(ici_cpuid4_info, i))  {
                                         sibling_leaf =
                                                 CPUID4_INFO_IDX(i, index);
                                         cpumask_set_cpu(cpu, to_cpumask(
@@ -575,8 +575,8 @@ static void __cpuinit free_cache_attributes(unsigned int cpu)
         for (i = 0; i < num_cache_leaves; i++)
                 cache_remove_shared_cpu_map(cpu, i);
 
-        kfree(per_cpu(cpuid4_info, cpu));
-        per_cpu(cpuid4_info, cpu) = NULL;
+        kfree(per_cpu(ici_cpuid4_info, cpu));
+        per_cpu(ici_cpuid4_info, cpu) = NULL;
 }
 
 static int
@@ -615,15 +615,15 @@ static int __cpuinit detect_cache_attributes(unsigned int cpu)
         if (num_cache_leaves == 0)
                 return -ENOENT;
 
-        per_cpu(cpuid4_info, cpu) = kzalloc(
+        per_cpu(ici_cpuid4_info, cpu) = kzalloc(
             sizeof(struct _cpuid4_info) * num_cache_leaves, GFP_KERNEL);
-        if (per_cpu(cpuid4_info, cpu) == NULL)
+        if (per_cpu(ici_cpuid4_info, cpu) == NULL)
                 return -ENOMEM;
 
         smp_call_function_single(cpu, get_cpu_leaves, &retval, true);
         if (retval) {
-                kfree(per_cpu(cpuid4_info, cpu));
-                per_cpu(cpuid4_info, cpu) = NULL;
+                kfree(per_cpu(ici_cpuid4_info, cpu));
+                per_cpu(ici_cpuid4_info, cpu) = NULL;
         }
 
         return retval;
@@ -635,7 +635,7 @@ static int __cpuinit detect_cache_attributes(unsigned int cpu)
 extern struct sysdev_class cpu_sysdev_class; /* from drivers/base/cpu.c */
 
 /* pointer to kobject for cpuX/cache */
-static DEFINE_PER_CPU(struct kobject *, cache_kobject);
+static DEFINE_PER_CPU(struct kobject *, ici_cache_kobject);
 
 struct _index_kobject {
         struct kobject kobj;
@@ -644,8 +644,8 @@ struct _index_kobject {
 };
 
 /* pointer to array of kobjects for cpuX/cache/indexY */
-static DEFINE_PER_CPU(struct _index_kobject *, index_kobject);
-#define INDEX_KOBJECT_PTR(x, y)         (&((per_cpu(index_kobject, x))[y]))
+static DEFINE_PER_CPU(struct _index_kobject *, ici_index_kobject);
+#define INDEX_KOBJECT_PTR(x, y)         (&((per_cpu(ici_index_kobject, x))[y]))
 
 #define show_one_plus(file_name, object, val)                           \
 static ssize_t show_##file_name                                         \
@@ -864,10 +864,10 @@ static struct kobj_type ktype_percpu_entry = {
 
 static void __cpuinit cpuid4_cache_sysfs_exit(unsigned int cpu)
 {
-        kfree(per_cpu(cache_kobject, cpu));
-        kfree(per_cpu(index_kobject, cpu));
-        per_cpu(cache_kobject, cpu) = NULL;
-        per_cpu(index_kobject, cpu) = NULL;
+        kfree(per_cpu(ici_cache_kobject, cpu));
+        kfree(per_cpu(ici_index_kobject, cpu));
+        per_cpu(ici_cache_kobject, cpu) = NULL;
+        per_cpu(ici_index_kobject, cpu) = NULL;
         free_cache_attributes(cpu);
 }
 
@@ -883,14 +883,14 @@ static int __cpuinit cpuid4_cache_sysfs_init(unsigned int cpu)
                 return err;
 
         /* Allocate all required memory */
-        per_cpu(cache_kobject, cpu) =
+        per_cpu(ici_cache_kobject, cpu) =
                 kzalloc(sizeof(struct kobject), GFP_KERNEL);
-        if (unlikely(per_cpu(cache_kobject, cpu) == NULL))
+        if (unlikely(per_cpu(ici_cache_kobject, cpu) == NULL))
                 goto err_out;
 
-        per_cpu(index_kobject, cpu) = kzalloc(
+        per_cpu(ici_index_kobject, cpu) = kzalloc(
             sizeof(struct _index_kobject) * num_cache_leaves, GFP_KERNEL);
-        if (unlikely(per_cpu(index_kobject, cpu) == NULL))
+        if (unlikely(per_cpu(ici_index_kobject, cpu) == NULL))
                 goto err_out;
 
         return 0;
@@ -914,7 +914,7 @@ static int __cpuinit cache_add_dev(struct sys_device * sys_dev)
         if (unlikely(retval < 0))
                 return retval;
 
-        retval = kobject_init_and_add(per_cpu(cache_kobject, cpu),
+        retval = kobject_init_and_add(per_cpu(ici_cache_kobject, cpu),
                                       &ktype_percpu_entry,
                                       &sys_dev->kobj, "%s", "cache");
         if (retval < 0) {
@@ -928,12 +928,12 @@ static int __cpuinit cache_add_dev(struct sys_device * sys_dev)
                 this_object->index = i;
                 retval = kobject_init_and_add(&(this_object->kobj),
                                               &ktype_cache,
-                                              per_cpu(cache_kobject, cpu),
+                                              per_cpu(ici_cache_kobject, cpu),
                                               "index%1lu", i);
                 if (unlikely(retval)) {
                         for (j = 0; j < i; j++)
                                 kobject_put(&(INDEX_KOBJECT_PTR(cpu, j)->kobj));
-                        kobject_put(per_cpu(cache_kobject, cpu));
+                        kobject_put(per_cpu(ici_cache_kobject, cpu));
                         cpuid4_cache_sysfs_exit(cpu);
                         return retval;
                 }
@@ -941,7 +941,7 @@ static int __cpuinit cache_add_dev(struct sys_device * sys_dev)
         }
         cpumask_set_cpu(cpu, to_cpumask(cache_dev_map));
 
-        kobject_uevent(per_cpu(cache_kobject, cpu), KOBJ_ADD);
+        kobject_uevent(per_cpu(ici_cache_kobject, cpu), KOBJ_ADD);
         return 0;
 }
 
@@ -950,7 +950,7 @@ static void __cpuinit cache_remove_dev(struct sys_device * sys_dev)
         unsigned int cpu = sys_dev->id;
         unsigned long i;
 
-        if (per_cpu(cpuid4_info, cpu) == NULL)
+        if (per_cpu(ici_cpuid4_info, cpu) == NULL)
                 return;
         if (!cpumask_test_cpu(cpu, to_cpumask(cache_dev_map)))
                 return;
@@ -958,7 +958,7 @@ static void __cpuinit cache_remove_dev(struct sys_device * sys_dev)
 
         for (i = 0; i < num_cache_leaves; i++)
                 kobject_put(&(INDEX_KOBJECT_PTR(cpu, i)->kobj));
-        kobject_put(per_cpu(cache_kobject, cpu));
+        kobject_put(per_cpu(ici_cache_kobject, cpu));
         cpuid4_cache_sysfs_exit(cpu);
 }
 
diff --git a/arch/x86/kernel/cpu/mtrr/if.c b/arch/x86/kernel/cpu/mtrr/if.c
index 3c1b12d461d1..e006e56f699c 100644
--- a/arch/x86/kernel/cpu/mtrr/if.c
+++ b/arch/x86/kernel/cpu/mtrr/if.c
@@ -4,6 +4,7 @@
 #include <linux/proc_fs.h>
 #include <linux/module.h>
 #include <linux/ctype.h>
+#include <linux/string.h>
 #include <linux/init.h>
 
 #define LINE_SIZE 80
@@ -133,8 +134,7 @@ mtrr_write(struct file *file, const char __user *buf, size_t len, loff_t * ppos)
                 return -EINVAL;
 
         base = simple_strtoull(line + 5, &ptr, 0);
-        while (isspace(*ptr))
-                ptr++;
+        ptr = skip_spaces(ptr);
 
         if (strncmp(ptr, "size=", 5))
                 return -EINVAL;
@@ -142,14 +142,11 @@ mtrr_write(struct file *file, const char __user *buf, size_t len, loff_t * ppos)
         size = simple_strtoull(ptr + 5, &ptr, 0);
         if ((base & 0xfff) || (size & 0xfff))
                 return -EINVAL;
-        while (isspace(*ptr))
-                ptr++;
+        ptr = skip_spaces(ptr);
 
         if (strncmp(ptr, "type=", 5))
                 return -EINVAL;
-        ptr += 5;
-        while (isspace(*ptr))
-                ptr++;
+        ptr = skip_spaces(ptr + 5);
 
         for (i = 0; i < MTRR_NUM_TYPES; ++i) {
                 if (strcmp(ptr, mtrr_strings[i]))
diff --git a/arch/x86/kernel/cpu/perf_event.c b/arch/x86/kernel/cpu/perf_event.c
index ab1a8a89b984..45506d5dd8df 100644
--- a/arch/x86/kernel/cpu/perf_event.c
+++ b/arch/x86/kernel/cpu/perf_event.c
@@ -1632,6 +1632,7 @@ static void intel_pmu_drain_bts_buffer(struct cpu_hw_events *cpuc)
 
         data.period     = event->hw.last_period;
         data.addr       = 0;
+        data.raw        = NULL;
         regs.ip         = 0;
 
         /*
@@ -1749,6 +1750,7 @@ static int p6_pmu_handle_irq(struct pt_regs *regs)
         u64 val;
 
         data.addr = 0;
+        data.raw = NULL;
 
         cpuc = &__get_cpu_var(cpu_hw_events);
 
@@ -1794,6 +1796,7 @@ static int intel_pmu_handle_irq(struct pt_regs *regs)
         u64 ack, status;
 
         data.addr = 0;
+        data.raw = NULL;
 
         cpuc = &__get_cpu_var(cpu_hw_events);
 
@@ -1857,6 +1860,7 @@ static int amd_pmu_handle_irq(struct pt_regs *regs)
         u64 val;
 
         data.addr = 0;
+        data.raw = NULL;
 
         cpuc = &__get_cpu_var(cpu_hw_events);
 
@@ -2062,12 +2066,6 @@ static __init int p6_pmu_init(void)
 
         x86_pmu = p6_pmu;
 
-        if (!cpu_has_apic) {
-                pr_info("no APIC, boot with the \"lapic\" boot parameter to force-enable it.\n");
-                pr_info("no hardware sampling interrupt available.\n");
-                x86_pmu.apic = 0;
-        }
-
         return 0;
 }
 
@@ -2159,6 +2157,16 @@ static __init int amd_pmu_init(void)
         return 0;
 }
 
+static void __init pmu_check_apic(void)
+{
+        if (cpu_has_apic)
+                return;
+
+        x86_pmu.apic = 0;
+        pr_info("no APIC, boot with the \"lapic\" boot parameter to force-enable it.\n");
+        pr_info("no hardware sampling interrupt available.\n");
+}
+
 void __init init_hw_perf_events(void)
 {
         int err;
@@ -2180,6 +2188,8 @@ void __init init_hw_perf_events(void)
                 return;
         }
 
+        pmu_check_apic();
+
         pr_cont("%s PMU driver.\n", x86_pmu.name);
 
         if (x86_pmu.num_events > X86_PMC_MAX_GENERIC) {
@@ -2287,7 +2297,7 @@ void callchain_store(struct perf_callchain_entry *entry, u64 ip)
 
 static DEFINE_PER_CPU(struct perf_callchain_entry, pmc_irq_entry);
 static DEFINE_PER_CPU(struct perf_callchain_entry, pmc_nmi_entry);
-static DEFINE_PER_CPU(int, in_nmi_frame);
+static DEFINE_PER_CPU(int, in_ignored_frame);
 
 
 static void
@@ -2303,8 +2313,9 @@ static void backtrace_warning(void *data, char *msg)
 
 static int backtrace_stack(void *data, char *name)
 {
-        per_cpu(in_nmi_frame, smp_processor_id()) =
-                        x86_is_stack_id(NMI_STACK, name);
+        per_cpu(in_ignored_frame, smp_processor_id()) =
+                        x86_is_stack_id(NMI_STACK, name) ||
+                        x86_is_stack_id(DEBUG_STACK, name);
 
         return 0;
 }
@@ -2313,7 +2324,7 @@ static void backtrace_address(void *data, unsigned long addr, int reliable)
 {
         struct perf_callchain_entry *entry = data;
 
-        if (per_cpu(in_nmi_frame, smp_processor_id()))
+        if (per_cpu(in_ignored_frame, smp_processor_id()))
                 return;
 
         if (reliable)
diff --git a/arch/x86/kernel/ds.c b/arch/x86/kernel/ds.c
index ef42a038f1a6..1c47390dd0e5 100644
--- a/arch/x86/kernel/ds.c
+++ b/arch/x86/kernel/ds.c
@@ -265,13 +265,13 @@ struct ds_context {
         int                     cpu;
 };
 
-static DEFINE_PER_CPU(struct ds_context *, cpu_context);
+static DEFINE_PER_CPU(struct ds_context *, cpu_ds_context);
 
 
 static struct ds_context *ds_get_context(struct task_struct *task, int cpu)
 {
         struct ds_context **p_context =
-                (task ? &task->thread.ds_ctx : &per_cpu(cpu_context, cpu));
+                (task ? &task->thread.ds_ctx : &per_cpu(cpu_ds_context, cpu));
         struct ds_context *context = NULL;
         struct ds_context *new_context = NULL;
 
diff --git a/arch/x86/kernel/dumpstack.c b/arch/x86/kernel/dumpstack.c
index b8ce165dde5d..0a0aa1cec8f1 100644
--- a/arch/x86/kernel/dumpstack.c
+++ b/arch/x86/kernel/dumpstack.c
@@ -188,7 +188,7 @@ void dump_stack(void)
 }
 EXPORT_SYMBOL(dump_stack);
 
-static raw_spinlock_t die_lock = __RAW_SPIN_LOCK_UNLOCKED;
+static arch_spinlock_t die_lock = __ARCH_SPIN_LOCK_UNLOCKED;
 static int die_owner = -1;
 static unsigned int die_nest_count;
 
@@ -207,11 +207,11 @@ unsigned __kprobes long oops_begin(void)
         /* racy, but better than risking deadlock. */
         raw_local_irq_save(flags);
         cpu = smp_processor_id();
-        if (!__raw_spin_trylock(&die_lock)) {
+        if (!arch_spin_trylock(&die_lock)) {
                 if (cpu == die_owner)
                         /* nested oops. should stop eventually */;
                 else
-                        __raw_spin_lock(&die_lock);
+                        arch_spin_lock(&die_lock);
         }
         die_nest_count++;
         die_owner = cpu;
@@ -231,7 +231,7 @@ void __kprobes oops_end(unsigned long flags, struct pt_regs *regs, int signr)
         die_nest_count--;
         if (!die_nest_count)
                 /* Nest count reaches zero, release the lock. */
-                __raw_spin_unlock(&die_lock);
+                arch_spin_unlock(&die_lock);
         raw_local_irq_restore(flags);
         oops_exit();
 
diff --git a/arch/x86/kernel/dumpstack_64.c b/arch/x86/kernel/dumpstack_64.c
index 8e740934bd1f..b13af53883aa 100644
--- a/arch/x86/kernel/dumpstack_64.c
+++ b/arch/x86/kernel/dumpstack_64.c
@@ -103,6 +103,35 @@ static unsigned long *in_exception_stack(unsigned cpu, unsigned long stack,
         return NULL;
 }
 
+static inline int
+in_irq_stack(unsigned long *stack, unsigned long *irq_stack,
+             unsigned long *irq_stack_end)
+{
+        return (stack >= irq_stack && stack < irq_stack_end);
+}
+
+/*
+ * We are returning from the irq stack and go to the previous one.
+ * If the previous stack is also in the irq stack, then bp in the first
+ * frame of the irq stack points to the previous, interrupted one.
+ * Otherwise we have another level of indirection: We first save
+ * the bp of the previous stack, then we switch the stack to the irq one
+ * and save a new bp that links to the previous one.
+ * (See save_args())
+ */
+static inline unsigned long
+fixup_bp_irq_link(unsigned long bp, unsigned long *stack,
+                  unsigned long *irq_stack, unsigned long *irq_stack_end)
+{
+#ifdef CONFIG_FRAME_POINTER
+        struct stack_frame *frame = (struct stack_frame *)bp;
+
+        if (!in_irq_stack(stack, irq_stack, irq_stack_end))
+                return (unsigned long)frame->next_frame;
+#endif
+        return bp;
+}
+
 /*
  * x86-64 can have up to three kernel stacks:
  * process stack
@@ -175,7 +204,7 @@ void dump_trace(struct task_struct *task, struct pt_regs *regs,
                         irq_stack = irq_stack_end -
                                 (IRQ_STACK_SIZE - 64) / sizeof(*irq_stack);
 
-                        if (stack >= irq_stack && stack < irq_stack_end) {
+                        if (in_irq_stack(stack, irq_stack, irq_stack_end)) {
                                 if (ops->stack(data, "IRQ") < 0)
                                         break;
                                 bp = print_context_stack(tinfo, stack, bp,
@@ -186,6 +215,8 @@ void dump_trace(struct task_struct *task, struct pt_regs *regs,
                                  * pointer (index -1 to end) in the IRQ stack:
                                  */
                                 stack = (unsigned long *) (irq_stack_end[-1]);
+                                bp = fixup_bp_irq_link(bp, stack, irq_stack,
+                                                       irq_stack_end);
                                 irq_stack_end = NULL;
                                 ops->stack(data, "EOI");
                                 continue;
diff --git a/arch/x86/kernel/entry_64.S b/arch/x86/kernel/entry_64.S
index 73d9b2c0e217..0697ff139837 100644
--- a/arch/x86/kernel/entry_64.S
+++ b/arch/x86/kernel/entry_64.S
@@ -1076,10 +1076,10 @@ ENTRY(\sym)
         TRACE_IRQS_OFF
         movq %rsp,%rdi          /* pt_regs pointer */
         xorl %esi,%esi          /* no error code */
-        PER_CPU(init_tss, %rbp)
-        subq $EXCEPTION_STKSZ, TSS_ist + (\ist - 1) * 8(%rbp)
+        PER_CPU(init_tss, %r12)
+        subq $EXCEPTION_STKSZ, TSS_ist + (\ist - 1) * 8(%r12)
         call \do_sym
-        addq $EXCEPTION_STKSZ, TSS_ist + (\ist - 1) * 8(%rbp)
+        addq $EXCEPTION_STKSZ, TSS_ist + (\ist - 1) * 8(%r12)
         jmp paranoid_exit       /* %ebx: no swapgs flag */
         CFI_ENDPROC
 END(\sym)
diff --git a/arch/x86/kernel/geode_32.c b/arch/x86/kernel/geode_32.c
deleted file mode 100644
index 9b08e852fd1a..000000000000
--- a/arch/x86/kernel/geode_32.c
+++ /dev/null
@@ -1,196 +0,0 @@
-/*
- * AMD Geode southbridge support code
- * Copyright (C) 2006, Advanced Micro Devices, Inc.
- * Copyright (C) 2007, Andres Salomon <dilinger@debian.org>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of version 2 of the GNU General Public License
- * as published by the Free Software Foundation.
- */
-
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/ioport.h>
-#include <linux/io.h>
-#include <asm/msr.h>
-#include <asm/geode.h>
-
-static struct {
-        char *name;
-        u32 msr;
-        int size;
-        u32 base;
-} lbars[] = {
-        { "geode-pms",   MSR_LBAR_PMS, LBAR_PMS_SIZE, 0 },
-        { "geode-acpi",  MSR_LBAR_ACPI, LBAR_ACPI_SIZE, 0 },
-        { "geode-gpio",  MSR_LBAR_GPIO, LBAR_GPIO_SIZE, 0 },
-        { "geode-mfgpt", MSR_LBAR_MFGPT, LBAR_MFGPT_SIZE, 0 }
-};
-
-static void __init init_lbars(void)
-{
-        u32 lo, hi;
-        int i;
-
-        for (i = 0; i < ARRAY_SIZE(lbars); i++) {
-                rdmsr(lbars[i].msr, lo, hi);
-                if (hi & 0x01)
-                        lbars[i].base = lo & 0x0000ffff;
-
-                if (lbars[i].base == 0)
-                        printk(KERN_ERR "geode:  Couldn't initialize '%s'\n",
-                                        lbars[i].name);
-        }
-}
-
-int geode_get_dev_base(unsigned int dev)
-{
-        BUG_ON(dev >= ARRAY_SIZE(lbars));
-        return lbars[dev].base;
-}
-EXPORT_SYMBOL_GPL(geode_get_dev_base);
-
-/* === GPIO API === */
-
-void geode_gpio_set(u32 gpio, unsigned int reg)
-{
-        u32 base = geode_get_dev_base(GEODE_DEV_GPIO);
-
-        if (!base)
-                return;
-
-        /* low bank register */
-        if (gpio & 0xFFFF)
-                outl(gpio & 0xFFFF, base + reg);
-        /* high bank register */
-        gpio >>= 16;
-        if (gpio)
-                outl(gpio, base + 0x80 + reg);
-}
-EXPORT_SYMBOL_GPL(geode_gpio_set);
-
-void geode_gpio_clear(u32 gpio, unsigned int reg)
-{
-        u32 base = geode_get_dev_base(GEODE_DEV_GPIO);
-
-        if (!base)
-                return;
-
-        /* low bank register */
-        if (gpio & 0xFFFF)
-                outl((gpio & 0xFFFF) << 16, base + reg);
-        /* high bank register */
-        gpio &= (0xFFFF << 16);
-        if (gpio)
-                outl(gpio, base + 0x80 + reg);
-}
-EXPORT_SYMBOL_GPL(geode_gpio_clear);
-
-int geode_gpio_isset(u32 gpio, unsigned int reg)
-{
-        u32 base = geode_get_dev_base(GEODE_DEV_GPIO);
-        u32 val;
-
-        if (!base)
-                return 0;
-
-        /* low bank register */
-        if (gpio & 0xFFFF) {
-                val = inl(base + reg) & (gpio & 0xFFFF);
-                if ((gpio & 0xFFFF) == val)
-                        return 1;
-        }
-        /* high bank register */
-        gpio >>= 16;
-        if (gpio) {
-                val = inl(base + 0x80 + reg) & gpio;
-                if (gpio == val)
-                        return 1;
-        }
-        return 0;
-}
-EXPORT_SYMBOL_GPL(geode_gpio_isset);
-
-void geode_gpio_set_irq(unsigned int group, unsigned int irq)
-{
-        u32 lo, hi;
-
-        if (group > 7 || irq > 15)
-                return;
-
-        rdmsr(MSR_PIC_ZSEL_HIGH, lo, hi);
-
-        lo &= ~(0xF << (group * 4));
-        lo |= (irq & 0xF) << (group * 4);
-
-        wrmsr(MSR_PIC_ZSEL_HIGH, lo, hi);
-}
-EXPORT_SYMBOL_GPL(geode_gpio_set_irq);
-
-void geode_gpio_setup_event(unsigned int gpio, int pair, int pme)
-{
-        u32 base = geode_get_dev_base(GEODE_DEV_GPIO);
-        u32 offset, shift, val;
-
-        if (gpio >= 24)
-                offset = GPIO_MAP_W;
-        else if (gpio >= 16)
-                offset = GPIO_MAP_Z;
-        else if (gpio >= 8)
-                offset = GPIO_MAP_Y;
-        else
-                offset = GPIO_MAP_X;
-
-        shift = (gpio % 8) * 4;
-
-        val = inl(base + offset);
-
-        /* Clear whatever was there before */
-        val &= ~(0xF << shift);
-
-        /* And set the new value */
-
-        val |= ((pair & 7) << shift);
-
-        /* Set the PME bit if this is a PME event */
-
-        if (pme)
-                val |= (1 << (shift + 3));
-
-        outl(val, base + offset);
-}
-EXPORT_SYMBOL_GPL(geode_gpio_setup_event);
-
-int geode_has_vsa2(void)
-{
-        static int has_vsa2 = -1;
-
-        if (has_vsa2 == -1) {
-                u16 val;
-
-                /*
-                 * The VSA has virtual registers that we can query for a
-                 * signature.
-                 */
-                outw(VSA_VR_UNLOCK, VSA_VRC_INDEX);
-                outw(VSA_VR_SIGNATURE, VSA_VRC_INDEX);
-
-                val = inw(VSA_VRC_DATA);
-                has_vsa2 = (val == AMD_VSA_SIG || val == GSW_VSA_SIG);
-        }
-
-        return has_vsa2;
-}
-EXPORT_SYMBOL_GPL(geode_has_vsa2);
-
-static int __init geode_southbridge_init(void)
-{
-        if (!is_geode())
-                return -ENODEV;
-
-        init_lbars();
-        (void) mfgpt_timer_setup();
-        return 0;
-}
-
-postcore_initcall(geode_southbridge_init);
diff --git a/arch/x86/kernel/hw_breakpoint.c b/arch/x86/kernel/hw_breakpoint.c
index d42f65ac4927..05d5fec64a94 100644
--- a/arch/x86/kernel/hw_breakpoint.c
+++ b/arch/x86/kernel/hw_breakpoint.c
@@ -362,8 +362,7 @@ int arch_validate_hwbkpt_settings(struct perf_event *bp,
                 return ret;
         }
 
-        if (bp->callback)
-                ret = arch_store_info(bp);
+        ret = arch_store_info(bp);
 
         if (ret < 0)
                 return ret;
@@ -519,7 +518,7 @@ static int __kprobes hw_breakpoint_handler(struct die_args *args)
                         break;
                 }
 
-                (bp->callback)(bp, args->regs);
+                perf_bp_event(bp, args->regs);
 
                 rcu_read_unlock();
         }
diff --git a/arch/x86/kernel/irq.c b/arch/x86/kernel/irq.c
index 664bcb7384ac..91fd0c70a18a 100644
--- a/arch/x86/kernel/irq.c
+++ b/arch/x86/kernel/irq.c
@@ -149,7 +149,7 @@ int show_interrupts(struct seq_file *p, void *v)
         if (!desc)
                 return 0;
 
-        spin_lock_irqsave(&desc->lock, flags);
+        raw_spin_lock_irqsave(&desc->lock, flags);
         for_each_online_cpu(j)
                 any_count |= kstat_irqs_cpu(i, j);
         action = desc->action;
@@ -170,7 +170,7 @@ int show_interrupts(struct seq_file *p, void *v)
 
         seq_putc(p, '\n');
 out:
-        spin_unlock_irqrestore(&desc->lock, flags);
+        raw_spin_unlock_irqrestore(&desc->lock, flags);
         return 0;
 }
 
@@ -294,12 +294,12 @@ void fixup_irqs(void)
                         continue;
 
                 /* interrupt's are disabled at this point */
-                spin_lock(&desc->lock);
+                raw_spin_lock(&desc->lock);
 
                 affinity = desc->affinity;
                 if (!irq_has_action(irq) ||
                     cpumask_equal(affinity, cpu_online_mask)) {
-                        spin_unlock(&desc->lock);
+                        raw_spin_unlock(&desc->lock);
                         continue;
                 }
 
@@ -326,7 +326,7 @@ void fixup_irqs(void)
                 if (!(desc->status & IRQ_MOVE_PCNTXT) && desc->chip->unmask)
                         desc->chip->unmask(irq);
 
-                spin_unlock(&desc->lock);
+                raw_spin_unlock(&desc->lock);
 
                 if (break_affinity && set_affinity)
                         printk("Broke affinity for irq %i\n", irq);
@@ -356,10 +356,10 @@ void fixup_irqs(void)
                         irq = __get_cpu_var(vector_irq)[vector];
 
                         desc = irq_to_desc(irq);
-                        spin_lock(&desc->lock);
+                        raw_spin_lock(&desc->lock);
                         if (desc->chip->retrigger)
                                 desc->chip->retrigger(irq);
-                        spin_unlock(&desc->lock);
+                        raw_spin_unlock(&desc->lock);
                 }
         }
 }
diff --git a/arch/x86/kernel/kgdb.c b/arch/x86/kernel/kgdb.c
index 20a5b3689463..dd74fe7273b1 100644
--- a/arch/x86/kernel/kgdb.c
+++ b/arch/x86/kernel/kgdb.c
@@ -86,9 +86,15 @@ void pt_regs_to_gdb_regs(unsigned long *gdb_regs, struct pt_regs *regs)
         gdb_regs[GDB_DS]        = regs->ds;
         gdb_regs[GDB_ES]        = regs->es;
         gdb_regs[GDB_CS]        = regs->cs;
-        gdb_regs[GDB_SS]        = __KERNEL_DS;
         gdb_regs[GDB_FS]        = 0xFFFF;
         gdb_regs[GDB_GS]        = 0xFFFF;
+        if (user_mode_vm(regs)) {
+                gdb_regs[GDB_SS] = regs->ss;
+                gdb_regs[GDB_SP] = regs->sp;
+        } else {
+                gdb_regs[GDB_SS] = __KERNEL_DS;
+                gdb_regs[GDB_SP] = kernel_stack_pointer(regs);
+        }
 #else
         gdb_regs[GDB_R8]        = regs->r8;
         gdb_regs[GDB_R9]        = regs->r9;
@@ -101,8 +107,8 @@ void pt_regs_to_gdb_regs(unsigned long *gdb_regs, struct pt_regs *regs)
         gdb_regs32[GDB_PS]      = regs->flags;
         gdb_regs32[GDB_CS]      = regs->cs;
         gdb_regs32[GDB_SS]      = regs->ss;
-#endif
         gdb_regs[GDB_SP]        = kernel_stack_pointer(regs);
+#endif
 }
 
 /**
@@ -220,8 +226,7 @@ static void kgdb_correct_hw_break(void)
                         dr7 |= ((breakinfo[breakno].len << 2) |
                                  breakinfo[breakno].type) <<
                                ((breakno << 2) + 16);
-                        if (breakno >= 0 && breakno <= 3)
-                                set_debugreg(breakinfo[breakno].addr, breakno);
+                        set_debugreg(breakinfo[breakno].addr, breakno);
 
                 } else {
                         if ((dr7 & breakbit) && !breakinfo[breakno].enabled) {
@@ -395,7 +400,6 @@ int kgdb_arch_handle_exception(int e_vector, int signo, int err_code,
                 /* set the trace bit if we're stepping */
                 if (remcomInBuffer[0] == 's') {
                         linux_regs->flags |= X86_EFLAGS_TF;
-                        kgdb_single_step = 1;
                         atomic_set(&kgdb_cpu_doing_single_step,
                                    raw_smp_processor_id());
                 }
diff --git a/arch/x86/kernel/mfgpt_32.c b/arch/x86/kernel/mfgpt_32.c
deleted file mode 100644
index 2a62d843f015..000000000000
--- a/arch/x86/kernel/mfgpt_32.c
+++ /dev/null
@@ -1,410 +0,0 @@
-/*
- * Driver/API for AMD Geode Multi-Function General Purpose Timers (MFGPT)
- *
- * Copyright (C) 2006, Advanced Micro Devices, Inc.
- * Copyright (C) 2007, Andres Salomon <dilinger@debian.org>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of version 2 of the GNU General Public License
- * as published by the Free Software Foundation.
- *
- * The MFGPTs are documented in AMD Geode CS5536 Companion Device Data Book.
- */
-
-/*
- * We are using the 32.768kHz input clock - it's the only one that has the
- * ranges we find desirable.  The following table lists the suitable
- * divisors and the associated Hz, minimum interval and the maximum interval:
- *
- *  Divisor   Hz      Min Delta (s)  Max Delta (s)
- *   1        32768   .00048828125      2.000
- *   2        16384   .0009765625       4.000
- *   4         8192   .001953125        8.000
- *   8         4096   .00390625        16.000
- *   16        2048   .0078125         32.000
- *   32        1024   .015625          64.000
- *   64         512   .03125          128.000
- *  128         256   .0625           256.000
- *  256         128   .125            512.000
- */
-
-#include <linux/kernel.h>
-#include <linux/interrupt.h>
-#include <linux/module.h>
-#include <asm/geode.h>
-
-#define MFGPT_DEFAULT_IRQ       7
-
-static struct mfgpt_timer_t {
-        unsigned int avail:1;
-} mfgpt_timers[MFGPT_MAX_TIMERS];
-
-/* Selected from the table above */
-
-#define MFGPT_DIVISOR 16
-#define MFGPT_SCALE  4     /* divisor = 2^(scale) */
-#define MFGPT_HZ  (32768 / MFGPT_DIVISOR)
-#define MFGPT_PERIODIC (MFGPT_HZ / HZ)
-
-/* Allow for disabling of MFGPTs */
-static int disable;
-static int __init mfgpt_disable(char *s)
-{
-        disable = 1;
-        return 1;
-}
-__setup("nomfgpt", mfgpt_disable);
-
-/* Reset the MFGPT timers. This is required by some broken BIOSes which already
- * do the same and leave the system in an unstable state. TinyBIOS 0.98 is
- * affected at least (0.99 is OK with MFGPT workaround left to off).
- */
-static int __init mfgpt_fix(char *s)
-{
-        u32 val, dummy;
-
-        /* The following udocumented bit resets the MFGPT timers */
-        val = 0xFF; dummy = 0;
-        wrmsr(MSR_MFGPT_SETUP, val, dummy);
-        return 1;
-}
-__setup("mfgptfix", mfgpt_fix);
-
-/*
- * Check whether any MFGPTs are available for the kernel to use.  In most
- * cases, firmware that uses AMD's VSA code will claim all timers during
- * bootup; we certainly don't want to take them if they're already in use.
- * In other cases (such as with VSAless OpenFirmware), the system firmware
- * leaves timers available for us to use.
- */
-
-
-static int timers = -1;
-
-static void geode_mfgpt_detect(void)
-{
-        int i;
-        u16 val;
-
-        timers = 0;
-
-        if (disable) {
-                printk(KERN_INFO "geode-mfgpt:  MFGPT support is disabled\n");
-                goto done;
-        }
-
-        if (!geode_get_dev_base(GEODE_DEV_MFGPT)) {
-                printk(KERN_INFO "geode-mfgpt:  MFGPT LBAR is not set up\n");
-                goto done;
-        }
-
-        for (i = 0; i < MFGPT_MAX_TIMERS; i++) {
-                val = geode_mfgpt_read(i, MFGPT_REG_SETUP);
-                if (!(val & MFGPT_SETUP_SETUP)) {
-                        mfgpt_timers[i].avail = 1;
-                        timers++;
-                }
-        }
-
-done:
-        printk(KERN_INFO "geode-mfgpt:  %d MFGPT timers available.\n", timers);
-}
-
-int geode_mfgpt_toggle_event(int timer, int cmp, int event, int enable)
-{
-        u32 msr, mask, value, dummy;
-        int shift = (cmp == MFGPT_CMP1) ? 0 : 8;
-
-        if (timer < 0 || timer >= MFGPT_MAX_TIMERS)
-                return -EIO;
-
-        /*
-         * The register maps for these are described in sections 6.17.1.x of
-         * the AMD Geode CS5536 Companion Device Data Book.
-         */
-        switch (event) {
-        case MFGPT_EVENT_RESET:
-                /*
-                 * XXX: According to the docs, we cannot reset timers above
-                 * 6; that is, resets for 7 and 8 will be ignored.  Is this
-                 * a problem?   -dilinger
-                 */
-                msr = MSR_MFGPT_NR;
-                mask = 1 << (timer + 24);
-                break;
-
-        case MFGPT_EVENT_NMI:
-                msr = MSR_MFGPT_NR;
-                mask = 1 << (timer + shift);
-                break;
-
-        case MFGPT_EVENT_IRQ:
-                msr = MSR_MFGPT_IRQ;
-                mask = 1 << (timer + shift);
-                break;
-
-        default:
-                return -EIO;
-        }
-
-        rdmsr(msr, value, dummy);
-
-        if (enable)
-                value |= mask;
-        else
-                value &= ~mask;
-
-        wrmsr(msr, value, dummy);
-        return 0;
-}
-EXPORT_SYMBOL_GPL(geode_mfgpt_toggle_event);
-
-int geode_mfgpt_set_irq(int timer, int cmp, int *irq, int enable)
-{
-        u32 zsel, lpc, dummy;
-        int shift;
-
-        if (timer < 0 || timer >= MFGPT_MAX_TIMERS)
-                return -EIO;
-
-        /*
-         * Unfortunately, MFGPTs come in pairs sharing their IRQ lines. If VSA
-         * is using the same CMP of the timer's Siamese twin, the IRQ is set to
-         * 2, and we mustn't use nor change it.
-         * XXX: Likewise, 2 Linux drivers might clash if the 2nd overwrites the
-         * IRQ of the 1st. This can only happen if forcing an IRQ, calling this
-         * with *irq==0 is safe. Currently there _are_ no 2 drivers.
-         */
-        rdmsr(MSR_PIC_ZSEL_LOW, zsel, dummy);
-        shift = ((cmp == MFGPT_CMP1 ? 0 : 4) + timer % 4) * 4;
-        if (((zsel >> shift) & 0xF) == 2)
-                return -EIO;
-
-        /* Choose IRQ: if none supplied, keep IRQ already set or use default */
-        if (!*irq)
-                *irq = (zsel >> shift) & 0xF;
-        if (!*irq)
-                *irq = MFGPT_DEFAULT_IRQ;
-
-        /* Can't use IRQ if it's 0 (=disabled), 2, or routed to LPC */
-        if (*irq < 1 || *irq == 2 || *irq > 15)
-                return -EIO;
-        rdmsr(MSR_PIC_IRQM_LPC, lpc, dummy);
-        if (lpc & (1 << *irq))
-                return -EIO;
-
-        /* All chosen and checked - go for it */
-        if (geode_mfgpt_toggle_event(timer, cmp, MFGPT_EVENT_IRQ, enable))
-                return -EIO;
-        if (enable) {
-                zsel = (zsel & ~(0xF << shift)) | (*irq << shift);
-                wrmsr(MSR_PIC_ZSEL_LOW, zsel, dummy);
-        }
-
-        return 0;
-}
-
-static int mfgpt_get(int timer)
-{
-        mfgpt_timers[timer].avail = 0;
-        printk(KERN_INFO "geode-mfgpt:  Registered timer %d\n", timer);
-        return timer;
-}
-
-int geode_mfgpt_alloc_timer(int timer, int domain)
-{
-        int i;
-
-        if (timers == -1) {
-                /* timers haven't been detected yet */
-                geode_mfgpt_detect();
-        }
-
-        if (!timers)
-                return -1;
-
-        if (timer >= MFGPT_MAX_TIMERS)
-                return -1;
-
-        if (timer < 0) {
-                /* Try to find an available timer */
-                for (i = 0; i < MFGPT_MAX_TIMERS; i++) {
-                        if (mfgpt_timers[i].avail)
-                                return mfgpt_get(i);
-
-                        if (i == 5 && domain == MFGPT_DOMAIN_WORKING)
-                                break;
-                }
-        } else {
-                /* If they requested a specific timer, try to honor that */
-                if (mfgpt_timers[timer].avail)
-                        return mfgpt_get(timer);
-        }
-
-        /* No timers available - too bad */
-        return -1;
-}
-EXPORT_SYMBOL_GPL(geode_mfgpt_alloc_timer);
-
-
-#ifdef CONFIG_GEODE_MFGPT_TIMER
-
-/*
- * The MFPGT timers on the CS5536 provide us with suitable timers to use
- * as clock event sources - not as good as a HPET or APIC, but certainly
- * better than the PIT.  This isn't a general purpose MFGPT driver, but
- * a simplified one designed specifically to act as a clock event source.
- * For full details about the MFGPT, please consult the CS5536 data sheet.
- */
-
-#include <linux/clocksource.h>
-#include <linux/clockchips.h>
-
-static unsigned int mfgpt_tick_mode = CLOCK_EVT_MODE_SHUTDOWN;
-static u16 mfgpt_event_clock;
-
-static int irq;
-static int __init mfgpt_setup(char *str)
-{
-        get_option(&str, &irq);
-        return 1;
-}
-__setup("mfgpt_irq=", mfgpt_setup);
-
-static void mfgpt_disable_timer(u16 clock)
-{
-        /* avoid races by clearing CMP1 and CMP2 unconditionally */
-        geode_mfgpt_write(clock, MFGPT_REG_SETUP, (u16) ~MFGPT_SETUP_CNTEN |
-                        MFGPT_SETUP_CMP1 | MFGPT_SETUP_CMP2);
-}
-
-static int mfgpt_next_event(unsigned long, struct clock_event_device *);
-static void mfgpt_set_mode(enum clock_event_mode, struct clock_event_device *);
-
-static struct clock_event_device mfgpt_clockevent = {
-        .name = "mfgpt-timer",
-        .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
-        .set_mode = mfgpt_set_mode,
-        .set_next_event = mfgpt_next_event,
-        .rating = 250,
-        .cpumask = cpu_all_mask,
-        .shift = 32
-};
-
-static void mfgpt_start_timer(u16 delta)
-{
-        geode_mfgpt_write(mfgpt_event_clock, MFGPT_REG_CMP2, (u16) delta);
-        geode_mfgpt_write(mfgpt_event_clock, MFGPT_REG_COUNTER, 0);
-
-        geode_mfgpt_write(mfgpt_event_clock, MFGPT_REG_SETUP,
-                          MFGPT_SETUP_CNTEN | MFGPT_SETUP_CMP2);
-}
-
-static void mfgpt_set_mode(enum clock_event_mode mode,
-                           struct clock_event_device *evt)
-{
-        mfgpt_disable_timer(mfgpt_event_clock);
-
-        if (mode == CLOCK_EVT_MODE_PERIODIC)
-                mfgpt_start_timer(MFGPT_PERIODIC);
-
-        mfgpt_tick_mode = mode;
-}
-
-static int mfgpt_next_event(unsigned long delta, struct clock_event_device *evt)
-{
-        mfgpt_start_timer(delta);
-        return 0;
-}
-
-static irqreturn_t mfgpt_tick(int irq, void *dev_id)
-{
-        u16 val = geode_mfgpt_read(mfgpt_event_clock, MFGPT_REG_SETUP);
-
-        /* See if the interrupt was for us */
-        if (!(val & (MFGPT_SETUP_SETUP  | MFGPT_SETUP_CMP2 | MFGPT_SETUP_CMP1)))
-                return IRQ_NONE;
-
-        /* Turn off the clock (and clear the event) */
-        mfgpt_disable_timer(mfgpt_event_clock);
-
-        if (mfgpt_tick_mode == CLOCK_EVT_MODE_SHUTDOWN)
-                return IRQ_HANDLED;
-
-        /* Clear the counter */
-        geode_mfgpt_write(mfgpt_event_clock, MFGPT_REG_COUNTER, 0);
-
-        /* Restart the clock in periodic mode */
-
-        if (mfgpt_tick_mode == CLOCK_EVT_MODE_PERIODIC) {
-                geode_mfgpt_write(mfgpt_event_clock, MFGPT_REG_SETUP,
-                                  MFGPT_SETUP_CNTEN | MFGPT_SETUP_CMP2);
-        }
-
-        mfgpt_clockevent.event_handler(&mfgpt_clockevent);
-        return IRQ_HANDLED;
-}
-
-static struct irqaction mfgptirq  = {
-        .handler = mfgpt_tick,
-        .flags = IRQF_DISABLED | IRQF_NOBALANCING | IRQF_TIMER,
-        .name = "mfgpt-timer"
-};
-
-int __init mfgpt_timer_setup(void)
-{
-        int timer, ret;
-        u16 val;
-
-        timer = geode_mfgpt_alloc_timer(MFGPT_TIMER_ANY, MFGPT_DOMAIN_WORKING);
-        if (timer < 0) {
-                printk(KERN_ERR
-                       "mfgpt-timer:  Could not allocate a MFPGT timer\n");
-                return -ENODEV;
-        }
-
-        mfgpt_event_clock = timer;
-
-        /* Set up the IRQ on the MFGPT side */
-        if (geode_mfgpt_setup_irq(mfgpt_event_clock, MFGPT_CMP2, &irq)) {
-                printk(KERN_ERR "mfgpt-timer:  Could not set up IRQ %d\n", irq);
-                return -EIO;
-        }
-
-        /* And register it with the kernel */
-        ret = setup_irq(irq, &mfgptirq);
-
-        if (ret) {
-                printk(KERN_ERR
-                       "mfgpt-timer:  Unable to set up the interrupt.\n");
-                goto err;
-        }
-
-        /* Set the clock scale and enable the event mode for CMP2 */
-        val = MFGPT_SCALE | (3 << 8);
-
-        geode_mfgpt_write(mfgpt_event_clock, MFGPT_REG_SETUP, val);
-
-        /* Set up the clock event */
-        mfgpt_clockevent.mult = div_sc(MFGPT_HZ, NSEC_PER_SEC,
-                                       mfgpt_clockevent.shift);
-        mfgpt_clockevent.min_delta_ns = clockevent_delta2ns(0xF,
-                        &mfgpt_clockevent);
-        mfgpt_clockevent.max_delta_ns = clockevent_delta2ns(0xFFFE,
-                        &mfgpt_clockevent);
-
-        printk(KERN_INFO
-               "mfgpt-timer:  Registering MFGPT timer %d as a clock event, using IRQ %d\n",
-               timer, irq);
-        clockevents_register_device(&mfgpt_clockevent);
-
-        return 0;
-
-err:
-        geode_mfgpt_release_irq(mfgpt_event_clock, MFGPT_CMP2, &irq);
-        printk(KERN_ERR
-               "mfgpt-timer:  Unable to set up the MFGPT clock source\n");
-        return -EIO;
-}
-
-#endif
diff --git a/arch/x86/kernel/olpc.c b/arch/x86/kernel/olpc.c
index 4006c522adc7..9d1d263f786f 100644
--- a/arch/x86/kernel/olpc.c
+++ b/arch/x86/kernel/olpc.c
@@ -212,7 +212,7 @@ static int __init olpc_init(void)
         unsigned char *romsig;
 
         /* The ioremap check is dangerous; limit what we run it on */
-        if (!is_geode() || geode_has_vsa2())
+        if (!is_geode() || cs5535_has_vsa2())
                 return 0;
 
         spin_lock_init(&ec_lock);
@@ -244,7 +244,7 @@ static int __init olpc_init(void)
                         (unsigned char *) &olpc_platform_info.ecver, 1);
 
         /* check to see if the VSA exists */
-        if (geode_has_vsa2())
+        if (cs5535_has_vsa2())
                 olpc_platform_info.flags |= OLPC_F_VSA;
 
         printk(KERN_INFO "OLPC board revision %s%X (EC=%x)\n",
diff --git a/arch/x86/kernel/paravirt-spinlocks.c b/arch/x86/kernel/paravirt-spinlocks.c
index 3a7c5a44082e..676b8c77a976 100644
--- a/arch/x86/kernel/paravirt-spinlocks.c
+++ b/arch/x86/kernel/paravirt-spinlocks.c
@@ -8,9 +8,9 @@
 #include <asm/paravirt.h>
 
 static inline void
-default_spin_lock_flags(raw_spinlock_t *lock, unsigned long flags)
+default_spin_lock_flags(arch_spinlock_t *lock, unsigned long flags)
 {
-        __raw_spin_lock(lock);
+        arch_spin_lock(lock);
 }
 
 struct pv_lock_ops pv_lock_ops = {
diff --git a/arch/x86/kernel/pci-calgary_64.c b/arch/x86/kernel/pci-calgary_64.c
index c563e4c8ff39..2bbde6078143 100644
--- a/arch/x86/kernel/pci-calgary_64.c
+++ b/arch/x86/kernel/pci-calgary_64.c
@@ -31,7 +31,7 @@
 #include <linux/string.h>
 #include <linux/crash_dump.h>
 #include <linux/dma-mapping.h>
-#include <linux/bitops.h>
+#include <linux/bitmap.h>
 #include <linux/pci_ids.h>
 #include <linux/pci.h>
 #include <linux/delay.h>
@@ -212,7 +212,7 @@ static void iommu_range_reserve(struct iommu_table *tbl,
 
         spin_lock_irqsave(&tbl->it_lock, flags);
 
-        iommu_area_reserve(tbl->it_map, index, npages);
+        bitmap_set(tbl->it_map, index, npages);
 
         spin_unlock_irqrestore(&tbl->it_lock, flags);
 }
@@ -303,7 +303,7 @@ static void iommu_free(struct iommu_table *tbl, dma_addr_t dma_addr,
 
         spin_lock_irqsave(&tbl->it_lock, flags);
 
-        iommu_area_free(tbl->it_map, entry, npages);
+        bitmap_clear(tbl->it_map, entry, npages);
 
         spin_unlock_irqrestore(&tbl->it_lock, flags);
 }
diff --git a/arch/x86/kernel/pci-gart_64.c b/arch/x86/kernel/pci-gart_64.c
index 56c0e730d3fe..34de53b46f87 100644
--- a/arch/x86/kernel/pci-gart_64.c
+++ b/arch/x86/kernel/pci-gart_64.c
@@ -23,7 +23,7 @@
 #include <linux/module.h>
 #include <linux/topology.h>
 #include <linux/interrupt.h>
-#include <linux/bitops.h>
+#include <linux/bitmap.h>
 #include <linux/kdebug.h>
 #include <linux/scatterlist.h>
 #include <linux/iommu-helper.h>
@@ -126,7 +126,7 @@ static void free_iommu(unsigned long offset, int size)
         unsigned long flags;
 
         spin_lock_irqsave(&iommu_bitmap_lock, flags);
-        iommu_area_free(iommu_gart_bitmap, offset, size);
+        bitmap_clear(iommu_gart_bitmap, offset, size);
         if (offset >= next_bit)
                 next_bit = offset + size;
         spin_unlock_irqrestore(&iommu_bitmap_lock, flags);
@@ -792,7 +792,7 @@ int __init gart_iommu_init(void)
          * Out of IOMMU space handling.
          * Reserve some invalid pages at the beginning of the GART.
          */
-        iommu_area_reserve(iommu_gart_bitmap, 0, EMERGENCY_PAGES);
+        bitmap_set(iommu_gart_bitmap, 0, EMERGENCY_PAGES);
 
         pr_info("PCI-DMA: Reserving %luMB of IOMMU area in the AGP aperture\n",
                iommu_size >> 20);
diff --git a/arch/x86/kernel/ptrace.c b/arch/x86/kernel/ptrace.c
index 04d182a7cfdb..017d937639fe 100644
--- a/arch/x86/kernel/ptrace.c
+++ b/arch/x86/kernel/ptrace.c
@@ -509,14 +509,14 @@ static int genregs_get(struct task_struct *target,
 {
         if (kbuf) {
                 unsigned long *k = kbuf;
-                while (count > 0) {
+                while (count >= sizeof(*k)) {
                         *k++ = getreg(target, pos);
                         count -= sizeof(*k);
                         pos += sizeof(*k);
                 }
         } else {
                 unsigned long __user *u = ubuf;
-                while (count > 0) {
+                while (count >= sizeof(*u)) {
                         if (__put_user(getreg(target, pos), u++))
                                 return -EFAULT;
                         count -= sizeof(*u);
@@ -535,14 +535,14 @@ static int genregs_set(struct task_struct *target,
         int ret = 0;
         if (kbuf) {
                 const unsigned long *k = kbuf;
-                while (count > 0 && !ret) {
+                while (count >= sizeof(*k) && !ret) {
                         ret = putreg(target, pos, *k++);
                         count -= sizeof(*k);
                         pos += sizeof(*k);
                 }
         } else {
                 const unsigned long  __user *u = ubuf;
-                while (count > 0 && !ret) {
+                while (count >= sizeof(*u) && !ret) {
                         unsigned long word;
                         ret = __get_user(word, u++);
                         if (ret)
@@ -555,7 +555,9 @@ static int genregs_set(struct task_struct *target,
         return ret;
 }
 
-static void ptrace_triggered(struct perf_event *bp, void *data)
+static void ptrace_triggered(struct perf_event *bp, int nmi,
+                             struct perf_sample_data *data,
+                             struct pt_regs *regs)
 {
         int i;
         struct thread_struct *thread = &(current->thread);
@@ -593,13 +595,13 @@ static unsigned long ptrace_get_dr7(struct perf_event *bp[])
         return dr7;
 }
 
-static struct perf_event *
+static int
 ptrace_modify_breakpoint(struct perf_event *bp, int len, int type,
                          struct task_struct *tsk, int disabled)
 {
         int err;
         int gen_len, gen_type;
-        DEFINE_BREAKPOINT_ATTR(attr);
+        struct perf_event_attr attr;
 
         /*
          * We shoud have at least an inactive breakpoint at this
@@ -607,18 +609,18 @@ ptrace_modify_breakpoint(struct perf_event *bp, int len, int type,
          * written the address register first
          */
         if (!bp)
-                return ERR_PTR(-EINVAL);
+                return -EINVAL;
 
         err = arch_bp_generic_fields(len, type, &gen_len, &gen_type);
         if (err)
-                return ERR_PTR(err);
+                return err;
 
         attr = bp->attr;
         attr.bp_len = gen_len;
         attr.bp_type = gen_type;
         attr.disabled = disabled;
 
-        return modify_user_hw_breakpoint(bp, &attr, bp->callback, tsk);
+        return modify_user_hw_breakpoint(bp, &attr);
 }
 
 /*
@@ -656,28 +658,17 @@ restore:
                                 if (!second_pass)
                                         continue;
 
-                                thread->ptrace_bps[i] = NULL;
-                                bp = ptrace_modify_breakpoint(bp, len, type,
+                                rc = ptrace_modify_breakpoint(bp, len, type,
                                                               tsk, 1);
-                                if (IS_ERR(bp)) {
-                                        rc = PTR_ERR(bp);
-                                        thread->ptrace_bps[i] = NULL;
+                                if (rc)
                                         break;
-                                }
-                                thread->ptrace_bps[i] = bp;
                         }
                         continue;
                 }
 
-                bp = ptrace_modify_breakpoint(bp, len, type, tsk, 0);
-
-                /* Incorrect bp, or we have a bug in bp API */
-                if (IS_ERR(bp)) {
-                        rc = PTR_ERR(bp);
-                        thread->ptrace_bps[i] = NULL;
+                rc = ptrace_modify_breakpoint(bp, len, type, tsk, 0);
+                if (rc)
                         break;
-                }
-                thread->ptrace_bps[i] = bp;
         }
         /*
          * Make a second pass to free the remaining unused breakpoints
@@ -721,9 +712,10 @@ static int ptrace_set_breakpoint_addr(struct task_struct *tsk, int nr,
 {
         struct perf_event *bp;
         struct thread_struct *t = &tsk->thread;
-        DEFINE_BREAKPOINT_ATTR(attr);
+        struct perf_event_attr attr;
 
         if (!t->ptrace_bps[nr]) {
+                hw_breakpoint_init(&attr);
                 /*
                  * Put stub len and type to register (reserve) an inactive but
                  * correct bp
@@ -734,26 +726,32 @@ static int ptrace_set_breakpoint_addr(struct task_struct *tsk, int nr,
                 attr.disabled = 1;
 
                 bp = register_user_hw_breakpoint(&attr, ptrace_triggered, tsk);
+
+                /*
+                 * CHECKME: the previous code returned -EIO if the addr wasn't
+                 * a valid task virtual addr. The new one will return -EINVAL in
+                 *  this case.
+                 * -EINVAL may be what we want for in-kernel breakpoints users,
+                 * but -EIO looks better for ptrace, since we refuse a register
+                 * writing for the user. And anyway this is the previous
+                 * behaviour.
+                 */
+                if (IS_ERR(bp))
+                        return PTR_ERR(bp);
+
+                t->ptrace_bps[nr] = bp;
         } else {
+                int err;
+
                 bp = t->ptrace_bps[nr];
-                t->ptrace_bps[nr] = NULL;
 
                 attr = bp->attr;
                 attr.bp_addr = addr;
-                bp = modify_user_hw_breakpoint(bp, &attr, bp->callback, tsk);
+                err = modify_user_hw_breakpoint(bp, &attr);
+                if (err)
+                        return err;
         }
-        /*
-         * CHECKME: the previous code returned -EIO if the addr wasn't a
-         * valid task virtual addr. The new one will return -EINVAL in this
-         * case.
-         * -EINVAL may be what we want for in-kernel breakpoints users, but
-         * -EIO looks better for ptrace, since we refuse a register writing
-         * for the user. And anyway this is the previous behaviour.
-         */
-        if (IS_ERR(bp))
-                return PTR_ERR(bp);
 
-        t->ptrace_bps[nr] = bp;
 
         return 0;
 }
@@ -1460,14 +1458,14 @@ static int genregs32_get(struct task_struct *target,
 {
         if (kbuf) {
                 compat_ulong_t *k = kbuf;
-                while (count > 0) {
+                while (count >= sizeof(*k)) {
                         getreg32(target, pos, k++);
                         count -= sizeof(*k);
                         pos += sizeof(*k);
                 }
         } else {
                 compat_ulong_t __user *u = ubuf;
-                while (count > 0) {
+                while (count >= sizeof(*u)) {
                         compat_ulong_t word;
                         getreg32(target, pos, &word);
                         if (__put_user(word, u++))
@@ -1488,14 +1486,14 @@ static int genregs32_set(struct task_struct *target,
         int ret = 0;
         if (kbuf) {
                 const compat_ulong_t *k = kbuf;
-                while (count > 0 && !ret) {
+                while (count >= sizeof(*k) && !ret) {
                         ret = putreg32(target, pos, *k++);
                         count -= sizeof(*k);
                         pos += sizeof(*k);
                 }
         } else {
                 const compat_ulong_t __user *u = ubuf;
-                while (count > 0 && !ret) {
+                while (count >= sizeof(*u) && !ret) {
                         compat_ulong_t word;
                         ret = __get_user(word, u++);
                         if (ret)
@@ -1678,21 +1676,33 @@ const struct user_regset_view *task_user_regset_view(struct task_struct *task)
 #endif
 }
 
-void send_sigtrap(struct task_struct *tsk, struct pt_regs *regs,
-                                         int error_code, int si_code)
+static void fill_sigtrap_info(struct task_struct *tsk,
+                                struct pt_regs *regs,
+                                int error_code, int si_code,
+                                struct siginfo *info)
 {
-        struct siginfo info;
-
         tsk->thread.trap_no = 1;
         tsk->thread.error_code = error_code;
 
-        memset(&info, 0, sizeof(info));
-        info.si_signo = SIGTRAP;
-        info.si_code = si_code;
+        memset(info, 0, sizeof(*info));
+        info->si_signo = SIGTRAP;
+        info->si_code = si_code;
+        info->si_addr = user_mode_vm(regs) ? (void __user *)regs->ip : NULL;
+}
+
+void user_single_step_siginfo(struct task_struct *tsk,
+                                struct pt_regs *regs,
+                                struct siginfo *info)
+{
+        fill_sigtrap_info(tsk, regs, 0, TRAP_BRKPT, info);
+}
 
-        /* User-mode ip? */
-        info.si_addr = user_mode_vm(regs) ? (void __user *) regs->ip : NULL;
+void send_sigtrap(struct task_struct *tsk, struct pt_regs *regs,
+                                         int error_code, int si_code)
+{
+        struct siginfo info;
 
+        fill_sigtrap_info(tsk, regs, error_code, si_code, &info);
         /* Send us the fake SIGTRAP */
         force_sig_info(SIGTRAP, &info, tsk);
 }
@@ -1757,29 +1767,22 @@ asmregparm long syscall_trace_enter(struct pt_regs *regs)
 
 asmregparm void syscall_trace_leave(struct pt_regs *regs)
 {
+        bool step;
+
         if (unlikely(current->audit_context))
                 audit_syscall_exit(AUDITSC_RESULT(regs->ax), regs->ax);
 
         if (unlikely(test_thread_flag(TIF_SYSCALL_TRACEPOINT)))
                 trace_sys_exit(regs, regs->ax);
 
-        if (test_thread_flag(TIF_SYSCALL_TRACE))
-                tracehook_report_syscall_exit(regs, 0);
-
         /*
          * If TIF_SYSCALL_EMU is set, we only get here because of
          * TIF_SINGLESTEP (i.e. this is PTRACE_SYSEMU_SINGLESTEP).
          * We already reported this syscall instruction in
-         * syscall_trace_enter(), so don't do any more now.
-         */
-        if (unlikely(test_thread_flag(TIF_SYSCALL_EMU)))
-                return;
-
-        /*
-         * If we are single-stepping, synthesize a trap to follow the
-         * system call instruction.
+         * syscall_trace_enter().
          */
-        if (test_thread_flag(TIF_SINGLESTEP) &&
-            tracehook_consider_fatal_signal(current, SIGTRAP))
-                send_sigtrap(current, regs, 0, TRAP_BRKPT);
+        step = unlikely(test_thread_flag(TIF_SINGLESTEP)) &&
+                        !test_thread_flag(TIF_SYSCALL_EMU);
+        if (step || test_thread_flag(TIF_SYSCALL_TRACE))
+                tracehook_report_syscall_exit(regs, step);
 }
diff --git a/arch/x86/kernel/reboot_fixups_32.c b/arch/x86/kernel/reboot_fixups_32.c
index 201eab63b05f..fda313ebbb03 100644
--- a/arch/x86/kernel/reboot_fixups_32.c
+++ b/arch/x86/kernel/reboot_fixups_32.c
@@ -12,7 +12,7 @@
 #include <linux/interrupt.h>
 #include <asm/reboot_fixups.h>
 #include <asm/msr.h>
-#include <asm/geode.h>
+#include <linux/cs5535.h>
 
 static void cs5530a_warm_reset(struct pci_dev *dev)
 {
diff --git a/arch/x86/kernel/sys_i386_32.c b/arch/x86/kernel/sys_i386_32.c
index 1884a8d12bfa..dee1ff7cba58 100644
--- a/arch/x86/kernel/sys_i386_32.c
+++ b/arch/x86/kernel/sys_i386_32.c
@@ -24,31 +24,6 @@
 
 #include <asm/syscalls.h>
 
-asmlinkage long sys_mmap2(unsigned long addr, unsigned long len,
-                          unsigned long prot, unsigned long flags,
-                          unsigned long fd, unsigned long pgoff)
-{
-        int error = -EBADF;
-        struct file *file = NULL;
-        struct mm_struct *mm = current->mm;
-
-        flags &= ~(MAP_EXECUTABLE | MAP_DENYWRITE);
-        if (!(flags & MAP_ANONYMOUS)) {
-                file = fget(fd);
-                if (!file)
-                        goto out;
-        }
-
-        down_write(&mm->mmap_sem);
-        error = do_mmap_pgoff(file, addr, len, prot, flags, pgoff);
-        up_write(&mm->mmap_sem);
-
-        if (file)
-                fput(file);
-out:
-        return error;
-}
-
 /*
  * Perform the select(nd, in, out, ex, tv) and mmap() system
  * calls. Linux/i386 didn't use to be able to handle more than
@@ -77,7 +52,7 @@ asmlinkage int old_mmap(struct mmap_arg_struct __user *arg)
         if (a.offset & ~PAGE_MASK)
                 goto out;
 
-        err = sys_mmap2(a.addr, a.len, a.prot, a.flags,
+        err = sys_mmap_pgoff(a.addr, a.len, a.prot, a.flags,
                         a.fd, a.offset >> PAGE_SHIFT);
 out:
         return err;
diff --git a/arch/x86/kernel/sys_x86_64.c b/arch/x86/kernel/sys_x86_64.c
index 45e00eb09c3a..8aa2057efd12 100644
--- a/arch/x86/kernel/sys_x86_64.c
+++ b/arch/x86/kernel/sys_x86_64.c
@@ -23,26 +23,11 @@ SYSCALL_DEFINE6(mmap, unsigned long, addr, unsigned long, len,
                 unsigned long, fd, unsigned long, off)
 {
         long error;
-        struct file *file;
-
         error = -EINVAL;
         if (off & ~PAGE_MASK)
                 goto out;
 
-        error = -EBADF;
-        file = NULL;
-        flags &= ~(MAP_EXECUTABLE | MAP_DENYWRITE);
-        if (!(flags & MAP_ANONYMOUS)) {
-                file = fget(fd);
-                if (!file)
-                        goto out;
-        }
-        down_write(&current->mm->mmap_sem);
-        error = do_mmap_pgoff(file, addr, len, prot, flags, off >> PAGE_SHIFT);
-        up_write(&current->mm->mmap_sem);
-
-        if (file)
-                fput(file);
+        error = sys_mmap_pgoff(addr, len, prot, flags, fd, off >> PAGE_SHIFT);
 out:
         return error;
 }
diff --git a/arch/x86/kernel/syscall_table_32.S b/arch/x86/kernel/syscall_table_32.S
index 70c2125d55b9..15228b5d3eb7 100644
--- a/arch/x86/kernel/syscall_table_32.S
+++ b/arch/x86/kernel/syscall_table_32.S
@@ -191,7 +191,7 @@ ENTRY(sys_call_table)
         .long sys_ni_syscall    /* reserved for streams2 */
         .long ptregs_vfork      /* 190 */
         .long sys_getrlimit
-        .long sys_mmap2
+        .long sys_mmap_pgoff
         .long sys_truncate64
         .long sys_ftruncate64
         .long sys_stat64        /* 195 */
diff --git a/arch/x86/kernel/tsc_sync.c b/arch/x86/kernel/tsc_sync.c
index eed156851f5d..0aa5fed8b9e6 100644
--- a/arch/x86/kernel/tsc_sync.c
+++ b/arch/x86/kernel/tsc_sync.c
@@ -33,7 +33,7 @@ static __cpuinitdata atomic_t stop_count;
  * we want to have the fastest, inlined, non-debug version
  * of a critical section, to be able to prove TSC time-warps:
  */
-static __cpuinitdata raw_spinlock_t sync_lock = __RAW_SPIN_LOCK_UNLOCKED;
+static __cpuinitdata arch_spinlock_t sync_lock = __ARCH_SPIN_LOCK_UNLOCKED;
 
 static __cpuinitdata cycles_t last_tsc;
 static __cpuinitdata cycles_t max_warp;
@@ -62,13 +62,13 @@ static __cpuinit void check_tsc_warp(void)
                  * previous TSC that was measured (possibly on
                  * another CPU) and update the previous TSC timestamp.
                  */
-                __raw_spin_lock(&sync_lock);
+                arch_spin_lock(&sync_lock);
                 prev = last_tsc;
                 rdtsc_barrier();
                 now = get_cycles();
                 rdtsc_barrier();
                 last_tsc = now;
-                __raw_spin_unlock(&sync_lock);
+                arch_spin_unlock(&sync_lock);
 
                 /*
                  * Be nice every now and then (and also check whether
@@ -87,10 +87,10 @@ static __cpuinit void check_tsc_warp(void)
                  * we saw a time-warp of the TSC going backwards:
                  */
                 if (unlikely(prev > now)) {
-                        __raw_spin_lock(&sync_lock);
+                        arch_spin_lock(&sync_lock);
                         max_warp = max(max_warp, prev - now);
                         nr_warps++;
-                        __raw_spin_unlock(&sync_lock);
+                        arch_spin_unlock(&sync_lock);
                 }
         }
         WARN(!(now-start),
diff --git a/arch/x86/kernel/x8664_ksyms_64.c b/arch/x86/kernel/x8664_ksyms_64.c
index 9fafaf83b3b8..619f7f88b8cc 100644
--- a/arch/x86/kernel/x8664_ksyms_64.c
+++ b/arch/x86/kernel/x8664_ksyms_64.c
@@ -54,4 +54,6 @@ EXPORT_SYMBOL(__memcpy);
 
 EXPORT_SYMBOL(empty_zero_page);
 EXPORT_SYMBOL(init_level4_pgt);
-EXPORT_SYMBOL(load_gs_index);
+#ifndef CONFIG_PARAVIRT
+EXPORT_SYMBOL(native_load_gs_index);
+#endif
diff --git a/arch/x86/kvm/svm.c b/arch/x86/kvm/svm.c
index 3de0b37ec038..1d9b33843c80 100644
--- a/arch/x86/kvm/svm.c
+++ b/arch/x86/kvm/svm.c
@@ -316,7 +316,7 @@ static void svm_hardware_disable(void *garbage)
 static int svm_hardware_enable(void *garbage)
 {
 
-        struct svm_cpu_data *svm_data;
+        struct svm_cpu_data *sd;
         uint64_t efer;
         struct descriptor_table gdt_descr;
         struct desc_struct *gdt;
@@ -331,63 +331,61 @@ static int svm_hardware_enable(void *garbage)
                        me);
                 return -EINVAL;
         }
-        svm_data = per_cpu(svm_data, me);
+        sd = per_cpu(svm_data, me);
 
-        if (!svm_data) {
+        if (!sd) {
                 printk(KERN_ERR "svm_hardware_enable: svm_data is NULL on %d\n",
                        me);
                 return -EINVAL;
         }
 
-        svm_data->asid_generation = 1;
-        svm_data->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
-        svm_data->next_asid = svm_data->max_asid + 1;
+        sd->asid_generation = 1;
+        sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
+        sd->next_asid = sd->max_asid + 1;
 
         kvm_get_gdt(&gdt_descr);
         gdt = (struct desc_struct *)gdt_descr.base;
-        svm_data->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
+        sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
 
         wrmsrl(MSR_EFER, efer | EFER_SVME);
 
-        wrmsrl(MSR_VM_HSAVE_PA,
-               page_to_pfn(svm_data->save_area) << PAGE_SHIFT);
+        wrmsrl(MSR_VM_HSAVE_PA, page_to_pfn(sd->save_area) << PAGE_SHIFT);
 
         return 0;
 }
 
 static void svm_cpu_uninit(int cpu)
 {
-        struct svm_cpu_data *svm_data
-                = per_cpu(svm_data, raw_smp_processor_id());
+        struct svm_cpu_data *sd = per_cpu(svm_data, raw_smp_processor_id());
 
-        if (!svm_data)
+        if (!sd)
                 return;
 
         per_cpu(svm_data, raw_smp_processor_id()) = NULL;
-        __free_page(svm_data->save_area);
-        kfree(svm_data);
+        __free_page(sd->save_area);
+        kfree(sd);
 }
 
 static int svm_cpu_init(int cpu)
 {
-        struct svm_cpu_data *svm_data;
+        struct svm_cpu_data *sd;
         int r;
 
-        svm_data = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
-        if (!svm_data)
+        sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
+        if (!sd)
                 return -ENOMEM;
-        svm_data->cpu = cpu;
-        svm_data->save_area = alloc_page(GFP_KERNEL);
+        sd->cpu = cpu;
+        sd->save_area = alloc_page(GFP_KERNEL);
         r = -ENOMEM;
-        if (!svm_data->save_area)
+        if (!sd->save_area)
                 goto err_1;
 
-        per_cpu(svm_data, cpu) = svm_data;
+        per_cpu(svm_data, cpu) = sd;
 
         return 0;
 
 err_1:
-        kfree(svm_data);
+        kfree(sd);
         return r;
 
 }
@@ -1092,16 +1090,16 @@ static void save_host_msrs(struct kvm_vcpu *vcpu)
 #endif
 }
 
-static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *svm_data)
+static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd)
 {
-        if (svm_data->next_asid > svm_data->max_asid) {
-                ++svm_data->asid_generation;
-                svm_data->next_asid = 1;
+        if (sd->next_asid > sd->max_asid) {
+                ++sd->asid_generation;
+                sd->next_asid = 1;
                 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
         }
 
-        svm->asid_generation = svm_data->asid_generation;
-        svm->vmcb->control.asid = svm_data->next_asid++;
+        svm->asid_generation = sd->asid_generation;
+        svm->vmcb->control.asid = sd->next_asid++;
 }
 
 static unsigned long svm_get_dr(struct kvm_vcpu *vcpu, int dr)
@@ -2429,8 +2427,8 @@ static void reload_tss(struct kvm_vcpu *vcpu)
 {
         int cpu = raw_smp_processor_id();
 
-        struct svm_cpu_data *svm_data = per_cpu(svm_data, cpu);
-        svm_data->tss_desc->type = 9; /* available 32/64-bit TSS */
+        struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
+        sd->tss_desc->type = 9; /* available 32/64-bit TSS */
         load_TR_desc();
 }
 
@@ -2438,12 +2436,12 @@ static void pre_svm_run(struct vcpu_svm *svm)
 {
         int cpu = raw_smp_processor_id();
 
-        struct svm_cpu_data *svm_data = per_cpu(svm_data, cpu);
+        struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
 
         svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
         /* FIXME: handle wraparound of asid_generation */
-        if (svm->asid_generation != svm_data->asid_generation)
-                new_asid(svm, svm_data);
+        if (svm->asid_generation != sd->asid_generation)
+                new_asid(svm, sd);
 }
 
 static void svm_inject_nmi(struct kvm_vcpu *vcpu)
diff --git a/arch/x86/lib/Makefile b/arch/x86/lib/Makefile
index 706be8bf967b..cffd754f3039 100644
--- a/arch/x86/lib/Makefile
+++ b/arch/x86/lib/Makefile
@@ -5,7 +5,7 @@
 inat_tables_script = $(srctree)/arch/x86/tools/gen-insn-attr-x86.awk
 inat_tables_maps = $(srctree)/arch/x86/lib/x86-opcode-map.txt
 quiet_cmd_inat_tables = GEN     $@
-      cmd_inat_tables = $(AWK) -f $(inat_tables_script) $(inat_tables_maps) > $@
+      cmd_inat_tables = $(AWK) -f $(inat_tables_script) $(inat_tables_maps) > $@ || rm -f $@
 
 $(obj)/inat-tables.c: $(inat_tables_script) $(inat_tables_maps)
         $(call cmd,inat_tables)
@@ -20,7 +20,7 @@ lib-y := delay.o
 lib-y += thunk_$(BITS).o
 lib-y += usercopy_$(BITS).o getuser.o putuser.o
 lib-y += memcpy_$(BITS).o
-lib-y += insn.o inat.o
+lib-$(CONFIG_KPROBES) += insn.o inat.o
 
 obj-y += msr.o msr-reg.o msr-reg-export.o
 
diff --git a/arch/x86/mm/pat.c b/arch/x86/mm/pat.c
index 66b55d6e69ed..ae9648eb1c7f 100644
--- a/arch/x86/mm/pat.c
+++ b/arch/x86/mm/pat.c
@@ -704,9 +704,8 @@ int phys_mem_access_prot_allowed(struct file *file, unsigned long pfn,
         if (!range_is_allowed(pfn, size))
                 return 0;
 
-        if (file->f_flags & O_SYNC) {
+        if (file->f_flags & O_DSYNC)
                 flags = _PAGE_CACHE_UC_MINUS;
-        }
 
 #ifdef CONFIG_X86_32
         /*
diff --git a/arch/x86/pci/Makefile b/arch/x86/pci/Makefile
index d49202e740ea..564b008a51c7 100644
--- a/arch/x86/pci/Makefile
+++ b/arch/x86/pci/Makefile
@@ -15,3 +15,8 @@ obj-$(CONFIG_X86_NUMAQ)		+= numaq_32.o
 
 obj-y                           += common.o early.o
 obj-y                           += amd_bus.o
+obj-$(CONFIG_X86_64)            += bus_numa.o intel_bus.o
+
+ifeq ($(CONFIG_PCI_DEBUG),y)
+EXTRA_CFLAGS += -DDEBUG
+endif
diff --git a/arch/x86/pci/acpi.c b/arch/x86/pci/acpi.c
index 1014eb4bfc37..959e548a7039 100644
--- a/arch/x86/pci/acpi.c
+++ b/arch/x86/pci/acpi.c
@@ -7,6 +7,7 @@
 #include <asm/pci_x86.h>
 
 struct pci_root_info {
+        struct acpi_device *bridge;
         char *name;
         unsigned int res_num;
         struct resource *res;
@@ -58,6 +59,30 @@ bus_has_transparent_bridge(struct pci_bus *bus)
         return false;
 }
 
+static void
+align_resource(struct acpi_device *bridge, struct resource *res)
+{
+        int align = (res->flags & IORESOURCE_MEM) ? 16 : 4;
+
+        /*
+         * Host bridge windows are not BARs, but the decoders on the PCI side
+         * that claim this address space have starting alignment and length
+         * constraints, so fix any obvious BIOS goofs.
+         */
+        if (!IS_ALIGNED(res->start, align)) {
+                dev_printk(KERN_DEBUG, &bridge->dev,
+                           "host bridge window %pR invalid; "
+                           "aligning start to %d-byte boundary\n", res, align);
+                res->start &= ~(align - 1);
+        }
+        if (!IS_ALIGNED(res->end + 1, align)) {
+                dev_printk(KERN_DEBUG, &bridge->dev,
+                           "host bridge window %pR invalid; "
+                           "aligning end to %d-byte boundary\n", res, align);
+                res->end = ALIGN(res->end, align) - 1;
+        }
+}
+
 static acpi_status
 setup_resource(struct acpi_resource *acpi_res, void *data)
 {
@@ -91,11 +116,12 @@ setup_resource(struct acpi_resource *acpi_res, void *data)
         start = addr.minimum + addr.translation_offset;
         end = start + addr.address_length - 1;
         if (info->res_num >= max_root_bus_resources) {
-                printk(KERN_WARNING "PCI: Failed to allocate 0x%lx-0x%lx "
-                        "from %s for %s due to _CRS returning more than "
-                        "%d resource descriptors\n", (unsigned long) start,
-                        (unsigned long) end, root->name, info->name,
-                        max_root_bus_resources);
+                if (pci_probe & PCI_USE__CRS)
+                        printk(KERN_WARNING "PCI: Failed to allocate "
+                               "0x%lx-0x%lx from %s for %s due to _CRS "
+                               "returning more than %d resource descriptors\n",
+                               (unsigned long) start, (unsigned long) end,
+                               root->name, info->name, max_root_bus_resources);
                 return AE_OK;
         }
 
@@ -105,14 +131,28 @@ setup_resource(struct acpi_resource *acpi_res, void *data)
         res->start = start;
         res->end = end;
         res->child = NULL;
+        align_resource(info->bridge, res);
+
+        if (!(pci_probe & PCI_USE__CRS)) {
+                dev_printk(KERN_DEBUG, &info->bridge->dev,
+                           "host bridge window %pR (ignored)\n", res);
+                return AE_OK;
+        }
 
         if (insert_resource(root, res)) {
-                printk(KERN_ERR "PCI: Failed to allocate 0x%lx-0x%lx "
-                        "from %s for %s\n", (unsigned long) res->start,
-                        (unsigned long) res->end, root->name, info->name);
+                dev_err(&info->bridge->dev,
+                        "can't allocate host bridge window %pR\n", res);
         } else {
                 info->bus->resource[info->res_num] = res;
                 info->res_num++;
+                if (addr.translation_offset)
+                        dev_info(&info->bridge->dev, "host bridge window %pR "
+                                 "(PCI address [%#llx-%#llx])\n",
+                                 res, res->start - addr.translation_offset,
+                                 res->end - addr.translation_offset);
+                else
+                        dev_info(&info->bridge->dev,
+                                 "host bridge window %pR\n", res);
         }
         return AE_OK;
 }
@@ -124,6 +164,12 @@ get_current_resources(struct acpi_device *device, int busnum,
         struct pci_root_info info;
         size_t size;
 
+        if (!(pci_probe & PCI_USE__CRS))
+                dev_info(&device->dev,
+                         "ignoring host bridge windows from ACPI; "
+                         "boot with \"pci=use_crs\" to use them\n");
+
+        info.bridge = device;
         info.bus = bus;
         info.res_num = 0;
         acpi_walk_resources(device->handle, METHOD_NAME__CRS, count_resource,
@@ -163,8 +209,9 @@ struct pci_bus * __devinit pci_acpi_scan_root(struct acpi_device *device, int do
 #endif
 
         if (domain && !pci_domains_supported) {
-                printk(KERN_WARNING "PCI: Multiple domains not supported "
-                       "(dom %d, bus %d)\n", domain, busnum);
+                printk(KERN_WARNING "pci_bus %04x:%02x: "
+                       "ignored (multiple domains not supported)\n",
+                       domain, busnum);
                 return NULL;
         }
 
@@ -188,7 +235,8 @@ struct pci_bus * __devinit pci_acpi_scan_root(struct acpi_device *device, int do
          */
         sd = kzalloc(sizeof(*sd), GFP_KERNEL);
         if (!sd) {
-                printk(KERN_ERR "PCI: OOM, not probing PCI bus %02x\n", busnum);
+                printk(KERN_WARNING "pci_bus %04x:%02x: "
+                       "ignored (out of memory)\n", domain, busnum);
                 return NULL;
         }
 
@@ -209,9 +257,7 @@ struct pci_bus * __devinit pci_acpi_scan_root(struct acpi_device *device, int do
         } else {
                 bus = pci_create_bus(NULL, busnum, &pci_root_ops, sd);
                 if (bus) {
-                        if (pci_probe & PCI_USE__CRS)
-                                get_current_resources(device, busnum, domain,
-                                                        bus);
+                        get_current_resources(device, busnum, domain, bus);
                         bus->subordinate = pci_scan_child_bus(bus);
                 }
         }
diff --git a/arch/x86/pci/amd_bus.c b/arch/x86/pci/amd_bus.c
index 572ee9782f2a..95ecbd495955 100644
--- a/arch/x86/pci/amd_bus.c
+++ b/arch/x86/pci/amd_bus.c
@@ -6,10 +6,10 @@
 
 #ifdef CONFIG_X86_64
 #include <asm/pci-direct.h>
-#include <asm/mpspec.h>
-#include <linux/cpumask.h>
 #endif
 
+#include "bus_numa.h"
+
 /*
  * This discovers the pcibus <-> node mapping on AMD K8.
  * also get peer root bus resource for io,mmio
@@ -17,67 +17,6 @@
 
 #ifdef CONFIG_X86_64
 
-/*
- * sub bus (transparent) will use entres from 3 to store extra from root,
- * so need to make sure have enought slot there, increase PCI_BUS_NUM_RESOURCES?
- */
-#define RES_NUM 16
-struct pci_root_info {
-        char name[12];
-        unsigned int res_num;
-        struct resource res[RES_NUM];
-        int bus_min;
-        int bus_max;
-        int node;
-        int link;
-};
-
-/* 4 at this time, it may become to 32 */
-#define PCI_ROOT_NR 4
-static int pci_root_num;
-static struct pci_root_info pci_root_info[PCI_ROOT_NR];
-
-void x86_pci_root_bus_res_quirks(struct pci_bus *b)
-{
-        int i;
-        int j;
-        struct pci_root_info *info;
-
-        /* don't go for it if _CRS is used already */
-        if (b->resource[0] != &ioport_resource ||
-            b->resource[1] != &iomem_resource)
-                return;
-
-        /* if only one root bus, don't need to anything */
-        if (pci_root_num < 2)
-                return;
-
-        for (i = 0; i < pci_root_num; i++) {
-                if (pci_root_info[i].bus_min == b->number)
-                        break;
-        }
-
-        if (i == pci_root_num)
-                return;
-
-        printk(KERN_DEBUG "PCI: peer root bus %02x res updated from pci conf\n",
-                        b->number);
-
-        info = &pci_root_info[i];
-        for (j = 0; j < info->res_num; j++) {
-                struct resource *res;
-                struct resource *root;
-
-                res = &info->res[j];
-                b->resource[j] = res;
-                if (res->flags & IORESOURCE_IO)
-                        root = &ioport_resource;
-                else
-                        root = &iomem_resource;
-                insert_resource(root, res);
-        }
-}
-
 #define RANGE_NUM 16
 
 struct res_range {
@@ -130,52 +69,6 @@ static void __init update_range(struct res_range *range, size_t start,
         }
 }
 
-static void __init update_res(struct pci_root_info *info, size_t start,
-                              size_t end, unsigned long flags, int merge)
-{
-        int i;
-        struct resource *res;
-
-        if (!merge)
-                goto addit;
-
-        /* try to merge it with old one */
-        for (i = 0; i < info->res_num; i++) {
-                size_t final_start, final_end;
-                size_t common_start, common_end;
-
-                res = &info->res[i];
-                if (res->flags != flags)
-                        continue;
-
-                common_start = max((size_t)res->start, start);
-                common_end = min((size_t)res->end, end);
-                if (common_start > common_end + 1)
-                        continue;
-
-                final_start = min((size_t)res->start, start);
-                final_end = max((size_t)res->end, end);
-
-                res->start = final_start;
-                res->end = final_end;
-                return;
-        }
-
-addit:
-
-        /* need to add that */
-        if (info->res_num >= RES_NUM)
-                return;
-
-        res = &info->res[info->res_num];
-        res->name = info->name;
-        res->flags = flags;
-        res->start = start;
-        res->end = end;
-        res->child = NULL;
-        info->res_num++;
-}
-
 struct pci_hostbridge_probe {
         u32 bus;
         u32 slot;
@@ -230,7 +123,6 @@ static int __init early_fill_mp_bus_info(void)
         int j;
         unsigned bus;
         unsigned slot;
-        int found;
         int node;
         int link;
         int def_node;
@@ -247,7 +139,7 @@ static int __init early_fill_mp_bus_info(void)
         if (!early_pci_allowed())
                 return -1;
 
-        found = 0;
+        found_all_numa_early = 0;
         for (i = 0; i < ARRAY_SIZE(pci_probes); i++) {
                 u32 id;
                 u16 device;
@@ -261,12 +153,12 @@ static int __init early_fill_mp_bus_info(void)
                 device = (id>>16) & 0xffff;
                 if (pci_probes[i].vendor == vendor &&
                     pci_probes[i].device == device) {
-                        found = 1;
+                        found_all_numa_early = 1;
                         break;
                 }
         }
 
-        if (!found)
+        if (!found_all_numa_early)
                 return 0;
 
         pci_root_num = 0;
@@ -488,7 +380,7 @@ static int __init early_fill_mp_bus_info(void)
                 info = &pci_root_info[i];
                 res_num = info->res_num;
                 busnum = info->bus_min;
-                printk(KERN_DEBUG "bus: [%02x,%02x] on node %x link %x\n",
+                printk(KERN_DEBUG "bus: [%02x, %02x] on node %x link %x\n",
                        info->bus_min, info->bus_max, info->node, info->link);
                 for (j = 0; j < res_num; j++) {
                         res = &info->res[j];
diff --git a/arch/x86/pci/bus_numa.c b/arch/x86/pci/bus_numa.c
new file mode 100644
index 000000000000..145df00e0387
--- /dev/null
+++ b/arch/x86/pci/bus_numa.c
@@ -0,0 +1,101 @@
+#include <linux/init.h>
+#include <linux/pci.h>
+
+#include "bus_numa.h"
+
+int pci_root_num;
+struct pci_root_info pci_root_info[PCI_ROOT_NR];
+int found_all_numa_early;
+
+void x86_pci_root_bus_res_quirks(struct pci_bus *b)
+{
+        int i;
+        int j;
+        struct pci_root_info *info;
+
+        /* don't go for it if _CRS is used already */
+        if (b->resource[0] != &ioport_resource ||
+            b->resource[1] != &iomem_resource)
+                return;
+
+        if (!pci_root_num)
+                return;
+
+        /* for amd, if only one root bus, don't need to do anything */
+        if (pci_root_num < 2 && found_all_numa_early)
+                return;
+
+        for (i = 0; i < pci_root_num; i++) {
+                if (pci_root_info[i].bus_min == b->number)
+                        break;
+        }
+
+        if (i == pci_root_num)
+                return;
+
+        printk(KERN_DEBUG "PCI: peer root bus %02x res updated from pci conf\n",
+                        b->number);
+
+        info = &pci_root_info[i];
+        for (j = 0; j < info->res_num; j++) {
+                struct resource *res;
+                struct resource *root;
+
+                res = &info->res[j];
+                b->resource[j] = res;
+                if (res->flags & IORESOURCE_IO)
+                        root = &ioport_resource;
+                else
+                        root = &iomem_resource;
+                insert_resource(root, res);
+        }
+}
+
+void __init update_res(struct pci_root_info *info, size_t start,
+                              size_t end, unsigned long flags, int merge)
+{
+        int i;
+        struct resource *res;
+
+        if (start > end)
+                return;
+
+        if (!merge)
+                goto addit;
+
+        /* try to merge it with old one */
+        for (i = 0; i < info->res_num; i++) {
+                size_t final_start, final_end;
+                size_t common_start, common_end;
+
+                res = &info->res[i];
+                if (res->flags != flags)
+                        continue;
+
+                common_start = max((size_t)res->start, start);
+                common_end = min((size_t)res->end, end);
+                if (common_start > common_end + 1)
+                        continue;
+
+                final_start = min((size_t)res->start, start);
+                final_end = max((size_t)res->end, end);
+
+                res->start = final_start;
+                res->end = final_end;
+                return;
+        }
+
+addit:
+
+        /* need to add that */
+        if (info->res_num >= RES_NUM)
+                return;
+
+        res = &info->res[info->res_num];
+        res->name = info->name;
+        res->flags = flags;
+        res->start = start;
+        res->end = end;
+        res->child = NULL;
+        info->res_num++;
+}
diff --git a/arch/x86/pci/bus_numa.h b/arch/x86/pci/bus_numa.h
new file mode 100644
index 000000000000..adbc23fe82ac
--- /dev/null
+++ b/arch/x86/pci/bus_numa.h
@@ -0,0 +1,27 @@
+#ifdef CONFIG_X86_64
+
+/*
+ * sub bus (transparent) will use entres from 3 to store extra from
+ * root, so need to make sure we have enough slot there, Should we
+ * increase PCI_BUS_NUM_RESOURCES?
+ */
+#define RES_NUM 16
+struct pci_root_info {
+        char name[12];
+        unsigned int res_num;
+        struct resource res[RES_NUM];
+        int bus_min;
+        int bus_max;
+        int node;
+        int link;
+};
+
+/* 4 at this time, it may become to 32 */
+#define PCI_ROOT_NR 4
+extern int pci_root_num;
+extern struct pci_root_info pci_root_info[PCI_ROOT_NR];
+extern int found_all_numa_early;
+
+extern void update_res(struct pci_root_info *info, size_t start,
+                              size_t end, unsigned long flags, int merge);
+#endif
diff --git a/arch/x86/pci/common.c b/arch/x86/pci/common.c
index 1331fcf26143..d2552c68e94d 100644
--- a/arch/x86/pci/common.c
+++ b/arch/x86/pci/common.c
@@ -410,8 +410,6 @@ struct pci_bus * __devinit pcibios_scan_root(int busnum)
         return bus;
 }
 
-extern u8 pci_cache_line_size;
-
 int __init pcibios_init(void)
 {
         struct cpuinfo_x86 *c = &boot_cpu_data;
@@ -422,15 +420,19 @@ int __init pcibios_init(void)
         }
 
         /*
-         * Assume PCI cacheline size of 32 bytes for all x86s except K7/K8
-         * and P4. It's also good for 386/486s (which actually have 16)
+         * Set PCI cacheline size to that of the CPU if the CPU has reported it.
+         * (For older CPUs that don't support cpuid, we se it to 32 bytes
+         * It's also good for 386/486s (which actually have 16)
          * as quite a few PCI devices do not support smaller values.
          */
-        pci_cache_line_size = 32 >> 2;
-        if (c->x86 >= 6 && c->x86_vendor == X86_VENDOR_AMD)
-                pci_cache_line_size = 64 >> 2;  /* K7 & K8 */
-        else if (c->x86 > 6 && c->x86_vendor == X86_VENDOR_INTEL)
-                pci_cache_line_size = 128 >> 2; /* P4 */
+        if (c->x86_clflush_size > 0) {
+                pci_dfl_cache_line_size = c->x86_clflush_size >> 2;
+                printk(KERN_DEBUG "PCI: pci_cache_line_size set to %d bytes\n",
+                        pci_dfl_cache_line_size << 2);
+        } else {
+                pci_dfl_cache_line_size = 32 >> 2;
+                printk(KERN_DEBUG "PCI: Unknown cacheline size. Setting to 32 bytes\n");
+        }
 
         pcibios_resource_survey();
 
diff --git a/arch/x86/pci/early.c b/arch/x86/pci/early.c
index aaf26ae58cd5..d1067d539bee 100644
--- a/arch/x86/pci/early.c
+++ b/arch/x86/pci/early.c
@@ -12,8 +12,6 @@ u32 read_pci_config(u8 bus, u8 slot, u8 func, u8 offset)
         u32 v;
         outl(0x80000000 | (bus<<16) | (slot<<11) | (func<<8) | offset, 0xcf8);
         v = inl(0xcfc);
-        if (v != 0xffffffff)
-                pr_debug("%x reading 4 from %x: %x\n", slot, offset, v);
         return v;
 }
 
@@ -22,7 +20,6 @@ u8 read_pci_config_byte(u8 bus, u8 slot, u8 func, u8 offset)
         u8 v;
         outl(0x80000000 | (bus<<16) | (slot<<11) | (func<<8) | offset, 0xcf8);
         v = inb(0xcfc + (offset&3));
-        pr_debug("%x reading 1 from %x: %x\n", slot, offset, v);
         return v;
 }
 
@@ -31,28 +28,24 @@ u16 read_pci_config_16(u8 bus, u8 slot, u8 func, u8 offset)
         u16 v;
         outl(0x80000000 | (bus<<16) | (slot<<11) | (func<<8) | offset, 0xcf8);
         v = inw(0xcfc + (offset&2));
-        pr_debug("%x reading 2 from %x: %x\n", slot, offset, v);
         return v;
 }
 
 void write_pci_config(u8 bus, u8 slot, u8 func, u8 offset,
                                     u32 val)
 {
-        pr_debug("%x writing to %x: %x\n", slot, offset, val);
         outl(0x80000000 | (bus<<16) | (slot<<11) | (func<<8) | offset, 0xcf8);
         outl(val, 0xcfc);
 }
 
 void write_pci_config_byte(u8 bus, u8 slot, u8 func, u8 offset, u8 val)
 {
-        pr_debug("%x writing to %x: %x\n", slot, offset, val);
         outl(0x80000000 | (bus<<16) | (slot<<11) | (func<<8) | offset, 0xcf8);
         outb(val, 0xcfc + (offset&3));
 }
 
 void write_pci_config_16(u8 bus, u8 slot, u8 func, u8 offset, u16 val)
 {
-        pr_debug("%x writing to %x: %x\n", slot, offset, val);
         outl(0x80000000 | (bus<<16) | (slot<<11) | (func<<8) | offset, 0xcf8);
         outw(val, 0xcfc + (offset&2));
 }
diff --git a/arch/x86/pci/i386.c b/arch/x86/pci/i386.c
index b22d13b0c71d..5dc9e8c63fcd 100644
--- a/arch/x86/pci/i386.c
+++ b/arch/x86/pci/i386.c
@@ -129,7 +129,9 @@ static void __init pcibios_allocate_bus_resources(struct list_head *bus_list)
                                         continue;
                                 if (!r->start ||
                                     pci_claim_resource(dev, idx) < 0) {
-                                        dev_info(&dev->dev, "BAR %d: can't allocate resource\n", idx);
+                                        dev_info(&dev->dev,
+                                                 "can't reserve window %pR\n",
+                                                 r);
                                         /*
                                          * Something is wrong with the region.
                                          * Invalidate the resource to prevent
@@ -144,16 +146,29 @@ static void __init pcibios_allocate_bus_resources(struct list_head *bus_list)
         }
 }
 
+struct pci_check_idx_range {
+        int start;
+        int end;
+};
+
 static void __init pcibios_allocate_resources(int pass)
 {
         struct pci_dev *dev = NULL;
-        int idx, disabled;
+        int idx, disabled, i;
         u16 command;
         struct resource *r;
 
+        struct pci_check_idx_range idx_range[] = {
+                { PCI_STD_RESOURCES, PCI_STD_RESOURCE_END },
+#ifdef CONFIG_PCI_IOV
+                { PCI_IOV_RESOURCES, PCI_IOV_RESOURCE_END },
+#endif
+        };
+
         for_each_pci_dev(dev) {
                 pci_read_config_word(dev, PCI_COMMAND, &command);
-                for (idx = 0; idx < PCI_ROM_RESOURCE; idx++) {
+                for (i = 0; i < ARRAY_SIZE(idx_range); i++)
+                for (idx = idx_range[i].start; idx <= idx_range[i].end; idx++) {
                         r = &dev->resource[idx];
                         if (r->parent)          /* Already allocated */
                                 continue;
@@ -164,12 +179,12 @@ static void __init pcibios_allocate_resources(int pass)
                         else
                                 disabled = !(command & PCI_COMMAND_MEMORY);
                         if (pass == disabled) {
-                                dev_dbg(&dev->dev, "resource %#08llx-%#08llx (f=%lx, d=%d, p=%d)\n",
-                                        (unsigned long long) r->start,
-                                        (unsigned long long) r->end,
-                                        r->flags, disabled, pass);
+                                dev_dbg(&dev->dev,
+                                        "BAR %d: reserving %pr (d=%d, p=%d)\n",
+                                        idx, r, disabled, pass);
                                 if (pci_claim_resource(dev, idx) < 0) {
-                                        dev_info(&dev->dev, "BAR %d: can't allocate resource\n", idx);
+                                        dev_info(&dev->dev,
+                                                 "can't reserve %pR\n", r);
                                         /* We'll assign a new address later */
                                         r->end -= r->start;
                                         r->start = 0;
@@ -182,7 +197,7 @@ static void __init pcibios_allocate_resources(int pass)
                                 /* Turn the ROM off, leave the resource region,
                                  * but keep it unregistered. */
                                 u32 reg;
-                                dev_dbg(&dev->dev, "disabling ROM\n");
+                                dev_dbg(&dev->dev, "disabling ROM %pR\n", r);
                                 r->flags &= ~IORESOURCE_ROM_ENABLE;
                                 pci_read_config_dword(dev,
                                                 dev->rom_base_reg, &reg);
@@ -282,6 +297,15 @@ int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
                 return -EINVAL;
 
         prot = pgprot_val(vma->vm_page_prot);
+
+        /*
+         * Return error if pat is not enabled and write_combine is requested.
+         * Caller can followup with UC MINUS request and add a WC mtrr if there
+         * is a free mtrr slot.
+         */
+        if (!pat_enabled && write_combine)
+                return -EINVAL;
+
         if (pat_enabled && write_combine)
                 prot |= _PAGE_CACHE_WC;
         else if (pat_enabled || boot_cpu_data.x86 > 3)
diff --git a/arch/x86/pci/intel_bus.c b/arch/x86/pci/intel_bus.c
new file mode 100644
index 000000000000..b7a55dc55d13
--- /dev/null
+++ b/arch/x86/pci/intel_bus.c
@@ -0,0 +1,90 @@
+/*
+ * to read io range from IOH pci conf, need to do it after mmconfig is there
+ */
+
+#include <linux/delay.h>
+#include <linux/dmi.h>
+#include <linux/pci.h>
+#include <linux/init.h>
+#include <asm/pci_x86.h>
+
+#include "bus_numa.h"
+
+static inline void print_ioh_resources(struct pci_root_info *info)
+{
+        int res_num;
+        int busnum;
+        int i;
+
+        printk(KERN_DEBUG "IOH bus: [%02x, %02x]\n",
+                        info->bus_min, info->bus_max);
+        res_num = info->res_num;
+        busnum = info->bus_min;
+        for (i = 0; i < res_num; i++) {
+                struct resource *res;
+
+                res = &info->res[i];
+                printk(KERN_DEBUG "IOH bus: %02x index %x %s: [%llx, %llx]\n",
+                        busnum, i,
+                        (res->flags & IORESOURCE_IO) ? "io port" :
+                                                        "mmio",
+                        res->start, res->end);
+        }
+}
+
+#define IOH_LIO                 0x108
+#define IOH_LMMIOL              0x10c
+#define IOH_LMMIOH              0x110
+#define IOH_LMMIOH_BASEU        0x114
+#define IOH_LMMIOH_LIMITU       0x118
+#define IOH_LCFGBUS             0x11c
+
+static void __devinit pci_root_bus_res(struct pci_dev *dev)
+{
+        u16 word;
+        u32 dword;
+        struct pci_root_info *info;
+        u16 io_base, io_end;
+        u32 mmiol_base, mmiol_end;
+        u64 mmioh_base, mmioh_end;
+        int bus_base, bus_end;
+
+        if (pci_root_num >= PCI_ROOT_NR) {
+                printk(KERN_DEBUG "intel_bus.c: PCI_ROOT_NR is too small\n");
+                return;
+        }
+
+        info = &pci_root_info[pci_root_num];
+        pci_root_num++;
+
+        pci_read_config_word(dev, IOH_LCFGBUS, &word);
+        bus_base = (word & 0xff);
+        bus_end = (word & 0xff00) >> 8;
+        sprintf(info->name, "PCI Bus #%02x", bus_base);
+        info->bus_min = bus_base;
+        info->bus_max = bus_end;
+
+        pci_read_config_word(dev, IOH_LIO, &word);
+        io_base = (word & 0xf0) << (12 - 4);
+        io_end = (word & 0xf000) | 0xfff;
+        update_res(info, io_base, io_end, IORESOURCE_IO, 0);
+
+        pci_read_config_dword(dev, IOH_LMMIOL, &dword);
+        mmiol_base = (dword & 0xff00) << (24 - 8);
+        mmiol_end = (dword & 0xff000000) | 0xffffff;
+        update_res(info, mmiol_base, mmiol_end, IORESOURCE_MEM, 0);
+
+        pci_read_config_dword(dev, IOH_LMMIOH, &dword);
+        mmioh_base = ((u64)(dword & 0xfc00)) << (26 - 10);
+        mmioh_end = ((u64)(dword & 0xfc000000) | 0x3ffffff);
+        pci_read_config_dword(dev, IOH_LMMIOH_BASEU, &dword);
+        mmioh_base |= ((u64)(dword & 0x7ffff)) << 32;
+        pci_read_config_dword(dev, IOH_LMMIOH_LIMITU, &dword);
+        mmioh_end |= ((u64)(dword & 0x7ffff)) << 32;
+        update_res(info, mmioh_base, mmioh_end, IORESOURCE_MEM, 0);
+
+        print_ioh_resources(info);
+}
+
+/* intel IOH */
+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x342e, pci_root_bus_res);
diff --git a/arch/x86/pci/mmconfig-shared.c b/arch/x86/pci/mmconfig-shared.c
index 602c172d3bd5..b19d1e54201e 100644
--- a/arch/x86/pci/mmconfig-shared.c
+++ b/arch/x86/pci/mmconfig-shared.c
@@ -15,48 +15,98 @@
 #include <linux/acpi.h>
 #include <linux/sfi_acpi.h>
 #include <linux/bitmap.h>
-#include <linux/sort.h>
+#include <linux/dmi.h>
 #include <asm/e820.h>
 #include <asm/pci_x86.h>
 #include <asm/acpi.h>
 
 #define PREFIX "PCI: "
 
-/* aperture is up to 256MB but BIOS may reserve less */
-#define MMCONFIG_APER_MIN       (2 * 1024*1024)
-#define MMCONFIG_APER_MAX       (256 * 1024*1024)
-
 /* Indicate if the mmcfg resources have been placed into the resource table. */
 static int __initdata pci_mmcfg_resources_inserted;
 
-static __init int extend_mmcfg(int num)
+LIST_HEAD(pci_mmcfg_list);
+
+static __init void pci_mmconfig_remove(struct pci_mmcfg_region *cfg)
 {
-        struct acpi_mcfg_allocation *new;
-        int new_num = pci_mmcfg_config_num + num;
+        if (cfg->res.parent)
+                release_resource(&cfg->res);
+        list_del(&cfg->list);
+        kfree(cfg);
+}
 
-        new = kzalloc(sizeof(pci_mmcfg_config[0]) * new_num, GFP_KERNEL);
-        if (!new)
-                return -1;
+static __init void free_all_mmcfg(void)
+{
+        struct pci_mmcfg_region *cfg, *tmp;
 
-        if (pci_mmcfg_config) {
-                memcpy(new, pci_mmcfg_config,
-                         sizeof(pci_mmcfg_config[0]) * new_num);
-                kfree(pci_mmcfg_config);
+        pci_mmcfg_arch_free();
+        list_for_each_entry_safe(cfg, tmp, &pci_mmcfg_list, list)
+                pci_mmconfig_remove(cfg);
+}
+
+static __init void list_add_sorted(struct pci_mmcfg_region *new)
+{
+        struct pci_mmcfg_region *cfg;
+
+        /* keep list sorted by segment and starting bus number */
+        list_for_each_entry(cfg, &pci_mmcfg_list, list) {
+                if (cfg->segment > new->segment ||
+                    (cfg->segment == new->segment &&
+                     cfg->start_bus >= new->start_bus)) {
+                        list_add_tail(&new->list, &cfg->list);
+                        return;
+                }
         }
-        pci_mmcfg_config = new;
+        list_add_tail(&new->list, &pci_mmcfg_list);
+}
 
-        return 0;
+static __init struct pci_mmcfg_region *pci_mmconfig_add(int segment, int start,
+                                                        int end, u64 addr)
+{
+        struct pci_mmcfg_region *new;
+        int num_buses;
+        struct resource *res;
+
+        if (addr == 0)
+                return NULL;
+
+        new = kzalloc(sizeof(*new), GFP_KERNEL);
+        if (!new)
+                return NULL;
+
+        new->address = addr;
+        new->segment = segment;
+        new->start_bus = start;
+        new->end_bus = end;
+
+        list_add_sorted(new);
+
+        num_buses = end - start + 1;
+        res = &new->res;
+        res->start = addr + PCI_MMCFG_BUS_OFFSET(start);
+        res->end = addr + PCI_MMCFG_BUS_OFFSET(num_buses) - 1;
+        res->flags = IORESOURCE_MEM | IORESOURCE_BUSY;
+        snprintf(new->name, PCI_MMCFG_RESOURCE_NAME_LEN,
+                 "PCI MMCONFIG %04x [bus %02x-%02x]", segment, start, end);
+        res->name = new->name;
+
+        printk(KERN_INFO PREFIX "MMCONFIG for domain %04x [bus %02x-%02x] at "
+               "%pR (base %#lx)\n", segment, start, end, &new->res,
+               (unsigned long) addr);
+
+        return new;
 }
 
-static __init void fill_one_mmcfg(u64 addr, int segment, int start, int end)
+struct pci_mmcfg_region *pci_mmconfig_lookup(int segment, int bus)
 {
-        int i = pci_mmcfg_config_num;
+        struct pci_mmcfg_region *cfg;
 
-        pci_mmcfg_config_num++;
-        pci_mmcfg_config[i].address = addr;
-        pci_mmcfg_config[i].pci_segment = segment;
-        pci_mmcfg_config[i].start_bus_number = start;
-        pci_mmcfg_config[i].end_bus_number = end;
+        list_for_each_entry(cfg, &pci_mmcfg_list, list)
+                if (cfg->segment == segment &&
+                    cfg->start_bus <= bus && bus <= cfg->end_bus)
+                        return cfg;
+
+        return NULL;
 }
 
 static const char __init *pci_mmcfg_e7520(void)
@@ -68,11 +118,9 @@ static const char __init *pci_mmcfg_e7520(void)
         if (win == 0x0000 || win == 0xf000)
                 return NULL;
 
-        if (extend_mmcfg(1) == -1)
+        if (pci_mmconfig_add(0, 0, 255, win << 16) == NULL)
                 return NULL;
 
-        fill_one_mmcfg(win << 16, 0, 0, 255);
-
         return "Intel Corporation E7520 Memory Controller Hub";
 }
 
@@ -114,11 +162,9 @@ static const char __init *pci_mmcfg_intel_945(void)
         if ((pciexbar & mask) >= 0xf0000000U)
                 return NULL;
 
-        if (extend_mmcfg(1) == -1)
+        if (pci_mmconfig_add(0, 0, (len >> 20) - 1, pciexbar & mask) == NULL)
                 return NULL;
 
-        fill_one_mmcfg(pciexbar & mask, 0, 0, (len >> 20) - 1);
-
         return "Intel Corporation 945G/GZ/P/PL Express Memory Controller Hub";
 }
 
@@ -127,7 +173,7 @@ static const char __init *pci_mmcfg_amd_fam10h(void)
         u32 low, high, address;
         u64 base, msr;
         int i;
-        unsigned segnbits = 0, busnbits;
+        unsigned segnbits = 0, busnbits, end_bus;
 
         if (!(pci_probe & PCI_CHECK_ENABLE_AMD_MMCONF))
                 return NULL;
@@ -161,11 +207,13 @@ static const char __init *pci_mmcfg_amd_fam10h(void)
                 busnbits = 8;
         }
 
-        if (extend_mmcfg(1 << segnbits) == -1)
-                return NULL;
-
+        end_bus = (1 << busnbits) - 1;
         for (i = 0; i < (1 << segnbits); i++)
-                fill_one_mmcfg(base + (1<<28) * i, i, 0, (1 << busnbits) - 1);
+                if (pci_mmconfig_add(i, 0, end_bus,
+                                     base + (1<<28) * i) == NULL) {
+                        free_all_mmcfg();
+                        return NULL;
+                }
 
         return "AMD Family 10h NB";
 }
@@ -190,7 +238,7 @@ static const char __init *pci_mmcfg_nvidia_mcp55(void)
         /*
          * do check if amd fam10h already took over
          */
-        if (!acpi_disabled || pci_mmcfg_config_num || mcp55_checked)
+        if (!acpi_disabled || !list_empty(&pci_mmcfg_list) || mcp55_checked)
                 return NULL;
 
         mcp55_checked = true;
@@ -213,16 +261,14 @@ static const char __init *pci_mmcfg_nvidia_mcp55(void)
                 if (!(extcfg & extcfg_enable_mask))
                         continue;
 
-                if (extend_mmcfg(1) == -1)
-                        continue;
-
                 size_index = (extcfg & extcfg_size_mask) >> extcfg_size_shift;
                 base = extcfg & extcfg_base_mask[size_index];
                 /* base could > 4G */
                 base <<= extcfg_base_lshift;
                 start = (extcfg & extcfg_start_mask) >> extcfg_start_shift;
                 end = start + extcfg_sizebus[size_index] - 1;
-                fill_one_mmcfg(base, 0, start, end);
+                if (pci_mmconfig_add(0, start, end, base) == NULL)
+                        continue;
                 mcp55_mmconf_found++;
         }
 
@@ -253,45 +299,27 @@ static struct pci_mmcfg_hostbridge_probe pci_mmcfg_probes[] __initdata = {
           0x0369, pci_mmcfg_nvidia_mcp55 },
 };
 
-static int __init cmp_mmcfg(const void *x1, const void *x2)
-{
-        const typeof(pci_mmcfg_config[0]) *m1 = x1;
-        const typeof(pci_mmcfg_config[0]) *m2 = x2;
-        int start1, start2;
-
-        start1 = m1->start_bus_number;
-        start2 = m2->start_bus_number;
-
-        return start1 - start2;
-}
-
 static void __init pci_mmcfg_check_end_bus_number(void)
 {
-        int i;
-        typeof(pci_mmcfg_config[0]) *cfg, *cfgx;
-
-        /* sort them at first */
-        sort(pci_mmcfg_config, pci_mmcfg_config_num,
-                 sizeof(pci_mmcfg_config[0]), cmp_mmcfg, NULL);
+        struct pci_mmcfg_region *cfg, *cfgx;
 
         /* last one*/
-        if (pci_mmcfg_config_num > 0) {
-                i = pci_mmcfg_config_num - 1;
-                cfg = &pci_mmcfg_config[i];
-                if (cfg->end_bus_number < cfg->start_bus_number)
-                        cfg->end_bus_number = 255;
-        }
+        cfg = list_entry(pci_mmcfg_list.prev, typeof(*cfg), list);
+        if (cfg)
+                if (cfg->end_bus < cfg->start_bus)
+                        cfg->end_bus = 255;
 
-        /* don't overlap please */
-        for (i = 0; i < pci_mmcfg_config_num - 1; i++) {
-                cfg = &pci_mmcfg_config[i];
-                cfgx = &pci_mmcfg_config[i+1];
+        if (list_is_singular(&pci_mmcfg_list))
+                return;
 
-                if (cfg->end_bus_number < cfg->start_bus_number)
-                        cfg->end_bus_number = 255;
+        /* don't overlap please */
+        list_for_each_entry(cfg, &pci_mmcfg_list, list) {
+                if (cfg->end_bus < cfg->start_bus)
+                        cfg->end_bus = 255;
 
-                if (cfg->end_bus_number >= cfgx->start_bus_number)
-                        cfg->end_bus_number = cfgx->start_bus_number - 1;
+                cfgx = list_entry(cfg->list.next, typeof(*cfg), list);
+                if (cfg != cfgx && cfg->end_bus >= cfgx->start_bus)
+                        cfg->end_bus = cfgx->start_bus - 1;
         }
 }
 
@@ -306,8 +334,7 @@ static int __init pci_mmcfg_check_hostbridge(void)
         if (!raw_pci_ops)
                 return 0;
 
-        pci_mmcfg_config_num = 0;
-        pci_mmcfg_config = NULL;
+        free_all_mmcfg();
 
         for (i = 0; i < ARRAY_SIZE(pci_mmcfg_probes); i++) {
                 bus =  pci_mmcfg_probes[i].bus;
@@ -322,45 +349,22 @@ static int __init pci_mmcfg_check_hostbridge(void)
                         name = pci_mmcfg_probes[i].probe();
 
                 if (name)
-                        printk(KERN_INFO "PCI: Found %s with MMCONFIG support.\n",
+                        printk(KERN_INFO PREFIX "%s with MMCONFIG support\n",
                                name);
         }
 
         /* some end_bus_number is crazy, fix it */
         pci_mmcfg_check_end_bus_number();
 
-        return pci_mmcfg_config_num != 0;
+        return !list_empty(&pci_mmcfg_list);
 }
 
 static void __init pci_mmcfg_insert_resources(void)
 {
-#define PCI_MMCFG_RESOURCE_NAME_LEN 24
-        int i;
-        struct resource *res;
-        char *names;
-        unsigned num_buses;
-
-        res = kcalloc(PCI_MMCFG_RESOURCE_NAME_LEN + sizeof(*res),
-                        pci_mmcfg_config_num, GFP_KERNEL);
-        if (!res) {
-                printk(KERN_ERR "PCI: Unable to allocate MMCONFIG resources\n");
-                return;
-        }
+        struct pci_mmcfg_region *cfg;
 
-        names = (void *)&res[pci_mmcfg_config_num];
-        for (i = 0; i < pci_mmcfg_config_num; i++, res++) {
-                struct acpi_mcfg_allocation *cfg = &pci_mmcfg_config[i];
-                num_buses = cfg->end_bus_number - cfg->start_bus_number + 1;
-                res->name = names;
-                snprintf(names, PCI_MMCFG_RESOURCE_NAME_LEN,
-                         "PCI MMCONFIG %u [%02x-%02x]", cfg->pci_segment,
-                         cfg->start_bus_number, cfg->end_bus_number);
-                res->start = cfg->address + (cfg->start_bus_number << 20);
-                res->end = res->start + (num_buses << 20) - 1;
-                res->flags = IORESOURCE_MEM | IORESOURCE_BUSY;
-                insert_resource(&iomem_resource, res);
-                names += PCI_MMCFG_RESOURCE_NAME_LEN;
-        }
+        list_for_each_entry(cfg, &pci_mmcfg_list, list)
+                insert_resource(&iomem_resource, &cfg->res);
 
         /* Mark that the resources have been inserted. */
         pci_mmcfg_resources_inserted = 1;
@@ -437,11 +441,12 @@ static int __init is_acpi_reserved(u64 start, u64 end, unsigned not_used)
 typedef int (*check_reserved_t)(u64 start, u64 end, unsigned type);
 
 static int __init is_mmconf_reserved(check_reserved_t is_reserved,
-                u64 addr, u64 size, int i,
-                typeof(pci_mmcfg_config[0]) *cfg, int with_e820)
+                                    struct pci_mmcfg_region *cfg, int with_e820)
 {
+        u64 addr = cfg->res.start;
+        u64 size = resource_size(&cfg->res);
         u64 old_size = size;
-        int valid = 0;
+        int valid = 0, num_buses;
 
         while (!is_reserved(addr, addr + size, E820_RESERVED)) {
                 size >>= 1;
@@ -450,19 +455,25 @@ static int __init is_mmconf_reserved(check_reserved_t is_reserved,
         }
 
         if (size >= (16UL<<20) || size == old_size) {
-                printk(KERN_NOTICE
-                       "PCI: MCFG area at %Lx reserved in %s\n",
-                        addr, with_e820?"E820":"ACPI motherboard resources");
+                printk(KERN_INFO PREFIX "MMCONFIG at %pR reserved in %s\n",
+                       &cfg->res,
+                       with_e820 ? "E820" : "ACPI motherboard resources");
                 valid = 1;
 
                 if (old_size != size) {
-                        /* update end_bus_number */
-                        cfg->end_bus_number = cfg->start_bus_number + ((size>>20) - 1);
-                        printk(KERN_NOTICE "PCI: updated MCFG configuration %d: base %lx "
-                               "segment %hu buses %u - %u\n",
-                               i, (unsigned long)cfg->address, cfg->pci_segment,
-                               (unsigned int)cfg->start_bus_number,
-                               (unsigned int)cfg->end_bus_number);
+                        /* update end_bus */
+                        cfg->end_bus = cfg->start_bus + ((size>>20) - 1);
+                        num_buses = cfg->end_bus - cfg->start_bus + 1;
+                        cfg->res.end = cfg->res.start +
+                            PCI_MMCFG_BUS_OFFSET(num_buses) - 1;
+                        snprintf(cfg->name, PCI_MMCFG_RESOURCE_NAME_LEN,
+                                 "PCI MMCONFIG %04x [bus %02x-%02x]",
+                                 cfg->segment, cfg->start_bus, cfg->end_bus);
+                        printk(KERN_INFO PREFIX
+                               "MMCONFIG for %04x [bus%02x-%02x] "
+                               "at %pR (base %#lx) (size reduced!)\n",
+                               cfg->segment, cfg->start_bus, cfg->end_bus,
+                               &cfg->res, (unsigned long) cfg->address);
                 }
         }
 
@@ -471,45 +482,26 @@ static int __init is_mmconf_reserved(check_reserved_t is_reserved,
 
 static void __init pci_mmcfg_reject_broken(int early)
 {
-        typeof(pci_mmcfg_config[0]) *cfg;
-        int i;
+        struct pci_mmcfg_region *cfg;
 
-        if ((pci_mmcfg_config_num == 0) ||
-            (pci_mmcfg_config == NULL) ||
-            (pci_mmcfg_config[0].address == 0))
-                return;
-
-        for (i = 0; i < pci_mmcfg_config_num; i++) {
+        list_for_each_entry(cfg, &pci_mmcfg_list, list) {
                 int valid = 0;
-                u64 addr, size;
-
-                cfg = &pci_mmcfg_config[i];
-                addr = cfg->start_bus_number;
-                addr <<= 20;
-                addr += cfg->address;
-                size = cfg->end_bus_number + 1 - cfg->start_bus_number;
-                size <<= 20;
-                printk(KERN_NOTICE "PCI: MCFG configuration %d: base %lx "
-                       "segment %hu buses %u - %u\n",
-                       i, (unsigned long)cfg->address, cfg->pci_segment,
-                       (unsigned int)cfg->start_bus_number,
-                       (unsigned int)cfg->end_bus_number);
 
                 if (!early && !acpi_disabled)
-                        valid = is_mmconf_reserved(is_acpi_reserved, addr, size, i, cfg, 0);
+                        valid = is_mmconf_reserved(is_acpi_reserved, cfg, 0);
 
                 if (valid)
                         continue;
 
                 if (!early)
-                        printk(KERN_ERR "PCI: BIOS Bug: MCFG area at %Lx is not"
-                               " reserved in ACPI motherboard resources\n",
-                               cfg->address);
+                        printk(KERN_ERR FW_BUG PREFIX
+                               "MMCONFIG at %pR not reserved in "
+                               "ACPI motherboard resources\n", &cfg->res);
 
                 /* Don't try to do this check unless configuration
                    type 1 is available. how about type 2 ?*/
                 if (raw_pci_ops)
-                        valid = is_mmconf_reserved(e820_all_mapped, addr, size, i, cfg, 1);
+                        valid = is_mmconf_reserved(e820_all_mapped, cfg, 1);
 
                 if (!valid)
                         goto reject;
@@ -518,34 +510,41 @@ static void __init pci_mmcfg_reject_broken(int early)
         return;
 
 reject:
-        printk(KERN_INFO "PCI: Not using MMCONFIG.\n");
-        pci_mmcfg_arch_free();
-        kfree(pci_mmcfg_config);
-        pci_mmcfg_config = NULL;
-        pci_mmcfg_config_num = 0;
+        printk(KERN_INFO PREFIX "not using MMCONFIG\n");
+        free_all_mmcfg();
 }
 
 static int __initdata known_bridge;
 
-static int acpi_mcfg_64bit_base_addr __initdata = FALSE;
+static int __init acpi_mcfg_check_entry(struct acpi_table_mcfg *mcfg,
+                                        struct acpi_mcfg_allocation *cfg)
+{
+        int year;
 
-/* The physical address of the MMCONFIG aperture.  Set from ACPI tables. */
-struct acpi_mcfg_allocation *pci_mmcfg_config;
-int pci_mmcfg_config_num;
+        if (cfg->address < 0xFFFFFFFF)
+                return 0;
 
-static int __init acpi_mcfg_oem_check(struct acpi_table_mcfg *mcfg)
-{
         if (!strcmp(mcfg->header.oem_id, "SGI"))
-                acpi_mcfg_64bit_base_addr = TRUE;
+                return 0;
 
-        return 0;
+        if (mcfg->header.revision >= 1) {
+                if (dmi_get_date(DMI_BIOS_DATE, &year, NULL, NULL) &&
+                    year >= 2010)
+                        return 0;
+        }
+
+        printk(KERN_ERR PREFIX "MCFG region for %04x [bus %02x-%02x] at %#llx "
+               "is above 4GB, ignored\n", cfg->pci_segment,
+               cfg->start_bus_number, cfg->end_bus_number, cfg->address);
+        return -EINVAL;
 }
 
 static int __init pci_parse_mcfg(struct acpi_table_header *header)
 {
         struct acpi_table_mcfg *mcfg;
+        struct acpi_mcfg_allocation *cfg_table, *cfg;
         unsigned long i;
-        int config_size;
+        int entries;
 
         if (!header)
                 return -EINVAL;
@@ -553,38 +552,33 @@ static int __init pci_parse_mcfg(struct acpi_table_header *header)
         mcfg = (struct acpi_table_mcfg *)header;
 
         /* how many config structures do we have */
-        pci_mmcfg_config_num = 0;
+        free_all_mmcfg();
+        entries = 0;
         i = header->length - sizeof(struct acpi_table_mcfg);
         while (i >= sizeof(struct acpi_mcfg_allocation)) {
-                ++pci_mmcfg_config_num;
+                entries++;
                 i -= sizeof(struct acpi_mcfg_allocation);
         };
-        if (pci_mmcfg_config_num == 0) {
+        if (entries == 0) {
                 printk(KERN_ERR PREFIX "MMCONFIG has no entries\n");
                 return -ENODEV;
         }
 
-        config_size = pci_mmcfg_config_num * sizeof(*pci_mmcfg_config);
-        pci_mmcfg_config = kmalloc(config_size, GFP_KERNEL);
-        if (!pci_mmcfg_config) {
-                printk(KERN_WARNING PREFIX
-                       "No memory for MCFG config tables\n");
-                return -ENOMEM;
-        }
-
-        memcpy(pci_mmcfg_config, &mcfg[1], config_size);
-
-        acpi_mcfg_oem_check(mcfg);
-
-        for (i = 0; i < pci_mmcfg_config_num; ++i) {
-                if ((pci_mmcfg_config[i].address > 0xFFFFFFFF) &&
-                    !acpi_mcfg_64bit_base_addr) {
-                        printk(KERN_ERR PREFIX
-                               "MMCONFIG not in low 4GB of memory\n");
-                        kfree(pci_mmcfg_config);
-                        pci_mmcfg_config_num = 0;
+        cfg_table = (struct acpi_mcfg_allocation *) &mcfg[1];
+        for (i = 0; i < entries; i++) {
+                cfg = &cfg_table[i];
+                if (acpi_mcfg_check_entry(mcfg, cfg)) {
+                        free_all_mmcfg();
                         return -ENODEV;
                 }
+
+                if (pci_mmconfig_add(cfg->pci_segment, cfg->start_bus_number,
+                                   cfg->end_bus_number, cfg->address) == NULL) {
+                        printk(KERN_WARNING PREFIX
+                               "no memory for MCFG entries\n");
+                        free_all_mmcfg();
+                        return -ENOMEM;
+                }
         }
 
         return 0;
@@ -614,9 +608,7 @@ static void __init __pci_mmcfg_init(int early)
 
         pci_mmcfg_reject_broken(early);
 
-        if ((pci_mmcfg_config_num == 0) ||
-            (pci_mmcfg_config == NULL) ||
-            (pci_mmcfg_config[0].address == 0))
+        if (list_empty(&pci_mmcfg_list))
                 return;
 
         if (pci_mmcfg_arch_init())
@@ -648,9 +640,7 @@ static int __init pci_mmcfg_late_insert_resources(void)
          */
         if ((pci_mmcfg_resources_inserted == 1) ||
             (pci_probe & PCI_PROBE_MMCONF) == 0 ||
-            (pci_mmcfg_config_num == 0) ||
-            (pci_mmcfg_config == NULL) ||
-            (pci_mmcfg_config[0].address == 0))
+            list_empty(&pci_mmcfg_list))
                 return 1;
 
         /*
diff --git a/arch/x86/pci/mmconfig_32.c b/arch/x86/pci/mmconfig_32.c
index f10a7e94a84c..90d5fd476ed4 100644
--- a/arch/x86/pci/mmconfig_32.c
+++ b/arch/x86/pci/mmconfig_32.c
@@ -27,18 +27,10 @@ static int mmcfg_last_accessed_cpu;
  */
 static u32 get_base_addr(unsigned int seg, int bus, unsigned devfn)
 {
-        struct acpi_mcfg_allocation *cfg;
-        int cfg_num;
-
-        for (cfg_num = 0; cfg_num < pci_mmcfg_config_num; cfg_num++) {
-                cfg = &pci_mmcfg_config[cfg_num];
-                if (cfg->pci_segment == seg &&
-                    (cfg->start_bus_number <= bus) &&
-                    (cfg->end_bus_number >= bus))
-                        return cfg->address;
-        }
+        struct pci_mmcfg_region *cfg = pci_mmconfig_lookup(seg, bus);
 
-        /* Fall back to type 0 */
+        if (cfg)
+                return cfg->address;
         return 0;
 }
 
@@ -47,7 +39,7 @@ static u32 get_base_addr(unsigned int seg, int bus, unsigned devfn)
  */
 static void pci_exp_set_dev_base(unsigned int base, int bus, int devfn)
 {
-        u32 dev_base = base | (bus << 20) | (devfn << 12);
+        u32 dev_base = base | PCI_MMCFG_BUS_OFFSET(bus) | (devfn << 12);
         int cpu = smp_processor_id();
         if (dev_base != mmcfg_last_accessed_device ||
             cpu != mmcfg_last_accessed_cpu) {
diff --git a/arch/x86/pci/mmconfig_64.c b/arch/x86/pci/mmconfig_64.c
index 94349f8b2f96..e783841bd1d7 100644
--- a/arch/x86/pci/mmconfig_64.c
+++ b/arch/x86/pci/mmconfig_64.c
@@ -12,38 +12,15 @@
 #include <asm/e820.h>
 #include <asm/pci_x86.h>
 
-/* Static virtual mapping of the MMCONFIG aperture */
-struct mmcfg_virt {
-        struct acpi_mcfg_allocation *cfg;
-        char __iomem *virt;
-};
-static struct mmcfg_virt *pci_mmcfg_virt;
-
-static char __iomem *get_virt(unsigned int seg, unsigned bus)
-{
-        struct acpi_mcfg_allocation *cfg;
-        int cfg_num;
-
-        for (cfg_num = 0; cfg_num < pci_mmcfg_config_num; cfg_num++) {
-                cfg = pci_mmcfg_virt[cfg_num].cfg;
-                if (cfg->pci_segment == seg &&
-                    (cfg->start_bus_number <= bus) &&
-                    (cfg->end_bus_number >= bus))
-                        return pci_mmcfg_virt[cfg_num].virt;
-        }
-
-        /* Fall back to type 0 */
-        return NULL;
-}
+#define PREFIX "PCI: "
 
 static char __iomem *pci_dev_base(unsigned int seg, unsigned int bus, unsigned int devfn)
 {
-        char __iomem *addr;
+        struct pci_mmcfg_region *cfg = pci_mmconfig_lookup(seg, bus);
 
-        addr = get_virt(seg, bus);
-        if (!addr)
-                return NULL;
-        return addr + ((bus << 20) | (devfn << 12));
+        if (cfg && cfg->virt)
+                return cfg->virt + (PCI_MMCFG_BUS_OFFSET(bus) | (devfn << 12));
+        return NULL;
 }
 
 static int pci_mmcfg_read(unsigned int seg, unsigned int bus,
@@ -109,42 +86,30 @@ static struct pci_raw_ops pci_mmcfg = {
         .write =        pci_mmcfg_write,
 };
 
-static void __iomem * __init mcfg_ioremap(struct acpi_mcfg_allocation *cfg)
+static void __iomem * __init mcfg_ioremap(struct pci_mmcfg_region *cfg)
 {
         void __iomem *addr;
         u64 start, size;
+        int num_buses;
 
-        start = cfg->start_bus_number;
-        start <<= 20;
-        start += cfg->address;
-        size = cfg->end_bus_number + 1 - cfg->start_bus_number;
-        size <<= 20;
+        start = cfg->address + PCI_MMCFG_BUS_OFFSET(cfg->start_bus);
+        num_buses = cfg->end_bus - cfg->start_bus + 1;
+        size = PCI_MMCFG_BUS_OFFSET(num_buses);
         addr = ioremap_nocache(start, size);
-        if (addr) {
-                printk(KERN_INFO "PCI: Using MMCONFIG at %Lx - %Lx\n",
-                       start, start + size - 1);
-                addr -= cfg->start_bus_number << 20;
-        }
+        if (addr)
+                addr -= PCI_MMCFG_BUS_OFFSET(cfg->start_bus);
         return addr;
 }
 
 int __init pci_mmcfg_arch_init(void)
 {
-        int i;
-        pci_mmcfg_virt = kzalloc(sizeof(*pci_mmcfg_virt) *
-                                 pci_mmcfg_config_num, GFP_KERNEL);
-        if (pci_mmcfg_virt == NULL) {
-                printk(KERN_ERR "PCI: Can not allocate memory for mmconfig structures\n");
-                return 0;
-        }
+        struct pci_mmcfg_region *cfg;
 
-        for (i = 0; i < pci_mmcfg_config_num; ++i) {
-                pci_mmcfg_virt[i].cfg = &pci_mmcfg_config[i];
-                pci_mmcfg_virt[i].virt = mcfg_ioremap(&pci_mmcfg_config[i]);
-                if (!pci_mmcfg_virt[i].virt) {
-                        printk(KERN_ERR "PCI: Cannot map mmconfig aperture for "
-                                        "segment %d\n",
-                                pci_mmcfg_config[i].pci_segment);
+        list_for_each_entry(cfg, &pci_mmcfg_list, list) {
+                cfg->virt = mcfg_ioremap(cfg);
+                if (!cfg->virt) {
+                        printk(KERN_ERR PREFIX "can't map MMCONFIG at %pR\n",
+                               &cfg->res);
                         pci_mmcfg_arch_free();
                         return 0;
                 }
@@ -155,19 +120,12 @@ int __init pci_mmcfg_arch_init(void)
 
 void __init pci_mmcfg_arch_free(void)
 {
-        int i;
-
-        if (pci_mmcfg_virt == NULL)
-                return;
+        struct pci_mmcfg_region *cfg;
 
-        for (i = 0; i < pci_mmcfg_config_num; ++i) {
-                if (pci_mmcfg_virt[i].virt) {
-                        iounmap(pci_mmcfg_virt[i].virt + (pci_mmcfg_virt[i].cfg->start_bus_number << 20));
-                        pci_mmcfg_virt[i].virt = NULL;
-                        pci_mmcfg_virt[i].cfg = NULL;
+        list_for_each_entry(cfg, &pci_mmcfg_list, list) {
+                if (cfg->virt) {
+                        iounmap(cfg->virt + PCI_MMCFG_BUS_OFFSET(cfg->start_bus));
+                        cfg->virt = NULL;
                 }
         }
-
-        kfree(pci_mmcfg_virt);
-        pci_mmcfg_virt = NULL;
 }
diff --git a/arch/x86/tools/test_get_len.c b/arch/x86/tools/test_get_len.c
index d8214dc03fa7..bee8d6ac2691 100644
--- a/arch/x86/tools/test_get_len.c
+++ b/arch/x86/tools/test_get_len.c
@@ -113,7 +113,7 @@ int main(int argc, char **argv)
         char line[BUFSIZE], sym[BUFSIZE] = "<unknown>";
         unsigned char insn_buf[16];
         struct insn insn;
-        int insns = 0, c;
+        int insns = 0;
         int warnings = 0;
 
         parse_args(argc, argv);
diff --git a/arch/x86/xen/enlighten.c b/arch/x86/xen/enlighten.c
index b8e45f164e2a..2b26dd5930c6 100644
--- a/arch/x86/xen/enlighten.c
+++ b/arch/x86/xen/enlighten.c
@@ -27,7 +27,9 @@
 #include <linux/page-flags.h>
 #include <linux/highmem.h>
 #include <linux/console.h>
+#include <linux/pci.h>
 
+#include <xen/xen.h>
 #include <xen/interface/xen.h>
 #include <xen/interface/version.h>
 #include <xen/interface/physdev.h>
@@ -1175,7 +1177,11 @@ asmlinkage void __init xen_start_kernel(void)
                 add_preferred_console("xenboot", 0, NULL);
                 add_preferred_console("tty", 0, NULL);
                 add_preferred_console("hvc", 0, NULL);
+        } else {
+                /* Make sure ACS will be enabled */
+                pci_request_acs();
         }
+                
 
         xen_raw_console_write("about to get started...\n");
 
diff --git a/arch/x86/xen/smp.c b/arch/x86/xen/smp.c
index 64757c0ba5fc..563d20504988 100644
--- a/arch/x86/xen/smp.c
+++ b/arch/x86/xen/smp.c
@@ -35,10 +35,10 @@
 
 cpumask_var_t xen_cpu_initialized_map;
 
-static DEFINE_PER_CPU(int, resched_irq);
-static DEFINE_PER_CPU(int, callfunc_irq);
-static DEFINE_PER_CPU(int, callfuncsingle_irq);
-static DEFINE_PER_CPU(int, debug_irq) = -1;
+static DEFINE_PER_CPU(int, xen_resched_irq);
+static DEFINE_PER_CPU(int, xen_callfunc_irq);
+static DEFINE_PER_CPU(int, xen_callfuncsingle_irq);
+static DEFINE_PER_CPU(int, xen_debug_irq) = -1;
 
 static irqreturn_t xen_call_function_interrupt(int irq, void *dev_id);
 static irqreturn_t xen_call_function_single_interrupt(int irq, void *dev_id);
@@ -103,7 +103,7 @@ static int xen_smp_intr_init(unsigned int cpu)
                                     NULL);
         if (rc < 0)
                 goto fail;
-        per_cpu(resched_irq, cpu) = rc;
+        per_cpu(xen_resched_irq, cpu) = rc;
 
         callfunc_name = kasprintf(GFP_KERNEL, "callfunc%d", cpu);
         rc = bind_ipi_to_irqhandler(XEN_CALL_FUNCTION_VECTOR,
@@ -114,7 +114,7 @@ static int xen_smp_intr_init(unsigned int cpu)
                                     NULL);
         if (rc < 0)
                 goto fail;
-        per_cpu(callfunc_irq, cpu) = rc;
+        per_cpu(xen_callfunc_irq, cpu) = rc;
 
         debug_name = kasprintf(GFP_KERNEL, "debug%d", cpu);
         rc = bind_virq_to_irqhandler(VIRQ_DEBUG, cpu, xen_debug_interrupt,
@@ -122,7 +122,7 @@ static int xen_smp_intr_init(unsigned int cpu)
                                      debug_name, NULL);
         if (rc < 0)
                 goto fail;
-        per_cpu(debug_irq, cpu) = rc;
+        per_cpu(xen_debug_irq, cpu) = rc;
 
         callfunc_name = kasprintf(GFP_KERNEL, "callfuncsingle%d", cpu);
         rc = bind_ipi_to_irqhandler(XEN_CALL_FUNCTION_SINGLE_VECTOR,
@@ -133,19 +133,20 @@ static int xen_smp_intr_init(unsigned int cpu)
                                     NULL);
         if (rc < 0)
                 goto fail;
-        per_cpu(callfuncsingle_irq, cpu) = rc;
+        per_cpu(xen_callfuncsingle_irq, cpu) = rc;
 
         return 0;
 
  fail:
-        if (per_cpu(resched_irq, cpu) >= 0)
-                unbind_from_irqhandler(per_cpu(resched_irq, cpu), NULL);
-        if (per_cpu(callfunc_irq, cpu) >= 0)
-                unbind_from_irqhandler(per_cpu(callfunc_irq, cpu), NULL);
-        if (per_cpu(debug_irq, cpu) >= 0)
-                unbind_from_irqhandler(per_cpu(debug_irq, cpu), NULL);
-        if (per_cpu(callfuncsingle_irq, cpu) >= 0)
-                unbind_from_irqhandler(per_cpu(callfuncsingle_irq, cpu), NULL);
+        if (per_cpu(xen_resched_irq, cpu) >= 0)
+                unbind_from_irqhandler(per_cpu(xen_resched_irq, cpu), NULL);
+        if (per_cpu(xen_callfunc_irq, cpu) >= 0)
+                unbind_from_irqhandler(per_cpu(xen_callfunc_irq, cpu), NULL);
+        if (per_cpu(xen_debug_irq, cpu) >= 0)
+                unbind_from_irqhandler(per_cpu(xen_debug_irq, cpu), NULL);
+        if (per_cpu(xen_callfuncsingle_irq, cpu) >= 0)
+                unbind_from_irqhandler(per_cpu(xen_callfuncsingle_irq, cpu),
+                                       NULL);
 
         return rc;
 }
@@ -349,10 +350,10 @@ static void xen_cpu_die(unsigned int cpu)
                 current->state = TASK_UNINTERRUPTIBLE;
                 schedule_timeout(HZ/10);
         }
-        unbind_from_irqhandler(per_cpu(resched_irq, cpu), NULL);
-        unbind_from_irqhandler(per_cpu(callfunc_irq, cpu), NULL);
-        unbind_from_irqhandler(per_cpu(debug_irq, cpu), NULL);
-        unbind_from_irqhandler(per_cpu(callfuncsingle_irq, cpu), NULL);
+        unbind_from_irqhandler(per_cpu(xen_resched_irq, cpu), NULL);
+        unbind_from_irqhandler(per_cpu(xen_callfunc_irq, cpu), NULL);
+        unbind_from_irqhandler(per_cpu(xen_debug_irq, cpu), NULL);
+        unbind_from_irqhandler(per_cpu(xen_callfuncsingle_irq, cpu), NULL);
         xen_uninit_lock_cpu(cpu);
         xen_teardown_timer(cpu);
 
diff --git a/arch/x86/xen/spinlock.c b/arch/x86/xen/spinlock.c
index 36a5141108df..24ded31b5aec 100644
--- a/arch/x86/xen/spinlock.c
+++ b/arch/x86/xen/spinlock.c
@@ -120,14 +120,14 @@ struct xen_spinlock {
         unsigned short spinners;        /* count of waiting cpus */
 };
 
-static int xen_spin_is_locked(struct raw_spinlock *lock)
+static int xen_spin_is_locked(struct arch_spinlock *lock)
 {
         struct xen_spinlock *xl = (struct xen_spinlock *)lock;
 
         return xl->lock != 0;
 }
 
-static int xen_spin_is_contended(struct raw_spinlock *lock)
+static int xen_spin_is_contended(struct arch_spinlock *lock)
 {
         struct xen_spinlock *xl = (struct xen_spinlock *)lock;
 
@@ -136,7 +136,7 @@ static int xen_spin_is_contended(struct raw_spinlock *lock)
         return xl->spinners != 0;
 }
 
-static int xen_spin_trylock(struct raw_spinlock *lock)
+static int xen_spin_trylock(struct arch_spinlock *lock)
 {
         struct xen_spinlock *xl = (struct xen_spinlock *)lock;
         u8 old = 1;
@@ -181,7 +181,7 @@ static inline void unspinning_lock(struct xen_spinlock *xl, struct xen_spinlock
         __get_cpu_var(lock_spinners) = prev;
 }
 
-static noinline int xen_spin_lock_slow(struct raw_spinlock *lock, bool irq_enable)
+static noinline int xen_spin_lock_slow(struct arch_spinlock *lock, bool irq_enable)
 {
         struct xen_spinlock *xl = (struct xen_spinlock *)lock;
         struct xen_spinlock *prev;
@@ -254,7 +254,7 @@ out:
         return ret;
 }
 
-static inline void __xen_spin_lock(struct raw_spinlock *lock, bool irq_enable)
+static inline void __xen_spin_lock(struct arch_spinlock *lock, bool irq_enable)
 {
         struct xen_spinlock *xl = (struct xen_spinlock *)lock;
         unsigned timeout;
@@ -291,12 +291,12 @@ static inline void __xen_spin_lock(struct raw_spinlock *lock, bool irq_enable)
         spin_time_accum_total(start_spin);
 }
 
-static void xen_spin_lock(struct raw_spinlock *lock)
+static void xen_spin_lock(struct arch_spinlock *lock)
 {
         __xen_spin_lock(lock, false);
 }
 
-static void xen_spin_lock_flags(struct raw_spinlock *lock, unsigned long flags)
+static void xen_spin_lock_flags(struct arch_spinlock *lock, unsigned long flags)
 {
         __xen_spin_lock(lock, !raw_irqs_disabled_flags(flags));
 }
@@ -317,7 +317,7 @@ static noinline void xen_spin_unlock_slow(struct xen_spinlock *xl)
         }
 }
 
-static void xen_spin_unlock(struct raw_spinlock *lock)
+static void xen_spin_unlock(struct arch_spinlock *lock)
 {
         struct xen_spinlock *xl = (struct xen_spinlock *)lock;
 
diff --git a/arch/x86/xen/time.c b/arch/x86/xen/time.c
index 9d1f853120d8..0d3f07cd1b5f 100644
--- a/arch/x86/xen/time.c
+++ b/arch/x86/xen/time.c
@@ -31,14 +31,14 @@
 #define NS_PER_TICK     (1000000000LL / HZ)
 
 /* runstate info updated by Xen */
-static DEFINE_PER_CPU(struct vcpu_runstate_info, runstate);
+static DEFINE_PER_CPU(struct vcpu_runstate_info, xen_runstate);
 
 /* snapshots of runstate info */
-static DEFINE_PER_CPU(struct vcpu_runstate_info, runstate_snapshot);
+static DEFINE_PER_CPU(struct vcpu_runstate_info, xen_runstate_snapshot);
 
 /* unused ns of stolen and blocked time */
-static DEFINE_PER_CPU(u64, residual_stolen);
-static DEFINE_PER_CPU(u64, residual_blocked);
+static DEFINE_PER_CPU(u64, xen_residual_stolen);
+static DEFINE_PER_CPU(u64, xen_residual_blocked);
 
 /* return an consistent snapshot of 64-bit time/counter value */
 static u64 get64(const u64 *p)
@@ -79,7 +79,7 @@ static void get_runstate_snapshot(struct vcpu_runstate_info *res)
 
         BUG_ON(preemptible());
 
-        state = &__get_cpu_var(runstate);
+        state = &__get_cpu_var(xen_runstate);
 
         /*
          * The runstate info is always updated by the hypervisor on
@@ -97,14 +97,14 @@ static void get_runstate_snapshot(struct vcpu_runstate_info *res)
 /* return true when a vcpu could run but has no real cpu to run on */
 bool xen_vcpu_stolen(int vcpu)
 {
-        return per_cpu(runstate, vcpu).state == RUNSTATE_runnable;
+        return per_cpu(xen_runstate, vcpu).state == RUNSTATE_runnable;
 }
 
 void xen_setup_runstate_info(int cpu)
 {
         struct vcpu_register_runstate_memory_area area;
 
-        area.addr.v = &per_cpu(runstate, cpu);
+        area.addr.v = &per_cpu(xen_runstate, cpu);
 
         if (HYPERVISOR_vcpu_op(VCPUOP_register_runstate_memory_area,
                                cpu, &area))
@@ -122,7 +122,7 @@ static void do_stolen_accounting(void)
 
         WARN_ON(state.state != RUNSTATE_running);
 
-        snap = &__get_cpu_var(runstate_snapshot);
+        snap = &__get_cpu_var(xen_runstate_snapshot);
 
         /* work out how much time the VCPU has not been runn*ing*  */
         blocked = state.time[RUNSTATE_blocked] - snap->time[RUNSTATE_blocked];
@@ -133,24 +133,24 @@ static void do_stolen_accounting(void)
 
         /* Add the appropriate number of ticks of stolen time,
            including any left-overs from last time. */
-        stolen = runnable + offline + __get_cpu_var(residual_stolen);
+        stolen = runnable + offline + __get_cpu_var(xen_residual_stolen);
 
         if (stolen < 0)
                 stolen = 0;
 
         ticks = iter_div_u64_rem(stolen, NS_PER_TICK, &stolen);
-        __get_cpu_var(residual_stolen) = stolen;
+        __get_cpu_var(xen_residual_stolen) = stolen;
         account_steal_ticks(ticks);
 
         /* Add the appropriate number of ticks of blocked time,
            including any left-overs from last time. */
-        blocked += __get_cpu_var(residual_blocked);
+        blocked += __get_cpu_var(xen_residual_blocked);
 
         if (blocked < 0)
                 blocked = 0;
 
         ticks = iter_div_u64_rem(blocked, NS_PER_TICK, &blocked);
-        __get_cpu_var(residual_blocked) = blocked;
+        __get_cpu_var(xen_residual_blocked) = blocked;
         account_idle_ticks(ticks);
 }
 
diff --git a/arch/xtensa/include/asm/asm-offsets.h b/arch/xtensa/include/asm/asm-offsets.h
new file mode 100644
index 000000000000..d370ee36a182
--- /dev/null
+++ b/arch/xtensa/include/asm/asm-offsets.h
@@ -0,0 +1 @@
+#include <generated/asm-offsets.h>
diff --git a/arch/xtensa/include/asm/elf.h b/arch/xtensa/include/asm/elf.h
index c3f53e755ca5..5eb6d695e987 100644
--- a/arch/xtensa/include/asm/elf.h
+++ b/arch/xtensa/include/asm/elf.h
@@ -123,7 +123,6 @@ extern void xtensa_elf_core_copy_regs (xtensa_gregset_t *, struct pt_regs *);
 #define ELF_CLASS       ELFCLASS32
 #define ELF_ARCH        EM_XTENSA
 
-#define USE_ELF_CORE_DUMP
 #define ELF_EXEC_PAGESIZE       PAGE_SIZE
 
 /*
diff --git a/arch/xtensa/include/asm/syscall.h b/arch/xtensa/include/asm/syscall.h
index 05cebf8f62b1..efcf33b92e4c 100644
--- a/arch/xtensa/include/asm/syscall.h
+++ b/arch/xtensa/include/asm/syscall.h
@@ -12,9 +12,6 @@ struct pt_regs;
 struct sigaction;
 asmlinkage long xtensa_execve(char*, char**, char**, struct pt_regs*);
 asmlinkage long xtensa_clone(unsigned long, unsigned long, struct pt_regs*);
-asmlinkage long xtensa_pipe(int __user *);
-asmlinkage long xtensa_mmap2(unsigned long, unsigned long, unsigned long,
-                             unsigned long, unsigned long, unsigned long);
 asmlinkage long xtensa_ptrace(long, long, long, long);
 asmlinkage long xtensa_sigreturn(struct pt_regs*);
 asmlinkage long xtensa_rt_sigreturn(struct pt_regs*);
diff --git a/arch/xtensa/include/asm/unistd.h b/arch/xtensa/include/asm/unistd.h
index 4e55dc763021..528042c2951e 100644
--- a/arch/xtensa/include/asm/unistd.h
+++ b/arch/xtensa/include/asm/unistd.h
@@ -94,7 +94,7 @@ __SYSCALL( 35, sys_readlink, 3)
 #define __NR_mknod                               36
 __SYSCALL( 36, sys_mknod, 3)
 #define __NR_pipe                                37
-__SYSCALL( 37, xtensa_pipe, 1)
+__SYSCALL( 37, sys_pipe, 1)
 #define __NR_unlink                              38
 __SYSCALL( 38, sys_unlink, 1)
 #define __NR_rmdir                               39
@@ -189,7 +189,7 @@ __SYSCALL( 79, sys_fremovexattr, 2)
 /* File Map / Shared Memory Operations */
 
 #define __NR_mmap2                               80
-__SYSCALL( 80, xtensa_mmap2, 6)
+__SYSCALL( 80, sys_mmap_pgoff, 6)
 #define __NR_munmap                              81
 __SYSCALL( 81, sys_munmap, 2)
 #define __NR_mprotect                            82
diff --git a/arch/xtensa/kernel/irq.c b/arch/xtensa/kernel/irq.c
index a1badb32fcda..8cd38484e130 100644
--- a/arch/xtensa/kernel/irq.c
+++ b/arch/xtensa/kernel/irq.c
@@ -90,7 +90,7 @@ int show_interrupts(struct seq_file *p, void *v)
         }
 
         if (i < NR_IRQS) {
-                spin_lock_irqsave(&irq_desc[i].lock, flags);
+                raw_spin_lock_irqsave(&irq_desc[i].lock, flags);
                 action = irq_desc[i].action;
                 if (!action)
                         goto skip;
@@ -109,7 +109,7 @@ int show_interrupts(struct seq_file *p, void *v)
 
                 seq_putc(p, '\n');
 skip:
-                spin_unlock_irqrestore(&irq_desc[i].lock, flags);
+                raw_spin_unlock_irqrestore(&irq_desc[i].lock, flags);
         } else if (i == NR_IRQS) {
                 seq_printf(p, "NMI: ");
                 for_each_online_cpu(j)
diff --git a/arch/xtensa/kernel/syscall.c b/arch/xtensa/kernel/syscall.c
index ac15ecbdf919..816e6d0d686c 100644
--- a/arch/xtensa/kernel/syscall.c
+++ b/arch/xtensa/kernel/syscall.c
@@ -39,49 +39,6 @@ syscall_t sys_call_table[__NR_syscall_count] /* FIXME __cacheline_aligned */= {
 #include <asm/unistd.h>
 };
 
-/*
- * xtensa_pipe() is the normal C calling standard for creating a pipe. It's not
- * the way unix traditional does this, though.
- */
-
-asmlinkage long xtensa_pipe(int __user *userfds)
-{
-        int fd[2];
-        int error;
-
-        error = do_pipe_flags(fd, 0);
-        if (!error) {
-                if (copy_to_user(userfds, fd, 2 * sizeof(int)))
-                        error = -EFAULT;
-        }
-        return error;
-}
-
-
-asmlinkage long xtensa_mmap2(unsigned long addr, unsigned long len,
-                             unsigned long prot, unsigned long flags,
-                             unsigned long fd, unsigned long pgoff)
-{
-        int error = -EBADF;
-        struct file * file = NULL;
-
-        flags &= ~(MAP_EXECUTABLE | MAP_DENYWRITE);
-        if (!(flags & MAP_ANONYMOUS)) {
-                file = fget(fd);
-                if (!file)
-                        goto out;
-        }
-
-        down_write(&current->mm->mmap_sem);
-        error = do_mmap_pgoff(file, addr, len, prot, flags, pgoff);
-        up_write(&current->mm->mmap_sem);
-
-        if (file)
-                fput(file);
-out:
-        return error;
-}
-
 asmlinkage long xtensa_shmat(int shmid, char __user *shmaddr, int shmflg)
 {
         unsigned long ret;
diff --git a/arch/xtensa/platforms/iss/console.c b/arch/xtensa/platforms/iss/console.c
index 4c559cf7da2d..e60a1f57022f 100644
--- a/arch/xtensa/platforms/iss/console.c
+++ b/arch/xtensa/platforms/iss/console.c
@@ -196,7 +196,7 @@ static const struct file_operations rs_proc_fops = {
         .release        = single_release,
 };
 
-static struct tty_operations serial_ops = {
+static const struct tty_operations serial_ops = {
         .open = rs_open,
         .close = rs_close,
         .write = rs_write,