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authorAnton Blanchard <anton@samba.org>2012-04-10 12:22:53 -0400
committerBenjamin Herrenschmidt <benh@kernel.crashing.org>2012-04-30 01:37:16 -0400
commit59c19cb2f6a7928a2fd3afd22bfe988e025b41d8 (patch)
tree59d2bf2c6b76c1891644d82234aa5e1d981d7e94 /arch
parent448054a6508d74767ba4c76654b42182e4f750b6 (diff)
powerpc: Reformat lppaca.h
Reformat lppaca.h to match Linux coding standards. Signed-off-by: Anton Blanchard <anton@samba.org> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Diffstat (limited to 'arch')
-rw-r--r--arch/powerpc/include/asm/lppaca.h140
1 files changed, 68 insertions, 72 deletions
diff --git a/arch/powerpc/include/asm/lppaca.h b/arch/powerpc/include/asm/lppaca.h
index 06effe61a0de..531fe0c3108f 100644
--- a/arch/powerpc/include/asm/lppaca.h
+++ b/arch/powerpc/include/asm/lppaca.h
@@ -20,18 +20,16 @@
20#define _ASM_POWERPC_LPPACA_H 20#define _ASM_POWERPC_LPPACA_H
21#ifdef __KERNEL__ 21#ifdef __KERNEL__
22 22
23/* These definitions relate to hypervisors that only exist when using 23/*
24 * These definitions relate to hypervisors that only exist when using
24 * a server type processor 25 * a server type processor
25 */ 26 */
26#ifdef CONFIG_PPC_BOOK3S 27#ifdef CONFIG_PPC_BOOK3S
27 28
28//============================================================================= 29/*
29// 30 * This control block contains the data that is shared between the
30// This control block contains the data that is shared between the 31 * hypervisor and the OS.
31// hypervisor and the OS. 32 */
32//
33//
34//----------------------------------------------------------------------------
35#include <linux/cache.h> 33#include <linux/cache.h>
36#include <linux/threads.h> 34#include <linux/threads.h>
37#include <asm/types.h> 35#include <asm/types.h>
@@ -43,67 +41,65 @@
43 */ 41 */
44#define NR_LPPACAS 1 42#define NR_LPPACAS 1
45 43
46 44/*
47/* The Hypervisor barfs if the lppaca crosses a page boundary. A 1k 45 * The Hypervisor barfs if the lppaca crosses a page boundary. A 1k
48 * alignment is sufficient to prevent this */ 46 * alignment is sufficient to prevent this
47 */
49struct lppaca { 48struct lppaca {
50//============================================================================= 49 /* cacheline 1 contains read-only data */
51// CACHE_LINE_1 0x0000 - 0x007F Contains read-only data 50
52//============================================================================= 51 u32 desc; /* Eye catcher 0xD397D781 */
53 u32 desc; // Eye catcher 0xD397D781 x00-x03 52 u16 size; /* Size of this struct */
54 u16 size; // Size of this struct x04-x05 53 u16 reserved1;
55 u16 reserved1; // Reserved x06-x07 54 u16 reserved2:14;
56 u16 reserved2:14; // Reserved x08-x09 55 u8 shared_proc:1; /* Shared processor indicator */
57 u8 shared_proc:1; // Shared processor indicator ... 56 u8 secondary_thread:1; /* Secondary thread indicator */
58 u8 secondary_thread:1; // Secondary thread indicator ... 57 u8 reserved3[14];
59 u8 reserved3[14]; // x0A-x17 58 volatile u32 dyn_hw_node_id; /* Dynamic hardware node id */
60 volatile u32 dyn_hw_node_id; // Dynamic Hardware Node id x18-x1B 59 volatile u32 dyn_hw_proc_id; /* Dynamic hardware proc id */
61 volatile u32 dyn_hw_proc_id; // Dynamic Hardware Proc Id x1C-x1F 60 u8 reserved4[56];
62 u8 reserved4[56]; // Reserved x20-x57 61 volatile u8 vphn_assoc_counts[8]; /* Virtual processor home node */
63 volatile u8 vphn_assoc_counts[8]; // Virtual processor home node 62 /* associativity change counters */
64 // associativity change counters x58-x5F 63 u8 reserved5[32];
65 u8 reserved5[32]; // Reserved x60-x7F 64
66 65 /* cacheline 2 contains local read-write data */
67//============================================================================= 66
68// CACHE_LINE_2 0x0080 - 0x00FF Contains local read-write data 67 u8 reserved6[48];
69//============================================================================= 68 u8 cede_latency_hint;
70 69 u8 reserved7[7];
71 u8 reserved6[48]; // x00-x2f 70 u8 dtl_enable_mask; /* Dispatch Trace Log mask */
72 u8 cede_latency_hint; /* x30 */ 71 u8 donate_dedicated_cpu; /* Donate dedicated CPU cycles */
73 u8 reserved7[7]; /* x31-x37 */ 72 u8 fpregs_in_use;
74 u8 dtl_enable_mask; // Dispatch Trace Log mask x38-x38 73 u8 pmcregs_in_use;
75 u8 donate_dedicated_cpu; // Donate dedicated CPU cycles x39-x39 74 u8 reserved8[28];
76 u8 fpregs_in_use; // FP regs in use x3A-x3A 75 u64 wait_state_cycles; /* Wait cycles for this proc */
77 u8 pmcregs_in_use; // PMC regs in use x3B-x3B 76 u8 reserved9[28];
78 u8 reserved8[28]; // x3C-x57 77 u16 slb_count; /* # of SLBs to maintain */
79 u64 wait_state_cycles; // Wait cycles for this proc x58-x5F 78 u8 idle; /* Indicate OS is idle */
80 u8 reserved9[28]; // x60-x7B 79 u8 vmxregs_in_use;
81 u16 slb_count; // # of SLBs to maintain x7C-x7D 80
82 u8 idle; // Indicate OS is idle x7E 81 /* cacheline 3 is shared with other processors */
83 u8 vmxregs_in_use; // VMX registers in use x7F 82
84 83 /*
85//============================================================================= 84 * This is the yield_count. An "odd" value (low bit on) means that
86// CACHE_LINE_3 0x0100 - 0x017F: This line is shared with other processors 85 * the processor is yielded (either because of an OS yield or a
87//============================================================================= 86 * hypervisor preempt). An even value implies that the processor is
88 // This is the yield_count. An "odd" value (low bit on) means that 87 * currently executing.
89 // the processor is yielded (either because of an OS yield or a PLIC 88 * NOTE: This value will ALWAYS be zero for dedicated processors and
90 // preempt). An even value implies that the processor is currently 89 * will NEVER be zero for shared processors (ie, initialized to a 1).
91 // executing. 90 */
92 // NOTE: This value will ALWAYS be zero for dedicated processors and 91 volatile u32 yield_count;
93 // will NEVER be zero for shared processors (ie, initialized to a 1). 92 volatile u32 dispersion_count; /* dispatch changed physical cpu */
94 volatile u32 yield_count; // PLIC increments each dispatchx00-x03 93 volatile u64 cmo_faults; /* CMO page fault count */
95 volatile u32 dispersion_count; // dispatch changed phys cpu x04-x07 94 volatile u64 cmo_fault_time; /* CMO page fault time */
96 volatile u64 cmo_faults; // CMO page fault count x08-x0F 95 u8 reserved10[104];
97 volatile u64 cmo_fault_time; // CMO page fault time x10-x17 96
98 u8 reserved10[104]; // Reserved x18-x7F 97 /* cacheline 4-5 */
99 98
100//============================================================================= 99 u32 page_ins; /* CMO Hint - # page ins by OS */
101// CACHE_LINE_4-5 0x0180 - 0x027F Contains PMC interrupt data 100 u8 reserved11[148];
102//============================================================================= 101 volatile u64 dtl_idx; /* Dispatch Trace Log head index */
103 u32 page_ins; // CMO Hint - # page ins by OS x00-x03 102 u8 reserved12[96];
104 u8 reserved11[148]; // Reserved x04-x97
105 volatile u64 dtl_idx; // Dispatch Trace Log head idx x98-x9F
106 u8 reserved12[96]; // Reserved xA0-xFF
107} __attribute__((__aligned__(0x400))); 103} __attribute__((__aligned__(0x400)));
108 104
109extern struct lppaca lppaca[]; 105extern struct lppaca lppaca[];
@@ -116,13 +112,13 @@ extern struct lppaca lppaca[];
116 * ESID is stored in the lower 64bits, then the VSID. 112 * ESID is stored in the lower 64bits, then the VSID.
117 */ 113 */
118struct slb_shadow { 114struct slb_shadow {
119 u32 persistent; // Number of persistent SLBs x00-x03 115 u32 persistent; /* Number of persistent SLBs */
120 u32 buffer_length; // Total shadow buffer length x04-x07 116 u32 buffer_length; /* Total shadow buffer length */
121 u64 reserved; // Alignment x08-x0f 117 u64 reserved;
122 struct { 118 struct {
123 u64 esid; 119 u64 esid;
124 u64 vsid; 120 u64 vsid;
125 } save_area[SLB_NUM_BOLTED]; // x10-x40 121 } save_area[SLB_NUM_BOLTED];
126} ____cacheline_aligned; 122} ____cacheline_aligned;
127 123
128extern struct slb_shadow slb_shadow[]; 124extern struct slb_shadow slb_shadow[];
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-08 16:21:57 -0400