diff options
author | Paul Walmsley <paul@pwsan.com> | 2012-04-04 12:20:15 -0400 |
---|---|---|
committer | Paul Walmsley <paul@pwsan.com> | 2012-04-04 16:52:49 -0400 |
commit | 5897a391d41d42f19285376a4ad1320d452c2946 (patch) | |
tree | 2993e798fb145cc02447376babe826d7a4768613 /arch | |
parent | 6c4a057bffe9823221eab547e11fac181dc18a2b (diff) |
ARM: OMAP3: clock data: fill in some missing clockdomains
Several clocks are missing clockdomains. This can cause problems with
the hwmod and power management code. Fill these in.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Matt Porter <mporter@ti.com>
Cc: Vaibhav Hiremath <hvaibhav@ti.com>
Diffstat (limited to 'arch')
-rw-r--r-- | arch/arm/mach-omap2/clock3xxx_data.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/arch/arm/mach-omap2/clock3xxx_data.c b/arch/arm/mach-omap2/clock3xxx_data.c index f3a9a4a0aa04..f4a626f7c79e 100644 --- a/arch/arm/mach-omap2/clock3xxx_data.c +++ b/arch/arm/mach-omap2/clock3xxx_data.c | |||
@@ -1394,6 +1394,7 @@ static struct clk cpefuse_fck = { | |||
1394 | .name = "cpefuse_fck", | 1394 | .name = "cpefuse_fck", |
1395 | .ops = &clkops_omap2_dflt, | 1395 | .ops = &clkops_omap2_dflt, |
1396 | .parent = &sys_ck, | 1396 | .parent = &sys_ck, |
1397 | .clkdm_name = "core_l4_clkdm", | ||
1397 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3), | 1398 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3), |
1398 | .enable_bit = OMAP3430ES2_EN_CPEFUSE_SHIFT, | 1399 | .enable_bit = OMAP3430ES2_EN_CPEFUSE_SHIFT, |
1399 | .recalc = &followparent_recalc, | 1400 | .recalc = &followparent_recalc, |
@@ -1403,6 +1404,7 @@ static struct clk ts_fck = { | |||
1403 | .name = "ts_fck", | 1404 | .name = "ts_fck", |
1404 | .ops = &clkops_omap2_dflt, | 1405 | .ops = &clkops_omap2_dflt, |
1405 | .parent = &omap_32k_fck, | 1406 | .parent = &omap_32k_fck, |
1407 | .clkdm_name = "core_l4_clkdm", | ||
1406 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3), | 1408 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3), |
1407 | .enable_bit = OMAP3430ES2_EN_TS_SHIFT, | 1409 | .enable_bit = OMAP3430ES2_EN_TS_SHIFT, |
1408 | .recalc = &followparent_recalc, | 1410 | .recalc = &followparent_recalc, |
@@ -1412,6 +1414,7 @@ static struct clk usbtll_fck = { | |||
1412 | .name = "usbtll_fck", | 1414 | .name = "usbtll_fck", |
1413 | .ops = &clkops_omap2_dflt_wait, | 1415 | .ops = &clkops_omap2_dflt_wait, |
1414 | .parent = &dpll5_m2_ck, | 1416 | .parent = &dpll5_m2_ck, |
1417 | .clkdm_name = "core_l4_clkdm", | ||
1415 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3), | 1418 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3), |
1416 | .enable_bit = OMAP3430ES2_EN_USBTLL_SHIFT, | 1419 | .enable_bit = OMAP3430ES2_EN_USBTLL_SHIFT, |
1417 | .recalc = &followparent_recalc, | 1420 | .recalc = &followparent_recalc, |
@@ -1617,6 +1620,7 @@ static struct clk fshostusb_fck = { | |||
1617 | .name = "fshostusb_fck", | 1620 | .name = "fshostusb_fck", |
1618 | .ops = &clkops_omap2_dflt_wait, | 1621 | .ops = &clkops_omap2_dflt_wait, |
1619 | .parent = &core_48m_fck, | 1622 | .parent = &core_48m_fck, |
1623 | .clkdm_name = "core_l4_clkdm", | ||
1620 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 1624 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
1621 | .enable_bit = OMAP3430ES1_EN_FSHOSTUSB_SHIFT, | 1625 | .enable_bit = OMAP3430ES1_EN_FSHOSTUSB_SHIFT, |
1622 | .recalc = &followparent_recalc, | 1626 | .recalc = &followparent_recalc, |
@@ -2043,6 +2047,7 @@ static struct clk omapctrl_ick = { | |||
2043 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 2047 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
2044 | .enable_bit = OMAP3430_EN_OMAPCTRL_SHIFT, | 2048 | .enable_bit = OMAP3430_EN_OMAPCTRL_SHIFT, |
2045 | .flags = ENABLE_ON_INIT, | 2049 | .flags = ENABLE_ON_INIT, |
2050 | .clkdm_name = "core_l4_clkdm", | ||
2046 | .recalc = &followparent_recalc, | 2051 | .recalc = &followparent_recalc, |
2047 | }; | 2052 | }; |
2048 | 2053 | ||
@@ -2094,6 +2099,7 @@ static struct clk usb_l4_ick = { | |||
2094 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), | 2099 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), |
2095 | .clksel_mask = OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK, | 2100 | .clksel_mask = OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK, |
2096 | .clksel = usb_l4_clksel, | 2101 | .clksel = usb_l4_clksel, |
2102 | .clkdm_name = "core_l4_clkdm", | ||
2097 | .recalc = &omap2_clksel_recalc, | 2103 | .recalc = &omap2_clksel_recalc, |
2098 | }; | 2104 | }; |
2099 | 2105 | ||