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authorRussell King <rmk@dyn-67.arm.linux.org.uk>2009-05-25 05:15:59 -0400
committerRussell King <rmk+kernel@arm.linux.org.uk>2009-05-25 05:20:21 -0400
commit56a459314a982bae75b9bce64bcca853d378ca7e (patch)
tree07d9121fb08229ebe2ac2f4420cec70434c7bbba /arch
parentfc05505b77f7900a1bb74fb3f3a4343dee4265a4 (diff)
parent5c651ffaee6f07aa1f5e6d0763845a2ee606b6bd (diff)
Merge branch 'iommu' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap-2.6.git into devel
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/include/asm/mach/map.h8
-rw-r--r--arch/arm/mach-omap2/Makefile5
-rw-r--r--arch/arm/mach-omap2/iommu2.c323
-rw-r--r--arch/arm/mach-omap2/omap3-iommu.c105
-rw-r--r--arch/arm/mm/ioremap.c6
-rw-r--r--arch/arm/mm/mmu.c1
-rw-r--r--arch/arm/plat-omap/Kconfig3
-rw-r--r--arch/arm/plat-omap/Makefile1
-rw-r--r--arch/arm/plat-omap/include/mach/iommu.h168
-rw-r--r--arch/arm/plat-omap/include/mach/iommu2.h96
-rw-r--r--arch/arm/plat-omap/include/mach/iovmm.h94
-rw-r--r--arch/arm/plat-omap/iommu.c996
-rw-r--r--arch/arm/plat-omap/iopgtable.h72
-rw-r--r--arch/arm/plat-omap/iovmm.c896
14 files changed, 2774 insertions, 0 deletions
diff --git a/arch/arm/include/asm/mach/map.h b/arch/arm/include/asm/mach/map.h
index 58cf91f38e6f..742c2aaeb020 100644
--- a/arch/arm/include/asm/mach/map.h
+++ b/arch/arm/include/asm/mach/map.h
@@ -30,6 +30,14 @@ struct map_desc {
30 30
31#ifdef CONFIG_MMU 31#ifdef CONFIG_MMU
32extern void iotable_init(struct map_desc *, int); 32extern void iotable_init(struct map_desc *, int);
33
34struct mem_type;
35extern const struct mem_type *get_mem_type(unsigned int type);
36/*
37 * external interface to remap single page with appropriate type
38 */
39extern int ioremap_page(unsigned long virt, unsigned long phys,
40 const struct mem_type *mtype);
33#else 41#else
34#define iotable_init(map,num) do { } while (0) 42#define iotable_init(map,num) do { } while (0)
35#endif 43#endif
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index c49d9bfa3abd..88629a7455a6 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -28,6 +28,11 @@ endif
28obj-$(CONFIG_ARCH_OMAP2) += clock24xx.o 28obj-$(CONFIG_ARCH_OMAP2) += clock24xx.o
29obj-$(CONFIG_ARCH_OMAP3) += clock34xx.o 29obj-$(CONFIG_ARCH_OMAP3) += clock34xx.o
30 30
31iommu-y += iommu2.o
32iommu-$(CONFIG_ARCH_OMAP3) += omap3-iommu.o
33
34obj-$(CONFIG_OMAP_IOMMU) += $(iommu-y)
35
31# Specific board support 36# Specific board support
32obj-$(CONFIG_MACH_OMAP_GENERIC) += board-generic.o 37obj-$(CONFIG_MACH_OMAP_GENERIC) += board-generic.o
33obj-$(CONFIG_MACH_OMAP_H4) += board-h4.o 38obj-$(CONFIG_MACH_OMAP_H4) += board-h4.o
diff --git a/arch/arm/mach-omap2/iommu2.c b/arch/arm/mach-omap2/iommu2.c
new file mode 100644
index 000000000000..015f22a53ead
--- /dev/null
+++ b/arch/arm/mach-omap2/iommu2.c
@@ -0,0 +1,323 @@
1/*
2 * omap iommu: omap2/3 architecture specific functions
3 *
4 * Copyright (C) 2008-2009 Nokia Corporation
5 *
6 * Written by Hiroshi DOYU <Hiroshi.DOYU@nokia.com>,
7 * Paul Mundt and Toshihiro Kobayashi
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#include <linux/err.h>
15#include <linux/device.h>
16#include <linux/jiffies.h>
17#include <linux/module.h>
18#include <linux/stringify.h>
19
20#include <mach/iommu.h>
21
22/*
23 * omap2 architecture specific register bit definitions
24 */
25#define IOMMU_ARCH_VERSION 0x00000011
26
27/* SYSCONF */
28#define MMU_SYS_IDLE_SHIFT 3
29#define MMU_SYS_IDLE_FORCE (0 << MMU_SYS_IDLE_SHIFT)
30#define MMU_SYS_IDLE_NONE (1 << MMU_SYS_IDLE_SHIFT)
31#define MMU_SYS_IDLE_SMART (2 << MMU_SYS_IDLE_SHIFT)
32#define MMU_SYS_IDLE_MASK (3 << MMU_SYS_IDLE_SHIFT)
33
34#define MMU_SYS_SOFTRESET (1 << 1)
35#define MMU_SYS_AUTOIDLE 1
36
37/* SYSSTATUS */
38#define MMU_SYS_RESETDONE 1
39
40/* IRQSTATUS & IRQENABLE */
41#define MMU_IRQ_MULTIHITFAULT (1 << 4)
42#define MMU_IRQ_TABLEWALKFAULT (1 << 3)
43#define MMU_IRQ_EMUMISS (1 << 2)
44#define MMU_IRQ_TRANSLATIONFAULT (1 << 1)
45#define MMU_IRQ_TLBMISS (1 << 0)
46#define MMU_IRQ_MASK \
47 (MMU_IRQ_MULTIHITFAULT | MMU_IRQ_TABLEWALKFAULT | MMU_IRQ_EMUMISS | \
48 MMU_IRQ_TRANSLATIONFAULT)
49
50/* MMU_CNTL */
51#define MMU_CNTL_SHIFT 1
52#define MMU_CNTL_MASK (7 << MMU_CNTL_SHIFT)
53#define MMU_CNTL_EML_TLB (1 << 3)
54#define MMU_CNTL_TWL_EN (1 << 2)
55#define MMU_CNTL_MMU_EN (1 << 1)
56
57#define get_cam_va_mask(pgsz) \
58 (((pgsz) == MMU_CAM_PGSZ_16M) ? 0xff000000 : \
59 ((pgsz) == MMU_CAM_PGSZ_1M) ? 0xfff00000 : \
60 ((pgsz) == MMU_CAM_PGSZ_64K) ? 0xffff0000 : \
61 ((pgsz) == MMU_CAM_PGSZ_4K) ? 0xfffff000 : 0)
62
63static int omap2_iommu_enable(struct iommu *obj)
64{
65 u32 l, pa;
66 unsigned long timeout;
67
68 if (!obj->iopgd || !IS_ALIGNED((u32)obj->iopgd, SZ_16K))
69 return -EINVAL;
70
71 pa = virt_to_phys(obj->iopgd);
72 if (!IS_ALIGNED(pa, SZ_16K))
73 return -EINVAL;
74
75 iommu_write_reg(obj, MMU_SYS_SOFTRESET, MMU_SYSCONFIG);
76
77 timeout = jiffies + msecs_to_jiffies(20);
78 do {
79 l = iommu_read_reg(obj, MMU_SYSSTATUS);
80 if (l & MMU_SYS_RESETDONE)
81 break;
82 } while (time_after(jiffies, timeout));
83
84 if (!(l & MMU_SYS_RESETDONE)) {
85 dev_err(obj->dev, "can't take mmu out of reset\n");
86 return -ENODEV;
87 }
88
89 l = iommu_read_reg(obj, MMU_REVISION);
90 dev_info(obj->dev, "%s: version %d.%d\n", obj->name,
91 (l >> 4) & 0xf, l & 0xf);
92
93 l = iommu_read_reg(obj, MMU_SYSCONFIG);
94 l &= ~MMU_SYS_IDLE_MASK;
95 l |= (MMU_SYS_IDLE_SMART | MMU_SYS_AUTOIDLE);
96 iommu_write_reg(obj, l, MMU_SYSCONFIG);
97
98 iommu_write_reg(obj, MMU_IRQ_MASK, MMU_IRQENABLE);
99 iommu_write_reg(obj, pa, MMU_TTB);
100
101 l = iommu_read_reg(obj, MMU_CNTL);
102 l &= ~MMU_CNTL_MASK;
103 l |= (MMU_CNTL_MMU_EN | MMU_CNTL_TWL_EN);
104 iommu_write_reg(obj, l, MMU_CNTL);
105
106 return 0;
107}
108
109static void omap2_iommu_disable(struct iommu *obj)
110{
111 u32 l = iommu_read_reg(obj, MMU_CNTL);
112
113 l &= ~MMU_CNTL_MASK;
114 iommu_write_reg(obj, l, MMU_CNTL);
115 iommu_write_reg(obj, MMU_SYS_IDLE_FORCE, MMU_SYSCONFIG);
116
117 dev_dbg(obj->dev, "%s is shutting down\n", obj->name);
118}
119
120static u32 omap2_iommu_fault_isr(struct iommu *obj, u32 *ra)
121{
122 int i;
123 u32 stat, da;
124 const char *err_msg[] = {
125 "tlb miss",
126 "translation fault",
127 "emulation miss",
128 "table walk fault",
129 "multi hit fault",
130 };
131
132 stat = iommu_read_reg(obj, MMU_IRQSTATUS);
133 stat &= MMU_IRQ_MASK;
134 if (!stat)
135 return 0;
136
137 da = iommu_read_reg(obj, MMU_FAULT_AD);
138 *ra = da;
139
140 dev_err(obj->dev, "%s:\tda:%08x ", __func__, da);
141
142 for (i = 0; i < ARRAY_SIZE(err_msg); i++) {
143 if (stat & (1 << i))
144 printk("%s ", err_msg[i]);
145 }
146 printk("\n");
147
148 iommu_write_reg(obj, stat, MMU_IRQSTATUS);
149 return stat;
150}
151
152static void omap2_tlb_read_cr(struct iommu *obj, struct cr_regs *cr)
153{
154 cr->cam = iommu_read_reg(obj, MMU_READ_CAM);
155 cr->ram = iommu_read_reg(obj, MMU_READ_RAM);
156}
157
158static void omap2_tlb_load_cr(struct iommu *obj, struct cr_regs *cr)
159{
160 iommu_write_reg(obj, cr->cam | MMU_CAM_V, MMU_CAM);
161 iommu_write_reg(obj, cr->ram, MMU_RAM);
162}
163
164static u32 omap2_cr_to_virt(struct cr_regs *cr)
165{
166 u32 page_size = cr->cam & MMU_CAM_PGSZ_MASK;
167 u32 mask = get_cam_va_mask(cr->cam & page_size);
168
169 return cr->cam & mask;
170}
171
172static struct cr_regs *omap2_alloc_cr(struct iommu *obj, struct iotlb_entry *e)
173{
174 struct cr_regs *cr;
175
176 if (e->da & ~(get_cam_va_mask(e->pgsz))) {
177 dev_err(obj->dev, "%s:\twrong alignment: %08x\n", __func__,
178 e->da);
179 return ERR_PTR(-EINVAL);
180 }
181
182 cr = kmalloc(sizeof(*cr), GFP_KERNEL);
183 if (!cr)
184 return ERR_PTR(-ENOMEM);
185
186 cr->cam = (e->da & MMU_CAM_VATAG_MASK) | e->prsvd | e->pgsz;
187 cr->ram = e->pa | e->endian | e->elsz | e->mixed;
188
189 return cr;
190}
191
192static inline int omap2_cr_valid(struct cr_regs *cr)
193{
194 return cr->cam & MMU_CAM_V;
195}
196
197static u32 omap2_get_pte_attr(struct iotlb_entry *e)
198{
199 u32 attr;
200
201 attr = e->mixed << 5;
202 attr |= e->endian;
203 attr |= e->elsz >> 3;
204 attr <<= ((e->pgsz & MMU_CAM_PGSZ_4K) ? 0 : 6);
205
206 return attr;
207}
208
209static ssize_t omap2_dump_cr(struct iommu *obj, struct cr_regs *cr, char *buf)
210{
211 char *p = buf;
212
213 /* FIXME: Need more detail analysis of cam/ram */
214 p += sprintf(p, "%08x %08x\n", cr->cam, cr->ram);
215
216 return p - buf;
217}
218
219#define pr_reg(name) \
220 p += sprintf(p, "%20s: %08x\n", \
221 __stringify(name), iommu_read_reg(obj, MMU_##name));
222
223static ssize_t omap2_iommu_dump_ctx(struct iommu *obj, char *buf)
224{
225 char *p = buf;
226
227 pr_reg(REVISION);
228 pr_reg(SYSCONFIG);
229 pr_reg(SYSSTATUS);
230 pr_reg(IRQSTATUS);
231 pr_reg(IRQENABLE);
232 pr_reg(WALKING_ST);
233 pr_reg(CNTL);
234 pr_reg(FAULT_AD);
235 pr_reg(TTB);
236 pr_reg(LOCK);
237 pr_reg(LD_TLB);
238 pr_reg(CAM);
239 pr_reg(RAM);
240 pr_reg(GFLUSH);
241 pr_reg(FLUSH_ENTRY);
242 pr_reg(READ_CAM);
243 pr_reg(READ_RAM);
244 pr_reg(EMU_FAULT_AD);
245
246 return p - buf;
247}
248
249static void omap2_iommu_save_ctx(struct iommu *obj)
250{
251 int i;
252 u32 *p = obj->ctx;
253
254 for (i = 0; i < (MMU_REG_SIZE / sizeof(u32)); i++) {
255 p[i] = iommu_read_reg(obj, i * sizeof(u32));
256 dev_dbg(obj->dev, "%s\t[%02d] %08x\n", __func__, i, p[i]);
257 }
258
259 BUG_ON(p[0] != IOMMU_ARCH_VERSION);
260}
261
262static void omap2_iommu_restore_ctx(struct iommu *obj)
263{
264 int i;
265 u32 *p = obj->ctx;
266
267 for (i = 0; i < (MMU_REG_SIZE / sizeof(u32)); i++) {
268 iommu_write_reg(obj, p[i], i * sizeof(u32));
269 dev_dbg(obj->dev, "%s\t[%02d] %08x\n", __func__, i, p[i]);
270 }
271
272 BUG_ON(p[0] != IOMMU_ARCH_VERSION);
273}
274
275static void omap2_cr_to_e(struct cr_regs *cr, struct iotlb_entry *e)
276{
277 e->da = cr->cam & MMU_CAM_VATAG_MASK;
278 e->pa = cr->ram & MMU_RAM_PADDR_MASK;
279 e->valid = cr->cam & MMU_CAM_V;
280 e->pgsz = cr->cam & MMU_CAM_PGSZ_MASK;
281 e->endian = cr->ram & MMU_RAM_ENDIAN_MASK;
282 e->elsz = cr->ram & MMU_RAM_ELSZ_MASK;
283 e->mixed = cr->ram & MMU_RAM_MIXED;
284}
285
286static const struct iommu_functions omap2_iommu_ops = {
287 .version = IOMMU_ARCH_VERSION,
288
289 .enable = omap2_iommu_enable,
290 .disable = omap2_iommu_disable,
291 .fault_isr = omap2_iommu_fault_isr,
292
293 .tlb_read_cr = omap2_tlb_read_cr,
294 .tlb_load_cr = omap2_tlb_load_cr,
295
296 .cr_to_e = omap2_cr_to_e,
297 .cr_to_virt = omap2_cr_to_virt,
298 .alloc_cr = omap2_alloc_cr,
299 .cr_valid = omap2_cr_valid,
300 .dump_cr = omap2_dump_cr,
301
302 .get_pte_attr = omap2_get_pte_attr,
303
304 .save_ctx = omap2_iommu_save_ctx,
305 .restore_ctx = omap2_iommu_restore_ctx,
306 .dump_ctx = omap2_iommu_dump_ctx,
307};
308
309static int __init omap2_iommu_init(void)
310{
311 return install_iommu_arch(&omap2_iommu_ops);
312}
313module_init(omap2_iommu_init);
314
315static void __exit omap2_iommu_exit(void)
316{
317 uninstall_iommu_arch(&omap2_iommu_ops);
318}
319module_exit(omap2_iommu_exit);
320
321MODULE_AUTHOR("Hiroshi DOYU, Paul Mundt and Toshihiro Kobayashi");
322MODULE_DESCRIPTION("omap iommu: omap2/3 architecture specific functions");
323MODULE_LICENSE("GPL v2");
diff --git a/arch/arm/mach-omap2/omap3-iommu.c b/arch/arm/mach-omap2/omap3-iommu.c
new file mode 100644
index 000000000000..194189c746c2
--- /dev/null
+++ b/arch/arm/mach-omap2/omap3-iommu.c
@@ -0,0 +1,105 @@
1/*
2 * omap iommu: omap3 device registration
3 *
4 * Copyright (C) 2008-2009 Nokia Corporation
5 *
6 * Written by Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#include <linux/platform_device.h>
14
15#include <mach/iommu.h>
16
17#define OMAP3_MMU1_BASE 0x480bd400
18#define OMAP3_MMU2_BASE 0x5d000000
19#define OMAP3_MMU1_IRQ 24
20#define OMAP3_MMU2_IRQ 28
21
22
23static unsigned long iommu_base[] __initdata = {
24 OMAP3_MMU1_BASE,
25 OMAP3_MMU2_BASE,
26};
27
28static int iommu_irq[] __initdata = {
29 OMAP3_MMU1_IRQ,
30 OMAP3_MMU2_IRQ,
31};
32
33static const struct iommu_platform_data omap3_iommu_pdata[] __initconst = {
34 {
35 .name = "isp",
36 .nr_tlb_entries = 8,
37 .clk_name = "cam_ick",
38 },
39#if defined(CONFIG_MPU_BRIDGE_IOMMU)
40 {
41 .name = "iva2",
42 .nr_tlb_entries = 32,
43 .clk_name = "iva2_ck",
44 },
45#endif
46};
47#define NR_IOMMU_DEVICES ARRAY_SIZE(omap3_iommu_pdata)
48
49static struct platform_device *omap3_iommu_pdev[NR_IOMMU_DEVICES];
50
51static int __init omap3_iommu_init(void)
52{
53 int i, err;
54
55 for (i = 0; i < NR_IOMMU_DEVICES; i++) {
56 struct platform_device *pdev;
57 struct resource res[2];
58
59 pdev = platform_device_alloc("omap-iommu", i);
60 if (!pdev) {
61 err = -ENOMEM;
62 goto err_out;
63 }
64
65 memset(res, 0, sizeof(res));
66 res[0].start = iommu_base[i];
67 res[0].end = iommu_base[i] + MMU_REG_SIZE - 1;
68 res[0].flags = IORESOURCE_MEM;
69 res[1].start = res[1].end = iommu_irq[i];
70 res[1].flags = IORESOURCE_IRQ;
71
72 err = platform_device_add_resources(pdev, res,
73 ARRAY_SIZE(res));
74 if (err)
75 goto err_out;
76 err = platform_device_add_data(pdev, &omap3_iommu_pdata[i],
77 sizeof(omap3_iommu_pdata[0]));
78 if (err)
79 goto err_out;
80 err = platform_device_add(pdev);
81 if (err)
82 goto err_out;
83 omap3_iommu_pdev[i] = pdev;
84 }
85 return 0;
86
87err_out:
88 while (i--)
89 platform_device_put(omap3_iommu_pdev[i]);
90 return err;
91}
92module_init(omap3_iommu_init);
93
94static void __exit omap3_iommu_exit(void)
95{
96 int i;
97
98 for (i = 0; i < NR_IOMMU_DEVICES; i++)
99 platform_device_unregister(omap3_iommu_pdev[i]);
100}
101module_exit(omap3_iommu_exit);
102
103MODULE_AUTHOR("Hiroshi DOYU");
104MODULE_DESCRIPTION("omap iommu: omap3 device registration");
105MODULE_LICENSE("GPL v2");
diff --git a/arch/arm/mm/ioremap.c b/arch/arm/mm/ioremap.c
index 9f88dd3be601..0ab75c60f7cf 100644
--- a/arch/arm/mm/ioremap.c
+++ b/arch/arm/mm/ioremap.c
@@ -110,6 +110,12 @@ static int remap_area_pages(unsigned long start, unsigned long pfn,
110 return err; 110 return err;
111} 111}
112 112
113int ioremap_page(unsigned long virt, unsigned long phys,
114 const struct mem_type *mtype)
115{
116 return remap_area_pages(virt, __phys_to_pfn(phys), PAGE_SIZE, mtype);
117}
118EXPORT_SYMBOL(ioremap_page);
113 119
114void __check_kvm_seq(struct mm_struct *mm) 120void __check_kvm_seq(struct mm_struct *mm)
115{ 121{
diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
index e6344ece00ce..70974d75a075 100644
--- a/arch/arm/mm/mmu.c
+++ b/arch/arm/mm/mmu.c
@@ -255,6 +255,7 @@ const struct mem_type *get_mem_type(unsigned int type)
255{ 255{
256 return type < ARRAY_SIZE(mem_types) ? &mem_types[type] : NULL; 256 return type < ARRAY_SIZE(mem_types) ? &mem_types[type] : NULL;
257} 257}
258EXPORT_SYMBOL(get_mem_type);
258 259
259/* 260/*
260 * Adjust the PMD section entries according to the CPU in use. 261 * Adjust the PMD section entries according to the CPU in use.
diff --git a/arch/arm/plat-omap/Kconfig b/arch/arm/plat-omap/Kconfig
index 9dd68fafb374..d483b2592ec8 100644
--- a/arch/arm/plat-omap/Kconfig
+++ b/arch/arm/plat-omap/Kconfig
@@ -115,6 +115,9 @@ config OMAP_MBOX_FWK
115 Say Y here if you want to use OMAP Mailbox framework support for 115 Say Y here if you want to use OMAP Mailbox framework support for
116 DSP, IVA1.0 and IVA2 in OMAP1/2/3. 116 DSP, IVA1.0 and IVA2 in OMAP1/2/3.
117 117
118config OMAP_IOMMU
119 tristate
120
118choice 121choice
119 prompt "System timer" 122 prompt "System timer"
120 default OMAP_MPU_TIMER 123 default OMAP_MPU_TIMER
diff --git a/arch/arm/plat-omap/Makefile b/arch/arm/plat-omap/Makefile
index 04a100cfb8e5..a83279523958 100644
--- a/arch/arm/plat-omap/Makefile
+++ b/arch/arm/plat-omap/Makefile
@@ -13,6 +13,7 @@ obj- :=
13obj-$(CONFIG_ARCH_OMAP16XX) += ocpi.o 13obj-$(CONFIG_ARCH_OMAP16XX) += ocpi.o
14 14
15obj-$(CONFIG_OMAP_MCBSP) += mcbsp.o 15obj-$(CONFIG_OMAP_MCBSP) += mcbsp.o
16obj-$(CONFIG_OMAP_IOMMU) += iommu.o iovmm.o
16 17
17obj-$(CONFIG_CPU_FREQ) += cpu-omap.o 18obj-$(CONFIG_CPU_FREQ) += cpu-omap.o
18obj-$(CONFIG_OMAP_DM_TIMER) += dmtimer.o 19obj-$(CONFIG_OMAP_DM_TIMER) += dmtimer.o
diff --git a/arch/arm/plat-omap/include/mach/iommu.h b/arch/arm/plat-omap/include/mach/iommu.h
new file mode 100644
index 000000000000..769b00b4c34a
--- /dev/null
+++ b/arch/arm/plat-omap/include/mach/iommu.h
@@ -0,0 +1,168 @@
1/*
2 * omap iommu: main structures
3 *
4 * Copyright (C) 2008-2009 Nokia Corporation
5 *
6 * Written by Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#ifndef __MACH_IOMMU_H
14#define __MACH_IOMMU_H
15
16struct iotlb_entry {
17 u32 da;
18 u32 pa;
19 u32 pgsz, prsvd, valid;
20 union {
21 u16 ap;
22 struct {
23 u32 endian, elsz, mixed;
24 };
25 };
26};
27
28struct iommu {
29 const char *name;
30 struct module *owner;
31 struct clk *clk;
32 void __iomem *regbase;
33 struct device *dev;
34
35 unsigned int refcount;
36 struct mutex iommu_lock; /* global for this whole object */
37
38 /*
39 * We don't change iopgd for a situation like pgd for a task,
40 * but share it globally for each iommu.
41 */
42 u32 *iopgd;
43 spinlock_t page_table_lock; /* protect iopgd */
44
45 int nr_tlb_entries;
46
47 struct list_head mmap;
48 struct mutex mmap_lock; /* protect mmap */
49
50 int (*isr)(struct iommu *obj);
51
52 void *ctx; /* iommu context: registres saved area */
53};
54
55struct cr_regs {
56 union {
57 struct {
58 u16 cam_l;
59 u16 cam_h;
60 };
61 u32 cam;
62 };
63 union {
64 struct {
65 u16 ram_l;
66 u16 ram_h;
67 };
68 u32 ram;
69 };
70};
71
72struct iotlb_lock {
73 short base;
74 short vict;
75};
76
77/* architecture specific functions */
78struct iommu_functions {
79 unsigned long version;
80
81 int (*enable)(struct iommu *obj);
82 void (*disable)(struct iommu *obj);
83 u32 (*fault_isr)(struct iommu *obj, u32 *ra);
84
85 void (*tlb_read_cr)(struct iommu *obj, struct cr_regs *cr);
86 void (*tlb_load_cr)(struct iommu *obj, struct cr_regs *cr);
87
88 struct cr_regs *(*alloc_cr)(struct iommu *obj, struct iotlb_entry *e);
89 int (*cr_valid)(struct cr_regs *cr);
90 u32 (*cr_to_virt)(struct cr_regs *cr);
91 void (*cr_to_e)(struct cr_regs *cr, struct iotlb_entry *e);
92 ssize_t (*dump_cr)(struct iommu *obj, struct cr_regs *cr, char *buf);
93
94 u32 (*get_pte_attr)(struct iotlb_entry *e);
95
96 void (*save_ctx)(struct iommu *obj);
97 void (*restore_ctx)(struct iommu *obj);
98 ssize_t (*dump_ctx)(struct iommu *obj, char *buf);
99};
100
101struct iommu_platform_data {
102 const char *name;
103 const char *clk_name;
104 const int nr_tlb_entries;
105};
106
107#if defined(CONFIG_ARCH_OMAP1)
108#error "iommu for this processor not implemented yet"
109#else
110#include <mach/iommu2.h>
111#endif
112
113/*
114 * utilities for super page(16MB, 1MB, 64KB and 4KB)
115 */
116
117#define iopgsz_max(bytes) \
118 (((bytes) >= SZ_16M) ? SZ_16M : \
119 ((bytes) >= SZ_1M) ? SZ_1M : \
120 ((bytes) >= SZ_64K) ? SZ_64K : \
121 ((bytes) >= SZ_4K) ? SZ_4K : 0)
122
123#define bytes_to_iopgsz(bytes) \
124 (((bytes) == SZ_16M) ? MMU_CAM_PGSZ_16M : \
125 ((bytes) == SZ_1M) ? MMU_CAM_PGSZ_1M : \
126 ((bytes) == SZ_64K) ? MMU_CAM_PGSZ_64K : \
127 ((bytes) == SZ_4K) ? MMU_CAM_PGSZ_4K : -1)
128
129#define iopgsz_to_bytes(iopgsz) \
130 (((iopgsz) == MMU_CAM_PGSZ_16M) ? SZ_16M : \
131 ((iopgsz) == MMU_CAM_PGSZ_1M) ? SZ_1M : \
132 ((iopgsz) == MMU_CAM_PGSZ_64K) ? SZ_64K : \
133 ((iopgsz) == MMU_CAM_PGSZ_4K) ? SZ_4K : 0)
134
135#define iopgsz_ok(bytes) (bytes_to_iopgsz(bytes) >= 0)
136
137/*
138 * global functions
139 */
140extern u32 iommu_arch_version(void);
141
142extern void iotlb_cr_to_e(struct cr_regs *cr, struct iotlb_entry *e);
143extern u32 iotlb_cr_to_virt(struct cr_regs *cr);
144
145extern int load_iotlb_entry(struct iommu *obj, struct iotlb_entry *e);
146extern void flush_iotlb_page(struct iommu *obj, u32 da);
147extern void flush_iotlb_range(struct iommu *obj, u32 start, u32 end);
148extern void flush_iotlb_all(struct iommu *obj);
149
150extern int iopgtable_store_entry(struct iommu *obj, struct iotlb_entry *e);
151extern size_t iopgtable_clear_entry(struct iommu *obj, u32 iova);
152
153extern struct iommu *iommu_get(const char *name);
154extern void iommu_put(struct iommu *obj);
155
156extern void iommu_save_ctx(struct iommu *obj);
157extern void iommu_restore_ctx(struct iommu *obj);
158
159extern int install_iommu_arch(const struct iommu_functions *ops);
160extern void uninstall_iommu_arch(const struct iommu_functions *ops);
161
162extern int foreach_iommu_device(void *data,
163 int (*fn)(struct device *, void *));
164
165extern ssize_t iommu_dump_ctx(struct iommu *obj, char *buf);
166extern size_t dump_tlb_entries(struct iommu *obj, char *buf);
167
168#endif /* __MACH_IOMMU_H */
diff --git a/arch/arm/plat-omap/include/mach/iommu2.h b/arch/arm/plat-omap/include/mach/iommu2.h
new file mode 100644
index 000000000000..10ad05f410e9
--- /dev/null
+++ b/arch/arm/plat-omap/include/mach/iommu2.h
@@ -0,0 +1,96 @@
1/*
2 * omap iommu: omap2 architecture specific definitions
3 *
4 * Copyright (C) 2008-2009 Nokia Corporation
5 *
6 * Written by Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#ifndef __MACH_IOMMU2_H
14#define __MACH_IOMMU2_H
15
16#include <linux/io.h>
17
18/*
19 * MMU Register offsets
20 */
21#define MMU_REVISION 0x00
22#define MMU_SYSCONFIG 0x10
23#define MMU_SYSSTATUS 0x14
24#define MMU_IRQSTATUS 0x18
25#define MMU_IRQENABLE 0x1c
26#define MMU_WALKING_ST 0x40
27#define MMU_CNTL 0x44
28#define MMU_FAULT_AD 0x48
29#define MMU_TTB 0x4c
30#define MMU_LOCK 0x50
31#define MMU_LD_TLB 0x54
32#define MMU_CAM 0x58
33#define MMU_RAM 0x5c
34#define MMU_GFLUSH 0x60
35#define MMU_FLUSH_ENTRY 0x64
36#define MMU_READ_CAM 0x68
37#define MMU_READ_RAM 0x6c
38#define MMU_EMU_FAULT_AD 0x70
39
40#define MMU_REG_SIZE 256
41
42/*
43 * MMU Register bit definitions
44 */
45#define MMU_LOCK_BASE_SHIFT 10
46#define MMU_LOCK_BASE_MASK (0x1f << MMU_LOCK_BASE_SHIFT)
47#define MMU_LOCK_BASE(x) \
48 ((x & MMU_LOCK_BASE_MASK) >> MMU_LOCK_BASE_SHIFT)
49
50#define MMU_LOCK_VICT_SHIFT 4
51#define MMU_LOCK_VICT_MASK (0x1f << MMU_LOCK_VICT_SHIFT)
52#define MMU_LOCK_VICT(x) \
53 ((x & MMU_LOCK_VICT_MASK) >> MMU_LOCK_VICT_SHIFT)
54
55#define MMU_CAM_VATAG_SHIFT 12
56#define MMU_CAM_VATAG_MASK \
57 ((~0UL >> MMU_CAM_VATAG_SHIFT) << MMU_CAM_VATAG_SHIFT)
58#define MMU_CAM_P (1 << 3)
59#define MMU_CAM_V (1 << 2)
60#define MMU_CAM_PGSZ_MASK 3
61#define MMU_CAM_PGSZ_1M (0 << 0)
62#define MMU_CAM_PGSZ_64K (1 << 0)
63#define MMU_CAM_PGSZ_4K (2 << 0)
64#define MMU_CAM_PGSZ_16M (3 << 0)
65
66#define MMU_RAM_PADDR_SHIFT 12
67#define MMU_RAM_PADDR_MASK \
68 ((~0UL >> MMU_RAM_PADDR_SHIFT) << MMU_RAM_PADDR_SHIFT)
69#define MMU_RAM_ENDIAN_SHIFT 9
70#define MMU_RAM_ENDIAN_MASK (1 << MMU_RAM_ENDIAN_SHIFT)
71#define MMU_RAM_ENDIAN_BIG (1 << MMU_RAM_ENDIAN_SHIFT)
72#define MMU_RAM_ENDIAN_LITTLE (0 << MMU_RAM_ENDIAN_SHIFT)
73#define MMU_RAM_ELSZ_SHIFT 7
74#define MMU_RAM_ELSZ_MASK (3 << MMU_RAM_ELSZ_SHIFT)
75#define MMU_RAM_ELSZ_8 (0 << MMU_RAM_ELSZ_SHIFT)
76#define MMU_RAM_ELSZ_16 (1 << MMU_RAM_ELSZ_SHIFT)
77#define MMU_RAM_ELSZ_32 (2 << MMU_RAM_ELSZ_SHIFT)
78#define MMU_RAM_ELSZ_NONE (3 << MMU_RAM_ELSZ_SHIFT)
79#define MMU_RAM_MIXED_SHIFT 6
80#define MMU_RAM_MIXED_MASK (1 << MMU_RAM_MIXED_SHIFT)
81#define MMU_RAM_MIXED MMU_RAM_MIXED_MASK
82
83/*
84 * register accessors
85 */
86static inline u32 iommu_read_reg(struct iommu *obj, size_t offs)
87{
88 return __raw_readl(obj->regbase + offs);
89}
90
91static inline void iommu_write_reg(struct iommu *obj, u32 val, size_t offs)
92{
93 __raw_writel(val, obj->regbase + offs);
94}
95
96#endif /* __MACH_IOMMU2_H */
diff --git a/arch/arm/plat-omap/include/mach/iovmm.h b/arch/arm/plat-omap/include/mach/iovmm.h
new file mode 100644
index 000000000000..bdc7ce5d7a4a
--- /dev/null
+++ b/arch/arm/plat-omap/include/mach/iovmm.h
@@ -0,0 +1,94 @@
1/*
2 * omap iommu: simple virtual address space management
3 *
4 * Copyright (C) 2008-2009 Nokia Corporation
5 *
6 * Written by Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#ifndef __IOMMU_MMAP_H
14#define __IOMMU_MMAP_H
15
16struct iovm_struct {
17 struct iommu *iommu; /* iommu object which this belongs to */
18 u32 da_start; /* area definition */
19 u32 da_end;
20 u32 flags; /* IOVMF_: see below */
21 struct list_head list; /* linked in ascending order */
22 const struct sg_table *sgt; /* keep 'page' <-> 'da' mapping */
23 void *va; /* mpu side mapped address */
24};
25
26/*
27 * IOVMF_FLAGS: attribute for iommu virtual memory area(iovma)
28 *
29 * lower 16 bit is used for h/w and upper 16 bit is for s/w.
30 */
31#define IOVMF_SW_SHIFT 16
32#define IOVMF_HW_SIZE (1 << IOVMF_SW_SHIFT)
33#define IOVMF_HW_MASK (IOVMF_HW_SIZE - 1)
34#define IOVMF_SW_MASK (~IOVMF_HW_MASK)UL
35
36/*
37 * iovma: h/w flags derived from cam and ram attribute
38 */
39#define IOVMF_CAM_MASK (~((1 << 10) - 1))
40#define IOVMF_RAM_MASK (~IOVMF_CAM_MASK)
41
42#define IOVMF_PGSZ_MASK (3 << 0)
43#define IOVMF_PGSZ_1M MMU_CAM_PGSZ_1M
44#define IOVMF_PGSZ_64K MMU_CAM_PGSZ_64K
45#define IOVMF_PGSZ_4K MMU_CAM_PGSZ_4K
46#define IOVMF_PGSZ_16M MMU_CAM_PGSZ_16M
47
48#define IOVMF_ENDIAN_MASK (1 << 9)
49#define IOVMF_ENDIAN_BIG MMU_RAM_ENDIAN_BIG
50#define IOVMF_ENDIAN_LITTLE MMU_RAM_ENDIAN_LITTLE
51
52#define IOVMF_ELSZ_MASK (3 << 7)
53#define IOVMF_ELSZ_8 MMU_RAM_ELSZ_8
54#define IOVMF_ELSZ_16 MMU_RAM_ELSZ_16
55#define IOVMF_ELSZ_32 MMU_RAM_ELSZ_32
56#define IOVMF_ELSZ_NONE MMU_RAM_ELSZ_NONE
57
58#define IOVMF_MIXED_MASK (1 << 6)
59#define IOVMF_MIXED MMU_RAM_MIXED
60
61/*
62 * iovma: s/w flags, used for mapping and umapping internally.
63 */
64#define IOVMF_MMIO (1 << IOVMF_SW_SHIFT)
65#define IOVMF_ALLOC (2 << IOVMF_SW_SHIFT)
66#define IOVMF_ALLOC_MASK (3 << IOVMF_SW_SHIFT)
67
68/* "superpages" is supported just with physically linear pages */
69#define IOVMF_DISCONT (1 << (2 + IOVMF_SW_SHIFT))
70#define IOVMF_LINEAR (2 << (2 + IOVMF_SW_SHIFT))
71#define IOVMF_LINEAR_MASK (3 << (2 + IOVMF_SW_SHIFT))
72
73#define IOVMF_DA_FIXED (1 << (4 + IOVMF_SW_SHIFT))
74#define IOVMF_DA_ANON (2 << (4 + IOVMF_SW_SHIFT))
75#define IOVMF_DA_MASK (3 << (4 + IOVMF_SW_SHIFT))
76
77
78extern struct iovm_struct *find_iovm_area(struct iommu *obj, u32 da);
79extern u32 iommu_vmap(struct iommu *obj, u32 da,
80 const struct sg_table *sgt, u32 flags);
81extern struct sg_table *iommu_vunmap(struct iommu *obj, u32 da);
82extern u32 iommu_vmalloc(struct iommu *obj, u32 da, size_t bytes,
83 u32 flags);
84extern void iommu_vfree(struct iommu *obj, const u32 da);
85extern u32 iommu_kmap(struct iommu *obj, u32 da, u32 pa, size_t bytes,
86 u32 flags);
87extern void iommu_kunmap(struct iommu *obj, u32 da);
88extern u32 iommu_kmalloc(struct iommu *obj, u32 da, size_t bytes,
89 u32 flags);
90extern void iommu_kfree(struct iommu *obj, u32 da);
91
92extern void *da_to_va(struct iommu *obj, u32 da);
93
94#endif /* __IOMMU_MMAP_H */
diff --git a/arch/arm/plat-omap/iommu.c b/arch/arm/plat-omap/iommu.c
new file mode 100644
index 000000000000..4cf449fa2cb5
--- /dev/null
+++ b/arch/arm/plat-omap/iommu.c
@@ -0,0 +1,996 @@
1/*
2 * omap iommu: tlb and pagetable primitives
3 *
4 * Copyright (C) 2008-2009 Nokia Corporation
5 *
6 * Written by Hiroshi DOYU <Hiroshi.DOYU@nokia.com>,
7 * Paul Mundt and Toshihiro Kobayashi
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#include <linux/err.h>
15#include <linux/module.h>
16#include <linux/interrupt.h>
17#include <linux/ioport.h>
18#include <linux/clk.h>
19#include <linux/platform_device.h>
20
21#include <asm/cacheflush.h>
22
23#include <mach/iommu.h>
24
25#include "iopgtable.h"
26
27/* accommodate the difference between omap1 and omap2/3 */
28static const struct iommu_functions *arch_iommu;
29
30static struct platform_driver omap_iommu_driver;
31static struct kmem_cache *iopte_cachep;
32
33/**
34 * install_iommu_arch - Install archtecure specific iommu functions
35 * @ops: a pointer to architecture specific iommu functions
36 *
37 * There are several kind of iommu algorithm(tlb, pagetable) among
38 * omap series. This interface installs such an iommu algorighm.
39 **/
40int install_iommu_arch(const struct iommu_functions *ops)
41{
42 if (arch_iommu)
43 return -EBUSY;
44
45 arch_iommu = ops;
46 return 0;
47}
48EXPORT_SYMBOL_GPL(install_iommu_arch);
49
50/**
51 * uninstall_iommu_arch - Uninstall archtecure specific iommu functions
52 * @ops: a pointer to architecture specific iommu functions
53 *
54 * This interface uninstalls the iommu algorighm installed previously.
55 **/
56void uninstall_iommu_arch(const struct iommu_functions *ops)
57{
58 if (arch_iommu != ops)
59 pr_err("%s: not your arch\n", __func__);
60
61 arch_iommu = NULL;
62}
63EXPORT_SYMBOL_GPL(uninstall_iommu_arch);
64
65/**
66 * iommu_save_ctx - Save registers for pm off-mode support
67 * @obj: target iommu
68 **/
69void iommu_save_ctx(struct iommu *obj)
70{
71 arch_iommu->save_ctx(obj);
72}
73EXPORT_SYMBOL_GPL(iommu_save_ctx);
74
75/**
76 * iommu_restore_ctx - Restore registers for pm off-mode support
77 * @obj: target iommu
78 **/
79void iommu_restore_ctx(struct iommu *obj)
80{
81 arch_iommu->restore_ctx(obj);
82}
83EXPORT_SYMBOL_GPL(iommu_restore_ctx);
84
85/**
86 * iommu_arch_version - Return running iommu arch version
87 **/
88u32 iommu_arch_version(void)
89{
90 return arch_iommu->version;
91}
92EXPORT_SYMBOL_GPL(iommu_arch_version);
93
94static int iommu_enable(struct iommu *obj)
95{
96 int err;
97
98 if (!obj)
99 return -EINVAL;
100
101 clk_enable(obj->clk);
102
103 err = arch_iommu->enable(obj);
104
105 clk_disable(obj->clk);
106 return err;
107}
108
109static void iommu_disable(struct iommu *obj)
110{
111 if (!obj)
112 return;
113
114 clk_enable(obj->clk);
115
116 arch_iommu->disable(obj);
117
118 clk_disable(obj->clk);
119}
120
121/*
122 * TLB operations
123 */
124void iotlb_cr_to_e(struct cr_regs *cr, struct iotlb_entry *e)
125{
126 BUG_ON(!cr || !e);
127
128 arch_iommu->cr_to_e(cr, e);
129}
130EXPORT_SYMBOL_GPL(iotlb_cr_to_e);
131
132static inline int iotlb_cr_valid(struct cr_regs *cr)
133{
134 if (!cr)
135 return -EINVAL;
136
137 return arch_iommu->cr_valid(cr);
138}
139
140static inline struct cr_regs *iotlb_alloc_cr(struct iommu *obj,
141 struct iotlb_entry *e)
142{
143 if (!e)
144 return NULL;
145
146 return arch_iommu->alloc_cr(obj, e);
147}
148
149u32 iotlb_cr_to_virt(struct cr_regs *cr)
150{
151 return arch_iommu->cr_to_virt(cr);
152}
153EXPORT_SYMBOL_GPL(iotlb_cr_to_virt);
154
155static u32 get_iopte_attr(struct iotlb_entry *e)
156{
157 return arch_iommu->get_pte_attr(e);
158}
159
160static u32 iommu_report_fault(struct iommu *obj, u32 *da)
161{
162 return arch_iommu->fault_isr(obj, da);
163}
164
165static void iotlb_lock_get(struct iommu *obj, struct iotlb_lock *l)
166{
167 u32 val;
168
169 val = iommu_read_reg(obj, MMU_LOCK);
170
171 l->base = MMU_LOCK_BASE(val);
172 l->vict = MMU_LOCK_VICT(val);
173
174 BUG_ON(l->base != 0); /* Currently no preservation is used */
175}
176
177static void iotlb_lock_set(struct iommu *obj, struct iotlb_lock *l)
178{
179 u32 val;
180
181 BUG_ON(l->base != 0); /* Currently no preservation is used */
182
183 val = (l->base << MMU_LOCK_BASE_SHIFT);
184 val |= (l->vict << MMU_LOCK_VICT_SHIFT);
185
186 iommu_write_reg(obj, val, MMU_LOCK);
187}
188
189static void iotlb_read_cr(struct iommu *obj, struct cr_regs *cr)
190{
191 arch_iommu->tlb_read_cr(obj, cr);
192}
193
194static void iotlb_load_cr(struct iommu *obj, struct cr_regs *cr)
195{
196 arch_iommu->tlb_load_cr(obj, cr);
197
198 iommu_write_reg(obj, 1, MMU_FLUSH_ENTRY);
199 iommu_write_reg(obj, 1, MMU_LD_TLB);
200}
201
202/**
203 * iotlb_dump_cr - Dump an iommu tlb entry into buf
204 * @obj: target iommu
205 * @cr: contents of cam and ram register
206 * @buf: output buffer
207 **/
208static inline ssize_t iotlb_dump_cr(struct iommu *obj, struct cr_regs *cr,
209 char *buf)
210{
211 BUG_ON(!cr || !buf);
212
213 return arch_iommu->dump_cr(obj, cr, buf);
214}
215
216/**
217 * load_iotlb_entry - Set an iommu tlb entry
218 * @obj: target iommu
219 * @e: an iommu tlb entry info
220 **/
221int load_iotlb_entry(struct iommu *obj, struct iotlb_entry *e)
222{
223 int i;
224 int err = 0;
225 struct iotlb_lock l;
226 struct cr_regs *cr;
227
228 if (!obj || !obj->nr_tlb_entries || !e)
229 return -EINVAL;
230
231 clk_enable(obj->clk);
232
233 for (i = 0; i < obj->nr_tlb_entries; i++) {
234 struct cr_regs tmp;
235
236 iotlb_lock_get(obj, &l);
237 l.vict = i;
238 iotlb_lock_set(obj, &l);
239 iotlb_read_cr(obj, &tmp);
240 if (!iotlb_cr_valid(&tmp))
241 break;
242 }
243
244 if (i == obj->nr_tlb_entries) {
245 dev_dbg(obj->dev, "%s: full: no entry\n", __func__);
246 err = -EBUSY;
247 goto out;
248 }
249
250 cr = iotlb_alloc_cr(obj, e);
251 if (IS_ERR(cr)) {
252 clk_disable(obj->clk);
253 return PTR_ERR(cr);
254 }
255
256 iotlb_load_cr(obj, cr);
257 kfree(cr);
258
259 /* increment victim for next tlb load */
260 if (++l.vict == obj->nr_tlb_entries)
261 l.vict = 0;
262 iotlb_lock_set(obj, &l);
263out:
264 clk_disable(obj->clk);
265 return err;
266}
267EXPORT_SYMBOL_GPL(load_iotlb_entry);
268
269/**
270 * flush_iotlb_page - Clear an iommu tlb entry
271 * @obj: target iommu
272 * @da: iommu device virtual address
273 *
274 * Clear an iommu tlb entry which includes 'da' address.
275 **/
276void flush_iotlb_page(struct iommu *obj, u32 da)
277{
278 struct iotlb_lock l;
279 int i;
280
281 clk_enable(obj->clk);
282
283 for (i = 0; i < obj->nr_tlb_entries; i++) {
284 struct cr_regs cr;
285 u32 start;
286 size_t bytes;
287
288 iotlb_lock_get(obj, &l);
289 l.vict = i;
290 iotlb_lock_set(obj, &l);
291 iotlb_read_cr(obj, &cr);
292 if (!iotlb_cr_valid(&cr))
293 continue;
294
295 start = iotlb_cr_to_virt(&cr);
296 bytes = iopgsz_to_bytes(cr.cam & 3);
297
298 if ((start <= da) && (da < start + bytes)) {
299 dev_dbg(obj->dev, "%s: %08x<=%08x(%x)\n",
300 __func__, start, da, bytes);
301
302 iommu_write_reg(obj, 1, MMU_FLUSH_ENTRY);
303 }
304 }
305 clk_disable(obj->clk);
306
307 if (i == obj->nr_tlb_entries)
308 dev_dbg(obj->dev, "%s: no page for %08x\n", __func__, da);
309}
310EXPORT_SYMBOL_GPL(flush_iotlb_page);
311
312/**
313 * flush_iotlb_range - Clear an iommu tlb entries
314 * @obj: target iommu
315 * @start: iommu device virtual address(start)
316 * @end: iommu device virtual address(end)
317 *
318 * Clear an iommu tlb entry which includes 'da' address.
319 **/
320void flush_iotlb_range(struct iommu *obj, u32 start, u32 end)
321{
322 u32 da = start;
323
324 while (da < end) {
325 flush_iotlb_page(obj, da);
326 /* FIXME: Optimize for multiple page size */
327 da += IOPTE_SIZE;
328 }
329}
330EXPORT_SYMBOL_GPL(flush_iotlb_range);
331
332/**
333 * flush_iotlb_all - Clear all iommu tlb entries
334 * @obj: target iommu
335 **/
336void flush_iotlb_all(struct iommu *obj)
337{
338 struct iotlb_lock l;
339
340 clk_enable(obj->clk);
341
342 l.base = 0;
343 l.vict = 0;
344 iotlb_lock_set(obj, &l);
345
346 iommu_write_reg(obj, 1, MMU_GFLUSH);
347
348 clk_disable(obj->clk);
349}
350EXPORT_SYMBOL_GPL(flush_iotlb_all);
351
352#if defined(CONFIG_OMAP_IOMMU_DEBUG_MODULE)
353
354ssize_t iommu_dump_ctx(struct iommu *obj, char *buf)
355{
356 ssize_t bytes;
357
358 if (!obj || !buf)
359 return -EINVAL;
360
361 clk_enable(obj->clk);
362
363 bytes = arch_iommu->dump_ctx(obj, buf);
364
365 clk_disable(obj->clk);
366
367 return bytes;
368}
369EXPORT_SYMBOL_GPL(iommu_dump_ctx);
370
371static int __dump_tlb_entries(struct iommu *obj, struct cr_regs *crs)
372{
373 int i;
374 struct iotlb_lock saved, l;
375 struct cr_regs *p = crs;
376
377 clk_enable(obj->clk);
378
379 iotlb_lock_get(obj, &saved);
380 memcpy(&l, &saved, sizeof(saved));
381
382 for (i = 0; i < obj->nr_tlb_entries; i++) {
383 struct cr_regs tmp;
384
385 iotlb_lock_get(obj, &l);
386 l.vict = i;
387 iotlb_lock_set(obj, &l);
388 iotlb_read_cr(obj, &tmp);
389 if (!iotlb_cr_valid(&tmp))
390 continue;
391
392 *p++ = tmp;
393 }
394 iotlb_lock_set(obj, &saved);
395 clk_disable(obj->clk);
396
397 return p - crs;
398}
399
400/**
401 * dump_tlb_entries - dump cr arrays to given buffer
402 * @obj: target iommu
403 * @buf: output buffer
404 **/
405size_t dump_tlb_entries(struct iommu *obj, char *buf)
406{
407 int i, n;
408 struct cr_regs *cr;
409 char *p = buf;
410
411 cr = kcalloc(obj->nr_tlb_entries, sizeof(*cr), GFP_KERNEL);
412 if (!cr)
413 return 0;
414
415 n = __dump_tlb_entries(obj, cr);
416 for (i = 0; i < n; i++)
417 p += iotlb_dump_cr(obj, cr + i, p);
418 kfree(cr);
419
420 return p - buf;
421}
422EXPORT_SYMBOL_GPL(dump_tlb_entries);
423
424int foreach_iommu_device(void *data, int (*fn)(struct device *, void *))
425{
426 return driver_for_each_device(&omap_iommu_driver.driver,
427 NULL, data, fn);
428}
429EXPORT_SYMBOL_GPL(foreach_iommu_device);
430
431#endif /* CONFIG_OMAP_IOMMU_DEBUG_MODULE */
432
433/*
434 * H/W pagetable operations
435 */
436static void flush_iopgd_range(u32 *first, u32 *last)
437{
438 /* FIXME: L2 cache should be taken care of if it exists */
439 do {
440 asm("mcr p15, 0, %0, c7, c10, 1 @ flush_pgd"
441 : : "r" (first));
442 first += L1_CACHE_BYTES / sizeof(*first);
443 } while (first <= last);
444}
445
446static void flush_iopte_range(u32 *first, u32 *last)
447{
448 /* FIXME: L2 cache should be taken care of if it exists */
449 do {
450 asm("mcr p15, 0, %0, c7, c10, 1 @ flush_pte"
451 : : "r" (first));
452 first += L1_CACHE_BYTES / sizeof(*first);
453 } while (first <= last);
454}
455
456static void iopte_free(u32 *iopte)
457{
458 /* Note: freed iopte's must be clean ready for re-use */
459 kmem_cache_free(iopte_cachep, iopte);
460}
461
462static u32 *iopte_alloc(struct iommu *obj, u32 *iopgd, u32 da)
463{
464 u32 *iopte;
465
466 /* a table has already existed */
467 if (*iopgd)
468 goto pte_ready;
469
470 /*
471 * do the allocation outside the page table lock
472 */
473 spin_unlock(&obj->page_table_lock);
474 iopte = kmem_cache_zalloc(iopte_cachep, GFP_KERNEL);
475 spin_lock(&obj->page_table_lock);
476
477 if (!*iopgd) {
478 if (!iopte)
479 return ERR_PTR(-ENOMEM);
480
481 *iopgd = virt_to_phys(iopte) | IOPGD_TABLE;
482 flush_iopgd_range(iopgd, iopgd);
483
484 dev_vdbg(obj->dev, "%s: a new pte:%p\n", __func__, iopte);
485 } else {
486 /* We raced, free the reduniovant table */
487 iopte_free(iopte);
488 }
489
490pte_ready:
491 iopte = iopte_offset(iopgd, da);
492
493 dev_vdbg(obj->dev,
494 "%s: da:%08x pgd:%p *pgd:%08x pte:%p *pte:%08x\n",
495 __func__, da, iopgd, *iopgd, iopte, *iopte);
496
497 return iopte;
498}
499
500static int iopgd_alloc_section(struct iommu *obj, u32 da, u32 pa, u32 prot)
501{
502 u32 *iopgd = iopgd_offset(obj, da);
503
504 *iopgd = (pa & IOSECTION_MASK) | prot | IOPGD_SECTION;
505 flush_iopgd_range(iopgd, iopgd);
506 return 0;
507}
508
509static int iopgd_alloc_super(struct iommu *obj, u32 da, u32 pa, u32 prot)
510{
511 u32 *iopgd = iopgd_offset(obj, da);
512 int i;
513
514 for (i = 0; i < 16; i++)
515 *(iopgd + i) = (pa & IOSUPER_MASK) | prot | IOPGD_SUPER;
516 flush_iopgd_range(iopgd, iopgd + 15);
517 return 0;
518}
519
520static int iopte_alloc_page(struct iommu *obj, u32 da, u32 pa, u32 prot)
521{
522 u32 *iopgd = iopgd_offset(obj, da);
523 u32 *iopte = iopte_alloc(obj, iopgd, da);
524
525 if (IS_ERR(iopte))
526 return PTR_ERR(iopte);
527
528 *iopte = (pa & IOPAGE_MASK) | prot | IOPTE_SMALL;
529 flush_iopte_range(iopte, iopte);
530
531 dev_vdbg(obj->dev, "%s: da:%08x pa:%08x pte:%p *pte:%08x\n",
532 __func__, da, pa, iopte, *iopte);
533
534 return 0;
535}
536
537static int iopte_alloc_large(struct iommu *obj, u32 da, u32 pa, u32 prot)
538{
539 u32 *iopgd = iopgd_offset(obj, da);
540 u32 *iopte = iopte_alloc(obj, iopgd, da);
541 int i;
542
543 if (IS_ERR(iopte))
544 return PTR_ERR(iopte);
545
546 for (i = 0; i < 16; i++)
547 *(iopte + i) = (pa & IOLARGE_MASK) | prot | IOPTE_LARGE;
548 flush_iopte_range(iopte, iopte + 15);
549 return 0;
550}
551
552static int iopgtable_store_entry_core(struct iommu *obj, struct iotlb_entry *e)
553{
554 int (*fn)(struct iommu *, u32, u32, u32);
555 u32 prot;
556 int err;
557
558 if (!obj || !e)
559 return -EINVAL;
560
561 switch (e->pgsz) {
562 case MMU_CAM_PGSZ_16M:
563 fn = iopgd_alloc_super;
564 break;
565 case MMU_CAM_PGSZ_1M:
566 fn = iopgd_alloc_section;
567 break;
568 case MMU_CAM_PGSZ_64K:
569 fn = iopte_alloc_large;
570 break;
571 case MMU_CAM_PGSZ_4K:
572 fn = iopte_alloc_page;
573 break;
574 default:
575 fn = NULL;
576 BUG();
577 break;
578 }
579
580 prot = get_iopte_attr(e);
581
582 spin_lock(&obj->page_table_lock);
583 err = fn(obj, e->da, e->pa, prot);
584 spin_unlock(&obj->page_table_lock);
585
586 return err;
587}
588
589/**
590 * iopgtable_store_entry - Make an iommu pte entry
591 * @obj: target iommu
592 * @e: an iommu tlb entry info
593 **/
594int iopgtable_store_entry(struct iommu *obj, struct iotlb_entry *e)
595{
596 int err;
597
598 flush_iotlb_page(obj, e->da);
599 err = iopgtable_store_entry_core(obj, e);
600#ifdef PREFETCH_IOTLB
601 if (!err)
602 load_iotlb_entry(obj, e);
603#endif
604 return err;
605}
606EXPORT_SYMBOL_GPL(iopgtable_store_entry);
607
608/**
609 * iopgtable_lookup_entry - Lookup an iommu pte entry
610 * @obj: target iommu
611 * @da: iommu device virtual address
612 * @ppgd: iommu pgd entry pointer to be returned
613 * @ppte: iommu pte entry pointer to be returned
614 **/
615void iopgtable_lookup_entry(struct iommu *obj, u32 da, u32 **ppgd, u32 **ppte)
616{
617 u32 *iopgd, *iopte = NULL;
618
619 iopgd = iopgd_offset(obj, da);
620 if (!*iopgd)
621 goto out;
622
623 if (*iopgd & IOPGD_TABLE)
624 iopte = iopte_offset(iopgd, da);
625out:
626 *ppgd = iopgd;
627 *ppte = iopte;
628}
629EXPORT_SYMBOL_GPL(iopgtable_lookup_entry);
630
631static size_t iopgtable_clear_entry_core(struct iommu *obj, u32 da)
632{
633 size_t bytes;
634 u32 *iopgd = iopgd_offset(obj, da);
635 int nent = 1;
636
637 if (!*iopgd)
638 return 0;
639
640 if (*iopgd & IOPGD_TABLE) {
641 int i;
642 u32 *iopte = iopte_offset(iopgd, da);
643
644 bytes = IOPTE_SIZE;
645 if (*iopte & IOPTE_LARGE) {
646 nent *= 16;
647 /* rewind to the 1st entry */
648 iopte = (u32 *)((u32)iopte & IOLARGE_MASK);
649 }
650 bytes *= nent;
651 memset(iopte, 0, nent * sizeof(*iopte));
652 flush_iopte_range(iopte, iopte + (nent - 1) * sizeof(*iopte));
653
654 /*
655 * do table walk to check if this table is necessary or not
656 */
657 iopte = iopte_offset(iopgd, 0);
658 for (i = 0; i < PTRS_PER_IOPTE; i++)
659 if (iopte[i])
660 goto out;
661
662 iopte_free(iopte);
663 nent = 1; /* for the next L1 entry */
664 } else {
665 bytes = IOPGD_SIZE;
666 if (*iopgd & IOPGD_SUPER) {
667 nent *= 16;
668 /* rewind to the 1st entry */
669 iopgd = (u32 *)((u32)iopgd & IOSUPER_MASK);
670 }
671 bytes *= nent;
672 }
673 memset(iopgd, 0, nent * sizeof(*iopgd));
674 flush_iopgd_range(iopgd, iopgd + (nent - 1) * sizeof(*iopgd));
675out:
676 return bytes;
677}
678
679/**
680 * iopgtable_clear_entry - Remove an iommu pte entry
681 * @obj: target iommu
682 * @da: iommu device virtual address
683 **/
684size_t iopgtable_clear_entry(struct iommu *obj, u32 da)
685{
686 size_t bytes;
687
688 spin_lock(&obj->page_table_lock);
689
690 bytes = iopgtable_clear_entry_core(obj, da);
691 flush_iotlb_page(obj, da);
692
693 spin_unlock(&obj->page_table_lock);
694
695 return bytes;
696}
697EXPORT_SYMBOL_GPL(iopgtable_clear_entry);
698
699static void iopgtable_clear_entry_all(struct iommu *obj)
700{
701 int i;
702
703 spin_lock(&obj->page_table_lock);
704
705 for (i = 0; i < PTRS_PER_IOPGD; i++) {
706 u32 da;
707 u32 *iopgd;
708
709 da = i << IOPGD_SHIFT;
710 iopgd = iopgd_offset(obj, da);
711
712 if (!*iopgd)
713 continue;
714
715 if (*iopgd & IOPGD_TABLE)
716 iopte_free(iopte_offset(iopgd, 0));
717
718 *iopgd = 0;
719 flush_iopgd_range(iopgd, iopgd);
720 }
721
722 flush_iotlb_all(obj);
723
724 spin_unlock(&obj->page_table_lock);
725}
726
727/*
728 * Device IOMMU generic operations
729 */
730static irqreturn_t iommu_fault_handler(int irq, void *data)
731{
732 u32 stat, da;
733 u32 *iopgd, *iopte;
734 int err = -EIO;
735 struct iommu *obj = data;
736
737 if (!obj->refcount)
738 return IRQ_NONE;
739
740 /* Dynamic loading TLB or PTE */
741 if (obj->isr)
742 err = obj->isr(obj);
743
744 if (!err)
745 return IRQ_HANDLED;
746
747 clk_enable(obj->clk);
748 stat = iommu_report_fault(obj, &da);
749 clk_disable(obj->clk);
750 if (!stat)
751 return IRQ_HANDLED;
752
753 iopgd = iopgd_offset(obj, da);
754
755 if (!(*iopgd & IOPGD_TABLE)) {
756 dev_err(obj->dev, "%s: da:%08x pgd:%p *pgd:%08x\n", __func__,
757 da, iopgd, *iopgd);
758 return IRQ_NONE;
759 }
760
761 iopte = iopte_offset(iopgd, da);
762
763 dev_err(obj->dev, "%s: da:%08x pgd:%p *pgd:%08x pte:%p *pte:%08x\n",
764 __func__, da, iopgd, *iopgd, iopte, *iopte);
765
766 return IRQ_NONE;
767}
768
769static int device_match_by_alias(struct device *dev, void *data)
770{
771 struct iommu *obj = to_iommu(dev);
772 const char *name = data;
773
774 pr_debug("%s: %s %s\n", __func__, obj->name, name);
775
776 return strcmp(obj->name, name) == 0;
777}
778
779/**
780 * iommu_get - Get iommu handler
781 * @name: target iommu name
782 **/
783struct iommu *iommu_get(const char *name)
784{
785 int err = -ENOMEM;
786 struct device *dev;
787 struct iommu *obj;
788
789 dev = driver_find_device(&omap_iommu_driver.driver, NULL, (void *)name,
790 device_match_by_alias);
791 if (!dev)
792 return ERR_PTR(-ENODEV);
793
794 obj = to_iommu(dev);
795
796 mutex_lock(&obj->iommu_lock);
797
798 if (obj->refcount++ == 0) {
799 err = iommu_enable(obj);
800 if (err)
801 goto err_enable;
802 flush_iotlb_all(obj);
803 }
804
805 if (!try_module_get(obj->owner))
806 goto err_module;
807
808 mutex_unlock(&obj->iommu_lock);
809
810 dev_dbg(obj->dev, "%s: %s\n", __func__, obj->name);
811 return obj;
812
813err_module:
814 if (obj->refcount == 1)
815 iommu_disable(obj);
816err_enable:
817 obj->refcount--;
818 mutex_unlock(&obj->iommu_lock);
819 return ERR_PTR(err);
820}
821EXPORT_SYMBOL_GPL(iommu_get);
822
823/**
824 * iommu_put - Put back iommu handler
825 * @obj: target iommu
826 **/
827void iommu_put(struct iommu *obj)
828{
829 if (!obj && IS_ERR(obj))
830 return;
831
832 mutex_lock(&obj->iommu_lock);
833
834 if (--obj->refcount == 0)
835 iommu_disable(obj);
836
837 module_put(obj->owner);
838
839 mutex_unlock(&obj->iommu_lock);
840
841 dev_dbg(obj->dev, "%s: %s\n", __func__, obj->name);
842}
843EXPORT_SYMBOL_GPL(iommu_put);
844
845/*
846 * OMAP Device MMU(IOMMU) detection
847 */
848static int __devinit omap_iommu_probe(struct platform_device *pdev)
849{
850 int err = -ENODEV;
851 void *p;
852 int irq;
853 struct iommu *obj;
854 struct resource *res;
855 struct iommu_platform_data *pdata = pdev->dev.platform_data;
856
857 if (pdev->num_resources != 2)
858 return -EINVAL;
859
860 obj = kzalloc(sizeof(*obj) + MMU_REG_SIZE, GFP_KERNEL);
861 if (!obj)
862 return -ENOMEM;
863
864 obj->clk = clk_get(&pdev->dev, pdata->clk_name);
865 if (IS_ERR(obj->clk))
866 goto err_clk;
867
868 obj->nr_tlb_entries = pdata->nr_tlb_entries;
869 obj->name = pdata->name;
870 obj->dev = &pdev->dev;
871 obj->ctx = (void *)obj + sizeof(*obj);
872
873 mutex_init(&obj->iommu_lock);
874 mutex_init(&obj->mmap_lock);
875 spin_lock_init(&obj->page_table_lock);
876 INIT_LIST_HEAD(&obj->mmap);
877
878 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
879 if (!res) {
880 err = -ENODEV;
881 goto err_mem;
882 }
883 obj->regbase = ioremap(res->start, resource_size(res));
884 if (!obj->regbase) {
885 err = -ENOMEM;
886 goto err_mem;
887 }
888
889 res = request_mem_region(res->start, resource_size(res),
890 dev_name(&pdev->dev));
891 if (!res) {
892 err = -EIO;
893 goto err_mem;
894 }
895
896 irq = platform_get_irq(pdev, 0);
897 if (irq < 0) {
898 err = -ENODEV;
899 goto err_irq;
900 }
901 err = request_irq(irq, iommu_fault_handler, IRQF_SHARED,
902 dev_name(&pdev->dev), obj);
903 if (err < 0)
904 goto err_irq;
905 platform_set_drvdata(pdev, obj);
906
907 p = (void *)__get_free_pages(GFP_KERNEL, get_order(IOPGD_TABLE_SIZE));
908 if (!p) {
909 err = -ENOMEM;
910 goto err_pgd;
911 }
912 memset(p, 0, IOPGD_TABLE_SIZE);
913 clean_dcache_area(p, IOPGD_TABLE_SIZE);
914 obj->iopgd = p;
915
916 BUG_ON(!IS_ALIGNED((unsigned long)obj->iopgd, IOPGD_TABLE_SIZE));
917
918 dev_info(&pdev->dev, "%s registered\n", obj->name);
919 return 0;
920
921err_pgd:
922 free_irq(irq, obj);
923err_irq:
924 release_mem_region(res->start, resource_size(res));
925 iounmap(obj->regbase);
926err_mem:
927 clk_put(obj->clk);
928err_clk:
929 kfree(obj);
930 return err;
931}
932
933static int __devexit omap_iommu_remove(struct platform_device *pdev)
934{
935 int irq;
936 struct resource *res;
937 struct iommu *obj = platform_get_drvdata(pdev);
938
939 platform_set_drvdata(pdev, NULL);
940
941 iopgtable_clear_entry_all(obj);
942 free_pages((unsigned long)obj->iopgd, get_order(IOPGD_TABLE_SIZE));
943
944 irq = platform_get_irq(pdev, 0);
945 free_irq(irq, obj);
946 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
947 release_mem_region(res->start, resource_size(res));
948 iounmap(obj->regbase);
949
950 clk_put(obj->clk);
951 dev_info(&pdev->dev, "%s removed\n", obj->name);
952 kfree(obj);
953 return 0;
954}
955
956static struct platform_driver omap_iommu_driver = {
957 .probe = omap_iommu_probe,
958 .remove = __devexit_p(omap_iommu_remove),
959 .driver = {
960 .name = "omap-iommu",
961 },
962};
963
964static void iopte_cachep_ctor(void *iopte)
965{
966 clean_dcache_area(iopte, IOPTE_TABLE_SIZE);
967}
968
969static int __init omap_iommu_init(void)
970{
971 struct kmem_cache *p;
972 const unsigned long flags = SLAB_HWCACHE_ALIGN;
973 size_t align = 1 << 10; /* L2 pagetable alignement */
974
975 p = kmem_cache_create("iopte_cache", IOPTE_TABLE_SIZE, align, flags,
976 iopte_cachep_ctor);
977 if (!p)
978 return -ENOMEM;
979 iopte_cachep = p;
980
981 return platform_driver_register(&omap_iommu_driver);
982}
983module_init(omap_iommu_init);
984
985static void __exit omap_iommu_exit(void)
986{
987 kmem_cache_destroy(iopte_cachep);
988
989 platform_driver_unregister(&omap_iommu_driver);
990}
991module_exit(omap_iommu_exit);
992
993MODULE_DESCRIPTION("omap iommu: tlb and pagetable primitives");
994MODULE_ALIAS("platform:omap-iommu");
995MODULE_AUTHOR("Hiroshi DOYU, Paul Mundt and Toshihiro Kobayashi");
996MODULE_LICENSE("GPL v2");
diff --git a/arch/arm/plat-omap/iopgtable.h b/arch/arm/plat-omap/iopgtable.h
new file mode 100644
index 000000000000..37dac434c7a1
--- /dev/null
+++ b/arch/arm/plat-omap/iopgtable.h
@@ -0,0 +1,72 @@
1/*
2 * omap iommu: pagetable definitions
3 *
4 * Copyright (C) 2008-2009 Nokia Corporation
5 *
6 * Written by Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#ifndef __PLAT_OMAP_IOMMU_H
14#define __PLAT_OMAP_IOMMU_H
15
16#define IOPGD_SHIFT 20
17#define IOPGD_SIZE (1 << IOPGD_SHIFT)
18#define IOPGD_MASK (~(IOPGD_SIZE - 1))
19#define IOSECTION_MASK IOPGD_MASK
20#define PTRS_PER_IOPGD (1 << (32 - IOPGD_SHIFT))
21#define IOPGD_TABLE_SIZE (PTRS_PER_IOPGD * sizeof(u32))
22
23#define IOSUPER_SIZE (IOPGD_SIZE << 4)
24#define IOSUPER_MASK (~(IOSUPER_SIZE - 1))
25
26#define IOPTE_SHIFT 12
27#define IOPTE_SIZE (1 << IOPTE_SHIFT)
28#define IOPTE_MASK (~(IOPTE_SIZE - 1))
29#define IOPAGE_MASK IOPTE_MASK
30#define PTRS_PER_IOPTE (1 << (IOPGD_SHIFT - IOPTE_SHIFT))
31#define IOPTE_TABLE_SIZE (PTRS_PER_IOPTE * sizeof(u32))
32
33#define IOLARGE_SIZE (IOPTE_SIZE << 4)
34#define IOLARGE_MASK (~(IOLARGE_SIZE - 1))
35
36#define IOPGD_TABLE (1 << 0)
37#define IOPGD_SECTION (2 << 0)
38#define IOPGD_SUPER (1 << 18 | 2 << 0)
39
40#define IOPTE_SMALL (2 << 0)
41#define IOPTE_LARGE (1 << 0)
42
43#define iopgd_index(da) (((da) >> IOPGD_SHIFT) & (PTRS_PER_IOPGD - 1))
44#define iopgd_offset(obj, da) ((obj)->iopgd + iopgd_index(da))
45
46#define iopte_paddr(iopgd) (*iopgd & ~((1 << 10) - 1))
47#define iopte_vaddr(iopgd) ((u32 *)phys_to_virt(iopte_paddr(iopgd)))
48
49#define iopte_index(da) (((da) >> IOPTE_SHIFT) & (PTRS_PER_IOPTE - 1))
50#define iopte_offset(iopgd, da) (iopte_vaddr(iopgd) + iopte_index(da))
51
52static inline u32 iotlb_init_entry(struct iotlb_entry *e, u32 da, u32 pa,
53 u32 flags)
54{
55 memset(e, 0, sizeof(*e));
56
57 e->da = da;
58 e->pa = pa;
59 e->valid = 1;
60 /* FIXME: add OMAP1 support */
61 e->pgsz = flags & MMU_CAM_PGSZ_MASK;
62 e->endian = flags & MMU_RAM_ENDIAN_MASK;
63 e->elsz = flags & MMU_RAM_ELSZ_MASK;
64 e->mixed = flags & MMU_RAM_MIXED_MASK;
65
66 return iopgsz_to_bytes(e->pgsz);
67}
68
69#define to_iommu(dev) \
70 (struct iommu *)platform_get_drvdata(to_platform_device(dev))
71
72#endif /* __PLAT_OMAP_IOMMU_H */
diff --git a/arch/arm/plat-omap/iovmm.c b/arch/arm/plat-omap/iovmm.c
new file mode 100644
index 000000000000..2fce2c151a95
--- /dev/null
+++ b/arch/arm/plat-omap/iovmm.c
@@ -0,0 +1,896 @@
1/*
2 * omap iommu: simple virtual address space management
3 *
4 * Copyright (C) 2008-2009 Nokia Corporation
5 *
6 * Written by Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#include <linux/err.h>
14#include <linux/vmalloc.h>
15#include <linux/device.h>
16#include <linux/scatterlist.h>
17
18#include <asm/cacheflush.h>
19#include <asm/mach/map.h>
20
21#include <mach/iommu.h>
22#include <mach/iovmm.h>
23
24#include "iopgtable.h"
25
26/*
27 * A device driver needs to create address mappings between:
28 *
29 * - iommu/device address
30 * - physical address
31 * - mpu virtual address
32 *
33 * There are 4 possible patterns for them:
34 *
35 * |iova/ mapping iommu_ page
36 * | da pa va (d)-(p)-(v) function type
37 * ---------------------------------------------------------------------------
38 * 1 | c c c 1 - 1 - 1 _kmap() / _kunmap() s
39 * 2 | c c,a c 1 - 1 - 1 _kmalloc()/ _kfree() s
40 * 3 | c d c 1 - n - 1 _vmap() / _vunmap() s
41 * 4 | c d,a c 1 - n - 1 _vmalloc()/ _vfree() n*
42 *
43 *
44 * 'iova': device iommu virtual address
45 * 'da': alias of 'iova'
46 * 'pa': physical address
47 * 'va': mpu virtual address
48 *
49 * 'c': contiguous memory area
50 * 'd': dicontiguous memory area
51 * 'a': anonymous memory allocation
52 * '()': optional feature
53 *
54 * 'n': a normal page(4KB) size is used.
55 * 's': multiple iommu superpage(16MB, 1MB, 64KB, 4KB) size is used.
56 *
57 * '*': not yet, but feasible.
58 */
59
60static struct kmem_cache *iovm_area_cachep;
61
62/* return total bytes of sg buffers */
63static size_t sgtable_len(const struct sg_table *sgt)
64{
65 unsigned int i, total = 0;
66 struct scatterlist *sg;
67
68 if (!sgt)
69 return 0;
70
71 for_each_sg(sgt->sgl, sg, sgt->nents, i) {
72 size_t bytes;
73
74 bytes = sg_dma_len(sg);
75
76 if (!iopgsz_ok(bytes)) {
77 pr_err("%s: sg[%d] not iommu pagesize(%x)\n",
78 __func__, i, bytes);
79 return 0;
80 }
81
82 total += bytes;
83 }
84
85 return total;
86}
87#define sgtable_ok(x) (!!sgtable_len(x))
88
89/*
90 * calculate the optimal number sg elements from total bytes based on
91 * iommu superpages
92 */
93static unsigned int sgtable_nents(size_t bytes)
94{
95 int i;
96 unsigned int nr_entries;
97 const unsigned long pagesize[] = { SZ_16M, SZ_1M, SZ_64K, SZ_4K, };
98
99 if (!IS_ALIGNED(bytes, PAGE_SIZE)) {
100 pr_err("%s: wrong size %08x\n", __func__, bytes);
101 return 0;
102 }
103
104 nr_entries = 0;
105 for (i = 0; i < ARRAY_SIZE(pagesize); i++) {
106 if (bytes >= pagesize[i]) {
107 nr_entries += (bytes / pagesize[i]);
108 bytes %= pagesize[i];
109 }
110 }
111 BUG_ON(bytes);
112
113 return nr_entries;
114}
115
116/* allocate and initialize sg_table header(a kind of 'superblock') */
117static struct sg_table *sgtable_alloc(const size_t bytes, u32 flags)
118{
119 unsigned int nr_entries;
120 int err;
121 struct sg_table *sgt;
122
123 if (!bytes)
124 return ERR_PTR(-EINVAL);
125
126 if (!IS_ALIGNED(bytes, PAGE_SIZE))
127 return ERR_PTR(-EINVAL);
128
129 /* FIXME: IOVMF_DA_FIXED should support 'superpages' */
130 if ((flags & IOVMF_LINEAR) && (flags & IOVMF_DA_ANON)) {
131 nr_entries = sgtable_nents(bytes);
132 if (!nr_entries)
133 return ERR_PTR(-EINVAL);
134 } else
135 nr_entries = bytes / PAGE_SIZE;
136
137 sgt = kzalloc(sizeof(*sgt), GFP_KERNEL);
138 if (!sgt)
139 return ERR_PTR(-ENOMEM);
140
141 err = sg_alloc_table(sgt, nr_entries, GFP_KERNEL);
142 if (err)
143 return ERR_PTR(err);
144
145 pr_debug("%s: sgt:%p(%d entries)\n", __func__, sgt, nr_entries);
146
147 return sgt;
148}
149
150/* free sg_table header(a kind of superblock) */
151static void sgtable_free(struct sg_table *sgt)
152{
153 if (!sgt)
154 return;
155
156 sg_free_table(sgt);
157 kfree(sgt);
158
159 pr_debug("%s: sgt:%p\n", __func__, sgt);
160}
161
162/* map 'sglist' to a contiguous mpu virtual area and return 'va' */
163static void *vmap_sg(const struct sg_table *sgt)
164{
165 u32 va;
166 size_t total;
167 unsigned int i;
168 struct scatterlist *sg;
169 struct vm_struct *new;
170 const struct mem_type *mtype;
171
172 mtype = get_mem_type(MT_DEVICE);
173 if (!mtype)
174 return ERR_PTR(-EINVAL);
175
176 total = sgtable_len(sgt);
177 if (!total)
178 return ERR_PTR(-EINVAL);
179
180 new = __get_vm_area(total, VM_IOREMAP, VMALLOC_START, VMALLOC_END);
181 if (!new)
182 return ERR_PTR(-ENOMEM);
183 va = (u32)new->addr;
184
185 for_each_sg(sgt->sgl, sg, sgt->nents, i) {
186 size_t bytes;
187 u32 pa;
188 int err;
189
190 pa = sg_phys(sg);
191 bytes = sg_dma_len(sg);
192
193 BUG_ON(bytes != PAGE_SIZE);
194
195 err = ioremap_page(va, pa, mtype);
196 if (err)
197 goto err_out;
198
199 va += bytes;
200 }
201
202 flush_cache_vmap(new->addr, total);
203 return new->addr;
204
205err_out:
206 WARN_ON(1); /* FIXME: cleanup some mpu mappings */
207 vunmap(new->addr);
208 return ERR_PTR(-EAGAIN);
209}
210
211static inline void vunmap_sg(const void *va)
212{
213 vunmap(va);
214}
215
216static struct iovm_struct *__find_iovm_area(struct iommu *obj, const u32 da)
217{
218 struct iovm_struct *tmp;
219
220 list_for_each_entry(tmp, &obj->mmap, list) {
221 if ((da >= tmp->da_start) && (da < tmp->da_end)) {
222 size_t len;
223
224 len = tmp->da_end - tmp->da_start;
225
226 dev_dbg(obj->dev, "%s: %08x-%08x-%08x(%x) %08x\n",
227 __func__, tmp->da_start, da, tmp->da_end, len,
228 tmp->flags);
229
230 return tmp;
231 }
232 }
233
234 return NULL;
235}
236
237/**
238 * find_iovm_area - find iovma which includes @da
239 * @da: iommu device virtual address
240 *
241 * Find the existing iovma starting at @da
242 */
243struct iovm_struct *find_iovm_area(struct iommu *obj, u32 da)
244{
245 struct iovm_struct *area;
246
247 mutex_lock(&obj->mmap_lock);
248 area = __find_iovm_area(obj, da);
249 mutex_unlock(&obj->mmap_lock);
250
251 return area;
252}
253EXPORT_SYMBOL_GPL(find_iovm_area);
254
255/*
256 * This finds the hole(area) which fits the requested address and len
257 * in iovmas mmap, and returns the new allocated iovma.
258 */
259static struct iovm_struct *alloc_iovm_area(struct iommu *obj, u32 da,
260 size_t bytes, u32 flags)
261{
262 struct iovm_struct *new, *tmp;
263 u32 start, prev_end, alignement;
264
265 if (!obj || !bytes)
266 return ERR_PTR(-EINVAL);
267
268 start = da;
269 alignement = PAGE_SIZE;
270
271 if (flags & IOVMF_DA_ANON) {
272 /*
273 * Reserve the first page for NULL
274 */
275 start = PAGE_SIZE;
276 if (flags & IOVMF_LINEAR)
277 alignement = iopgsz_max(bytes);
278 start = roundup(start, alignement);
279 }
280
281 tmp = NULL;
282 if (list_empty(&obj->mmap))
283 goto found;
284
285 prev_end = 0;
286 list_for_each_entry(tmp, &obj->mmap, list) {
287
288 if ((prev_end <= start) && (start + bytes < tmp->da_start))
289 goto found;
290
291 if (flags & IOVMF_DA_ANON)
292 start = roundup(tmp->da_end, alignement);
293
294 prev_end = tmp->da_end;
295 }
296
297 if ((start >= prev_end) && (ULONG_MAX - start >= bytes))
298 goto found;
299
300 dev_dbg(obj->dev, "%s: no space to fit %08x(%x) flags: %08x\n",
301 __func__, da, bytes, flags);
302
303 return ERR_PTR(-EINVAL);
304
305found:
306 new = kmem_cache_zalloc(iovm_area_cachep, GFP_KERNEL);
307 if (!new)
308 return ERR_PTR(-ENOMEM);
309
310 new->iommu = obj;
311 new->da_start = start;
312 new->da_end = start + bytes;
313 new->flags = flags;
314
315 /*
316 * keep ascending order of iovmas
317 */
318 if (tmp)
319 list_add_tail(&new->list, &tmp->list);
320 else
321 list_add(&new->list, &obj->mmap);
322
323 dev_dbg(obj->dev, "%s: found %08x-%08x-%08x(%x) %08x\n",
324 __func__, new->da_start, start, new->da_end, bytes, flags);
325
326 return new;
327}
328
329static void free_iovm_area(struct iommu *obj, struct iovm_struct *area)
330{
331 size_t bytes;
332
333 BUG_ON(!obj || !area);
334
335 bytes = area->da_end - area->da_start;
336
337 dev_dbg(obj->dev, "%s: %08x-%08x(%x) %08x\n",
338 __func__, area->da_start, area->da_end, bytes, area->flags);
339
340 list_del(&area->list);
341 kmem_cache_free(iovm_area_cachep, area);
342}
343
344/**
345 * da_to_va - convert (d) to (v)
346 * @obj: objective iommu
347 * @da: iommu device virtual address
348 * @va: mpu virtual address
349 *
350 * Returns mpu virtual addr which corresponds to a given device virtual addr
351 */
352void *da_to_va(struct iommu *obj, u32 da)
353{
354 void *va = NULL;
355 struct iovm_struct *area;
356
357 mutex_lock(&obj->mmap_lock);
358
359 area = __find_iovm_area(obj, da);
360 if (!area) {
361 dev_dbg(obj->dev, "%s: no da area(%08x)\n", __func__, da);
362 goto out;
363 }
364 va = area->va;
365 mutex_unlock(&obj->mmap_lock);
366out:
367 return va;
368}
369EXPORT_SYMBOL_GPL(da_to_va);
370
371static void sgtable_fill_vmalloc(struct sg_table *sgt, void *_va)
372{
373 unsigned int i;
374 struct scatterlist *sg;
375 void *va = _va;
376 void *va_end;
377
378 for_each_sg(sgt->sgl, sg, sgt->nents, i) {
379 struct page *pg;
380 const size_t bytes = PAGE_SIZE;
381
382 /*
383 * iommu 'superpage' isn't supported with 'iommu_vmalloc()'
384 */
385 pg = vmalloc_to_page(va);
386 BUG_ON(!pg);
387 sg_set_page(sg, pg, bytes, 0);
388
389 va += bytes;
390 }
391
392 va_end = _va + PAGE_SIZE * i;
393 flush_cache_vmap(_va, va_end);
394}
395
396static inline void sgtable_drain_vmalloc(struct sg_table *sgt)
397{
398 /*
399 * Actually this is not necessary at all, just exists for
400 * consistency of the code readibility.
401 */
402 BUG_ON(!sgt);
403}
404
405static void sgtable_fill_kmalloc(struct sg_table *sgt, u32 pa, size_t len)
406{
407 unsigned int i;
408 struct scatterlist *sg;
409 void *va;
410
411 va = phys_to_virt(pa);
412
413 for_each_sg(sgt->sgl, sg, sgt->nents, i) {
414 size_t bytes;
415
416 bytes = iopgsz_max(len);
417
418 BUG_ON(!iopgsz_ok(bytes));
419
420 sg_set_buf(sg, phys_to_virt(pa), bytes);
421 /*
422 * 'pa' is cotinuous(linear).
423 */
424 pa += bytes;
425 len -= bytes;
426 }
427 BUG_ON(len);
428
429 clean_dcache_area(va, len);
430}
431
432static inline void sgtable_drain_kmalloc(struct sg_table *sgt)
433{
434 /*
435 * Actually this is not necessary at all, just exists for
436 * consistency of the code readibility
437 */
438 BUG_ON(!sgt);
439}
440
441/* create 'da' <-> 'pa' mapping from 'sgt' */
442static int map_iovm_area(struct iommu *obj, struct iovm_struct *new,
443 const struct sg_table *sgt, u32 flags)
444{
445 int err;
446 unsigned int i, j;
447 struct scatterlist *sg;
448 u32 da = new->da_start;
449
450 if (!obj || !new || !sgt)
451 return -EINVAL;
452
453 BUG_ON(!sgtable_ok(sgt));
454
455 for_each_sg(sgt->sgl, sg, sgt->nents, i) {
456 u32 pa;
457 int pgsz;
458 size_t bytes;
459 struct iotlb_entry e;
460
461 pa = sg_phys(sg);
462 bytes = sg_dma_len(sg);
463
464 flags &= ~IOVMF_PGSZ_MASK;
465 pgsz = bytes_to_iopgsz(bytes);
466 if (pgsz < 0)
467 goto err_out;
468 flags |= pgsz;
469
470 pr_debug("%s: [%d] %08x %08x(%x)\n", __func__,
471 i, da, pa, bytes);
472
473 iotlb_init_entry(&e, da, pa, flags);
474 err = iopgtable_store_entry(obj, &e);
475 if (err)
476 goto err_out;
477
478 da += bytes;
479 }
480 return 0;
481
482err_out:
483 da = new->da_start;
484
485 for_each_sg(sgt->sgl, sg, i, j) {
486 size_t bytes;
487
488 bytes = iopgtable_clear_entry(obj, da);
489
490 BUG_ON(!iopgsz_ok(bytes));
491
492 da += bytes;
493 }
494 return err;
495}
496
497/* release 'da' <-> 'pa' mapping */
498static void unmap_iovm_area(struct iommu *obj, struct iovm_struct *area)
499{
500 u32 start;
501 size_t total = area->da_end - area->da_start;
502
503 BUG_ON((!total) || !IS_ALIGNED(total, PAGE_SIZE));
504
505 start = area->da_start;
506 while (total > 0) {
507 size_t bytes;
508
509 bytes = iopgtable_clear_entry(obj, start);
510 if (bytes == 0)
511 bytes = PAGE_SIZE;
512 else
513 dev_dbg(obj->dev, "%s: unmap %08x(%x) %08x\n",
514 __func__, start, bytes, area->flags);
515
516 BUG_ON(!IS_ALIGNED(bytes, PAGE_SIZE));
517
518 total -= bytes;
519 start += bytes;
520 }
521 BUG_ON(total);
522}
523
524/* template function for all unmapping */
525static struct sg_table *unmap_vm_area(struct iommu *obj, const u32 da,
526 void (*fn)(const void *), u32 flags)
527{
528 struct sg_table *sgt = NULL;
529 struct iovm_struct *area;
530
531 if (!IS_ALIGNED(da, PAGE_SIZE)) {
532 dev_err(obj->dev, "%s: alignment err(%08x)\n", __func__, da);
533 return NULL;
534 }
535
536 mutex_lock(&obj->mmap_lock);
537
538 area = __find_iovm_area(obj, da);
539 if (!area) {
540 dev_dbg(obj->dev, "%s: no da area(%08x)\n", __func__, da);
541 goto out;
542 }
543
544 if ((area->flags & flags) != flags) {
545 dev_err(obj->dev, "%s: wrong flags(%08x)\n", __func__,
546 area->flags);
547 goto out;
548 }
549 sgt = (struct sg_table *)area->sgt;
550
551 unmap_iovm_area(obj, area);
552
553 fn(area->va);
554
555 dev_dbg(obj->dev, "%s: %08x-%08x-%08x(%x) %08x\n", __func__,
556 area->da_start, da, area->da_end,
557 area->da_end - area->da_start, area->flags);
558
559 free_iovm_area(obj, area);
560out:
561 mutex_unlock(&obj->mmap_lock);
562
563 return sgt;
564}
565
566static u32 map_iommu_region(struct iommu *obj, u32 da,
567 const struct sg_table *sgt, void *va, size_t bytes, u32 flags)
568{
569 int err = -ENOMEM;
570 struct iovm_struct *new;
571
572 mutex_lock(&obj->mmap_lock);
573
574 new = alloc_iovm_area(obj, da, bytes, flags);
575 if (IS_ERR(new)) {
576 err = PTR_ERR(new);
577 goto err_alloc_iovma;
578 }
579 new->va = va;
580 new->sgt = sgt;
581
582 if (map_iovm_area(obj, new, sgt, new->flags))
583 goto err_map;
584
585 mutex_unlock(&obj->mmap_lock);
586
587 dev_dbg(obj->dev, "%s: da:%08x(%x) flags:%08x va:%p\n",
588 __func__, new->da_start, bytes, new->flags, va);
589
590 return new->da_start;
591
592err_map:
593 free_iovm_area(obj, new);
594err_alloc_iovma:
595 mutex_unlock(&obj->mmap_lock);
596 return err;
597}
598
599static inline u32 __iommu_vmap(struct iommu *obj, u32 da,
600 const struct sg_table *sgt, void *va, size_t bytes, u32 flags)
601{
602 return map_iommu_region(obj, da, sgt, va, bytes, flags);
603}
604
605/**
606 * iommu_vmap - (d)-(p)-(v) address mapper
607 * @obj: objective iommu
608 * @sgt: address of scatter gather table
609 * @flags: iovma and page property
610 *
611 * Creates 1-n-1 mapping with given @sgt and returns @da.
612 * All @sgt element must be io page size aligned.
613 */
614u32 iommu_vmap(struct iommu *obj, u32 da, const struct sg_table *sgt,
615 u32 flags)
616{
617 size_t bytes;
618 void *va;
619
620 if (!obj || !obj->dev || !sgt)
621 return -EINVAL;
622
623 bytes = sgtable_len(sgt);
624 if (!bytes)
625 return -EINVAL;
626 bytes = PAGE_ALIGN(bytes);
627
628 va = vmap_sg(sgt);
629 if (IS_ERR(va))
630 return PTR_ERR(va);
631
632 flags &= IOVMF_HW_MASK;
633 flags |= IOVMF_DISCONT;
634 flags |= IOVMF_MMIO;
635 flags |= (da ? IOVMF_DA_FIXED : IOVMF_DA_ANON);
636
637 da = __iommu_vmap(obj, da, sgt, va, bytes, flags);
638 if (IS_ERR_VALUE(da))
639 vunmap_sg(va);
640
641 return da;
642}
643EXPORT_SYMBOL_GPL(iommu_vmap);
644
645/**
646 * iommu_vunmap - release virtual mapping obtained by 'iommu_vmap()'
647 * @obj: objective iommu
648 * @da: iommu device virtual address
649 *
650 * Free the iommu virtually contiguous memory area starting at
651 * @da, which was returned by 'iommu_vmap()'.
652 */
653struct sg_table *iommu_vunmap(struct iommu *obj, u32 da)
654{
655 struct sg_table *sgt;
656 /*
657 * 'sgt' is allocated before 'iommu_vmalloc()' is called.
658 * Just returns 'sgt' to the caller to free
659 */
660 sgt = unmap_vm_area(obj, da, vunmap_sg, IOVMF_DISCONT | IOVMF_MMIO);
661 if (!sgt)
662 dev_dbg(obj->dev, "%s: No sgt\n", __func__);
663 return sgt;
664}
665EXPORT_SYMBOL_GPL(iommu_vunmap);
666
667/**
668 * iommu_vmalloc - (d)-(p)-(v) address allocator and mapper
669 * @obj: objective iommu
670 * @da: contiguous iommu virtual memory
671 * @bytes: allocation size
672 * @flags: iovma and page property
673 *
674 * Allocate @bytes linearly and creates 1-n-1 mapping and returns
675 * @da again, which might be adjusted if 'IOVMF_DA_ANON' is set.
676 */
677u32 iommu_vmalloc(struct iommu *obj, u32 da, size_t bytes, u32 flags)
678{
679 void *va;
680 struct sg_table *sgt;
681
682 if (!obj || !obj->dev || !bytes)
683 return -EINVAL;
684
685 bytes = PAGE_ALIGN(bytes);
686
687 va = vmalloc(bytes);
688 if (!va)
689 return -ENOMEM;
690
691 sgt = sgtable_alloc(bytes, flags);
692 if (IS_ERR(sgt)) {
693 da = PTR_ERR(sgt);
694 goto err_sgt_alloc;
695 }
696 sgtable_fill_vmalloc(sgt, va);
697
698 flags &= IOVMF_HW_MASK;
699 flags |= IOVMF_DISCONT;
700 flags |= IOVMF_ALLOC;
701 flags |= (da ? IOVMF_DA_FIXED : IOVMF_DA_ANON);
702
703 da = __iommu_vmap(obj, da, sgt, va, bytes, flags);
704 if (IS_ERR_VALUE(da))
705 goto err_iommu_vmap;
706
707 return da;
708
709err_iommu_vmap:
710 sgtable_drain_vmalloc(sgt);
711 sgtable_free(sgt);
712err_sgt_alloc:
713 vfree(va);
714 return da;
715}
716EXPORT_SYMBOL_GPL(iommu_vmalloc);
717
718/**
719 * iommu_vfree - release memory allocated by 'iommu_vmalloc()'
720 * @obj: objective iommu
721 * @da: iommu device virtual address
722 *
723 * Frees the iommu virtually continuous memory area starting at
724 * @da, as obtained from 'iommu_vmalloc()'.
725 */
726void iommu_vfree(struct iommu *obj, const u32 da)
727{
728 struct sg_table *sgt;
729
730 sgt = unmap_vm_area(obj, da, vfree, IOVMF_DISCONT | IOVMF_ALLOC);
731 if (!sgt)
732 dev_dbg(obj->dev, "%s: No sgt\n", __func__);
733 sgtable_free(sgt);
734}
735EXPORT_SYMBOL_GPL(iommu_vfree);
736
737static u32 __iommu_kmap(struct iommu *obj, u32 da, u32 pa, void *va,
738 size_t bytes, u32 flags)
739{
740 struct sg_table *sgt;
741
742 sgt = sgtable_alloc(bytes, flags);
743 if (IS_ERR(sgt))
744 return PTR_ERR(sgt);
745
746 sgtable_fill_kmalloc(sgt, pa, bytes);
747
748 da = map_iommu_region(obj, da, sgt, va, bytes, flags);
749 if (IS_ERR_VALUE(da)) {
750 sgtable_drain_kmalloc(sgt);
751 sgtable_free(sgt);
752 }
753
754 return da;
755}
756
757/**
758 * iommu_kmap - (d)-(p)-(v) address mapper
759 * @obj: objective iommu
760 * @da: contiguous iommu virtual memory
761 * @pa: contiguous physical memory
762 * @flags: iovma and page property
763 *
764 * Creates 1-1-1 mapping and returns @da again, which can be
765 * adjusted if 'IOVMF_DA_ANON' is set.
766 */
767u32 iommu_kmap(struct iommu *obj, u32 da, u32 pa, size_t bytes,
768 u32 flags)
769{
770 void *va;
771
772 if (!obj || !obj->dev || !bytes)
773 return -EINVAL;
774
775 bytes = PAGE_ALIGN(bytes);
776
777 va = ioremap(pa, bytes);
778 if (!va)
779 return -ENOMEM;
780
781 flags &= IOVMF_HW_MASK;
782 flags |= IOVMF_LINEAR;
783 flags |= IOVMF_MMIO;
784 flags |= (da ? IOVMF_DA_FIXED : IOVMF_DA_ANON);
785
786 da = __iommu_kmap(obj, da, pa, va, bytes, flags);
787 if (IS_ERR_VALUE(da))
788 iounmap(va);
789
790 return da;
791}
792EXPORT_SYMBOL_GPL(iommu_kmap);
793
794/**
795 * iommu_kunmap - release virtual mapping obtained by 'iommu_kmap()'
796 * @obj: objective iommu
797 * @da: iommu device virtual address
798 *
799 * Frees the iommu virtually contiguous memory area starting at
800 * @da, which was passed to and was returned by'iommu_kmap()'.
801 */
802void iommu_kunmap(struct iommu *obj, u32 da)
803{
804 struct sg_table *sgt;
805 typedef void (*func_t)(const void *);
806
807 sgt = unmap_vm_area(obj, da, (func_t)__iounmap,
808 IOVMF_LINEAR | IOVMF_MMIO);
809 if (!sgt)
810 dev_dbg(obj->dev, "%s: No sgt\n", __func__);
811 sgtable_free(sgt);
812}
813EXPORT_SYMBOL_GPL(iommu_kunmap);
814
815/**
816 * iommu_kmalloc - (d)-(p)-(v) address allocator and mapper
817 * @obj: objective iommu
818 * @da: contiguous iommu virtual memory
819 * @bytes: bytes for allocation
820 * @flags: iovma and page property
821 *
822 * Allocate @bytes linearly and creates 1-1-1 mapping and returns
823 * @da again, which might be adjusted if 'IOVMF_DA_ANON' is set.
824 */
825u32 iommu_kmalloc(struct iommu *obj, u32 da, size_t bytes, u32 flags)
826{
827 void *va;
828 u32 pa;
829
830 if (!obj || !obj->dev || !bytes)
831 return -EINVAL;
832
833 bytes = PAGE_ALIGN(bytes);
834
835 va = kmalloc(bytes, GFP_KERNEL | GFP_DMA);
836 if (!va)
837 return -ENOMEM;
838 pa = virt_to_phys(va);
839
840 flags &= IOVMF_HW_MASK;
841 flags |= IOVMF_LINEAR;
842 flags |= IOVMF_ALLOC;
843 flags |= (da ? IOVMF_DA_FIXED : IOVMF_DA_ANON);
844
845 da = __iommu_kmap(obj, da, pa, va, bytes, flags);
846 if (IS_ERR_VALUE(da))
847 kfree(va);
848
849 return da;
850}
851EXPORT_SYMBOL_GPL(iommu_kmalloc);
852
853/**
854 * iommu_kfree - release virtual mapping obtained by 'iommu_kmalloc()'
855 * @obj: objective iommu
856 * @da: iommu device virtual address
857 *
858 * Frees the iommu virtually contiguous memory area starting at
859 * @da, which was passed to and was returned by'iommu_kmalloc()'.
860 */
861void iommu_kfree(struct iommu *obj, u32 da)
862{
863 struct sg_table *sgt;
864
865 sgt = unmap_vm_area(obj, da, kfree, IOVMF_LINEAR | IOVMF_ALLOC);
866 if (!sgt)
867 dev_dbg(obj->dev, "%s: No sgt\n", __func__);
868 sgtable_free(sgt);
869}
870EXPORT_SYMBOL_GPL(iommu_kfree);
871
872
873static int __init iovmm_init(void)
874{
875 const unsigned long flags = SLAB_HWCACHE_ALIGN;
876 struct kmem_cache *p;
877
878 p = kmem_cache_create("iovm_area_cache", sizeof(struct iovm_struct), 0,
879 flags, NULL);
880 if (!p)
881 return -ENOMEM;
882 iovm_area_cachep = p;
883
884 return 0;
885}
886module_init(iovmm_init);
887
888static void __exit iovmm_exit(void)
889{
890 kmem_cache_destroy(iovm_area_cachep);
891}
892module_exit(iovmm_exit);
893
894MODULE_DESCRIPTION("omap iommu: simple virtual address space management");
895MODULE_AUTHOR("Hiroshi DOYU <Hiroshi.DOYU@nokia.com>");
896MODULE_LICENSE("GPL v2");
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-12 03:11:33 -0500