Merge branch 'fixes-dss' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into fixes

11 files changed, 276 insertions, 28 deletions

diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index 69ab1c069134..b009f17dee56 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -4,7 +4,7 @@
 
 # Common support
 obj-y := id.o io.o control.o mux.o devices.o serial.o gpmc.o timer.o pm.o \
-         common.o gpio.o dma.o wd_timer.o
+         common.o gpio.o dma.o wd_timer.o display.o
 
 omap-2-3-common                         = irq.o sdrc.o
 hwmod-common                            = omap_hwmod.o \
@@ -264,7 +264,4 @@ smsc911x-$(CONFIG_SMSC911X)		:= gpmc-smsc911x.o
 obj-y                                   += $(smsc911x-m) $(smsc911x-y)
 obj-$(CONFIG_ARCH_OMAP4)                += hwspinlock.o
 
-disp-$(CONFIG_OMAP2_DSS)                := display.o
-obj-y                                   += $(disp-m) $(disp-y)
-
 obj-y                                   += common-board-devices.o twl-common.o
diff --git a/arch/arm/mach-omap2/display.c b/arch/arm/mach-omap2/display.c
index adb2756e242f..dce9905d64bb 100644
--- a/arch/arm/mach-omap2/display.c
+++ b/arch/arm/mach-omap2/display.c
@@ -27,8 +27,35 @@
 #include <plat/omap_hwmod.h>
 #include <plat/omap_device.h>
 #include <plat/omap-pm.h>
+#include <plat/common.h>
 
 #include "control.h"
+#include "display.h"
+
+#define DISPC_CONTROL           0x0040
+#define DISPC_CONTROL2          0x0238
+#define DISPC_IRQSTATUS         0x0018
+
+#define DSS_SYSCONFIG           0x10
+#define DSS_SYSSTATUS           0x14
+#define DSS_CONTROL             0x40
+#define DSS_SDI_CONTROL         0x44
+#define DSS_PLL_CONTROL         0x48
+
+#define LCD_EN_MASK             (0x1 << 0)
+#define DIGIT_EN_MASK           (0x1 << 1)
+
+#define FRAMEDONE_IRQ_SHIFT     0
+#define EVSYNC_EVEN_IRQ_SHIFT   2
+#define EVSYNC_ODD_IRQ_SHIFT    3
+#define FRAMEDONE2_IRQ_SHIFT    22
+#define FRAMEDONETV_IRQ_SHIFT   24
+
+/*
+ * FRAMEDONE_IRQ_TIMEOUT: how long (in milliseconds) to wait during DISPC
+ *     reset before deciding that something has gone wrong
+ */
+#define FRAMEDONE_IRQ_TIMEOUT           100
 
 static struct platform_device omap_display_device = {
         .name          = "omapdss",
@@ -172,3 +199,135 @@ int __init omap_display_init(struct omap_dss_board_info *board_data)
 
         return r;
 }
+
+static void dispc_disable_outputs(void)
+{
+        u32 v, irq_mask = 0;
+        bool lcd_en, digit_en, lcd2_en = false;
+        int i;
+        struct omap_dss_dispc_dev_attr *da;
+        struct omap_hwmod *oh;
+
+        oh = omap_hwmod_lookup("dss_dispc");
+        if (!oh) {
+                WARN(1, "display: could not disable outputs during reset - could not find dss_dispc hwmod\n");
+                return;
+        }
+
+        if (!oh->dev_attr) {
+                pr_err("display: could not disable outputs during reset due to missing dev_attr\n");
+                return;
+        }
+
+        da = (struct omap_dss_dispc_dev_attr *)oh->dev_attr;
+
+        /* store value of LCDENABLE and DIGITENABLE bits */
+        v = omap_hwmod_read(oh, DISPC_CONTROL);
+        lcd_en = v & LCD_EN_MASK;
+        digit_en = v & DIGIT_EN_MASK;
+
+        /* store value of LCDENABLE for LCD2 */
+        if (da->manager_count > 2) {
+                v = omap_hwmod_read(oh, DISPC_CONTROL2);
+                lcd2_en = v & LCD_EN_MASK;
+        }
+
+        if (!(lcd_en | digit_en | lcd2_en))
+                return; /* no managers currently enabled */
+
+        /*
+         * If any manager was enabled, we need to disable it before
+         * DSS clocks are disabled or DISPC module is reset
+         */
+        if (lcd_en)
+                irq_mask |= 1 << FRAMEDONE_IRQ_SHIFT;
+
+        if (digit_en) {
+                if (da->has_framedonetv_irq) {
+                        irq_mask |= 1 << FRAMEDONETV_IRQ_SHIFT;
+                } else {
+                        irq_mask |= 1 << EVSYNC_EVEN_IRQ_SHIFT |
+                                1 << EVSYNC_ODD_IRQ_SHIFT;
+                }
+        }
+
+        if (lcd2_en)
+                irq_mask |= 1 << FRAMEDONE2_IRQ_SHIFT;
+
+        /*
+         * clear any previous FRAMEDONE, FRAMEDONETV,
+         * EVSYNC_EVEN/ODD or FRAMEDONE2 interrupts
+         */
+        omap_hwmod_write(irq_mask, oh, DISPC_IRQSTATUS);
+
+        /* disable LCD and TV managers */
+        v = omap_hwmod_read(oh, DISPC_CONTROL);
+        v &= ~(LCD_EN_MASK | DIGIT_EN_MASK);
+        omap_hwmod_write(v, oh, DISPC_CONTROL);
+
+        /* disable LCD2 manager */
+        if (da->manager_count > 2) {
+                v = omap_hwmod_read(oh, DISPC_CONTROL2);
+                v &= ~LCD_EN_MASK;
+                omap_hwmod_write(v, oh, DISPC_CONTROL2);
+        }
+
+        i = 0;
+        while ((omap_hwmod_read(oh, DISPC_IRQSTATUS) & irq_mask) !=
+               irq_mask) {
+                i++;
+                if (i > FRAMEDONE_IRQ_TIMEOUT) {
+                        pr_err("didn't get FRAMEDONE1/2 or TV interrupt\n");
+                        break;
+                }
+                mdelay(1);
+        }
+}
+
+#define MAX_MODULE_SOFTRESET_WAIT       10000
+int omap_dss_reset(struct omap_hwmod *oh)
+{
+        struct omap_hwmod_opt_clk *oc;
+        int c = 0;
+        int i, r;
+
+        if (!(oh->class->sysc->sysc_flags & SYSS_HAS_RESET_STATUS)) {
+                pr_err("dss_core: hwmod data doesn't contain reset data\n");
+                return -EINVAL;
+        }
+
+        for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++)
+                if (oc->_clk)
+                        clk_enable(oc->_clk);
+
+        dispc_disable_outputs();
+
+        /* clear SDI registers */
+        if (cpu_is_omap3430()) {
+                omap_hwmod_write(0x0, oh, DSS_SDI_CONTROL);
+                omap_hwmod_write(0x0, oh, DSS_PLL_CONTROL);
+        }
+
+        /*
+         * clear DSS_CONTROL register to switch DSS clock sources to
+         * PRCM clock, if any
+         */
+        omap_hwmod_write(0x0, oh, DSS_CONTROL);
+
+        omap_test_timeout((omap_hwmod_read(oh, oh->class->sysc->syss_offs)
+                                & SYSS_RESETDONE_MASK),
+                        MAX_MODULE_SOFTRESET_WAIT, c);
+
+        if (c == MAX_MODULE_SOFTRESET_WAIT)
+                pr_warning("dss_core: waiting for reset to finish failed\n");
+        else
+                pr_debug("dss_core: softreset done\n");
+
+        for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++)
+                if (oc->_clk)
+                        clk_disable(oc->_clk);
+
+        r = (c == MAX_MODULE_SOFTRESET_WAIT) ? -ETIMEDOUT : 0;
+
+        return r;
+}
diff --git a/arch/arm/mach-omap2/display.h b/arch/arm/mach-omap2/display.h
new file mode 100644
index 000000000000..b871b017b352
--- /dev/null
+++ b/arch/arm/mach-omap2/display.h
@@ -0,0 +1,29 @@
+/*
+ * display.h - OMAP2+ integration-specific DSS header
+ *
+ * Copyright (C) 2011 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef __ARCH_ARM_MACH_OMAP2_DISPLAY_H
+#define __ARCH_ARM_MACH_OMAP2_DISPLAY_H
+
+#include <linux/kernel.h>
+
+struct omap_dss_dispc_dev_attr {
+        u8      manager_count;
+        bool    has_framedonetv_irq;
+};
+
+#endif
diff --git a/arch/arm/mach-omap2/omap_hwmod_2420_data.c b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
index 6d7206213525..a5409ce3f323 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2420_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
@@ -875,6 +875,10 @@ static struct omap_hwmod_ocp_if *omap2420_dss_slaves[] = {
 };
 
 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
+        /*
+         * The DSS HW needs all DSS clocks enabled during reset. The dss_core
+         * driver does not use these clocks.
+         */
         { .role = "tv_clk", .clk = "dss_54m_fck" },
         { .role = "sys_clk", .clk = "dss2_fck" },
 };
@@ -899,7 +903,7 @@ static struct omap_hwmod omap2420_dss_core_hwmod = {
         .slaves_cnt     = ARRAY_SIZE(omap2420_dss_slaves),
         .masters        = omap2420_dss_masters,
         .masters_cnt    = ARRAY_SIZE(omap2420_dss_masters),
-        .flags          = HWMOD_NO_IDLEST,
+        .flags          = HWMOD_NO_IDLEST | HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 };
 
 /* l4_core -> dss_dispc */
@@ -939,6 +943,7 @@ static struct omap_hwmod omap2420_dss_dispc_hwmod = {
         .slaves         = omap2420_dss_dispc_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap2420_dss_dispc_slaves),
         .flags          = HWMOD_NO_IDLEST,
+        .dev_attr       = &omap2_3_dss_dispc_dev_attr
 };
 
 /* l4_core -> dss_rfbi */
@@ -961,6 +966,10 @@ static struct omap_hwmod_ocp_if *omap2420_dss_rfbi_slaves[] = {
         &omap2420_l4_core__dss_rfbi,
 };
 
+static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
+        { .role = "ick", .clk = "dss_ick" },
+};
+
 static struct omap_hwmod omap2420_dss_rfbi_hwmod = {
         .name           = "dss_rfbi",
         .class          = &omap2_rfbi_hwmod_class,
@@ -972,6 +981,8 @@ static struct omap_hwmod omap2420_dss_rfbi_hwmod = {
                         .module_offs = CORE_MOD,
                 },
         },
+        .opt_clks       = dss_rfbi_opt_clks,
+        .opt_clks_cnt   = ARRAY_SIZE(dss_rfbi_opt_clks),
         .slaves         = omap2420_dss_rfbi_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap2420_dss_rfbi_slaves),
         .flags          = HWMOD_NO_IDLEST,
@@ -981,7 +992,7 @@ static struct omap_hwmod omap2420_dss_rfbi_hwmod = {
 static struct omap_hwmod_ocp_if omap2420_l4_core__dss_venc = {
         .master         = &omap2420_l4_core_hwmod,
         .slave          = &omap2420_dss_venc_hwmod,
-        .clk            = "dss_54m_fck",
+        .clk            = "dss_ick",
         .addr           = omap2_dss_venc_addrs,
         .fw = {
                 .omap2 = {
@@ -1001,7 +1012,7 @@ static struct omap_hwmod_ocp_if *omap2420_dss_venc_slaves[] = {
 static struct omap_hwmod omap2420_dss_venc_hwmod = {
         .name           = "dss_venc",
         .class          = &omap2_venc_hwmod_class,
-        .main_clk       = "dss1_fck",
+        .main_clk       = "dss_54m_fck",
         .prcm           = {
                 .omap2 = {
                         .prcm_reg_id = 1,
diff --git a/arch/arm/mach-omap2/omap_hwmod_2430_data.c b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
index a2580d01c3ff..c4f56cb60d7d 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
@@ -942,6 +942,10 @@ static struct omap_hwmod_ocp_if *omap2430_dss_slaves[] = {
 };
 
 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
+        /*
+         * The DSS HW needs all DSS clocks enabled during reset. The dss_core
+         * driver does not use these clocks.
+         */
         { .role = "tv_clk", .clk = "dss_54m_fck" },
         { .role = "sys_clk", .clk = "dss2_fck" },
 };
@@ -966,7 +970,7 @@ static struct omap_hwmod omap2430_dss_core_hwmod = {
         .slaves_cnt     = ARRAY_SIZE(omap2430_dss_slaves),
         .masters        = omap2430_dss_masters,
         .masters_cnt    = ARRAY_SIZE(omap2430_dss_masters),
-        .flags          = HWMOD_NO_IDLEST,
+        .flags          = HWMOD_NO_IDLEST | HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 };
 
 /* l4_core -> dss_dispc */
@@ -1000,6 +1004,7 @@ static struct omap_hwmod omap2430_dss_dispc_hwmod = {
         .slaves         = omap2430_dss_dispc_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap2430_dss_dispc_slaves),
         .flags          = HWMOD_NO_IDLEST,
+        .dev_attr       = &omap2_3_dss_dispc_dev_attr
 };
 
 /* l4_core -> dss_rfbi */
@@ -1016,6 +1021,10 @@ static struct omap_hwmod_ocp_if *omap2430_dss_rfbi_slaves[] = {
         &omap2430_l4_core__dss_rfbi,
 };
 
+static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
+        { .role = "ick", .clk = "dss_ick" },
+};
+
 static struct omap_hwmod omap2430_dss_rfbi_hwmod = {
         .name           = "dss_rfbi",
         .class          = &omap2_rfbi_hwmod_class,
@@ -1027,6 +1036,8 @@ static struct omap_hwmod omap2430_dss_rfbi_hwmod = {
                         .module_offs = CORE_MOD,
                 },
         },
+        .opt_clks       = dss_rfbi_opt_clks,
+        .opt_clks_cnt   = ARRAY_SIZE(dss_rfbi_opt_clks),
         .slaves         = omap2430_dss_rfbi_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap2430_dss_rfbi_slaves),
         .flags          = HWMOD_NO_IDLEST,
@@ -1036,7 +1047,7 @@ static struct omap_hwmod omap2430_dss_rfbi_hwmod = {
 static struct omap_hwmod_ocp_if omap2430_l4_core__dss_venc = {
         .master         = &omap2430_l4_core_hwmod,
         .slave          = &omap2430_dss_venc_hwmod,
-        .clk            = "dss_54m_fck",
+        .clk            = "dss_ick",
         .addr           = omap2_dss_venc_addrs,
         .flags          = OCPIF_SWSUP_IDLE,
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
@@ -1050,7 +1061,7 @@ static struct omap_hwmod_ocp_if *omap2430_dss_venc_slaves[] = {
 static struct omap_hwmod omap2430_dss_venc_hwmod = {
         .name           = "dss_venc",
         .class          = &omap2_venc_hwmod_class,
-        .main_clk       = "dss1_fck",
+        .main_clk       = "dss_54m_fck",
         .prcm           = {
                 .omap2 = {
                         .prcm_reg_id = 1,
diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c
index c451729d289a..c11273da5dcc 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c
@@ -11,6 +11,7 @@
 #include <plat/omap_hwmod.h>
 #include <plat/serial.h>
 #include <plat/dma.h>
+#include <plat/common.h>
 
 #include <mach/irqs.h>
 
@@ -43,13 +44,15 @@ static struct omap_hwmod_class_sysconfig omap2_dss_sysc = {
         .rev_offs       = 0x0000,
         .sysc_offs      = 0x0010,
         .syss_offs      = 0x0014,
-        .sysc_flags     = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
+        .sysc_flags     = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
+                           SYSS_HAS_RESET_STATUS),
         .sysc_fields    = &omap_hwmod_sysc_type1,
 };
 
 struct omap_hwmod_class omap2_dss_hwmod_class = {
         .name   = "dss",
         .sysc   = &omap2_dss_sysc,
+        .reset  = omap_dss_reset,
 };
 
 /*
diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
index bc9035ec87fc..7f8915ad5099 100644
--- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
@@ -1369,9 +1369,14 @@ static struct omap_hwmod_ocp_if *omap3xxx_dss_slaves[] = {
 };
 
 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
-        { .role = "tv_clk", .clk = "dss_tv_fck" },
-        { .role = "video_clk", .clk = "dss_96m_fck" },
+        /*
+         * The DSS HW needs all DSS clocks enabled during reset. The dss_core
+         * driver does not use these clocks.
+         */
         { .role = "sys_clk", .clk = "dss2_alwon_fck" },
+        { .role = "tv_clk", .clk = "dss_tv_fck" },
+        /* required only on OMAP3430 */
+        { .role = "tv_dac_clk", .clk = "dss_96m_fck" },
 };
 
 static struct omap_hwmod omap3430es1_dss_core_hwmod = {
@@ -1394,11 +1399,12 @@ static struct omap_hwmod omap3430es1_dss_core_hwmod = {
         .slaves_cnt     = ARRAY_SIZE(omap3430es1_dss_slaves),
         .masters        = omap3xxx_dss_masters,
         .masters_cnt    = ARRAY_SIZE(omap3xxx_dss_masters),
-        .flags          = HWMOD_NO_IDLEST,
+        .flags          = HWMOD_NO_IDLEST | HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 };
 
 static struct omap_hwmod omap3xxx_dss_core_hwmod = {
         .name           = "dss_core",
+        .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
         .class          = &omap2_dss_hwmod_class,
         .main_clk       = "dss1_alwon_fck", /* instead of dss_fck */
         .sdma_reqs      = omap3xxx_dss_sdma_chs,
@@ -1456,6 +1462,7 @@ static struct omap_hwmod omap3xxx_dss_dispc_hwmod = {
         .slaves         = omap3xxx_dss_dispc_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap3xxx_dss_dispc_slaves),
         .flags          = HWMOD_NO_IDLEST,
+        .dev_attr       = &omap2_3_dss_dispc_dev_attr
 };
 
 /*
@@ -1486,6 +1493,7 @@ static struct omap_hwmod_addr_space omap3xxx_dss_dsi1_addrs[] = {
 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dsi1 = {
         .master         = &omap3xxx_l4_core_hwmod,
         .slave          = &omap3xxx_dss_dsi1_hwmod,
+        .clk            = "dss_ick",
         .addr           = omap3xxx_dss_dsi1_addrs,
         .fw = {
                 .omap2 = {
@@ -1502,6 +1510,10 @@ static struct omap_hwmod_ocp_if *omap3xxx_dss_dsi1_slaves[] = {
         &omap3xxx_l4_core__dss_dsi1,
 };
 
+static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = {
+        { .role = "sys_clk", .clk = "dss2_alwon_fck" },
+};
+
 static struct omap_hwmod omap3xxx_dss_dsi1_hwmod = {
         .name           = "dss_dsi1",
         .class          = &omap3xxx_dsi_hwmod_class,
@@ -1514,6 +1526,8 @@ static struct omap_hwmod omap3xxx_dss_dsi1_hwmod = {
                         .module_offs = OMAP3430_DSS_MOD,
                 },
         },
+        .opt_clks       = dss_dsi1_opt_clks,
+        .opt_clks_cnt   = ARRAY_SIZE(dss_dsi1_opt_clks),
         .slaves         = omap3xxx_dss_dsi1_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap3xxx_dss_dsi1_slaves),
         .flags          = HWMOD_NO_IDLEST,
@@ -1540,6 +1554,10 @@ static struct omap_hwmod_ocp_if *omap3xxx_dss_rfbi_slaves[] = {
         &omap3xxx_l4_core__dss_rfbi,
 };
 
+static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
+        { .role = "ick", .clk = "dss_ick" },
+};
+
 static struct omap_hwmod omap3xxx_dss_rfbi_hwmod = {
         .name           = "dss_rfbi",
         .class          = &omap2_rfbi_hwmod_class,
@@ -1551,6 +1569,8 @@ static struct omap_hwmod omap3xxx_dss_rfbi_hwmod = {
                         .module_offs = OMAP3430_DSS_MOD,
                 },
         },
+        .opt_clks       = dss_rfbi_opt_clks,
+        .opt_clks_cnt   = ARRAY_SIZE(dss_rfbi_opt_clks),
         .slaves         = omap3xxx_dss_rfbi_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap3xxx_dss_rfbi_slaves),
         .flags          = HWMOD_NO_IDLEST,
@@ -1560,7 +1580,7 @@ static struct omap_hwmod omap3xxx_dss_rfbi_hwmod = {
 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_venc = {
         .master         = &omap3xxx_l4_core_hwmod,
         .slave          = &omap3xxx_dss_venc_hwmod,
-        .clk            = "dss_tv_fck",
+        .clk            = "dss_ick",
         .addr           = omap2_dss_venc_addrs,
         .fw = {
                 .omap2 = {
@@ -1578,10 +1598,15 @@ static struct omap_hwmod_ocp_if *omap3xxx_dss_venc_slaves[] = {
         &omap3xxx_l4_core__dss_venc,
 };
 
+static struct omap_hwmod_opt_clk dss_venc_opt_clks[] = {
+        /* required only on OMAP3430 */
+        { .role = "tv_dac_clk", .clk = "dss_96m_fck" },
+};
+
 static struct omap_hwmod omap3xxx_dss_venc_hwmod = {
         .name           = "dss_venc",
         .class          = &omap2_venc_hwmod_class,
-        .main_clk       = "dss1_alwon_fck",
+        .main_clk       = "dss_tv_fck",
         .prcm           = {
                 .omap2 = {
                         .prcm_reg_id = 1,
@@ -1589,6 +1614,8 @@ static struct omap_hwmod omap3xxx_dss_venc_hwmod = {
                         .module_offs = OMAP3430_DSS_MOD,
                 },
         },
+        .opt_clks       = dss_venc_opt_clks,
+        .opt_clks_cnt   = ARRAY_SIZE(dss_venc_opt_clks),
         .slaves         = omap3xxx_dss_venc_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap3xxx_dss_venc_slaves),
         .flags          = HWMOD_NO_IDLEST,
diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
index 7695e5d43316..daaf165af696 100644
--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
@@ -30,6 +30,7 @@
 #include <plat/mmc.h>
 #include <plat/i2c.h>
 #include <plat/dmtimer.h>
+#include <plat/common.h>
 
 #include "omap_hwmod_common_data.h"
 
@@ -1187,6 +1188,7 @@ static struct omap_hwmod_class_sysconfig omap44xx_dss_sysc = {
 static struct omap_hwmod_class omap44xx_dss_hwmod_class = {
         .name   = "dss",
         .sysc   = &omap44xx_dss_sysc,
+        .reset  = omap_dss_reset,
 };
 
 /* dss */
@@ -1240,12 +1242,12 @@ static struct omap_hwmod_ocp_if *omap44xx_dss_slaves[] = {
 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
         { .role = "sys_clk", .clk = "dss_sys_clk" },
         { .role = "tv_clk", .clk = "dss_tv_clk" },
-        { .role = "dss_clk", .clk = "dss_dss_clk" },
-        { .role = "video_clk", .clk = "dss_48mhz_clk" },
+        { .role = "hdmi_clk", .clk = "dss_48mhz_clk" },
 };
 
 static struct omap_hwmod omap44xx_dss_hwmod = {
         .name           = "dss_core",
+        .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
         .class          = &omap44xx_dss_hwmod_class,
         .clkdm_name     = "l3_dss_clkdm",
         .main_clk       = "dss_dss_clk",
@@ -1325,6 +1327,11 @@ static struct omap_hwmod_addr_space omap44xx_dss_dispc_addrs[] = {
         { }
 };
 
+static struct omap_dss_dispc_dev_attr omap44xx_dss_dispc_dev_attr = {
+        .manager_count          = 3,
+        .has_framedonetv_irq    = 1
+};
+
 /* l4_per -> dss_dispc */
 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dispc = {
         .master         = &omap44xx_l4_per_hwmod,
@@ -1340,12 +1347,6 @@ static struct omap_hwmod_ocp_if *omap44xx_dss_dispc_slaves[] = {
         &omap44xx_l4_per__dss_dispc,
 };
 
-static struct omap_hwmod_opt_clk dss_dispc_opt_clks[] = {
-        { .role = "sys_clk", .clk = "dss_sys_clk" },
-        { .role = "tv_clk", .clk = "dss_tv_clk" },
-        { .role = "hdmi_clk", .clk = "dss_48mhz_clk" },
-};
-
 static struct omap_hwmod omap44xx_dss_dispc_hwmod = {
         .name           = "dss_dispc",
         .class          = &omap44xx_dispc_hwmod_class,
@@ -1359,10 +1360,9 @@ static struct omap_hwmod omap44xx_dss_dispc_hwmod = {
                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
                 },
         },
-        .opt_clks       = dss_dispc_opt_clks,
-        .opt_clks_cnt   = ARRAY_SIZE(dss_dispc_opt_clks),
         .slaves         = omap44xx_dss_dispc_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap44xx_dss_dispc_slaves),
+        .dev_attr       = &omap44xx_dss_dispc_dev_attr
 };
 
 /*
@@ -1624,7 +1624,7 @@ static struct omap_hwmod omap44xx_dss_hdmi_hwmod = {
         .clkdm_name     = "l3_dss_clkdm",
         .mpu_irqs       = omap44xx_dss_hdmi_irqs,
         .sdma_reqs      = omap44xx_dss_hdmi_sdma_reqs,
-        .main_clk       = "dss_dss_clk",
+        .main_clk       = "dss_48mhz_clk",
         .prcm = {
                 .omap4 = {
                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
@@ -1785,7 +1785,7 @@ static struct omap_hwmod omap44xx_dss_venc_hwmod = {
         .name           = "dss_venc",
         .class          = &omap44xx_venc_hwmod_class,
         .clkdm_name     = "l3_dss_clkdm",
-        .main_clk       = "dss_dss_clk",
+        .main_clk       = "dss_tv_clk",
         .prcm = {
                 .omap4 = {
                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
diff --git a/arch/arm/mach-omap2/omap_hwmod_common_data.c b/arch/arm/mach-omap2/omap_hwmod_common_data.c
index de832ebc93a9..51e5418899fb 100644
--- a/arch/arm/mach-omap2/omap_hwmod_common_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_common_data.c
@@ -49,3 +49,7 @@ struct omap_hwmod_sysc_fields omap_hwmod_sysc_type2 = {
         .srst_shift     = SYSC_TYPE2_SOFTRESET_SHIFT,
 };
 
+struct omap_dss_dispc_dev_attr omap2_3_dss_dispc_dev_attr = {
+        .manager_count          = 2,
+        .has_framedonetv_irq    = 0
+};
diff --git a/arch/arm/mach-omap2/omap_hwmod_common_data.h b/arch/arm/mach-omap2/omap_hwmod_common_data.h
index 39a7c37f4587..ad5d8f04c0b8 100644
--- a/arch/arm/mach-omap2/omap_hwmod_common_data.h
+++ b/arch/arm/mach-omap2/omap_hwmod_common_data.h
@@ -16,6 +16,8 @@
 
 #include <plat/omap_hwmod.h>
 
+#include "display.h"
+
 /* Common address space across OMAP2xxx */
 extern struct omap_hwmod_addr_space omap2xxx_uart1_addr_space[];
 extern struct omap_hwmod_addr_space omap2xxx_uart2_addr_space[];
@@ -111,4 +113,6 @@ extern struct omap_hwmod_class omap2xxx_dma_hwmod_class;
 extern struct omap_hwmod_class omap2xxx_mailbox_hwmod_class;
 extern struct omap_hwmod_class omap2xxx_mcspi_class;
 
+extern struct omap_dss_dispc_dev_attr omap2_3_dss_dispc_dev_attr;
+
 #endif
diff --git a/arch/arm/plat-omap/include/plat/common.h b/arch/arm/plat-omap/include/plat/common.h
index c50df4814f6f..3ff3e36580f2 100644
--- a/arch/arm/plat-omap/include/plat/common.h
+++ b/arch/arm/plat-omap/include/plat/common.h
@@ -30,6 +30,7 @@
 #include <linux/delay.h>
 
 #include <plat/i2c.h>
+#include <plat/omap_hwmod.h>
 
 struct sys_timer;
 
@@ -55,6 +56,8 @@ void am35xx_init_early(void);
 void ti816x_init_early(void);
 void omap4430_init_early(void);
 
+extern int omap_dss_reset(struct omap_hwmod *);
+
 void omap_sram_init(void);
 
 /*