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authorPratyush Anand <pratyush.anand@st.com>2014-04-14 05:57:36 -0400
committerViresh Kumar <viresh.kumar@linaro.org>2014-07-14 01:34:43 -0400
commit549f3ae1beb187e53f4cec7ee0cbe79b01d27111 (patch)
treec0741434bbeefe7fb1a59e4e5f3f35327ea7734e /arch
parent23b7ad23cb95db188403677c51c997338fb9effd (diff)
ARM: SPEAr13xx: Add pcie and miphy DT nodes
This patch adds necessary DT nodes for pcie controllers and miphys for SPEAr13xx SoCs. SPEAr1310 has 3 PCIe ports and SPEAr1340 has 1, which are multiplexed with ahci/sata pins. By default evaluation board of both controller works in ahci mode. Because of this, these nodes are marked "disabled" by default. In order to use pcie controller on evaluation boards do necessary modifications on board and enable (By replacing "disabled" with "okay") pcie and miphy from respective 'evb' dtsi file. Phy specific initialization was previously done from spear1340.c, which isn't required anymore as we have separate drivers for it. Remove it. Acked-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Pratyush Anand <pratyush.anand@st.com> Signed-off-by: Mohit Kumar <mohit.kumar@st.com> [viresh: fixed logs/cclist/checkpatch warnings, clubbed multiple patches into one] Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/boot/dts/spear1310-evb.dts4
-rw-r--r--arch/arm/boot/dts/spear1310.dtsi93
-rw-r--r--arch/arm/boot/dts/spear1340-evb.dts4
-rw-r--r--arch/arm/boot/dts/spear1340.dtsi30
-rw-r--r--arch/arm/boot/dts/spear13xx.dtsi4
-rw-r--r--arch/arm/mach-spear/Kconfig3
-rw-r--r--arch/arm/mach-spear/spear1340.c125
7 files changed, 133 insertions, 130 deletions
diff --git a/arch/arm/boot/dts/spear1310-evb.dts b/arch/arm/boot/dts/spear1310-evb.dts
index b56a801e42a2..d42c84b1df8d 100644
--- a/arch/arm/boot/dts/spear1310-evb.dts
+++ b/arch/arm/boot/dts/spear1310-evb.dts
@@ -106,6 +106,10 @@
106 status = "okay"; 106 status = "okay";
107 }; 107 };
108 108
109 miphy@eb800000 {
110 status = "okay";
111 };
112
109 cf@b2800000 { 113 cf@b2800000 {
110 status = "okay"; 114 status = "okay";
111 }; 115 };
diff --git a/arch/arm/boot/dts/spear1310.dtsi b/arch/arm/boot/dts/spear1310.dtsi
index 122ae94076c8..fa5f2bb5f106 100644
--- a/arch/arm/boot/dts/spear1310.dtsi
+++ b/arch/arm/boot/dts/spear1310.dtsi
@@ -29,24 +29,111 @@
29 #gpio-cells = <2>; 29 #gpio-cells = <2>;
30 }; 30 };
31 31
32 ahci@b1000000 { 32 miphy0: miphy@eb800000 {
33 compatible = "st,spear1310-miphy";
34 reg = <0xeb800000 0x4000>;
35 misc = <&misc>;
36 phy-id = <0>;
37 #phy-cells = <1>;
38 status = "disabled";
39 };
40
41 miphy1: miphy@eb804000 {
42 compatible = "st,spear1310-miphy";
43 reg = <0xeb804000 0x4000>;
44 misc = <&misc>;
45 phy-id = <1>;
46 #phy-cells = <1>;
47 status = "disabled";
48 };
49
50 miphy2: miphy@eb808000 {
51 compatible = "st,spear1310-miphy";
52 reg = <0xeb808000 0x4000>;
53 misc = <&misc>;
54 phy-id = <2>;
55 #phy-cells = <1>;
56 status = "disabled";
57 };
58
59 ahci0: ahci@b1000000 {
33 compatible = "snps,spear-ahci"; 60 compatible = "snps,spear-ahci";
34 reg = <0xb1000000 0x10000>; 61 reg = <0xb1000000 0x10000>;
35 interrupts = <0 68 0x4>; 62 interrupts = <0 68 0x4>;
63 phys = <&miphy0 0>;
64 phy-names = "sata-phy";
36 status = "disabled"; 65 status = "disabled";
37 }; 66 };
38 67
39 ahci@b1800000 { 68 ahci1: ahci@b1800000 {
40 compatible = "snps,spear-ahci"; 69 compatible = "snps,spear-ahci";
41 reg = <0xb1800000 0x10000>; 70 reg = <0xb1800000 0x10000>;
42 interrupts = <0 69 0x4>; 71 interrupts = <0 69 0x4>;
72 phys = <&miphy1 0>;
73 phy-names = "sata-phy";
43 status = "disabled"; 74 status = "disabled";
44 }; 75 };
45 76
46 ahci@b4000000 { 77 ahci2: ahci@b4000000 {
47 compatible = "snps,spear-ahci"; 78 compatible = "snps,spear-ahci";
48 reg = <0xb4000000 0x10000>; 79 reg = <0xb4000000 0x10000>;
49 interrupts = <0 70 0x4>; 80 interrupts = <0 70 0x4>;
81 phys = <&miphy2 0>;
82 phy-names = "sata-phy";
83 status = "disabled";
84 };
85
86 pcie0: pcie@b1000000 {
87 compatible = "st,spear1340-pcie", "snps,dw-pcie";
88 reg = <0xb1000000 0x4000>;
89 interrupts = <0 68 0x4>;
90 interrupt-map-mask = <0 0 0 0>;
91 interrupt-map = <0x0 0 &gic 0 68 0x4>;
92 num-lanes = <1>;
93 phys = <&miphy0 1>;
94 phy-names = "pcie-phy";
95 #address-cells = <3>;
96 #size-cells = <2>;
97 device_type = "pci";
98 ranges = <0x00000800 0 0x80000000 0x80000000 0 0x00020000 /* configuration space */
99 0x81000000 0 0 0x80020000 0 0x00010000 /* downstream I/O */
100 0x82000000 0 0x80030000 0xc0030000 0 0x0ffd0000>; /* non-prefetchable memory */
101 status = "disabled";
102 };
103
104 pcie1: pcie@b1800000 {
105 compatible = "st,spear1340-pcie", "snps,dw-pcie";
106 reg = <0xb1800000 0x4000>;
107 interrupts = <0 69 0x4>;
108 interrupt-map-mask = <0 0 0 0>;
109 interrupt-map = <0x0 0 &gic 0 69 0x4>;
110 num-lanes = <1>;
111 phys = <&miphy1 1>;
112 phy-names = "pcie-phy";
113 #address-cells = <3>;
114 #size-cells = <2>;
115 device_type = "pci";
116 ranges = <0x00000800 0 0x90000000 0x90000000 0 0x00020000 /* configuration space */
117 0x81000000 0 0 0x90020000 0 0x00010000 /* downstream I/O */
118 0x82000000 0 0x90030000 0x90030000 0 0x0ffd0000>; /* non-prefetchable memory */
119 status = "disabled";
120 };
121
122 pcie2: pcie@b4000000 {
123 compatible = "st,spear1340-pcie", "snps,dw-pcie";
124 reg = <0xb4000000 0x4000>;
125 interrupts = <0 70 0x4>;
126 interrupt-map-mask = <0 0 0 0>;
127 interrupt-map = <0x0 0 &gic 0 70 0x4>;
128 num-lanes = <1>;
129 phys = <&miphy2 1>;
130 phy-names = "pcie-phy";
131 #address-cells = <3>;
132 #size-cells = <2>;
133 device_type = "pci";
134 ranges = <0x00000800 0 0xc0000000 0xc0000000 0 0x00020000 /* configuration space */
135 0x81000000 0 0 0xc0020000 0 0x00010000 /* downstream I/O */
136 0x82000000 0 0xc0030000 0xc0030000 0 0x0ffd0000>; /* non-prefetchable memory */
50 status = "disabled"; 137 status = "disabled";
51 }; 138 };
52 139
diff --git a/arch/arm/boot/dts/spear1340-evb.dts b/arch/arm/boot/dts/spear1340-evb.dts
index d6c30ae0a8d7..b23e05ed1d60 100644
--- a/arch/arm/boot/dts/spear1340-evb.dts
+++ b/arch/arm/boot/dts/spear1340-evb.dts
@@ -122,6 +122,10 @@
122 status = "okay"; 122 status = "okay";
123 }; 123 };
124 124
125 miphy@eb800000 {
126 status = "okay";
127 };
128
125 dma@ea800000 { 129 dma@ea800000 {
126 status = "okay"; 130 status = "okay";
127 }; 131 };
diff --git a/arch/arm/boot/dts/spear1340.dtsi b/arch/arm/boot/dts/spear1340.dtsi
index 54d128d35681..e71df0f2cb52 100644
--- a/arch/arm/boot/dts/spear1340.dtsi
+++ b/arch/arm/boot/dts/spear1340.dtsi
@@ -31,10 +31,38 @@
31 status = "disabled"; 31 status = "disabled";
32 }; 32 };
33 33
34 ahci@b1000000 { 34 miphy0: miphy@eb800000 {
35 compatible = "st,spear1340-miphy";
36 reg = <0xeb800000 0x4000>;
37 misc = <&misc>;
38 #phy-cells = <1>;
39 status = "disabled";
40 };
41
42 ahci0: ahci@b1000000 {
35 compatible = "snps,spear-ahci"; 43 compatible = "snps,spear-ahci";
36 reg = <0xb1000000 0x10000>; 44 reg = <0xb1000000 0x10000>;
37 interrupts = <0 72 0x4>; 45 interrupts = <0 72 0x4>;
46 phys = <&miphy0 0>;
47 phy-names = "sata-phy";
48 status = "disabled";
49 };
50
51 pcie0: pcie@b1000000 {
52 compatible = "st,spear1340-pcie", "snps,dw-pcie";
53 reg = <0xb1000000 0x4000>;
54 interrupts = <0 68 0x4>;
55 interrupt-map-mask = <0 0 0 0>;
56 interrupt-map = <0x0 0 &gic 0 68 0x4>;
57 num-lanes = <1>;
58 phys = <&miphy0 1>;
59 phy-names = "pcie-phy";
60 #address-cells = <3>;
61 #size-cells = <2>;
62 device_type = "pci";
63 ranges = <0x00000800 0 0x80000000 0x80000000 0 0x00020000 /* configuration space */
64 0x81000000 0 0 0x80020000 0 0x00010000 /* downstream I/O */
65 0x82000000 0 0x80030000 0xc0030000 0 0x0ffd0000>; /* non-prefetchable memory */
38 status = "disabled"; 66 status = "disabled";
39 }; 67 };
40 68
diff --git a/arch/arm/boot/dts/spear13xx.dtsi b/arch/arm/boot/dts/spear13xx.dtsi
index 3a72508c578f..a6eb5436d26d 100644
--- a/arch/arm/boot/dts/spear13xx.dtsi
+++ b/arch/arm/boot/dts/spear13xx.dtsi
@@ -83,8 +83,8 @@
83 #size-cells = <1>; 83 #size-cells = <1>;
84 compatible = "simple-bus"; 84 compatible = "simple-bus";
85 ranges = <0x50000000 0x50000000 0x10000000 85 ranges = <0x50000000 0x50000000 0x10000000
86 0xb0000000 0xb0000000 0x10000000 86 0x80000000 0x80000000 0x20000000
87 0xd0000000 0xd0000000 0x02000000 87 0xb0000000 0xb0000000 0x22000000
88 0xd8000000 0xd8000000 0x01000000 88 0xd8000000 0xd8000000 0x01000000
89 0xe0000000 0xe0000000 0x10000000>; 89 0xe0000000 0xe0000000 0x10000000>;
90 90
diff --git a/arch/arm/mach-spear/Kconfig b/arch/arm/mach-spear/Kconfig
index ba57677cee28..6fd4dc88160b 100644
--- a/arch/arm/mach-spear/Kconfig
+++ b/arch/arm/mach-spear/Kconfig
@@ -20,6 +20,7 @@ config ARCH_SPEAR13XX
20 select HAVE_ARM_TWD if SMP 20 select HAVE_ARM_TWD if SMP
21 select PINCTRL 21 select PINCTRL
22 select MFD_SYSCON 22 select MFD_SYSCON
23 select MIGHT_HAVE_PCI
23 help 24 help
24 Supports for ARM's SPEAR13XX family 25 Supports for ARM's SPEAR13XX family
25 26
@@ -28,12 +29,14 @@ if ARCH_SPEAR13XX
28config MACH_SPEAR1310 29config MACH_SPEAR1310
29 bool "SPEAr1310 Machine support with Device Tree" 30 bool "SPEAr1310 Machine support with Device Tree"
30 select PINCTRL_SPEAR1310 31 select PINCTRL_SPEAR1310
32 select PHY_ST_SPEAR1310_MIPHY
31 help 33 help
32 Supports ST SPEAr1310 machine configured via the device-tree 34 Supports ST SPEAr1310 machine configured via the device-tree
33 35
34config MACH_SPEAR1340 36config MACH_SPEAR1340
35 bool "SPEAr1340 Machine support with Device Tree" 37 bool "SPEAr1340 Machine support with Device Tree"
36 select PINCTRL_SPEAR1340 38 select PINCTRL_SPEAR1340
39 select PHY_ST_SPEAR1340_MIPHY
37 help 40 help
38 Supports ST SPEAr1340 machine configured via the device-tree 41 Supports ST SPEAr1340 machine configured via the device-tree
39 42
diff --git a/arch/arm/mach-spear/spear1340.c b/arch/arm/mach-spear/spear1340.c
index 7b6bff7154e1..3f3c0f124bd3 100644
--- a/arch/arm/mach-spear/spear1340.c
+++ b/arch/arm/mach-spear/spear1340.c
@@ -13,136 +13,13 @@
13 13
14#define pr_fmt(fmt) "SPEAr1340: " fmt 14#define pr_fmt(fmt) "SPEAr1340: " fmt
15 15
16#include <linux/ahci_platform.h>
17#include <linux/amba/serial.h>
18#include <linux/delay.h>
19#include <linux/of_platform.h> 16#include <linux/of_platform.h>
20#include <asm/mach/arch.h> 17#include <asm/mach/arch.h>
21#include "generic.h" 18#include "generic.h"
22#include <mach/spear.h>
23
24/* FIXME: Move SATA PHY code into a standalone driver */
25
26/* Base addresses */
27#define SPEAR1340_SATA_BASE UL(0xB1000000)
28
29/* Power Management Registers */
30#define SPEAR1340_PCM_CFG (VA_MISC_BASE + 0x100)
31#define SPEAR1340_PCM_WKUP_CFG (VA_MISC_BASE + 0x104)
32#define SPEAR1340_SWITCH_CTR (VA_MISC_BASE + 0x108)
33
34#define SPEAR1340_PERIP1_SW_RST (VA_MISC_BASE + 0x318)
35#define SPEAR1340_PERIP2_SW_RST (VA_MISC_BASE + 0x31C)
36#define SPEAR1340_PERIP3_SW_RST (VA_MISC_BASE + 0x320)
37
38/* PCIE - SATA configuration registers */
39#define SPEAR1340_PCIE_SATA_CFG (VA_MISC_BASE + 0x424)
40 /* PCIE CFG MASks */
41 #define SPEAR1340_PCIE_CFG_DEVICE_PRESENT (1 << 11)
42 #define SPEAR1340_PCIE_CFG_POWERUP_RESET (1 << 10)
43 #define SPEAR1340_PCIE_CFG_CORE_CLK_EN (1 << 9)
44 #define SPEAR1340_PCIE_CFG_AUX_CLK_EN (1 << 8)
45 #define SPEAR1340_SATA_CFG_TX_CLK_EN (1 << 4)
46 #define SPEAR1340_SATA_CFG_RX_CLK_EN (1 << 3)
47 #define SPEAR1340_SATA_CFG_POWERUP_RESET (1 << 2)
48 #define SPEAR1340_SATA_CFG_PM_CLK_EN (1 << 1)
49 #define SPEAR1340_PCIE_SATA_SEL_PCIE (0)
50 #define SPEAR1340_PCIE_SATA_SEL_SATA (1)
51 #define SPEAR1340_SATA_PCIE_CFG_MASK 0xF1F
52 #define SPEAR1340_PCIE_CFG_VAL (SPEAR1340_PCIE_SATA_SEL_PCIE | \
53 SPEAR1340_PCIE_CFG_AUX_CLK_EN | \
54 SPEAR1340_PCIE_CFG_CORE_CLK_EN | \
55 SPEAR1340_PCIE_CFG_POWERUP_RESET | \
56 SPEAR1340_PCIE_CFG_DEVICE_PRESENT)
57 #define SPEAR1340_SATA_CFG_VAL (SPEAR1340_PCIE_SATA_SEL_SATA | \
58 SPEAR1340_SATA_CFG_PM_CLK_EN | \
59 SPEAR1340_SATA_CFG_POWERUP_RESET | \
60 SPEAR1340_SATA_CFG_RX_CLK_EN | \
61 SPEAR1340_SATA_CFG_TX_CLK_EN)
62
63#define SPEAR1340_PCIE_MIPHY_CFG (VA_MISC_BASE + 0x428)
64 #define SPEAR1340_MIPHY_OSC_BYPASS_EXT (1 << 31)
65 #define SPEAR1340_MIPHY_CLK_REF_DIV2 (1 << 27)
66 #define SPEAR1340_MIPHY_CLK_REF_DIV4 (2 << 27)
67 #define SPEAR1340_MIPHY_CLK_REF_DIV8 (3 << 27)
68 #define SPEAR1340_MIPHY_PLL_RATIO_TOP(x) (x << 0)
69 #define SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA \
70 (SPEAR1340_MIPHY_OSC_BYPASS_EXT | \
71 SPEAR1340_MIPHY_CLK_REF_DIV2 | \
72 SPEAR1340_MIPHY_PLL_RATIO_TOP(60))
73 #define SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA_25M_CRYSTAL_CLK \
74 (SPEAR1340_MIPHY_PLL_RATIO_TOP(120))
75 #define SPEAR1340_PCIE_SATA_MIPHY_CFG_PCIE \
76 (SPEAR1340_MIPHY_OSC_BYPASS_EXT | \
77 SPEAR1340_MIPHY_PLL_RATIO_TOP(25))
78
79/* SATA device registration */
80static int sata_miphy_init(struct device *dev, void __iomem *addr)
81{
82 writel(SPEAR1340_SATA_CFG_VAL, SPEAR1340_PCIE_SATA_CFG);
83 writel(SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA_25M_CRYSTAL_CLK,
84 SPEAR1340_PCIE_MIPHY_CFG);
85 /* Switch on sata power domain */
86 writel((readl(SPEAR1340_PCM_CFG) | (0x800)), SPEAR1340_PCM_CFG);
87 msleep(20);
88 /* Disable PCIE SATA Controller reset */
89 writel((readl(SPEAR1340_PERIP1_SW_RST) & (~0x1000)),
90 SPEAR1340_PERIP1_SW_RST);
91 msleep(20);
92
93 return 0;
94}
95
96void sata_miphy_exit(struct device *dev)
97{
98 writel(0, SPEAR1340_PCIE_SATA_CFG);
99 writel(0, SPEAR1340_PCIE_MIPHY_CFG);
100
101 /* Enable PCIE SATA Controller reset */
102 writel((readl(SPEAR1340_PERIP1_SW_RST) | (0x1000)),
103 SPEAR1340_PERIP1_SW_RST);
104 msleep(20);
105 /* Switch off sata power domain */
106 writel((readl(SPEAR1340_PCM_CFG) & (~0x800)), SPEAR1340_PCM_CFG);
107 msleep(20);
108}
109
110int sata_suspend(struct device *dev)
111{
112 if (dev->power.power_state.event == PM_EVENT_FREEZE)
113 return 0;
114
115 sata_miphy_exit(dev);
116
117 return 0;
118}
119
120int sata_resume(struct device *dev)
121{
122 if (dev->power.power_state.event == PM_EVENT_THAW)
123 return 0;
124
125 return sata_miphy_init(dev, NULL);
126}
127
128static struct ahci_platform_data sata_pdata = {
129 .init = sata_miphy_init,
130 .exit = sata_miphy_exit,
131 .suspend = sata_suspend,
132 .resume = sata_resume,
133};
134
135/* Add SPEAr1340 auxdata to pass platform data */
136static struct of_dev_auxdata spear1340_auxdata_lookup[] __initdata = {
137 OF_DEV_AUXDATA("snps,spear-ahci", SPEAR1340_SATA_BASE, NULL,
138 &sata_pdata),
139 {}
140};
141 19
142static void __init spear1340_dt_init(void) 20static void __init spear1340_dt_init(void)
143{ 21{
144 of_platform_populate(NULL, of_default_bus_match_table, 22 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
145 spear1340_auxdata_lookup, NULL);
146 platform_device_register_simple("spear-cpufreq", -1, NULL, 0); 23 platform_device_register_simple("spear-cpufreq", -1, NULL, 0);
147} 24}
148 25
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