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authorSantosh Shilimkar <santosh.shilimkar@ti.com>2011-02-04 04:58:57 -0500
committerPaul Walmsley <paul@pwsan.com>2011-02-25 14:45:05 -0500
commit51c404b2c514930e98e81e0b9294f19892a4f871 (patch)
tree27ad306fb5c9a6234677705808998b6751fefe45 /arch
parentea68c00e2623bb5b001c2117a4dcca4754781b4e (diff)
omap4: prcm: Fix the CPUx clockdomain offsets
CPU0 and CPU1 clockdomain is at the offset of 0x18 from the LPRM base. The header file has set it wrongly to 0x0. Offset 0x0 is for CPUx power domain control register Fix the same. The autogen scripts is fixed thanks to Benoit Cousson With the old value, the clockdomain code would access the *_PWRSTCTRL.POWERSTATE field when it thought it was accessing the *_CLKSTCTRL.CLKTRCTRL field. In the worst case, this could cause system power management to behave incorrectly. Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Cc: Paul Walmsley <paul@pwsan.com> Cc: Rajendra Nayak <rnayak@ti.com> Cc: Benoit Cousson <b-cousson@ti.com> [paul@pwsan.com: added second paragraph to commit message] Signed-off-by: Paul Walmsley <paul@pwsan.com>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/mach-omap2/prcm_mpu44xx.h4
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm/mach-omap2/prcm_mpu44xx.h b/arch/arm/mach-omap2/prcm_mpu44xx.h
index 729a644ce852..3300ff6e3cfe 100644
--- a/arch/arm/mach-omap2/prcm_mpu44xx.h
+++ b/arch/arm/mach-omap2/prcm_mpu44xx.h
@@ -38,8 +38,8 @@
38#define OMAP4430_PRCM_MPU_CPU1_INST 0x0800 38#define OMAP4430_PRCM_MPU_CPU1_INST 0x0800
39 39
40/* PRCM_MPU clockdomain register offsets (from instance start) */ 40/* PRCM_MPU clockdomain register offsets (from instance start) */
41#define OMAP4430_PRCM_MPU_CPU0_MPU_CDOFFS 0x0000 41#define OMAP4430_PRCM_MPU_CPU0_MPU_CDOFFS 0x0018
42#define OMAP4430_PRCM_MPU_CPU1_MPU_CDOFFS 0x0000 42#define OMAP4430_PRCM_MPU_CPU1_MPU_CDOFFS 0x0018
43 43
44 44
45/* 45/*