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authorTim Harvey <tharvey@gateworks.com>2014-08-22 17:52:54 -0400
committerShawn Guo <shawn.guo@freescale.com>2014-09-15 22:25:56 -0400
commit4e394cd999fe99cbebd0c8ca753d000d6db66f59 (patch)
tree58caaa577d60ed74d67e3676d1db4bc1febef6c7 /arch
parent6ff7f51ef9d34a7be945468de8383f29e151ce11 (diff)
ARM: dts: Gateworks GW5520 support (i.MX6)
Add support for the Gateworks GW5520 board. Signed-off-by: Tim Harvey <tharvey@gateworks.com> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/boot/dts/Makefile2
-rw-r--r--arch/arm/boot/dts/imx6dl-gw552x.dts20
-rw-r--r--arch/arm/boot/dts/imx6q-gw552x.dts24
-rw-r--r--arch/arm/boot/dts/imx6qdl-gw552x.dtsi267
4 files changed, 313 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 5a70f83f9e8d..60a6214ff49f 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -200,6 +200,7 @@ dtb-$(CONFIG_ARCH_MXC) += \
200 imx6dl-gw52xx.dtb \ 200 imx6dl-gw52xx.dtb \
201 imx6dl-gw53xx.dtb \ 201 imx6dl-gw53xx.dtb \
202 imx6dl-gw54xx.dtb \ 202 imx6dl-gw54xx.dtb \
203 imx6dl-gw552x.dtb \
203 imx6dl-hummingboard.dtb \ 204 imx6dl-hummingboard.dtb \
204 imx6dl-nitrogen6x.dtb \ 205 imx6dl-nitrogen6x.dtb \
205 imx6dl-phytec-pbab01.dtb \ 206 imx6dl-phytec-pbab01.dtb \
@@ -224,6 +225,7 @@ dtb-$(CONFIG_ARCH_MXC) += \
224 imx6q-gw53xx.dtb \ 225 imx6q-gw53xx.dtb \
225 imx6q-gw5400-a.dtb \ 226 imx6q-gw5400-a.dtb \
226 imx6q-gw54xx.dtb \ 227 imx6q-gw54xx.dtb \
228 imx6q-gw552x.dtb \
227 imx6q-nitrogen6x.dtb \ 229 imx6q-nitrogen6x.dtb \
228 imx6q-phytec-pbab01.dtb \ 230 imx6q-phytec-pbab01.dtb \
229 imx6q-rex-pro.dtb \ 231 imx6q-rex-pro.dtb \
diff --git a/arch/arm/boot/dts/imx6dl-gw552x.dts b/arch/arm/boot/dts/imx6dl-gw552x.dts
new file mode 100644
index 000000000000..a4b700cef188
--- /dev/null
+++ b/arch/arm/boot/dts/imx6dl-gw552x.dts
@@ -0,0 +1,20 @@
1/*
2 * Copyright 2014 Gateworks Corporation
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12/dts-v1/;
13
14#include "imx6dl.dtsi"
15#include "imx6qdl-gw552x.dtsi"
16
17/ {
18 model = "Gateworks Ventana i.MX6 DualLite/Solo GW552X";
19 compatible = "gw,imx6dl-gw552x", "gw,ventana", "fsl,imx6dl";
20};
diff --git a/arch/arm/boot/dts/imx6q-gw552x.dts b/arch/arm/boot/dts/imx6q-gw552x.dts
new file mode 100644
index 000000000000..f87a8fa6e04d
--- /dev/null
+++ b/arch/arm/boot/dts/imx6q-gw552x.dts
@@ -0,0 +1,24 @@
1/*
2 * Copyright 2014 Gateworks Corporation
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12/dts-v1/;
13
14#include "imx6q.dtsi"
15#include "imx6qdl-gw552x.dtsi"
16
17/ {
18 model = "Gateworks Ventana i.MX6 Dual/Quad GW552X";
19 compatible = "gw,imx6q-gw552x", "gw,ventana", "fsl,imx6q";
20};
21
22&sata {
23 status = "okay";
24};
diff --git a/arch/arm/boot/dts/imx6qdl-gw552x.dtsi b/arch/arm/boot/dts/imx6qdl-gw552x.dtsi
new file mode 100644
index 000000000000..5c6587f6c420
--- /dev/null
+++ b/arch/arm/boot/dts/imx6qdl-gw552x.dtsi
@@ -0,0 +1,267 @@
1/*
2 * Copyright 2014 Gateworks Corporation
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12#include <dt-bindings/gpio/gpio.h>
13
14/ {
15 /* these are used by bootloader for disabling nodes */
16 aliases {
17 led0 = &led0;
18 led1 = &led1;
19 led2 = &led2;
20 nand = &gpmi;
21 usb0 = &usbh1;
22 usb1 = &usbotg;
23 };
24
25 chosen {
26 bootargs = "console=ttymxc1,115200";
27 };
28
29 leds {
30 compatible = "gpio-leds";
31 pinctrl-names = "default";
32 pinctrl-0 = <&pinctrl_gpio_leds>;
33
34 led0: user1 {
35 label = "user1";
36 gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */
37 default-state = "on";
38 linux,default-trigger = "heartbeat";
39 };
40
41 led1: user2 {
42 label = "user2";
43 gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */
44 default-state = "off";
45 };
46
47 led2: user3 {
48 label = "user3";
49 gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */
50 default-state = "off";
51 };
52 };
53
54 memory {
55 reg = <0x10000000 0x20000000>;
56 };
57
58 regulators {
59 compatible = "simple-bus";
60 #address-cells = <1>;
61 #size-cells = <0>;
62
63 reg_1p0v: regulator@0 {
64 compatible = "regulator-fixed";
65 reg = <0>;
66 regulator-name = "1P0V";
67 regulator-min-microvolt = <1000000>;
68 regulator-max-microvolt = <1000000>;
69 regulator-always-on;
70 };
71
72 reg_3p3v: regulator@2 {
73 compatible = "regulator-fixed";
74 reg = <2>;
75 regulator-name = "3P3V";
76 regulator-min-microvolt = <3300000>;
77 regulator-max-microvolt = <3300000>;
78 regulator-always-on;
79 };
80
81 reg_5p0v: regulator@3 {
82 compatible = "regulator-fixed";
83 reg = <3>;
84 regulator-name = "5P0V";
85 regulator-min-microvolt = <5000000>;
86 regulator-max-microvolt = <5000000>;
87 regulator-always-on;
88 };
89 };
90};
91
92&gpmi {
93 pinctrl-names = "default";
94 pinctrl-0 = <&pinctrl_gpmi_nand>;
95 status = "okay";
96};
97
98&hdmi {
99 ddc-i2c-bus = <&i2c3>;
100 status = "okay";
101};
102
103&i2c1 {
104 clock-frequency = <100000>;
105 pinctrl-names = "default";
106 pinctrl-0 = <&pinctrl_i2c1>;
107 status = "okay";
108
109 eeprom1: eeprom@50 {
110 compatible = "atmel,24c02";
111 reg = <0x50>;
112 pagesize = <16>;
113 };
114
115 eeprom2: eeprom@51 {
116 compatible = "atmel,24c02";
117 reg = <0x51>;
118 pagesize = <16>;
119 };
120
121 eeprom3: eeprom@52 {
122 compatible = "atmel,24c02";
123 reg = <0x52>;
124 pagesize = <16>;
125 };
126
127 eeprom4: eeprom@53 {
128 compatible = "atmel,24c02";
129 reg = <0x53>;
130 pagesize = <16>;
131 };
132
133 gpio: pca9555@23 {
134 compatible = "nxp,pca9555";
135 reg = <0x23>;
136 gpio-controller;
137 #gpio-cells = <2>;
138 };
139
140 rtc: ds1672@68 {
141 compatible = "dallas,ds1672";
142 reg = <0x68>;
143 };
144};
145
146&i2c2 {
147 clock-frequency = <100000>;
148 pinctrl-names = "default";
149 pinctrl-0 = <&pinctrl_i2c2>;
150 status = "okay";
151};
152
153&i2c3 {
154 clock-frequency = <100000>;
155 pinctrl-names = "default";
156 pinctrl-0 = <&pinctrl_i2c3>;
157 status = "okay";
158};
159
160&pcie {
161 pinctrl-names = "default";
162 pinctrl-0 = <&pinctrl_pcie>;
163 reset-gpio = <&gpio1 29 GPIO_ACTIVE_LOW>;
164 status = "okay";
165};
166
167&uart2 {
168 pinctrl-names = "default";
169 pinctrl-0 = <&pinctrl_uart2>;
170 status = "okay";
171};
172
173&uart3 {
174 pinctrl-names = "default";
175 pinctrl-0 = <&pinctrl_uart3>;
176 status = "okay";
177};
178
179&uart5 {
180 pinctrl-names = "default";
181 pinctrl-0 = <&pinctrl_uart5>;
182 status = "okay"; };
183
184&usbh1 {
185 status = "okay";
186};
187
188&iomuxc {
189 imx6qdl-gw552x {
190 pinctrl_gpio_leds: gpioledsgrp {
191 fsl,pins = <
192 MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0
193 MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0
194 MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0
195 >;
196 };
197
198 pinctrl_gpmi_nand: gpminandgrp {
199 fsl,pins = <
200 MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
201 MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
202 MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
203 MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
204 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
205 MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1
206 MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
207 MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
208 MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
209 MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
210 MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
211 MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
212 MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
213 MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
214 MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
215 MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
216 >;
217 };
218
219 pinctrl_i2c1: i2c1grp {
220 fsl,pins = <
221 MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
222 MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
223 >;
224 };
225
226 pinctrl_i2c2: i2c2grp {
227 fsl,pins = <
228 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
229 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
230 >;
231 };
232
233 pinctrl_i2c3: i2c3grp {
234 fsl,pins = <
235 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
236 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
237 >;
238 };
239
240 pinctrl_pcie: pciegrp {
241 fsl,pins = <
242 MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0
243 >;
244 };
245
246 pinctrl_uart2: uart2grp {
247 fsl,pins = <
248 MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
249 MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
250 >;
251 };
252
253 pinctrl_uart3: uart3grp {
254 fsl,pins = <
255 MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
256 MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
257 >;
258 };
259
260 pinctrl_uart5: uart5grp {
261 fsl,pins = <
262 MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
263 MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
264 >;
265 };
266 };
267};
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