diff options
author | Eric Miao <eric.y.miao@gmail.com> | 2007-06-06 01:22:20 -0400 |
---|---|---|
committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2007-07-12 09:28:09 -0400 |
commit | 486c955118dbbb0f13dc4d40cc5dac2b23f82676 (patch) | |
tree | a38ba53eb3d924e34c312ec6e2eaa1d491a82446 /arch | |
parent | 88dfe98c688e1700a4a9f73f8b7d570f4f52170d (diff) |
[ARM] 4434/1: PXA: remove PXA_IRQ_SKIP
1. PXA_IRQ_SKIP is defined to be 7 on PXA25x so that the first IRQ
starts from zero. This makes IRQ numbering inconsistent between
PXA25x and PXA27x. Remove this macro so that the same IRQ_XXXXX
definition has the same value on both PXA25x and PXA27x.
2. make IRQ_SSP3..IRQ_PWRI2C valid only if PXA27x is defined, this
avoids unintentional use of these macros on PXA25x
Signed-off-by: eric miao <eric.miao@marvell.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch')
-rw-r--r-- | arch/arm/mach-pxa/irq.c | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/arch/arm/mach-pxa/irq.c b/arch/arm/mach-pxa/irq.c index 4619d5fe606c..45ce711f0472 100644 --- a/arch/arm/mach-pxa/irq.c +++ b/arch/arm/mach-pxa/irq.c | |||
@@ -30,12 +30,12 @@ | |||
30 | 30 | ||
31 | static void pxa_mask_low_irq(unsigned int irq) | 31 | static void pxa_mask_low_irq(unsigned int irq) |
32 | { | 32 | { |
33 | ICMR &= ~(1 << (irq + PXA_IRQ_SKIP)); | 33 | ICMR &= ~(1 << irq); |
34 | } | 34 | } |
35 | 35 | ||
36 | static void pxa_unmask_low_irq(unsigned int irq) | 36 | static void pxa_unmask_low_irq(unsigned int irq) |
37 | { | 37 | { |
38 | ICMR |= (1 << (irq + PXA_IRQ_SKIP)); | 38 | ICMR |= (1 << irq); |
39 | } | 39 | } |
40 | 40 | ||
41 | static int pxa_set_wake(unsigned int irq, unsigned int on) | 41 | static int pxa_set_wake(unsigned int irq, unsigned int on) |
@@ -75,12 +75,12 @@ static struct irq_chip pxa_internal_chip_low = { | |||
75 | 75 | ||
76 | static void pxa_mask_high_irq(unsigned int irq) | 76 | static void pxa_mask_high_irq(unsigned int irq) |
77 | { | 77 | { |
78 | ICMR2 &= ~(1 << (irq - 32 + PXA_IRQ_SKIP)); | 78 | ICMR2 &= ~(1 << (irq - 32)); |
79 | } | 79 | } |
80 | 80 | ||
81 | static void pxa_unmask_high_irq(unsigned int irq) | 81 | static void pxa_unmask_high_irq(unsigned int irq) |
82 | { | 82 | { |
83 | ICMR2 |= (1 << (irq - 32 + PXA_IRQ_SKIP)); | 83 | ICMR2 |= (1 << (irq - 32)); |
84 | } | 84 | } |
85 | 85 | ||
86 | static struct irq_chip pxa_internal_chip_high = { | 86 | static struct irq_chip pxa_internal_chip_high = { |
@@ -351,7 +351,7 @@ void __init pxa_init_irq(void) | |||
351 | /* GPIO 0 and 1 must have their mask bit always set */ | 351 | /* GPIO 0 and 1 must have their mask bit always set */ |
352 | GPIO_IRQ_mask[0] = 3; | 352 | GPIO_IRQ_mask[0] = 3; |
353 | 353 | ||
354 | for (irq = PXA_IRQ(PXA_IRQ_SKIP); irq <= PXA_IRQ(31); irq++) { | 354 | for (irq = PXA_IRQ(0); irq <= PXA_IRQ(31); irq++) { |
355 | set_irq_chip(irq, &pxa_internal_chip_low); | 355 | set_irq_chip(irq, &pxa_internal_chip_low); |
356 | set_irq_handler(irq, handle_level_irq); | 356 | set_irq_handler(irq, handle_level_irq); |
357 | set_irq_flags(irq, IRQF_VALID); | 357 | set_irq_flags(irq, IRQF_VALID); |