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authorLinus Torvalds <torvalds@linux-foundation.org>2014-04-02 16:15:58 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2014-04-02 16:15:58 -0400
commit467cbd207abdbfe29514b5804a22661ab6e80dc6 (patch)
tree026a03bfcb0f755c5d61fcf288d98582ebd55093 /arch
parent7125764c5d1a5c72d522f1011b6cc8b8100b48fe (diff)
parentb5660ba76b41af69a0c09d434927bb4b4cadd4b1 (diff)
Merge branch 'x86-nuke-platforms-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull x86 old platform removal from Peter Anvin: "This patchset removes support for several completely obsolete platforms, where the maintainers either have completely vanished or acked the removal. For some of them it is questionable if there even exists functional specimens of the hardware" Geert Uytterhoeven apparently thought this was a April Fool's pull request ;) * 'x86-nuke-platforms-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: x86, platforms: Remove NUMAQ x86, platforms: Remove SGI Visual Workstation x86, apic: Remove support for IBM Summit/EXA chipset x86, apic: Remove support for ia32-based Unisys ES7000
Diffstat (limited to 'arch')
-rw-r--r--arch/x86/Kconfig82
-rw-r--r--arch/x86/Kconfig.cpu2
-rw-r--r--arch/x86/include/asm/fixmap.h6
-rw-r--r--arch/x86/include/asm/hw_irq.h1
-rw-r--r--arch/x86/include/asm/mmzone_32.h3
-rw-r--r--arch/x86/include/asm/mpspec.h6
-rw-r--r--arch/x86/include/asm/numaq.h171
-rw-r--r--arch/x86/include/asm/setup.h6
-rw-r--r--arch/x86/include/asm/visws/cobalt.h127
-rw-r--r--arch/x86/include/asm/visws/lithium.h53
-rw-r--r--arch/x86/include/asm/visws/piix4.h107
-rw-r--r--arch/x86/include/asm/visws/sgivw.h5
-rw-r--r--arch/x86/kernel/acpi/boot.c12
-rw-r--r--arch/x86/kernel/apic/Makefile3
-rw-r--r--arch/x86/kernel/apic/apic.c1
-rw-r--r--arch/x86/kernel/apic/es7000_32.c738
-rw-r--r--arch/x86/kernel/apic/numaq_32.c524
-rw-r--r--arch/x86/kernel/apic/summit_32.c550
-rw-r--r--arch/x86/kernel/cpu/intel.c4
-rw-r--r--arch/x86/kernel/setup.c1
-rw-r--r--arch/x86/mm/numa.c4
-rw-r--r--arch/x86/pci/Makefile3
-rw-r--r--arch/x86/pci/common.c5
-rw-r--r--arch/x86/pci/numaq_32.c165
-rw-r--r--arch/x86/pci/visws.c87
-rw-r--r--arch/x86/platform/Makefile1
-rw-r--r--arch/x86/platform/visws/Makefile1
-rw-r--r--arch/x86/platform/visws/visws_quirks.c608
-rw-r--r--arch/x86/xen/Kconfig2
29 files changed, 12 insertions, 3266 deletions
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index ac04d9804391..f73071742975 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -344,12 +344,9 @@ config X86_EXTENDED_PLATFORM
344 for the following (non-PC) 32 bit x86 platforms: 344 for the following (non-PC) 32 bit x86 platforms:
345 Goldfish (Android emulator) 345 Goldfish (Android emulator)
346 AMD Elan 346 AMD Elan
347 NUMAQ (IBM/Sequent)
348 RDC R-321x SoC 347 RDC R-321x SoC
349 SGI 320/540 (Visual Workstation) 348 SGI 320/540 (Visual Workstation)
350 STA2X11-based (e.g. Northville) 349 STA2X11-based (e.g. Northville)
351 Summit/EXA (IBM x440)
352 Unisys ES7000 IA32 series
353 Moorestown MID devices 350 Moorestown MID devices
354 351
355 If you have one of these systems, or if you want to build a 352 If you have one of these systems, or if you want to build a
@@ -487,49 +484,22 @@ config X86_32_NON_STANDARD
487 depends on X86_32 && SMP 484 depends on X86_32 && SMP
488 depends on X86_EXTENDED_PLATFORM 485 depends on X86_EXTENDED_PLATFORM
489 ---help--- 486 ---help---
490 This option compiles in the NUMAQ, Summit, bigsmp, ES7000, 487 This option compiles in the bigsmp and STA2X11 default
491 STA2X11, default subarchitectures. It is intended for a generic 488 subarchitectures. It is intended for a generic binary
492 binary kernel. If you select them all, kernel will probe it 489 kernel. If you select them all, kernel will probe it one by
493 one by one and will fallback to default. 490 one and will fallback to default.
494 491
495# Alphabetically sorted list of Non standard 32 bit platforms 492# Alphabetically sorted list of Non standard 32 bit platforms
496 493
497config X86_NUMAQ
498 bool "NUMAQ (IBM/Sequent)"
499 depends on X86_32_NON_STANDARD
500 depends on PCI
501 select NUMA
502 select X86_MPPARSE
503 ---help---
504 This option is used for getting Linux to run on a NUMAQ (IBM/Sequent)
505 NUMA multiquad box. This changes the way that processors are
506 bootstrapped, and uses Clustered Logical APIC addressing mode instead
507 of Flat Logical. You will need a new lynxer.elf file to flash your
508 firmware with - send email to <Martin.Bligh@us.ibm.com>.
509
510config X86_SUPPORTS_MEMORY_FAILURE 494config X86_SUPPORTS_MEMORY_FAILURE
511 def_bool y 495 def_bool y
512 # MCE code calls memory_failure(): 496 # MCE code calls memory_failure():
513 depends on X86_MCE 497 depends on X86_MCE
514 # On 32-bit this adds too big of NODES_SHIFT and we run out of page flags: 498 # On 32-bit this adds too big of NODES_SHIFT and we run out of page flags:
515 depends on !X86_NUMAQ
516 # On 32-bit SPARSEMEM adds too big of SECTIONS_WIDTH: 499 # On 32-bit SPARSEMEM adds too big of SECTIONS_WIDTH:
517 depends on X86_64 || !SPARSEMEM 500 depends on X86_64 || !SPARSEMEM
518 select ARCH_SUPPORTS_MEMORY_FAILURE 501 select ARCH_SUPPORTS_MEMORY_FAILURE
519 502
520config X86_VISWS
521 bool "SGI 320/540 (Visual Workstation)"
522 depends on X86_32 && PCI && X86_MPPARSE && PCI_GODIRECT
523 depends on X86_32_NON_STANDARD
524 ---help---
525 The SGI Visual Workstation series is an IA32-based workstation
526 based on SGI systems chips with some legacy PC hardware attached.
527
528 Say Y here to create a kernel to run on the SGI 320 or 540.
529
530 A kernel compiled for the Visual Workstation will run on general
531 PCs as well. See <file:Documentation/sgi-visws.txt> for details.
532
533config STA2X11 503config STA2X11
534 bool "STA2X11 Companion Chip Support" 504 bool "STA2X11 Companion Chip Support"
535 depends on X86_32_NON_STANDARD && PCI 505 depends on X86_32_NON_STANDARD && PCI
@@ -546,20 +516,6 @@ config STA2X11
546 option is selected the kernel will still be able to boot on 516 option is selected the kernel will still be able to boot on
547 standard PC machines. 517 standard PC machines.
548 518
549config X86_SUMMIT
550 bool "Summit/EXA (IBM x440)"
551 depends on X86_32_NON_STANDARD
552 ---help---
553 This option is needed for IBM systems that use the Summit/EXA chipset.
554 In particular, it is needed for the x440.
555
556config X86_ES7000
557 bool "Unisys ES7000 IA32 series"
558 depends on X86_32_NON_STANDARD && X86_BIGSMP
559 ---help---
560 Support for Unisys ES7000 systems. Say 'Y' here if this kernel is
561 supposed to run on an IA32-based Unisys ES7000 system.
562
563config X86_32_IRIS 519config X86_32_IRIS
564 tristate "Eurobraille/Iris poweroff module" 520 tristate "Eurobraille/Iris poweroff module"
565 depends on X86_32 521 depends on X86_32
@@ -682,14 +638,6 @@ config MEMTEST
682 memtest=4, mean do 4 test patterns. 638 memtest=4, mean do 4 test patterns.
683 If you are unsure how to answer this question, answer N. 639 If you are unsure how to answer this question, answer N.
684 640
685config X86_SUMMIT_NUMA
686 def_bool y
687 depends on X86_32 && NUMA && X86_32_NON_STANDARD
688
689config X86_CYCLONE_TIMER
690 def_bool y
691 depends on X86_SUMMIT
692
693source "arch/x86/Kconfig.cpu" 641source "arch/x86/Kconfig.cpu"
694 642
695config HPET_TIMER 643config HPET_TIMER
@@ -818,7 +766,7 @@ config NR_CPUS
818 range 2 8192 if SMP && !MAXSMP && CPUMASK_OFFSTACK && X86_64 766 range 2 8192 if SMP && !MAXSMP && CPUMASK_OFFSTACK && X86_64
819 default "1" if !SMP 767 default "1" if !SMP
820 default "8192" if MAXSMP 768 default "8192" if MAXSMP
821 default "32" if SMP && (X86_NUMAQ || X86_SUMMIT || X86_BIGSMP || X86_ES7000) 769 default "32" if SMP && X86_BIGSMP
822 default "8" if SMP 770 default "8" if SMP
823 ---help--- 771 ---help---
824 This allows you to specify the maximum number of CPUs which this 772 This allows you to specify the maximum number of CPUs which this
@@ -882,10 +830,6 @@ config X86_IO_APIC
882 def_bool y 830 def_bool y
883 depends on X86_64 || SMP || X86_32_NON_STANDARD || X86_UP_IOAPIC || PCI_MSI 831 depends on X86_64 || SMP || X86_32_NON_STANDARD || X86_UP_IOAPIC || PCI_MSI
884 832
885config X86_VISWS_APIC
886 def_bool y
887 depends on X86_32 && X86_VISWS
888
889config X86_REROUTE_FOR_BROKEN_BOOT_IRQS 833config X86_REROUTE_FOR_BROKEN_BOOT_IRQS
890 bool "Reroute for broken boot IRQs" 834 bool "Reroute for broken boot IRQs"
891 depends on X86_IO_APIC 835 depends on X86_IO_APIC
@@ -1103,13 +1047,11 @@ config X86_CPUID
1103 1047
1104choice 1048choice
1105 prompt "High Memory Support" 1049 prompt "High Memory Support"
1106 default HIGHMEM64G if X86_NUMAQ
1107 default HIGHMEM4G 1050 default HIGHMEM4G
1108 depends on X86_32 1051 depends on X86_32
1109 1052
1110config NOHIGHMEM 1053config NOHIGHMEM
1111 bool "off" 1054 bool "off"
1112 depends on !X86_NUMAQ
1113 ---help--- 1055 ---help---
1114 Linux can use up to 64 Gigabytes of physical memory on x86 systems. 1056 Linux can use up to 64 Gigabytes of physical memory on x86 systems.
1115 However, the address space of 32-bit x86 processors is only 4 1057 However, the address space of 32-bit x86 processors is only 4
@@ -1146,7 +1088,6 @@ config NOHIGHMEM
1146 1088
1147config HIGHMEM4G 1089config HIGHMEM4G
1148 bool "4GB" 1090 bool "4GB"
1149 depends on !X86_NUMAQ
1150 ---help--- 1091 ---help---
1151 Select this if you have a 32-bit processor and between 1 and 4 1092 Select this if you have a 32-bit processor and between 1 and 4
1152 gigabytes of physical RAM. 1093 gigabytes of physical RAM.
@@ -1238,8 +1179,8 @@ config DIRECT_GBPAGES
1238config NUMA 1179config NUMA
1239 bool "Numa Memory Allocation and Scheduler Support" 1180 bool "Numa Memory Allocation and Scheduler Support"
1240 depends on SMP 1181 depends on SMP
1241 depends on X86_64 || (X86_32 && HIGHMEM64G && (X86_NUMAQ || X86_BIGSMP || X86_SUMMIT && ACPI)) 1182 depends on X86_64 || (X86_32 && HIGHMEM64G && X86_BIGSMP)
1242 default y if (X86_NUMAQ || X86_SUMMIT || X86_BIGSMP) 1183 default y if X86_BIGSMP
1243 ---help--- 1184 ---help---
1244 Enable NUMA (Non Uniform Memory Access) support. 1185 Enable NUMA (Non Uniform Memory Access) support.
1245 1186
@@ -1250,15 +1191,11 @@ config NUMA
1250 For 64-bit this is recommended if the system is Intel Core i7 1191 For 64-bit this is recommended if the system is Intel Core i7
1251 (or later), AMD Opteron, or EM64T NUMA. 1192 (or later), AMD Opteron, or EM64T NUMA.
1252 1193
1253 For 32-bit this is only needed on (rare) 32-bit-only platforms 1194 For 32-bit this is only needed if you boot a 32-bit
1254 that support NUMA topologies, such as NUMAQ / Summit, or if you 1195 kernel on a 64-bit NUMA platform.
1255 boot a 32-bit kernel on a 64-bit NUMA platform.
1256 1196
1257 Otherwise, you should say N. 1197 Otherwise, you should say N.
1258 1198
1259comment "NUMA (Summit) requires SMP, 64GB highmem support, ACPI"
1260 depends on X86_32 && X86_SUMMIT && (!HIGHMEM64G || !ACPI)
1261
1262config AMD_NUMA 1199config AMD_NUMA
1263 def_bool y 1200 def_bool y
1264 prompt "Old style AMD Opteron NUMA detection" 1201 prompt "Old style AMD Opteron NUMA detection"
@@ -1300,7 +1237,6 @@ config NODES_SHIFT
1300 range 1 10 1237 range 1 10
1301 default "10" if MAXSMP 1238 default "10" if MAXSMP
1302 default "6" if X86_64 1239 default "6" if X86_64
1303 default "4" if X86_NUMAQ
1304 default "3" 1240 default "3"
1305 depends on NEED_MULTIPLE_NODES 1241 depends on NEED_MULTIPLE_NODES
1306 ---help--- 1242 ---help---
diff --git a/arch/x86/Kconfig.cpu b/arch/x86/Kconfig.cpu
index f3aaf231b4e5..6983314c8b37 100644
--- a/arch/x86/Kconfig.cpu
+++ b/arch/x86/Kconfig.cpu
@@ -359,7 +359,7 @@ config X86_P6_NOP
359 359
360config X86_TSC 360config X86_TSC
361 def_bool y 361 def_bool y
362 depends on ((MWINCHIP3D || MCRUSOE || MEFFICEON || MCYRIXIII || MK7 || MK6 || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || M586MMX || M586TSC || MK8 || MVIAC3_2 || MVIAC7 || MGEODEGX1 || MGEODE_LX || MCORE2 || MATOM) && !X86_NUMAQ) || X86_64 362 depends on (MWINCHIP3D || MCRUSOE || MEFFICEON || MCYRIXIII || MK7 || MK6 || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || M586MMX || M586TSC || MK8 || MVIAC3_2 || MVIAC7 || MGEODEGX1 || MGEODE_LX || MCORE2 || MATOM) || X86_64
363 363
364config X86_CMPXCHG64 364config X86_CMPXCHG64
365 def_bool y 365 def_bool y
diff --git a/arch/x86/include/asm/fixmap.h b/arch/x86/include/asm/fixmap.h
index 2377f5618fb7..8dcd35c4c787 100644
--- a/arch/x86/include/asm/fixmap.h
+++ b/arch/x86/include/asm/fixmap.h
@@ -90,12 +90,6 @@ enum fixed_addresses {
90 FIX_IO_APIC_BASE_0, 90 FIX_IO_APIC_BASE_0,
91 FIX_IO_APIC_BASE_END = FIX_IO_APIC_BASE_0 + MAX_IO_APICS - 1, 91 FIX_IO_APIC_BASE_END = FIX_IO_APIC_BASE_0 + MAX_IO_APICS - 1,
92#endif 92#endif
93#ifdef CONFIG_X86_VISWS_APIC
94 FIX_CO_CPU, /* Cobalt timer */
95 FIX_CO_APIC, /* Cobalt APIC Redirection Table */
96 FIX_LI_PCIA, /* Lithium PCI Bridge A */
97 FIX_LI_PCIB, /* Lithium PCI Bridge B */
98#endif
99 FIX_RO_IDT, /* Virtual mapping for read-only IDT */ 93 FIX_RO_IDT, /* Virtual mapping for read-only IDT */
100#ifdef CONFIG_X86_32 94#ifdef CONFIG_X86_32
101 FIX_KMAP_BEGIN, /* reserved pte's for temporary kernel mappings */ 95 FIX_KMAP_BEGIN, /* reserved pte's for temporary kernel mappings */
diff --git a/arch/x86/include/asm/hw_irq.h b/arch/x86/include/asm/hw_irq.h
index 67d69b8e2d20..a307b7530e54 100644
--- a/arch/x86/include/asm/hw_irq.h
+++ b/arch/x86/include/asm/hw_irq.h
@@ -98,7 +98,6 @@ extern void trace_call_function_single_interrupt(void);
98#define IO_APIC_IRQ(x) (((x) >= NR_IRQS_LEGACY) || ((1<<(x)) & io_apic_irqs)) 98#define IO_APIC_IRQ(x) (((x) >= NR_IRQS_LEGACY) || ((1<<(x)) & io_apic_irqs))
99extern unsigned long io_apic_irqs; 99extern unsigned long io_apic_irqs;
100 100
101extern void init_VISWS_APIC_irqs(void);
102extern void setup_IO_APIC(void); 101extern void setup_IO_APIC(void);
103extern void disable_IO_APIC(void); 102extern void disable_IO_APIC(void);
104 103
diff --git a/arch/x86/include/asm/mmzone_32.h b/arch/x86/include/asm/mmzone_32.h
index 8a9b3e288cb4..1ec990bd7dc0 100644
--- a/arch/x86/include/asm/mmzone_32.h
+++ b/arch/x86/include/asm/mmzone_32.h
@@ -11,9 +11,6 @@
11#ifdef CONFIG_NUMA 11#ifdef CONFIG_NUMA
12extern struct pglist_data *node_data[]; 12extern struct pglist_data *node_data[];
13#define NODE_DATA(nid) (node_data[nid]) 13#define NODE_DATA(nid) (node_data[nid])
14
15#include <asm/numaq.h>
16
17#endif /* CONFIG_NUMA */ 14#endif /* CONFIG_NUMA */
18 15
19#ifdef CONFIG_DISCONTIGMEM 16#ifdef CONFIG_DISCONTIGMEM
diff --git a/arch/x86/include/asm/mpspec.h b/arch/x86/include/asm/mpspec.h
index 3e6b4920ef5d..f5a617956735 100644
--- a/arch/x86/include/asm/mpspec.h
+++ b/arch/x86/include/asm/mpspec.h
@@ -25,12 +25,6 @@ extern int pic_mode;
25 25
26extern unsigned int def_to_bigsmp; 26extern unsigned int def_to_bigsmp;
27 27
28#ifdef CONFIG_X86_NUMAQ
29extern int mp_bus_id_to_node[MAX_MP_BUSSES];
30extern int mp_bus_id_to_local[MAX_MP_BUSSES];
31extern int quad_local_to_mp_bus_id [NR_CPUS/4][4];
32#endif
33
34#else /* CONFIG_X86_64: */ 28#else /* CONFIG_X86_64: */
35 29
36#define MAX_MP_BUSSES 256 30#define MAX_MP_BUSSES 256
diff --git a/arch/x86/include/asm/numaq.h b/arch/x86/include/asm/numaq.h
deleted file mode 100644
index c3b3c322fd87..000000000000
--- a/arch/x86/include/asm/numaq.h
+++ /dev/null
@@ -1,171 +0,0 @@
1/*
2 * Written by: Patricia Gaughen, IBM Corporation
3 *
4 * Copyright (C) 2002, IBM Corp.
5 *
6 * All rights reserved.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
16 * NON INFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22 *
23 * Send feedback to <gone@us.ibm.com>
24 */
25
26#ifndef _ASM_X86_NUMAQ_H
27#define _ASM_X86_NUMAQ_H
28
29#ifdef CONFIG_X86_NUMAQ
30
31extern int found_numaq;
32extern int numaq_numa_init(void);
33extern int pci_numaq_init(void);
34
35extern void *xquad_portio;
36
37#define XQUAD_PORTIO_BASE 0xfe400000
38#define XQUAD_PORTIO_QUAD 0x40000 /* 256k per quad. */
39#define XQUAD_PORT_ADDR(port, quad) (xquad_portio + (XQUAD_PORTIO_QUAD*quad) + port)
40
41/*
42 * SYS_CFG_DATA_PRIV_ADDR, struct eachquadmem, and struct sys_cfg_data are the
43 */
44#define SYS_CFG_DATA_PRIV_ADDR 0x0009d000 /* place for scd in private
45 quad space */
46
47/*
48 * Communication area for each processor on lynxer-processor tests.
49 *
50 * NOTE: If you change the size of this eachproc structure you need
51 * to change the definition for EACH_QUAD_SIZE.
52 */
53struct eachquadmem {
54 unsigned int priv_mem_start; /* Starting address of this */
55 /* quad's private memory. */
56 /* This is always 0. */
57 /* In MB. */
58 unsigned int priv_mem_size; /* Size of this quad's */
59 /* private memory. */
60 /* In MB. */
61 unsigned int low_shrd_mem_strp_start;/* Starting address of this */
62 /* quad's low shared block */
63 /* (untranslated). */
64 /* In MB. */
65 unsigned int low_shrd_mem_start; /* Starting address of this */
66 /* quad's low shared memory */
67 /* (untranslated). */
68 /* In MB. */
69 unsigned int low_shrd_mem_size; /* Size of this quad's low */
70 /* shared memory. */
71 /* In MB. */
72 unsigned int lmmio_copb_start; /* Starting address of this */
73 /* quad's local memory */
74 /* mapped I/O in the */
75 /* compatibility OPB. */
76 /* In MB. */
77 unsigned int lmmio_copb_size; /* Size of this quad's local */
78 /* memory mapped I/O in the */
79 /* compatibility OPB. */
80 /* In MB. */
81 unsigned int lmmio_nopb_start; /* Starting address of this */
82 /* quad's local memory */
83 /* mapped I/O in the */
84 /* non-compatibility OPB. */
85 /* In MB. */
86 unsigned int lmmio_nopb_size; /* Size of this quad's local */
87 /* memory mapped I/O in the */
88 /* non-compatibility OPB. */
89 /* In MB. */
90 unsigned int io_apic_0_start; /* Starting address of I/O */
91 /* APIC 0. */
92 unsigned int io_apic_0_sz; /* Size I/O APIC 0. */
93 unsigned int io_apic_1_start; /* Starting address of I/O */
94 /* APIC 1. */
95 unsigned int io_apic_1_sz; /* Size I/O APIC 1. */
96 unsigned int hi_shrd_mem_start; /* Starting address of this */
97 /* quad's high shared memory.*/
98 /* In MB. */
99 unsigned int hi_shrd_mem_size; /* Size of this quad's high */
100 /* shared memory. */
101 /* In MB. */
102 unsigned int mps_table_addr; /* Address of this quad's */
103 /* MPS tables from BIOS, */
104 /* in system space.*/
105 unsigned int lcl_MDC_pio_addr; /* Port-I/O address for */
106 /* local access of MDC. */
107 unsigned int rmt_MDC_mmpio_addr; /* MM-Port-I/O address for */
108 /* remote access of MDC. */
109 unsigned int mm_port_io_start; /* Starting address of this */
110 /* quad's memory mapped Port */
111 /* I/O space. */
112 unsigned int mm_port_io_size; /* Size of this quad's memory*/
113 /* mapped Port I/O space. */
114 unsigned int mm_rmt_io_apic_start; /* Starting address of this */
115 /* quad's memory mapped */
116 /* remote I/O APIC space. */
117 unsigned int mm_rmt_io_apic_size; /* Size of this quad's memory*/
118 /* mapped remote I/O APIC */
119 /* space. */
120 unsigned int mm_isa_start; /* Starting address of this */
121 /* quad's memory mapped ISA */
122 /* space (contains MDC */
123 /* memory space). */
124 unsigned int mm_isa_size; /* Size of this quad's memory*/
125 /* mapped ISA space (contains*/
126 /* MDC memory space). */
127 unsigned int rmt_qmi_addr; /* Remote addr to access QMI.*/
128 unsigned int lcl_qmi_addr; /* Local addr to access QMI. */
129};
130
131/*
132 * Note: This structure must be NOT be changed unless the multiproc and
133 * OS are changed to reflect the new structure.
134 */
135struct sys_cfg_data {
136 unsigned int quad_id;
137 unsigned int bsp_proc_id; /* Boot Strap Processor in this quad. */
138 unsigned int scd_version; /* Version number of this table. */
139 unsigned int first_quad_id;
140 unsigned int quads_present31_0; /* 1 bit for each quad */
141 unsigned int quads_present63_32; /* 1 bit for each quad */
142 unsigned int config_flags;
143 unsigned int boot_flags;
144 unsigned int csr_start_addr; /* Absolute value (not in MB) */
145 unsigned int csr_size; /* Absolute value (not in MB) */
146 unsigned int lcl_apic_start_addr; /* Absolute value (not in MB) */
147 unsigned int lcl_apic_size; /* Absolute value (not in MB) */
148 unsigned int low_shrd_mem_base; /* 0 or 512MB or 1GB */
149 unsigned int low_shrd_mem_quad_offset; /* 0,128M,256M,512M,1G */
150 /* may not be totally populated */
151 unsigned int split_mem_enbl; /* 0 for no low shared memory */
152 unsigned int mmio_sz; /* Size of total system memory mapped I/O */
153 /* (in MB). */
154 unsigned int quad_spin_lock; /* Spare location used for quad */
155 /* bringup. */
156 unsigned int nonzero55; /* For checksumming. */
157 unsigned int nonzeroaa; /* For checksumming. */
158 unsigned int scd_magic_number;
159 unsigned int system_type;
160 unsigned int checksum;
161 /*
162 * memory configuration area for each quad
163 */
164 struct eachquadmem eq[MAX_NUMNODES]; /* indexed by quad id */
165};
166
167void numaq_tsc_disable(void);
168
169#endif /* CONFIG_X86_NUMAQ */
170#endif /* _ASM_X86_NUMAQ_H */
171
diff --git a/arch/x86/include/asm/setup.h b/arch/x86/include/asm/setup.h
index d62c9f809bc5..9264f04a4c55 100644
--- a/arch/x86/include/asm/setup.h
+++ b/arch/x86/include/asm/setup.h
@@ -39,12 +39,6 @@ static inline void vsmp_init(void) { }
39 39
40void setup_bios_corruption_check(void); 40void setup_bios_corruption_check(void);
41 41
42#ifdef CONFIG_X86_VISWS
43extern void visws_early_detect(void);
44#else
45static inline void visws_early_detect(void) { }
46#endif
47
48extern unsigned long saved_video_mode; 42extern unsigned long saved_video_mode;
49 43
50extern void reserve_standard_io_resources(void); 44extern void reserve_standard_io_resources(void);
diff --git a/arch/x86/include/asm/visws/cobalt.h b/arch/x86/include/asm/visws/cobalt.h
deleted file mode 100644
index 2edb37637ead..000000000000
--- a/arch/x86/include/asm/visws/cobalt.h
+++ /dev/null
@@ -1,127 +0,0 @@
1#ifndef _ASM_X86_VISWS_COBALT_H
2#define _ASM_X86_VISWS_COBALT_H
3
4#include <asm/fixmap.h>
5
6/*
7 * Cobalt SGI Visual Workstation system ASIC
8 */
9
10#define CO_CPU_NUM_PHYS 0x1e00
11#define CO_CPU_TAB_PHYS (CO_CPU_NUM_PHYS + 2)
12
13#define CO_CPU_MAX 4
14
15#define CO_CPU_PHYS 0xc2000000
16#define CO_APIC_PHYS 0xc4000000
17
18/* see set_fixmap() and asm/fixmap.h */
19#define CO_CPU_VADDR (fix_to_virt(FIX_CO_CPU))
20#define CO_APIC_VADDR (fix_to_virt(FIX_CO_APIC))
21
22/* Cobalt CPU registers -- relative to CO_CPU_VADDR, use co_cpu_*() */
23#define CO_CPU_REV 0x08
24#define CO_CPU_CTRL 0x10
25#define CO_CPU_STAT 0x20
26#define CO_CPU_TIMEVAL 0x30
27
28/* CO_CPU_CTRL bits */
29#define CO_CTRL_TIMERUN 0x04 /* 0 == disabled */
30#define CO_CTRL_TIMEMASK 0x08 /* 0 == unmasked */
31
32/* CO_CPU_STATUS bits */
33#define CO_STAT_TIMEINTR 0x02 /* (r) 1 == int pend, (w) 0 == clear */
34
35/* CO_CPU_TIMEVAL value */
36#define CO_TIME_HZ 100000000 /* Cobalt core rate */
37
38/* Cobalt APIC registers -- relative to CO_APIC_VADDR, use co_apic_*() */
39#define CO_APIC_HI(n) (((n) * 0x10) + 4)
40#define CO_APIC_LO(n) ((n) * 0x10)
41#define CO_APIC_ID 0x0ffc
42
43/* CO_APIC_ID bits */
44#define CO_APIC_ENABLE 0x00000100
45
46/* CO_APIC_LO bits */
47#define CO_APIC_MASK 0x00010000 /* 0 = enabled */
48#define CO_APIC_LEVEL 0x00008000 /* 0 = edge */
49
50/*
51 * Where things are physically wired to Cobalt
52 * #defines with no board _<type>_<rev>_ are common to all (thus far)
53 */
54#define CO_APIC_IDE0 4
55#define CO_APIC_IDE1 2 /* Only on 320 */
56
57#define CO_APIC_8259 12 /* serial, floppy, par-l-l */
58
59/* Lithium PCI Bridge A -- "the one with 82557 Ethernet" */
60#define CO_APIC_PCIA_BASE0 0 /* and 1 */ /* slot 0, line 0 */
61#define CO_APIC_PCIA_BASE123 5 /* and 6 */ /* slot 0, line 1 */
62
63#define CO_APIC_PIIX4_USB 7 /* this one is weird */
64
65/* Lithium PCI Bridge B -- "the one with PIIX4" */
66#define CO_APIC_PCIB_BASE0 8 /* and 9-12 *//* slot 0, line 0 */
67#define CO_APIC_PCIB_BASE123 13 /* 14.15 */ /* slot 0, line 1 */
68
69#define CO_APIC_VIDOUT0 16
70#define CO_APIC_VIDOUT1 17
71#define CO_APIC_VIDIN0 18
72#define CO_APIC_VIDIN1 19
73
74#define CO_APIC_LI_AUDIO 22
75
76#define CO_APIC_AS 24
77#define CO_APIC_RE 25
78
79#define CO_APIC_CPU 28 /* Timer and Cache interrupt */
80#define CO_APIC_NMI 29
81#define CO_APIC_LAST CO_APIC_NMI
82
83/*
84 * This is how irqs are assigned on the Visual Workstation.
85 * Legacy devices get irq's 1-15 (system clock is 0 and is CO_APIC_CPU).
86 * All other devices (including PCI) go to Cobalt and are irq's 16 on up.
87 */
88#define CO_IRQ_APIC0 16 /* irq of apic entry 0 */
89#define IS_CO_APIC(irq) ((irq) >= CO_IRQ_APIC0)
90#define CO_IRQ(apic) (CO_IRQ_APIC0 + (apic)) /* apic ent to irq */
91#define CO_APIC(irq) ((irq) - CO_IRQ_APIC0) /* irq to apic ent */
92#define CO_IRQ_IDE0 14 /* knowledge of... */
93#define CO_IRQ_IDE1 15 /* ... ide driver defaults! */
94#define CO_IRQ_8259 CO_IRQ(CO_APIC_8259)
95
96#ifdef CONFIG_X86_VISWS_APIC
97static inline void co_cpu_write(unsigned long reg, unsigned long v)
98{
99 *((volatile unsigned long *)(CO_CPU_VADDR+reg))=v;
100}
101
102static inline unsigned long co_cpu_read(unsigned long reg)
103{
104 return *((volatile unsigned long *)(CO_CPU_VADDR+reg));
105}
106
107static inline void co_apic_write(unsigned long reg, unsigned long v)
108{
109 *((volatile unsigned long *)(CO_APIC_VADDR+reg))=v;
110}
111
112static inline unsigned long co_apic_read(unsigned long reg)
113{
114 return *((volatile unsigned long *)(CO_APIC_VADDR+reg));
115}
116#endif
117
118extern char visws_board_type;
119
120#define VISWS_320 0
121#define VISWS_540 1
122
123extern char visws_board_rev;
124
125extern int pci_visws_init(void);
126
127#endif /* _ASM_X86_VISWS_COBALT_H */
diff --git a/arch/x86/include/asm/visws/lithium.h b/arch/x86/include/asm/visws/lithium.h
deleted file mode 100644
index a10d89bc1270..000000000000
--- a/arch/x86/include/asm/visws/lithium.h
+++ /dev/null
@@ -1,53 +0,0 @@
1#ifndef _ASM_X86_VISWS_LITHIUM_H
2#define _ASM_X86_VISWS_LITHIUM_H
3
4#include <asm/fixmap.h>
5
6/*
7 * Lithium is the SGI Visual Workstation I/O ASIC
8 */
9
10#define LI_PCI_A_PHYS 0xfc000000 /* Enet is dev 3 */
11#define LI_PCI_B_PHYS 0xfd000000 /* PIIX4 is here */
12
13/* see set_fixmap() and asm/fixmap.h */
14#define LI_PCIA_VADDR (fix_to_virt(FIX_LI_PCIA))
15#define LI_PCIB_VADDR (fix_to_virt(FIX_LI_PCIB))
16
17/* Not a standard PCI? (not in linux/pci.h) */
18#define LI_PCI_BUSNUM 0x44 /* lo8: primary, hi8: sub */
19#define LI_PCI_INTEN 0x46
20
21/* LI_PCI_INTENT bits */
22#define LI_INTA_0 0x0001
23#define LI_INTA_1 0x0002
24#define LI_INTA_2 0x0004
25#define LI_INTA_3 0x0008
26#define LI_INTA_4 0x0010
27#define LI_INTB 0x0020
28#define LI_INTC 0x0040
29#define LI_INTD 0x0080
30
31/* More special purpose macros... */
32static inline void li_pcia_write16(unsigned long reg, unsigned short v)
33{
34 *((volatile unsigned short *)(LI_PCIA_VADDR+reg))=v;
35}
36
37static inline unsigned short li_pcia_read16(unsigned long reg)
38{
39 return *((volatile unsigned short *)(LI_PCIA_VADDR+reg));
40}
41
42static inline void li_pcib_write16(unsigned long reg, unsigned short v)
43{
44 *((volatile unsigned short *)(LI_PCIB_VADDR+reg))=v;
45}
46
47static inline unsigned short li_pcib_read16(unsigned long reg)
48{
49 return *((volatile unsigned short *)(LI_PCIB_VADDR+reg));
50}
51
52#endif /* _ASM_X86_VISWS_LITHIUM_H */
53
diff --git a/arch/x86/include/asm/visws/piix4.h b/arch/x86/include/asm/visws/piix4.h
deleted file mode 100644
index d0af4d338e7f..000000000000
--- a/arch/x86/include/asm/visws/piix4.h
+++ /dev/null
@@ -1,107 +0,0 @@
1#ifndef _ASM_X86_VISWS_PIIX4_H
2#define _ASM_X86_VISWS_PIIX4_H
3
4/*
5 * PIIX4 as used on SGI Visual Workstations
6 */
7
8#define PIIX_PM_START 0x0F80
9
10#define SIO_GPIO_START 0x0FC0
11
12#define SIO_PM_START 0x0FC8
13
14#define PMBASE PIIX_PM_START
15#define GPIREG0 (PMBASE+0x30)
16#define GPIREG(x) (GPIREG0+((x)/8))
17#define GPIBIT(x) (1 << ((x)%8))
18
19#define PIIX_GPI_BD_ID1 18
20#define PIIX_GPI_BD_ID2 19
21#define PIIX_GPI_BD_ID3 20
22#define PIIX_GPI_BD_ID4 21
23#define PIIX_GPI_BD_REG GPIREG(PIIX_GPI_BD_ID1)
24#define PIIX_GPI_BD_MASK (GPIBIT(PIIX_GPI_BD_ID1) | \
25 GPIBIT(PIIX_GPI_BD_ID2) | \
26 GPIBIT(PIIX_GPI_BD_ID3) | \
27 GPIBIT(PIIX_GPI_BD_ID4) )
28
29#define PIIX_GPI_BD_SHIFT (PIIX_GPI_BD_ID1 % 8)
30
31#define SIO_INDEX 0x2e
32#define SIO_DATA 0x2f
33
34#define SIO_DEV_SEL 0x7
35#define SIO_DEV_ENB 0x30
36#define SIO_DEV_MSB 0x60
37#define SIO_DEV_LSB 0x61
38
39#define SIO_GP_DEV 0x7
40
41#define SIO_GP_BASE SIO_GPIO_START
42#define SIO_GP_MSB (SIO_GP_BASE>>8)
43#define SIO_GP_LSB (SIO_GP_BASE&0xff)
44
45#define SIO_GP_DATA1 (SIO_GP_BASE+0)
46
47#define SIO_PM_DEV 0x8
48
49#define SIO_PM_BASE SIO_PM_START
50#define SIO_PM_MSB (SIO_PM_BASE>>8)
51#define SIO_PM_LSB (SIO_PM_BASE&0xff)
52#define SIO_PM_INDEX (SIO_PM_BASE+0)
53#define SIO_PM_DATA (SIO_PM_BASE+1)
54
55#define SIO_PM_FER2 0x1
56
57#define SIO_PM_GP_EN 0x80
58
59
60
61/*
62 * This is the dev/reg where generating a config cycle will
63 * result in a PCI special cycle.
64 */
65#define SPECIAL_DEV 0xff
66#define SPECIAL_REG 0x00
67
68/*
69 * PIIX4 needs to see a special cycle with the following data
70 * to be convinced the processor has gone into the stop grant
71 * state. PIIX4 insists on seeing this before it will power
72 * down a system.
73 */
74#define PIIX_SPECIAL_STOP 0x00120002
75
76#define PIIX4_RESET_PORT 0xcf9
77#define PIIX4_RESET_VAL 0x6
78
79#define PMSTS_PORT 0xf80 // 2 bytes PM Status
80#define PMEN_PORT 0xf82 // 2 bytes PM Enable
81#define PMCNTRL_PORT 0xf84 // 2 bytes PM Control
82
83#define PM_SUSPEND_ENABLE 0x2000 // start sequence to suspend state
84
85/*
86 * PMSTS and PMEN I/O bit definitions.
87 * (Bits are the same in both registers)
88 */
89#define PM_STS_RSM (1<<15) // Resume Status
90#define PM_STS_PWRBTNOR (1<<11) // Power Button Override
91#define PM_STS_RTC (1<<10) // RTC status
92#define PM_STS_PWRBTN (1<<8) // Power Button Pressed?
93#define PM_STS_GBL (1<<5) // Global Status
94#define PM_STS_BM (1<<4) // Bus Master Status
95#define PM_STS_TMROF (1<<0) // Timer Overflow Status.
96
97/*
98 * Stop clock GPI register
99 */
100#define PIIX_GPIREG0 (0xf80 + 0x30)
101
102/*
103 * Stop clock GPI bit in GPIREG0
104 */
105#define PIIX_GPI_STPCLK 0x4 // STPCLK signal routed back in
106
107#endif /* _ASM_X86_VISWS_PIIX4_H */
diff --git a/arch/x86/include/asm/visws/sgivw.h b/arch/x86/include/asm/visws/sgivw.h
deleted file mode 100644
index 5fbf63e1003c..000000000000
--- a/arch/x86/include/asm/visws/sgivw.h
+++ /dev/null
@@ -1,5 +0,0 @@
1/*
2 * Frame buffer position and size:
3 */
4extern unsigned long sgivwfb_mem_phys;
5extern unsigned long sgivwfb_mem_size;
diff --git a/arch/x86/kernel/acpi/boot.c b/arch/x86/kernel/acpi/boot.c
index 8e61d23b8f64..86281ffb96d6 100644
--- a/arch/x86/kernel/acpi/boot.c
+++ b/arch/x86/kernel/acpi/boot.c
@@ -903,10 +903,6 @@ static int __init acpi_parse_madt_lapic_entries(void)
903#ifdef CONFIG_X86_IO_APIC 903#ifdef CONFIG_X86_IO_APIC
904#define MP_ISA_BUS 0 904#define MP_ISA_BUS 0
905 905
906#ifdef CONFIG_X86_ES7000
907extern int es7000_plat;
908#endif
909
910void __init mp_override_legacy_irq(u8 bus_irq, u8 polarity, u8 trigger, u32 gsi) 906void __init mp_override_legacy_irq(u8 bus_irq, u8 polarity, u8 trigger, u32 gsi)
911{ 907{
912 int ioapic; 908 int ioapic;
@@ -956,14 +952,6 @@ void __init mp_config_acpi_legacy_irqs(void)
956 set_bit(MP_ISA_BUS, mp_bus_not_pci); 952 set_bit(MP_ISA_BUS, mp_bus_not_pci);
957 pr_debug("Bus #%d is ISA\n", MP_ISA_BUS); 953 pr_debug("Bus #%d is ISA\n", MP_ISA_BUS);
958 954
959#ifdef CONFIG_X86_ES7000
960 /*
961 * Older generations of ES7000 have no legacy identity mappings
962 */
963 if (es7000_plat == 1)
964 return;
965#endif
966
967 /* 955 /*
968 * Use the default configuration for the IRQs 0-15. Unless 956 * Use the default configuration for the IRQs 0-15. Unless
969 * overridden by (MADT) interrupt source override entries. 957 * overridden by (MADT) interrupt source override entries.
diff --git a/arch/x86/kernel/apic/Makefile b/arch/x86/kernel/apic/Makefile
index 0ae0323b1f9c..dcb5b15401ce 100644
--- a/arch/x86/kernel/apic/Makefile
+++ b/arch/x86/kernel/apic/Makefile
@@ -18,10 +18,7 @@ obj-y += apic_flat_64.o
18endif 18endif
19 19
20# APIC probe will depend on the listing order here 20# APIC probe will depend on the listing order here
21obj-$(CONFIG_X86_NUMAQ) += numaq_32.o
22obj-$(CONFIG_X86_SUMMIT) += summit_32.o
23obj-$(CONFIG_X86_BIGSMP) += bigsmp_32.o 21obj-$(CONFIG_X86_BIGSMP) += bigsmp_32.o
24obj-$(CONFIG_X86_ES7000) += es7000_32.o
25 22
26# For 32bit, probe_32 need to be listed last 23# For 32bit, probe_32 need to be listed last
27obj-$(CONFIG_X86_LOCAL_APIC) += probe_$(BITS).o 24obj-$(CONFIG_X86_LOCAL_APIC) += probe_$(BITS).o
diff --git a/arch/x86/kernel/apic/apic.c b/arch/x86/kernel/apic/apic.c
index 53e20531470e..481ae38f6a44 100644
--- a/arch/x86/kernel/apic/apic.c
+++ b/arch/x86/kernel/apic/apic.c
@@ -2136,7 +2136,6 @@ int generic_processor_info(int apicid, int version)
2136 * 2136 *
2137 * - arch/x86/kernel/mpparse.c: MP_processor_info() 2137 * - arch/x86/kernel/mpparse.c: MP_processor_info()
2138 * - arch/x86/mm/amdtopology.c: amd_numa_init() 2138 * - arch/x86/mm/amdtopology.c: amd_numa_init()
2139 * - arch/x86/platform/visws/visws_quirks.c: MP_processor_info()
2140 * 2139 *
2141 * This function is executed with the modified 2140 * This function is executed with the modified
2142 * boot_cpu_physical_apicid. So, disabled_cpu_apicid kernel 2141 * boot_cpu_physical_apicid. So, disabled_cpu_apicid kernel
diff --git a/arch/x86/kernel/apic/es7000_32.c b/arch/x86/kernel/apic/es7000_32.c
deleted file mode 100644
index 6f8f8b348a39..000000000000
--- a/arch/x86/kernel/apic/es7000_32.c
+++ /dev/null
@@ -1,738 +0,0 @@
1/*
2 * Written by: Garry Forsgren, Unisys Corporation
3 * Natalie Protasevich, Unisys Corporation
4 *
5 * This file contains the code to configure and interface
6 * with Unisys ES7000 series hardware system manager.
7 *
8 * Copyright (c) 2003 Unisys Corporation.
9 * Copyright (C) 2009, Red Hat, Inc., Ingo Molnar
10 *
11 * All Rights Reserved.
12 *
13 * This program is free software; you can redistribute it and/or modify it
14 * under the terms of version 2 of the GNU General Public License as
15 * published by the Free Software Foundation.
16 *
17 * This program is distributed in the hope that it would be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
20 *
21 * You should have received a copy of the GNU General Public License along
22 * with this program; if not, write the Free Software Foundation, Inc., 59
23 * Temple Place - Suite 330, Boston MA 02111-1307, USA.
24 *
25 * Contact information: Unisys Corporation, Township Line & Union Meeting
26 * Roads-A, Unisys Way, Blue Bell, Pennsylvania, 19424, or:
27 *
28 * http://www.unisys.com
29 */
30
31#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
32
33#include <linux/notifier.h>
34#include <linux/spinlock.h>
35#include <linux/cpumask.h>
36#include <linux/threads.h>
37#include <linux/kernel.h>
38#include <linux/module.h>
39#include <linux/reboot.h>
40#include <linux/string.h>
41#include <linux/types.h>
42#include <linux/errno.h>
43#include <linux/acpi.h>
44#include <linux/init.h>
45#include <linux/gfp.h>
46#include <linux/nmi.h>
47#include <linux/smp.h>
48#include <linux/io.h>
49
50#include <asm/apicdef.h>
51#include <linux/atomic.h>
52#include <asm/fixmap.h>
53#include <asm/mpspec.h>
54#include <asm/setup.h>
55#include <asm/apic.h>
56#include <asm/ipi.h>
57
58/*
59 * ES7000 chipsets
60 */
61
62#define NON_UNISYS 0
63#define ES7000_CLASSIC 1
64#define ES7000_ZORRO 2
65
66#define MIP_REG 1
67#define MIP_PSAI_REG 4
68
69#define MIP_BUSY 1
70#define MIP_SPIN 0xf0000
71#define MIP_VALID 0x0100000000000000ULL
72#define MIP_SW_APIC 0x1020b
73
74#define MIP_PORT(val) ((val >> 32) & 0xffff)
75
76#define MIP_RD_LO(val) (val & 0xffffffff)
77
78struct mip_reg {
79 unsigned long long off_0x00;
80 unsigned long long off_0x08;
81 unsigned long long off_0x10;
82 unsigned long long off_0x18;
83 unsigned long long off_0x20;
84 unsigned long long off_0x28;
85 unsigned long long off_0x30;
86 unsigned long long off_0x38;
87};
88
89struct mip_reg_info {
90 unsigned long long mip_info;
91 unsigned long long delivery_info;
92 unsigned long long host_reg;
93 unsigned long long mip_reg;
94};
95
96struct psai {
97 unsigned long long entry_type;
98 unsigned long long addr;
99 unsigned long long bep_addr;
100};
101
102#ifdef CONFIG_ACPI
103
104struct es7000_oem_table {
105 struct acpi_table_header Header;
106 u32 OEMTableAddr;
107 u32 OEMTableSize;
108};
109
110static unsigned long oem_addrX;
111static unsigned long oem_size;
112
113#endif
114
115/*
116 * ES7000 Globals
117 */
118
119static volatile unsigned long *psai;
120static struct mip_reg *mip_reg;
121static struct mip_reg *host_reg;
122static int mip_port;
123static unsigned long mip_addr;
124static unsigned long host_addr;
125
126int es7000_plat;
127
128/*
129 * GSI override for ES7000 platforms.
130 */
131
132
133static int wakeup_secondary_cpu_via_mip(int cpu, unsigned long eip)
134{
135 unsigned long vect = 0, psaival = 0;
136
137 if (psai == NULL)
138 return -1;
139
140 vect = ((unsigned long)__pa(eip)/0x1000) << 16;
141 psaival = (0x1000000 | vect | cpu);
142
143 while (*psai & 0x1000000)
144 ;
145
146 *psai = psaival;
147
148 return 0;
149}
150
151static int es7000_apic_is_cluster(void)
152{
153 /* MPENTIUMIII */
154 if (boot_cpu_data.x86 == 6 &&
155 (boot_cpu_data.x86_model >= 7 && boot_cpu_data.x86_model <= 11))
156 return 1;
157
158 return 0;
159}
160
161static void setup_unisys(void)
162{
163 /*
164 * Determine the generation of the ES7000 currently running.
165 *
166 * es7000_plat = 1 if the machine is a 5xx ES7000 box
167 * es7000_plat = 2 if the machine is a x86_64 ES7000 box
168 *
169 */
170 if (!(boot_cpu_data.x86 <= 15 && boot_cpu_data.x86_model <= 2))
171 es7000_plat = ES7000_ZORRO;
172 else
173 es7000_plat = ES7000_CLASSIC;
174}
175
176/*
177 * Parse the OEM Table:
178 */
179static int parse_unisys_oem(char *oemptr)
180{
181 int i;
182 int success = 0;
183 unsigned char type, size;
184 unsigned long val;
185 char *tp = NULL;
186 struct psai *psaip = NULL;
187 struct mip_reg_info *mi;
188 struct mip_reg *host, *mip;
189
190 tp = oemptr;
191
192 tp += 8;
193
194 for (i = 0; i <= 6; i++) {
195 type = *tp++;
196 size = *tp++;
197 tp -= 2;
198 switch (type) {
199 case MIP_REG:
200 mi = (struct mip_reg_info *)tp;
201 val = MIP_RD_LO(mi->host_reg);
202 host_addr = val;
203 host = (struct mip_reg *)val;
204 host_reg = __va(host);
205 val = MIP_RD_LO(mi->mip_reg);
206 mip_port = MIP_PORT(mi->mip_info);
207 mip_addr = val;
208 mip = (struct mip_reg *)val;
209 mip_reg = __va(mip);
210 pr_debug("host_reg = 0x%lx\n",
211 (unsigned long)host_reg);
212 pr_debug("mip_reg = 0x%lx\n",
213 (unsigned long)mip_reg);
214 success++;
215 break;
216 case MIP_PSAI_REG:
217 psaip = (struct psai *)tp;
218 if (tp != NULL) {
219 if (psaip->addr)
220 psai = __va(psaip->addr);
221 else
222 psai = NULL;
223 success++;
224 }
225 break;
226 default:
227 break;
228 }
229 tp += size;
230 }
231
232 if (success < 2)
233 es7000_plat = NON_UNISYS;
234 else
235 setup_unisys();
236
237 return es7000_plat;
238}
239
240#ifdef CONFIG_ACPI
241static int __init find_unisys_acpi_oem_table(unsigned long *oem_addr)
242{
243 struct acpi_table_header *header = NULL;
244 struct es7000_oem_table *table;
245 acpi_size tbl_size;
246 acpi_status ret;
247 int i = 0;
248
249 for (;;) {
250 ret = acpi_get_table_with_size("OEM1", i++, &header, &tbl_size);
251 if (!ACPI_SUCCESS(ret))
252 return -1;
253
254 if (!memcmp((char *) &header->oem_id, "UNISYS", 6))
255 break;
256
257 early_acpi_os_unmap_memory(header, tbl_size);
258 }
259
260 table = (void *)header;
261
262 oem_addrX = table->OEMTableAddr;
263 oem_size = table->OEMTableSize;
264
265 early_acpi_os_unmap_memory(header, tbl_size);
266
267 *oem_addr = (unsigned long)__acpi_map_table(oem_addrX, oem_size);
268
269 return 0;
270}
271
272static void __init unmap_unisys_acpi_oem_table(unsigned long oem_addr)
273{
274 if (!oem_addr)
275 return;
276
277 __acpi_unmap_table((char *)oem_addr, oem_size);
278}
279
280static int es7000_check_dsdt(void)
281{
282 struct acpi_table_header header;
283
284 if (ACPI_SUCCESS(acpi_get_table_header(ACPI_SIG_DSDT, 0, &header)) &&
285 !strncmp(header.oem_id, "UNISYS", 6))
286 return 1;
287 return 0;
288}
289
290static int es7000_acpi_ret;
291
292/* Hook from generic ACPI tables.c */
293static int __init es7000_acpi_madt_oem_check(char *oem_id, char *oem_table_id)
294{
295 unsigned long oem_addr = 0;
296 int check_dsdt;
297 int ret = 0;
298
299 /* check dsdt at first to avoid clear fix_map for oem_addr */
300 check_dsdt = es7000_check_dsdt();
301
302 if (!find_unisys_acpi_oem_table(&oem_addr)) {
303 if (check_dsdt) {
304 ret = parse_unisys_oem((char *)oem_addr);
305 } else {
306 setup_unisys();
307 ret = 1;
308 }
309 /*
310 * we need to unmap it
311 */
312 unmap_unisys_acpi_oem_table(oem_addr);
313 }
314
315 es7000_acpi_ret = ret;
316
317 return ret && !es7000_apic_is_cluster();
318}
319
320static int es7000_acpi_madt_oem_check_cluster(char *oem_id, char *oem_table_id)
321{
322 int ret = es7000_acpi_ret;
323
324 return ret && es7000_apic_is_cluster();
325}
326
327#else /* !CONFIG_ACPI: */
328static int es7000_acpi_madt_oem_check(char *oem_id, char *oem_table_id)
329{
330 return 0;
331}
332
333static int es7000_acpi_madt_oem_check_cluster(char *oem_id, char *oem_table_id)
334{
335 return 0;
336}
337#endif /* !CONFIG_ACPI */
338
339static void es7000_spin(int n)
340{
341 int i = 0;
342
343 while (i++ < n)
344 rep_nop();
345}
346
347static int es7000_mip_write(struct mip_reg *mip_reg)
348{
349 int status = 0;
350 int spin;
351
352 spin = MIP_SPIN;
353 while ((host_reg->off_0x38 & MIP_VALID) != 0) {
354 if (--spin <= 0) {
355 WARN(1, "Timeout waiting for Host Valid Flag\n");
356 return -1;
357 }
358 es7000_spin(MIP_SPIN);
359 }
360
361 memcpy(host_reg, mip_reg, sizeof(struct mip_reg));
362 outb(1, mip_port);
363
364 spin = MIP_SPIN;
365
366 while ((mip_reg->off_0x38 & MIP_VALID) == 0) {
367 if (--spin <= 0) {
368 WARN(1, "Timeout waiting for MIP Valid Flag\n");
369 return -1;
370 }
371 es7000_spin(MIP_SPIN);
372 }
373
374 status = (mip_reg->off_0x00 & 0xffff0000000000ULL) >> 48;
375 mip_reg->off_0x38 &= ~MIP_VALID;
376
377 return status;
378}
379
380static void es7000_enable_apic_mode(void)
381{
382 struct mip_reg es7000_mip_reg;
383 int mip_status;
384
385 if (!es7000_plat)
386 return;
387
388 pr_info("Enabling APIC mode.\n");
389 memset(&es7000_mip_reg, 0, sizeof(struct mip_reg));
390 es7000_mip_reg.off_0x00 = MIP_SW_APIC;
391 es7000_mip_reg.off_0x38 = MIP_VALID;
392
393 while ((mip_status = es7000_mip_write(&es7000_mip_reg)) != 0)
394 WARN(1, "Command failed, status = %x\n", mip_status);
395}
396
397static unsigned int es7000_get_apic_id(unsigned long x)
398{
399 return (x >> 24) & 0xFF;
400}
401
402static void es7000_send_IPI_mask(const struct cpumask *mask, int vector)
403{
404 default_send_IPI_mask_sequence_phys(mask, vector);
405}
406
407static void es7000_send_IPI_allbutself(int vector)
408{
409 default_send_IPI_mask_allbutself_phys(cpu_online_mask, vector);
410}
411
412static void es7000_send_IPI_all(int vector)
413{
414 es7000_send_IPI_mask(cpu_online_mask, vector);
415}
416
417static int es7000_apic_id_registered(void)
418{
419 return 1;
420}
421
422static const struct cpumask *target_cpus_cluster(void)
423{
424 return cpu_all_mask;
425}
426
427static const struct cpumask *es7000_target_cpus(void)
428{
429 return cpumask_of(smp_processor_id());
430}
431
432static unsigned long es7000_check_apicid_used(physid_mask_t *map, int apicid)
433{
434 return 0;
435}
436
437static unsigned long es7000_check_apicid_present(int bit)
438{
439 return physid_isset(bit, phys_cpu_present_map);
440}
441
442static int es7000_early_logical_apicid(int cpu)
443{
444 /* on es7000, logical apicid is the same as physical */
445 return early_per_cpu(x86_bios_cpu_apicid, cpu);
446}
447
448static unsigned long calculate_ldr(int cpu)
449{
450 unsigned long id = per_cpu(x86_bios_cpu_apicid, cpu);
451
452 return SET_APIC_LOGICAL_ID(id);
453}
454
455/*
456 * Set up the logical destination ID.
457 *
458 * Intel recommends to set DFR, LdR and TPR before enabling
459 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
460 * document number 292116). So here it goes...
461 */
462static void es7000_init_apic_ldr_cluster(void)
463{
464 unsigned long val;
465 int cpu = smp_processor_id();
466
467 apic_write(APIC_DFR, APIC_DFR_CLUSTER);
468 val = calculate_ldr(cpu);
469 apic_write(APIC_LDR, val);
470}
471
472static void es7000_init_apic_ldr(void)
473{
474 unsigned long val;
475 int cpu = smp_processor_id();
476
477 apic_write(APIC_DFR, APIC_DFR_FLAT);
478 val = calculate_ldr(cpu);
479 apic_write(APIC_LDR, val);
480}
481
482static void es7000_setup_apic_routing(void)
483{
484 int apic = per_cpu(x86_bios_cpu_apicid, smp_processor_id());
485
486 pr_info("Enabling APIC mode: %s. Using %d I/O APICs, target cpus %lx\n",
487 (apic_version[apic] == 0x14) ?
488 "Physical Cluster" : "Logical Cluster",
489 nr_ioapics, cpumask_bits(es7000_target_cpus())[0]);
490}
491
492static int es7000_cpu_present_to_apicid(int mps_cpu)
493{
494 if (!mps_cpu)
495 return boot_cpu_physical_apicid;
496 else if (mps_cpu < nr_cpu_ids)
497 return per_cpu(x86_bios_cpu_apicid, mps_cpu);
498 else
499 return BAD_APICID;
500}
501
502static int cpu_id;
503
504static void es7000_apicid_to_cpu_present(int phys_apicid, physid_mask_t *retmap)
505{
506 physid_set_mask_of_physid(cpu_id, retmap);
507 ++cpu_id;
508}
509
510static void es7000_ioapic_phys_id_map(physid_mask_t *phys_map, physid_mask_t *retmap)
511{
512 /* For clustered we don't have a good way to do this yet - hack */
513 physids_promote(0xFFL, retmap);
514}
515
516static int es7000_check_phys_apicid_present(int cpu_physical_apicid)
517{
518 boot_cpu_physical_apicid = read_apic_id();
519 return 1;
520}
521
522static inline int
523es7000_cpu_mask_to_apicid(const struct cpumask *cpumask, unsigned int *dest_id)
524{
525 unsigned int round = 0;
526 unsigned int cpu, uninitialized_var(apicid);
527
528 /*
529 * The cpus in the mask must all be on the apic cluster.
530 */
531 for_each_cpu_and(cpu, cpumask, cpu_online_mask) {
532 int new_apicid = early_per_cpu(x86_cpu_to_logical_apicid, cpu);
533
534 if (round && APIC_CLUSTER(apicid) != APIC_CLUSTER(new_apicid)) {
535 WARN(1, "Not a valid mask!");
536
537 return -EINVAL;
538 }
539 apicid |= new_apicid;
540 round++;
541 }
542 if (!round)
543 return -EINVAL;
544 *dest_id = apicid;
545 return 0;
546}
547
548static int
549es7000_cpu_mask_to_apicid_and(const struct cpumask *inmask,
550 const struct cpumask *andmask,
551 unsigned int *apicid)
552{
553 cpumask_var_t cpumask;
554 *apicid = early_per_cpu(x86_cpu_to_logical_apicid, 0);
555
556 if (!alloc_cpumask_var(&cpumask, GFP_ATOMIC))
557 return 0;
558
559 cpumask_and(cpumask, inmask, andmask);
560 es7000_cpu_mask_to_apicid(cpumask, apicid);
561
562 free_cpumask_var(cpumask);
563
564 return 0;
565}
566
567static int es7000_phys_pkg_id(int cpuid_apic, int index_msb)
568{
569 return cpuid_apic >> index_msb;
570}
571
572static int probe_es7000(void)
573{
574 /* probed later in mptable/ACPI hooks */
575 return 0;
576}
577
578static int es7000_mps_ret;
579static int es7000_mps_oem_check(struct mpc_table *mpc, char *oem,
580 char *productid)
581{
582 int ret = 0;
583
584 if (mpc->oemptr) {
585 struct mpc_oemtable *oem_table =
586 (struct mpc_oemtable *)mpc->oemptr;
587
588 if (!strncmp(oem, "UNISYS", 6))
589 ret = parse_unisys_oem((char *)oem_table);
590 }
591
592 es7000_mps_ret = ret;
593
594 return ret && !es7000_apic_is_cluster();
595}
596
597static int es7000_mps_oem_check_cluster(struct mpc_table *mpc, char *oem,
598 char *productid)
599{
600 int ret = es7000_mps_ret;
601
602 return ret && es7000_apic_is_cluster();
603}
604
605/* We've been warned by a false positive warning.Use __refdata to keep calm. */
606static struct apic __refdata apic_es7000_cluster = {
607
608 .name = "es7000",
609 .probe = probe_es7000,
610 .acpi_madt_oem_check = es7000_acpi_madt_oem_check_cluster,
611 .apic_id_valid = default_apic_id_valid,
612 .apic_id_registered = es7000_apic_id_registered,
613
614 .irq_delivery_mode = dest_LowestPrio,
615 /* logical delivery broadcast to all procs: */
616 .irq_dest_mode = 1,
617
618 .target_cpus = target_cpus_cluster,
619 .disable_esr = 1,
620 .dest_logical = 0,
621 .check_apicid_used = es7000_check_apicid_used,
622 .check_apicid_present = es7000_check_apicid_present,
623
624 .vector_allocation_domain = flat_vector_allocation_domain,
625 .init_apic_ldr = es7000_init_apic_ldr_cluster,
626
627 .ioapic_phys_id_map = es7000_ioapic_phys_id_map,
628 .setup_apic_routing = es7000_setup_apic_routing,
629 .multi_timer_check = NULL,
630 .cpu_present_to_apicid = es7000_cpu_present_to_apicid,
631 .apicid_to_cpu_present = es7000_apicid_to_cpu_present,
632 .setup_portio_remap = NULL,
633 .check_phys_apicid_present = es7000_check_phys_apicid_present,
634 .enable_apic_mode = es7000_enable_apic_mode,
635 .phys_pkg_id = es7000_phys_pkg_id,
636 .mps_oem_check = es7000_mps_oem_check_cluster,
637
638 .get_apic_id = es7000_get_apic_id,
639 .set_apic_id = NULL,
640 .apic_id_mask = 0xFF << 24,
641
642 .cpu_mask_to_apicid_and = es7000_cpu_mask_to_apicid_and,
643
644 .send_IPI_mask = es7000_send_IPI_mask,
645 .send_IPI_mask_allbutself = NULL,
646 .send_IPI_allbutself = es7000_send_IPI_allbutself,
647 .send_IPI_all = es7000_send_IPI_all,
648 .send_IPI_self = default_send_IPI_self,
649
650 .wakeup_secondary_cpu = wakeup_secondary_cpu_via_mip,
651
652 .trampoline_phys_low = 0x467,
653 .trampoline_phys_high = 0x469,
654
655 .wait_for_init_deassert = false,
656 /* Nothing to do for most platforms, since cleared by the INIT cycle: */
657 .smp_callin_clear_local_apic = NULL,
658 .inquire_remote_apic = default_inquire_remote_apic,
659
660 .read = native_apic_mem_read,
661 .write = native_apic_mem_write,
662 .eoi_write = native_apic_mem_write,
663 .icr_read = native_apic_icr_read,
664 .icr_write = native_apic_icr_write,
665 .wait_icr_idle = native_apic_wait_icr_idle,
666 .safe_wait_icr_idle = native_safe_apic_wait_icr_idle,
667
668 .x86_32_early_logical_apicid = es7000_early_logical_apicid,
669};
670
671static struct apic __refdata apic_es7000 = {
672
673 .name = "es7000",
674 .probe = probe_es7000,
675 .acpi_madt_oem_check = es7000_acpi_madt_oem_check,
676 .apic_id_valid = default_apic_id_valid,
677 .apic_id_registered = es7000_apic_id_registered,
678
679 .irq_delivery_mode = dest_Fixed,
680 /* phys delivery to target CPUs: */
681 .irq_dest_mode = 0,
682
683 .target_cpus = es7000_target_cpus,
684 .disable_esr = 1,
685 .dest_logical = 0,
686 .check_apicid_used = es7000_check_apicid_used,
687 .check_apicid_present = es7000_check_apicid_present,
688
689 .vector_allocation_domain = flat_vector_allocation_domain,
690 .init_apic_ldr = es7000_init_apic_ldr,
691
692 .ioapic_phys_id_map = es7000_ioapic_phys_id_map,
693 .setup_apic_routing = es7000_setup_apic_routing,
694 .multi_timer_check = NULL,
695 .cpu_present_to_apicid = es7000_cpu_present_to_apicid,
696 .apicid_to_cpu_present = es7000_apicid_to_cpu_present,
697 .setup_portio_remap = NULL,
698 .check_phys_apicid_present = es7000_check_phys_apicid_present,
699 .enable_apic_mode = es7000_enable_apic_mode,
700 .phys_pkg_id = es7000_phys_pkg_id,
701 .mps_oem_check = es7000_mps_oem_check,
702
703 .get_apic_id = es7000_get_apic_id,
704 .set_apic_id = NULL,
705 .apic_id_mask = 0xFF << 24,
706
707 .cpu_mask_to_apicid_and = es7000_cpu_mask_to_apicid_and,
708
709 .send_IPI_mask = es7000_send_IPI_mask,
710 .send_IPI_mask_allbutself = NULL,
711 .send_IPI_allbutself = es7000_send_IPI_allbutself,
712 .send_IPI_all = es7000_send_IPI_all,
713 .send_IPI_self = default_send_IPI_self,
714
715 .trampoline_phys_low = 0x467,
716 .trampoline_phys_high = 0x469,
717
718 .wait_for_init_deassert = true,
719 /* Nothing to do for most platforms, since cleared by the INIT cycle: */
720 .smp_callin_clear_local_apic = NULL,
721 .inquire_remote_apic = default_inquire_remote_apic,
722
723 .read = native_apic_mem_read,
724 .write = native_apic_mem_write,
725 .eoi_write = native_apic_mem_write,
726 .icr_read = native_apic_icr_read,
727 .icr_write = native_apic_icr_write,
728 .wait_icr_idle = native_apic_wait_icr_idle,
729 .safe_wait_icr_idle = native_safe_apic_wait_icr_idle,
730
731 .x86_32_early_logical_apicid = es7000_early_logical_apicid,
732};
733
734/*
735 * Need to check for es7000 followed by es7000_cluster, so this order
736 * in apic_drivers is important.
737 */
738apic_drivers(apic_es7000, apic_es7000_cluster);
diff --git a/arch/x86/kernel/apic/numaq_32.c b/arch/x86/kernel/apic/numaq_32.c
deleted file mode 100644
index 030ea1c04f72..000000000000
--- a/arch/x86/kernel/apic/numaq_32.c
+++ /dev/null
@@ -1,524 +0,0 @@
1/*
2 * Written by: Patricia Gaughen, IBM Corporation
3 *
4 * Copyright (C) 2002, IBM Corp.
5 * Copyright (C) 2009, Red Hat, Inc., Ingo Molnar
6 *
7 * All rights reserved.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful, but
15 * WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
17 * NON INFRINGEMENT. See the GNU General Public License for more
18 * details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 *
24 * Send feedback to <gone@us.ibm.com>
25 */
26#include <linux/nodemask.h>
27#include <linux/topology.h>
28#include <linux/bootmem.h>
29#include <linux/memblock.h>
30#include <linux/threads.h>
31#include <linux/cpumask.h>
32#include <linux/kernel.h>
33#include <linux/mmzone.h>
34#include <linux/module.h>
35#include <linux/string.h>
36#include <linux/init.h>
37#include <linux/numa.h>
38#include <linux/smp.h>
39#include <linux/io.h>
40#include <linux/mm.h>
41
42#include <asm/processor.h>
43#include <asm/fixmap.h>
44#include <asm/mpspec.h>
45#include <asm/numaq.h>
46#include <asm/setup.h>
47#include <asm/apic.h>
48#include <asm/e820.h>
49#include <asm/ipi.h>
50
51int found_numaq;
52
53/*
54 * Have to match translation table entries to main table entries by counter
55 * hence the mpc_record variable .... can't see a less disgusting way of
56 * doing this ....
57 */
58struct mpc_trans {
59 unsigned char mpc_type;
60 unsigned char trans_len;
61 unsigned char trans_type;
62 unsigned char trans_quad;
63 unsigned char trans_global;
64 unsigned char trans_local;
65 unsigned short trans_reserved;
66};
67
68static int mpc_record;
69
70static struct mpc_trans *translation_table[MAX_MPC_ENTRY];
71
72int mp_bus_id_to_node[MAX_MP_BUSSES];
73int mp_bus_id_to_local[MAX_MP_BUSSES];
74int quad_local_to_mp_bus_id[NR_CPUS/4][4];
75
76
77static inline void numaq_register_node(int node, struct sys_cfg_data *scd)
78{
79 struct eachquadmem *eq = scd->eq + node;
80 u64 start = (u64)(eq->hi_shrd_mem_start - eq->priv_mem_size) << 20;
81 u64 end = (u64)(eq->hi_shrd_mem_start + eq->hi_shrd_mem_size) << 20;
82 int ret;
83
84 node_set(node, numa_nodes_parsed);
85 ret = numa_add_memblk(node, start, end);
86 BUG_ON(ret < 0);
87}
88
89/*
90 * Function: smp_dump_qct()
91 *
92 * Description: gets memory layout from the quad config table. This
93 * function also updates numa_nodes_parsed with the nodes (quads) present.
94 */
95static void __init smp_dump_qct(void)
96{
97 struct sys_cfg_data *scd;
98 int node;
99
100 scd = (void *)__va(SYS_CFG_DATA_PRIV_ADDR);
101
102 for_each_node(node) {
103 if (scd->quads_present31_0 & (1 << node))
104 numaq_register_node(node, scd);
105 }
106}
107
108void numaq_tsc_disable(void)
109{
110 if (!found_numaq)
111 return;
112
113 if (num_online_nodes() > 1) {
114 printk(KERN_DEBUG "NUMAQ: disabling TSC\n");
115 setup_clear_cpu_cap(X86_FEATURE_TSC);
116 }
117}
118
119static void __init numaq_tsc_init(void)
120{
121 numaq_tsc_disable();
122}
123
124static inline int generate_logical_apicid(int quad, int phys_apicid)
125{
126 return (quad << 4) + (phys_apicid ? phys_apicid << 1 : 1);
127}
128
129/* x86_quirks member */
130static int mpc_apic_id(struct mpc_cpu *m)
131{
132 int quad = translation_table[mpc_record]->trans_quad;
133 int logical_apicid = generate_logical_apicid(quad, m->apicid);
134
135 printk(KERN_DEBUG
136 "Processor #%d %u:%u APIC version %d (quad %d, apic %d)\n",
137 m->apicid, (m->cpufeature & CPU_FAMILY_MASK) >> 8,
138 (m->cpufeature & CPU_MODEL_MASK) >> 4,
139 m->apicver, quad, logical_apicid);
140
141 return logical_apicid;
142}
143
144/* x86_quirks member */
145static void mpc_oem_bus_info(struct mpc_bus *m, char *name)
146{
147 int quad = translation_table[mpc_record]->trans_quad;
148 int local = translation_table[mpc_record]->trans_local;
149
150 mp_bus_id_to_node[m->busid] = quad;
151 mp_bus_id_to_local[m->busid] = local;
152
153 printk(KERN_INFO "Bus #%d is %s (node %d)\n", m->busid, name, quad);
154}
155
156/* x86_quirks member */
157static void mpc_oem_pci_bus(struct mpc_bus *m)
158{
159 int quad = translation_table[mpc_record]->trans_quad;
160 int local = translation_table[mpc_record]->trans_local;
161
162 quad_local_to_mp_bus_id[quad][local] = m->busid;
163}
164
165/*
166 * Called from mpparse code.
167 * mode = 0: prescan
168 * mode = 1: one mpc entry scanned
169 */
170static void numaq_mpc_record(unsigned int mode)
171{
172 if (!mode)
173 mpc_record = 0;
174 else
175 mpc_record++;
176}
177
178static void __init MP_translation_info(struct mpc_trans *m)
179{
180 printk(KERN_INFO
181 "Translation: record %d, type %d, quad %d, global %d, local %d\n",
182 mpc_record, m->trans_type, m->trans_quad, m->trans_global,
183 m->trans_local);
184
185 if (mpc_record >= MAX_MPC_ENTRY)
186 printk(KERN_ERR "MAX_MPC_ENTRY exceeded!\n");
187 else
188 translation_table[mpc_record] = m; /* stash this for later */
189
190 if (m->trans_quad < MAX_NUMNODES && !node_online(m->trans_quad))
191 node_set_online(m->trans_quad);
192}
193
194static int __init mpf_checksum(unsigned char *mp, int len)
195{
196 int sum = 0;
197
198 while (len--)
199 sum += *mp++;
200
201 return sum & 0xFF;
202}
203
204/*
205 * Read/parse the MPC oem tables
206 */
207static void __init smp_read_mpc_oem(struct mpc_table *mpc)
208{
209 struct mpc_oemtable *oemtable = (void *)(long)mpc->oemptr;
210 int count = sizeof(*oemtable); /* the header size */
211 unsigned char *oemptr = ((unsigned char *)oemtable) + count;
212
213 mpc_record = 0;
214 printk(KERN_INFO
215 "Found an OEM MPC table at %8p - parsing it...\n", oemtable);
216
217 if (memcmp(oemtable->signature, MPC_OEM_SIGNATURE, 4)) {
218 printk(KERN_WARNING
219 "SMP mpc oemtable: bad signature [%c%c%c%c]!\n",
220 oemtable->signature[0], oemtable->signature[1],
221 oemtable->signature[2], oemtable->signature[3]);
222 return;
223 }
224
225 if (mpf_checksum((unsigned char *)oemtable, oemtable->length)) {
226 printk(KERN_WARNING "SMP oem mptable: checksum error!\n");
227 return;
228 }
229
230 while (count < oemtable->length) {
231 switch (*oemptr) {
232 case MP_TRANSLATION:
233 {
234 struct mpc_trans *m = (void *)oemptr;
235
236 MP_translation_info(m);
237 oemptr += sizeof(*m);
238 count += sizeof(*m);
239 ++mpc_record;
240 break;
241 }
242 default:
243 printk(KERN_WARNING
244 "Unrecognised OEM table entry type! - %d\n",
245 (int)*oemptr);
246 return;
247 }
248 }
249}
250
251static __init void early_check_numaq(void)
252{
253 /*
254 * get boot-time SMP configuration:
255 */
256 if (smp_found_config)
257 early_get_smp_config();
258
259 if (found_numaq) {
260 x86_init.mpparse.mpc_record = numaq_mpc_record;
261 x86_init.mpparse.setup_ioapic_ids = x86_init_noop;
262 x86_init.mpparse.mpc_apic_id = mpc_apic_id;
263 x86_init.mpparse.smp_read_mpc_oem = smp_read_mpc_oem;
264 x86_init.mpparse.mpc_oem_pci_bus = mpc_oem_pci_bus;
265 x86_init.mpparse.mpc_oem_bus_info = mpc_oem_bus_info;
266 x86_init.timers.tsc_pre_init = numaq_tsc_init;
267 x86_init.pci.init = pci_numaq_init;
268 }
269}
270
271int __init numaq_numa_init(void)
272{
273 early_check_numaq();
274 if (!found_numaq)
275 return -ENOENT;
276 smp_dump_qct();
277
278 return 0;
279}
280
281#define NUMAQ_APIC_DFR_VALUE (APIC_DFR_CLUSTER)
282
283static inline unsigned int numaq_get_apic_id(unsigned long x)
284{
285 return (x >> 24) & 0x0F;
286}
287
288static inline void numaq_send_IPI_mask(const struct cpumask *mask, int vector)
289{
290 default_send_IPI_mask_sequence_logical(mask, vector);
291}
292
293static inline void numaq_send_IPI_allbutself(int vector)
294{
295 default_send_IPI_mask_allbutself_logical(cpu_online_mask, vector);
296}
297
298static inline void numaq_send_IPI_all(int vector)
299{
300 numaq_send_IPI_mask(cpu_online_mask, vector);
301}
302
303#define NUMAQ_TRAMPOLINE_PHYS_LOW (0x8)
304#define NUMAQ_TRAMPOLINE_PHYS_HIGH (0xa)
305
306/*
307 * Because we use NMIs rather than the INIT-STARTUP sequence to
308 * bootstrap the CPUs, the APIC may be in a weird state. Kick it:
309 */
310static inline void numaq_smp_callin_clear_local_apic(void)
311{
312 clear_local_APIC();
313}
314
315static inline const struct cpumask *numaq_target_cpus(void)
316{
317 return cpu_all_mask;
318}
319
320static unsigned long numaq_check_apicid_used(physid_mask_t *map, int apicid)
321{
322 return physid_isset(apicid, *map);
323}
324
325static inline unsigned long numaq_check_apicid_present(int bit)
326{
327 return physid_isset(bit, phys_cpu_present_map);
328}
329
330static inline int numaq_apic_id_registered(void)
331{
332 return 1;
333}
334
335static inline void numaq_init_apic_ldr(void)
336{
337 /* Already done in NUMA-Q firmware */
338}
339
340static inline void numaq_setup_apic_routing(void)
341{
342 printk(KERN_INFO
343 "Enabling APIC mode: NUMA-Q. Using %d I/O APICs\n",
344 nr_ioapics);
345}
346
347/*
348 * Skip adding the timer int on secondary nodes, which causes
349 * a small but painful rift in the time-space continuum.
350 */
351static inline int numaq_multi_timer_check(int apic, int irq)
352{
353 return apic != 0 && irq == 0;
354}
355
356static inline void numaq_ioapic_phys_id_map(physid_mask_t *phys_map, physid_mask_t *retmap)
357{
358 /* We don't have a good way to do this yet - hack */
359 return physids_promote(0xFUL, retmap);
360}
361
362/*
363 * Supporting over 60 cpus on NUMA-Q requires a locality-dependent
364 * cpu to APIC ID relation to properly interact with the intelligent
365 * mode of the cluster controller.
366 */
367static inline int numaq_cpu_present_to_apicid(int mps_cpu)
368{
369 if (mps_cpu < 60)
370 return ((mps_cpu >> 2) << 4) | (1 << (mps_cpu & 0x3));
371 else
372 return BAD_APICID;
373}
374
375static inline int numaq_apicid_to_node(int logical_apicid)
376{
377 return logical_apicid >> 4;
378}
379
380static int numaq_numa_cpu_node(int cpu)
381{
382 int logical_apicid = early_per_cpu(x86_cpu_to_logical_apicid, cpu);
383
384 if (logical_apicid != BAD_APICID)
385 return numaq_apicid_to_node(logical_apicid);
386 return NUMA_NO_NODE;
387}
388
389static void numaq_apicid_to_cpu_present(int logical_apicid, physid_mask_t *retmap)
390{
391 int node = numaq_apicid_to_node(logical_apicid);
392 int cpu = __ffs(logical_apicid & 0xf);
393
394 physid_set_mask_of_physid(cpu + 4*node, retmap);
395}
396
397/* Where the IO area was mapped on multiquad, always 0 otherwise */
398void *xquad_portio;
399
400static inline int numaq_check_phys_apicid_present(int phys_apicid)
401{
402 return 1;
403}
404
405/*
406 * We use physical apicids here, not logical, so just return the default
407 * physical broadcast to stop people from breaking us
408 */
409static int
410numaq_cpu_mask_to_apicid_and(const struct cpumask *cpumask,
411 const struct cpumask *andmask,
412 unsigned int *apicid)
413{
414 *apicid = 0x0F;
415 return 0;
416}
417
418/* No NUMA-Q box has a HT CPU, but it can't hurt to use the default code. */
419static inline int numaq_phys_pkg_id(int cpuid_apic, int index_msb)
420{
421 return cpuid_apic >> index_msb;
422}
423
424static int
425numaq_mps_oem_check(struct mpc_table *mpc, char *oem, char *productid)
426{
427 if (strncmp(oem, "IBM NUMA", 8))
428 printk(KERN_ERR "Warning! Not a NUMA-Q system!\n");
429 else
430 found_numaq = 1;
431
432 return found_numaq;
433}
434
435static int probe_numaq(void)
436{
437 /* already know from get_memcfg_numaq() */
438 return found_numaq;
439}
440
441static void numaq_setup_portio_remap(void)
442{
443 int num_quads = num_online_nodes();
444
445 if (num_quads <= 1)
446 return;
447
448 printk(KERN_INFO
449 "Remapping cross-quad port I/O for %d quads\n", num_quads);
450
451 xquad_portio = ioremap(XQUAD_PORTIO_BASE, num_quads*XQUAD_PORTIO_QUAD);
452
453 printk(KERN_INFO
454 "xquad_portio vaddr 0x%08lx, len %08lx\n",
455 (u_long) xquad_portio, (u_long) num_quads*XQUAD_PORTIO_QUAD);
456}
457
458/* Use __refdata to keep false positive warning calm. */
459static struct apic __refdata apic_numaq = {
460
461 .name = "NUMAQ",
462 .probe = probe_numaq,
463 .acpi_madt_oem_check = NULL,
464 .apic_id_valid = default_apic_id_valid,
465 .apic_id_registered = numaq_apic_id_registered,
466
467 .irq_delivery_mode = dest_LowestPrio,
468 /* physical delivery on LOCAL quad: */
469 .irq_dest_mode = 0,
470
471 .target_cpus = numaq_target_cpus,
472 .disable_esr = 1,
473 .dest_logical = APIC_DEST_LOGICAL,
474 .check_apicid_used = numaq_check_apicid_used,
475 .check_apicid_present = numaq_check_apicid_present,
476
477 .vector_allocation_domain = flat_vector_allocation_domain,
478 .init_apic_ldr = numaq_init_apic_ldr,
479
480 .ioapic_phys_id_map = numaq_ioapic_phys_id_map,
481 .setup_apic_routing = numaq_setup_apic_routing,
482 .multi_timer_check = numaq_multi_timer_check,
483 .cpu_present_to_apicid = numaq_cpu_present_to_apicid,
484 .apicid_to_cpu_present = numaq_apicid_to_cpu_present,
485 .setup_portio_remap = numaq_setup_portio_remap,
486 .check_phys_apicid_present = numaq_check_phys_apicid_present,
487 .enable_apic_mode = NULL,
488 .phys_pkg_id = numaq_phys_pkg_id,
489 .mps_oem_check = numaq_mps_oem_check,
490
491 .get_apic_id = numaq_get_apic_id,
492 .set_apic_id = NULL,
493 .apic_id_mask = 0x0F << 24,
494
495 .cpu_mask_to_apicid_and = numaq_cpu_mask_to_apicid_and,
496
497 .send_IPI_mask = numaq_send_IPI_mask,
498 .send_IPI_mask_allbutself = NULL,
499 .send_IPI_allbutself = numaq_send_IPI_allbutself,
500 .send_IPI_all = numaq_send_IPI_all,
501 .send_IPI_self = default_send_IPI_self,
502
503 .wakeup_secondary_cpu = wakeup_secondary_cpu_via_nmi,
504 .trampoline_phys_low = NUMAQ_TRAMPOLINE_PHYS_LOW,
505 .trampoline_phys_high = NUMAQ_TRAMPOLINE_PHYS_HIGH,
506
507 /* We don't do anything here because we use NMI's to boot instead */
508 .wait_for_init_deassert = false,
509 .smp_callin_clear_local_apic = numaq_smp_callin_clear_local_apic,
510 .inquire_remote_apic = NULL,
511
512 .read = native_apic_mem_read,
513 .write = native_apic_mem_write,
514 .eoi_write = native_apic_mem_write,
515 .icr_read = native_apic_icr_read,
516 .icr_write = native_apic_icr_write,
517 .wait_icr_idle = native_apic_wait_icr_idle,
518 .safe_wait_icr_idle = native_safe_apic_wait_icr_idle,
519
520 .x86_32_early_logical_apicid = noop_x86_32_early_logical_apicid,
521 .x86_32_numa_cpu_node = numaq_numa_cpu_node,
522};
523
524apic_driver(apic_numaq);
diff --git a/arch/x86/kernel/apic/summit_32.c b/arch/x86/kernel/apic/summit_32.c
deleted file mode 100644
index b656128611cd..000000000000
--- a/arch/x86/kernel/apic/summit_32.c
+++ /dev/null
@@ -1,550 +0,0 @@
1/*
2 * IBM Summit-Specific Code
3 *
4 * Written By: Matthew Dobson, IBM Corporation
5 *
6 * Copyright (c) 2003 IBM Corp.
7 *
8 * All rights reserved.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or (at
13 * your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful, but
16 * WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
18 * NON INFRINGEMENT. See the GNU General Public License for more
19 * details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 * Send feedback to <colpatch@us.ibm.com>
26 *
27 */
28
29#define pr_fmt(fmt) "summit: %s: " fmt, __func__
30
31#include <linux/mm.h>
32#include <asm/io.h>
33#include <asm/bios_ebda.h>
34
35/*
36 * APIC driver for the IBM "Summit" chipset.
37 */
38#include <linux/threads.h>
39#include <linux/cpumask.h>
40#include <asm/mpspec.h>
41#include <asm/apic.h>
42#include <asm/smp.h>
43#include <asm/fixmap.h>
44#include <asm/apicdef.h>
45#include <asm/ipi.h>
46#include <linux/kernel.h>
47#include <linux/string.h>
48#include <linux/gfp.h>
49#include <linux/smp.h>
50
51static unsigned summit_get_apic_id(unsigned long x)
52{
53 return (x >> 24) & 0xFF;
54}
55
56static inline void summit_send_IPI_mask(const struct cpumask *mask, int vector)
57{
58 default_send_IPI_mask_sequence_logical(mask, vector);
59}
60
61static void summit_send_IPI_allbutself(int vector)
62{
63 default_send_IPI_mask_allbutself_logical(cpu_online_mask, vector);
64}
65
66static void summit_send_IPI_all(int vector)
67{
68 summit_send_IPI_mask(cpu_online_mask, vector);
69}
70
71#include <asm/tsc.h>
72
73extern int use_cyclone;
74
75#ifdef CONFIG_X86_SUMMIT_NUMA
76static void setup_summit(void);
77#else
78static inline void setup_summit(void) {}
79#endif
80
81static int summit_mps_oem_check(struct mpc_table *mpc, char *oem,
82 char *productid)
83{
84 if (!strncmp(oem, "IBM ENSW", 8) &&
85 (!strncmp(productid, "VIGIL SMP", 9)
86 || !strncmp(productid, "EXA", 3)
87 || !strncmp(productid, "RUTHLESS SMP", 12))){
88 mark_tsc_unstable("Summit based system");
89 use_cyclone = 1; /*enable cyclone-timer*/
90 setup_summit();
91 return 1;
92 }
93 return 0;
94}
95
96/* Hook from generic ACPI tables.c */
97static int summit_acpi_madt_oem_check(char *oem_id, char *oem_table_id)
98{
99 if (!strncmp(oem_id, "IBM", 3) &&
100 (!strncmp(oem_table_id, "SERVIGIL", 8)
101 || !strncmp(oem_table_id, "EXA", 3))){
102 mark_tsc_unstable("Summit based system");
103 use_cyclone = 1; /*enable cyclone-timer*/
104 setup_summit();
105 return 1;
106 }
107 return 0;
108}
109
110struct rio_table_hdr {
111 unsigned char version; /* Version number of this data structure */
112 /* Version 3 adds chassis_num & WP_index */
113 unsigned char num_scal_dev; /* # of Scalability devices (Twisters for Vigil) */
114 unsigned char num_rio_dev; /* # of RIO I/O devices (Cyclones and Winnipegs) */
115} __attribute__((packed));
116
117struct scal_detail {
118 unsigned char node_id; /* Scalability Node ID */
119 unsigned long CBAR; /* Address of 1MB register space */
120 unsigned char port0node; /* Node ID port connected to: 0xFF=None */
121 unsigned char port0port; /* Port num port connected to: 0,1,2, or 0xFF=None */
122 unsigned char port1node; /* Node ID port connected to: 0xFF = None */
123 unsigned char port1port; /* Port num port connected to: 0,1,2, or 0xFF=None */
124 unsigned char port2node; /* Node ID port connected to: 0xFF = None */
125 unsigned char port2port; /* Port num port connected to: 0,1,2, or 0xFF=None */
126 unsigned char chassis_num; /* 1 based Chassis number (1 = boot node) */
127} __attribute__((packed));
128
129struct rio_detail {
130 unsigned char node_id; /* RIO Node ID */
131 unsigned long BBAR; /* Address of 1MB register space */
132 unsigned char type; /* Type of device */
133 unsigned char owner_id; /* For WPEG: Node ID of Cyclone that owns this WPEG*/
134 /* For CYC: Node ID of Twister that owns this CYC */
135 unsigned char port0node; /* Node ID port connected to: 0xFF=None */
136 unsigned char port0port; /* Port num port connected to: 0,1,2, or 0xFF=None */
137 unsigned char port1node; /* Node ID port connected to: 0xFF=None */
138 unsigned char port1port; /* Port num port connected to: 0,1,2, or 0xFF=None */
139 unsigned char first_slot; /* For WPEG: Lowest slot number below this WPEG */
140 /* For CYC: 0 */
141 unsigned char status; /* For WPEG: Bit 0 = 1 : the XAPIC is used */
142 /* = 0 : the XAPIC is not used, ie:*/
143 /* ints fwded to another XAPIC */
144 /* Bits1:7 Reserved */
145 /* For CYC: Bits0:7 Reserved */
146 unsigned char WP_index; /* For WPEG: WPEG instance index - lower ones have */
147 /* lower slot numbers/PCI bus numbers */
148 /* For CYC: No meaning */
149 unsigned char chassis_num; /* 1 based Chassis number */
150 /* For LookOut WPEGs this field indicates the */
151 /* Expansion Chassis #, enumerated from Boot */
152 /* Node WPEG external port, then Boot Node CYC */
153 /* external port, then Next Vigil chassis WPEG */
154 /* external port, etc. */
155 /* Shared Lookouts have only 1 chassis number (the */
156 /* first one assigned) */
157} __attribute__((packed));
158
159
160typedef enum {
161 CompatTwister = 0, /* Compatibility Twister */
162 AltTwister = 1, /* Alternate Twister of internal 8-way */
163 CompatCyclone = 2, /* Compatibility Cyclone */
164 AltCyclone = 3, /* Alternate Cyclone of internal 8-way */
165 CompatWPEG = 4, /* Compatibility WPEG */
166 AltWPEG = 5, /* Second Planar WPEG */
167 LookOutAWPEG = 6, /* LookOut WPEG */
168 LookOutBWPEG = 7, /* LookOut WPEG */
169} node_type;
170
171static inline int is_WPEG(struct rio_detail *rio){
172 return (rio->type == CompatWPEG || rio->type == AltWPEG ||
173 rio->type == LookOutAWPEG || rio->type == LookOutBWPEG);
174}
175
176#define SUMMIT_APIC_DFR_VALUE (APIC_DFR_CLUSTER)
177
178static const struct cpumask *summit_target_cpus(void)
179{
180 /* CPU_MASK_ALL (0xff) has undefined behaviour with
181 * dest_LowestPrio mode logical clustered apic interrupt routing
182 * Just start on cpu 0. IRQ balancing will spread load
183 */
184 return cpumask_of(0);
185}
186
187static unsigned long summit_check_apicid_used(physid_mask_t *map, int apicid)
188{
189 return 0;
190}
191
192/* we don't use the phys_cpu_present_map to indicate apicid presence */
193static unsigned long summit_check_apicid_present(int bit)
194{
195 return 1;
196}
197
198static int summit_early_logical_apicid(int cpu)
199{
200 int count = 0;
201 u8 my_id = early_per_cpu(x86_cpu_to_apicid, cpu);
202 u8 my_cluster = APIC_CLUSTER(my_id);
203#ifdef CONFIG_SMP
204 u8 lid;
205 int i;
206
207 /* Create logical APIC IDs by counting CPUs already in cluster. */
208 for (count = 0, i = nr_cpu_ids; --i >= 0; ) {
209 lid = early_per_cpu(x86_cpu_to_logical_apicid, i);
210 if (lid != BAD_APICID && APIC_CLUSTER(lid) == my_cluster)
211 ++count;
212 }
213#endif
214 /* We only have a 4 wide bitmap in cluster mode. If a deranged
215 * BIOS puts 5 CPUs in one APIC cluster, we're hosed. */
216 BUG_ON(count >= XAPIC_DEST_CPUS_SHIFT);
217 return my_cluster | (1UL << count);
218}
219
220static void summit_init_apic_ldr(void)
221{
222 int cpu = smp_processor_id();
223 unsigned long id = early_per_cpu(x86_cpu_to_logical_apicid, cpu);
224 unsigned long val;
225
226 apic_write(APIC_DFR, SUMMIT_APIC_DFR_VALUE);
227 val = apic_read(APIC_LDR) & ~APIC_LDR_MASK;
228 val |= SET_APIC_LOGICAL_ID(id);
229 apic_write(APIC_LDR, val);
230}
231
232static int summit_apic_id_registered(void)
233{
234 return 1;
235}
236
237static void summit_setup_apic_routing(void)
238{
239 pr_info("Enabling APIC mode: Summit. Using %d I/O APICs\n",
240 nr_ioapics);
241}
242
243static int summit_cpu_present_to_apicid(int mps_cpu)
244{
245 if (mps_cpu < nr_cpu_ids)
246 return (int)per_cpu(x86_bios_cpu_apicid, mps_cpu);
247 else
248 return BAD_APICID;
249}
250
251static void summit_ioapic_phys_id_map(physid_mask_t *phys_id_map, physid_mask_t *retmap)
252{
253 /* For clustered we don't have a good way to do this yet - hack */
254 physids_promote(0x0FL, retmap);
255}
256
257static void summit_apicid_to_cpu_present(int apicid, physid_mask_t *retmap)
258{
259 physid_set_mask_of_physid(0, retmap);
260}
261
262static int summit_check_phys_apicid_present(int physical_apicid)
263{
264 return 1;
265}
266
267static inline int
268summit_cpu_mask_to_apicid(const struct cpumask *cpumask, unsigned int *dest_id)
269{
270 unsigned int round = 0;
271 unsigned int cpu, apicid = 0;
272
273 /*
274 * The cpus in the mask must all be on the apic cluster.
275 */
276 for_each_cpu_and(cpu, cpumask, cpu_online_mask) {
277 int new_apicid = early_per_cpu(x86_cpu_to_logical_apicid, cpu);
278
279 if (round && APIC_CLUSTER(apicid) != APIC_CLUSTER(new_apicid)) {
280 pr_err("Not a valid mask!\n");
281 return -EINVAL;
282 }
283 apicid |= new_apicid;
284 round++;
285 }
286 if (!round)
287 return -EINVAL;
288 *dest_id = apicid;
289 return 0;
290}
291
292static int
293summit_cpu_mask_to_apicid_and(const struct cpumask *inmask,
294 const struct cpumask *andmask,
295 unsigned int *apicid)
296{
297 cpumask_var_t cpumask;
298 *apicid = early_per_cpu(x86_cpu_to_logical_apicid, 0);
299
300 if (!alloc_cpumask_var(&cpumask, GFP_ATOMIC))
301 return 0;
302
303 cpumask_and(cpumask, inmask, andmask);
304 summit_cpu_mask_to_apicid(cpumask, apicid);
305
306 free_cpumask_var(cpumask);
307
308 return 0;
309}
310
311/*
312 * cpuid returns the value latched in the HW at reset, not the APIC ID
313 * register's value. For any box whose BIOS changes APIC IDs, like
314 * clustered APIC systems, we must use hard_smp_processor_id.
315 *
316 * See Intel's IA-32 SW Dev's Manual Vol2 under CPUID.
317 */
318static int summit_phys_pkg_id(int cpuid_apic, int index_msb)
319{
320 return hard_smp_processor_id() >> index_msb;
321}
322
323static int probe_summit(void)
324{
325 /* probed later in mptable/ACPI hooks */
326 return 0;
327}
328
329#ifdef CONFIG_X86_SUMMIT_NUMA
330static struct rio_table_hdr *rio_table_hdr;
331static struct scal_detail *scal_devs[MAX_NUMNODES];
332static struct rio_detail *rio_devs[MAX_NUMNODES*4];
333
334#ifndef CONFIG_X86_NUMAQ
335static int mp_bus_id_to_node[MAX_MP_BUSSES];
336#endif
337
338static int setup_pci_node_map_for_wpeg(int wpeg_num, int last_bus)
339{
340 int twister = 0, node = 0;
341 int i, bus, num_buses;
342
343 for (i = 0; i < rio_table_hdr->num_rio_dev; i++) {
344 if (rio_devs[i]->node_id == rio_devs[wpeg_num]->owner_id) {
345 twister = rio_devs[i]->owner_id;
346 break;
347 }
348 }
349 if (i == rio_table_hdr->num_rio_dev) {
350 pr_err("Couldn't find owner Cyclone for Winnipeg!\n");
351 return last_bus;
352 }
353
354 for (i = 0; i < rio_table_hdr->num_scal_dev; i++) {
355 if (scal_devs[i]->node_id == twister) {
356 node = scal_devs[i]->node_id;
357 break;
358 }
359 }
360 if (i == rio_table_hdr->num_scal_dev) {
361 pr_err("Couldn't find owner Twister for Cyclone!\n");
362 return last_bus;
363 }
364
365 switch (rio_devs[wpeg_num]->type) {
366 case CompatWPEG:
367 /*
368 * The Compatibility Winnipeg controls the 2 legacy buses,
369 * the 66MHz PCI bus [2 slots] and the 2 "extra" buses in case
370 * a PCI-PCI bridge card is used in either slot: total 5 buses.
371 */
372 num_buses = 5;
373 break;
374 case AltWPEG:
375 /*
376 * The Alternate Winnipeg controls the 2 133MHz buses [1 slot
377 * each], their 2 "extra" buses, the 100MHz bus [2 slots] and
378 * the "extra" buses for each of those slots: total 7 buses.
379 */
380 num_buses = 7;
381 break;
382 case LookOutAWPEG:
383 case LookOutBWPEG:
384 /*
385 * A Lookout Winnipeg controls 3 100MHz buses [2 slots each]
386 * & the "extra" buses for each of those slots: total 9 buses.
387 */
388 num_buses = 9;
389 break;
390 default:
391 pr_info("Unsupported Winnipeg type!\n");
392 return last_bus;
393 }
394
395 for (bus = last_bus; bus < last_bus + num_buses; bus++)
396 mp_bus_id_to_node[bus] = node;
397 return bus;
398}
399
400static int build_detail_arrays(void)
401{
402 unsigned long ptr;
403 int i, scal_detail_size, rio_detail_size;
404
405 if (rio_table_hdr->num_scal_dev > MAX_NUMNODES) {
406 pr_warn("MAX_NUMNODES too low! Defined as %d, but system has %d nodes\n",
407 MAX_NUMNODES, rio_table_hdr->num_scal_dev);
408 return 0;
409 }
410
411 switch (rio_table_hdr->version) {
412 default:
413 pr_warn("Invalid Rio Grande Table Version: %d\n",
414 rio_table_hdr->version);
415 return 0;
416 case 2:
417 scal_detail_size = 11;
418 rio_detail_size = 13;
419 break;
420 case 3:
421 scal_detail_size = 12;
422 rio_detail_size = 15;
423 break;
424 }
425
426 ptr = (unsigned long)rio_table_hdr + 3;
427 for (i = 0; i < rio_table_hdr->num_scal_dev; i++, ptr += scal_detail_size)
428 scal_devs[i] = (struct scal_detail *)ptr;
429
430 for (i = 0; i < rio_table_hdr->num_rio_dev; i++, ptr += rio_detail_size)
431 rio_devs[i] = (struct rio_detail *)ptr;
432
433 return 1;
434}
435
436void setup_summit(void)
437{
438 unsigned long ptr;
439 unsigned short offset;
440 int i, next_wpeg, next_bus = 0;
441
442 /* The pointer to the EBDA is stored in the word @ phys 0x40E(40:0E) */
443 ptr = get_bios_ebda();
444 ptr = (unsigned long)phys_to_virt(ptr);
445
446 rio_table_hdr = NULL;
447 offset = 0x180;
448 while (offset) {
449 /* The block id is stored in the 2nd word */
450 if (*((unsigned short *)(ptr + offset + 2)) == 0x4752) {
451 /* set the pointer past the offset & block id */
452 rio_table_hdr = (struct rio_table_hdr *)(ptr + offset + 4);
453 break;
454 }
455 /* The next offset is stored in the 1st word. 0 means no more */
456 offset = *((unsigned short *)(ptr + offset));
457 }
458 if (!rio_table_hdr) {
459 pr_err("Unable to locate Rio Grande Table in EBDA - bailing!\n");
460 return;
461 }
462
463 if (!build_detail_arrays())
464 return;
465
466 /* The first Winnipeg we're looking for has an index of 0 */
467 next_wpeg = 0;
468 do {
469 for (i = 0; i < rio_table_hdr->num_rio_dev; i++) {
470 if (is_WPEG(rio_devs[i]) && rio_devs[i]->WP_index == next_wpeg) {
471 /* It's the Winnipeg we're looking for! */
472 next_bus = setup_pci_node_map_for_wpeg(i, next_bus);
473 next_wpeg++;
474 break;
475 }
476 }
477 /*
478 * If we go through all Rio devices and don't find one with
479 * the next index, it means we've found all the Winnipegs,
480 * and thus all the PCI buses.
481 */
482 if (i == rio_table_hdr->num_rio_dev)
483 next_wpeg = 0;
484 } while (next_wpeg != 0);
485}
486#endif
487
488static struct apic apic_summit = {
489
490 .name = "summit",
491 .probe = probe_summit,
492 .acpi_madt_oem_check = summit_acpi_madt_oem_check,
493 .apic_id_valid = default_apic_id_valid,
494 .apic_id_registered = summit_apic_id_registered,
495
496 .irq_delivery_mode = dest_LowestPrio,
497 /* logical delivery broadcast to all CPUs: */
498 .irq_dest_mode = 1,
499
500 .target_cpus = summit_target_cpus,
501 .disable_esr = 1,
502 .dest_logical = APIC_DEST_LOGICAL,
503 .check_apicid_used = summit_check_apicid_used,
504 .check_apicid_present = summit_check_apicid_present,
505
506 .vector_allocation_domain = flat_vector_allocation_domain,
507 .init_apic_ldr = summit_init_apic_ldr,
508
509 .ioapic_phys_id_map = summit_ioapic_phys_id_map,
510 .setup_apic_routing = summit_setup_apic_routing,
511 .multi_timer_check = NULL,
512 .cpu_present_to_apicid = summit_cpu_present_to_apicid,
513 .apicid_to_cpu_present = summit_apicid_to_cpu_present,
514 .setup_portio_remap = NULL,
515 .check_phys_apicid_present = summit_check_phys_apicid_present,
516 .enable_apic_mode = NULL,
517 .phys_pkg_id = summit_phys_pkg_id,
518 .mps_oem_check = summit_mps_oem_check,
519
520 .get_apic_id = summit_get_apic_id,
521 .set_apic_id = NULL,
522 .apic_id_mask = 0xFF << 24,
523
524 .cpu_mask_to_apicid_and = summit_cpu_mask_to_apicid_and,
525
526 .send_IPI_mask = summit_send_IPI_mask,
527 .send_IPI_mask_allbutself = NULL,
528 .send_IPI_allbutself = summit_send_IPI_allbutself,
529 .send_IPI_all = summit_send_IPI_all,
530 .send_IPI_self = default_send_IPI_self,
531
532 .trampoline_phys_low = DEFAULT_TRAMPOLINE_PHYS_LOW,
533 .trampoline_phys_high = DEFAULT_TRAMPOLINE_PHYS_HIGH,
534
535 .wait_for_init_deassert = true,
536 .smp_callin_clear_local_apic = NULL,
537 .inquire_remote_apic = default_inquire_remote_apic,
538
539 .read = native_apic_mem_read,
540 .write = native_apic_mem_write,
541 .eoi_write = native_apic_mem_write,
542 .icr_read = native_apic_icr_read,
543 .icr_write = native_apic_icr_write,
544 .wait_icr_idle = native_apic_wait_icr_idle,
545 .safe_wait_icr_idle = native_safe_apic_wait_icr_idle,
546
547 .x86_32_early_logical_apicid = summit_early_logical_apicid,
548};
549
550apic_driver(apic_summit);
diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c
index 897d6201ef10..a80029035bf2 100644
--- a/arch/x86/kernel/cpu/intel.c
+++ b/arch/x86/kernel/cpu/intel.c
@@ -274,10 +274,6 @@ static void intel_workarounds(struct cpuinfo_x86 *c)
274 } 274 }
275#endif 275#endif
276 276
277#ifdef CONFIG_X86_NUMAQ
278 numaq_tsc_disable();
279#endif
280
281 intel_smp_check(c); 277 intel_smp_check(c);
282} 278}
283#else 279#else
diff --git a/arch/x86/kernel/setup.c b/arch/x86/kernel/setup.c
index fa511acff7e6..09c76d265550 100644
--- a/arch/x86/kernel/setup.c
+++ b/arch/x86/kernel/setup.c
@@ -869,7 +869,6 @@ void __init setup_arch(char **cmdline_p)
869 869
870#ifdef CONFIG_X86_32 870#ifdef CONFIG_X86_32
871 memcpy(&boot_cpu_data, &new_cpu_data, sizeof(new_cpu_data)); 871 memcpy(&boot_cpu_data, &new_cpu_data, sizeof(new_cpu_data));
872 visws_early_detect();
873 872
874 /* 873 /*
875 * copy kernel address range established so far and switch 874 * copy kernel address range established so far and switch
diff --git a/arch/x86/mm/numa.c b/arch/x86/mm/numa.c
index 27aa0455fab3..1d045f9c390f 100644
--- a/arch/x86/mm/numa.c
+++ b/arch/x86/mm/numa.c
@@ -687,10 +687,6 @@ static int __init dummy_numa_init(void)
687void __init x86_numa_init(void) 687void __init x86_numa_init(void)
688{ 688{
689 if (!numa_off) { 689 if (!numa_off) {
690#ifdef CONFIG_X86_NUMAQ
691 if (!numa_init(numaq_numa_init))
692 return;
693#endif
694#ifdef CONFIG_ACPI_NUMA 690#ifdef CONFIG_ACPI_NUMA
695 if (!numa_init(x86_acpi_numa_init)) 691 if (!numa_init(x86_acpi_numa_init))
696 return; 692 return;
diff --git a/arch/x86/pci/Makefile b/arch/x86/pci/Makefile
index e063eed0f912..5c6fc3577a49 100644
--- a/arch/x86/pci/Makefile
+++ b/arch/x86/pci/Makefile
@@ -13,9 +13,6 @@ obj-y += legacy.o irq.o
13 13
14obj-$(CONFIG_STA2X11) += sta2x11-fixup.o 14obj-$(CONFIG_STA2X11) += sta2x11-fixup.o
15 15
16obj-$(CONFIG_X86_VISWS) += visws.o
17
18obj-$(CONFIG_X86_NUMAQ) += numaq_32.o
19obj-$(CONFIG_X86_NUMACHIP) += numachip.o 16obj-$(CONFIG_X86_NUMACHIP) += numachip.o
20 17
21obj-$(CONFIG_X86_INTEL_MID) += intel_mid_pci.o 18obj-$(CONFIG_X86_INTEL_MID) += intel_mid_pci.o
diff --git a/arch/x86/pci/common.c b/arch/x86/pci/common.c
index d491deddebae..059a76c29739 100644
--- a/arch/x86/pci/common.c
+++ b/arch/x86/pci/common.c
@@ -567,7 +567,6 @@ char * __init pcibios_setup(char *str)
567 pci_probe |= PCI_PROBE_NOEARLY; 567 pci_probe |= PCI_PROBE_NOEARLY;
568 return NULL; 568 return NULL;
569 } 569 }
570#ifndef CONFIG_X86_VISWS
571 else if (!strcmp(str, "usepirqmask")) { 570 else if (!strcmp(str, "usepirqmask")) {
572 pci_probe |= PCI_USE_PIRQ_MASK; 571 pci_probe |= PCI_USE_PIRQ_MASK;
573 return NULL; 572 return NULL;
@@ -577,9 +576,7 @@ char * __init pcibios_setup(char *str)
577 } else if (!strncmp(str, "lastbus=", 8)) { 576 } else if (!strncmp(str, "lastbus=", 8)) {
578 pcibios_last_bus = simple_strtol(str+8, NULL, 0); 577 pcibios_last_bus = simple_strtol(str+8, NULL, 0);
579 return NULL; 578 return NULL;
580 } 579 } else if (!strcmp(str, "rom")) {
581#endif
582 else if (!strcmp(str, "rom")) {
583 pci_probe |= PCI_ASSIGN_ROMS; 580 pci_probe |= PCI_ASSIGN_ROMS;
584 return NULL; 581 return NULL;
585 } else if (!strcmp(str, "norom")) { 582 } else if (!strcmp(str, "norom")) {
diff --git a/arch/x86/pci/numaq_32.c b/arch/x86/pci/numaq_32.c
deleted file mode 100644
index 080eb0374fff..000000000000
--- a/arch/x86/pci/numaq_32.c
+++ /dev/null
@@ -1,165 +0,0 @@
1/*
2 * numaq_32.c - Low-level PCI access for NUMA-Q machines
3 */
4
5#include <linux/pci.h>
6#include <linux/init.h>
7#include <linux/nodemask.h>
8#include <asm/apic.h>
9#include <asm/mpspec.h>
10#include <asm/pci_x86.h>
11#include <asm/numaq.h>
12
13#define BUS2QUAD(global) (mp_bus_id_to_node[global])
14
15#define BUS2LOCAL(global) (mp_bus_id_to_local[global])
16
17#define QUADLOCAL2BUS(quad,local) (quad_local_to_mp_bus_id[quad][local])
18
19#define PCI_CONF1_MQ_ADDRESS(bus, devfn, reg) \
20 (0x80000000 | (BUS2LOCAL(bus) << 16) | (devfn << 8) | (reg & ~3))
21
22static void write_cf8(unsigned bus, unsigned devfn, unsigned reg)
23{
24 unsigned val = PCI_CONF1_MQ_ADDRESS(bus, devfn, reg);
25 if (xquad_portio)
26 writel(val, XQUAD_PORT_ADDR(0xcf8, BUS2QUAD(bus)));
27 else
28 outl(val, 0xCF8);
29}
30
31static int pci_conf1_mq_read(unsigned int seg, unsigned int bus,
32 unsigned int devfn, int reg, int len, u32 *value)
33{
34 unsigned long flags;
35 void *adr __iomem = XQUAD_PORT_ADDR(0xcfc, BUS2QUAD(bus));
36
37 WARN_ON(seg);
38 if (!value || (bus >= MAX_MP_BUSSES) || (devfn > 255) || (reg > 255))
39 return -EINVAL;
40
41 raw_spin_lock_irqsave(&pci_config_lock, flags);
42
43 write_cf8(bus, devfn, reg);
44
45 switch (len) {
46 case 1:
47 if (xquad_portio)
48 *value = readb(adr + (reg & 3));
49 else
50 *value = inb(0xCFC + (reg & 3));
51 break;
52 case 2:
53 if (xquad_portio)
54 *value = readw(adr + (reg & 2));
55 else
56 *value = inw(0xCFC + (reg & 2));
57 break;
58 case 4:
59 if (xquad_portio)
60 *value = readl(adr);
61 else
62 *value = inl(0xCFC);
63 break;
64 }
65
66 raw_spin_unlock_irqrestore(&pci_config_lock, flags);
67
68 return 0;
69}
70
71static int pci_conf1_mq_write(unsigned int seg, unsigned int bus,
72 unsigned int devfn, int reg, int len, u32 value)
73{
74 unsigned long flags;
75 void *adr __iomem = XQUAD_PORT_ADDR(0xcfc, BUS2QUAD(bus));
76
77 WARN_ON(seg);
78 if ((bus >= MAX_MP_BUSSES) || (devfn > 255) || (reg > 255))
79 return -EINVAL;
80
81 raw_spin_lock_irqsave(&pci_config_lock, flags);
82
83 write_cf8(bus, devfn, reg);
84
85 switch (len) {
86 case 1:
87 if (xquad_portio)
88 writeb(value, adr + (reg & 3));
89 else
90 outb((u8)value, 0xCFC + (reg & 3));
91 break;
92 case 2:
93 if (xquad_portio)
94 writew(value, adr + (reg & 2));
95 else
96 outw((u16)value, 0xCFC + (reg & 2));
97 break;
98 case 4:
99 if (xquad_portio)
100 writel(value, adr + reg);
101 else
102 outl((u32)value, 0xCFC);
103 break;
104 }
105
106 raw_spin_unlock_irqrestore(&pci_config_lock, flags);
107
108 return 0;
109}
110
111#undef PCI_CONF1_MQ_ADDRESS
112
113static const struct pci_raw_ops pci_direct_conf1_mq = {
114 .read = pci_conf1_mq_read,
115 .write = pci_conf1_mq_write
116};
117
118
119static void pci_fixup_i450nx(struct pci_dev *d)
120{
121 /*
122 * i450NX -- Find and scan all secondary buses on all PXB's.
123 */
124 int pxb, reg;
125 u8 busno, suba, subb;
126 int quad = BUS2QUAD(d->bus->number);
127
128 dev_info(&d->dev, "searching for i450NX host bridges\n");
129 reg = 0xd0;
130 for(pxb=0; pxb<2; pxb++) {
131 pci_read_config_byte(d, reg++, &busno);
132 pci_read_config_byte(d, reg++, &suba);
133 pci_read_config_byte(d, reg++, &subb);
134 dev_dbg(&d->dev, "i450NX PXB %d: %02x/%02x/%02x\n",
135 pxb, busno, suba, subb);
136 if (busno) {
137 /* Bus A */
138 pcibios_scan_root(QUADLOCAL2BUS(quad, busno));
139 }
140 if (suba < subb) {
141 /* Bus B */
142 pcibios_scan_root(QUADLOCAL2BUS(quad, suba+1));
143 }
144 }
145 pcibios_last_bus = -1;
146}
147DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82451NX, pci_fixup_i450nx);
148
149int __init pci_numaq_init(void)
150{
151 int quad;
152
153 raw_pci_ops = &pci_direct_conf1_mq;
154
155 pcibios_scan_root(0);
156 if (num_online_nodes() > 1)
157 for_each_online_node(quad) {
158 if (quad == 0)
159 continue;
160 printk("Scanning PCI bus %d for quad %d\n",
161 QUADLOCAL2BUS(quad,0), quad);
162 pcibios_scan_root(QUADLOCAL2BUS(quad, 0));
163 }
164 return 0;
165}
diff --git a/arch/x86/pci/visws.c b/arch/x86/pci/visws.c
deleted file mode 100644
index cd9d4d1681d2..000000000000
--- a/arch/x86/pci/visws.c
+++ /dev/null
@@ -1,87 +0,0 @@
1/*
2 * Low-Level PCI Support for SGI Visual Workstation
3 *
4 * (c) 1999--2000 Martin Mares <mj@ucw.cz>
5 */
6
7#include <linux/kernel.h>
8#include <linux/pci.h>
9#include <linux/init.h>
10
11#include <asm/setup.h>
12#include <asm/pci_x86.h>
13#include <asm/visws/cobalt.h>
14#include <asm/visws/lithium.h>
15
16static int pci_visws_enable_irq(struct pci_dev *dev) { return 0; }
17static void pci_visws_disable_irq(struct pci_dev *dev) { }
18
19/* int (*pcibios_enable_irq)(struct pci_dev *dev) = &pci_visws_enable_irq; */
20/* void (*pcibios_disable_irq)(struct pci_dev *dev) = &pci_visws_disable_irq; */
21
22/* void __init pcibios_penalize_isa_irq(int irq, int active) {} */
23
24
25unsigned int pci_bus0, pci_bus1;
26
27static int __init visws_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
28{
29 int irq, bus = dev->bus->number;
30
31 pin--;
32
33 /* Nothing useful at PIIX4 pin 1 */
34 if (bus == pci_bus0 && slot == 4 && pin == 0)
35 return -1;
36
37 /* PIIX4 USB is on Bus 0, Slot 4, Line 3 */
38 if (bus == pci_bus0 && slot == 4 && pin == 3) {
39 irq = CO_IRQ(CO_APIC_PIIX4_USB);
40 goto out;
41 }
42
43 /* First pin spread down 1 APIC entry per slot */
44 if (pin == 0) {
45 irq = CO_IRQ((bus == pci_bus0 ? CO_APIC_PCIB_BASE0 :
46 CO_APIC_PCIA_BASE0) + slot);
47 goto out;
48 }
49
50 /* lines 1,2,3 from any slot is shared in this twirly pattern */
51 if (bus == pci_bus1) {
52 /* lines 1-3 from devices 0 1 rotate over 2 apic entries */
53 irq = CO_IRQ(CO_APIC_PCIA_BASE123 + ((slot + (pin - 1)) % 2));
54 } else { /* bus == pci_bus0 */
55 /* lines 1-3 from devices 0-3 rotate over 3 apic entries */
56 if (slot == 0)
57 slot = 3; /* same pattern */
58 irq = CO_IRQ(CO_APIC_PCIA_BASE123 + ((3 - slot) + (pin - 1) % 3));
59 }
60out:
61 printk(KERN_DEBUG "PCI: Bus %d Slot %d Line %d -> IRQ %d\n", bus, slot, pin, irq);
62 return irq;
63}
64
65int __init pci_visws_init(void)
66{
67 pcibios_enable_irq = &pci_visws_enable_irq;
68 pcibios_disable_irq = &pci_visws_disable_irq;
69
70 /* The VISWS supports configuration access type 1 only */
71 pci_probe = (pci_probe | PCI_PROBE_CONF1) &
72 ~(PCI_PROBE_BIOS | PCI_PROBE_CONF2);
73
74 pci_bus0 = li_pcib_read16(LI_PCI_BUSNUM) & 0xff;
75 pci_bus1 = li_pcia_read16(LI_PCI_BUSNUM) & 0xff;
76
77 printk(KERN_INFO "PCI: Lithium bridge A bus: %u, "
78 "bridge B (PIIX4) bus: %u\n", pci_bus1, pci_bus0);
79
80 raw_pci_ops = &pci_direct_conf1;
81 pcibios_scan_root(pci_bus0);
82 pcibios_scan_root(pci_bus1);
83 pci_fixup_irqs(pci_common_swizzle, visws_map_irq);
84 pcibios_resource_survey();
85 /* Request bus scan */
86 return 1;
87}
diff --git a/arch/x86/platform/Makefile b/arch/x86/platform/Makefile
index 20342d4c82ce..85afde1fa3e5 100644
--- a/arch/x86/platform/Makefile
+++ b/arch/x86/platform/Makefile
@@ -9,5 +9,4 @@ obj-y += olpc/
9obj-y += scx200/ 9obj-y += scx200/
10obj-y += sfi/ 10obj-y += sfi/
11obj-y += ts5500/ 11obj-y += ts5500/
12obj-y += visws/
13obj-y += uv/ 12obj-y += uv/
diff --git a/arch/x86/platform/visws/Makefile b/arch/x86/platform/visws/Makefile
deleted file mode 100644
index 91bc17ab2fd5..000000000000
--- a/arch/x86/platform/visws/Makefile
+++ /dev/null
@@ -1 +0,0 @@
1obj-$(CONFIG_X86_VISWS) += visws_quirks.o
diff --git a/arch/x86/platform/visws/visws_quirks.c b/arch/x86/platform/visws/visws_quirks.c
deleted file mode 100644
index 94d8a39332ec..000000000000
--- a/arch/x86/platform/visws/visws_quirks.c
+++ /dev/null
@@ -1,608 +0,0 @@
1/*
2 * SGI Visual Workstation support and quirks, unmaintained.
3 *
4 * Split out from setup.c by davej@suse.de
5 *
6 * Copyright (C) 1999 Bent Hagemark, Ingo Molnar
7 *
8 * SGI Visual Workstation interrupt controller
9 *
10 * The Cobalt system ASIC in the Visual Workstation contains a "Cobalt" APIC
11 * which serves as the main interrupt controller in the system. Non-legacy
12 * hardware in the system uses this controller directly. Legacy devices
13 * are connected to the PIIX4 which in turn has its 8259(s) connected to
14 * a of the Cobalt APIC entry.
15 *
16 * 09/02/2000 - Updated for 2.4 by jbarnes@sgi.com
17 *
18 * 25/11/2002 - Updated for 2.5 by Andrey Panin <pazke@orbita1.ru>
19 */
20#include <linux/interrupt.h>
21#include <linux/module.h>
22#include <linux/init.h>
23#include <linux/smp.h>
24
25#include <asm/visws/cobalt.h>
26#include <asm/visws/piix4.h>
27#include <asm/io_apic.h>
28#include <asm/fixmap.h>
29#include <asm/reboot.h>
30#include <asm/setup.h>
31#include <asm/apic.h>
32#include <asm/e820.h>
33#include <asm/time.h>
34#include <asm/io.h>
35
36#include <linux/kernel_stat.h>
37
38#include <asm/i8259.h>
39#include <asm/irq_vectors.h>
40#include <asm/visws/lithium.h>
41
42#include <linux/sched.h>
43#include <linux/kernel.h>
44#include <linux/pci.h>
45#include <linux/pci_ids.h>
46
47extern int no_broadcast;
48
49char visws_board_type = -1;
50char visws_board_rev = -1;
51
52static void __init visws_time_init(void)
53{
54 printk(KERN_INFO "Starting Cobalt Timer system clock\n");
55
56 /* Set the countdown value */
57 co_cpu_write(CO_CPU_TIMEVAL, CO_TIME_HZ/HZ);
58
59 /* Start the timer */
60 co_cpu_write(CO_CPU_CTRL, co_cpu_read(CO_CPU_CTRL) | CO_CTRL_TIMERUN);
61
62 /* Enable (unmask) the timer interrupt */
63 co_cpu_write(CO_CPU_CTRL, co_cpu_read(CO_CPU_CTRL) & ~CO_CTRL_TIMEMASK);
64
65 setup_default_timer_irq();
66}
67
68/* Replaces the default init_ISA_irqs in the generic setup */
69static void __init visws_pre_intr_init(void);
70
71/* Quirk for machine specific memory setup. */
72
73#define MB (1024 * 1024)
74
75unsigned long sgivwfb_mem_phys;
76unsigned long sgivwfb_mem_size;
77EXPORT_SYMBOL(sgivwfb_mem_phys);
78EXPORT_SYMBOL(sgivwfb_mem_size);
79
80long long mem_size __initdata = 0;
81
82static char * __init visws_memory_setup(void)
83{
84 long long gfx_mem_size = 8 * MB;
85
86 mem_size = boot_params.alt_mem_k;
87
88 if (!mem_size) {
89 printk(KERN_WARNING "Bootloader didn't set memory size, upgrade it !\n");
90 mem_size = 128 * MB;
91 }
92
93 /*
94 * this hardcodes the graphics memory to 8 MB
95 * it really should be sized dynamically (or at least
96 * set as a boot param)
97 */
98 if (!sgivwfb_mem_size) {
99 printk(KERN_WARNING "Defaulting to 8 MB framebuffer size\n");
100 sgivwfb_mem_size = 8 * MB;
101 }
102
103 /*
104 * Trim to nearest MB
105 */
106 sgivwfb_mem_size &= ~((1 << 20) - 1);
107 sgivwfb_mem_phys = mem_size - gfx_mem_size;
108
109 e820_add_region(0, LOWMEMSIZE(), E820_RAM);
110 e820_add_region(HIGH_MEMORY, mem_size - sgivwfb_mem_size - HIGH_MEMORY, E820_RAM);
111 e820_add_region(sgivwfb_mem_phys, sgivwfb_mem_size, E820_RESERVED);
112
113 return "PROM";
114}
115
116static void visws_machine_emergency_restart(void)
117{
118 /*
119 * Visual Workstations restart after this
120 * register is poked on the PIIX4
121 */
122 outb(PIIX4_RESET_VAL, PIIX4_RESET_PORT);
123}
124
125static void visws_machine_power_off(void)
126{
127 unsigned short pm_status;
128/* extern unsigned int pci_bus0; */
129
130 while ((pm_status = inw(PMSTS_PORT)) & 0x100)
131 outw(pm_status, PMSTS_PORT);
132
133 outw(PM_SUSPEND_ENABLE, PMCNTRL_PORT);
134
135 mdelay(10);
136
137#define PCI_CONF1_ADDRESS(bus, devfn, reg) \
138 (0x80000000 | (bus << 16) | (devfn << 8) | (reg & ~3))
139
140/* outl(PCI_CONF1_ADDRESS(pci_bus0, SPECIAL_DEV, SPECIAL_REG), 0xCF8); */
141 outl(PIIX_SPECIAL_STOP, 0xCFC);
142}
143
144static void __init visws_get_smp_config(unsigned int early)
145{
146}
147
148/*
149 * The Visual Workstation is Intel MP compliant in the hardware
150 * sense, but it doesn't have a BIOS(-configuration table).
151 * No problem for Linux.
152 */
153
154static void __init MP_processor_info(struct mpc_cpu *m)
155{
156 int ver, logical_apicid;
157 physid_mask_t apic_cpus;
158
159 if (!(m->cpuflag & CPU_ENABLED))
160 return;
161
162 logical_apicid = m->apicid;
163 printk(KERN_INFO "%sCPU #%d %u:%u APIC version %d\n",
164 m->cpuflag & CPU_BOOTPROCESSOR ? "Bootup " : "",
165 m->apicid, (m->cpufeature & CPU_FAMILY_MASK) >> 8,
166 (m->cpufeature & CPU_MODEL_MASK) >> 4, m->apicver);
167
168 if (m->cpuflag & CPU_BOOTPROCESSOR)
169 boot_cpu_physical_apicid = m->apicid;
170
171 ver = m->apicver;
172 if ((ver >= 0x14 && m->apicid >= 0xff) || m->apicid >= 0xf) {
173 printk(KERN_ERR "Processor #%d INVALID. (Max ID: %d).\n",
174 m->apicid, MAX_LOCAL_APIC);
175 return;
176 }
177
178 apic->apicid_to_cpu_present(m->apicid, &apic_cpus);
179 physids_or(phys_cpu_present_map, phys_cpu_present_map, apic_cpus);
180 /*
181 * Validate version
182 */
183 if (ver == 0x0) {
184 printk(KERN_ERR "BIOS bug, APIC version is 0 for CPU#%d! "
185 "fixing up to 0x10. (tell your hw vendor)\n",
186 m->apicid);
187 ver = 0x10;
188 }
189 apic_version[m->apicid] = ver;
190}
191
192static void __init visws_find_smp_config(void)
193{
194 struct mpc_cpu *mp = phys_to_virt(CO_CPU_TAB_PHYS);
195 unsigned short ncpus = readw(phys_to_virt(CO_CPU_NUM_PHYS));
196
197 if (ncpus > CO_CPU_MAX) {
198 printk(KERN_WARNING "find_visws_smp: got cpu count of %d at %p\n",
199 ncpus, mp);
200
201 ncpus = CO_CPU_MAX;
202 }
203
204 if (ncpus > setup_max_cpus)
205 ncpus = setup_max_cpus;
206
207#ifdef CONFIG_X86_LOCAL_APIC
208 smp_found_config = 1;
209#endif
210 while (ncpus--)
211 MP_processor_info(mp++);
212
213 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
214}
215
216static void visws_trap_init(void);
217
218void __init visws_early_detect(void)
219{
220 int raw;
221
222 visws_board_type = (char)(inb_p(PIIX_GPI_BD_REG) & PIIX_GPI_BD_REG)
223 >> PIIX_GPI_BD_SHIFT;
224
225 if (visws_board_type < 0)
226 return;
227
228 /*
229 * Override the default platform setup functions
230 */
231 x86_init.resources.memory_setup = visws_memory_setup;
232 x86_init.mpparse.get_smp_config = visws_get_smp_config;
233 x86_init.mpparse.find_smp_config = visws_find_smp_config;
234 x86_init.irqs.pre_vector_init = visws_pre_intr_init;
235 x86_init.irqs.trap_init = visws_trap_init;
236 x86_init.timers.timer_init = visws_time_init;
237 x86_init.pci.init = pci_visws_init;
238 x86_init.pci.init_irq = x86_init_noop;
239
240 /*
241 * Install reboot quirks:
242 */
243 pm_power_off = visws_machine_power_off;
244 machine_ops.emergency_restart = visws_machine_emergency_restart;
245
246 /*
247 * Do not use broadcast IPIs:
248 */
249 no_broadcast = 0;
250
251#ifdef CONFIG_X86_IO_APIC
252 /*
253 * Turn off IO-APIC detection and initialization:
254 */
255 skip_ioapic_setup = 1;
256#endif
257
258 /*
259 * Get Board rev.
260 * First, we have to initialize the 307 part to allow us access
261 * to the GPIO registers. Let's map them at 0x0fc0 which is right
262 * after the PIIX4 PM section.
263 */
264 outb_p(SIO_DEV_SEL, SIO_INDEX);
265 outb_p(SIO_GP_DEV, SIO_DATA); /* Talk to GPIO regs. */
266
267 outb_p(SIO_DEV_MSB, SIO_INDEX);
268 outb_p(SIO_GP_MSB, SIO_DATA); /* MSB of GPIO base address */
269
270 outb_p(SIO_DEV_LSB, SIO_INDEX);
271 outb_p(SIO_GP_LSB, SIO_DATA); /* LSB of GPIO base address */
272
273 outb_p(SIO_DEV_ENB, SIO_INDEX);
274 outb_p(1, SIO_DATA); /* Enable GPIO registers. */
275
276 /*
277 * Now, we have to map the power management section to write
278 * a bit which enables access to the GPIO registers.
279 * What lunatic came up with this shit?
280 */
281 outb_p(SIO_DEV_SEL, SIO_INDEX);
282 outb_p(SIO_PM_DEV, SIO_DATA); /* Talk to GPIO regs. */
283
284 outb_p(SIO_DEV_MSB, SIO_INDEX);
285 outb_p(SIO_PM_MSB, SIO_DATA); /* MSB of PM base address */
286
287 outb_p(SIO_DEV_LSB, SIO_INDEX);
288 outb_p(SIO_PM_LSB, SIO_DATA); /* LSB of PM base address */
289
290 outb_p(SIO_DEV_ENB, SIO_INDEX);
291 outb_p(1, SIO_DATA); /* Enable PM registers. */
292
293 /*
294 * Now, write the PM register which enables the GPIO registers.
295 */
296 outb_p(SIO_PM_FER2, SIO_PM_INDEX);
297 outb_p(SIO_PM_GP_EN, SIO_PM_DATA);
298
299 /*
300 * Now, initialize the GPIO registers.
301 * We want them all to be inputs which is the
302 * power on default, so let's leave them alone.
303 * So, let's just read the board rev!
304 */
305 raw = inb_p(SIO_GP_DATA1);
306 raw &= 0x7f; /* 7 bits of valid board revision ID. */
307
308 if (visws_board_type == VISWS_320) {
309 if (raw < 0x6) {
310 visws_board_rev = 4;
311 } else if (raw < 0xc) {
312 visws_board_rev = 5;
313 } else {
314 visws_board_rev = 6;
315 }
316 } else if (visws_board_type == VISWS_540) {
317 visws_board_rev = 2;
318 } else {
319 visws_board_rev = raw;
320 }
321
322 printk(KERN_INFO "Silicon Graphics Visual Workstation %s (rev %d) detected\n",
323 (visws_board_type == VISWS_320 ? "320" :
324 (visws_board_type == VISWS_540 ? "540" :
325 "unknown")), visws_board_rev);
326}
327
328#define A01234 (LI_INTA_0 | LI_INTA_1 | LI_INTA_2 | LI_INTA_3 | LI_INTA_4)
329#define BCD (LI_INTB | LI_INTC | LI_INTD)
330#define ALLDEVS (A01234 | BCD)
331
332static __init void lithium_init(void)
333{
334 set_fixmap(FIX_LI_PCIA, LI_PCI_A_PHYS);
335 set_fixmap(FIX_LI_PCIB, LI_PCI_B_PHYS);
336
337 if ((li_pcia_read16(PCI_VENDOR_ID) != PCI_VENDOR_ID_SGI) ||
338 (li_pcia_read16(PCI_DEVICE_ID) != PCI_DEVICE_ID_SGI_LITHIUM)) {
339 printk(KERN_EMERG "Lithium hostbridge %c not found\n", 'A');
340/* panic("This machine is not SGI Visual Workstation 320/540"); */
341 }
342
343 if ((li_pcib_read16(PCI_VENDOR_ID) != PCI_VENDOR_ID_SGI) ||
344 (li_pcib_read16(PCI_DEVICE_ID) != PCI_DEVICE_ID_SGI_LITHIUM)) {
345 printk(KERN_EMERG "Lithium hostbridge %c not found\n", 'B');
346/* panic("This machine is not SGI Visual Workstation 320/540"); */
347 }
348
349 li_pcia_write16(LI_PCI_INTEN, ALLDEVS);
350 li_pcib_write16(LI_PCI_INTEN, ALLDEVS);
351}
352
353static __init void cobalt_init(void)
354{
355 /*
356 * On normal SMP PC this is used only with SMP, but we have to
357 * use it and set it up here to start the Cobalt clock
358 */
359 set_fixmap(FIX_APIC_BASE, APIC_DEFAULT_PHYS_BASE);
360 setup_local_APIC();
361 printk(KERN_INFO "Local APIC Version %#x, ID %#x\n",
362 (unsigned int)apic_read(APIC_LVR),
363 (unsigned int)apic_read(APIC_ID));
364
365 set_fixmap(FIX_CO_CPU, CO_CPU_PHYS);
366 set_fixmap(FIX_CO_APIC, CO_APIC_PHYS);
367 printk(KERN_INFO "Cobalt Revision %#lx, APIC ID %#lx\n",
368 co_cpu_read(CO_CPU_REV), co_apic_read(CO_APIC_ID));
369
370 /* Enable Cobalt APIC being careful to NOT change the ID! */
371 co_apic_write(CO_APIC_ID, co_apic_read(CO_APIC_ID) | CO_APIC_ENABLE);
372
373 printk(KERN_INFO "Cobalt APIC enabled: ID reg %#lx\n",
374 co_apic_read(CO_APIC_ID));
375}
376
377static void __init visws_trap_init(void)
378{
379 lithium_init();
380 cobalt_init();
381}
382
383/*
384 * IRQ controller / APIC support:
385 */
386
387static DEFINE_SPINLOCK(cobalt_lock);
388
389/*
390 * Set the given Cobalt APIC Redirection Table entry to point
391 * to the given IDT vector/index.
392 */
393static inline void co_apic_set(int entry, int irq)
394{
395 co_apic_write(CO_APIC_LO(entry), CO_APIC_LEVEL | (irq + FIRST_EXTERNAL_VECTOR));
396 co_apic_write(CO_APIC_HI(entry), 0);
397}
398
399/*
400 * Cobalt (IO)-APIC functions to handle PCI devices.
401 */
402static inline int co_apic_ide0_hack(void)
403{
404 extern char visws_board_type;
405 extern char visws_board_rev;
406
407 if (visws_board_type == VISWS_320 && visws_board_rev == 5)
408 return 5;
409 return CO_APIC_IDE0;
410}
411
412static int is_co_apic(unsigned int irq)
413{
414 if (IS_CO_APIC(irq))
415 return CO_APIC(irq);
416
417 switch (irq) {
418 case 0: return CO_APIC_CPU;
419 case CO_IRQ_IDE0: return co_apic_ide0_hack();
420 case CO_IRQ_IDE1: return CO_APIC_IDE1;
421 default: return -1;
422 }
423}
424
425
426/*
427 * This is the SGI Cobalt (IO-)APIC:
428 */
429static void enable_cobalt_irq(struct irq_data *data)
430{
431 co_apic_set(is_co_apic(data->irq), data->irq);
432}
433
434static void disable_cobalt_irq(struct irq_data *data)
435{
436 int entry = is_co_apic(data->irq);
437
438 co_apic_write(CO_APIC_LO(entry), CO_APIC_MASK);
439 co_apic_read(CO_APIC_LO(entry));
440}
441
442static void ack_cobalt_irq(struct irq_data *data)
443{
444 unsigned long flags;
445
446 spin_lock_irqsave(&cobalt_lock, flags);
447 disable_cobalt_irq(data);
448 apic_write(APIC_EOI, APIC_EOI_ACK);
449 spin_unlock_irqrestore(&cobalt_lock, flags);
450}
451
452static struct irq_chip cobalt_irq_type = {
453 .name = "Cobalt-APIC",
454 .irq_enable = enable_cobalt_irq,
455 .irq_disable = disable_cobalt_irq,
456 .irq_ack = ack_cobalt_irq,
457};
458
459
460/*
461 * This is the PIIX4-based 8259 that is wired up indirectly to Cobalt
462 * -- not the manner expected by the code in i8259.c.
463 *
464 * there is a 'master' physical interrupt source that gets sent to
465 * the CPU. But in the chipset there are various 'virtual' interrupts
466 * waiting to be handled. We represent this to Linux through a 'master'
467 * interrupt controller type, and through a special virtual interrupt-
468 * controller. Device drivers only see the virtual interrupt sources.
469 */
470static unsigned int startup_piix4_master_irq(struct irq_data *data)
471{
472 legacy_pic->init(0);
473 enable_cobalt_irq(data);
474 return 0;
475}
476
477static struct irq_chip piix4_master_irq_type = {
478 .name = "PIIX4-master",
479 .irq_startup = startup_piix4_master_irq,
480 .irq_ack = ack_cobalt_irq,
481};
482
483static void pii4_mask(struct irq_data *data) { }
484
485static struct irq_chip piix4_virtual_irq_type = {
486 .name = "PIIX4-virtual",
487 .irq_mask = pii4_mask,
488};
489
490/*
491 * PIIX4-8259 master/virtual functions to handle interrupt requests
492 * from legacy devices: floppy, parallel, serial, rtc.
493 *
494 * None of these get Cobalt APIC entries, neither do they have IDT
495 * entries. These interrupts are purely virtual and distributed from
496 * the 'master' interrupt source: CO_IRQ_8259.
497 *
498 * When the 8259 interrupts its handler figures out which of these
499 * devices is interrupting and dispatches to its handler.
500 *
501 * CAREFUL: devices see the 'virtual' interrupt only. Thus disable/
502 * enable_irq gets the right irq. This 'master' irq is never directly
503 * manipulated by any driver.
504 */
505static irqreturn_t piix4_master_intr(int irq, void *dev_id)
506{
507 unsigned long flags;
508 int realirq;
509
510 raw_spin_lock_irqsave(&i8259A_lock, flags);
511
512 /* Find out what's interrupting in the PIIX4 master 8259 */
513 outb(0x0c, 0x20); /* OCW3 Poll command */
514 realirq = inb(0x20);
515
516 /*
517 * Bit 7 == 0 means invalid/spurious
518 */
519 if (unlikely(!(realirq & 0x80)))
520 goto out_unlock;
521
522 realirq &= 7;
523
524 if (unlikely(realirq == 2)) {
525 outb(0x0c, 0xa0);
526 realirq = inb(0xa0);
527
528 if (unlikely(!(realirq & 0x80)))
529 goto out_unlock;
530
531 realirq = (realirq & 7) + 8;
532 }
533
534 /* mask and ack interrupt */
535 cached_irq_mask |= 1 << realirq;
536 if (unlikely(realirq > 7)) {
537 inb(0xa1);
538 outb(cached_slave_mask, 0xa1);
539 outb(0x60 + (realirq & 7), 0xa0);
540 outb(0x60 + 2, 0x20);
541 } else {
542 inb(0x21);
543 outb(cached_master_mask, 0x21);
544 outb(0x60 + realirq, 0x20);
545 }
546
547 raw_spin_unlock_irqrestore(&i8259A_lock, flags);
548
549 /*
550 * handle this 'virtual interrupt' as a Cobalt one now.
551 */
552 generic_handle_irq(realirq);
553
554 return IRQ_HANDLED;
555
556out_unlock:
557 raw_spin_unlock_irqrestore(&i8259A_lock, flags);
558 return IRQ_NONE;
559}
560
561static struct irqaction master_action = {
562 .handler = piix4_master_intr,
563 .name = "PIIX4-8259",
564 .flags = IRQF_NO_THREAD,
565};
566
567static struct irqaction cascade_action = {
568 .handler = no_action,
569 .name = "cascade",
570 .flags = IRQF_NO_THREAD,
571};
572
573static inline void set_piix4_virtual_irq_type(void)
574{
575 piix4_virtual_irq_type.irq_enable = i8259A_chip.irq_unmask;
576 piix4_virtual_irq_type.irq_disable = i8259A_chip.irq_mask;
577 piix4_virtual_irq_type.irq_unmask = i8259A_chip.irq_unmask;
578}
579
580static void __init visws_pre_intr_init(void)
581{
582 int i;
583
584 set_piix4_virtual_irq_type();
585
586 for (i = 0; i < CO_IRQ_APIC0 + CO_APIC_LAST + 1; i++) {
587 struct irq_chip *chip = NULL;
588
589 if (i == 0)
590 chip = &cobalt_irq_type;
591 else if (i == CO_IRQ_IDE0)
592 chip = &cobalt_irq_type;
593 else if (i == CO_IRQ_IDE1)
594 chip = &cobalt_irq_type;
595 else if (i == CO_IRQ_8259)
596 chip = &piix4_master_irq_type;
597 else if (i < CO_IRQ_APIC0)
598 chip = &piix4_virtual_irq_type;
599 else if (IS_CO_APIC(i))
600 chip = &cobalt_irq_type;
601
602 if (chip)
603 irq_set_chip(i, chip);
604 }
605
606 setup_irq(CO_IRQ_8259, &master_action);
607 setup_irq(2, &cascade_action);
608}
diff --git a/arch/x86/xen/Kconfig b/arch/x86/xen/Kconfig
index 01b90261fa38..9c50cc2e403b 100644
--- a/arch/x86/xen/Kconfig
+++ b/arch/x86/xen/Kconfig
@@ -7,7 +7,7 @@ config XEN
7 depends on PARAVIRT 7 depends on PARAVIRT
8 select PARAVIRT_CLOCK 8 select PARAVIRT_CLOCK
9 select XEN_HAVE_PVMMU 9 select XEN_HAVE_PVMMU
10 depends on X86_64 || (X86_32 && X86_PAE && !X86_VISWS) 10 depends on X86_64 || (X86_32 && X86_PAE)
11 depends on X86_TSC 11 depends on X86_TSC
12 help 12 help
13 This is the Linux Xen port. Enabling this will allow the 13 This is the Linux Xen port. Enabling this will allow the
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-20 02:20:15 -0500