diff options
author | Santosh Shilimkar <santosh.shilimkar@ti.com> | 2013-02-08 06:37:31 -0500 |
---|---|---|
committer | Nishanth Menon <nm@ti.com> | 2014-09-08 12:38:41 -0400 |
commit | 4664d4d86012c4a51b9f40d0d72e27e39205e874 (patch) | |
tree | 1f7a7a8e296dc06a22a474409c24c5be6466389c /arch | |
parent | d2136bce9db79f7d983f081c5d1b6e9359714dd6 (diff) |
ARM: OMAP5 / DRA7: PM / wakeupgen: Enables ES2 PM mode by default
Enables MPUSS ES2 power management mode using ES2_PM_MODE in
AMBA_IF_MODE register.
0x0: OMAP5 ES1 behavior, CPU cores would enter and exit OFF mode together.
Broken! Fortunately, we do not support this anymore.
0x1: OMAP5 ES2, DRA7 behavior, CPU cores are allowed to enter/exit OFF mode
independently.
This is one time settings thanks to always ON domain.
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
[nm@ti.com: minor conflict resolutions, consolidation for DRA7]
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Kevin Hilman <khilman@linaro.org>
Tested-by: Kevin Hilman <khilman@linaro.org>
Diffstat (limited to 'arch')
-rw-r--r-- | arch/arm/mach-omap2/omap-secure.h | 1 | ||||
-rw-r--r-- | arch/arm/mach-omap2/omap-wakeupgen.c | 17 | ||||
-rw-r--r-- | arch/arm/mach-omap2/omap-wakeupgen.h | 1 |
3 files changed, 19 insertions, 0 deletions
diff --git a/arch/arm/mach-omap2/omap-secure.h b/arch/arm/mach-omap2/omap-secure.h index 3e97c6c8ecf1..dec2b05d184b 100644 --- a/arch/arm/mach-omap2/omap-secure.h +++ b/arch/arm/mach-omap2/omap-secure.h | |||
@@ -45,6 +45,7 @@ | |||
45 | #define OMAP4_MON_L2X0_PREFETCH_INDEX 0x113 | 45 | #define OMAP4_MON_L2X0_PREFETCH_INDEX 0x113 |
46 | 46 | ||
47 | #define OMAP5_DRA7_MON_SET_CNTFRQ_INDEX 0x109 | 47 | #define OMAP5_DRA7_MON_SET_CNTFRQ_INDEX 0x109 |
48 | #define OMAP5_MON_AMBA_IF_INDEX 0x108 | ||
48 | 49 | ||
49 | /* Secure PPA(Primary Protected Application) APIs */ | 50 | /* Secure PPA(Primary Protected Application) APIs */ |
50 | #define OMAP4_PPA_L2_POR_INDEX 0x23 | 51 | #define OMAP4_PPA_L2_POR_INDEX 0x23 |
diff --git a/arch/arm/mach-omap2/omap-wakeupgen.c b/arch/arm/mach-omap2/omap-wakeupgen.c index 37843a7d3639..e844e1603d76 100644 --- a/arch/arm/mach-omap2/omap-wakeupgen.c +++ b/arch/arm/mach-omap2/omap-wakeupgen.c | |||
@@ -406,6 +406,7 @@ int __init omap_wakeupgen_init(void) | |||
406 | { | 406 | { |
407 | int i; | 407 | int i; |
408 | unsigned int boot_cpu = smp_processor_id(); | 408 | unsigned int boot_cpu = smp_processor_id(); |
409 | u32 val; | ||
409 | 410 | ||
410 | /* Not supported on OMAP4 ES1.0 silicon */ | 411 | /* Not supported on OMAP4 ES1.0 silicon */ |
411 | if (omap_rev() == OMAP4430_REV_ES1_0) { | 412 | if (omap_rev() == OMAP4430_REV_ES1_0) { |
@@ -451,6 +452,22 @@ int __init omap_wakeupgen_init(void) | |||
451 | for (i = 0; i < max_irqs; i++) | 452 | for (i = 0; i < max_irqs; i++) |
452 | irq_target_cpu[i] = boot_cpu; | 453 | irq_target_cpu[i] = boot_cpu; |
453 | 454 | ||
455 | /* | ||
456 | * Enables OMAP5 ES2 PM Mode using ES2_PM_MODE in AMBA_IF_MODE | ||
457 | * 0x0: ES1 behavior, CPU cores would enter and exit OFF mode together. | ||
458 | * 0x1: ES2 behavior, CPU cores are allowed to enter/exit OFF mode | ||
459 | * independently. | ||
460 | * This needs to be set one time thanks to always ON domain. | ||
461 | * | ||
462 | * We do not support ES1 behavior anymore. OMAP5 is assumed to be | ||
463 | * ES2.0, and the same is applicable for DRA7. | ||
464 | */ | ||
465 | if (soc_is_omap54xx() || soc_is_dra7xx()) { | ||
466 | val = __raw_readl(wakeupgen_base + OMAP_AMBA_IF_MODE); | ||
467 | val |= BIT(5); | ||
468 | omap_smc1(OMAP5_MON_AMBA_IF_INDEX, val); | ||
469 | } | ||
470 | |||
454 | irq_hotplug_init(); | 471 | irq_hotplug_init(); |
455 | irq_pm_init(); | 472 | irq_pm_init(); |
456 | 473 | ||
diff --git a/arch/arm/mach-omap2/omap-wakeupgen.h b/arch/arm/mach-omap2/omap-wakeupgen.h index b0fd16f5c391..b3c8eccfae79 100644 --- a/arch/arm/mach-omap2/omap-wakeupgen.h +++ b/arch/arm/mach-omap2/omap-wakeupgen.h | |||
@@ -27,6 +27,7 @@ | |||
27 | #define OMAP_WKG_ENB_E_1 0x420 | 27 | #define OMAP_WKG_ENB_E_1 0x420 |
28 | #define OMAP_AUX_CORE_BOOT_0 0x800 | 28 | #define OMAP_AUX_CORE_BOOT_0 0x800 |
29 | #define OMAP_AUX_CORE_BOOT_1 0x804 | 29 | #define OMAP_AUX_CORE_BOOT_1 0x804 |
30 | #define OMAP_AMBA_IF_MODE 0x80c | ||
30 | #define OMAP_PTMSYNCREQ_MASK 0xc00 | 31 | #define OMAP_PTMSYNCREQ_MASK 0xc00 |
31 | #define OMAP_PTMSYNCREQ_EN 0xc04 | 32 | #define OMAP_PTMSYNCREQ_EN 0xc04 |
32 | #define OMAP_TIMESTAMPCYCLELO 0xc08 | 33 | #define OMAP_TIMESTAMPCYCLELO 0xc08 |