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authorMatt Evans <matt@ozlabs.org>2011-04-06 15:48:50 -0400
committerBenjamin Herrenschmidt <benh@kernel.crashing.org>2011-04-27 00:18:52 -0400
commit44ae3ab3358e962039c36ad4ae461ae9fb29596c (patch)
tree08c0628a5226c0535b7fe236be64b48e5eb0fbd6 /arch
parenteca590f402332ab873d13f2d8d00fa0b91cfff36 (diff)
powerpc: Free up some CPU feature bits by moving out MMU-related features
Some of the 64bit PPC CPU features are MMU-related, so this patch moves them to MMU_FTR_ bits. All cpu_has_feature()-style tests are moved to mmu_has_feature(), and seven feature bits are freed as a result. Signed-off-by: Matt Evans <matt@ozlabs.org> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Diffstat (limited to 'arch')
-rw-r--r--arch/powerpc/include/asm/cputable.h37
-rw-r--r--arch/powerpc/include/asm/mmu.h48
-rw-r--r--arch/powerpc/include/asm/mmu_context.h2
-rw-r--r--arch/powerpc/kernel/cputable.c45
-rw-r--r--arch/powerpc/kernel/entry_64.S8
-rw-r--r--arch/powerpc/kernel/exceptions-64s.S4
-rw-r--r--arch/powerpc/kernel/process.c4
-rw-r--r--arch/powerpc/kernel/prom.c17
-rw-r--r--arch/powerpc/kernel/setup_64.c2
-rw-r--r--arch/powerpc/mm/hash_low_64.S8
-rw-r--r--arch/powerpc/mm/hash_native_64.c8
-rw-r--r--arch/powerpc/mm/hash_utils_64.c18
-rw-r--r--arch/powerpc/mm/hugetlbpage.c2
-rw-r--r--arch/powerpc/mm/slb.c4
-rw-r--r--arch/powerpc/mm/slb_low.S8
-rw-r--r--arch/powerpc/mm/stab.c2
-rw-r--r--arch/powerpc/platforms/iseries/exception.S3
-rw-r--r--arch/powerpc/platforms/iseries/setup.c4
-rw-r--r--arch/powerpc/platforms/pseries/lpar.c2
-rw-r--r--arch/powerpc/xmon/xmon.c2
20 files changed, 132 insertions, 96 deletions
diff --git a/arch/powerpc/include/asm/cputable.h b/arch/powerpc/include/asm/cputable.h
index 2d71523ebb03..3db2476704d6 100644
--- a/arch/powerpc/include/asm/cputable.h
+++ b/arch/powerpc/include/asm/cputable.h
@@ -178,23 +178,17 @@ extern const char *powerpc_base_platform;
178#define LONG_ASM_CONST(x) 0 178#define LONG_ASM_CONST(x) 0
179#endif 179#endif
180 180
181#define CPU_FTR_SLB LONG_ASM_CONST(0x0000000100000000) 181
182#define CPU_FTR_16M_PAGE LONG_ASM_CONST(0x0000000200000000)
183#define CPU_FTR_TLBIEL LONG_ASM_CONST(0x0000000400000000)
184#define CPU_FTR_HVMODE_206 LONG_ASM_CONST(0x0000000800000000) 182#define CPU_FTR_HVMODE_206 LONG_ASM_CONST(0x0000000800000000)
185#define CPU_FTR_IABR LONG_ASM_CONST(0x0000002000000000) 183#define CPU_FTR_IABR LONG_ASM_CONST(0x0000002000000000)
186#define CPU_FTR_MMCRA LONG_ASM_CONST(0x0000004000000000) 184#define CPU_FTR_MMCRA LONG_ASM_CONST(0x0000004000000000)
187#define CPU_FTR_CTRL LONG_ASM_CONST(0x0000008000000000) 185#define CPU_FTR_CTRL LONG_ASM_CONST(0x0000008000000000)
188#define CPU_FTR_SMT LONG_ASM_CONST(0x0000010000000000) 186#define CPU_FTR_SMT LONG_ASM_CONST(0x0000010000000000)
189#define CPU_FTR_LOCKLESS_TLBIE LONG_ASM_CONST(0x0000040000000000)
190#define CPU_FTR_CI_LARGE_PAGE LONG_ASM_CONST(0x0000100000000000)
191#define CPU_FTR_PAUSE_ZERO LONG_ASM_CONST(0x0000200000000000) 187#define CPU_FTR_PAUSE_ZERO LONG_ASM_CONST(0x0000200000000000)
192#define CPU_FTR_PURR LONG_ASM_CONST(0x0000400000000000) 188#define CPU_FTR_PURR LONG_ASM_CONST(0x0000400000000000)
193#define CPU_FTR_CELL_TB_BUG LONG_ASM_CONST(0x0000800000000000) 189#define CPU_FTR_CELL_TB_BUG LONG_ASM_CONST(0x0000800000000000)
194#define CPU_FTR_SPURR LONG_ASM_CONST(0x0001000000000000) 190#define CPU_FTR_SPURR LONG_ASM_CONST(0x0001000000000000)
195#define CPU_FTR_DSCR LONG_ASM_CONST(0x0002000000000000) 191#define CPU_FTR_DSCR LONG_ASM_CONST(0x0002000000000000)
196#define CPU_FTR_1T_SEGMENT LONG_ASM_CONST(0x0004000000000000)
197#define CPU_FTR_NO_SLBIE_B LONG_ASM_CONST(0x0008000000000000)
198#define CPU_FTR_VSX LONG_ASM_CONST(0x0010000000000000) 192#define CPU_FTR_VSX LONG_ASM_CONST(0x0010000000000000)
199#define CPU_FTR_SAO LONG_ASM_CONST(0x0020000000000000) 193#define CPU_FTR_SAO LONG_ASM_CONST(0x0020000000000000)
200#define CPU_FTR_CP_USE_DCBTZ LONG_ASM_CONST(0x0040000000000000) 194#define CPU_FTR_CP_USE_DCBTZ LONG_ASM_CONST(0x0040000000000000)
@@ -206,9 +200,10 @@ extern const char *powerpc_base_platform;
206 200
207#ifndef __ASSEMBLY__ 201#ifndef __ASSEMBLY__
208 202
209#define CPU_FTR_PPCAS_ARCH_V2 (CPU_FTR_SLB | \ 203#define CPU_FTR_PPCAS_ARCH_V2 (CPU_FTR_NOEXECUTE | CPU_FTR_NODSISRALIGN)
210 CPU_FTR_TLBIEL | CPU_FTR_NOEXECUTE | \ 204
211 CPU_FTR_NODSISRALIGN | CPU_FTR_16M_PAGE) 205#define MMU_FTR_PPCAS_ARCH_V2 (MMU_FTR_SLB | MMU_FTR_TLBIEL | \
206 MMU_FTR_16M_PAGE)
212 207
213/* We only set the altivec features if the kernel was compiled with altivec 208/* We only set the altivec features if the kernel was compiled with altivec
214 * support 209 * support
@@ -408,38 +403,34 @@ extern const char *powerpc_base_platform;
408#define CPU_FTRS_POWER5 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \ 403#define CPU_FTRS_POWER5 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
409 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \ 404 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
410 CPU_FTR_MMCRA | CPU_FTR_SMT | \ 405 CPU_FTR_MMCRA | CPU_FTR_SMT | \
411 CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \ 406 CPU_FTR_COHERENT_ICACHE | CPU_FTR_PURR | \
412 CPU_FTR_PURR | CPU_FTR_STCX_CHECKS_ADDRESS | \ 407 CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB)
413 CPU_FTR_POPCNTB)
414#define CPU_FTRS_POWER6 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \ 408#define CPU_FTRS_POWER6 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
415 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \ 409 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
416 CPU_FTR_MMCRA | CPU_FTR_SMT | \ 410 CPU_FTR_MMCRA | CPU_FTR_SMT | \
417 CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \ 411 CPU_FTR_COHERENT_ICACHE | \
418 CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \ 412 CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
419 CPU_FTR_DSCR | CPU_FTR_UNALIGNED_LD_STD | \ 413 CPU_FTR_DSCR | CPU_FTR_UNALIGNED_LD_STD | \
420 CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB) 414 CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB)
421#define CPU_FTRS_POWER7 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \ 415#define CPU_FTRS_POWER7 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
422 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_HVMODE_206 |\ 416 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_HVMODE_206 |\
423 CPU_FTR_MMCRA | CPU_FTR_SMT | \ 417 CPU_FTR_MMCRA | CPU_FTR_SMT | \
424 CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \ 418 CPU_FTR_COHERENT_ICACHE | \
425 CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \ 419 CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
426 CPU_FTR_DSCR | CPU_FTR_SAO | CPU_FTR_ASYM_SMT | \ 420 CPU_FTR_DSCR | CPU_FTR_SAO | CPU_FTR_ASYM_SMT | \
427 CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD) 421 CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD)
428#define CPU_FTRS_CELL (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \ 422#define CPU_FTRS_CELL (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
429 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \ 423 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
430 CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \ 424 CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \
431 CPU_FTR_PAUSE_ZERO | CPU_FTR_CI_LARGE_PAGE | \ 425 CPU_FTR_PAUSE_ZERO | CPU_FTR_CELL_TB_BUG | CPU_FTR_CP_USE_DCBTZ | \
432 CPU_FTR_CELL_TB_BUG | CPU_FTR_CP_USE_DCBTZ | \
433 CPU_FTR_UNALIGNED_LD_STD) 426 CPU_FTR_UNALIGNED_LD_STD)
434#define CPU_FTRS_PA6T (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \ 427#define CPU_FTRS_PA6T (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
435 CPU_FTR_PPCAS_ARCH_V2 | \ 428 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_ALTIVEC_COMP | \
436 CPU_FTR_ALTIVEC_COMP | CPU_FTR_CI_LARGE_PAGE | \ 429 CPU_FTR_PURR | CPU_FTR_REAL_LE)
437 CPU_FTR_PURR | CPU_FTR_REAL_LE | CPU_FTR_NO_SLBIE_B)
438#define CPU_FTRS_COMPATIBLE (CPU_FTR_USE_TB | CPU_FTR_PPCAS_ARCH_V2) 430#define CPU_FTRS_COMPATIBLE (CPU_FTR_USE_TB | CPU_FTR_PPCAS_ARCH_V2)
439 431
440#define CPU_FTRS_A2 (CPU_FTR_USE_TB | CPU_FTR_SMT | CPU_FTR_DBELL | \ 432#define CPU_FTRS_A2 (CPU_FTR_USE_TB | CPU_FTR_SMT | CPU_FTR_DBELL | \
441 CPU_FTR_TLBIEL | CPU_FTR_NOEXECUTE | CPU_FTR_NODSISRALIGN | \ 433 CPU_FTR_NOEXECUTE | CPU_FTR_NODSISRALIGN)
442 CPU_FTR_16M_PAGE)
443 434
444#ifdef __powerpc64__ 435#ifdef __powerpc64__
445#ifdef CONFIG_PPC_BOOK3E 436#ifdef CONFIG_PPC_BOOK3E
@@ -449,7 +440,7 @@ extern const char *powerpc_base_platform;
449 (CPU_FTRS_POWER3 | CPU_FTRS_RS64 | CPU_FTRS_POWER4 | \ 440 (CPU_FTRS_POWER3 | CPU_FTRS_RS64 | CPU_FTRS_POWER4 | \
450 CPU_FTRS_PPC970 | CPU_FTRS_POWER5 | CPU_FTRS_POWER6 | \ 441 CPU_FTRS_PPC970 | CPU_FTRS_POWER5 | CPU_FTRS_POWER6 | \
451 CPU_FTRS_POWER7 | CPU_FTRS_CELL | CPU_FTRS_PA6T | \ 442 CPU_FTRS_POWER7 | CPU_FTRS_CELL | CPU_FTRS_PA6T | \
452 CPU_FTR_1T_SEGMENT | CPU_FTR_VSX) 443 CPU_FTR_VSX)
453#endif 444#endif
454#else 445#else
455enum { 446enum {
diff --git a/arch/powerpc/include/asm/mmu.h b/arch/powerpc/include/asm/mmu.h
index bb40a06d3b77..a39304b74f84 100644
--- a/arch/powerpc/include/asm/mmu.h
+++ b/arch/powerpc/include/asm/mmu.h
@@ -70,6 +70,54 @@
70 */ 70 */
71#define MMU_FTR_USE_PAIRED_MAS ASM_CONST(0x01000000) 71#define MMU_FTR_USE_PAIRED_MAS ASM_CONST(0x01000000)
72 72
73/* MMU is SLB-based
74 */
75#define MMU_FTR_SLB ASM_CONST(0x02000000)
76
77/* Support 16M large pages
78 */
79#define MMU_FTR_16M_PAGE ASM_CONST(0x04000000)
80
81/* Supports TLBIEL variant
82 */
83#define MMU_FTR_TLBIEL ASM_CONST(0x08000000)
84
85/* Supports tlbies w/o locking
86 */
87#define MMU_FTR_LOCKLESS_TLBIE ASM_CONST(0x10000000)
88
89/* Large pages can be marked CI
90 */
91#define MMU_FTR_CI_LARGE_PAGE ASM_CONST(0x20000000)
92
93/* 1T segments available
94 */
95#define MMU_FTR_1T_SEGMENT ASM_CONST(0x40000000)
96
97/* Doesn't support the B bit (1T segment) in SLBIE
98 */
99#define MMU_FTR_NO_SLBIE_B ASM_CONST(0x80000000)
100
101/* MMU feature bit sets for various CPUs */
102#define MMU_FTRS_DEFAULT_HPTE_ARCH_V2 \
103 MMU_FTR_HPTE_TABLE | MMU_FTR_PPCAS_ARCH_V2
104#define MMU_FTRS_POWER4 MMU_FTRS_DEFAULT_HPTE_ARCH_V2
105#define MMU_FTRS_PPC970 MMU_FTRS_POWER4
106#define MMU_FTRS_POWER5 MMU_FTRS_POWER4 | MMU_FTR_LOCKLESS_TLBIE
107#define MMU_FTRS_POWER6 MMU_FTRS_POWER4 | MMU_FTR_LOCKLESS_TLBIE
108#define MMU_FTRS_POWER7 MMU_FTRS_POWER4 | MMU_FTR_LOCKLESS_TLBIE | \
109 MMU_FTR_TLBIE_206
110#define MMU_FTRS_CELL MMU_FTRS_DEFAULT_HPTE_ARCH_V2 | \
111 MMU_FTR_CI_LARGE_PAGE
112#define MMU_FTRS_PA6T MMU_FTRS_DEFAULT_HPTE_ARCH_V2 | \
113 MMU_FTR_CI_LARGE_PAGE | MMU_FTR_NO_SLBIE_B
114#define MMU_FTRS_A2 MMU_FTR_TYPE_3E | MMU_FTR_USE_TLBILX | \
115 MMU_FTR_USE_TLBIVAX_BCAST | \
116 MMU_FTR_LOCK_BCAST_INVAL | \
117 MMU_FTR_USE_TLBRSRV | \
118 MMU_FTR_USE_PAIRED_MAS | \
119 MMU_FTR_TLBIEL | \
120 MMU_FTR_16M_PAGE
73#ifndef __ASSEMBLY__ 121#ifndef __ASSEMBLY__
74#include <asm/cputable.h> 122#include <asm/cputable.h>
75 123
diff --git a/arch/powerpc/include/asm/mmu_context.h b/arch/powerpc/include/asm/mmu_context.h
index 81fb41289d6c..8e13f65b498c 100644
--- a/arch/powerpc/include/asm/mmu_context.h
+++ b/arch/powerpc/include/asm/mmu_context.h
@@ -67,7 +67,7 @@ static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next,
67 * sub architectures. 67 * sub architectures.
68 */ 68 */
69#ifdef CONFIG_PPC_STD_MMU_64 69#ifdef CONFIG_PPC_STD_MMU_64
70 if (cpu_has_feature(CPU_FTR_SLB)) 70 if (mmu_has_feature(MMU_FTR_SLB))
71 switch_slb(tsk, next); 71 switch_slb(tsk, next);
72 else 72 else
73 switch_stab(tsk, next); 73 switch_stab(tsk, next);
diff --git a/arch/powerpc/kernel/cputable.c b/arch/powerpc/kernel/cputable.c
index 3d7b65ad4962..34d2722b9451 100644
--- a/arch/powerpc/kernel/cputable.c
+++ b/arch/powerpc/kernel/cputable.c
@@ -201,7 +201,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
201 .cpu_name = "POWER4 (gp)", 201 .cpu_name = "POWER4 (gp)",
202 .cpu_features = CPU_FTRS_POWER4, 202 .cpu_features = CPU_FTRS_POWER4,
203 .cpu_user_features = COMMON_USER_POWER4, 203 .cpu_user_features = COMMON_USER_POWER4,
204 .mmu_features = MMU_FTR_HPTE_TABLE, 204 .mmu_features = MMU_FTRS_POWER4,
205 .icache_bsize = 128, 205 .icache_bsize = 128,
206 .dcache_bsize = 128, 206 .dcache_bsize = 128,
207 .num_pmcs = 8, 207 .num_pmcs = 8,
@@ -216,7 +216,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
216 .cpu_name = "POWER4+ (gq)", 216 .cpu_name = "POWER4+ (gq)",
217 .cpu_features = CPU_FTRS_POWER4, 217 .cpu_features = CPU_FTRS_POWER4,
218 .cpu_user_features = COMMON_USER_POWER4, 218 .cpu_user_features = COMMON_USER_POWER4,
219 .mmu_features = MMU_FTR_HPTE_TABLE, 219 .mmu_features = MMU_FTRS_POWER4,
220 .icache_bsize = 128, 220 .icache_bsize = 128,
221 .dcache_bsize = 128, 221 .dcache_bsize = 128,
222 .num_pmcs = 8, 222 .num_pmcs = 8,
@@ -232,7 +232,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
232 .cpu_features = CPU_FTRS_PPC970, 232 .cpu_features = CPU_FTRS_PPC970,
233 .cpu_user_features = COMMON_USER_POWER4 | 233 .cpu_user_features = COMMON_USER_POWER4 |
234 PPC_FEATURE_HAS_ALTIVEC_COMP, 234 PPC_FEATURE_HAS_ALTIVEC_COMP,
235 .mmu_features = MMU_FTR_HPTE_TABLE, 235 .mmu_features = MMU_FTRS_PPC970,
236 .icache_bsize = 128, 236 .icache_bsize = 128,
237 .dcache_bsize = 128, 237 .dcache_bsize = 128,
238 .num_pmcs = 8, 238 .num_pmcs = 8,
@@ -250,7 +250,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
250 .cpu_features = CPU_FTRS_PPC970, 250 .cpu_features = CPU_FTRS_PPC970,
251 .cpu_user_features = COMMON_USER_POWER4 | 251 .cpu_user_features = COMMON_USER_POWER4 |
252 PPC_FEATURE_HAS_ALTIVEC_COMP, 252 PPC_FEATURE_HAS_ALTIVEC_COMP,
253 .mmu_features = MMU_FTR_HPTE_TABLE, 253 .mmu_features = MMU_FTRS_PPC970,
254 .icache_bsize = 128, 254 .icache_bsize = 128,
255 .dcache_bsize = 128, 255 .dcache_bsize = 128,
256 .num_pmcs = 8, 256 .num_pmcs = 8,
@@ -286,7 +286,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
286 .cpu_features = CPU_FTRS_PPC970, 286 .cpu_features = CPU_FTRS_PPC970,
287 .cpu_user_features = COMMON_USER_POWER4 | 287 .cpu_user_features = COMMON_USER_POWER4 |
288 PPC_FEATURE_HAS_ALTIVEC_COMP, 288 PPC_FEATURE_HAS_ALTIVEC_COMP,
289 .mmu_features = MMU_FTR_HPTE_TABLE, 289 .mmu_features = MMU_FTRS_PPC970,
290 .icache_bsize = 128, 290 .icache_bsize = 128,
291 .dcache_bsize = 128, 291 .dcache_bsize = 128,
292 .num_pmcs = 8, 292 .num_pmcs = 8,
@@ -304,7 +304,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
304 .cpu_features = CPU_FTRS_PPC970, 304 .cpu_features = CPU_FTRS_PPC970,
305 .cpu_user_features = COMMON_USER_POWER4 | 305 .cpu_user_features = COMMON_USER_POWER4 |
306 PPC_FEATURE_HAS_ALTIVEC_COMP, 306 PPC_FEATURE_HAS_ALTIVEC_COMP,
307 .mmu_features = MMU_FTR_HPTE_TABLE, 307 .mmu_features = MMU_FTRS_PPC970,
308 .icache_bsize = 128, 308 .icache_bsize = 128,
309 .dcache_bsize = 128, 309 .dcache_bsize = 128,
310 .num_pmcs = 8, 310 .num_pmcs = 8,
@@ -320,7 +320,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
320 .cpu_name = "POWER5 (gr)", 320 .cpu_name = "POWER5 (gr)",
321 .cpu_features = CPU_FTRS_POWER5, 321 .cpu_features = CPU_FTRS_POWER5,
322 .cpu_user_features = COMMON_USER_POWER5, 322 .cpu_user_features = COMMON_USER_POWER5,
323 .mmu_features = MMU_FTR_HPTE_TABLE, 323 .mmu_features = MMU_FTRS_POWER5,
324 .icache_bsize = 128, 324 .icache_bsize = 128,
325 .dcache_bsize = 128, 325 .dcache_bsize = 128,
326 .num_pmcs = 6, 326 .num_pmcs = 6,
@@ -340,7 +340,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
340 .cpu_name = "POWER5+ (gs)", 340 .cpu_name = "POWER5+ (gs)",
341 .cpu_features = CPU_FTRS_POWER5, 341 .cpu_features = CPU_FTRS_POWER5,
342 .cpu_user_features = COMMON_USER_POWER5_PLUS, 342 .cpu_user_features = COMMON_USER_POWER5_PLUS,
343 .mmu_features = MMU_FTR_HPTE_TABLE, 343 .mmu_features = MMU_FTRS_POWER5,
344 .icache_bsize = 128, 344 .icache_bsize = 128,
345 .dcache_bsize = 128, 345 .dcache_bsize = 128,
346 .num_pmcs = 6, 346 .num_pmcs = 6,
@@ -356,7 +356,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
356 .cpu_name = "POWER5+ (gs)", 356 .cpu_name = "POWER5+ (gs)",
357 .cpu_features = CPU_FTRS_POWER5, 357 .cpu_features = CPU_FTRS_POWER5,
358 .cpu_user_features = COMMON_USER_POWER5_PLUS, 358 .cpu_user_features = COMMON_USER_POWER5_PLUS,
359 .mmu_features = MMU_FTR_HPTE_TABLE, 359 .mmu_features = MMU_FTRS_POWER5,
360 .icache_bsize = 128, 360 .icache_bsize = 128,
361 .dcache_bsize = 128, 361 .dcache_bsize = 128,
362 .num_pmcs = 6, 362 .num_pmcs = 6,
@@ -373,7 +373,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
373 .cpu_name = "POWER5+", 373 .cpu_name = "POWER5+",
374 .cpu_features = CPU_FTRS_POWER5, 374 .cpu_features = CPU_FTRS_POWER5,
375 .cpu_user_features = COMMON_USER_POWER5_PLUS, 375 .cpu_user_features = COMMON_USER_POWER5_PLUS,
376 .mmu_features = MMU_FTR_HPTE_TABLE, 376 .mmu_features = MMU_FTRS_POWER5,
377 .icache_bsize = 128, 377 .icache_bsize = 128,
378 .dcache_bsize = 128, 378 .dcache_bsize = 128,
379 .oprofile_cpu_type = "ppc64/ibm-compat-v1", 379 .oprofile_cpu_type = "ppc64/ibm-compat-v1",
@@ -387,7 +387,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
387 .cpu_features = CPU_FTRS_POWER6, 387 .cpu_features = CPU_FTRS_POWER6,
388 .cpu_user_features = COMMON_USER_POWER6 | 388 .cpu_user_features = COMMON_USER_POWER6 |
389 PPC_FEATURE_POWER6_EXT, 389 PPC_FEATURE_POWER6_EXT,
390 .mmu_features = MMU_FTR_HPTE_TABLE, 390 .mmu_features = MMU_FTRS_POWER6,
391 .icache_bsize = 128, 391 .icache_bsize = 128,
392 .dcache_bsize = 128, 392 .dcache_bsize = 128,
393 .num_pmcs = 6, 393 .num_pmcs = 6,
@@ -406,7 +406,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
406 .cpu_name = "POWER6 (architected)", 406 .cpu_name = "POWER6 (architected)",
407 .cpu_features = CPU_FTRS_POWER6, 407 .cpu_features = CPU_FTRS_POWER6,
408 .cpu_user_features = COMMON_USER_POWER6, 408 .cpu_user_features = COMMON_USER_POWER6,
409 .mmu_features = MMU_FTR_HPTE_TABLE, 409 .mmu_features = MMU_FTRS_POWER6,
410 .icache_bsize = 128, 410 .icache_bsize = 128,
411 .dcache_bsize = 128, 411 .dcache_bsize = 128,
412 .oprofile_cpu_type = "ppc64/ibm-compat-v1", 412 .oprofile_cpu_type = "ppc64/ibm-compat-v1",
@@ -419,8 +419,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
419 .cpu_name = "POWER7 (architected)", 419 .cpu_name = "POWER7 (architected)",
420 .cpu_features = CPU_FTRS_POWER7, 420 .cpu_features = CPU_FTRS_POWER7,
421 .cpu_user_features = COMMON_USER_POWER7, 421 .cpu_user_features = COMMON_USER_POWER7,
422 .mmu_features = MMU_FTR_HPTE_TABLE | 422 .mmu_features = MMU_FTRS_POWER7,
423 MMU_FTR_TLBIE_206,
424 .icache_bsize = 128, 423 .icache_bsize = 128,
425 .dcache_bsize = 128, 424 .dcache_bsize = 128,
426 .oprofile_type = PPC_OPROFILE_POWER4, 425 .oprofile_type = PPC_OPROFILE_POWER4,
@@ -435,8 +434,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
435 .cpu_name = "POWER7 (raw)", 434 .cpu_name = "POWER7 (raw)",
436 .cpu_features = CPU_FTRS_POWER7, 435 .cpu_features = CPU_FTRS_POWER7,
437 .cpu_user_features = COMMON_USER_POWER7, 436 .cpu_user_features = COMMON_USER_POWER7,
438 .mmu_features = MMU_FTR_HPTE_TABLE | 437 .mmu_features = MMU_FTRS_POWER7,
439 MMU_FTR_TLBIE_206,
440 .icache_bsize = 128, 438 .icache_bsize = 128,
441 .dcache_bsize = 128, 439 .dcache_bsize = 128,
442 .num_pmcs = 6, 440 .num_pmcs = 6,
@@ -453,8 +451,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
453 .cpu_name = "POWER7+ (raw)", 451 .cpu_name = "POWER7+ (raw)",
454 .cpu_features = CPU_FTRS_POWER7, 452 .cpu_features = CPU_FTRS_POWER7,
455 .cpu_user_features = COMMON_USER_POWER7, 453 .cpu_user_features = COMMON_USER_POWER7,
456 .mmu_features = MMU_FTR_HPTE_TABLE | 454 .mmu_features = MMU_FTRS_POWER7,
457 MMU_FTR_TLBIE_206,
458 .icache_bsize = 128, 455 .icache_bsize = 128,
459 .dcache_bsize = 128, 456 .dcache_bsize = 128,
460 .num_pmcs = 6, 457 .num_pmcs = 6,
@@ -473,7 +470,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
473 .cpu_user_features = COMMON_USER_PPC64 | 470 .cpu_user_features = COMMON_USER_PPC64 |
474 PPC_FEATURE_CELL | PPC_FEATURE_HAS_ALTIVEC_COMP | 471 PPC_FEATURE_CELL | PPC_FEATURE_HAS_ALTIVEC_COMP |
475 PPC_FEATURE_SMT, 472 PPC_FEATURE_SMT,
476 .mmu_features = MMU_FTR_HPTE_TABLE, 473 .mmu_features = MMU_FTRS_CELL,
477 .icache_bsize = 128, 474 .icache_bsize = 128,
478 .dcache_bsize = 128, 475 .dcache_bsize = 128,
479 .num_pmcs = 4, 476 .num_pmcs = 4,
@@ -488,7 +485,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
488 .cpu_name = "PA6T", 485 .cpu_name = "PA6T",
489 .cpu_features = CPU_FTRS_PA6T, 486 .cpu_features = CPU_FTRS_PA6T,
490 .cpu_user_features = COMMON_USER_PA6T, 487 .cpu_user_features = COMMON_USER_PA6T,
491 .mmu_features = MMU_FTR_HPTE_TABLE, 488 .mmu_features = MMU_FTRS_PA6T,
492 .icache_bsize = 64, 489 .icache_bsize = 64,
493 .dcache_bsize = 64, 490 .dcache_bsize = 64,
494 .num_pmcs = 6, 491 .num_pmcs = 6,
@@ -505,7 +502,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
505 .cpu_name = "POWER4 (compatible)", 502 .cpu_name = "POWER4 (compatible)",
506 .cpu_features = CPU_FTRS_COMPATIBLE, 503 .cpu_features = CPU_FTRS_COMPATIBLE,
507 .cpu_user_features = COMMON_USER_PPC64, 504 .cpu_user_features = COMMON_USER_PPC64,
508 .mmu_features = MMU_FTR_HPTE_TABLE, 505 .mmu_features = MMU_FTRS_DEFAULT_HPTE_ARCH_V2,
509 .icache_bsize = 128, 506 .icache_bsize = 128,
510 .dcache_bsize = 128, 507 .dcache_bsize = 128,
511 .num_pmcs = 6, 508 .num_pmcs = 6,
@@ -2020,11 +2017,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
2020 .cpu_name = "A2 (>= DD2)", 2017 .cpu_name = "A2 (>= DD2)",
2021 .cpu_features = CPU_FTRS_A2, 2018 .cpu_features = CPU_FTRS_A2,
2022 .cpu_user_features = COMMON_USER_PPC64, 2019 .cpu_user_features = COMMON_USER_PPC64,
2023 .mmu_features = MMU_FTR_TYPE_3E | MMU_FTR_USE_TLBILX | 2020 .mmu_features = MMU_FTRS_A2,
2024 MMU_FTR_USE_TLBIVAX_BCAST |
2025 MMU_FTR_LOCK_BCAST_INVAL |
2026 MMU_FTR_USE_TLBRSRV |
2027 MMU_FTR_USE_PAIRED_MAS,
2028 .icache_bsize = 64, 2021 .icache_bsize = 64,
2029 .dcache_bsize = 64, 2022 .dcache_bsize = 64,
2030 .num_pmcs = 0, 2023 .num_pmcs = 0,
diff --git a/arch/powerpc/kernel/entry_64.S b/arch/powerpc/kernel/entry_64.S
index 64693706ebfd..d834425186ae 100644
--- a/arch/powerpc/kernel/entry_64.S
+++ b/arch/powerpc/kernel/entry_64.S
@@ -468,10 +468,10 @@ BEGIN_FTR_SECTION
468 FTR_SECTION_ELSE_NESTED(95) 468 FTR_SECTION_ELSE_NESTED(95)
469 clrrdi r6,r8,40 /* get its 1T ESID */ 469 clrrdi r6,r8,40 /* get its 1T ESID */
470 clrrdi r9,r1,40 /* get current sp 1T ESID */ 470 clrrdi r9,r1,40 /* get current sp 1T ESID */
471 ALT_FTR_SECTION_END_NESTED_IFCLR(CPU_FTR_1T_SEGMENT, 95) 471 ALT_MMU_FTR_SECTION_END_NESTED_IFCLR(MMU_FTR_1T_SEGMENT, 95)
472FTR_SECTION_ELSE 472FTR_SECTION_ELSE
473 b 2f 473 b 2f
474ALT_FTR_SECTION_END_IFSET(CPU_FTR_SLB) 474ALT_MMU_FTR_SECTION_END_IFSET(MMU_FTR_SLB)
475 clrldi. r0,r6,2 /* is new ESID c00000000? */ 475 clrldi. r0,r6,2 /* is new ESID c00000000? */
476 cmpd cr1,r6,r9 /* or is new ESID the same as current ESID? */ 476 cmpd cr1,r6,r9 /* or is new ESID the same as current ESID? */
477 cror eq,4*cr1+eq,eq 477 cror eq,4*cr1+eq,eq
@@ -485,7 +485,7 @@ BEGIN_FTR_SECTION
485 li r9,MMU_SEGSIZE_1T /* insert B field */ 485 li r9,MMU_SEGSIZE_1T /* insert B field */
486 oris r6,r6,(MMU_SEGSIZE_1T << SLBIE_SSIZE_SHIFT)@h 486 oris r6,r6,(MMU_SEGSIZE_1T << SLBIE_SSIZE_SHIFT)@h
487 rldimi r7,r9,SLB_VSID_SSIZE_SHIFT,0 487 rldimi r7,r9,SLB_VSID_SSIZE_SHIFT,0
488END_FTR_SECTION_IFSET(CPU_FTR_1T_SEGMENT) 488END_MMU_FTR_SECTION_IFSET(MMU_FTR_1T_SEGMENT)
489 489
490 /* Update the last bolted SLB. No write barriers are needed 490 /* Update the last bolted SLB. No write barriers are needed
491 * here, provided we only update the current CPU's SLB shadow 491 * here, provided we only update the current CPU's SLB shadow
@@ -497,7 +497,7 @@ END_FTR_SECTION_IFSET(CPU_FTR_1T_SEGMENT)
497 std r7,SLBSHADOW_STACKVSID(r9) /* Save VSID */ 497 std r7,SLBSHADOW_STACKVSID(r9) /* Save VSID */
498 std r0,SLBSHADOW_STACKESID(r9) /* Save ESID */ 498 std r0,SLBSHADOW_STACKESID(r9) /* Save ESID */
499 499
500 /* No need to check for CPU_FTR_NO_SLBIE_B here, since when 500 /* No need to check for MMU_FTR_NO_SLBIE_B here, since when
501 * we have 1TB segments, the only CPUs known to have the errata 501 * we have 1TB segments, the only CPUs known to have the errata
502 * only support less than 1TB of system memory and we'll never 502 * only support less than 1TB of system memory and we'll never
503 * actually hit this code path. 503 * actually hit this code path.
diff --git a/arch/powerpc/kernel/exceptions-64s.S b/arch/powerpc/kernel/exceptions-64s.S
index ad06333631ac..226cc8c62224 100644
--- a/arch/powerpc/kernel/exceptions-64s.S
+++ b/arch/powerpc/kernel/exceptions-64s.S
@@ -102,7 +102,7 @@ BEGIN_FTR_SECTION
102 EXCEPTION_PROLOG_PSERIES_1(data_access_common, EXC_STD) 102 EXCEPTION_PROLOG_PSERIES_1(data_access_common, EXC_STD)
103FTR_SECTION_ELSE 103FTR_SECTION_ELSE
104 EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, data_access_common, EXC_STD) 104 EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, data_access_common, EXC_STD)
105ALT_FTR_SECTION_END_IFCLR(CPU_FTR_SLB) 105ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_SLB)
106 106
107 . = 0x380 107 . = 0x380
108 .globl data_access_slb_pSeries 108 .globl data_access_slb_pSeries
@@ -840,7 +840,7 @@ _STATIC(do_hash_page)
840BEGIN_FTR_SECTION 840BEGIN_FTR_SECTION
841 andis. r0,r4,0x0020 /* Is it a segment table fault? */ 841 andis. r0,r4,0x0020 /* Is it a segment table fault? */
842 bne- do_ste_alloc /* If so handle it */ 842 bne- do_ste_alloc /* If so handle it */
843END_FTR_SECTION_IFCLR(CPU_FTR_SLB) 843END_MMU_FTR_SECTION_IFCLR(MMU_FTR_SLB)
844 844
845 clrrdi r11,r1,THREAD_SHIFT 845 clrrdi r11,r1,THREAD_SHIFT
846 lwz r0,TI_PREEMPT(r11) /* If we're in an "NMI" */ 846 lwz r0,TI_PREEMPT(r11) /* If we're in an "NMI" */
diff --git a/arch/powerpc/kernel/process.c b/arch/powerpc/kernel/process.c
index a01c2d93fd2f..095043d79946 100644
--- a/arch/powerpc/kernel/process.c
+++ b/arch/powerpc/kernel/process.c
@@ -757,11 +757,11 @@ int copy_thread(unsigned long clone_flags, unsigned long usp,
757 _ALIGN_UP(sizeof(struct thread_info), 16); 757 _ALIGN_UP(sizeof(struct thread_info), 16);
758 758
759#ifdef CONFIG_PPC_STD_MMU_64 759#ifdef CONFIG_PPC_STD_MMU_64
760 if (cpu_has_feature(CPU_FTR_SLB)) { 760 if (mmu_has_feature(MMU_FTR_SLB)) {
761 unsigned long sp_vsid; 761 unsigned long sp_vsid;
762 unsigned long llp = mmu_psize_defs[mmu_linear_psize].sllp; 762 unsigned long llp = mmu_psize_defs[mmu_linear_psize].sllp;
763 763
764 if (cpu_has_feature(CPU_FTR_1T_SEGMENT)) 764 if (mmu_has_feature(MMU_FTR_1T_SEGMENT))
765 sp_vsid = get_kernel_vsid(sp, MMU_SEGSIZE_1T) 765 sp_vsid = get_kernel_vsid(sp, MMU_SEGSIZE_1T)
766 << SLB_VSID_SHIFT_1T; 766 << SLB_VSID_SHIFT_1T;
767 else 767 else
diff --git a/arch/powerpc/kernel/prom.c b/arch/powerpc/kernel/prom.c
index c391dc4c8bad..5f5e6aed2b70 100644
--- a/arch/powerpc/kernel/prom.c
+++ b/arch/powerpc/kernel/prom.c
@@ -123,18 +123,19 @@ static void __init move_device_tree(void)
123 */ 123 */
124static struct ibm_pa_feature { 124static struct ibm_pa_feature {
125 unsigned long cpu_features; /* CPU_FTR_xxx bit */ 125 unsigned long cpu_features; /* CPU_FTR_xxx bit */
126 unsigned long mmu_features; /* MMU_FTR_xxx bit */
126 unsigned int cpu_user_ftrs; /* PPC_FEATURE_xxx bit */ 127 unsigned int cpu_user_ftrs; /* PPC_FEATURE_xxx bit */
127 unsigned char pabyte; /* byte number in ibm,pa-features */ 128 unsigned char pabyte; /* byte number in ibm,pa-features */
128 unsigned char pabit; /* bit number (big-endian) */ 129 unsigned char pabit; /* bit number (big-endian) */
129 unsigned char invert; /* if 1, pa bit set => clear feature */ 130 unsigned char invert; /* if 1, pa bit set => clear feature */
130} ibm_pa_features[] __initdata = { 131} ibm_pa_features[] __initdata = {
131 {0, PPC_FEATURE_HAS_MMU, 0, 0, 0}, 132 {0, 0, PPC_FEATURE_HAS_MMU, 0, 0, 0},
132 {0, PPC_FEATURE_HAS_FPU, 0, 1, 0}, 133 {0, 0, PPC_FEATURE_HAS_FPU, 0, 1, 0},
133 {CPU_FTR_SLB, 0, 0, 2, 0}, 134 {0, MMU_FTR_SLB, 0, 0, 2, 0},
134 {CPU_FTR_CTRL, 0, 0, 3, 0}, 135 {CPU_FTR_CTRL, 0, 0, 0, 3, 0},
135 {CPU_FTR_NOEXECUTE, 0, 0, 6, 0}, 136 {CPU_FTR_NOEXECUTE, 0, 0, 0, 6, 0},
136 {CPU_FTR_NODSISRALIGN, 0, 1, 1, 1}, 137 {CPU_FTR_NODSISRALIGN, 0, 0, 1, 1, 1},
137 {CPU_FTR_CI_LARGE_PAGE, 0, 1, 2, 0}, 138 {0, MMU_FTR_CI_LARGE_PAGE, 0, 1, 2, 0},
138 {CPU_FTR_REAL_LE, PPC_FEATURE_TRUE_LE, 5, 0, 0}, 139 {CPU_FTR_REAL_LE, PPC_FEATURE_TRUE_LE, 5, 0, 0},
139}; 140};
140 141
@@ -166,9 +167,11 @@ static void __init scan_features(unsigned long node, unsigned char *ftrs,
166 if (bit ^ fp->invert) { 167 if (bit ^ fp->invert) {
167 cur_cpu_spec->cpu_features |= fp->cpu_features; 168 cur_cpu_spec->cpu_features |= fp->cpu_features;
168 cur_cpu_spec->cpu_user_features |= fp->cpu_user_ftrs; 169 cur_cpu_spec->cpu_user_features |= fp->cpu_user_ftrs;
170 cur_cpu_spec->mmu_features |= fp->mmu_features;
169 } else { 171 } else {
170 cur_cpu_spec->cpu_features &= ~fp->cpu_features; 172 cur_cpu_spec->cpu_features &= ~fp->cpu_features;
171 cur_cpu_spec->cpu_user_features &= ~fp->cpu_user_ftrs; 173 cur_cpu_spec->cpu_user_features &= ~fp->cpu_user_ftrs;
174 cur_cpu_spec->mmu_features &= ~fp->mmu_features;
172 } 175 }
173 } 176 }
174} 177}
diff --git a/arch/powerpc/kernel/setup_64.c b/arch/powerpc/kernel/setup_64.c
index 91a5cc5f0d02..959c63cf62e4 100644
--- a/arch/powerpc/kernel/setup_64.c
+++ b/arch/powerpc/kernel/setup_64.c
@@ -436,7 +436,7 @@ void __init setup_system(void)
436 436
437static u64 slb0_limit(void) 437static u64 slb0_limit(void)
438{ 438{
439 if (cpu_has_feature(CPU_FTR_1T_SEGMENT)) { 439 if (mmu_has_feature(MMU_FTR_1T_SEGMENT)) {
440 return 1UL << SID_SHIFT_1T; 440 return 1UL << SID_SHIFT_1T;
441 } 441 }
442 return 1UL << SID_SHIFT; 442 return 1UL << SID_SHIFT;
diff --git a/arch/powerpc/mm/hash_low_64.S b/arch/powerpc/mm/hash_low_64.S
index 5b7dd4ea02b5..a242b5d7cbe4 100644
--- a/arch/powerpc/mm/hash_low_64.S
+++ b/arch/powerpc/mm/hash_low_64.S
@@ -118,7 +118,7 @@ _GLOBAL(__hash_page_4K)
118BEGIN_FTR_SECTION 118BEGIN_FTR_SECTION
119 cmpdi r9,0 /* check segment size */ 119 cmpdi r9,0 /* check segment size */
120 bne 3f 120 bne 3f
121END_FTR_SECTION_IFSET(CPU_FTR_1T_SEGMENT) 121END_MMU_FTR_SECTION_IFSET(MMU_FTR_1T_SEGMENT)
122 /* Calc va and put it in r29 */ 122 /* Calc va and put it in r29 */
123 rldicr r29,r5,28,63-28 123 rldicr r29,r5,28,63-28
124 rldicl r3,r3,0,36 124 rldicl r3,r3,0,36
@@ -401,7 +401,7 @@ _GLOBAL(__hash_page_4K)
401BEGIN_FTR_SECTION 401BEGIN_FTR_SECTION
402 cmpdi r9,0 /* check segment size */ 402 cmpdi r9,0 /* check segment size */
403 bne 3f 403 bne 3f
404END_FTR_SECTION_IFSET(CPU_FTR_1T_SEGMENT) 404END_MMU_FTR_SECTION_IFSET(MMU_FTR_1T_SEGMENT)
405 /* Calc va and put it in r29 */ 405 /* Calc va and put it in r29 */
406 rldicr r29,r5,28,63-28 /* r29 = (vsid << 28) */ 406 rldicr r29,r5,28,63-28 /* r29 = (vsid << 28) */
407 rldicl r3,r3,0,36 /* r3 = (ea & 0x0fffffff) */ 407 rldicl r3,r3,0,36 /* r3 = (ea & 0x0fffffff) */
@@ -715,7 +715,7 @@ BEGIN_FTR_SECTION
715 andi. r0,r31,_PAGE_NO_CACHE 715 andi. r0,r31,_PAGE_NO_CACHE
716 /* If so, bail out and refault as a 4k page */ 716 /* If so, bail out and refault as a 4k page */
717 bne- ht64_bail_ok 717 bne- ht64_bail_ok
718END_FTR_SECTION_IFCLR(CPU_FTR_CI_LARGE_PAGE) 718END_MMU_FTR_SECTION_IFCLR(MMU_FTR_CI_LARGE_PAGE)
719 /* Prepare new PTE value (turn access RW into DIRTY, then 719 /* Prepare new PTE value (turn access RW into DIRTY, then
720 * add BUSY and ACCESSED) 720 * add BUSY and ACCESSED)
721 */ 721 */
@@ -736,7 +736,7 @@ END_FTR_SECTION_IFCLR(CPU_FTR_CI_LARGE_PAGE)
736BEGIN_FTR_SECTION 736BEGIN_FTR_SECTION
737 cmpdi r9,0 /* check segment size */ 737 cmpdi r9,0 /* check segment size */
738 bne 3f 738 bne 3f
739END_FTR_SECTION_IFSET(CPU_FTR_1T_SEGMENT) 739END_MMU_FTR_SECTION_IFSET(MMU_FTR_1T_SEGMENT)
740 /* Calc va and put it in r29 */ 740 /* Calc va and put it in r29 */
741 rldicr r29,r5,28,63-28 741 rldicr r29,r5,28,63-28
742 rldicl r3,r3,0,36 742 rldicl r3,r3,0,36
diff --git a/arch/powerpc/mm/hash_native_64.c b/arch/powerpc/mm/hash_native_64.c
index 784a400e0781..c23eef2b81a6 100644
--- a/arch/powerpc/mm/hash_native_64.c
+++ b/arch/powerpc/mm/hash_native_64.c
@@ -98,8 +98,8 @@ static inline void __tlbiel(unsigned long va, int psize, int ssize)
98 98
99static inline void tlbie(unsigned long va, int psize, int ssize, int local) 99static inline void tlbie(unsigned long va, int psize, int ssize, int local)
100{ 100{
101 unsigned int use_local = local && cpu_has_feature(CPU_FTR_TLBIEL); 101 unsigned int use_local = local && mmu_has_feature(MMU_FTR_TLBIEL);
102 int lock_tlbie = !cpu_has_feature(CPU_FTR_LOCKLESS_TLBIE); 102 int lock_tlbie = !mmu_has_feature(MMU_FTR_LOCKLESS_TLBIE);
103 103
104 if (use_local) 104 if (use_local)
105 use_local = mmu_psize_defs[psize].tlbiel; 105 use_local = mmu_psize_defs[psize].tlbiel;
@@ -503,7 +503,7 @@ static void native_flush_hash_range(unsigned long number, int local)
503 } pte_iterate_hashed_end(); 503 } pte_iterate_hashed_end();
504 } 504 }
505 505
506 if (cpu_has_feature(CPU_FTR_TLBIEL) && 506 if (mmu_has_feature(MMU_FTR_TLBIEL) &&
507 mmu_psize_defs[psize].tlbiel && local) { 507 mmu_psize_defs[psize].tlbiel && local) {
508 asm volatile("ptesync":::"memory"); 508 asm volatile("ptesync":::"memory");
509 for (i = 0; i < number; i++) { 509 for (i = 0; i < number; i++) {
@@ -517,7 +517,7 @@ static void native_flush_hash_range(unsigned long number, int local)
517 } 517 }
518 asm volatile("ptesync":::"memory"); 518 asm volatile("ptesync":::"memory");
519 } else { 519 } else {
520 int lock_tlbie = !cpu_has_feature(CPU_FTR_LOCKLESS_TLBIE); 520 int lock_tlbie = !mmu_has_feature(MMU_FTR_LOCKLESS_TLBIE);
521 521
522 if (lock_tlbie) 522 if (lock_tlbie)
523 raw_spin_lock(&native_tlbie_lock); 523 raw_spin_lock(&native_tlbie_lock);
diff --git a/arch/powerpc/mm/hash_utils_64.c b/arch/powerpc/mm/hash_utils_64.c
index d95d8f484d2f..26b2872b3d00 100644
--- a/arch/powerpc/mm/hash_utils_64.c
+++ b/arch/powerpc/mm/hash_utils_64.c
@@ -259,11 +259,11 @@ static int __init htab_dt_scan_seg_sizes(unsigned long node,
259 for (; size >= 4; size -= 4, ++prop) { 259 for (; size >= 4; size -= 4, ++prop) {
260 if (prop[0] == 40) { 260 if (prop[0] == 40) {
261 DBG("1T segment support detected\n"); 261 DBG("1T segment support detected\n");
262 cur_cpu_spec->cpu_features |= CPU_FTR_1T_SEGMENT; 262 cur_cpu_spec->mmu_features |= MMU_FTR_1T_SEGMENT;
263 return 1; 263 return 1;
264 } 264 }
265 } 265 }
266 cur_cpu_spec->cpu_features &= ~CPU_FTR_NO_SLBIE_B; 266 cur_cpu_spec->mmu_features &= ~MMU_FTR_NO_SLBIE_B;
267 return 0; 267 return 0;
268} 268}
269 269
@@ -289,7 +289,7 @@ static int __init htab_dt_scan_page_sizes(unsigned long node,
289 if (prop != NULL) { 289 if (prop != NULL) {
290 DBG("Page sizes from device-tree:\n"); 290 DBG("Page sizes from device-tree:\n");
291 size /= 4; 291 size /= 4;
292 cur_cpu_spec->cpu_features &= ~(CPU_FTR_16M_PAGE); 292 cur_cpu_spec->mmu_features &= ~(MMU_FTR_16M_PAGE);
293 while(size > 0) { 293 while(size > 0) {
294 unsigned int shift = prop[0]; 294 unsigned int shift = prop[0];
295 unsigned int slbenc = prop[1]; 295 unsigned int slbenc = prop[1];
@@ -317,7 +317,7 @@ static int __init htab_dt_scan_page_sizes(unsigned long node,
317 break; 317 break;
318 case 0x18: 318 case 0x18:
319 idx = MMU_PAGE_16M; 319 idx = MMU_PAGE_16M;
320 cur_cpu_spec->cpu_features |= CPU_FTR_16M_PAGE; 320 cur_cpu_spec->mmu_features |= MMU_FTR_16M_PAGE;
321 break; 321 break;
322 case 0x22: 322 case 0x22:
323 idx = MMU_PAGE_16G; 323 idx = MMU_PAGE_16G;
@@ -412,7 +412,7 @@ static void __init htab_init_page_sizes(void)
412 * Not in the device-tree, let's fallback on known size 412 * Not in the device-tree, let's fallback on known size
413 * list for 16M capable GP & GR 413 * list for 16M capable GP & GR
414 */ 414 */
415 if (cpu_has_feature(CPU_FTR_16M_PAGE)) 415 if (mmu_has_feature(MMU_FTR_16M_PAGE))
416 memcpy(mmu_psize_defs, mmu_psize_defaults_gp, 416 memcpy(mmu_psize_defs, mmu_psize_defaults_gp,
417 sizeof(mmu_psize_defaults_gp)); 417 sizeof(mmu_psize_defaults_gp));
418 found: 418 found:
@@ -442,7 +442,7 @@ static void __init htab_init_page_sizes(void)
442 mmu_vmalloc_psize = MMU_PAGE_64K; 442 mmu_vmalloc_psize = MMU_PAGE_64K;
443 if (mmu_linear_psize == MMU_PAGE_4K) 443 if (mmu_linear_psize == MMU_PAGE_4K)
444 mmu_linear_psize = MMU_PAGE_64K; 444 mmu_linear_psize = MMU_PAGE_64K;
445 if (cpu_has_feature(CPU_FTR_CI_LARGE_PAGE)) { 445 if (mmu_has_feature(MMU_FTR_CI_LARGE_PAGE)) {
446 /* 446 /*
447 * Don't use 64k pages for ioremap on pSeries, since 447 * Don't use 64k pages for ioremap on pSeries, since
448 * that would stop us accessing the HEA ethernet. 448 * that would stop us accessing the HEA ethernet.
@@ -608,7 +608,7 @@ static void __init htab_initialize(void)
608 /* Initialize page sizes */ 608 /* Initialize page sizes */
609 htab_init_page_sizes(); 609 htab_init_page_sizes();
610 610
611 if (cpu_has_feature(CPU_FTR_1T_SEGMENT)) { 611 if (mmu_has_feature(MMU_FTR_1T_SEGMENT)) {
612 mmu_kernel_ssize = MMU_SEGSIZE_1T; 612 mmu_kernel_ssize = MMU_SEGSIZE_1T;
613 mmu_highuser_ssize = MMU_SEGSIZE_1T; 613 mmu_highuser_ssize = MMU_SEGSIZE_1T;
614 printk(KERN_INFO "Using 1TB segments\n"); 614 printk(KERN_INFO "Using 1TB segments\n");
@@ -749,7 +749,7 @@ void __init early_init_mmu(void)
749 749
750 /* Initialize stab / SLB management except on iSeries 750 /* Initialize stab / SLB management except on iSeries
751 */ 751 */
752 if (cpu_has_feature(CPU_FTR_SLB)) 752 if (mmu_has_feature(MMU_FTR_SLB))
753 slb_initialize(); 753 slb_initialize();
754 else if (!firmware_has_feature(FW_FEATURE_ISERIES)) 754 else if (!firmware_has_feature(FW_FEATURE_ISERIES))
755 stab_initialize(get_paca()->stab_real); 755 stab_initialize(get_paca()->stab_real);
@@ -766,7 +766,7 @@ void __cpuinit early_init_mmu_secondary(void)
766 * in real mode on pSeries and we want a virtual address on 766 * in real mode on pSeries and we want a virtual address on
767 * iSeries anyway 767 * iSeries anyway
768 */ 768 */
769 if (cpu_has_feature(CPU_FTR_SLB)) 769 if (mmu_has_feature(MMU_FTR_SLB))
770 slb_initialize(); 770 slb_initialize();
771 else 771 else
772 stab_initialize(get_paca()->stab_addr); 772 stab_initialize(get_paca()->stab_addr);
diff --git a/arch/powerpc/mm/hugetlbpage.c b/arch/powerpc/mm/hugetlbpage.c
index 9bb249c3046e..0b9a5c1901b9 100644
--- a/arch/powerpc/mm/hugetlbpage.c
+++ b/arch/powerpc/mm/hugetlbpage.c
@@ -529,7 +529,7 @@ static int __init hugetlbpage_init(void)
529{ 529{
530 int psize; 530 int psize;
531 531
532 if (!cpu_has_feature(CPU_FTR_16M_PAGE)) 532 if (!mmu_has_feature(MMU_FTR_16M_PAGE))
533 return -ENODEV; 533 return -ENODEV;
534 534
535 for (psize = 0; psize < MMU_PAGE_COUNT; ++psize) { 535 for (psize = 0; psize < MMU_PAGE_COUNT; ++psize) {
diff --git a/arch/powerpc/mm/slb.c b/arch/powerpc/mm/slb.c
index 5500712781d4..e22276cb67a4 100644
--- a/arch/powerpc/mm/slb.c
+++ b/arch/powerpc/mm/slb.c
@@ -167,7 +167,7 @@ static inline int esids_match(unsigned long addr1, unsigned long addr2)
167 int esid_1t_count; 167 int esid_1t_count;
168 168
169 /* System is not 1T segment size capable. */ 169 /* System is not 1T segment size capable. */
170 if (!cpu_has_feature(CPU_FTR_1T_SEGMENT)) 170 if (!mmu_has_feature(MMU_FTR_1T_SEGMENT))
171 return (GET_ESID(addr1) == GET_ESID(addr2)); 171 return (GET_ESID(addr1) == GET_ESID(addr2));
172 172
173 esid_1t_count = (((addr1 >> SID_SHIFT_1T) != 0) + 173 esid_1t_count = (((addr1 >> SID_SHIFT_1T) != 0) +
@@ -202,7 +202,7 @@ void switch_slb(struct task_struct *tsk, struct mm_struct *mm)
202 */ 202 */
203 hard_irq_disable(); 203 hard_irq_disable();
204 offset = get_paca()->slb_cache_ptr; 204 offset = get_paca()->slb_cache_ptr;
205 if (!cpu_has_feature(CPU_FTR_NO_SLBIE_B) && 205 if (!mmu_has_feature(MMU_FTR_NO_SLBIE_B) &&
206 offset <= SLB_CACHE_ENTRIES) { 206 offset <= SLB_CACHE_ENTRIES) {
207 int i; 207 int i;
208 asm volatile("isync" : : : "memory"); 208 asm volatile("isync" : : : "memory");
diff --git a/arch/powerpc/mm/slb_low.S b/arch/powerpc/mm/slb_low.S
index 95ce35581696..ef653dc95b65 100644
--- a/arch/powerpc/mm/slb_low.S
+++ b/arch/powerpc/mm/slb_low.S
@@ -58,7 +58,7 @@ _GLOBAL(slb_miss_kernel_load_linear)
58 li r11,0 58 li r11,0
59BEGIN_FTR_SECTION 59BEGIN_FTR_SECTION
60 b slb_finish_load 60 b slb_finish_load
61END_FTR_SECTION_IFCLR(CPU_FTR_1T_SEGMENT) 61END_MMU_FTR_SECTION_IFCLR(MMU_FTR_1T_SEGMENT)
62 b slb_finish_load_1T 62 b slb_finish_load_1T
63 63
641: 641:
@@ -87,7 +87,7 @@ _GLOBAL(slb_miss_kernel_load_vmemmap)
876: 876:
88BEGIN_FTR_SECTION 88BEGIN_FTR_SECTION
89 b slb_finish_load 89 b slb_finish_load
90END_FTR_SECTION_IFCLR(CPU_FTR_1T_SEGMENT) 90END_MMU_FTR_SECTION_IFCLR(MMU_FTR_1T_SEGMENT)
91 b slb_finish_load_1T 91 b slb_finish_load_1T
92 92
930: /* user address: proto-VSID = context << 15 | ESID. First check 930: /* user address: proto-VSID = context << 15 | ESID. First check
@@ -138,11 +138,11 @@ END_FTR_SECTION_IFCLR(CPU_FTR_1T_SEGMENT)
138 ld r9,PACACONTEXTID(r13) 138 ld r9,PACACONTEXTID(r13)
139BEGIN_FTR_SECTION 139BEGIN_FTR_SECTION
140 cmpldi r10,0x1000 140 cmpldi r10,0x1000
141END_FTR_SECTION_IFSET(CPU_FTR_1T_SEGMENT) 141END_MMU_FTR_SECTION_IFSET(MMU_FTR_1T_SEGMENT)
142 rldimi r10,r9,USER_ESID_BITS,0 142 rldimi r10,r9,USER_ESID_BITS,0
143BEGIN_FTR_SECTION 143BEGIN_FTR_SECTION
144 bge slb_finish_load_1T 144 bge slb_finish_load_1T
145END_FTR_SECTION_IFSET(CPU_FTR_1T_SEGMENT) 145END_MMU_FTR_SECTION_IFSET(MMU_FTR_1T_SEGMENT)
146 b slb_finish_load 146 b slb_finish_load
147 147
1488: /* invalid EA */ 1488: /* invalid EA */
diff --git a/arch/powerpc/mm/stab.c b/arch/powerpc/mm/stab.c
index 446a01842a73..41e31642a86a 100644
--- a/arch/powerpc/mm/stab.c
+++ b/arch/powerpc/mm/stab.c
@@ -243,7 +243,7 @@ void __init stabs_alloc(void)
243{ 243{
244 int cpu; 244 int cpu;
245 245
246 if (cpu_has_feature(CPU_FTR_SLB)) 246 if (mmu_has_feature(MMU_FTR_SLB))
247 return; 247 return;
248 248
249 for_each_possible_cpu(cpu) { 249 for_each_possible_cpu(cpu) {
diff --git a/arch/powerpc/platforms/iseries/exception.S b/arch/powerpc/platforms/iseries/exception.S
index 32a56c6dfa72..a67984c04954 100644
--- a/arch/powerpc/platforms/iseries/exception.S
+++ b/arch/powerpc/platforms/iseries/exception.S
@@ -31,6 +31,7 @@
31#include <asm/thread_info.h> 31#include <asm/thread_info.h>
32#include <asm/ptrace.h> 32#include <asm/ptrace.h>
33#include <asm/cputable.h> 33#include <asm/cputable.h>
34#include <asm/mmu.h>
34 35
35#include "exception.h" 36#include "exception.h"
36 37
@@ -157,7 +158,7 @@ BEGIN_FTR_SECTION
157FTR_SECTION_ELSE 158FTR_SECTION_ELSE
158 EXCEPTION_PROLOG_1(PACA_EXGEN) 159 EXCEPTION_PROLOG_1(PACA_EXGEN)
159 EXCEPTION_PROLOG_ISERIES_1 160 EXCEPTION_PROLOG_ISERIES_1
160ALT_FTR_SECTION_END_IFCLR(CPU_FTR_SLB) 161ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_SLB)
161 b data_access_common 162 b data_access_common
162 163
163.do_stab_bolted_iSeries: 164.do_stab_bolted_iSeries:
diff --git a/arch/powerpc/platforms/iseries/setup.c b/arch/powerpc/platforms/iseries/setup.c
index 2946ae10fbfd..81cb8d2c4132 100644
--- a/arch/powerpc/platforms/iseries/setup.c
+++ b/arch/powerpc/platforms/iseries/setup.c
@@ -249,7 +249,7 @@ static unsigned long iSeries_process_mainstore_vpd(struct MemoryBlock *mb_array,
249 unsigned long i; 249 unsigned long i;
250 unsigned long mem_blocks = 0; 250 unsigned long mem_blocks = 0;
251 251
252 if (cpu_has_feature(CPU_FTR_SLB)) 252 if (mmu_has_feature(MMU_FTR_SLB))
253 mem_blocks = iSeries_process_Regatta_mainstore_vpd(mb_array, 253 mem_blocks = iSeries_process_Regatta_mainstore_vpd(mb_array,
254 max_entries); 254 max_entries);
255 else 255 else
@@ -634,7 +634,7 @@ static int __init iseries_probe(void)
634 634
635 hpte_init_iSeries(); 635 hpte_init_iSeries();
636 /* iSeries does not support 16M pages */ 636 /* iSeries does not support 16M pages */
637 cur_cpu_spec->cpu_features &= ~CPU_FTR_16M_PAGE; 637 cur_cpu_spec->mmu_features &= ~MMU_FTR_16M_PAGE;
638 638
639 return 1; 639 return 1;
640} 640}
diff --git a/arch/powerpc/platforms/pseries/lpar.c b/arch/powerpc/platforms/pseries/lpar.c
index ca5d5898d320..6f0ed3aac77f 100644
--- a/arch/powerpc/platforms/pseries/lpar.c
+++ b/arch/powerpc/platforms/pseries/lpar.c
@@ -573,7 +573,7 @@ static void pSeries_lpar_flush_hash_range(unsigned long number, int local)
573 unsigned long i, pix, rc; 573 unsigned long i, pix, rc;
574 unsigned long flags = 0; 574 unsigned long flags = 0;
575 struct ppc64_tlb_batch *batch = &__get_cpu_var(ppc64_tlb_batch); 575 struct ppc64_tlb_batch *batch = &__get_cpu_var(ppc64_tlb_batch);
576 int lock_tlbie = !cpu_has_feature(CPU_FTR_LOCKLESS_TLBIE); 576 int lock_tlbie = !mmu_has_feature(MMU_FTR_LOCKLESS_TLBIE);
577 unsigned long param[9]; 577 unsigned long param[9];
578 unsigned long va; 578 unsigned long va;
579 unsigned long hash, index, shift, hidx, slot; 579 unsigned long hash, index, shift, hidx, slot;
diff --git a/arch/powerpc/xmon/xmon.c b/arch/powerpc/xmon/xmon.c
index ef9756ee284e..60593ad861e8 100644
--- a/arch/powerpc/xmon/xmon.c
+++ b/arch/powerpc/xmon/xmon.c
@@ -2663,7 +2663,7 @@ static void dump_stab(void)
2663 2663
2664void dump_segments(void) 2664void dump_segments(void)
2665{ 2665{
2666 if (cpu_has_feature(CPU_FTR_SLB)) 2666 if (mmu_has_feature(MMU_FTR_SLB))
2667 dump_slb(); 2667 dump_slb();
2668 else 2668 else
2669 dump_stab(); 2669 dump_stab();
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-11 00:54:26 -0500