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authorSascha Hauer <s.hauer@pengutronix.de>2012-09-18 04:05:31 -0400
committerSascha Hauer <s.hauer@pengutronix.de>2012-09-18 10:46:50 -0400
commit42a3f891caee0d9baa60a6964e41a28b9c657407 (patch)
treea1f3863aeee88b10556c4b609a8a5e9324841959 /arch
parent35495173e1df621dff0e9a244accbe32cd28a98f (diff)
ARM i.MX25: Make timer irq work again
Since i.MX has SPARSE_IRQ enabled the i.MX25 timer is broken. This is because the internal irqs now start at an offset of NR_IRQS_LEGACY. The patch fixed this up, but missed the i.MX25 timer which used a hardcoded value instead of a define. This patch introduces a define for the timer irq and uses it. This is broken since introduced with 3.6-rc1: | commit 8842a9e2869cae14bbb8184004a42fc3070587fb | Author: Shawn Guo <shawn.guo@linaro.org> | Date: Thu Jun 14 11:16:14 2012 +0800 | | ARM: imx: enable SPARSE_IRQ for imx platform Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Acked-by: Shawn Guo <shawn.guo@linaro.org>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/mach-imx/clk-imx25.c2
-rw-r--r--arch/arm/plat-mxc/include/mach/mx25.h1
2 files changed, 2 insertions, 1 deletions
diff --git a/arch/arm/mach-imx/clk-imx25.c b/arch/arm/mach-imx/clk-imx25.c
index 4431a62fff5b..d20d4795f4ea 100644
--- a/arch/arm/mach-imx/clk-imx25.c
+++ b/arch/arm/mach-imx/clk-imx25.c
@@ -241,6 +241,6 @@ int __init mx25_clocks_init(void)
241 clk_register_clkdev(clk[sdma_ahb], "ahb", "imx35-sdma"); 241 clk_register_clkdev(clk[sdma_ahb], "ahb", "imx35-sdma");
242 clk_register_clkdev(clk[iim_ipg], "iim", NULL); 242 clk_register_clkdev(clk[iim_ipg], "iim", NULL);
243 243
244 mxc_timer_init(MX25_IO_ADDRESS(MX25_GPT1_BASE_ADDR), 54); 244 mxc_timer_init(MX25_IO_ADDRESS(MX25_GPT1_BASE_ADDR), MX25_INT_GPT1);
245 return 0; 245 return 0;
246} 246}
diff --git a/arch/arm/plat-mxc/include/mach/mx25.h b/arch/arm/plat-mxc/include/mach/mx25.h
index 627d94f1b010..ec466400a200 100644
--- a/arch/arm/plat-mxc/include/mach/mx25.h
+++ b/arch/arm/plat-mxc/include/mach/mx25.h
@@ -98,6 +98,7 @@
98#define MX25_INT_UART1 (NR_IRQS_LEGACY + 45) 98#define MX25_INT_UART1 (NR_IRQS_LEGACY + 45)
99#define MX25_INT_GPIO2 (NR_IRQS_LEGACY + 51) 99#define MX25_INT_GPIO2 (NR_IRQS_LEGACY + 51)
100#define MX25_INT_GPIO1 (NR_IRQS_LEGACY + 52) 100#define MX25_INT_GPIO1 (NR_IRQS_LEGACY + 52)
101#define MX25_INT_GPT1 (NR_IRQS_LEGACY + 54)
101#define MX25_INT_FEC (NR_IRQS_LEGACY + 57) 102#define MX25_INT_FEC (NR_IRQS_LEGACY + 57)
102 103
103#define MX25_DMA_REQ_SSI2_RX1 22 104#define MX25_DMA_REQ_SSI2_RX1 22