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authorRalf Baechle <ralf@linux-mips.org>2007-10-14 19:51:34 -0400
committerRalf Baechle <ralf@linux-mips.org>2007-10-16 13:23:48 -0400
commit41bd61a8e357f79dc65502b22d9d124a619491c0 (patch)
treef52911289c54eb2bff2cdd3fc126e2aca78b0906 /arch
parenta5ccfe5c1a48bff1e47788d470ee50974f7dd33d (diff)
[MIPS] Alchemy: cleanup interrupt code.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch')
-rw-r--r--arch/mips/au1000/common/irq.c654
1 files changed, 313 insertions, 341 deletions
diff --git a/arch/mips/au1000/common/irq.c b/arch/mips/au1000/common/irq.c
index a6640b998c6e..e86b4303994f 100644
--- a/arch/mips/au1000/common/irq.c
+++ b/arch/mips/au1000/common/irq.c
@@ -26,39 +26,18 @@
26 * with this program; if not, write to the Free Software Foundation, Inc., 26 * with this program; if not, write to the Free Software Foundation, Inc.,
27 * 675 Mass Ave, Cambridge, MA 02139, USA. 27 * 675 Mass Ave, Cambridge, MA 02139, USA.
28 */ 28 */
29#include <linux/errno.h> 29#include <linux/bitops.h>
30#include <linux/init.h> 30#include <linux/init.h>
31#include <linux/irq.h> 31#include <linux/io.h>
32#include <linux/kernel_stat.h>
33#include <linux/module.h>
34#include <linux/signal.h>
35#include <linux/sched.h>
36#include <linux/types.h>
37#include <linux/interrupt.h> 32#include <linux/interrupt.h>
38#include <linux/ioport.h> 33#include <linux/irq.h>
39#include <linux/timex.h>
40#include <linux/slab.h>
41#include <linux/random.h>
42#include <linux/delay.h>
43#include <linux/bitops.h>
44 34
45#include <asm/bootinfo.h>
46#include <asm/io.h>
47#include <asm/mipsregs.h> 35#include <asm/mipsregs.h>
48#include <asm/system.h>
49#include <asm/mach-au1x00/au1000.h> 36#include <asm/mach-au1x00/au1000.h>
50#ifdef CONFIG_MIPS_PB1000 37#ifdef CONFIG_MIPS_PB1000
51#include <asm/mach-pb1x00/pb1000.h> 38#include <asm/mach-pb1x00/pb1000.h>
52#endif 39#endif
53 40
54#undef DEBUG_IRQ
55#ifdef DEBUG_IRQ
56/* note: prints function name for you */
57#define DPRINTK(fmt, args...) printk("%s: " fmt, __FUNCTION__ , ## args)
58#else
59#define DPRINTK(fmt, args...)
60#endif
61
62#define EXT_INTC0_REQ0 2 /* IP 2 */ 41#define EXT_INTC0_REQ0 2 /* IP 2 */
63#define EXT_INTC0_REQ1 3 /* IP 3 */ 42#define EXT_INTC0_REQ1 3 /* IP 3 */
64#define EXT_INTC1_REQ0 4 /* IP 4 */ 43#define EXT_INTC1_REQ0 4 /* IP 4 */
@@ -69,16 +48,98 @@ void (*board_init_irq)(void);
69 48
70static DEFINE_SPINLOCK(irq_lock); 49static DEFINE_SPINLOCK(irq_lock);
71 50
51#ifdef CONFIG_PM
52
53/*
54 * Save/restore the interrupt controller state.
55 * Called from the save/restore core registers as part of the
56 * au_sleep function in power.c.....maybe I should just pm_register()
57 * them instead?
58 */
59static unsigned int sleep_intctl_config0[2];
60static unsigned int sleep_intctl_config1[2];
61static unsigned int sleep_intctl_config2[2];
62static unsigned int sleep_intctl_src[2];
63static unsigned int sleep_intctl_assign[2];
64static unsigned int sleep_intctl_wake[2];
65static unsigned int sleep_intctl_mask[2];
66
67void save_au1xxx_intctl(void)
68{
69 sleep_intctl_config0[0] = au_readl(IC0_CFG0RD);
70 sleep_intctl_config1[0] = au_readl(IC0_CFG1RD);
71 sleep_intctl_config2[0] = au_readl(IC0_CFG2RD);
72 sleep_intctl_src[0] = au_readl(IC0_SRCRD);
73 sleep_intctl_assign[0] = au_readl(IC0_ASSIGNRD);
74 sleep_intctl_wake[0] = au_readl(IC0_WAKERD);
75 sleep_intctl_mask[0] = au_readl(IC0_MASKRD);
76
77 sleep_intctl_config0[1] = au_readl(IC1_CFG0RD);
78 sleep_intctl_config1[1] = au_readl(IC1_CFG1RD);
79 sleep_intctl_config2[1] = au_readl(IC1_CFG2RD);
80 sleep_intctl_src[1] = au_readl(IC1_SRCRD);
81 sleep_intctl_assign[1] = au_readl(IC1_ASSIGNRD);
82 sleep_intctl_wake[1] = au_readl(IC1_WAKERD);
83 sleep_intctl_mask[1] = au_readl(IC1_MASKRD);
84}
85
86/*
87 * For most restore operations, we clear the entire register and
88 * then set the bits we found during the save.
89 */
90void restore_au1xxx_intctl(void)
91{
92 au_writel(0xffffffff, IC0_MASKCLR); au_sync();
93
94 au_writel(0xffffffff, IC0_CFG0CLR); au_sync();
95 au_writel(sleep_intctl_config0[0], IC0_CFG0SET); au_sync();
96 au_writel(0xffffffff, IC0_CFG1CLR); au_sync();
97 au_writel(sleep_intctl_config1[0], IC0_CFG1SET); au_sync();
98 au_writel(0xffffffff, IC0_CFG2CLR); au_sync();
99 au_writel(sleep_intctl_config2[0], IC0_CFG2SET); au_sync();
100 au_writel(0xffffffff, IC0_SRCCLR); au_sync();
101 au_writel(sleep_intctl_src[0], IC0_SRCSET); au_sync();
102 au_writel(0xffffffff, IC0_ASSIGNCLR); au_sync();
103 au_writel(sleep_intctl_assign[0], IC0_ASSIGNSET); au_sync();
104 au_writel(0xffffffff, IC0_WAKECLR); au_sync();
105 au_writel(sleep_intctl_wake[0], IC0_WAKESET); au_sync();
106 au_writel(0xffffffff, IC0_RISINGCLR); au_sync();
107 au_writel(0xffffffff, IC0_FALLINGCLR); au_sync();
108 au_writel(0x00000000, IC0_TESTBIT); au_sync();
109
110 au_writel(0xffffffff, IC1_MASKCLR); au_sync();
111
112 au_writel(0xffffffff, IC1_CFG0CLR); au_sync();
113 au_writel(sleep_intctl_config0[1], IC1_CFG0SET); au_sync();
114 au_writel(0xffffffff, IC1_CFG1CLR); au_sync();
115 au_writel(sleep_intctl_config1[1], IC1_CFG1SET); au_sync();
116 au_writel(0xffffffff, IC1_CFG2CLR); au_sync();
117 au_writel(sleep_intctl_config2[1], IC1_CFG2SET); au_sync();
118 au_writel(0xffffffff, IC1_SRCCLR); au_sync();
119 au_writel(sleep_intctl_src[1], IC1_SRCSET); au_sync();
120 au_writel(0xffffffff, IC1_ASSIGNCLR); au_sync();
121 au_writel(sleep_intctl_assign[1], IC1_ASSIGNSET); au_sync();
122 au_writel(0xffffffff, IC1_WAKECLR); au_sync();
123 au_writel(sleep_intctl_wake[1], IC1_WAKESET); au_sync();
124 au_writel(0xffffffff, IC1_RISINGCLR); au_sync();
125 au_writel(0xffffffff, IC1_FALLINGCLR); au_sync();
126 au_writel(0x00000000, IC1_TESTBIT); au_sync();
127
128 au_writel(sleep_intctl_mask[1], IC1_MASKSET); au_sync();
129
130 au_writel(sleep_intctl_mask[0], IC0_MASKSET); au_sync();
131}
132#endif /* CONFIG_PM */
133
72 134
73inline void local_enable_irq(unsigned int irq_nr) 135inline void local_enable_irq(unsigned int irq_nr)
74{ 136{
75 if (irq_nr > AU1000_LAST_INTC0_INT) { 137 if (irq_nr > AU1000_LAST_INTC0_INT) {
76 au_writel(1<<(irq_nr-32), IC1_MASKSET); 138 au_writel(1 << (irq_nr - 32), IC1_MASKSET);
77 au_writel(1<<(irq_nr-32), IC1_WAKESET); 139 au_writel(1 << (irq_nr - 32), IC1_WAKESET);
78 } 140 } else {
79 else { 141 au_writel(1 << irq_nr, IC0_MASKSET);
80 au_writel(1<<irq_nr, IC0_MASKSET); 142 au_writel(1 << irq_nr, IC0_WAKESET);
81 au_writel(1<<irq_nr, IC0_WAKESET);
82 } 143 }
83 au_sync(); 144 au_sync();
84} 145}
@@ -87,12 +148,11 @@ inline void local_enable_irq(unsigned int irq_nr)
87inline void local_disable_irq(unsigned int irq_nr) 148inline void local_disable_irq(unsigned int irq_nr)
88{ 149{
89 if (irq_nr > AU1000_LAST_INTC0_INT) { 150 if (irq_nr > AU1000_LAST_INTC0_INT) {
90 au_writel(1<<(irq_nr-32), IC1_MASKCLR); 151 au_writel(1 << (irq_nr - 32), IC1_MASKCLR);
91 au_writel(1<<(irq_nr-32), IC1_WAKECLR); 152 au_writel(1 << (irq_nr - 32), IC1_WAKECLR);
92 } 153 } else {
93 else { 154 au_writel(1 << irq_nr, IC0_MASKCLR);
94 au_writel(1<<irq_nr, IC0_MASKCLR); 155 au_writel(1 << irq_nr, IC0_WAKECLR);
95 au_writel(1<<irq_nr, IC0_WAKECLR);
96 } 156 }
97 au_sync(); 157 au_sync();
98} 158}
@@ -101,12 +161,11 @@ inline void local_disable_irq(unsigned int irq_nr)
101static inline void mask_and_ack_rise_edge_irq(unsigned int irq_nr) 161static inline void mask_and_ack_rise_edge_irq(unsigned int irq_nr)
102{ 162{
103 if (irq_nr > AU1000_LAST_INTC0_INT) { 163 if (irq_nr > AU1000_LAST_INTC0_INT) {
104 au_writel(1<<(irq_nr-32), IC1_RISINGCLR); 164 au_writel(1 << (irq_nr - 32), IC1_RISINGCLR);
105 au_writel(1<<(irq_nr-32), IC1_MASKCLR); 165 au_writel(1 << (irq_nr - 32), IC1_MASKCLR);
106 } 166 } else {
107 else { 167 au_writel(1 << irq_nr, IC0_RISINGCLR);
108 au_writel(1<<irq_nr, IC0_RISINGCLR); 168 au_writel(1 << irq_nr, IC0_MASKCLR);
109 au_writel(1<<irq_nr, IC0_MASKCLR);
110 } 169 }
111 au_sync(); 170 au_sync();
112} 171}
@@ -115,12 +174,11 @@ static inline void mask_and_ack_rise_edge_irq(unsigned int irq_nr)
115static inline void mask_and_ack_fall_edge_irq(unsigned int irq_nr) 174static inline void mask_and_ack_fall_edge_irq(unsigned int irq_nr)
116{ 175{
117 if (irq_nr > AU1000_LAST_INTC0_INT) { 176 if (irq_nr > AU1000_LAST_INTC0_INT) {
118 au_writel(1<<(irq_nr-32), IC1_FALLINGCLR); 177 au_writel(1 << (irq_nr - 32), IC1_FALLINGCLR);
119 au_writel(1<<(irq_nr-32), IC1_MASKCLR); 178 au_writel(1 << (irq_nr - 32), IC1_MASKCLR);
120 } 179 } else {
121 else { 180 au_writel(1 << irq_nr, IC0_FALLINGCLR);
122 au_writel(1<<irq_nr, IC0_FALLINGCLR); 181 au_writel(1 << irq_nr, IC0_MASKCLR);
123 au_writel(1<<irq_nr, IC0_MASKCLR);
124 } 182 }
125 au_sync(); 183 au_sync();
126} 184}
@@ -132,14 +190,13 @@ static inline void mask_and_ack_either_edge_irq(unsigned int irq_nr)
132 * both edges at once, or if we do, that we don't care. 190 * both edges at once, or if we do, that we don't care.
133 */ 191 */
134 if (irq_nr > AU1000_LAST_INTC0_INT) { 192 if (irq_nr > AU1000_LAST_INTC0_INT) {
135 au_writel(1<<(irq_nr-32), IC1_FALLINGCLR); 193 au_writel(1 << (irq_nr - 32), IC1_FALLINGCLR);
136 au_writel(1<<(irq_nr-32), IC1_RISINGCLR); 194 au_writel(1 << (irq_nr - 32), IC1_RISINGCLR);
137 au_writel(1<<(irq_nr-32), IC1_MASKCLR); 195 au_writel(1 << (irq_nr - 32), IC1_MASKCLR);
138 } 196 } else {
139 else { 197 au_writel(1 << irq_nr, IC0_FALLINGCLR);
140 au_writel(1<<irq_nr, IC0_FALLINGCLR); 198 au_writel(1 << irq_nr, IC0_RISINGCLR);
141 au_writel(1<<irq_nr, IC0_RISINGCLR); 199 au_writel(1 << irq_nr, IC0_MASKCLR);
142 au_writel(1<<irq_nr, IC0_MASKCLR);
143 } 200 }
144 au_sync(); 201 au_sync();
145} 202}
@@ -162,9 +219,9 @@ static inline void mask_and_ack_level_irq(unsigned int irq_nr)
162 219
163static void end_irq(unsigned int irq_nr) 220static void end_irq(unsigned int irq_nr)
164{ 221{
165 if (!(irq_desc[irq_nr].status & (IRQ_DISABLED|IRQ_INPROGRESS))) { 222 if (!(irq_desc[irq_nr].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
166 local_enable_irq(irq_nr); 223 local_enable_irq(irq_nr);
167 } 224
168#if defined(CONFIG_MIPS_PB1000) 225#if defined(CONFIG_MIPS_PB1000)
169 if (irq_nr == AU1000_GPIO_15) { 226 if (irq_nr == AU1000_GPIO_15) {
170 au_writel(0x4000, PB1000_MDR); /* enable int */ 227 au_writel(0x4000, PB1000_MDR); /* enable int */
@@ -181,15 +238,12 @@ unsigned long save_local_and_disable(int controller)
181 spin_lock_irqsave(&irq_lock, flags); 238 spin_lock_irqsave(&irq_lock, flags);
182 if (controller) { 239 if (controller) {
183 mask = au_readl(IC1_MASKSET); 240 mask = au_readl(IC1_MASKSET);
184 for (i=32; i<64; i++) { 241 for (i = 32; i < 64; i++)
185 local_disable_irq(i); 242 local_disable_irq(i);
186 } 243 } else {
187 }
188 else {
189 mask = au_readl(IC0_MASKSET); 244 mask = au_readl(IC0_MASKSET);
190 for (i=0; i<32; i++) { 245 for (i = 0; i < 32; i++)
191 local_disable_irq(i); 246 local_disable_irq(i);
192 }
193 } 247 }
194 spin_unlock_irqrestore(&irq_lock, flags); 248 spin_unlock_irqrestore(&irq_lock, flags);
195 249
@@ -202,10 +256,10 @@ void restore_local_and_enable(int controller, unsigned long mask)
202 unsigned long flags, new_mask; 256 unsigned long flags, new_mask;
203 257
204 spin_lock_irqsave(&irq_lock, flags); 258 spin_lock_irqsave(&irq_lock, flags);
205 for (i=0; i<32; i++) { 259 for (i = 0; i < 32; i++) {
206 if (mask & (1<<i)) { 260 if (mask & (1 << i)) {
207 if (controller) 261 if (controller)
208 local_enable_irq(i+32); 262 local_enable_irq(i + 32);
209 else 263 else
210 local_enable_irq(i); 264 local_enable_irq(i);
211 } 265 }
@@ -220,39 +274,39 @@ void restore_local_and_enable(int controller, unsigned long mask)
220 274
221 275
222static struct irq_chip rise_edge_irq_type = { 276static struct irq_chip rise_edge_irq_type = {
223 .name = "Au1000 Rise Edge", 277 .name = "Au1000 Rise Edge",
224 .ack = mask_and_ack_rise_edge_irq, 278 .ack = mask_and_ack_rise_edge_irq,
225 .mask = local_disable_irq, 279 .mask = local_disable_irq,
226 .mask_ack = mask_and_ack_rise_edge_irq, 280 .mask_ack = mask_and_ack_rise_edge_irq,
227 .unmask = local_enable_irq, 281 .unmask = local_enable_irq,
228 .end = end_irq, 282 .end = end_irq,
229}; 283};
230 284
231static struct irq_chip fall_edge_irq_type = { 285static struct irq_chip fall_edge_irq_type = {
232 .name = "Au1000 Fall Edge", 286 .name = "Au1000 Fall Edge",
233 .ack = mask_and_ack_fall_edge_irq, 287 .ack = mask_and_ack_fall_edge_irq,
234 .mask = local_disable_irq, 288 .mask = local_disable_irq,
235 .mask_ack = mask_and_ack_fall_edge_irq, 289 .mask_ack = mask_and_ack_fall_edge_irq,
236 .unmask = local_enable_irq, 290 .unmask = local_enable_irq,
237 .end = end_irq, 291 .end = end_irq,
238}; 292};
239 293
240static struct irq_chip either_edge_irq_type = { 294static struct irq_chip either_edge_irq_type = {
241 .name = "Au1000 Rise or Fall Edge", 295 .name = "Au1000 Rise or Fall Edge",
242 .ack = mask_and_ack_either_edge_irq, 296 .ack = mask_and_ack_either_edge_irq,
243 .mask = local_disable_irq, 297 .mask = local_disable_irq,
244 .mask_ack = mask_and_ack_either_edge_irq, 298 .mask_ack = mask_and_ack_either_edge_irq,
245 .unmask = local_enable_irq, 299 .unmask = local_enable_irq,
246 .end = end_irq, 300 .end = end_irq,
247}; 301};
248 302
249static struct irq_chip level_irq_type = { 303static struct irq_chip level_irq_type = {
250 .name = "Au1000 Level", 304 .name = "Au1000 Level",
251 .ack = mask_and_ack_level_irq, 305 .ack = mask_and_ack_level_irq,
252 .mask = local_disable_irq, 306 .mask = local_disable_irq,
253 .mask_ack = mask_and_ack_level_irq, 307 .mask_ack = mask_and_ack_level_irq,
254 .unmask = local_enable_irq, 308 .unmask = local_enable_irq,
255 .end = end_irq, 309 .end = end_irq,
256}; 310};
257 311
258#ifdef CONFIG_PM 312#ifdef CONFIG_PM
@@ -263,7 +317,8 @@ void startup_match20_interrupt(irq_handler_t handler)
263 static struct irqaction action; 317 static struct irqaction action;
264 memset(&action, 0, sizeof(struct irqaction)); 318 memset(&action, 0, sizeof(struct irqaction));
265 319
266 /* This is a big problem.... since we didn't use request_irq 320 /*
321 * This is a big problem.... since we didn't use request_irq
267 * when kernel/irq.c calls probe_irq_xxx this interrupt will 322 * when kernel/irq.c calls probe_irq_xxx this interrupt will
268 * be probed for usage. This will end up disabling the device :( 323 * be probed for usage. This will end up disabling the device :(
269 * Give it a bogus "action" pointer -- this will keep it from 324 * Give it a bogus "action" pointer -- this will keep it from
@@ -292,173 +347,112 @@ static void setup_local_irq(unsigned int irq_nr, int type, int int_req)
292 /* Config2[n], Config1[n], Config0[n] */ 347 /* Config2[n], Config1[n], Config0[n] */
293 if (irq_nr > AU1000_LAST_INTC0_INT) { 348 if (irq_nr > AU1000_LAST_INTC0_INT) {
294 switch (type) { 349 switch (type) {
295 case INTC_INT_RISE_EDGE: /* 0:0:1 */ 350 case INTC_INT_RISE_EDGE: /* 0:0:1 */
296 au_writel(1<<(irq_nr-32), IC1_CFG2CLR); 351 au_writel(1 << (irq_nr - 32), IC1_CFG2CLR);
297 au_writel(1<<(irq_nr-32), IC1_CFG1CLR); 352 au_writel(1 << (irq_nr - 32), IC1_CFG1CLR);
298 au_writel(1<<(irq_nr-32), IC1_CFG0SET); 353 au_writel(1 << (irq_nr - 32), IC1_CFG0SET);
299 set_irq_chip(irq_nr, &rise_edge_irq_type); 354 set_irq_chip(irq_nr, &rise_edge_irq_type);
300 break; 355 break;
301 case INTC_INT_FALL_EDGE: /* 0:1:0 */ 356 case INTC_INT_FALL_EDGE: /* 0:1:0 */
302 au_writel(1<<(irq_nr-32), IC1_CFG2CLR); 357 au_writel(1 << (irq_nr - 32), IC1_CFG2CLR);
303 au_writel(1<<(irq_nr-32), IC1_CFG1SET); 358 au_writel(1 << (irq_nr - 32), IC1_CFG1SET);
304 au_writel(1<<(irq_nr-32), IC1_CFG0CLR); 359 au_writel(1 << (irq_nr - 32), IC1_CFG0CLR);
305 set_irq_chip(irq_nr, &fall_edge_irq_type); 360 set_irq_chip(irq_nr, &fall_edge_irq_type);
306 break; 361 break;
307 case INTC_INT_RISE_AND_FALL_EDGE: /* 0:1:1 */ 362 case INTC_INT_RISE_AND_FALL_EDGE: /* 0:1:1 */
308 au_writel(1<<(irq_nr-32), IC1_CFG2CLR); 363 au_writel(1 << (irq_nr - 32), IC1_CFG2CLR);
309 au_writel(1<<(irq_nr-32), IC1_CFG1SET); 364 au_writel(1 << (irq_nr - 32), IC1_CFG1SET);
310 au_writel(1<<(irq_nr-32), IC1_CFG0SET); 365 au_writel(1 << (irq_nr - 32), IC1_CFG0SET);
311 set_irq_chip(irq_nr, &either_edge_irq_type); 366 set_irq_chip(irq_nr, &either_edge_irq_type);
312 break; 367 break;
313 case INTC_INT_HIGH_LEVEL: /* 1:0:1 */ 368 case INTC_INT_HIGH_LEVEL: /* 1:0:1 */
314 au_writel(1<<(irq_nr-32), IC1_CFG2SET); 369 au_writel(1 << (irq_nr - 32), IC1_CFG2SET);
315 au_writel(1<<(irq_nr-32), IC1_CFG1CLR); 370 au_writel(1 << (irq_nr - 32), IC1_CFG1CLR);
316 au_writel(1<<(irq_nr-32), IC1_CFG0SET); 371 au_writel(1 << (irq_nr - 32), IC1_CFG0SET);
317 set_irq_chip(irq_nr, &level_irq_type); 372 set_irq_chip(irq_nr, &level_irq_type);
318 break; 373 break;
319 case INTC_INT_LOW_LEVEL: /* 1:1:0 */ 374 case INTC_INT_LOW_LEVEL: /* 1:1:0 */
320 au_writel(1<<(irq_nr-32), IC1_CFG2SET); 375 au_writel(1 << (irq_nr - 32), IC1_CFG2SET);
321 au_writel(1<<(irq_nr-32), IC1_CFG1SET); 376 au_writel(1 << (irq_nr - 32), IC1_CFG1SET);
322 au_writel(1<<(irq_nr-32), IC1_CFG0CLR); 377 au_writel(1 << (irq_nr - 32), IC1_CFG0CLR);
323 set_irq_chip(irq_nr, &level_irq_type); 378 set_irq_chip(irq_nr, &level_irq_type);
324 break; 379 break;
325 case INTC_INT_DISABLED: /* 0:0:0 */ 380 case INTC_INT_DISABLED: /* 0:0:0 */
326 au_writel(1<<(irq_nr-32), IC1_CFG0CLR); 381 au_writel(1 << (irq_nr - 32), IC1_CFG0CLR);
327 au_writel(1<<(irq_nr-32), IC1_CFG1CLR); 382 au_writel(1 << (irq_nr - 32), IC1_CFG1CLR);
328 au_writel(1<<(irq_nr-32), IC1_CFG2CLR); 383 au_writel(1 << (irq_nr - 32), IC1_CFG2CLR);
329 break; 384 break;
330 default: /* disable the interrupt */ 385 default: /* disable the interrupt */
331 printk("unexpected int type %d (irq %d)\n", type, irq_nr); 386 printk(KERN_WARNING "unexpected int type %d (irq %d)\n",
332 au_writel(1<<(irq_nr-32), IC1_CFG0CLR); 387 type, irq_nr);
333 au_writel(1<<(irq_nr-32), IC1_CFG1CLR); 388 au_writel(1 << (irq_nr - 32), IC1_CFG0CLR);
334 au_writel(1<<(irq_nr-32), IC1_CFG2CLR); 389 au_writel(1 << (irq_nr - 32), IC1_CFG1CLR);
335 return; 390 au_writel(1 << (irq_nr - 32), IC1_CFG2CLR);
391 return;
336 } 392 }
337 if (int_req) /* assign to interrupt request 1 */ 393 if (int_req) /* assign to interrupt request 1 */
338 au_writel(1<<(irq_nr-32), IC1_ASSIGNCLR); 394 au_writel(1 << (irq_nr - 32), IC1_ASSIGNCLR);
339 else /* assign to interrupt request 0 */ 395 else /* assign to interrupt request 0 */
340 au_writel(1<<(irq_nr-32), IC1_ASSIGNSET); 396 au_writel(1 << (irq_nr - 32), IC1_ASSIGNSET);
341 au_writel(1<<(irq_nr-32), IC1_SRCSET); 397 au_writel(1 << (irq_nr - 32), IC1_SRCSET);
342 au_writel(1<<(irq_nr-32), IC1_MASKCLR); 398 au_writel(1 << (irq_nr - 32), IC1_MASKCLR);
343 au_writel(1<<(irq_nr-32), IC1_WAKECLR); 399 au_writel(1 << (irq_nr - 32), IC1_WAKECLR);
344 } 400 } else {
345 else {
346 switch (type) { 401 switch (type) {
347 case INTC_INT_RISE_EDGE: /* 0:0:1 */ 402 case INTC_INT_RISE_EDGE: /* 0:0:1 */
348 au_writel(1<<irq_nr, IC0_CFG2CLR); 403 au_writel(1 << irq_nr, IC0_CFG2CLR);
349 au_writel(1<<irq_nr, IC0_CFG1CLR); 404 au_writel(1 << irq_nr, IC0_CFG1CLR);
350 au_writel(1<<irq_nr, IC0_CFG0SET); 405 au_writel(1 << irq_nr, IC0_CFG0SET);
351 set_irq_chip(irq_nr, &rise_edge_irq_type); 406 set_irq_chip(irq_nr, &rise_edge_irq_type);
352 break; 407 break;
353 case INTC_INT_FALL_EDGE: /* 0:1:0 */ 408 case INTC_INT_FALL_EDGE: /* 0:1:0 */
354 au_writel(1<<irq_nr, IC0_CFG2CLR); 409 au_writel(1 << irq_nr, IC0_CFG2CLR);
355 au_writel(1<<irq_nr, IC0_CFG1SET); 410 au_writel(1 << irq_nr, IC0_CFG1SET);
356 au_writel(1<<irq_nr, IC0_CFG0CLR); 411 au_writel(1 << irq_nr, IC0_CFG0CLR);
357 set_irq_chip(irq_nr, &fall_edge_irq_type); 412 set_irq_chip(irq_nr, &fall_edge_irq_type);
358 break; 413 break;
359 case INTC_INT_RISE_AND_FALL_EDGE: /* 0:1:1 */ 414 case INTC_INT_RISE_AND_FALL_EDGE: /* 0:1:1 */
360 au_writel(1<<irq_nr, IC0_CFG2CLR); 415 au_writel(1 << irq_nr, IC0_CFG2CLR);
361 au_writel(1<<irq_nr, IC0_CFG1SET); 416 au_writel(1 << irq_nr, IC0_CFG1SET);
362 au_writel(1<<irq_nr, IC0_CFG0SET); 417 au_writel(1 << irq_nr, IC0_CFG0SET);
363 set_irq_chip(irq_nr, &either_edge_irq_type); 418 set_irq_chip(irq_nr, &either_edge_irq_type);
364 break; 419 break;
365 case INTC_INT_HIGH_LEVEL: /* 1:0:1 */ 420 case INTC_INT_HIGH_LEVEL: /* 1:0:1 */
366 au_writel(1<<irq_nr, IC0_CFG2SET); 421 au_writel(1 << irq_nr, IC0_CFG2SET);
367 au_writel(1<<irq_nr, IC0_CFG1CLR); 422 au_writel(1 << irq_nr, IC0_CFG1CLR);
368 au_writel(1<<irq_nr, IC0_CFG0SET); 423 au_writel(1 << irq_nr, IC0_CFG0SET);
369 set_irq_chip(irq_nr, &level_irq_type); 424 set_irq_chip(irq_nr, &level_irq_type);
370 break; 425 break;
371 case INTC_INT_LOW_LEVEL: /* 1:1:0 */ 426 case INTC_INT_LOW_LEVEL: /* 1:1:0 */
372 au_writel(1<<irq_nr, IC0_CFG2SET); 427 au_writel(1 << irq_nr, IC0_CFG2SET);
373 au_writel(1<<irq_nr, IC0_CFG1SET); 428 au_writel(1 << irq_nr, IC0_CFG1SET);
374 au_writel(1<<irq_nr, IC0_CFG0CLR); 429 au_writel(1 << irq_nr, IC0_CFG0CLR);
375 set_irq_chip(irq_nr, &level_irq_type); 430 set_irq_chip(irq_nr, &level_irq_type);
376 break; 431 break;
377 case INTC_INT_DISABLED: /* 0:0:0 */ 432 case INTC_INT_DISABLED: /* 0:0:0 */
378 au_writel(1<<irq_nr, IC0_CFG0CLR); 433 au_writel(1 << irq_nr, IC0_CFG0CLR);
379 au_writel(1<<irq_nr, IC0_CFG1CLR); 434 au_writel(1 << irq_nr, IC0_CFG1CLR);
380 au_writel(1<<irq_nr, IC0_CFG2CLR); 435 au_writel(1 << irq_nr, IC0_CFG2CLR);
381 break; 436 break;
382 default: /* disable the interrupt */ 437 default: /* disable the interrupt */
383 printk("unexpected int type %d (irq %d)\n", type, irq_nr); 438 printk(KERN_WARNING "unexpected int type %d (irq %d)\n",
384 au_writel(1<<irq_nr, IC0_CFG0CLR); 439 type, irq_nr);
385 au_writel(1<<irq_nr, IC0_CFG1CLR); 440 au_writel(1 << irq_nr, IC0_CFG0CLR);
386 au_writel(1<<irq_nr, IC0_CFG2CLR); 441 au_writel(1 << irq_nr, IC0_CFG1CLR);
387 return; 442 au_writel(1 << irq_nr, IC0_CFG2CLR);
443 return;
388 } 444 }
389 if (int_req) /* assign to interrupt request 1 */ 445 if (int_req) /* assign to interrupt request 1 */
390 au_writel(1<<irq_nr, IC0_ASSIGNCLR); 446 au_writel(1 << irq_nr, IC0_ASSIGNCLR);
391 else /* assign to interrupt request 0 */ 447 else /* assign to interrupt request 0 */
392 au_writel(1<<irq_nr, IC0_ASSIGNSET); 448 au_writel(1 << irq_nr, IC0_ASSIGNSET);
393 au_writel(1<<irq_nr, IC0_SRCSET); 449 au_writel(1 << irq_nr, IC0_SRCSET);
394 au_writel(1<<irq_nr, IC0_MASKCLR); 450 au_writel(1 << irq_nr, IC0_MASKCLR);
395 au_writel(1<<irq_nr, IC0_WAKECLR); 451 au_writel(1 << irq_nr, IC0_WAKECLR);
396 } 452 }
397 au_sync(); 453 au_sync();
398} 454}
399 455
400
401void __init arch_init_irq(void)
402{
403 int i;
404 unsigned long cp0_status;
405 au1xxx_irq_map_t *imp;
406 extern au1xxx_irq_map_t au1xxx_irq_map[];
407 extern au1xxx_irq_map_t au1xxx_ic0_map[];
408 extern int au1xxx_nr_irqs;
409 extern int au1xxx_ic0_nr_irqs;
410
411 cp0_status = read_c0_status();
412
413 /* Initialize interrupt controllers to a safe state.
414 */
415 au_writel(0xffffffff, IC0_CFG0CLR);
416 au_writel(0xffffffff, IC0_CFG1CLR);
417 au_writel(0xffffffff, IC0_CFG2CLR);
418 au_writel(0xffffffff, IC0_MASKCLR);
419 au_writel(0xffffffff, IC0_ASSIGNSET);
420 au_writel(0xffffffff, IC0_WAKECLR);
421 au_writel(0xffffffff, IC0_SRCSET);
422 au_writel(0xffffffff, IC0_FALLINGCLR);
423 au_writel(0xffffffff, IC0_RISINGCLR);
424 au_writel(0x00000000, IC0_TESTBIT);
425
426 au_writel(0xffffffff, IC1_CFG0CLR);
427 au_writel(0xffffffff, IC1_CFG1CLR);
428 au_writel(0xffffffff, IC1_CFG2CLR);
429 au_writel(0xffffffff, IC1_MASKCLR);
430 au_writel(0xffffffff, IC1_ASSIGNSET);
431 au_writel(0xffffffff, IC1_WAKECLR);
432 au_writel(0xffffffff, IC1_SRCSET);
433 au_writel(0xffffffff, IC1_FALLINGCLR);
434 au_writel(0xffffffff, IC1_RISINGCLR);
435 au_writel(0x00000000, IC1_TESTBIT);
436
437 /* Initialize IC0, which is fixed per processor.
438 */
439 imp = au1xxx_ic0_map;
440 for (i=0; i<au1xxx_ic0_nr_irqs; i++) {
441 setup_local_irq(imp->im_irq, imp->im_type, imp->im_request);
442 imp++;
443 }
444
445 /* Now set up the irq mapping for the board.
446 */
447 imp = au1xxx_irq_map;
448 for (i=0; i<au1xxx_nr_irqs; i++) {
449 setup_local_irq(imp->im_irq, imp->im_type, imp->im_request);
450 imp++;
451 }
452
453 set_c0_status(ALLINTS);
454
455 /* Board specific IRQ initialization.
456 */
457 if (board_init_irq)
458 (*board_init_irq)();
459}
460
461
462/* 456/*
463 * Interrupts are nested. Even if an interrupt handler is registered 457 * Interrupts are nested. Even if an interrupt handler is registered
464 * as "fast", we might get another interrupt before we return from 458 * as "fast", we might get another interrupt before we return from
@@ -468,26 +462,27 @@ void __init arch_init_irq(void)
468static void intc0_req0_irqdispatch(void) 462static void intc0_req0_irqdispatch(void)
469{ 463{
470 int irq = 0; 464 int irq = 0;
471 static unsigned long intc0_req0 = 0; 465 static unsigned long intc0_req0;
472 466
473 intc0_req0 |= au_readl(IC0_REQ0INT); 467 intc0_req0 |= au_readl(IC0_REQ0INT);
474 468
475 if (!intc0_req0) 469 if (!intc0_req0)
476 return; 470 return;
471
477#ifdef AU1000_USB_DEV_REQ_INT 472#ifdef AU1000_USB_DEV_REQ_INT
478 /* 473 /*
479 * Because of the tight timing of SETUP token to reply 474 * Because of the tight timing of SETUP token to reply
480 * transactions, the USB devices-side packet complete 475 * transactions, the USB devices-side packet complete
481 * interrupt needs the highest priority. 476 * interrupt needs the highest priority.
482 */ 477 */
483 if ((intc0_req0 & (1<<AU1000_USB_DEV_REQ_INT))) { 478 if ((intc0_req0 & (1 << AU1000_USB_DEV_REQ_INT))) {
484 intc0_req0 &= ~(1<<AU1000_USB_DEV_REQ_INT); 479 intc0_req0 &= ~(1 << AU1000_USB_DEV_REQ_INT);
485 do_IRQ(AU1000_USB_DEV_REQ_INT); 480 do_IRQ(AU1000_USB_DEV_REQ_INT);
486 return; 481 return;
487 } 482 }
488#endif 483#endif
489 irq = au_ffs(intc0_req0) - 1; 484 irq = au_ffs(intc0_req0) - 1;
490 intc0_req0 &= ~(1<<irq); 485 intc0_req0 &= ~(1 << irq);
491 do_IRQ(irq); 486 do_IRQ(irq);
492} 487}
493 488
@@ -495,7 +490,7 @@ static void intc0_req0_irqdispatch(void)
495static void intc0_req1_irqdispatch(void) 490static void intc0_req1_irqdispatch(void)
496{ 491{
497 int irq = 0; 492 int irq = 0;
498 static unsigned long intc0_req1 = 0; 493 static unsigned long intc0_req1;
499 494
500 intc0_req1 |= au_readl(IC0_REQ1INT); 495 intc0_req1 |= au_readl(IC0_REQ1INT);
501 496
@@ -503,7 +498,7 @@ static void intc0_req1_irqdispatch(void)
503 return; 498 return;
504 499
505 irq = au_ffs(intc0_req1) - 1; 500 irq = au_ffs(intc0_req1) - 1;
506 intc0_req1 &= ~(1<<irq); 501 intc0_req1 &= ~(1 << irq);
507 do_IRQ(irq); 502 do_IRQ(irq);
508} 503}
509 504
@@ -515,7 +510,7 @@ static void intc0_req1_irqdispatch(void)
515static void intc1_req0_irqdispatch(void) 510static void intc1_req0_irqdispatch(void)
516{ 511{
517 int irq = 0; 512 int irq = 0;
518 static unsigned long intc1_req0 = 0; 513 static unsigned long intc1_req0;
519 514
520 intc1_req0 |= au_readl(IC1_REQ0INT); 515 intc1_req0 |= au_readl(IC1_REQ0INT);
521 516
@@ -523,7 +518,7 @@ static void intc1_req0_irqdispatch(void)
523 return; 518 return;
524 519
525 irq = au_ffs(intc1_req0) - 1; 520 irq = au_ffs(intc1_req0) - 1;
526 intc1_req0 &= ~(1<<irq); 521 intc1_req0 &= ~(1 << irq);
527 irq += 32; 522 irq += 32;
528 do_IRQ(irq); 523 do_IRQ(irq);
529} 524}
@@ -532,7 +527,7 @@ static void intc1_req0_irqdispatch(void)
532static void intc1_req1_irqdispatch(void) 527static void intc1_req1_irqdispatch(void)
533{ 528{
534 int irq = 0; 529 int irq = 0;
535 static unsigned long intc1_req1 = 0; 530 static unsigned long intc1_req1;
536 531
537 intc1_req1 |= au_readl(IC1_REQ1INT); 532 intc1_req1 |= au_readl(IC1_REQ1INT);
538 533
@@ -540,94 +535,11 @@ static void intc1_req1_irqdispatch(void)
540 return; 535 return;
541 536
542 irq = au_ffs(intc1_req1) - 1; 537 irq = au_ffs(intc1_req1) - 1;
543 intc1_req1 &= ~(1<<irq); 538 intc1_req1 &= ~(1 << irq);
544 irq += 32; 539 irq += 32;
545 do_IRQ(irq); 540 do_IRQ(irq);
546} 541}
547 542
548#ifdef CONFIG_PM
549
550/* Save/restore the interrupt controller state.
551 * Called from the save/restore core registers as part of the
552 * au_sleep function in power.c.....maybe I should just pm_register()
553 * them instead?
554 */
555static unsigned int sleep_intctl_config0[2];
556static unsigned int sleep_intctl_config1[2];
557static unsigned int sleep_intctl_config2[2];
558static unsigned int sleep_intctl_src[2];
559static unsigned int sleep_intctl_assign[2];
560static unsigned int sleep_intctl_wake[2];
561static unsigned int sleep_intctl_mask[2];
562
563void
564save_au1xxx_intctl(void)
565{
566 sleep_intctl_config0[0] = au_readl(IC0_CFG0RD);
567 sleep_intctl_config1[0] = au_readl(IC0_CFG1RD);
568 sleep_intctl_config2[0] = au_readl(IC0_CFG2RD);
569 sleep_intctl_src[0] = au_readl(IC0_SRCRD);
570 sleep_intctl_assign[0] = au_readl(IC0_ASSIGNRD);
571 sleep_intctl_wake[0] = au_readl(IC0_WAKERD);
572 sleep_intctl_mask[0] = au_readl(IC0_MASKRD);
573
574 sleep_intctl_config0[1] = au_readl(IC1_CFG0RD);
575 sleep_intctl_config1[1] = au_readl(IC1_CFG1RD);
576 sleep_intctl_config2[1] = au_readl(IC1_CFG2RD);
577 sleep_intctl_src[1] = au_readl(IC1_SRCRD);
578 sleep_intctl_assign[1] = au_readl(IC1_ASSIGNRD);
579 sleep_intctl_wake[1] = au_readl(IC1_WAKERD);
580 sleep_intctl_mask[1] = au_readl(IC1_MASKRD);
581}
582
583/* For most restore operations, we clear the entire register and
584 * then set the bits we found during the save.
585 */
586void
587restore_au1xxx_intctl(void)
588{
589 au_writel(0xffffffff, IC0_MASKCLR); au_sync();
590
591 au_writel(0xffffffff, IC0_CFG0CLR); au_sync();
592 au_writel(sleep_intctl_config0[0], IC0_CFG0SET); au_sync();
593 au_writel(0xffffffff, IC0_CFG1CLR); au_sync();
594 au_writel(sleep_intctl_config1[0], IC0_CFG1SET); au_sync();
595 au_writel(0xffffffff, IC0_CFG2CLR); au_sync();
596 au_writel(sleep_intctl_config2[0], IC0_CFG2SET); au_sync();
597 au_writel(0xffffffff, IC0_SRCCLR); au_sync();
598 au_writel(sleep_intctl_src[0], IC0_SRCSET); au_sync();
599 au_writel(0xffffffff, IC0_ASSIGNCLR); au_sync();
600 au_writel(sleep_intctl_assign[0], IC0_ASSIGNSET); au_sync();
601 au_writel(0xffffffff, IC0_WAKECLR); au_sync();
602 au_writel(sleep_intctl_wake[0], IC0_WAKESET); au_sync();
603 au_writel(0xffffffff, IC0_RISINGCLR); au_sync();
604 au_writel(0xffffffff, IC0_FALLINGCLR); au_sync();
605 au_writel(0x00000000, IC0_TESTBIT); au_sync();
606
607 au_writel(0xffffffff, IC1_MASKCLR); au_sync();
608
609 au_writel(0xffffffff, IC1_CFG0CLR); au_sync();
610 au_writel(sleep_intctl_config0[1], IC1_CFG0SET); au_sync();
611 au_writel(0xffffffff, IC1_CFG1CLR); au_sync();
612 au_writel(sleep_intctl_config1[1], IC1_CFG1SET); au_sync();
613 au_writel(0xffffffff, IC1_CFG2CLR); au_sync();
614 au_writel(sleep_intctl_config2[1], IC1_CFG2SET); au_sync();
615 au_writel(0xffffffff, IC1_SRCCLR); au_sync();
616 au_writel(sleep_intctl_src[1], IC1_SRCSET); au_sync();
617 au_writel(0xffffffff, IC1_ASSIGNCLR); au_sync();
618 au_writel(sleep_intctl_assign[1], IC1_ASSIGNSET); au_sync();
619 au_writel(0xffffffff, IC1_WAKECLR); au_sync();
620 au_writel(sleep_intctl_wake[1], IC1_WAKESET); au_sync();
621 au_writel(0xffffffff, IC1_RISINGCLR); au_sync();
622 au_writel(0xffffffff, IC1_FALLINGCLR); au_sync();
623 au_writel(0x00000000, IC1_TESTBIT); au_sync();
624
625 au_writel(sleep_intctl_mask[1], IC1_MASKSET); au_sync();
626
627 au_writel(sleep_intctl_mask[0], IC0_MASKSET); au_sync();
628}
629#endif /* CONFIG_PM */
630
631asmlinkage void plat_irq_dispatch(void) 543asmlinkage void plat_irq_dispatch(void)
632{ 544{
633 unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM; 545 unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM;
@@ -645,3 +557,63 @@ asmlinkage void plat_irq_dispatch(void)
645 else 557 else
646 spurious_interrupt(); 558 spurious_interrupt();
647} 559}
560
561void __init arch_init_irq(void)
562{
563 int i;
564 unsigned long cp0_status;
565 au1xxx_irq_map_t *imp;
566 extern au1xxx_irq_map_t au1xxx_irq_map[];
567 extern au1xxx_irq_map_t au1xxx_ic0_map[];
568 extern int au1xxx_nr_irqs;
569 extern int au1xxx_ic0_nr_irqs;
570
571 cp0_status = read_c0_status();
572
573 /* Initialize interrupt controllers to a safe state.
574 */
575 au_writel(0xffffffff, IC0_CFG0CLR);
576 au_writel(0xffffffff, IC0_CFG1CLR);
577 au_writel(0xffffffff, IC0_CFG2CLR);
578 au_writel(0xffffffff, IC0_MASKCLR);
579 au_writel(0xffffffff, IC0_ASSIGNSET);
580 au_writel(0xffffffff, IC0_WAKECLR);
581 au_writel(0xffffffff, IC0_SRCSET);
582 au_writel(0xffffffff, IC0_FALLINGCLR);
583 au_writel(0xffffffff, IC0_RISINGCLR);
584 au_writel(0x00000000, IC0_TESTBIT);
585
586 au_writel(0xffffffff, IC1_CFG0CLR);
587 au_writel(0xffffffff, IC1_CFG1CLR);
588 au_writel(0xffffffff, IC1_CFG2CLR);
589 au_writel(0xffffffff, IC1_MASKCLR);
590 au_writel(0xffffffff, IC1_ASSIGNSET);
591 au_writel(0xffffffff, IC1_WAKECLR);
592 au_writel(0xffffffff, IC1_SRCSET);
593 au_writel(0xffffffff, IC1_FALLINGCLR);
594 au_writel(0xffffffff, IC1_RISINGCLR);
595 au_writel(0x00000000, IC1_TESTBIT);
596
597 /* Initialize IC0, which is fixed per processor.
598 */
599 imp = au1xxx_ic0_map;
600 for (i = 0; i < au1xxx_ic0_nr_irqs; i++) {
601 setup_local_irq(imp->im_irq, imp->im_type, imp->im_request);
602 imp++;
603 }
604
605 /* Now set up the irq mapping for the board.
606 */
607 imp = au1xxx_irq_map;
608 for (i = 0; i < au1xxx_nr_irqs; i++) {
609 setup_local_irq(imp->im_irq, imp->im_type, imp->im_request);
610 imp++;
611 }
612
613 set_c0_status(ALLINTS);
614
615 /* Board specific IRQ initialization.
616 */
617 if (board_init_irq)
618 (*board_init_irq)();
619}
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-15 21:58:47 -0500