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authorHeiko Stuebner <heiko@sntech.de>2014-02-24 19:50:44 -0500
committerKukjin Kim <kgene.kim@samsung.com>2014-04-14 13:11:49 -0400
commit3c27f314c676ee31eafd423ce2c640ed129cd5e0 (patch)
treeaad459937e1ef77ec5195f3f983926ac1bb031af /arch
parentca2e90ac1809c49c2306df4e23e17dad67c785b6 (diff)
ARM: S3C24XX: convert s3c2412 to common clock framework
Convert all machines using these cpus to use the ccf clock driver instead of the legacy Samsung clock implementation. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/mach-s3c24xx/Kconfig8
-rw-r--r--arch/arm/mach-s3c24xx/Makefile2
-rw-r--r--arch/arm/mach-s3c24xx/clock-s3c2412.c760
-rw-r--r--arch/arm/mach-s3c24xx/common.c9
-rw-r--r--arch/arm/mach-s3c24xx/common.h4
-rw-r--r--arch/arm/mach-s3c24xx/mach-jive.c9
-rw-r--r--arch/arm/mach-s3c24xx/mach-smdk2413.c9
-rw-r--r--arch/arm/mach-s3c24xx/mach-vstms.c9
-rw-r--r--arch/arm/mach-s3c24xx/s3c2412.c43
9 files changed, 40 insertions, 813 deletions
diff --git a/arch/arm/mach-s3c24xx/Kconfig b/arch/arm/mach-s3c24xx/Kconfig
index 52f1c40ccf07..fbafb9a1975b 100644
--- a/arch/arm/mach-s3c24xx/Kconfig
+++ b/arch/arm/mach-s3c24xx/Kconfig
@@ -39,9 +39,10 @@ config CPU_S3C2410
39 39
40config CPU_S3C2412 40config CPU_S3C2412
41 bool "SAMSUNG S3C2412" 41 bool "SAMSUNG S3C2412"
42 depends on SAMSUNG_CLOCK 42 select COMMON_CLK
43 select CPU_ARM926T 43 select CPU_ARM926T
44 select CPU_LLSERIAL_S3C2440 44 select CPU_LLSERIAL_S3C2440
45 select S3C2412_COMMON_CLK
45 select S3C2412_DMA if S3C24XX_DMA 46 select S3C2412_DMA if S3C24XX_DMA
46 select S3C2412_PM if PM 47 select S3C2412_PM if PM
47 help 48 help
@@ -363,6 +364,11 @@ config S3C2412_PM_SLEEP
363 364
364if CPU_S3C2412 365if CPU_S3C2412
365 366
367config S3C2412_COMMON_CLK
368 bool
369 help
370 Build the s3c2412 clock driver based on the common clock framework.
371
366config CPU_S3C2412_ONLY 372config CPU_S3C2412_ONLY
367 bool 373 bool
368 depends on !CPU_S3C2410 && !CPU_S3C2416 && !CPU_S3C2440 && \ 374 depends on !CPU_S3C2410 && !CPU_S3C2416 && !CPU_S3C2440 && \
diff --git a/arch/arm/mach-s3c24xx/Makefile b/arch/arm/mach-s3c24xx/Makefile
index ba0e5475a807..f25479721dc9 100644
--- a/arch/arm/mach-s3c24xx/Makefile
+++ b/arch/arm/mach-s3c24xx/Makefile
@@ -21,7 +21,7 @@ obj-$(CONFIG_S3C2410_DMA) += dma-s3c2410.o
21obj-$(CONFIG_S3C2410_PLL) += pll-s3c2410.o 21obj-$(CONFIG_S3C2410_PLL) += pll-s3c2410.o
22obj-$(CONFIG_S3C2410_PM) += pm-s3c2410.o sleep-s3c2410.o 22obj-$(CONFIG_S3C2410_PM) += pm-s3c2410.o sleep-s3c2410.o
23 23
24obj-$(CONFIG_CPU_S3C2412) += s3c2412.o clock-s3c2412.o 24obj-$(CONFIG_CPU_S3C2412) += s3c2412.o
25obj-$(CONFIG_S3C2412_DMA) += dma-s3c2412.o 25obj-$(CONFIG_S3C2412_DMA) += dma-s3c2412.o
26obj-$(CONFIG_S3C2412_PM) += pm-s3c2412.o 26obj-$(CONFIG_S3C2412_PM) += pm-s3c2412.o
27obj-$(CONFIG_S3C2412_PM_SLEEP) += sleep-s3c2412.o 27obj-$(CONFIG_S3C2412_PM_SLEEP) += sleep-s3c2412.o
diff --git a/arch/arm/mach-s3c24xx/clock-s3c2412.c b/arch/arm/mach-s3c24xx/clock-s3c2412.c
deleted file mode 100644
index 192a5b2550b0..000000000000
--- a/arch/arm/mach-s3c24xx/clock-s3c2412.c
+++ /dev/null
@@ -1,760 +0,0 @@
1/* linux/arch/arm/mach-s3c2412/clock.c
2 *
3 * Copyright (c) 2006 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * S3C2412,S3C2413 Clock control support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21*/
22
23#include <linux/init.h>
24#include <linux/module.h>
25#include <linux/kernel.h>
26#include <linux/list.h>
27#include <linux/errno.h>
28#include <linux/err.h>
29#include <linux/device.h>
30#include <linux/clk.h>
31#include <linux/mutex.h>
32#include <linux/delay.h>
33#include <linux/serial_core.h>
34#include <linux/serial_s3c.h>
35#include <linux/io.h>
36
37#include <asm/mach/map.h>
38
39#include <mach/hardware.h>
40#include <mach/regs-clock.h>
41#include <mach/regs-gpio.h>
42
43#include <plat/clock.h>
44#include <plat/cpu.h>
45
46/* We currently have to assume that the system is running
47 * from the XTPll input, and that all ***REFCLKs are being
48 * fed from it, as we cannot read the state of OM[4] from
49 * software.
50 *
51 * It would be possible for each board initialisation to
52 * set the correct muxing at initialisation
53*/
54
55static int s3c2412_clkcon_enable(struct clk *clk, int enable)
56{
57 unsigned int clocks = clk->ctrlbit;
58 unsigned long clkcon;
59
60 clkcon = __raw_readl(S3C2410_CLKCON);
61
62 if (enable)
63 clkcon |= clocks;
64 else
65 clkcon &= ~clocks;
66
67 __raw_writel(clkcon, S3C2410_CLKCON);
68
69 return 0;
70}
71
72static int s3c2412_upll_enable(struct clk *clk, int enable)
73{
74 unsigned long upllcon = __raw_readl(S3C2410_UPLLCON);
75 unsigned long orig = upllcon;
76
77 if (!enable)
78 upllcon |= S3C2412_PLLCON_OFF;
79 else
80 upllcon &= ~S3C2412_PLLCON_OFF;
81
82 __raw_writel(upllcon, S3C2410_UPLLCON);
83
84 /* allow ~150uS for the PLL to settle and lock */
85
86 if (enable && (orig & S3C2412_PLLCON_OFF))
87 udelay(150);
88
89 return 0;
90}
91
92/* clock selections */
93
94static struct clk clk_erefclk = {
95 .name = "erefclk",
96};
97
98static struct clk clk_urefclk = {
99 .name = "urefclk",
100};
101
102static int s3c2412_setparent_usysclk(struct clk *clk, struct clk *parent)
103{
104 unsigned long clksrc = __raw_readl(S3C2412_CLKSRC);
105
106 if (parent == &clk_urefclk)
107 clksrc &= ~S3C2412_CLKSRC_USYSCLK_UPLL;
108 else if (parent == &clk_upll)
109 clksrc |= S3C2412_CLKSRC_USYSCLK_UPLL;
110 else
111 return -EINVAL;
112
113 clk->parent = parent;
114
115 __raw_writel(clksrc, S3C2412_CLKSRC);
116 return 0;
117}
118
119static struct clk clk_usysclk = {
120 .name = "usysclk",
121 .parent = &clk_xtal,
122 .ops = &(struct clk_ops) {
123 .set_parent = s3c2412_setparent_usysclk,
124 },
125};
126
127static struct clk clk_mrefclk = {
128 .name = "mrefclk",
129 .parent = &clk_xtal,
130};
131
132static struct clk clk_mdivclk = {
133 .name = "mdivclk",
134 .parent = &clk_xtal,
135};
136
137static int s3c2412_setparent_usbsrc(struct clk *clk, struct clk *parent)
138{
139 unsigned long clksrc = __raw_readl(S3C2412_CLKSRC);
140
141 if (parent == &clk_usysclk)
142 clksrc &= ~S3C2412_CLKSRC_USBCLK_HCLK;
143 else if (parent == &clk_h)
144 clksrc |= S3C2412_CLKSRC_USBCLK_HCLK;
145 else
146 return -EINVAL;
147
148 clk->parent = parent;
149
150 __raw_writel(clksrc, S3C2412_CLKSRC);
151 return 0;
152}
153
154static unsigned long s3c2412_roundrate_usbsrc(struct clk *clk,
155 unsigned long rate)
156{
157 unsigned long parent_rate = clk_get_rate(clk->parent);
158 int div;
159
160 if (rate > parent_rate)
161 return parent_rate;
162
163 div = parent_rate / rate;
164 if (div > 2)
165 div = 2;
166
167 return parent_rate / div;
168}
169
170static unsigned long s3c2412_getrate_usbsrc(struct clk *clk)
171{
172 unsigned long parent_rate = clk_get_rate(clk->parent);
173 unsigned long div = __raw_readl(S3C2410_CLKDIVN);
174
175 return parent_rate / ((div & S3C2412_CLKDIVN_USB48DIV) ? 2 : 1);
176}
177
178static int s3c2412_setrate_usbsrc(struct clk *clk, unsigned long rate)
179{
180 unsigned long parent_rate = clk_get_rate(clk->parent);
181 unsigned long clkdivn = __raw_readl(S3C2410_CLKDIVN);
182
183 rate = s3c2412_roundrate_usbsrc(clk, rate);
184
185 if ((parent_rate / rate) == 2)
186 clkdivn |= S3C2412_CLKDIVN_USB48DIV;
187 else
188 clkdivn &= ~S3C2412_CLKDIVN_USB48DIV;
189
190 __raw_writel(clkdivn, S3C2410_CLKDIVN);
191 return 0;
192}
193
194static struct clk clk_usbsrc = {
195 .name = "usbsrc",
196 .ops = &(struct clk_ops) {
197 .get_rate = s3c2412_getrate_usbsrc,
198 .set_rate = s3c2412_setrate_usbsrc,
199 .round_rate = s3c2412_roundrate_usbsrc,
200 .set_parent = s3c2412_setparent_usbsrc,
201 },
202};
203
204static int s3c2412_setparent_msysclk(struct clk *clk, struct clk *parent)
205{
206 unsigned long clksrc = __raw_readl(S3C2412_CLKSRC);
207
208 if (parent == &clk_mdivclk)
209 clksrc &= ~S3C2412_CLKSRC_MSYSCLK_MPLL;
210 else if (parent == &clk_mpll)
211 clksrc |= S3C2412_CLKSRC_MSYSCLK_MPLL;
212 else
213 return -EINVAL;
214
215 clk->parent = parent;
216
217 __raw_writel(clksrc, S3C2412_CLKSRC);
218 return 0;
219}
220
221static struct clk clk_msysclk = {
222 .name = "msysclk",
223 .ops = &(struct clk_ops) {
224 .set_parent = s3c2412_setparent_msysclk,
225 },
226};
227
228static int s3c2412_setparent_armclk(struct clk *clk, struct clk *parent)
229{
230 unsigned long flags;
231 unsigned long clkdiv;
232 unsigned long dvs;
233
234 /* Note, we current equate fclk andf msysclk for S3C2412 */
235
236 if (parent == &clk_msysclk || parent == &clk_f)
237 dvs = 0;
238 else if (parent == &clk_h)
239 dvs = S3C2412_CLKDIVN_DVSEN;
240 else
241 return -EINVAL;
242
243 clk->parent = parent;
244
245 /* update this under irq lockdown, clkdivn is not protected
246 * by the clock system. */
247
248 local_irq_save(flags);
249
250 clkdiv = __raw_readl(S3C2410_CLKDIVN);
251 clkdiv &= ~S3C2412_CLKDIVN_DVSEN;
252 clkdiv |= dvs;
253 __raw_writel(clkdiv, S3C2410_CLKDIVN);
254
255 local_irq_restore(flags);
256
257 return 0;
258}
259
260static struct clk clk_armclk = {
261 .name = "armclk",
262 .parent = &clk_msysclk,
263 .ops = &(struct clk_ops) {
264 .set_parent = s3c2412_setparent_armclk,
265 },
266};
267
268/* these next clocks have an divider immediately after them,
269 * so we can register them with their divider and leave out the
270 * intermediate clock stage
271*/
272static unsigned long s3c2412_roundrate_clksrc(struct clk *clk,
273 unsigned long rate)
274{
275 unsigned long parent_rate = clk_get_rate(clk->parent);
276 int div;
277
278 if (rate > parent_rate)
279 return parent_rate;
280
281 /* note, we remove the +/- 1 calculations as they cancel out */
282
283 div = (rate / parent_rate);
284
285 if (div < 1)
286 div = 1;
287 else if (div > 16)
288 div = 16;
289
290 return parent_rate / div;
291}
292
293static int s3c2412_setparent_uart(struct clk *clk, struct clk *parent)
294{
295 unsigned long clksrc = __raw_readl(S3C2412_CLKSRC);
296
297 if (parent == &clk_erefclk)
298 clksrc &= ~S3C2412_CLKSRC_UARTCLK_MPLL;
299 else if (parent == &clk_mpll)
300 clksrc |= S3C2412_CLKSRC_UARTCLK_MPLL;
301 else
302 return -EINVAL;
303
304 clk->parent = parent;
305
306 __raw_writel(clksrc, S3C2412_CLKSRC);
307 return 0;
308}
309
310static unsigned long s3c2412_getrate_uart(struct clk *clk)
311{
312 unsigned long parent_rate = clk_get_rate(clk->parent);
313 unsigned long div = __raw_readl(S3C2410_CLKDIVN);
314
315 div &= S3C2412_CLKDIVN_UARTDIV_MASK;
316 div >>= S3C2412_CLKDIVN_UARTDIV_SHIFT;
317
318 return parent_rate / (div + 1);
319}
320
321static int s3c2412_setrate_uart(struct clk *clk, unsigned long rate)
322{
323 unsigned long parent_rate = clk_get_rate(clk->parent);
324 unsigned long clkdivn = __raw_readl(S3C2410_CLKDIVN);
325
326 rate = s3c2412_roundrate_clksrc(clk, rate);
327
328 clkdivn &= ~S3C2412_CLKDIVN_UARTDIV_MASK;
329 clkdivn |= ((parent_rate / rate) - 1) << S3C2412_CLKDIVN_UARTDIV_SHIFT;
330
331 __raw_writel(clkdivn, S3C2410_CLKDIVN);
332 return 0;
333}
334
335static struct clk clk_uart = {
336 .name = "uartclk",
337 .ops = &(struct clk_ops) {
338 .get_rate = s3c2412_getrate_uart,
339 .set_rate = s3c2412_setrate_uart,
340 .set_parent = s3c2412_setparent_uart,
341 .round_rate = s3c2412_roundrate_clksrc,
342 },
343};
344
345static int s3c2412_setparent_i2s(struct clk *clk, struct clk *parent)
346{
347 unsigned long clksrc = __raw_readl(S3C2412_CLKSRC);
348
349 if (parent == &clk_erefclk)
350 clksrc &= ~S3C2412_CLKSRC_I2SCLK_MPLL;
351 else if (parent == &clk_mpll)
352 clksrc |= S3C2412_CLKSRC_I2SCLK_MPLL;
353 else
354 return -EINVAL;
355
356 clk->parent = parent;
357
358 __raw_writel(clksrc, S3C2412_CLKSRC);
359 return 0;
360}
361
362static unsigned long s3c2412_getrate_i2s(struct clk *clk)
363{
364 unsigned long parent_rate = clk_get_rate(clk->parent);
365 unsigned long div = __raw_readl(S3C2410_CLKDIVN);
366
367 div &= S3C2412_CLKDIVN_I2SDIV_MASK;
368 div >>= S3C2412_CLKDIVN_I2SDIV_SHIFT;
369
370 return parent_rate / (div + 1);
371}
372
373static int s3c2412_setrate_i2s(struct clk *clk, unsigned long rate)
374{
375 unsigned long parent_rate = clk_get_rate(clk->parent);
376 unsigned long clkdivn = __raw_readl(S3C2410_CLKDIVN);
377
378 rate = s3c2412_roundrate_clksrc(clk, rate);
379
380 clkdivn &= ~S3C2412_CLKDIVN_I2SDIV_MASK;
381 clkdivn |= ((parent_rate / rate) - 1) << S3C2412_CLKDIVN_I2SDIV_SHIFT;
382
383 __raw_writel(clkdivn, S3C2410_CLKDIVN);
384 return 0;
385}
386
387static struct clk clk_i2s = {
388 .name = "i2sclk",
389 .ops = &(struct clk_ops) {
390 .get_rate = s3c2412_getrate_i2s,
391 .set_rate = s3c2412_setrate_i2s,
392 .set_parent = s3c2412_setparent_i2s,
393 .round_rate = s3c2412_roundrate_clksrc,
394 },
395};
396
397static int s3c2412_setparent_cam(struct clk *clk, struct clk *parent)
398{
399 unsigned long clksrc = __raw_readl(S3C2412_CLKSRC);
400
401 if (parent == &clk_usysclk)
402 clksrc &= ~S3C2412_CLKSRC_CAMCLK_HCLK;
403 else if (parent == &clk_h)
404 clksrc |= S3C2412_CLKSRC_CAMCLK_HCLK;
405 else
406 return -EINVAL;
407
408 clk->parent = parent;
409
410 __raw_writel(clksrc, S3C2412_CLKSRC);
411 return 0;
412}
413static unsigned long s3c2412_getrate_cam(struct clk *clk)
414{
415 unsigned long parent_rate = clk_get_rate(clk->parent);
416 unsigned long div = __raw_readl(S3C2410_CLKDIVN);
417
418 div &= S3C2412_CLKDIVN_CAMDIV_MASK;
419 div >>= S3C2412_CLKDIVN_CAMDIV_SHIFT;
420
421 return parent_rate / (div + 1);
422}
423
424static int s3c2412_setrate_cam(struct clk *clk, unsigned long rate)
425{
426 unsigned long parent_rate = clk_get_rate(clk->parent);
427 unsigned long clkdivn = __raw_readl(S3C2410_CLKDIVN);
428
429 rate = s3c2412_roundrate_clksrc(clk, rate);
430
431 clkdivn &= ~S3C2412_CLKDIVN_CAMDIV_MASK;
432 clkdivn |= ((parent_rate / rate) - 1) << S3C2412_CLKDIVN_CAMDIV_SHIFT;
433
434 __raw_writel(clkdivn, S3C2410_CLKDIVN);
435 return 0;
436}
437
438static struct clk clk_cam = {
439 .name = "camif-upll", /* same as 2440 name */
440 .ops = &(struct clk_ops) {
441 .get_rate = s3c2412_getrate_cam,
442 .set_rate = s3c2412_setrate_cam,
443 .set_parent = s3c2412_setparent_cam,
444 .round_rate = s3c2412_roundrate_clksrc,
445 },
446};
447
448/* standard clock definitions */
449
450static struct clk init_clocks_disable[] = {
451 {
452 .name = "nand",
453 .parent = &clk_h,
454 .enable = s3c2412_clkcon_enable,
455 .ctrlbit = S3C2412_CLKCON_NAND,
456 }, {
457 .name = "sdi",
458 .parent = &clk_p,
459 .enable = s3c2412_clkcon_enable,
460 .ctrlbit = S3C2412_CLKCON_SDI,
461 }, {
462 .name = "adc",
463 .parent = &clk_p,
464 .enable = s3c2412_clkcon_enable,
465 .ctrlbit = S3C2412_CLKCON_ADC,
466 }, {
467 .name = "i2c",
468 .parent = &clk_p,
469 .enable = s3c2412_clkcon_enable,
470 .ctrlbit = S3C2412_CLKCON_IIC,
471 }, {
472 .name = "iis",
473 .parent = &clk_p,
474 .enable = s3c2412_clkcon_enable,
475 .ctrlbit = S3C2412_CLKCON_IIS,
476 }, {
477 .name = "spi",
478 .parent = &clk_p,
479 .enable = s3c2412_clkcon_enable,
480 .ctrlbit = S3C2412_CLKCON_SPI,
481 }
482};
483
484static struct clk init_clocks[] = {
485 {
486 .name = "dma.0",
487 .parent = &clk_h,
488 .enable = s3c2412_clkcon_enable,
489 .ctrlbit = S3C2412_CLKCON_DMA0,
490 }, {
491 .name = "dma.1",
492 .parent = &clk_h,
493 .enable = s3c2412_clkcon_enable,
494 .ctrlbit = S3C2412_CLKCON_DMA1,
495 }, {
496 .name = "dma.2",
497 .parent = &clk_h,
498 .enable = s3c2412_clkcon_enable,
499 .ctrlbit = S3C2412_CLKCON_DMA2,
500 }, {
501 .name = "dma.3",
502 .parent = &clk_h,
503 .enable = s3c2412_clkcon_enable,
504 .ctrlbit = S3C2412_CLKCON_DMA3,
505 }, {
506 .name = "lcd",
507 .parent = &clk_h,
508 .enable = s3c2412_clkcon_enable,
509 .ctrlbit = S3C2412_CLKCON_LCDC,
510 }, {
511 .name = "gpio",
512 .parent = &clk_p,
513 .enable = s3c2412_clkcon_enable,
514 .ctrlbit = S3C2412_CLKCON_GPIO,
515 }, {
516 .name = "usb-host",
517 .parent = &clk_h,
518 .enable = s3c2412_clkcon_enable,
519 .ctrlbit = S3C2412_CLKCON_USBH,
520 }, {
521 .name = "usb-device",
522 .parent = &clk_h,
523 .enable = s3c2412_clkcon_enable,
524 .ctrlbit = S3C2412_CLKCON_USBD,
525 }, {
526 .name = "timers",
527 .parent = &clk_p,
528 .enable = s3c2412_clkcon_enable,
529 .ctrlbit = S3C2412_CLKCON_PWMT,
530 }, {
531 .name = "uart",
532 .devname = "s3c2412-uart.0",
533 .parent = &clk_p,
534 .enable = s3c2412_clkcon_enable,
535 .ctrlbit = S3C2412_CLKCON_UART0,
536 }, {
537 .name = "uart",
538 .devname = "s3c2412-uart.1",
539 .parent = &clk_p,
540 .enable = s3c2412_clkcon_enable,
541 .ctrlbit = S3C2412_CLKCON_UART1,
542 }, {
543 .name = "uart",
544 .devname = "s3c2412-uart.2",
545 .parent = &clk_p,
546 .enable = s3c2412_clkcon_enable,
547 .ctrlbit = S3C2412_CLKCON_UART2,
548 }, {
549 .name = "rtc",
550 .parent = &clk_p,
551 .enable = s3c2412_clkcon_enable,
552 .ctrlbit = S3C2412_CLKCON_RTC,
553 }, {
554 .name = "watchdog",
555 .parent = &clk_p,
556 .ctrlbit = 0,
557 }, {
558 .name = "usb-bus-gadget",
559 .parent = &clk_usb_bus,
560 .enable = s3c2412_clkcon_enable,
561 .ctrlbit = S3C2412_CLKCON_USB_DEV48,
562 }, {
563 .name = "usb-bus-host",
564 .parent = &clk_usb_bus,
565 .enable = s3c2412_clkcon_enable,
566 .ctrlbit = S3C2412_CLKCON_USB_HOST48,
567 }
568};
569
570/* clocks to add where we need to check their parentage */
571
572struct clk_init {
573 struct clk *clk;
574 unsigned int bit;
575 struct clk *src_0;
576 struct clk *src_1;
577};
578
579static struct clk_init clks_src[] __initdata = {
580 {
581 .clk = &clk_usysclk,
582 .bit = S3C2412_CLKSRC_USBCLK_HCLK,
583 .src_0 = &clk_urefclk,
584 .src_1 = &clk_upll,
585 }, {
586 .clk = &clk_i2s,
587 .bit = S3C2412_CLKSRC_I2SCLK_MPLL,
588 .src_0 = &clk_erefclk,
589 .src_1 = &clk_mpll,
590 }, {
591 .clk = &clk_cam,
592 .bit = S3C2412_CLKSRC_CAMCLK_HCLK,
593 .src_0 = &clk_usysclk,
594 .src_1 = &clk_h,
595 }, {
596 .clk = &clk_msysclk,
597 .bit = S3C2412_CLKSRC_MSYSCLK_MPLL,
598 .src_0 = &clk_mdivclk,
599 .src_1 = &clk_mpll,
600 }, {
601 .clk = &clk_uart,
602 .bit = S3C2412_CLKSRC_UARTCLK_MPLL,
603 .src_0 = &clk_erefclk,
604 .src_1 = &clk_mpll,
605 }, {
606 .clk = &clk_usbsrc,
607 .bit = S3C2412_CLKSRC_USBCLK_HCLK,
608 .src_0 = &clk_usysclk,
609 .src_1 = &clk_h,
610 /* here we assume OM[4] select xtal */
611 }, {
612 .clk = &clk_erefclk,
613 .bit = S3C2412_CLKSRC_EREFCLK_EXTCLK,
614 .src_0 = &clk_xtal,
615 .src_1 = &clk_ext,
616 }, {
617 .clk = &clk_urefclk,
618 .bit = S3C2412_CLKSRC_UREFCLK_EXTCLK,
619 .src_0 = &clk_xtal,
620 .src_1 = &clk_ext,
621 },
622};
623
624/* s3c2412_clk_initparents
625 *
626 * Initialise the parents for the clocks that we get at start-time
627*/
628
629static void __init s3c2412_clk_initparents(void)
630{
631 unsigned long clksrc = __raw_readl(S3C2412_CLKSRC);
632 struct clk_init *cip = clks_src;
633 struct clk *src;
634 int ptr;
635 int ret;
636
637 for (ptr = 0; ptr < ARRAY_SIZE(clks_src); ptr++, cip++) {
638 ret = s3c24xx_register_clock(cip->clk);
639 if (ret < 0) {
640 printk(KERN_ERR "Failed to register clock %s (%d)\n",
641 cip->clk->name, ret);
642 }
643
644 src = (clksrc & cip->bit) ? cip->src_1 : cip->src_0;
645
646 printk(KERN_INFO "%s: parent %s\n", cip->clk->name, src->name);
647 clk_set_parent(cip->clk, src);
648 }
649}
650
651/* clocks to add straight away */
652
653static struct clk *clks[] __initdata = {
654 &clk_ext,
655 &clk_usb_bus,
656 &clk_mrefclk,
657 &clk_armclk,
658};
659
660static struct clk_lookup s3c2412_clk_lookup[] = {
661 CLKDEV_INIT(NULL, "clk_uart_baud1", &s3c24xx_uclk),
662 CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_p),
663 CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_usysclk),
664};
665
666int __init s3c2412_baseclk_add(void)
667{
668 unsigned long clkcon = __raw_readl(S3C2410_CLKCON);
669 unsigned int dvs;
670 struct clk *clkp;
671 int ret;
672 int ptr;
673
674 clk_upll.enable = s3c2412_upll_enable;
675 clk_usb_bus.parent = &clk_usbsrc;
676 clk_usb_bus.rate = 0x0;
677
678 clk_f.parent = &clk_msysclk;
679
680 s3c2412_clk_initparents();
681
682 for (ptr = 0; ptr < ARRAY_SIZE(clks); ptr++) {
683 clkp = clks[ptr];
684
685 ret = s3c24xx_register_clock(clkp);
686 if (ret < 0) {
687 printk(KERN_ERR "Failed to register clock %s (%d)\n",
688 clkp->name, ret);
689 }
690 }
691
692 /* set the dvs state according to what we got at boot time */
693
694 dvs = __raw_readl(S3C2410_CLKDIVN) & S3C2412_CLKDIVN_DVSEN;
695
696 if (dvs)
697 clk_armclk.parent = &clk_h;
698
699 printk(KERN_INFO "S3C2412: DVS is %s\n", dvs ? "on" : "off");
700
701 /* ensure usb bus clock is within correct rate of 48MHz */
702
703 if (clk_get_rate(&clk_usb_bus) != (48 * 1000 * 1000)) {
704 printk(KERN_INFO "Warning: USB bus clock not at 48MHz\n");
705
706 /* for the moment, let's use the UPLL, and see if we can
707 * get 48MHz */
708
709 clk_set_parent(&clk_usysclk, &clk_upll);
710 clk_set_parent(&clk_usbsrc, &clk_usysclk);
711 clk_set_rate(&clk_usbsrc, 48*1000*1000);
712 }
713
714 printk("S3C2412: upll %s, %ld.%03ld MHz, usb-bus %ld.%03ld MHz\n",
715 (__raw_readl(S3C2410_UPLLCON) & S3C2412_PLLCON_OFF) ? "off":"on",
716 print_mhz(clk_get_rate(&clk_upll)),
717 print_mhz(clk_get_rate(&clk_usb_bus)));
718
719 /* register clocks from clock array */
720
721 clkp = init_clocks;
722 for (ptr = 0; ptr < ARRAY_SIZE(init_clocks); ptr++, clkp++) {
723 /* ensure that we note the clock state */
724
725 clkp->usage = clkcon & clkp->ctrlbit ? 1 : 0;
726
727 ret = s3c24xx_register_clock(clkp);
728 if (ret < 0) {
729 printk(KERN_ERR "Failed to register clock %s (%d)\n",
730 clkp->name, ret);
731 }
732 }
733
734 /* We must be careful disabling the clocks we are not intending to
735 * be using at boot time, as subsystems such as the LCD which do
736 * their own DMA requests to the bus can cause the system to lockup
737 * if they where in the middle of requesting bus access.
738 *
739 * Disabling the LCD clock if the LCD is active is very dangerous,
740 * and therefore the bootloader should be careful to not enable
741 * the LCD clock if it is not needed.
742 */
743
744 /* install (and disable) the clocks we do not need immediately */
745
746 clkp = init_clocks_disable;
747 for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) {
748
749 ret = s3c24xx_register_clock(clkp);
750 if (ret < 0) {
751 printk(KERN_ERR "Failed to register clock %s (%d)\n",
752 clkp->name, ret);
753 }
754
755 s3c2412_clkcon_enable(clkp, 0);
756 }
757
758 clkdev_add_table(s3c2412_clk_lookup, ARRAY_SIZE(s3c2412_clk_lookup));
759 return 0;
760}
diff --git a/arch/arm/mach-s3c24xx/common.c b/arch/arm/mach-s3c24xx/common.c
index 412ca006fcce..ad5b76bf4d51 100644
--- a/arch/arm/mach-s3c24xx/common.c
+++ b/arch/arm/mach-s3c24xx/common.c
@@ -127,7 +127,6 @@ static struct cpu_table cpu_ids[] __initdata = {
127 .idcode = 0x32412001, 127 .idcode = 0x32412001,
128 .idmask = 0xffffffff, 128 .idmask = 0xffffffff,
129 .map_io = s3c2412_map_io, 129 .map_io = s3c2412_map_io,
130 .init_clocks = s3c2412_init_clocks,
131 .init_uarts = s3c2412_init_uarts, 130 .init_uarts = s3c2412_init_uarts,
132 .init = s3c2412_init, 131 .init = s3c2412_init,
133 .name = name_s3c2412, 132 .name = name_s3c2412,
@@ -136,7 +135,6 @@ static struct cpu_table cpu_ids[] __initdata = {
136 .idcode = 0x32412003, 135 .idcode = 0x32412003,
137 .idmask = 0xffffffff, 136 .idmask = 0xffffffff,
138 .map_io = s3c2412_map_io, 137 .map_io = s3c2412_map_io,
139 .init_clocks = s3c2412_init_clocks,
140 .init_uarts = s3c2412_init_uarts, 138 .init_uarts = s3c2412_init_uarts,
141 .init = s3c2412_init, 139 .init = s3c2412_init,
142 .name = name_s3c2412, 140 .name = name_s3c2412,
@@ -535,6 +533,13 @@ struct platform_device s3c2443_device_dma = {
535}; 533};
536#endif 534#endif
537 535
536#ifdef CONFIG_CPU_S3C2412
537void __init s3c2412_init_clocks(int xtal)
538{
539 s3c2412_common_clk_init(NULL, xtal, 0, S3C24XX_VA_CLKPWR);
540}
541#endif
542
538#ifdef CONFIG_CPU_S3C2416 543#ifdef CONFIG_CPU_S3C2416
539void __init s3c2416_init_clocks(int xtal) 544void __init s3c2416_init_clocks(int xtal)
540{ 545{
diff --git a/arch/arm/mach-s3c24xx/common.h b/arch/arm/mach-s3c24xx/common.h
index d7323f16427f..3fade6d796f9 100644
--- a/arch/arm/mach-s3c24xx/common.h
+++ b/arch/arm/mach-s3c24xx/common.h
@@ -114,6 +114,10 @@ extern struct platform_device s3c2412_device_dma;
114extern struct platform_device s3c2440_device_dma; 114extern struct platform_device s3c2440_device_dma;
115extern struct platform_device s3c2443_device_dma; 115extern struct platform_device s3c2443_device_dma;
116 116
117#ifdef CONFIG_S3C2412_COMMON_CLK
118void __init s3c2412_common_clk_init(struct device_node *np, unsigned long xti_f,
119 unsigned long ext_f, void __iomem *reg_base);
120#endif
117#ifdef CONFIG_S3C2443_COMMON_CLK 121#ifdef CONFIG_S3C2443_COMMON_CLK
118void __init s3c2443_common_clk_init(struct device_node *np, unsigned long xti_f, 122void __init s3c2443_common_clk_init(struct device_node *np, unsigned long xti_f,
119 int current_soc, 123 int current_soc,
diff --git a/arch/arm/mach-s3c24xx/mach-jive.c b/arch/arm/mach-s3c24xx/mach-jive.c
index 5faa7239e7d6..e81ea82c55f9 100644
--- a/arch/arm/mach-s3c24xx/mach-jive.c
+++ b/arch/arm/mach-s3c24xx/mach-jive.c
@@ -507,11 +507,16 @@ static struct syscore_ops jive_pm_syscore_ops = {
507static void __init jive_map_io(void) 507static void __init jive_map_io(void)
508{ 508{
509 s3c24xx_init_io(jive_iodesc, ARRAY_SIZE(jive_iodesc)); 509 s3c24xx_init_io(jive_iodesc, ARRAY_SIZE(jive_iodesc));
510 s3c24xx_init_clocks(12000000);
511 s3c24xx_init_uarts(jive_uartcfgs, ARRAY_SIZE(jive_uartcfgs)); 510 s3c24xx_init_uarts(jive_uartcfgs, ARRAY_SIZE(jive_uartcfgs));
512 samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4); 511 samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
513} 512}
514 513
514static void __init jive_init_time(void)
515{
516 s3c2412_init_clocks(12000000);
517 samsung_timer_init();
518}
519
515static void jive_power_off(void) 520static void jive_power_off(void)
516{ 521{
517 printk(KERN_INFO "powering system down...\n"); 522 printk(KERN_INFO "powering system down...\n");
@@ -665,6 +670,6 @@ MACHINE_START(JIVE, "JIVE")
665 .init_irq = s3c2412_init_irq, 670 .init_irq = s3c2412_init_irq,
666 .map_io = jive_map_io, 671 .map_io = jive_map_io,
667 .init_machine = jive_machine_init, 672 .init_machine = jive_machine_init,
668 .init_time = samsung_timer_init, 673 .init_time = jive_init_time,
669 .restart = s3c2412_restart, 674 .restart = s3c2412_restart,
670MACHINE_END 675MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-smdk2413.c b/arch/arm/mach-s3c24xx/mach-smdk2413.c
index 233fe52d2015..a38f8a049e22 100644
--- a/arch/arm/mach-s3c24xx/mach-smdk2413.c
+++ b/arch/arm/mach-s3c24xx/mach-smdk2413.c
@@ -106,11 +106,16 @@ static void __init smdk2413_fixup(struct tag *tags, char **cmdline,
106static void __init smdk2413_map_io(void) 106static void __init smdk2413_map_io(void)
107{ 107{
108 s3c24xx_init_io(smdk2413_iodesc, ARRAY_SIZE(smdk2413_iodesc)); 108 s3c24xx_init_io(smdk2413_iodesc, ARRAY_SIZE(smdk2413_iodesc));
109 s3c24xx_init_clocks(12000000);
110 s3c24xx_init_uarts(smdk2413_uartcfgs, ARRAY_SIZE(smdk2413_uartcfgs)); 109 s3c24xx_init_uarts(smdk2413_uartcfgs, ARRAY_SIZE(smdk2413_uartcfgs));
111 samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4); 110 samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
112} 111}
113 112
113static void __init smdk2413_init_time(void)
114{
115 s3c2412_init_clocks(12000000);
116 samsung_timer_init();
117}
118
114static void __init smdk2413_machine_init(void) 119static void __init smdk2413_machine_init(void)
115{ /* Turn off suspend on both USB ports, and switch the 120{ /* Turn off suspend on both USB ports, and switch the
116 * selectable USB port to USB device mode. */ 121 * selectable USB port to USB device mode. */
@@ -159,6 +164,6 @@ MACHINE_START(SMDK2413, "SMDK2413")
159 .init_irq = s3c2412_init_irq, 164 .init_irq = s3c2412_init_irq,
160 .map_io = smdk2413_map_io, 165 .map_io = smdk2413_map_io,
161 .init_machine = smdk2413_machine_init, 166 .init_machine = smdk2413_machine_init,
162 .init_time = samsung_timer_init, 167 .init_time = smdk2413_init_time,
163 .restart = s3c2412_restart, 168 .restart = s3c2412_restart,
164MACHINE_END 169MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-vstms.c b/arch/arm/mach-s3c24xx/mach-vstms.c
index 40868c0e0a68..6b706c915387 100644
--- a/arch/arm/mach-s3c24xx/mach-vstms.c
+++ b/arch/arm/mach-s3c24xx/mach-vstms.c
@@ -142,11 +142,16 @@ static void __init vstms_fixup(struct tag *tags, char **cmdline,
142static void __init vstms_map_io(void) 142static void __init vstms_map_io(void)
143{ 143{
144 s3c24xx_init_io(vstms_iodesc, ARRAY_SIZE(vstms_iodesc)); 144 s3c24xx_init_io(vstms_iodesc, ARRAY_SIZE(vstms_iodesc));
145 s3c24xx_init_clocks(12000000);
146 s3c24xx_init_uarts(vstms_uartcfgs, ARRAY_SIZE(vstms_uartcfgs)); 145 s3c24xx_init_uarts(vstms_uartcfgs, ARRAY_SIZE(vstms_uartcfgs));
147 samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4); 146 samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
148} 147}
149 148
149static void __init vstms_init_time(void)
150{
151 s3c2412_init_clocks(12000000);
152 samsung_timer_init();
153}
154
150static void __init vstms_init(void) 155static void __init vstms_init(void)
151{ 156{
152 s3c_i2c0_set_platdata(NULL); 157 s3c_i2c0_set_platdata(NULL);
@@ -162,6 +167,6 @@ MACHINE_START(VSTMS, "VSTMS")
162 .init_irq = s3c2412_init_irq, 167 .init_irq = s3c2412_init_irq,
163 .init_machine = vstms_init, 168 .init_machine = vstms_init,
164 .map_io = vstms_map_io, 169 .map_io = vstms_map_io,
165 .init_time = samsung_timer_init, 170 .init_time = vstms_init_time,
166 .restart = s3c2412_restart, 171 .restart = s3c2412_restart,
167MACHINE_END 172MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/s3c2412.c b/arch/arm/mach-s3c24xx/s3c2412.c
index 657cbaca80ac..d49f52fbc842 100644
--- a/arch/arm/mach-s3c24xx/s3c2412.c
+++ b/arch/arm/mach-s3c24xx/s3c2412.c
@@ -173,49 +173,6 @@ void __init s3c2412_map_io(void)
173 173
174void __init_or_cpufreq s3c2412_setup_clocks(void) 174void __init_or_cpufreq s3c2412_setup_clocks(void)
175{ 175{
176 struct clk *xtal_clk;
177 unsigned long tmp;
178 unsigned long xtal;
179 unsigned long fclk;
180 unsigned long hclk;
181 unsigned long pclk;
182
183 xtal_clk = clk_get(NULL, "xtal");
184 xtal = clk_get_rate(xtal_clk);
185 clk_put(xtal_clk);
186
187 /* now we've got our machine bits initialised, work out what
188 * clocks we've got */
189
190 fclk = s3c24xx_get_pll(__raw_readl(S3C2410_MPLLCON), xtal * 2);
191
192 clk_mpll.rate = fclk;
193
194 tmp = __raw_readl(S3C2410_CLKDIVN);
195
196 /* work out clock scalings */
197
198 hclk = fclk / ((tmp & S3C2412_CLKDIVN_HDIVN_MASK) + 1);
199 hclk /= ((tmp & S3C2412_CLKDIVN_ARMDIVN) ? 2 : 1);
200 pclk = hclk / ((tmp & S3C2412_CLKDIVN_PDIVN) ? 2 : 1);
201
202 /* print brieft summary of clocks, etc */
203
204 printk("S3C2412: core %ld.%03ld MHz, memory %ld.%03ld MHz, peripheral %ld.%03ld MHz\n",
205 print_mhz(fclk), print_mhz(hclk), print_mhz(pclk));
206
207 s3c24xx_setup_clocks(fclk, hclk, pclk);
208}
209
210void __init s3c2412_init_clocks(int xtal)
211{
212 /* initialise the clocks here, to allow other things like the
213 * console to use them
214 */
215
216 s3c24xx_register_baseclocks(xtal);
217 s3c2412_setup_clocks();
218 s3c2412_baseclk_add();
219} 176}
220 177
221/* need to register the subsystem before we actually register the device, and 178/* need to register the subsystem before we actually register the device, and
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-14 08:59:41 -0500