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| author | Linus Torvalds <torvalds@woody.linux-foundation.org> | 2007-05-08 15:07:28 -0400 |
|---|---|---|
| committer | Linus Torvalds <torvalds@woody.linux-foundation.org> | 2007-05-08 15:07:28 -0400 |
| commit | 36f021b579d195cdc5fa6f3e2bab198b4bf70643 (patch) | |
| tree | 96d3c97f5e5214d2aa7151c12a22a7eb345dbaa1 /arch | |
| parent | 215d06780d13fd7de629b02b61b7b7bf88ce5039 (diff) | |
| parent | 1d72acf91abb327e25137ad2e371c1a788b34e45 (diff) | |
Merge branch 'hwmon-for-linus' of git://jdelvare.pck.nerim.net/jdelvare-2.6
* 'hwmon-for-linus' of git://jdelvare.pck.nerim.net/jdelvare-2.6: (32 commits)
Use menuconfig objects - hwmon
hwmon/smsc47b397: Use dynamic sysfs callbacks
hwmon/smsc47b397: Convert to a platform driver
hwmon/w83781d: Deprecate W83627HF support
hwmon/w83781d: Use dynamic sysfs callbacks
hwmon/w83781d: Be less i2c_client-centric
hwmon/w83781d: Clean up conversion macros
hwmon/w83781d: No longer use i2c-isa
hwmon/ams: Do not print error on systems without apple motion sensor
hwmon/ams: Fix I2C read retry logic
hwmon: New AD7416, AD7417 and AD7418 driver
hwmon/coretemp: Add documentation
hwmon: New coretemp driver
i386: Use functions from library in msr driver
i386: Add safe variants of rdmsr_on_cpu and wrmsr_on_cpu
hwmon/lm75: Use dynamic sysfs callbacks
hwmon/lm78: Use dynamic sysfs callbacks
hwmon/lm78: Be less i2c_client-centric
hwmon/lm78: No longer use i2c-isa
hwmon: New max6650 driver
...
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/i386/kernel/msr.c | 106 | ||||
| -rw-r--r-- | arch/i386/lib/msr-on-cpu.c | 73 |
2 files changed, 71 insertions, 108 deletions
diff --git a/arch/i386/kernel/msr.c b/arch/i386/kernel/msr.c index bcaa6e9b6197..8cd0a91ce107 100644 --- a/arch/i386/kernel/msr.c +++ b/arch/i386/kernel/msr.c | |||
| @@ -45,104 +45,6 @@ | |||
| 45 | 45 | ||
| 46 | static struct class *msr_class; | 46 | static struct class *msr_class; |
| 47 | 47 | ||
| 48 | static inline int wrmsr_eio(u32 reg, u32 eax, u32 edx) | ||
| 49 | { | ||
| 50 | int err; | ||
| 51 | |||
| 52 | err = wrmsr_safe(reg, eax, edx); | ||
| 53 | if (err) | ||
| 54 | err = -EIO; | ||
| 55 | return err; | ||
| 56 | } | ||
| 57 | |||
| 58 | static inline int rdmsr_eio(u32 reg, u32 *eax, u32 *edx) | ||
| 59 | { | ||
| 60 | int err; | ||
| 61 | |||
| 62 | err = rdmsr_safe(reg, eax, edx); | ||
| 63 | if (err) | ||
| 64 | err = -EIO; | ||
| 65 | return err; | ||
| 66 | } | ||
| 67 | |||
| 68 | #ifdef CONFIG_SMP | ||
| 69 | |||
| 70 | struct msr_command { | ||
| 71 | int err; | ||
| 72 | u32 reg; | ||
| 73 | u32 data[2]; | ||
| 74 | }; | ||
| 75 | |||
| 76 | static void msr_smp_wrmsr(void *cmd_block) | ||
| 77 | { | ||
| 78 | struct msr_command *cmd = (struct msr_command *)cmd_block; | ||
| 79 | |||
| 80 | cmd->err = wrmsr_eio(cmd->reg, cmd->data[0], cmd->data[1]); | ||
| 81 | } | ||
| 82 | |||
| 83 | static void msr_smp_rdmsr(void *cmd_block) | ||
| 84 | { | ||
| 85 | struct msr_command *cmd = (struct msr_command *)cmd_block; | ||
| 86 | |||
| 87 | cmd->err = rdmsr_eio(cmd->reg, &cmd->data[0], &cmd->data[1]); | ||
| 88 | } | ||
| 89 | |||
| 90 | static inline int do_wrmsr(int cpu, u32 reg, u32 eax, u32 edx) | ||
| 91 | { | ||
| 92 | struct msr_command cmd; | ||
| 93 | int ret; | ||
| 94 | |||
| 95 | preempt_disable(); | ||
| 96 | if (cpu == smp_processor_id()) { | ||
| 97 | ret = wrmsr_eio(reg, eax, edx); | ||
| 98 | } else { | ||
| 99 | cmd.reg = reg; | ||
| 100 | cmd.data[0] = eax; | ||
| 101 | cmd.data[1] = edx; | ||
| 102 | |||
| 103 | smp_call_function_single(cpu, msr_smp_wrmsr, &cmd, 1, 1); | ||
| 104 | ret = cmd.err; | ||
| 105 | } | ||
| 106 | preempt_enable(); | ||
| 107 | return ret; | ||
| 108 | } | ||
| 109 | |||
| 110 | static inline int do_rdmsr(int cpu, u32 reg, u32 * eax, u32 * edx) | ||
| 111 | { | ||
| 112 | struct msr_command cmd; | ||
| 113 | int ret; | ||
| 114 | |||
| 115 | preempt_disable(); | ||
| 116 | if (cpu == smp_processor_id()) { | ||
| 117 | ret = rdmsr_eio(reg, eax, edx); | ||
| 118 | } else { | ||
| 119 | cmd.reg = reg; | ||
| 120 | |||
| 121 | smp_call_function_single(cpu, msr_smp_rdmsr, &cmd, 1, 1); | ||
| 122 | |||
| 123 | *eax = cmd.data[0]; | ||
| 124 | *edx = cmd.data[1]; | ||
| 125 | |||
| 126 | ret = cmd.err; | ||
| 127 | } | ||
| 128 | preempt_enable(); | ||
| 129 | return ret; | ||
| 130 | } | ||
| 131 | |||
| 132 | #else /* ! CONFIG_SMP */ | ||
| 133 | |||
| 134 | static inline int do_wrmsr(int cpu, u32 reg, u32 eax, u32 edx) | ||
| 135 | { | ||
| 136 | return wrmsr_eio(reg, eax, edx); | ||
| 137 | } | ||
| 138 | |||
| 139 | static inline int do_rdmsr(int cpu, u32 reg, u32 *eax, u32 *edx) | ||
| 140 | { | ||
| 141 | return rdmsr_eio(reg, eax, edx); | ||
| 142 | } | ||
| 143 | |||
| 144 | #endif /* ! CONFIG_SMP */ | ||
| 145 | |||
| 146 | static loff_t msr_seek(struct file *file, loff_t offset, int orig) | 48 | static loff_t msr_seek(struct file *file, loff_t offset, int orig) |
| 147 | { | 49 | { |
| 148 | loff_t ret = -EINVAL; | 50 | loff_t ret = -EINVAL; |
| @@ -174,9 +76,9 @@ static ssize_t msr_read(struct file *file, char __user * buf, | |||
| 174 | return -EINVAL; /* Invalid chunk size */ | 76 | return -EINVAL; /* Invalid chunk size */ |
| 175 | 77 | ||
| 176 | for (; count; count -= 8) { | 78 | for (; count; count -= 8) { |
| 177 | err = do_rdmsr(cpu, reg, &data[0], &data[1]); | 79 | err = rdmsr_safe_on_cpu(cpu, reg, &data[0], &data[1]); |
| 178 | if (err) | 80 | if (err) |
| 179 | return err; | 81 | return -EIO; |
| 180 | if (copy_to_user(tmp, &data, 8)) | 82 | if (copy_to_user(tmp, &data, 8)) |
| 181 | return -EFAULT; | 83 | return -EFAULT; |
| 182 | tmp += 2; | 84 | tmp += 2; |
| @@ -200,9 +102,9 @@ static ssize_t msr_write(struct file *file, const char __user *buf, | |||
| 200 | for (; count; count -= 8) { | 102 | for (; count; count -= 8) { |
| 201 | if (copy_from_user(&data, tmp, 8)) | 103 | if (copy_from_user(&data, tmp, 8)) |
| 202 | return -EFAULT; | 104 | return -EFAULT; |
| 203 | err = do_wrmsr(cpu, reg, data[0], data[1]); | 105 | err = wrmsr_safe_on_cpu(cpu, reg, data[0], data[1]); |
| 204 | if (err) | 106 | if (err) |
| 205 | return err; | 107 | return -EIO; |
| 206 | tmp += 2; | 108 | tmp += 2; |
| 207 | } | 109 | } |
| 208 | 110 | ||
diff --git a/arch/i386/lib/msr-on-cpu.c b/arch/i386/lib/msr-on-cpu.c index 1c46bda409ff..7767962f25d3 100644 --- a/arch/i386/lib/msr-on-cpu.c +++ b/arch/i386/lib/msr-on-cpu.c | |||
| @@ -6,6 +6,7 @@ | |||
| 6 | struct msr_info { | 6 | struct msr_info { |
| 7 | u32 msr_no; | 7 | u32 msr_no; |
| 8 | u32 l, h; | 8 | u32 l, h; |
| 9 | int err; | ||
| 9 | }; | 10 | }; |
| 10 | 11 | ||
| 11 | static void __rdmsr_on_cpu(void *info) | 12 | static void __rdmsr_on_cpu(void *info) |
| @@ -15,20 +16,38 @@ static void __rdmsr_on_cpu(void *info) | |||
| 15 | rdmsr(rv->msr_no, rv->l, rv->h); | 16 | rdmsr(rv->msr_no, rv->l, rv->h); |
| 16 | } | 17 | } |
| 17 | 18 | ||
| 18 | void rdmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h) | 19 | static void __rdmsr_safe_on_cpu(void *info) |
| 19 | { | 20 | { |
| 21 | struct msr_info *rv = info; | ||
| 22 | |||
| 23 | rv->err = rdmsr_safe(rv->msr_no, &rv->l, &rv->h); | ||
| 24 | } | ||
| 25 | |||
| 26 | static int _rdmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h, int safe) | ||
| 27 | { | ||
| 28 | int err = 0; | ||
| 20 | preempt_disable(); | 29 | preempt_disable(); |
| 21 | if (smp_processor_id() == cpu) | 30 | if (smp_processor_id() == cpu) |
| 22 | rdmsr(msr_no, *l, *h); | 31 | if (safe) |
| 32 | err = rdmsr_safe(msr_no, l, h); | ||
| 33 | else | ||
| 34 | rdmsr(msr_no, *l, *h); | ||
| 23 | else { | 35 | else { |
| 24 | struct msr_info rv; | 36 | struct msr_info rv; |
| 25 | 37 | ||
| 26 | rv.msr_no = msr_no; | 38 | rv.msr_no = msr_no; |
| 27 | smp_call_function_single(cpu, __rdmsr_on_cpu, &rv, 0, 1); | 39 | if (safe) { |
| 40 | smp_call_function_single(cpu, __rdmsr_safe_on_cpu, | ||
| 41 | &rv, 0, 1); | ||
| 42 | err = rv.err; | ||
| 43 | } else { | ||
| 44 | smp_call_function_single(cpu, __rdmsr_on_cpu, &rv, 0, 1); | ||
| 45 | } | ||
| 28 | *l = rv.l; | 46 | *l = rv.l; |
| 29 | *h = rv.h; | 47 | *h = rv.h; |
| 30 | } | 48 | } |
| 31 | preempt_enable(); | 49 | preempt_enable(); |
| 50 | return err; | ||
| 32 | } | 51 | } |
| 33 | 52 | ||
| 34 | static void __wrmsr_on_cpu(void *info) | 53 | static void __wrmsr_on_cpu(void *info) |
| @@ -38,21 +57,63 @@ static void __wrmsr_on_cpu(void *info) | |||
| 38 | wrmsr(rv->msr_no, rv->l, rv->h); | 57 | wrmsr(rv->msr_no, rv->l, rv->h); |
| 39 | } | 58 | } |
| 40 | 59 | ||
| 41 | void wrmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h) | 60 | static void __wrmsr_safe_on_cpu(void *info) |
| 42 | { | 61 | { |
| 62 | struct msr_info *rv = info; | ||
| 63 | |||
| 64 | rv->err = wrmsr_safe(rv->msr_no, rv->l, rv->h); | ||
| 65 | } | ||
| 66 | |||
| 67 | static int _wrmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h, int safe) | ||
| 68 | { | ||
| 69 | int err = 0; | ||
| 43 | preempt_disable(); | 70 | preempt_disable(); |
| 44 | if (smp_processor_id() == cpu) | 71 | if (smp_processor_id() == cpu) |
| 45 | wrmsr(msr_no, l, h); | 72 | if (safe) |
| 73 | err = wrmsr_safe(msr_no, l, h); | ||
| 74 | else | ||
| 75 | wrmsr(msr_no, l, h); | ||
| 46 | else { | 76 | else { |
| 47 | struct msr_info rv; | 77 | struct msr_info rv; |
| 48 | 78 | ||
| 49 | rv.msr_no = msr_no; | 79 | rv.msr_no = msr_no; |
| 50 | rv.l = l; | 80 | rv.l = l; |
| 51 | rv.h = h; | 81 | rv.h = h; |
| 52 | smp_call_function_single(cpu, __wrmsr_on_cpu, &rv, 0, 1); | 82 | if (safe) { |
| 83 | smp_call_function_single(cpu, __wrmsr_safe_on_cpu, | ||
| 84 | &rv, 0, 1); | ||
| 85 | err = rv.err; | ||
| 86 | } else { | ||
| 87 | smp_call_function_single(cpu, __wrmsr_on_cpu, &rv, 0, 1); | ||
| 88 | } | ||
| 53 | } | 89 | } |
| 54 | preempt_enable(); | 90 | preempt_enable(); |
| 91 | return err; | ||
| 92 | } | ||
| 93 | |||
| 94 | void wrmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h) | ||
| 95 | { | ||
| 96 | _wrmsr_on_cpu(cpu, msr_no, l, h, 0); | ||
| 97 | } | ||
| 98 | |||
| 99 | void rdmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h) | ||
| 100 | { | ||
| 101 | _rdmsr_on_cpu(cpu, msr_no, l, h, 0); | ||
| 102 | } | ||
| 103 | |||
| 104 | /* These "safe" variants are slower and should be used when the target MSR | ||
| 105 | may not actually exist. */ | ||
| 106 | int wrmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h) | ||
| 107 | { | ||
| 108 | return _wrmsr_on_cpu(cpu, msr_no, l, h, 1); | ||
| 109 | } | ||
| 110 | |||
| 111 | int rdmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h) | ||
| 112 | { | ||
| 113 | return _rdmsr_on_cpu(cpu, msr_no, l, h, 1); | ||
| 55 | } | 114 | } |
| 56 | 115 | ||
| 57 | EXPORT_SYMBOL(rdmsr_on_cpu); | 116 | EXPORT_SYMBOL(rdmsr_on_cpu); |
| 58 | EXPORT_SYMBOL(wrmsr_on_cpu); | 117 | EXPORT_SYMBOL(wrmsr_on_cpu); |
| 118 | EXPORT_SYMBOL(rdmsr_safe_on_cpu); | ||
| 119 | EXPORT_SYMBOL(wrmsr_safe_on_cpu); | ||
