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authorDavid Daney <david.daney@cavium.com>2013-08-19 15:10:35 -0400
committerRalf Baechle <ralf@linux-mips.org>2013-08-26 09:33:40 -0400
commit36b0f79b3087f4e4863ce1253df605e809e74531 (patch)
treed1c13e94348bb76242d3e47e899b78a27d82dfb9 /arch
parent43d309390349010cd384ab5a0feebf16b03b9a94 (diff)
MIPS: Remove unreachable break statements from cp1emu.c
There were many cases of: return something; break; All those break statements are unreachable and thus redundant. Signed-off-by: David Daney <david.daney@cavium.com> Reviewed-by: Aaro Koskinen <aaro.koskinen@iki.fi> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5727/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch')
-rw-r--r--arch/mips/math-emu/cp1emu.c27
1 files changed, 0 insertions, 27 deletions
diff --git a/arch/mips/math-emu/cp1emu.c b/arch/mips/math-emu/cp1emu.c
index 46048d24328c..efe008846ed0 100644
--- a/arch/mips/math-emu/cp1emu.c
+++ b/arch/mips/math-emu/cp1emu.c
@@ -436,7 +436,6 @@ static int microMIPS32_to_MIPS32(union mips_instruction *insn_ptr)
436 break; 436 break;
437 default: 437 default:
438 return SIGILL; 438 return SIGILL;
439 break;
440 } 439 }
441 break; 440 break;
442 case mm_32f_74_op: /* c.cond.fmt */ 441 case mm_32f_74_op: /* c.cond.fmt */
@@ -451,12 +450,10 @@ static int microMIPS32_to_MIPS32(union mips_instruction *insn_ptr)
451 break; 450 break;
452 default: 451 default:
453 return SIGILL; 452 return SIGILL;
454 break;
455 } 453 }
456 break; 454 break;
457 default: 455 default:
458 return SIGILL; 456 return SIGILL;
459 break;
460 } 457 }
461 458
462 *insn_ptr = mips32_insn; 459 *insn_ptr = mips32_insn;
@@ -491,7 +488,6 @@ int mm_isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn,
491 dec_insn.next_pc_inc; 488 dec_insn.next_pc_inc;
492 *contpc = regs->regs[insn.mm_i_format.rs]; 489 *contpc = regs->regs[insn.mm_i_format.rs];
493 return 1; 490 return 1;
494 break;
495 } 491 }
496 } 492 }
497 break; 493 break;
@@ -513,7 +509,6 @@ int mm_isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn,
513 dec_insn.pc_inc + 509 dec_insn.pc_inc +
514 dec_insn.next_pc_inc; 510 dec_insn.next_pc_inc;
515 return 1; 511 return 1;
516 break;
517 case mm_bgezals_op: 512 case mm_bgezals_op:
518 case mm_bgezal_op: 513 case mm_bgezal_op:
519 regs->regs[31] = regs->cp0_epc + 514 regs->regs[31] = regs->cp0_epc +
@@ -530,7 +525,6 @@ int mm_isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn,
530 dec_insn.pc_inc + 525 dec_insn.pc_inc +
531 dec_insn.next_pc_inc; 526 dec_insn.next_pc_inc;
532 return 1; 527 return 1;
533 break;
534 case mm_blez_op: 528 case mm_blez_op:
535 if ((long)regs->regs[insn.mm_i_format.rs] <= 0) 529 if ((long)regs->regs[insn.mm_i_format.rs] <= 0)
536 *contpc = regs->cp0_epc + 530 *contpc = regs->cp0_epc +
@@ -541,7 +535,6 @@ int mm_isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn,
541 dec_insn.pc_inc + 535 dec_insn.pc_inc +
542 dec_insn.next_pc_inc; 536 dec_insn.next_pc_inc;
543 return 1; 537 return 1;
544 break;
545 case mm_bgtz_op: 538 case mm_bgtz_op:
546 if ((long)regs->regs[insn.mm_i_format.rs] <= 0) 539 if ((long)regs->regs[insn.mm_i_format.rs] <= 0)
547 *contpc = regs->cp0_epc + 540 *contpc = regs->cp0_epc +
@@ -552,7 +545,6 @@ int mm_isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn,
552 dec_insn.pc_inc + 545 dec_insn.pc_inc +
553 dec_insn.next_pc_inc; 546 dec_insn.next_pc_inc;
554 return 1; 547 return 1;
555 break;
556 case mm_bc2f_op: 548 case mm_bc2f_op:
557 case mm_bc1f_op: 549 case mm_bc1f_op:
558 bc_false = 1; 550 bc_false = 1;
@@ -580,7 +572,6 @@ int mm_isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn,
580 *contpc = regs->cp0_epc + 572 *contpc = regs->cp0_epc +
581 dec_insn.pc_inc + dec_insn.next_pc_inc; 573 dec_insn.pc_inc + dec_insn.next_pc_inc;
582 return 1; 574 return 1;
583 break;
584 } 575 }
585 break; 576 break;
586 case mm_pool16c_op: 577 case mm_pool16c_op:
@@ -593,7 +584,6 @@ int mm_isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn,
593 case mm_jr16_op: 584 case mm_jr16_op:
594 *contpc = regs->regs[insn.mm_i_format.rs]; 585 *contpc = regs->regs[insn.mm_i_format.rs];
595 return 1; 586 return 1;
596 break;
597 } 587 }
598 break; 588 break;
599 case mm_beqz16_op: 589 case mm_beqz16_op:
@@ -605,7 +595,6 @@ int mm_isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn,
605 *contpc = regs->cp0_epc + 595 *contpc = regs->cp0_epc +
606 dec_insn.pc_inc + dec_insn.next_pc_inc; 596 dec_insn.pc_inc + dec_insn.next_pc_inc;
607 return 1; 597 return 1;
608 break;
609 case mm_bnez16_op: 598 case mm_bnez16_op:
610 if ((long)regs->regs[reg16to32map[insn.mm_b1_format.rs]] != 0) 599 if ((long)regs->regs[reg16to32map[insn.mm_b1_format.rs]] != 0)
611 *contpc = regs->cp0_epc + 600 *contpc = regs->cp0_epc +
@@ -615,12 +604,10 @@ int mm_isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn,
615 *contpc = regs->cp0_epc + 604 *contpc = regs->cp0_epc +
616 dec_insn.pc_inc + dec_insn.next_pc_inc; 605 dec_insn.pc_inc + dec_insn.next_pc_inc;
617 return 1; 606 return 1;
618 break;
619 case mm_b16_op: 607 case mm_b16_op:
620 *contpc = regs->cp0_epc + dec_insn.pc_inc + 608 *contpc = regs->cp0_epc + dec_insn.pc_inc +
621 (insn.mm_b0_format.simmediate << 1); 609 (insn.mm_b0_format.simmediate << 1);
622 return 1; 610 return 1;
623 break;
624 case mm_beq32_op: 611 case mm_beq32_op:
625 if (regs->regs[insn.mm_i_format.rs] == 612 if (regs->regs[insn.mm_i_format.rs] ==
626 regs->regs[insn.mm_i_format.rt]) 613 regs->regs[insn.mm_i_format.rt])
@@ -632,7 +619,6 @@ int mm_isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn,
632 dec_insn.pc_inc + 619 dec_insn.pc_inc +
633 dec_insn.next_pc_inc; 620 dec_insn.next_pc_inc;
634 return 1; 621 return 1;
635 break;
636 case mm_bne32_op: 622 case mm_bne32_op:
637 if (regs->regs[insn.mm_i_format.rs] != 623 if (regs->regs[insn.mm_i_format.rs] !=
638 regs->regs[insn.mm_i_format.rt]) 624 regs->regs[insn.mm_i_format.rt])
@@ -643,7 +629,6 @@ int mm_isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn,
643 *contpc = regs->cp0_epc + 629 *contpc = regs->cp0_epc +
644 dec_insn.pc_inc + dec_insn.next_pc_inc; 630 dec_insn.pc_inc + dec_insn.next_pc_inc;
645 return 1; 631 return 1;
646 break;
647 case mm_jalx32_op: 632 case mm_jalx32_op:
648 regs->regs[31] = regs->cp0_epc + 633 regs->regs[31] = regs->cp0_epc +
649 dec_insn.pc_inc + dec_insn.next_pc_inc; 634 dec_insn.pc_inc + dec_insn.next_pc_inc;
@@ -652,7 +637,6 @@ int mm_isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn,
652 *contpc <<= 28; 637 *contpc <<= 28;
653 *contpc |= (insn.j_format.target << 2); 638 *contpc |= (insn.j_format.target << 2);
654 return 1; 639 return 1;
655 break;
656 case mm_jals32_op: 640 case mm_jals32_op:
657 case mm_jal32_op: 641 case mm_jal32_op:
658 regs->regs[31] = regs->cp0_epc + 642 regs->regs[31] = regs->cp0_epc +
@@ -665,7 +649,6 @@ int mm_isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn,
665 *contpc |= (insn.j_format.target << 1); 649 *contpc |= (insn.j_format.target << 1);
666 set_isa16_mode(*contpc); 650 set_isa16_mode(*contpc);
667 return 1; 651 return 1;
668 break;
669 } 652 }
670 return 0; 653 return 0;
671} 654}
@@ -694,7 +677,6 @@ static int isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn,
694 case jr_op: 677 case jr_op:
695 *contpc = regs->regs[insn.r_format.rs]; 678 *contpc = regs->regs[insn.r_format.rs];
696 return 1; 679 return 1;
697 break;
698 } 680 }
699 break; 681 break;
700 case bcond_op: 682 case bcond_op:
@@ -716,7 +698,6 @@ static int isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn,
716 dec_insn.pc_inc + 698 dec_insn.pc_inc +
717 dec_insn.next_pc_inc; 699 dec_insn.next_pc_inc;
718 return 1; 700 return 1;
719 break;
720 case bgezal_op: 701 case bgezal_op:
721 case bgezall_op: 702 case bgezall_op:
722 regs->regs[31] = regs->cp0_epc + 703 regs->regs[31] = regs->cp0_epc +
@@ -734,7 +715,6 @@ static int isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn,
734 dec_insn.pc_inc + 715 dec_insn.pc_inc +
735 dec_insn.next_pc_inc; 716 dec_insn.next_pc_inc;
736 return 1; 717 return 1;
737 break;
738 } 718 }
739 break; 719 break;
740 case jalx_op: 720 case jalx_op:
@@ -752,7 +732,6 @@ static int isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn,
752 /* Set microMIPS mode bit: XOR for jalx. */ 732 /* Set microMIPS mode bit: XOR for jalx. */
753 *contpc ^= bit; 733 *contpc ^= bit;
754 return 1; 734 return 1;
755 break;
756 case beq_op: 735 case beq_op:
757 case beql_op: 736 case beql_op:
758 if (regs->regs[insn.i_format.rs] == 737 if (regs->regs[insn.i_format.rs] ==
@@ -765,7 +744,6 @@ static int isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn,
765 dec_insn.pc_inc + 744 dec_insn.pc_inc +
766 dec_insn.next_pc_inc; 745 dec_insn.next_pc_inc;
767 return 1; 746 return 1;
768 break;
769 case bne_op: 747 case bne_op:
770 case bnel_op: 748 case bnel_op:
771 if (regs->regs[insn.i_format.rs] != 749 if (regs->regs[insn.i_format.rs] !=
@@ -778,7 +756,6 @@ static int isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn,
778 dec_insn.pc_inc + 756 dec_insn.pc_inc +
779 dec_insn.next_pc_inc; 757 dec_insn.next_pc_inc;
780 return 1; 758 return 1;
781 break;
782 case blez_op: 759 case blez_op:
783 case blezl_op: 760 case blezl_op:
784 if ((long)regs->regs[insn.i_format.rs] <= 0) 761 if ((long)regs->regs[insn.i_format.rs] <= 0)
@@ -790,7 +767,6 @@ static int isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn,
790 dec_insn.pc_inc + 767 dec_insn.pc_inc +
791 dec_insn.next_pc_inc; 768 dec_insn.next_pc_inc;
792 return 1; 769 return 1;
793 break;
794 case bgtz_op: 770 case bgtz_op:
795 case bgtzl_op: 771 case bgtzl_op:
796 if ((long)regs->regs[insn.i_format.rs] > 0) 772 if ((long)regs->regs[insn.i_format.rs] > 0)
@@ -802,7 +778,6 @@ static int isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn,
802 dec_insn.pc_inc + 778 dec_insn.pc_inc +
803 dec_insn.next_pc_inc; 779 dec_insn.next_pc_inc;
804 return 1; 780 return 1;
805 break;
806#ifdef CONFIG_CPU_CAVIUM_OCTEON 781#ifdef CONFIG_CPU_CAVIUM_OCTEON
807 case lwc2_op: /* This is bbit0 on Octeon */ 782 case lwc2_op: /* This is bbit0 on Octeon */
808 if ((regs->regs[insn.i_format.rs] & (1ull<<insn.i_format.rt)) == 0) 783 if ((regs->regs[insn.i_format.rs] & (1ull<<insn.i_format.rt)) == 0)
@@ -856,7 +831,6 @@ static int isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn,
856 dec_insn.pc_inc + 831 dec_insn.pc_inc +
857 dec_insn.next_pc_inc; 832 dec_insn.next_pc_inc;
858 return 1; 833 return 1;
859 break;
860 case 1: /* bc1t */ 834 case 1: /* bc1t */
861 case 3: /* bc1tl */ 835 case 3: /* bc1tl */
862 if (fcr31 & (1 << bit)) 836 if (fcr31 & (1 << bit))
@@ -868,7 +842,6 @@ static int isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn,
868 dec_insn.pc_inc + 842 dec_insn.pc_inc +
869 dec_insn.next_pc_inc; 843 dec_insn.next_pc_inc;
870 return 1; 844 return 1;
871 break;
872 } 845 }
873 } 846 }
874 break; 847 break;
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-26 15:52:23 -0500