diff options
author | Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> | 2011-10-16 06:17:09 -0400 |
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committer | Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> | 2011-11-28 09:50:37 -0500 |
commit | 2f5893cf42ca10a1eb73bc527e2198847f4d0a79 (patch) | |
tree | e575202f0abde6fb8fa014e6346825b952fefb9b /arch | |
parent | caca6a03d365883564885f2c1da3e88dcf65d139 (diff) |
ARM: at91: define CLOCK_TICK_RATE to bogus value except A91X40
We have a clocksource which renders CLOCK_TICK_RATE useless. Define
it to a bogus value to get rid of some ifdeffery.
use local LATCH for at91rm9200 timer
but keep it for A91X40 as we do not use a clocksource
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Cc: Nicolas Ferre <nicolas.ferre@atmel.com>
Diffstat (limited to 'arch')
-rw-r--r-- | arch/arm/mach-at91/at91rm9200_time.c | 8 | ||||
-rw-r--r-- | arch/arm/mach-at91/include/mach/timex.h | 65 |
2 files changed, 10 insertions, 63 deletions
diff --git a/arch/arm/mach-at91/at91rm9200_time.c b/arch/arm/mach-at91/at91rm9200_time.c index 1dd69c85dfec..a028cdf8f974 100644 --- a/arch/arm/mach-at91/at91rm9200_time.c +++ b/arch/arm/mach-at91/at91rm9200_time.c | |||
@@ -32,6 +32,8 @@ static unsigned long last_crtr; | |||
32 | static u32 irqmask; | 32 | static u32 irqmask; |
33 | static struct clock_event_device clkevt; | 33 | static struct clock_event_device clkevt; |
34 | 34 | ||
35 | #define RM9200_TIMER_LATCH ((AT91_SLOW_CLOCK + HZ/2) / HZ) | ||
36 | |||
35 | /* | 37 | /* |
36 | * The ST_CRTR is updated asynchronously to the master clock ... but | 38 | * The ST_CRTR is updated asynchronously to the master clock ... but |
37 | * the updates as seen by the CPU don't seem to be strictly monotonic. | 39 | * the updates as seen by the CPU don't seem to be strictly monotonic. |
@@ -74,8 +76,8 @@ static irqreturn_t at91rm9200_timer_interrupt(int irq, void *dev_id) | |||
74 | if (sr & AT91_ST_PITS) { | 76 | if (sr & AT91_ST_PITS) { |
75 | u32 crtr = read_CRTR(); | 77 | u32 crtr = read_CRTR(); |
76 | 78 | ||
77 | while (((crtr - last_crtr) & AT91_ST_CRTV) >= LATCH) { | 79 | while (((crtr - last_crtr) & AT91_ST_CRTV) >= RM9200_TIMER_LATCH) { |
78 | last_crtr += LATCH; | 80 | last_crtr += RM9200_TIMER_LATCH; |
79 | clkevt.event_handler(&clkevt); | 81 | clkevt.event_handler(&clkevt); |
80 | } | 82 | } |
81 | return IRQ_HANDLED; | 83 | return IRQ_HANDLED; |
@@ -116,7 +118,7 @@ clkevt32k_mode(enum clock_event_mode mode, struct clock_event_device *dev) | |||
116 | case CLOCK_EVT_MODE_PERIODIC: | 118 | case CLOCK_EVT_MODE_PERIODIC: |
117 | /* PIT for periodic irqs; fixed rate of 1/HZ */ | 119 | /* PIT for periodic irqs; fixed rate of 1/HZ */ |
118 | irqmask = AT91_ST_PITS; | 120 | irqmask = AT91_ST_PITS; |
119 | at91_sys_write(AT91_ST_PIMR, LATCH); | 121 | at91_sys_write(AT91_ST_PIMR, RM9200_TIMER_LATCH); |
120 | break; | 122 | break; |
121 | case CLOCK_EVT_MODE_ONESHOT: | 123 | case CLOCK_EVT_MODE_ONESHOT: |
122 | /* ALM for oneshot irqs, set by next_event() | 124 | /* ALM for oneshot irqs, set by next_event() |
diff --git a/arch/arm/mach-at91/include/mach/timex.h b/arch/arm/mach-at91/include/mach/timex.h index 85820ad801cc..5e917a66edd7 100644 --- a/arch/arm/mach-at91/include/mach/timex.h +++ b/arch/arm/mach-at91/include/mach/timex.h | |||
@@ -23,70 +23,15 @@ | |||
23 | 23 | ||
24 | #include <mach/hardware.h> | 24 | #include <mach/hardware.h> |
25 | 25 | ||
26 | #if defined(CONFIG_ARCH_AT91RM9200) | 26 | #ifdef CONFIG_ARCH_AT91X40 |
27 | 27 | ||
28 | #define CLOCK_TICK_RATE (AT91_SLOW_CLOCK) | 28 | #define AT91X40_MASTER_CLOCK 40000000 |
29 | 29 | #define CLOCK_TICK_RATE (AT91X40_MASTER_CLOCK) | |
30 | #elif defined(CONFIG_ARCH_AT91SAM9260) | ||
31 | |||
32 | #if defined(CONFIG_MACH_USB_A9260) || defined(CONFIG_MACH_QIL_A9260) | ||
33 | #define AT91SAM9_MASTER_CLOCK 90000000 | ||
34 | #else | ||
35 | #define AT91SAM9_MASTER_CLOCK 99300000 | ||
36 | #endif | ||
37 | |||
38 | #define CLOCK_TICK_RATE (AT91SAM9_MASTER_CLOCK/16) | ||
39 | |||
40 | #elif defined(CONFIG_ARCH_AT91SAM9261) | ||
41 | |||
42 | #define AT91SAM9_MASTER_CLOCK 99300000 | ||
43 | #define CLOCK_TICK_RATE (AT91SAM9_MASTER_CLOCK/16) | ||
44 | |||
45 | #elif defined(CONFIG_ARCH_AT91SAM9G10) | ||
46 | |||
47 | #define AT91SAM9_MASTER_CLOCK 133000000 | ||
48 | #define CLOCK_TICK_RATE (AT91SAM9_MASTER_CLOCK/16) | ||
49 | |||
50 | #elif defined(CONFIG_ARCH_AT91SAM9263) | ||
51 | |||
52 | #if defined(CONFIG_MACH_USB_A9263) | ||
53 | #define AT91SAM9_MASTER_CLOCK 90000000 | ||
54 | #else | ||
55 | #define AT91SAM9_MASTER_CLOCK 99959500 | ||
56 | #endif | ||
57 | |||
58 | #define CLOCK_TICK_RATE (AT91SAM9_MASTER_CLOCK/16) | ||
59 | |||
60 | #elif defined(CONFIG_ARCH_AT91SAM9RL) | ||
61 | |||
62 | #define AT91SAM9_MASTER_CLOCK 100000000 | ||
63 | #define CLOCK_TICK_RATE (AT91SAM9_MASTER_CLOCK/16) | ||
64 | |||
65 | #elif defined(CONFIG_ARCH_AT91SAM9G20) | ||
66 | 30 | ||
67 | #if defined(CONFIG_MACH_USB_A9G20) | ||
68 | #define AT91SAM9_MASTER_CLOCK 133000000 | ||
69 | #else | 31 | #else |
70 | #define AT91SAM9_MASTER_CLOCK 132096000 | ||
71 | #endif | ||
72 | |||
73 | #define CLOCK_TICK_RATE (AT91SAM9_MASTER_CLOCK/16) | ||
74 | |||
75 | #elif defined(CONFIG_ARCH_AT91SAM9G45) | ||
76 | 32 | ||
77 | #define AT91SAM9_MASTER_CLOCK 133333333 | 33 | #define CLOCK_TICK_RATE 12345678 |
78 | #define CLOCK_TICK_RATE (AT91SAM9_MASTER_CLOCK/16) | ||
79 | |||
80 | #elif defined(CONFIG_ARCH_AT91CAP9) | ||
81 | |||
82 | #define AT91CAP9_MASTER_CLOCK 100000000 | ||
83 | #define CLOCK_TICK_RATE (AT91CAP9_MASTER_CLOCK/16) | ||
84 | |||
85 | #elif defined(CONFIG_ARCH_AT91X40) | ||
86 | |||
87 | #define AT91X40_MASTER_CLOCK 40000000 | ||
88 | #define CLOCK_TICK_RATE (AT91X40_MASTER_CLOCK) | ||
89 | 34 | ||
90 | #endif | 35 | #endif |
91 | 36 | ||
92 | #endif | 37 | #endif /* __ASM_ARCH_TIMEX_H */ |