diff options
| author | Manuel Lauss <manuel.lauss@gmail.com> | 2014-07-23 10:36:23 -0400 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2014-07-30 07:53:07 -0400 |
| commit | 2ef1bb99116e49226e8bab8ebab255f12fa8a99e (patch) | |
| tree | 032cd2643e04361f6588f16fb68478583c5043a1 /arch | |
| parent | fb1a7602dde1c82f08ba1ec997ac87af06e946e6 (diff) | |
MIPS: Alchemy: au1000.h move C-code after register definitions.
Move the C-code after all macros: A follow-on patch which
introduces helpers to access the SYS_* registers needs this to build.
Just code shuffling, no functional changes.
Signed-off-by: Manuel Lauss <manuel.lauss@gmail.com>
Cc: Linux-MIPS <linux-mips@linux-mips.org>
Patchwork: https://patchwork.linux-mips.org/patch/7461/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/mips/include/asm/mach-au1x00/au1000.h | 1240 |
1 files changed, 622 insertions, 618 deletions
diff --git a/arch/mips/include/asm/mach-au1x00/au1000.h b/arch/mips/include/asm/mach-au1x00/au1000.h index e50671019122..16cd01236dc3 100644 --- a/arch/mips/include/asm/mach-au1x00/au1000.h +++ b/arch/mips/include/asm/mach-au1x00/au1000.h | |||
| @@ -34,6 +34,607 @@ | |||
| 34 | #ifndef _AU1000_H_ | 34 | #ifndef _AU1000_H_ |
| 35 | #define _AU1000_H_ | 35 | #define _AU1000_H_ |
| 36 | 36 | ||
| 37 | /* SOC Interrupt numbers */ | ||
| 38 | /* Au1000-style (IC0/1): 2 controllers with 32 sources each */ | ||
| 39 | #define AU1000_INTC0_INT_BASE (MIPS_CPU_IRQ_BASE + 8) | ||
| 40 | #define AU1000_INTC0_INT_LAST (AU1000_INTC0_INT_BASE + 31) | ||
| 41 | #define AU1000_INTC1_INT_BASE (AU1000_INTC0_INT_LAST + 1) | ||
| 42 | #define AU1000_INTC1_INT_LAST (AU1000_INTC1_INT_BASE + 31) | ||
| 43 | #define AU1000_MAX_INTR AU1000_INTC1_INT_LAST | ||
| 44 | |||
| 45 | /* Au1300-style (GPIC): 1 controller with up to 128 sources */ | ||
| 46 | #define ALCHEMY_GPIC_INT_BASE (MIPS_CPU_IRQ_BASE + 8) | ||
| 47 | #define ALCHEMY_GPIC_INT_NUM 128 | ||
| 48 | #define ALCHEMY_GPIC_INT_LAST (ALCHEMY_GPIC_INT_BASE + ALCHEMY_GPIC_INT_NUM - 1) | ||
| 49 | |||
| 50 | |||
| 51 | /* Au1300 peripheral interrupt numbers */ | ||
| 52 | #define AU1300_FIRST_INT (ALCHEMY_GPIC_INT_BASE) | ||
| 53 | #define AU1300_UART1_INT (AU1300_FIRST_INT + 17) | ||
| 54 | #define AU1300_UART2_INT (AU1300_FIRST_INT + 25) | ||
| 55 | #define AU1300_UART3_INT (AU1300_FIRST_INT + 27) | ||
| 56 | #define AU1300_SD1_INT (AU1300_FIRST_INT + 32) | ||
| 57 | #define AU1300_SD2_INT (AU1300_FIRST_INT + 38) | ||
| 58 | #define AU1300_PSC0_INT (AU1300_FIRST_INT + 48) | ||
| 59 | #define AU1300_PSC1_INT (AU1300_FIRST_INT + 52) | ||
| 60 | #define AU1300_PSC2_INT (AU1300_FIRST_INT + 56) | ||
| 61 | #define AU1300_PSC3_INT (AU1300_FIRST_INT + 60) | ||
| 62 | #define AU1300_NAND_INT (AU1300_FIRST_INT + 62) | ||
| 63 | #define AU1300_DDMA_INT (AU1300_FIRST_INT + 75) | ||
| 64 | #define AU1300_MMU_INT (AU1300_FIRST_INT + 76) | ||
| 65 | #define AU1300_MPU_INT (AU1300_FIRST_INT + 77) | ||
| 66 | #define AU1300_GPU_INT (AU1300_FIRST_INT + 78) | ||
| 67 | #define AU1300_UDMA_INT (AU1300_FIRST_INT + 79) | ||
| 68 | #define AU1300_TOY_INT (AU1300_FIRST_INT + 80) | ||
| 69 | #define AU1300_TOY_MATCH0_INT (AU1300_FIRST_INT + 81) | ||
| 70 | #define AU1300_TOY_MATCH1_INT (AU1300_FIRST_INT + 82) | ||
| 71 | #define AU1300_TOY_MATCH2_INT (AU1300_FIRST_INT + 83) | ||
| 72 | #define AU1300_RTC_INT (AU1300_FIRST_INT + 84) | ||
| 73 | #define AU1300_RTC_MATCH0_INT (AU1300_FIRST_INT + 85) | ||
| 74 | #define AU1300_RTC_MATCH1_INT (AU1300_FIRST_INT + 86) | ||
| 75 | #define AU1300_RTC_MATCH2_INT (AU1300_FIRST_INT + 87) | ||
| 76 | #define AU1300_UART0_INT (AU1300_FIRST_INT + 88) | ||
| 77 | #define AU1300_SD0_INT (AU1300_FIRST_INT + 89) | ||
| 78 | #define AU1300_USB_INT (AU1300_FIRST_INT + 90) | ||
| 79 | #define AU1300_LCD_INT (AU1300_FIRST_INT + 91) | ||
| 80 | #define AU1300_BSA_INT (AU1300_FIRST_INT + 92) | ||
| 81 | #define AU1300_MPE_INT (AU1300_FIRST_INT + 93) | ||
| 82 | #define AU1300_ITE_INT (AU1300_FIRST_INT + 94) | ||
| 83 | #define AU1300_AES_INT (AU1300_FIRST_INT + 95) | ||
| 84 | #define AU1300_CIM_INT (AU1300_FIRST_INT + 96) | ||
| 85 | |||
| 86 | /**********************************************************************/ | ||
| 87 | |||
| 88 | /* | ||
| 89 | * Physical base addresses for integrated peripherals | ||
| 90 | * 0..au1000 1..au1500 2..au1100 3..au1550 4..au1200 5..au1300 | ||
| 91 | */ | ||
| 92 | |||
| 93 | #define AU1000_AC97_PHYS_ADDR 0x10000000 /* 012 */ | ||
| 94 | #define AU1300_ROM_PHYS_ADDR 0x10000000 /* 5 */ | ||
| 95 | #define AU1300_OTP_PHYS_ADDR 0x10002000 /* 5 */ | ||
| 96 | #define AU1300_VSS_PHYS_ADDR 0x10003000 /* 5 */ | ||
| 97 | #define AU1300_UART0_PHYS_ADDR 0x10100000 /* 5 */ | ||
| 98 | #define AU1300_UART1_PHYS_ADDR 0x10101000 /* 5 */ | ||
| 99 | #define AU1300_UART2_PHYS_ADDR 0x10102000 /* 5 */ | ||
| 100 | #define AU1300_UART3_PHYS_ADDR 0x10103000 /* 5 */ | ||
| 101 | #define AU1000_USB_OHCI_PHYS_ADDR 0x10100000 /* 012 */ | ||
| 102 | #define AU1000_USB_UDC_PHYS_ADDR 0x10200000 /* 0123 */ | ||
| 103 | #define AU1300_GPIC_PHYS_ADDR 0x10200000 /* 5 */ | ||
| 104 | #define AU1000_IRDA_PHYS_ADDR 0x10300000 /* 02 */ | ||
| 105 | #define AU1200_AES_PHYS_ADDR 0x10300000 /* 45 */ | ||
| 106 | #define AU1000_IC0_PHYS_ADDR 0x10400000 /* 01234 */ | ||
| 107 | #define AU1300_GPU_PHYS_ADDR 0x10500000 /* 5 */ | ||
| 108 | #define AU1000_MAC0_PHYS_ADDR 0x10500000 /* 023 */ | ||
| 109 | #define AU1000_MAC1_PHYS_ADDR 0x10510000 /* 023 */ | ||
| 110 | #define AU1000_MACEN_PHYS_ADDR 0x10520000 /* 023 */ | ||
| 111 | #define AU1100_SD0_PHYS_ADDR 0x10600000 /* 245 */ | ||
| 112 | #define AU1300_SD1_PHYS_ADDR 0x10601000 /* 5 */ | ||
| 113 | #define AU1300_SD2_PHYS_ADDR 0x10602000 /* 5 */ | ||
| 114 | #define AU1100_SD1_PHYS_ADDR 0x10680000 /* 24 */ | ||
| 115 | #define AU1300_SYS_PHYS_ADDR 0x10900000 /* 5 */ | ||
| 116 | #define AU1550_PSC2_PHYS_ADDR 0x10A00000 /* 3 */ | ||
| 117 | #define AU1550_PSC3_PHYS_ADDR 0x10B00000 /* 3 */ | ||
| 118 | #define AU1300_PSC0_PHYS_ADDR 0x10A00000 /* 5 */ | ||
| 119 | #define AU1300_PSC1_PHYS_ADDR 0x10A01000 /* 5 */ | ||
| 120 | #define AU1300_PSC2_PHYS_ADDR 0x10A02000 /* 5 */ | ||
| 121 | #define AU1300_PSC3_PHYS_ADDR 0x10A03000 /* 5 */ | ||
| 122 | #define AU1000_I2S_PHYS_ADDR 0x11000000 /* 02 */ | ||
| 123 | #define AU1500_MAC0_PHYS_ADDR 0x11500000 /* 1 */ | ||
| 124 | #define AU1500_MAC1_PHYS_ADDR 0x11510000 /* 1 */ | ||
| 125 | #define AU1500_MACEN_PHYS_ADDR 0x11520000 /* 1 */ | ||
| 126 | #define AU1000_UART0_PHYS_ADDR 0x11100000 /* 01234 */ | ||
| 127 | #define AU1200_SWCNT_PHYS_ADDR 0x1110010C /* 4 */ | ||
| 128 | #define AU1000_UART1_PHYS_ADDR 0x11200000 /* 0234 */ | ||
| 129 | #define AU1000_UART2_PHYS_ADDR 0x11300000 /* 0 */ | ||
| 130 | #define AU1000_UART3_PHYS_ADDR 0x11400000 /* 0123 */ | ||
| 131 | #define AU1000_SSI0_PHYS_ADDR 0x11600000 /* 02 */ | ||
| 132 | #define AU1000_SSI1_PHYS_ADDR 0x11680000 /* 02 */ | ||
| 133 | #define AU1500_GPIO2_PHYS_ADDR 0x11700000 /* 1234 */ | ||
| 134 | #define AU1000_IC1_PHYS_ADDR 0x11800000 /* 01234 */ | ||
| 135 | #define AU1000_SYS_PHYS_ADDR 0x11900000 /* 012345 */ | ||
| 136 | #define AU1550_PSC0_PHYS_ADDR 0x11A00000 /* 34 */ | ||
| 137 | #define AU1550_PSC1_PHYS_ADDR 0x11B00000 /* 34 */ | ||
| 138 | #define AU1000_MEM_PHYS_ADDR 0x14000000 /* 01234 */ | ||
| 139 | #define AU1000_STATIC_MEM_PHYS_ADDR 0x14001000 /* 01234 */ | ||
| 140 | #define AU1300_UDMA_PHYS_ADDR 0x14001800 /* 5 */ | ||
| 141 | #define AU1000_DMA_PHYS_ADDR 0x14002000 /* 012 */ | ||
| 142 | #define AU1550_DBDMA_PHYS_ADDR 0x14002000 /* 345 */ | ||
| 143 | #define AU1550_DBDMA_CONF_PHYS_ADDR 0x14003000 /* 345 */ | ||
| 144 | #define AU1000_MACDMA0_PHYS_ADDR 0x14004000 /* 0123 */ | ||
| 145 | #define AU1000_MACDMA1_PHYS_ADDR 0x14004200 /* 0123 */ | ||
| 146 | #define AU1200_CIM_PHYS_ADDR 0x14004000 /* 45 */ | ||
| 147 | #define AU1500_PCI_PHYS_ADDR 0x14005000 /* 13 */ | ||
| 148 | #define AU1550_PE_PHYS_ADDR 0x14008000 /* 3 */ | ||
| 149 | #define AU1200_MAEBE_PHYS_ADDR 0x14010000 /* 4 */ | ||
| 150 | #define AU1200_MAEFE_PHYS_ADDR 0x14012000 /* 4 */ | ||
| 151 | #define AU1300_MAEITE_PHYS_ADDR 0x14010000 /* 5 */ | ||
| 152 | #define AU1300_MAEMPE_PHYS_ADDR 0x14014000 /* 5 */ | ||
| 153 | #define AU1550_USB_OHCI_PHYS_ADDR 0x14020000 /* 3 */ | ||
| 154 | #define AU1200_USB_CTL_PHYS_ADDR 0x14020000 /* 4 */ | ||
| 155 | #define AU1200_USB_OTG_PHYS_ADDR 0x14020020 /* 4 */ | ||
| 156 | #define AU1200_USB_OHCI_PHYS_ADDR 0x14020100 /* 4 */ | ||
| 157 | #define AU1200_USB_EHCI_PHYS_ADDR 0x14020200 /* 4 */ | ||
| 158 | #define AU1200_USB_UDC_PHYS_ADDR 0x14022000 /* 4 */ | ||
| 159 | #define AU1300_USB_EHCI_PHYS_ADDR 0x14020000 /* 5 */ | ||
| 160 | #define AU1300_USB_OHCI0_PHYS_ADDR 0x14020400 /* 5 */ | ||
| 161 | #define AU1300_USB_OHCI1_PHYS_ADDR 0x14020800 /* 5 */ | ||
| 162 | #define AU1300_USB_CTL_PHYS_ADDR 0x14021000 /* 5 */ | ||
| 163 | #define AU1300_USB_OTG_PHYS_ADDR 0x14022000 /* 5 */ | ||
| 164 | #define AU1300_MAEBSA_PHYS_ADDR 0x14030000 /* 5 */ | ||
| 165 | #define AU1100_LCD_PHYS_ADDR 0x15000000 /* 2 */ | ||
| 166 | #define AU1200_LCD_PHYS_ADDR 0x15000000 /* 45 */ | ||
| 167 | #define AU1500_PCI_MEM_PHYS_ADDR 0x400000000ULL /* 13 */ | ||
| 168 | #define AU1500_PCI_IO_PHYS_ADDR 0x500000000ULL /* 13 */ | ||
| 169 | #define AU1500_PCI_CONFIG0_PHYS_ADDR 0x600000000ULL /* 13 */ | ||
| 170 | #define AU1500_PCI_CONFIG1_PHYS_ADDR 0x680000000ULL /* 13 */ | ||
| 171 | #define AU1000_PCMCIA_IO_PHYS_ADDR 0xF00000000ULL /* 012345 */ | ||
| 172 | #define AU1000_PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL /* 012345 */ | ||
| 173 | #define AU1000_PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL /* 012345 */ | ||
| 174 | |||
| 175 | /**********************************************************************/ | ||
| 176 | |||
| 177 | |||
| 178 | /* | ||
| 179 | * Au1300 GPIO+INT controller (GPIC) register offsets and bits | ||
| 180 | * Registers are 128bits (0x10 bytes), divided into 4 "banks". | ||
| 181 | */ | ||
| 182 | #define AU1300_GPIC_PINVAL 0x0000 | ||
| 183 | #define AU1300_GPIC_PINVALCLR 0x0010 | ||
| 184 | #define AU1300_GPIC_IPEND 0x0020 | ||
| 185 | #define AU1300_GPIC_PRIENC 0x0030 | ||
| 186 | #define AU1300_GPIC_IEN 0x0040 /* int_mask in manual */ | ||
| 187 | #define AU1300_GPIC_IDIS 0x0050 /* int_maskclr in manual */ | ||
| 188 | #define AU1300_GPIC_DMASEL 0x0060 | ||
| 189 | #define AU1300_GPIC_DEVSEL 0x0080 | ||
| 190 | #define AU1300_GPIC_DEVCLR 0x0090 | ||
| 191 | #define AU1300_GPIC_RSTVAL 0x00a0 | ||
| 192 | /* pin configuration space. one 32bit register for up to 128 IRQs */ | ||
| 193 | #define AU1300_GPIC_PINCFG 0x1000 | ||
| 194 | |||
| 195 | #define GPIC_GPIO_TO_BIT(gpio) \ | ||
| 196 | (1 << ((gpio) & 0x1f)) | ||
| 197 | |||
| 198 | #define GPIC_GPIO_BANKOFF(gpio) \ | ||
| 199 | (((gpio) >> 5) * 4) | ||
| 200 | |||
| 201 | /* Pin Control bits: who owns the pin, what does it do */ | ||
| 202 | #define GPIC_CFG_PC_GPIN 0 | ||
| 203 | #define GPIC_CFG_PC_DEV 1 | ||
| 204 | #define GPIC_CFG_PC_GPOLOW 2 | ||
| 205 | #define GPIC_CFG_PC_GPOHIGH 3 | ||
| 206 | #define GPIC_CFG_PC_MASK 3 | ||
| 207 | |||
| 208 | /* assign pin to MIPS IRQ line */ | ||
| 209 | #define GPIC_CFG_IL_SET(x) (((x) & 3) << 2) | ||
| 210 | #define GPIC_CFG_IL_MASK (3 << 2) | ||
| 211 | |||
| 212 | /* pin interrupt type setup */ | ||
| 213 | #define GPIC_CFG_IC_OFF (0 << 4) | ||
| 214 | #define GPIC_CFG_IC_LEVEL_LOW (1 << 4) | ||
| 215 | #define GPIC_CFG_IC_LEVEL_HIGH (2 << 4) | ||
| 216 | #define GPIC_CFG_IC_EDGE_FALL (5 << 4) | ||
| 217 | #define GPIC_CFG_IC_EDGE_RISE (6 << 4) | ||
| 218 | #define GPIC_CFG_IC_EDGE_BOTH (7 << 4) | ||
| 219 | #define GPIC_CFG_IC_MASK (7 << 4) | ||
| 220 | |||
| 221 | /* allow interrupt to wake cpu from 'wait' */ | ||
| 222 | #define GPIC_CFG_IDLEWAKE (1 << 7) | ||
| 223 | |||
| 224 | /***********************************************************************/ | ||
| 225 | |||
| 226 | /* Au1000 SDRAM memory controller register offsets */ | ||
| 227 | #define AU1000_MEM_SDMODE0 0x0000 | ||
| 228 | #define AU1000_MEM_SDMODE1 0x0004 | ||
| 229 | #define AU1000_MEM_SDMODE2 0x0008 | ||
| 230 | #define AU1000_MEM_SDADDR0 0x000C | ||
| 231 | #define AU1000_MEM_SDADDR1 0x0010 | ||
| 232 | #define AU1000_MEM_SDADDR2 0x0014 | ||
| 233 | #define AU1000_MEM_SDREFCFG 0x0018 | ||
| 234 | #define AU1000_MEM_SDPRECMD 0x001C | ||
| 235 | #define AU1000_MEM_SDAUTOREF 0x0020 | ||
| 236 | #define AU1000_MEM_SDWRMD0 0x0024 | ||
| 237 | #define AU1000_MEM_SDWRMD1 0x0028 | ||
| 238 | #define AU1000_MEM_SDWRMD2 0x002C | ||
| 239 | #define AU1000_MEM_SDSLEEP 0x0030 | ||
| 240 | #define AU1000_MEM_SDSMCKE 0x0034 | ||
| 241 | |||
| 242 | /* MEM_SDMODE register content definitions */ | ||
| 243 | #define MEM_SDMODE_F (1 << 22) | ||
| 244 | #define MEM_SDMODE_SR (1 << 21) | ||
| 245 | #define MEM_SDMODE_BS (1 << 20) | ||
| 246 | #define MEM_SDMODE_RS (3 << 18) | ||
| 247 | #define MEM_SDMODE_CS (7 << 15) | ||
| 248 | #define MEM_SDMODE_TRAS (15 << 11) | ||
| 249 | #define MEM_SDMODE_TMRD (3 << 9) | ||
| 250 | #define MEM_SDMODE_TWR (3 << 7) | ||
| 251 | #define MEM_SDMODE_TRP (3 << 5) | ||
| 252 | #define MEM_SDMODE_TRCD (3 << 3) | ||
| 253 | #define MEM_SDMODE_TCL (7 << 0) | ||
| 254 | |||
| 255 | #define MEM_SDMODE_BS_2Bank (0 << 20) | ||
| 256 | #define MEM_SDMODE_BS_4Bank (1 << 20) | ||
| 257 | #define MEM_SDMODE_RS_11Row (0 << 18) | ||
| 258 | #define MEM_SDMODE_RS_12Row (1 << 18) | ||
| 259 | #define MEM_SDMODE_RS_13Row (2 << 18) | ||
| 260 | #define MEM_SDMODE_RS_N(N) ((N) << 18) | ||
| 261 | #define MEM_SDMODE_CS_7Col (0 << 15) | ||
| 262 | #define MEM_SDMODE_CS_8Col (1 << 15) | ||
| 263 | #define MEM_SDMODE_CS_9Col (2 << 15) | ||
| 264 | #define MEM_SDMODE_CS_10Col (3 << 15) | ||
| 265 | #define MEM_SDMODE_CS_11Col (4 << 15) | ||
| 266 | #define MEM_SDMODE_CS_N(N) ((N) << 15) | ||
| 267 | #define MEM_SDMODE_TRAS_N(N) ((N) << 11) | ||
| 268 | #define MEM_SDMODE_TMRD_N(N) ((N) << 9) | ||
| 269 | #define MEM_SDMODE_TWR_N(N) ((N) << 7) | ||
| 270 | #define MEM_SDMODE_TRP_N(N) ((N) << 5) | ||
| 271 | #define MEM_SDMODE_TRCD_N(N) ((N) << 3) | ||
| 272 | #define MEM_SDMODE_TCL_N(N) ((N) << 0) | ||
| 273 | |||
| 274 | /* MEM_SDADDR register contents definitions */ | ||
| 275 | #define MEM_SDADDR_E (1 << 20) | ||
| 276 | #define MEM_SDADDR_CSBA (0x03FF << 10) | ||
| 277 | #define MEM_SDADDR_CSMASK (0x03FF << 0) | ||
| 278 | #define MEM_SDADDR_CSBA_N(N) ((N) & (0x03FF << 22) >> 12) | ||
| 279 | #define MEM_SDADDR_CSMASK_N(N) ((N)&(0x03FF << 22) >> 22) | ||
| 280 | |||
| 281 | /* MEM_SDREFCFG register content definitions */ | ||
| 282 | #define MEM_SDREFCFG_TRC (15 << 28) | ||
| 283 | #define MEM_SDREFCFG_TRPM (3 << 26) | ||
| 284 | #define MEM_SDREFCFG_E (1 << 25) | ||
| 285 | #define MEM_SDREFCFG_RE (0x1ffffff << 0) | ||
| 286 | #define MEM_SDREFCFG_TRC_N(N) ((N) << MEM_SDREFCFG_TRC) | ||
| 287 | #define MEM_SDREFCFG_TRPM_N(N) ((N) << MEM_SDREFCFG_TRPM) | ||
| 288 | #define MEM_SDREFCFG_REF_N(N) (N) | ||
| 289 | |||
| 290 | /* Au1550 SDRAM Register Offsets */ | ||
| 291 | #define AU1550_MEM_SDMODE0 0x0800 | ||
| 292 | #define AU1550_MEM_SDMODE1 0x0808 | ||
| 293 | #define AU1550_MEM_SDMODE2 0x0810 | ||
| 294 | #define AU1550_MEM_SDADDR0 0x0820 | ||
| 295 | #define AU1550_MEM_SDADDR1 0x0828 | ||
| 296 | #define AU1550_MEM_SDADDR2 0x0830 | ||
| 297 | #define AU1550_MEM_SDCONFIGA 0x0840 | ||
| 298 | #define AU1550_MEM_SDCONFIGB 0x0848 | ||
| 299 | #define AU1550_MEM_SDSTAT 0x0850 | ||
| 300 | #define AU1550_MEM_SDERRADDR 0x0858 | ||
| 301 | #define AU1550_MEM_SDSTRIDE0 0x0860 | ||
| 302 | #define AU1550_MEM_SDSTRIDE1 0x0868 | ||
| 303 | #define AU1550_MEM_SDSTRIDE2 0x0870 | ||
| 304 | #define AU1550_MEM_SDWRMD0 0x0880 | ||
| 305 | #define AU1550_MEM_SDWRMD1 0x0888 | ||
| 306 | #define AU1550_MEM_SDWRMD2 0x0890 | ||
| 307 | #define AU1550_MEM_SDPRECMD 0x08C0 | ||
| 308 | #define AU1550_MEM_SDAUTOREF 0x08C8 | ||
| 309 | #define AU1550_MEM_SDSREF 0x08D0 | ||
| 310 | #define AU1550_MEM_SDSLEEP MEM_SDSREF | ||
| 311 | |||
| 312 | /* Static Bus Controller */ | ||
| 313 | #define MEM_STCFG0 0xB4001000 | ||
| 314 | #define MEM_STTIME0 0xB4001004 | ||
| 315 | #define MEM_STADDR0 0xB4001008 | ||
| 316 | |||
| 317 | #define MEM_STCFG1 0xB4001010 | ||
| 318 | #define MEM_STTIME1 0xB4001014 | ||
| 319 | #define MEM_STADDR1 0xB4001018 | ||
| 320 | |||
| 321 | #define MEM_STCFG2 0xB4001020 | ||
| 322 | #define MEM_STTIME2 0xB4001024 | ||
| 323 | #define MEM_STADDR2 0xB4001028 | ||
| 324 | |||
| 325 | #define MEM_STCFG3 0xB4001030 | ||
| 326 | #define MEM_STTIME3 0xB4001034 | ||
| 327 | #define MEM_STADDR3 0xB4001038 | ||
| 328 | |||
| 329 | #define MEM_STNDCTL 0xB4001100 | ||
| 330 | #define MEM_STSTAT 0xB4001104 | ||
| 331 | |||
| 332 | #define MEM_STNAND_CMD 0x0 | ||
| 333 | #define MEM_STNAND_ADDR 0x4 | ||
| 334 | #define MEM_STNAND_DATA 0x20 | ||
| 335 | |||
| 336 | |||
| 337 | /* Programmable Counters 0 and 1 */ | ||
| 338 | #define SYS_BASE 0xB1900000 | ||
| 339 | #define SYS_COUNTER_CNTRL (SYS_BASE + 0x14) | ||
| 340 | # define SYS_CNTRL_E1S (1 << 23) | ||
| 341 | # define SYS_CNTRL_T1S (1 << 20) | ||
| 342 | # define SYS_CNTRL_M21 (1 << 19) | ||
| 343 | # define SYS_CNTRL_M11 (1 << 18) | ||
| 344 | # define SYS_CNTRL_M01 (1 << 17) | ||
| 345 | # define SYS_CNTRL_C1S (1 << 16) | ||
| 346 | # define SYS_CNTRL_BP (1 << 14) | ||
| 347 | # define SYS_CNTRL_EN1 (1 << 13) | ||
| 348 | # define SYS_CNTRL_BT1 (1 << 12) | ||
| 349 | # define SYS_CNTRL_EN0 (1 << 11) | ||
| 350 | # define SYS_CNTRL_BT0 (1 << 10) | ||
| 351 | # define SYS_CNTRL_E0 (1 << 8) | ||
| 352 | # define SYS_CNTRL_E0S (1 << 7) | ||
| 353 | # define SYS_CNTRL_32S (1 << 5) | ||
| 354 | # define SYS_CNTRL_T0S (1 << 4) | ||
| 355 | # define SYS_CNTRL_M20 (1 << 3) | ||
| 356 | # define SYS_CNTRL_M10 (1 << 2) | ||
| 357 | # define SYS_CNTRL_M00 (1 << 1) | ||
| 358 | # define SYS_CNTRL_C0S (1 << 0) | ||
| 359 | |||
| 360 | /* Programmable Counter 0 Registers */ | ||
| 361 | #define SYS_TOYTRIM (SYS_BASE + 0) | ||
| 362 | #define SYS_TOYWRITE (SYS_BASE + 4) | ||
| 363 | #define SYS_TOYMATCH0 (SYS_BASE + 8) | ||
| 364 | #define SYS_TOYMATCH1 (SYS_BASE + 0xC) | ||
| 365 | #define SYS_TOYMATCH2 (SYS_BASE + 0x10) | ||
| 366 | #define SYS_TOYREAD (SYS_BASE + 0x40) | ||
| 367 | |||
| 368 | /* Programmable Counter 1 Registers */ | ||
| 369 | #define SYS_RTCTRIM (SYS_BASE + 0x44) | ||
| 370 | #define SYS_RTCWRITE (SYS_BASE + 0x48) | ||
| 371 | #define SYS_RTCMATCH0 (SYS_BASE + 0x4C) | ||
| 372 | #define SYS_RTCMATCH1 (SYS_BASE + 0x50) | ||
| 373 | #define SYS_RTCMATCH2 (SYS_BASE + 0x54) | ||
| 374 | #define SYS_RTCREAD (SYS_BASE + 0x58) | ||
| 375 | |||
| 376 | |||
| 377 | /* GPIO */ | ||
| 378 | #define SYS_PINFUNC 0xB190002C | ||
| 379 | # define SYS_PF_USB (1 << 15) /* 2nd USB device/host */ | ||
| 380 | # define SYS_PF_U3 (1 << 14) /* GPIO23/U3TXD */ | ||
| 381 | # define SYS_PF_U2 (1 << 13) /* GPIO22/U2TXD */ | ||
| 382 | # define SYS_PF_U1 (1 << 12) /* GPIO21/U1TXD */ | ||
| 383 | # define SYS_PF_SRC (1 << 11) /* GPIO6/SROMCKE */ | ||
| 384 | # define SYS_PF_CK5 (1 << 10) /* GPIO3/CLK5 */ | ||
| 385 | # define SYS_PF_CK4 (1 << 9) /* GPIO2/CLK4 */ | ||
| 386 | # define SYS_PF_IRF (1 << 8) /* GPIO15/IRFIRSEL */ | ||
| 387 | # define SYS_PF_UR3 (1 << 7) /* GPIO[14:9]/UART3 */ | ||
| 388 | # define SYS_PF_I2D (1 << 6) /* GPIO8/I2SDI */ | ||
| 389 | # define SYS_PF_I2S (1 << 5) /* I2S/GPIO[29:31] */ | ||
| 390 | # define SYS_PF_NI2 (1 << 4) /* NI2/GPIO[24:28] */ | ||
| 391 | # define SYS_PF_U0 (1 << 3) /* U0TXD/GPIO20 */ | ||
| 392 | # define SYS_PF_RD (1 << 2) /* IRTXD/GPIO19 */ | ||
| 393 | # define SYS_PF_A97 (1 << 1) /* AC97/SSL1 */ | ||
| 394 | # define SYS_PF_S0 (1 << 0) /* SSI_0/GPIO[16:18] */ | ||
| 395 | |||
| 396 | /* Au1100 only */ | ||
| 397 | # define SYS_PF_PC (1 << 18) /* PCMCIA/GPIO[207:204] */ | ||
| 398 | # define SYS_PF_LCD (1 << 17) /* extern lcd/GPIO[203:200] */ | ||
| 399 | # define SYS_PF_CS (1 << 16) /* EXTCLK0/32KHz to gpio2 */ | ||
| 400 | # define SYS_PF_EX0 (1 << 9) /* GPIO2/clock */ | ||
| 401 | |||
| 402 | /* Au1550 only. Redefines lots of pins */ | ||
| 403 | # define SYS_PF_PSC2_MASK (7 << 17) | ||
| 404 | # define SYS_PF_PSC2_AC97 0 | ||
| 405 | # define SYS_PF_PSC2_SPI 0 | ||
| 406 | # define SYS_PF_PSC2_I2S (1 << 17) | ||
| 407 | # define SYS_PF_PSC2_SMBUS (3 << 17) | ||
| 408 | # define SYS_PF_PSC2_GPIO (7 << 17) | ||
| 409 | # define SYS_PF_PSC3_MASK (7 << 20) | ||
| 410 | # define SYS_PF_PSC3_AC97 0 | ||
| 411 | # define SYS_PF_PSC3_SPI 0 | ||
| 412 | # define SYS_PF_PSC3_I2S (1 << 20) | ||
| 413 | # define SYS_PF_PSC3_SMBUS (3 << 20) | ||
| 414 | # define SYS_PF_PSC3_GPIO (7 << 20) | ||
| 415 | # define SYS_PF_PSC1_S1 (1 << 1) | ||
| 416 | # define SYS_PF_MUST_BE_SET ((1 << 5) | (1 << 2)) | ||
| 417 | |||
| 418 | /* Au1200 only */ | ||
| 419 | #define SYS_PINFUNC_DMA (1 << 31) | ||
| 420 | #define SYS_PINFUNC_S0A (1 << 30) | ||
| 421 | #define SYS_PINFUNC_S1A (1 << 29) | ||
| 422 | #define SYS_PINFUNC_LP0 (1 << 28) | ||
| 423 | #define SYS_PINFUNC_LP1 (1 << 27) | ||
| 424 | #define SYS_PINFUNC_LD16 (1 << 26) | ||
| 425 | #define SYS_PINFUNC_LD8 (1 << 25) | ||
| 426 | #define SYS_PINFUNC_LD1 (1 << 24) | ||
| 427 | #define SYS_PINFUNC_LD0 (1 << 23) | ||
| 428 | #define SYS_PINFUNC_P1A (3 << 21) | ||
| 429 | #define SYS_PINFUNC_P1B (1 << 20) | ||
| 430 | #define SYS_PINFUNC_FS3 (1 << 19) | ||
| 431 | #define SYS_PINFUNC_P0A (3 << 17) | ||
| 432 | #define SYS_PINFUNC_CS (1 << 16) | ||
| 433 | #define SYS_PINFUNC_CIM (1 << 15) | ||
| 434 | #define SYS_PINFUNC_P1C (1 << 14) | ||
| 435 | #define SYS_PINFUNC_U1T (1 << 12) | ||
| 436 | #define SYS_PINFUNC_U1R (1 << 11) | ||
| 437 | #define SYS_PINFUNC_EX1 (1 << 10) | ||
| 438 | #define SYS_PINFUNC_EX0 (1 << 9) | ||
| 439 | #define SYS_PINFUNC_U0R (1 << 8) | ||
| 440 | #define SYS_PINFUNC_MC (1 << 7) | ||
| 441 | #define SYS_PINFUNC_S0B (1 << 6) | ||
| 442 | #define SYS_PINFUNC_S0C (1 << 5) | ||
| 443 | #define SYS_PINFUNC_P0B (1 << 4) | ||
| 444 | #define SYS_PINFUNC_U0T (1 << 3) | ||
| 445 | #define SYS_PINFUNC_S1B (1 << 2) | ||
| 446 | |||
| 447 | /* Power Management */ | ||
| 448 | #define SYS_SCRATCH0 0xB1900018 | ||
| 449 | #define SYS_SCRATCH1 0xB190001C | ||
| 450 | #define SYS_WAKEMSK 0xB1900034 | ||
| 451 | #define SYS_ENDIAN 0xB1900038 | ||
| 452 | #define SYS_POWERCTRL 0xB190003C | ||
| 453 | #define SYS_WAKESRC 0xB190005C | ||
| 454 | #define SYS_SLPPWR 0xB1900078 | ||
| 455 | #define SYS_SLEEP 0xB190007C | ||
| 456 | |||
| 457 | #define SYS_WAKEMSK_D2 (1 << 9) | ||
| 458 | #define SYS_WAKEMSK_M2 (1 << 8) | ||
| 459 | #define SYS_WAKEMSK_GPIO(x) (1 << (x)) | ||
| 460 | |||
| 461 | /* Clock Controller */ | ||
| 462 | #define SYS_FREQCTRL0 0xB1900020 | ||
| 463 | # define SYS_FC_FRDIV2_BIT 22 | ||
| 464 | # define SYS_FC_FRDIV2_MASK (0xff << SYS_FC_FRDIV2_BIT) | ||
| 465 | # define SYS_FC_FE2 (1 << 21) | ||
| 466 | # define SYS_FC_FS2 (1 << 20) | ||
| 467 | # define SYS_FC_FRDIV1_BIT 12 | ||
| 468 | # define SYS_FC_FRDIV1_MASK (0xff << SYS_FC_FRDIV1_BIT) | ||
| 469 | # define SYS_FC_FE1 (1 << 11) | ||
| 470 | # define SYS_FC_FS1 (1 << 10) | ||
| 471 | # define SYS_FC_FRDIV0_BIT 2 | ||
| 472 | # define SYS_FC_FRDIV0_MASK (0xff << SYS_FC_FRDIV0_BIT) | ||
| 473 | # define SYS_FC_FE0 (1 << 1) | ||
| 474 | # define SYS_FC_FS0 (1 << 0) | ||
| 475 | #define SYS_FREQCTRL1 0xB1900024 | ||
| 476 | # define SYS_FC_FRDIV5_BIT 22 | ||
| 477 | # define SYS_FC_FRDIV5_MASK (0xff << SYS_FC_FRDIV5_BIT) | ||
| 478 | # define SYS_FC_FE5 (1 << 21) | ||
| 479 | # define SYS_FC_FS5 (1 << 20) | ||
| 480 | # define SYS_FC_FRDIV4_BIT 12 | ||
| 481 | # define SYS_FC_FRDIV4_MASK (0xff << SYS_FC_FRDIV4_BIT) | ||
| 482 | # define SYS_FC_FE4 (1 << 11) | ||
| 483 | # define SYS_FC_FS4 (1 << 10) | ||
| 484 | # define SYS_FC_FRDIV3_BIT 2 | ||
| 485 | # define SYS_FC_FRDIV3_MASK (0xff << SYS_FC_FRDIV3_BIT) | ||
| 486 | # define SYS_FC_FE3 (1 << 1) | ||
| 487 | # define SYS_FC_FS3 (1 << 0) | ||
| 488 | #define SYS_CLKSRC 0xB1900028 | ||
| 489 | # define SYS_CS_ME1_BIT 27 | ||
| 490 | # define SYS_CS_ME1_MASK (0x7 << SYS_CS_ME1_BIT) | ||
| 491 | # define SYS_CS_DE1 (1 << 26) | ||
| 492 | # define SYS_CS_CE1 (1 << 25) | ||
| 493 | # define SYS_CS_ME0_BIT 22 | ||
| 494 | # define SYS_CS_ME0_MASK (0x7 << SYS_CS_ME0_BIT) | ||
| 495 | # define SYS_CS_DE0 (1 << 21) | ||
| 496 | # define SYS_CS_CE0 (1 << 20) | ||
| 497 | # define SYS_CS_MI2_BIT 17 | ||
| 498 | # define SYS_CS_MI2_MASK (0x7 << SYS_CS_MI2_BIT) | ||
| 499 | # define SYS_CS_DI2 (1 << 16) | ||
| 500 | # define SYS_CS_CI2 (1 << 15) | ||
| 501 | |||
| 502 | # define SYS_CS_ML_BIT 7 | ||
| 503 | # define SYS_CS_ML_MASK (0x7 << SYS_CS_ML_BIT) | ||
| 504 | # define SYS_CS_DL (1 << 6) | ||
| 505 | # define SYS_CS_CL (1 << 5) | ||
| 506 | |||
| 507 | # define SYS_CS_MUH_BIT 12 | ||
| 508 | # define SYS_CS_MUH_MASK (0x7 << SYS_CS_MUH_BIT) | ||
| 509 | # define SYS_CS_DUH (1 << 11) | ||
| 510 | # define SYS_CS_CUH (1 << 10) | ||
| 511 | # define SYS_CS_MUD_BIT 7 | ||
| 512 | # define SYS_CS_MUD_MASK (0x7 << SYS_CS_MUD_BIT) | ||
| 513 | # define SYS_CS_DUD (1 << 6) | ||
| 514 | # define SYS_CS_CUD (1 << 5) | ||
| 515 | |||
| 516 | # define SYS_CS_MIR_BIT 2 | ||
| 517 | # define SYS_CS_MIR_MASK (0x7 << SYS_CS_MIR_BIT) | ||
| 518 | # define SYS_CS_DIR (1 << 1) | ||
| 519 | # define SYS_CS_CIR (1 << 0) | ||
| 520 | |||
| 521 | # define SYS_CS_MUX_AUX 0x1 | ||
| 522 | # define SYS_CS_MUX_FQ0 0x2 | ||
| 523 | # define SYS_CS_MUX_FQ1 0x3 | ||
| 524 | # define SYS_CS_MUX_FQ2 0x4 | ||
| 525 | # define SYS_CS_MUX_FQ3 0x5 | ||
| 526 | # define SYS_CS_MUX_FQ4 0x6 | ||
| 527 | # define SYS_CS_MUX_FQ5 0x7 | ||
| 528 | #define SYS_CPUPLL 0xB1900060 | ||
| 529 | #define SYS_AUXPLL 0xB1900064 | ||
| 530 | |||
| 531 | |||
| 532 | /* The PCI chip selects are outside the 32bit space, and since we can't | ||
| 533 | * just program the 36bit addresses into BARs, we have to take a chunk | ||
| 534 | * out of the 32bit space and reserve it for PCI. When these addresses | ||
| 535 | * are ioremap()ed, they'll be fixed up to the real 36bit address before | ||
| 536 | * being passed to the real ioremap function. | ||
| 537 | */ | ||
| 538 | #define ALCHEMY_PCI_MEMWIN_START (AU1500_PCI_MEM_PHYS_ADDR >> 4) | ||
| 539 | #define ALCHEMY_PCI_MEMWIN_END (ALCHEMY_PCI_MEMWIN_START + 0x0FFFFFFF) | ||
| 540 | |||
| 541 | /* for PCI IO it's simpler because we get to do the ioremap ourselves and then | ||
| 542 | * adjust the device's resources. | ||
| 543 | */ | ||
| 544 | #define ALCHEMY_PCI_IOWIN_START 0x00001000 | ||
| 545 | #define ALCHEMY_PCI_IOWIN_END 0x0000FFFF | ||
| 546 | |||
| 547 | #ifdef CONFIG_PCI | ||
| 548 | |||
| 549 | #define IOPORT_RESOURCE_START 0x00001000 /* skip legacy probing */ | ||
| 550 | #define IOPORT_RESOURCE_END 0xffffffff | ||
| 551 | #define IOMEM_RESOURCE_START 0x10000000 | ||
| 552 | #define IOMEM_RESOURCE_END 0xfffffffffULL | ||
| 553 | |||
| 554 | #else | ||
| 555 | |||
| 556 | /* Don't allow any legacy ports probing */ | ||
| 557 | #define IOPORT_RESOURCE_START 0x10000000 | ||
| 558 | #define IOPORT_RESOURCE_END 0xffffffff | ||
| 559 | #define IOMEM_RESOURCE_START 0x10000000 | ||
| 560 | #define IOMEM_RESOURCE_END 0xfffffffffULL | ||
| 561 | |||
| 562 | #endif | ||
| 563 | |||
| 564 | /* PCI controller block register offsets */ | ||
| 565 | #define PCI_REG_CMEM 0x0000 | ||
| 566 | #define PCI_REG_CONFIG 0x0004 | ||
| 567 | #define PCI_REG_B2BMASK_CCH 0x0008 | ||
| 568 | #define PCI_REG_B2BBASE0_VID 0x000C | ||
| 569 | #define PCI_REG_B2BBASE1_SID 0x0010 | ||
| 570 | #define PCI_REG_MWMASK_DEV 0x0014 | ||
| 571 | #define PCI_REG_MWBASE_REV_CCL 0x0018 | ||
| 572 | #define PCI_REG_ERR_ADDR 0x001C | ||
| 573 | #define PCI_REG_SPEC_INTACK 0x0020 | ||
| 574 | #define PCI_REG_ID 0x0100 | ||
| 575 | #define PCI_REG_STATCMD 0x0104 | ||
| 576 | #define PCI_REG_CLASSREV 0x0108 | ||
| 577 | #define PCI_REG_PARAM 0x010C | ||
| 578 | #define PCI_REG_MBAR 0x0110 | ||
| 579 | #define PCI_REG_TIMEOUT 0x0140 | ||
| 580 | |||
| 581 | /* PCI controller block register bits */ | ||
| 582 | #define PCI_CMEM_E (1 << 28) /* enable cacheable memory */ | ||
| 583 | #define PCI_CMEM_CMBASE(x) (((x) & 0x3fff) << 14) | ||
| 584 | #define PCI_CMEM_CMMASK(x) ((x) & 0x3fff) | ||
| 585 | #define PCI_CONFIG_ERD (1 << 27) /* pci error during R/W */ | ||
| 586 | #define PCI_CONFIG_ET (1 << 26) /* error in target mode */ | ||
| 587 | #define PCI_CONFIG_EF (1 << 25) /* fatal error */ | ||
| 588 | #define PCI_CONFIG_EP (1 << 24) /* parity error */ | ||
| 589 | #define PCI_CONFIG_EM (1 << 23) /* multiple errors */ | ||
| 590 | #define PCI_CONFIG_BM (1 << 22) /* bad master error */ | ||
| 591 | #define PCI_CONFIG_PD (1 << 20) /* PCI Disable */ | ||
| 592 | #define PCI_CONFIG_BME (1 << 19) /* Byte Mask Enable for reads */ | ||
| 593 | #define PCI_CONFIG_NC (1 << 16) /* mark mem access non-coherent */ | ||
| 594 | #define PCI_CONFIG_IA (1 << 15) /* INTA# enabled (target mode) */ | ||
| 595 | #define PCI_CONFIG_IP (1 << 13) /* int on PCI_PERR# */ | ||
| 596 | #define PCI_CONFIG_IS (1 << 12) /* int on PCI_SERR# */ | ||
| 597 | #define PCI_CONFIG_IMM (1 << 11) /* int on master abort */ | ||
| 598 | #define PCI_CONFIG_ITM (1 << 10) /* int on target abort (as master) */ | ||
| 599 | #define PCI_CONFIG_ITT (1 << 9) /* int on target abort (as target) */ | ||
| 600 | #define PCI_CONFIG_IPB (1 << 8) /* int on PERR# in bus master acc */ | ||
| 601 | #define PCI_CONFIG_SIC_NO (0 << 6) /* no byte mask changes */ | ||
| 602 | #define PCI_CONFIG_SIC_BA_ADR (1 << 6) /* on byte/hw acc, invert adr bits */ | ||
| 603 | #define PCI_CONFIG_SIC_HWA_DAT (2 << 6) /* on halfword acc, swap data */ | ||
| 604 | #define PCI_CONFIG_SIC_ALL (3 << 6) /* swap data bytes on all accesses */ | ||
| 605 | #define PCI_CONFIG_ST (1 << 5) /* swap data by target transactions */ | ||
| 606 | #define PCI_CONFIG_SM (1 << 4) /* swap data from PCI ctl */ | ||
| 607 | #define PCI_CONFIG_AEN (1 << 3) /* enable internal arbiter */ | ||
| 608 | #define PCI_CONFIG_R2H (1 << 2) /* REQ2# to hi-prio arbiter */ | ||
| 609 | #define PCI_CONFIG_R1H (1 << 1) /* REQ1# to hi-prio arbiter */ | ||
| 610 | #define PCI_CONFIG_CH (1 << 0) /* PCI ctl to hi-prio arbiter */ | ||
| 611 | #define PCI_B2BMASK_B2BMASK(x) (((x) & 0xffff) << 16) | ||
| 612 | #define PCI_B2BMASK_CCH(x) ((x) & 0xffff) /* 16 upper bits of class code */ | ||
| 613 | #define PCI_B2BBASE0_VID_B0(x) (((x) & 0xffff) << 16) | ||
| 614 | #define PCI_B2BBASE0_VID_SV(x) ((x) & 0xffff) | ||
| 615 | #define PCI_B2BBASE1_SID_B1(x) (((x) & 0xffff) << 16) | ||
| 616 | #define PCI_B2BBASE1_SID_SI(x) ((x) & 0xffff) | ||
| 617 | #define PCI_MWMASKDEV_MWMASK(x) (((x) & 0xffff) << 16) | ||
| 618 | #define PCI_MWMASKDEV_DEVID(x) ((x) & 0xffff) | ||
| 619 | #define PCI_MWBASEREVCCL_BASE(x) (((x) & 0xffff) << 16) | ||
| 620 | #define PCI_MWBASEREVCCL_REV(x) (((x) & 0xff) << 8) | ||
| 621 | #define PCI_MWBASEREVCCL_CCL(x) ((x) & 0xff) | ||
| 622 | #define PCI_ID_DID(x) (((x) & 0xffff) << 16) | ||
| 623 | #define PCI_ID_VID(x) ((x) & 0xffff) | ||
| 624 | #define PCI_STATCMD_STATUS(x) (((x) & 0xffff) << 16) | ||
| 625 | #define PCI_STATCMD_CMD(x) ((x) & 0xffff) | ||
| 626 | #define PCI_CLASSREV_CLASS(x) (((x) & 0x00ffffff) << 8) | ||
| 627 | #define PCI_CLASSREV_REV(x) ((x) & 0xff) | ||
| 628 | #define PCI_PARAM_BIST(x) (((x) & 0xff) << 24) | ||
| 629 | #define PCI_PARAM_HT(x) (((x) & 0xff) << 16) | ||
| 630 | #define PCI_PARAM_LT(x) (((x) & 0xff) << 8) | ||
| 631 | #define PCI_PARAM_CLS(x) ((x) & 0xff) | ||
| 632 | #define PCI_TIMEOUT_RETRIES(x) (((x) & 0xff) << 8) /* max retries */ | ||
| 633 | #define PCI_TIMEOUT_TO(x) ((x) & 0xff) /* target ready timeout */ | ||
| 634 | |||
| 635 | |||
| 636 | /**********************************************************************/ | ||
| 637 | |||
| 37 | 638 | ||
| 38 | #ifndef _LANGUAGE_ASSEMBLY | 639 | #ifndef _LANGUAGE_ASSEMBLY |
| 39 | 640 | ||
| @@ -192,19 +793,20 @@ static inline void alchemy_uart_enable(u32 uart_phys) | |||
| 192 | /* reset, enable clock, deassert reset */ | 793 | /* reset, enable clock, deassert reset */ |
| 193 | if ((__raw_readl(addr + 0x100) & 3) != 3) { | 794 | if ((__raw_readl(addr + 0x100) & 3) != 3) { |
| 194 | __raw_writel(0, addr + 0x100); | 795 | __raw_writel(0, addr + 0x100); |
| 195 | wmb(); | 796 | wmb(); /* drain writebuffer */ |
| 196 | __raw_writel(1, addr + 0x100); | 797 | __raw_writel(1, addr + 0x100); |
| 197 | wmb(); | 798 | wmb(); /* drain writebuffer */ |
| 198 | } | 799 | } |
| 199 | __raw_writel(3, addr + 0x100); | 800 | __raw_writel(3, addr + 0x100); |
| 200 | wmb(); | 801 | wmb(); /* drain writebuffer */ |
| 201 | } | 802 | } |
| 202 | 803 | ||
| 203 | static inline void alchemy_uart_disable(u32 uart_phys) | 804 | static inline void alchemy_uart_disable(u32 uart_phys) |
| 204 | { | 805 | { |
| 205 | void __iomem *addr = (void __iomem *)KSEG1ADDR(uart_phys); | 806 | void __iomem *addr = (void __iomem *)KSEG1ADDR(uart_phys); |
| 807 | |||
| 206 | __raw_writel(0, addr + 0x100); /* UART_MOD_CNTRL */ | 808 | __raw_writel(0, addr + 0x100); /* UART_MOD_CNTRL */ |
| 207 | wmb(); | 809 | wmb(); /* drain writebuffer */ |
| 208 | } | 810 | } |
| 209 | 811 | ||
| 210 | static inline void alchemy_uart_putchar(u32 uart_phys, u8 c) | 812 | static inline void alchemy_uart_putchar(u32 uart_phys, u8 c) |
| @@ -223,7 +825,7 @@ static inline void alchemy_uart_putchar(u32 uart_phys, u8 c) | |||
| 223 | } while (--timeout); | 825 | } while (--timeout); |
| 224 | 826 | ||
| 225 | __raw_writel(c, base + 0x04); /* tx */ | 827 | __raw_writel(c, base + 0x04); /* tx */ |
| 226 | wmb(); | 828 | wmb(); /* drain writebuffer */ |
| 227 | } | 829 | } |
| 228 | 830 | ||
| 229 | /* return number of ethernet MACs on a given cputype */ | 831 | /* return number of ethernet MACs on a given cputype */ |
| @@ -253,7 +855,7 @@ void alchemy_sleep_au1550(void); | |||
| 253 | void alchemy_sleep_au1300(void); | 855 | void alchemy_sleep_au1300(void); |
| 254 | void au_sleep(void); | 856 | void au_sleep(void); |
| 255 | 857 | ||
| 256 | /* USB: drivers/usb/host/alchemy-common.c */ | 858 | /* USB: arch/mips/alchemy/common/usb.c */ |
| 257 | enum alchemy_usb_block { | 859 | enum alchemy_usb_block { |
| 258 | ALCHEMY_USB_OHCI0, | 860 | ALCHEMY_USB_OHCI0, |
| 259 | ALCHEMY_USB_UDC0, | 861 | ALCHEMY_USB_UDC0, |
| @@ -272,6 +874,20 @@ struct alchemy_pci_platdata { | |||
| 272 | unsigned long pci_cfg_clr; | 874 | unsigned long pci_cfg_clr; |
| 273 | }; | 875 | }; |
| 274 | 876 | ||
| 877 | /* The IrDA peripheral has an IRFIRSEL pin, but on the DB/PB boards it's | ||
| 878 | * not used to select FIR/SIR mode on the transceiver but as a GPIO. | ||
| 879 | * Instead a CPLD has to be told about the mode. The driver calls the | ||
| 880 | * set_phy_mode() function in addition to driving the IRFIRSEL pin. | ||
| 881 | */ | ||
| 882 | #define AU1000_IRDA_PHY_MODE_OFF 0 | ||
| 883 | #define AU1000_IRDA_PHY_MODE_SIR 1 | ||
| 884 | #define AU1000_IRDA_PHY_MODE_FIR 2 | ||
| 885 | |||
| 886 | struct au1k_irda_platform_data { | ||
| 887 | void (*set_phy_mode)(int mode); | ||
| 888 | }; | ||
| 889 | |||
| 890 | |||
| 275 | /* Multifunction pins: Each of these pins can either be assigned to the | 891 | /* Multifunction pins: Each of these pins can either be assigned to the |
| 276 | * GPIO controller or a on-chip peripheral. | 892 | * GPIO controller or a on-chip peripheral. |
| 277 | * Call "au1300_pinfunc_to_dev()" or "au1300_pinfunc_to_gpio()" to | 893 | * Call "au1300_pinfunc_to_dev()" or "au1300_pinfunc_to_gpio()" to |
| @@ -344,20 +960,6 @@ enum au1300_vss_block { | |||
| 344 | 960 | ||
| 345 | extern void au1300_vss_block_control(int block, int enable); | 961 | extern void au1300_vss_block_control(int block, int enable); |
| 346 | 962 | ||
| 347 | |||
| 348 | /* SOC Interrupt numbers */ | ||
| 349 | /* Au1000-style (IC0/1): 2 controllers with 32 sources each */ | ||
| 350 | #define AU1000_INTC0_INT_BASE (MIPS_CPU_IRQ_BASE + 8) | ||
| 351 | #define AU1000_INTC0_INT_LAST (AU1000_INTC0_INT_BASE + 31) | ||
| 352 | #define AU1000_INTC1_INT_BASE (AU1000_INTC0_INT_LAST + 1) | ||
| 353 | #define AU1000_INTC1_INT_LAST (AU1000_INTC1_INT_BASE + 31) | ||
| 354 | #define AU1000_MAX_INTR AU1000_INTC1_INT_LAST | ||
| 355 | |||
| 356 | /* Au1300-style (GPIC): 1 controller with up to 128 sources */ | ||
| 357 | #define ALCHEMY_GPIC_INT_BASE (MIPS_CPU_IRQ_BASE + 8) | ||
| 358 | #define ALCHEMY_GPIC_INT_NUM 128 | ||
| 359 | #define ALCHEMY_GPIC_INT_LAST (ALCHEMY_GPIC_INT_BASE + ALCHEMY_GPIC_INT_NUM - 1) | ||
| 360 | |||
| 361 | enum soc_au1000_ints { | 963 | enum soc_au1000_ints { |
| 362 | AU1000_FIRST_INT = AU1000_INTC0_INT_BASE, | 964 | AU1000_FIRST_INT = AU1000_INTC0_INT_BASE, |
| 363 | AU1000_UART0_INT = AU1000_FIRST_INT, | 965 | AU1000_UART0_INT = AU1000_FIRST_INT, |
| @@ -678,602 +1280,4 @@ enum soc_au1200_ints { | |||
| 678 | 1280 | ||
| 679 | #endif /* !defined (_LANGUAGE_ASSEMBLY) */ | 1281 | #endif /* !defined (_LANGUAGE_ASSEMBLY) */ |
| 680 | 1282 | ||
| 681 | /* Au1300 peripheral interrupt numbers */ | ||
| 682 | #define AU1300_FIRST_INT (ALCHEMY_GPIC_INT_BASE) | ||
| 683 | #define AU1300_UART1_INT (AU1300_FIRST_INT + 17) | ||
| 684 | #define AU1300_UART2_INT (AU1300_FIRST_INT + 25) | ||
| 685 | #define AU1300_UART3_INT (AU1300_FIRST_INT + 27) | ||
| 686 | #define AU1300_SD1_INT (AU1300_FIRST_INT + 32) | ||
| 687 | #define AU1300_SD2_INT (AU1300_FIRST_INT + 38) | ||
| 688 | #define AU1300_PSC0_INT (AU1300_FIRST_INT + 48) | ||
| 689 | #define AU1300_PSC1_INT (AU1300_FIRST_INT + 52) | ||
| 690 | #define AU1300_PSC2_INT (AU1300_FIRST_INT + 56) | ||
| 691 | #define AU1300_PSC3_INT (AU1300_FIRST_INT + 60) | ||
| 692 | #define AU1300_NAND_INT (AU1300_FIRST_INT + 62) | ||
| 693 | #define AU1300_DDMA_INT (AU1300_FIRST_INT + 75) | ||
| 694 | #define AU1300_MMU_INT (AU1300_FIRST_INT + 76) | ||
| 695 | #define AU1300_MPU_INT (AU1300_FIRST_INT + 77) | ||
| 696 | #define AU1300_GPU_INT (AU1300_FIRST_INT + 78) | ||
| 697 | #define AU1300_UDMA_INT (AU1300_FIRST_INT + 79) | ||
| 698 | #define AU1300_TOY_INT (AU1300_FIRST_INT + 80) | ||
| 699 | #define AU1300_TOY_MATCH0_INT (AU1300_FIRST_INT + 81) | ||
| 700 | #define AU1300_TOY_MATCH1_INT (AU1300_FIRST_INT + 82) | ||
| 701 | #define AU1300_TOY_MATCH2_INT (AU1300_FIRST_INT + 83) | ||
| 702 | #define AU1300_RTC_INT (AU1300_FIRST_INT + 84) | ||
| 703 | #define AU1300_RTC_MATCH0_INT (AU1300_FIRST_INT + 85) | ||
| 704 | #define AU1300_RTC_MATCH1_INT (AU1300_FIRST_INT + 86) | ||
| 705 | #define AU1300_RTC_MATCH2_INT (AU1300_FIRST_INT + 87) | ||
| 706 | #define AU1300_UART0_INT (AU1300_FIRST_INT + 88) | ||
| 707 | #define AU1300_SD0_INT (AU1300_FIRST_INT + 89) | ||
| 708 | #define AU1300_USB_INT (AU1300_FIRST_INT + 90) | ||
| 709 | #define AU1300_LCD_INT (AU1300_FIRST_INT + 91) | ||
| 710 | #define AU1300_BSA_INT (AU1300_FIRST_INT + 92) | ||
| 711 | #define AU1300_MPE_INT (AU1300_FIRST_INT + 93) | ||
| 712 | #define AU1300_ITE_INT (AU1300_FIRST_INT + 94) | ||
| 713 | #define AU1300_AES_INT (AU1300_FIRST_INT + 95) | ||
| 714 | #define AU1300_CIM_INT (AU1300_FIRST_INT + 96) | ||
| 715 | |||
| 716 | /**********************************************************************/ | ||
| 717 | |||
| 718 | /* | ||
| 719 | * Physical base addresses for integrated peripherals | ||
| 720 | * 0..au1000 1..au1500 2..au1100 3..au1550 4..au1200 5..au1300 | ||
| 721 | */ | ||
| 722 | |||
| 723 | #define AU1000_AC97_PHYS_ADDR 0x10000000 /* 012 */ | ||
| 724 | #define AU1300_ROM_PHYS_ADDR 0x10000000 /* 5 */ | ||
| 725 | #define AU1300_OTP_PHYS_ADDR 0x10002000 /* 5 */ | ||
| 726 | #define AU1300_VSS_PHYS_ADDR 0x10003000 /* 5 */ | ||
| 727 | #define AU1300_UART0_PHYS_ADDR 0x10100000 /* 5 */ | ||
| 728 | #define AU1300_UART1_PHYS_ADDR 0x10101000 /* 5 */ | ||
| 729 | #define AU1300_UART2_PHYS_ADDR 0x10102000 /* 5 */ | ||
| 730 | #define AU1300_UART3_PHYS_ADDR 0x10103000 /* 5 */ | ||
| 731 | #define AU1000_USB_OHCI_PHYS_ADDR 0x10100000 /* 012 */ | ||
| 732 | #define AU1000_USB_UDC_PHYS_ADDR 0x10200000 /* 0123 */ | ||
| 733 | #define AU1300_GPIC_PHYS_ADDR 0x10200000 /* 5 */ | ||
| 734 | #define AU1000_IRDA_PHYS_ADDR 0x10300000 /* 02 */ | ||
| 735 | #define AU1200_AES_PHYS_ADDR 0x10300000 /* 45 */ | ||
| 736 | #define AU1000_IC0_PHYS_ADDR 0x10400000 /* 01234 */ | ||
| 737 | #define AU1300_GPU_PHYS_ADDR 0x10500000 /* 5 */ | ||
| 738 | #define AU1000_MAC0_PHYS_ADDR 0x10500000 /* 023 */ | ||
| 739 | #define AU1000_MAC1_PHYS_ADDR 0x10510000 /* 023 */ | ||
| 740 | #define AU1000_MACEN_PHYS_ADDR 0x10520000 /* 023 */ | ||
| 741 | #define AU1100_SD0_PHYS_ADDR 0x10600000 /* 245 */ | ||
| 742 | #define AU1300_SD1_PHYS_ADDR 0x10601000 /* 5 */ | ||
| 743 | #define AU1300_SD2_PHYS_ADDR 0x10602000 /* 5 */ | ||
| 744 | #define AU1100_SD1_PHYS_ADDR 0x10680000 /* 24 */ | ||
| 745 | #define AU1300_SYS_PHYS_ADDR 0x10900000 /* 5 */ | ||
| 746 | #define AU1550_PSC2_PHYS_ADDR 0x10A00000 /* 3 */ | ||
| 747 | #define AU1550_PSC3_PHYS_ADDR 0x10B00000 /* 3 */ | ||
| 748 | #define AU1300_PSC0_PHYS_ADDR 0x10A00000 /* 5 */ | ||
| 749 | #define AU1300_PSC1_PHYS_ADDR 0x10A01000 /* 5 */ | ||
| 750 | #define AU1300_PSC2_PHYS_ADDR 0x10A02000 /* 5 */ | ||
| 751 | #define AU1300_PSC3_PHYS_ADDR 0x10A03000 /* 5 */ | ||
| 752 | #define AU1000_I2S_PHYS_ADDR 0x11000000 /* 02 */ | ||
| 753 | #define AU1500_MAC0_PHYS_ADDR 0x11500000 /* 1 */ | ||
| 754 | #define AU1500_MAC1_PHYS_ADDR 0x11510000 /* 1 */ | ||
| 755 | #define AU1500_MACEN_PHYS_ADDR 0x11520000 /* 1 */ | ||
| 756 | #define AU1000_UART0_PHYS_ADDR 0x11100000 /* 01234 */ | ||
| 757 | #define AU1200_SWCNT_PHYS_ADDR 0x1110010C /* 4 */ | ||
| 758 | #define AU1000_UART1_PHYS_ADDR 0x11200000 /* 0234 */ | ||
| 759 | #define AU1000_UART2_PHYS_ADDR 0x11300000 /* 0 */ | ||
| 760 | #define AU1000_UART3_PHYS_ADDR 0x11400000 /* 0123 */ | ||
| 761 | #define AU1000_SSI0_PHYS_ADDR 0x11600000 /* 02 */ | ||
| 762 | #define AU1000_SSI1_PHYS_ADDR 0x11680000 /* 02 */ | ||
| 763 | #define AU1500_GPIO2_PHYS_ADDR 0x11700000 /* 1234 */ | ||
| 764 | #define AU1000_IC1_PHYS_ADDR 0x11800000 /* 01234 */ | ||
| 765 | #define AU1000_SYS_PHYS_ADDR 0x11900000 /* 012345 */ | ||
| 766 | #define AU1550_PSC0_PHYS_ADDR 0x11A00000 /* 34 */ | ||
| 767 | #define AU1550_PSC1_PHYS_ADDR 0x11B00000 /* 34 */ | ||
| 768 | #define AU1000_MEM_PHYS_ADDR 0x14000000 /* 01234 */ | ||
| 769 | #define AU1000_STATIC_MEM_PHYS_ADDR 0x14001000 /* 01234 */ | ||
| 770 | #define AU1300_UDMA_PHYS_ADDR 0x14001800 /* 5 */ | ||
| 771 | #define AU1000_DMA_PHYS_ADDR 0x14002000 /* 012 */ | ||
| 772 | #define AU1550_DBDMA_PHYS_ADDR 0x14002000 /* 345 */ | ||
| 773 | #define AU1550_DBDMA_CONF_PHYS_ADDR 0x14003000 /* 345 */ | ||
| 774 | #define AU1000_MACDMA0_PHYS_ADDR 0x14004000 /* 0123 */ | ||
| 775 | #define AU1000_MACDMA1_PHYS_ADDR 0x14004200 /* 0123 */ | ||
| 776 | #define AU1200_CIM_PHYS_ADDR 0x14004000 /* 45 */ | ||
| 777 | #define AU1500_PCI_PHYS_ADDR 0x14005000 /* 13 */ | ||
| 778 | #define AU1550_PE_PHYS_ADDR 0x14008000 /* 3 */ | ||
| 779 | #define AU1200_MAEBE_PHYS_ADDR 0x14010000 /* 4 */ | ||
| 780 | #define AU1200_MAEFE_PHYS_ADDR 0x14012000 /* 4 */ | ||
| 781 | #define AU1300_MAEITE_PHYS_ADDR 0x14010000 /* 5 */ | ||
| 782 | #define AU1300_MAEMPE_PHYS_ADDR 0x14014000 /* 5 */ | ||
| 783 | #define AU1550_USB_OHCI_PHYS_ADDR 0x14020000 /* 3 */ | ||
| 784 | #define AU1200_USB_CTL_PHYS_ADDR 0x14020000 /* 4 */ | ||
| 785 | #define AU1200_USB_OTG_PHYS_ADDR 0x14020020 /* 4 */ | ||
| 786 | #define AU1200_USB_OHCI_PHYS_ADDR 0x14020100 /* 4 */ | ||
| 787 | #define AU1200_USB_EHCI_PHYS_ADDR 0x14020200 /* 4 */ | ||
| 788 | #define AU1200_USB_UDC_PHYS_ADDR 0x14022000 /* 4 */ | ||
| 789 | #define AU1300_USB_EHCI_PHYS_ADDR 0x14020000 /* 5 */ | ||
| 790 | #define AU1300_USB_OHCI0_PHYS_ADDR 0x14020400 /* 5 */ | ||
| 791 | #define AU1300_USB_OHCI1_PHYS_ADDR 0x14020800 /* 5 */ | ||
| 792 | #define AU1300_USB_CTL_PHYS_ADDR 0x14021000 /* 5 */ | ||
| 793 | #define AU1300_USB_OTG_PHYS_ADDR 0x14022000 /* 5 */ | ||
| 794 | #define AU1300_MAEBSA_PHYS_ADDR 0x14030000 /* 5 */ | ||
| 795 | #define AU1100_LCD_PHYS_ADDR 0x15000000 /* 2 */ | ||
| 796 | #define AU1200_LCD_PHYS_ADDR 0x15000000 /* 45 */ | ||
| 797 | #define AU1500_PCI_MEM_PHYS_ADDR 0x400000000ULL /* 13 */ | ||
| 798 | #define AU1500_PCI_IO_PHYS_ADDR 0x500000000ULL /* 13 */ | ||
| 799 | #define AU1500_PCI_CONFIG0_PHYS_ADDR 0x600000000ULL /* 13 */ | ||
| 800 | #define AU1500_PCI_CONFIG1_PHYS_ADDR 0x680000000ULL /* 13 */ | ||
| 801 | #define AU1000_PCMCIA_IO_PHYS_ADDR 0xF00000000ULL /* 012345 */ | ||
| 802 | #define AU1000_PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL /* 012345 */ | ||
| 803 | #define AU1000_PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL /* 012345 */ | ||
| 804 | |||
| 805 | /**********************************************************************/ | ||
| 806 | |||
| 807 | |||
| 808 | /* | ||
| 809 | * Au1300 GPIO+INT controller (GPIC) register offsets and bits | ||
| 810 | * Registers are 128bits (0x10 bytes), divided into 4 "banks". | ||
| 811 | */ | ||
| 812 | #define AU1300_GPIC_PINVAL 0x0000 | ||
| 813 | #define AU1300_GPIC_PINVALCLR 0x0010 | ||
| 814 | #define AU1300_GPIC_IPEND 0x0020 | ||
| 815 | #define AU1300_GPIC_PRIENC 0x0030 | ||
| 816 | #define AU1300_GPIC_IEN 0x0040 /* int_mask in manual */ | ||
| 817 | #define AU1300_GPIC_IDIS 0x0050 /* int_maskclr in manual */ | ||
| 818 | #define AU1300_GPIC_DMASEL 0x0060 | ||
| 819 | #define AU1300_GPIC_DEVSEL 0x0080 | ||
| 820 | #define AU1300_GPIC_DEVCLR 0x0090 | ||
| 821 | #define AU1300_GPIC_RSTVAL 0x00a0 | ||
| 822 | /* pin configuration space. one 32bit register for up to 128 IRQs */ | ||
| 823 | #define AU1300_GPIC_PINCFG 0x1000 | ||
| 824 | |||
| 825 | #define GPIC_GPIO_TO_BIT(gpio) \ | ||
| 826 | (1 << ((gpio) & 0x1f)) | ||
| 827 | |||
| 828 | #define GPIC_GPIO_BANKOFF(gpio) \ | ||
| 829 | (((gpio) >> 5) * 4) | ||
| 830 | |||
| 831 | /* Pin Control bits: who owns the pin, what does it do */ | ||
| 832 | #define GPIC_CFG_PC_GPIN 0 | ||
| 833 | #define GPIC_CFG_PC_DEV 1 | ||
| 834 | #define GPIC_CFG_PC_GPOLOW 2 | ||
| 835 | #define GPIC_CFG_PC_GPOHIGH 3 | ||
| 836 | #define GPIC_CFG_PC_MASK 3 | ||
| 837 | |||
| 838 | /* assign pin to MIPS IRQ line */ | ||
| 839 | #define GPIC_CFG_IL_SET(x) (((x) & 3) << 2) | ||
| 840 | #define GPIC_CFG_IL_MASK (3 << 2) | ||
| 841 | |||
| 842 | /* pin interrupt type setup */ | ||
| 843 | #define GPIC_CFG_IC_OFF (0 << 4) | ||
| 844 | #define GPIC_CFG_IC_LEVEL_LOW (1 << 4) | ||
| 845 | #define GPIC_CFG_IC_LEVEL_HIGH (2 << 4) | ||
| 846 | #define GPIC_CFG_IC_EDGE_FALL (5 << 4) | ||
| 847 | #define GPIC_CFG_IC_EDGE_RISE (6 << 4) | ||
| 848 | #define GPIC_CFG_IC_EDGE_BOTH (7 << 4) | ||
| 849 | #define GPIC_CFG_IC_MASK (7 << 4) | ||
| 850 | |||
| 851 | /* allow interrupt to wake cpu from 'wait' */ | ||
| 852 | #define GPIC_CFG_IDLEWAKE (1 << 7) | ||
| 853 | |||
| 854 | /***********************************************************************/ | ||
| 855 | |||
| 856 | /* Au1000 SDRAM memory controller register offsets */ | ||
| 857 | #define AU1000_MEM_SDMODE0 0x0000 | ||
| 858 | #define AU1000_MEM_SDMODE1 0x0004 | ||
| 859 | #define AU1000_MEM_SDMODE2 0x0008 | ||
| 860 | #define AU1000_MEM_SDADDR0 0x000C | ||
| 861 | #define AU1000_MEM_SDADDR1 0x0010 | ||
| 862 | #define AU1000_MEM_SDADDR2 0x0014 | ||
| 863 | #define AU1000_MEM_SDREFCFG 0x0018 | ||
| 864 | #define AU1000_MEM_SDPRECMD 0x001C | ||
| 865 | #define AU1000_MEM_SDAUTOREF 0x0020 | ||
| 866 | #define AU1000_MEM_SDWRMD0 0x0024 | ||
| 867 | #define AU1000_MEM_SDWRMD1 0x0028 | ||
| 868 | #define AU1000_MEM_SDWRMD2 0x002C | ||
| 869 | #define AU1000_MEM_SDSLEEP 0x0030 | ||
| 870 | #define AU1000_MEM_SDSMCKE 0x0034 | ||
| 871 | |||
| 872 | /* MEM_SDMODE register content definitions */ | ||
| 873 | #define MEM_SDMODE_F (1 << 22) | ||
| 874 | #define MEM_SDMODE_SR (1 << 21) | ||
| 875 | #define MEM_SDMODE_BS (1 << 20) | ||
| 876 | #define MEM_SDMODE_RS (3 << 18) | ||
| 877 | #define MEM_SDMODE_CS (7 << 15) | ||
| 878 | #define MEM_SDMODE_TRAS (15 << 11) | ||
| 879 | #define MEM_SDMODE_TMRD (3 << 9) | ||
| 880 | #define MEM_SDMODE_TWR (3 << 7) | ||
| 881 | #define MEM_SDMODE_TRP (3 << 5) | ||
| 882 | #define MEM_SDMODE_TRCD (3 << 3) | ||
| 883 | #define MEM_SDMODE_TCL (7 << 0) | ||
| 884 | |||
| 885 | #define MEM_SDMODE_BS_2Bank (0 << 20) | ||
| 886 | #define MEM_SDMODE_BS_4Bank (1 << 20) | ||
| 887 | #define MEM_SDMODE_RS_11Row (0 << 18) | ||
| 888 | #define MEM_SDMODE_RS_12Row (1 << 18) | ||
| 889 | #define MEM_SDMODE_RS_13Row (2 << 18) | ||
| 890 | #define MEM_SDMODE_RS_N(N) ((N) << 18) | ||
| 891 | #define MEM_SDMODE_CS_7Col (0 << 15) | ||
| 892 | #define MEM_SDMODE_CS_8Col (1 << 15) | ||
| 893 | #define MEM_SDMODE_CS_9Col (2 << 15) | ||
| 894 | #define MEM_SDMODE_CS_10Col (3 << 15) | ||
| 895 | #define MEM_SDMODE_CS_11Col (4 << 15) | ||
| 896 | #define MEM_SDMODE_CS_N(N) ((N) << 15) | ||
| 897 | #define MEM_SDMODE_TRAS_N(N) ((N) << 11) | ||
| 898 | #define MEM_SDMODE_TMRD_N(N) ((N) << 9) | ||
| 899 | #define MEM_SDMODE_TWR_N(N) ((N) << 7) | ||
| 900 | #define MEM_SDMODE_TRP_N(N) ((N) << 5) | ||
| 901 | #define MEM_SDMODE_TRCD_N(N) ((N) << 3) | ||
| 902 | #define MEM_SDMODE_TCL_N(N) ((N) << 0) | ||
| 903 | |||
| 904 | /* MEM_SDADDR register contents definitions */ | ||
| 905 | #define MEM_SDADDR_E (1 << 20) | ||
| 906 | #define MEM_SDADDR_CSBA (0x03FF << 10) | ||
| 907 | #define MEM_SDADDR_CSMASK (0x03FF << 0) | ||
| 908 | #define MEM_SDADDR_CSBA_N(N) ((N) & (0x03FF << 22) >> 12) | ||
| 909 | #define MEM_SDADDR_CSMASK_N(N) ((N)&(0x03FF << 22) >> 22) | ||
| 910 | |||
| 911 | /* MEM_SDREFCFG register content definitions */ | ||
| 912 | #define MEM_SDREFCFG_TRC (15 << 28) | ||
| 913 | #define MEM_SDREFCFG_TRPM (3 << 26) | ||
| 914 | #define MEM_SDREFCFG_E (1 << 25) | ||
| 915 | #define MEM_SDREFCFG_RE (0x1ffffff << 0) | ||
| 916 | #define MEM_SDREFCFG_TRC_N(N) ((N) << MEM_SDREFCFG_TRC) | ||
| 917 | #define MEM_SDREFCFG_TRPM_N(N) ((N) << MEM_SDREFCFG_TRPM) | ||
| 918 | #define MEM_SDREFCFG_REF_N(N) (N) | ||
| 919 | |||
| 920 | /* Au1550 SDRAM Register Offsets */ | ||
| 921 | #define AU1550_MEM_SDMODE0 0x0800 | ||
| 922 | #define AU1550_MEM_SDMODE1 0x0808 | ||
| 923 | #define AU1550_MEM_SDMODE2 0x0810 | ||
| 924 | #define AU1550_MEM_SDADDR0 0x0820 | ||
| 925 | #define AU1550_MEM_SDADDR1 0x0828 | ||
| 926 | #define AU1550_MEM_SDADDR2 0x0830 | ||
| 927 | #define AU1550_MEM_SDCONFIGA 0x0840 | ||
| 928 | #define AU1550_MEM_SDCONFIGB 0x0848 | ||
| 929 | #define AU1550_MEM_SDSTAT 0x0850 | ||
| 930 | #define AU1550_MEM_SDERRADDR 0x0858 | ||
| 931 | #define AU1550_MEM_SDSTRIDE0 0x0860 | ||
| 932 | #define AU1550_MEM_SDSTRIDE1 0x0868 | ||
| 933 | #define AU1550_MEM_SDSTRIDE2 0x0870 | ||
| 934 | #define AU1550_MEM_SDWRMD0 0x0880 | ||
| 935 | #define AU1550_MEM_SDWRMD1 0x0888 | ||
| 936 | #define AU1550_MEM_SDWRMD2 0x0890 | ||
| 937 | #define AU1550_MEM_SDPRECMD 0x08C0 | ||
| 938 | #define AU1550_MEM_SDAUTOREF 0x08C8 | ||
| 939 | #define AU1550_MEM_SDSREF 0x08D0 | ||
| 940 | #define AU1550_MEM_SDSLEEP MEM_SDSREF | ||
| 941 | |||
| 942 | /* Static Bus Controller */ | ||
| 943 | #define MEM_STCFG0 0xB4001000 | ||
| 944 | #define MEM_STTIME0 0xB4001004 | ||
| 945 | #define MEM_STADDR0 0xB4001008 | ||
| 946 | |||
| 947 | #define MEM_STCFG1 0xB4001010 | ||
| 948 | #define MEM_STTIME1 0xB4001014 | ||
| 949 | #define MEM_STADDR1 0xB4001018 | ||
| 950 | |||
| 951 | #define MEM_STCFG2 0xB4001020 | ||
| 952 | #define MEM_STTIME2 0xB4001024 | ||
| 953 | #define MEM_STADDR2 0xB4001028 | ||
| 954 | |||
| 955 | #define MEM_STCFG3 0xB4001030 | ||
| 956 | #define MEM_STTIME3 0xB4001034 | ||
| 957 | #define MEM_STADDR3 0xB4001038 | ||
| 958 | |||
| 959 | #define MEM_STNDCTL 0xB4001100 | ||
| 960 | #define MEM_STSTAT 0xB4001104 | ||
| 961 | |||
| 962 | #define MEM_STNAND_CMD 0x0 | ||
| 963 | #define MEM_STNAND_ADDR 0x4 | ||
| 964 | #define MEM_STNAND_DATA 0x20 | ||
| 965 | |||
| 966 | |||
| 967 | /* Programmable Counters 0 and 1 */ | ||
| 968 | #define SYS_BASE 0xB1900000 | ||
| 969 | #define SYS_COUNTER_CNTRL (SYS_BASE + 0x14) | ||
| 970 | # define SYS_CNTRL_E1S (1 << 23) | ||
| 971 | # define SYS_CNTRL_T1S (1 << 20) | ||
| 972 | # define SYS_CNTRL_M21 (1 << 19) | ||
| 973 | # define SYS_CNTRL_M11 (1 << 18) | ||
| 974 | # define SYS_CNTRL_M01 (1 << 17) | ||
| 975 | # define SYS_CNTRL_C1S (1 << 16) | ||
| 976 | # define SYS_CNTRL_BP (1 << 14) | ||
| 977 | # define SYS_CNTRL_EN1 (1 << 13) | ||
| 978 | # define SYS_CNTRL_BT1 (1 << 12) | ||
| 979 | # define SYS_CNTRL_EN0 (1 << 11) | ||
| 980 | # define SYS_CNTRL_BT0 (1 << 10) | ||
| 981 | # define SYS_CNTRL_E0 (1 << 8) | ||
| 982 | # define SYS_CNTRL_E0S (1 << 7) | ||
| 983 | # define SYS_CNTRL_32S (1 << 5) | ||
| 984 | # define SYS_CNTRL_T0S (1 << 4) | ||
| 985 | # define SYS_CNTRL_M20 (1 << 3) | ||
| 986 | # define SYS_CNTRL_M10 (1 << 2) | ||
| 987 | # define SYS_CNTRL_M00 (1 << 1) | ||
| 988 | # define SYS_CNTRL_C0S (1 << 0) | ||
| 989 | |||
| 990 | /* Programmable Counter 0 Registers */ | ||
| 991 | #define SYS_TOYTRIM (SYS_BASE + 0) | ||
| 992 | #define SYS_TOYWRITE (SYS_BASE + 4) | ||
| 993 | #define SYS_TOYMATCH0 (SYS_BASE + 8) | ||
| 994 | #define SYS_TOYMATCH1 (SYS_BASE + 0xC) | ||
| 995 | #define SYS_TOYMATCH2 (SYS_BASE + 0x10) | ||
| 996 | #define SYS_TOYREAD (SYS_BASE + 0x40) | ||
| 997 | |||
| 998 | /* Programmable Counter 1 Registers */ | ||
| 999 | #define SYS_RTCTRIM (SYS_BASE + 0x44) | ||
| 1000 | #define SYS_RTCWRITE (SYS_BASE + 0x48) | ||
| 1001 | #define SYS_RTCMATCH0 (SYS_BASE + 0x4C) | ||
| 1002 | #define SYS_RTCMATCH1 (SYS_BASE + 0x50) | ||
| 1003 | #define SYS_RTCMATCH2 (SYS_BASE + 0x54) | ||
| 1004 | #define SYS_RTCREAD (SYS_BASE + 0x58) | ||
| 1005 | |||
| 1006 | |||
| 1007 | /* | ||
| 1008 | * The IrDA peripheral has an IRFIRSEL pin, but on the DB/PB boards it's not | ||
| 1009 | * used to select FIR/SIR mode on the transceiver but as a GPIO. Instead a | ||
| 1010 | * CPLD has to be told about the mode. | ||
| 1011 | */ | ||
| 1012 | #define AU1000_IRDA_PHY_MODE_OFF 0 | ||
| 1013 | #define AU1000_IRDA_PHY_MODE_SIR 1 | ||
| 1014 | #define AU1000_IRDA_PHY_MODE_FIR 2 | ||
| 1015 | |||
| 1016 | struct au1k_irda_platform_data { | ||
| 1017 | void(*set_phy_mode)(int mode); | ||
| 1018 | }; | ||
| 1019 | |||
| 1020 | |||
| 1021 | /* GPIO */ | ||
| 1022 | #define SYS_PINFUNC 0xB190002C | ||
| 1023 | # define SYS_PF_USB (1 << 15) /* 2nd USB device/host */ | ||
| 1024 | # define SYS_PF_U3 (1 << 14) /* GPIO23/U3TXD */ | ||
| 1025 | # define SYS_PF_U2 (1 << 13) /* GPIO22/U2TXD */ | ||
| 1026 | # define SYS_PF_U1 (1 << 12) /* GPIO21/U1TXD */ | ||
| 1027 | # define SYS_PF_SRC (1 << 11) /* GPIO6/SROMCKE */ | ||
| 1028 | # define SYS_PF_CK5 (1 << 10) /* GPIO3/CLK5 */ | ||
| 1029 | # define SYS_PF_CK4 (1 << 9) /* GPIO2/CLK4 */ | ||
| 1030 | # define SYS_PF_IRF (1 << 8) /* GPIO15/IRFIRSEL */ | ||
| 1031 | # define SYS_PF_UR3 (1 << 7) /* GPIO[14:9]/UART3 */ | ||
| 1032 | # define SYS_PF_I2D (1 << 6) /* GPIO8/I2SDI */ | ||
| 1033 | # define SYS_PF_I2S (1 << 5) /* I2S/GPIO[29:31] */ | ||
| 1034 | # define SYS_PF_NI2 (1 << 4) /* NI2/GPIO[24:28] */ | ||
| 1035 | # define SYS_PF_U0 (1 << 3) /* U0TXD/GPIO20 */ | ||
| 1036 | # define SYS_PF_RD (1 << 2) /* IRTXD/GPIO19 */ | ||
| 1037 | # define SYS_PF_A97 (1 << 1) /* AC97/SSL1 */ | ||
| 1038 | # define SYS_PF_S0 (1 << 0) /* SSI_0/GPIO[16:18] */ | ||
| 1039 | |||
| 1040 | /* Au1100 only */ | ||
| 1041 | # define SYS_PF_PC (1 << 18) /* PCMCIA/GPIO[207:204] */ | ||
| 1042 | # define SYS_PF_LCD (1 << 17) /* extern lcd/GPIO[203:200] */ | ||
| 1043 | # define SYS_PF_CS (1 << 16) /* EXTCLK0/32KHz to gpio2 */ | ||
| 1044 | # define SYS_PF_EX0 (1 << 9) /* GPIO2/clock */ | ||
| 1045 | |||
| 1046 | /* Au1550 only. Redefines lots of pins */ | ||
| 1047 | # define SYS_PF_PSC2_MASK (7 << 17) | ||
| 1048 | # define SYS_PF_PSC2_AC97 0 | ||
| 1049 | # define SYS_PF_PSC2_SPI 0 | ||
| 1050 | # define SYS_PF_PSC2_I2S (1 << 17) | ||
| 1051 | # define SYS_PF_PSC2_SMBUS (3 << 17) | ||
| 1052 | # define SYS_PF_PSC2_GPIO (7 << 17) | ||
| 1053 | # define SYS_PF_PSC3_MASK (7 << 20) | ||
| 1054 | # define SYS_PF_PSC3_AC97 0 | ||
| 1055 | # define SYS_PF_PSC3_SPI 0 | ||
| 1056 | # define SYS_PF_PSC3_I2S (1 << 20) | ||
| 1057 | # define SYS_PF_PSC3_SMBUS (3 << 20) | ||
| 1058 | # define SYS_PF_PSC3_GPIO (7 << 20) | ||
| 1059 | # define SYS_PF_PSC1_S1 (1 << 1) | ||
| 1060 | # define SYS_PF_MUST_BE_SET ((1 << 5) | (1 << 2)) | ||
| 1061 | |||
| 1062 | /* Au1200 only */ | ||
| 1063 | #define SYS_PINFUNC_DMA (1 << 31) | ||
| 1064 | #define SYS_PINFUNC_S0A (1 << 30) | ||
| 1065 | #define SYS_PINFUNC_S1A (1 << 29) | ||
| 1066 | #define SYS_PINFUNC_LP0 (1 << 28) | ||
| 1067 | #define SYS_PINFUNC_LP1 (1 << 27) | ||
| 1068 | #define SYS_PINFUNC_LD16 (1 << 26) | ||
| 1069 | #define SYS_PINFUNC_LD8 (1 << 25) | ||
| 1070 | #define SYS_PINFUNC_LD1 (1 << 24) | ||
| 1071 | #define SYS_PINFUNC_LD0 (1 << 23) | ||
| 1072 | #define SYS_PINFUNC_P1A (3 << 21) | ||
| 1073 | #define SYS_PINFUNC_P1B (1 << 20) | ||
| 1074 | #define SYS_PINFUNC_FS3 (1 << 19) | ||
| 1075 | #define SYS_PINFUNC_P0A (3 << 17) | ||
| 1076 | #define SYS_PINFUNC_CS (1 << 16) | ||
| 1077 | #define SYS_PINFUNC_CIM (1 << 15) | ||
| 1078 | #define SYS_PINFUNC_P1C (1 << 14) | ||
| 1079 | #define SYS_PINFUNC_U1T (1 << 12) | ||
| 1080 | #define SYS_PINFUNC_U1R (1 << 11) | ||
| 1081 | #define SYS_PINFUNC_EX1 (1 << 10) | ||
| 1082 | #define SYS_PINFUNC_EX0 (1 << 9) | ||
| 1083 | #define SYS_PINFUNC_U0R (1 << 8) | ||
| 1084 | #define SYS_PINFUNC_MC (1 << 7) | ||
| 1085 | #define SYS_PINFUNC_S0B (1 << 6) | ||
| 1086 | #define SYS_PINFUNC_S0C (1 << 5) | ||
| 1087 | #define SYS_PINFUNC_P0B (1 << 4) | ||
| 1088 | #define SYS_PINFUNC_U0T (1 << 3) | ||
| 1089 | #define SYS_PINFUNC_S1B (1 << 2) | ||
| 1090 | |||
| 1091 | /* Power Management */ | ||
| 1092 | #define SYS_SCRATCH0 0xB1900018 | ||
| 1093 | #define SYS_SCRATCH1 0xB190001C | ||
| 1094 | #define SYS_WAKEMSK 0xB1900034 | ||
| 1095 | #define SYS_ENDIAN 0xB1900038 | ||
| 1096 | #define SYS_POWERCTRL 0xB190003C | ||
| 1097 | #define SYS_WAKESRC 0xB190005C | ||
| 1098 | #define SYS_SLPPWR 0xB1900078 | ||
| 1099 | #define SYS_SLEEP 0xB190007C | ||
| 1100 | |||
| 1101 | #define SYS_WAKEMSK_D2 (1 << 9) | ||
| 1102 | #define SYS_WAKEMSK_M2 (1 << 8) | ||
| 1103 | #define SYS_WAKEMSK_GPIO(x) (1 << (x)) | ||
| 1104 | |||
| 1105 | /* Clock Controller */ | ||
| 1106 | #define SYS_FREQCTRL0 0xB1900020 | ||
| 1107 | # define SYS_FC_FRDIV2_BIT 22 | ||
| 1108 | # define SYS_FC_FRDIV2_MASK (0xff << SYS_FC_FRDIV2_BIT) | ||
| 1109 | # define SYS_FC_FE2 (1 << 21) | ||
| 1110 | # define SYS_FC_FS2 (1 << 20) | ||
| 1111 | # define SYS_FC_FRDIV1_BIT 12 | ||
| 1112 | # define SYS_FC_FRDIV1_MASK (0xff << SYS_FC_FRDIV1_BIT) | ||
| 1113 | # define SYS_FC_FE1 (1 << 11) | ||
| 1114 | # define SYS_FC_FS1 (1 << 10) | ||
| 1115 | # define SYS_FC_FRDIV0_BIT 2 | ||
| 1116 | # define SYS_FC_FRDIV0_MASK (0xff << SYS_FC_FRDIV0_BIT) | ||
| 1117 | # define SYS_FC_FE0 (1 << 1) | ||
| 1118 | # define SYS_FC_FS0 (1 << 0) | ||
| 1119 | #define SYS_FREQCTRL1 0xB1900024 | ||
| 1120 | # define SYS_FC_FRDIV5_BIT 22 | ||
| 1121 | # define SYS_FC_FRDIV5_MASK (0xff << SYS_FC_FRDIV5_BIT) | ||
| 1122 | # define SYS_FC_FE5 (1 << 21) | ||
| 1123 | # define SYS_FC_FS5 (1 << 20) | ||
| 1124 | # define SYS_FC_FRDIV4_BIT 12 | ||
| 1125 | # define SYS_FC_FRDIV4_MASK (0xff << SYS_FC_FRDIV4_BIT) | ||
| 1126 | # define SYS_FC_FE4 (1 << 11) | ||
| 1127 | # define SYS_FC_FS4 (1 << 10) | ||
| 1128 | # define SYS_FC_FRDIV3_BIT 2 | ||
| 1129 | # define SYS_FC_FRDIV3_MASK (0xff << SYS_FC_FRDIV3_BIT) | ||
| 1130 | # define SYS_FC_FE3 (1 << 1) | ||
| 1131 | # define SYS_FC_FS3 (1 << 0) | ||
| 1132 | #define SYS_CLKSRC 0xB1900028 | ||
| 1133 | # define SYS_CS_ME1_BIT 27 | ||
| 1134 | # define SYS_CS_ME1_MASK (0x7 << SYS_CS_ME1_BIT) | ||
| 1135 | # define SYS_CS_DE1 (1 << 26) | ||
| 1136 | # define SYS_CS_CE1 (1 << 25) | ||
| 1137 | # define SYS_CS_ME0_BIT 22 | ||
| 1138 | # define SYS_CS_ME0_MASK (0x7 << SYS_CS_ME0_BIT) | ||
| 1139 | # define SYS_CS_DE0 (1 << 21) | ||
| 1140 | # define SYS_CS_CE0 (1 << 20) | ||
| 1141 | # define SYS_CS_MI2_BIT 17 | ||
| 1142 | # define SYS_CS_MI2_MASK (0x7 << SYS_CS_MI2_BIT) | ||
| 1143 | # define SYS_CS_DI2 (1 << 16) | ||
| 1144 | # define SYS_CS_CI2 (1 << 15) | ||
| 1145 | |||
| 1146 | # define SYS_CS_ML_BIT 7 | ||
| 1147 | # define SYS_CS_ML_MASK (0x7 << SYS_CS_ML_BIT) | ||
| 1148 | # define SYS_CS_DL (1 << 6) | ||
| 1149 | # define SYS_CS_CL (1 << 5) | ||
| 1150 | |||
| 1151 | # define SYS_CS_MUH_BIT 12 | ||
| 1152 | # define SYS_CS_MUH_MASK (0x7 << SYS_CS_MUH_BIT) | ||
| 1153 | # define SYS_CS_DUH (1 << 11) | ||
| 1154 | # define SYS_CS_CUH (1 << 10) | ||
| 1155 | # define SYS_CS_MUD_BIT 7 | ||
| 1156 | # define SYS_CS_MUD_MASK (0x7 << SYS_CS_MUD_BIT) | ||
| 1157 | # define SYS_CS_DUD (1 << 6) | ||
| 1158 | # define SYS_CS_CUD (1 << 5) | ||
| 1159 | |||
| 1160 | # define SYS_CS_MIR_BIT 2 | ||
| 1161 | # define SYS_CS_MIR_MASK (0x7 << SYS_CS_MIR_BIT) | ||
| 1162 | # define SYS_CS_DIR (1 << 1) | ||
| 1163 | # define SYS_CS_CIR (1 << 0) | ||
| 1164 | |||
| 1165 | # define SYS_CS_MUX_AUX 0x1 | ||
| 1166 | # define SYS_CS_MUX_FQ0 0x2 | ||
| 1167 | # define SYS_CS_MUX_FQ1 0x3 | ||
| 1168 | # define SYS_CS_MUX_FQ2 0x4 | ||
| 1169 | # define SYS_CS_MUX_FQ3 0x5 | ||
| 1170 | # define SYS_CS_MUX_FQ4 0x6 | ||
| 1171 | # define SYS_CS_MUX_FQ5 0x7 | ||
| 1172 | #define SYS_CPUPLL 0xB1900060 | ||
| 1173 | #define SYS_AUXPLL 0xB1900064 | ||
| 1174 | |||
| 1175 | |||
| 1176 | /* The PCI chip selects are outside the 32bit space, and since we can't | ||
| 1177 | * just program the 36bit addresses into BARs, we have to take a chunk | ||
| 1178 | * out of the 32bit space and reserve it for PCI. When these addresses | ||
| 1179 | * are ioremap()ed, they'll be fixed up to the real 36bit address before | ||
| 1180 | * being passed to the real ioremap function. | ||
| 1181 | */ | ||
| 1182 | #define ALCHEMY_PCI_MEMWIN_START (AU1500_PCI_MEM_PHYS_ADDR >> 4) | ||
| 1183 | #define ALCHEMY_PCI_MEMWIN_END (ALCHEMY_PCI_MEMWIN_START + 0x0FFFFFFF) | ||
| 1184 | |||
| 1185 | /* for PCI IO it's simpler because we get to do the ioremap ourselves and then | ||
| 1186 | * adjust the device's resources. | ||
| 1187 | */ | ||
| 1188 | #define ALCHEMY_PCI_IOWIN_START 0x00001000 | ||
| 1189 | #define ALCHEMY_PCI_IOWIN_END 0x0000FFFF | ||
| 1190 | |||
| 1191 | #ifdef CONFIG_PCI | ||
| 1192 | |||
| 1193 | #define IOPORT_RESOURCE_START 0x00001000 /* skip legacy probing */ | ||
| 1194 | #define IOPORT_RESOURCE_END 0xffffffff | ||
| 1195 | #define IOMEM_RESOURCE_START 0x10000000 | ||
| 1196 | #define IOMEM_RESOURCE_END 0xfffffffffULL | ||
| 1197 | |||
| 1198 | #else | ||
| 1199 | |||
| 1200 | /* Don't allow any legacy ports probing */ | ||
| 1201 | #define IOPORT_RESOURCE_START 0x10000000 | ||
| 1202 | #define IOPORT_RESOURCE_END 0xffffffff | ||
| 1203 | #define IOMEM_RESOURCE_START 0x10000000 | ||
| 1204 | #define IOMEM_RESOURCE_END 0xfffffffffULL | ||
| 1205 | |||
| 1206 | #endif | ||
| 1207 | |||
| 1208 | /* PCI controller block register offsets */ | ||
| 1209 | #define PCI_REG_CMEM 0x0000 | ||
| 1210 | #define PCI_REG_CONFIG 0x0004 | ||
| 1211 | #define PCI_REG_B2BMASK_CCH 0x0008 | ||
| 1212 | #define PCI_REG_B2BBASE0_VID 0x000C | ||
| 1213 | #define PCI_REG_B2BBASE1_SID 0x0010 | ||
| 1214 | #define PCI_REG_MWMASK_DEV 0x0014 | ||
| 1215 | #define PCI_REG_MWBASE_REV_CCL 0x0018 | ||
| 1216 | #define PCI_REG_ERR_ADDR 0x001C | ||
| 1217 | #define PCI_REG_SPEC_INTACK 0x0020 | ||
| 1218 | #define PCI_REG_ID 0x0100 | ||
| 1219 | #define PCI_REG_STATCMD 0x0104 | ||
| 1220 | #define PCI_REG_CLASSREV 0x0108 | ||
| 1221 | #define PCI_REG_PARAM 0x010C | ||
| 1222 | #define PCI_REG_MBAR 0x0110 | ||
| 1223 | #define PCI_REG_TIMEOUT 0x0140 | ||
| 1224 | |||
| 1225 | /* PCI controller block register bits */ | ||
| 1226 | #define PCI_CMEM_E (1 << 28) /* enable cacheable memory */ | ||
| 1227 | #define PCI_CMEM_CMBASE(x) (((x) & 0x3fff) << 14) | ||
| 1228 | #define PCI_CMEM_CMMASK(x) ((x) & 0x3fff) | ||
| 1229 | #define PCI_CONFIG_ERD (1 << 27) /* pci error during R/W */ | ||
| 1230 | #define PCI_CONFIG_ET (1 << 26) /* error in target mode */ | ||
| 1231 | #define PCI_CONFIG_EF (1 << 25) /* fatal error */ | ||
| 1232 | #define PCI_CONFIG_EP (1 << 24) /* parity error */ | ||
| 1233 | #define PCI_CONFIG_EM (1 << 23) /* multiple errors */ | ||
| 1234 | #define PCI_CONFIG_BM (1 << 22) /* bad master error */ | ||
| 1235 | #define PCI_CONFIG_PD (1 << 20) /* PCI Disable */ | ||
| 1236 | #define PCI_CONFIG_BME (1 << 19) /* Byte Mask Enable for reads */ | ||
| 1237 | #define PCI_CONFIG_NC (1 << 16) /* mark mem access non-coherent */ | ||
| 1238 | #define PCI_CONFIG_IA (1 << 15) /* INTA# enabled (target mode) */ | ||
| 1239 | #define PCI_CONFIG_IP (1 << 13) /* int on PCI_PERR# */ | ||
| 1240 | #define PCI_CONFIG_IS (1 << 12) /* int on PCI_SERR# */ | ||
| 1241 | #define PCI_CONFIG_IMM (1 << 11) /* int on master abort */ | ||
| 1242 | #define PCI_CONFIG_ITM (1 << 10) /* int on target abort (as master) */ | ||
| 1243 | #define PCI_CONFIG_ITT (1 << 9) /* int on target abort (as target) */ | ||
| 1244 | #define PCI_CONFIG_IPB (1 << 8) /* int on PERR# in bus master acc */ | ||
| 1245 | #define PCI_CONFIG_SIC_NO (0 << 6) /* no byte mask changes */ | ||
| 1246 | #define PCI_CONFIG_SIC_BA_ADR (1 << 6) /* on byte/hw acc, invert adr bits */ | ||
| 1247 | #define PCI_CONFIG_SIC_HWA_DAT (2 << 6) /* on halfword acc, swap data */ | ||
| 1248 | #define PCI_CONFIG_SIC_ALL (3 << 6) /* swap data bytes on all accesses */ | ||
| 1249 | #define PCI_CONFIG_ST (1 << 5) /* swap data by target transactions */ | ||
| 1250 | #define PCI_CONFIG_SM (1 << 4) /* swap data from PCI ctl */ | ||
| 1251 | #define PCI_CONFIG_AEN (1 << 3) /* enable internal arbiter */ | ||
| 1252 | #define PCI_CONFIG_R2H (1 << 2) /* REQ2# to hi-prio arbiter */ | ||
| 1253 | #define PCI_CONFIG_R1H (1 << 1) /* REQ1# to hi-prio arbiter */ | ||
| 1254 | #define PCI_CONFIG_CH (1 << 0) /* PCI ctl to hi-prio arbiter */ | ||
| 1255 | #define PCI_B2BMASK_B2BMASK(x) (((x) & 0xffff) << 16) | ||
| 1256 | #define PCI_B2BMASK_CCH(x) ((x) & 0xffff) /* 16 upper bits of class code */ | ||
| 1257 | #define PCI_B2BBASE0_VID_B0(x) (((x) & 0xffff) << 16) | ||
| 1258 | #define PCI_B2BBASE0_VID_SV(x) ((x) & 0xffff) | ||
| 1259 | #define PCI_B2BBASE1_SID_B1(x) (((x) & 0xffff) << 16) | ||
| 1260 | #define PCI_B2BBASE1_SID_SI(x) ((x) & 0xffff) | ||
| 1261 | #define PCI_MWMASKDEV_MWMASK(x) (((x) & 0xffff) << 16) | ||
| 1262 | #define PCI_MWMASKDEV_DEVID(x) ((x) & 0xffff) | ||
| 1263 | #define PCI_MWBASEREVCCL_BASE(x) (((x) & 0xffff) << 16) | ||
| 1264 | #define PCI_MWBASEREVCCL_REV(x) (((x) & 0xff) << 8) | ||
| 1265 | #define PCI_MWBASEREVCCL_CCL(x) ((x) & 0xff) | ||
| 1266 | #define PCI_ID_DID(x) (((x) & 0xffff) << 16) | ||
| 1267 | #define PCI_ID_VID(x) ((x) & 0xffff) | ||
| 1268 | #define PCI_STATCMD_STATUS(x) (((x) & 0xffff) << 16) | ||
| 1269 | #define PCI_STATCMD_CMD(x) ((x) & 0xffff) | ||
| 1270 | #define PCI_CLASSREV_CLASS(x) (((x) & 0x00ffffff) << 8) | ||
| 1271 | #define PCI_CLASSREV_REV(x) ((x) & 0xff) | ||
| 1272 | #define PCI_PARAM_BIST(x) (((x) & 0xff) << 24) | ||
| 1273 | #define PCI_PARAM_HT(x) (((x) & 0xff) << 16) | ||
| 1274 | #define PCI_PARAM_LT(x) (((x) & 0xff) << 8) | ||
| 1275 | #define PCI_PARAM_CLS(x) ((x) & 0xff) | ||
| 1276 | #define PCI_TIMEOUT_RETRIES(x) (((x) & 0xff) << 8) /* max retries */ | ||
| 1277 | #define PCI_TIMEOUT_TO(x) ((x) & 0xff) /* target ready timeout */ | ||
| 1278 | |||
| 1279 | #endif | 1283 | #endif |