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authorRussell King <rmk+kernel@arm.linux.org.uk>2014-04-06 18:32:25 -0400
committerShawn Guo <shawn.guo@freescale.com>2014-04-13 22:22:37 -0400
commit2e3b9650561ae791ca0bd8c5f4868ef4df3cb842 (patch)
treebb9f48ba90635895d03d8786fbf29cdc0b823f9a /arch
parentc2bece3cb1215bdb68f2345f6a9b5d0b27c8724e (diff)
ARM: dt: microsom: don't set bit 7 for ethernet mux settings
Bit 6,7 are marked as reserved for the ethernet RGMII pins, so avoid setting these bits. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/boot/dts/imx6qdl-microsom-ar8035.dtsi22
1 files changed, 11 insertions, 11 deletions
diff --git a/arch/arm/boot/dts/imx6qdl-microsom-ar8035.dtsi b/arch/arm/boot/dts/imx6qdl-microsom-ar8035.dtsi
index a3cb2fff8f61..d16066608e21 100644
--- a/arch/arm/boot/dts/imx6qdl-microsom-ar8035.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-microsom-ar8035.dtsi
@@ -26,25 +26,25 @@
26 /* GPIO16 -> AR8035 25MHz */ 26 /* GPIO16 -> AR8035 25MHz */
27 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0xc0000000 27 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0xc0000000
28 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x80000000 28 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x80000000
29 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 29 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
30 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 30 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
31 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 31 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
32 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 32 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
33 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 33 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
34 /* AR8035 CLK_25M --> ENET_REF_CLK (V22) */ 34 /* AR8035 CLK_25M --> ENET_REF_CLK (V22) */
35 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x0a0b1 35 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x0a0b1
36 /* AR8035 pin strapping: IO voltage: pull up */ 36 /* AR8035 pin strapping: IO voltage: pull up */
37 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 37 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
38 /* AR8035 pin strapping: PHYADDR#0: pull down */ 38 /* AR8035 pin strapping: PHYADDR#0: pull down */
39 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x130b0 39 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x13030
40 /* AR8035 pin strapping: PHYADDR#1: pull down */ 40 /* AR8035 pin strapping: PHYADDR#1: pull down */
41 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x130b0 41 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x13030
42 /* AR8035 pin strapping: MODE#1: pull up */ 42 /* AR8035 pin strapping: MODE#1: pull up */
43 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 43 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
44 /* AR8035 pin strapping: MODE#3: pull up */ 44 /* AR8035 pin strapping: MODE#3: pull up */
45 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 45 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
46 /* AR8035 pin strapping: MODE#0: pull down */ 46 /* AR8035 pin strapping: MODE#0: pull down */
47 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x130b0 47 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x13030
48 48
49 /* 49 /*
50 * As the RMII pins are also connected to RGMII 50 * As the RMII pins are also connected to RGMII