arm/arm64: KVM: Fix BE accesses to GICv2 EISR and ELRSR regs

The EIRSR and ELRSR registers are 32-bit registers on GICv2, and we
store these as an array of two such registers on the vgic vcpu struct.
However, we access them as a single 64-bit value or as a bitmap pointer
in the generic vgic code, which breaks BE support.

Instead, store them as u64 values on the vgic structure and do the
word-swapping in the assembly code, which already handles the byte order
for BE systems.

Tested-by: Victor Kamensky <victor.kamensky@linaro.org>
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>

2 files changed, 15 insertions, 4 deletions

diff --git a/arch/arm/kvm/interrupts_head.S b/arch/arm/kvm/interrupts_head.S
index 98c8c5b9a87f..14d488388480 100644
--- a/arch/arm/kvm/interrupts_head.S
+++ b/arch/arm/kvm/interrupts_head.S
@@ -433,10 +433,17 @@ ARM_BE8(rev	r10, r10	)
         str     r3, [r11, #VGIC_V2_CPU_HCR]
         str     r4, [r11, #VGIC_V2_CPU_VMCR]
         str     r5, [r11, #VGIC_V2_CPU_MISR]
+#ifdef CONFIG_CPU_ENDIAN_BE8
+        str     r6, [r11, #(VGIC_V2_CPU_EISR + 4)]
+        str     r7, [r11, #VGIC_V2_CPU_EISR]
+        str     r8, [r11, #(VGIC_V2_CPU_ELRSR + 4)]
+        str     r9, [r11, #VGIC_V2_CPU_ELRSR]
+#else
         str     r6, [r11, #VGIC_V2_CPU_EISR]
         str     r7, [r11, #(VGIC_V2_CPU_EISR + 4)]
         str     r8, [r11, #VGIC_V2_CPU_ELRSR]
         str     r9, [r11, #(VGIC_V2_CPU_ELRSR + 4)]
+#endif
         str     r10, [r11, #VGIC_V2_CPU_APR]
 
         /* Clear GICH_HCR */
diff --git a/arch/arm64/kvm/vgic-v2-switch.S b/arch/arm64/kvm/vgic-v2-switch.S
index ae211772f991..f002fe1c3700 100644
--- a/arch/arm64/kvm/vgic-v2-switch.S
+++ b/arch/arm64/kvm/vgic-v2-switch.S
@@ -67,10 +67,14 @@ CPU_BE(	rev	w11, w11 )
         str     w4, [x3, #VGIC_V2_CPU_HCR]
         str     w5, [x3, #VGIC_V2_CPU_VMCR]
         str     w6, [x3, #VGIC_V2_CPU_MISR]
-        str     w7, [x3, #VGIC_V2_CPU_EISR]
-        str     w8, [x3, #(VGIC_V2_CPU_EISR + 4)]
-        str     w9, [x3, #VGIC_V2_CPU_ELRSR]
-        str     w10, [x3, #(VGIC_V2_CPU_ELRSR + 4)]
+CPU_LE( str     w7, [x3, #VGIC_V2_CPU_EISR] )
+CPU_LE( str     w8, [x3, #(VGIC_V2_CPU_EISR + 4)] )
+CPU_LE( str     w9, [x3, #VGIC_V2_CPU_ELRSR] )
+CPU_LE( str     w10, [x3, #(VGIC_V2_CPU_ELRSR + 4)] )
+CPU_BE( str     w7, [x3, #(VGIC_V2_CPU_EISR + 4)] )
+CPU_BE( str     w8, [x3, #VGIC_V2_CPU_EISR] )
+CPU_BE( str     w9, [x3, #(VGIC_V2_CPU_ELRSR + 4)] )
+CPU_BE( str     w10, [x3, #VGIC_V2_CPU_ELRSR] )
         str     w11, [x3, #VGIC_V2_CPU_APR]
 
         /* Clear GICH_HCR */