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authorKuninori Morimoto <kuninori.morimoto.gx@renesas.com>2013-10-21 22:36:02 -0400
committerSimon Horman <horms+renesas@verge.net.au>2013-12-10 03:26:59 -0500
commit2624705ceb7b139cffdb409682d3e1bc480abec7 (patch)
tree5c08a75ba19d7a91f1879288dc0ed0a98804f8a6 /arch
parent14e1d9147d96e0e6cc7f14eb339a7754404b4b73 (diff)
ARM: shmobile: r8a7779: tidyup DT node naming
According to ePAPR spec, this patch tidies up DT node name and related clock. Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/boot/dts/r8a7779.dtsi8
-rw-r--r--arch/arm/mach-shmobile/clock-r8a7779.c8
2 files changed, 8 insertions, 8 deletions
diff --git a/arch/arm/boot/dts/r8a7779.dtsi b/arch/arm/boot/dts/r8a7779.dtsi
index be737efb02b6..05fd41c6012f 100644
--- a/arch/arm/boot/dts/r8a7779.dtsi
+++ b/arch/arm/boot/dts/r8a7779.dtsi
@@ -207,7 +207,7 @@
207 interrupts = <0 100 0x4>; 207 interrupts = <0 100 0x4>;
208 }; 208 };
209 209
210 sdhi0: sdhi@ffe4c000 { 210 sdhi0: sd@ffe4c000 {
211 compatible = "renesas,sdhi-r8a7779"; 211 compatible = "renesas,sdhi-r8a7779";
212 reg = <0xffe4c000 0x100>; 212 reg = <0xffe4c000 0x100>;
213 interrupt-parent = <&gic>; 213 interrupt-parent = <&gic>;
@@ -217,7 +217,7 @@
217 status = "disabled"; 217 status = "disabled";
218 }; 218 };
219 219
220 sdhi1: sdhi@ffe4d000 { 220 sdhi1: sd@ffe4d000 {
221 compatible = "renesas,sdhi-r8a7779"; 221 compatible = "renesas,sdhi-r8a7779";
222 reg = <0xffe4d000 0x100>; 222 reg = <0xffe4d000 0x100>;
223 interrupt-parent = <&gic>; 223 interrupt-parent = <&gic>;
@@ -227,7 +227,7 @@
227 status = "disabled"; 227 status = "disabled";
228 }; 228 };
229 229
230 sdhi2: sdhi@ffe4e000 { 230 sdhi2: sd@ffe4e000 {
231 compatible = "renesas,sdhi-r8a7779"; 231 compatible = "renesas,sdhi-r8a7779";
232 reg = <0xffe4e000 0x100>; 232 reg = <0xffe4e000 0x100>;
233 interrupt-parent = <&gic>; 233 interrupt-parent = <&gic>;
@@ -237,7 +237,7 @@
237 status = "disabled"; 237 status = "disabled";
238 }; 238 };
239 239
240 sdhi3: sdhi@ffe4f000 { 240 sdhi3: sd@ffe4f000 {
241 compatible = "renesas,sdhi-r8a7779"; 241 compatible = "renesas,sdhi-r8a7779";
242 reg = <0xffe4f000 0x100>; 242 reg = <0xffe4f000 0x100>;
243 interrupt-parent = <&gic>; 243 interrupt-parent = <&gic>;
diff --git a/arch/arm/mach-shmobile/clock-r8a7779.c b/arch/arm/mach-shmobile/clock-r8a7779.c
index b545c8dbb818..f1fb89b76786 100644
--- a/arch/arm/mach-shmobile/clock-r8a7779.c
+++ b/arch/arm/mach-shmobile/clock-r8a7779.c
@@ -204,13 +204,13 @@ static struct clk_lookup lookups[] = {
204 CLKDEV_DEV_ID("sh-hspi.2", &mstp_clks[MSTP007]), /* HSPI2 */ 204 CLKDEV_DEV_ID("sh-hspi.2", &mstp_clks[MSTP007]), /* HSPI2 */
205 CLKDEV_DEV_ID("fffc6000.spi", &mstp_clks[MSTP007]), /* HSPI2 */ 205 CLKDEV_DEV_ID("fffc6000.spi", &mstp_clks[MSTP007]), /* HSPI2 */
206 CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP323]), /* SDHI0 */ 206 CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP323]), /* SDHI0 */
207 CLKDEV_DEV_ID("ffe4c000.sdhi", &mstp_clks[MSTP323]), /* SDHI0 */ 207 CLKDEV_DEV_ID("ffe4c000.sd", &mstp_clks[MSTP323]), /* SDHI0 */
208 CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP322]), /* SDHI1 */ 208 CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP322]), /* SDHI1 */
209 CLKDEV_DEV_ID("ffe4d000.sdhi", &mstp_clks[MSTP322]), /* SDHI1 */ 209 CLKDEV_DEV_ID("ffe4d000.sd", &mstp_clks[MSTP322]), /* SDHI1 */
210 CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP321]), /* SDHI2 */ 210 CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP321]), /* SDHI2 */
211 CLKDEV_DEV_ID("ffe4e000.sdhi", &mstp_clks[MSTP321]), /* SDHI2 */ 211 CLKDEV_DEV_ID("ffe4e000.sd", &mstp_clks[MSTP321]), /* SDHI2 */
212 CLKDEV_DEV_ID("sh_mobile_sdhi.3", &mstp_clks[MSTP320]), /* SDHI3 */ 212 CLKDEV_DEV_ID("sh_mobile_sdhi.3", &mstp_clks[MSTP320]), /* SDHI3 */
213 CLKDEV_DEV_ID("ffe4f000.sdhi", &mstp_clks[MSTP320]), /* SDHI3 */ 213 CLKDEV_DEV_ID("ffe4f000.sd", &mstp_clks[MSTP320]), /* SDHI3 */
214 CLKDEV_DEV_ID("rcar-du-r8a7779", &mstp_clks[MSTP103]), /* DU */ 214 CLKDEV_DEV_ID("rcar-du-r8a7779", &mstp_clks[MSTP103]), /* DU */
215}; 215};
216 216