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authorSimon Horman <horms+renesas@verge.net.au>2013-12-24 07:50:13 -0500
committerSimon Horman <horms+renesas@verge.net.au>2013-12-24 07:50:13 -0500
commit20f4e334272dc191e475039d68a3bf3eb46ec66e (patch)
treeb4021dc2a50ed50f3b2d2fac0bf49f6262dc69ba /arch
parentd85bcfa916ffdf078f188aeab60f738b290f4309 (diff)
parentd5917ef318b850fc72bd10db438580f7d1c406d9 (diff)
Merge branch 'sh-soc' into sh-sci2-base
Diffstat (limited to 'arch')
-rw-r--r--arch/sh/kernel/cpu/sh2/setup-sh7619.c30
-rw-r--r--arch/sh/kernel/cpu/sh2a/setup-mxg.c10
-rw-r--r--arch/sh/kernel/cpu/sh2a/setup-sh7201.c80
-rw-r--r--arch/sh/kernel/cpu/sh2a/setup-sh7203.c40
-rw-r--r--arch/sh/kernel/cpu/sh2a/setup-sh7206.c40
-rw-r--r--arch/sh/kernel/cpu/sh2a/setup-sh7264.c104
-rw-r--r--arch/sh/kernel/cpu/sh2a/setup-sh7269.c104
-rw-r--r--arch/sh/kernel/cpu/sh3/setup-sh7705.c20
-rw-r--r--arch/sh/kernel/cpu/sh3/setup-sh770x.c30
-rw-r--r--arch/sh/kernel/cpu/sh3/setup-sh7710.c20
-rw-r--r--arch/sh/kernel/cpu/sh3/setup-sh7720.c20
-rw-r--r--arch/sh/kernel/cpu/sh4/setup-sh4-202.c16
-rw-r--r--arch/sh/kernel/cpu/sh4/setup-sh7750.c20
-rw-r--r--arch/sh/kernel/cpu/sh4/setup-sh7760.c62
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7343.c40
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7366.c10
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7722.c30
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7723.c63
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7724.c63
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7734.c72
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7757.c30
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7763.c30
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7770.c100
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7780.c22
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7785.c60
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7786.c88
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-shx3.c48
-rw-r--r--arch/sh/kernel/cpu/sh5/setup-sh5.c12
28 files changed, 889 insertions, 375 deletions
diff --git a/arch/sh/kernel/cpu/sh2/setup-sh7619.c b/arch/sh/kernel/cpu/sh2/setup-sh7619.c
index 4df4d4ffe39b..3860b0be56c7 100644
--- a/arch/sh/kernel/cpu/sh2/setup-sh7619.c
+++ b/arch/sh/kernel/cpu/sh2/setup-sh7619.c
@@ -61,51 +61,63 @@ static DECLARE_INTC_DESC(intc_desc, "sh7619", vectors, NULL,
61 NULL, prio_registers, NULL); 61 NULL, prio_registers, NULL);
62 62
63static struct plat_sci_port scif0_platform_data = { 63static struct plat_sci_port scif0_platform_data = {
64 .mapbase = 0xf8400000,
65 .flags = UPF_BOOT_AUTOCONF, 64 .flags = UPF_BOOT_AUTOCONF,
66 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 65 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
67 .scbrr_algo_id = SCBRR_ALGO_2,
68 .type = PORT_SCIF, 66 .type = PORT_SCIF,
69 .irqs = SCIx_IRQ_MUXED(88), 67};
68
69static struct resource scif0_resources[] = {
70 DEFINE_RES_MEM(0xf8400000, 0x100),
71 DEFINE_RES_IRQ(88),
70}; 72};
71 73
72static struct platform_device scif0_device = { 74static struct platform_device scif0_device = {
73 .name = "sh-sci", 75 .name = "sh-sci",
74 .id = 0, 76 .id = 0,
77 .resource = scif0_resources,
78 .num_resources = ARRAY_SIZE(scif0_resources),
75 .dev = { 79 .dev = {
76 .platform_data = &scif0_platform_data, 80 .platform_data = &scif0_platform_data,
77 }, 81 },
78}; 82};
79 83
80static struct plat_sci_port scif1_platform_data = { 84static struct plat_sci_port scif1_platform_data = {
81 .mapbase = 0xf8410000,
82 .flags = UPF_BOOT_AUTOCONF, 85 .flags = UPF_BOOT_AUTOCONF,
83 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 86 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
84 .scbrr_algo_id = SCBRR_ALGO_2,
85 .type = PORT_SCIF, 87 .type = PORT_SCIF,
86 .irqs = SCIx_IRQ_MUXED(92), 88};
89
90static struct resource scif1_resources[] = {
91 DEFINE_RES_MEM(0xf8410000, 0x100),
92 DEFINE_RES_IRQ(92),
87}; 93};
88 94
89static struct platform_device scif1_device = { 95static struct platform_device scif1_device = {
90 .name = "sh-sci", 96 .name = "sh-sci",
91 .id = 1, 97 .id = 1,
98 .resource = scif1_resources,
99 .num_resources = ARRAY_SIZE(scif1_resources),
92 .dev = { 100 .dev = {
93 .platform_data = &scif1_platform_data, 101 .platform_data = &scif1_platform_data,
94 }, 102 },
95}; 103};
96 104
97static struct plat_sci_port scif2_platform_data = { 105static struct plat_sci_port scif2_platform_data = {
98 .mapbase = 0xf8420000,
99 .flags = UPF_BOOT_AUTOCONF, 106 .flags = UPF_BOOT_AUTOCONF,
100 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 107 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
101 .scbrr_algo_id = SCBRR_ALGO_2,
102 .type = PORT_SCIF, 108 .type = PORT_SCIF,
103 .irqs = SCIx_IRQ_MUXED(96), 109};
110
111static struct resource scif2_resources[] = {
112 DEFINE_RES_MEM(0xf8420000, 0x100),
113 DEFINE_RES_IRQ(96),
104}; 114};
105 115
106static struct platform_device scif2_device = { 116static struct platform_device scif2_device = {
107 .name = "sh-sci", 117 .name = "sh-sci",
108 .id = 2, 118 .id = 2,
119 .resource = scif2_resources,
120 .num_resources = ARRAY_SIZE(scif2_resources),
109 .dev = { 121 .dev = {
110 .platform_data = &scif2_platform_data, 122 .platform_data = &scif2_platform_data,
111 }, 123 },
diff --git a/arch/sh/kernel/cpu/sh2a/setup-mxg.c b/arch/sh/kernel/cpu/sh2a/setup-mxg.c
index f7f1cf2af302..63e996f9a7ed 100644
--- a/arch/sh/kernel/cpu/sh2a/setup-mxg.c
+++ b/arch/sh/kernel/cpu/sh2a/setup-mxg.c
@@ -199,17 +199,21 @@ static struct platform_device mtu2_2_device = {
199}; 199};
200 200
201static struct plat_sci_port scif0_platform_data = { 201static struct plat_sci_port scif0_platform_data = {
202 .mapbase = 0xff804000,
203 .flags = UPF_BOOT_AUTOCONF, 202 .flags = UPF_BOOT_AUTOCONF,
204 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 203 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
205 .scbrr_algo_id = SCBRR_ALGO_2,
206 .type = PORT_SCIF, 204 .type = PORT_SCIF,
207 .irqs = SCIx_IRQ_MUXED(220), 205};
206
207static struct resource scif0_resources[] = {
208 DEFINE_RES_MEM(0xff804000, 0x100),
209 DEFINE_RES_IRQ(220),
208}; 210};
209 211
210static struct platform_device scif0_device = { 212static struct platform_device scif0_device = {
211 .name = "sh-sci", 213 .name = "sh-sci",
212 .id = 0, 214 .id = 0,
215 .resource = scif0_resources,
216 .num_resources = ARRAY_SIZE(scif0_resources),
213 .dev = { 217 .dev = {
214 .platform_data = &scif0_platform_data, 218 .platform_data = &scif0_platform_data,
215 }, 219 },
diff --git a/arch/sh/kernel/cpu/sh2a/setup-sh7201.c b/arch/sh/kernel/cpu/sh2a/setup-sh7201.c
index 7b84785b8962..2c6874461536 100644
--- a/arch/sh/kernel/cpu/sh2a/setup-sh7201.c
+++ b/arch/sh/kernel/cpu/sh2a/setup-sh7201.c
@@ -178,136 +178,168 @@ static DECLARE_INTC_DESC(intc_desc, "sh7201", vectors, groups,
178 mask_registers, prio_registers, NULL); 178 mask_registers, prio_registers, NULL);
179 179
180static struct plat_sci_port scif0_platform_data = { 180static struct plat_sci_port scif0_platform_data = {
181 .mapbase = 0xfffe8000,
182 .flags = UPF_BOOT_AUTOCONF, 181 .flags = UPF_BOOT_AUTOCONF,
183 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 182 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
184 .scbrr_algo_id = SCBRR_ALGO_2,
185 .type = PORT_SCIF, 183 .type = PORT_SCIF,
186 .irqs = SCIx_IRQ_MUXED(180), 184};
185
186static struct resource scif0_resources[] = {
187 DEFINE_RES_MEM(0xfffe8000, 0x100),
188 DEFINE_RES_IRQ(180),
187}; 189};
188 190
189static struct platform_device scif0_device = { 191static struct platform_device scif0_device = {
190 .name = "sh-sci", 192 .name = "sh-sci",
191 .id = 0, 193 .id = 0,
194 .resource = scif0_resources,
195 .num_resources = ARRAY_SIZE(scif0_resources),
192 .dev = { 196 .dev = {
193 .platform_data = &scif0_platform_data, 197 .platform_data = &scif0_platform_data,
194 }, 198 },
195}; 199};
196 200
197static struct plat_sci_port scif1_platform_data = { 201static struct plat_sci_port scif1_platform_data = {
198 .mapbase = 0xfffe8800,
199 .flags = UPF_BOOT_AUTOCONF, 202 .flags = UPF_BOOT_AUTOCONF,
200 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 203 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
201 .scbrr_algo_id = SCBRR_ALGO_2,
202 .type = PORT_SCIF, 204 .type = PORT_SCIF,
203 .irqs = SCIx_IRQ_MUXED(184), 205};
206
207static struct resource scif1_resources[] = {
208 DEFINE_RES_MEM(0xfffe8800, 0x100),
209 DEFINE_RES_IRQ(184),
204}; 210};
205 211
206static struct platform_device scif1_device = { 212static struct platform_device scif1_device = {
207 .name = "sh-sci", 213 .name = "sh-sci",
208 .id = 1, 214 .id = 1,
215 .resource = scif1_resources,
216 .num_resources = ARRAY_SIZE(scif1_resources),
209 .dev = { 217 .dev = {
210 .platform_data = &scif1_platform_data, 218 .platform_data = &scif1_platform_data,
211 }, 219 },
212}; 220};
213 221
214static struct plat_sci_port scif2_platform_data = { 222static struct plat_sci_port scif2_platform_data = {
215 .mapbase = 0xfffe9000,
216 .flags = UPF_BOOT_AUTOCONF, 223 .flags = UPF_BOOT_AUTOCONF,
217 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 224 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
218 .scbrr_algo_id = SCBRR_ALGO_2,
219 .type = PORT_SCIF, 225 .type = PORT_SCIF,
220 .irqs = SCIx_IRQ_MUXED(188), 226};
227
228static struct resource scif2_resources[] = {
229 DEFINE_RES_MEM(0xfffe9000, 0x100),
230 DEFINE_RES_IRQ(188),
221}; 231};
222 232
223static struct platform_device scif2_device = { 233static struct platform_device scif2_device = {
224 .name = "sh-sci", 234 .name = "sh-sci",
225 .id = 2, 235 .id = 2,
236 .resource = scif2_resources,
237 .num_resources = ARRAY_SIZE(scif2_resources),
226 .dev = { 238 .dev = {
227 .platform_data = &scif2_platform_data, 239 .platform_data = &scif2_platform_data,
228 }, 240 },
229}; 241};
230 242
231static struct plat_sci_port scif3_platform_data = { 243static struct plat_sci_port scif3_platform_data = {
232 .mapbase = 0xfffe9800,
233 .flags = UPF_BOOT_AUTOCONF, 244 .flags = UPF_BOOT_AUTOCONF,
234 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 245 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
235 .scbrr_algo_id = SCBRR_ALGO_2,
236 .type = PORT_SCIF, 246 .type = PORT_SCIF,
237 .irqs = SCIx_IRQ_MUXED(192), 247};
248
249static struct resource scif3_resources[] = {
250 DEFINE_RES_MEM(0xfffe9800, 0x100),
251 DEFINE_RES_IRQ(192),
238}; 252};
239 253
240static struct platform_device scif3_device = { 254static struct platform_device scif3_device = {
241 .name = "sh-sci", 255 .name = "sh-sci",
242 .id = 3, 256 .id = 3,
257 .resource = scif3_resources,
258 .num_resources = ARRAY_SIZE(scif3_resources),
243 .dev = { 259 .dev = {
244 .platform_data = &scif3_platform_data, 260 .platform_data = &scif3_platform_data,
245 }, 261 },
246}; 262};
247 263
248static struct plat_sci_port scif4_platform_data = { 264static struct plat_sci_port scif4_platform_data = {
249 .mapbase = 0xfffea000,
250 .flags = UPF_BOOT_AUTOCONF, 265 .flags = UPF_BOOT_AUTOCONF,
251 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 266 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
252 .scbrr_algo_id = SCBRR_ALGO_2,
253 .type = PORT_SCIF, 267 .type = PORT_SCIF,
254 .irqs = SCIx_IRQ_MUXED(196), 268};
269
270static struct resource scif4_resources[] = {
271 DEFINE_RES_MEM(0xfffea000, 0x100),
272 DEFINE_RES_IRQ(196),
255}; 273};
256 274
257static struct platform_device scif4_device = { 275static struct platform_device scif4_device = {
258 .name = "sh-sci", 276 .name = "sh-sci",
259 .id = 4, 277 .id = 4,
278 .resource = scif4_resources,
279 .num_resources = ARRAY_SIZE(scif4_resources),
260 .dev = { 280 .dev = {
261 .platform_data = &scif4_platform_data, 281 .platform_data = &scif4_platform_data,
262 }, 282 },
263}; 283};
264 284
265static struct plat_sci_port scif5_platform_data = { 285static struct plat_sci_port scif5_platform_data = {
266 .mapbase = 0xfffea800,
267 .flags = UPF_BOOT_AUTOCONF, 286 .flags = UPF_BOOT_AUTOCONF,
268 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 287 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
269 .scbrr_algo_id = SCBRR_ALGO_2,
270 .type = PORT_SCIF, 288 .type = PORT_SCIF,
271 .irqs = SCIx_IRQ_MUXED(200), 289};
290
291static struct resource scif5_resources[] = {
292 DEFINE_RES_MEM(0xfffea800, 0x100),
293 DEFINE_RES_IRQ(200),
272}; 294};
273 295
274static struct platform_device scif5_device = { 296static struct platform_device scif5_device = {
275 .name = "sh-sci", 297 .name = "sh-sci",
276 .id = 5, 298 .id = 5,
299 .resource = scif5_resources,
300 .num_resources = ARRAY_SIZE(scif5_resources),
277 .dev = { 301 .dev = {
278 .platform_data = &scif5_platform_data, 302 .platform_data = &scif5_platform_data,
279 }, 303 },
280}; 304};
281 305
282static struct plat_sci_port scif6_platform_data = { 306static struct plat_sci_port scif6_platform_data = {
283 .mapbase = 0xfffeb000,
284 .flags = UPF_BOOT_AUTOCONF, 307 .flags = UPF_BOOT_AUTOCONF,
285 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 308 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
286 .scbrr_algo_id = SCBRR_ALGO_2,
287 .type = PORT_SCIF, 309 .type = PORT_SCIF,
288 .irqs = SCIx_IRQ_MUXED(204), 310};
311
312static struct resource scif6_resources[] = {
313 DEFINE_RES_MEM(0xfffeb000, 0x100),
314 DEFINE_RES_IRQ(204),
289}; 315};
290 316
291static struct platform_device scif6_device = { 317static struct platform_device scif6_device = {
292 .name = "sh-sci", 318 .name = "sh-sci",
293 .id = 6, 319 .id = 6,
320 .resource = scif6_resources,
321 .num_resources = ARRAY_SIZE(scif6_resources),
294 .dev = { 322 .dev = {
295 .platform_data = &scif6_platform_data, 323 .platform_data = &scif6_platform_data,
296 }, 324 },
297}; 325};
298 326
299static struct plat_sci_port scif7_platform_data = { 327static struct plat_sci_port scif7_platform_data = {
300 .mapbase = 0xfffeb800,
301 .flags = UPF_BOOT_AUTOCONF, 328 .flags = UPF_BOOT_AUTOCONF,
302 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 329 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
303 .scbrr_algo_id = SCBRR_ALGO_2,
304 .type = PORT_SCIF, 330 .type = PORT_SCIF,
305 .irqs = SCIx_IRQ_MUXED(208), 331};
332
333static struct resource scif7_resources[] = {
334 DEFINE_RES_MEM(0xfffeb800, 0x100),
335 DEFINE_RES_IRQ(208),
306}; 336};
307 337
308static struct platform_device scif7_device = { 338static struct platform_device scif7_device = {
309 .name = "sh-sci", 339 .name = "sh-sci",
310 .id = 7, 340 .id = 7,
341 .resource = scif7_resources,
342 .num_resources = ARRAY_SIZE(scif7_resources),
311 .dev = { 343 .dev = {
312 .platform_data = &scif7_platform_data, 344 .platform_data = &scif7_platform_data,
313 }, 345 },
diff --git a/arch/sh/kernel/cpu/sh2a/setup-sh7203.c b/arch/sh/kernel/cpu/sh2a/setup-sh7203.c
index bfc33f6a28c3..d55a0f30ada3 100644
--- a/arch/sh/kernel/cpu/sh2a/setup-sh7203.c
+++ b/arch/sh/kernel/cpu/sh2a/setup-sh7203.c
@@ -174,76 +174,92 @@ static DECLARE_INTC_DESC(intc_desc, "sh7203", vectors, groups,
174 mask_registers, prio_registers, NULL); 174 mask_registers, prio_registers, NULL);
175 175
176static struct plat_sci_port scif0_platform_data = { 176static struct plat_sci_port scif0_platform_data = {
177 .mapbase = 0xfffe8000,
178 .flags = UPF_BOOT_AUTOCONF, 177 .flags = UPF_BOOT_AUTOCONF,
179 .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | 178 .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
180 SCSCR_REIE, 179 SCSCR_REIE,
181 .scbrr_algo_id = SCBRR_ALGO_2,
182 .type = PORT_SCIF, 180 .type = PORT_SCIF,
183 .irqs = SCIx_IRQ_MUXED(192),
184 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, 181 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
185}; 182};
186 183
184static struct resource scif0_resources[] = {
185 DEFINE_RES_MEM(0xfffe8000, 0x100),
186 DEFINE_RES_IRQ(192),
187};
188
187static struct platform_device scif0_device = { 189static struct platform_device scif0_device = {
188 .name = "sh-sci", 190 .name = "sh-sci",
189 .id = 0, 191 .id = 0,
192 .resource = scif0_resources,
193 .num_resources = ARRAY_SIZE(scif0_resources),
190 .dev = { 194 .dev = {
191 .platform_data = &scif0_platform_data, 195 .platform_data = &scif0_platform_data,
192 }, 196 },
193}; 197};
194 198
195static struct plat_sci_port scif1_platform_data = { 199static struct plat_sci_port scif1_platform_data = {
196 .mapbase = 0xfffe8800,
197 .flags = UPF_BOOT_AUTOCONF, 200 .flags = UPF_BOOT_AUTOCONF,
198 .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | 201 .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
199 SCSCR_REIE, 202 SCSCR_REIE,
200 .scbrr_algo_id = SCBRR_ALGO_2,
201 .type = PORT_SCIF, 203 .type = PORT_SCIF,
202 .irqs = SCIx_IRQ_MUXED(196),
203 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, 204 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
204}; 205};
205 206
207static struct resource scif1_resources[] = {
208 DEFINE_RES_MEM(0xfffe8800, 0x100),
209 DEFINE_RES_IRQ(196),
210};
211
206static struct platform_device scif1_device = { 212static struct platform_device scif1_device = {
207 .name = "sh-sci", 213 .name = "sh-sci",
208 .id = 1, 214 .id = 1,
215 .resource = scif1_resources,
216 .num_resources = ARRAY_SIZE(scif1_resources),
209 .dev = { 217 .dev = {
210 .platform_data = &scif1_platform_data, 218 .platform_data = &scif1_platform_data,
211 }, 219 },
212}; 220};
213 221
214static struct plat_sci_port scif2_platform_data = { 222static struct plat_sci_port scif2_platform_data = {
215 .mapbase = 0xfffe9000,
216 .flags = UPF_BOOT_AUTOCONF, 223 .flags = UPF_BOOT_AUTOCONF,
217 .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | 224 .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
218 SCSCR_REIE, 225 SCSCR_REIE,
219 .scbrr_algo_id = SCBRR_ALGO_2,
220 .type = PORT_SCIF, 226 .type = PORT_SCIF,
221 .irqs = SCIx_IRQ_MUXED(200),
222 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, 227 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
223}; 228};
224 229
230static struct resource scif2_resources[] = {
231 DEFINE_RES_MEM(0xfffe9000, 0x100),
232 DEFINE_RES_IRQ(200),
233};
234
225static struct platform_device scif2_device = { 235static struct platform_device scif2_device = {
226 .name = "sh-sci", 236 .name = "sh-sci",
227 .id = 2, 237 .id = 2,
238 .resource = scif2_resources,
239 .num_resources = ARRAY_SIZE(scif2_resources),
228 .dev = { 240 .dev = {
229 .platform_data = &scif2_platform_data, 241 .platform_data = &scif2_platform_data,
230 }, 242 },
231}; 243};
232 244
233static struct plat_sci_port scif3_platform_data = { 245static struct plat_sci_port scif3_platform_data = {
234 .mapbase = 0xfffe9800,
235 .flags = UPF_BOOT_AUTOCONF, 246 .flags = UPF_BOOT_AUTOCONF,
236 .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | 247 .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
237 SCSCR_REIE, 248 SCSCR_REIE,
238 .scbrr_algo_id = SCBRR_ALGO_2,
239 .type = PORT_SCIF, 249 .type = PORT_SCIF,
240 .irqs = SCIx_IRQ_MUXED(204),
241 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, 250 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
242}; 251};
243 252
253static struct resource scif3_resources[] = {
254 DEFINE_RES_MEM(0xfffe9800, 0x100),
255 DEFINE_RES_IRQ(204),
256};
257
244static struct platform_device scif3_device = { 258static struct platform_device scif3_device = {
245 .name = "sh-sci", 259 .name = "sh-sci",
246 .id = 3, 260 .id = 3,
261 .resource = scif3_resources,
262 .num_resources = ARRAY_SIZE(scif3_resources),
247 .dev = { 263 .dev = {
248 .platform_data = &scif3_platform_data, 264 .platform_data = &scif3_platform_data,
249 }, 265 },
diff --git a/arch/sh/kernel/cpu/sh2a/setup-sh7206.c b/arch/sh/kernel/cpu/sh2a/setup-sh7206.c
index a5010741de85..241e745e3ced 100644
--- a/arch/sh/kernel/cpu/sh2a/setup-sh7206.c
+++ b/arch/sh/kernel/cpu/sh2a/setup-sh7206.c
@@ -134,68 +134,84 @@ static DECLARE_INTC_DESC(intc_desc, "sh7206", vectors, groups,
134 mask_registers, prio_registers, NULL); 134 mask_registers, prio_registers, NULL);
135 135
136static struct plat_sci_port scif0_platform_data = { 136static struct plat_sci_port scif0_platform_data = {
137 .mapbase = 0xfffe8000,
138 .flags = UPF_BOOT_AUTOCONF, 137 .flags = UPF_BOOT_AUTOCONF,
139 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 138 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
140 .scbrr_algo_id = SCBRR_ALGO_2,
141 .type = PORT_SCIF, 139 .type = PORT_SCIF,
142 .irqs = SCIx_IRQ_MUXED(240), 140};
141
142static struct resource scif0_resources[] = {
143 DEFINE_RES_MEM(0xfffe8000, 0x100),
144 DEFINE_RES_IRQ(240),
143}; 145};
144 146
145static struct platform_device scif0_device = { 147static struct platform_device scif0_device = {
146 .name = "sh-sci", 148 .name = "sh-sci",
147 .id = 0, 149 .id = 0,
150 .resource = scif0_resources,
151 .num_resources = ARRAY_SIZE(scif0_resources),
148 .dev = { 152 .dev = {
149 .platform_data = &scif0_platform_data, 153 .platform_data = &scif0_platform_data,
150 }, 154 },
151}; 155};
152 156
153static struct plat_sci_port scif1_platform_data = { 157static struct plat_sci_port scif1_platform_data = {
154 .mapbase = 0xfffe8800,
155 .flags = UPF_BOOT_AUTOCONF, 158 .flags = UPF_BOOT_AUTOCONF,
156 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 159 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
157 .scbrr_algo_id = SCBRR_ALGO_2,
158 .type = PORT_SCIF, 160 .type = PORT_SCIF,
159 .irqs = SCIx_IRQ_MUXED(244), 161};
162
163static struct resource scif1_resources[] = {
164 DEFINE_RES_MEM(0xfffe8800, 0x100),
165 DEFINE_RES_IRQ(244),
160}; 166};
161 167
162static struct platform_device scif1_device = { 168static struct platform_device scif1_device = {
163 .name = "sh-sci", 169 .name = "sh-sci",
164 .id = 1, 170 .id = 1,
171 .resource = scif1_resources,
172 .num_resources = ARRAY_SIZE(scif1_resources),
165 .dev = { 173 .dev = {
166 .platform_data = &scif1_platform_data, 174 .platform_data = &scif1_platform_data,
167 }, 175 },
168}; 176};
169 177
170static struct plat_sci_port scif2_platform_data = { 178static struct plat_sci_port scif2_platform_data = {
171 .mapbase = 0xfffe9000,
172 .flags = UPF_BOOT_AUTOCONF, 179 .flags = UPF_BOOT_AUTOCONF,
173 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 180 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
174 .scbrr_algo_id = SCBRR_ALGO_2,
175 .type = PORT_SCIF, 181 .type = PORT_SCIF,
176 .irqs = SCIx_IRQ_MUXED(248), 182};
183
184static struct resource scif2_resources[] = {
185 DEFINE_RES_MEM(0xfffe9000, 0x100),
186 DEFINE_RES_IRQ(248),
177}; 187};
178 188
179static struct platform_device scif2_device = { 189static struct platform_device scif2_device = {
180 .name = "sh-sci", 190 .name = "sh-sci",
181 .id = 2, 191 .id = 2,
192 .resource = scif2_resources,
193 .num_resources = ARRAY_SIZE(scif2_resources),
182 .dev = { 194 .dev = {
183 .platform_data = &scif2_platform_data, 195 .platform_data = &scif2_platform_data,
184 }, 196 },
185}; 197};
186 198
187static struct plat_sci_port scif3_platform_data = { 199static struct plat_sci_port scif3_platform_data = {
188 .mapbase = 0xfffe9800,
189 .flags = UPF_BOOT_AUTOCONF, 200 .flags = UPF_BOOT_AUTOCONF,
190 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 201 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
191 .scbrr_algo_id = SCBRR_ALGO_2,
192 .type = PORT_SCIF, 202 .type = PORT_SCIF,
193 .irqs = SCIx_IRQ_MUXED(252), 203};
204
205static struct resource scif3_resources[] = {
206 DEFINE_RES_MEM(0xfffe9800, 0x100),
207 DEFINE_RES_IRQ(252),
194}; 208};
195 209
196static struct platform_device scif3_device = { 210static struct platform_device scif3_device = {
197 .name = "sh-sci", 211 .name = "sh-sci",
198 .id = 3, 212 .id = 3,
213 .resource = scif3_resources,
214 .num_resources = ARRAY_SIZE(scif3_resources),
199 .dev = { 215 .dev = {
200 .platform_data = &scif3_platform_data, 216 .platform_data = &scif3_platform_data,
201 }, 217 },
diff --git a/arch/sh/kernel/cpu/sh2a/setup-sh7264.c b/arch/sh/kernel/cpu/sh2a/setup-sh7264.c
index ce5c1b5aebfa..ad5b0f429882 100644
--- a/arch/sh/kernel/cpu/sh2a/setup-sh7264.c
+++ b/arch/sh/kernel/cpu/sh2a/setup-sh7264.c
@@ -226,152 +226,208 @@ static DECLARE_INTC_DESC(intc_desc, "sh7264", vectors, groups,
226 mask_registers, prio_registers, NULL); 226 mask_registers, prio_registers, NULL);
227 227
228static struct plat_sci_port scif0_platform_data = { 228static struct plat_sci_port scif0_platform_data = {
229 .mapbase = 0xfffe8000,
230 .flags = UPF_BOOT_AUTOCONF, 229 .flags = UPF_BOOT_AUTOCONF,
231 .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | 230 .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
232 SCSCR_REIE | SCSCR_TOIE, 231 SCSCR_REIE | SCSCR_TOIE,
233 .scbrr_algo_id = SCBRR_ALGO_2,
234 .type = PORT_SCIF, 232 .type = PORT_SCIF,
235 .irqs = { 233, 234, 235, 232 },
236 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, 233 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
237}; 234};
238 235
236static struct resource scif0_resources[] = {
237 DEFINE_RES_MEM(0xfffe8000, 0x100),
238 DEFINE_RES_IRQ(233),
239 DEFINE_RES_IRQ(234),
240 DEFINE_RES_IRQ(235),
241 DEFINE_RES_IRQ(232),
242};
243
239static struct platform_device scif0_device = { 244static struct platform_device scif0_device = {
240 .name = "sh-sci", 245 .name = "sh-sci",
241 .id = 0, 246 .id = 0,
247 .resource = scif0_resources,
248 .num_resources = ARRAY_SIZE(scif0_resources),
242 .dev = { 249 .dev = {
243 .platform_data = &scif0_platform_data, 250 .platform_data = &scif0_platform_data,
244 }, 251 },
245}; 252};
246 253
247static struct plat_sci_port scif1_platform_data = { 254static struct plat_sci_port scif1_platform_data = {
248 .mapbase = 0xfffe8800,
249 .flags = UPF_BOOT_AUTOCONF, 255 .flags = UPF_BOOT_AUTOCONF,
250 .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | 256 .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
251 SCSCR_REIE | SCSCR_TOIE, 257 SCSCR_REIE | SCSCR_TOIE,
252 .scbrr_algo_id = SCBRR_ALGO_2,
253 .type = PORT_SCIF, 258 .type = PORT_SCIF,
254 .irqs = { 237, 238, 239, 236 },
255 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, 259 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
256}; 260};
257 261
262static struct resource scif1_resources[] = {
263 DEFINE_RES_MEM(0xfffe8800, 0x100),
264 DEFINE_RES_IRQ(237),
265 DEFINE_RES_IRQ(238),
266 DEFINE_RES_IRQ(239),
267 DEFINE_RES_IRQ(236),
268};
269
258static struct platform_device scif1_device = { 270static struct platform_device scif1_device = {
259 .name = "sh-sci", 271 .name = "sh-sci",
260 .id = 1, 272 .id = 1,
273 .resource = scif1_resources,
274 .num_resources = ARRAY_SIZE(scif1_resources),
261 .dev = { 275 .dev = {
262 .platform_data = &scif1_platform_data, 276 .platform_data = &scif1_platform_data,
263 }, 277 },
264}; 278};
265 279
266static struct plat_sci_port scif2_platform_data = { 280static struct plat_sci_port scif2_platform_data = {
267 .mapbase = 0xfffe9000,
268 .flags = UPF_BOOT_AUTOCONF, 281 .flags = UPF_BOOT_AUTOCONF,
269 .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | 282 .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
270 SCSCR_REIE | SCSCR_TOIE, 283 SCSCR_REIE | SCSCR_TOIE,
271 .scbrr_algo_id = SCBRR_ALGO_2,
272 .type = PORT_SCIF, 284 .type = PORT_SCIF,
273 .irqs = { 241, 242, 243, 240 },
274 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, 285 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
275}; 286};
276 287
288static struct resource scif2_resources[] = {
289 DEFINE_RES_MEM(0xfffe9000, 0x100),
290 DEFINE_RES_IRQ(241),
291 DEFINE_RES_IRQ(242),
292 DEFINE_RES_IRQ(243),
293 DEFINE_RES_IRQ(240),
294};
295
277static struct platform_device scif2_device = { 296static struct platform_device scif2_device = {
278 .name = "sh-sci", 297 .name = "sh-sci",
279 .id = 2, 298 .id = 2,
299 .resource = scif2_resources,
300 .num_resources = ARRAY_SIZE(scif2_resources),
280 .dev = { 301 .dev = {
281 .platform_data = &scif2_platform_data, 302 .platform_data = &scif2_platform_data,
282 }, 303 },
283}; 304};
284 305
285static struct plat_sci_port scif3_platform_data = { 306static struct plat_sci_port scif3_platform_data = {
286 .mapbase = 0xfffe9800,
287 .flags = UPF_BOOT_AUTOCONF, 307 .flags = UPF_BOOT_AUTOCONF,
288 .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | 308 .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
289 SCSCR_REIE | SCSCR_TOIE, 309 SCSCR_REIE | SCSCR_TOIE,
290 .scbrr_algo_id = SCBRR_ALGO_2,
291 .type = PORT_SCIF, 310 .type = PORT_SCIF,
292 .irqs = { 245, 246, 247, 244 },
293 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, 311 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
294}; 312};
295 313
314static struct resource scif3_resources[] = {
315 DEFINE_RES_MEM(0xfffe9800, 0x100),
316 DEFINE_RES_IRQ(245),
317 DEFINE_RES_IRQ(246),
318 DEFINE_RES_IRQ(247),
319 DEFINE_RES_IRQ(244),
320};
321
296static struct platform_device scif3_device = { 322static struct platform_device scif3_device = {
297 .name = "sh-sci", 323 .name = "sh-sci",
298 .id = 3, 324 .id = 3,
325 .resource = scif3_resources,
326 .num_resources = ARRAY_SIZE(scif3_resources),
299 .dev = { 327 .dev = {
300 .platform_data = &scif3_platform_data, 328 .platform_data = &scif3_platform_data,
301 }, 329 },
302}; 330};
303 331
304static struct plat_sci_port scif4_platform_data = { 332static struct plat_sci_port scif4_platform_data = {
305 .mapbase = 0xfffea000,
306 .flags = UPF_BOOT_AUTOCONF, 333 .flags = UPF_BOOT_AUTOCONF,
307 .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | 334 .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
308 SCSCR_REIE | SCSCR_TOIE, 335 SCSCR_REIE | SCSCR_TOIE,
309 .scbrr_algo_id = SCBRR_ALGO_2,
310 .type = PORT_SCIF, 336 .type = PORT_SCIF,
311 .irqs = { 249, 250, 251, 248 },
312 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, 337 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
313}; 338};
314 339
340static struct resource scif4_resources[] = {
341 DEFINE_RES_MEM(0xfffea000, 0x100),
342 DEFINE_RES_IRQ(249),
343 DEFINE_RES_IRQ(250),
344 DEFINE_RES_IRQ(251),
345 DEFINE_RES_IRQ(248),
346};
347
315static struct platform_device scif4_device = { 348static struct platform_device scif4_device = {
316 .name = "sh-sci", 349 .name = "sh-sci",
317 .id = 4, 350 .id = 4,
351 .resource = scif4_resources,
352 .num_resources = ARRAY_SIZE(scif4_resources),
318 .dev = { 353 .dev = {
319 .platform_data = &scif4_platform_data, 354 .platform_data = &scif4_platform_data,
320 }, 355 },
321}; 356};
322 357
323static struct plat_sci_port scif5_platform_data = { 358static struct plat_sci_port scif5_platform_data = {
324 .mapbase = 0xfffea800,
325 .flags = UPF_BOOT_AUTOCONF, 359 .flags = UPF_BOOT_AUTOCONF,
326 .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | 360 .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
327 SCSCR_REIE | SCSCR_TOIE, 361 SCSCR_REIE | SCSCR_TOIE,
328 .scbrr_algo_id = SCBRR_ALGO_2,
329 .type = PORT_SCIF, 362 .type = PORT_SCIF,
330 .irqs = { 253, 254, 255, 252 },
331 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, 363 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
332}; 364};
333 365
366static struct resource scif5_resources[] = {
367 DEFINE_RES_MEM(0xfffea800, 0x100),
368 DEFINE_RES_IRQ(253),
369 DEFINE_RES_IRQ(254),
370 DEFINE_RES_IRQ(255),
371 DEFINE_RES_IRQ(252),
372};
373
334static struct platform_device scif5_device = { 374static struct platform_device scif5_device = {
335 .name = "sh-sci", 375 .name = "sh-sci",
336 .id = 5, 376 .id = 5,
377 .resource = scif5_resources,
378 .num_resources = ARRAY_SIZE(scif5_resources),
337 .dev = { 379 .dev = {
338 .platform_data = &scif5_platform_data, 380 .platform_data = &scif5_platform_data,
339 }, 381 },
340}; 382};
341 383
342static struct plat_sci_port scif6_platform_data = { 384static struct plat_sci_port scif6_platform_data = {
343 .mapbase = 0xfffeb000,
344 .flags = UPF_BOOT_AUTOCONF, 385 .flags = UPF_BOOT_AUTOCONF,
345 .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | 386 .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
346 SCSCR_REIE | SCSCR_TOIE, 387 SCSCR_REIE | SCSCR_TOIE,
347 .scbrr_algo_id = SCBRR_ALGO_2,
348 .type = PORT_SCIF, 388 .type = PORT_SCIF,
349 .irqs = { 257, 258, 259, 256 },
350 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, 389 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
351}; 390};
352 391
392static struct resource scif6_resources[] = {
393 DEFINE_RES_MEM(0xfffeb000, 0x100),
394 DEFINE_RES_IRQ(257),
395 DEFINE_RES_IRQ(258),
396 DEFINE_RES_IRQ(259),
397 DEFINE_RES_IRQ(256),
398};
399
353static struct platform_device scif6_device = { 400static struct platform_device scif6_device = {
354 .name = "sh-sci", 401 .name = "sh-sci",
355 .id = 6, 402 .id = 6,
403 .resource = scif6_resources,
404 .num_resources = ARRAY_SIZE(scif6_resources),
356 .dev = { 405 .dev = {
357 .platform_data = &scif6_platform_data, 406 .platform_data = &scif6_platform_data,
358 }, 407 },
359}; 408};
360 409
361static struct plat_sci_port scif7_platform_data = { 410static struct plat_sci_port scif7_platform_data = {
362 .mapbase = 0xfffeb800,
363 .flags = UPF_BOOT_AUTOCONF, 411 .flags = UPF_BOOT_AUTOCONF,
364 .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | 412 .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
365 SCSCR_REIE | SCSCR_TOIE, 413 SCSCR_REIE | SCSCR_TOIE,
366 .scbrr_algo_id = SCBRR_ALGO_2,
367 .type = PORT_SCIF, 414 .type = PORT_SCIF,
368 .irqs = { 261, 262, 263, 260 },
369 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, 415 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
370}; 416};
371 417
418static struct resource scif7_resources[] = {
419 DEFINE_RES_MEM(0xfffeb800, 0x100),
420 DEFINE_RES_IRQ(261),
421 DEFINE_RES_IRQ(262),
422 DEFINE_RES_IRQ(263),
423 DEFINE_RES_IRQ(260),
424};
425
372static struct platform_device scif7_device = { 426static struct platform_device scif7_device = {
373 .name = "sh-sci", 427 .name = "sh-sci",
374 .id = 7, 428 .id = 7,
429 .resource = scif7_resources,
430 .num_resources = ARRAY_SIZE(scif7_resources),
375 .dev = { 431 .dev = {
376 .platform_data = &scif7_platform_data, 432 .platform_data = &scif7_platform_data,
377 }, 433 },
diff --git a/arch/sh/kernel/cpu/sh2a/setup-sh7269.c b/arch/sh/kernel/cpu/sh2a/setup-sh7269.c
index e82ae9d8d3bc..3995119f65dc 100644
--- a/arch/sh/kernel/cpu/sh2a/setup-sh7269.c
+++ b/arch/sh/kernel/cpu/sh2a/setup-sh7269.c
@@ -248,152 +248,208 @@ static DECLARE_INTC_DESC(intc_desc, "sh7269", vectors, groups,
248 mask_registers, prio_registers, NULL); 248 mask_registers, prio_registers, NULL);
249 249
250static struct plat_sci_port scif0_platform_data = { 250static struct plat_sci_port scif0_platform_data = {
251 .mapbase = 0xe8007000,
252 .flags = UPF_BOOT_AUTOCONF, 251 .flags = UPF_BOOT_AUTOCONF,
253 .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | 252 .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
254 SCSCR_REIE | SCSCR_TOIE, 253 SCSCR_REIE | SCSCR_TOIE,
255 .scbrr_algo_id = SCBRR_ALGO_2,
256 .type = PORT_SCIF, 254 .type = PORT_SCIF,
257 .irqs = { 259, 260, 261, 258 },
258 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, 255 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
259}; 256};
260 257
258static struct resource scif0_resources[] = {
259 DEFINE_RES_MEM(0xe8007000, 0x100),
260 DEFINE_RES_IRQ(259),
261 DEFINE_RES_IRQ(260),
262 DEFINE_RES_IRQ(261),
263 DEFINE_RES_IRQ(258),
264};
265
261static struct platform_device scif0_device = { 266static struct platform_device scif0_device = {
262 .name = "sh-sci", 267 .name = "sh-sci",
263 .id = 0, 268 .id = 0,
269 .resource = scif0_resources,
270 .num_resources = ARRAY_SIZE(scif0_resources),
264 .dev = { 271 .dev = {
265 .platform_data = &scif0_platform_data, 272 .platform_data = &scif0_platform_data,
266 }, 273 },
267}; 274};
268 275
269static struct plat_sci_port scif1_platform_data = { 276static struct plat_sci_port scif1_platform_data = {
270 .mapbase = 0xe8007800,
271 .flags = UPF_BOOT_AUTOCONF, 277 .flags = UPF_BOOT_AUTOCONF,
272 .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | 278 .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
273 SCSCR_REIE | SCSCR_TOIE, 279 SCSCR_REIE | SCSCR_TOIE,
274 .scbrr_algo_id = SCBRR_ALGO_2,
275 .type = PORT_SCIF, 280 .type = PORT_SCIF,
276 .irqs = { 263, 264, 265, 262 },
277 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, 281 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
278}; 282};
279 283
284static struct resource scif1_resources[] = {
285 DEFINE_RES_MEM(0xe8007800, 0x100),
286 DEFINE_RES_IRQ(263),
287 DEFINE_RES_IRQ(264),
288 DEFINE_RES_IRQ(265),
289 DEFINE_RES_IRQ(262),
290};
291
280static struct platform_device scif1_device = { 292static struct platform_device scif1_device = {
281 .name = "sh-sci", 293 .name = "sh-sci",
282 .id = 1, 294 .id = 1,
295 .resource = scif1_resources,
296 .num_resources = ARRAY_SIZE(scif1_resources),
283 .dev = { 297 .dev = {
284 .platform_data = &scif1_platform_data, 298 .platform_data = &scif1_platform_data,
285 }, 299 },
286}; 300};
287 301
288static struct plat_sci_port scif2_platform_data = { 302static struct plat_sci_port scif2_platform_data = {
289 .mapbase = 0xe8008000,
290 .flags = UPF_BOOT_AUTOCONF, 303 .flags = UPF_BOOT_AUTOCONF,
291 .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | 304 .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
292 SCSCR_REIE | SCSCR_TOIE, 305 SCSCR_REIE | SCSCR_TOIE,
293 .scbrr_algo_id = SCBRR_ALGO_2,
294 .type = PORT_SCIF, 306 .type = PORT_SCIF,
295 .irqs = { 267, 268, 269, 266 },
296 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, 307 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
297}; 308};
298 309
310static struct resource scif2_resources[] = {
311 DEFINE_RES_MEM(0xe8008000, 0x100),
312 DEFINE_RES_IRQ(267),
313 DEFINE_RES_IRQ(268),
314 DEFINE_RES_IRQ(269),
315 DEFINE_RES_IRQ(266),
316};
317
299static struct platform_device scif2_device = { 318static struct platform_device scif2_device = {
300 .name = "sh-sci", 319 .name = "sh-sci",
301 .id = 2, 320 .id = 2,
321 .resource = scif2_resources,
322 .num_resources = ARRAY_SIZE(scif2_resources),
302 .dev = { 323 .dev = {
303 .platform_data = &scif2_platform_data, 324 .platform_data = &scif2_platform_data,
304 }, 325 },
305}; 326};
306 327
307static struct plat_sci_port scif3_platform_data = { 328static struct plat_sci_port scif3_platform_data = {
308 .mapbase = 0xe8008800,
309 .flags = UPF_BOOT_AUTOCONF, 329 .flags = UPF_BOOT_AUTOCONF,
310 .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | 330 .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
311 SCSCR_REIE | SCSCR_TOIE, 331 SCSCR_REIE | SCSCR_TOIE,
312 .scbrr_algo_id = SCBRR_ALGO_2,
313 .type = PORT_SCIF, 332 .type = PORT_SCIF,
314 .irqs = { 271, 272, 273, 270 },
315 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, 333 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
316}; 334};
317 335
336static struct resource scif3_resources[] = {
337 DEFINE_RES_MEM(0xe8008800, 0x100),
338 DEFINE_RES_IRQ(271),
339 DEFINE_RES_IRQ(272),
340 DEFINE_RES_IRQ(273),
341 DEFINE_RES_IRQ(270),
342};
343
318static struct platform_device scif3_device = { 344static struct platform_device scif3_device = {
319 .name = "sh-sci", 345 .name = "sh-sci",
320 .id = 3, 346 .id = 3,
347 .resource = scif3_resources,
348 .num_resources = ARRAY_SIZE(scif3_resources),
321 .dev = { 349 .dev = {
322 .platform_data = &scif3_platform_data, 350 .platform_data = &scif3_platform_data,
323 }, 351 },
324}; 352};
325 353
326static struct plat_sci_port scif4_platform_data = { 354static struct plat_sci_port scif4_platform_data = {
327 .mapbase = 0xe8009000,
328 .flags = UPF_BOOT_AUTOCONF, 355 .flags = UPF_BOOT_AUTOCONF,
329 .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | 356 .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
330 SCSCR_REIE | SCSCR_TOIE, 357 SCSCR_REIE | SCSCR_TOIE,
331 .scbrr_algo_id = SCBRR_ALGO_2,
332 .type = PORT_SCIF, 358 .type = PORT_SCIF,
333 .irqs = { 275, 276, 277, 274 },
334 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, 359 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
335}; 360};
336 361
362static struct resource scif4_resources[] = {
363 DEFINE_RES_MEM(0xe8009000, 0x100),
364 DEFINE_RES_IRQ(275),
365 DEFINE_RES_IRQ(276),
366 DEFINE_RES_IRQ(277),
367 DEFINE_RES_IRQ(274),
368};
369
337static struct platform_device scif4_device = { 370static struct platform_device scif4_device = {
338 .name = "sh-sci", 371 .name = "sh-sci",
339 .id = 4, 372 .id = 4,
373 .resource = scif4_resources,
374 .num_resources = ARRAY_SIZE(scif4_resources),
340 .dev = { 375 .dev = {
341 .platform_data = &scif4_platform_data, 376 .platform_data = &scif4_platform_data,
342 }, 377 },
343}; 378};
344 379
345static struct plat_sci_port scif5_platform_data = { 380static struct plat_sci_port scif5_platform_data = {
346 .mapbase = 0xe8009800,
347 .flags = UPF_BOOT_AUTOCONF, 381 .flags = UPF_BOOT_AUTOCONF,
348 .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | 382 .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
349 SCSCR_REIE | SCSCR_TOIE, 383 SCSCR_REIE | SCSCR_TOIE,
350 .scbrr_algo_id = SCBRR_ALGO_2,
351 .type = PORT_SCIF, 384 .type = PORT_SCIF,
352 .irqs = { 279, 280, 281, 278 },
353 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, 385 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
354}; 386};
355 387
388static struct resource scif5_resources[] = {
389 DEFINE_RES_MEM(0xe8009800, 0x100),
390 DEFINE_RES_IRQ(279),
391 DEFINE_RES_IRQ(280),
392 DEFINE_RES_IRQ(281),
393 DEFINE_RES_IRQ(278),
394};
395
356static struct platform_device scif5_device = { 396static struct platform_device scif5_device = {
357 .name = "sh-sci", 397 .name = "sh-sci",
358 .id = 5, 398 .id = 5,
399 .resource = scif5_resources,
400 .num_resources = ARRAY_SIZE(scif5_resources),
359 .dev = { 401 .dev = {
360 .platform_data = &scif5_platform_data, 402 .platform_data = &scif5_platform_data,
361 }, 403 },
362}; 404};
363 405
364static struct plat_sci_port scif6_platform_data = { 406static struct plat_sci_port scif6_platform_data = {
365 .mapbase = 0xe800a000,
366 .flags = UPF_BOOT_AUTOCONF, 407 .flags = UPF_BOOT_AUTOCONF,
367 .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | 408 .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
368 SCSCR_REIE | SCSCR_TOIE, 409 SCSCR_REIE | SCSCR_TOIE,
369 .scbrr_algo_id = SCBRR_ALGO_2,
370 .type = PORT_SCIF, 410 .type = PORT_SCIF,
371 .irqs = { 283, 284, 285, 282 },
372 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, 411 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
373}; 412};
374 413
414static struct resource scif6_resources[] = {
415 DEFINE_RES_MEM(0xe800a000, 0x100),
416 DEFINE_RES_IRQ(283),
417 DEFINE_RES_IRQ(284),
418 DEFINE_RES_IRQ(285),
419 DEFINE_RES_IRQ(282),
420};
421
375static struct platform_device scif6_device = { 422static struct platform_device scif6_device = {
376 .name = "sh-sci", 423 .name = "sh-sci",
377 .id = 6, 424 .id = 6,
425 .resource = scif6_resources,
426 .num_resources = ARRAY_SIZE(scif6_resources),
378 .dev = { 427 .dev = {
379 .platform_data = &scif6_platform_data, 428 .platform_data = &scif6_platform_data,
380 }, 429 },
381}; 430};
382 431
383static struct plat_sci_port scif7_platform_data = { 432static struct plat_sci_port scif7_platform_data = {
384 .mapbase = 0xe800a800,
385 .flags = UPF_BOOT_AUTOCONF, 433 .flags = UPF_BOOT_AUTOCONF,
386 .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | 434 .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
387 SCSCR_REIE | SCSCR_TOIE, 435 SCSCR_REIE | SCSCR_TOIE,
388 .scbrr_algo_id = SCBRR_ALGO_2,
389 .type = PORT_SCIF, 436 .type = PORT_SCIF,
390 .irqs = { 287, 288, 289, 286 },
391 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, 437 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
392}; 438};
393 439
440static struct resource scif7_resources[] = {
441 DEFINE_RES_MEM(0xe800a800, 0x100),
442 DEFINE_RES_IRQ(287),
443 DEFINE_RES_IRQ(288),
444 DEFINE_RES_IRQ(289),
445 DEFINE_RES_IRQ(286),
446};
447
394static struct platform_device scif7_device = { 448static struct platform_device scif7_device = {
395 .name = "sh-sci", 449 .name = "sh-sci",
396 .id = 7, 450 .id = 7,
451 .resource = scif7_resources,
452 .num_resources = ARRAY_SIZE(scif7_resources),
397 .dev = { 453 .dev = {
398 .platform_data = &scif7_platform_data, 454 .platform_data = &scif7_platform_data,
399 }, 455 },
diff --git a/arch/sh/kernel/cpu/sh3/setup-sh7705.c b/arch/sh/kernel/cpu/sh3/setup-sh7705.c
index 03e4c96f2b11..c76b2543b85f 100644
--- a/arch/sh/kernel/cpu/sh3/setup-sh7705.c
+++ b/arch/sh/kernel/cpu/sh3/setup-sh7705.c
@@ -70,39 +70,47 @@ static DECLARE_INTC_DESC(intc_desc, "sh7705", vectors, NULL,
70 NULL, prio_registers, NULL); 70 NULL, prio_registers, NULL);
71 71
72static struct plat_sci_port scif0_platform_data = { 72static struct plat_sci_port scif0_platform_data = {
73 .mapbase = 0xa4410000,
74 .flags = UPF_BOOT_AUTOCONF, 73 .flags = UPF_BOOT_AUTOCONF,
75 .scscr = SCSCR_TIE | SCSCR_RIE | SCSCR_TE | 74 .scscr = SCSCR_TIE | SCSCR_RIE | SCSCR_TE |
76 SCSCR_RE | SCSCR_CKE1 | SCSCR_CKE0, 75 SCSCR_RE | SCSCR_CKE1 | SCSCR_CKE0,
77 .scbrr_algo_id = SCBRR_ALGO_4,
78 .type = PORT_SCIF, 76 .type = PORT_SCIF,
79 .irqs = SCIx_IRQ_MUXED(evt2irq(0x900)),
80 .ops = &sh770x_sci_port_ops, 77 .ops = &sh770x_sci_port_ops,
81 .regtype = SCIx_SH7705_SCIF_REGTYPE, 78 .regtype = SCIx_SH7705_SCIF_REGTYPE,
82}; 79};
83 80
81static struct resource scif0_resources[] = {
82 DEFINE_RES_MEM(0xa4410000, 0x100),
83 DEFINE_RES_IRQ(evt2irq(0x900)),
84};
85
84static struct platform_device scif0_device = { 86static struct platform_device scif0_device = {
85 .name = "sh-sci", 87 .name = "sh-sci",
86 .id = 0, 88 .id = 0,
89 .resource = scif0_resources,
90 .num_resources = ARRAY_SIZE(scif0_resources),
87 .dev = { 91 .dev = {
88 .platform_data = &scif0_platform_data, 92 .platform_data = &scif0_platform_data,
89 }, 93 },
90}; 94};
91 95
92static struct plat_sci_port scif1_platform_data = { 96static struct plat_sci_port scif1_platform_data = {
93 .mapbase = 0xa4400000,
94 .flags = UPF_BOOT_AUTOCONF, 97 .flags = UPF_BOOT_AUTOCONF,
95 .scscr = SCSCR_TIE | SCSCR_RIE | SCSCR_TE | SCSCR_RE, 98 .scscr = SCSCR_TIE | SCSCR_RIE | SCSCR_TE | SCSCR_RE,
96 .scbrr_algo_id = SCBRR_ALGO_4,
97 .type = PORT_SCIF, 99 .type = PORT_SCIF,
98 .irqs = SCIx_IRQ_MUXED(evt2irq(0x880)),
99 .ops = &sh770x_sci_port_ops, 100 .ops = &sh770x_sci_port_ops,
100 .regtype = SCIx_SH7705_SCIF_REGTYPE, 101 .regtype = SCIx_SH7705_SCIF_REGTYPE,
101}; 102};
102 103
104static struct resource scif1_resources[] = {
105 DEFINE_RES_MEM(0xa4400000, 0x100),
106 DEFINE_RES_IRQ(evt2irq(0x880)),
107};
108
103static struct platform_device scif1_device = { 109static struct platform_device scif1_device = {
104 .name = "sh-sci", 110 .name = "sh-sci",
105 .id = 1, 111 .id = 1,
112 .resource = scif1_resources,
113 .num_resources = ARRAY_SIZE(scif1_resources),
106 .dev = { 114 .dev = {
107 .platform_data = &scif1_platform_data, 115 .platform_data = &scif1_platform_data,
108 }, 116 },
diff --git a/arch/sh/kernel/cpu/sh3/setup-sh770x.c b/arch/sh/kernel/cpu/sh3/setup-sh770x.c
index ba26cd9ce69b..ff1465c0519c 100644
--- a/arch/sh/kernel/cpu/sh3/setup-sh770x.c
+++ b/arch/sh/kernel/cpu/sh3/setup-sh770x.c
@@ -109,20 +109,24 @@ static struct platform_device rtc_device = {
109}; 109};
110 110
111static struct plat_sci_port scif0_platform_data = { 111static struct plat_sci_port scif0_platform_data = {
112 .mapbase = 0xfffffe80,
113 .port_reg = 0xa4000136, 112 .port_reg = 0xa4000136,
114 .flags = UPF_BOOT_AUTOCONF, 113 .flags = UPF_BOOT_AUTOCONF,
115 .scscr = SCSCR_TE | SCSCR_RE, 114 .scscr = SCSCR_TE | SCSCR_RE,
116 .scbrr_algo_id = SCBRR_ALGO_2,
117 .type = PORT_SCI, 115 .type = PORT_SCI,
118 .irqs = SCIx_IRQ_MUXED(evt2irq(0x4e0)),
119 .ops = &sh770x_sci_port_ops, 116 .ops = &sh770x_sci_port_ops,
120 .regshift = 1, 117 .regshift = 1,
121}; 118};
122 119
120static struct resource scif0_resources[] = {
121 DEFINE_RES_MEM(0xfffffe80, 0x100),
122 DEFINE_RES_IRQ(evt2irq(0x4e0)),
123};
124
123static struct platform_device scif0_device = { 125static struct platform_device scif0_device = {
124 .name = "sh-sci", 126 .name = "sh-sci",
125 .id = 0, 127 .id = 0,
128 .resource = scif0_resources,
129 .num_resources = ARRAY_SIZE(scif0_resources),
126 .dev = { 130 .dev = {
127 .platform_data = &scif0_platform_data, 131 .platform_data = &scif0_platform_data,
128 }, 132 },
@@ -131,19 +135,23 @@ static struct platform_device scif0_device = {
131 defined(CONFIG_CPU_SUBTYPE_SH7707) || \ 135 defined(CONFIG_CPU_SUBTYPE_SH7707) || \
132 defined(CONFIG_CPU_SUBTYPE_SH7709) 136 defined(CONFIG_CPU_SUBTYPE_SH7709)
133static struct plat_sci_port scif1_platform_data = { 137static struct plat_sci_port scif1_platform_data = {
134 .mapbase = 0xa4000150,
135 .flags = UPF_BOOT_AUTOCONF, 138 .flags = UPF_BOOT_AUTOCONF,
136 .scscr = SCSCR_TE | SCSCR_RE, 139 .scscr = SCSCR_TE | SCSCR_RE,
137 .scbrr_algo_id = SCBRR_ALGO_2,
138 .type = PORT_SCIF, 140 .type = PORT_SCIF,
139 .irqs = SCIx_IRQ_MUXED(evt2irq(0x900)),
140 .ops = &sh770x_sci_port_ops, 141 .ops = &sh770x_sci_port_ops,
141 .regtype = SCIx_SH3_SCIF_REGTYPE, 142 .regtype = SCIx_SH3_SCIF_REGTYPE,
142}; 143};
143 144
145static struct resource scif1_resources[] = {
146 DEFINE_RES_MEM(0xa4000150, 0x100),
147 DEFINE_RES_IRQ(evt2irq(0x900)),
148};
149
144static struct platform_device scif1_device = { 150static struct platform_device scif1_device = {
145 .name = "sh-sci", 151 .name = "sh-sci",
146 .id = 1, 152 .id = 1,
153 .resource = scif1_resources,
154 .num_resources = ARRAY_SIZE(scif1_resources),
147 .dev = { 155 .dev = {
148 .platform_data = &scif1_platform_data, 156 .platform_data = &scif1_platform_data,
149 }, 157 },
@@ -152,20 +160,24 @@ static struct platform_device scif1_device = {
152#if defined(CONFIG_CPU_SUBTYPE_SH7707) || \ 160#if defined(CONFIG_CPU_SUBTYPE_SH7707) || \
153 defined(CONFIG_CPU_SUBTYPE_SH7709) 161 defined(CONFIG_CPU_SUBTYPE_SH7709)
154static struct plat_sci_port scif2_platform_data = { 162static struct plat_sci_port scif2_platform_data = {
155 .mapbase = 0xa4000140,
156 .port_reg = SCIx_NOT_SUPPORTED, 163 .port_reg = SCIx_NOT_SUPPORTED,
157 .flags = UPF_BOOT_AUTOCONF, 164 .flags = UPF_BOOT_AUTOCONF,
158 .scscr = SCSCR_TE | SCSCR_RE, 165 .scscr = SCSCR_TE | SCSCR_RE,
159 .scbrr_algo_id = SCBRR_ALGO_2,
160 .type = PORT_IRDA, 166 .type = PORT_IRDA,
161 .irqs = SCIx_IRQ_MUXED(evt2irq(0x880)),
162 .ops = &sh770x_sci_port_ops, 167 .ops = &sh770x_sci_port_ops,
163 .regshift = 1, 168 .regshift = 1,
164}; 169};
165 170
171static struct resource scif2_resources[] = {
172 DEFINE_RES_MEM(0xa4000140, 0x100),
173 DEFINE_RES_IRQ(evt2irq(0x880)),
174};
175
166static struct platform_device scif2_device = { 176static struct platform_device scif2_device = {
167 .name = "sh-sci", 177 .name = "sh-sci",
168 .id = 2, 178 .id = 2,
179 .resource = scif2_resources,
180 .num_resources = ARRAY_SIZE(scif2_resources),
169 .dev = { 181 .dev = {
170 .platform_data = &scif2_platform_data, 182 .platform_data = &scif2_platform_data,
171 }, 183 },
diff --git a/arch/sh/kernel/cpu/sh3/setup-sh7710.c b/arch/sh/kernel/cpu/sh3/setup-sh7710.c
index 93c9c5e24a7a..e2ce9360ed5a 100644
--- a/arch/sh/kernel/cpu/sh3/setup-sh7710.c
+++ b/arch/sh/kernel/cpu/sh3/setup-sh7710.c
@@ -98,36 +98,44 @@ static struct platform_device rtc_device = {
98}; 98};
99 99
100static struct plat_sci_port scif0_platform_data = { 100static struct plat_sci_port scif0_platform_data = {
101 .mapbase = 0xa4400000,
102 .flags = UPF_BOOT_AUTOCONF, 101 .flags = UPF_BOOT_AUTOCONF,
103 .scscr = SCSCR_TE | SCSCR_RE | SCSCR_REIE | 102 .scscr = SCSCR_TE | SCSCR_RE | SCSCR_REIE |
104 SCSCR_CKE1 | SCSCR_CKE0, 103 SCSCR_CKE1 | SCSCR_CKE0,
105 .scbrr_algo_id = SCBRR_ALGO_2,
106 .type = PORT_SCIF, 104 .type = PORT_SCIF,
107 .irqs = SCIx_IRQ_MUXED(evt2irq(0x880)), 105};
106
107static struct resource scif0_resources[] = {
108 DEFINE_RES_MEM(0xa4400000, 0x100),
109 DEFINE_RES_IRQ(evt2irq(0x880)),
108}; 110};
109 111
110static struct platform_device scif0_device = { 112static struct platform_device scif0_device = {
111 .name = "sh-sci", 113 .name = "sh-sci",
112 .id = 0, 114 .id = 0,
115 .resource = scif0_resources,
116 .num_resources = ARRAY_SIZE(scif0_resources),
113 .dev = { 117 .dev = {
114 .platform_data = &scif0_platform_data, 118 .platform_data = &scif0_platform_data,
115 }, 119 },
116}; 120};
117 121
118static struct plat_sci_port scif1_platform_data = { 122static struct plat_sci_port scif1_platform_data = {
119 .mapbase = 0xa4410000,
120 .flags = UPF_BOOT_AUTOCONF, 123 .flags = UPF_BOOT_AUTOCONF,
121 .scscr = SCSCR_TE | SCSCR_RE | SCSCR_REIE | 124 .scscr = SCSCR_TE | SCSCR_RE | SCSCR_REIE |
122 SCSCR_CKE1 | SCSCR_CKE0, 125 SCSCR_CKE1 | SCSCR_CKE0,
123 .scbrr_algo_id = SCBRR_ALGO_2,
124 .type = PORT_SCIF, 126 .type = PORT_SCIF,
125 .irqs = SCIx_IRQ_MUXED(evt2irq(0x900)), 127};
128
129static struct resource scif1_resources[] = {
130 DEFINE_RES_MEM(0xa4410000, 0x100),
131 DEFINE_RES_IRQ(evt2irq(0x900)),
126}; 132};
127 133
128static struct platform_device scif1_device = { 134static struct platform_device scif1_device = {
129 .name = "sh-sci", 135 .name = "sh-sci",
130 .id = 1, 136 .id = 1,
137 .resource = scif1_resources,
138 .num_resources = ARRAY_SIZE(scif1_resources),
131 .dev = { 139 .dev = {
132 .platform_data = &scif1_platform_data, 140 .platform_data = &scif1_platform_data,
133 }, 141 },
diff --git a/arch/sh/kernel/cpu/sh3/setup-sh7720.c b/arch/sh/kernel/cpu/sh3/setup-sh7720.c
index 42d991f632b1..1d5729dc0724 100644
--- a/arch/sh/kernel/cpu/sh3/setup-sh7720.c
+++ b/arch/sh/kernel/cpu/sh3/setup-sh7720.c
@@ -52,38 +52,46 @@ static struct platform_device rtc_device = {
52}; 52};
53 53
54static struct plat_sci_port scif0_platform_data = { 54static struct plat_sci_port scif0_platform_data = {
55 .mapbase = 0xa4430000,
56 .flags = UPF_BOOT_AUTOCONF, 55 .flags = UPF_BOOT_AUTOCONF,
57 .scscr = SCSCR_RE | SCSCR_TE, 56 .scscr = SCSCR_RE | SCSCR_TE,
58 .scbrr_algo_id = SCBRR_ALGO_4,
59 .type = PORT_SCIF, 57 .type = PORT_SCIF,
60 .irqs = SCIx_IRQ_MUXED(evt2irq(0xc00)),
61 .ops = &sh7720_sci_port_ops, 58 .ops = &sh7720_sci_port_ops,
62 .regtype = SCIx_SH7705_SCIF_REGTYPE, 59 .regtype = SCIx_SH7705_SCIF_REGTYPE,
63}; 60};
64 61
62static struct resource scif0_resources[] = {
63 DEFINE_RES_MEM(0xa4430000, 0x100),
64 DEFINE_RES_IRQ(evt2irq(0xc00)),
65};
66
65static struct platform_device scif0_device = { 67static struct platform_device scif0_device = {
66 .name = "sh-sci", 68 .name = "sh-sci",
67 .id = 0, 69 .id = 0,
70 .resource = scif0_resources,
71 .num_resources = ARRAY_SIZE(scif0_resources),
68 .dev = { 72 .dev = {
69 .platform_data = &scif0_platform_data, 73 .platform_data = &scif0_platform_data,
70 }, 74 },
71}; 75};
72 76
73static struct plat_sci_port scif1_platform_data = { 77static struct plat_sci_port scif1_platform_data = {
74 .mapbase = 0xa4438000,
75 .flags = UPF_BOOT_AUTOCONF, 78 .flags = UPF_BOOT_AUTOCONF,
76 .scscr = SCSCR_RE | SCSCR_TE, 79 .scscr = SCSCR_RE | SCSCR_TE,
77 .scbrr_algo_id = SCBRR_ALGO_4,
78 .type = PORT_SCIF, 80 .type = PORT_SCIF,
79 .irqs = SCIx_IRQ_MUXED(evt2irq(0xc20)),
80 .ops = &sh7720_sci_port_ops, 81 .ops = &sh7720_sci_port_ops,
81 .regtype = SCIx_SH7705_SCIF_REGTYPE, 82 .regtype = SCIx_SH7705_SCIF_REGTYPE,
82}; 83};
83 84
85static struct resource scif1_resources[] = {
86 DEFINE_RES_MEM(0xa4438000, 0x100),
87 DEFINE_RES_IRQ(evt2irq(0xc20)),
88};
89
84static struct platform_device scif1_device = { 90static struct platform_device scif1_device = {
85 .name = "sh-sci", 91 .name = "sh-sci",
86 .id = 1, 92 .id = 1,
93 .resource = scif1_resources,
94 .num_resources = ARRAY_SIZE(scif1_resources),
87 .dev = { 95 .dev = {
88 .platform_data = &scif1_platform_data, 96 .platform_data = &scif1_platform_data,
89 }, 97 },
diff --git a/arch/sh/kernel/cpu/sh4/setup-sh4-202.c b/arch/sh/kernel/cpu/sh4/setup-sh4-202.c
index 2a5320aa73bb..a8bd778d5ac8 100644
--- a/arch/sh/kernel/cpu/sh4/setup-sh4-202.c
+++ b/arch/sh/kernel/cpu/sh4/setup-sh4-202.c
@@ -17,20 +17,24 @@
17#include <linux/io.h> 17#include <linux/io.h>
18 18
19static struct plat_sci_port scif0_platform_data = { 19static struct plat_sci_port scif0_platform_data = {
20 .mapbase = 0xffe80000,
21 .flags = UPF_BOOT_AUTOCONF, 20 .flags = UPF_BOOT_AUTOCONF,
22 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 21 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
23 .scbrr_algo_id = SCBRR_ALGO_2,
24 .type = PORT_SCIF, 22 .type = PORT_SCIF,
25 .irqs = { evt2irq(0x700), 23};
26 evt2irq(0x720), 24
27 evt2irq(0x760), 25static struct resource scif0_resources[] = {
28 evt2irq(0x740) }, 26 DEFINE_RES_MEM(0xffe80000, 0x100),
27 DEFINE_RES_IRQ(evt2irq(0x700)),
28 DEFINE_RES_IRQ(evt2irq(0x720)),
29 DEFINE_RES_IRQ(evt2irq(0x760)),
30 DEFINE_RES_IRQ(evt2irq(0x740)),
29}; 31};
30 32
31static struct platform_device scif0_device = { 33static struct platform_device scif0_device = {
32 .name = "sh-sci", 34 .name = "sh-sci",
33 .id = 0, 35 .id = 0,
36 .resource = scif0_resources,
37 .num_resources = ARRAY_SIZE(scif0_resources),
34 .dev = { 38 .dev = {
35 .platform_data = &scif0_platform_data, 39 .platform_data = &scif0_platform_data,
36 }, 40 },
diff --git a/arch/sh/kernel/cpu/sh4/setup-sh7750.c b/arch/sh/kernel/cpu/sh4/setup-sh7750.c
index 04a45512596f..a447a248491f 100644
--- a/arch/sh/kernel/cpu/sh4/setup-sh7750.c
+++ b/arch/sh/kernel/cpu/sh4/setup-sh7750.c
@@ -38,36 +38,44 @@ static struct platform_device rtc_device = {
38}; 38};
39 39
40static struct plat_sci_port sci_platform_data = { 40static struct plat_sci_port sci_platform_data = {
41 .mapbase = 0xffe00000,
42 .port_reg = 0xffe0001C, 41 .port_reg = 0xffe0001C,
43 .flags = UPF_BOOT_AUTOCONF, 42 .flags = UPF_BOOT_AUTOCONF,
44 .scscr = SCSCR_TE | SCSCR_RE, 43 .scscr = SCSCR_TE | SCSCR_RE,
45 .scbrr_algo_id = SCBRR_ALGO_2,
46 .type = PORT_SCI, 44 .type = PORT_SCI,
47 .irqs = SCIx_IRQ_MUXED(evt2irq(0x4e0)),
48 .regshift = 2, 45 .regshift = 2,
49}; 46};
50 47
48static struct resource sci_resources[] = {
49 DEFINE_RES_MEM(0xffe00000, 0x100),
50 DEFINE_RES_IRQ(evt2irq(0x4e0)),
51};
52
51static struct platform_device sci_device = { 53static struct platform_device sci_device = {
52 .name = "sh-sci", 54 .name = "sh-sci",
53 .id = 0, 55 .id = 0,
56 .resource = sci_resources,
57 .num_resources = ARRAY_SIZE(sci_resources),
54 .dev = { 58 .dev = {
55 .platform_data = &sci_platform_data, 59 .platform_data = &sci_platform_data,
56 }, 60 },
57}; 61};
58 62
59static struct plat_sci_port scif_platform_data = { 63static struct plat_sci_port scif_platform_data = {
60 .mapbase = 0xffe80000,
61 .flags = UPF_BOOT_AUTOCONF, 64 .flags = UPF_BOOT_AUTOCONF,
62 .scscr = SCSCR_TE | SCSCR_RE | SCSCR_REIE, 65 .scscr = SCSCR_TE | SCSCR_RE | SCSCR_REIE,
63 .scbrr_algo_id = SCBRR_ALGO_2,
64 .type = PORT_SCIF, 66 .type = PORT_SCIF,
65 .irqs = SCIx_IRQ_MUXED(evt2irq(0x700)), 67};
68
69static struct resource scif_resources[] = {
70 DEFINE_RES_MEM(0xffe80000, 0x100),
71 DEFINE_RES_IRQ(evt2irq(0x700)),
66}; 72};
67 73
68static struct platform_device scif_device = { 74static struct platform_device scif_device = {
69 .name = "sh-sci", 75 .name = "sh-sci",
70 .id = 1, 76 .id = 1,
77 .resource = scif_resources,
78 .num_resources = ARRAY_SIZE(scif_resources),
71 .dev = { 79 .dev = {
72 .platform_data = &scif_platform_data, 80 .platform_data = &scif_platform_data,
73 }, 81 },
diff --git a/arch/sh/kernel/cpu/sh4/setup-sh7760.c b/arch/sh/kernel/cpu/sh4/setup-sh7760.c
index 98e075ada44e..1abd9fb4a386 100644
--- a/arch/sh/kernel/cpu/sh4/setup-sh7760.c
+++ b/arch/sh/kernel/cpu/sh4/setup-sh7760.c
@@ -128,83 +128,99 @@ static DECLARE_INTC_DESC(intc_desc_irq, "sh7760-irq", vectors_irq, groups,
128 mask_registers, prio_registers, NULL); 128 mask_registers, prio_registers, NULL);
129 129
130static struct plat_sci_port scif0_platform_data = { 130static struct plat_sci_port scif0_platform_data = {
131 .mapbase = 0xfe600000,
132 .flags = UPF_BOOT_AUTOCONF, 131 .flags = UPF_BOOT_AUTOCONF,
133 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 132 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
134 .scbrr_algo_id = SCBRR_ALGO_2,
135 .type = PORT_SCIF, 133 .type = PORT_SCIF,
136 .irqs = { evt2irq(0x880),
137 evt2irq(0x8a0),
138 evt2irq(0x8e0),
139 evt2irq(0x8c0) },
140 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, 134 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
141}; 135};
142 136
137static struct resource scif0_resources[] = {
138 DEFINE_RES_MEM(0xfe600000, 0x100),
139 DEFINE_RES_IRQ(evt2irq(0x880)),
140 DEFINE_RES_IRQ(evt2irq(0x8a0)),
141 DEFINE_RES_IRQ(evt2irq(0x8e0)),
142 DEFINE_RES_IRQ(evt2irq(0x8c0)),
143};
144
143static struct platform_device scif0_device = { 145static struct platform_device scif0_device = {
144 .name = "sh-sci", 146 .name = "sh-sci",
145 .id = 0, 147 .id = 0,
148 .resource = scif0_resources,
149 .num_resources = ARRAY_SIZE(scif0_resources),
146 .dev = { 150 .dev = {
147 .platform_data = &scif0_platform_data, 151 .platform_data = &scif0_platform_data,
148 }, 152 },
149}; 153};
150 154
151static struct plat_sci_port scif1_platform_data = { 155static struct plat_sci_port scif1_platform_data = {
152 .mapbase = 0xfe610000,
153 .flags = UPF_BOOT_AUTOCONF, 156 .flags = UPF_BOOT_AUTOCONF,
154 .type = PORT_SCIF, 157 .type = PORT_SCIF,
155 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 158 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
156 .scbrr_algo_id = SCBRR_ALGO_2,
157 .irqs = { evt2irq(0xb00),
158 evt2irq(0xb20),
159 evt2irq(0xb60),
160 evt2irq(0xb40) },
161 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, 159 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
162}; 160};
163 161
162static struct resource scif1_resources[] = {
163 DEFINE_RES_MEM(0xfe610000, 0x100),
164 DEFINE_RES_IRQ(evt2irq(0xb00)),
165 DEFINE_RES_IRQ(evt2irq(0xb20)),
166 DEFINE_RES_IRQ(evt2irq(0xb60)),
167 DEFINE_RES_IRQ(evt2irq(0xb40)),
168};
169
164static struct platform_device scif1_device = { 170static struct platform_device scif1_device = {
165 .name = "sh-sci", 171 .name = "sh-sci",
166 .id = 1, 172 .id = 1,
173 .resource = scif1_resources,
174 .num_resources = ARRAY_SIZE(scif1_resources),
167 .dev = { 175 .dev = {
168 .platform_data = &scif1_platform_data, 176 .platform_data = &scif1_platform_data,
169 }, 177 },
170}; 178};
171 179
172static struct plat_sci_port scif2_platform_data = { 180static struct plat_sci_port scif2_platform_data = {
173 .mapbase = 0xfe620000,
174 .flags = UPF_BOOT_AUTOCONF, 181 .flags = UPF_BOOT_AUTOCONF,
175 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 182 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
176 .scbrr_algo_id = SCBRR_ALGO_2,
177 .type = PORT_SCIF, 183 .type = PORT_SCIF,
178 .irqs = { evt2irq(0xb80),
179 evt2irq(0xba0),
180 evt2irq(0xbe0),
181 evt2irq(0xbc0) },
182 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, 184 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
183}; 185};
184 186
187static struct resource scif2_resources[] = {
188 DEFINE_RES_MEM(0xfe620000, 0x100),
189 DEFINE_RES_IRQ(evt2irq(0xb80)),
190 DEFINE_RES_IRQ(evt2irq(0xba0)),
191 DEFINE_RES_IRQ(evt2irq(0xbe0)),
192 DEFINE_RES_IRQ(evt2irq(0xbc0)),
193};
194
185static struct platform_device scif2_device = { 195static struct platform_device scif2_device = {
186 .name = "sh-sci", 196 .name = "sh-sci",
187 .id = 2, 197 .id = 2,
198 .resource = scif2_resources,
199 .num_resources = ARRAY_SIZE(scif2_resources),
188 .dev = { 200 .dev = {
189 .platform_data = &scif2_platform_data, 201 .platform_data = &scif2_platform_data,
190 }, 202 },
191}; 203};
192 204
193static struct plat_sci_port scif3_platform_data = { 205static struct plat_sci_port scif3_platform_data = {
194 .mapbase = 0xfe480000,
195 .flags = UPF_BOOT_AUTOCONF, 206 .flags = UPF_BOOT_AUTOCONF,
196 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 207 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
197 .scbrr_algo_id = SCBRR_ALGO_2,
198 .type = PORT_SCI, 208 .type = PORT_SCI,
199 .irqs = { evt2irq(0xc00),
200 evt2irq(0xc20),
201 evt2irq(0xc40), },
202 .regshift = 2, 209 .regshift = 2,
203}; 210};
204 211
212static struct resource scif3_resources[] = {
213 DEFINE_RES_MEM(0xfe480000, 0x100),
214 DEFINE_RES_IRQ(evt2irq(0xc00)),
215 DEFINE_RES_IRQ(evt2irq(0xc20)),
216 DEFINE_RES_IRQ(evt2irq(0xc40)),
217};
218
205static struct platform_device scif3_device = { 219static struct platform_device scif3_device = {
206 .name = "sh-sci", 220 .name = "sh-sci",
207 .id = 3, 221 .id = 3,
222 .resource = scif3_resources,
223 .num_resources = ARRAY_SIZE(scif3_resources),
208 .dev = { 224 .dev = {
209 .platform_data = &scif3_platform_data, 225 .platform_data = &scif3_platform_data,
210 }, 226 },
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7343.c b/arch/sh/kernel/cpu/sh4a/setup-sh7343.c
index b91ea8300a3e..245d19254489 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7343.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7343.c
@@ -18,68 +18,84 @@
18 18
19/* Serial */ 19/* Serial */
20static struct plat_sci_port scif0_platform_data = { 20static struct plat_sci_port scif0_platform_data = {
21 .mapbase = 0xffe00000,
22 .flags = UPF_BOOT_AUTOCONF, 21 .flags = UPF_BOOT_AUTOCONF,
23 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, 22 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
24 .scbrr_algo_id = SCBRR_ALGO_2,
25 .type = PORT_SCIF, 23 .type = PORT_SCIF,
26 .irqs = SCIx_IRQ_MUXED(evt2irq(0xc00)), 24};
25
26static struct resource scif0_resources[] = {
27 DEFINE_RES_MEM(0xffe00000, 0x100),
28 DEFINE_RES_IRQ(evt2irq(0xc00)),
27}; 29};
28 30
29static struct platform_device scif0_device = { 31static struct platform_device scif0_device = {
30 .name = "sh-sci", 32 .name = "sh-sci",
31 .id = 0, 33 .id = 0,
34 .resource = scif0_resources,
35 .num_resources = ARRAY_SIZE(scif0_resources),
32 .dev = { 36 .dev = {
33 .platform_data = &scif0_platform_data, 37 .platform_data = &scif0_platform_data,
34 }, 38 },
35}; 39};
36 40
37static struct plat_sci_port scif1_platform_data = { 41static struct plat_sci_port scif1_platform_data = {
38 .mapbase = 0xffe10000,
39 .flags = UPF_BOOT_AUTOCONF, 42 .flags = UPF_BOOT_AUTOCONF,
40 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, 43 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
41 .scbrr_algo_id = SCBRR_ALGO_2,
42 .type = PORT_SCIF, 44 .type = PORT_SCIF,
43 .irqs = SCIx_IRQ_MUXED(evt2irq(0xc20)), 45};
46
47static struct resource scif1_resources[] = {
48 DEFINE_RES_MEM(0xffe10000, 0x100),
49 DEFINE_RES_IRQ(evt2irq(0xc20)),
44}; 50};
45 51
46static struct platform_device scif1_device = { 52static struct platform_device scif1_device = {
47 .name = "sh-sci", 53 .name = "sh-sci",
48 .id = 1, 54 .id = 1,
55 .resource = scif1_resources,
56 .num_resources = ARRAY_SIZE(scif1_resources),
49 .dev = { 57 .dev = {
50 .platform_data = &scif1_platform_data, 58 .platform_data = &scif1_platform_data,
51 }, 59 },
52}; 60};
53 61
54static struct plat_sci_port scif2_platform_data = { 62static struct plat_sci_port scif2_platform_data = {
55 .mapbase = 0xffe20000,
56 .flags = UPF_BOOT_AUTOCONF, 63 .flags = UPF_BOOT_AUTOCONF,
57 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, 64 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
58 .scbrr_algo_id = SCBRR_ALGO_2,
59 .type = PORT_SCIF, 65 .type = PORT_SCIF,
60 .irqs = SCIx_IRQ_MUXED(evt2irq(0xc40)), 66};
67
68static struct resource scif2_resources[] = {
69 DEFINE_RES_MEM(0xffe20000, 0x100),
70 DEFINE_RES_IRQ(evt2irq(0xc40)),
61}; 71};
62 72
63static struct platform_device scif2_device = { 73static struct platform_device scif2_device = {
64 .name = "sh-sci", 74 .name = "sh-sci",
65 .id = 2, 75 .id = 2,
76 .resource = scif2_resources,
77 .num_resources = ARRAY_SIZE(scif2_resources),
66 .dev = { 78 .dev = {
67 .platform_data = &scif2_platform_data, 79 .platform_data = &scif2_platform_data,
68 }, 80 },
69}; 81};
70 82
71static struct plat_sci_port scif3_platform_data = { 83static struct plat_sci_port scif3_platform_data = {
72 .mapbase = 0xffe30000,
73 .flags = UPF_BOOT_AUTOCONF, 84 .flags = UPF_BOOT_AUTOCONF,
74 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, 85 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
75 .scbrr_algo_id = SCBRR_ALGO_2,
76 .type = PORT_SCIF, 86 .type = PORT_SCIF,
77 .irqs = SCIx_IRQ_MUXED(evt2irq(0xc60)), 87};
88
89static struct resource scif3_resources[] = {
90 DEFINE_RES_MEM(0xffe30000, 0x100),
91 DEFINE_RES_IRQ(evt2irq(0xc60)),
78}; 92};
79 93
80static struct platform_device scif3_device = { 94static struct platform_device scif3_device = {
81 .name = "sh-sci", 95 .name = "sh-sci",
82 .id = 3, 96 .id = 3,
97 .resource = scif3_resources,
98 .num_resources = ARRAY_SIZE(scif3_resources),
83 .dev = { 99 .dev = {
84 .platform_data = &scif3_platform_data, 100 .platform_data = &scif3_platform_data,
85 }, 101 },
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7366.c b/arch/sh/kernel/cpu/sh4a/setup-sh7366.c
index 0bd09d51419f..6f56cbd76b20 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7366.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7366.c
@@ -20,18 +20,22 @@
20#include <asm/clock.h> 20#include <asm/clock.h>
21 21
22static struct plat_sci_port scif0_platform_data = { 22static struct plat_sci_port scif0_platform_data = {
23 .mapbase = 0xffe00000,
24 .port_reg = 0xa405013e, 23 .port_reg = 0xa405013e,
25 .flags = UPF_BOOT_AUTOCONF, 24 .flags = UPF_BOOT_AUTOCONF,
26 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 25 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
27 .scbrr_algo_id = SCBRR_ALGO_2,
28 .type = PORT_SCIF, 26 .type = PORT_SCIF,
29 .irqs = SCIx_IRQ_MUXED(evt2irq(0xc00)), 27};
28
29static struct resource scif0_resources[] = {
30 DEFINE_RES_MEM(0xffe00000, 0x100),
31 DEFINE_RES_IRQ(evt2irq(0xc00)),
30}; 32};
31 33
32static struct platform_device scif0_device = { 34static struct platform_device scif0_device = {
33 .name = "sh-sci", 35 .name = "sh-sci",
34 .id = 0, 36 .id = 0,
37 .resource = scif0_resources,
38 .num_resources = ARRAY_SIZE(scif0_resources),
35 .dev = { 39 .dev = {
36 .platform_data = &scif0_platform_data, 40 .platform_data = &scif0_platform_data,
37 }, 41 },
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7722.c b/arch/sh/kernel/cpu/sh4a/setup-sh7722.c
index 6a868b091c2d..5a94efc8d4ce 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7722.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7722.c
@@ -179,57 +179,69 @@ struct platform_device dma_device = {
179 179
180/* Serial */ 180/* Serial */
181static struct plat_sci_port scif0_platform_data = { 181static struct plat_sci_port scif0_platform_data = {
182 .mapbase = 0xffe00000,
183 .flags = UPF_BOOT_AUTOCONF, 182 .flags = UPF_BOOT_AUTOCONF,
184 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 183 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
185 .scbrr_algo_id = SCBRR_ALGO_2,
186 .type = PORT_SCIF, 184 .type = PORT_SCIF,
187 .irqs = SCIx_IRQ_MUXED(evt2irq(0xc00)),
188 .ops = &sh7722_sci_port_ops, 185 .ops = &sh7722_sci_port_ops,
189 .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE, 186 .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE,
190}; 187};
191 188
189static struct resource scif0_resources[] = {
190 DEFINE_RES_MEM(0xffe00000, 0x100),
191 DEFINE_RES_IRQ(evt2irq(0xc00)),
192};
193
192static struct platform_device scif0_device = { 194static struct platform_device scif0_device = {
193 .name = "sh-sci", 195 .name = "sh-sci",
194 .id = 0, 196 .id = 0,
197 .resource = scif0_resources,
198 .num_resources = ARRAY_SIZE(scif0_resources),
195 .dev = { 199 .dev = {
196 .platform_data = &scif0_platform_data, 200 .platform_data = &scif0_platform_data,
197 }, 201 },
198}; 202};
199 203
200static struct plat_sci_port scif1_platform_data = { 204static struct plat_sci_port scif1_platform_data = {
201 .mapbase = 0xffe10000,
202 .flags = UPF_BOOT_AUTOCONF, 205 .flags = UPF_BOOT_AUTOCONF,
203 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 206 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
204 .scbrr_algo_id = SCBRR_ALGO_2,
205 .type = PORT_SCIF, 207 .type = PORT_SCIF,
206 .irqs = SCIx_IRQ_MUXED(evt2irq(0xc20)),
207 .ops = &sh7722_sci_port_ops, 208 .ops = &sh7722_sci_port_ops,
208 .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE, 209 .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE,
209}; 210};
210 211
212static struct resource scif1_resources[] = {
213 DEFINE_RES_MEM(0xffe10000, 0x100),
214 DEFINE_RES_IRQ(evt2irq(0xc20)),
215};
216
211static struct platform_device scif1_device = { 217static struct platform_device scif1_device = {
212 .name = "sh-sci", 218 .name = "sh-sci",
213 .id = 1, 219 .id = 1,
220 .resource = scif1_resources,
221 .num_resources = ARRAY_SIZE(scif1_resources),
214 .dev = { 222 .dev = {
215 .platform_data = &scif1_platform_data, 223 .platform_data = &scif1_platform_data,
216 }, 224 },
217}; 225};
218 226
219static struct plat_sci_port scif2_platform_data = { 227static struct plat_sci_port scif2_platform_data = {
220 .mapbase = 0xffe20000,
221 .flags = UPF_BOOT_AUTOCONF, 228 .flags = UPF_BOOT_AUTOCONF,
222 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 229 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
223 .scbrr_algo_id = SCBRR_ALGO_2,
224 .type = PORT_SCIF, 230 .type = PORT_SCIF,
225 .irqs = SCIx_IRQ_MUXED(evt2irq(0xc40)),
226 .ops = &sh7722_sci_port_ops, 231 .ops = &sh7722_sci_port_ops,
227 .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE, 232 .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE,
228}; 233};
229 234
235static struct resource scif2_resources[] = {
236 DEFINE_RES_MEM(0xffe20000, 0x100),
237 DEFINE_RES_IRQ(evt2irq(0xc40)),
238};
239
230static struct platform_device scif2_device = { 240static struct platform_device scif2_device = {
231 .name = "sh-sci", 241 .name = "sh-sci",
232 .id = 2, 242 .id = 2,
243 .resource = scif2_resources,
244 .num_resources = ARRAY_SIZE(scif2_resources),
233 .dev = { 245 .dev = {
234 .platform_data = &scif2_platform_data, 246 .platform_data = &scif2_platform_data,
235 }, 247 },
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7723.c b/arch/sh/kernel/cpu/sh4a/setup-sh7723.c
index 28d6fd835fe0..3c5eb0993a75 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7723.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7723.c
@@ -23,111 +23,138 @@
23 23
24/* Serial */ 24/* Serial */
25static struct plat_sci_port scif0_platform_data = { 25static struct plat_sci_port scif0_platform_data = {
26 .mapbase = 0xffe00000,
27 .port_reg = 0xa4050160, 26 .port_reg = 0xa4050160,
28 .flags = UPF_BOOT_AUTOCONF, 27 .flags = UPF_BOOT_AUTOCONF,
29 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 28 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
30 .scbrr_algo_id = SCBRR_ALGO_2,
31 .type = PORT_SCIF, 29 .type = PORT_SCIF,
32 .irqs = SCIx_IRQ_MUXED(evt2irq(0xc00)),
33 .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE, 30 .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE,
34}; 31};
35 32
33static struct resource scif0_resources[] = {
34 DEFINE_RES_MEM(0xffe00000, 0x100),
35 DEFINE_RES_IRQ(evt2irq(0xc00)),
36};
37
36static struct platform_device scif0_device = { 38static struct platform_device scif0_device = {
37 .name = "sh-sci", 39 .name = "sh-sci",
38 .id = 0, 40 .id = 0,
41 .resource = scif0_resources,
42 .num_resources = ARRAY_SIZE(scif0_resources),
39 .dev = { 43 .dev = {
40 .platform_data = &scif0_platform_data, 44 .platform_data = &scif0_platform_data,
41 }, 45 },
42}; 46};
43 47
44static struct plat_sci_port scif1_platform_data = { 48static struct plat_sci_port scif1_platform_data = {
45 .mapbase = 0xffe10000,
46 .port_reg = SCIx_NOT_SUPPORTED, 49 .port_reg = SCIx_NOT_SUPPORTED,
47 .flags = UPF_BOOT_AUTOCONF, 50 .flags = UPF_BOOT_AUTOCONF,
48 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 51 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
49 .scbrr_algo_id = SCBRR_ALGO_2,
50 .type = PORT_SCIF, 52 .type = PORT_SCIF,
51 .irqs = SCIx_IRQ_MUXED(evt2irq(0xc20)),
52 .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE, 53 .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE,
53}; 54};
54 55
56static struct resource scif1_resources[] = {
57 DEFINE_RES_MEM(0xffe10000, 0x100),
58 DEFINE_RES_IRQ(evt2irq(0xc20)),
59};
60
55static struct platform_device scif1_device = { 61static struct platform_device scif1_device = {
56 .name = "sh-sci", 62 .name = "sh-sci",
57 .id = 1, 63 .id = 1,
64 .resource = scif1_resources,
65 .num_resources = ARRAY_SIZE(scif1_resources),
58 .dev = { 66 .dev = {
59 .platform_data = &scif1_platform_data, 67 .platform_data = &scif1_platform_data,
60 }, 68 },
61}; 69};
62 70
63static struct plat_sci_port scif2_platform_data = { 71static struct plat_sci_port scif2_platform_data = {
64 .mapbase = 0xffe20000,
65 .port_reg = SCIx_NOT_SUPPORTED, 72 .port_reg = SCIx_NOT_SUPPORTED,
66 .flags = UPF_BOOT_AUTOCONF, 73 .flags = UPF_BOOT_AUTOCONF,
67 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 74 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
68 .scbrr_algo_id = SCBRR_ALGO_2,
69 .type = PORT_SCIF, 75 .type = PORT_SCIF,
70 .irqs = SCIx_IRQ_MUXED(evt2irq(0xc40)),
71 .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE, 76 .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE,
72}; 77};
73 78
79static struct resource scif2_resources[] = {
80 DEFINE_RES_MEM(0xffe20000, 0x100),
81 DEFINE_RES_IRQ(evt2irq(0xc40)),
82};
83
74static struct platform_device scif2_device = { 84static struct platform_device scif2_device = {
75 .name = "sh-sci", 85 .name = "sh-sci",
76 .id = 2, 86 .id = 2,
87 .resource = scif2_resources,
88 .num_resources = ARRAY_SIZE(scif2_resources),
77 .dev = { 89 .dev = {
78 .platform_data = &scif2_platform_data, 90 .platform_data = &scif2_platform_data,
79 }, 91 },
80}; 92};
81 93
82static struct plat_sci_port scif3_platform_data = { 94static struct plat_sci_port scif3_platform_data = {
83 .mapbase = 0xa4e30000,
84 .flags = UPF_BOOT_AUTOCONF, 95 .flags = UPF_BOOT_AUTOCONF,
85 .port_reg = SCIx_NOT_SUPPORTED, 96 .port_reg = SCIx_NOT_SUPPORTED,
86 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 97 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
87 .scbrr_algo_id = SCBRR_ALGO_3, 98 .sampling_rate = 8,
88 .type = PORT_SCIFA, 99 .type = PORT_SCIFA,
89 .irqs = SCIx_IRQ_MUXED(evt2irq(0x900)), 100};
101
102static struct resource scif3_resources[] = {
103 DEFINE_RES_MEM(0xa4e30000, 0x100),
104 DEFINE_RES_IRQ(evt2irq(0x900)),
90}; 105};
91 106
92static struct platform_device scif3_device = { 107static struct platform_device scif3_device = {
93 .name = "sh-sci", 108 .name = "sh-sci",
94 .id = 3, 109 .id = 3,
110 .resource = scif3_resources,
111 .num_resources = ARRAY_SIZE(scif3_resources),
95 .dev = { 112 .dev = {
96 .platform_data = &scif3_platform_data, 113 .platform_data = &scif3_platform_data,
97 }, 114 },
98}; 115};
99 116
100static struct plat_sci_port scif4_platform_data = { 117static struct plat_sci_port scif4_platform_data = {
101 .mapbase = 0xa4e40000,
102 .port_reg = SCIx_NOT_SUPPORTED, 118 .port_reg = SCIx_NOT_SUPPORTED,
103 .flags = UPF_BOOT_AUTOCONF, 119 .flags = UPF_BOOT_AUTOCONF,
104 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 120 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
105 .scbrr_algo_id = SCBRR_ALGO_3, 121 .sampling_rate = 8,
106 .type = PORT_SCIFA, 122 .type = PORT_SCIFA,
107 .irqs = SCIx_IRQ_MUXED(evt2irq(0xd00)), 123};
124
125static struct resource scif4_resources[] = {
126 DEFINE_RES_MEM(0xa4e40000, 0x100),
127 DEFINE_RES_IRQ(evt2irq(0xd00)),
108}; 128};
109 129
110static struct platform_device scif4_device = { 130static struct platform_device scif4_device = {
111 .name = "sh-sci", 131 .name = "sh-sci",
112 .id = 4, 132 .id = 4,
133 .resource = scif4_resources,
134 .num_resources = ARRAY_SIZE(scif4_resources),
113 .dev = { 135 .dev = {
114 .platform_data = &scif4_platform_data, 136 .platform_data = &scif4_platform_data,
115 }, 137 },
116}; 138};
117 139
118static struct plat_sci_port scif5_platform_data = { 140static struct plat_sci_port scif5_platform_data = {
119 .mapbase = 0xa4e50000,
120 .port_reg = SCIx_NOT_SUPPORTED, 141 .port_reg = SCIx_NOT_SUPPORTED,
121 .flags = UPF_BOOT_AUTOCONF, 142 .flags = UPF_BOOT_AUTOCONF,
122 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 143 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
123 .scbrr_algo_id = SCBRR_ALGO_3, 144 .sampling_rate = 8,
124 .type = PORT_SCIFA, 145 .type = PORT_SCIFA,
125 .irqs = SCIx_IRQ_MUXED(evt2irq(0xfa0)), 146};
147
148static struct resource scif5_resources[] = {
149 DEFINE_RES_MEM(0xa4e50000, 0x100),
150 DEFINE_RES_IRQ(evt2irq(0xfa0)),
126}; 151};
127 152
128static struct platform_device scif5_device = { 153static struct platform_device scif5_device = {
129 .name = "sh-sci", 154 .name = "sh-sci",
130 .id = 5, 155 .id = 5,
156 .resource = scif5_resources,
157 .num_resources = ARRAY_SIZE(scif5_resources),
131 .dev = { 158 .dev = {
132 .platform_data = &scif5_platform_data, 159 .platform_data = &scif5_platform_data,
133 }, 160 },
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7724.c b/arch/sh/kernel/cpu/sh4a/setup-sh7724.c
index 26b74c2f9496..60ebbc6842ff 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7724.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7724.c
@@ -290,111 +290,138 @@ static struct platform_device dma1_device = {
290 290
291/* Serial */ 291/* Serial */
292static struct plat_sci_port scif0_platform_data = { 292static struct plat_sci_port scif0_platform_data = {
293 .mapbase = 0xffe00000,
294 .port_reg = SCIx_NOT_SUPPORTED, 293 .port_reg = SCIx_NOT_SUPPORTED,
295 .flags = UPF_BOOT_AUTOCONF, 294 .flags = UPF_BOOT_AUTOCONF,
296 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 295 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
297 .scbrr_algo_id = SCBRR_ALGO_2,
298 .type = PORT_SCIF, 296 .type = PORT_SCIF,
299 .irqs = SCIx_IRQ_MUXED(evt2irq(0xc00)),
300 .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE, 297 .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE,
301}; 298};
302 299
300static struct resource scif0_resources[] = {
301 DEFINE_RES_MEM(0xffe00000, 0x100),
302 DEFINE_RES_IRQ(evt2irq(0xc00)),
303};
304
303static struct platform_device scif0_device = { 305static struct platform_device scif0_device = {
304 .name = "sh-sci", 306 .name = "sh-sci",
305 .id = 0, 307 .id = 0,
308 .resource = scif0_resources,
309 .num_resources = ARRAY_SIZE(scif0_resources),
306 .dev = { 310 .dev = {
307 .platform_data = &scif0_platform_data, 311 .platform_data = &scif0_platform_data,
308 }, 312 },
309}; 313};
310 314
311static struct plat_sci_port scif1_platform_data = { 315static struct plat_sci_port scif1_platform_data = {
312 .mapbase = 0xffe10000,
313 .port_reg = SCIx_NOT_SUPPORTED, 316 .port_reg = SCIx_NOT_SUPPORTED,
314 .flags = UPF_BOOT_AUTOCONF, 317 .flags = UPF_BOOT_AUTOCONF,
315 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 318 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
316 .scbrr_algo_id = SCBRR_ALGO_2,
317 .type = PORT_SCIF, 319 .type = PORT_SCIF,
318 .irqs = SCIx_IRQ_MUXED(evt2irq(0xc20)),
319 .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE, 320 .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE,
320}; 321};
321 322
323static struct resource scif1_resources[] = {
324 DEFINE_RES_MEM(0xffe10000, 0x100),
325 DEFINE_RES_IRQ(evt2irq(0xc20)),
326};
327
322static struct platform_device scif1_device = { 328static struct platform_device scif1_device = {
323 .name = "sh-sci", 329 .name = "sh-sci",
324 .id = 1, 330 .id = 1,
331 .resource = scif1_resources,
332 .num_resources = ARRAY_SIZE(scif1_resources),
325 .dev = { 333 .dev = {
326 .platform_data = &scif1_platform_data, 334 .platform_data = &scif1_platform_data,
327 }, 335 },
328}; 336};
329 337
330static struct plat_sci_port scif2_platform_data = { 338static struct plat_sci_port scif2_platform_data = {
331 .mapbase = 0xffe20000,
332 .port_reg = SCIx_NOT_SUPPORTED, 339 .port_reg = SCIx_NOT_SUPPORTED,
333 .flags = UPF_BOOT_AUTOCONF, 340 .flags = UPF_BOOT_AUTOCONF,
334 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 341 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
335 .scbrr_algo_id = SCBRR_ALGO_2,
336 .type = PORT_SCIF, 342 .type = PORT_SCIF,
337 .irqs = SCIx_IRQ_MUXED(evt2irq(0xc40)),
338 .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE, 343 .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE,
339}; 344};
340 345
346static struct resource scif2_resources[] = {
347 DEFINE_RES_MEM(0xffe20000, 0x100),
348 DEFINE_RES_IRQ(evt2irq(0xc40)),
349};
350
341static struct platform_device scif2_device = { 351static struct platform_device scif2_device = {
342 .name = "sh-sci", 352 .name = "sh-sci",
343 .id = 2, 353 .id = 2,
354 .resource = scif2_resources,
355 .num_resources = ARRAY_SIZE(scif2_resources),
344 .dev = { 356 .dev = {
345 .platform_data = &scif2_platform_data, 357 .platform_data = &scif2_platform_data,
346 }, 358 },
347}; 359};
348 360
349static struct plat_sci_port scif3_platform_data = { 361static struct plat_sci_port scif3_platform_data = {
350 .mapbase = 0xa4e30000,
351 .port_reg = SCIx_NOT_SUPPORTED, 362 .port_reg = SCIx_NOT_SUPPORTED,
352 .flags = UPF_BOOT_AUTOCONF, 363 .flags = UPF_BOOT_AUTOCONF,
353 .scscr = SCSCR_RE | SCSCR_TE, 364 .scscr = SCSCR_RE | SCSCR_TE,
354 .scbrr_algo_id = SCBRR_ALGO_3, 365 .sampling_rate = 8,
355 .type = PORT_SCIFA, 366 .type = PORT_SCIFA,
356 .irqs = SCIx_IRQ_MUXED(evt2irq(0x900)), 367};
368
369static struct resource scif3_resources[] = {
370 DEFINE_RES_MEM(0xa4e30000, 0x100),
371 DEFINE_RES_IRQ(evt2irq(0x900)),
357}; 372};
358 373
359static struct platform_device scif3_device = { 374static struct platform_device scif3_device = {
360 .name = "sh-sci", 375 .name = "sh-sci",
361 .id = 3, 376 .id = 3,
377 .resource = scif3_resources,
378 .num_resources = ARRAY_SIZE(scif3_resources),
362 .dev = { 379 .dev = {
363 .platform_data = &scif3_platform_data, 380 .platform_data = &scif3_platform_data,
364 }, 381 },
365}; 382};
366 383
367static struct plat_sci_port scif4_platform_data = { 384static struct plat_sci_port scif4_platform_data = {
368 .mapbase = 0xa4e40000,
369 .port_reg = SCIx_NOT_SUPPORTED, 385 .port_reg = SCIx_NOT_SUPPORTED,
370 .flags = UPF_BOOT_AUTOCONF, 386 .flags = UPF_BOOT_AUTOCONF,
371 .scscr = SCSCR_RE | SCSCR_TE, 387 .scscr = SCSCR_RE | SCSCR_TE,
372 .scbrr_algo_id = SCBRR_ALGO_3, 388 .sampling_rate = 8,
373 .type = PORT_SCIFA, 389 .type = PORT_SCIFA,
374 .irqs = SCIx_IRQ_MUXED(evt2irq(0xd00)), 390};
391
392static struct resource scif4_resources[] = {
393 DEFINE_RES_MEM(0xa4e40000, 0x100),
394 DEFINE_RES_IRQ(evt2irq(0xd00)),
375}; 395};
376 396
377static struct platform_device scif4_device = { 397static struct platform_device scif4_device = {
378 .name = "sh-sci", 398 .name = "sh-sci",
379 .id = 4, 399 .id = 4,
400 .resource = scif4_resources,
401 .num_resources = ARRAY_SIZE(scif4_resources),
380 .dev = { 402 .dev = {
381 .platform_data = &scif4_platform_data, 403 .platform_data = &scif4_platform_data,
382 }, 404 },
383}; 405};
384 406
385static struct plat_sci_port scif5_platform_data = { 407static struct plat_sci_port scif5_platform_data = {
386 .mapbase = 0xa4e50000,
387 .port_reg = SCIx_NOT_SUPPORTED, 408 .port_reg = SCIx_NOT_SUPPORTED,
388 .flags = UPF_BOOT_AUTOCONF, 409 .flags = UPF_BOOT_AUTOCONF,
389 .scscr = SCSCR_RE | SCSCR_TE, 410 .scscr = SCSCR_RE | SCSCR_TE,
390 .scbrr_algo_id = SCBRR_ALGO_3, 411 .sampling_rate = 8,
391 .type = PORT_SCIFA, 412 .type = PORT_SCIFA,
392 .irqs = SCIx_IRQ_MUXED(evt2irq(0xfa0)), 413};
414
415static struct resource scif5_resources[] = {
416 DEFINE_RES_MEM(0xa4e50000, 0x100),
417 DEFINE_RES_IRQ(evt2irq(0xfa0)),
393}; 418};
394 419
395static struct platform_device scif5_device = { 420static struct platform_device scif5_device = {
396 .name = "sh-sci", 421 .name = "sh-sci",
397 .id = 5, 422 .id = 5,
423 .resource = scif5_resources,
424 .num_resources = ARRAY_SIZE(scif5_resources),
398 .dev = { 425 .dev = {
399 .platform_data = &scif5_platform_data, 426 .platform_data = &scif5_platform_data,
400 }, 427 },
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7734.c b/arch/sh/kernel/cpu/sh4a/setup-sh7734.c
index f799971d453c..dad4ed1b2f94 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7734.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7734.c
@@ -25,108 +25,132 @@
25 25
26/* SCIF */ 26/* SCIF */
27static struct plat_sci_port scif0_platform_data = { 27static struct plat_sci_port scif0_platform_data = {
28 .mapbase = 0xFFE40000,
29 .flags = UPF_BOOT_AUTOCONF, 28 .flags = UPF_BOOT_AUTOCONF,
30 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 29 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
31 .scbrr_algo_id = SCBRR_ALGO_2,
32 .type = PORT_SCIF, 30 .type = PORT_SCIF,
33 .irqs = SCIx_IRQ_MUXED(evt2irq(0x8C0)),
34 .regtype = SCIx_SH4_SCIF_REGTYPE, 31 .regtype = SCIx_SH4_SCIF_REGTYPE,
35}; 32};
36 33
34static struct resource scif0_resources[] = {
35 DEFINE_RES_MEM(0xffe40000, 0x100),
36 DEFINE_RES_IRQ(evt2irq(0x8c0)),
37};
38
37static struct platform_device scif0_device = { 39static struct platform_device scif0_device = {
38 .name = "sh-sci", 40 .name = "sh-sci",
39 .id = 0, 41 .id = 0,
42 .resource = scif0_resources,
43 .num_resources = ARRAY_SIZE(scif0_resources),
40 .dev = { 44 .dev = {
41 .platform_data = &scif0_platform_data, 45 .platform_data = &scif0_platform_data,
42 }, 46 },
43}; 47};
44 48
45static struct plat_sci_port scif1_platform_data = { 49static struct plat_sci_port scif1_platform_data = {
46 .mapbase = 0xFFE41000,
47 .flags = UPF_BOOT_AUTOCONF, 50 .flags = UPF_BOOT_AUTOCONF,
48 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 51 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
49 .scbrr_algo_id = SCBRR_ALGO_2,
50 .type = PORT_SCIF, 52 .type = PORT_SCIF,
51 .irqs = SCIx_IRQ_MUXED(evt2irq(0x8E0)),
52 .regtype = SCIx_SH4_SCIF_REGTYPE, 53 .regtype = SCIx_SH4_SCIF_REGTYPE,
53}; 54};
54 55
56static struct resource scif1_resources[] = {
57 DEFINE_RES_MEM(0xffe41000, 0x100),
58 DEFINE_RES_IRQ(evt2irq(0x8e0)),
59};
60
55static struct platform_device scif1_device = { 61static struct platform_device scif1_device = {
56 .name = "sh-sci", 62 .name = "sh-sci",
57 .id = 1, 63 .id = 1,
64 .resource = scif1_resources,
65 .num_resources = ARRAY_SIZE(scif1_resources),
58 .dev = { 66 .dev = {
59 .platform_data = &scif1_platform_data, 67 .platform_data = &scif1_platform_data,
60 }, 68 },
61}; 69};
62 70
63static struct plat_sci_port scif2_platform_data = { 71static struct plat_sci_port scif2_platform_data = {
64 .mapbase = 0xFFE42000,
65 .flags = UPF_BOOT_AUTOCONF, 72 .flags = UPF_BOOT_AUTOCONF,
66 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 73 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
67 .scbrr_algo_id = SCBRR_ALGO_2,
68 .type = PORT_SCIF, 74 .type = PORT_SCIF,
69 .irqs = SCIx_IRQ_MUXED(evt2irq(0x900)),
70 .regtype = SCIx_SH4_SCIF_REGTYPE, 75 .regtype = SCIx_SH4_SCIF_REGTYPE,
71}; 76};
72 77
78static struct resource scif2_resources[] = {
79 DEFINE_RES_MEM(0xffe42000, 0x100),
80 DEFINE_RES_IRQ(evt2irq(0x900)),
81};
82
73static struct platform_device scif2_device = { 83static struct platform_device scif2_device = {
74 .name = "sh-sci", 84 .name = "sh-sci",
75 .id = 2, 85 .id = 2,
86 .resource = scif2_resources,
87 .num_resources = ARRAY_SIZE(scif2_resources),
76 .dev = { 88 .dev = {
77 .platform_data = &scif2_platform_data, 89 .platform_data = &scif2_platform_data,
78 }, 90 },
79}; 91};
80 92
81static struct plat_sci_port scif3_platform_data = { 93static struct plat_sci_port scif3_platform_data = {
82 .mapbase = 0xFFE43000,
83 .flags = UPF_BOOT_AUTOCONF, 94 .flags = UPF_BOOT_AUTOCONF,
84 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, 95 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
85 .scbrr_algo_id = SCBRR_ALGO_2,
86 .type = PORT_SCIF, 96 .type = PORT_SCIF,
87 .irqs = SCIx_IRQ_MUXED(evt2irq(0x920)),
88 .regtype = SCIx_SH4_SCIF_REGTYPE, 97 .regtype = SCIx_SH4_SCIF_REGTYPE,
89}; 98};
90 99
100static struct resource scif3_resources[] = {
101 DEFINE_RES_MEM(0xffe43000, 0x100),
102 DEFINE_RES_IRQ(evt2irq(0x920)),
103};
104
91static struct platform_device scif3_device = { 105static struct platform_device scif3_device = {
92 .name = "sh-sci", 106 .name = "sh-sci",
93 .id = 3, 107 .id = 3,
108 .resource = scif3_resources,
109 .num_resources = ARRAY_SIZE(scif3_resources),
94 .dev = { 110 .dev = {
95 .platform_data = &scif3_platform_data, 111 .platform_data = &scif3_platform_data,
96 }, 112 },
97}; 113};
98 114
99static struct plat_sci_port scif4_platform_data = { 115static struct plat_sci_port scif4_platform_data = {
100 .mapbase = 0xFFE44000,
101 .flags = UPF_BOOT_AUTOCONF, 116 .flags = UPF_BOOT_AUTOCONF,
102 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 117 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
103 .scbrr_algo_id = SCBRR_ALGO_2,
104 .type = PORT_SCIF, 118 .type = PORT_SCIF,
105 .irqs = SCIx_IRQ_MUXED(evt2irq(0x940)),
106 .regtype = SCIx_SH4_SCIF_REGTYPE, 119 .regtype = SCIx_SH4_SCIF_REGTYPE,
107}; 120};
108 121
122static struct resource scif4_resources[] = {
123 DEFINE_RES_MEM(0xffe44000, 0x100),
124 DEFINE_RES_IRQ(evt2irq(0x940)),
125};
126
109static struct platform_device scif4_device = { 127static struct platform_device scif4_device = {
110 .name = "sh-sci", 128 .name = "sh-sci",
111 .id = 4, 129 .id = 4,
130 .resource = scif4_resources,
131 .num_resources = ARRAY_SIZE(scif4_resources),
112 .dev = { 132 .dev = {
113 .platform_data = &scif4_platform_data, 133 .platform_data = &scif4_platform_data,
114 }, 134 },
115}; 135};
116 136
117static struct plat_sci_port scif5_platform_data = { 137static struct plat_sci_port scif5_platform_data = {
118 .mapbase = 0xFFE43000,
119 .flags = UPF_BOOT_AUTOCONF, 138 .flags = UPF_BOOT_AUTOCONF,
120 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 139 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
121 .scbrr_algo_id = SCBRR_ALGO_2,
122 .type = PORT_SCIF, 140 .type = PORT_SCIF,
123 .irqs = SCIx_IRQ_MUXED(evt2irq(0x960)),
124 .regtype = SCIx_SH4_SCIF_REGTYPE, 141 .regtype = SCIx_SH4_SCIF_REGTYPE,
125}; 142};
126 143
144static struct resource scif5_resources[] = {
145 DEFINE_RES_MEM(0xffe43000, 0x100),
146 DEFINE_RES_IRQ(evt2irq(0x960)),
147};
148
127static struct platform_device scif5_device = { 149static struct platform_device scif5_device = {
128 .name = "sh-sci", 150 .name = "sh-sci",
129 .id = 5, 151 .id = 5,
152 .resource = scif5_resources,
153 .num_resources = ARRAY_SIZE(scif5_resources),
130 .dev = { 154 .dev = {
131 .platform_data = &scif5_platform_data, 155 .platform_data = &scif5_platform_data,
132 }, 156 },
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7757.c b/arch/sh/kernel/cpu/sh4a/setup-sh7757.c
index 9079a0f9ea9b..e43e5db53913 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7757.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7757.c
@@ -24,51 +24,63 @@
24#include <cpu/sh7757.h> 24#include <cpu/sh7757.h>
25 25
26static struct plat_sci_port scif2_platform_data = { 26static struct plat_sci_port scif2_platform_data = {
27 .mapbase = 0xfe4b0000, /* SCIF2 */
28 .flags = UPF_BOOT_AUTOCONF, 27 .flags = UPF_BOOT_AUTOCONF,
29 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 28 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
30 .scbrr_algo_id = SCBRR_ALGO_2,
31 .type = PORT_SCIF, 29 .type = PORT_SCIF,
32 .irqs = SCIx_IRQ_MUXED(evt2irq(0x700)), 30};
31
32static struct resource scif2_resources[] = {
33 DEFINE_RES_MEM(0xfe4b0000, 0x100), /* SCIF2 */
34 DEFINE_RES_IRQ(evt2irq(0x700)),
33}; 35};
34 36
35static struct platform_device scif2_device = { 37static struct platform_device scif2_device = {
36 .name = "sh-sci", 38 .name = "sh-sci",
37 .id = 0, 39 .id = 0,
40 .resource = scif2_resources,
41 .num_resources = ARRAY_SIZE(scif2_resources),
38 .dev = { 42 .dev = {
39 .platform_data = &scif2_platform_data, 43 .platform_data = &scif2_platform_data,
40 }, 44 },
41}; 45};
42 46
43static struct plat_sci_port scif3_platform_data = { 47static struct plat_sci_port scif3_platform_data = {
44 .mapbase = 0xfe4c0000, /* SCIF3 */
45 .flags = UPF_BOOT_AUTOCONF, 48 .flags = UPF_BOOT_AUTOCONF,
46 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 49 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
47 .scbrr_algo_id = SCBRR_ALGO_2,
48 .type = PORT_SCIF, 50 .type = PORT_SCIF,
49 .irqs = SCIx_IRQ_MUXED(evt2irq(0xb80)), 51};
52
53static struct resource scif3_resources[] = {
54 DEFINE_RES_MEM(0xfe4c0000, 0x100), /* SCIF3 */
55 DEFINE_RES_IRQ(evt2irq(0xb80)),
50}; 56};
51 57
52static struct platform_device scif3_device = { 58static struct platform_device scif3_device = {
53 .name = "sh-sci", 59 .name = "sh-sci",
54 .id = 1, 60 .id = 1,
61 .resource = scif3_resources,
62 .num_resources = ARRAY_SIZE(scif3_resources),
55 .dev = { 63 .dev = {
56 .platform_data = &scif3_platform_data, 64 .platform_data = &scif3_platform_data,
57 }, 65 },
58}; 66};
59 67
60static struct plat_sci_port scif4_platform_data = { 68static struct plat_sci_port scif4_platform_data = {
61 .mapbase = 0xfe4d0000, /* SCIF4 */
62 .flags = UPF_BOOT_AUTOCONF, 69 .flags = UPF_BOOT_AUTOCONF,
63 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 70 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
64 .scbrr_algo_id = SCBRR_ALGO_2,
65 .type = PORT_SCIF, 71 .type = PORT_SCIF,
66 .irqs = SCIx_IRQ_MUXED(evt2irq(0xF00)), 72};
73
74static struct resource scif4_resources[] = {
75 DEFINE_RES_MEM(0xfe4d0000, 0x100), /* SCIF4 */
76 DEFINE_RES_IRQ(evt2irq(0xf00)),
67}; 77};
68 78
69static struct platform_device scif4_device = { 79static struct platform_device scif4_device = {
70 .name = "sh-sci", 80 .name = "sh-sci",
71 .id = 2, 81 .id = 2,
82 .resource = scif4_resources,
83 .num_resources = ARRAY_SIZE(scif4_resources),
72 .dev = { 84 .dev = {
73 .platform_data = &scif4_platform_data, 85 .platform_data = &scif4_platform_data,
74 }, 86 },
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7763.c b/arch/sh/kernel/cpu/sh4a/setup-sh7763.c
index 1686acaaf45a..5eebbd7f4c21 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7763.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7763.c
@@ -19,54 +19,66 @@
19#include <linux/usb/ohci_pdriver.h> 19#include <linux/usb/ohci_pdriver.h>
20 20
21static struct plat_sci_port scif0_platform_data = { 21static struct plat_sci_port scif0_platform_data = {
22 .mapbase = 0xffe00000,
23 .flags = UPF_BOOT_AUTOCONF, 22 .flags = UPF_BOOT_AUTOCONF,
24 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 23 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
25 .scbrr_algo_id = SCBRR_ALGO_2,
26 .type = PORT_SCIF, 24 .type = PORT_SCIF,
27 .irqs = SCIx_IRQ_MUXED(evt2irq(0x700)),
28 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, 25 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
29}; 26};
30 27
28static struct resource scif0_resources[] = {
29 DEFINE_RES_MEM(0xffe00000, 0x100),
30 DEFINE_RES_IRQ(evt2irq(0x700)),
31};
32
31static struct platform_device scif0_device = { 33static struct platform_device scif0_device = {
32 .name = "sh-sci", 34 .name = "sh-sci",
33 .id = 0, 35 .id = 0,
36 .resource = scif0_resources,
37 .num_resources = ARRAY_SIZE(scif0_resources),
34 .dev = { 38 .dev = {
35 .platform_data = &scif0_platform_data, 39 .platform_data = &scif0_platform_data,
36 }, 40 },
37}; 41};
38 42
39static struct plat_sci_port scif1_platform_data = { 43static struct plat_sci_port scif1_platform_data = {
40 .mapbase = 0xffe08000,
41 .flags = UPF_BOOT_AUTOCONF, 44 .flags = UPF_BOOT_AUTOCONF,
42 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 45 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
43 .scbrr_algo_id = SCBRR_ALGO_2,
44 .type = PORT_SCIF, 46 .type = PORT_SCIF,
45 .irqs = SCIx_IRQ_MUXED(evt2irq(0xb80)),
46 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, 47 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
47}; 48};
48 49
50static struct resource scif1_resources[] = {
51 DEFINE_RES_MEM(0xffe08000, 0x100),
52 DEFINE_RES_IRQ(evt2irq(0xb80)),
53};
54
49static struct platform_device scif1_device = { 55static struct platform_device scif1_device = {
50 .name = "sh-sci", 56 .name = "sh-sci",
51 .id = 1, 57 .id = 1,
58 .resource = scif1_resources,
59 .num_resources = ARRAY_SIZE(scif1_resources),
52 .dev = { 60 .dev = {
53 .platform_data = &scif1_platform_data, 61 .platform_data = &scif1_platform_data,
54 }, 62 },
55}; 63};
56 64
57static struct plat_sci_port scif2_platform_data = { 65static struct plat_sci_port scif2_platform_data = {
58 .mapbase = 0xffe10000,
59 .flags = UPF_BOOT_AUTOCONF, 66 .flags = UPF_BOOT_AUTOCONF,
60 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 67 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
61 .scbrr_algo_id = SCBRR_ALGO_2,
62 .type = PORT_SCIF, 68 .type = PORT_SCIF,
63 .irqs = SCIx_IRQ_MUXED(evt2irq(0xf00)),
64 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, 69 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
65}; 70};
66 71
72static struct resource scif2_resources[] = {
73 DEFINE_RES_MEM(0xffe10000, 0x100),
74 DEFINE_RES_IRQ(evt2irq(0xf00)),
75};
76
67static struct platform_device scif2_device = { 77static struct platform_device scif2_device = {
68 .name = "sh-sci", 78 .name = "sh-sci",
69 .id = 2, 79 .id = 2,
80 .resource = scif2_resources,
81 .num_resources = ARRAY_SIZE(scif2_resources),
70 .dev = { 82 .dev = {
71 .platform_data = &scif2_platform_data, 83 .platform_data = &scif2_platform_data,
72 }, 84 },
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7770.c b/arch/sh/kernel/cpu/sh4a/setup-sh7770.c
index 256ea7a45164..e1ba8cb74e5a 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7770.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7770.c
@@ -16,170 +16,210 @@
16#include <linux/io.h> 16#include <linux/io.h>
17 17
18static struct plat_sci_port scif0_platform_data = { 18static struct plat_sci_port scif0_platform_data = {
19 .mapbase = 0xff923000,
20 .flags = UPF_BOOT_AUTOCONF, 19 .flags = UPF_BOOT_AUTOCONF,
21 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, 20 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
22 .scbrr_algo_id = SCBRR_ALGO_2,
23 .type = PORT_SCIF, 21 .type = PORT_SCIF,
24 .irqs = SCIx_IRQ_MUXED(evt2irq(0x9a0)), 22};
23
24static struct resource scif0_resources[] = {
25 DEFINE_RES_MEM(0xff923000, 0x100),
26 DEFINE_RES_IRQ(evt2irq(0x9a0)),
25}; 27};
26 28
27static struct platform_device scif0_device = { 29static struct platform_device scif0_device = {
28 .name = "sh-sci", 30 .name = "sh-sci",
29 .id = 0, 31 .id = 0,
32 .resource = scif0_resources,
33 .num_resources = ARRAY_SIZE(scif0_resources),
30 .dev = { 34 .dev = {
31 .platform_data = &scif0_platform_data, 35 .platform_data = &scif0_platform_data,
32 }, 36 },
33}; 37};
34 38
35static struct plat_sci_port scif1_platform_data = { 39static struct plat_sci_port scif1_platform_data = {
36 .mapbase = 0xff924000,
37 .flags = UPF_BOOT_AUTOCONF, 40 .flags = UPF_BOOT_AUTOCONF,
38 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, 41 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
39 .scbrr_algo_id = SCBRR_ALGO_2,
40 .type = PORT_SCIF, 42 .type = PORT_SCIF,
41 .irqs = SCIx_IRQ_MUXED(evt2irq(0x9c0)), 43};
44
45static struct resource scif1_resources[] = {
46 DEFINE_RES_MEM(0xff924000, 0x100),
47 DEFINE_RES_IRQ(evt2irq(0x9c0)),
42}; 48};
43 49
44static struct platform_device scif1_device = { 50static struct platform_device scif1_device = {
45 .name = "sh-sci", 51 .name = "sh-sci",
46 .id = 1, 52 .id = 1,
53 .resource = scif1_resources,
54 .num_resources = ARRAY_SIZE(scif1_resources),
47 .dev = { 55 .dev = {
48 .platform_data = &scif1_platform_data, 56 .platform_data = &scif1_platform_data,
49 }, 57 },
50}; 58};
51 59
52static struct plat_sci_port scif2_platform_data = { 60static struct plat_sci_port scif2_platform_data = {
53 .mapbase = 0xff925000,
54 .flags = UPF_BOOT_AUTOCONF, 61 .flags = UPF_BOOT_AUTOCONF,
55 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, 62 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
56 .scbrr_algo_id = SCBRR_ALGO_2,
57 .type = PORT_SCIF, 63 .type = PORT_SCIF,
58 .irqs = SCIx_IRQ_MUXED(evt2irq(0x9e0)), 64};
65
66static struct resource scif2_resources[] = {
67 DEFINE_RES_MEM(0xff925000, 0x100),
68 DEFINE_RES_IRQ(evt2irq(0x9e0)),
59}; 69};
60 70
61static struct platform_device scif2_device = { 71static struct platform_device scif2_device = {
62 .name = "sh-sci", 72 .name = "sh-sci",
63 .id = 2, 73 .id = 2,
74 .resource = scif2_resources,
75 .num_resources = ARRAY_SIZE(scif2_resources),
64 .dev = { 76 .dev = {
65 .platform_data = &scif2_platform_data, 77 .platform_data = &scif2_platform_data,
66 }, 78 },
67}; 79};
68 80
69static struct plat_sci_port scif3_platform_data = { 81static struct plat_sci_port scif3_platform_data = {
70 .mapbase = 0xff926000,
71 .flags = UPF_BOOT_AUTOCONF, 82 .flags = UPF_BOOT_AUTOCONF,
72 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, 83 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
73 .scbrr_algo_id = SCBRR_ALGO_2,
74 .type = PORT_SCIF, 84 .type = PORT_SCIF,
75 .irqs = SCIx_IRQ_MUXED(evt2irq(0xa00)), 85};
86
87static struct resource scif3_resources[] = {
88 DEFINE_RES_MEM(0xff926000, 0x100),
89 DEFINE_RES_IRQ(evt2irq(0xa00)),
76}; 90};
77 91
78static struct platform_device scif3_device = { 92static struct platform_device scif3_device = {
79 .name = "sh-sci", 93 .name = "sh-sci",
80 .id = 3, 94 .id = 3,
95 .resource = scif3_resources,
96 .num_resources = ARRAY_SIZE(scif3_resources),
81 .dev = { 97 .dev = {
82 .platform_data = &scif3_platform_data, 98 .platform_data = &scif3_platform_data,
83 }, 99 },
84}; 100};
85 101
86static struct plat_sci_port scif4_platform_data = { 102static struct plat_sci_port scif4_platform_data = {
87 .mapbase = 0xff927000,
88 .flags = UPF_BOOT_AUTOCONF, 103 .flags = UPF_BOOT_AUTOCONF,
89 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, 104 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
90 .scbrr_algo_id = SCBRR_ALGO_2,
91 .type = PORT_SCIF, 105 .type = PORT_SCIF,
92 .irqs = SCIx_IRQ_MUXED(evt2irq(0xa20)), 106};
107
108static struct resource scif4_resources[] = {
109 DEFINE_RES_MEM(0xff927000, 0x100),
110 DEFINE_RES_IRQ(evt2irq(0xa20)),
93}; 111};
94 112
95static struct platform_device scif4_device = { 113static struct platform_device scif4_device = {
96 .name = "sh-sci", 114 .name = "sh-sci",
97 .id = 4, 115 .id = 4,
116 .resource = scif4_resources,
117 .num_resources = ARRAY_SIZE(scif4_resources),
98 .dev = { 118 .dev = {
99 .platform_data = &scif4_platform_data, 119 .platform_data = &scif4_platform_data,
100 }, 120 },
101}; 121};
102 122
103static struct plat_sci_port scif5_platform_data = { 123static struct plat_sci_port scif5_platform_data = {
104 .mapbase = 0xff928000,
105 .flags = UPF_BOOT_AUTOCONF, 124 .flags = UPF_BOOT_AUTOCONF,
106 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, 125 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
107 .scbrr_algo_id = SCBRR_ALGO_2,
108 .type = PORT_SCIF, 126 .type = PORT_SCIF,
109 .irqs = SCIx_IRQ_MUXED(evt2irq(0xa40)), 127};
128
129static struct resource scif5_resources[] = {
130 DEFINE_RES_MEM(0xff928000, 0x100),
131 DEFINE_RES_IRQ(evt2irq(0xa40)),
110}; 132};
111 133
112static struct platform_device scif5_device = { 134static struct platform_device scif5_device = {
113 .name = "sh-sci", 135 .name = "sh-sci",
114 .id = 5, 136 .id = 5,
137 .resource = scif5_resources,
138 .num_resources = ARRAY_SIZE(scif5_resources),
115 .dev = { 139 .dev = {
116 .platform_data = &scif5_platform_data, 140 .platform_data = &scif5_platform_data,
117 }, 141 },
118}; 142};
119 143
120static struct plat_sci_port scif6_platform_data = { 144static struct plat_sci_port scif6_platform_data = {
121 .mapbase = 0xff929000,
122 .flags = UPF_BOOT_AUTOCONF, 145 .flags = UPF_BOOT_AUTOCONF,
123 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, 146 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
124 .scbrr_algo_id = SCBRR_ALGO_2,
125 .type = PORT_SCIF, 147 .type = PORT_SCIF,
126 .irqs = SCIx_IRQ_MUXED(evt2irq(0xa60)), 148};
149
150static struct resource scif6_resources[] = {
151 DEFINE_RES_MEM(0xff929000, 0x100),
152 DEFINE_RES_IRQ(evt2irq(0xa60)),
127}; 153};
128 154
129static struct platform_device scif6_device = { 155static struct platform_device scif6_device = {
130 .name = "sh-sci", 156 .name = "sh-sci",
131 .id = 6, 157 .id = 6,
158 .resource = scif6_resources,
159 .num_resources = ARRAY_SIZE(scif6_resources),
132 .dev = { 160 .dev = {
133 .platform_data = &scif6_platform_data, 161 .platform_data = &scif6_platform_data,
134 }, 162 },
135}; 163};
136 164
137static struct plat_sci_port scif7_platform_data = { 165static struct plat_sci_port scif7_platform_data = {
138 .mapbase = 0xff92a000,
139 .flags = UPF_BOOT_AUTOCONF, 166 .flags = UPF_BOOT_AUTOCONF,
140 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, 167 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
141 .scbrr_algo_id = SCBRR_ALGO_2,
142 .type = PORT_SCIF, 168 .type = PORT_SCIF,
143 .irqs = SCIx_IRQ_MUXED(evt2irq(0xa80)), 169};
170
171static struct resource scif7_resources[] = {
172 DEFINE_RES_MEM(0xff92a000, 0x100),
173 DEFINE_RES_IRQ(evt2irq(0xa80)),
144}; 174};
145 175
146static struct platform_device scif7_device = { 176static struct platform_device scif7_device = {
147 .name = "sh-sci", 177 .name = "sh-sci",
148 .id = 7, 178 .id = 7,
179 .resource = scif7_resources,
180 .num_resources = ARRAY_SIZE(scif7_resources),
149 .dev = { 181 .dev = {
150 .platform_data = &scif7_platform_data, 182 .platform_data = &scif7_platform_data,
151 }, 183 },
152}; 184};
153 185
154static struct plat_sci_port scif8_platform_data = { 186static struct plat_sci_port scif8_platform_data = {
155 .mapbase = 0xff92b000,
156 .flags = UPF_BOOT_AUTOCONF, 187 .flags = UPF_BOOT_AUTOCONF,
157 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, 188 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
158 .scbrr_algo_id = SCBRR_ALGO_2,
159 .type = PORT_SCIF, 189 .type = PORT_SCIF,
160 .irqs = SCIx_IRQ_MUXED(evt2irq(0xaa0)), 190};
191
192static struct resource scif8_resources[] = {
193 DEFINE_RES_MEM(0xff92b000, 0x100),
194 DEFINE_RES_IRQ(evt2irq(0xaa0)),
161}; 195};
162 196
163static struct platform_device scif8_device = { 197static struct platform_device scif8_device = {
164 .name = "sh-sci", 198 .name = "sh-sci",
165 .id = 8, 199 .id = 8,
200 .resource = scif8_resources,
201 .num_resources = ARRAY_SIZE(scif8_resources),
166 .dev = { 202 .dev = {
167 .platform_data = &scif8_platform_data, 203 .platform_data = &scif8_platform_data,
168 }, 204 },
169}; 205};
170 206
171static struct plat_sci_port scif9_platform_data = { 207static struct plat_sci_port scif9_platform_data = {
172 .mapbase = 0xff92c000,
173 .flags = UPF_BOOT_AUTOCONF, 208 .flags = UPF_BOOT_AUTOCONF,
174 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, 209 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
175 .scbrr_algo_id = SCBRR_ALGO_2,
176 .type = PORT_SCIF, 210 .type = PORT_SCIF,
177 .irqs = SCIx_IRQ_MUXED(evt2irq(0xac0)), 211};
212
213static struct resource scif9_resources[] = {
214 DEFINE_RES_MEM(0xff92c000, 0x100),
215 DEFINE_RES_IRQ(evt2irq(0xac0)),
178}; 216};
179 217
180static struct platform_device scif9_device = { 218static struct platform_device scif9_device = {
181 .name = "sh-sci", 219 .name = "sh-sci",
182 .id = 9, 220 .id = 9,
221 .resource = scif9_resources,
222 .num_resources = ARRAY_SIZE(scif9_resources),
183 .dev = { 223 .dev = {
184 .platform_data = &scif9_platform_data, 224 .platform_data = &scif9_platform_data,
185 }, 225 },
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7780.c b/arch/sh/kernel/cpu/sh4a/setup-sh7780.c
index de45b704687a..668e54bafa86 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7780.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7780.c
@@ -18,36 +18,44 @@
18#include <cpu/dma-register.h> 18#include <cpu/dma-register.h>
19 19
20static struct plat_sci_port scif0_platform_data = { 20static struct plat_sci_port scif0_platform_data = {
21 .mapbase = 0xffe00000,
22 .flags = UPF_BOOT_AUTOCONF, 21 .flags = UPF_BOOT_AUTOCONF,
23 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, 22 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
24 .scbrr_algo_id = SCBRR_ALGO_1,
25 .type = PORT_SCIF, 23 .type = PORT_SCIF,
26 .irqs = SCIx_IRQ_MUXED(evt2irq(0x700)),
27 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, 24 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
28}; 25};
29 26
27static struct resource scif0_resources[] = {
28 DEFINE_RES_MEM(0xffe00000, 0x100),
29 DEFINE_RES_IRQ(evt2irq(0x700)),
30};
31
30static struct platform_device scif0_device = { 32static struct platform_device scif0_device = {
31 .name = "sh-sci", 33 .name = "sh-sci",
32 .id = 0, 34 .id = 0,
35 .resource = scif0_resources,
36 .num_resources = ARRAY_SIZE(scif0_resources),
33 .dev = { 37 .dev = {
34 .platform_data = &scif0_platform_data, 38 .platform_data = &scif0_platform_data,
35 }, 39 },
36}; 40};
37 41
38static struct plat_sci_port scif1_platform_data = { 42static struct plat_sci_port scif1_platform_data = {
39 .mapbase = 0xffe10000,
40 .flags = UPF_BOOT_AUTOCONF, 43 .flags = UPF_BOOT_AUTOCONF,
41 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, 44 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
42 .scbrr_algo_id = SCBRR_ALGO_1,
43 .type = PORT_SCIF, 45 .type = PORT_SCIF,
44 .irqs = SCIx_IRQ_MUXED(evt2irq(0xb80)),
45 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, 46 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
46}; 47};
47 48
49static struct resource scif1_resources[] = {
50 DEFINE_RES_MEM(0xffe10000, 0x100),
51 DEFINE_RES_IRQ(evt2irq(0xb80)),
52};
53
48static struct platform_device scif1_device = { 54static struct platform_device scif1_device = {
49 .name = "sh-sci", 55 .name = "sh-sci",
50 .id = 1, 56 .id = 1,
57 .resource = scif1_resources,
58 .num_resources = ARRAY_SIZE(scif1_resources),
51 .dev = { 59 .dev = {
52 .platform_data = &scif1_platform_data, 60 .platform_data = &scif1_platform_data,
53 }, 61 },
@@ -409,9 +417,7 @@ void __init plat_early_device_setup(void)
409{ 417{
410 if (mach_is_sh2007()) { 418 if (mach_is_sh2007()) {
411 scif0_platform_data.scscr &= ~SCSCR_CKE1; 419 scif0_platform_data.scscr &= ~SCSCR_CKE1;
412 scif0_platform_data.scbrr_algo_id = SCBRR_ALGO_2;
413 scif1_platform_data.scscr &= ~SCSCR_CKE1; 420 scif1_platform_data.scscr &= ~SCSCR_CKE1;
414 scif1_platform_data.scbrr_algo_id = SCBRR_ALGO_2;
415 } 421 }
416 422
417 early_platform_add_devices(sh7780_early_devices, 423 early_platform_add_devices(sh7780_early_devices,
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7785.c b/arch/sh/kernel/cpu/sh4a/setup-sh7785.c
index 0968ecb962e6..4aa679140209 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7785.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7785.c
@@ -20,108 +20,132 @@
20#include <cpu/dma-register.h> 20#include <cpu/dma-register.h>
21 21
22static struct plat_sci_port scif0_platform_data = { 22static struct plat_sci_port scif0_platform_data = {
23 .mapbase = 0xffea0000,
24 .flags = UPF_BOOT_AUTOCONF, 23 .flags = UPF_BOOT_AUTOCONF,
25 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, 24 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
26 .scbrr_algo_id = SCBRR_ALGO_1,
27 .type = PORT_SCIF, 25 .type = PORT_SCIF,
28 .irqs = SCIx_IRQ_MUXED(evt2irq(0x700)),
29 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, 26 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
30}; 27};
31 28
29static struct resource scif0_resources[] = {
30 DEFINE_RES_MEM(0xffea0000, 0x100),
31 DEFINE_RES_IRQ(evt2irq(0x700)),
32};
33
32static struct platform_device scif0_device = { 34static struct platform_device scif0_device = {
33 .name = "sh-sci", 35 .name = "sh-sci",
34 .id = 0, 36 .id = 0,
37 .resource = scif0_resources,
38 .num_resources = ARRAY_SIZE(scif0_resources),
35 .dev = { 39 .dev = {
36 .platform_data = &scif0_platform_data, 40 .platform_data = &scif0_platform_data,
37 }, 41 },
38}; 42};
39 43
40static struct plat_sci_port scif1_platform_data = { 44static struct plat_sci_port scif1_platform_data = {
41 .mapbase = 0xffeb0000,
42 .flags = UPF_BOOT_AUTOCONF, 45 .flags = UPF_BOOT_AUTOCONF,
43 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, 46 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
44 .scbrr_algo_id = SCBRR_ALGO_1,
45 .type = PORT_SCIF, 47 .type = PORT_SCIF,
46 .irqs = SCIx_IRQ_MUXED(evt2irq(0x780)),
47 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, 48 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
48}; 49};
49 50
51static struct resource scif1_resources[] = {
52 DEFINE_RES_MEM(0xffeb0000, 0x100),
53 DEFINE_RES_IRQ(evt2irq(0x780)),
54};
55
50static struct platform_device scif1_device = { 56static struct platform_device scif1_device = {
51 .name = "sh-sci", 57 .name = "sh-sci",
52 .id = 1, 58 .id = 1,
59 .resource = scif1_resources,
60 .num_resources = ARRAY_SIZE(scif1_resources),
53 .dev = { 61 .dev = {
54 .platform_data = &scif1_platform_data, 62 .platform_data = &scif1_platform_data,
55 }, 63 },
56}; 64};
57 65
58static struct plat_sci_port scif2_platform_data = { 66static struct plat_sci_port scif2_platform_data = {
59 .mapbase = 0xffec0000,
60 .flags = UPF_BOOT_AUTOCONF, 67 .flags = UPF_BOOT_AUTOCONF,
61 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, 68 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
62 .scbrr_algo_id = SCBRR_ALGO_1,
63 .type = PORT_SCIF, 69 .type = PORT_SCIF,
64 .irqs = SCIx_IRQ_MUXED(evt2irq(0x980)),
65 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, 70 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
66}; 71};
67 72
73static struct resource scif2_resources[] = {
74 DEFINE_RES_MEM(0xffec0000, 0x100),
75 DEFINE_RES_IRQ(evt2irq(0x980)),
76};
77
68static struct platform_device scif2_device = { 78static struct platform_device scif2_device = {
69 .name = "sh-sci", 79 .name = "sh-sci",
70 .id = 2, 80 .id = 2,
81 .resource = scif2_resources,
82 .num_resources = ARRAY_SIZE(scif2_resources),
71 .dev = { 83 .dev = {
72 .platform_data = &scif2_platform_data, 84 .platform_data = &scif2_platform_data,
73 }, 85 },
74}; 86};
75 87
76static struct plat_sci_port scif3_platform_data = { 88static struct plat_sci_port scif3_platform_data = {
77 .mapbase = 0xffed0000,
78 .flags = UPF_BOOT_AUTOCONF, 89 .flags = UPF_BOOT_AUTOCONF,
79 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, 90 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
80 .scbrr_algo_id = SCBRR_ALGO_1,
81 .type = PORT_SCIF, 91 .type = PORT_SCIF,
82 .irqs = SCIx_IRQ_MUXED(evt2irq(0x9a0)),
83 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, 92 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
84}; 93};
85 94
95static struct resource scif3_resources[] = {
96 DEFINE_RES_MEM(0xffed0000, 0x100),
97 DEFINE_RES_IRQ(evt2irq(0x9a0)),
98};
99
86static struct platform_device scif3_device = { 100static struct platform_device scif3_device = {
87 .name = "sh-sci", 101 .name = "sh-sci",
88 .id = 3, 102 .id = 3,
103 .resource = scif3_resources,
104 .num_resources = ARRAY_SIZE(scif3_resources),
89 .dev = { 105 .dev = {
90 .platform_data = &scif3_platform_data, 106 .platform_data = &scif3_platform_data,
91 }, 107 },
92}; 108};
93 109
94static struct plat_sci_port scif4_platform_data = { 110static struct plat_sci_port scif4_platform_data = {
95 .mapbase = 0xffee0000,
96 .flags = UPF_BOOT_AUTOCONF, 111 .flags = UPF_BOOT_AUTOCONF,
97 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, 112 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
98 .scbrr_algo_id = SCBRR_ALGO_1,
99 .type = PORT_SCIF, 113 .type = PORT_SCIF,
100 .irqs = SCIx_IRQ_MUXED(evt2irq(0x9c0)),
101 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, 114 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
102}; 115};
103 116
117static struct resource scif4_resources[] = {
118 DEFINE_RES_MEM(0xffee0000, 0x100),
119 DEFINE_RES_IRQ(evt2irq(0x9c0)),
120};
121
104static struct platform_device scif4_device = { 122static struct platform_device scif4_device = {
105 .name = "sh-sci", 123 .name = "sh-sci",
106 .id = 4, 124 .id = 4,
125 .resource = scif4_resources,
126 .num_resources = ARRAY_SIZE(scif4_resources),
107 .dev = { 127 .dev = {
108 .platform_data = &scif4_platform_data, 128 .platform_data = &scif4_platform_data,
109 }, 129 },
110}; 130};
111 131
112static struct plat_sci_port scif5_platform_data = { 132static struct plat_sci_port scif5_platform_data = {
113 .mapbase = 0xffef0000,
114 .flags = UPF_BOOT_AUTOCONF, 133 .flags = UPF_BOOT_AUTOCONF,
115 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, 134 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
116 .scbrr_algo_id = SCBRR_ALGO_1,
117 .type = PORT_SCIF, 135 .type = PORT_SCIF,
118 .irqs = SCIx_IRQ_MUXED(evt2irq(0x9e0)),
119 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, 136 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
120}; 137};
121 138
139static struct resource scif5_resources[] = {
140 DEFINE_RES_MEM(0xffef0000, 0x100),
141 DEFINE_RES_IRQ(evt2irq(0x9e0)),
142};
143
122static struct platform_device scif5_device = { 144static struct platform_device scif5_device = {
123 .name = "sh-sci", 145 .name = "sh-sci",
124 .id = 5, 146 .id = 5,
147 .resource = scif5_resources,
148 .num_resources = ARRAY_SIZE(scif5_resources),
125 .dev = { 149 .dev = {
126 .platform_data = &scif5_platform_data, 150 .platform_data = &scif5_platform_data,
127 }, 151 },
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7786.c b/arch/sh/kernel/cpu/sh4a/setup-sh7786.c
index ab52d4d4484d..5d619a551a3b 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7786.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7786.c
@@ -28,21 +28,25 @@
28#include <asm/mmzone.h> 28#include <asm/mmzone.h>
29 29
30static struct plat_sci_port scif0_platform_data = { 30static struct plat_sci_port scif0_platform_data = {
31 .mapbase = 0xffea0000,
32 .flags = UPF_BOOT_AUTOCONF, 31 .flags = UPF_BOOT_AUTOCONF,
33 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, 32 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
34 .scbrr_algo_id = SCBRR_ALGO_1,
35 .type = PORT_SCIF, 33 .type = PORT_SCIF,
36 .irqs = { evt2irq(0x700),
37 evt2irq(0x720),
38 evt2irq(0x760),
39 evt2irq(0x740) },
40 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, 34 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
41}; 35};
42 36
37static struct resource scif0_resources[] = {
38 DEFINE_RES_MEM(0xffea0000, 0x100),
39 DEFINE_RES_IRQ(evt2irq(0x700)),
40 DEFINE_RES_IRQ(evt2irq(0x720)),
41 DEFINE_RES_IRQ(evt2irq(0x760)),
42 DEFINE_RES_IRQ(evt2irq(0x740)),
43};
44
43static struct platform_device scif0_device = { 45static struct platform_device scif0_device = {
44 .name = "sh-sci", 46 .name = "sh-sci",
45 .id = 0, 47 .id = 0,
48 .resource = scif0_resources,
49 .num_resources = ARRAY_SIZE(scif0_resources),
46 .dev = { 50 .dev = {
47 .platform_data = &scif0_platform_data, 51 .platform_data = &scif0_platform_data,
48 }, 52 },
@@ -52,90 +56,119 @@ static struct platform_device scif0_device = {
52 * The rest of these all have multiplexed IRQs 56 * The rest of these all have multiplexed IRQs
53 */ 57 */
54static struct plat_sci_port scif1_platform_data = { 58static struct plat_sci_port scif1_platform_data = {
55 .mapbase = 0xffeb0000,
56 .flags = UPF_BOOT_AUTOCONF, 59 .flags = UPF_BOOT_AUTOCONF,
57 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, 60 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
58 .scbrr_algo_id = SCBRR_ALGO_1,
59 .type = PORT_SCIF, 61 .type = PORT_SCIF,
60 .irqs = SCIx_IRQ_MUXED(evt2irq(0x780)),
61 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, 62 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
62}; 63};
63 64
65static struct resource scif1_resources[] = {
66 DEFINE_RES_MEM(0xffeb0000, 0x100),
67 DEFINE_RES_IRQ(evt2irq(0x780)),
68};
69
70static struct resource scif1_demux_resources[] = {
71 DEFINE_RES_MEM(0xffeb0000, 0x100),
72 /* Placeholders, see sh7786_devices_setup() */
73 DEFINE_RES_IRQ(0),
74 DEFINE_RES_IRQ(0),
75 DEFINE_RES_IRQ(0),
76 DEFINE_RES_IRQ(0),
77};
78
64static struct platform_device scif1_device = { 79static struct platform_device scif1_device = {
65 .name = "sh-sci", 80 .name = "sh-sci",
66 .id = 1, 81 .id = 1,
82 .resource = scif1_resources,
83 .num_resources = ARRAY_SIZE(scif1_resources),
67 .dev = { 84 .dev = {
68 .platform_data = &scif1_platform_data, 85 .platform_data = &scif1_platform_data,
69 }, 86 },
70}; 87};
71 88
72static struct plat_sci_port scif2_platform_data = { 89static struct plat_sci_port scif2_platform_data = {
73 .mapbase = 0xffec0000,
74 .flags = UPF_BOOT_AUTOCONF, 90 .flags = UPF_BOOT_AUTOCONF,
75 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, 91 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
76 .scbrr_algo_id = SCBRR_ALGO_1,
77 .type = PORT_SCIF, 92 .type = PORT_SCIF,
78 .irqs = SCIx_IRQ_MUXED(evt2irq(0x840)),
79 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, 93 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
80}; 94};
81 95
96static struct resource scif2_resources[] = {
97 DEFINE_RES_MEM(0xffec0000, 0x100),
98 DEFINE_RES_IRQ(evt2irq(0x840)),
99};
100
82static struct platform_device scif2_device = { 101static struct platform_device scif2_device = {
83 .name = "sh-sci", 102 .name = "sh-sci",
84 .id = 2, 103 .id = 2,
104 .resource = scif2_resources,
105 .num_resources = ARRAY_SIZE(scif2_resources),
85 .dev = { 106 .dev = {
86 .platform_data = &scif2_platform_data, 107 .platform_data = &scif2_platform_data,
87 }, 108 },
88}; 109};
89 110
90static struct plat_sci_port scif3_platform_data = { 111static struct plat_sci_port scif3_platform_data = {
91 .mapbase = 0xffed0000,
92 .flags = UPF_BOOT_AUTOCONF, 112 .flags = UPF_BOOT_AUTOCONF,
93 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, 113 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
94 .scbrr_algo_id = SCBRR_ALGO_1,
95 .type = PORT_SCIF, 114 .type = PORT_SCIF,
96 .irqs = SCIx_IRQ_MUXED(evt2irq(0x860)),
97 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, 115 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
98}; 116};
99 117
118static struct resource scif3_resources[] = {
119 DEFINE_RES_MEM(0xffed0000, 0x100),
120 DEFINE_RES_IRQ(evt2irq(0x860)),
121};
122
100static struct platform_device scif3_device = { 123static struct platform_device scif3_device = {
101 .name = "sh-sci", 124 .name = "sh-sci",
102 .id = 3, 125 .id = 3,
126 .resource = scif3_resources,
127 .num_resources = ARRAY_SIZE(scif3_resources),
103 .dev = { 128 .dev = {
104 .platform_data = &scif3_platform_data, 129 .platform_data = &scif3_platform_data,
105 }, 130 },
106}; 131};
107 132
108static struct plat_sci_port scif4_platform_data = { 133static struct plat_sci_port scif4_platform_data = {
109 .mapbase = 0xffee0000,
110 .flags = UPF_BOOT_AUTOCONF, 134 .flags = UPF_BOOT_AUTOCONF,
111 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, 135 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
112 .scbrr_algo_id = SCBRR_ALGO_1,
113 .type = PORT_SCIF, 136 .type = PORT_SCIF,
114 .irqs = SCIx_IRQ_MUXED(evt2irq(0x880)),
115 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, 137 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
116}; 138};
117 139
140static struct resource scif4_resources[] = {
141 DEFINE_RES_MEM(0xffee0000, 0x100),
142 DEFINE_RES_IRQ(evt2irq(0x880)),
143};
144
118static struct platform_device scif4_device = { 145static struct platform_device scif4_device = {
119 .name = "sh-sci", 146 .name = "sh-sci",
120 .id = 4, 147 .id = 4,
148 .resource = scif4_resources,
149 .num_resources = ARRAY_SIZE(scif4_resources),
121 .dev = { 150 .dev = {
122 .platform_data = &scif4_platform_data, 151 .platform_data = &scif4_platform_data,
123 }, 152 },
124}; 153};
125 154
126static struct plat_sci_port scif5_platform_data = { 155static struct plat_sci_port scif5_platform_data = {
127 .mapbase = 0xffef0000,
128 .flags = UPF_BOOT_AUTOCONF, 156 .flags = UPF_BOOT_AUTOCONF,
129 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, 157 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
130 .scbrr_algo_id = SCBRR_ALGO_1,
131 .type = PORT_SCIF, 158 .type = PORT_SCIF,
132 .irqs = SCIx_IRQ_MUXED(evt2irq(0x8a0)),
133 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, 159 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
134}; 160};
135 161
162static struct resource scif5_resources[] = {
163 DEFINE_RES_MEM(0xffef0000, 0x100),
164 DEFINE_RES_IRQ(evt2irq(0x8a0)),
165};
166
136static struct platform_device scif5_device = { 167static struct platform_device scif5_device = {
137 .name = "sh-sci", 168 .name = "sh-sci",
138 .id = 5, 169 .id = 5,
170 .resource = scif5_resources,
171 .num_resources = ARRAY_SIZE(scif5_resources),
139 .dev = { 172 .dev = {
140 .platform_data = &scif5_platform_data, 173 .platform_data = &scif5_platform_data,
141 }, 174 },
@@ -1037,13 +1070,16 @@ static int __init sh7786_devices_setup(void)
1037 */ 1070 */
1038 irq = intc_irq_lookup(sh7786_intc_desc.name, TXI1); 1071 irq = intc_irq_lookup(sh7786_intc_desc.name, TXI1);
1039 if (irq > 0) { 1072 if (irq > 0) {
1040 scif1_platform_data.irqs[SCIx_TXI_IRQ] = irq; 1073 scif1_demux_resources[1].start =
1041 scif1_platform_data.irqs[SCIx_ERI_IRQ] =
1042 intc_irq_lookup(sh7786_intc_desc.name, ERI1); 1074 intc_irq_lookup(sh7786_intc_desc.name, ERI1);
1043 scif1_platform_data.irqs[SCIx_BRI_IRQ] = 1075 scif1_demux_resources[2].start =
1044 intc_irq_lookup(sh7786_intc_desc.name, BRI1);
1045 scif1_platform_data.irqs[SCIx_RXI_IRQ] =
1046 intc_irq_lookup(sh7786_intc_desc.name, RXI1); 1076 intc_irq_lookup(sh7786_intc_desc.name, RXI1);
1077 scif1_demux_resources[3].start = irq;
1078 scif1_demux_resources[4].start =
1079 intc_irq_lookup(sh7786_intc_desc.name, BRI1);
1080
1081 scif1_device.resource = scif1_demux_resources;
1082 scif1_device.num_resources = ARRAY_SIZE(scif1_demux_resources);
1047 } 1083 }
1048 1084
1049 ret = platform_add_devices(sh7786_early_devices, 1085 ret = platform_add_devices(sh7786_early_devices,
diff --git a/arch/sh/kernel/cpu/sh4a/setup-shx3.c b/arch/sh/kernel/cpu/sh4a/setup-shx3.c
index 688f7ed1bab1..0856bcbb1da0 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-shx3.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-shx3.c
@@ -28,60 +28,72 @@
28 * all rather than adding infrastructure to hack around it. 28 * all rather than adding infrastructure to hack around it.
29 */ 29 */
30static struct plat_sci_port scif0_platform_data = { 30static struct plat_sci_port scif0_platform_data = {
31 .mapbase = 0xffc30000,
32 .flags = UPF_BOOT_AUTOCONF, 31 .flags = UPF_BOOT_AUTOCONF,
33 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 32 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
34 .scbrr_algo_id = SCBRR_ALGO_2,
35 .type = PORT_SCIF, 33 .type = PORT_SCIF,
36 .irqs = { evt2irq(0x700), 34};
37 evt2irq(0x720), 35
38 evt2irq(0x760), 36static struct resource scif0_resources[] = {
39 evt2irq(0x740) }, 37 DEFINE_RES_MEM(0xffc30000, 0x100),
38 DEFINE_RES_IRQ(evt2irq(0x700)),
39 DEFINE_RES_IRQ(evt2irq(0x720)),
40 DEFINE_RES_IRQ(evt2irq(0x760)),
41 DEFINE_RES_IRQ(evt2irq(0x740)),
40}; 42};
41 43
42static struct platform_device scif0_device = { 44static struct platform_device scif0_device = {
43 .name = "sh-sci", 45 .name = "sh-sci",
44 .id = 0, 46 .id = 0,
47 .resource = scif0_resources,
48 .num_resources = ARRAY_SIZE(scif0_resources),
45 .dev = { 49 .dev = {
46 .platform_data = &scif0_platform_data, 50 .platform_data = &scif0_platform_data,
47 }, 51 },
48}; 52};
49 53
50static struct plat_sci_port scif1_platform_data = { 54static struct plat_sci_port scif1_platform_data = {
51 .mapbase = 0xffc40000,
52 .flags = UPF_BOOT_AUTOCONF, 55 .flags = UPF_BOOT_AUTOCONF,
53 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 56 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
54 .scbrr_algo_id = SCBRR_ALGO_2,
55 .type = PORT_SCIF, 57 .type = PORT_SCIF,
56 .irqs = { evt2irq(0x780), 58};
57 evt2irq(0x7a0), 59
58 evt2irq(0x7e0), 60static struct resource scif1_resources[] = {
59 evt2irq(0x7c0) }, 61 DEFINE_RES_MEM(0xffc40000, 0x100),
62 DEFINE_RES_IRQ(evt2irq(0x780)),
63 DEFINE_RES_IRQ(evt2irq(0x7a0)),
64 DEFINE_RES_IRQ(evt2irq(0x7e0)),
65 DEFINE_RES_IRQ(evt2irq(0x7c0)),
60}; 66};
61 67
62static struct platform_device scif1_device = { 68static struct platform_device scif1_device = {
63 .name = "sh-sci", 69 .name = "sh-sci",
64 .id = 1, 70 .id = 1,
71 .resource = scif1_resources,
72 .num_resources = ARRAY_SIZE(scif1_resources),
65 .dev = { 73 .dev = {
66 .platform_data = &scif1_platform_data, 74 .platform_data = &scif1_platform_data,
67 }, 75 },
68}; 76};
69 77
70static struct plat_sci_port scif2_platform_data = { 78static struct plat_sci_port scif2_platform_data = {
71 .mapbase = 0xffc60000,
72 .flags = UPF_BOOT_AUTOCONF, 79 .flags = UPF_BOOT_AUTOCONF,
73 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 80 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
74 .scbrr_algo_id = SCBRR_ALGO_2,
75 .type = PORT_SCIF, 81 .type = PORT_SCIF,
76 .irqs = { evt2irq(0x880), 82};
77 evt2irq(0x8a0), 83
78 evt2irq(0x8e0), 84static struct resource scif2_resources[] = {
79 evt2irq(0x8c0) }, 85 DEFINE_RES_MEM(0xffc60000, 0x100),
86 DEFINE_RES_IRQ(evt2irq(0x880)),
87 DEFINE_RES_IRQ(evt2irq(0x8a0)),
88 DEFINE_RES_IRQ(evt2irq(0x8e0)),
89 DEFINE_RES_IRQ(evt2irq(0x8c0)),
80}; 90};
81 91
82static struct platform_device scif2_device = { 92static struct platform_device scif2_device = {
83 .name = "sh-sci", 93 .name = "sh-sci",
84 .id = 2, 94 .id = 2,
95 .resource = scif2_resources,
96 .num_resources = ARRAY_SIZE(scif2_resources),
85 .dev = { 97 .dev = {
86 .platform_data = &scif2_platform_data, 98 .platform_data = &scif2_platform_data,
87 }, 99 },
diff --git a/arch/sh/kernel/cpu/sh5/setup-sh5.c b/arch/sh/kernel/cpu/sh5/setup-sh5.c
index 18419f1de963..14d68213d16b 100644
--- a/arch/sh/kernel/cpu/sh5/setup-sh5.c
+++ b/arch/sh/kernel/cpu/sh5/setup-sh5.c
@@ -17,17 +17,23 @@
17#include <asm/addrspace.h> 17#include <asm/addrspace.h>
18 18
19static struct plat_sci_port scif0_platform_data = { 19static struct plat_sci_port scif0_platform_data = {
20 .mapbase = PHYS_PERIPHERAL_BLOCK + 0x01030000,
21 .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, 20 .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP,
22 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 21 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
23 .scbrr_algo_id = SCBRR_ALGO_2,
24 .type = PORT_SCIF, 22 .type = PORT_SCIF,
25 .irqs = { 39, 40, 42, 0 }, 23};
24
25static struct resource scif0_resources[] = {
26 DEFINE_RES_MEM(PHYS_PERIPHERAL_BLOCK + 0x01030000, 0x100),
27 DEFINE_RES_IRQ(39),
28 DEFINE_RES_IRQ(40),
29 DEFINE_RES_IRQ(42),
26}; 30};
27 31
28static struct platform_device scif0_device = { 32static struct platform_device scif0_device = {
29 .name = "sh-sci", 33 .name = "sh-sci",
30 .id = 0, 34 .id = 0,
35 .resource = scif0_resources,
36 .num_resources = ARRAY_SIZE(scif0_resources),
31 .dev = { 37 .dev = {
32 .platform_data = &scif0_platform_data, 38 .platform_data = &scif0_platform_data,
33 }, 39 },
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-16 03:58:14 -0400