Merge branch 'l2x0' of rmk tree into prima2-l2x0

13 files changed, 352 insertions, 14 deletions

diff --git a/arch/arm/include/asm/hardware/cache-l2x0.h b/arch/arm/include/asm/hardware/cache-l2x0.h
index bfa706ffd968..434edccdf7f3 100644
--- a/arch/arm/include/asm/hardware/cache-l2x0.h
+++ b/arch/arm/include/asm/hardware/cache-l2x0.h
@@ -45,8 +45,15 @@
 #define L2X0_CLEAN_INV_LINE_PA          0x7F0
 #define L2X0_CLEAN_INV_LINE_IDX         0x7F8
 #define L2X0_CLEAN_INV_WAY              0x7FC
-#define L2X0_LOCKDOWN_WAY_D             0x900
-#define L2X0_LOCKDOWN_WAY_I             0x904
+/*
+ * The lockdown registers repeat 8 times for L310, the L210 has only one
+ * D and one I lockdown register at 0x0900 and 0x0904.
+ */
+#define L2X0_LOCKDOWN_WAY_D_BASE        0x900
+#define L2X0_LOCKDOWN_WAY_I_BASE        0x904
+#define L2X0_LOCKDOWN_STRIDE            0x08
+#define L2X0_ADDR_FILTER_START          0xC00
+#define L2X0_ADDR_FILTER_END            0xC04
 #define L2X0_TEST_OPERATION             0xF00
 #define L2X0_LINE_DATA                  0xF10
 #define L2X0_LINE_TAG                   0xF30
@@ -60,8 +67,23 @@
 #define L2X0_CACHE_ID_PART_MASK         (0xf << 6)
 #define L2X0_CACHE_ID_PART_L210         (1 << 6)
 #define L2X0_CACHE_ID_PART_L310         (3 << 6)
+#define L2X0_CACHE_ID_RTL_MASK          0x3f
+#define L2X0_CACHE_ID_RTL_R0P0          0x0
+#define L2X0_CACHE_ID_RTL_R1P0          0x2
+#define L2X0_CACHE_ID_RTL_R2P0          0x4
+#define L2X0_CACHE_ID_RTL_R3P0          0x5
+#define L2X0_CACHE_ID_RTL_R3P1          0x6
+#define L2X0_CACHE_ID_RTL_R3P2          0x8
 
 #define L2X0_AUX_CTRL_MASK                      0xc0000fff
+#define L2X0_AUX_CTRL_DATA_RD_LATENCY_SHIFT     0
+#define L2X0_AUX_CTRL_DATA_RD_LATENCY_MASK      0x7
+#define L2X0_AUX_CTRL_DATA_WR_LATENCY_SHIFT     3
+#define L2X0_AUX_CTRL_DATA_WR_LATENCY_MASK      (0x7 << 3)
+#define L2X0_AUX_CTRL_TAG_LATENCY_SHIFT         6
+#define L2X0_AUX_CTRL_TAG_LATENCY_MASK          (0x7 << 6)
+#define L2X0_AUX_CTRL_DIRTY_LATENCY_SHIFT       9
+#define L2X0_AUX_CTRL_DIRTY_LATENCY_MASK        (0x7 << 9)
 #define L2X0_AUX_CTRL_ASSOCIATIVITY_SHIFT       16
 #define L2X0_AUX_CTRL_WAY_SIZE_SHIFT            17
 #define L2X0_AUX_CTRL_WAY_SIZE_MASK             (0x7 << 17)
@@ -72,8 +94,33 @@
 #define L2X0_AUX_CTRL_INSTR_PREFETCH_SHIFT      29
 #define L2X0_AUX_CTRL_EARLY_BRESP_SHIFT         30
 
+#define L2X0_LATENCY_CTRL_SETUP_SHIFT   0
+#define L2X0_LATENCY_CTRL_RD_SHIFT      4
+#define L2X0_LATENCY_CTRL_WR_SHIFT      8
+
+#define L2X0_ADDR_FILTER_EN             1
+
 #ifndef __ASSEMBLY__
 extern void __init l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask);
+extern int l2x0_of_init(__u32 aux_val, __u32 aux_mask);
+
+struct l2x0_regs {
+        unsigned long phy_base;
+        unsigned long aux_ctrl;
+        /*
+         * Whether the following registers need to be saved/restored
+         * depends on platform
+         */
+        unsigned long tag_latency;
+        unsigned long data_latency;
+        unsigned long filter_start;
+        unsigned long filter_end;
+        unsigned long prefetch_ctrl;
+        unsigned long pwr_ctrl;
+};
+
+extern struct l2x0_regs l2x0_saved_regs;
+
 #endif
 
 #endif
diff --git a/arch/arm/include/asm/outercache.h b/arch/arm/include/asm/outercache.h
index d8387437ec5a..53426c66352a 100644
--- a/arch/arm/include/asm/outercache.h
+++ b/arch/arm/include/asm/outercache.h
@@ -34,6 +34,7 @@ struct outer_cache_fns {
         void (*sync)(void);
 #endif
         void (*set_debug)(unsigned long);
+        void (*resume)(void);
 };
 
 #ifdef CONFIG_OUTER_CACHE
@@ -74,6 +75,12 @@ static inline void outer_disable(void)
                 outer_cache.disable();
 }
 
+static inline void outer_resume(void)
+{
+        if (outer_cache.resume)
+                outer_cache.resume();
+}
+
 #else
 
 static inline void outer_inv_range(phys_addr_t start, phys_addr_t end)
diff --git a/arch/arm/kernel/asm-offsets.c b/arch/arm/kernel/asm-offsets.c
index 16baba2e4369..1429d8989fb9 100644
--- a/arch/arm/kernel/asm-offsets.c
+++ b/arch/arm/kernel/asm-offsets.c
@@ -20,6 +20,7 @@
 #include <asm/thread_info.h>
 #include <asm/memory.h>
 #include <asm/procinfo.h>
+#include <asm/hardware/cache-l2x0.h>
 #include <linux/kbuild.h>
 
 /*
@@ -92,6 +93,17 @@ int main(void)
   DEFINE(S_OLD_R0,              offsetof(struct pt_regs, ARM_ORIG_r0));
   DEFINE(S_FRAME_SIZE,          sizeof(struct pt_regs));
   BLANK();
+#ifdef CONFIG_CACHE_L2X0
+  DEFINE(L2X0_R_PHY_BASE,       offsetof(struct l2x0_regs, phy_base));
+  DEFINE(L2X0_R_AUX_CTRL,       offsetof(struct l2x0_regs, aux_ctrl));
+  DEFINE(L2X0_R_TAG_LATENCY,    offsetof(struct l2x0_regs, tag_latency));
+  DEFINE(L2X0_R_DATA_LATENCY,   offsetof(struct l2x0_regs, data_latency));
+  DEFINE(L2X0_R_FILTER_START,   offsetof(struct l2x0_regs, filter_start));
+  DEFINE(L2X0_R_FILTER_END,     offsetof(struct l2x0_regs, filter_end));
+  DEFINE(L2X0_R_PREFETCH_CTRL,  offsetof(struct l2x0_regs, prefetch_ctrl));
+  DEFINE(L2X0_R_PWR_CTRL,       offsetof(struct l2x0_regs, pwr_ctrl));
+  BLANK();
+#endif
 #ifdef CONFIG_CPU_HAS_ASID
   DEFINE(MM_CONTEXT_ID,         offsetof(struct mm_struct, context.id));
   BLANK();
diff --git a/arch/arm/mach-integrator/integrator_ap.c b/arch/arm/mach-integrator/integrator_ap.c
index 2fbbdd5eac35..fcf0ae95651f 100644
--- a/arch/arm/mach-integrator/integrator_ap.c
+++ b/arch/arm/mach-integrator/integrator_ap.c
@@ -337,15 +337,15 @@ static unsigned long timer_reload;
 static void integrator_clocksource_init(u32 khz)
 {
         void __iomem *base = (void __iomem *)TIMER2_VA_BASE;
-        u32 ctrl = TIMER_CTRL_ENABLE;
+        u32 ctrl = TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC;
 
         if (khz >= 1500) {
                 khz /= 16;
-                ctrl = TIMER_CTRL_DIV16;
+                ctrl |= TIMER_CTRL_DIV16;
         }
 
-        writel(ctrl, base + TIMER_CTRL);
         writel(0xffff, base + TIMER_LOAD);
+        writel(ctrl, base + TIMER_CTRL);
 
         clocksource_mmio_init(base + TIMER_VALUE, "timer2",
                 khz * 1000, 200, 16, clocksource_mmio_readl_down);
diff --git a/arch/arm/mm/abort-macro.S b/arch/arm/mm/abort-macro.S
index 52162d59407a..2cbf68ef0e83 100644
--- a/arch/arm/mm/abort-macro.S
+++ b/arch/arm/mm/abort-macro.S
@@ -17,7 +17,7 @@
         cmp     \tmp, # 0x5600                  @ Is it ldrsb?
         orreq   \tmp, \tmp, #1 << 11            @ Set L-bit if yes
         tst     \tmp, #1 << 11                  @ L = 0 -> write
-        orreq   \psr, \psr, #1 << 11            @ yes.
+        orreq   \fsr, \fsr, #1 << 11            @ yes.
         b       do_DataAbort
 not_thumb:
         .endm
diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
index 44c086710d2b..3f9b9980478e 100644
--- a/arch/arm/mm/cache-l2x0.c
+++ b/arch/arm/mm/cache-l2x0.c
@@ -16,9 +16,12 @@
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  */
+#include <linux/err.h>
 #include <linux/init.h>
 #include <linux/spinlock.h>
 #include <linux/io.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
 
 #include <asm/cacheflush.h>
 #include <asm/hardware/cache-l2x0.h>
@@ -30,11 +33,19 @@ static DEFINE_SPINLOCK(l2x0_lock);
 static uint32_t l2x0_way_mask;  /* Bitmask of active ways */
 static uint32_t l2x0_size;
 
+struct l2x0_regs l2x0_saved_regs;
+
+struct l2x0_of_data {
+        void (*setup)(const struct device_node *, __u32 *, __u32 *);
+        void (*save)(void);
+        void (*resume)(void);
+};
+
 static inline void cache_wait_way(void __iomem *reg, unsigned long mask)
 {
         /* wait for cache operation by line or way to complete */
         while (readl_relaxed(reg) & mask)
-                ;
+                cpu_relax();
 }
 
 #ifdef CONFIG_CACHE_PL310
@@ -277,6 +288,25 @@ static void l2x0_disable(void)
         spin_unlock_irqrestore(&l2x0_lock, flags);
 }
 
+static void l2x0_unlock(__u32 cache_id)
+{
+        int lockregs;
+        int i;
+
+        if (cache_id == L2X0_CACHE_ID_PART_L310)
+                lockregs = 8;
+        else
+                /* L210 and unknown types */
+                lockregs = 1;
+
+        for (i = 0; i < lockregs; i++) {
+                writel_relaxed(0x0, l2x0_base + L2X0_LOCKDOWN_WAY_D_BASE +
+                               i * L2X0_LOCKDOWN_STRIDE);
+                writel_relaxed(0x0, l2x0_base + L2X0_LOCKDOWN_WAY_I_BASE +
+                               i * L2X0_LOCKDOWN_STRIDE);
+        }
+}
+
 void __init l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask)
 {
         __u32 aux;
@@ -328,10 +358,14 @@ void __init l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask)
          * accessing the below registers will fault.
          */
         if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & 1)) {
+                /* Make sure that I&D is not locked down when starting */
+                l2x0_unlock(cache_id);
 
                 /* l2x0 controller is disabled */
                 writel_relaxed(aux, l2x0_base + L2X0_AUX_CTRL);
 
+                l2x0_saved_regs.aux_ctrl = aux;
+
                 l2x0_inv_all();
 
                 /* enable L2X0 */
@@ -351,3 +385,202 @@ void __init l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask)
         printk(KERN_INFO "l2x0: %d ways, CACHE_ID 0x%08x, AUX_CTRL 0x%08x, Cache size: %d B\n",
                         ways, cache_id, aux, l2x0_size);
 }
+
+#ifdef CONFIG_OF
+static void __init l2x0_of_setup(const struct device_node *np,
+                                 __u32 *aux_val, __u32 *aux_mask)
+{
+        u32 data[2] = { 0, 0 };
+        u32 tag = 0;
+        u32 dirty = 0;
+        u32 val = 0, mask = 0;
+
+        of_property_read_u32(np, "arm,tag-latency", &tag);
+        if (tag) {
+                mask |= L2X0_AUX_CTRL_TAG_LATENCY_MASK;
+                val |= (tag - 1) << L2X0_AUX_CTRL_TAG_LATENCY_SHIFT;
+        }
+
+        of_property_read_u32_array(np, "arm,data-latency",
+                                   data, ARRAY_SIZE(data));
+        if (data[0] && data[1]) {
+                mask |= L2X0_AUX_CTRL_DATA_RD_LATENCY_MASK |
+                        L2X0_AUX_CTRL_DATA_WR_LATENCY_MASK;
+                val |= ((data[0] - 1) << L2X0_AUX_CTRL_DATA_RD_LATENCY_SHIFT) |
+                       ((data[1] - 1) << L2X0_AUX_CTRL_DATA_WR_LATENCY_SHIFT);
+        }
+
+        of_property_read_u32(np, "arm,dirty-latency", &dirty);
+        if (dirty) {
+                mask |= L2X0_AUX_CTRL_DIRTY_LATENCY_MASK;
+                val |= (dirty - 1) << L2X0_AUX_CTRL_DIRTY_LATENCY_SHIFT;
+        }
+
+        *aux_val &= ~mask;
+        *aux_val |= val;
+        *aux_mask &= ~mask;
+}
+
+static void __init pl310_of_setup(const struct device_node *np,
+                                  __u32 *aux_val, __u32 *aux_mask)
+{
+        u32 data[3] = { 0, 0, 0 };
+        u32 tag[3] = { 0, 0, 0 };
+        u32 filter[2] = { 0, 0 };
+
+        of_property_read_u32_array(np, "arm,tag-latency", tag, ARRAY_SIZE(tag));
+        if (tag[0] && tag[1] && tag[2])
+                writel_relaxed(
+                        ((tag[0] - 1) << L2X0_LATENCY_CTRL_RD_SHIFT) |
+                        ((tag[1] - 1) << L2X0_LATENCY_CTRL_WR_SHIFT) |
+                        ((tag[2] - 1) << L2X0_LATENCY_CTRL_SETUP_SHIFT),
+                        l2x0_base + L2X0_TAG_LATENCY_CTRL);
+
+        of_property_read_u32_array(np, "arm,data-latency",
+                                   data, ARRAY_SIZE(data));
+        if (data[0] && data[1] && data[2])
+                writel_relaxed(
+                        ((data[0] - 1) << L2X0_LATENCY_CTRL_RD_SHIFT) |
+                        ((data[1] - 1) << L2X0_LATENCY_CTRL_WR_SHIFT) |
+                        ((data[2] - 1) << L2X0_LATENCY_CTRL_SETUP_SHIFT),
+                        l2x0_base + L2X0_DATA_LATENCY_CTRL);
+
+        of_property_read_u32_array(np, "arm,filter-ranges",
+                                   filter, ARRAY_SIZE(filter));
+        if (filter[1]) {
+                writel_relaxed(ALIGN(filter[0] + filter[1], SZ_1M),
+                               l2x0_base + L2X0_ADDR_FILTER_END);
+                writel_relaxed((filter[0] & ~(SZ_1M - 1)) | L2X0_ADDR_FILTER_EN,
+                               l2x0_base + L2X0_ADDR_FILTER_START);
+        }
+}
+
+static void __init pl310_save(void)
+{
+        u32 l2x0_revision = readl_relaxed(l2x0_base + L2X0_CACHE_ID) &
+                L2X0_CACHE_ID_RTL_MASK;
+
+        l2x0_saved_regs.tag_latency = readl_relaxed(l2x0_base +
+                L2X0_TAG_LATENCY_CTRL);
+        l2x0_saved_regs.data_latency = readl_relaxed(l2x0_base +
+                L2X0_DATA_LATENCY_CTRL);
+        l2x0_saved_regs.filter_end = readl_relaxed(l2x0_base +
+                L2X0_ADDR_FILTER_END);
+        l2x0_saved_regs.filter_start = readl_relaxed(l2x0_base +
+                L2X0_ADDR_FILTER_START);
+
+        if (l2x0_revision >= L2X0_CACHE_ID_RTL_R2P0) {
+                /*
+                 * From r2p0, there is Prefetch offset/control register
+                 */
+                l2x0_saved_regs.prefetch_ctrl = readl_relaxed(l2x0_base +
+                        L2X0_PREFETCH_CTRL);
+                /*
+                 * From r3p0, there is Power control register
+                 */
+                if (l2x0_revision >= L2X0_CACHE_ID_RTL_R3P0)
+                        l2x0_saved_regs.pwr_ctrl = readl_relaxed(l2x0_base +
+                                L2X0_POWER_CTRL);
+        }
+}
+
+static void l2x0_resume(void)
+{
+        if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & 1)) {
+                /* restore aux ctrl and enable l2 */
+                l2x0_unlock(readl_relaxed(l2x0_base + L2X0_CACHE_ID));
+
+                writel_relaxed(l2x0_saved_regs.aux_ctrl, l2x0_base +
+                        L2X0_AUX_CTRL);
+
+                l2x0_inv_all();
+
+                writel_relaxed(1, l2x0_base + L2X0_CTRL);
+        }
+}
+
+static void pl310_resume(void)
+{
+        u32 l2x0_revision;
+
+        if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & 1)) {
+                /* restore pl310 setup */
+                writel_relaxed(l2x0_saved_regs.tag_latency,
+                        l2x0_base + L2X0_TAG_LATENCY_CTRL);
+                writel_relaxed(l2x0_saved_regs.data_latency,
+                        l2x0_base + L2X0_DATA_LATENCY_CTRL);
+                writel_relaxed(l2x0_saved_regs.filter_end,
+                        l2x0_base + L2X0_ADDR_FILTER_END);
+                writel_relaxed(l2x0_saved_regs.filter_start,
+                        l2x0_base + L2X0_ADDR_FILTER_START);
+
+                l2x0_revision = readl_relaxed(l2x0_base + L2X0_CACHE_ID) &
+                        L2X0_CACHE_ID_RTL_MASK;
+
+                if (l2x0_revision >= L2X0_CACHE_ID_RTL_R2P0) {
+                        writel_relaxed(l2x0_saved_regs.prefetch_ctrl,
+                                l2x0_base + L2X0_PREFETCH_CTRL);
+                        if (l2x0_revision >= L2X0_CACHE_ID_RTL_R3P0)
+                                writel_relaxed(l2x0_saved_regs.pwr_ctrl,
+                                        l2x0_base + L2X0_POWER_CTRL);
+                }
+        }
+
+        l2x0_resume();
+}
+
+static const struct l2x0_of_data pl310_data = {
+        pl310_of_setup,
+        pl310_save,
+        pl310_resume,
+};
+
+static const struct l2x0_of_data l2x0_data = {
+        l2x0_of_setup,
+        NULL,
+        l2x0_resume,
+};
+
+static const struct of_device_id l2x0_ids[] __initconst = {
+        { .compatible = "arm,pl310-cache", .data = (void *)&pl310_data },
+        { .compatible = "arm,l220-cache", .data = (void *)&l2x0_data },
+        { .compatible = "arm,l210-cache", .data = (void *)&l2x0_data },
+        {}
+};
+
+int __init l2x0_of_init(__u32 aux_val, __u32 aux_mask)
+{
+        struct device_node *np;
+        struct l2x0_of_data *data;
+        struct resource res;
+
+        np = of_find_matching_node(NULL, l2x0_ids);
+        if (!np)
+                return -ENODEV;
+
+        if (of_address_to_resource(np, 0, &res))
+                return -ENODEV;
+
+        l2x0_base = ioremap(res.start, resource_size(&res));
+        if (!l2x0_base)
+                return -ENOMEM;
+
+        l2x0_saved_regs.phy_base = res.start;
+
+        data = of_match_node(l2x0_ids, np)->data;
+
+        /* L2 configuration can only be changed if the cache is disabled */
+        if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & 1)) {
+                if (data->setup)
+                        data->setup(np, &aux_val, &aux_mask);
+        }
+
+        if (data->save)
+                data->save();
+
+        l2x0_init(l2x0_base, aux_val, aux_mask);
+
+        outer_cache.resume = data->resume;
+        return 0;
+}
+#endif
diff --git a/arch/arm/mm/init.c b/arch/arm/mm/init.c
index 91bca355cd31..cc7e2d8be9aa 100644
--- a/arch/arm/mm/init.c
+++ b/arch/arm/mm/init.c
@@ -298,7 +298,7 @@ static void __init arm_bootmem_free(unsigned long min, unsigned long max_low,
 #ifdef CONFIG_HAVE_ARCH_PFN_VALID
 int pfn_valid(unsigned long pfn)
 {
-        return memblock_is_memory(pfn << PAGE_SHIFT);
+        return memblock_is_memory(__pfn_to_phys(pfn));
 }
 EXPORT_SYMBOL(pfn_valid);
 #endif
diff --git a/arch/x86/include/asm/pvclock.h b/arch/x86/include/asm/pvclock.h
index a518c0a45044..c59cc97fe6c1 100644
--- a/arch/x86/include/asm/pvclock.h
+++ b/arch/x86/include/asm/pvclock.h
@@ -44,7 +44,7 @@ static inline u64 pvclock_scale_delta(u64 delta, u32 mul_frac, int shift)
                 : "a" ((u32)delta), "1" ((u32)(delta >> 32)), "2" (mul_frac) );
 #elif defined(__x86_64__)
         __asm__ (
-                "mul %[mul_frac] ; shrd $32, %[hi], %[lo]"
+                "mulq %[mul_frac] ; shrd $32, %[hi], %[lo]"
                 : [lo]"=a"(product),
                   [hi]"=d"(tmp)
                 : "0"(delta),
diff --git a/arch/x86/kernel/cpu/perf_event.c b/arch/x86/kernel/cpu/perf_event.c
index 4ee3abf20ed6..cfa62ec090ec 100644
--- a/arch/x86/kernel/cpu/perf_event.c
+++ b/arch/x86/kernel/cpu/perf_event.c
@@ -1900,6 +1900,9 @@ perf_callchain_user(struct perf_callchain_entry *entry, struct pt_regs *regs)
 
         perf_callchain_store(entry, regs->ip);
 
+        if (!current->mm)
+                return;
+
         if (perf_callchain_user32(regs, entry))
                 return;
 
diff --git a/arch/x86/pci/acpi.c b/arch/x86/pci/acpi.c
index c95330267f08..039d91315bc5 100644
--- a/arch/x86/pci/acpi.c
+++ b/arch/x86/pci/acpi.c
@@ -365,8 +365,13 @@ struct pci_bus * __devinit pci_acpi_scan_root(struct acpi_pci_root *root)
          */
         if (bus) {
                 struct pci_bus *child;
-                list_for_each_entry(child, &bus->children, node)
-                        pcie_bus_configure_settings(child, child->self->pcie_mpss);
+                list_for_each_entry(child, &bus->children, node) {
+                        struct pci_dev *self = child->self;
+                        if (!self)
+                                continue;
+
+                        pcie_bus_configure_settings(child, self->pcie_mpss);
+                }
         }
 
         if (!bus)
diff --git a/arch/x86/xen/setup.c b/arch/x86/xen/setup.c
index df118a825f39..c3b8d440873c 100644
--- a/arch/x86/xen/setup.c
+++ b/arch/x86/xen/setup.c
@@ -184,6 +184,19 @@ static unsigned long __init xen_set_identity(const struct e820entry *list,
                                         PFN_UP(start_pci), PFN_DOWN(last));
         return identity;
 }
+
+static unsigned long __init xen_get_max_pages(void)
+{
+        unsigned long max_pages = MAX_DOMAIN_PAGES;
+        domid_t domid = DOMID_SELF;
+        int ret;
+
+        ret = HYPERVISOR_memory_op(XENMEM_maximum_reservation, &domid);
+        if (ret > 0)
+                max_pages = ret;
+        return min(max_pages, MAX_DOMAIN_PAGES);
+}
+
 /**
  * machine_specific_memory_setup - Hook for machine specific memory setup.
  **/
@@ -292,6 +305,12 @@ char * __init xen_memory_setup(void)
 
         sanitize_e820_map(e820.map, ARRAY_SIZE(e820.map), &e820.nr_map);
 
+        extra_limit = xen_get_max_pages();
+        if (extra_limit >= max_pfn)
+                extra_pages = extra_limit - max_pfn;
+        else
+                extra_pages = 0;
+
         extra_pages += xen_return_unused_memory(xen_start_info->nr_pages, &e820);
 
         /*
diff --git a/arch/x86/xen/smp.c b/arch/x86/xen/smp.c
index e79dbb95482b..d4fc6d454f8d 100644
--- a/arch/x86/xen/smp.c
+++ b/arch/x86/xen/smp.c
@@ -32,6 +32,7 @@
 #include <xen/page.h>
 #include <xen/events.h>
 
+#include <xen/hvc-console.h>
 #include "xen-ops.h"
 #include "mmu.h"
 
@@ -207,6 +208,15 @@ static void __init xen_smp_prepare_cpus(unsigned int max_cpus)
         unsigned cpu;
         unsigned int i;
 
+        if (skip_ioapic_setup) {
+                char *m = (max_cpus == 0) ?
+                        "The nosmp parameter is incompatible with Xen; " \
+                        "use Xen dom0_max_vcpus=1 parameter" :
+                        "The noapic parameter is incompatible with Xen";
+
+                xen_raw_printk(m);
+                panic(m);
+        }
         xen_init_lock_cpu(0);
 
         smp_store_cpu_info(0);
diff --git a/arch/x86/xen/xen-asm_32.S b/arch/x86/xen/xen-asm_32.S
index 22a2093b5862..b040b0e518ca 100644
--- a/arch/x86/xen/xen-asm_32.S
+++ b/arch/x86/xen/xen-asm_32.S
@@ -113,11 +113,13 @@ xen_iret_start_crit:
 
         /*
          * If there's something pending, mask events again so we can
-         * jump back into xen_hypervisor_callback
+         * jump back into xen_hypervisor_callback. Otherwise do not
+         * touch XEN_vcpu_info_mask.
          */
-        sete XEN_vcpu_info_mask(%eax)
+        jne 1f
+        movb $1, XEN_vcpu_info_mask(%eax)
 
-        popl %eax
+1:      popl %eax
 
         /*
          * From this point on the registers are restored and the stack