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authorLinus Torvalds <torvalds@woody.linux-foundation.org>2008-01-13 13:03:10 -0500
committerLinus Torvalds <torvalds@woody.linux-foundation.org>2008-01-13 13:03:10 -0500
commit1a1b285c24e1468afe82b09330dde5192a6e0013 (patch)
tree94406d24339b3791b7b5481ee969f0300e3c48cf /arch
parentd72ec9e20e4de995aa957f171cf84b136689e4c0 (diff)
parent90e6b048365950416419c031f2f2d9a8afb5b70c (diff)
Merge master.kernel.org:/home/rmk/linux-2.6-arm
* master.kernel.org:/home/rmk/linux-2.6-arm: [ARM] vfp: fix fuitod/fsitod instructions [ARM] pxa: silence warnings from cpu_is_xxx() macros
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/vfp/vfp.h2
-rw-r--r--arch/arm/vfp/vfpdouble.c14
2 files changed, 13 insertions, 3 deletions
diff --git a/arch/arm/vfp/vfp.h b/arch/arm/vfp/vfp.h
index 54a2ad6d9ca2..791d0238c68f 100644
--- a/arch/arm/vfp/vfp.h
+++ b/arch/arm/vfp/vfp.h
@@ -361,10 +361,12 @@ u32 vfp_estimate_sqrt_significand(u32 exponent, u32 significand);
361 * OP_SCALAR - this operation always operates in scalar mode 361 * OP_SCALAR - this operation always operates in scalar mode
362 * OP_SD - the instruction exceptionally writes to a single precision result. 362 * OP_SD - the instruction exceptionally writes to a single precision result.
363 * OP_DD - the instruction exceptionally writes to a double precision result. 363 * OP_DD - the instruction exceptionally writes to a double precision result.
364 * OP_SM - the instruction exceptionally reads from a single precision operand.
364 */ 365 */
365#define OP_SCALAR (1 << 0) 366#define OP_SCALAR (1 << 0)
366#define OP_SD (1 << 1) 367#define OP_SD (1 << 1)
367#define OP_DD (1 << 1) 368#define OP_DD (1 << 1)
369#define OP_SM (1 << 2)
368 370
369struct op { 371struct op {
370 u32 (* const fn)(int dd, int dn, int dm, u32 fpscr); 372 u32 (* const fn)(int dd, int dn, int dm, u32 fpscr);
diff --git a/arch/arm/vfp/vfpdouble.c b/arch/arm/vfp/vfpdouble.c
index 190a09ad18eb..6cac43bd1d86 100644
--- a/arch/arm/vfp/vfpdouble.c
+++ b/arch/arm/vfp/vfpdouble.c
@@ -668,8 +668,8 @@ static struct op fops_ext[32] = {
668 [FEXT_TO_IDX(FEXT_FCMPZ)] = { vfp_double_fcmpz, OP_SCALAR }, 668 [FEXT_TO_IDX(FEXT_FCMPZ)] = { vfp_double_fcmpz, OP_SCALAR },
669 [FEXT_TO_IDX(FEXT_FCMPEZ)] = { vfp_double_fcmpez, OP_SCALAR }, 669 [FEXT_TO_IDX(FEXT_FCMPEZ)] = { vfp_double_fcmpez, OP_SCALAR },
670 [FEXT_TO_IDX(FEXT_FCVT)] = { vfp_double_fcvts, OP_SCALAR|OP_SD }, 670 [FEXT_TO_IDX(FEXT_FCVT)] = { vfp_double_fcvts, OP_SCALAR|OP_SD },
671 [FEXT_TO_IDX(FEXT_FUITO)] = { vfp_double_fuito, OP_SCALAR }, 671 [FEXT_TO_IDX(FEXT_FUITO)] = { vfp_double_fuito, OP_SCALAR|OP_SM },
672 [FEXT_TO_IDX(FEXT_FSITO)] = { vfp_double_fsito, OP_SCALAR }, 672 [FEXT_TO_IDX(FEXT_FSITO)] = { vfp_double_fsito, OP_SCALAR|OP_SM },
673 [FEXT_TO_IDX(FEXT_FTOUI)] = { vfp_double_ftoui, OP_SCALAR|OP_SD }, 673 [FEXT_TO_IDX(FEXT_FTOUI)] = { vfp_double_ftoui, OP_SCALAR|OP_SD },
674 [FEXT_TO_IDX(FEXT_FTOUIZ)] = { vfp_double_ftouiz, OP_SCALAR|OP_SD }, 674 [FEXT_TO_IDX(FEXT_FTOUIZ)] = { vfp_double_ftouiz, OP_SCALAR|OP_SD },
675 [FEXT_TO_IDX(FEXT_FTOSI)] = { vfp_double_ftosi, OP_SCALAR|OP_SD }, 675 [FEXT_TO_IDX(FEXT_FTOSI)] = { vfp_double_ftosi, OP_SCALAR|OP_SD },
@@ -1128,7 +1128,7 @@ u32 vfp_double_cpdo(u32 inst, u32 fpscr)
1128 u32 exceptions = 0; 1128 u32 exceptions = 0;
1129 unsigned int dest; 1129 unsigned int dest;
1130 unsigned int dn = vfp_get_dn(inst); 1130 unsigned int dn = vfp_get_dn(inst);
1131 unsigned int dm = vfp_get_dm(inst); 1131 unsigned int dm;
1132 unsigned int vecitr, veclen, vecstride; 1132 unsigned int vecitr, veclen, vecstride;
1133 struct op *fop; 1133 struct op *fop;
1134 1134
@@ -1146,6 +1146,14 @@ u32 vfp_double_cpdo(u32 inst, u32 fpscr)
1146 dest = vfp_get_dd(inst); 1146 dest = vfp_get_dd(inst);
1147 1147
1148 /* 1148 /*
1149 * f[us]ito takes a sN operand, not a dN operand.
1150 */
1151 if (fop->flags & OP_SM)
1152 dm = vfp_get_sm(inst);
1153 else
1154 dm = vfp_get_dm(inst);
1155
1156 /*
1149 * If destination bank is zero, vector length is always '1'. 1157 * If destination bank is zero, vector length is always '1'.
1150 * ARM DDI0100F C5.1.3, C5.3.2. 1158 * ARM DDI0100F C5.1.3, C5.3.2.
1151 */ 1159 */