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authorEzequiel Garcia <ezequiel.garcia@free-electrons.com>2013-08-16 05:28:24 -0400
committerRussell King <rmk+kernel@arm.linux.org.uk>2013-08-19 19:12:52 -0400
commit19a0519d3642d140bfb1bd602a34dc4f98606b19 (patch)
treece8c8b73e3b5ce595e9832ce089e975b4af2fd7b /arch
parentda0ec6f7c1e1125e792b0a73a04edad035cf8d42 (diff)
ARM: 7818/1: feroceon: Add suspend/resume operation
Add support for suspend/resume operations. The implemented procedures are identical to the ones for ARM926. Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/Kconfig2
-rw-r--r--arch/arm/mm/proc-feroceon.S26
2 files changed, 27 insertions, 1 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 32506dfa5e73..57562f8d1f92 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -2240,7 +2240,7 @@ source "kernel/power/Kconfig"
2240 2240
2241config ARCH_SUSPEND_POSSIBLE 2241config ARCH_SUSPEND_POSSIBLE
2242 depends on !ARCH_S5PC100 2242 depends on !ARCH_S5PC100
2243 depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \ 2243 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \
2244 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK 2244 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2245 def_bool y 2245 def_bool y
2246 2246
diff --git a/arch/arm/mm/proc-feroceon.S b/arch/arm/mm/proc-feroceon.S
index d5146b98c8d1..db79b62c92fb 100644
--- a/arch/arm/mm/proc-feroceon.S
+++ b/arch/arm/mm/proc-feroceon.S
@@ -514,6 +514,32 @@ ENTRY(cpu_feroceon_set_pte_ext)
514#endif 514#endif
515 mov pc, lr 515 mov pc, lr
516 516
517/* Suspend/resume support: taken from arch/arm/mm/proc-arm926.S */
518.globl cpu_feroceon_suspend_size
519.equ cpu_feroceon_suspend_size, 4 * 3
520#ifdef CONFIG_ARM_CPU_SUSPEND
521ENTRY(cpu_feroceon_do_suspend)
522 stmfd sp!, {r4 - r6, lr}
523 mrc p15, 0, r4, c13, c0, 0 @ PID
524 mrc p15, 0, r5, c3, c0, 0 @ Domain ID
525 mrc p15, 0, r6, c1, c0, 0 @ Control register
526 stmia r0, {r4 - r6}
527 ldmfd sp!, {r4 - r6, pc}
528ENDPROC(cpu_feroceon_do_suspend)
529
530ENTRY(cpu_feroceon_do_resume)
531 mov ip, #0
532 mcr p15, 0, ip, c8, c7, 0 @ invalidate I+D TLBs
533 mcr p15, 0, ip, c7, c7, 0 @ invalidate I+D caches
534 ldmia r0, {r4 - r6}
535 mcr p15, 0, r4, c13, c0, 0 @ PID
536 mcr p15, 0, r5, c3, c0, 0 @ Domain ID
537 mcr p15, 0, r1, c2, c0, 0 @ TTB address
538 mov r0, r6 @ control register
539 b cpu_resume_mmu
540ENDPROC(cpu_feroceon_do_resume)
541#endif
542
517 .type __feroceon_setup, #function 543 .type __feroceon_setup, #function
518__feroceon_setup: 544__feroceon_setup:
519 mov r0, #0 545 mov r0, #0