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authorUwe Kleine-König <u.kleine-koenig@pengutronix.de>2011-04-07 05:13:25 -0400
committerSascha Hauer <s.hauer@pengutronix.de>2011-05-19 07:11:28 -0400
commit13cf8df97d075cf61445c689a30c8b0ce70b415f (patch)
tree7c9294508d8983a9a11b2ee6e8001050e31e1f69 /arch
parentf142b6196891660b329408e71573f97475823667 (diff)
ARM: remove support for mxc91231
Since support for mxc91231 was introduced 2009 it only saw patches that were part of (mxc or arm) global cleanups. The only supported machine only had 4 devices (2x UART, sdhc, watchdog). Cc: Dmitriy Taychenachev <dimichxp@gmail.com> LAKML-Reference: 1302211482-17926-1-git-send-email-u.kleine-koenig@pengutronix.de Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/Makefile1
-rw-r--r--arch/arm/mach-mxc91231/Kconfig11
-rw-r--r--arch/arm/mach-mxc91231/Makefile2
-rw-r--r--arch/arm/mach-mxc91231/Makefile.boot3
-rw-r--r--arch/arm/mach-mxc91231/clock.c640
-rw-r--r--arch/arm/mach-mxc91231/crm_regs.h394
-rw-r--r--arch/arm/mach-mxc91231/devices.c251
-rw-r--r--arch/arm/mach-mxc91231/devices.h13
-rw-r--r--arch/arm/mach-mxc91231/iomux.c177
-rw-r--r--arch/arm/mach-mxc91231/magx-zn5.c62
-rw-r--r--arch/arm/mach-mxc91231/mm.c62
-rw-r--r--arch/arm/mach-mxc91231/system.c51
-rw-r--r--arch/arm/plat-mxc/Kconfig8
-rw-r--r--arch/arm/plat-mxc/include/mach/common.h7
-rw-r--r--arch/arm/plat-mxc/include/mach/debug-macro.S7
-rw-r--r--arch/arm/plat-mxc/include/mach/hardware.h13
-rw-r--r--arch/arm/plat-mxc/include/mach/iomux-mxc91231.h283
-rw-r--r--arch/arm/plat-mxc/include/mach/irqs.h2
-rw-r--r--arch/arm/plat-mxc/include/mach/memory.h3
-rw-r--r--arch/arm/plat-mxc/include/mach/mxc.h15
-rw-r--r--arch/arm/plat-mxc/include/mach/mxc91231.h256
-rw-r--r--arch/arm/plat-mxc/include/mach/system.h6
-rw-r--r--arch/arm/plat-mxc/include/mach/timex.h2
-rw-r--r--arch/arm/plat-mxc/system.c6
-rw-r--r--arch/arm/plat-mxc/time.c2
25 files changed, 2 insertions, 2275 deletions
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index c7d321a3d95d..80d178878f6e 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -160,7 +160,6 @@ machine-$(CONFIG_ARCH_MX2) := imx
160machine-$(CONFIG_ARCH_MX25) := imx 160machine-$(CONFIG_ARCH_MX25) := imx
161machine-$(CONFIG_ARCH_MX3) := mx3 161machine-$(CONFIG_ARCH_MX3) := mx3
162machine-$(CONFIG_ARCH_MX5) := mx5 162machine-$(CONFIG_ARCH_MX5) := mx5
163machine-$(CONFIG_ARCH_MXC91231) := mxc91231
164machine-$(CONFIG_ARCH_MXS) := mxs 163machine-$(CONFIG_ARCH_MXS) := mxs
165machine-$(CONFIG_ARCH_NETX) := netx 164machine-$(CONFIG_ARCH_NETX) := netx
166machine-$(CONFIG_ARCH_NOMADIK) := nomadik 165machine-$(CONFIG_ARCH_NOMADIK) := nomadik
diff --git a/arch/arm/mach-mxc91231/Kconfig b/arch/arm/mach-mxc91231/Kconfig
deleted file mode 100644
index 8e5fa38ebb67..000000000000
--- a/arch/arm/mach-mxc91231/Kconfig
+++ /dev/null
@@ -1,11 +0,0 @@
1if ARCH_MXC91231
2
3comment "MXC91231 platforms:"
4
5config MACH_MAGX_ZN5
6 bool "Support Motorola Zn5 GSM phone"
7 default n
8 help
9 Include support for Motorola Zn5 GSM phone.
10
11endif
diff --git a/arch/arm/mach-mxc91231/Makefile b/arch/arm/mach-mxc91231/Makefile
deleted file mode 100644
index 011d5e197125..000000000000
--- a/arch/arm/mach-mxc91231/Makefile
+++ /dev/null
@@ -1,2 +0,0 @@
1obj-y := mm.o clock.o devices.o system.o iomux.o
2obj-$(CONFIG_MACH_MAGX_ZN5) += magx-zn5.o
diff --git a/arch/arm/mach-mxc91231/Makefile.boot b/arch/arm/mach-mxc91231/Makefile.boot
deleted file mode 100644
index 9939a19d99a1..000000000000
--- a/arch/arm/mach-mxc91231/Makefile.boot
+++ /dev/null
@@ -1,3 +0,0 @@
1 zreladdr-y := 0x90008000
2params_phys-y := 0x90000100
3initrd_phys-y := 0x90800000
diff --git a/arch/arm/mach-mxc91231/clock.c b/arch/arm/mach-mxc91231/clock.c
deleted file mode 100644
index 9fab505f1eb1..000000000000
--- a/arch/arm/mach-mxc91231/clock.c
+++ /dev/null
@@ -1,640 +0,0 @@
1#include <linux/clk.h>
2#include <linux/kernel.h>
3#include <linux/init.h>
4#include <linux/io.h>
5#include <linux/clkdev.h>
6
7#include <mach/clock.h>
8#include <mach/hardware.h>
9#include <mach/common.h>
10
11#include <asm/bug.h>
12#include <asm/div64.h>
13
14#include "crm_regs.h"
15
16#define CRM_SMALL_DIVIDER(base, name) \
17 crm_small_divider(base, \
18 base ## _ ## name ## _OFFSET, \
19 base ## _ ## name ## _MASK)
20#define CRM_1DIVIDER(base, name) \
21 crm_divider(base, \
22 base ## _ ## name ## _OFFSET, \
23 base ## _ ## name ## _MASK, 1)
24#define CRM_16DIVIDER(base, name) \
25 crm_divider(base, \
26 base ## _ ## name ## _OFFSET, \
27 base ## _ ## name ## _MASK, 16)
28
29static u32 crm_small_divider(void __iomem *reg, u8 offset, u32 mask)
30{
31 static const u32 crm_small_dividers[] = {
32 2, 3, 4, 5, 6, 8, 10, 12
33 };
34 u8 idx;
35
36 idx = (__raw_readl(reg) & mask) >> offset;
37 if (idx > 7)
38 return 1;
39
40 return crm_small_dividers[idx];
41}
42
43static u32 crm_divider(void __iomem *reg, u8 offset, u32 mask, u32 z)
44{
45 u32 div;
46 div = (__raw_readl(reg) & mask) >> offset;
47 return div ? div : z;
48}
49
50static int _clk_1bit_enable(struct clk *clk)
51{
52 u32 reg;
53
54 reg = __raw_readl(clk->enable_reg);
55 reg |= 1 << clk->enable_shift;
56 __raw_writel(reg, clk->enable_reg);
57
58 return 0;
59}
60
61static void _clk_1bit_disable(struct clk *clk)
62{
63 u32 reg;
64
65 reg = __raw_readl(clk->enable_reg);
66 reg &= ~(1 << clk->enable_shift);
67 __raw_writel(reg, clk->enable_reg);
68}
69
70static int _clk_3bit_enable(struct clk *clk)
71{
72 u32 reg;
73
74 reg = __raw_readl(clk->enable_reg);
75 reg |= 0x7 << clk->enable_shift;
76 __raw_writel(reg, clk->enable_reg);
77
78 return 0;
79}
80
81static void _clk_3bit_disable(struct clk *clk)
82{
83 u32 reg;
84
85 reg = __raw_readl(clk->enable_reg);
86 reg &= ~(0x7 << clk->enable_shift);
87 __raw_writel(reg, clk->enable_reg);
88}
89
90static unsigned long ckih_rate;
91
92static unsigned long clk_ckih_get_rate(struct clk *clk)
93{
94 return ckih_rate;
95}
96
97static struct clk ckih_clk = {
98 .get_rate = clk_ckih_get_rate,
99};
100
101static unsigned long clk_ckih_x2_get_rate(struct clk *clk)
102{
103 return 2 * clk_get_rate(clk->parent);
104}
105
106static struct clk ckih_x2_clk = {
107 .parent = &ckih_clk,
108 .get_rate = clk_ckih_x2_get_rate,
109};
110
111static unsigned long clk_ckil_get_rate(struct clk *clk)
112{
113 return CKIL_CLK_FREQ;
114}
115
116static struct clk ckil_clk = {
117 .get_rate = clk_ckil_get_rate,
118};
119
120/* plls stuff */
121static struct clk mcu_pll_clk;
122static struct clk dsp_pll_clk;
123static struct clk usb_pll_clk;
124
125static struct clk *pll_clk(u8 sel)
126{
127 switch (sel) {
128 case 0:
129 return &mcu_pll_clk;
130 case 1:
131 return &dsp_pll_clk;
132 case 2:
133 return &usb_pll_clk;
134 }
135 BUG();
136}
137
138static void __iomem *pll_base(struct clk *clk)
139{
140 if (clk == &mcu_pll_clk)
141 return MXC_PLL0_BASE;
142 else if (clk == &dsp_pll_clk)
143 return MXC_PLL1_BASE;
144 else if (clk == &usb_pll_clk)
145 return MXC_PLL2_BASE;
146 BUG();
147}
148
149static unsigned long clk_pll_get_rate(struct clk *clk)
150{
151 const void __iomem *pllbase;
152 unsigned long dp_op, dp_mfd, dp_mfn, pll_hfsm, ref_clk, mfi;
153 long mfn, mfn_abs, mfd, pdf;
154 s64 temp;
155 pllbase = pll_base(clk);
156
157 pll_hfsm = __raw_readl(pllbase + MXC_PLL_DP_CTL) & MXC_PLL_DP_CTL_HFSM;
158 if (pll_hfsm == 0) {
159 dp_op = __raw_readl(pllbase + MXC_PLL_DP_OP);
160 dp_mfd = __raw_readl(pllbase + MXC_PLL_DP_MFD);
161 dp_mfn = __raw_readl(pllbase + MXC_PLL_DP_MFN);
162 } else {
163 dp_op = __raw_readl(pllbase + MXC_PLL_DP_HFS_OP);
164 dp_mfd = __raw_readl(pllbase + MXC_PLL_DP_HFS_MFD);
165 dp_mfn = __raw_readl(pllbase + MXC_PLL_DP_HFS_MFN);
166 }
167
168 pdf = dp_op & MXC_PLL_DP_OP_PDF_MASK;
169 mfi = (dp_op >> MXC_PLL_DP_OP_MFI_OFFSET) & MXC_PLL_DP_OP_PDF_MASK;
170 mfi = (mfi <= 5) ? 5 : mfi;
171 mfd = dp_mfd & MXC_PLL_DP_MFD_MASK;
172 mfn = dp_mfn & MXC_PLL_DP_MFN_MASK;
173 mfn = (mfn <= 0x4000000) ? mfn : (mfn - 0x10000000);
174
175 if (mfn < 0)
176 mfn_abs = -mfn;
177 else
178 mfn_abs = mfn;
179
180/* XXX: actually this asumes that ckih is fed to pll, but spec says
181 * that ckih_x2 is also possible. need to check this out.
182 */
183 ref_clk = clk_get_rate(&ckih_clk);
184
185 ref_clk *= 2;
186 ref_clk /= pdf + 1;
187
188 temp = (u64) ref_clk * mfn_abs;
189 do_div(temp, mfd);
190 if (mfn < 0)
191 temp = -temp;
192 temp += ref_clk * mfi;
193
194 return temp;
195}
196
197static int clk_pll_enable(struct clk *clk)
198{
199 void __iomem *ctl;
200 u32 reg;
201
202 ctl = pll_base(clk);
203 reg = __raw_readl(ctl);
204 reg |= (MXC_PLL_DP_CTL_RST | MXC_PLL_DP_CTL_UPEN);
205 __raw_writel(reg, ctl);
206 do {
207 reg = __raw_readl(ctl);
208 } while ((reg & MXC_PLL_DP_CTL_LRF) != MXC_PLL_DP_CTL_LRF);
209 return 0;
210}
211
212static void clk_pll_disable(struct clk *clk)
213{
214 void __iomem *ctl;
215 u32 reg;
216
217 ctl = pll_base(clk);
218 reg = __raw_readl(ctl);
219 reg &= ~(MXC_PLL_DP_CTL_RST | MXC_PLL_DP_CTL_UPEN);
220 __raw_writel(reg, ctl);
221}
222
223static struct clk mcu_pll_clk = {
224 .parent = &ckih_clk,
225 .get_rate = clk_pll_get_rate,
226 .enable = clk_pll_enable,
227 .disable = clk_pll_disable,
228};
229
230static struct clk dsp_pll_clk = {
231 .parent = &ckih_clk,
232 .get_rate = clk_pll_get_rate,
233 .enable = clk_pll_enable,
234 .disable = clk_pll_disable,
235};
236
237static struct clk usb_pll_clk = {
238 .parent = &ckih_clk,
239 .get_rate = clk_pll_get_rate,
240 .enable = clk_pll_enable,
241 .disable = clk_pll_disable,
242};
243/* plls stuff end */
244
245/* ap_ref_clk stuff */
246static struct clk ap_ref_clk;
247
248static unsigned long clk_ap_ref_get_rate(struct clk *clk)
249{
250 u32 ascsr, acsr;
251 u8 ap_pat_ref_div_2, ap_isel, acs, ads;
252
253 ascsr = __raw_readl(MXC_CRMAP_ASCSR);
254 acsr = __raw_readl(MXC_CRMAP_ACSR);
255
256 /* 0 for ckih, 1 for ckih*2 */
257 ap_isel = ascsr & MXC_CRMAP_ASCSR_APISEL;
258 /* reg divider */
259 ap_pat_ref_div_2 = (ascsr >> MXC_CRMAP_ASCSR_AP_PATDIV2_OFFSET) & 0x1;
260 /* undocumented, 1 for disabling divider */
261 ads = (acsr >> MXC_CRMAP_ACSR_ADS_OFFSET) & 0x1;
262 /* 0 for pat_ref, 1 for divider out */
263 acs = acsr & MXC_CRMAP_ACSR_ACS;
264
265 if (acs & !ads)
266 /* use divided clock */
267 return clk_get_rate(clk->parent) / (ap_pat_ref_div_2 ? 2 : 1);
268
269 return clk_get_rate(clk->parent) * (ap_isel ? 2 : 1);
270}
271
272static struct clk ap_ref_clk = {
273 .parent = &ckih_clk,
274 .get_rate = clk_ap_ref_get_rate,
275};
276/* ap_ref_clk stuff end */
277
278/* ap_pre_dfs_clk stuff */
279static struct clk ap_pre_dfs_clk;
280
281static unsigned long clk_ap_pre_dfs_get_rate(struct clk *clk)
282{
283 u32 acsr, ascsr;
284
285 acsr = __raw_readl(MXC_CRMAP_ACSR);
286 ascsr = __raw_readl(MXC_CRMAP_ASCSR);
287
288 if (acsr & MXC_CRMAP_ACSR_ACS) {
289 u8 sel;
290 sel = (ascsr & MXC_CRMAP_ASCSR_APSEL_MASK) >>
291 MXC_CRMAP_ASCSR_APSEL_OFFSET;
292 return clk_get_rate(pll_clk(sel)) /
293 CRM_SMALL_DIVIDER(MXC_CRMAP_ACDR, ARMDIV);
294 }
295 return clk_get_rate(&ap_ref_clk);
296}
297
298static struct clk ap_pre_dfs_clk = {
299 .get_rate = clk_ap_pre_dfs_get_rate,
300};
301/* ap_pre_dfs_clk stuff end */
302
303/* usb_clk stuff */
304static struct clk usb_clk;
305
306static struct clk *clk_usb_parent(struct clk *clk)
307{
308 u32 acsr, ascsr;
309
310 acsr = __raw_readl(MXC_CRMAP_ACSR);
311 ascsr = __raw_readl(MXC_CRMAP_ASCSR);
312
313 if (acsr & MXC_CRMAP_ACSR_ACS) {
314 u8 sel;
315 sel = (ascsr & MXC_CRMAP_ASCSR_USBSEL_MASK) >>
316 MXC_CRMAP_ASCSR_USBSEL_OFFSET;
317 return pll_clk(sel);
318 }
319 return &ap_ref_clk;
320}
321
322static unsigned long clk_usb_get_rate(struct clk *clk)
323{
324 return clk_get_rate(clk->parent) /
325 CRM_SMALL_DIVIDER(MXC_CRMAP_ACDER2, USBDIV);
326}
327
328static struct clk usb_clk = {
329 .enable_reg = MXC_CRMAP_ACDER2,
330 .enable_shift = MXC_CRMAP_ACDER2_USBEN_OFFSET,
331 .get_rate = clk_usb_get_rate,
332 .enable = _clk_1bit_enable,
333 .disable = _clk_1bit_disable,
334};
335/* usb_clk stuff end */
336
337static unsigned long clk_ipg_get_rate(struct clk *clk)
338{
339 return clk_get_rate(clk->parent) / CRM_16DIVIDER(MXC_CRMAP_ACDR, IPDIV);
340}
341
342static unsigned long clk_ahb_get_rate(struct clk *clk)
343{
344 return clk_get_rate(clk->parent) /
345 CRM_16DIVIDER(MXC_CRMAP_ACDR, AHBDIV);
346}
347
348static struct clk ipg_clk = {
349 .parent = &ap_pre_dfs_clk,
350 .get_rate = clk_ipg_get_rate,
351};
352
353static struct clk ahb_clk = {
354 .parent = &ap_pre_dfs_clk,
355 .get_rate = clk_ahb_get_rate,
356};
357
358/* perclk_clk stuff */
359static struct clk perclk_clk;
360
361static unsigned long clk_perclk_get_rate(struct clk *clk)
362{
363 u32 acder2;
364
365 acder2 = __raw_readl(MXC_CRMAP_ACDER2);
366 if (acder2 & MXC_CRMAP_ACDER2_BAUD_ISEL_MASK)
367 return 2 * clk_get_rate(clk->parent);
368
369 return clk_get_rate(clk->parent);
370}
371
372static struct clk perclk_clk = {
373 .parent = &ckih_clk,
374 .get_rate = clk_perclk_get_rate,
375};
376/* perclk_clk stuff end */
377
378/* uart_clk stuff */
379static struct clk uart_clk[];
380
381static unsigned long clk_uart_get_rate(struct clk *clk)
382{
383 u32 div;
384
385 switch (clk->id) {
386 case 0:
387 case 1:
388 div = CRM_SMALL_DIVIDER(MXC_CRMAP_ACDER2, BAUDDIV);
389 break;
390 case 2:
391 div = CRM_SMALL_DIVIDER(MXC_CRMAP_APRA, UART3DIV);
392 break;
393 default:
394 BUG();
395 }
396 return clk_get_rate(clk->parent) / div;
397}
398
399static struct clk uart_clk[] = {
400 {
401 .id = 0,
402 .parent = &perclk_clk,
403 .enable_reg = MXC_CRMAP_APRA,
404 .enable_shift = MXC_CRMAP_APRA_UART1EN_OFFSET,
405 .get_rate = clk_uart_get_rate,
406 .enable = _clk_1bit_enable,
407 .disable = _clk_1bit_disable,
408 }, {
409 .id = 1,
410 .parent = &perclk_clk,
411 .enable_reg = MXC_CRMAP_APRA,
412 .enable_shift = MXC_CRMAP_APRA_UART2EN_OFFSET,
413 .get_rate = clk_uart_get_rate,
414 .enable = _clk_1bit_enable,
415 .disable = _clk_1bit_disable,
416 }, {
417 .id = 2,
418 .parent = &perclk_clk,
419 .enable_reg = MXC_CRMAP_APRA,
420 .enable_shift = MXC_CRMAP_APRA_UART3EN_OFFSET,
421 .get_rate = clk_uart_get_rate,
422 .enable = _clk_1bit_enable,
423 .disable = _clk_1bit_disable,
424 },
425};
426/* uart_clk stuff end */
427
428/* sdhc_clk stuff */
429static struct clk nfc_clk;
430
431static unsigned long clk_nfc_get_rate(struct clk *clk)
432{
433 return clk_get_rate(clk->parent) /
434 CRM_1DIVIDER(MXC_CRMAP_ACDER2, NFCDIV);
435}
436
437static struct clk nfc_clk = {
438 .parent = &ahb_clk,
439 .enable_reg = MXC_CRMAP_ACDER2,
440 .enable_shift = MXC_CRMAP_ACDER2_NFCEN_OFFSET,
441 .get_rate = clk_nfc_get_rate,
442 .enable = _clk_1bit_enable,
443 .disable = _clk_1bit_disable,
444};
445/* sdhc_clk stuff end */
446
447/* sdhc_clk stuff */
448static struct clk sdhc_clk[];
449
450static struct clk *clk_sdhc_parent(struct clk *clk)
451{
452 u32 aprb;
453 u8 sel;
454 u32 mask;
455 int offset;
456
457 aprb = __raw_readl(MXC_CRMAP_APRB);
458
459 switch (clk->id) {
460 case 0:
461 mask = MXC_CRMAP_APRB_SDHC1_ISEL_MASK;
462 offset = MXC_CRMAP_APRB_SDHC1_ISEL_OFFSET;
463 break;
464 case 1:
465 mask = MXC_CRMAP_APRB_SDHC2_ISEL_MASK;
466 offset = MXC_CRMAP_APRB_SDHC2_ISEL_OFFSET;
467 break;
468 default:
469 BUG();
470 }
471 sel = (aprb & mask) >> offset;
472
473 switch (sel) {
474 case 0:
475 return &ckih_clk;
476 case 1:
477 return &ckih_x2_clk;
478 }
479 return &usb_clk;
480}
481
482static unsigned long clk_sdhc_get_rate(struct clk *clk)
483{
484 u32 div;
485
486 switch (clk->id) {
487 case 0:
488 div = CRM_SMALL_DIVIDER(MXC_CRMAP_APRB, SDHC1_DIV);
489 break;
490 case 1:
491 div = CRM_SMALL_DIVIDER(MXC_CRMAP_APRB, SDHC2_DIV);
492 break;
493 default:
494 BUG();
495 }
496
497 return clk_get_rate(clk->parent) / div;
498}
499
500static int clk_sdhc_enable(struct clk *clk)
501{
502 u32 amlpmre1, aprb;
503
504 amlpmre1 = __raw_readl(MXC_CRMAP_AMLPMRE1);
505 aprb = __raw_readl(MXC_CRMAP_APRB);
506 switch (clk->id) {
507 case 0:
508 amlpmre1 |= (0x7 << MXC_CRMAP_AMLPMRE1_MLPME4_OFFSET);
509 aprb |= (0x1 << MXC_CRMAP_APRB_SDHC1EN_OFFSET);
510 break;
511 case 1:
512 amlpmre1 |= (0x7 << MXC_CRMAP_AMLPMRE1_MLPME5_OFFSET);
513 aprb |= (0x1 << MXC_CRMAP_APRB_SDHC2EN_OFFSET);
514 break;
515 }
516 __raw_writel(amlpmre1, MXC_CRMAP_AMLPMRE1);
517 __raw_writel(aprb, MXC_CRMAP_APRB);
518 return 0;
519}
520
521static void clk_sdhc_disable(struct clk *clk)
522{
523 u32 amlpmre1, aprb;
524
525 amlpmre1 = __raw_readl(MXC_CRMAP_AMLPMRE1);
526 aprb = __raw_readl(MXC_CRMAP_APRB);
527 switch (clk->id) {
528 case 0:
529 amlpmre1 &= ~(0x7 << MXC_CRMAP_AMLPMRE1_MLPME4_OFFSET);
530 aprb &= ~(0x1 << MXC_CRMAP_APRB_SDHC1EN_OFFSET);
531 break;
532 case 1:
533 amlpmre1 &= ~(0x7 << MXC_CRMAP_AMLPMRE1_MLPME5_OFFSET);
534 aprb &= ~(0x1 << MXC_CRMAP_APRB_SDHC2EN_OFFSET);
535 break;
536 }
537 __raw_writel(amlpmre1, MXC_CRMAP_AMLPMRE1);
538 __raw_writel(aprb, MXC_CRMAP_APRB);
539}
540
541static struct clk sdhc_clk[] = {
542 {
543 .id = 0,
544 .get_rate = clk_sdhc_get_rate,
545 .enable = clk_sdhc_enable,
546 .disable = clk_sdhc_disable,
547 }, {
548 .id = 1,
549 .get_rate = clk_sdhc_get_rate,
550 .enable = clk_sdhc_enable,
551 .disable = clk_sdhc_disable,
552 },
553};
554/* sdhc_clk stuff end */
555
556/* wdog_clk stuff */
557static struct clk wdog_clk[] = {
558 {
559 .id = 0,
560 .parent = &ipg_clk,
561 .enable_reg = MXC_CRMAP_AMLPMRD,
562 .enable_shift = MXC_CRMAP_AMLPMRD_MLPMD7_OFFSET,
563 .enable = _clk_3bit_enable,
564 .disable = _clk_3bit_disable,
565 }, {
566 .id = 1,
567 .parent = &ipg_clk,
568 .enable_reg = MXC_CRMAP_AMLPMRD,
569 .enable_shift = MXC_CRMAP_AMLPMRD_MLPMD3_OFFSET,
570 .enable = _clk_3bit_enable,
571 .disable = _clk_3bit_disable,
572 },
573};
574/* wdog_clk stuff end */
575
576/* gpt_clk stuff */
577static struct clk gpt_clk = {
578 .parent = &ipg_clk,
579 .enable_reg = MXC_CRMAP_AMLPMRC,
580 .enable_shift = MXC_CRMAP_AMLPMRC_MLPMC4_OFFSET,
581 .enable = _clk_3bit_enable,
582 .disable = _clk_3bit_disable,
583};
584/* gpt_clk stuff end */
585
586/* cspi_clk stuff */
587static struct clk cspi_clk[] = {
588 {
589 .id = 0,
590 .parent = &ipg_clk,
591 .enable_reg = MXC_CRMAP_AMLPMRE2,
592 .enable_shift = MXC_CRMAP_AMLPMRE2_MLPME0_OFFSET,
593 .enable = _clk_3bit_enable,
594 .disable = _clk_3bit_disable,
595 }, {
596 .id = 1,
597 .parent = &ipg_clk,
598 .enable_reg = MXC_CRMAP_AMLPMRE1,
599 .enable_shift = MXC_CRMAP_AMLPMRE1_MLPME6_OFFSET,
600 .enable = _clk_3bit_enable,
601 .disable = _clk_3bit_disable,
602 },
603};
604/* cspi_clk stuff end */
605
606#define _REGISTER_CLOCK(d, n, c) \
607 { \
608 .dev_id = d, \
609 .con_id = n, \
610 .clk = &c, \
611 },
612
613static struct clk_lookup lookups[] = {
614 _REGISTER_CLOCK("imx-uart.0", NULL, uart_clk[0])
615 _REGISTER_CLOCK("imx-uart.1", NULL, uart_clk[1])
616 _REGISTER_CLOCK("imx-uart.2", NULL, uart_clk[2])
617 _REGISTER_CLOCK("mxc-mmc.0", NULL, sdhc_clk[0])
618 _REGISTER_CLOCK("mxc-mmc.1", NULL, sdhc_clk[1])
619 _REGISTER_CLOCK("mxc-wdt.0", NULL, wdog_clk[0])
620 _REGISTER_CLOCK("spi_imx.0", NULL, cspi_clk[0])
621 _REGISTER_CLOCK("spi_imx.1", NULL, cspi_clk[1])
622};
623
624int __init mxc91231_clocks_init(unsigned long fref)
625{
626 void __iomem *gpt_base;
627
628 ckih_rate = fref;
629
630 usb_clk.parent = clk_usb_parent(&usb_clk);
631 sdhc_clk[0].parent = clk_sdhc_parent(&sdhc_clk[0]);
632 sdhc_clk[1].parent = clk_sdhc_parent(&sdhc_clk[1]);
633
634 clkdev_add_table(lookups, ARRAY_SIZE(lookups));
635
636 gpt_base = MXC91231_IO_ADDRESS(MXC91231_GPT1_BASE_ADDR);
637 mxc_timer_init(&gpt_clk, gpt_base, MXC91231_INT_GPT);
638
639 return 0;
640}
diff --git a/arch/arm/mach-mxc91231/crm_regs.h b/arch/arm/mach-mxc91231/crm_regs.h
deleted file mode 100644
index b989baccd675..000000000000
--- a/arch/arm/mach-mxc91231/crm_regs.h
+++ /dev/null
@@ -1,394 +0,0 @@
1/*
2 * Copyright 2006 Freescale Semiconductor, Inc.
3 * Copyright 2006-2007 Motorola, Inc.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16#ifndef _ARCH_ARM_MACH_MXC91231_CRM_REGS_H_
17#define _ARCH_ARM_MACH_MXC91231_CRM_REGS_H_
18
19#define CKIL_CLK_FREQ 32768
20
21#define MXC_CRM_AP_BASE MXC91231_IO_ADDRESS(MXC91231_CRM_AP_BASE_ADDR)
22#define MXC_CRM_COM_BASE MXC91231_IO_ADDRESS(MXC91231_CRM_COM_BASE_ADDR)
23#define MXC_DSM_BASE MXC91231_IO_ADDRESS(MXC91231_DSM_BASE_ADDR)
24#define MXC_PLL0_BASE MXC91231_IO_ADDRESS(MXC91231_PLL0_BASE_ADDR)
25#define MXC_PLL1_BASE MXC91231_IO_ADDRESS(MXC91231_PLL1_BASE_ADDR)
26#define MXC_PLL2_BASE MXC91231_IO_ADDRESS(MXC91231_PLL2_BASE_ADDR)
27#define MXC_CLKCTL_BASE MXC91231_IO_ADDRESS(MXC91231_CLKCTL_BASE_ADDR)
28
29/* PLL Register Offsets */
30#define MXC_PLL_DP_CTL 0x00
31#define MXC_PLL_DP_CONFIG 0x04
32#define MXC_PLL_DP_OP 0x08
33#define MXC_PLL_DP_MFD 0x0C
34#define MXC_PLL_DP_MFN 0x10
35#define MXC_PLL_DP_HFS_OP 0x1C
36#define MXC_PLL_DP_HFS_MFD 0x20
37#define MXC_PLL_DP_HFS_MFN 0x24
38
39/* PLL Register Bit definitions */
40#define MXC_PLL_DP_CTL_DPDCK0_2_EN 0x1000
41#define MXC_PLL_DP_CTL_ADE 0x800
42#define MXC_PLL_DP_CTL_REF_CLK_DIV 0x400
43#define MXC_PLL_DP_CTL_HFSM 0x80
44#define MXC_PLL_DP_CTL_PRE 0x40
45#define MXC_PLL_DP_CTL_UPEN 0x20
46#define MXC_PLL_DP_CTL_RST 0x10
47#define MXC_PLL_DP_CTL_RCP 0x8
48#define MXC_PLL_DP_CTL_PLM 0x4
49#define MXC_PLL_DP_CTL_BRM0 0x2
50#define MXC_PLL_DP_CTL_LRF 0x1
51
52#define MXC_PLL_DP_OP_MFI_OFFSET 4
53#define MXC_PLL_DP_OP_MFI_MASK 0xF
54#define MXC_PLL_DP_OP_PDF_OFFSET 0
55#define MXC_PLL_DP_OP_PDF_MASK 0xF
56
57#define MXC_PLL_DP_MFD_OFFSET 0
58#define MXC_PLL_DP_MFD_MASK 0x7FFFFFF
59
60#define MXC_PLL_DP_MFN_OFFSET 0
61#define MXC_PLL_DP_MFN_MASK 0x7FFFFFF
62
63/* CRM AP Register Offsets */
64#define MXC_CRMAP_ASCSR (MXC_CRM_AP_BASE + 0x00)
65#define MXC_CRMAP_ACDR (MXC_CRM_AP_BASE + 0x04)
66#define MXC_CRMAP_ACDER1 (MXC_CRM_AP_BASE + 0x08)
67#define MXC_CRMAP_ACDER2 (MXC_CRM_AP_BASE + 0x0C)
68#define MXC_CRMAP_ACGCR (MXC_CRM_AP_BASE + 0x10)
69#define MXC_CRMAP_ACCGCR (MXC_CRM_AP_BASE + 0x14)
70#define MXC_CRMAP_AMLPMRA (MXC_CRM_AP_BASE + 0x18)
71#define MXC_CRMAP_AMLPMRB (MXC_CRM_AP_BASE + 0x1C)
72#define MXC_CRMAP_AMLPMRC (MXC_CRM_AP_BASE + 0x20)
73#define MXC_CRMAP_AMLPMRD (MXC_CRM_AP_BASE + 0x24)
74#define MXC_CRMAP_AMLPMRE1 (MXC_CRM_AP_BASE + 0x28)
75#define MXC_CRMAP_AMLPMRE2 (MXC_CRM_AP_BASE + 0x2C)
76#define MXC_CRMAP_AMLPMRF (MXC_CRM_AP_BASE + 0x30)
77#define MXC_CRMAP_AMLPMRG (MXC_CRM_AP_BASE + 0x34)
78#define MXC_CRMAP_APGCR (MXC_CRM_AP_BASE + 0x38)
79#define MXC_CRMAP_ACSR (MXC_CRM_AP_BASE + 0x3C)
80#define MXC_CRMAP_ADCR (MXC_CRM_AP_BASE + 0x40)
81#define MXC_CRMAP_ACR (MXC_CRM_AP_BASE + 0x44)
82#define MXC_CRMAP_AMCR (MXC_CRM_AP_BASE + 0x48)
83#define MXC_CRMAP_APCR (MXC_CRM_AP_BASE + 0x4C)
84#define MXC_CRMAP_AMORA (MXC_CRM_AP_BASE + 0x50)
85#define MXC_CRMAP_AMORB (MXC_CRM_AP_BASE + 0x54)
86#define MXC_CRMAP_AGPR (MXC_CRM_AP_BASE + 0x58)
87#define MXC_CRMAP_APRA (MXC_CRM_AP_BASE + 0x5C)
88#define MXC_CRMAP_APRB (MXC_CRM_AP_BASE + 0x60)
89#define MXC_CRMAP_APOR (MXC_CRM_AP_BASE + 0x64)
90#define MXC_CRMAP_ADFMR (MXC_CRM_AP_BASE + 0x68)
91
92/* CRM AP Register Bit definitions */
93#define MXC_CRMAP_ASCSR_CRS 0x10000
94#define MXC_CRMAP_ASCSR_AP_PATDIV2_OFFSET 15
95#define MXC_CRMAP_ASCSR_AP_PATREF_DIV2 0x8000
96#define MXC_CRMAP_ASCSR_USBSEL_OFFSET 13
97#define MXC_CRMAP_ASCSR_USBSEL_MASK (0x3 << 13)
98#define MXC_CRMAP_ASCSR_CSISEL_OFFSET 11
99#define MXC_CRMAP_ASCSR_CSISEL_MASK (0x3 << 11)
100#define MXC_CRMAP_ASCSR_SSI2SEL_OFFSET 7
101#define MXC_CRMAP_ASCSR_SSI2SEL_MASK (0x3 << 7)
102#define MXC_CRMAP_ASCSR_SSI1SEL_OFFSET 5
103#define MXC_CRMAP_ASCSR_SSI1SEL_MASK (0x3 << 5)
104#define MXC_CRMAP_ASCSR_APSEL_OFFSET 3
105#define MXC_CRMAP_ASCSR_APSEL_MASK (0x3 << 3)
106#define MXC_CRMAP_ASCSR_AP_PATDIV1_OFFSET 2
107#define MXC_CRMAP_ASCSR_AP_PATREF_DIV1 0x4
108#define MXC_CRMAP_ASCSR_APISEL 0x1
109
110#define MXC_CRMAP_ACDR_ARMDIV_OFFSET 8
111#define MXC_CRMAP_ACDR_ARMDIV_MASK (0xF << 8)
112#define MXC_CRMAP_ACDR_AHBDIV_OFFSET 4
113#define MXC_CRMAP_ACDR_AHBDIV_MASK (0xF << 4)
114#define MXC_CRMAP_ACDR_IPDIV_OFFSET 0
115#define MXC_CRMAP_ACDR_IPDIV_MASK 0xF
116
117#define MXC_CRMAP_ACDER1_CSIEN_OFFSET 30
118#define MXC_CRMAP_ACDER1_CSIDIV_OFFSET 24
119#define MXC_CRMAP_ACDER1_CSIDIV_MASK (0x3F << 24)
120#define MXC_CRMAP_ACDER1_SSI2EN_OFFSET 14
121#define MXC_CRMAP_ACDER1_SSI2DIV_OFFSET 8
122#define MXC_CRMAP_ACDER1_SSI2DIV_MASK (0x3F << 8)
123#define MXC_CRMAP_ACDER1_SSI1EN_OFFSET 6
124#define MXC_CRMAP_ACDER1_SSI1DIV_OFFSET 0
125#define MXC_CRMAP_ACDER1_SSI1DIV_MASK 0x3F
126
127#define MXC_CRMAP_ACDER2_CRCT_CLK_DIV_OFFSET 24
128#define MXC_CRMAP_ACDER2_CRCT_CLK_DIV_MASK (0x7 << 24)
129#define MXC_CRMAP_ACDER2_NFCEN_OFFSET 20
130#define MXC_CRMAP_ACDER2_NFCDIV_OFFSET 16
131#define MXC_CRMAP_ACDER2_NFCDIV_MASK (0xF << 16)
132#define MXC_CRMAP_ACDER2_USBEN_OFFSET 12
133#define MXC_CRMAP_ACDER2_USBDIV_OFFSET 8
134#define MXC_CRMAP_ACDER2_USBDIV_MASK (0xF << 8)
135#define MXC_CRMAP_ACDER2_BAUD_ISEL_OFFSET 5
136#define MXC_CRMAP_ACDER2_BAUD_ISEL_MASK (0x3 << 5)
137#define MXC_CRMAP_ACDER2_BAUDDIV_OFFSET 0
138#define MXC_CRMAP_ACDER2_BAUDDIV_MASK 0xF
139
140#define MXC_CRMAP_AMLPMRA_MLPMA7_OFFSET 22
141#define MXC_CRMAP_AMLPMRA_MLPMA7_MASK (0x7 << 22)
142#define MXC_CRMAP_AMLPMRA_MLPMA6_OFFSET 19
143#define MXC_CRMAP_AMLPMRA_MLPMA6_MASK (0x7 << 19)
144#define MXC_CRMAP_AMLPMRA_MLPMA4_OFFSET 12
145#define MXC_CRMAP_AMLPMRA_MLPMA4_MASK (0x7 << 12)
146#define MXC_CRMAP_AMLPMRA_MLPMA3_OFFSET 9
147#define MXC_CRMAP_AMLPMRA_MLPMA3_MASK (0x7 << 9)
148#define MXC_CRMAP_AMLPMRA_MLPMA2_OFFSET 6
149#define MXC_CRMAP_AMLPMRA_MLPMA2_MASK (0x7 << 6)
150#define MXC_CRMAP_AMLPMRA_MLPMA1_OFFSET 3
151#define MXC_CRMAP_AMLPMRA_MLPMA1_MASK (0x7 << 3)
152
153#define MXC_CRMAP_AMLPMRB_MLPMB0_OFFSET 0
154#define MXC_CRMAP_AMLPMRB_MLPMB0_MASK 0x7
155
156#define MXC_CRMAP_AMLPMRC_MLPMC9_OFFSET 28
157#define MXC_CRMAP_AMLPMRC_MLPMC9_MASK (0x7 << 28)
158#define MXC_CRMAP_AMLPMRC_MLPMC7_OFFSET 22
159#define MXC_CRMAP_AMLPMRC_MLPMC7_MASK (0x7 << 22)
160#define MXC_CRMAP_AMLPMRC_MLPMC5_OFFSET 16
161#define MXC_CRMAP_AMLPMRC_MLPMC5_MASK (0x7 << 16)
162#define MXC_CRMAP_AMLPMRC_MLPMC4_OFFSET 12
163#define MXC_CRMAP_AMLPMRC_MLPMC4_MASK (0x7 << 12)
164#define MXC_CRMAP_AMLPMRC_MLPMC3_OFFSET 9
165#define MXC_CRMAP_AMLPMRC_MLPMC3_MASK (0x7 << 9)
166#define MXC_CRMAP_AMLPMRC_MLPMC2_OFFSET 6
167#define MXC_CRMAP_AMLPMRC_MLPMC2_MASK (0x7 << 6)
168#define MXC_CRMAP_AMLPMRC_MLPMC1_OFFSET 3
169#define MXC_CRMAP_AMLPMRC_MLPMC1_MASK (0x7 << 3)
170#define MXC_CRMAP_AMLPMRC_MLPMC0_OFFSET 0
171#define MXC_CRMAP_AMLPMRC_MLPMC0_MASK 0x7
172
173#define MXC_CRMAP_AMLPMRD_MLPMD7_OFFSET 22
174#define MXC_CRMAP_AMLPMRD_MLPMD7_MASK (0x7 << 22)
175#define MXC_CRMAP_AMLPMRD_MLPMD4_OFFSET 12
176#define MXC_CRMAP_AMLPMRD_MLPMD4_MASK (0x7 << 12)
177#define MXC_CRMAP_AMLPMRD_MLPMD3_OFFSET 9
178#define MXC_CRMAP_AMLPMRD_MLPMD3_MASK (0x7 << 9)
179#define MXC_CRMAP_AMLPMRD_MLPMD2_OFFSET 6
180#define MXC_CRMAP_AMLPMRD_MLPMD2_MASK (0x7 << 6)
181#define MXC_CRMAP_AMLPMRD_MLPMD0_OFFSET 0
182#define MXC_CRMAP_AMLPMRD_MLPMD0_MASK 0x7
183
184#define MXC_CRMAP_AMLPMRE1_MLPME9_OFFSET 28
185#define MXC_CRMAP_AMLPMRE1_MLPME9_MASK (0x7 << 28)
186#define MXC_CRMAP_AMLPMRE1_MLPME8_OFFSET 25
187#define MXC_CRMAP_AMLPMRE1_MLPME8_MASK (0x7 << 25)
188#define MXC_CRMAP_AMLPMRE1_MLPME7_OFFSET 22
189#define MXC_CRMAP_AMLPMRE1_MLPME7_MASK (0x7 << 22)
190#define MXC_CRMAP_AMLPMRE1_MLPME6_OFFSET 19
191#define MXC_CRMAP_AMLPMRE1_MLPME6_MASK (0x7 << 19)
192#define MXC_CRMAP_AMLPMRE1_MLPME5_OFFSET 16
193#define MXC_CRMAP_AMLPMRE1_MLPME5_MASK (0x7 << 16)
194#define MXC_CRMAP_AMLPMRE1_MLPME4_OFFSET 12
195#define MXC_CRMAP_AMLPMRE1_MLPME4_MASK (0x7 << 12)
196#define MXC_CRMAP_AMLPMRE1_MLPME3_OFFSET 9
197#define MXC_CRMAP_AMLPMRE1_MLPME3_MASK (0x7 << 9)
198#define MXC_CRMAP_AMLPMRE1_MLPME2_OFFSET 6
199#define MXC_CRMAP_AMLPMRE1_MLPME2_MASK (0x7 << 6)
200#define MXC_CRMAP_AMLPMRE1_MLPME1_OFFSET 3
201#define MXC_CRMAP_AMLPMRE1_MLPME1_MASK (0x7 << 3)
202#define MXC_CRMAP_AMLPMRE1_MLPME0_OFFSET 0
203#define MXC_CRMAP_AMLPMRE1_MLPME0_MASK 0x7
204
205#define MXC_CRMAP_AMLPMRE2_MLPME0_OFFSET 0
206#define MXC_CRMAP_AMLPMRE2_MLPME0_MASK 0x7
207
208#define MXC_CRMAP_AMLPMRF_MLPMF6_OFFSET 19
209#define MXC_CRMAP_AMLPMRF_MLPMF6_MASK (0x7 << 19)
210#define MXC_CRMAP_AMLPMRF_MLPMF5_OFFSET 16
211#define MXC_CRMAP_AMLPMRF_MLPMF5_MASK (0x7 << 16)
212#define MXC_CRMAP_AMLPMRF_MLPMF3_OFFSET 9
213#define MXC_CRMAP_AMLPMRF_MLPMF3_MASK (0x7 << 9)
214#define MXC_CRMAP_AMLPMRF_MLPMF2_OFFSET 6
215#define MXC_CRMAP_AMLPMRF_MLPMF2_MASK (0x7 << 6)
216#define MXC_CRMAP_AMLPMRF_MLPMF1_OFFSET 3
217#define MXC_CRMAP_AMLPMRF_MLPMF1_MASK (0x7 << 3)
218#define MXC_CRMAP_AMLPMRF_MLPMF0_OFFSET 0
219#define MXC_CRMAP_AMLPMRF_MLPMF0_MASK (0x7 << 0)
220
221#define MXC_CRMAP_AMLPMRG_MLPMG9_OFFSET 28
222#define MXC_CRMAP_AMLPMRG_MLPMG9_MASK (0x7 << 28)
223#define MXC_CRMAP_AMLPMRG_MLPMG7_OFFSET 22
224#define MXC_CRMAP_AMLPMRG_MLPMG7_MASK (0x7 << 22)
225#define MXC_CRMAP_AMLPMRG_MLPMG6_OFFSET 19
226#define MXC_CRMAP_AMLPMRG_MLPMG6_MASK (0x7 << 19)
227#define MXC_CRMAP_AMLPMRG_MLPMG5_OFFSET 16
228#define MXC_CRMAP_AMLPMRG_MLPMG5_MASK (0x7 << 16)
229#define MXC_CRMAP_AMLPMRG_MLPMG4_OFFSET 12
230#define MXC_CRMAP_AMLPMRG_MLPMG4_MASK (0x7 << 12)
231#define MXC_CRMAP_AMLPMRG_MLPMG3_OFFSET 9
232#define MXC_CRMAP_AMLPMRG_MLPMG3_MASK (0x7 << 9)
233#define MXC_CRMAP_AMLPMRG_MLPMG2_OFFSET 6
234#define MXC_CRMAP_AMLPMRG_MLPMG2_MASK (0x7 << 6)
235#define MXC_CRMAP_AMLPMRG_MLPMG1_OFFSET 3
236#define MXC_CRMAP_AMLPMRG_MLPMG1_MASK (0x7 << 3)
237#define MXC_CRMAP_AMLPMRG_MLPMG0_OFFSET 0
238#define MXC_CRMAP_AMLPMRG_MLPMG0_MASK 0x7
239
240#define MXC_CRMAP_AGPR_IPUPAD_OFFSET 20
241#define MXC_CRMAP_AGPR_IPUPAD_MASK (0x7 << 20)
242
243#define MXC_CRMAP_APRA_EL1TEN_OFFSET 29
244#define MXC_CRMAP_APRA_SIMEN_OFFSET 24
245#define MXC_CRMAP_APRA_UART3DIV_OFFSET 17
246#define MXC_CRMAP_APRA_UART3DIV_MASK (0xF << 17)
247#define MXC_CRMAP_APRA_UART3EN_OFFSET 16
248#define MXC_CRMAP_APRA_SAHARA_DIV2_CLKEN_OFFSET 14
249#define MXC_CRMAP_APRA_MQSPIEN_OFFSET 13
250#define MXC_CRMAP_APRA_UART2EN_OFFSET 8
251#define MXC_CRMAP_APRA_UART1EN_OFFSET 0
252
253#define MXC_CRMAP_APRB_SDHC2_ISEL_OFFSET 13
254#define MXC_CRMAP_APRB_SDHC2_ISEL_MASK (0x7 << 13)
255#define MXC_CRMAP_APRB_SDHC2_DIV_OFFSET 9
256#define MXC_CRMAP_APRB_SDHC2_DIV_MASK (0xF << 9)
257#define MXC_CRMAP_APRB_SDHC2EN_OFFSET 8
258#define MXC_CRMAP_APRB_SDHC1_ISEL_OFFSET 5
259#define MXC_CRMAP_APRB_SDHC1_ISEL_MASK (0x7 << 5)
260#define MXC_CRMAP_APRB_SDHC1_DIV_OFFSET 1
261#define MXC_CRMAP_APRB_SDHC1_DIV_MASK (0xF << 1)
262#define MXC_CRMAP_APRB_SDHC1EN_OFFSET 0
263
264#define MXC_CRMAP_ACSR_ADS_OFFSET 8
265#define MXC_CRMAP_ACSR_ADS (0x1 << 8)
266#define MXC_CRMAP_ACSR_ACS 0x1
267
268#define MXC_CRMAP_ADCR_LFDF_0 (0x0 << 8)
269#define MXC_CRMAP_ADCR_LFDF_2 (0x1 << 8)
270#define MXC_CRMAP_ADCR_LFDF_4 (0x2 << 8)
271#define MXC_CRMAP_ADCR_LFDF_8 (0x3 << 8)
272#define MXC_CRMAP_ADCR_LFDF_OFFSET 8
273#define MXC_CRMAP_ADCR_LFDF_MASK (0x3 << 8)
274#define MXC_CRMAP_ADCR_ALT_PLL 0x80
275#define MXC_CRMAP_ADCR_DFS_DIVEN 0x20
276#define MXC_CRMAP_ADCR_DIV_BYP 0x2
277#define MXC_CRMAP_ADCR_VSTAT 0x8
278#define MXC_CRMAP_ADCR_TSTAT 0x10
279#define MXC_CRMAP_ADCR_DVFS_VCTRL 0x10
280#define MXC_CRMAP_ADCR_CLK_ON 0x40
281
282#define MXC_CRMAP_ADFMR_FC_OFFSET 16
283#define MXC_CRMAP_ADFMR_FC_MASK (0x1F << 16)
284#define MXC_CRMAP_ADFMR_MF_OFFSET 1
285#define MXC_CRMAP_ADFMR_MF_MASK (0x3FF << 1)
286#define MXC_CRMAP_ADFMR_DFM_CLK_READY 0x1
287#define MXC_CRMAP_ADFMR_DFM_PWR_DOWN 0x8000
288
289#define MXC_CRMAP_ACR_CKOHS_HIGH (1 << 18)
290#define MXC_CRMAP_ACR_CKOS_HIGH (1 << 16)
291#define MXC_CRMAP_ACR_CKOHS_MASK (0x7 << 12)
292#define MXC_CRMAP_ACR_CKOHD (1 << 11)
293#define MXC_CRMAP_ACR_CKOHDIV_MASK (0xF << 8)
294#define MXC_CRMAP_ACR_CKOHDIV_OFFSET 8
295#define MXC_CRMAP_ACR_CKOD (1 << 7)
296#define MXC_CRMAP_ACR_CKOS_MASK (0x7 << 4)
297
298/* AP Warm reset */
299#define MXC_CRMAP_AMCR_SW_AP (1 << 14)
300
301/* Bit definitions of ACGCR in CRM_AP for tree level clock gating */
302#define MXC_CRMAP_ACGCR_ACG0_STOP_WAIT 0x00000001
303#define MXC_CRMAP_ACGCR_ACG0_STOP 0x00000003
304#define MXC_CRMAP_ACGCR_ACG0_RUN 0x00000007
305#define MXC_CRMAP_ACGCR_ACG0_DISABLED 0x00000000
306
307#define MXC_CRMAP_ACGCR_ACG1_STOP_WAIT 0x00000008
308#define MXC_CRMAP_ACGCR_ACG1_STOP 0x00000018
309#define MXC_CRMAP_ACGCR_ACG1_RUN 0x00000038
310#define MXC_CRMAP_ACGCR_ACG1_DISABLED 0x00000000
311
312#define MXC_CRMAP_ACGCR_ACG2_STOP_WAIT 0x00000040
313#define MXC_CRMAP_ACGCR_ACG2_STOP 0x000000C0
314#define MXC_CRMAP_ACGCR_ACG2_RUN 0x000001C0
315#define MXC_CRMAP_ACGCR_ACG2_DISABLED 0x00000000
316
317#define MXC_CRMAP_ACGCR_ACG3_STOP_WAIT 0x00000200
318#define MXC_CRMAP_ACGCR_ACG3_STOP 0x00000600
319#define MXC_CRMAP_ACGCR_ACG3_RUN 0x00000E00
320#define MXC_CRMAP_ACGCR_ACG3_DISABLED 0x00000000
321
322#define MXC_CRMAP_ACGCR_ACG4_STOP_WAIT 0x00001000
323#define MXC_CRMAP_ACGCR_ACG4_STOP 0x00003000
324#define MXC_CRMAP_ACGCR_ACG4_RUN 0x00007000
325#define MXC_CRMAP_ACGCR_ACG4_DISABLED 0x00000000
326
327#define MXC_CRMAP_ACGCR_ACG5_STOP_WAIT 0x00010000
328#define MXC_CRMAP_ACGCR_ACG5_STOP 0x00030000
329#define MXC_CRMAP_ACGCR_ACG5_RUN 0x00070000
330#define MXC_CRMAP_ACGCR_ACG5_DISABLED 0x00000000
331
332#define MXC_CRMAP_ACGCR_ACG6_STOP_WAIT 0x00080000
333#define MXC_CRMAP_ACGCR_ACG6_STOP 0x00180000
334#define MXC_CRMAP_ACGCR_ACG6_RUN 0x00380000
335#define MXC_CRMAP_ACGCR_ACG6_DISABLED 0x00000000
336
337#define NUM_GATE_CTRL 6
338
339/* CRM COM Register Offsets */
340#define MXC_CRMCOM_CSCR (MXC_CRM_COM_BASE + 0x0C)
341#define MXC_CRMCOM_CCCR (MXC_CRM_COM_BASE + 0x10)
342
343/* CRM COM Bit Definitions */
344#define MXC_CRMCOM_CSCR_PPD1 0x08000000
345#define MXC_CRMCOM_CSCR_CKOHSEL (1 << 18)
346#define MXC_CRMCOM_CSCR_CKOSEL (1 << 17)
347#define MXC_CRMCOM_CCCR_CC_DIV_OFFSET 8
348#define MXC_CRMCOM_CCCR_CC_DIV_MASK (0x1F << 8)
349#define MXC_CRMCOM_CCCR_CC_SEL_OFFSET 0
350#define MXC_CRMCOM_CCCR_CC_SEL_MASK 0x3
351
352/* DSM Register Offsets */
353#define MXC_DSM_SLEEP_TIME (MXC_DSM_BASE + 0x0c)
354#define MXC_DSM_CONTROL0 (MXC_DSM_BASE + 0x20)
355#define MXC_DSM_CONTROL1 (MXC_DSM_BASE + 0x24)
356#define MXC_DSM_CTREN (MXC_DSM_BASE + 0x28)
357#define MXC_DSM_WARM_PER (MXC_DSM_BASE + 0x40)
358#define MXC_DSM_LOCK_PER (MXC_DSM_BASE + 0x44)
359#define MXC_DSM_MGPER (MXC_DSM_BASE + 0x4c)
360#define MXC_DSM_CRM_CONTROL (MXC_DSM_BASE + 0x50)
361
362/* Bit definitions of various registers in DSM */
363#define MXC_DSM_CRM_CTRL_DVFS_BYP 0x00000008
364#define MXC_DSM_CRM_CTRL_DVFS_VCTRL 0x00000004
365#define MXC_DSM_CRM_CTRL_LPMD1 0x00000002
366#define MXC_DSM_CRM_CTRL_LPMD0 0x00000001
367#define MXC_DSM_CRM_CTRL_LPMD_STOP_MODE 0x00000000
368#define MXC_DSM_CRM_CTRL_LPMD_WAIT_MODE 0x00000001
369#define MXC_DSM_CRM_CTRL_LPMD_RUN_MODE 0x00000003
370#define MXC_DSM_CONTROL0_STBY_COMMIT_EN 0x00000200
371#define MXC_DSM_CONTROL0_MSTR_EN 0x00000001
372#define MXC_DSM_CONTROL0_RESTART 0x00000010
373/* Counter Block reset */
374#define MXC_DSM_CONTROL1_CB_RST 0x00000002
375/* State Machine reset */
376#define MXC_DSM_CONTROL1_SM_RST 0x00000004
377/* Bit needed to reset counter block */
378#define MXC_CONTROL1_RST_CNT32 0x00000008
379#define MXC_DSM_CONTROL1_RST_CNT32_EN 0x00000800
380#define MXC_DSM_CONTROL1_SLEEP 0x00000100
381#define MXC_DSM_CONTROL1_WAKEUP_DISABLE 0x00004000
382#define MXC_DSM_CTREN_CNT32 0x00000001
383
384/* Magic Fix enable bit */
385#define MXC_DSM_MGPER_EN_MGFX 0x80000000
386#define MXC_DSM_MGPER_PER_MASK 0x000003FF
387#define MXC_DSM_MGPER_PER(n) (MXC_DSM_MGPER_PER_MASK & n)
388
389/* Address offsets of the CLKCTL registers */
390#define MXC_CLKCTL_GP_CTRL (MXC_CLKCTL_BASE + 0x00)
391#define MXC_CLKCTL_GP_SER (MXC_CLKCTL_BASE + 0x04)
392#define MXC_CLKCTL_GP_CER (MXC_CLKCTL_BASE + 0x08)
393
394#endif /* _ARCH_ARM_MACH_MXC91231_CRM_REGS_H_ */
diff --git a/arch/arm/mach-mxc91231/devices.c b/arch/arm/mach-mxc91231/devices.c
deleted file mode 100644
index 027af4f0d18a..000000000000
--- a/arch/arm/mach-mxc91231/devices.c
+++ /dev/null
@@ -1,251 +0,0 @@
1/*
2 * Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright 2008 Sascha Hauer, kernel@pengutronix.de
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin Street, Fifth Floor,
17 * Boston, MA 02110-1301, USA.
18 */
19
20#include <linux/module.h>
21#include <linux/platform_device.h>
22#include <linux/serial.h>
23#include <linux/gpio.h>
24#include <mach/hardware.h>
25#include <mach/irqs.h>
26#include <mach/imx-uart.h>
27
28static struct resource uart0[] = {
29 {
30 .start = MXC91231_UART1_BASE_ADDR,
31 .end = MXC91231_UART1_BASE_ADDR + 0x0B5,
32 .flags = IORESOURCE_MEM,
33 }, {
34 .start = MXC91231_INT_UART1_RX,
35 .end = MXC91231_INT_UART1_RX,
36 .flags = IORESOURCE_IRQ,
37 }, {
38 .start = MXC91231_INT_UART1_TX,
39 .end = MXC91231_INT_UART1_TX,
40 .flags = IORESOURCE_IRQ,
41 }, {
42 .start = MXC91231_INT_UART1_MINT,
43 .end = MXC91231_INT_UART1_MINT,
44 .flags = IORESOURCE_IRQ,
45 },
46};
47
48struct platform_device mxc_uart_device0 = {
49 .name = "imx-uart",
50 .id = 0,
51 .resource = uart0,
52 .num_resources = ARRAY_SIZE(uart0),
53};
54
55static struct resource uart1[] = {
56 {
57 .start = MXC91231_UART2_BASE_ADDR,
58 .end = MXC91231_UART2_BASE_ADDR + 0x0B5,
59 .flags = IORESOURCE_MEM,
60 }, {
61 .start = MXC91231_INT_UART2_RX,
62 .end = MXC91231_INT_UART2_RX,
63 .flags = IORESOURCE_IRQ,
64 }, {
65 .start = MXC91231_INT_UART2_TX,
66 .end = MXC91231_INT_UART2_TX,
67 .flags = IORESOURCE_IRQ,
68 }, {
69 .start = MXC91231_INT_UART2_MINT,
70 .end = MXC91231_INT_UART2_MINT,
71 .flags = IORESOURCE_IRQ,
72 },
73};
74
75struct platform_device mxc_uart_device1 = {
76 .name = "imx-uart",
77 .id = 1,
78 .resource = uart1,
79 .num_resources = ARRAY_SIZE(uart1),
80};
81
82static struct resource uart2[] = {
83 {
84 .start = MXC91231_UART3_BASE_ADDR,
85 .end = MXC91231_UART3_BASE_ADDR + 0x0B5,
86 .flags = IORESOURCE_MEM,
87 }, {
88 .start = MXC91231_INT_UART3_RX,
89 .end = MXC91231_INT_UART3_RX,
90 .flags = IORESOURCE_IRQ,
91 }, {
92 .start = MXC91231_INT_UART3_TX,
93 .end = MXC91231_INT_UART3_TX,
94 .flags = IORESOURCE_IRQ,
95 }, {
96 .start = MXC91231_INT_UART3_MINT,
97 .end = MXC91231_INT_UART3_MINT,
98 .flags = IORESOURCE_IRQ,
99
100 },
101};
102
103struct platform_device mxc_uart_device2 = {
104 .name = "imx-uart",
105 .id = 2,
106 .resource = uart2,
107 .num_resources = ARRAY_SIZE(uart2),
108};
109
110/* GPIO port description */
111static struct mxc_gpio_port mxc_gpio_ports[] = {
112 [0] = {
113 .chip.label = "gpio-0",
114 .base = MXC91231_IO_ADDRESS(MXC91231_GPIO1_AP_BASE_ADDR),
115 .irq = MXC91231_INT_GPIO1,
116 .virtual_irq_start = MXC_GPIO_IRQ_START,
117 },
118 [1] = {
119 .chip.label = "gpio-1",
120 .base = MXC91231_IO_ADDRESS(MXC91231_GPIO2_AP_BASE_ADDR),
121 .irq = MXC91231_INT_GPIO2,
122 .virtual_irq_start = MXC_GPIO_IRQ_START + 32,
123 },
124 [2] = {
125 .chip.label = "gpio-2",
126 .base = MXC91231_IO_ADDRESS(MXC91231_GPIO3_AP_BASE_ADDR),
127 .irq = MXC91231_INT_GPIO3,
128 .virtual_irq_start = MXC_GPIO_IRQ_START + 64,
129 },
130 [3] = {
131 .chip.label = "gpio-3",
132 .base = MXC91231_IO_ADDRESS(MXC91231_GPIO4_SH_BASE_ADDR),
133 .irq = MXC91231_INT_GPIO4,
134 .virtual_irq_start = MXC_GPIO_IRQ_START + 96,
135 },
136};
137
138int __init mxc91231_register_gpios(void)
139{
140 return mxc_gpio_init(mxc_gpio_ports, ARRAY_SIZE(mxc_gpio_ports));
141}
142
143static struct resource mxc_nand_resources[] = {
144 {
145 .start = MXC91231_NFC_BASE_ADDR,
146 .end = MXC91231_NFC_BASE_ADDR + 0xfff,
147 .flags = IORESOURCE_MEM
148 }, {
149 .start = MXC91231_INT_NANDFC,
150 .end = MXC91231_INT_NANDFC,
151 .flags = IORESOURCE_IRQ
152 },
153};
154
155struct platform_device mxc_nand_device = {
156 .name = "mxc_nand",
157 .id = 0,
158 .num_resources = ARRAY_SIZE(mxc_nand_resources),
159 .resource = mxc_nand_resources,
160};
161
162static struct resource mxc_sdhc0_resources[] = {
163 {
164 .start = MXC91231_MMC_SDHC1_BASE_ADDR,
165 .end = MXC91231_MMC_SDHC1_BASE_ADDR + SZ_16K - 1,
166 .flags = IORESOURCE_MEM,
167 }, {
168 .start = MXC91231_INT_MMC_SDHC1,
169 .end = MXC91231_INT_MMC_SDHC1,
170 .flags = IORESOURCE_IRQ,
171 },
172};
173
174static struct resource mxc_sdhc1_resources[] = {
175 {
176 .start = MXC91231_MMC_SDHC2_BASE_ADDR,
177 .end = MXC91231_MMC_SDHC2_BASE_ADDR + SZ_16K - 1,
178 .flags = IORESOURCE_MEM,
179 }, {
180 .start = MXC91231_INT_MMC_SDHC2,
181 .end = MXC91231_INT_MMC_SDHC2,
182 .flags = IORESOURCE_IRQ,
183 },
184};
185
186struct platform_device mxc_sdhc_device0 = {
187 .name = "mxc-mmc",
188 .id = 0,
189 .num_resources = ARRAY_SIZE(mxc_sdhc0_resources),
190 .resource = mxc_sdhc0_resources,
191};
192
193struct platform_device mxc_sdhc_device1 = {
194 .name = "mxc-mmc",
195 .id = 1,
196 .num_resources = ARRAY_SIZE(mxc_sdhc1_resources),
197 .resource = mxc_sdhc1_resources,
198};
199
200static struct resource mxc_cspi0_resources[] = {
201 {
202 .start = MXC91231_CSPI1_BASE_ADDR,
203 .end = MXC91231_CSPI1_BASE_ADDR + 0x20,
204 .flags = IORESOURCE_MEM,
205 }, {
206 .start = MXC91231_INT_CSPI1,
207 .end = MXC91231_INT_CSPI1,
208 .flags = IORESOURCE_IRQ,
209 },
210};
211
212struct platform_device mxc_cspi_device0 = {
213 .name = "spi_imx",
214 .id = 0,
215 .num_resources = ARRAY_SIZE(mxc_cspi0_resources),
216 .resource = mxc_cspi0_resources,
217};
218
219static struct resource mxc_cspi1_resources[] = {
220 {
221 .start = MXC91231_CSPI2_BASE_ADDR,
222 .end = MXC91231_CSPI2_BASE_ADDR + 0x20,
223 .flags = IORESOURCE_MEM,
224 }, {
225 .start = MXC91231_INT_CSPI2,
226 .end = MXC91231_INT_CSPI2,
227 .flags = IORESOURCE_IRQ,
228 },
229};
230
231struct platform_device mxc_cspi_device1 = {
232 .name = "spi_imx",
233 .id = 1,
234 .num_resources = ARRAY_SIZE(mxc_cspi1_resources),
235 .resource = mxc_cspi1_resources,
236};
237
238static struct resource mxc_wdog0_resources[] = {
239 {
240 .start = MXC91231_WDOG1_BASE_ADDR,
241 .end = MXC91231_WDOG1_BASE_ADDR + 0x10,
242 .flags = IORESOURCE_MEM,
243 },
244};
245
246struct platform_device mxc_wdog_device0 = {
247 .name = "mxc-wdt",
248 .id = 0,
249 .num_resources = ARRAY_SIZE(mxc_wdog0_resources),
250 .resource = mxc_wdog0_resources,
251};
diff --git a/arch/arm/mach-mxc91231/devices.h b/arch/arm/mach-mxc91231/devices.h
deleted file mode 100644
index 72a2136ce27d..000000000000
--- a/arch/arm/mach-mxc91231/devices.h
+++ /dev/null
@@ -1,13 +0,0 @@
1extern struct platform_device mxc_uart_device0;
2extern struct platform_device mxc_uart_device1;
3extern struct platform_device mxc_uart_device2;
4
5extern struct platform_device mxc_nand_device;
6
7extern struct platform_device mxc_sdhc_device0;
8extern struct platform_device mxc_sdhc_device1;
9
10extern struct platform_device mxc_cspi_device0;
11extern struct platform_device mxc_cspi_device1;
12
13extern struct platform_device mxc_wdog_device0;
diff --git a/arch/arm/mach-mxc91231/iomux.c b/arch/arm/mach-mxc91231/iomux.c
deleted file mode 100644
index 66fc41cbf2ca..000000000000
--- a/arch/arm/mach-mxc91231/iomux.c
+++ /dev/null
@@ -1,177 +0,0 @@
1/*
2 * Copyright 2004-2006 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de>
4 * Copyright (C) 2009 by Valentin Longchamp <valentin.longchamp@epfl.ch>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
18 * MA 02110-1301, USA.
19 */
20
21#include <linux/module.h>
22#include <linux/spinlock.h>
23#include <linux/io.h>
24#include <linux/kernel.h>
25#include <mach/hardware.h>
26#include <mach/gpio.h>
27#include <mach/iomux-mxc91231.h>
28
29/*
30 * IOMUX register (base) addresses
31 */
32#define IOMUX_AP_BASE MXC91231_IO_ADDRESS(MXC91231_IOMUX_AP_BASE_ADDR)
33#define IOMUX_COM_BASE MXC91231_IO_ADDRESS(MXC91231_IOMUX_COM_BASE_ADDR)
34#define IOMUXSW_AP_MUX_CTL (IOMUX_AP_BASE + 0x000)
35#define IOMUXSW_SP_MUX_CTL (IOMUX_COM_BASE + 0x000)
36#define IOMUXSW_PAD_CTL (IOMUX_COM_BASE + 0x200)
37
38#define IOMUXINT_OBS1 (IOMUX_AP_BASE + 0x600)
39#define IOMUXINT_OBS2 (IOMUX_AP_BASE + 0x004)
40
41static DEFINE_SPINLOCK(gpio_mux_lock);
42
43#define NB_PORTS ((PIN_MAX + 32) / 32)
44#define PIN_GLOBAL_NUM(pin) \
45 (((pin & MUX_SIDE_MASK) >> MUX_SIDE_SHIFT)*PIN_AP_MAX + \
46 ((pin & MUX_REG_MASK) >> MUX_REG_SHIFT)*4 + \
47 ((pin & MUX_FIELD_MASK) >> MUX_FIELD_SHIFT))
48
49unsigned long mxc_pin_alloc_map[NB_PORTS * 32 / BITS_PER_LONG];
50/*
51 * set the mode for a IOMUX pin.
52 */
53int mxc_iomux_mode(unsigned int pin_mode)
54{
55 u32 side, field, l, mode, ret = 0;
56 void __iomem *reg;
57
58 side = (pin_mode & MUX_SIDE_MASK) >> MUX_SIDE_SHIFT;
59 switch (side) {
60 case MUX_SIDE_AP:
61 reg = IOMUXSW_AP_MUX_CTL;
62 break;
63 case MUX_SIDE_SP:
64 reg = IOMUXSW_SP_MUX_CTL;
65 break;
66 default:
67 return -EINVAL;
68 }
69 reg += ((pin_mode & MUX_REG_MASK) >> MUX_REG_SHIFT) * 4;
70 field = (pin_mode & MUX_FIELD_MASK) >> MUX_FIELD_SHIFT;
71 mode = (pin_mode & MUX_MODE_MASK) >> MUX_MODE_SHIFT;
72
73 spin_lock(&gpio_mux_lock);
74
75 l = __raw_readl(reg);
76 l &= ~(0xff << (field * 8));
77 l |= mode << (field * 8);
78 __raw_writel(l, reg);
79
80 spin_unlock(&gpio_mux_lock);
81
82 return ret;
83}
84EXPORT_SYMBOL(mxc_iomux_mode);
85
86/*
87 * This function configures the pad value for a IOMUX pin.
88 */
89void mxc_iomux_set_pad(enum iomux_pins pin, u32 config)
90{
91 u32 padgrp, field, l;
92 void __iomem *reg;
93
94 padgrp = (pin & MUX_PADGRP_MASK) >> MUX_PADGRP_SHIFT;
95 reg = IOMUXSW_PAD_CTL + (pin + 2) / 3 * 4;
96 field = (pin + 2) % 3;
97
98 pr_debug("%s: reg offset = 0x%x, field = %d\n",
99 __func__, (pin + 2) / 3, field);
100
101 spin_lock(&gpio_mux_lock);
102
103 l = __raw_readl(reg);
104 l &= ~(0x1ff << (field * 10));
105 l |= config << (field * 10);
106 __raw_writel(l, reg);
107
108 spin_unlock(&gpio_mux_lock);
109}
110EXPORT_SYMBOL(mxc_iomux_set_pad);
111
112/*
113 * allocs a single pin:
114 * - reserves the pin so that it is not claimed by another driver
115 * - setups the iomux according to the configuration
116 */
117int mxc_iomux_alloc_pin(unsigned int pin_mode, const char *label)
118{
119 unsigned pad = PIN_GLOBAL_NUM(pin_mode);
120 if (pad >= (PIN_MAX + 1)) {
121 printk(KERN_ERR "mxc_iomux: Attempt to request nonexistant pin %u for \"%s\"\n",
122 pad, label ? label : "?");
123 return -EINVAL;
124 }
125
126 if (test_and_set_bit(pad, mxc_pin_alloc_map)) {
127 printk(KERN_ERR "mxc_iomux: pin %u already used. Allocation for \"%s\" failed\n",
128 pad, label ? label : "?");
129 return -EBUSY;
130 }
131 mxc_iomux_mode(pin_mode);
132
133 return 0;
134}
135EXPORT_SYMBOL(mxc_iomux_alloc_pin);
136
137int mxc_iomux_setup_multiple_pins(const unsigned int *pin_list, unsigned count,
138 const char *label)
139{
140 const unsigned int *p = pin_list;
141 int i;
142 int ret = -EINVAL;
143
144 for (i = 0; i < count; i++) {
145 ret = mxc_iomux_alloc_pin(*p, label);
146 if (ret)
147 goto setup_error;
148 p++;
149 }
150 return 0;
151
152setup_error:
153 mxc_iomux_release_multiple_pins(pin_list, i);
154 return ret;
155}
156EXPORT_SYMBOL(mxc_iomux_setup_multiple_pins);
157
158void mxc_iomux_release_pin(unsigned int pin_mode)
159{
160 unsigned pad = PIN_GLOBAL_NUM(pin_mode);
161
162 if (pad < (PIN_MAX + 1))
163 clear_bit(pad, mxc_pin_alloc_map);
164}
165EXPORT_SYMBOL(mxc_iomux_release_pin);
166
167void mxc_iomux_release_multiple_pins(const unsigned int *pin_list, int count)
168{
169 const unsigned int *p = pin_list;
170 int i;
171
172 for (i = 0; i < count; i++) {
173 mxc_iomux_release_pin(*p);
174 p++;
175 }
176}
177EXPORT_SYMBOL(mxc_iomux_release_multiple_pins);
diff --git a/arch/arm/mach-mxc91231/magx-zn5.c b/arch/arm/mach-mxc91231/magx-zn5.c
deleted file mode 100644
index f31a45e5a0b8..000000000000
--- a/arch/arm/mach-mxc91231/magx-zn5.c
+++ /dev/null
@@ -1,62 +0,0 @@
1/*
2 * Copyright 2009 Dmitriy Taychenachev <dimichxp@gmail.com>
3 *
4 * This file is released under the GPLv2 or later.
5 */
6
7#include <linux/irq.h>
8#include <linux/init.h>
9#include <linux/device.h>
10
11#include <asm/mach-types.h>
12#include <asm/mach/time.h>
13#include <asm/mach/arch.h>
14
15#include <mach/common.h>
16#include <mach/hardware.h>
17#include <mach/iomux-mxc91231.h>
18#include <mach/mmc.h>
19#include <mach/imx-uart.h>
20
21#include "devices.h"
22
23static struct imxuart_platform_data uart_pdata = {
24};
25
26static struct imxmmc_platform_data sdhc_pdata = {
27};
28
29static void __init zn5_init(void)
30{
31 pm_power_off = mxc91231_power_off;
32
33 mxc_iomux_alloc_pin(MXC91231_PIN_SP_USB_DAT_VP__RXD2, "uart2-rx");
34 mxc_iomux_alloc_pin(MXC91231_PIN_SP_USB_SE0_VM__TXD2, "uart2-tx");
35
36 mxc_register_device(&mxc_uart_device1, &uart_pdata);
37 mxc_register_device(&mxc_uart_device0, &uart_pdata);
38
39 mxc_register_device(&mxc_sdhc_device0, &sdhc_pdata);
40
41 mxc_register_device(&mxc_wdog_device0, NULL);
42
43 return;
44}
45
46static void __init zn5_timer_init(void)
47{
48 mxc91231_clocks_init(26000000); /* 26mhz ckih */
49}
50
51struct sys_timer zn5_timer = {
52 .init = zn5_timer_init,
53};
54
55MACHINE_START(MAGX_ZN5, "Motorola Zn5")
56 .boot_params = MXC91231_PHYS_OFFSET + 0x100,
57 .map_io = mxc91231_map_io,
58 .init_early = mxc91231_init_early,
59 .init_irq = mxc91231_init_irq,
60 .timer = &zn5_timer,
61 .init_machine = zn5_init,
62MACHINE_END
diff --git a/arch/arm/mach-mxc91231/mm.c b/arch/arm/mach-mxc91231/mm.c
deleted file mode 100644
index a77f6daf6a26..000000000000
--- a/arch/arm/mach-mxc91231/mm.c
+++ /dev/null
@@ -1,62 +0,0 @@
1/*
2 * Copyright (C) 1999,2000 Arm Limited
3 * Copyright (C) 2000 Deep Blue Solutions Ltd
4 * Copyright (C) 2002 Shane Nay (shane@minirl.com)
5 * Copyright 2004-2005 Freescale Semiconductor, Inc. All Rights Reserved.
6 * - add MXC specific definitions
7 * Copyright 2006 Motorola, Inc.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 */
19
20#include <linux/mm.h>
21#include <linux/init.h>
22#include <mach/hardware.h>
23#include <mach/common.h>
24#include <asm/pgtable.h>
25#include <asm/mach/map.h>
26
27/*
28 * This structure defines the MXC memory map.
29 */
30static struct map_desc mxc91231_io_desc[] __initdata = {
31 imx_map_entry(MXC91231, L2CC, MT_DEVICE),
32 imx_map_entry(MXC91231, X_MEMC, MT_DEVICE),
33 imx_map_entry(MXC91231, ROMP, MT_DEVICE),
34 imx_map_entry(MXC91231, AVIC, MT_DEVICE),
35 imx_map_entry(MXC91231, AIPS1, MT_DEVICE),
36 imx_map_entry(MXC91231, SPBA0, MT_DEVICE),
37 imx_map_entry(MXC91231, SPBA1, MT_DEVICE),
38 imx_map_entry(MXC91231, AIPS2, MT_DEVICE),
39};
40
41/*
42 * This function initializes the memory map. It is called during the
43 * system startup to create static physical to virtual memory map for
44 * the IO modules.
45 */
46void __init mxc91231_map_io(void)
47{
48 iotable_init(mxc91231_io_desc, ARRAY_SIZE(mxc91231_io_desc));
49}
50
51void __init mxc91231_init_early(void)
52{
53 mxc_set_cpu_type(MXC_CPU_MXC91231);
54}
55
56int mxc91231_register_gpios(void);
57
58void __init mxc91231_init_irq(void)
59{
60 mxc91231_register_gpios();
61 mxc_init_irq(MXC91231_IO_ADDRESS(MXC91231_AVIC_BASE_ADDR));
62}
diff --git a/arch/arm/mach-mxc91231/system.c b/arch/arm/mach-mxc91231/system.c
deleted file mode 100644
index 736f7efd874a..000000000000
--- a/arch/arm/mach-mxc91231/system.c
+++ /dev/null
@@ -1,51 +0,0 @@
1/*
2 * Copyright 2009 Dmitriy Taychenachev <dimichxp@gmail.com>
3 *
4 * This file is released under the GPLv2 or later.
5 */
6
7#include <linux/delay.h>
8#include <linux/io.h>
9
10#include <asm/proc-fns.h>
11#include <mach/hardware.h>
12
13#include "crm_regs.h"
14
15#define WDOG_WCR MXC91231_IO_ADDRESS(MXC91231_WDOG1_BASE_ADDR)
16#define WDOG_WCR_OUT_ENABLE (1 << 6)
17#define WDOG_WCR_ASSERT (1 << 5)
18
19void mxc91231_power_off(void)
20{
21 u16 wcr;
22
23 wcr = __raw_readw(WDOG_WCR);
24 wcr |= WDOG_WCR_OUT_ENABLE;
25 wcr &= ~WDOG_WCR_ASSERT;
26 __raw_writew(wcr, WDOG_WCR);
27}
28
29void mxc91231_arch_reset(char mode, const char *cmd)
30{
31 u32 amcr;
32
33 /* Reset the AP using CRM */
34 amcr = __raw_readl(MXC_CRMAP_AMCR);
35 amcr &= ~MXC_CRMAP_AMCR_SW_AP;
36 __raw_writel(amcr, MXC_CRMAP_AMCR);
37
38 mdelay(10);
39 cpu_reset(0);
40}
41
42void mxc91231_prepare_idle(void)
43{
44 u32 crm_ctl;
45
46 /* Go to WAIT mode after WFI */
47 crm_ctl = __raw_readl(MXC_DSM_CRM_CONTROL);
48 crm_ctl &= ~(MXC_DSM_CRM_CTRL_LPMD0 | MXC_DSM_CRM_CTRL_LPMD1);
49 crm_ctl |= MXC_DSM_CRM_CTRL_LPMD_WAIT_MODE;
50 __raw_writel(crm_ctl, MXC_DSM_CRM_CONTROL);
51}
diff --git a/arch/arm/plat-mxc/Kconfig b/arch/arm/plat-mxc/Kconfig
index b0cb4258e382..debd7be52450 100644
--- a/arch/arm/plat-mxc/Kconfig
+++ b/arch/arm/plat-mxc/Kconfig
@@ -30,13 +30,6 @@ config ARCH_MX3
30 help 30 help
31 This enables support for systems based on the Freescale i.MX3 family 31 This enables support for systems based on the Freescale i.MX3 family
32 32
33config ARCH_MXC91231
34 bool "MXC91231-based"
35 select CPU_V6
36 select MXC_AVIC
37 help
38 This enables support for systems based on the Freescale MXC91231 family
39
40config ARCH_MX5 33config ARCH_MX5
41 bool "MX5-based" 34 bool "MX5-based"
42 select CPU_V7 35 select CPU_V7
@@ -48,7 +41,6 @@ endchoice
48 41
49source "arch/arm/mach-imx/Kconfig" 42source "arch/arm/mach-imx/Kconfig"
50source "arch/arm/mach-mx3/Kconfig" 43source "arch/arm/mach-mx3/Kconfig"
51source "arch/arm/mach-mxc91231/Kconfig"
52source "arch/arm/mach-mx5/Kconfig" 44source "arch/arm/mach-mx5/Kconfig"
53 45
54endmenu 46endmenu
diff --git a/arch/arm/plat-mxc/include/mach/common.h b/arch/arm/plat-mxc/include/mach/common.h
index bfa1ffca5d79..da7991832af6 100644
--- a/arch/arm/plat-mxc/include/mach/common.h
+++ b/arch/arm/plat-mxc/include/mach/common.h
@@ -23,7 +23,6 @@ extern void mx35_map_io(void);
23extern void mx50_map_io(void); 23extern void mx50_map_io(void);
24extern void mx51_map_io(void); 24extern void mx51_map_io(void);
25extern void mx53_map_io(void); 25extern void mx53_map_io(void);
26extern void mxc91231_map_io(void);
27extern void imx1_init_early(void); 26extern void imx1_init_early(void);
28extern void imx21_init_early(void); 27extern void imx21_init_early(void);
29extern void imx25_init_early(void); 28extern void imx25_init_early(void);
@@ -33,7 +32,6 @@ extern void imx35_init_early(void);
33extern void imx50_init_early(void); 32extern void imx50_init_early(void);
34extern void imx51_init_early(void); 33extern void imx51_init_early(void);
35extern void imx53_init_early(void); 34extern void imx53_init_early(void);
36extern void mxc91231_init_early(void);
37extern void mxc_init_irq(void __iomem *); 35extern void mxc_init_irq(void __iomem *);
38extern void tzic_init_irq(void __iomem *); 36extern void tzic_init_irq(void __iomem *);
39extern void mx1_init_irq(void); 37extern void mx1_init_irq(void);
@@ -45,7 +43,6 @@ extern void mx35_init_irq(void);
45extern void mx50_init_irq(void); 43extern void mx50_init_irq(void);
46extern void mx51_init_irq(void); 44extern void mx51_init_irq(void);
47extern void mx53_init_irq(void); 45extern void mx53_init_irq(void);
48extern void mxc91231_init_irq(void);
49extern void epit_timer_init(struct clk *timer_clk, void __iomem *base, int irq); 46extern void epit_timer_init(struct clk *timer_clk, void __iomem *base, int irq);
50extern void mxc_timer_init(struct clk *timer_clk, void __iomem *, int); 47extern void mxc_timer_init(struct clk *timer_clk, void __iomem *, int);
51extern int mx1_clocks_init(unsigned long fref); 48extern int mx1_clocks_init(unsigned long fref);
@@ -58,14 +55,10 @@ extern int mx51_clocks_init(unsigned long ckil, unsigned long osc,
58 unsigned long ckih1, unsigned long ckih2); 55 unsigned long ckih1, unsigned long ckih2);
59extern int mx53_clocks_init(unsigned long ckil, unsigned long osc, 56extern int mx53_clocks_init(unsigned long ckil, unsigned long osc,
60 unsigned long ckih1, unsigned long ckih2); 57 unsigned long ckih1, unsigned long ckih2);
61extern int mxc91231_clocks_init(unsigned long fref);
62extern int mxc_register_gpios(void); 58extern int mxc_register_gpios(void);
63extern int mxc_register_device(struct platform_device *pdev, void *data); 59extern int mxc_register_device(struct platform_device *pdev, void *data);
64extern void mxc_set_cpu_type(unsigned int type); 60extern void mxc_set_cpu_type(unsigned int type);
65extern void mxc_arch_reset_init(void __iomem *); 61extern void mxc_arch_reset_init(void __iomem *);
66extern void mxc91231_power_off(void);
67extern void mxc91231_arch_reset(int, const char *);
68extern void mxc91231_prepare_idle(void);
69extern void mx51_efikamx_reset(void); 62extern void mx51_efikamx_reset(void);
70extern int mx53_revision(void); 63extern int mx53_revision(void);
71extern int mx53_display_revision(void); 64extern int mx53_display_revision(void);
diff --git a/arch/arm/plat-mxc/include/mach/debug-macro.S b/arch/arm/plat-mxc/include/mach/debug-macro.S
index 3b3a37c25c56..8e8d175e5077 100644
--- a/arch/arm/plat-mxc/include/mach/debug-macro.S
+++ b/arch/arm/plat-mxc/include/mach/debug-macro.S
@@ -44,13 +44,6 @@
44#define UART_PADDR MX51_UART1_BASE_ADDR 44#define UART_PADDR MX51_UART1_BASE_ADDR
45#endif 45#endif
46 46
47#ifdef CONFIG_ARCH_MXC91231
48#ifdef UART_PADDR
49#error "CONFIG_DEBUG_LL is incompatible with multiple archs"
50#endif
51#define UART_PADDR MXC91231_UART2_BASE_ADDR
52#endif
53
54#define UART_VADDR IMX_IO_ADDRESS(UART_PADDR) 47#define UART_VADDR IMX_IO_ADDRESS(UART_PADDR)
55 48
56 .macro addruart, rp, rv 49 .macro addruart, rp, rv
diff --git a/arch/arm/plat-mxc/include/mach/hardware.h b/arch/arm/plat-mxc/include/mach/hardware.h
index 26bb1bab4aeb..a881db5c395e 100644
--- a/arch/arm/plat-mxc/include/mach/hardware.h
+++ b/arch/arm/plat-mxc/include/mach/hardware.h
@@ -86,15 +86,6 @@
86 * SPBA0 0x70000000+0x100000 -> 0xf5400000+0x100000 86 * SPBA0 0x70000000+0x100000 -> 0xf5400000+0x100000
87 * AIPS1 0x73f00000+0x100000 -> 0xf5700000+0x100000 87 * AIPS1 0x73f00000+0x100000 -> 0xf5700000+0x100000
88 * AIPS2 0x83f00000+0x100000 -> 0xf4300000+0x100000 88 * AIPS2 0x83f00000+0x100000 -> 0xf4300000+0x100000
89 * mxc91231:
90 * L2CC 0x30000000+0x010000 -> 0xf4400000+0x010000
91 * X_MEMC 0xb8000000+0x010000 -> 0xf4c00000+0x010000
92 * ROMP 0x60000000+0x010000 -> 0xf5000000+0x010000
93 * AVIC 0x68000000+0x010000 -> 0xf5800000+0x010000
94 * AIPS1 0x43f00000+0x100000 -> 0xf5300000+0x100000
95 * SPBA0 0x50000000+0x100000 -> 0xf5400000+0x100000
96 * SPBA1 0x52000000+0x100000 -> 0xf5600000+0x100000
97 * AIPS2 0x53f00000+0x100000 -> 0xf5700000+0x100000
98 */ 89 */
99#define IMX_IO_P2V(x) ( \ 90#define IMX_IO_P2V(x) ( \
100 0xf4000000 + \ 91 0xf4000000 + \
@@ -134,10 +125,6 @@
134# include <mach/mx25.h> 125# include <mach/mx25.h>
135#endif 126#endif
136 127
137#ifdef CONFIG_ARCH_MXC91231
138# include <mach/mxc91231.h>
139#endif
140
141#include <mach/mxc.h> 128#include <mach/mxc.h>
142 129
143#define imx_map_entry(soc, name, _type) { \ 130#define imx_map_entry(soc, name, _type) { \
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mxc91231.h b/arch/arm/plat-mxc/include/mach/iomux-mxc91231.h
deleted file mode 100644
index bf28df0d58b7..000000000000
--- a/arch/arm/plat-mxc/include/mach/iomux-mxc91231.h
+++ /dev/null
@@ -1,283 +0,0 @@
1/*
2 * Copyright 2004-2006 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de>
4 * Copyright (C) 2009 by Dmitriy Taychenachev <dimichxp@gmail.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17#ifndef __MACH_IOMUX_MXC91231_H__
18#define __MACH_IOMUX_MXC91231_H__
19
20/*
21 * various IOMUX output functions
22 */
23
24#define IOMUX_OCONFIG_GPIO (0 << 4) /* used as GPIO */
25#define IOMUX_OCONFIG_FUNC (1 << 4) /* used as function */
26#define IOMUX_OCONFIG_ALT1 (2 << 4) /* used as alternate function 1 */
27#define IOMUX_OCONFIG_ALT2 (3 << 4) /* used as alternate function 2 */
28#define IOMUX_OCONFIG_ALT3 (4 << 4) /* used as alternate function 3 */
29#define IOMUX_OCONFIG_ALT4 (5 << 4) /* used as alternate function 4 */
30#define IOMUX_OCONFIG_ALT5 (6 << 4) /* used as alternate function 5 */
31#define IOMUX_OCONFIG_ALT6 (7 << 4) /* used as alternate function 6 */
32#define IOMUX_ICONFIG_NONE 0 /* not configured for input */
33#define IOMUX_ICONFIG_GPIO 1 /* used as GPIO */
34#define IOMUX_ICONFIG_FUNC 2 /* used as function */
35#define IOMUX_ICONFIG_ALT1 4 /* used as alternate function 1 */
36#define IOMUX_ICONFIG_ALT2 8 /* used as alternate function 2 */
37
38#define IOMUX_CONFIG_GPIO (IOMUX_OCONFIG_GPIO | IOMUX_ICONFIG_GPIO)
39#define IOMUX_CONFIG_FUNC (IOMUX_OCONFIG_FUNC | IOMUX_ICONFIG_FUNC)
40#define IOMUX_CONFIG_ALT1 (IOMUX_OCONFIG_ALT1 | IOMUX_ICONFIG_ALT1)
41#define IOMUX_CONFIG_ALT2 (IOMUX_OCONFIG_ALT2 | IOMUX_ICONFIG_ALT2)
42
43/*
44 * setups a single pin:
45 * - reserves the pin so that it is not claimed by another driver
46 * - setups the iomux according to the configuration
47 * - if the pin is configured as a GPIO, we claim it through kernel gpiolib
48 */
49int mxc_iomux_alloc_pin(unsigned int pin_mode, const char *label);
50/*
51 * setups mutliple pins
52 * convenient way to call the above function with tables
53 */
54int mxc_iomux_setup_multiple_pins(const unsigned int *pin_list, unsigned count,
55 const char *label);
56
57/*
58 * releases a single pin:
59 * - make it available for a future use by another driver
60 * - frees the GPIO if the pin was configured as GPIO
61 * - DOES NOT reconfigure the IOMUX in its reset state
62 */
63void mxc_iomux_release_pin(unsigned int pin_mode);
64/*
65 * releases multiple pins
66 * convenvient way to call the above function with tables
67 */
68void mxc_iomux_release_multiple_pins(const unsigned int *pin_list, int count);
69
70#define MUX_SIDE_AP (0)
71#define MUX_SIDE_SP (1)
72
73#define MUX_SIDE_SHIFT (26)
74#define MUX_SIDE_MASK (0x1 << MUX_SIDE_SHIFT)
75
76#define MUX_GPIO_PORT_SHIFT (23)
77#define MUX_GPIO_PORT_MASK (0x7 << MUX_GPIO_PORT_SHIFT)
78
79#define MUX_GPIO_PIN_SHIFT (20)
80#define MUX_GPIO_PIN_MASK (0x1f << MUX_GPIO_PIN_SHIFT)
81
82#define MUX_REG_SHIFT (15)
83#define MUX_REG_MASK (0x1f << MUX_REG_SHIFT)
84
85#define MUX_FIELD_SHIFT (13)
86#define MUX_FIELD_MASK (0x3 << MUX_FIELD_SHIFT)
87
88#define MUX_PADGRP_SHIFT (8)
89#define MUX_PADGRP_MASK (0x1f << MUX_PADGRP_SHIFT)
90
91#define MUX_PIN_MASK (0xffffff << 8)
92
93#define GPIO_PORT_MAX (3)
94
95#define IOMUX_PIN(side, gport, gpin, ctlreg, ctlfield, padgrp) \
96 (((side) << MUX_SIDE_SHIFT) | \
97 (gport << MUX_GPIO_PORT_SHIFT) | \
98 ((gpin) << MUX_GPIO_PIN_SHIFT) | \
99 ((ctlreg) << MUX_REG_SHIFT) | \
100 ((ctlfield) << MUX_FIELD_SHIFT) | \
101 ((padgrp) << MUX_PADGRP_SHIFT))
102
103#define MUX_MODE_OUT_SHIFT (4)
104#define MUX_MODE_IN_SHIFT (0)
105#define MUX_MODE_SHIFT (0)
106#define MUX_MODE_MASK (0xff << MUX_MODE_SHIFT)
107
108#define IOMUX_MODE(pin, mode) \
109 (pin | (mode << MUX_MODE_SHIFT))
110
111enum iomux_pins {
112 /* AP Side pins */
113 MXC91231_PIN_AP_CLE = IOMUX_PIN(0, 0, 0, 0, 0, 24),
114 MXC91231_PIN_AP_ALE = IOMUX_PIN(0, 0, 1, 0, 1, 24),
115 MXC91231_PIN_AP_CE_B = IOMUX_PIN(0, 0, 2, 0, 2, 24),
116 MXC91231_PIN_AP_RE_B = IOMUX_PIN(0, 0, 3, 0, 3, 24),
117 MXC91231_PIN_AP_WE_B = IOMUX_PIN(0, 0, 4, 1, 0, 24),
118 MXC91231_PIN_AP_WP_B = IOMUX_PIN(0, 0, 5, 1, 1, 24),
119 MXC91231_PIN_AP_BSY_B = IOMUX_PIN(0, 0, 6, 1, 2, 24),
120 MXC91231_PIN_AP_U1_TXD = IOMUX_PIN(0, 0, 7, 1, 3, 28),
121 MXC91231_PIN_AP_U1_RXD = IOMUX_PIN(0, 0, 8, 2, 0, 28),
122 MXC91231_PIN_AP_U1_RTS_B = IOMUX_PIN(0, 0, 9, 2, 1, 28),
123 MXC91231_PIN_AP_U1_CTS_B = IOMUX_PIN(0, 0, 10, 2, 2, 28),
124 MXC91231_PIN_AP_AD1_TXD = IOMUX_PIN(0, 0, 11, 2, 3, 9),
125 MXC91231_PIN_AP_AD1_RXD = IOMUX_PIN(0, 0, 12, 3, 0, 9),
126 MXC91231_PIN_AP_AD1_TXC = IOMUX_PIN(0, 0, 13, 3, 1, 9),
127 MXC91231_PIN_AP_AD1_TXFS = IOMUX_PIN(0, 0, 14, 3, 2, 9),
128 MXC91231_PIN_AP_AD2_TXD = IOMUX_PIN(0, 0, 15, 3, 3, 9),
129 MXC91231_PIN_AP_AD2_RXD = IOMUX_PIN(0, 0, 16, 4, 0, 9),
130 MXC91231_PIN_AP_AD2_TXC = IOMUX_PIN(0, 0, 17, 4, 1, 9),
131 MXC91231_PIN_AP_AD2_TXFS = IOMUX_PIN(0, 0, 18, 4, 2, 9),
132 MXC91231_PIN_AP_OWDAT = IOMUX_PIN(0, 0, 19, 4, 3, 28),
133 MXC91231_PIN_AP_IPU_LD17 = IOMUX_PIN(0, 0, 20, 5, 0, 28),
134 MXC91231_PIN_AP_IPU_D3_VSYNC = IOMUX_PIN(0, 0, 21, 5, 1, 28),
135 MXC91231_PIN_AP_IPU_D3_HSYNC = IOMUX_PIN(0, 0, 22, 5, 2, 28),
136 MXC91231_PIN_AP_IPU_D3_CLK = IOMUX_PIN(0, 0, 23, 5, 3, 28),
137 MXC91231_PIN_AP_IPU_D3_DRDY = IOMUX_PIN(0, 0, 24, 6, 0, 28),
138 MXC91231_PIN_AP_IPU_D3_CONTR = IOMUX_PIN(0, 0, 25, 6, 1, 28),
139 MXC91231_PIN_AP_IPU_D0_CS = IOMUX_PIN(0, 0, 26, 6, 2, 28),
140 MXC91231_PIN_AP_IPU_LD16 = IOMUX_PIN(0, 0, 27, 6, 3, 28),
141 MXC91231_PIN_AP_IPU_D2_CS = IOMUX_PIN(0, 0, 28, 7, 0, 28),
142 MXC91231_PIN_AP_IPU_PAR_RS = IOMUX_PIN(0, 0, 29, 7, 1, 28),
143 MXC91231_PIN_AP_IPU_D3_PS = IOMUX_PIN(0, 0, 30, 7, 2, 28),
144 MXC91231_PIN_AP_IPU_D3_CLS = IOMUX_PIN(0, 0, 31, 7, 3, 28),
145 MXC91231_PIN_AP_IPU_RD = IOMUX_PIN(0, 1, 0, 8, 0, 28),
146 MXC91231_PIN_AP_IPU_WR = IOMUX_PIN(0, 1, 1, 8, 1, 28),
147 MXC91231_PIN_AP_IPU_LD0 = IOMUX_PIN(0, 7, 0, 8, 2, 28),
148 MXC91231_PIN_AP_IPU_LD1 = IOMUX_PIN(0, 7, 0, 8, 3, 28),
149 MXC91231_PIN_AP_IPU_LD2 = IOMUX_PIN(0, 7, 0, 9, 0, 28),
150 MXC91231_PIN_AP_IPU_LD3 = IOMUX_PIN(0, 1, 2, 9, 1, 28),
151 MXC91231_PIN_AP_IPU_LD4 = IOMUX_PIN(0, 1, 3, 9, 2, 28),
152 MXC91231_PIN_AP_IPU_LD5 = IOMUX_PIN(0, 1, 4, 9, 3, 28),
153 MXC91231_PIN_AP_IPU_LD6 = IOMUX_PIN(0, 1, 5, 10, 0, 28),
154 MXC91231_PIN_AP_IPU_LD7 = IOMUX_PIN(0, 1, 6, 10, 1, 28),
155 MXC91231_PIN_AP_IPU_LD8 = IOMUX_PIN(0, 1, 7, 10, 2, 28),
156 MXC91231_PIN_AP_IPU_LD9 = IOMUX_PIN(0, 1, 8, 10, 3, 28),
157 MXC91231_PIN_AP_IPU_LD10 = IOMUX_PIN(0, 1, 9, 11, 0, 28),
158 MXC91231_PIN_AP_IPU_LD11 = IOMUX_PIN(0, 1, 10, 11, 1, 28),
159 MXC91231_PIN_AP_IPU_LD12 = IOMUX_PIN(0, 1, 11, 11, 2, 28),
160 MXC91231_PIN_AP_IPU_LD13 = IOMUX_PIN(0, 1, 12, 11, 3, 28),
161 MXC91231_PIN_AP_IPU_LD14 = IOMUX_PIN(0, 1, 13, 12, 0, 28),
162 MXC91231_PIN_AP_IPU_LD15 = IOMUX_PIN(0, 1, 14, 12, 1, 28),
163 MXC91231_PIN_AP_KPROW4 = IOMUX_PIN(0, 7, 0, 12, 2, 10),
164 MXC91231_PIN_AP_KPROW5 = IOMUX_PIN(0, 1, 16, 12, 3, 10),
165 MXC91231_PIN_AP_GPIO_AP_B17 = IOMUX_PIN(0, 1, 17, 13, 0, 10),
166 MXC91231_PIN_AP_GPIO_AP_B18 = IOMUX_PIN(0, 1, 18, 13, 1, 10),
167 MXC91231_PIN_AP_KPCOL3 = IOMUX_PIN(0, 1, 19, 13, 2, 11),
168 MXC91231_PIN_AP_KPCOL4 = IOMUX_PIN(0, 1, 20, 13, 3, 11),
169 MXC91231_PIN_AP_KPCOL5 = IOMUX_PIN(0, 1, 21, 14, 0, 11),
170 MXC91231_PIN_AP_GPIO_AP_B22 = IOMUX_PIN(0, 1, 22, 14, 1, 11),
171 MXC91231_PIN_AP_GPIO_AP_B23 = IOMUX_PIN(0, 1, 23, 14, 2, 11),
172 MXC91231_PIN_AP_CSI_D0 = IOMUX_PIN(0, 1, 24, 14, 3, 21),
173 MXC91231_PIN_AP_CSI_D1 = IOMUX_PIN(0, 1, 25, 15, 0, 21),
174 MXC91231_PIN_AP_CSI_D2 = IOMUX_PIN(0, 1, 26, 15, 1, 21),
175 MXC91231_PIN_AP_CSI_D3 = IOMUX_PIN(0, 1, 27, 15, 2, 21),
176 MXC91231_PIN_AP_CSI_D4 = IOMUX_PIN(0, 1, 28, 15, 3, 21),
177 MXC91231_PIN_AP_CSI_D5 = IOMUX_PIN(0, 1, 29, 16, 0, 21),
178 MXC91231_PIN_AP_CSI_D6 = IOMUX_PIN(0, 1, 30, 16, 1, 21),
179 MXC91231_PIN_AP_CSI_D7 = IOMUX_PIN(0, 1, 31, 16, 2, 21),
180 MXC91231_PIN_AP_CSI_D8 = IOMUX_PIN(0, 2, 0, 16, 3, 21),
181 MXC91231_PIN_AP_CSI_D9 = IOMUX_PIN(0, 2, 1, 17, 0, 21),
182 MXC91231_PIN_AP_CSI_MCLK = IOMUX_PIN(0, 2, 2, 17, 1, 21),
183 MXC91231_PIN_AP_CSI_VSYNC = IOMUX_PIN(0, 2, 3, 17, 2, 21),
184 MXC91231_PIN_AP_CSI_HSYNC = IOMUX_PIN(0, 2, 4, 17, 3, 21),
185 MXC91231_PIN_AP_CSI_PIXCLK = IOMUX_PIN(0, 2, 5, 18, 0, 21),
186 MXC91231_PIN_AP_I2CLK = IOMUX_PIN(0, 2, 6, 18, 1, 12),
187 MXC91231_PIN_AP_I2DAT = IOMUX_PIN(0, 2, 7, 18, 2, 12),
188 MXC91231_PIN_AP_GPIO_AP_C8 = IOMUX_PIN(0, 2, 8, 18, 3, 9),
189 MXC91231_PIN_AP_GPIO_AP_C9 = IOMUX_PIN(0, 2, 9, 19, 0, 9),
190 MXC91231_PIN_AP_GPIO_AP_C10 = IOMUX_PIN(0, 2, 10, 19, 1, 9),
191 MXC91231_PIN_AP_GPIO_AP_C11 = IOMUX_PIN(0, 2, 11, 19, 2, 9),
192 MXC91231_PIN_AP_GPIO_AP_C12 = IOMUX_PIN(0, 2, 12, 19, 3, 9),
193 MXC91231_PIN_AP_GPIO_AP_C13 = IOMUX_PIN(0, 2, 13, 20, 0, 28),
194 MXC91231_PIN_AP_GPIO_AP_C14 = IOMUX_PIN(0, 2, 14, 20, 1, 28),
195 MXC91231_PIN_AP_GPIO_AP_C15 = IOMUX_PIN(0, 2, 15, 20, 2, 9),
196 MXC91231_PIN_AP_GPIO_AP_C16 = IOMUX_PIN(0, 2, 16, 20, 3, 9),
197 MXC91231_PIN_AP_GPIO_AP_C17 = IOMUX_PIN(0, 2, 17, 21, 0, 9),
198 MXC91231_PIN_AP_ED_INT0 = IOMUX_PIN(0, 2, 18, 21, 1, 22),
199 MXC91231_PIN_AP_ED_INT1 = IOMUX_PIN(0, 2, 19, 21, 2, 22),
200 MXC91231_PIN_AP_ED_INT2 = IOMUX_PIN(0, 2, 20, 21, 3, 22),
201 MXC91231_PIN_AP_ED_INT3 = IOMUX_PIN(0, 2, 21, 22, 0, 22),
202 MXC91231_PIN_AP_ED_INT4 = IOMUX_PIN(0, 2, 22, 22, 1, 23),
203 MXC91231_PIN_AP_ED_INT5 = IOMUX_PIN(0, 2, 23, 22, 2, 23),
204 MXC91231_PIN_AP_ED_INT6 = IOMUX_PIN(0, 2, 24, 22, 3, 23),
205 MXC91231_PIN_AP_ED_INT7 = IOMUX_PIN(0, 2, 25, 23, 0, 23),
206 MXC91231_PIN_AP_U2_DSR_B = IOMUX_PIN(0, 2, 26, 23, 1, 28),
207 MXC91231_PIN_AP_U2_RI_B = IOMUX_PIN(0, 2, 27, 23, 2, 28),
208 MXC91231_PIN_AP_U2_CTS_B = IOMUX_PIN(0, 2, 28, 23, 3, 28),
209 MXC91231_PIN_AP_U2_DTR_B = IOMUX_PIN(0, 2, 29, 24, 0, 28),
210 MXC91231_PIN_AP_KPROW0 = IOMUX_PIN(0, 7, 0, 24, 1, 10),
211 MXC91231_PIN_AP_KPROW1 = IOMUX_PIN(0, 1, 15, 24, 2, 10),
212 MXC91231_PIN_AP_KPROW2 = IOMUX_PIN(0, 7, 0, 24, 3, 10),
213 MXC91231_PIN_AP_KPROW3 = IOMUX_PIN(0, 7, 0, 25, 0, 10),
214 MXC91231_PIN_AP_KPCOL0 = IOMUX_PIN(0, 7, 0, 25, 1, 11),
215 MXC91231_PIN_AP_KPCOL1 = IOMUX_PIN(0, 7, 0, 25, 2, 11),
216 MXC91231_PIN_AP_KPCOL2 = IOMUX_PIN(0, 7, 0, 25, 3, 11),
217
218 /* Shared pins */
219 MXC91231_PIN_SP_U3_TXD = IOMUX_PIN(1, 3, 0, 0, 0, 28),
220 MXC91231_PIN_SP_U3_RXD = IOMUX_PIN(1, 3, 1, 0, 1, 28),
221 MXC91231_PIN_SP_U3_RTS_B = IOMUX_PIN(1, 3, 2, 0, 2, 28),
222 MXC91231_PIN_SP_U3_CTS_B = IOMUX_PIN(1, 3, 3, 0, 3, 28),
223 MXC91231_PIN_SP_USB_TXOE_B = IOMUX_PIN(1, 3, 4, 1, 0, 28),
224 MXC91231_PIN_SP_USB_DAT_VP = IOMUX_PIN(1, 3, 5, 1, 1, 28),
225 MXC91231_PIN_SP_USB_SE0_VM = IOMUX_PIN(1, 3, 6, 1, 2, 28),
226 MXC91231_PIN_SP_USB_RXD = IOMUX_PIN(1, 3, 7, 1, 3, 28),
227 MXC91231_PIN_SP_UH2_TXOE_B = IOMUX_PIN(1, 3, 8, 2, 0, 28),
228 MXC91231_PIN_SP_UH2_SPEED = IOMUX_PIN(1, 3, 9, 2, 1, 28),
229 MXC91231_PIN_SP_UH2_SUSPEN = IOMUX_PIN(1, 3, 10, 2, 2, 28),
230 MXC91231_PIN_SP_UH2_TXDP = IOMUX_PIN(1, 3, 11, 2, 3, 28),
231 MXC91231_PIN_SP_UH2_RXDP = IOMUX_PIN(1, 3, 12, 3, 0, 28),
232 MXC91231_PIN_SP_UH2_RXDM = IOMUX_PIN(1, 3, 13, 3, 1, 28),
233 MXC91231_PIN_SP_UH2_OVR = IOMUX_PIN(1, 3, 14, 3, 2, 28),
234 MXC91231_PIN_SP_UH2_PWR = IOMUX_PIN(1, 3, 15, 3, 3, 28),
235 MXC91231_PIN_SP_SD1_DAT0 = IOMUX_PIN(1, 3, 16, 4, 0, 25),
236 MXC91231_PIN_SP_SD1_DAT1 = IOMUX_PIN(1, 3, 17, 4, 1, 25),
237 MXC91231_PIN_SP_SD1_DAT2 = IOMUX_PIN(1, 3, 18, 4, 2, 25),
238 MXC91231_PIN_SP_SD1_DAT3 = IOMUX_PIN(1, 3, 19, 4, 3, 25),
239 MXC91231_PIN_SP_SD1_CMD = IOMUX_PIN(1, 3, 20, 5, 0, 25),
240 MXC91231_PIN_SP_SD1_CLK = IOMUX_PIN(1, 3, 21, 5, 1, 25),
241 MXC91231_PIN_SP_SD2_DAT0 = IOMUX_PIN(1, 3, 22, 5, 2, 26),
242 MXC91231_PIN_SP_SD2_DAT1 = IOMUX_PIN(1, 3, 23, 5, 3, 26),
243 MXC91231_PIN_SP_SD2_DAT2 = IOMUX_PIN(1, 3, 24, 6, 0, 26),
244 MXC91231_PIN_SP_SD2_DAT3 = IOMUX_PIN(1, 3, 25, 6, 1, 26),
245 MXC91231_PIN_SP_GPIO_SP_A26 = IOMUX_PIN(1, 3, 26, 6, 2, 28),
246 MXC91231_PIN_SP_SPI1_CLK = IOMUX_PIN(1, 3, 27, 6, 3, 13),
247 MXC91231_PIN_SP_SPI1_MOSI = IOMUX_PIN(1, 3, 28, 7, 0, 13),
248 MXC91231_PIN_SP_SPI1_MISO = IOMUX_PIN(1, 3, 29, 7, 1, 13),
249 MXC91231_PIN_SP_SPI1_SS0 = IOMUX_PIN(1, 3, 30, 7, 2, 13),
250 MXC91231_PIN_SP_SPI1_SS1 = IOMUX_PIN(1, 3, 31, 7, 3, 13),
251 MXC91231_PIN_SP_SD2_CMD = IOMUX_PIN(1, 7, 0, 8, 0, 26),
252 MXC91231_PIN_SP_SD2_CLK = IOMUX_PIN(1, 7, 0, 8, 1, 26),
253 MXC91231_PIN_SP_SIM1_RST_B = IOMUX_PIN(1, 2, 30, 8, 2, 28),
254 MXC91231_PIN_SP_SIM1_SVEN = IOMUX_PIN(1, 7, 0, 8, 3, 28),
255 MXC91231_PIN_SP_SIM1_CLK = IOMUX_PIN(1, 7, 0, 9, 0, 28),
256 MXC91231_PIN_SP_SIM1_TRXD = IOMUX_PIN(1, 7, 0, 9, 1, 28),
257 MXC91231_PIN_SP_SIM1_PD = IOMUX_PIN(1, 2, 31, 9, 2, 28),
258 MXC91231_PIN_SP_UH2_TXDM = IOMUX_PIN(1, 7, 0, 9, 3, 28),
259 MXC91231_PIN_SP_UH2_RXD = IOMUX_PIN(1, 7, 0, 10, 0, 28),
260};
261
262#define PIN_AP_MAX (104)
263#define PIN_SP_MAX (41)
264
265#define PIN_MAX (PIN_AP_MAX + PIN_SP_MAX)
266
267/*
268 * Convenience values for use with mxc_iomux_mode()
269 *
270 * Format here is MXC91231_PIN_(pin name)__(function)
271 */
272
273#define MXC91231_PIN_SP_USB_DAT_VP__USB_DAT_VP \
274 IOMUX_MODE(MXC91231_PIN_SP_USB_DAT_VP, IOMUX_CONFIG_FUNC)
275#define MXC91231_PIN_SP_USB_SE0_VM__USB_SE0_VM \
276 IOMUX_MODE(MXC91231_PIN_SP_USB_SE0_VM, IOMUX_CONFIG_FUNC)
277#define MXC91231_PIN_SP_USB_DAT_VP__RXD2 \
278 IOMUX_MODE(MXC91231_PIN_SP_USB_DAT_VP, IOMUX_CONFIG_ALT1)
279#define MXC91231_PIN_SP_USB_SE0_VM__TXD2 \
280 IOMUX_MODE(MXC91231_PIN_SP_USB_SE0_VM, IOMUX_CONFIG_ALT1)
281
282
283#endif /* __MACH_IOMUX_MXC91231_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/irqs.h b/arch/arm/plat-mxc/include/mach/irqs.h
index a3d930d3e65d..35c89bcdf758 100644
--- a/arch/arm/plat-mxc/include/mach/irqs.h
+++ b/arch/arm/plat-mxc/include/mach/irqs.h
@@ -35,8 +35,6 @@
35#define MXC_GPIO_IRQS (32 * 4) 35#define MXC_GPIO_IRQS (32 * 4)
36#elif defined CONFIG_SOC_IMX51 36#elif defined CONFIG_SOC_IMX51
37#define MXC_GPIO_IRQS (32 * 4) 37#define MXC_GPIO_IRQS (32 * 4)
38#elif defined CONFIG_ARCH_MXC91231
39#define MXC_GPIO_IRQS (32 * 4)
40#elif defined CONFIG_ARCH_MX3 38#elif defined CONFIG_ARCH_MX3
41#define MXC_GPIO_IRQS (32 * 3) 39#define MXC_GPIO_IRQS (32 * 3)
42#endif 40#endif
diff --git a/arch/arm/plat-mxc/include/mach/memory.h b/arch/arm/plat-mxc/include/mach/memory.h
index 5d51cbb98893..11be5cdbdd1a 100644
--- a/arch/arm/plat-mxc/include/mach/memory.h
+++ b/arch/arm/plat-mxc/include/mach/memory.h
@@ -19,7 +19,6 @@
19#define MX50_PHYS_OFFSET UL(0x70000000) 19#define MX50_PHYS_OFFSET UL(0x70000000)
20#define MX51_PHYS_OFFSET UL(0x90000000) 20#define MX51_PHYS_OFFSET UL(0x90000000)
21#define MX53_PHYS_OFFSET UL(0x70000000) 21#define MX53_PHYS_OFFSET UL(0x70000000)
22#define MXC91231_PHYS_OFFSET UL(0x90000000)
23 22
24#if !defined(CONFIG_RUNTIME_PHYS_OFFSET) 23#if !defined(CONFIG_RUNTIME_PHYS_OFFSET)
25# if defined CONFIG_ARCH_MX1 24# if defined CONFIG_ARCH_MX1
@@ -32,8 +31,6 @@
32# define PLAT_PHYS_OFFSET MX27_PHYS_OFFSET 31# define PLAT_PHYS_OFFSET MX27_PHYS_OFFSET
33# elif defined CONFIG_ARCH_MX3 32# elif defined CONFIG_ARCH_MX3
34# define PLAT_PHYS_OFFSET MX3x_PHYS_OFFSET 33# define PLAT_PHYS_OFFSET MX3x_PHYS_OFFSET
35# elif defined CONFIG_ARCH_MXC91231
36# define PLAT_PHYS_OFFSET MXC91231_PHYS_OFFSET
37# elif defined CONFIG_ARCH_MX50 34# elif defined CONFIG_ARCH_MX50
38# define PLAT_PHYS_OFFSET MX50_PHYS_OFFSET 35# define PLAT_PHYS_OFFSET MX50_PHYS_OFFSET
39# elif defined CONFIG_ARCH_MX51 36# elif defined CONFIG_ARCH_MX51
diff --git a/arch/arm/plat-mxc/include/mach/mxc.h b/arch/arm/plat-mxc/include/mach/mxc.h
index 1aea818d9d31..0aba8b18bc4f 100644
--- a/arch/arm/plat-mxc/include/mach/mxc.h
+++ b/arch/arm/plat-mxc/include/mach/mxc.h
@@ -35,7 +35,6 @@
35#define MXC_CPU_MX50 50 35#define MXC_CPU_MX50 50
36#define MXC_CPU_MX51 51 36#define MXC_CPU_MX51 51
37#define MXC_CPU_MX53 53 37#define MXC_CPU_MX53 53
38#define MXC_CPU_MXC91231 91231
39 38
40#define IMX_CHIP_REVISION_1_0 0x10 39#define IMX_CHIP_REVISION_1_0 0x10
41#define IMX_CHIP_REVISION_1_1 0x11 40#define IMX_CHIP_REVISION_1_1 0x11
@@ -177,18 +176,6 @@ extern unsigned int __mxc_cpu_type;
177# define cpu_is_mx53() (0) 176# define cpu_is_mx53() (0)
178#endif 177#endif
179 178
180#ifdef CONFIG_ARCH_MXC91231
181# ifdef mxc_cpu_type
182# undef mxc_cpu_type
183# define mxc_cpu_type __mxc_cpu_type
184# else
185# define mxc_cpu_type MXC_CPU_MXC91231
186# endif
187# define cpu_is_mxc91231() (mxc_cpu_type == MXC_CPU_MXC91231)
188#else
189# define cpu_is_mxc91231() (0)
190#endif
191
192#ifndef __ASSEMBLY__ 179#ifndef __ASSEMBLY__
193 180
194struct cpu_op { 181struct cpu_op {
@@ -214,7 +201,7 @@ extern struct cpu_op *(*get_cpu_op)(int *op);
214#define CSCR_A(n) (IO_ADDRESS(WEIM_BASE_ADDR + n * 0x10 + 0x8)) 201#define CSCR_A(n) (IO_ADDRESS(WEIM_BASE_ADDR + n * 0x10 + 0x8))
215#endif 202#endif
216 203
217#define cpu_is_mx3() (cpu_is_mx31() || cpu_is_mx35() || cpu_is_mxc91231()) 204#define cpu_is_mx3() (cpu_is_mx31() || cpu_is_mx35())
218#define cpu_is_mx2() (cpu_is_mx21() || cpu_is_mx27()) 205#define cpu_is_mx2() (cpu_is_mx21() || cpu_is_mx27())
219 206
220#endif /* __ASM_ARCH_MXC_H__ */ 207#endif /* __ASM_ARCH_MXC_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/mxc91231.h b/arch/arm/plat-mxc/include/mach/mxc91231.h
deleted file mode 100644
index 765190fe6332..000000000000
--- a/arch/arm/plat-mxc/include/mach/mxc91231.h
+++ /dev/null
@@ -1,256 +0,0 @@
1/*
2 * Copyright 2004-2006 Freescale Semiconductor, Inc. All Rights Reserved.
3 * - Platform specific register memory map
4 *
5 * Copyright 2005-2007 Motorola, Inc.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 */
17#ifndef __MACH_MXC91231_H__
18#define __MACH_MXC91231_H__
19
20/*
21 * L2CC
22 */
23#define MXC91231_L2CC_BASE_ADDR 0x30000000
24#define MXC91231_L2CC_SIZE SZ_64K
25
26/*
27 * AIPS 1
28 */
29#define MXC91231_AIPS1_BASE_ADDR 0x43F00000
30#define MXC91231_AIPS1_SIZE SZ_1M
31
32#define MXC91231_AIPS1_CTRL_BASE_ADDR MXC91231_AIPS1_BASE_ADDR
33#define MXC91231_MAX_BASE_ADDR (MXC91231_AIPS1_BASE_ADDR + 0x04000)
34#define MXC91231_EVTMON_BASE_ADDR (MXC91231_AIPS1_BASE_ADDR + 0x08000)
35#define MXC91231_CLKCTL_BASE_ADDR (MXC91231_AIPS1_BASE_ADDR + 0x0C000)
36#define MXC91231_ETB_SLOT4_BASE_ADDR (MXC91231_AIPS1_BASE_ADDR + 0x10000)
37#define MXC91231_ETB_SLOT5_BASE_ADDR (MXC91231_AIPS1_BASE_ADDR + 0x14000)
38#define MXC91231_ECT_CTIO_BASE_ADDR (MXC91231_AIPS1_BASE_ADDR + 0x18000)
39#define MXC91231_I2C_BASE_ADDR (MXC91231_AIPS1_BASE_ADDR + 0x80000)
40#define MXC91231_MU_BASE_ADDR (MXC91231_AIPS1_BASE_ADDR + 0x88000)
41#define MXC91231_UART1_BASE_ADDR (MXC91231_AIPS1_BASE_ADDR + 0x90000)
42#define MXC91231_UART2_BASE_ADDR (MXC91231_AIPS1_BASE_ADDR + 0x94000)
43#define MXC91231_DSM_BASE_ADDR (MXC91231_AIPS1_BASE_ADDR + 0x98000)
44#define MXC91231_OWIRE_BASE_ADDR (MXC91231_AIPS1_BASE_ADDR + 0x9C000)
45#define MXC91231_SSI1_BASE_ADDR (MXC91231_AIPS1_BASE_ADDR + 0xA0000)
46#define MXC91231_KPP_BASE_ADDR (MXC91231_AIPS1_BASE_ADDR + 0xA8000)
47#define MXC91231_IOMUX_AP_BASE_ADDR (MXC91231_AIPS1_BASE_ADDR + 0xAC000)
48#define MXC91231_CTI_AP_BASE_ADDR (MXC91231_AIPS1_BASE_ADDR + 0xB8000)
49
50/*
51 * AIPS 2
52 */
53#define MXC91231_AIPS2_BASE_ADDR 0x53F00000
54#define MXC91231_AIPS2_SIZE SZ_1M
55
56#define MXC91231_GEMK_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0x8C000)
57#define MXC91231_GPT1_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0x90000)
58#define MXC91231_EPIT1_AP_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0x94000)
59#define MXC91231_SCC_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0xAC000)
60#define MXC91231_RNGA_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0xB0000)
61#define MXC91231_IPU_CTRL_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0xC0000)
62#define MXC91231_AUDMUX_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0xC4000)
63#define MXC91231_EDIO_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0xC8000)
64#define MXC91231_GPIO1_AP_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0xCC000)
65#define MXC91231_GPIO2_AP_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0xD0000)
66#define MXC91231_SDMA_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0xD4000)
67#define MXC91231_RTC_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0xD8000)
68#define MXC91231_WDOG1_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0xDC000)
69#define MXC91231_PWM_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0xE0000)
70#define MXC91231_GPIO3_AP_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0xE4000)
71#define MXC91231_WDOG2_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0xE8000)
72#define MXC91231_RTIC_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0xEC000)
73#define MXC91231_LPMC_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0xF0000)
74
75/*
76 * SPBA global module 0
77 */
78#define MXC91231_SPBA0_BASE_ADDR 0x50000000
79#define MXC91231_SPBA0_SIZE SZ_1M
80
81#define MXC91231_MMC_SDHC1_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x04000)
82#define MXC91231_MMC_SDHC2_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x08000)
83#define MXC91231_UART3_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x0C000)
84#define MXC91231_CSPI2_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x10000)
85#define MXC91231_SSI2_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x14000)
86#define MXC91231_SIM_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x18000)
87#define MXC91231_IIM_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x1C000)
88#define MXC91231_CTI_SDMA_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x20000)
89#define MXC91231_USBOTG_CTRL_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x24000)
90#define MXC91231_USBOTG_DATA_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x28000)
91#define MXC91231_CSPI1_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x30000)
92#define MXC91231_SPBA_CTRL_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x3C000)
93#define MXC91231_IOMUX_COM_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x40000)
94#define MXC91231_CRM_COM_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x44000)
95#define MXC91231_CRM_AP_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x48000)
96#define MXC91231_PLL0_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x4C000)
97#define MXC91231_PLL1_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x50000)
98#define MXC91231_PLL2_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x54000)
99#define MXC91231_GPIO4_SH_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x58000)
100#define MXC91231_HAC_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x5C000)
101#define MXC91231_SAHARA_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x5C000)
102#define MXC91231_PLL3_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x60000)
103
104/*
105 * SPBA global module 1
106 */
107#define MXC91231_SPBA1_BASE_ADDR 0x52000000
108#define MXC91231_SPBA1_SIZE SZ_1M
109
110#define MXC91231_MQSPI_BASE_ADDR (MXC91231_SPBA1_BASE_ADDR + 0x34000)
111#define MXC91231_EL1T_BASE_ADDR (MXC91231_SPBA1_BASE_ADDR + 0x38000)
112
113/*!
114 * Defines for SPBA modules
115 */
116#define MXC91231_SPBA_SDHC1 0x04
117#define MXC91231_SPBA_SDHC2 0x08
118#define MXC91231_SPBA_UART3 0x0C
119#define MXC91231_SPBA_CSPI2 0x10
120#define MXC91231_SPBA_SSI2 0x14
121#define MXC91231_SPBA_SIM 0x18
122#define MXC91231_SPBA_IIM 0x1C
123#define MXC91231_SPBA_CTI_SDMA 0x20
124#define MXC91231_SPBA_USBOTG_CTRL_REGS 0x24
125#define MXC91231_SPBA_USBOTG_DATA_REGS 0x28
126#define MXC91231_SPBA_CSPI1 0x30
127#define MXC91231_SPBA_MQSPI 0x34
128#define MXC91231_SPBA_EL1T 0x38
129#define MXC91231_SPBA_IOMUX 0x40
130#define MXC91231_SPBA_CRM_COM 0x44
131#define MXC91231_SPBA_CRM_AP 0x48
132#define MXC91231_SPBA_PLL0 0x4C
133#define MXC91231_SPBA_PLL1 0x50
134#define MXC91231_SPBA_PLL2 0x54
135#define MXC91231_SPBA_GPIO4 0x58
136#define MXC91231_SPBA_SAHARA 0x5C
137
138/*
139 * ROMP and AVIC
140 */
141#define MXC91231_ROMP_BASE_ADDR 0x60000000
142#define MXC91231_ROMP_SIZE SZ_64K
143
144#define MXC91231_AVIC_BASE_ADDR 0x68000000
145#define MXC91231_AVIC_SIZE SZ_64K
146
147/*
148 * NAND, SDRAM, WEIM, M3IF, EMI controllers
149 */
150#define MXC91231_X_MEMC_BASE_ADDR 0xB8000000
151#define MXC91231_X_MEMC_SIZE SZ_64K
152
153#define MXC91231_NFC_BASE_ADDR (MXC91231_X_MEMC_BASE_ADDR + 0x0000)
154#define MXC91231_ESDCTL_BASE_ADDR (MXC91231_X_MEMC_BASE_ADDR + 0x1000)
155#define MXC91231_WEIM_BASE_ADDR (MXC91231_X_MEMC_BASE_ADDR + 0x2000)
156#define MXC91231_M3IF_BASE_ADDR (MXC91231_X_MEMC_BASE_ADDR + 0x3000)
157#define MXC91231_EMI_CTL_BASE_ADDR (MXC91231_X_MEMC_BASE_ADDR + 0x4000)
158
159/*
160 * Memory regions and CS
161 * CPLD is connected on CS4
162 * CS5 is TP1021 or it is not connected
163 * */
164#define MXC91231_FB_RAM_BASE_ADDR 0x78000000
165#define MXC91231_FB_RAM_SIZE SZ_256K
166#define MXC91231_CSD0_BASE_ADDR 0x80000000
167#define MXC91231_CSD1_BASE_ADDR 0x90000000
168#define MXC91231_CS0_BASE_ADDR 0xA0000000
169#define MXC91231_CS1_BASE_ADDR 0xA8000000
170#define MXC91231_CS2_BASE_ADDR 0xB0000000
171#define MXC91231_CS3_BASE_ADDR 0xB2000000
172#define MXC91231_CS4_BASE_ADDR 0xB4000000
173#define MXC91231_CS5_BASE_ADDR 0xB6000000
174
175/*
176 * This macro defines the physical to virtual address mapping for all the
177 * peripheral modules. It is used by passing in the physical address as x
178 * and returning the virtual address.
179 */
180#define MXC91231_IO_P2V(x) IMX_IO_P2V(x)
181#define MXC91231_IO_ADDRESS(x) IOMEM(MXC91231_IO_P2V(x))
182
183/*
184 * Interrupt numbers
185 */
186#define MXC91231_INT_GPIO3 0
187#define MXC91231_INT_EL1T_CI 1
188#define MXC91231_INT_EL1T_RFCI 2
189#define MXC91231_INT_EL1T_RFI 3
190#define MXC91231_INT_EL1T_MCU 4
191#define MXC91231_INT_EL1T_IPI 5
192#define MXC91231_INT_MU_GEN 6
193#define MXC91231_INT_GPIO4 7
194#define MXC91231_INT_MMC_SDHC2 8
195#define MXC91231_INT_MMC_SDHC1 9
196#define MXC91231_INT_I2C 10
197#define MXC91231_INT_SSI2 11
198#define MXC91231_INT_SSI1 12
199#define MXC91231_INT_CSPI2 13
200#define MXC91231_INT_CSPI1 14
201#define MXC91231_INT_RTIC 15
202#define MXC91231_INT_SAHARA 15
203#define MXC91231_INT_HAC 15
204#define MXC91231_INT_UART3_RX 16
205#define MXC91231_INT_UART3_TX 17
206#define MXC91231_INT_UART3_MINT 18
207#define MXC91231_INT_ECT 19
208#define MXC91231_INT_SIM_IPB 20
209#define MXC91231_INT_SIM_DATA 21
210#define MXC91231_INT_RNGA 22
211#define MXC91231_INT_DSM_AP 23
212#define MXC91231_INT_KPP 24
213#define MXC91231_INT_RTC 25
214#define MXC91231_INT_PWM 26
215#define MXC91231_INT_GEMK_AP 27
216#define MXC91231_INT_EPIT 28
217#define MXC91231_INT_GPT 29
218#define MXC91231_INT_UART2_RX 30
219#define MXC91231_INT_UART2_TX 31
220#define MXC91231_INT_UART2_MINT 32
221#define MXC91231_INT_NANDFC 33
222#define MXC91231_INT_SDMA 34
223#define MXC91231_INT_USB_WAKEUP 35
224#define MXC91231_INT_USB_SOF 36
225#define MXC91231_INT_PMU_EVTMON 37
226#define MXC91231_INT_USB_FUNC 38
227#define MXC91231_INT_USB_DMA 39
228#define MXC91231_INT_USB_CTRL 40
229#define MXC91231_INT_IPU_ERR 41
230#define MXC91231_INT_IPU_SYN 42
231#define MXC91231_INT_UART1_RX 43
232#define MXC91231_INT_UART1_TX 44
233#define MXC91231_INT_UART1_MINT 45
234#define MXC91231_INT_IIM 46
235#define MXC91231_INT_MU_RX_OR 47
236#define MXC91231_INT_MU_TX_OR 48
237#define MXC91231_INT_SCC_SCM 49
238#define MXC91231_INT_SCC_SMN 50
239#define MXC91231_INT_GPIO2 51
240#define MXC91231_INT_GPIO1 52
241#define MXC91231_INT_MQSPI1 53
242#define MXC91231_INT_MQSPI2 54
243#define MXC91231_INT_WDOG2 55
244#define MXC91231_INT_EXT_INT7 56
245#define MXC91231_INT_EXT_INT6 57
246#define MXC91231_INT_EXT_INT5 58
247#define MXC91231_INT_EXT_INT4 59
248#define MXC91231_INT_EXT_INT3 60
249#define MXC91231_INT_EXT_INT2 61
250#define MXC91231_INT_EXT_INT1 62
251#define MXC91231_INT_EXT_INT0 63
252
253#define MXC91231_MAX_INT_LINES 63
254#define MXC91231_MAX_EXT_LINES 8
255
256#endif /* __MACH_MXC91231_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/system.h b/arch/arm/plat-mxc/include/mach/system.h
index 0417da9f710d..51f02a9d41a3 100644
--- a/arch/arm/plat-mxc/include/mach/system.h
+++ b/arch/arm/plat-mxc/include/mach/system.h
@@ -24,12 +24,6 @@ extern void mx5_cpu_lp_set(enum mxc_cpu_pwr_mode mode);
24 24
25static inline void arch_idle(void) 25static inline void arch_idle(void)
26{ 26{
27#ifdef CONFIG_ARCH_MXC91231
28 if (cpu_is_mxc91231()) {
29 /* Need this to set DSM low-power mode */
30 mxc91231_prepare_idle();
31 }
32#endif
33 /* fix i.MX31 errata TLSbo65953 and i.MX35 errata ENGcm09472 */ 27 /* fix i.MX31 errata TLSbo65953 and i.MX35 errata ENGcm09472 */
34 if (cpu_is_mx31() || cpu_is_mx35()) { 28 if (cpu_is_mx31() || cpu_is_mx35()) {
35 unsigned long reg = 0; 29 unsigned long reg = 0;
diff --git a/arch/arm/plat-mxc/include/mach/timex.h b/arch/arm/plat-mxc/include/mach/timex.h
index 2d9624697cc9..d61d5c74817c 100644
--- a/arch/arm/plat-mxc/include/mach/timex.h
+++ b/arch/arm/plat-mxc/include/mach/timex.h
@@ -26,8 +26,6 @@
26#define CLOCK_TICK_RATE 16000000 26#define CLOCK_TICK_RATE 16000000
27#elif defined CONFIG_ARCH_MX5 27#elif defined CONFIG_ARCH_MX5
28#define CLOCK_TICK_RATE 8000000 28#define CLOCK_TICK_RATE 8000000
29#elif defined CONFIG_ARCH_MXC91231
30#define CLOCK_TICK_RATE 13000000
31#endif 29#endif
32 30
33#endif /* __ASM_ARCH_MXC_TIMEX_H__ */ 31#endif /* __ASM_ARCH_MXC_TIMEX_H__ */
diff --git a/arch/arm/plat-mxc/system.c b/arch/arm/plat-mxc/system.c
index 3455fc0575a6..8024f2ac177c 100644
--- a/arch/arm/plat-mxc/system.c
+++ b/arch/arm/plat-mxc/system.c
@@ -37,12 +37,6 @@ void arch_reset(char mode, const char *cmd)
37{ 37{
38 unsigned int wcr_enable; 38 unsigned int wcr_enable;
39 39
40#ifdef CONFIG_ARCH_MXC91231
41 if (cpu_is_mxc91231()) {
42 mxc91231_arch_reset(mode, cmd);
43 return;
44 }
45#endif
46#ifdef CONFIG_MACH_MX51_EFIKAMX 40#ifdef CONFIG_MACH_MX51_EFIKAMX
47 if (machine_is_mx51_efikamx()) { 41 if (machine_is_mx51_efikamx()) {
48 mx51_efikamx_reset(); 42 mx51_efikamx_reset();
diff --git a/arch/arm/plat-mxc/time.c b/arch/arm/plat-mxc/time.c
index 2237ff8b434f..40f32e7950ae 100644
--- a/arch/arm/plat-mxc/time.c
+++ b/arch/arm/plat-mxc/time.c
@@ -54,7 +54,7 @@
54#define MX2_TSTAT_CAPT (1 << 1) 54#define MX2_TSTAT_CAPT (1 << 1)
55#define MX2_TSTAT_COMP (1 << 0) 55#define MX2_TSTAT_COMP (1 << 0)
56 56
57/* MX31, MX35, MX25, MXC91231, MX5 */ 57/* MX31, MX35, MX25, MX5 */
58#define V2_TCTL_WAITEN (1 << 3) /* Wait enable mode */ 58#define V2_TCTL_WAITEN (1 << 3) /* Wait enable mode */
59#define V2_TCTL_CLK_IPG (1 << 6) 59#define V2_TCTL_CLK_IPG (1 << 6)
60#define V2_TCTL_FRR (1 << 9) 60#define V2_TCTL_FRR (1 << 9)
generated by cgit v1.2.2 (git 2.25.0) at 2024-09-25 06:18:03 -0400