aboutsummaryrefslogtreecommitdiffstats
path: root/arch
diff options
context:
space:
mode:
authorMarkos Chandras <markos.chandras@imgtec.com>2013-10-30 10:27:48 -0400
committerRalf Baechle <ralf@linux-mips.org>2013-10-30 10:43:18 -0400
commit13b7ea6377fb23f02784a38e894f8fad49816376 (patch)
tree9d248b18ca861092fc59db81f46f35ae36ea4532 /arch
parent7f081f175502373673c015a4d0fa1d5cc264758a (diff)
MIPS: malta: Fix GIC interrupt offsets
The GIC interrupt offsets are calculated based on the value of NR_CPUS. However, this is wrong because NR_CPUS may or may not contain the real number of the actual cpus present in the system. We fix that by using the 'nr_cpu_ids' variable which contains the real number of cpus in the system. Previously, an MT core (eg with 8 VPEs) will fail to boot if NR_CPUS was > 8 with the following errors: ------------[ cut here ]------------ WARNING: CPU: 0 PID: 0 at kernel/irq/chip.c:670 __irq_set_handler+0x15c/0x164() Modules linked in: CPU: 0 PID: 0 Comm: swapper/0 Tainted: G W 3.12.0-rc5-00087-gced5633 5 Stack : 00000006 00000004 00000000 00000000 00000000 00000000 807a4f36 00000053 807a0000 00000000 80173218 80565aa8 00000000 00000000 00000000 0000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 0000000 00000000 00000000 00000000 8054fd00 8054fd94 80500514 805657a7 8016eb4 807a0000 80500514 00000000 00000000 80565aa8 8079a5d8 80565766 8054fd0 ... Call Trace: [<801098c0>] show_stack+0x64/0x7c [<8049c6b0>] dump_stack+0x64/0x84 [<8012efc4>] warn_slowpath_common+0x84/0xb4 [<8012f00c>] warn_slowpath_null+0x18/0x24 [<80173218>] __irq_set_handler+0x15c/0x164 [<80587cf4>] arch_init_ipiirq+0x2c/0x3c [<805880c8>] arch_init_irq+0x3c4/0x4bc [<80588e28>] init_IRQ+0x3c/0x50 [<805847e8>] start_kernel+0x230/0x3d8 ---[ end trace 4eaa2a86a8e2da26 ]--- This is now fixed and the Malta board can boot with any NR_CPUS value which also helps supporting more processors in a single kernel binary. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6091/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch')
-rw-r--r--arch/mips/mti-malta/malta-int.c9
1 files changed, 5 insertions, 4 deletions
diff --git a/arch/mips/mti-malta/malta-int.c b/arch/mips/mti-malta/malta-int.c
index c69da3734699..5b28e81d94a0 100644
--- a/arch/mips/mti-malta/malta-int.c
+++ b/arch/mips/mti-malta/malta-int.c
@@ -473,7 +473,7 @@ static void __init fill_ipi_map(void)
473{ 473{
474 int cpu; 474 int cpu;
475 475
476 for (cpu = 0; cpu < NR_CPUS; cpu++) { 476 for (cpu = 0; cpu < nr_cpu_ids; cpu++) {
477 fill_ipi_map1(gic_resched_int_base, cpu, GIC_CPU_INT1); 477 fill_ipi_map1(gic_resched_int_base, cpu, GIC_CPU_INT1);
478 fill_ipi_map1(gic_call_int_base, cpu, GIC_CPU_INT2); 478 fill_ipi_map1(gic_call_int_base, cpu, GIC_CPU_INT2);
479 } 479 }
@@ -574,8 +574,9 @@ void __init arch_init_irq(void)
574 /* FIXME */ 574 /* FIXME */
575 int i; 575 int i;
576#if defined(CONFIG_MIPS_MT_SMP) 576#if defined(CONFIG_MIPS_MT_SMP)
577 gic_call_int_base = GIC_NUM_INTRS - NR_CPUS; 577 gic_call_int_base = GIC_NUM_INTRS -
578 gic_resched_int_base = gic_call_int_base - NR_CPUS; 578 (NR_CPUS - nr_cpu_ids) * 2 - nr_cpu_ids;
579 gic_resched_int_base = gic_call_int_base - nr_cpu_ids;
579 fill_ipi_map(); 580 fill_ipi_map();
580#endif 581#endif
581 gic_init(GIC_BASE_ADDR, GIC_ADDRSPACE_SZ, gic_intr_map, 582 gic_init(GIC_BASE_ADDR, GIC_ADDRSPACE_SZ, gic_intr_map,
@@ -599,7 +600,7 @@ void __init arch_init_irq(void)
599 printk("CPU%d: status register now %08x\n", smp_processor_id(), read_c0_status()); 600 printk("CPU%d: status register now %08x\n", smp_processor_id(), read_c0_status());
600 write_c0_status(0x1100dc00); 601 write_c0_status(0x1100dc00);
601 printk("CPU%d: status register frc %08x\n", smp_processor_id(), read_c0_status()); 602 printk("CPU%d: status register frc %08x\n", smp_processor_id(), read_c0_status());
602 for (i = 0; i < NR_CPUS; i++) { 603 for (i = 0; i < nr_cpu_ids; i++) {
603 arch_init_ipiirq(MIPS_GIC_IRQ_BASE + 604 arch_init_ipiirq(MIPS_GIC_IRQ_BASE +
604 GIC_RESCHED_INT(i), &irq_resched); 605 GIC_RESCHED_INT(i), &irq_resched);
605 arch_init_ipiirq(MIPS_GIC_IRQ_BASE + 606 arch_init_ipiirq(MIPS_GIC_IRQ_BASE +