MIPS: Emulate the new MIPS R6 BNVC, BNEC and BNEZLAC instructions

MIPS R6 uses the <R6 DADDI opcode for the new BNVC, BNEC and
BNEZLAC instructions.

Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>

3 files changed, 7 insertions, 2 deletions

diff --git a/arch/mips/include/uapi/asm/inst.h b/arch/mips/include/uapi/asm/inst.h
index 782af0f83421..78335414b18a 100644
--- a/arch/mips/include/uapi/asm/inst.h
+++ b/arch/mips/include/uapi/asm/inst.h
@@ -25,7 +25,7 @@ enum major_op {
         andi_op, ori_op, xori_op, lui_op,
         cop0_op, cop1_op, cop2_op, cop1x_op,
         beql_op, bnel_op, blezl_op, bgtzl_op,
-        daddi_op, daddiu_op, ldl_op, ldr_op,
+        daddi_op, cbcond1_op = daddi_op, daddiu_op, ldl_op, ldr_op,
         spec2_op, jalx_op, mdmx_op, spec3_op,
         lb_op, lh_op, lwl_op, lw_op,
         lbu_op, lhu_op, lwr_op, lwu_op,
diff --git a/arch/mips/kernel/branch.c b/arch/mips/kernel/branch.c
index 80a073ced200..37c752757346 100644
--- a/arch/mips/kernel/branch.c
+++ b/arch/mips/kernel/branch.c
@@ -791,12 +791,16 @@ int __compute_return_epc_for_insn(struct pt_regs *regs,
                 break;
 #endif
         case cbcond0_op:
+        case cbcond1_op:
                 /* Only valid for MIPS R6 */
                 if (!cpu_has_mips_r6) {
                         ret = -SIGILL;
                         break;
                 }
-                /* Compact branches: bovc, beqc, beqzalc */
+                /*
+                 * Compact branches:
+                 * bovc, beqc, beqzalc, bnvc, bnec, bnezlac
+                 */
                 if (insn.i_format.rt && !insn.i_format.rs)
                         regs->regs[31] = epc + 4;
                 regs->cp0_epc += 8;
diff --git a/arch/mips/math-emu/cp1emu.c b/arch/mips/math-emu/cp1emu.c
index c115d969664b..0d8407b51470 100644
--- a/arch/mips/math-emu/cp1emu.c
+++ b/arch/mips/math-emu/cp1emu.c
@@ -624,6 +624,7 @@ static int isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn,
                                 dec_insn.next_pc_inc;
                 return 1;
         case cbcond0_op:
+        case cbcond1_op:
                 if (!cpu_has_mips_r6)
                         break;
                 if (insn.i_format.rt && !insn.i_format.rs)