diff options
author | Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> | 2012-02-22 11:50:53 -0500 |
---|---|---|
committer | Nicolas Ferre <nicolas.ferre@atmel.com> | 2012-02-23 03:26:40 -0500 |
commit | 0dcfed1486739afdce053ebdccac28076e9d9e1f (patch) | |
tree | d1827133c81612151fde94d7198865e405c85c9d /arch | |
parent | 9e1c0b2ee8ae69dd4b35187ffbfb749272db3e00 (diff) |
ARM: at91/pm_slowclock: rename register to named define
This patch will give a name to ARM registers in the assembly
source code. It is done to simplify the code reading and
the passing of parameters to functions.
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Diffstat (limited to 'arch')
-rw-r--r-- | arch/arm/mach-at91/pm_slowclock.S | 177 |
1 files changed, 91 insertions, 86 deletions
diff --git a/arch/arm/mach-at91/pm_slowclock.S b/arch/arm/mach-at91/pm_slowclock.S index f8539a8bcd6c..c802d309582f 100644 --- a/arch/arm/mach-at91/pm_slowclock.S +++ b/arch/arm/mach-at91/pm_slowclock.S | |||
@@ -46,17 +46,22 @@ | |||
46 | #define PLLALOCK_TIMEOUT 1000 | 46 | #define PLLALOCK_TIMEOUT 1000 |
47 | #define PLLBLOCK_TIMEOUT 1000 | 47 | #define PLLBLOCK_TIMEOUT 1000 |
48 | 48 | ||
49 | pmc .req r1 | ||
50 | sdramc .req r2 | ||
51 | tmp1 .req r3 | ||
52 | tmp2 .req r4 | ||
53 | ramc1 .req r5 | ||
49 | 54 | ||
50 | /* | 55 | /* |
51 | * Wait until master clock is ready (after switching master clock source) | 56 | * Wait until master clock is ready (after switching master clock source) |
52 | */ | 57 | */ |
53 | .macro wait_mckrdy | 58 | .macro wait_mckrdy |
54 | mov r4, #MCKRDY_TIMEOUT | 59 | mov tmp2, #MCKRDY_TIMEOUT |
55 | 1: sub r4, r4, #1 | 60 | 1: sub tmp2, tmp2, #1 |
56 | cmp r4, #0 | 61 | cmp tmp2, #0 |
57 | beq 2f | 62 | beq 2f |
58 | ldr r3, [r1, #(AT91_PMC_SR - AT91_PMC)] | 63 | ldr tmp1, [pmc, #(AT91_PMC_SR - AT91_PMC)] |
59 | tst r3, #AT91_PMC_MCKRDY | 64 | tst tmp1, #AT91_PMC_MCKRDY |
60 | beq 1b | 65 | beq 1b |
61 | 2: | 66 | 2: |
62 | .endm | 67 | .endm |
@@ -65,12 +70,12 @@ | |||
65 | * Wait until master oscillator has stabilized. | 70 | * Wait until master oscillator has stabilized. |
66 | */ | 71 | */ |
67 | .macro wait_moscrdy | 72 | .macro wait_moscrdy |
68 | mov r4, #MOSCRDY_TIMEOUT | 73 | mov tmp2, #MOSCRDY_TIMEOUT |
69 | 1: sub r4, r4, #1 | 74 | 1: sub tmp2, tmp2, #1 |
70 | cmp r4, #0 | 75 | cmp tmp2, #0 |
71 | beq 2f | 76 | beq 2f |
72 | ldr r3, [r1, #(AT91_PMC_SR - AT91_PMC)] | 77 | ldr tmp1, [pmc, #(AT91_PMC_SR - AT91_PMC)] |
73 | tst r3, #AT91_PMC_MOSCS | 78 | tst tmp1, #AT91_PMC_MOSCS |
74 | beq 1b | 79 | beq 1b |
75 | 2: | 80 | 2: |
76 | .endm | 81 | .endm |
@@ -79,12 +84,12 @@ | |||
79 | * Wait until PLLA has locked. | 84 | * Wait until PLLA has locked. |
80 | */ | 85 | */ |
81 | .macro wait_pllalock | 86 | .macro wait_pllalock |
82 | mov r4, #PLLALOCK_TIMEOUT | 87 | mov tmp2, #PLLALOCK_TIMEOUT |
83 | 1: sub r4, r4, #1 | 88 | 1: sub tmp2, tmp2, #1 |
84 | cmp r4, #0 | 89 | cmp tmp2, #0 |
85 | beq 2f | 90 | beq 2f |
86 | ldr r3, [r1, #(AT91_PMC_SR - AT91_PMC)] | 91 | ldr tmp1, [pmc, #(AT91_PMC_SR - AT91_PMC)] |
87 | tst r3, #AT91_PMC_LOCKA | 92 | tst tmp1, #AT91_PMC_LOCKA |
88 | beq 1b | 93 | beq 1b |
89 | 2: | 94 | 2: |
90 | .endm | 95 | .endm |
@@ -93,12 +98,12 @@ | |||
93 | * Wait until PLLB has locked. | 98 | * Wait until PLLB has locked. |
94 | */ | 99 | */ |
95 | .macro wait_pllblock | 100 | .macro wait_pllblock |
96 | mov r4, #PLLBLOCK_TIMEOUT | 101 | mov tmp2, #PLLBLOCK_TIMEOUT |
97 | 1: sub r4, r4, #1 | 102 | 1: sub tmp2, tmp2, #1 |
98 | cmp r4, #0 | 103 | cmp tmp2, #0 |
99 | beq 2f | 104 | beq 2f |
100 | ldr r3, [r1, #(AT91_PMC_SR - AT91_PMC)] | 105 | ldr tmp1, [pmc, #(AT91_PMC_SR - AT91_PMC)] |
101 | tst r3, #AT91_PMC_LOCKB | 106 | tst tmp1, #AT91_PMC_LOCKB |
102 | beq 1b | 107 | beq 1b |
103 | 2: | 108 | 2: |
104 | .endm | 109 | .endm |
@@ -117,55 +122,55 @@ ENTRY(at91_slow_clock) | |||
117 | * R4 = temporary register | 122 | * R4 = temporary register |
118 | * R5 = Base address of second RAM Controller or 0 if not present | 123 | * R5 = Base address of second RAM Controller or 0 if not present |
119 | */ | 124 | */ |
120 | ldr r1, .at91_va_base_pmc | 125 | ldr pmc, .at91_va_base_pmc |
121 | ldr r2, .at91_va_base_sdramc | 126 | ldr sdramc, .at91_va_base_sdramc |
122 | ldr r5, .at91_va_base_ramc1 | 127 | ldr ramc1, .at91_va_base_ramc1 |
123 | 128 | ||
124 | /* Drain write buffer */ | 129 | /* Drain write buffer */ |
125 | mov r0, #0 | 130 | mov tmp1, #0 |
126 | mcr p15, 0, r0, c7, c10, 4 | 131 | mcr p15, 0, tmp1, c7, c10, 4 |
127 | 132 | ||
128 | #ifdef CONFIG_ARCH_AT91RM9200 | 133 | #ifdef CONFIG_ARCH_AT91RM9200 |
129 | /* Put SDRAM in self-refresh mode */ | 134 | /* Put SDRAM in self-refresh mode */ |
130 | mov r3, #1 | 135 | mov tmp1, #1 |
131 | str r3, [r2, #AT91_SDRAMC_SRR] | 136 | str tmp1, [sdramc, #AT91_SDRAMC_SRR] |
132 | #elif defined(CONFIG_ARCH_AT91SAM9G45) | 137 | #elif defined(CONFIG_ARCH_AT91SAM9G45) |
133 | 138 | ||
134 | /* prepare for DDRAM self-refresh mode */ | 139 | /* prepare for DDRAM self-refresh mode */ |
135 | ldr r3, [r2, #AT91_DDRSDRC_LPR] | 140 | ldr tmp1, [sdramc, #AT91_DDRSDRC_LPR] |
136 | str r3, .saved_sam9_lpr | 141 | str tmp1, .saved_sam9_lpr |
137 | bic r3, #AT91_DDRSDRC_LPCB | 142 | bic tmp1, #AT91_DDRSDRC_LPCB |
138 | orr r3, #AT91_DDRSDRC_LPCB_SELF_REFRESH | 143 | orr tmp1, #AT91_DDRSDRC_LPCB_SELF_REFRESH |
139 | 144 | ||
140 | /* figure out if we use the second ram controller */ | 145 | /* figure out if we use the second ram controller */ |
141 | cmp r5, #0 | 146 | cmp ramc1, #0 |
142 | ldrne r4, [r5, #AT91_DDRSDRC_LPR] | 147 | ldrne tmp2, [ramc1, #AT91_DDRSDRC_LPR] |
143 | strne r4, .saved_sam9_lpr1 | 148 | strne tmp2, .saved_sam9_lpr1 |
144 | bicne r4, #AT91_DDRSDRC_LPCB | 149 | bicne tmp2, #AT91_DDRSDRC_LPCB |
145 | orrne r4, #AT91_DDRSDRC_LPCB_SELF_REFRESH | 150 | orrne tmp2, #AT91_DDRSDRC_LPCB_SELF_REFRESH |
146 | 151 | ||
147 | /* Enable DDRAM self-refresh mode */ | 152 | /* Enable DDRAM self-refresh mode */ |
148 | str r3, [r2, #AT91_DDRSDRC_LPR] | 153 | str tmp1, [sdramc, #AT91_DDRSDRC_LPR] |
149 | strne r4, [r5, #AT91_DDRSDRC_LPR] | 154 | strne tmp2, [ramc1, #AT91_DDRSDRC_LPR] |
150 | #else | 155 | #else |
151 | /* Enable SDRAM self-refresh mode */ | 156 | /* Enable SDRAM self-refresh mode */ |
152 | ldr r3, [r2, #AT91_SDRAMC_LPR] | 157 | ldr tmp1, [sdramc, #AT91_SDRAMC_LPR] |
153 | str r3, .saved_sam9_lpr | 158 | str tmp1, .saved_sam9_lpr |
154 | 159 | ||
155 | bic r3, #AT91_SDRAMC_LPCB | 160 | bic tmp1, #AT91_SDRAMC_LPCB |
156 | orr r3, #AT91_SDRAMC_LPCB_SELF_REFRESH | 161 | orr tmp1, #AT91_SDRAMC_LPCB_SELF_REFRESH |
157 | str r3, [r2, #AT91_SDRAMC_LPR] | 162 | str tmp1, [sdramc, #AT91_SDRAMC_LPR] |
158 | #endif | 163 | #endif |
159 | 164 | ||
160 | /* Save Master clock setting */ | 165 | /* Save Master clock setting */ |
161 | ldr r3, [r1, #(AT91_PMC_MCKR - AT91_PMC)] | 166 | ldr tmp1, [pmc, #(AT91_PMC_MCKR - AT91_PMC)] |
162 | str r3, .saved_mckr | 167 | str tmp1, .saved_mckr |
163 | 168 | ||
164 | /* | 169 | /* |
165 | * Set the Master clock source to slow clock | 170 | * Set the Master clock source to slow clock |
166 | */ | 171 | */ |
167 | bic r3, r3, #AT91_PMC_CSS | 172 | bic tmp1, tmp1, #AT91_PMC_CSS |
168 | str r3, [r1, #(AT91_PMC_MCKR - AT91_PMC)] | 173 | str tmp1, [pmc, #(AT91_PMC_MCKR - AT91_PMC)] |
169 | 174 | ||
170 | wait_mckrdy | 175 | wait_mckrdy |
171 | 176 | ||
@@ -175,61 +180,61 @@ ENTRY(at91_slow_clock) | |||
175 | * | 180 | * |
176 | * See AT91RM9200 errata #27 and #28 for details. | 181 | * See AT91RM9200 errata #27 and #28 for details. |
177 | */ | 182 | */ |
178 | mov r3, #0 | 183 | mov tmp1, #0 |
179 | str r3, [r1, #(AT91_PMC_MCKR - AT91_PMC)] | 184 | str tmp1, [pmc, #(AT91_PMC_MCKR - AT91_PMC)] |
180 | 185 | ||
181 | wait_mckrdy | 186 | wait_mckrdy |
182 | #endif | 187 | #endif |
183 | 188 | ||
184 | /* Save PLLA setting and disable it */ | 189 | /* Save PLLA setting and disable it */ |
185 | ldr r3, [r1, #(AT91_CKGR_PLLAR - AT91_PMC)] | 190 | ldr tmp1, [pmc, #(AT91_CKGR_PLLAR - AT91_PMC)] |
186 | str r3, .saved_pllar | 191 | str tmp1, .saved_pllar |
187 | 192 | ||
188 | mov r3, #AT91_PMC_PLLCOUNT | 193 | mov tmp1, #AT91_PMC_PLLCOUNT |
189 | orr r3, r3, #(1 << 29) /* bit 29 always set */ | 194 | orr tmp1, tmp1, #(1 << 29) /* bit 29 always set */ |
190 | str r3, [r1, #(AT91_CKGR_PLLAR - AT91_PMC)] | 195 | str tmp1, [pmc, #(AT91_CKGR_PLLAR - AT91_PMC)] |
191 | 196 | ||
192 | /* Save PLLB setting and disable it */ | 197 | /* Save PLLB setting and disable it */ |
193 | ldr r3, [r1, #(AT91_CKGR_PLLBR - AT91_PMC)] | 198 | ldr tmp1, [pmc, #(AT91_CKGR_PLLBR - AT91_PMC)] |
194 | str r3, .saved_pllbr | 199 | str tmp1, .saved_pllbr |
195 | 200 | ||
196 | mov r3, #AT91_PMC_PLLCOUNT | 201 | mov tmp1, #AT91_PMC_PLLCOUNT |
197 | str r3, [r1, #(AT91_CKGR_PLLBR - AT91_PMC)] | 202 | str tmp1, [pmc, #(AT91_CKGR_PLLBR - AT91_PMC)] |
198 | 203 | ||
199 | /* Turn off the main oscillator */ | 204 | /* Turn off the main oscillator */ |
200 | ldr r3, [r1, #(AT91_CKGR_MOR - AT91_PMC)] | 205 | ldr tmp1, [pmc, #(AT91_CKGR_MOR - AT91_PMC)] |
201 | bic r3, r3, #AT91_PMC_MOSCEN | 206 | bic tmp1, tmp1, #AT91_PMC_MOSCEN |
202 | str r3, [r1, #(AT91_CKGR_MOR - AT91_PMC)] | 207 | str tmp1, [pmc, #(AT91_CKGR_MOR - AT91_PMC)] |
203 | 208 | ||
204 | /* Wait for interrupt */ | 209 | /* Wait for interrupt */ |
205 | mcr p15, 0, r0, c7, c0, 4 | 210 | mcr p15, 0, tmp1, c7, c0, 4 |
206 | 211 | ||
207 | /* Turn on the main oscillator */ | 212 | /* Turn on the main oscillator */ |
208 | ldr r3, [r1, #(AT91_CKGR_MOR - AT91_PMC)] | 213 | ldr tmp1, [pmc, #(AT91_CKGR_MOR - AT91_PMC)] |
209 | orr r3, r3, #AT91_PMC_MOSCEN | 214 | orr tmp1, tmp1, #AT91_PMC_MOSCEN |
210 | str r3, [r1, #(AT91_CKGR_MOR - AT91_PMC)] | 215 | str tmp1, [pmc, #(AT91_CKGR_MOR - AT91_PMC)] |
211 | 216 | ||
212 | wait_moscrdy | 217 | wait_moscrdy |
213 | 218 | ||
214 | /* Restore PLLB setting */ | 219 | /* Restore PLLB setting */ |
215 | ldr r3, .saved_pllbr | 220 | ldr tmp1, .saved_pllbr |
216 | str r3, [r1, #(AT91_CKGR_PLLBR - AT91_PMC)] | 221 | str tmp1, [pmc, #(AT91_CKGR_PLLBR - AT91_PMC)] |
217 | 222 | ||
218 | tst r3, #(AT91_PMC_MUL & 0xff0000) | 223 | tst tmp1, #(AT91_PMC_MUL & 0xff0000) |
219 | bne 1f | 224 | bne 1f |
220 | tst r3, #(AT91_PMC_MUL & ~0xff0000) | 225 | tst tmp1, #(AT91_PMC_MUL & ~0xff0000) |
221 | beq 2f | 226 | beq 2f |
222 | 1: | 227 | 1: |
223 | wait_pllblock | 228 | wait_pllblock |
224 | 2: | 229 | 2: |
225 | 230 | ||
226 | /* Restore PLLA setting */ | 231 | /* Restore PLLA setting */ |
227 | ldr r3, .saved_pllar | 232 | ldr tmp1, .saved_pllar |
228 | str r3, [r1, #(AT91_CKGR_PLLAR - AT91_PMC)] | 233 | str tmp1, [pmc, #(AT91_CKGR_PLLAR - AT91_PMC)] |
229 | 234 | ||
230 | tst r3, #(AT91_PMC_MUL & 0xff0000) | 235 | tst tmp1, #(AT91_PMC_MUL & 0xff0000) |
231 | bne 3f | 236 | bne 3f |
232 | tst r3, #(AT91_PMC_MUL & ~0xff0000) | 237 | tst tmp1, #(AT91_PMC_MUL & ~0xff0000) |
233 | beq 4f | 238 | beq 4f |
234 | 3: | 239 | 3: |
235 | wait_pllalock | 240 | wait_pllalock |
@@ -242,11 +247,11 @@ ENTRY(at91_slow_clock) | |||
242 | * | 247 | * |
243 | * See AT91RM9200 errata #27 and #28 for details. | 248 | * See AT91RM9200 errata #27 and #28 for details. |
244 | */ | 249 | */ |
245 | ldr r3, .saved_mckr | 250 | ldr tmp1, .saved_mckr |
246 | tst r3, #AT91_PMC_PRES | 251 | tst tmp1, #AT91_PMC_PRES |
247 | beq 2f | 252 | beq 2f |
248 | and r3, r3, #AT91_PMC_PRES | 253 | and tmp1, tmp1, #AT91_PMC_PRES |
249 | str r3, [r1, #(AT91_PMC_MCKR - AT91_PMC)] | 254 | str tmp1, [pmc, #(AT91_PMC_MCKR - AT91_PMC)] |
250 | 255 | ||
251 | wait_mckrdy | 256 | wait_mckrdy |
252 | #endif | 257 | #endif |
@@ -254,8 +259,8 @@ ENTRY(at91_slow_clock) | |||
254 | /* | 259 | /* |
255 | * Restore master clock setting | 260 | * Restore master clock setting |
256 | */ | 261 | */ |
257 | 2: ldr r3, .saved_mckr | 262 | 2: ldr tmp1, .saved_mckr |
258 | str r3, [r1, #(AT91_PMC_MCKR - AT91_PMC)] | 263 | str tmp1, [pmc, #(AT91_PMC_MCKR - AT91_PMC)] |
259 | 264 | ||
260 | wait_mckrdy | 265 | wait_mckrdy |
261 | 266 | ||
@@ -263,18 +268,18 @@ ENTRY(at91_slow_clock) | |||
263 | /* Do nothing - self-refresh is automatically disabled. */ | 268 | /* Do nothing - self-refresh is automatically disabled. */ |
264 | #elif defined(CONFIG_ARCH_AT91SAM9G45) | 269 | #elif defined(CONFIG_ARCH_AT91SAM9G45) |
265 | /* Restore LPR on AT91 with DDRAM */ | 270 | /* Restore LPR on AT91 with DDRAM */ |
266 | ldr r3, .saved_sam9_lpr | 271 | ldr tmp1, .saved_sam9_lpr |
267 | str r3, [r2, #AT91_DDRSDRC_LPR] | 272 | str tmp1, [sdramc, #AT91_DDRSDRC_LPR] |
268 | 273 | ||
269 | /* if we use the second ram controller */ | 274 | /* if we use the second ram controller */ |
270 | cmp r5, #0 | 275 | cmp ramc1, #0 |
271 | ldrne r4, .saved_sam9_lpr1 | 276 | ldrne tmp2, .saved_sam9_lpr1 |
272 | strne r4, [r5, #AT91_DDRSDRC_LPR] | 277 | strne tmp2, [ramc1, #AT91_DDRSDRC_LPR] |
273 | 278 | ||
274 | #else | 279 | #else |
275 | /* Restore LPR on AT91 with SDRAM */ | 280 | /* Restore LPR on AT91 with SDRAM */ |
276 | ldr r3, .saved_sam9_lpr | 281 | ldr tmp1, .saved_sam9_lpr |
277 | str r3, [r2, #AT91_SDRAMC_LPR] | 282 | str tmp1, [sdramc, #AT91_SDRAMC_LPR] |
278 | #endif | 283 | #endif |
279 | 284 | ||
280 | /* Restore registers, and return */ | 285 | /* Restore registers, and return */ |