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authorPaul Gortmaker <paul.gortmaker@windriver.com>2013-06-18 09:38:59 -0400
committerPaul Gortmaker <paul.gortmaker@windriver.com>2013-07-14 19:36:51 -0400
commit078a55fc824c1633b3a507e4ad48b4637c1dfc18 (patch)
treeb7abb8d50bf6e322baaea322e9224d7715b52f5b /arch
parent60ffef065dd40b91f6f76af6c7510ddf23102f54 (diff)
MIPS: Delete __cpuinit/__CPUINIT usage from MIPS code
commit 3747069b25e419f6b51395f48127e9812abc3596 upstream. The __cpuinit type of throwaway sections might have made sense some time ago when RAM was more constrained, but now the savings do not offset the cost and complications. For example, the fix in commit 5e427ec2d0 ("x86: Fix bit corruption at CPU resume time") is a good example of the nasty type of bugs that can be created with improper use of the various __init prefixes. After a discussion on LKML[1] it was decided that cpuinit should go the way of devinit and be phased out. Once all the users are gone, we can then finally remove the macros themselves from linux/init.h. Note that some harmless section mismatch warnings may result, since notify_cpu_starting() and cpu_up() are arch independent (kernel/cpu.c) and are flagged as __cpuinit -- so if we remove the __cpuinit from the arch specific callers, we will also get section mismatch warnings. As an intermediate step, we intend to turn the linux/init.h cpuinit related content into no-ops as early as possible, since that will get rid of these warnings. In any case, they are temporary and harmless. Here, we remove all the MIPS __cpuinit from C code and __CPUINIT from asm files. MIPS is interesting in this respect, because there are also uasm users hiding behind their own renamed versions of the __cpuinit macros. [1] https://lkml.org/lkml/2013/5/20/589 [ralf@linux-mips.org: Folded in Paul's followup fix.] Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5494/ Patchwork: https://patchwork.linux-mips.org/patch/5495/ Patchwork: https://patchwork.linux-mips.org/patch/5509/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch')
-rw-r--r--arch/mips/ath79/setup.c2
-rw-r--r--arch/mips/cavium-octeon/octeon-irq.c12
-rw-r--r--arch/mips/cavium-octeon/smp.c6
-rw-r--r--arch/mips/include/asm/uasm.h37
-rw-r--r--arch/mips/kernel/bmips_vec.S4
-rw-r--r--arch/mips/kernel/cevt-bcm1480.c2
-rw-r--r--arch/mips/kernel/cevt-gic.c2
-rw-r--r--arch/mips/kernel/cevt-r4k.c2
-rw-r--r--arch/mips/kernel/cevt-sb1250.c2
-rw-r--r--arch/mips/kernel/cevt-smtc.c2
-rw-r--r--arch/mips/kernel/cpu-bugs64.c2
-rw-r--r--arch/mips/kernel/cpu-probe.c14
-rw-r--r--arch/mips/kernel/head.S4
-rw-r--r--arch/mips/kernel/smp-bmips.c6
-rw-r--r--arch/mips/kernel/smp-mt.c6
-rw-r--r--arch/mips/kernel/smp-up.c6
-rw-r--r--arch/mips/kernel/smp.c6
-rw-r--r--arch/mips/kernel/smtc.c2
-rw-r--r--arch/mips/kernel/spram.c14
-rw-r--r--arch/mips/kernel/sync-r4k.c12
-rw-r--r--arch/mips/kernel/traps.c12
-rw-r--r--arch/mips/kernel/watch.c2
-rw-r--r--arch/mips/lantiq/irq.c2
-rw-r--r--arch/mips/lib/uncached.c2
-rw-r--r--arch/mips/mm/c-octeon.c6
-rw-r--r--arch/mips/mm/c-r3k.c8
-rw-r--r--arch/mips/mm/c-r4k.c34
-rw-r--r--arch/mips/mm/c-tx39.c2
-rw-r--r--arch/mips/mm/cache.c2
-rw-r--r--arch/mips/mm/cex-sb1.S4
-rw-r--r--arch/mips/mm/page.c40
-rw-r--r--arch/mips/mm/sc-ip22.c2
-rw-r--r--arch/mips/mm/sc-mips.c2
-rw-r--r--arch/mips/mm/sc-r5k.c2
-rw-r--r--arch/mips/mm/sc-rm7k.c12
-rw-r--r--arch/mips/mm/tlb-r3k.c2
-rw-r--r--arch/mips/mm/tlb-r4k.c4
-rw-r--r--arch/mips/mm/tlb-r8k.c4
-rw-r--r--arch/mips/mm/tlbex.c144
-rw-r--r--arch/mips/mm/uasm-micromips.c10
-rw-r--r--arch/mips/mm/uasm-mips.c10
-rw-r--r--arch/mips/mm/uasm.c106
-rw-r--r--arch/mips/mti-malta/malta-smtc.c6
-rw-r--r--arch/mips/mti-malta/malta-time.c2
-rw-r--r--arch/mips/mti-sead3/sead3-time.c2
-rw-r--r--arch/mips/netlogic/common/smp.c4
-rw-r--r--arch/mips/netlogic/common/smpboot.S4
-rw-r--r--arch/mips/netlogic/common/time.c2
-rw-r--r--arch/mips/netlogic/xlr/wakeup.c2
-rw-r--r--arch/mips/pci/pci-ip27.c2
-rw-r--r--arch/mips/pmcs-msp71xx/msp_smtc.c7
-rw-r--r--arch/mips/pmcs-msp71xx/msp_time.c2
-rw-r--r--arch/mips/pnx833x/common/interrupts.c2
-rw-r--r--arch/mips/powertv/time.c2
-rw-r--r--arch/mips/ralink/irq.c2
-rw-r--r--arch/mips/sgi-ip27/ip27-init.c4
-rw-r--r--arch/mips/sgi-ip27/ip27-smp.c6
-rw-r--r--arch/mips/sgi-ip27/ip27-timer.c6
-rw-r--r--arch/mips/sgi-ip27/ip27-xtalk.c6
-rw-r--r--arch/mips/sibyte/bcm1480/smp.c8
-rw-r--r--arch/mips/sibyte/sb1250/smp.c8
61 files changed, 294 insertions, 338 deletions
diff --git a/arch/mips/ath79/setup.c b/arch/mips/ath79/setup.c
index 8be4e856b8b8..80f4ecd42b0d 100644
--- a/arch/mips/ath79/setup.c
+++ b/arch/mips/ath79/setup.c
@@ -182,7 +182,7 @@ const char *get_system_type(void)
182 return ath79_sys_type; 182 return ath79_sys_type;
183} 183}
184 184
185unsigned int __cpuinit get_c0_compare_int(void) 185unsigned int get_c0_compare_int(void)
186{ 186{
187 return CP0_LEGACY_COMPARE_IRQ; 187 return CP0_LEGACY_COMPARE_IRQ;
188} 188}
diff --git a/arch/mips/cavium-octeon/octeon-irq.c b/arch/mips/cavium-octeon/octeon-irq.c
index 7181def6037a..9d36774bded1 100644
--- a/arch/mips/cavium-octeon/octeon-irq.c
+++ b/arch/mips/cavium-octeon/octeon-irq.c
@@ -1095,7 +1095,7 @@ static void octeon_irq_ip3_ciu(void)
1095 1095
1096static bool octeon_irq_use_ip4; 1096static bool octeon_irq_use_ip4;
1097 1097
1098static void __cpuinit octeon_irq_local_enable_ip4(void *arg) 1098static void octeon_irq_local_enable_ip4(void *arg)
1099{ 1099{
1100 set_c0_status(STATUSF_IP4); 1100 set_c0_status(STATUSF_IP4);
1101} 1101}
@@ -1110,21 +1110,21 @@ static void (*octeon_irq_ip2)(void);
1110static void (*octeon_irq_ip3)(void); 1110static void (*octeon_irq_ip3)(void);
1111static void (*octeon_irq_ip4)(void); 1111static void (*octeon_irq_ip4)(void);
1112 1112
1113void __cpuinitdata (*octeon_irq_setup_secondary)(void); 1113void (*octeon_irq_setup_secondary)(void);
1114 1114
1115void __cpuinit octeon_irq_set_ip4_handler(octeon_irq_ip4_handler_t h) 1115void octeon_irq_set_ip4_handler(octeon_irq_ip4_handler_t h)
1116{ 1116{
1117 octeon_irq_ip4 = h; 1117 octeon_irq_ip4 = h;
1118 octeon_irq_use_ip4 = true; 1118 octeon_irq_use_ip4 = true;
1119 on_each_cpu(octeon_irq_local_enable_ip4, NULL, 1); 1119 on_each_cpu(octeon_irq_local_enable_ip4, NULL, 1);
1120} 1120}
1121 1121
1122static void __cpuinit octeon_irq_percpu_enable(void) 1122static void octeon_irq_percpu_enable(void)
1123{ 1123{
1124 irq_cpu_online(); 1124 irq_cpu_online();
1125} 1125}
1126 1126
1127static void __cpuinit octeon_irq_init_ciu_percpu(void) 1127static void octeon_irq_init_ciu_percpu(void)
1128{ 1128{
1129 int coreid = cvmx_get_core_num(); 1129 int coreid = cvmx_get_core_num();
1130 1130
@@ -1167,7 +1167,7 @@ static void octeon_irq_init_ciu2_percpu(void)
1167 cvmx_read_csr(CVMX_CIU2_SUM_PPX_IP2(coreid)); 1167 cvmx_read_csr(CVMX_CIU2_SUM_PPX_IP2(coreid));
1168} 1168}
1169 1169
1170static void __cpuinit octeon_irq_setup_secondary_ciu(void) 1170static void octeon_irq_setup_secondary_ciu(void)
1171{ 1171{
1172 octeon_irq_init_ciu_percpu(); 1172 octeon_irq_init_ciu_percpu();
1173 octeon_irq_percpu_enable(); 1173 octeon_irq_percpu_enable();
diff --git a/arch/mips/cavium-octeon/smp.c b/arch/mips/cavium-octeon/smp.c
index 295137dfdc37..138cc80c5928 100644
--- a/arch/mips/cavium-octeon/smp.c
+++ b/arch/mips/cavium-octeon/smp.c
@@ -173,7 +173,7 @@ static void octeon_boot_secondary(int cpu, struct task_struct *idle)
173 * After we've done initial boot, this function is called to allow the 173 * After we've done initial boot, this function is called to allow the
174 * board code to clean up state, if needed 174 * board code to clean up state, if needed
175 */ 175 */
176static void __cpuinit octeon_init_secondary(void) 176static void octeon_init_secondary(void)
177{ 177{
178 unsigned int sr; 178 unsigned int sr;
179 179
@@ -375,7 +375,7 @@ static int octeon_update_boot_vector(unsigned int cpu)
375 return 0; 375 return 0;
376} 376}
377 377
378static int __cpuinit octeon_cpu_callback(struct notifier_block *nfb, 378static int octeon_cpu_callback(struct notifier_block *nfb,
379 unsigned long action, void *hcpu) 379 unsigned long action, void *hcpu)
380{ 380{
381 unsigned int cpu = (unsigned long)hcpu; 381 unsigned int cpu = (unsigned long)hcpu;
@@ -394,7 +394,7 @@ static int __cpuinit octeon_cpu_callback(struct notifier_block *nfb,
394 return NOTIFY_OK; 394 return NOTIFY_OK;
395} 395}
396 396
397static int __cpuinit register_cavium_notifier(void) 397static int register_cavium_notifier(void)
398{ 398{
399 hotcpu_notifier(octeon_cpu_callback, 0); 399 hotcpu_notifier(octeon_cpu_callback, 0);
400 return 0; 400 return 0;
diff --git a/arch/mips/include/asm/uasm.h b/arch/mips/include/asm/uasm.h
index 370d967725c2..c33a9564fb41 100644
--- a/arch/mips/include/asm/uasm.h
+++ b/arch/mips/include/asm/uasm.h
@@ -13,12 +13,8 @@
13 13
14#ifdef CONFIG_EXPORT_UASM 14#ifdef CONFIG_EXPORT_UASM
15#include <linux/export.h> 15#include <linux/export.h>
16#define __uasminit
17#define __uasminitdata
18#define UASM_EXPORT_SYMBOL(sym) EXPORT_SYMBOL(sym) 16#define UASM_EXPORT_SYMBOL(sym) EXPORT_SYMBOL(sym)
19#else 17#else
20#define __uasminit __cpuinit
21#define __uasminitdata __cpuinitdata
22#define UASM_EXPORT_SYMBOL(sym) 18#define UASM_EXPORT_SYMBOL(sym)
23#endif 19#endif
24 20
@@ -54,43 +50,36 @@
54#endif 50#endif
55 51
56#define Ip_u1u2u3(op) \ 52#define Ip_u1u2u3(op) \
57void __uasminit \ 53void ISAOPC(op)(u32 **buf, unsigned int a, unsigned int b, unsigned int c)
58ISAOPC(op)(u32 **buf, unsigned int a, unsigned int b, unsigned int c)
59 54
60#define Ip_u2u1u3(op) \ 55#define Ip_u2u1u3(op) \
61void __uasminit \ 56void ISAOPC(op)(u32 **buf, unsigned int a, unsigned int b, unsigned int c)
62ISAOPC(op)(u32 **buf, unsigned int a, unsigned int b, unsigned int c)
63 57
64#define Ip_u3u1u2(op) \ 58#define Ip_u3u1u2(op) \
65void __uasminit \ 59void ISAOPC(op)(u32 **buf, unsigned int a, unsigned int b, unsigned int c)
66ISAOPC(op)(u32 **buf, unsigned int a, unsigned int b, unsigned int c)
67 60
68#define Ip_u1u2s3(op) \ 61#define Ip_u1u2s3(op) \
69void __uasminit \ 62void ISAOPC(op)(u32 **buf, unsigned int a, unsigned int b, signed int c)
70ISAOPC(op)(u32 **buf, unsigned int a, unsigned int b, signed int c)
71 63
72#define Ip_u2s3u1(op) \ 64#define Ip_u2s3u1(op) \
73void __uasminit \ 65void ISAOPC(op)(u32 **buf, unsigned int a, signed int b, unsigned int c)
74ISAOPC(op)(u32 **buf, unsigned int a, signed int b, unsigned int c)
75 66
76#define Ip_u2u1s3(op) \ 67#define Ip_u2u1s3(op) \
77void __uasminit \ 68void ISAOPC(op)(u32 **buf, unsigned int a, unsigned int b, signed int c)
78ISAOPC(op)(u32 **buf, unsigned int a, unsigned int b, signed int c)
79 69
80#define Ip_u2u1msbu3(op) \ 70#define Ip_u2u1msbu3(op) \
81void __uasminit \ 71void ISAOPC(op)(u32 **buf, unsigned int a, unsigned int b, unsigned int c, \
82ISAOPC(op)(u32 **buf, unsigned int a, unsigned int b, unsigned int c, \
83 unsigned int d) 72 unsigned int d)
84 73
85#define Ip_u1u2(op) \ 74#define Ip_u1u2(op) \
86void __uasminit ISAOPC(op)(u32 **buf, unsigned int a, unsigned int b) 75void ISAOPC(op)(u32 **buf, unsigned int a, unsigned int b)
87 76
88#define Ip_u1s2(op) \ 77#define Ip_u1s2(op) \
89void __uasminit ISAOPC(op)(u32 **buf, unsigned int a, signed int b) 78void ISAOPC(op)(u32 **buf, unsigned int a, signed int b)
90 79
91#define Ip_u1(op) void __uasminit ISAOPC(op)(u32 **buf, unsigned int a) 80#define Ip_u1(op) void ISAOPC(op)(u32 **buf, unsigned int a)
92 81
93#define Ip_0(op) void __uasminit ISAOPC(op)(u32 **buf) 82#define Ip_0(op) void ISAOPC(op)(u32 **buf)
94 83
95Ip_u2u1s3(_addiu); 84Ip_u2u1s3(_addiu);
96Ip_u3u1u2(_addu); 85Ip_u3u1u2(_addu);
@@ -163,7 +152,7 @@ struct uasm_label {
163 int lab; 152 int lab;
164}; 153};
165 154
166void __uasminit ISAFUNC(uasm_build_label)(struct uasm_label **lab, u32 *addr, 155void ISAFUNC(uasm_build_label)(struct uasm_label **lab, u32 *addr,
167 int lid); 156 int lid);
168#ifdef CONFIG_64BIT 157#ifdef CONFIG_64BIT
169int ISAFUNC(uasm_in_compat_space_p)(long addr); 158int ISAFUNC(uasm_in_compat_space_p)(long addr);
@@ -174,7 +163,7 @@ void ISAFUNC(UASM_i_LA_mostly)(u32 **buf, unsigned int rs, long addr);
174void ISAFUNC(UASM_i_LA)(u32 **buf, unsigned int rs, long addr); 163void ISAFUNC(UASM_i_LA)(u32 **buf, unsigned int rs, long addr);
175 164
176#define UASM_L_LA(lb) \ 165#define UASM_L_LA(lb) \
177static inline void __uasminit ISAFUNC(uasm_l##lb)(struct uasm_label **lab, u32 *addr) \ 166static inline void ISAFUNC(uasm_l##lb)(struct uasm_label **lab, u32 *addr) \
178{ \ 167{ \
179 ISAFUNC(uasm_build_label)(lab, addr, label##lb); \ 168 ISAFUNC(uasm_build_label)(lab, addr, label##lb); \
180} 169}
diff --git a/arch/mips/kernel/bmips_vec.S b/arch/mips/kernel/bmips_vec.S
index 64c4fd62cf08..f739aedcb509 100644
--- a/arch/mips/kernel/bmips_vec.S
+++ b/arch/mips/kernel/bmips_vec.S
@@ -28,8 +28,6 @@
28 .set mips0 28 .set mips0
29 .endm 29 .endm
30 30
31 __CPUINIT
32
33/*********************************************************************** 31/***********************************************************************
34 * Alternate CPU1 startup vector for BMIPS4350 32 * Alternate CPU1 startup vector for BMIPS4350
35 * 33 *
@@ -216,8 +214,6 @@ END(bmips_smp_int_vec)
216 * Certain CPUs support extending kseg0 to 1024MB. 214 * Certain CPUs support extending kseg0 to 1024MB.
217 ***********************************************************************/ 215 ***********************************************************************/
218 216
219 __CPUINIT
220
221LEAF(bmips_enable_xks01) 217LEAF(bmips_enable_xks01)
222 218
223#if defined(CONFIG_XKS01) 219#if defined(CONFIG_XKS01)
diff --git a/arch/mips/kernel/cevt-bcm1480.c b/arch/mips/kernel/cevt-bcm1480.c
index 15f618b40cf6..7976457184b1 100644
--- a/arch/mips/kernel/cevt-bcm1480.c
+++ b/arch/mips/kernel/cevt-bcm1480.c
@@ -109,7 +109,7 @@ static DEFINE_PER_CPU(struct clock_event_device, sibyte_hpt_clockevent);
109static DEFINE_PER_CPU(struct irqaction, sibyte_hpt_irqaction); 109static DEFINE_PER_CPU(struct irqaction, sibyte_hpt_irqaction);
110static DEFINE_PER_CPU(char [18], sibyte_hpt_name); 110static DEFINE_PER_CPU(char [18], sibyte_hpt_name);
111 111
112void __cpuinit sb1480_clockevent_init(void) 112void sb1480_clockevent_init(void)
113{ 113{
114 unsigned int cpu = smp_processor_id(); 114 unsigned int cpu = smp_processor_id();
115 unsigned int irq = K_BCM1480_INT_TIMER_0 + cpu; 115 unsigned int irq = K_BCM1480_INT_TIMER_0 + cpu;
diff --git a/arch/mips/kernel/cevt-gic.c b/arch/mips/kernel/cevt-gic.c
index 730eaf92c018..594cbbf16d62 100644
--- a/arch/mips/kernel/cevt-gic.c
+++ b/arch/mips/kernel/cevt-gic.c
@@ -59,7 +59,7 @@ void gic_event_handler(struct clock_event_device *dev)
59{ 59{
60} 60}
61 61
62int __cpuinit gic_clockevent_init(void) 62int gic_clockevent_init(void)
63{ 63{
64 unsigned int cpu = smp_processor_id(); 64 unsigned int cpu = smp_processor_id();
65 struct clock_event_device *cd; 65 struct clock_event_device *cd;
diff --git a/arch/mips/kernel/cevt-r4k.c b/arch/mips/kernel/cevt-r4k.c
index 02033eaf8825..50d3f5a8d6bb 100644
--- a/arch/mips/kernel/cevt-r4k.c
+++ b/arch/mips/kernel/cevt-r4k.c
@@ -171,7 +171,7 @@ int c0_compare_int_usable(void)
171} 171}
172 172
173#ifndef CONFIG_MIPS_MT_SMTC 173#ifndef CONFIG_MIPS_MT_SMTC
174int __cpuinit r4k_clockevent_init(void) 174int r4k_clockevent_init(void)
175{ 175{
176 unsigned int cpu = smp_processor_id(); 176 unsigned int cpu = smp_processor_id();
177 struct clock_event_device *cd; 177 struct clock_event_device *cd;
diff --git a/arch/mips/kernel/cevt-sb1250.c b/arch/mips/kernel/cevt-sb1250.c
index 200f2778bf36..5ea6d6b1de15 100644
--- a/arch/mips/kernel/cevt-sb1250.c
+++ b/arch/mips/kernel/cevt-sb1250.c
@@ -107,7 +107,7 @@ static DEFINE_PER_CPU(struct clock_event_device, sibyte_hpt_clockevent);
107static DEFINE_PER_CPU(struct irqaction, sibyte_hpt_irqaction); 107static DEFINE_PER_CPU(struct irqaction, sibyte_hpt_irqaction);
108static DEFINE_PER_CPU(char [18], sibyte_hpt_name); 108static DEFINE_PER_CPU(char [18], sibyte_hpt_name);
109 109
110void __cpuinit sb1250_clockevent_init(void) 110void sb1250_clockevent_init(void)
111{ 111{
112 unsigned int cpu = smp_processor_id(); 112 unsigned int cpu = smp_processor_id();
113 unsigned int irq = K_INT_TIMER_0 + cpu; 113 unsigned int irq = K_INT_TIMER_0 + cpu;
diff --git a/arch/mips/kernel/cevt-smtc.c b/arch/mips/kernel/cevt-smtc.c
index 9de5ed7ef1a3..b6cf0a60d896 100644
--- a/arch/mips/kernel/cevt-smtc.c
+++ b/arch/mips/kernel/cevt-smtc.c
@@ -248,7 +248,7 @@ irqreturn_t c0_compare_interrupt(int irq, void *dev_id)
248} 248}
249 249
250 250
251int __cpuinit smtc_clockevent_init(void) 251int smtc_clockevent_init(void)
252{ 252{
253 uint64_t mips_freq = mips_hpt_frequency; 253 uint64_t mips_freq = mips_hpt_frequency;
254 unsigned int cpu = smp_processor_id(); 254 unsigned int cpu = smp_processor_id();
diff --git a/arch/mips/kernel/cpu-bugs64.c b/arch/mips/kernel/cpu-bugs64.c
index 0c61df281ce6..2d80b5f1aeae 100644
--- a/arch/mips/kernel/cpu-bugs64.c
+++ b/arch/mips/kernel/cpu-bugs64.c
@@ -168,7 +168,7 @@ static inline void check_mult_sh(void)
168 panic(bug64hit, !R4000_WAR ? r4kwar : nowar); 168 panic(bug64hit, !R4000_WAR ? r4kwar : nowar);
169} 169}
170 170
171static volatile int daddi_ov __cpuinitdata; 171static volatile int daddi_ov;
172 172
173asmlinkage void __init do_daddi_ov(struct pt_regs *regs) 173asmlinkage void __init do_daddi_ov(struct pt_regs *regs)
174{ 174{
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index c7b1b3c5a761..4c6167a17875 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -27,7 +27,7 @@
27#include <asm/spram.h> 27#include <asm/spram.h>
28#include <asm/uaccess.h> 28#include <asm/uaccess.h>
29 29
30static int __cpuinitdata mips_fpu_disabled; 30static int mips_fpu_disabled;
31 31
32static int __init fpu_disable(char *s) 32static int __init fpu_disable(char *s)
33{ 33{
@@ -39,7 +39,7 @@ static int __init fpu_disable(char *s)
39 39
40__setup("nofpu", fpu_disable); 40__setup("nofpu", fpu_disable);
41 41
42int __cpuinitdata mips_dsp_disabled; 42int mips_dsp_disabled;
43 43
44static int __init dsp_disable(char *s) 44static int __init dsp_disable(char *s)
45{ 45{
@@ -134,7 +134,7 @@ static inline void cpu_probe_vmbits(struct cpuinfo_mips *c)
134#endif 134#endif
135} 135}
136 136
137static void __cpuinit set_isa(struct cpuinfo_mips *c, unsigned int isa) 137static void set_isa(struct cpuinfo_mips *c, unsigned int isa)
138{ 138{
139 switch (isa) { 139 switch (isa) {
140 case MIPS_CPU_ISA_M64R2: 140 case MIPS_CPU_ISA_M64R2:
@@ -159,7 +159,7 @@ static void __cpuinit set_isa(struct cpuinfo_mips *c, unsigned int isa)
159 } 159 }
160} 160}
161 161
162static char unknown_isa[] __cpuinitdata = KERN_ERR \ 162static char unknown_isa[] = KERN_ERR \
163 "Unsupported ISA type, c0.config0: %d."; 163 "Unsupported ISA type, c0.config0: %d.";
164 164
165static inline unsigned int decode_config0(struct cpuinfo_mips *c) 165static inline unsigned int decode_config0(struct cpuinfo_mips *c)
@@ -290,7 +290,7 @@ static inline unsigned int decode_config4(struct cpuinfo_mips *c)
290 return config4 & MIPS_CONF_M; 290 return config4 & MIPS_CONF_M;
291} 291}
292 292
293static void __cpuinit decode_configs(struct cpuinfo_mips *c) 293static void decode_configs(struct cpuinfo_mips *c)
294{ 294{
295 int ok; 295 int ok;
296 296
@@ -962,7 +962,7 @@ EXPORT_SYMBOL(__ua_limit);
962const char *__cpu_name[NR_CPUS]; 962const char *__cpu_name[NR_CPUS];
963const char *__elf_platform; 963const char *__elf_platform;
964 964
965__cpuinit void cpu_probe(void) 965void cpu_probe(void)
966{ 966{
967 struct cpuinfo_mips *c = &current_cpu_data; 967 struct cpuinfo_mips *c = &current_cpu_data;
968 unsigned int cpu = smp_processor_id(); 968 unsigned int cpu = smp_processor_id();
@@ -1047,7 +1047,7 @@ __cpuinit void cpu_probe(void)
1047#endif 1047#endif
1048} 1048}
1049 1049
1050__cpuinit void cpu_report(void) 1050void cpu_report(void)
1051{ 1051{
1052 struct cpuinfo_mips *c = &current_cpu_data; 1052 struct cpuinfo_mips *c = &current_cpu_data;
1053 1053
diff --git a/arch/mips/kernel/head.S b/arch/mips/kernel/head.S
index 099912324423..7b6a5b3e3acf 100644
--- a/arch/mips/kernel/head.S
+++ b/arch/mips/kernel/head.S
@@ -158,8 +158,6 @@ NESTED(kernel_entry, 16, sp) # kernel entry point
158 j start_kernel 158 j start_kernel
159 END(kernel_entry) 159 END(kernel_entry)
160 160
161 __CPUINIT
162
163#ifdef CONFIG_SMP 161#ifdef CONFIG_SMP
164/* 162/*
165 * SMP slave cpus entry point. Board specific code for bootstrap calls this 163 * SMP slave cpus entry point. Board specific code for bootstrap calls this
@@ -188,5 +186,3 @@ NESTED(smp_bootstrap, 16, sp)
188 j start_secondary 186 j start_secondary
189 END(smp_bootstrap) 187 END(smp_bootstrap)
190#endif /* CONFIG_SMP */ 188#endif /* CONFIG_SMP */
191
192 __FINIT
diff --git a/arch/mips/kernel/smp-bmips.c b/arch/mips/kernel/smp-bmips.c
index aea6c0885838..76f31353e718 100644
--- a/arch/mips/kernel/smp-bmips.c
+++ b/arch/mips/kernel/smp-bmips.c
@@ -398,7 +398,7 @@ struct plat_smp_ops bmips_smp_ops = {
398 * UP BMIPS systems as well. 398 * UP BMIPS systems as well.
399 ***********************************************************************/ 399 ***********************************************************************/
400 400
401static void __cpuinit bmips_wr_vec(unsigned long dst, char *start, char *end) 401static void bmips_wr_vec(unsigned long dst, char *start, char *end)
402{ 402{
403 memcpy((void *)dst, start, end - start); 403 memcpy((void *)dst, start, end - start);
404 dma_cache_wback((unsigned long)start, end - start); 404 dma_cache_wback((unsigned long)start, end - start);
@@ -406,7 +406,7 @@ static void __cpuinit bmips_wr_vec(unsigned long dst, char *start, char *end)
406 instruction_hazard(); 406 instruction_hazard();
407} 407}
408 408
409static inline void __cpuinit bmips_nmi_handler_setup(void) 409static inline void bmips_nmi_handler_setup(void)
410{ 410{
411 bmips_wr_vec(BMIPS_NMI_RESET_VEC, &bmips_reset_nmi_vec, 411 bmips_wr_vec(BMIPS_NMI_RESET_VEC, &bmips_reset_nmi_vec,
412 &bmips_reset_nmi_vec_end); 412 &bmips_reset_nmi_vec_end);
@@ -414,7 +414,7 @@ static inline void __cpuinit bmips_nmi_handler_setup(void)
414 &bmips_smp_int_vec_end); 414 &bmips_smp_int_vec_end);
415} 415}
416 416
417void __cpuinit bmips_ebase_setup(void) 417void bmips_ebase_setup(void)
418{ 418{
419 unsigned long new_ebase = ebase; 419 unsigned long new_ebase = ebase;
420 void __iomem __maybe_unused *cbr; 420 void __iomem __maybe_unused *cbr;
diff --git a/arch/mips/kernel/smp-mt.c b/arch/mips/kernel/smp-mt.c
index 3e5164c11cac..57a3f7a2b370 100644
--- a/arch/mips/kernel/smp-mt.c
+++ b/arch/mips/kernel/smp-mt.c
@@ -149,7 +149,7 @@ static void vsmp_send_ipi_mask(const struct cpumask *mask, unsigned int action)
149 vsmp_send_ipi_single(i, action); 149 vsmp_send_ipi_single(i, action);
150} 150}
151 151
152static void __cpuinit vsmp_init_secondary(void) 152static void vsmp_init_secondary(void)
153{ 153{
154#ifdef CONFIG_IRQ_GIC 154#ifdef CONFIG_IRQ_GIC
155 /* This is Malta specific: IPI,performance and timer interrupts */ 155 /* This is Malta specific: IPI,performance and timer interrupts */
@@ -162,7 +162,7 @@ static void __cpuinit vsmp_init_secondary(void)
162 STATUSF_IP6 | STATUSF_IP7); 162 STATUSF_IP6 | STATUSF_IP7);
163} 163}
164 164
165static void __cpuinit vsmp_smp_finish(void) 165static void vsmp_smp_finish(void)
166{ 166{
167 /* CDFIXME: remove this? */ 167 /* CDFIXME: remove this? */
168 write_c0_compare(read_c0_count() + (8* mips_hpt_frequency/HZ)); 168 write_c0_compare(read_c0_count() + (8* mips_hpt_frequency/HZ));
@@ -188,7 +188,7 @@ static void vsmp_cpus_done(void)
188 * (unsigned long)idle->thread_info the gp 188 * (unsigned long)idle->thread_info the gp
189 * assumes a 1:1 mapping of TC => VPE 189 * assumes a 1:1 mapping of TC => VPE
190 */ 190 */
191static void __cpuinit vsmp_boot_secondary(int cpu, struct task_struct *idle) 191static void vsmp_boot_secondary(int cpu, struct task_struct *idle)
192{ 192{
193 struct thread_info *gp = task_thread_info(idle); 193 struct thread_info *gp = task_thread_info(idle);
194 dvpe(); 194 dvpe();
diff --git a/arch/mips/kernel/smp-up.c b/arch/mips/kernel/smp-up.c
index 00500fea2750..7fde3e4d978f 100644
--- a/arch/mips/kernel/smp-up.c
+++ b/arch/mips/kernel/smp-up.c
@@ -28,11 +28,11 @@ static inline void up_send_ipi_mask(const struct cpumask *mask,
28 * After we've done initial boot, this function is called to allow the 28 * After we've done initial boot, this function is called to allow the
29 * board code to clean up state, if needed 29 * board code to clean up state, if needed
30 */ 30 */
31static void __cpuinit up_init_secondary(void) 31static void up_init_secondary(void)
32{ 32{
33} 33}
34 34
35static void __cpuinit up_smp_finish(void) 35static void up_smp_finish(void)
36{ 36{
37} 37}
38 38
@@ -44,7 +44,7 @@ static void up_cpus_done(void)
44/* 44/*
45 * Firmware CPU startup hook 45 * Firmware CPU startup hook
46 */ 46 */
47static void __cpuinit up_boot_secondary(int cpu, struct task_struct *idle) 47static void up_boot_secondary(int cpu, struct task_struct *idle)
48{ 48{
49} 49}
50 50
diff --git a/arch/mips/kernel/smp.c b/arch/mips/kernel/smp.c
index 6e7862ab46cc..5c208ed8f856 100644
--- a/arch/mips/kernel/smp.c
+++ b/arch/mips/kernel/smp.c
@@ -86,7 +86,7 @@ static inline void set_cpu_sibling_map(int cpu)
86struct plat_smp_ops *mp_ops; 86struct plat_smp_ops *mp_ops;
87EXPORT_SYMBOL(mp_ops); 87EXPORT_SYMBOL(mp_ops);
88 88
89__cpuinit void register_smp_ops(struct plat_smp_ops *ops) 89void register_smp_ops(struct plat_smp_ops *ops)
90{ 90{
91 if (mp_ops) 91 if (mp_ops)
92 printk(KERN_WARNING "Overriding previously set SMP ops\n"); 92 printk(KERN_WARNING "Overriding previously set SMP ops\n");
@@ -98,7 +98,7 @@ __cpuinit void register_smp_ops(struct plat_smp_ops *ops)
98 * First C code run on the secondary CPUs after being started up by 98 * First C code run on the secondary CPUs after being started up by
99 * the master. 99 * the master.
100 */ 100 */
101asmlinkage __cpuinit void start_secondary(void) 101asmlinkage void start_secondary(void)
102{ 102{
103 unsigned int cpu; 103 unsigned int cpu;
104 104
@@ -197,7 +197,7 @@ void smp_prepare_boot_cpu(void)
197 cpu_set(0, cpu_callin_map); 197 cpu_set(0, cpu_callin_map);
198} 198}
199 199
200int __cpuinit __cpu_up(unsigned int cpu, struct task_struct *tidle) 200int __cpu_up(unsigned int cpu, struct task_struct *tidle)
201{ 201{
202 mp_ops->boot_secondary(cpu, tidle); 202 mp_ops->boot_secondary(cpu, tidle);
203 203
diff --git a/arch/mips/kernel/smtc.c b/arch/mips/kernel/smtc.c
index 75a4fd709841..dfc1b911be04 100644
--- a/arch/mips/kernel/smtc.c
+++ b/arch/mips/kernel/smtc.c
@@ -645,7 +645,7 @@ void smtc_prepare_cpus(int cpus)
645 * (unsigned long)idle->thread_info the gp 645 * (unsigned long)idle->thread_info the gp
646 * 646 *
647 */ 647 */
648void __cpuinit smtc_boot_secondary(int cpu, struct task_struct *idle) 648void smtc_boot_secondary(int cpu, struct task_struct *idle)
649{ 649{
650 extern u32 kernelsp[NR_CPUS]; 650 extern u32 kernelsp[NR_CPUS];
651 unsigned long flags; 651 unsigned long flags;
diff --git a/arch/mips/kernel/spram.c b/arch/mips/kernel/spram.c
index 6af08d896e20..93f86817f20a 100644
--- a/arch/mips/kernel/spram.c
+++ b/arch/mips/kernel/spram.c
@@ -37,7 +37,7 @@
37/* 37/*
38 * Different semantics to the set_c0_* function built by __BUILD_SET_C0 38 * Different semantics to the set_c0_* function built by __BUILD_SET_C0
39 */ 39 */
40static __cpuinit unsigned int bis_c0_errctl(unsigned int set) 40static unsigned int bis_c0_errctl(unsigned int set)
41{ 41{
42 unsigned int res; 42 unsigned int res;
43 res = read_c0_errctl(); 43 res = read_c0_errctl();
@@ -45,7 +45,7 @@ static __cpuinit unsigned int bis_c0_errctl(unsigned int set)
45 return res; 45 return res;
46} 46}
47 47
48static __cpuinit void ispram_store_tag(unsigned int offset, unsigned int data) 48static void ispram_store_tag(unsigned int offset, unsigned int data)
49{ 49{
50 unsigned int errctl; 50 unsigned int errctl;
51 51
@@ -64,7 +64,7 @@ static __cpuinit void ispram_store_tag(unsigned int offset, unsigned int data)
64} 64}
65 65
66 66
67static __cpuinit unsigned int ispram_load_tag(unsigned int offset) 67static unsigned int ispram_load_tag(unsigned int offset)
68{ 68{
69 unsigned int data; 69 unsigned int data;
70 unsigned int errctl; 70 unsigned int errctl;
@@ -82,7 +82,7 @@ static __cpuinit unsigned int ispram_load_tag(unsigned int offset)
82 return data; 82 return data;
83} 83}
84 84
85static __cpuinit void dspram_store_tag(unsigned int offset, unsigned int data) 85static void dspram_store_tag(unsigned int offset, unsigned int data)
86{ 86{
87 unsigned int errctl; 87 unsigned int errctl;
88 88
@@ -98,7 +98,7 @@ static __cpuinit void dspram_store_tag(unsigned int offset, unsigned int data)
98} 98}
99 99
100 100
101static __cpuinit unsigned int dspram_load_tag(unsigned int offset) 101static unsigned int dspram_load_tag(unsigned int offset)
102{ 102{
103 unsigned int data; 103 unsigned int data;
104 unsigned int errctl; 104 unsigned int errctl;
@@ -115,7 +115,7 @@ static __cpuinit unsigned int dspram_load_tag(unsigned int offset)
115 return data; 115 return data;
116} 116}
117 117
118static __cpuinit void probe_spram(char *type, 118static void probe_spram(char *type,
119 unsigned int base, 119 unsigned int base,
120 unsigned int (*read)(unsigned int), 120 unsigned int (*read)(unsigned int),
121 void (*write)(unsigned int, unsigned int)) 121 void (*write)(unsigned int, unsigned int))
@@ -196,7 +196,7 @@ static __cpuinit void probe_spram(char *type,
196 offset += 2 * SPRAM_TAG_STRIDE; 196 offset += 2 * SPRAM_TAG_STRIDE;
197 } 197 }
198} 198}
199void __cpuinit spram_config(void) 199void spram_config(void)
200{ 200{
201 struct cpuinfo_mips *c = &current_cpu_data; 201 struct cpuinfo_mips *c = &current_cpu_data;
202 unsigned int config0; 202 unsigned int config0;
diff --git a/arch/mips/kernel/sync-r4k.c b/arch/mips/kernel/sync-r4k.c
index 1ff43d5ac2c4..84536bf4a154 100644
--- a/arch/mips/kernel/sync-r4k.c
+++ b/arch/mips/kernel/sync-r4k.c
@@ -20,15 +20,15 @@
20#include <asm/barrier.h> 20#include <asm/barrier.h>
21#include <asm/mipsregs.h> 21#include <asm/mipsregs.h>
22 22
23static atomic_t __cpuinitdata count_start_flag = ATOMIC_INIT(0); 23static atomic_t count_start_flag = ATOMIC_INIT(0);
24static atomic_t __cpuinitdata count_count_start = ATOMIC_INIT(0); 24static atomic_t count_count_start = ATOMIC_INIT(0);
25static atomic_t __cpuinitdata count_count_stop = ATOMIC_INIT(0); 25static atomic_t count_count_stop = ATOMIC_INIT(0);
26static atomic_t __cpuinitdata count_reference = ATOMIC_INIT(0); 26static atomic_t count_reference = ATOMIC_INIT(0);
27 27
28#define COUNTON 100 28#define COUNTON 100
29#define NR_LOOPS 5 29#define NR_LOOPS 5
30 30
31void __cpuinit synchronise_count_master(int cpu) 31void synchronise_count_master(int cpu)
32{ 32{
33 int i; 33 int i;
34 unsigned long flags; 34 unsigned long flags;
@@ -106,7 +106,7 @@ void __cpuinit synchronise_count_master(int cpu)
106 printk("done.\n"); 106 printk("done.\n");
107} 107}
108 108
109void __cpuinit synchronise_count_slave(int cpu) 109void synchronise_count_slave(int cpu)
110{ 110{
111 int i; 111 int i;
112 unsigned int initcount; 112 unsigned int initcount;
diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index 0903d70b2cfe..c89568f88bfd 100644
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -90,7 +90,7 @@ void (*board_nmi_handler_setup)(void);
90void (*board_ejtag_handler_setup)(void); 90void (*board_ejtag_handler_setup)(void);
91void (*board_bind_eic_interrupt)(int irq, int regset); 91void (*board_bind_eic_interrupt)(int irq, int regset);
92void (*board_ebase_setup)(void); 92void (*board_ebase_setup)(void);
93void __cpuinitdata(*board_cache_error_setup)(void); 93void(*board_cache_error_setup)(void);
94 94
95static void show_raw_backtrace(unsigned long reg29) 95static void show_raw_backtrace(unsigned long reg29)
96{ 96{
@@ -1682,7 +1682,7 @@ int cp0_compare_irq_shift;
1682int cp0_perfcount_irq; 1682int cp0_perfcount_irq;
1683EXPORT_SYMBOL_GPL(cp0_perfcount_irq); 1683EXPORT_SYMBOL_GPL(cp0_perfcount_irq);
1684 1684
1685static int __cpuinitdata noulri; 1685static int noulri;
1686 1686
1687static int __init ulri_disable(char *s) 1687static int __init ulri_disable(char *s)
1688{ 1688{
@@ -1693,7 +1693,7 @@ static int __init ulri_disable(char *s)
1693} 1693}
1694__setup("noulri", ulri_disable); 1694__setup("noulri", ulri_disable);
1695 1695
1696void __cpuinit per_cpu_trap_init(bool is_boot_cpu) 1696void per_cpu_trap_init(bool is_boot_cpu)
1697{ 1697{
1698 unsigned int cpu = smp_processor_id(); 1698 unsigned int cpu = smp_processor_id();
1699 unsigned int status_set = ST0_CU0; 1699 unsigned int status_set = ST0_CU0;
@@ -1810,7 +1810,7 @@ void __cpuinit per_cpu_trap_init(bool is_boot_cpu)
1810} 1810}
1811 1811
1812/* Install CPU exception handler */ 1812/* Install CPU exception handler */
1813void __cpuinit set_handler(unsigned long offset, void *addr, unsigned long size) 1813void set_handler(unsigned long offset, void *addr, unsigned long size)
1814{ 1814{
1815#ifdef CONFIG_CPU_MICROMIPS 1815#ifdef CONFIG_CPU_MICROMIPS
1816 memcpy((void *)(ebase + offset), ((unsigned char *)addr - 1), size); 1816 memcpy((void *)(ebase + offset), ((unsigned char *)addr - 1), size);
@@ -1820,7 +1820,7 @@ void __cpuinit set_handler(unsigned long offset, void *addr, unsigned long size)
1820 local_flush_icache_range(ebase + offset, ebase + offset + size); 1820 local_flush_icache_range(ebase + offset, ebase + offset + size);
1821} 1821}
1822 1822
1823static char panic_null_cerr[] __cpuinitdata = 1823static char panic_null_cerr[] =
1824 "Trying to set NULL cache error exception handler"; 1824 "Trying to set NULL cache error exception handler";
1825 1825
1826/* 1826/*
@@ -1828,7 +1828,7 @@ static char panic_null_cerr[] __cpuinitdata =
1828 * This is suitable only for the cache error exception which is the only 1828 * This is suitable only for the cache error exception which is the only
1829 * exception handler that is being run uncached. 1829 * exception handler that is being run uncached.
1830 */ 1830 */
1831void __cpuinit set_uncached_handler(unsigned long offset, void *addr, 1831void set_uncached_handler(unsigned long offset, void *addr,
1832 unsigned long size) 1832 unsigned long size)
1833{ 1833{
1834 unsigned long uncached_ebase = CKSEG1ADDR(ebase); 1834 unsigned long uncached_ebase = CKSEG1ADDR(ebase);
diff --git a/arch/mips/kernel/watch.c b/arch/mips/kernel/watch.c
index cbdc4de85bb4..2a03abb5bd2c 100644
--- a/arch/mips/kernel/watch.c
+++ b/arch/mips/kernel/watch.c
@@ -100,7 +100,7 @@ void mips_clear_watch_registers(void)
100 } 100 }
101} 101}
102 102
103__cpuinit void mips_probe_watch_registers(struct cpuinfo_mips *c) 103void mips_probe_watch_registers(struct cpuinfo_mips *c)
104{ 104{
105 unsigned int t; 105 unsigned int t;
106 106
diff --git a/arch/mips/lantiq/irq.c b/arch/mips/lantiq/irq.c
index 51194875f158..eb3e18659630 100644
--- a/arch/mips/lantiq/irq.c
+++ b/arch/mips/lantiq/irq.c
@@ -461,7 +461,7 @@ int __init icu_of_init(struct device_node *node, struct device_node *parent)
461 return 0; 461 return 0;
462} 462}
463 463
464unsigned int __cpuinit get_c0_compare_int(void) 464unsigned int get_c0_compare_int(void)
465{ 465{
466 return MIPS_CPU_TIMER_IRQ; 466 return MIPS_CPU_TIMER_IRQ;
467} 467}
diff --git a/arch/mips/lib/uncached.c b/arch/mips/lib/uncached.c
index 65e3dfc4e585..d8522f8e842a 100644
--- a/arch/mips/lib/uncached.c
+++ b/arch/mips/lib/uncached.c
@@ -36,7 +36,7 @@
36 * values, so we can avoid sharing the same stack area between a cached 36 * values, so we can avoid sharing the same stack area between a cached
37 * and the uncached mode. 37 * and the uncached mode.
38 */ 38 */
39unsigned long __cpuinit run_uncached(void *func) 39unsigned long run_uncached(void *func)
40{ 40{
41 register long sp __asm__("$sp"); 41 register long sp __asm__("$sp");
42 register long ret __asm__("$2"); 42 register long ret __asm__("$2");
diff --git a/arch/mips/mm/c-octeon.c b/arch/mips/mm/c-octeon.c
index 8557fb552863..a0bcdbb81d41 100644
--- a/arch/mips/mm/c-octeon.c
+++ b/arch/mips/mm/c-octeon.c
@@ -180,7 +180,7 @@ static void octeon_flush_kernel_vmap_range(unsigned long vaddr, int size)
180 * Probe Octeon's caches 180 * Probe Octeon's caches
181 * 181 *
182 */ 182 */
183static void __cpuinit probe_octeon(void) 183static void probe_octeon(void)
184{ 184{
185 unsigned long icache_size; 185 unsigned long icache_size;
186 unsigned long dcache_size; 186 unsigned long dcache_size;
@@ -251,7 +251,7 @@ static void __cpuinit probe_octeon(void)
251 } 251 }
252} 252}
253 253
254static void __cpuinit octeon_cache_error_setup(void) 254static void octeon_cache_error_setup(void)
255{ 255{
256 extern char except_vec2_octeon; 256 extern char except_vec2_octeon;
257 set_handler(0x100, &except_vec2_octeon, 0x80); 257 set_handler(0x100, &except_vec2_octeon, 0x80);
@@ -261,7 +261,7 @@ static void __cpuinit octeon_cache_error_setup(void)
261 * Setup the Octeon cache flush routines 261 * Setup the Octeon cache flush routines
262 * 262 *
263 */ 263 */
264void __cpuinit octeon_cache_init(void) 264void octeon_cache_init(void)
265{ 265{
266 probe_octeon(); 266 probe_octeon();
267 267
diff --git a/arch/mips/mm/c-r3k.c b/arch/mips/mm/c-r3k.c
index 704dc735a59d..2fcde0c8ea02 100644
--- a/arch/mips/mm/c-r3k.c
+++ b/arch/mips/mm/c-r3k.c
@@ -26,7 +26,7 @@
26static unsigned long icache_size, dcache_size; /* Size in bytes */ 26static unsigned long icache_size, dcache_size; /* Size in bytes */
27static unsigned long icache_lsize, dcache_lsize; /* Size in bytes */ 27static unsigned long icache_lsize, dcache_lsize; /* Size in bytes */
28 28
29unsigned long __cpuinit r3k_cache_size(unsigned long ca_flags) 29unsigned long r3k_cache_size(unsigned long ca_flags)
30{ 30{
31 unsigned long flags, status, dummy, size; 31 unsigned long flags, status, dummy, size;
32 volatile unsigned long *p; 32 volatile unsigned long *p;
@@ -61,7 +61,7 @@ unsigned long __cpuinit r3k_cache_size(unsigned long ca_flags)
61 return size * sizeof(*p); 61 return size * sizeof(*p);
62} 62}
63 63
64unsigned long __cpuinit r3k_cache_lsize(unsigned long ca_flags) 64unsigned long r3k_cache_lsize(unsigned long ca_flags)
65{ 65{
66 unsigned long flags, status, lsize, i; 66 unsigned long flags, status, lsize, i;
67 volatile unsigned long *p; 67 volatile unsigned long *p;
@@ -90,7 +90,7 @@ unsigned long __cpuinit r3k_cache_lsize(unsigned long ca_flags)
90 return lsize * sizeof(*p); 90 return lsize * sizeof(*p);
91} 91}
92 92
93static void __cpuinit r3k_probe_cache(void) 93static void r3k_probe_cache(void)
94{ 94{
95 dcache_size = r3k_cache_size(ST0_ISC); 95 dcache_size = r3k_cache_size(ST0_ISC);
96 if (dcache_size) 96 if (dcache_size)
@@ -312,7 +312,7 @@ static void r3k_dma_cache_wback_inv(unsigned long start, unsigned long size)
312 r3k_flush_dcache_range(start, start + size); 312 r3k_flush_dcache_range(start, start + size);
313} 313}
314 314
315void __cpuinit r3k_cache_init(void) 315void r3k_cache_init(void)
316{ 316{
317 extern void build_clear_page(void); 317 extern void build_clear_page(void);
318 extern void build_copy_page(void); 318 extern void build_copy_page(void);
diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index 21813beec7a5..f749f687ee87 100644
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -107,7 +107,7 @@ static inline void r4k_blast_dcache_page_dc64(unsigned long addr)
107 blast_dcache64_page(addr); 107 blast_dcache64_page(addr);
108} 108}
109 109
110static void __cpuinit r4k_blast_dcache_page_setup(void) 110static void r4k_blast_dcache_page_setup(void)
111{ 111{
112 unsigned long dc_lsize = cpu_dcache_line_size(); 112 unsigned long dc_lsize = cpu_dcache_line_size();
113 113
@@ -123,7 +123,7 @@ static void __cpuinit r4k_blast_dcache_page_setup(void)
123 123
124static void (* r4k_blast_dcache_page_indexed)(unsigned long addr); 124static void (* r4k_blast_dcache_page_indexed)(unsigned long addr);
125 125
126static void __cpuinit r4k_blast_dcache_page_indexed_setup(void) 126static void r4k_blast_dcache_page_indexed_setup(void)
127{ 127{
128 unsigned long dc_lsize = cpu_dcache_line_size(); 128 unsigned long dc_lsize = cpu_dcache_line_size();
129 129
@@ -140,7 +140,7 @@ static void __cpuinit r4k_blast_dcache_page_indexed_setup(void)
140void (* r4k_blast_dcache)(void); 140void (* r4k_blast_dcache)(void);
141EXPORT_SYMBOL(r4k_blast_dcache); 141EXPORT_SYMBOL(r4k_blast_dcache);
142 142
143static void __cpuinit r4k_blast_dcache_setup(void) 143static void r4k_blast_dcache_setup(void)
144{ 144{
145 unsigned long dc_lsize = cpu_dcache_line_size(); 145 unsigned long dc_lsize = cpu_dcache_line_size();
146 146
@@ -227,7 +227,7 @@ static inline void tx49_blast_icache32_page_indexed(unsigned long page)
227 227
228static void (* r4k_blast_icache_page)(unsigned long addr); 228static void (* r4k_blast_icache_page)(unsigned long addr);
229 229
230static void __cpuinit r4k_blast_icache_page_setup(void) 230static void r4k_blast_icache_page_setup(void)
231{ 231{
232 unsigned long ic_lsize = cpu_icache_line_size(); 232 unsigned long ic_lsize = cpu_icache_line_size();
233 233
@@ -244,7 +244,7 @@ static void __cpuinit r4k_blast_icache_page_setup(void)
244 244
245static void (* r4k_blast_icache_page_indexed)(unsigned long addr); 245static void (* r4k_blast_icache_page_indexed)(unsigned long addr);
246 246
247static void __cpuinit r4k_blast_icache_page_indexed_setup(void) 247static void r4k_blast_icache_page_indexed_setup(void)
248{ 248{
249 unsigned long ic_lsize = cpu_icache_line_size(); 249 unsigned long ic_lsize = cpu_icache_line_size();
250 250
@@ -269,7 +269,7 @@ static void __cpuinit r4k_blast_icache_page_indexed_setup(void)
269void (* r4k_blast_icache)(void); 269void (* r4k_blast_icache)(void);
270EXPORT_SYMBOL(r4k_blast_icache); 270EXPORT_SYMBOL(r4k_blast_icache);
271 271
272static void __cpuinit r4k_blast_icache_setup(void) 272static void r4k_blast_icache_setup(void)
273{ 273{
274 unsigned long ic_lsize = cpu_icache_line_size(); 274 unsigned long ic_lsize = cpu_icache_line_size();
275 275
@@ -290,7 +290,7 @@ static void __cpuinit r4k_blast_icache_setup(void)
290 290
291static void (* r4k_blast_scache_page)(unsigned long addr); 291static void (* r4k_blast_scache_page)(unsigned long addr);
292 292
293static void __cpuinit r4k_blast_scache_page_setup(void) 293static void r4k_blast_scache_page_setup(void)
294{ 294{
295 unsigned long sc_lsize = cpu_scache_line_size(); 295 unsigned long sc_lsize = cpu_scache_line_size();
296 296
@@ -308,7 +308,7 @@ static void __cpuinit r4k_blast_scache_page_setup(void)
308 308
309static void (* r4k_blast_scache_page_indexed)(unsigned long addr); 309static void (* r4k_blast_scache_page_indexed)(unsigned long addr);
310 310
311static void __cpuinit r4k_blast_scache_page_indexed_setup(void) 311static void r4k_blast_scache_page_indexed_setup(void)
312{ 312{
313 unsigned long sc_lsize = cpu_scache_line_size(); 313 unsigned long sc_lsize = cpu_scache_line_size();
314 314
@@ -326,7 +326,7 @@ static void __cpuinit r4k_blast_scache_page_indexed_setup(void)
326 326
327static void (* r4k_blast_scache)(void); 327static void (* r4k_blast_scache)(void);
328 328
329static void __cpuinit r4k_blast_scache_setup(void) 329static void r4k_blast_scache_setup(void)
330{ 330{
331 unsigned long sc_lsize = cpu_scache_line_size(); 331 unsigned long sc_lsize = cpu_scache_line_size();
332 332
@@ -797,11 +797,11 @@ static inline void alias_74k_erratum(struct cpuinfo_mips *c)
797 } 797 }
798} 798}
799 799
800static char *way_string[] __cpuinitdata = { NULL, "direct mapped", "2-way", 800static char *way_string[] = { NULL, "direct mapped", "2-way",
801 "3-way", "4-way", "5-way", "6-way", "7-way", "8-way" 801 "3-way", "4-way", "5-way", "6-way", "7-way", "8-way"
802}; 802};
803 803
804static void __cpuinit probe_pcache(void) 804static void probe_pcache(void)
805{ 805{
806 struct cpuinfo_mips *c = &current_cpu_data; 806 struct cpuinfo_mips *c = &current_cpu_data;
807 unsigned int config = read_c0_config(); 807 unsigned int config = read_c0_config();
@@ -1119,7 +1119,7 @@ static void __cpuinit probe_pcache(void)
1119 * executes in KSEG1 space or else you will crash and burn badly. You have 1119 * executes in KSEG1 space or else you will crash and burn badly. You have
1120 * been warned. 1120 * been warned.
1121 */ 1121 */
1122static int __cpuinit probe_scache(void) 1122static int probe_scache(void)
1123{ 1123{
1124 unsigned long flags, addr, begin, end, pow2; 1124 unsigned long flags, addr, begin, end, pow2;
1125 unsigned int config = read_c0_config(); 1125 unsigned int config = read_c0_config();
@@ -1196,7 +1196,7 @@ extern int r5k_sc_init(void);
1196extern int rm7k_sc_init(void); 1196extern int rm7k_sc_init(void);
1197extern int mips_sc_init(void); 1197extern int mips_sc_init(void);
1198 1198
1199static void __cpuinit setup_scache(void) 1199static void setup_scache(void)
1200{ 1200{
1201 struct cpuinfo_mips *c = &current_cpu_data; 1201 struct cpuinfo_mips *c = &current_cpu_data;
1202 unsigned int config = read_c0_config(); 1202 unsigned int config = read_c0_config();
@@ -1329,7 +1329,7 @@ static void nxp_pr4450_fixup_config(void)
1329 NXP_BARRIER(); 1329 NXP_BARRIER();
1330} 1330}
1331 1331
1332static int __cpuinitdata cca = -1; 1332static int cca = -1;
1333 1333
1334static int __init cca_setup(char *str) 1334static int __init cca_setup(char *str)
1335{ 1335{
@@ -1340,7 +1340,7 @@ static int __init cca_setup(char *str)
1340 1340
1341early_param("cca", cca_setup); 1341early_param("cca", cca_setup);
1342 1342
1343static void __cpuinit coherency_setup(void) 1343static void coherency_setup(void)
1344{ 1344{
1345 if (cca < 0 || cca > 7) 1345 if (cca < 0 || cca > 7)
1346 cca = read_c0_config() & CONF_CM_CMASK; 1346 cca = read_c0_config() & CONF_CM_CMASK;
@@ -1380,7 +1380,7 @@ static void __cpuinit coherency_setup(void)
1380 } 1380 }
1381} 1381}
1382 1382
1383static void __cpuinit r4k_cache_error_setup(void) 1383static void r4k_cache_error_setup(void)
1384{ 1384{
1385 extern char __weak except_vec2_generic; 1385 extern char __weak except_vec2_generic;
1386 extern char __weak except_vec2_sb1; 1386 extern char __weak except_vec2_sb1;
@@ -1398,7 +1398,7 @@ static void __cpuinit r4k_cache_error_setup(void)
1398 } 1398 }
1399} 1399}
1400 1400
1401void __cpuinit r4k_cache_init(void) 1401void r4k_cache_init(void)
1402{ 1402{
1403 extern void build_clear_page(void); 1403 extern void build_clear_page(void);
1404 extern void build_copy_page(void); 1404 extern void build_copy_page(void);
diff --git a/arch/mips/mm/c-tx39.c b/arch/mips/mm/c-tx39.c
index ba9da270289f..8d909dbbf37f 100644
--- a/arch/mips/mm/c-tx39.c
+++ b/arch/mips/mm/c-tx39.c
@@ -344,7 +344,7 @@ static __init void tx39_probe_cache(void)
344 } 344 }
345} 345}
346 346
347void __cpuinit tx39_cache_init(void) 347void tx39_cache_init(void)
348{ 348{
349 extern void build_clear_page(void); 349 extern void build_clear_page(void);
350 extern void build_copy_page(void); 350 extern void build_copy_page(void);
diff --git a/arch/mips/mm/cache.c b/arch/mips/mm/cache.c
index 5aeb3eb0b72f..15f813c303b4 100644
--- a/arch/mips/mm/cache.c
+++ b/arch/mips/mm/cache.c
@@ -182,7 +182,7 @@ static inline void setup_protection_map(void)
182 } 182 }
183} 183}
184 184
185void __cpuinit cpu_cache_init(void) 185void cpu_cache_init(void)
186{ 186{
187 if (cpu_has_3k_cache) { 187 if (cpu_has_3k_cache) {
188 extern void __weak r3k_cache_init(void); 188 extern void __weak r3k_cache_init(void);
diff --git a/arch/mips/mm/cex-sb1.S b/arch/mips/mm/cex-sb1.S
index fe1d887e8d70..191cf6e0c725 100644
--- a/arch/mips/mm/cex-sb1.S
+++ b/arch/mips/mm/cex-sb1.S
@@ -49,8 +49,6 @@
49 * (0x170-0x17f) are used to preserve k0, k1, and ra. 49 * (0x170-0x17f) are used to preserve k0, k1, and ra.
50 */ 50 */
51 51
52 __CPUINIT
53
54LEAF(except_vec2_sb1) 52LEAF(except_vec2_sb1)
55 /* 53 /*
56 * If this error is recoverable, we need to exit the handler 54 * If this error is recoverable, we need to exit the handler
@@ -142,8 +140,6 @@ unrecoverable:
142 140
143END(except_vec2_sb1) 141END(except_vec2_sb1)
144 142
145 __FINIT
146
147 LEAF(handle_vec2_sb1) 143 LEAF(handle_vec2_sb1)
148 mfc0 k0,CP0_CONFIG 144 mfc0 k0,CP0_CONFIG
149 li k1,~CONF_CM_CMASK 145 li k1,~CONF_CM_CMASK
diff --git a/arch/mips/mm/page.c b/arch/mips/mm/page.c
index 2c0bd580b9da..218c2109a55d 100644
--- a/arch/mips/mm/page.c
+++ b/arch/mips/mm/page.c
@@ -66,29 +66,29 @@ UASM_L_LA(_copy_pref_both)
66UASM_L_LA(_copy_pref_store) 66UASM_L_LA(_copy_pref_store)
67 67
68/* We need one branch and therefore one relocation per target label. */ 68/* We need one branch and therefore one relocation per target label. */
69static struct uasm_label __cpuinitdata labels[5]; 69static struct uasm_label labels[5];
70static struct uasm_reloc __cpuinitdata relocs[5]; 70static struct uasm_reloc relocs[5];
71 71
72#define cpu_is_r4600_v1_x() ((read_c0_prid() & 0xfffffff0) == 0x00002010) 72#define cpu_is_r4600_v1_x() ((read_c0_prid() & 0xfffffff0) == 0x00002010)
73#define cpu_is_r4600_v2_x() ((read_c0_prid() & 0xfffffff0) == 0x00002020) 73#define cpu_is_r4600_v2_x() ((read_c0_prid() & 0xfffffff0) == 0x00002020)
74 74
75static int pref_bias_clear_store __cpuinitdata; 75static int pref_bias_clear_store;
76static int pref_bias_copy_load __cpuinitdata; 76static int pref_bias_copy_load;
77static int pref_bias_copy_store __cpuinitdata; 77static int pref_bias_copy_store;
78 78
79static u32 pref_src_mode __cpuinitdata; 79static u32 pref_src_mode;
80static u32 pref_dst_mode __cpuinitdata; 80static u32 pref_dst_mode;
81 81
82static int clear_word_size __cpuinitdata; 82static int clear_word_size;
83static int copy_word_size __cpuinitdata; 83static int copy_word_size;
84 84
85static int half_clear_loop_size __cpuinitdata; 85static int half_clear_loop_size;
86static int half_copy_loop_size __cpuinitdata; 86static int half_copy_loop_size;
87 87
88static int cache_line_size __cpuinitdata; 88static int cache_line_size;
89#define cache_line_mask() (cache_line_size - 1) 89#define cache_line_mask() (cache_line_size - 1)
90 90
91static inline void __cpuinit 91static inline void
92pg_addiu(u32 **buf, unsigned int reg1, unsigned int reg2, unsigned int off) 92pg_addiu(u32 **buf, unsigned int reg1, unsigned int reg2, unsigned int off)
93{ 93{
94 if (cpu_has_64bit_gp_regs && DADDI_WAR && r4k_daddiu_bug()) { 94 if (cpu_has_64bit_gp_regs && DADDI_WAR && r4k_daddiu_bug()) {
@@ -108,7 +108,7 @@ pg_addiu(u32 **buf, unsigned int reg1, unsigned int reg2, unsigned int off)
108 } 108 }
109} 109}
110 110
111static void __cpuinit set_prefetch_parameters(void) 111static void set_prefetch_parameters(void)
112{ 112{
113 if (cpu_has_64bit_gp_regs || cpu_has_64bit_zero_reg) 113 if (cpu_has_64bit_gp_regs || cpu_has_64bit_zero_reg)
114 clear_word_size = 8; 114 clear_word_size = 8;
@@ -199,7 +199,7 @@ static void __cpuinit set_prefetch_parameters(void)
199 4 * copy_word_size)); 199 4 * copy_word_size));
200} 200}
201 201
202static void __cpuinit build_clear_store(u32 **buf, int off) 202static void build_clear_store(u32 **buf, int off)
203{ 203{
204 if (cpu_has_64bit_gp_regs || cpu_has_64bit_zero_reg) { 204 if (cpu_has_64bit_gp_regs || cpu_has_64bit_zero_reg) {
205 uasm_i_sd(buf, ZERO, off, A0); 205 uasm_i_sd(buf, ZERO, off, A0);
@@ -208,7 +208,7 @@ static void __cpuinit build_clear_store(u32 **buf, int off)
208 } 208 }
209} 209}
210 210
211static inline void __cpuinit build_clear_pref(u32 **buf, int off) 211static inline void build_clear_pref(u32 **buf, int off)
212{ 212{
213 if (off & cache_line_mask()) 213 if (off & cache_line_mask())
214 return; 214 return;
@@ -240,7 +240,7 @@ extern u32 __clear_page_end;
240extern u32 __copy_page_start; 240extern u32 __copy_page_start;
241extern u32 __copy_page_end; 241extern u32 __copy_page_end;
242 242
243void __cpuinit build_clear_page(void) 243void build_clear_page(void)
244{ 244{
245 int off; 245 int off;
246 u32 *buf = &__clear_page_start; 246 u32 *buf = &__clear_page_start;
@@ -333,7 +333,7 @@ void __cpuinit build_clear_page(void)
333 pr_debug("\t.set pop\n"); 333 pr_debug("\t.set pop\n");
334} 334}
335 335
336static void __cpuinit build_copy_load(u32 **buf, int reg, int off) 336static void build_copy_load(u32 **buf, int reg, int off)
337{ 337{
338 if (cpu_has_64bit_gp_regs) { 338 if (cpu_has_64bit_gp_regs) {
339 uasm_i_ld(buf, reg, off, A1); 339 uasm_i_ld(buf, reg, off, A1);
@@ -342,7 +342,7 @@ static void __cpuinit build_copy_load(u32 **buf, int reg, int off)
342 } 342 }
343} 343}
344 344
345static void __cpuinit build_copy_store(u32 **buf, int reg, int off) 345static void build_copy_store(u32 **buf, int reg, int off)
346{ 346{
347 if (cpu_has_64bit_gp_regs) { 347 if (cpu_has_64bit_gp_regs) {
348 uasm_i_sd(buf, reg, off, A0); 348 uasm_i_sd(buf, reg, off, A0);
@@ -387,7 +387,7 @@ static inline void build_copy_store_pref(u32 **buf, int off)
387 } 387 }
388} 388}
389 389
390void __cpuinit build_copy_page(void) 390void build_copy_page(void)
391{ 391{
392 int off; 392 int off;
393 u32 *buf = &__copy_page_start; 393 u32 *buf = &__copy_page_start;
diff --git a/arch/mips/mm/sc-ip22.c b/arch/mips/mm/sc-ip22.c
index c6aaed934d53..dc7c5a5214a9 100644
--- a/arch/mips/mm/sc-ip22.c
+++ b/arch/mips/mm/sc-ip22.c
@@ -167,7 +167,7 @@ static struct bcache_ops indy_sc_ops = {
167 .bc_inv = indy_sc_wback_invalidate 167 .bc_inv = indy_sc_wback_invalidate
168}; 168};
169 169
170void __cpuinit indy_sc_init(void) 170void indy_sc_init(void)
171{ 171{
172 if (indy_sc_probe()) { 172 if (indy_sc_probe()) {
173 indy_sc_enable(); 173 indy_sc_enable();
diff --git a/arch/mips/mm/sc-mips.c b/arch/mips/mm/sc-mips.c
index df96da7e939b..5d01392e3518 100644
--- a/arch/mips/mm/sc-mips.c
+++ b/arch/mips/mm/sc-mips.c
@@ -132,7 +132,7 @@ static inline int __init mips_sc_probe(void)
132 return 1; 132 return 1;
133} 133}
134 134
135int __cpuinit mips_sc_init(void) 135int mips_sc_init(void)
136{ 136{
137 int found = mips_sc_probe(); 137 int found = mips_sc_probe();
138 if (found) { 138 if (found) {
diff --git a/arch/mips/mm/sc-r5k.c b/arch/mips/mm/sc-r5k.c
index 8bc67720e145..0216ed6eaa2a 100644
--- a/arch/mips/mm/sc-r5k.c
+++ b/arch/mips/mm/sc-r5k.c
@@ -98,7 +98,7 @@ static struct bcache_ops r5k_sc_ops = {
98 .bc_inv = r5k_dma_cache_inv_sc 98 .bc_inv = r5k_dma_cache_inv_sc
99}; 99};
100 100
101void __cpuinit r5k_sc_init(void) 101void r5k_sc_init(void)
102{ 102{
103 if (r5k_sc_probe()) { 103 if (r5k_sc_probe()) {
104 r5k_sc_enable(); 104 r5k_sc_enable();
diff --git a/arch/mips/mm/sc-rm7k.c b/arch/mips/mm/sc-rm7k.c
index 274af3be1442..aaffbba33706 100644
--- a/arch/mips/mm/sc-rm7k.c
+++ b/arch/mips/mm/sc-rm7k.c
@@ -104,7 +104,7 @@ static void blast_rm7k_tcache(void)
104/* 104/*
105 * This function is executed in uncached address space. 105 * This function is executed in uncached address space.
106 */ 106 */
107static __cpuinit void __rm7k_tc_enable(void) 107static void __rm7k_tc_enable(void)
108{ 108{
109 int i; 109 int i;
110 110
@@ -117,7 +117,7 @@ static __cpuinit void __rm7k_tc_enable(void)
117 cache_op(Index_Store_Tag_T, CKSEG0ADDR(i)); 117 cache_op(Index_Store_Tag_T, CKSEG0ADDR(i));
118} 118}
119 119
120static __cpuinit void rm7k_tc_enable(void) 120static void rm7k_tc_enable(void)
121{ 121{
122 if (read_c0_config() & RM7K_CONF_TE) 122 if (read_c0_config() & RM7K_CONF_TE)
123 return; 123 return;
@@ -130,7 +130,7 @@ static __cpuinit void rm7k_tc_enable(void)
130/* 130/*
131 * This function is executed in uncached address space. 131 * This function is executed in uncached address space.
132 */ 132 */
133static __cpuinit void __rm7k_sc_enable(void) 133static void __rm7k_sc_enable(void)
134{ 134{
135 int i; 135 int i;
136 136
@@ -143,7 +143,7 @@ static __cpuinit void __rm7k_sc_enable(void)
143 cache_op(Index_Store_Tag_SD, CKSEG0ADDR(i)); 143 cache_op(Index_Store_Tag_SD, CKSEG0ADDR(i));
144} 144}
145 145
146static __cpuinit void rm7k_sc_enable(void) 146static void rm7k_sc_enable(void)
147{ 147{
148 if (read_c0_config() & RM7K_CONF_SE) 148 if (read_c0_config() & RM7K_CONF_SE)
149 return; 149 return;
@@ -184,7 +184,7 @@ static struct bcache_ops rm7k_sc_ops = {
184 * This is a probing function like the one found in c-r4k.c, we look for the 184 * This is a probing function like the one found in c-r4k.c, we look for the
185 * wrap around point with different addresses. 185 * wrap around point with different addresses.
186 */ 186 */
187static __cpuinit void __probe_tcache(void) 187static void __probe_tcache(void)
188{ 188{
189 unsigned long flags, addr, begin, end, pow2; 189 unsigned long flags, addr, begin, end, pow2;
190 190
@@ -226,7 +226,7 @@ static __cpuinit void __probe_tcache(void)
226 local_irq_restore(flags); 226 local_irq_restore(flags);
227} 227}
228 228
229void __cpuinit rm7k_sc_init(void) 229void rm7k_sc_init(void)
230{ 230{
231 struct cpuinfo_mips *c = &current_cpu_data; 231 struct cpuinfo_mips *c = &current_cpu_data;
232 unsigned int config = read_c0_config(); 232 unsigned int config = read_c0_config();
diff --git a/arch/mips/mm/tlb-r3k.c b/arch/mips/mm/tlb-r3k.c
index a63d1ed0827f..9aca10994cd2 100644
--- a/arch/mips/mm/tlb-r3k.c
+++ b/arch/mips/mm/tlb-r3k.c
@@ -276,7 +276,7 @@ void add_wired_entry(unsigned long entrylo0, unsigned long entrylo1,
276 } 276 }
277} 277}
278 278
279void __cpuinit tlb_init(void) 279void tlb_init(void)
280{ 280{
281 local_flush_tlb_all(); 281 local_flush_tlb_all();
282 282
diff --git a/arch/mips/mm/tlb-r4k.c b/arch/mips/mm/tlb-r4k.c
index c643de4c473a..00b26a67a06d 100644
--- a/arch/mips/mm/tlb-r4k.c
+++ b/arch/mips/mm/tlb-r4k.c
@@ -389,7 +389,7 @@ int __init has_transparent_hugepage(void)
389 389
390#endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 390#endif /* CONFIG_TRANSPARENT_HUGEPAGE */
391 391
392static int __cpuinitdata ntlb; 392static int ntlb;
393static int __init set_ntlb(char *str) 393static int __init set_ntlb(char *str)
394{ 394{
395 get_option(&str, &ntlb); 395 get_option(&str, &ntlb);
@@ -398,7 +398,7 @@ static int __init set_ntlb(char *str)
398 398
399__setup("ntlb=", set_ntlb); 399__setup("ntlb=", set_ntlb);
400 400
401void __cpuinit tlb_init(void) 401void tlb_init(void)
402{ 402{
403 /* 403 /*
404 * You should never change this register: 404 * You should never change this register:
diff --git a/arch/mips/mm/tlb-r8k.c b/arch/mips/mm/tlb-r8k.c
index 91c2499f806a..6a99733a4440 100644
--- a/arch/mips/mm/tlb-r8k.c
+++ b/arch/mips/mm/tlb-r8k.c
@@ -213,14 +213,14 @@ void __update_tlb(struct vm_area_struct * vma, unsigned long address, pte_t pte)
213 local_irq_restore(flags); 213 local_irq_restore(flags);
214} 214}
215 215
216static void __cpuinit probe_tlb(unsigned long config) 216static void probe_tlb(unsigned long config)
217{ 217{
218 struct cpuinfo_mips *c = &current_cpu_data; 218 struct cpuinfo_mips *c = &current_cpu_data;
219 219
220 c->tlbsize = 3 * 128; /* 3 sets each 128 entries */ 220 c->tlbsize = 3 * 128; /* 3 sets each 128 entries */
221} 221}
222 222
223void __cpuinit tlb_init(void) 223void tlb_init(void)
224{ 224{
225 unsigned int config = read_c0_config(); 225 unsigned int config = read_c0_config();
226 unsigned long status; 226 unsigned long status;
diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c
index 9ab0f907a52c..34fce2b2095b 100644
--- a/arch/mips/mm/tlbex.c
+++ b/arch/mips/mm/tlbex.c
@@ -136,7 +136,7 @@ static int scratchpad_offset(int i)
136 * why; it's not an issue caused by the core RTL. 136 * why; it's not an issue caused by the core RTL.
137 * 137 *
138 */ 138 */
139static int __cpuinit m4kc_tlbp_war(void) 139static int m4kc_tlbp_war(void)
140{ 140{
141 return (current_cpu_data.processor_id & 0xffff00) == 141 return (current_cpu_data.processor_id & 0xffff00) ==
142 (PRID_COMP_MIPS | PRID_IMP_4KC); 142 (PRID_COMP_MIPS | PRID_IMP_4KC);
@@ -181,11 +181,9 @@ UASM_L_LA(_large_segbits_fault)
181UASM_L_LA(_tlb_huge_update) 181UASM_L_LA(_tlb_huge_update)
182#endif 182#endif
183 183
184static int __cpuinitdata hazard_instance; 184static int hazard_instance;
185 185
186static void __cpuinit uasm_bgezl_hazard(u32 **p, 186static void uasm_bgezl_hazard(u32 **p, struct uasm_reloc **r, int instance)
187 struct uasm_reloc **r,
188 int instance)
189{ 187{
190 switch (instance) { 188 switch (instance) {
191 case 0 ... 7: 189 case 0 ... 7:
@@ -196,9 +194,7 @@ static void __cpuinit uasm_bgezl_hazard(u32 **p,
196 } 194 }
197} 195}
198 196
199static void __cpuinit uasm_bgezl_label(struct uasm_label **l, 197static void uasm_bgezl_label(struct uasm_label **l, u32 **p, int instance)
200 u32 **p,
201 int instance)
202{ 198{
203 switch (instance) { 199 switch (instance) {
204 case 0 ... 7: 200 case 0 ... 7:
@@ -295,15 +291,15 @@ static inline void dump_handler(const char *symbol, const u32 *handler, int coun
295 * We deliberately chose a buffer size of 128, so we won't scribble 291 * We deliberately chose a buffer size of 128, so we won't scribble
296 * over anything important on overflow before we panic. 292 * over anything important on overflow before we panic.
297 */ 293 */
298static u32 tlb_handler[128] __cpuinitdata; 294static u32 tlb_handler[128];
299 295
300/* simply assume worst case size for labels and relocs */ 296/* simply assume worst case size for labels and relocs */
301static struct uasm_label labels[128] __cpuinitdata; 297static struct uasm_label labels[128];
302static struct uasm_reloc relocs[128] __cpuinitdata; 298static struct uasm_reloc relocs[128];
303 299
304static int check_for_high_segbits __cpuinitdata; 300static int check_for_high_segbits;
305 301
306static unsigned int kscratch_used_mask __cpuinitdata; 302static unsigned int kscratch_used_mask;
307 303
308static inline int __maybe_unused c0_kscratch(void) 304static inline int __maybe_unused c0_kscratch(void)
309{ 305{
@@ -316,7 +312,7 @@ static inline int __maybe_unused c0_kscratch(void)
316 } 312 }
317} 313}
318 314
319static int __cpuinit allocate_kscratch(void) 315static int allocate_kscratch(void)
320{ 316{
321 int r; 317 int r;
322 unsigned int a = cpu_data[0].kscratch_mask & ~kscratch_used_mask; 318 unsigned int a = cpu_data[0].kscratch_mask & ~kscratch_used_mask;
@@ -333,11 +329,11 @@ static int __cpuinit allocate_kscratch(void)
333 return r; 329 return r;
334} 330}
335 331
336static int scratch_reg __cpuinitdata; 332static int scratch_reg;
337static int pgd_reg __cpuinitdata; 333static int pgd_reg;
338enum vmalloc64_mode {not_refill, refill_scratch, refill_noscratch}; 334enum vmalloc64_mode {not_refill, refill_scratch, refill_noscratch};
339 335
340static struct work_registers __cpuinit build_get_work_registers(u32 **p) 336static struct work_registers build_get_work_registers(u32 **p)
341{ 337{
342 struct work_registers r; 338 struct work_registers r;
343 339
@@ -393,7 +389,7 @@ static struct work_registers __cpuinit build_get_work_registers(u32 **p)
393 return r; 389 return r;
394} 390}
395 391
396static void __cpuinit build_restore_work_registers(u32 **p) 392static void build_restore_work_registers(u32 **p)
397{ 393{
398 if (scratch_reg >= 0) { 394 if (scratch_reg >= 0) {
399 UASM_i_MFC0(p, 1, c0_kscratch(), scratch_reg); 395 UASM_i_MFC0(p, 1, c0_kscratch(), scratch_reg);
@@ -418,7 +414,7 @@ extern unsigned long pgd_current[];
418/* 414/*
419 * The R3000 TLB handler is simple. 415 * The R3000 TLB handler is simple.
420 */ 416 */
421static void __cpuinit build_r3000_tlb_refill_handler(void) 417static void build_r3000_tlb_refill_handler(void)
422{ 418{
423 long pgdc = (long)pgd_current; 419 long pgdc = (long)pgd_current;
424 u32 *p; 420 u32 *p;
@@ -463,7 +459,7 @@ static void __cpuinit build_r3000_tlb_refill_handler(void)
463 * other one.To keep things simple, we first assume linear space, 459 * other one.To keep things simple, we first assume linear space,
464 * then we relocate it to the final handler layout as needed. 460 * then we relocate it to the final handler layout as needed.
465 */ 461 */
466static u32 final_handler[64] __cpuinitdata; 462static u32 final_handler[64];
467 463
468/* 464/*
469 * Hazards 465 * Hazards
@@ -487,7 +483,7 @@ static u32 final_handler[64] __cpuinitdata;
487 * 483 *
488 * As if we MIPS hackers wouldn't know how to nop pipelines happy ... 484 * As if we MIPS hackers wouldn't know how to nop pipelines happy ...
489 */ 485 */
490static void __cpuinit __maybe_unused build_tlb_probe_entry(u32 **p) 486static void __maybe_unused build_tlb_probe_entry(u32 **p)
491{ 487{
492 switch (current_cpu_type()) { 488 switch (current_cpu_type()) {
493 /* Found by experiment: R4600 v2.0/R4700 needs this, too. */ 489 /* Found by experiment: R4600 v2.0/R4700 needs this, too. */
@@ -511,9 +507,9 @@ static void __cpuinit __maybe_unused build_tlb_probe_entry(u32 **p)
511 */ 507 */
512enum tlb_write_entry { tlb_random, tlb_indexed }; 508enum tlb_write_entry { tlb_random, tlb_indexed };
513 509
514static void __cpuinit build_tlb_write_entry(u32 **p, struct uasm_label **l, 510static void build_tlb_write_entry(u32 **p, struct uasm_label **l,
515 struct uasm_reloc **r, 511 struct uasm_reloc **r,
516 enum tlb_write_entry wmode) 512 enum tlb_write_entry wmode)
517{ 513{
518 void(*tlbw)(u32 **) = NULL; 514 void(*tlbw)(u32 **) = NULL;
519 515
@@ -647,8 +643,8 @@ static void __cpuinit build_tlb_write_entry(u32 **p, struct uasm_label **l,
647 } 643 }
648} 644}
649 645
650static __cpuinit __maybe_unused void build_convert_pte_to_entrylo(u32 **p, 646static __maybe_unused void build_convert_pte_to_entrylo(u32 **p,
651 unsigned int reg) 647 unsigned int reg)
652{ 648{
653 if (cpu_has_rixi) { 649 if (cpu_has_rixi) {
654 UASM_i_ROTR(p, reg, reg, ilog2(_PAGE_GLOBAL)); 650 UASM_i_ROTR(p, reg, reg, ilog2(_PAGE_GLOBAL));
@@ -663,11 +659,9 @@ static __cpuinit __maybe_unused void build_convert_pte_to_entrylo(u32 **p,
663 659
664#ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT 660#ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
665 661
666static __cpuinit void build_restore_pagemask(u32 **p, 662static void build_restore_pagemask(u32 **p, struct uasm_reloc **r,
667 struct uasm_reloc **r, 663 unsigned int tmp, enum label_id lid,
668 unsigned int tmp, 664 int restore_scratch)
669 enum label_id lid,
670 int restore_scratch)
671{ 665{
672 if (restore_scratch) { 666 if (restore_scratch) {
673 /* Reset default page size */ 667 /* Reset default page size */
@@ -706,12 +700,11 @@ static __cpuinit void build_restore_pagemask(u32 **p,
706 } 700 }
707} 701}
708 702
709static __cpuinit void build_huge_tlb_write_entry(u32 **p, 703static void build_huge_tlb_write_entry(u32 **p, struct uasm_label **l,
710 struct uasm_label **l, 704 struct uasm_reloc **r,
711 struct uasm_reloc **r, 705 unsigned int tmp,
712 unsigned int tmp, 706 enum tlb_write_entry wmode,
713 enum tlb_write_entry wmode, 707 int restore_scratch)
714 int restore_scratch)
715{ 708{
716 /* Set huge page tlb entry size */ 709 /* Set huge page tlb entry size */
717 uasm_i_lui(p, tmp, PM_HUGE_MASK >> 16); 710 uasm_i_lui(p, tmp, PM_HUGE_MASK >> 16);
@@ -726,9 +719,9 @@ static __cpuinit void build_huge_tlb_write_entry(u32 **p,
726/* 719/*
727 * Check if Huge PTE is present, if so then jump to LABEL. 720 * Check if Huge PTE is present, if so then jump to LABEL.
728 */ 721 */
729static void __cpuinit 722static void
730build_is_huge_pte(u32 **p, struct uasm_reloc **r, unsigned int tmp, 723build_is_huge_pte(u32 **p, struct uasm_reloc **r, unsigned int tmp,
731 unsigned int pmd, int lid) 724 unsigned int pmd, int lid)
732{ 725{
733 UASM_i_LW(p, tmp, 0, pmd); 726 UASM_i_LW(p, tmp, 0, pmd);
734 if (use_bbit_insns()) { 727 if (use_bbit_insns()) {
@@ -739,9 +732,8 @@ build_is_huge_pte(u32 **p, struct uasm_reloc **r, unsigned int tmp,
739 } 732 }
740} 733}
741 734
742static __cpuinit void build_huge_update_entries(u32 **p, 735static void build_huge_update_entries(u32 **p, unsigned int pte,
743 unsigned int pte, 736 unsigned int tmp)
744 unsigned int tmp)
745{ 737{
746 int small_sequence; 738 int small_sequence;
747 739
@@ -771,11 +763,10 @@ static __cpuinit void build_huge_update_entries(u32 **p,
771 UASM_i_MTC0(p, pte, C0_ENTRYLO1); /* load it */ 763 UASM_i_MTC0(p, pte, C0_ENTRYLO1); /* load it */
772} 764}
773 765
774static __cpuinit void build_huge_handler_tail(u32 **p, 766static void build_huge_handler_tail(u32 **p, struct uasm_reloc **r,
775 struct uasm_reloc **r, 767 struct uasm_label **l,
776 struct uasm_label **l, 768 unsigned int pte,
777 unsigned int pte, 769 unsigned int ptr)
778 unsigned int ptr)
779{ 770{
780#ifdef CONFIG_SMP 771#ifdef CONFIG_SMP
781 UASM_i_SC(p, pte, 0, ptr); 772 UASM_i_SC(p, pte, 0, ptr);
@@ -794,7 +785,7 @@ static __cpuinit void build_huge_handler_tail(u32 **p,
794 * TMP and PTR are scratch. 785 * TMP and PTR are scratch.
795 * TMP will be clobbered, PTR will hold the pmd entry. 786 * TMP will be clobbered, PTR will hold the pmd entry.
796 */ 787 */
797static void __cpuinit 788static void
798build_get_pmde64(u32 **p, struct uasm_label **l, struct uasm_reloc **r, 789build_get_pmde64(u32 **p, struct uasm_label **l, struct uasm_reloc **r,
799 unsigned int tmp, unsigned int ptr) 790 unsigned int tmp, unsigned int ptr)
800{ 791{
@@ -886,7 +877,7 @@ build_get_pmde64(u32 **p, struct uasm_label **l, struct uasm_reloc **r,
886 * BVADDR is the faulting address, PTR is scratch. 877 * BVADDR is the faulting address, PTR is scratch.
887 * PTR will hold the pgd for vmalloc. 878 * PTR will hold the pgd for vmalloc.
888 */ 879 */
889static void __cpuinit 880static void
890build_get_pgd_vmalloc64(u32 **p, struct uasm_label **l, struct uasm_reloc **r, 881build_get_pgd_vmalloc64(u32 **p, struct uasm_label **l, struct uasm_reloc **r,
891 unsigned int bvaddr, unsigned int ptr, 882 unsigned int bvaddr, unsigned int ptr,
892 enum vmalloc64_mode mode) 883 enum vmalloc64_mode mode)
@@ -956,7 +947,7 @@ build_get_pgd_vmalloc64(u32 **p, struct uasm_label **l, struct uasm_reloc **r,
956 * TMP and PTR are scratch. 947 * TMP and PTR are scratch.
957 * TMP will be clobbered, PTR will hold the pgd entry. 948 * TMP will be clobbered, PTR will hold the pgd entry.
958 */ 949 */
959static void __cpuinit __maybe_unused 950static void __maybe_unused
960build_get_pgde32(u32 **p, unsigned int tmp, unsigned int ptr) 951build_get_pgde32(u32 **p, unsigned int tmp, unsigned int ptr)
961{ 952{
962 long pgdc = (long)pgd_current; 953 long pgdc = (long)pgd_current;
@@ -991,7 +982,7 @@ build_get_pgde32(u32 **p, unsigned int tmp, unsigned int ptr)
991 982
992#endif /* !CONFIG_64BIT */ 983#endif /* !CONFIG_64BIT */
993 984
994static void __cpuinit build_adjust_context(u32 **p, unsigned int ctx) 985static void build_adjust_context(u32 **p, unsigned int ctx)
995{ 986{
996 unsigned int shift = 4 - (PTE_T_LOG2 + 1) + PAGE_SHIFT - 12; 987 unsigned int shift = 4 - (PTE_T_LOG2 + 1) + PAGE_SHIFT - 12;
997 unsigned int mask = (PTRS_PER_PTE / 2 - 1) << (PTE_T_LOG2 + 1); 988 unsigned int mask = (PTRS_PER_PTE / 2 - 1) << (PTE_T_LOG2 + 1);
@@ -1017,7 +1008,7 @@ static void __cpuinit build_adjust_context(u32 **p, unsigned int ctx)
1017 uasm_i_andi(p, ctx, ctx, mask); 1008 uasm_i_andi(p, ctx, ctx, mask);
1018} 1009}
1019 1010
1020static void __cpuinit build_get_ptep(u32 **p, unsigned int tmp, unsigned int ptr) 1011static void build_get_ptep(u32 **p, unsigned int tmp, unsigned int ptr)
1021{ 1012{
1022 /* 1013 /*
1023 * Bug workaround for the Nevada. It seems as if under certain 1014 * Bug workaround for the Nevada. It seems as if under certain
@@ -1042,8 +1033,7 @@ static void __cpuinit build_get_ptep(u32 **p, unsigned int tmp, unsigned int ptr
1042 UASM_i_ADDU(p, ptr, ptr, tmp); /* add in offset */ 1033 UASM_i_ADDU(p, ptr, ptr, tmp); /* add in offset */
1043} 1034}
1044 1035
1045static void __cpuinit build_update_entries(u32 **p, unsigned int tmp, 1036static void build_update_entries(u32 **p, unsigned int tmp, unsigned int ptep)
1046 unsigned int ptep)
1047{ 1037{
1048 /* 1038 /*
1049 * 64bit address support (36bit on a 32bit CPU) in a 32bit 1039 * 64bit address support (36bit on a 32bit CPU) in a 32bit
@@ -1104,7 +1094,7 @@ struct mips_huge_tlb_info {
1104 int restore_scratch; 1094 int restore_scratch;
1105}; 1095};
1106 1096
1107static struct mips_huge_tlb_info __cpuinit 1097static struct mips_huge_tlb_info
1108build_fast_tlb_refill_handler (u32 **p, struct uasm_label **l, 1098build_fast_tlb_refill_handler (u32 **p, struct uasm_label **l,
1109 struct uasm_reloc **r, unsigned int tmp, 1099 struct uasm_reloc **r, unsigned int tmp,
1110 unsigned int ptr, int c0_scratch_reg) 1100 unsigned int ptr, int c0_scratch_reg)
@@ -1282,7 +1272,7 @@ build_fast_tlb_refill_handler (u32 **p, struct uasm_label **l,
1282 */ 1272 */
1283#define MIPS64_REFILL_INSNS 32 1273#define MIPS64_REFILL_INSNS 32
1284 1274
1285static void __cpuinit build_r4000_tlb_refill_handler(void) 1275static void build_r4000_tlb_refill_handler(void)
1286{ 1276{
1287 u32 *p = tlb_handler; 1277 u32 *p = tlb_handler;
1288 struct uasm_label *l = labels; 1278 struct uasm_label *l = labels;
@@ -1462,7 +1452,7 @@ extern u32 handle_tlbm[], handle_tlbm_end[];
1462#ifdef CONFIG_MIPS_PGD_C0_CONTEXT 1452#ifdef CONFIG_MIPS_PGD_C0_CONTEXT
1463extern u32 tlbmiss_handler_setup_pgd[], tlbmiss_handler_setup_pgd_end[]; 1453extern u32 tlbmiss_handler_setup_pgd[], tlbmiss_handler_setup_pgd_end[];
1464 1454
1465static void __cpuinit build_r4000_setup_pgd(void) 1455static void build_r4000_setup_pgd(void)
1466{ 1456{
1467 const int a0 = 4; 1457 const int a0 = 4;
1468 const int a1 = 5; 1458 const int a1 = 5;
@@ -1513,7 +1503,7 @@ static void __cpuinit build_r4000_setup_pgd(void)
1513} 1503}
1514#endif 1504#endif
1515 1505
1516static void __cpuinit 1506static void
1517iPTE_LW(u32 **p, unsigned int pte, unsigned int ptr) 1507iPTE_LW(u32 **p, unsigned int pte, unsigned int ptr)
1518{ 1508{
1519#ifdef CONFIG_SMP 1509#ifdef CONFIG_SMP
@@ -1533,7 +1523,7 @@ iPTE_LW(u32 **p, unsigned int pte, unsigned int ptr)
1533#endif 1523#endif
1534} 1524}
1535 1525
1536static void __cpuinit 1526static void
1537iPTE_SW(u32 **p, struct uasm_reloc **r, unsigned int pte, unsigned int ptr, 1527iPTE_SW(u32 **p, struct uasm_reloc **r, unsigned int pte, unsigned int ptr,
1538 unsigned int mode) 1528 unsigned int mode)
1539{ 1529{
@@ -1593,7 +1583,7 @@ iPTE_SW(u32 **p, struct uasm_reloc **r, unsigned int pte, unsigned int ptr,
1593 * the page table where this PTE is located, PTE will be re-loaded 1583 * the page table where this PTE is located, PTE will be re-loaded
1594 * with it's original value. 1584 * with it's original value.
1595 */ 1585 */
1596static void __cpuinit 1586static void
1597build_pte_present(u32 **p, struct uasm_reloc **r, 1587build_pte_present(u32 **p, struct uasm_reloc **r,
1598 int pte, int ptr, int scratch, enum label_id lid) 1588 int pte, int ptr, int scratch, enum label_id lid)
1599{ 1589{
@@ -1621,7 +1611,7 @@ build_pte_present(u32 **p, struct uasm_reloc **r,
1621} 1611}
1622 1612
1623/* Make PTE valid, store result in PTR. */ 1613/* Make PTE valid, store result in PTR. */
1624static void __cpuinit 1614static void
1625build_make_valid(u32 **p, struct uasm_reloc **r, unsigned int pte, 1615build_make_valid(u32 **p, struct uasm_reloc **r, unsigned int pte,
1626 unsigned int ptr) 1616 unsigned int ptr)
1627{ 1617{
@@ -1634,7 +1624,7 @@ build_make_valid(u32 **p, struct uasm_reloc **r, unsigned int pte,
1634 * Check if PTE can be written to, if not branch to LABEL. Regardless 1624 * Check if PTE can be written to, if not branch to LABEL. Regardless
1635 * restore PTE with value from PTR when done. 1625 * restore PTE with value from PTR when done.
1636 */ 1626 */
1637static void __cpuinit 1627static void
1638build_pte_writable(u32 **p, struct uasm_reloc **r, 1628build_pte_writable(u32 **p, struct uasm_reloc **r,
1639 unsigned int pte, unsigned int ptr, int scratch, 1629 unsigned int pte, unsigned int ptr, int scratch,
1640 enum label_id lid) 1630 enum label_id lid)
@@ -1654,7 +1644,7 @@ build_pte_writable(u32 **p, struct uasm_reloc **r,
1654/* Make PTE writable, update software status bits as well, then store 1644/* Make PTE writable, update software status bits as well, then store
1655 * at PTR. 1645 * at PTR.
1656 */ 1646 */
1657static void __cpuinit 1647static void
1658build_make_write(u32 **p, struct uasm_reloc **r, unsigned int pte, 1648build_make_write(u32 **p, struct uasm_reloc **r, unsigned int pte,
1659 unsigned int ptr) 1649 unsigned int ptr)
1660{ 1650{
@@ -1668,7 +1658,7 @@ build_make_write(u32 **p, struct uasm_reloc **r, unsigned int pte,
1668 * Check if PTE can be modified, if not branch to LABEL. Regardless 1658 * Check if PTE can be modified, if not branch to LABEL. Regardless
1669 * restore PTE with value from PTR when done. 1659 * restore PTE with value from PTR when done.
1670 */ 1660 */
1671static void __cpuinit 1661static void
1672build_pte_modifiable(u32 **p, struct uasm_reloc **r, 1662build_pte_modifiable(u32 **p, struct uasm_reloc **r,
1673 unsigned int pte, unsigned int ptr, int scratch, 1663 unsigned int pte, unsigned int ptr, int scratch,
1674 enum label_id lid) 1664 enum label_id lid)
@@ -1697,7 +1687,7 @@ build_pte_modifiable(u32 **p, struct uasm_reloc **r,
1697 * This places the pte into ENTRYLO0 and writes it with tlbwi. 1687 * This places the pte into ENTRYLO0 and writes it with tlbwi.
1698 * Then it returns. 1688 * Then it returns.
1699 */ 1689 */
1700static void __cpuinit 1690static void
1701build_r3000_pte_reload_tlbwi(u32 **p, unsigned int pte, unsigned int tmp) 1691build_r3000_pte_reload_tlbwi(u32 **p, unsigned int pte, unsigned int tmp)
1702{ 1692{
1703 uasm_i_mtc0(p, pte, C0_ENTRYLO0); /* cp0 delay */ 1693 uasm_i_mtc0(p, pte, C0_ENTRYLO0); /* cp0 delay */
@@ -1713,7 +1703,7 @@ build_r3000_pte_reload_tlbwi(u32 **p, unsigned int pte, unsigned int tmp)
1713 * may have the probe fail bit set as a result of a trap on a 1703 * may have the probe fail bit set as a result of a trap on a
1714 * kseg2 access, i.e. without refill. Then it returns. 1704 * kseg2 access, i.e. without refill. Then it returns.
1715 */ 1705 */
1716static void __cpuinit 1706static void
1717build_r3000_tlb_reload_write(u32 **p, struct uasm_label **l, 1707build_r3000_tlb_reload_write(u32 **p, struct uasm_label **l,
1718 struct uasm_reloc **r, unsigned int pte, 1708 struct uasm_reloc **r, unsigned int pte,
1719 unsigned int tmp) 1709 unsigned int tmp)
@@ -1731,7 +1721,7 @@ build_r3000_tlb_reload_write(u32 **p, struct uasm_label **l,
1731 uasm_i_rfe(p); /* branch delay */ 1721 uasm_i_rfe(p); /* branch delay */
1732} 1722}
1733 1723
1734static void __cpuinit 1724static void
1735build_r3000_tlbchange_handler_head(u32 **p, unsigned int pte, 1725build_r3000_tlbchange_handler_head(u32 **p, unsigned int pte,
1736 unsigned int ptr) 1726 unsigned int ptr)
1737{ 1727{
@@ -1751,7 +1741,7 @@ build_r3000_tlbchange_handler_head(u32 **p, unsigned int pte,
1751 uasm_i_tlbp(p); /* load delay */ 1741 uasm_i_tlbp(p); /* load delay */
1752} 1742}
1753 1743
1754static void __cpuinit build_r3000_tlb_load_handler(void) 1744static void build_r3000_tlb_load_handler(void)
1755{ 1745{
1756 u32 *p = handle_tlbl; 1746 u32 *p = handle_tlbl;
1757 const int handle_tlbl_size = handle_tlbl_end - handle_tlbl; 1747 const int handle_tlbl_size = handle_tlbl_end - handle_tlbl;
@@ -1782,7 +1772,7 @@ static void __cpuinit build_r3000_tlb_load_handler(void)
1782 dump_handler("r3000_tlb_load", handle_tlbl, handle_tlbl_size); 1772 dump_handler("r3000_tlb_load", handle_tlbl, handle_tlbl_size);
1783} 1773}
1784 1774
1785static void __cpuinit build_r3000_tlb_store_handler(void) 1775static void build_r3000_tlb_store_handler(void)
1786{ 1776{
1787 u32 *p = handle_tlbs; 1777 u32 *p = handle_tlbs;
1788 const int handle_tlbs_size = handle_tlbs_end - handle_tlbs; 1778 const int handle_tlbs_size = handle_tlbs_end - handle_tlbs;
@@ -1813,7 +1803,7 @@ static void __cpuinit build_r3000_tlb_store_handler(void)
1813 dump_handler("r3000_tlb_store", handle_tlbs, handle_tlbs_size); 1803 dump_handler("r3000_tlb_store", handle_tlbs, handle_tlbs_size);
1814} 1804}
1815 1805
1816static void __cpuinit build_r3000_tlb_modify_handler(void) 1806static void build_r3000_tlb_modify_handler(void)
1817{ 1807{
1818 u32 *p = handle_tlbm; 1808 u32 *p = handle_tlbm;
1819 const int handle_tlbm_size = handle_tlbm_end - handle_tlbm; 1809 const int handle_tlbm_size = handle_tlbm_end - handle_tlbm;
@@ -1848,7 +1838,7 @@ static void __cpuinit build_r3000_tlb_modify_handler(void)
1848/* 1838/*
1849 * R4000 style TLB load/store/modify handlers. 1839 * R4000 style TLB load/store/modify handlers.
1850 */ 1840 */
1851static struct work_registers __cpuinit 1841static struct work_registers
1852build_r4000_tlbchange_handler_head(u32 **p, struct uasm_label **l, 1842build_r4000_tlbchange_handler_head(u32 **p, struct uasm_label **l,
1853 struct uasm_reloc **r) 1843 struct uasm_reloc **r)
1854{ 1844{
@@ -1884,7 +1874,7 @@ build_r4000_tlbchange_handler_head(u32 **p, struct uasm_label **l,
1884 return wr; 1874 return wr;
1885} 1875}
1886 1876
1887static void __cpuinit 1877static void
1888build_r4000_tlbchange_handler_tail(u32 **p, struct uasm_label **l, 1878build_r4000_tlbchange_handler_tail(u32 **p, struct uasm_label **l,
1889 struct uasm_reloc **r, unsigned int tmp, 1879 struct uasm_reloc **r, unsigned int tmp,
1890 unsigned int ptr) 1880 unsigned int ptr)
@@ -1902,7 +1892,7 @@ build_r4000_tlbchange_handler_tail(u32 **p, struct uasm_label **l,
1902#endif 1892#endif
1903} 1893}
1904 1894
1905static void __cpuinit build_r4000_tlb_load_handler(void) 1895static void build_r4000_tlb_load_handler(void)
1906{ 1896{
1907 u32 *p = handle_tlbl; 1897 u32 *p = handle_tlbl;
1908 const int handle_tlbl_size = handle_tlbl_end - handle_tlbl; 1898 const int handle_tlbl_size = handle_tlbl_end - handle_tlbl;
@@ -2085,7 +2075,7 @@ static void __cpuinit build_r4000_tlb_load_handler(void)
2085 dump_handler("r4000_tlb_load", handle_tlbl, handle_tlbl_size); 2075 dump_handler("r4000_tlb_load", handle_tlbl, handle_tlbl_size);
2086} 2076}
2087 2077
2088static void __cpuinit build_r4000_tlb_store_handler(void) 2078static void build_r4000_tlb_store_handler(void)
2089{ 2079{
2090 u32 *p = handle_tlbs; 2080 u32 *p = handle_tlbs;
2091 const int handle_tlbs_size = handle_tlbs_end - handle_tlbs; 2081 const int handle_tlbs_size = handle_tlbs_end - handle_tlbs;
@@ -2140,7 +2130,7 @@ static void __cpuinit build_r4000_tlb_store_handler(void)
2140 dump_handler("r4000_tlb_store", handle_tlbs, handle_tlbs_size); 2130 dump_handler("r4000_tlb_store", handle_tlbs, handle_tlbs_size);
2141} 2131}
2142 2132
2143static void __cpuinit build_r4000_tlb_modify_handler(void) 2133static void build_r4000_tlb_modify_handler(void)
2144{ 2134{
2145 u32 *p = handle_tlbm; 2135 u32 *p = handle_tlbm;
2146 const int handle_tlbm_size = handle_tlbm_end - handle_tlbm; 2136 const int handle_tlbm_size = handle_tlbm_end - handle_tlbm;
@@ -2196,7 +2186,7 @@ static void __cpuinit build_r4000_tlb_modify_handler(void)
2196 dump_handler("r4000_tlb_modify", handle_tlbm, handle_tlbm_size); 2186 dump_handler("r4000_tlb_modify", handle_tlbm, handle_tlbm_size);
2197} 2187}
2198 2188
2199static void __cpuinit flush_tlb_handlers(void) 2189static void flush_tlb_handlers(void)
2200{ 2190{
2201 local_flush_icache_range((unsigned long)handle_tlbl, 2191 local_flush_icache_range((unsigned long)handle_tlbl,
2202 (unsigned long)handle_tlbl_end); 2192 (unsigned long)handle_tlbl_end);
@@ -2210,7 +2200,7 @@ static void __cpuinit flush_tlb_handlers(void)
2210#endif 2200#endif
2211} 2201}
2212 2202
2213void __cpuinit build_tlb_refill_handler(void) 2203void build_tlb_refill_handler(void)
2214{ 2204{
2215 /* 2205 /*
2216 * The refill handler is generated per-CPU, multi-node systems 2206 * The refill handler is generated per-CPU, multi-node systems
diff --git a/arch/mips/mm/uasm-micromips.c b/arch/mips/mm/uasm-micromips.c
index 162ee6d62788..060000fa653c 100644
--- a/arch/mips/mm/uasm-micromips.c
+++ b/arch/mips/mm/uasm-micromips.c
@@ -49,7 +49,7 @@
49 49
50#include "uasm.c" 50#include "uasm.c"
51 51
52static struct insn insn_table_MM[] __uasminitdata = { 52static struct insn insn_table_MM[] = {
53 { insn_addu, M(mm_pool32a_op, 0, 0, 0, 0, mm_addu32_op), RT | RS | RD }, 53 { insn_addu, M(mm_pool32a_op, 0, 0, 0, 0, mm_addu32_op), RT | RS | RD },
54 { insn_addiu, M(mm_addiu32_op, 0, 0, 0, 0, 0), RT | RS | SIMM }, 54 { insn_addiu, M(mm_addiu32_op, 0, 0, 0, 0, 0), RT | RS | SIMM },
55 { insn_and, M(mm_pool32a_op, 0, 0, 0, 0, mm_and_op), RT | RS | RD }, 55 { insn_and, M(mm_pool32a_op, 0, 0, 0, 0, mm_and_op), RT | RS | RD },
@@ -118,7 +118,7 @@ static struct insn insn_table_MM[] __uasminitdata = {
118 118
119#undef M 119#undef M
120 120
121static inline __uasminit u32 build_bimm(s32 arg) 121static inline u32 build_bimm(s32 arg)
122{ 122{
123 WARN(arg > 0xffff || arg < -0x10000, 123 WARN(arg > 0xffff || arg < -0x10000,
124 KERN_WARNING "Micro-assembler field overflow\n"); 124 KERN_WARNING "Micro-assembler field overflow\n");
@@ -128,7 +128,7 @@ static inline __uasminit u32 build_bimm(s32 arg)
128 return ((arg < 0) ? (1 << 15) : 0) | ((arg >> 1) & 0x7fff); 128 return ((arg < 0) ? (1 << 15) : 0) | ((arg >> 1) & 0x7fff);
129} 129}
130 130
131static inline __uasminit u32 build_jimm(u32 arg) 131static inline u32 build_jimm(u32 arg)
132{ 132{
133 133
134 WARN(arg & ~((JIMM_MASK << 2) | 1), 134 WARN(arg & ~((JIMM_MASK << 2) | 1),
@@ -141,7 +141,7 @@ static inline __uasminit u32 build_jimm(u32 arg)
141 * The order of opcode arguments is implicitly left to right, 141 * The order of opcode arguments is implicitly left to right,
142 * starting with RS and ending with FUNC or IMM. 142 * starting with RS and ending with FUNC or IMM.
143 */ 143 */
144static void __uasminit build_insn(u32 **buf, enum opcode opc, ...) 144static void build_insn(u32 **buf, enum opcode opc, ...)
145{ 145{
146 struct insn *ip = NULL; 146 struct insn *ip = NULL;
147 unsigned int i; 147 unsigned int i;
@@ -199,7 +199,7 @@ static void __uasminit build_insn(u32 **buf, enum opcode opc, ...)
199 (*buf)++; 199 (*buf)++;
200} 200}
201 201
202static inline void __uasminit 202static inline void
203__resolve_relocs(struct uasm_reloc *rel, struct uasm_label *lab) 203__resolve_relocs(struct uasm_reloc *rel, struct uasm_label *lab)
204{ 204{
205 long laddr = (long)lab->addr; 205 long laddr = (long)lab->addr;
diff --git a/arch/mips/mm/uasm-mips.c b/arch/mips/mm/uasm-mips.c
index 5fcdd8fe3e83..0c724589854e 100644
--- a/arch/mips/mm/uasm-mips.c
+++ b/arch/mips/mm/uasm-mips.c
@@ -49,7 +49,7 @@
49 49
50#include "uasm.c" 50#include "uasm.c"
51 51
52static struct insn insn_table[] __uasminitdata = { 52static struct insn insn_table[] = {
53 { insn_addiu, M(addiu_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, 53 { insn_addiu, M(addiu_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
54 { insn_addu, M(spec_op, 0, 0, 0, 0, addu_op), RS | RT | RD }, 54 { insn_addu, M(spec_op, 0, 0, 0, 0, addu_op), RS | RT | RD },
55 { insn_andi, M(andi_op, 0, 0, 0, 0, 0), RS | RT | UIMM }, 55 { insn_andi, M(andi_op, 0, 0, 0, 0, 0), RS | RT | UIMM },
@@ -119,7 +119,7 @@ static struct insn insn_table[] __uasminitdata = {
119 119
120#undef M 120#undef M
121 121
122static inline __uasminit u32 build_bimm(s32 arg) 122static inline u32 build_bimm(s32 arg)
123{ 123{
124 WARN(arg > 0x1ffff || arg < -0x20000, 124 WARN(arg > 0x1ffff || arg < -0x20000,
125 KERN_WARNING "Micro-assembler field overflow\n"); 125 KERN_WARNING "Micro-assembler field overflow\n");
@@ -129,7 +129,7 @@ static inline __uasminit u32 build_bimm(s32 arg)
129 return ((arg < 0) ? (1 << 15) : 0) | ((arg >> 2) & 0x7fff); 129 return ((arg < 0) ? (1 << 15) : 0) | ((arg >> 2) & 0x7fff);
130} 130}
131 131
132static inline __uasminit u32 build_jimm(u32 arg) 132static inline u32 build_jimm(u32 arg)
133{ 133{
134 WARN(arg & ~(JIMM_MASK << 2), 134 WARN(arg & ~(JIMM_MASK << 2),
135 KERN_WARNING "Micro-assembler field overflow\n"); 135 KERN_WARNING "Micro-assembler field overflow\n");
@@ -141,7 +141,7 @@ static inline __uasminit u32 build_jimm(u32 arg)
141 * The order of opcode arguments is implicitly left to right, 141 * The order of opcode arguments is implicitly left to right,
142 * starting with RS and ending with FUNC or IMM. 142 * starting with RS and ending with FUNC or IMM.
143 */ 143 */
144static void __uasminit build_insn(u32 **buf, enum opcode opc, ...) 144static void build_insn(u32 **buf, enum opcode opc, ...)
145{ 145{
146 struct insn *ip = NULL; 146 struct insn *ip = NULL;
147 unsigned int i; 147 unsigned int i;
@@ -187,7 +187,7 @@ static void __uasminit build_insn(u32 **buf, enum opcode opc, ...)
187 (*buf)++; 187 (*buf)++;
188} 188}
189 189
190static inline void __uasminit 190static inline void
191__resolve_relocs(struct uasm_reloc *rel, struct uasm_label *lab) 191__resolve_relocs(struct uasm_reloc *rel, struct uasm_label *lab)
192{ 192{
193 long laddr = (long)lab->addr; 193 long laddr = (long)lab->addr;
diff --git a/arch/mips/mm/uasm.c b/arch/mips/mm/uasm.c
index 7eb5e4355d25..b9d14b6c7f58 100644
--- a/arch/mips/mm/uasm.c
+++ b/arch/mips/mm/uasm.c
@@ -63,35 +63,35 @@ struct insn {
63 enum fields fields; 63 enum fields fields;
64}; 64};
65 65
66static inline __uasminit u32 build_rs(u32 arg) 66static inline u32 build_rs(u32 arg)
67{ 67{
68 WARN(arg & ~RS_MASK, KERN_WARNING "Micro-assembler field overflow\n"); 68 WARN(arg & ~RS_MASK, KERN_WARNING "Micro-assembler field overflow\n");
69 69
70 return (arg & RS_MASK) << RS_SH; 70 return (arg & RS_MASK) << RS_SH;
71} 71}
72 72
73static inline __uasminit u32 build_rt(u32 arg) 73static inline u32 build_rt(u32 arg)
74{ 74{
75 WARN(arg & ~RT_MASK, KERN_WARNING "Micro-assembler field overflow\n"); 75 WARN(arg & ~RT_MASK, KERN_WARNING "Micro-assembler field overflow\n");
76 76
77 return (arg & RT_MASK) << RT_SH; 77 return (arg & RT_MASK) << RT_SH;
78} 78}
79 79
80static inline __uasminit u32 build_rd(u32 arg) 80static inline u32 build_rd(u32 arg)
81{ 81{
82 WARN(arg & ~RD_MASK, KERN_WARNING "Micro-assembler field overflow\n"); 82 WARN(arg & ~RD_MASK, KERN_WARNING "Micro-assembler field overflow\n");
83 83
84 return (arg & RD_MASK) << RD_SH; 84 return (arg & RD_MASK) << RD_SH;
85} 85}
86 86
87static inline __uasminit u32 build_re(u32 arg) 87static inline u32 build_re(u32 arg)
88{ 88{
89 WARN(arg & ~RE_MASK, KERN_WARNING "Micro-assembler field overflow\n"); 89 WARN(arg & ~RE_MASK, KERN_WARNING "Micro-assembler field overflow\n");
90 90
91 return (arg & RE_MASK) << RE_SH; 91 return (arg & RE_MASK) << RE_SH;
92} 92}
93 93
94static inline __uasminit u32 build_simm(s32 arg) 94static inline u32 build_simm(s32 arg)
95{ 95{
96 WARN(arg > 0x7fff || arg < -0x8000, 96 WARN(arg > 0x7fff || arg < -0x8000,
97 KERN_WARNING "Micro-assembler field overflow\n"); 97 KERN_WARNING "Micro-assembler field overflow\n");
@@ -99,14 +99,14 @@ static inline __uasminit u32 build_simm(s32 arg)
99 return arg & 0xffff; 99 return arg & 0xffff;
100} 100}
101 101
102static inline __uasminit u32 build_uimm(u32 arg) 102static inline u32 build_uimm(u32 arg)
103{ 103{
104 WARN(arg & ~IMM_MASK, KERN_WARNING "Micro-assembler field overflow\n"); 104 WARN(arg & ~IMM_MASK, KERN_WARNING "Micro-assembler field overflow\n");
105 105
106 return arg & IMM_MASK; 106 return arg & IMM_MASK;
107} 107}
108 108
109static inline __uasminit u32 build_scimm(u32 arg) 109static inline u32 build_scimm(u32 arg)
110{ 110{
111 WARN(arg & ~SCIMM_MASK, 111 WARN(arg & ~SCIMM_MASK,
112 KERN_WARNING "Micro-assembler field overflow\n"); 112 KERN_WARNING "Micro-assembler field overflow\n");
@@ -114,21 +114,21 @@ static inline __uasminit u32 build_scimm(u32 arg)
114 return (arg & SCIMM_MASK) << SCIMM_SH; 114 return (arg & SCIMM_MASK) << SCIMM_SH;
115} 115}
116 116
117static inline __uasminit u32 build_func(u32 arg) 117static inline u32 build_func(u32 arg)
118{ 118{
119 WARN(arg & ~FUNC_MASK, KERN_WARNING "Micro-assembler field overflow\n"); 119 WARN(arg & ~FUNC_MASK, KERN_WARNING "Micro-assembler field overflow\n");
120 120
121 return arg & FUNC_MASK; 121 return arg & FUNC_MASK;
122} 122}
123 123
124static inline __uasminit u32 build_set(u32 arg) 124static inline u32 build_set(u32 arg)
125{ 125{
126 WARN(arg & ~SET_MASK, KERN_WARNING "Micro-assembler field overflow\n"); 126 WARN(arg & ~SET_MASK, KERN_WARNING "Micro-assembler field overflow\n");
127 127
128 return arg & SET_MASK; 128 return arg & SET_MASK;
129} 129}
130 130
131static void __uasminit build_insn(u32 **buf, enum opcode opc, ...); 131static void build_insn(u32 **buf, enum opcode opc, ...);
132 132
133#define I_u1u2u3(op) \ 133#define I_u1u2u3(op) \
134Ip_u1u2u3(op) \ 134Ip_u1u2u3(op) \
@@ -286,7 +286,7 @@ I_u3u1u2(_ldx)
286 286
287#ifdef CONFIG_CPU_CAVIUM_OCTEON 287#ifdef CONFIG_CPU_CAVIUM_OCTEON
288#include <asm/octeon/octeon.h> 288#include <asm/octeon/octeon.h>
289void __uasminit ISAFUNC(uasm_i_pref)(u32 **buf, unsigned int a, signed int b, 289void ISAFUNC(uasm_i_pref)(u32 **buf, unsigned int a, signed int b,
290 unsigned int c) 290 unsigned int c)
291{ 291{
292 if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_X) && a <= 24 && a != 5) 292 if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_X) && a <= 24 && a != 5)
@@ -304,7 +304,7 @@ I_u2s3u1(_pref)
304#endif 304#endif
305 305
306/* Handle labels. */ 306/* Handle labels. */
307void __uasminit ISAFUNC(uasm_build_label)(struct uasm_label **lab, u32 *addr, int lid) 307void ISAFUNC(uasm_build_label)(struct uasm_label **lab, u32 *addr, int lid)
308{ 308{
309 (*lab)->addr = addr; 309 (*lab)->addr = addr;
310 (*lab)->lab = lid; 310 (*lab)->lab = lid;
@@ -312,7 +312,7 @@ void __uasminit ISAFUNC(uasm_build_label)(struct uasm_label **lab, u32 *addr, in
312} 312}
313UASM_EXPORT_SYMBOL(ISAFUNC(uasm_build_label)); 313UASM_EXPORT_SYMBOL(ISAFUNC(uasm_build_label));
314 314
315int __uasminit ISAFUNC(uasm_in_compat_space_p)(long addr) 315int ISAFUNC(uasm_in_compat_space_p)(long addr)
316{ 316{
317 /* Is this address in 32bit compat space? */ 317 /* Is this address in 32bit compat space? */
318#ifdef CONFIG_64BIT 318#ifdef CONFIG_64BIT
@@ -323,7 +323,7 @@ int __uasminit ISAFUNC(uasm_in_compat_space_p)(long addr)
323} 323}
324UASM_EXPORT_SYMBOL(ISAFUNC(uasm_in_compat_space_p)); 324UASM_EXPORT_SYMBOL(ISAFUNC(uasm_in_compat_space_p));
325 325
326static int __uasminit uasm_rel_highest(long val) 326static int uasm_rel_highest(long val)
327{ 327{
328#ifdef CONFIG_64BIT 328#ifdef CONFIG_64BIT
329 return ((((val + 0x800080008000L) >> 48) & 0xffff) ^ 0x8000) - 0x8000; 329 return ((((val + 0x800080008000L) >> 48) & 0xffff) ^ 0x8000) - 0x8000;
@@ -332,7 +332,7 @@ static int __uasminit uasm_rel_highest(long val)
332#endif 332#endif
333} 333}
334 334
335static int __uasminit uasm_rel_higher(long val) 335static int uasm_rel_higher(long val)
336{ 336{
337#ifdef CONFIG_64BIT 337#ifdef CONFIG_64BIT
338 return ((((val + 0x80008000L) >> 32) & 0xffff) ^ 0x8000) - 0x8000; 338 return ((((val + 0x80008000L) >> 32) & 0xffff) ^ 0x8000) - 0x8000;
@@ -341,19 +341,19 @@ static int __uasminit uasm_rel_higher(long val)
341#endif 341#endif
342} 342}
343 343
344int __uasminit ISAFUNC(uasm_rel_hi)(long val) 344int ISAFUNC(uasm_rel_hi)(long val)
345{ 345{
346 return ((((val + 0x8000L) >> 16) & 0xffff) ^ 0x8000) - 0x8000; 346 return ((((val + 0x8000L) >> 16) & 0xffff) ^ 0x8000) - 0x8000;
347} 347}
348UASM_EXPORT_SYMBOL(ISAFUNC(uasm_rel_hi)); 348UASM_EXPORT_SYMBOL(ISAFUNC(uasm_rel_hi));
349 349
350int __uasminit ISAFUNC(uasm_rel_lo)(long val) 350int ISAFUNC(uasm_rel_lo)(long val)
351{ 351{
352 return ((val & 0xffff) ^ 0x8000) - 0x8000; 352 return ((val & 0xffff) ^ 0x8000) - 0x8000;
353} 353}
354UASM_EXPORT_SYMBOL(ISAFUNC(uasm_rel_lo)); 354UASM_EXPORT_SYMBOL(ISAFUNC(uasm_rel_lo));
355 355
356void __uasminit ISAFUNC(UASM_i_LA_mostly)(u32 **buf, unsigned int rs, long addr) 356void ISAFUNC(UASM_i_LA_mostly)(u32 **buf, unsigned int rs, long addr)
357{ 357{
358 if (!ISAFUNC(uasm_in_compat_space_p)(addr)) { 358 if (!ISAFUNC(uasm_in_compat_space_p)(addr)) {
359 ISAFUNC(uasm_i_lui)(buf, rs, uasm_rel_highest(addr)); 359 ISAFUNC(uasm_i_lui)(buf, rs, uasm_rel_highest(addr));
@@ -371,7 +371,7 @@ void __uasminit ISAFUNC(UASM_i_LA_mostly)(u32 **buf, unsigned int rs, long addr)
371} 371}
372UASM_EXPORT_SYMBOL(ISAFUNC(UASM_i_LA_mostly)); 372UASM_EXPORT_SYMBOL(ISAFUNC(UASM_i_LA_mostly));
373 373
374void __uasminit ISAFUNC(UASM_i_LA)(u32 **buf, unsigned int rs, long addr) 374void ISAFUNC(UASM_i_LA)(u32 **buf, unsigned int rs, long addr)
375{ 375{
376 ISAFUNC(UASM_i_LA_mostly)(buf, rs, addr); 376 ISAFUNC(UASM_i_LA_mostly)(buf, rs, addr);
377 if (ISAFUNC(uasm_rel_lo(addr))) { 377 if (ISAFUNC(uasm_rel_lo(addr))) {
@@ -386,8 +386,7 @@ void __uasminit ISAFUNC(UASM_i_LA)(u32 **buf, unsigned int rs, long addr)
386UASM_EXPORT_SYMBOL(ISAFUNC(UASM_i_LA)); 386UASM_EXPORT_SYMBOL(ISAFUNC(UASM_i_LA));
387 387
388/* Handle relocations. */ 388/* Handle relocations. */
389void __uasminit 389void ISAFUNC(uasm_r_mips_pc16)(struct uasm_reloc **rel, u32 *addr, int lid)
390ISAFUNC(uasm_r_mips_pc16)(struct uasm_reloc **rel, u32 *addr, int lid)
391{ 390{
392 (*rel)->addr = addr; 391 (*rel)->addr = addr;
393 (*rel)->type = R_MIPS_PC16; 392 (*rel)->type = R_MIPS_PC16;
@@ -396,11 +395,11 @@ ISAFUNC(uasm_r_mips_pc16)(struct uasm_reloc **rel, u32 *addr, int lid)
396} 395}
397UASM_EXPORT_SYMBOL(ISAFUNC(uasm_r_mips_pc16)); 396UASM_EXPORT_SYMBOL(ISAFUNC(uasm_r_mips_pc16));
398 397
399static inline void __uasminit 398static inline void __resolve_relocs(struct uasm_reloc *rel,
400__resolve_relocs(struct uasm_reloc *rel, struct uasm_label *lab); 399 struct uasm_label *lab);
401 400
402void __uasminit 401void ISAFUNC(uasm_resolve_relocs)(struct uasm_reloc *rel,
403ISAFUNC(uasm_resolve_relocs)(struct uasm_reloc *rel, struct uasm_label *lab) 402 struct uasm_label *lab)
404{ 403{
405 struct uasm_label *l; 404 struct uasm_label *l;
406 405
@@ -411,8 +410,8 @@ ISAFUNC(uasm_resolve_relocs)(struct uasm_reloc *rel, struct uasm_label *lab)
411} 410}
412UASM_EXPORT_SYMBOL(ISAFUNC(uasm_resolve_relocs)); 411UASM_EXPORT_SYMBOL(ISAFUNC(uasm_resolve_relocs));
413 412
414void __uasminit 413void ISAFUNC(uasm_move_relocs)(struct uasm_reloc *rel, u32 *first, u32 *end,
415ISAFUNC(uasm_move_relocs)(struct uasm_reloc *rel, u32 *first, u32 *end, long off) 414 long off)
416{ 415{
417 for (; rel->lab != UASM_LABEL_INVALID; rel++) 416 for (; rel->lab != UASM_LABEL_INVALID; rel++)
418 if (rel->addr >= first && rel->addr < end) 417 if (rel->addr >= first && rel->addr < end)
@@ -420,8 +419,8 @@ ISAFUNC(uasm_move_relocs)(struct uasm_reloc *rel, u32 *first, u32 *end, long off
420} 419}
421UASM_EXPORT_SYMBOL(ISAFUNC(uasm_move_relocs)); 420UASM_EXPORT_SYMBOL(ISAFUNC(uasm_move_relocs));
422 421
423void __uasminit 422void ISAFUNC(uasm_move_labels)(struct uasm_label *lab, u32 *first, u32 *end,
424ISAFUNC(uasm_move_labels)(struct uasm_label *lab, u32 *first, u32 *end, long off) 423 long off)
425{ 424{
426 for (; lab->lab != UASM_LABEL_INVALID; lab++) 425 for (; lab->lab != UASM_LABEL_INVALID; lab++)
427 if (lab->addr >= first && lab->addr < end) 426 if (lab->addr >= first && lab->addr < end)
@@ -429,9 +428,8 @@ ISAFUNC(uasm_move_labels)(struct uasm_label *lab, u32 *first, u32 *end, long off
429} 428}
430UASM_EXPORT_SYMBOL(ISAFUNC(uasm_move_labels)); 429UASM_EXPORT_SYMBOL(ISAFUNC(uasm_move_labels));
431 430
432void __uasminit 431void ISAFUNC(uasm_copy_handler)(struct uasm_reloc *rel, struct uasm_label *lab,
433ISAFUNC(uasm_copy_handler)(struct uasm_reloc *rel, struct uasm_label *lab, u32 *first, 432 u32 *first, u32 *end, u32 *target)
434 u32 *end, u32 *target)
435{ 433{
436 long off = (long)(target - first); 434 long off = (long)(target - first);
437 435
@@ -442,7 +440,7 @@ ISAFUNC(uasm_copy_handler)(struct uasm_reloc *rel, struct uasm_label *lab, u32 *
442} 440}
443UASM_EXPORT_SYMBOL(ISAFUNC(uasm_copy_handler)); 441UASM_EXPORT_SYMBOL(ISAFUNC(uasm_copy_handler));
444 442
445int __uasminit ISAFUNC(uasm_insn_has_bdelay)(struct uasm_reloc *rel, u32 *addr) 443int ISAFUNC(uasm_insn_has_bdelay)(struct uasm_reloc *rel, u32 *addr)
446{ 444{
447 for (; rel->lab != UASM_LABEL_INVALID; rel++) { 445 for (; rel->lab != UASM_LABEL_INVALID; rel++) {
448 if (rel->addr == addr 446 if (rel->addr == addr
@@ -456,83 +454,79 @@ int __uasminit ISAFUNC(uasm_insn_has_bdelay)(struct uasm_reloc *rel, u32 *addr)
456UASM_EXPORT_SYMBOL(ISAFUNC(uasm_insn_has_bdelay)); 454UASM_EXPORT_SYMBOL(ISAFUNC(uasm_insn_has_bdelay));
457 455
458/* Convenience functions for labeled branches. */ 456/* Convenience functions for labeled branches. */
459void __uasminit 457void ISAFUNC(uasm_il_bltz)(u32 **p, struct uasm_reloc **r, unsigned int reg,
460ISAFUNC(uasm_il_bltz)(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid) 458 int lid)
461{ 459{
462 uasm_r_mips_pc16(r, *p, lid); 460 uasm_r_mips_pc16(r, *p, lid);
463 ISAFUNC(uasm_i_bltz)(p, reg, 0); 461 ISAFUNC(uasm_i_bltz)(p, reg, 0);
464} 462}
465UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_bltz)); 463UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_bltz));
466 464
467void __uasminit 465void ISAFUNC(uasm_il_b)(u32 **p, struct uasm_reloc **r, int lid)
468ISAFUNC(uasm_il_b)(u32 **p, struct uasm_reloc **r, int lid)
469{ 466{
470 uasm_r_mips_pc16(r, *p, lid); 467 uasm_r_mips_pc16(r, *p, lid);
471 ISAFUNC(uasm_i_b)(p, 0); 468 ISAFUNC(uasm_i_b)(p, 0);
472} 469}
473UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_b)); 470UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_b));
474 471
475void __uasminit 472void ISAFUNC(uasm_il_beqz)(u32 **p, struct uasm_reloc **r, unsigned int reg,
476ISAFUNC(uasm_il_beqz)(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid) 473 int lid)
477{ 474{
478 uasm_r_mips_pc16(r, *p, lid); 475 uasm_r_mips_pc16(r, *p, lid);
479 ISAFUNC(uasm_i_beqz)(p, reg, 0); 476 ISAFUNC(uasm_i_beqz)(p, reg, 0);
480} 477}
481UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_beqz)); 478UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_beqz));
482 479
483void __uasminit 480void ISAFUNC(uasm_il_beqzl)(u32 **p, struct uasm_reloc **r, unsigned int reg,
484ISAFUNC(uasm_il_beqzl)(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid) 481 int lid)
485{ 482{
486 uasm_r_mips_pc16(r, *p, lid); 483 uasm_r_mips_pc16(r, *p, lid);
487 ISAFUNC(uasm_i_beqzl)(p, reg, 0); 484 ISAFUNC(uasm_i_beqzl)(p, reg, 0);
488} 485}
489UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_beqzl)); 486UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_beqzl));
490 487
491void __uasminit 488void ISAFUNC(uasm_il_bne)(u32 **p, struct uasm_reloc **r, unsigned int reg1,
492ISAFUNC(uasm_il_bne)(u32 **p, struct uasm_reloc **r, unsigned int reg1, 489 unsigned int reg2, int lid)
493 unsigned int reg2, int lid)
494{ 490{
495 uasm_r_mips_pc16(r, *p, lid); 491 uasm_r_mips_pc16(r, *p, lid);
496 ISAFUNC(uasm_i_bne)(p, reg1, reg2, 0); 492 ISAFUNC(uasm_i_bne)(p, reg1, reg2, 0);
497} 493}
498UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_bne)); 494UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_bne));
499 495
500void __uasminit 496void ISAFUNC(uasm_il_bnez)(u32 **p, struct uasm_reloc **r, unsigned int reg,
501ISAFUNC(uasm_il_bnez)(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid) 497 int lid)
502{ 498{
503 uasm_r_mips_pc16(r, *p, lid); 499 uasm_r_mips_pc16(r, *p, lid);
504 ISAFUNC(uasm_i_bnez)(p, reg, 0); 500 ISAFUNC(uasm_i_bnez)(p, reg, 0);
505} 501}
506UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_bnez)); 502UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_bnez));
507 503
508void __uasminit 504void ISAFUNC(uasm_il_bgezl)(u32 **p, struct uasm_reloc **r, unsigned int reg,
509ISAFUNC(uasm_il_bgezl)(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid) 505 int lid)
510{ 506{
511 uasm_r_mips_pc16(r, *p, lid); 507 uasm_r_mips_pc16(r, *p, lid);
512 ISAFUNC(uasm_i_bgezl)(p, reg, 0); 508 ISAFUNC(uasm_i_bgezl)(p, reg, 0);
513} 509}
514UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_bgezl)); 510UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_bgezl));
515 511
516void __uasminit 512void ISAFUNC(uasm_il_bgez)(u32 **p, struct uasm_reloc **r, unsigned int reg,
517ISAFUNC(uasm_il_bgez)(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid) 513 int lid)
518{ 514{
519 uasm_r_mips_pc16(r, *p, lid); 515 uasm_r_mips_pc16(r, *p, lid);
520 ISAFUNC(uasm_i_bgez)(p, reg, 0); 516 ISAFUNC(uasm_i_bgez)(p, reg, 0);
521} 517}
522UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_bgez)); 518UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_bgez));
523 519
524void __uasminit 520void ISAFUNC(uasm_il_bbit0)(u32 **p, struct uasm_reloc **r, unsigned int reg,
525ISAFUNC(uasm_il_bbit0)(u32 **p, struct uasm_reloc **r, unsigned int reg, 521 unsigned int bit, int lid)
526 unsigned int bit, int lid)
527{ 522{
528 uasm_r_mips_pc16(r, *p, lid); 523 uasm_r_mips_pc16(r, *p, lid);
529 ISAFUNC(uasm_i_bbit0)(p, reg, bit, 0); 524 ISAFUNC(uasm_i_bbit0)(p, reg, bit, 0);
530} 525}
531UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_bbit0)); 526UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_bbit0));
532 527
533void __uasminit 528void ISAFUNC(uasm_il_bbit1)(u32 **p, struct uasm_reloc **r, unsigned int reg,
534ISAFUNC(uasm_il_bbit1)(u32 **p, struct uasm_reloc **r, unsigned int reg, 529 unsigned int bit, int lid)
535 unsigned int bit, int lid)
536{ 530{
537 uasm_r_mips_pc16(r, *p, lid); 531 uasm_r_mips_pc16(r, *p, lid);
538 ISAFUNC(uasm_i_bbit1)(p, reg, bit, 0); 532 ISAFUNC(uasm_i_bbit1)(p, reg, bit, 0);
diff --git a/arch/mips/mti-malta/malta-smtc.c b/arch/mips/mti-malta/malta-smtc.c
index becbf47506a5..c4849904f013 100644
--- a/arch/mips/mti-malta/malta-smtc.c
+++ b/arch/mips/mti-malta/malta-smtc.c
@@ -32,7 +32,7 @@ static void msmtc_send_ipi_mask(const struct cpumask *mask, unsigned int action)
32/* 32/*
33 * Post-config but pre-boot cleanup entry point 33 * Post-config but pre-boot cleanup entry point
34 */ 34 */
35static void __cpuinit msmtc_init_secondary(void) 35static void msmtc_init_secondary(void)
36{ 36{
37 int myvpe; 37 int myvpe;
38 38
@@ -53,7 +53,7 @@ static void __cpuinit msmtc_init_secondary(void)
53/* 53/*
54 * Platform "CPU" startup hook 54 * Platform "CPU" startup hook
55 */ 55 */
56static void __cpuinit msmtc_boot_secondary(int cpu, struct task_struct *idle) 56static void msmtc_boot_secondary(int cpu, struct task_struct *idle)
57{ 57{
58 smtc_boot_secondary(cpu, idle); 58 smtc_boot_secondary(cpu, idle);
59} 59}
@@ -61,7 +61,7 @@ static void __cpuinit msmtc_boot_secondary(int cpu, struct task_struct *idle)
61/* 61/*
62 * SMP initialization finalization entry point 62 * SMP initialization finalization entry point
63 */ 63 */
64static void __cpuinit msmtc_smp_finish(void) 64static void msmtc_smp_finish(void)
65{ 65{
66 smtc_smp_finish(); 66 smtc_smp_finish();
67} 67}
diff --git a/arch/mips/mti-malta/malta-time.c b/arch/mips/mti-malta/malta-time.c
index 0ad305f75802..53aad4a35375 100644
--- a/arch/mips/mti-malta/malta-time.c
+++ b/arch/mips/mti-malta/malta-time.c
@@ -150,7 +150,7 @@ static void __init plat_perf_setup(void)
150 } 150 }
151} 151}
152 152
153unsigned int __cpuinit get_c0_compare_int(void) 153unsigned int get_c0_compare_int(void)
154{ 154{
155#ifdef MSC01E_INT_BASE 155#ifdef MSC01E_INT_BASE
156 if (cpu_has_veic) { 156 if (cpu_has_veic) {
diff --git a/arch/mips/mti-sead3/sead3-time.c b/arch/mips/mti-sead3/sead3-time.c
index 96b42eb9b5e2..a43ea3cc0a3b 100644
--- a/arch/mips/mti-sead3/sead3-time.c
+++ b/arch/mips/mti-sead3/sead3-time.c
@@ -91,7 +91,7 @@ static void __init plat_perf_setup(void)
91 } 91 }
92} 92}
93 93
94unsigned int __cpuinit get_c0_compare_int(void) 94unsigned int get_c0_compare_int(void)
95{ 95{
96 if (cpu_has_vint) 96 if (cpu_has_vint)
97 set_vi_handler(cp0_compare_irq, mips_timer_dispatch); 97 set_vi_handler(cp0_compare_irq, mips_timer_dispatch);
diff --git a/arch/mips/netlogic/common/smp.c b/arch/mips/netlogic/common/smp.c
index 885d293b61da..4e35d9c453e2 100644
--- a/arch/mips/netlogic/common/smp.c
+++ b/arch/mips/netlogic/common/smp.c
@@ -116,7 +116,7 @@ void nlm_early_init_secondary(int cpu)
116/* 116/*
117 * Code to run on secondary just after probing the CPU 117 * Code to run on secondary just after probing the CPU
118 */ 118 */
119static void __cpuinit nlm_init_secondary(void) 119static void nlm_init_secondary(void)
120{ 120{
121 int hwtid; 121 int hwtid;
122 122
@@ -252,7 +252,7 @@ unsupp:
252 return 0; 252 return 0;
253} 253}
254 254
255int __cpuinit nlm_wakeup_secondary_cpus(void) 255int nlm_wakeup_secondary_cpus(void)
256{ 256{
257 u32 *reset_data; 257 u32 *reset_data;
258 int threadmode; 258 int threadmode;
diff --git a/arch/mips/netlogic/common/smpboot.S b/arch/mips/netlogic/common/smpboot.S
index 528c46c5a170..aa6cff0a229b 100644
--- a/arch/mips/netlogic/common/smpboot.S
+++ b/arch/mips/netlogic/common/smpboot.S
@@ -70,7 +70,6 @@ FEXPORT(xlp_boot_core0_siblings) /* "Master" cpu starts from here */
70 nop 70 nop
71 /* not reached */ 71 /* not reached */
72 72
73 __CPUINIT
74NESTED(nlm_boot_secondary_cpus, 16, sp) 73NESTED(nlm_boot_secondary_cpus, 16, sp)
75 /* Initialize CP0 Status */ 74 /* Initialize CP0 Status */
76 move t1, zero 75 move t1, zero
@@ -94,7 +93,6 @@ NESTED(nlm_boot_secondary_cpus, 16, sp)
94 jr t0 93 jr t0
95 nop 94 nop
96END(nlm_boot_secondary_cpus) 95END(nlm_boot_secondary_cpus)
97 __FINIT
98 96
99/* 97/*
100 * In case of RMIboot bootloader which is used on XLR boards, the CPUs 98 * In case of RMIboot bootloader which is used on XLR boards, the CPUs
@@ -102,7 +100,6 @@ END(nlm_boot_secondary_cpus)
102 * This will get them out of the bootloader code and into linux. Needed 100 * This will get them out of the bootloader code and into linux. Needed
103 * because the bootloader area will be taken and initialized by linux. 101 * because the bootloader area will be taken and initialized by linux.
104 */ 102 */
105 __CPUINIT
106NESTED(nlm_rmiboot_preboot, 16, sp) 103NESTED(nlm_rmiboot_preboot, 16, sp)
107 mfc0 t0, $15, 1 /* read ebase */ 104 mfc0 t0, $15, 1 /* read ebase */
108 andi t0, 0x1f /* t0 has the processor_id() */ 105 andi t0, 0x1f /* t0 has the processor_id() */
@@ -140,4 +137,3 @@ NESTED(nlm_rmiboot_preboot, 16, sp)
140 b 1b 137 b 1b
141 nop 138 nop
142END(nlm_rmiboot_preboot) 139END(nlm_rmiboot_preboot)
143 __FINIT
diff --git a/arch/mips/netlogic/common/time.c b/arch/mips/netlogic/common/time.c
index 5c56555380bb..045a396c57ce 100644
--- a/arch/mips/netlogic/common/time.c
+++ b/arch/mips/netlogic/common/time.c
@@ -54,7 +54,7 @@
54#error "Unknown CPU" 54#error "Unknown CPU"
55#endif 55#endif
56 56
57unsigned int __cpuinit get_c0_compare_int(void) 57unsigned int get_c0_compare_int(void)
58{ 58{
59 return IRQ_TIMER; 59 return IRQ_TIMER;
60} 60}
diff --git a/arch/mips/netlogic/xlr/wakeup.c b/arch/mips/netlogic/xlr/wakeup.c
index c06e4c9f0478..9fb81fa6272a 100644
--- a/arch/mips/netlogic/xlr/wakeup.c
+++ b/arch/mips/netlogic/xlr/wakeup.c
@@ -49,7 +49,7 @@
49#include <asm/netlogic/xlr/iomap.h> 49#include <asm/netlogic/xlr/iomap.h>
50#include <asm/netlogic/xlr/pic.h> 50#include <asm/netlogic/xlr/pic.h>
51 51
52int __cpuinit xlr_wakeup_secondary_cpus(void) 52int xlr_wakeup_secondary_cpus(void)
53{ 53{
54 struct nlm_soc_info *nodep; 54 struct nlm_soc_info *nodep;
55 unsigned int i, j, boot_cpu; 55 unsigned int i, j, boot_cpu;
diff --git a/arch/mips/pci/pci-ip27.c b/arch/mips/pci/pci-ip27.c
index 7b2ac81e1f59..162b4cb29dba 100644
--- a/arch/mips/pci/pci-ip27.c
+++ b/arch/mips/pci/pci-ip27.c
@@ -42,7 +42,7 @@ int irq_to_slot[MAX_PCI_BUSSES * MAX_DEVICES_PER_PCIBUS];
42 42
43extern struct pci_ops bridge_pci_ops; 43extern struct pci_ops bridge_pci_ops;
44 44
45int __cpuinit bridge_probe(nasid_t nasid, int widget_id, int masterwid) 45int bridge_probe(nasid_t nasid, int widget_id, int masterwid)
46{ 46{
47 unsigned long offset = NODE_OFFSET(nasid); 47 unsigned long offset = NODE_OFFSET(nasid);
48 struct bridge_controller *bc; 48 struct bridge_controller *bc;
diff --git a/arch/mips/pmcs-msp71xx/msp_smtc.c b/arch/mips/pmcs-msp71xx/msp_smtc.c
index c8dcc1c01e18..6b5607fce279 100644
--- a/arch/mips/pmcs-msp71xx/msp_smtc.c
+++ b/arch/mips/pmcs-msp71xx/msp_smtc.c
@@ -33,7 +33,7 @@ static void msp_smtc_send_ipi_mask(const struct cpumask *mask,
33/* 33/*
34 * Post-config but pre-boot cleanup entry point 34 * Post-config but pre-boot cleanup entry point
35 */ 35 */
36static void __cpuinit msp_smtc_init_secondary(void) 36static void msp_smtc_init_secondary(void)
37{ 37{
38 int myvpe; 38 int myvpe;
39 39
@@ -48,8 +48,7 @@ static void __cpuinit msp_smtc_init_secondary(void)
48/* 48/*
49 * Platform "CPU" startup hook 49 * Platform "CPU" startup hook
50 */ 50 */
51static void __cpuinit msp_smtc_boot_secondary(int cpu, 51static void msp_smtc_boot_secondary(int cpu, struct task_struct *idle)
52 struct task_struct *idle)
53{ 52{
54 smtc_boot_secondary(cpu, idle); 53 smtc_boot_secondary(cpu, idle);
55} 54}
@@ -57,7 +56,7 @@ static void __cpuinit msp_smtc_boot_secondary(int cpu,
57/* 56/*
58 * SMP initialization finalization entry point 57 * SMP initialization finalization entry point
59 */ 58 */
60static void __cpuinit msp_smtc_smp_finish(void) 59static void msp_smtc_smp_finish(void)
61{ 60{
62 smtc_smp_finish(); 61 smtc_smp_finish();
63} 62}
diff --git a/arch/mips/pmcs-msp71xx/msp_time.c b/arch/mips/pmcs-msp71xx/msp_time.c
index 8f12ecc55ace..fea917be0ff1 100644
--- a/arch/mips/pmcs-msp71xx/msp_time.c
+++ b/arch/mips/pmcs-msp71xx/msp_time.c
@@ -88,7 +88,7 @@ void __init plat_time_init(void)
88 mips_hpt_frequency = cpu_rate/2; 88 mips_hpt_frequency = cpu_rate/2;
89} 89}
90 90
91unsigned int __cpuinit get_c0_compare_int(void) 91unsigned int get_c0_compare_int(void)
92{ 92{
93 /* MIPS_MT modes may want timer for second VPE */ 93 /* MIPS_MT modes may want timer for second VPE */
94 if ((get_current_vpe()) && !tim_installed) { 94 if ((get_current_vpe()) && !tim_installed) {
diff --git a/arch/mips/pnx833x/common/interrupts.c b/arch/mips/pnx833x/common/interrupts.c
index a4a90596c0ad..e460865873c1 100644
--- a/arch/mips/pnx833x/common/interrupts.c
+++ b/arch/mips/pnx833x/common/interrupts.c
@@ -281,7 +281,7 @@ void __init arch_init_irq(void)
281 write_c0_status(read_c0_status() | IE_IRQ2); 281 write_c0_status(read_c0_status() | IE_IRQ2);
282} 282}
283 283
284unsigned int __cpuinit get_c0_compare_int(void) 284unsigned int get_c0_compare_int(void)
285{ 285{
286 if (cpu_has_vint) 286 if (cpu_has_vint)
287 set_vi_handler(cp0_compare_irq, pnx833x_timer_dispatch); 287 set_vi_handler(cp0_compare_irq, pnx833x_timer_dispatch);
diff --git a/arch/mips/powertv/time.c b/arch/mips/powertv/time.c
index 9fd7b67f2af7..f38b0d45eca9 100644
--- a/arch/mips/powertv/time.c
+++ b/arch/mips/powertv/time.c
@@ -25,7 +25,7 @@
25 25
26#include "powertv-clock.h" 26#include "powertv-clock.h"
27 27
28unsigned int __cpuinit get_c0_compare_int(void) 28unsigned int get_c0_compare_int(void)
29{ 29{
30 return irq_mips_timer; 30 return irq_mips_timer;
31} 31}
diff --git a/arch/mips/ralink/irq.c b/arch/mips/ralink/irq.c
index 320b1f1043ff..781b3d14a489 100644
--- a/arch/mips/ralink/irq.c
+++ b/arch/mips/ralink/irq.c
@@ -73,7 +73,7 @@ static struct irq_chip ralink_intc_irq_chip = {
73 .irq_mask_ack = ralink_intc_irq_mask, 73 .irq_mask_ack = ralink_intc_irq_mask,
74}; 74};
75 75
76unsigned int __cpuinit get_c0_compare_int(void) 76unsigned int get_c0_compare_int(void)
77{ 77{
78 return CP0_LEGACY_COMPARE_IRQ; 78 return CP0_LEGACY_COMPARE_IRQ;
79} 79}
diff --git a/arch/mips/sgi-ip27/ip27-init.c b/arch/mips/sgi-ip27/ip27-init.c
index d41b1c6fb032..ee736bd103f8 100644
--- a/arch/mips/sgi-ip27/ip27-init.c
+++ b/arch/mips/sgi-ip27/ip27-init.c
@@ -54,7 +54,7 @@ extern void pcibr_setup(cnodeid_t);
54 54
55extern void xtalk_probe_node(cnodeid_t nid); 55extern void xtalk_probe_node(cnodeid_t nid);
56 56
57static void __cpuinit per_hub_init(cnodeid_t cnode) 57static void per_hub_init(cnodeid_t cnode)
58{ 58{
59 struct hub_data *hub = hub_data(cnode); 59 struct hub_data *hub = hub_data(cnode);
60 nasid_t nasid = COMPACT_TO_NASID_NODEID(cnode); 60 nasid_t nasid = COMPACT_TO_NASID_NODEID(cnode);
@@ -110,7 +110,7 @@ static void __cpuinit per_hub_init(cnodeid_t cnode)
110 } 110 }
111} 111}
112 112
113void __cpuinit per_cpu_init(void) 113void per_cpu_init(void)
114{ 114{
115 int cpu = smp_processor_id(); 115 int cpu = smp_processor_id();
116 int slice = LOCAL_HUB_L(PI_CPU_NUM); 116 int slice = LOCAL_HUB_L(PI_CPU_NUM);
diff --git a/arch/mips/sgi-ip27/ip27-smp.c b/arch/mips/sgi-ip27/ip27-smp.c
index f94638141b20..f4ea8aa79ba2 100644
--- a/arch/mips/sgi-ip27/ip27-smp.c
+++ b/arch/mips/sgi-ip27/ip27-smp.c
@@ -173,12 +173,12 @@ static void ip27_send_ipi_mask(const struct cpumask *mask, unsigned int action)
173 ip27_send_ipi_single(i, action); 173 ip27_send_ipi_single(i, action);
174} 174}
175 175
176static void __cpuinit ip27_init_secondary(void) 176static void ip27_init_secondary(void)
177{ 177{
178 per_cpu_init(); 178 per_cpu_init();
179} 179}
180 180
181static void __cpuinit ip27_smp_finish(void) 181static void ip27_smp_finish(void)
182{ 182{
183 extern void hub_rt_clock_event_init(void); 183 extern void hub_rt_clock_event_init(void);
184 184
@@ -195,7 +195,7 @@ static void __init ip27_cpus_done(void)
195 * set sp to the kernel stack of the newly created idle process, gp to the proc 195 * set sp to the kernel stack of the newly created idle process, gp to the proc
196 * struct so that current_thread_info() will work. 196 * struct so that current_thread_info() will work.
197 */ 197 */
198static void __cpuinit ip27_boot_secondary(int cpu, struct task_struct *idle) 198static void ip27_boot_secondary(int cpu, struct task_struct *idle)
199{ 199{
200 unsigned long gp = (unsigned long)task_thread_info(idle); 200 unsigned long gp = (unsigned long)task_thread_info(idle);
201 unsigned long sp = __KSTK_TOS(idle); 201 unsigned long sp = __KSTK_TOS(idle);
diff --git a/arch/mips/sgi-ip27/ip27-timer.c b/arch/mips/sgi-ip27/ip27-timer.c
index 2e21b761cb9c..1d97eaba0c5f 100644
--- a/arch/mips/sgi-ip27/ip27-timer.c
+++ b/arch/mips/sgi-ip27/ip27-timer.c
@@ -106,7 +106,7 @@ struct irqaction hub_rt_irqaction = {
106#define NSEC_PER_CYCLE 800 106#define NSEC_PER_CYCLE 800
107#define CYCLES_PER_SEC (NSEC_PER_SEC / NSEC_PER_CYCLE) 107#define CYCLES_PER_SEC (NSEC_PER_SEC / NSEC_PER_CYCLE)
108 108
109void __cpuinit hub_rt_clock_event_init(void) 109void hub_rt_clock_event_init(void)
110{ 110{
111 unsigned int cpu = smp_processor_id(); 111 unsigned int cpu = smp_processor_id();
112 struct clock_event_device *cd = &per_cpu(hub_rt_clockevent, cpu); 112 struct clock_event_device *cd = &per_cpu(hub_rt_clockevent, cpu);
@@ -173,7 +173,7 @@ void __init plat_time_init(void)
173 hub_rt_clock_event_init(); 173 hub_rt_clock_event_init();
174} 174}
175 175
176void __cpuinit cpu_time_init(void) 176void cpu_time_init(void)
177{ 177{
178 lboard_t *board; 178 lboard_t *board;
179 klcpu_t *cpu; 179 klcpu_t *cpu;
@@ -194,7 +194,7 @@ void __cpuinit cpu_time_init(void)
194 set_c0_status(SRB_TIMOCLK); 194 set_c0_status(SRB_TIMOCLK);
195} 195}
196 196
197void __cpuinit hub_rtc_init(cnodeid_t cnode) 197void hub_rtc_init(cnodeid_t cnode)
198{ 198{
199 199
200 /* 200 /*
diff --git a/arch/mips/sgi-ip27/ip27-xtalk.c b/arch/mips/sgi-ip27/ip27-xtalk.c
index a4df7d0f6f12..d59b820f528d 100644
--- a/arch/mips/sgi-ip27/ip27-xtalk.c
+++ b/arch/mips/sgi-ip27/ip27-xtalk.c
@@ -23,7 +23,7 @@
23 23
24extern int bridge_probe(nasid_t nasid, int widget, int masterwid); 24extern int bridge_probe(nasid_t nasid, int widget, int masterwid);
25 25
26static int __cpuinit probe_one_port(nasid_t nasid, int widget, int masterwid) 26static int probe_one_port(nasid_t nasid, int widget, int masterwid)
27{ 27{
28 widgetreg_t widget_id; 28 widgetreg_t widget_id;
29 xwidget_part_num_t partnum; 29 xwidget_part_num_t partnum;
@@ -47,7 +47,7 @@ static int __cpuinit probe_one_port(nasid_t nasid, int widget, int masterwid)
47 return 0; 47 return 0;
48} 48}
49 49
50static int __cpuinit xbow_probe(nasid_t nasid) 50static int xbow_probe(nasid_t nasid)
51{ 51{
52 lboard_t *brd; 52 lboard_t *brd;
53 klxbow_t *xbow_p; 53 klxbow_t *xbow_p;
@@ -100,7 +100,7 @@ static int __cpuinit xbow_probe(nasid_t nasid)
100 return 0; 100 return 0;
101} 101}
102 102
103void __cpuinit xtalk_probe_node(cnodeid_t nid) 103void xtalk_probe_node(cnodeid_t nid)
104{ 104{
105 volatile u64 hubreg; 105 volatile u64 hubreg;
106 nasid_t nasid; 106 nasid_t nasid;
diff --git a/arch/mips/sibyte/bcm1480/smp.c b/arch/mips/sibyte/bcm1480/smp.c
index de88e22694a0..54e2c4de15c1 100644
--- a/arch/mips/sibyte/bcm1480/smp.c
+++ b/arch/mips/sibyte/bcm1480/smp.c
@@ -60,7 +60,7 @@ static void *mailbox_0_regs[] = {
60/* 60/*
61 * SMP init and finish on secondary CPUs 61 * SMP init and finish on secondary CPUs
62 */ 62 */
63void __cpuinit bcm1480_smp_init(void) 63void bcm1480_smp_init(void)
64{ 64{
65 unsigned int imask = STATUSF_IP4 | STATUSF_IP3 | STATUSF_IP2 | 65 unsigned int imask = STATUSF_IP4 | STATUSF_IP3 | STATUSF_IP2 |
66 STATUSF_IP1 | STATUSF_IP0; 66 STATUSF_IP1 | STATUSF_IP0;
@@ -95,7 +95,7 @@ static void bcm1480_send_ipi_mask(const struct cpumask *mask,
95/* 95/*
96 * Code to run on secondary just after probing the CPU 96 * Code to run on secondary just after probing the CPU
97 */ 97 */
98static void __cpuinit bcm1480_init_secondary(void) 98static void bcm1480_init_secondary(void)
99{ 99{
100 extern void bcm1480_smp_init(void); 100 extern void bcm1480_smp_init(void);
101 101
@@ -106,7 +106,7 @@ static void __cpuinit bcm1480_init_secondary(void)
106 * Do any tidying up before marking online and running the idle 106 * Do any tidying up before marking online and running the idle
107 * loop 107 * loop
108 */ 108 */
109static void __cpuinit bcm1480_smp_finish(void) 109static void bcm1480_smp_finish(void)
110{ 110{
111 extern void sb1480_clockevent_init(void); 111 extern void sb1480_clockevent_init(void);
112 112
@@ -125,7 +125,7 @@ static void bcm1480_cpus_done(void)
125 * Setup the PC, SP, and GP of a secondary processor and start it 125 * Setup the PC, SP, and GP of a secondary processor and start it
126 * running! 126 * running!
127 */ 127 */
128static void __cpuinit bcm1480_boot_secondary(int cpu, struct task_struct *idle) 128static void bcm1480_boot_secondary(int cpu, struct task_struct *idle)
129{ 129{
130 int retval; 130 int retval;
131 131
diff --git a/arch/mips/sibyte/sb1250/smp.c b/arch/mips/sibyte/sb1250/smp.c
index 285cfef4ebc0..d7b942db0ea5 100644
--- a/arch/mips/sibyte/sb1250/smp.c
+++ b/arch/mips/sibyte/sb1250/smp.c
@@ -48,7 +48,7 @@ static void *mailbox_regs[] = {
48/* 48/*
49 * SMP init and finish on secondary CPUs 49 * SMP init and finish on secondary CPUs
50 */ 50 */
51void __cpuinit sb1250_smp_init(void) 51void sb1250_smp_init(void)
52{ 52{
53 unsigned int imask = STATUSF_IP4 | STATUSF_IP3 | STATUSF_IP2 | 53 unsigned int imask = STATUSF_IP4 | STATUSF_IP3 | STATUSF_IP2 |
54 STATUSF_IP1 | STATUSF_IP0; 54 STATUSF_IP1 | STATUSF_IP0;
@@ -83,7 +83,7 @@ static inline void sb1250_send_ipi_mask(const struct cpumask *mask,
83/* 83/*
84 * Code to run on secondary just after probing the CPU 84 * Code to run on secondary just after probing the CPU
85 */ 85 */
86static void __cpuinit sb1250_init_secondary(void) 86static void sb1250_init_secondary(void)
87{ 87{
88 extern void sb1250_smp_init(void); 88 extern void sb1250_smp_init(void);
89 89
@@ -94,7 +94,7 @@ static void __cpuinit sb1250_init_secondary(void)
94 * Do any tidying up before marking online and running the idle 94 * Do any tidying up before marking online and running the idle
95 * loop 95 * loop
96 */ 96 */
97static void __cpuinit sb1250_smp_finish(void) 97static void sb1250_smp_finish(void)
98{ 98{
99 extern void sb1250_clockevent_init(void); 99 extern void sb1250_clockevent_init(void);
100 100
@@ -113,7 +113,7 @@ static void sb1250_cpus_done(void)
113 * Setup the PC, SP, and GP of a secondary processor and start it 113 * Setup the PC, SP, and GP of a secondary processor and start it
114 * running! 114 * running!
115 */ 115 */
116static void __cpuinit sb1250_boot_secondary(int cpu, struct task_struct *idle) 116static void sb1250_boot_secondary(int cpu, struct task_struct *idle)
117{ 117{
118 int retval; 118 int retval;
119 119
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-28 10:05:23 -0500