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authorRalf Baechle <ralf@linux-mips.org>2005-10-01 08:06:32 -0400
committerRalf Baechle <ralf@linux-mips.org>2005-10-29 14:32:32 -0400
commit02cf2119684e52e97a8a90bd7630386e0f1a250a (patch)
treefbe051feacc403d7703bf27043ac048b5d2f2369 /arch
parent942d042d17c77febab9af6815b2e77f665d0f9c1 (diff)
Cleanup the mess in cpu_cache_init.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch')
-rw-r--r--arch/mips/kernel/cpu-probe.c25
-rw-r--r--arch/mips/mm/c-r3k.c2
-rw-r--r--arch/mips/mm/c-r4k.c2
-rw-r--r--arch/mips/mm/c-sb1.c2
-rw-r--r--arch/mips/mm/c-tx39.c2
-rw-r--r--arch/mips/mm/cache.c90
6 files changed, 62 insertions, 61 deletions
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index 5d71eca41575..8e6427a50916 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -191,7 +191,7 @@ static inline int __cpu_has_fpu(void)
191 return ((cpu_get_fpu_id() & 0xff00) != FPIR_IMP_NONE); 191 return ((cpu_get_fpu_id() & 0xff00) != FPIR_IMP_NONE);
192} 192}
193 193
194#define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4KTLB \ 194#define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \
195 | MIPS_CPU_COUNTER) 195 | MIPS_CPU_COUNTER)
196 196
197static inline void cpu_probe_legacy(struct cpuinfo_mips *c) 197static inline void cpu_probe_legacy(struct cpuinfo_mips *c)
@@ -200,7 +200,8 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c)
200 case PRID_IMP_R2000: 200 case PRID_IMP_R2000:
201 c->cputype = CPU_R2000; 201 c->cputype = CPU_R2000;
202 c->isa_level = MIPS_CPU_ISA_I; 202 c->isa_level = MIPS_CPU_ISA_I;
203 c->options = MIPS_CPU_TLB | MIPS_CPU_NOFPUEX; 203 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
204 MIPS_CPU_NOFPUEX;
204 if (__cpu_has_fpu()) 205 if (__cpu_has_fpu())
205 c->options |= MIPS_CPU_FPU; 206 c->options |= MIPS_CPU_FPU;
206 c->tlbsize = 64; 207 c->tlbsize = 64;
@@ -214,7 +215,8 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c)
214 else 215 else
215 c->cputype = CPU_R3000; 216 c->cputype = CPU_R3000;
216 c->isa_level = MIPS_CPU_ISA_I; 217 c->isa_level = MIPS_CPU_ISA_I;
217 c->options = MIPS_CPU_TLB | MIPS_CPU_NOFPUEX; 218 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
219 MIPS_CPU_NOFPUEX;
218 if (__cpu_has_fpu()) 220 if (__cpu_has_fpu())
219 c->options |= MIPS_CPU_FPU; 221 c->options |= MIPS_CPU_FPU;
220 c->tlbsize = 64; 222 c->tlbsize = 64;
@@ -297,7 +299,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c)
297 #endif 299 #endif
298 case PRID_IMP_TX39: 300 case PRID_IMP_TX39:
299 c->isa_level = MIPS_CPU_ISA_I; 301 c->isa_level = MIPS_CPU_ISA_I;
300 c->options = MIPS_CPU_TLB; 302 c->options = MIPS_CPU_TLB | MIPS_CPU_TX39_CACHE;
301 303
302 if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) { 304 if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) {
303 c->cputype = CPU_TX3927; 305 c->cputype = CPU_TX3927;
@@ -441,7 +443,7 @@ static inline unsigned int decode_config0(struct cpuinfo_mips *c)
441 config0 = read_c0_config(); 443 config0 = read_c0_config();
442 444
443 if (((config0 & MIPS_CONF_MT) >> 7) == 1) 445 if (((config0 & MIPS_CONF_MT) >> 7) == 1)
444 c->options |= MIPS_CPU_TLB | MIPS_CPU_4KTLB; 446 c->options |= MIPS_CPU_TLB;
445 isa = (config0 & MIPS_CONF_AT) >> 13; 447 isa = (config0 & MIPS_CONF_AT) >> 13;
446 switch (isa) { 448 switch (isa) {
447 case 0: 449 case 0:
@@ -516,8 +518,8 @@ static inline unsigned int decode_config3(struct cpuinfo_mips *c)
516static inline void decode_configs(struct cpuinfo_mips *c) 518static inline void decode_configs(struct cpuinfo_mips *c)
517{ 519{
518 /* MIPS32 or MIPS64 compliant CPU. */ 520 /* MIPS32 or MIPS64 compliant CPU. */
519 c->options = MIPS_CPU_4KEX | MIPS_CPU_COUNTER | MIPS_CPU_DIVEC | 521 c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER |
520 MIPS_CPU_LLSC | MIPS_CPU_MCHECK; 522 MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK;
521 523
522 c->scache.flags = MIPS_CACHE_NOT_PRESENT; 524 c->scache.flags = MIPS_CACHE_NOT_PRESENT;
523 525
@@ -603,6 +605,15 @@ static inline void cpu_probe_alchemy(struct cpuinfo_mips *c)
603static inline void cpu_probe_sibyte(struct cpuinfo_mips *c) 605static inline void cpu_probe_sibyte(struct cpuinfo_mips *c)
604{ 606{
605 decode_configs(c); 607 decode_configs(c);
608
609 /*
610 * For historical reasons the SB1 comes with it's own variant of
611 * cache code which eventually will be folded into c-r4k.c. Until
612 * then we pretend it's got it's own cache architecture.
613 */
614 c->options &= MIPS_CPU_4K_CACHE;
615 c->options |= MIPS_CPU_SB1_CACHE;
616
606 switch (c->processor_id & 0xff00) { 617 switch (c->processor_id & 0xff00) {
607 case PRID_IMP_SB1: 618 case PRID_IMP_SB1:
608 c->cputype = CPU_SB1; 619 c->cputype = CPU_SB1;
diff --git a/arch/mips/mm/c-r3k.c b/arch/mips/mm/c-r3k.c
index 03492a5c21f1..27f4fa25e8c9 100644
--- a/arch/mips/mm/c-r3k.c
+++ b/arch/mips/mm/c-r3k.c
@@ -319,7 +319,7 @@ static void r3k_dma_cache_wback_inv(unsigned long start, unsigned long size)
319 r3k_flush_dcache_range(start, start + size); 319 r3k_flush_dcache_range(start, start + size);
320} 320}
321 321
322void __init ld_mmu_r23000(void) 322void __init r3k_cache_init(void)
323{ 323{
324 extern void build_clear_page(void); 324 extern void build_clear_page(void);
325 extern void build_copy_page(void); 325 extern void build_copy_page(void);
diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index aa87ae552170..31f080b5f44c 100644
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -1221,7 +1221,7 @@ static inline void coherency_setup(void)
1221 } 1221 }
1222} 1222}
1223 1223
1224void __init ld_mmu_r4xx0(void) 1224void __init r4k_cache_init(void)
1225{ 1225{
1226 extern void build_clear_page(void); 1226 extern void build_clear_page(void);
1227 extern void build_copy_page(void); 1227 extern void build_copy_page(void);
diff --git a/arch/mips/mm/c-sb1.c b/arch/mips/mm/c-sb1.c
index d183dbced687..70d1ab30f7af 100644
--- a/arch/mips/mm/c-sb1.c
+++ b/arch/mips/mm/c-sb1.c
@@ -496,7 +496,7 @@ static __init void probe_cache_sizes(void)
496 * memory management function pointers, as well as initialize 496 * memory management function pointers, as well as initialize
497 * the caches and tlbs 497 * the caches and tlbs
498 */ 498 */
499void ld_mmu_sb1(void) 499void sb1_cache_init(void)
500{ 500{
501 extern char except_vec2_sb1; 501 extern char except_vec2_sb1;
502 extern char handle_vec2_sb1; 502 extern char handle_vec2_sb1;
diff --git a/arch/mips/mm/c-tx39.c b/arch/mips/mm/c-tx39.c
index c3ba81dab31d..0a97a9434eba 100644
--- a/arch/mips/mm/c-tx39.c
+++ b/arch/mips/mm/c-tx39.c
@@ -410,7 +410,7 @@ static __init void tx39_probe_cache(void)
410 } 410 }
411} 411}
412 412
413void __init ld_mmu_tx39(void) 413void __init tx39_cache_init(void)
414{ 414{
415 extern void build_clear_page(void); 415 extern void build_clear_page(void);
416 extern void build_copy_page(void); 416 extern void build_copy_page(void);
diff --git a/arch/mips/mm/cache.c b/arch/mips/mm/cache.c
index 172293b58390..611b48dde737 100644
--- a/arch/mips/mm/cache.c
+++ b/arch/mips/mm/cache.c
@@ -104,58 +104,48 @@ void __update_cache(struct vm_area_struct *vma, unsigned long address,
104 } 104 }
105} 105}
106 106
107extern void ld_mmu_r23000(void); 107#define __weak __attribute__((weak))
108extern void ld_mmu_r4xx0(void); 108
109extern void ld_mmu_tx39(void); 109static char cache_panic[] __initdata = "Yeee, unsupported cache architecture.";
110extern void ld_mmu_r6000(void);
111extern void ld_mmu_tfp(void);
112extern void ld_mmu_andes(void);
113extern void ld_mmu_sb1(void);
114 110
115void __init cpu_cache_init(void) 111void __init cpu_cache_init(void)
116{ 112{
117 if (cpu_has_4ktlb) { 113 if (cpu_has_3k_cache) {
118#if defined(CONFIG_CPU_R4X00) || defined(CONFIG_CPU_VR41XX) || \ 114 extern void __weak r3k_cache_init(void);
119 defined(CONFIG_CPU_R4300) || defined(CONFIG_CPU_R5000) || \ 115
120 defined(CONFIG_CPU_NEVADA) || defined(CONFIG_CPU_R5432) || \ 116 r3k_cache_init();
121 defined(CONFIG_CPU_R5500) || defined(CONFIG_CPU_MIPS32_R1) || \ 117 return;
122 defined(CONFIG_CPU_MIPS64_R1) || defined(CONFIG_CPU_TX49XX) || \ 118 }
123 defined(CONFIG_CPU_RM7000) || defined(CONFIG_CPU_RM9000) 119 if (cpu_has_6k_cache) {
124 ld_mmu_r4xx0(); 120 extern void __weak r6k_cache_init(void);
125#endif 121
126 } else switch (current_cpu_data.cputype) { 122 r6k_cache_init();
127#ifdef CONFIG_CPU_R3000 123 return;
128 case CPU_R2000:
129 case CPU_R3000:
130 case CPU_R3000A:
131 case CPU_R3081E:
132 ld_mmu_r23000();
133 break;
134#endif
135#ifdef CONFIG_CPU_TX39XX
136 case CPU_TX3912:
137 case CPU_TX3922:
138 case CPU_TX3927:
139 ld_mmu_tx39();
140 break;
141#endif
142#ifdef CONFIG_CPU_R10000
143 case CPU_R10000:
144 case CPU_R12000:
145 ld_mmu_r4xx0();
146 break;
147#endif
148#ifdef CONFIG_CPU_SB1
149 case CPU_SB1:
150 ld_mmu_sb1();
151 break;
152#endif
153
154 case CPU_R8000:
155 panic("R8000 is unsupported");
156 break;
157
158 default:
159 panic("Yeee, unsupported cache architecture.");
160 } 124 }
125 if (cpu_has_4k_cache) {
126 extern void __weak r4k_cache_init(void);
127
128 r4k_cache_init();
129 return;
130 }
131 if (cpu_has_8k_cache) {
132 extern void __weak r8k_cache_init(void);
133
134 r8k_cache_init();
135 return;
136 }
137 if (cpu_has_tx39_cache) {
138 extern void __weak tx39_cache_init(void);
139
140 tx39_cache_init();
141 return;
142 }
143 if (cpu_has_sb1_cache) {
144 extern void __weak sb1_cache_init(void);
145
146 sb1_cache_init();
147 return;
148 }
149
150 panic(cache_panic);
161} 151}