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authorLinus Torvalds <torvalds@linux-foundation.org>2011-03-22 20:53:13 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2011-03-22 20:53:13 -0400
commit6447f55da90b77faec1697d499ed7986bb4f6de6 (patch)
tree2d360d48121bdaa354d1ef19fed48467d08dfb1f /arch
parentc50e3f512a5a15a73acd94e6ec8ed63cd512e04f (diff)
parent3ea205c449d2b5996d0256aa8b2894f7aea228a2 (diff)
Merge branch 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/djbw/async_tx
* 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/djbw/async_tx: (66 commits) avr32: at32ap700x: fix typo in DMA master configuration dmaengine/dmatest: Pass timeout via module params dma: let IMX_DMA depend on IMX_HAVE_DMA_V1 instead of an explicit list of SoCs fsldma: make halt behave nicely on all supported controllers fsldma: reduce locking during descriptor cleanup fsldma: support async_tx dependencies and automatic unmapping fsldma: fix controller lockups fsldma: minor codingstyle and consistency fixes fsldma: improve link descriptor debugging fsldma: use channel name in printk output fsldma: move related helper functions near each other dmatest: fix automatic buffer unmap type drivers, pch_dma: Fix warning when CONFIG_PM=n. dmaengine/dw_dmac fix: use readl & writel instead of __raw_readl & __raw_writel avr32: at32ap700x: Specify DMA Flow Controller, Src and Dst msize dw_dmac: Setting Default Burst length for transfers as 16. dw_dmac: Allow src/dst msize & flow controller to be configured at runtime dw_dmac: Changing type of src_master and dest_master to u8. dw_dmac: Pass Channel Priority from platform_data dw_dmac: Pass Channel Allocation Order from platform_data ...
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/mach-mxs/include/mach/dma.h26
-rw-r--r--arch/arm/plat-nomadik/include/plat/ste_dma40.h22
-rw-r--r--arch/avr32/mach-at32ap/at32ap700x.c15
3 files changed, 44 insertions, 19 deletions
diff --git a/arch/arm/mach-mxs/include/mach/dma.h b/arch/arm/mach-mxs/include/mach/dma.h
new file mode 100644
index 000000000000..7f4aeeaba8df
--- /dev/null
+++ b/arch/arm/mach-mxs/include/mach/dma.h
@@ -0,0 +1,26 @@
1/*
2 * Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9#ifndef __MACH_MXS_DMA_H__
10#define __MACH_MXS_DMA_H__
11
12struct mxs_dma_data {
13 int chan_irq;
14};
15
16static inline int mxs_dma_is_apbh(struct dma_chan *chan)
17{
18 return !strcmp(dev_name(chan->device->dev), "mxs-dma-apbh");
19}
20
21static inline int mxs_dma_is_apbx(struct dma_chan *chan)
22{
23 return !strcmp(dev_name(chan->device->dev), "mxs-dma-apbx");
24}
25
26#endif /* __MACH_MXS_DMA_H__ */
diff --git a/arch/arm/plat-nomadik/include/plat/ste_dma40.h b/arch/arm/plat-nomadik/include/plat/ste_dma40.h
index 4d6dd4c39b75..c44886062f8e 100644
--- a/arch/arm/plat-nomadik/include/plat/ste_dma40.h
+++ b/arch/arm/plat-nomadik/include/plat/ste_dma40.h
@@ -104,6 +104,8 @@ struct stedma40_half_channel_info {
104 * 104 *
105 * @dir: MEM 2 MEM, PERIPH 2 MEM , MEM 2 PERIPH, PERIPH 2 PERIPH 105 * @dir: MEM 2 MEM, PERIPH 2 MEM , MEM 2 PERIPH, PERIPH 2 PERIPH
106 * @high_priority: true if high-priority 106 * @high_priority: true if high-priority
107 * @realtime: true if realtime mode is to be enabled. Only available on DMA40
108 * version 3+, i.e DB8500v2+
107 * @mode: channel mode: physical, logical, or operation 109 * @mode: channel mode: physical, logical, or operation
108 * @mode_opt: options for the chosen channel mode 110 * @mode_opt: options for the chosen channel mode
109 * @src_dev_type: Src device type 111 * @src_dev_type: Src device type
@@ -119,6 +121,7 @@ struct stedma40_half_channel_info {
119struct stedma40_chan_cfg { 121struct stedma40_chan_cfg {
120 enum stedma40_xfer_dir dir; 122 enum stedma40_xfer_dir dir;
121 bool high_priority; 123 bool high_priority;
124 bool realtime;
122 enum stedma40_mode mode; 125 enum stedma40_mode mode;
123 enum stedma40_mode_opt mode_opt; 126 enum stedma40_mode_opt mode_opt;
124 int src_dev_type; 127 int src_dev_type;
@@ -169,25 +172,6 @@ struct stedma40_platform_data {
169bool stedma40_filter(struct dma_chan *chan, void *data); 172bool stedma40_filter(struct dma_chan *chan, void *data);
170 173
171/** 174/**
172 * stedma40_memcpy_sg() - extension of the dma framework, memcpy to/from
173 * scattergatter lists.
174 *
175 * @chan: dmaengine handle
176 * @sgl_dst: Destination scatter list
177 * @sgl_src: Source scatter list
178 * @sgl_len: The length of each scatterlist. Both lists must be of equal length
179 * and each element must match the corresponding element in the other scatter
180 * list.
181 * @flags: is actually enum dma_ctrl_flags. See dmaengine.h
182 */
183
184struct dma_async_tx_descriptor *stedma40_memcpy_sg(struct dma_chan *chan,
185 struct scatterlist *sgl_dst,
186 struct scatterlist *sgl_src,
187 unsigned int sgl_len,
188 unsigned long flags);
189
190/**
191 * stedma40_slave_mem() - Transfers a raw data buffer to or from a slave 175 * stedma40_slave_mem() - Transfers a raw data buffer to or from a slave
192 * (=device) 176 * (=device)
193 * 177 *
diff --git a/arch/avr32/mach-at32ap/at32ap700x.c b/arch/avr32/mach-at32ap/at32ap700x.c
index e67c99945428..bfc9d071db9b 100644
--- a/arch/avr32/mach-at32ap/at32ap700x.c
+++ b/arch/avr32/mach-at32ap/at32ap700x.c
@@ -2048,6 +2048,11 @@ at32_add_device_ac97c(unsigned int id, struct ac97c_platform_data *data,
2048 rx_dws->reg_width = DW_DMA_SLAVE_WIDTH_16BIT; 2048 rx_dws->reg_width = DW_DMA_SLAVE_WIDTH_16BIT;
2049 rx_dws->cfg_hi = DWC_CFGH_SRC_PER(3); 2049 rx_dws->cfg_hi = DWC_CFGH_SRC_PER(3);
2050 rx_dws->cfg_lo &= ~(DWC_CFGL_HS_DST_POL | DWC_CFGL_HS_SRC_POL); 2050 rx_dws->cfg_lo &= ~(DWC_CFGL_HS_DST_POL | DWC_CFGL_HS_SRC_POL);
2051 rx_dws->src_master = 0;
2052 rx_dws->dst_master = 1;
2053 rx_dws->src_msize = DW_DMA_MSIZE_1;
2054 rx_dws->dst_msize = DW_DMA_MSIZE_1;
2055 rx_dws->fc = DW_DMA_FC_D_P2M;
2051 } 2056 }
2052 2057
2053 /* Check if DMA slave interface for playback should be configured. */ 2058 /* Check if DMA slave interface for playback should be configured. */
@@ -2056,6 +2061,11 @@ at32_add_device_ac97c(unsigned int id, struct ac97c_platform_data *data,
2056 tx_dws->reg_width = DW_DMA_SLAVE_WIDTH_16BIT; 2061 tx_dws->reg_width = DW_DMA_SLAVE_WIDTH_16BIT;
2057 tx_dws->cfg_hi = DWC_CFGH_DST_PER(4); 2062 tx_dws->cfg_hi = DWC_CFGH_DST_PER(4);
2058 tx_dws->cfg_lo &= ~(DWC_CFGL_HS_DST_POL | DWC_CFGL_HS_SRC_POL); 2063 tx_dws->cfg_lo &= ~(DWC_CFGL_HS_DST_POL | DWC_CFGL_HS_SRC_POL);
2064 tx_dws->src_master = 0;
2065 tx_dws->dst_master = 1;
2066 tx_dws->src_msize = DW_DMA_MSIZE_1;
2067 tx_dws->dst_msize = DW_DMA_MSIZE_1;
2068 tx_dws->fc = DW_DMA_FC_D_M2P;
2059 } 2069 }
2060 2070
2061 if (platform_device_add_data(pdev, data, 2071 if (platform_device_add_data(pdev, data,
@@ -2128,6 +2138,11 @@ at32_add_device_abdac(unsigned int id, struct atmel_abdac_pdata *data)
2128 dws->reg_width = DW_DMA_SLAVE_WIDTH_32BIT; 2138 dws->reg_width = DW_DMA_SLAVE_WIDTH_32BIT;
2129 dws->cfg_hi = DWC_CFGH_DST_PER(2); 2139 dws->cfg_hi = DWC_CFGH_DST_PER(2);
2130 dws->cfg_lo &= ~(DWC_CFGL_HS_DST_POL | DWC_CFGL_HS_SRC_POL); 2140 dws->cfg_lo &= ~(DWC_CFGL_HS_DST_POL | DWC_CFGL_HS_SRC_POL);
2141 dws->src_master = 0;
2142 dws->dst_master = 1;
2143 dws->src_msize = DW_DMA_MSIZE_1;
2144 dws->dst_msize = DW_DMA_MSIZE_1;
2145 dws->fc = DW_DMA_FC_D_M2P;
2131 2146
2132 if (platform_device_add_data(pdev, data, 2147 if (platform_device_add_data(pdev, data,
2133 sizeof(struct atmel_abdac_pdata))) 2148 sizeof(struct atmel_abdac_pdata)))