diff options
author | Tony Lindgren <tony@atomide.com> | 2010-02-15 12:27:24 -0500 |
---|---|---|
committer | Tony Lindgren <tony@atomide.com> | 2010-02-15 12:27:24 -0500 |
commit | 95d2b4e9cbba4c9a2ac63205e846e7ccfebe69b4 (patch) | |
tree | 70cba28f0c96a9cec107117d95dd820ba487596b /arch | |
parent | 1cf9d079637e1479842dad0b25f445b5ceec0bab (diff) |
omap2/3/4: Clean up defines for entry-macro.S
Define the irq base the same way as for omap2 and omap3,
and start using get_irqnr_preamble.
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Diffstat (limited to 'arch')
-rw-r--r-- | arch/arm/mach-omap2/include/mach/entry-macro.S | 15 |
1 files changed, 7 insertions, 8 deletions
diff --git a/arch/arm/mach-omap2/include/mach/entry-macro.S b/arch/arm/mach-omap2/include/mach/entry-macro.S index 4fd6b1bdcb2b..3e63aaabebe7 100644 --- a/arch/arm/mach-omap2/include/mach/entry-macro.S +++ b/arch/arm/mach-omap2/include/mach/entry-macro.S | |||
@@ -19,6 +19,12 @@ | |||
19 | #include <plat/omap34xx.h> | 19 | #include <plat/omap34xx.h> |
20 | #include <plat/omap44xx.h> | 20 | #include <plat/omap44xx.h> |
21 | 21 | ||
22 | #define OMAP2_IRQ_BASE OMAP2_L4_IO_ADDRESS(OMAP24XX_IC_BASE) | ||
23 | #define OMAP3_IRQ_BASE OMAP2_L4_IO_ADDRESS(OMAP34XX_IC_BASE) | ||
24 | #define OMAP4_IRQ_BASE OMAP2_L4_IO_ADDRESS(OMAP44XX_GIC_CPU_BASE) | ||
25 | #define INTCPS_SIR_IRQ_OFFSET 0x0040 /* omap2/3 active interrupt offset */ | ||
26 | #define ACTIVEIRQ_MASK 0x7f /* omap2/3 active interrupt bits */ | ||
27 | |||
22 | .macro disable_fiq | 28 | .macro disable_fiq |
23 | .endm | 29 | .endm |
24 | 30 | ||
@@ -27,11 +33,6 @@ | |||
27 | 33 | ||
28 | #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) | 34 | #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) |
29 | 35 | ||
30 | #define OMAP2_IRQ_BASE OMAP2_L4_IO_ADDRESS(OMAP24XX_IC_BASE) | ||
31 | #define OMAP3_IRQ_BASE OMAP2_L4_IO_ADDRESS(OMAP34XX_IC_BASE) | ||
32 | #define INTCPS_SIR_IRQ_OFFSET 0x0040 /* Active interrupt offset */ | ||
33 | #define ACTIVEIRQ_MASK 0x7f /* Active interrupt bits */ | ||
34 | |||
35 | .pushsection .data | 36 | .pushsection .data |
36 | omap_irq_base: .word 0 | 37 | omap_irq_base: .word 0 |
37 | .popsection | 38 | .popsection |
@@ -90,8 +91,6 @@ omap_irq_base: .word 0 | |||
90 | 91 | ||
91 | #ifdef CONFIG_ARCH_OMAP4 | 92 | #ifdef CONFIG_ARCH_OMAP4 |
92 | 93 | ||
93 | #define OMAP44XX_VA_GIC_CPU_BASE OMAP2_L4_IO_ADDRESS(OMAP44XX_GIC_CPU_BASE) | ||
94 | |||
95 | .macro get_irqnr_preamble, base, tmp | 94 | .macro get_irqnr_preamble, base, tmp |
96 | .endm | 95 | .endm |
97 | 96 | ||
@@ -115,7 +114,7 @@ omap_irq_base: .word 0 | |||
115 | * valid range for an IRQ (30-1020 inclusive). | 114 | * valid range for an IRQ (30-1020 inclusive). |
116 | */ | 115 | */ |
117 | .macro get_irqnr_and_base, irqnr, irqstat, base, tmp | 116 | .macro get_irqnr_and_base, irqnr, irqstat, base, tmp |
118 | ldr \base, =OMAP44XX_VA_GIC_CPU_BASE | 117 | ldr \base, =OMAP4_IRQ_BASE |
119 | ldr \irqstat, [\base, #GIC_CPU_INTACK] | 118 | ldr \irqstat, [\base, #GIC_CPU_INTACK] |
120 | 119 | ||
121 | ldr \tmp, =1021 | 120 | ldr \tmp, =1021 |