aboutsummaryrefslogtreecommitdiffstats
path: root/arch
diff options
context:
space:
mode:
authorDavid S. Miller <davem@davemloft.net>2008-11-19 02:38:23 -0500
committerDavid S. Miller <davem@davemloft.net>2008-11-19 02:38:23 -0500
commit198d6ba4d7f48c94f990f4604f0b3d73925e0ded (patch)
tree56bbdf8ba2553c23c8099da9344a8f1d1aba97ab /arch
parent9a57f7fabd383920585ed8b74eacd117c6551f2d (diff)
parent7f0f598a0069d1ab072375965a4b69137233169c (diff)
Merge branch 'master' of master.kernel.org:/pub/scm/linux/kernel/git/davem/net-2.6
Conflicts: drivers/isdn/i4l/isdn_net.c fs/cifs/connect.c
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/include/asm/dma-mapping.h13
-rw-r--r--arch/arm/include/asm/hardware/iop3xx-adma.h5
-rw-r--r--arch/arm/include/asm/hardware/iop_adma.h6
-rw-r--r--arch/arm/include/asm/mach/map.h13
-rw-r--r--arch/arm/mach-clps711x/include/mach/hardware.h22
-rw-r--r--arch/arm/mach-clps7500/core.c6
-rw-r--r--arch/arm/mach-clps7500/include/mach/hardware.h6
-rw-r--r--arch/arm/mach-h720x/include/mach/boards.h6
-rw-r--r--arch/arm/mach-integrator/include/mach/platform.h19
-rw-r--r--arch/arm/mach-iop13xx/include/mach/adma.h3
-rw-r--r--arch/arm/mach-realview/clock.c2
-rw-r--r--arch/arm/mach-realview/include/mach/platform.h19
-rw-r--r--arch/arm/mach-versatile/clock.c2
-rw-r--r--arch/arm/mach-versatile/include/mach/platform.h18
-rw-r--r--arch/arm/mm/cache-feroceon-l2.c4
-rw-r--r--arch/arm/mm/mmu.c6
-rw-r--r--arch/arm/plat-iop/setup.c5
-rw-r--r--arch/blackfin/include/asm/bfin-global.h2
-rw-r--r--arch/blackfin/include/asm/dma-mapping.h6
-rw-r--r--arch/blackfin/kernel/bfin_gpio.c2
-rw-r--r--arch/blackfin/kernel/cplb-nompu/cplbinit.c9
-rw-r--r--arch/blackfin/kernel/process.c7
-rw-r--r--arch/blackfin/kernel/setup.c12
-rw-r--r--arch/blackfin/kernel/traps.c11
-rw-r--r--arch/blackfin/mach-common/cache.S8
-rw-r--r--arch/blackfin/mach-common/cpufreq.c14
-rw-r--r--arch/blackfin/mach-common/entry.S2
-rw-r--r--arch/blackfin/mm/sram-alloc.c8
-rw-r--r--arch/ia64/kvm/Kconfig2
-rw-r--r--arch/ia64/kvm/kvm-ia64.c12
-rw-r--r--arch/ia64/kvm/vcpu.h5
-rw-r--r--arch/m68k/kernel/ints.c2
-rw-r--r--arch/mn10300/Kconfig.debug9
-rw-r--r--arch/mn10300/mm/misalignment.c538
-rw-r--r--arch/parisc/include/asm/smp.h2
-rw-r--r--arch/s390/kernel/entry.S20
-rw-r--r--arch/s390/kernel/entry64.S11
-rw-r--r--arch/s390/kernel/process.c3
-rw-r--r--arch/s390/kernel/setup.c4
-rw-r--r--arch/s390/kernel/sys_s390.c2
-rw-r--r--arch/s390/kernel/topology.c11
-rw-r--r--arch/sh/include/asm/io.h4
-rw-r--r--arch/sh/include/asm/pgtable.h6
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7723.c6
-rw-r--r--arch/sh/kernel/early_printk.c3
-rw-r--r--arch/sh/kernel/timers/timer-tmu.c2
-rw-r--r--arch/sh/lib/copy_page.S11
-rw-r--r--arch/sh/mm/Makefile_322
-rw-r--r--arch/sh/mm/Makefile_642
-rw-r--r--arch/sh/mm/init.c12
-rw-r--r--arch/sh/mm/mmap.c31
-rw-r--r--arch/sh/mm/pg-sh4.c17
-rw-r--r--arch/sparc/include/asm/termbits.h11
-rw-r--r--arch/sparc/kernel/of_device.c4
-rw-r--r--arch/x86/include/asm/acpi.h1
-rw-r--r--arch/x86/include/asm/iommu.h1
-rw-r--r--arch/x86/kernel/acpi/boot.c1
-rw-r--r--arch/x86/kernel/early-quirks.c18
-rw-r--r--arch/x86/kernel/kvmclock.c2
-rw-r--r--arch/x86/kvm/Kconfig2
-rw-r--r--arch/x86/kvm/i8254.c4
-rw-r--r--arch/x86/kvm/mmu.c2
-rw-r--r--arch/x86/kvm/vmx.c3
-rw-r--r--arch/x86/kvm/vmx.h1
64 files changed, 682 insertions, 321 deletions
diff --git a/arch/arm/include/asm/dma-mapping.h b/arch/arm/include/asm/dma-mapping.h
index 1cb8602dd9d5..4ed149cbb32a 100644
--- a/arch/arm/include/asm/dma-mapping.h
+++ b/arch/arm/include/asm/dma-mapping.h
@@ -256,8 +256,17 @@ int dmabounce_sync_for_cpu(struct device *, dma_addr_t, unsigned long,
256int dmabounce_sync_for_device(struct device *, dma_addr_t, unsigned long, 256int dmabounce_sync_for_device(struct device *, dma_addr_t, unsigned long,
257 size_t, enum dma_data_direction); 257 size_t, enum dma_data_direction);
258#else 258#else
259#define dmabounce_sync_for_cpu(dev,dma,off,sz,dir) (1) 259static inline int dmabounce_sync_for_cpu(struct device *d, dma_addr_t addr,
260#define dmabounce_sync_for_device(dev,dma,off,sz,dir) (1) 260 unsigned long offset, size_t size, enum dma_data_direction dir)
261{
262 return 1;
263}
264
265static inline int dmabounce_sync_for_device(struct device *d, dma_addr_t addr,
266 unsigned long offset, size_t size, enum dma_data_direction dir)
267{
268 return 1;
269}
261 270
262 271
263/** 272/**
diff --git a/arch/arm/include/asm/hardware/iop3xx-adma.h b/arch/arm/include/asm/hardware/iop3xx-adma.h
index 87bff09633aa..83e6ba338e2c 100644
--- a/arch/arm/include/asm/hardware/iop3xx-adma.h
+++ b/arch/arm/include/asm/hardware/iop3xx-adma.h
@@ -730,7 +730,8 @@ static inline void iop_desc_set_next_desc(struct iop_adma_desc_slot *desc,
730{ 730{
731 /* hw_desc->next_desc is the same location for all channels */ 731 /* hw_desc->next_desc is the same location for all channels */
732 union iop3xx_desc hw_desc = { .ptr = desc->hw_desc, }; 732 union iop3xx_desc hw_desc = { .ptr = desc->hw_desc, };
733 BUG_ON(hw_desc.dma->next_desc); 733
734 iop_paranoia(hw_desc.dma->next_desc);
734 hw_desc.dma->next_desc = next_desc_addr; 735 hw_desc.dma->next_desc = next_desc_addr;
735} 736}
736 737
@@ -760,7 +761,7 @@ static inline int iop_desc_get_zero_result(struct iop_adma_desc_slot *desc)
760 struct iop3xx_desc_aau *hw_desc = desc->hw_desc; 761 struct iop3xx_desc_aau *hw_desc = desc->hw_desc;
761 struct iop3xx_aau_desc_ctrl desc_ctrl = hw_desc->desc_ctrl_field; 762 struct iop3xx_aau_desc_ctrl desc_ctrl = hw_desc->desc_ctrl_field;
762 763
763 BUG_ON(!(desc_ctrl.tx_complete && desc_ctrl.zero_result_en)); 764 iop_paranoia(!(desc_ctrl.tx_complete && desc_ctrl.zero_result_en));
764 return desc_ctrl.zero_result_err; 765 return desc_ctrl.zero_result_err;
765} 766}
766 767
diff --git a/arch/arm/include/asm/hardware/iop_adma.h b/arch/arm/include/asm/hardware/iop_adma.h
index cb7e3611bcba..385c6e8cbbd2 100644
--- a/arch/arm/include/asm/hardware/iop_adma.h
+++ b/arch/arm/include/asm/hardware/iop_adma.h
@@ -23,6 +23,12 @@
23 23
24#define IOP_ADMA_SLOT_SIZE 32 24#define IOP_ADMA_SLOT_SIZE 32
25#define IOP_ADMA_THRESHOLD 4 25#define IOP_ADMA_THRESHOLD 4
26#ifdef DEBUG
27#define IOP_PARANOIA 1
28#else
29#define IOP_PARANOIA 0
30#endif
31#define iop_paranoia(x) BUG_ON(IOP_PARANOIA && (x))
26 32
27/** 33/**
28 * struct iop_adma_device - internal representation of an ADMA device 34 * struct iop_adma_device - internal representation of an ADMA device
diff --git a/arch/arm/include/asm/mach/map.h b/arch/arm/include/asm/mach/map.h
index cb1139ac1943..39d949b63e80 100644
--- a/arch/arm/include/asm/mach/map.h
+++ b/arch/arm/include/asm/mach/map.h
@@ -19,12 +19,13 @@ struct map_desc {
19}; 19};
20 20
21/* types 0-3 are defined in asm/io.h */ 21/* types 0-3 are defined in asm/io.h */
22#define MT_CACHECLEAN 4 22#define MT_UNCACHED 4
23#define MT_MINICLEAN 5 23#define MT_CACHECLEAN 5
24#define MT_LOW_VECTORS 6 24#define MT_MINICLEAN 6
25#define MT_HIGH_VECTORS 7 25#define MT_LOW_VECTORS 7
26#define MT_MEMORY 8 26#define MT_HIGH_VECTORS 8
27#define MT_ROM 9 27#define MT_MEMORY 9
28#define MT_ROM 10
28 29
29#ifdef CONFIG_MMU 30#ifdef CONFIG_MMU
30extern void iotable_init(struct map_desc *, int); 31extern void iotable_init(struct map_desc *, int);
diff --git a/arch/arm/mach-clps711x/include/mach/hardware.h b/arch/arm/mach-clps711x/include/mach/hardware.h
index 4c3e101b96c9..b3ebe9e4871f 100644
--- a/arch/arm/mach-clps711x/include/mach/hardware.h
+++ b/arch/arm/mach-clps711x/include/mach/hardware.h
@@ -94,20 +94,6 @@
94#include <asm/hardware/ep7212.h> 94#include <asm/hardware/ep7212.h>
95#include <asm/hardware/cs89712.h> 95#include <asm/hardware/cs89712.h>
96 96
97/* dynamic ioremap() areas */
98#define FLASH_START 0x00000000
99#define FLASH_SIZE 0x800000
100#define FLASH_WIDTH 4
101
102#define SRAM_START 0x60000000
103#define SRAM_SIZE 0xc000
104#define SRAM_WIDTH 4
105
106#define BOOTROM_START 0x70000000
107#define BOOTROM_SIZE 0x80
108#define BOOTROM_WIDTH 4
109
110
111/* static cdb89712_map_io() areas */ 97/* static cdb89712_map_io() areas */
112#define REGISTER_START 0x80000000 98#define REGISTER_START 0x80000000
113#define REGISTER_SIZE 0x4000 99#define REGISTER_SIZE 0x4000
@@ -198,14 +184,6 @@
198#define CEIVA_FLASH_SIZE 0x100000 184#define CEIVA_FLASH_SIZE 0x100000
199#define CEIVA_FLASH_WIDTH 2 185#define CEIVA_FLASH_WIDTH 2
200 186
201#define SRAM_START 0x60000000
202#define SRAM_SIZE 0xc000
203#define SRAM_WIDTH 4
204
205#define BOOTROM_START 0x70000000
206#define BOOTROM_SIZE 0x80
207#define BOOTROM_WIDTH 4
208
209/* 187/*
210 * SED1355 LCD controller 188 * SED1355 LCD controller
211 */ 189 */
diff --git a/arch/arm/mach-clps7500/core.c b/arch/arm/mach-clps7500/core.c
index c3a33b8a5aac..7e247c04d41c 100644
--- a/arch/arm/mach-clps7500/core.c
+++ b/arch/arm/mach-clps7500/core.c
@@ -275,9 +275,9 @@ static struct map_desc cl7500_io_desc[] __initdata = {
275 .length = ISA_SIZE, 275 .length = ISA_SIZE,
276 .type = MT_DEVICE 276 .type = MT_DEVICE
277 }, { /* Flash */ 277 }, { /* Flash */
278 .virtual = FLASH_BASE, 278 .virtual = CLPS7500_FLASH_BASE,
279 .pfn = __phys_to_pfn(FLASH_START), 279 .pfn = __phys_to_pfn(CLPS7500_FLASH_START),
280 .length = FLASH_SIZE, 280 .length = CLPS7500_FLASH_SIZE,
281 .type = MT_DEVICE 281 .type = MT_DEVICE
282 }, { /* LED */ 282 }, { /* LED */
283 .virtual = LED_BASE, 283 .virtual = LED_BASE,
diff --git a/arch/arm/mach-clps7500/include/mach/hardware.h b/arch/arm/mach-clps7500/include/mach/hardware.h
index d66578a3371c..a6ad1d44badf 100644
--- a/arch/arm/mach-clps7500/include/mach/hardware.h
+++ b/arch/arm/mach-clps7500/include/mach/hardware.h
@@ -39,9 +39,9 @@
39#define ISA_SIZE 0x00010000 39#define ISA_SIZE 0x00010000
40#define ISA_BASE 0xe1000000 40#define ISA_BASE 0xe1000000
41 41
42#define FLASH_START 0x01000000 /* XXX */ 42#define CLPS7500_FLASH_START 0x01000000 /* XXX */
43#define FLASH_SIZE 0x01000000 43#define CLPS7500_FLASH_SIZE 0x01000000
44#define FLASH_BASE 0xe2000000 44#define CLPS7500_FLASH_BASE 0xe2000000
45 45
46#define LED_START 0x0302B000 46#define LED_START 0x0302B000
47#define LED_SIZE 0x00001000 47#define LED_SIZE 0x00001000
diff --git a/arch/arm/mach-h720x/include/mach/boards.h b/arch/arm/mach-h720x/include/mach/boards.h
index 079b279e1242..38b8e0d61fbf 100644
--- a/arch/arm/mach-h720x/include/mach/boards.h
+++ b/arch/arm/mach-h720x/include/mach/boards.h
@@ -19,9 +19,9 @@
19#ifdef CONFIG_ARCH_H7202 19#ifdef CONFIG_ARCH_H7202
20 20
21/* FLASH */ 21/* FLASH */
22#define FLASH_VIRT 0xd0000000 22#define H720X_FLASH_VIRT 0xd0000000
23#define FLASH_PHYS 0x00000000 23#define H720X_FLASH_PHYS 0x00000000
24#define FLASH_SIZE 0x02000000 24#define H720X_FLASH_SIZE 0x02000000
25 25
26/* onboard LAN controller */ 26/* onboard LAN controller */
27# define ETH0_PHYS 0x08000000 27# define ETH0_PHYS 0x08000000
diff --git a/arch/arm/mach-integrator/include/mach/platform.h b/arch/arm/mach-integrator/include/mach/platform.h
index 028b87839c0f..e00a2624f269 100644
--- a/arch/arm/mach-integrator/include/mach/platform.h
+++ b/arch/arm/mach-integrator/include/mach/platform.h
@@ -408,27 +408,10 @@
408#define uHAL_MEMORY_SIZE INTEGRATOR_SSRAM_SIZE 408#define uHAL_MEMORY_SIZE INTEGRATOR_SSRAM_SIZE
409 409
410/* 410/*
411 * Application Flash
412 *
413 */
414#define FLASH_BASE INTEGRATOR_FLASH_BASE
415#define FLASH_SIZE INTEGRATOR_FLASH_SIZE
416#define FLASH_END (FLASH_BASE + FLASH_SIZE - 1)
417#define FLASH_BLOCK_SIZE SZ_128K
418
419/*
420 * Boot Flash
421 *
422 */
423#define EPROM_BASE INTEGRATOR_BOOT_ROM_HI
424#define EPROM_SIZE INTEGRATOR_BOOT_ROM_SIZE
425#define EPROM_END (EPROM_BASE + EPROM_SIZE - 1)
426
427/*
428 * Clean base - dummy 411 * Clean base - dummy
429 * 412 *
430 */ 413 */
431#define CLEAN_BASE EPROM_BASE 414#define CLEAN_BASE INTEGRATOR_BOOT_ROM_HI
432 415
433/* 416/*
434 * Timer definitions 417 * Timer definitions
diff --git a/arch/arm/mach-iop13xx/include/mach/adma.h b/arch/arm/mach-iop13xx/include/mach/adma.h
index 60019c8e6465..5722e86f2174 100644
--- a/arch/arm/mach-iop13xx/include/mach/adma.h
+++ b/arch/arm/mach-iop13xx/include/mach/adma.h
@@ -404,7 +404,8 @@ static inline void iop_desc_set_next_desc(struct iop_adma_desc_slot *desc,
404 u32 next_desc_addr) 404 u32 next_desc_addr)
405{ 405{
406 struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc; 406 struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc;
407 BUG_ON(hw_desc->next_desc); 407
408 iop_paranoia(hw_desc->next_desc);
408 hw_desc->next_desc = next_desc_addr; 409 hw_desc->next_desc = next_desc_addr;
409} 410}
410 411
diff --git a/arch/arm/mach-realview/clock.c b/arch/arm/mach-realview/clock.c
index 3e706c57833a..3347c4236a60 100644
--- a/arch/arm/mach-realview/clock.c
+++ b/arch/arm/mach-realview/clock.c
@@ -104,7 +104,7 @@ static struct clk uart_clk = {
104 104
105static struct clk mmci_clk = { 105static struct clk mmci_clk = {
106 .name = "MCLK", 106 .name = "MCLK",
107 .rate = 33000000, 107 .rate = 24000000,
108}; 108};
109 109
110int clk_register(struct clk *clk) 110int clk_register(struct clk *clk)
diff --git a/arch/arm/mach-realview/include/mach/platform.h b/arch/arm/mach-realview/include/mach/platform.h
index 4034b54950c2..793a3a332712 100644
--- a/arch/arm/mach-realview/include/mach/platform.h
+++ b/arch/arm/mach-realview/include/mach/platform.h
@@ -239,27 +239,10 @@
239#define REALVIEW_DECODE_OFFSET 0xC /* Fitted logic modules */ 239#define REALVIEW_DECODE_OFFSET 0xC /* Fitted logic modules */
240 240
241/* 241/*
242 * Application Flash
243 *
244 */
245#define FLASH_BASE REALVIEW_FLASH_BASE
246#define FLASH_SIZE REALVIEW_FLASH_SIZE
247#define FLASH_END (FLASH_BASE + FLASH_SIZE - 1)
248#define FLASH_BLOCK_SIZE SZ_128K
249
250/*
251 * Boot Flash
252 *
253 */
254#define EPROM_BASE REALVIEW_BOOT_ROM_HI
255#define EPROM_SIZE REALVIEW_BOOT_ROM_SIZE
256#define EPROM_END (EPROM_BASE + EPROM_SIZE - 1)
257
258/*
259 * Clean base - dummy 242 * Clean base - dummy
260 * 243 *
261 */ 244 */
262#define CLEAN_BASE EPROM_BASE 245#define CLEAN_BASE REALVIEW_BOOT_ROM_HI
263 246
264/* 247/*
265 * System controller bit assignment 248 * System controller bit assignment
diff --git a/arch/arm/mach-versatile/clock.c b/arch/arm/mach-versatile/clock.c
index 9336508ec0b2..58937f1fb38c 100644
--- a/arch/arm/mach-versatile/clock.c
+++ b/arch/arm/mach-versatile/clock.c
@@ -105,7 +105,7 @@ static struct clk uart_clk = {
105 105
106static struct clk mmci_clk = { 106static struct clk mmci_clk = {
107 .name = "MCLK", 107 .name = "MCLK",
108 .rate = 33000000, 108 .rate = 24000000,
109}; 109};
110 110
111int clk_register(struct clk *clk) 111int clk_register(struct clk *clk)
diff --git a/arch/arm/mach-versatile/include/mach/platform.h b/arch/arm/mach-versatile/include/mach/platform.h
index 27cbe6a3f220..f91ba930ca8a 100644
--- a/arch/arm/mach-versatile/include/mach/platform.h
+++ b/arch/arm/mach-versatile/include/mach/platform.h
@@ -436,28 +436,12 @@
436#define SIC_INTMASK_PCI1 (1 << SIC_INT_PCI1) 436#define SIC_INTMASK_PCI1 (1 << SIC_INT_PCI1)
437#define SIC_INTMASK_PCI2 (1 << SIC_INT_PCI2) 437#define SIC_INTMASK_PCI2 (1 << SIC_INT_PCI2)
438#define SIC_INTMASK_PCI3 (1 << SIC_INT_PCI3) 438#define SIC_INTMASK_PCI3 (1 << SIC_INT_PCI3)
439/*
440 * Application Flash
441 *
442 */
443#define FLASH_BASE VERSATILE_FLASH_BASE
444#define FLASH_SIZE VERSATILE_FLASH_SIZE
445#define FLASH_END (FLASH_BASE + FLASH_SIZE - 1)
446#define FLASH_BLOCK_SIZE SZ_128K
447
448/*
449 * Boot Flash
450 *
451 */
452#define EPROM_BASE VERSATILE_BOOT_ROM_HI
453#define EPROM_SIZE VERSATILE_BOOT_ROM_SIZE
454#define EPROM_END (EPROM_BASE + EPROM_SIZE - 1)
455 439
456/* 440/*
457 * Clean base - dummy 441 * Clean base - dummy
458 * 442 *
459 */ 443 */
460#define CLEAN_BASE EPROM_BASE 444#define CLEAN_BASE VERSATILE_BOOT_ROM_HI
461 445
462/* 446/*
463 * System controller bit assignment 447 * System controller bit assignment
diff --git a/arch/arm/mm/cache-feroceon-l2.c b/arch/arm/mm/cache-feroceon-l2.c
index 13cdae8b0d44..80cd207cbaea 100644
--- a/arch/arm/mm/cache-feroceon-l2.c
+++ b/arch/arm/mm/cache-feroceon-l2.c
@@ -150,7 +150,7 @@ static void feroceon_l2_inv_range(unsigned long start, unsigned long end)
150 /* 150 /*
151 * Clean and invalidate partial last cache line. 151 * Clean and invalidate partial last cache line.
152 */ 152 */
153 if (end & (CACHE_LINE_SIZE - 1)) { 153 if (start < end && end & (CACHE_LINE_SIZE - 1)) {
154 l2_clean_inv_pa(end & ~(CACHE_LINE_SIZE - 1)); 154 l2_clean_inv_pa(end & ~(CACHE_LINE_SIZE - 1));
155 end &= ~(CACHE_LINE_SIZE - 1); 155 end &= ~(CACHE_LINE_SIZE - 1);
156 } 156 }
@@ -158,7 +158,7 @@ static void feroceon_l2_inv_range(unsigned long start, unsigned long end)
158 /* 158 /*
159 * Invalidate all full cache lines between 'start' and 'end'. 159 * Invalidate all full cache lines between 'start' and 'end'.
160 */ 160 */
161 while (start != end) { 161 while (start < end) {
162 unsigned long range_end = calc_range_end(start, end); 162 unsigned long range_end = calc_range_end(start, end);
163 l2_inv_pa_range(start, range_end - CACHE_LINE_SIZE); 163 l2_inv_pa_range(start, range_end - CACHE_LINE_SIZE);
164 start = range_end; 164 start = range_end;
diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
index e63db11f16a8..7f36c825718d 100644
--- a/arch/arm/mm/mmu.c
+++ b/arch/arm/mm/mmu.c
@@ -208,6 +208,12 @@ static struct mem_type mem_types[] = {
208 .prot_sect = PROT_SECT_DEVICE, 208 .prot_sect = PROT_SECT_DEVICE,
209 .domain = DOMAIN_IO, 209 .domain = DOMAIN_IO,
210 }, 210 },
211 [MT_UNCACHED] = {
212 .prot_pte = PROT_PTE_DEVICE,
213 .prot_l1 = PMD_TYPE_TABLE,
214 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN,
215 .domain = DOMAIN_IO,
216 },
211 [MT_CACHECLEAN] = { 217 [MT_CACHECLEAN] = {
212 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN, 218 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN,
213 .domain = DOMAIN_KERNEL, 219 .domain = DOMAIN_KERNEL,
diff --git a/arch/arm/plat-iop/setup.c b/arch/arm/plat-iop/setup.c
index 4689db638e95..9e573e78176a 100644
--- a/arch/arm/plat-iop/setup.c
+++ b/arch/arm/plat-iop/setup.c
@@ -16,14 +16,15 @@
16#include <asm/hardware/iop3xx.h> 16#include <asm/hardware/iop3xx.h>
17 17
18/* 18/*
19 * Standard IO mapping for all IOP3xx based systems 19 * Standard IO mapping for all IOP3xx based systems. Note that
20 * the IOP3xx OCCDR must be mapped uncached and unbuffered.
20 */ 21 */
21static struct map_desc iop3xx_std_desc[] __initdata = { 22static struct map_desc iop3xx_std_desc[] __initdata = {
22 { /* mem mapped registers */ 23 { /* mem mapped registers */
23 .virtual = IOP3XX_PERIPHERAL_VIRT_BASE, 24 .virtual = IOP3XX_PERIPHERAL_VIRT_BASE,
24 .pfn = __phys_to_pfn(IOP3XX_PERIPHERAL_PHYS_BASE), 25 .pfn = __phys_to_pfn(IOP3XX_PERIPHERAL_PHYS_BASE),
25 .length = IOP3XX_PERIPHERAL_SIZE, 26 .length = IOP3XX_PERIPHERAL_SIZE,
26 .type = MT_DEVICE, 27 .type = MT_UNCACHED,
27 }, { /* PCI IO space */ 28 }, { /* PCI IO space */
28 .virtual = IOP3XX_PCI_LOWER_IO_VA, 29 .virtual = IOP3XX_PCI_LOWER_IO_VA,
29 .pfn = __phys_to_pfn(IOP3XX_PCI_LOWER_IO_PA), 30 .pfn = __phys_to_pfn(IOP3XX_PCI_LOWER_IO_PA),
diff --git a/arch/blackfin/include/asm/bfin-global.h b/arch/blackfin/include/asm/bfin-global.h
index 56dcb0a2d244..77295666c34b 100644
--- a/arch/blackfin/include/asm/bfin-global.h
+++ b/arch/blackfin/include/asm/bfin-global.h
@@ -101,7 +101,7 @@ extern u16 _bfin_swrst; /* shadow for Software Reset Register (SWRST) */
101extern unsigned long _ramstart, _ramend, _rambase; 101extern unsigned long _ramstart, _ramend, _rambase;
102extern unsigned long memory_start, memory_end, physical_mem_end; 102extern unsigned long memory_start, memory_end, physical_mem_end;
103extern char _stext_l1[], _etext_l1[], _sdata_l1[], _edata_l1[], _sbss_l1[], 103extern char _stext_l1[], _etext_l1[], _sdata_l1[], _edata_l1[], _sbss_l1[],
104 _ebss_l1[], _l1_lma_start[], _sdata_b_l1[], _ebss_b_l1[], 104 _ebss_l1[], _l1_lma_start[], _sdata_b_l1[], _sbss_b_l1[], _ebss_b_l1[],
105 _stext_l2[], _etext_l2[], _sdata_l2[], _edata_l2[], _sbss_l2[], 105 _stext_l2[], _etext_l2[], _sdata_l2[], _edata_l2[], _sbss_l2[],
106 _ebss_l2[], _l2_lma_start[]; 106 _ebss_l2[], _l2_lma_start[];
107 107
diff --git a/arch/blackfin/include/asm/dma-mapping.h b/arch/blackfin/include/asm/dma-mapping.h
index ede748d67efd..d7d9148e433c 100644
--- a/arch/blackfin/include/asm/dma-mapping.h
+++ b/arch/blackfin/include/asm/dma-mapping.h
@@ -15,7 +15,11 @@ void dma_free_coherent(struct device *dev, size_t size, void *vaddr,
15#define dma_alloc_noncoherent(d, s, h, f) dma_alloc_coherent(d, s, h, f) 15#define dma_alloc_noncoherent(d, s, h, f) dma_alloc_coherent(d, s, h, f)
16#define dma_free_noncoherent(d, s, v, h) dma_free_coherent(d, s, v, h) 16#define dma_free_noncoherent(d, s, v, h) dma_free_coherent(d, s, v, h)
17 17
18#define dma_mapping_error 18static inline
19int dma_mapping_error(struct device *dev, dma_addr_t dma_addr)
20{
21 return 0;
22}
19 23
20/* 24/*
21 * Map a single buffer of the indicated size for DMA in streaming mode. 25 * Map a single buffer of the indicated size for DMA in streaming mode.
diff --git a/arch/blackfin/kernel/bfin_gpio.c b/arch/blackfin/kernel/bfin_gpio.c
index 6e08f425bb44..5c0800adb4dd 100644
--- a/arch/blackfin/kernel/bfin_gpio.c
+++ b/arch/blackfin/kernel/bfin_gpio.c
@@ -218,7 +218,7 @@ inline int check_gpio(unsigned gpio)
218 if (gpio == GPIO_PB15 || gpio == GPIO_PC14 || gpio == GPIO_PC15 218 if (gpio == GPIO_PB15 || gpio == GPIO_PC14 || gpio == GPIO_PC15
219 || gpio == GPIO_PH14 || gpio == GPIO_PH15 219 || gpio == GPIO_PH14 || gpio == GPIO_PH15
220 || gpio == GPIO_PJ14 || gpio == GPIO_PJ15 220 || gpio == GPIO_PJ14 || gpio == GPIO_PJ15
221 || gpio > MAX_BLACKFIN_GPIOS) 221 || gpio >= MAX_BLACKFIN_GPIOS)
222 return -EINVAL; 222 return -EINVAL;
223 return 0; 223 return 0;
224} 224}
diff --git a/arch/blackfin/kernel/cplb-nompu/cplbinit.c b/arch/blackfin/kernel/cplb-nompu/cplbinit.c
index 512f8c92ead5..2debc900e246 100644
--- a/arch/blackfin/kernel/cplb-nompu/cplbinit.c
+++ b/arch/blackfin/kernel/cplb-nompu/cplbinit.c
@@ -188,10 +188,11 @@ static struct cplb_desc cplb_data[] = {
188 188
189static u16 __init lock_kernel_check(u32 start, u32 end) 189static u16 __init lock_kernel_check(u32 start, u32 end)
190{ 190{
191 if ((end <= (u32) _end && end >= (u32)_stext) || 191 if (start >= (u32)_end || end <= (u32)_stext)
192 (start <= (u32) _end && start >= (u32)_stext)) 192 return 0;
193 return IN_KERNEL; 193
194 return 0; 194 /* This cplb block overlapped with kernel area. */
195 return IN_KERNEL;
195} 196}
196 197
197static unsigned short __init 198static unsigned short __init
diff --git a/arch/blackfin/kernel/process.c b/arch/blackfin/kernel/process.c
index 77800dd83e57..0c3ea118b657 100644
--- a/arch/blackfin/kernel/process.c
+++ b/arch/blackfin/kernel/process.c
@@ -351,10 +351,15 @@ int _access_ok(unsigned long addr, unsigned long size)
351 return 1; 351 return 1;
352#endif 352#endif
353#if L1_DATA_B_LENGTH != 0 353#if L1_DATA_B_LENGTH != 0
354 if (addr >= L1_DATA_B_START 354 if (addr >= L1_DATA_B_START + (_ebss_b_l1 - _sdata_b_l1)
355 && addr + size <= L1_DATA_B_START + L1_DATA_B_LENGTH) 355 && addr + size <= L1_DATA_B_START + L1_DATA_B_LENGTH)
356 return 1; 356 return 1;
357#endif 357#endif
358#if L2_LENGTH != 0
359 if (addr >= L2_START + (_ebss_l2 - _stext_l2)
360 && addr + size <= L2_START + L2_LENGTH)
361 return 1;
362#endif
358 return 0; 363 return 0;
359} 364}
360EXPORT_SYMBOL(_access_ok); 365EXPORT_SYMBOL(_access_ok);
diff --git a/arch/blackfin/kernel/setup.c b/arch/blackfin/kernel/setup.c
index 7f35d1046cd8..71a9a8c53cea 100644
--- a/arch/blackfin/kernel/setup.c
+++ b/arch/blackfin/kernel/setup.c
@@ -119,23 +119,23 @@ void __init bfin_relocate_l1_mem(void)
119 /* Copy _stext_l1 to _etext_l1 to L1 instruction SRAM */ 119 /* Copy _stext_l1 to _etext_l1 to L1 instruction SRAM */
120 dma_memcpy(_stext_l1, _l1_lma_start, l1_code_length); 120 dma_memcpy(_stext_l1, _l1_lma_start, l1_code_length);
121 121
122 l1_data_a_length = _ebss_l1 - _sdata_l1; 122 l1_data_a_length = _sbss_l1 - _sdata_l1;
123 if (l1_data_a_length > L1_DATA_A_LENGTH) 123 if (l1_data_a_length > L1_DATA_A_LENGTH)
124 panic("L1 Data SRAM Bank A Overflow\n"); 124 panic("L1 Data SRAM Bank A Overflow\n");
125 125
126 /* Copy _sdata_l1 to _ebss_l1 to L1 data bank A SRAM */ 126 /* Copy _sdata_l1 to _sbss_l1 to L1 data bank A SRAM */
127 dma_memcpy(_sdata_l1, _l1_lma_start + l1_code_length, l1_data_a_length); 127 dma_memcpy(_sdata_l1, _l1_lma_start + l1_code_length, l1_data_a_length);
128 128
129 l1_data_b_length = _ebss_b_l1 - _sdata_b_l1; 129 l1_data_b_length = _sbss_b_l1 - _sdata_b_l1;
130 if (l1_data_b_length > L1_DATA_B_LENGTH) 130 if (l1_data_b_length > L1_DATA_B_LENGTH)
131 panic("L1 Data SRAM Bank B Overflow\n"); 131 panic("L1 Data SRAM Bank B Overflow\n");
132 132
133 /* Copy _sdata_b_l1 to _ebss_b_l1 to L1 data bank B SRAM */ 133 /* Copy _sdata_b_l1 to _sbss_b_l1 to L1 data bank B SRAM */
134 dma_memcpy(_sdata_b_l1, _l1_lma_start + l1_code_length + 134 dma_memcpy(_sdata_b_l1, _l1_lma_start + l1_code_length +
135 l1_data_a_length, l1_data_b_length); 135 l1_data_a_length, l1_data_b_length);
136 136
137 if (L2_LENGTH != 0) { 137 if (L2_LENGTH != 0) {
138 l2_length = _ebss_l2 - _stext_l2; 138 l2_length = _sbss_l2 - _stext_l2;
139 if (l2_length > L2_LENGTH) 139 if (l2_length > L2_LENGTH)
140 panic("L2 SRAM Overflow\n"); 140 panic("L2 SRAM Overflow\n");
141 141
@@ -827,7 +827,7 @@ void __init setup_arch(char **cmdline_p)
827 printk(KERN_ERR "Warning: Compiled for Rev %d, but running on Rev %d\n", 827 printk(KERN_ERR "Warning: Compiled for Rev %d, but running on Rev %d\n",
828 bfin_compiled_revid(), bfin_revid()); 828 bfin_compiled_revid(), bfin_revid());
829 } 829 }
830 if (bfin_revid() <= CONFIG_BF_REV_MIN || bfin_revid() > CONFIG_BF_REV_MAX) 830 if (bfin_revid() < CONFIG_BF_REV_MIN || bfin_revid() > CONFIG_BF_REV_MAX)
831 printk(KERN_ERR "Warning: Unsupported Chip Revision ADSP-%s Rev 0.%d detected\n", 831 printk(KERN_ERR "Warning: Unsupported Chip Revision ADSP-%s Rev 0.%d detected\n",
832 CPU, bfin_revid()); 832 CPU, bfin_revid());
833 } 833 }
diff --git a/arch/blackfin/kernel/traps.c b/arch/blackfin/kernel/traps.c
index 1aa2c788e228..bef025b07443 100644
--- a/arch/blackfin/kernel/traps.c
+++ b/arch/blackfin/kernel/traps.c
@@ -59,7 +59,7 @@
59#endif 59#endif
60 60
61 61
62#ifdef CONFIG_VERBOSE_DEBUG 62#ifdef CONFIG_DEBUG_VERBOSE
63#define verbose_printk(fmt, arg...) \ 63#define verbose_printk(fmt, arg...) \
64 printk(fmt, ##arg) 64 printk(fmt, ##arg)
65#else 65#else
@@ -147,9 +147,12 @@ static void decode_address(char *buf, unsigned long address)
147 char *name = p->comm; 147 char *name = p->comm;
148 struct file *file = vma->vm_file; 148 struct file *file = vma->vm_file;
149 149
150 if (file) 150 if (file) {
151 name = d_path(&file->f_path, _tmpbuf, 151 char *d_name = d_path(&file->f_path, _tmpbuf,
152 sizeof(_tmpbuf)); 152 sizeof(_tmpbuf));
153 if (!IS_ERR(d_name))
154 name = d_name;
155 }
153 156
154 /* FLAT does not have its text aligned to the start of 157 /* FLAT does not have its text aligned to the start of
155 * the map while FDPIC ELF does ... 158 * the map while FDPIC ELF does ...
@@ -571,7 +574,7 @@ asmlinkage void trap_c(struct pt_regs *fp)
571#endif 574#endif
572 panic("Kernel exception"); 575 panic("Kernel exception");
573 } else { 576 } else {
574#ifdef CONFIG_VERBOSE_DEBUG 577#ifdef CONFIG_DEBUG_VERBOSE
575 unsigned long *stack; 578 unsigned long *stack;
576 /* Dump the user space stack */ 579 /* Dump the user space stack */
577 stack = (unsigned long *)rdusp(); 580 stack = (unsigned long *)rdusp();
diff --git a/arch/blackfin/mach-common/cache.S b/arch/blackfin/mach-common/cache.S
index db532181fbde..a028e9450419 100644
--- a/arch/blackfin/mach-common/cache.S
+++ b/arch/blackfin/mach-common/cache.S
@@ -25,9 +25,13 @@
25 */ 25 */
26.macro do_flush flushins:req optflushins optnopins label 26.macro do_flush flushins:req optflushins optnopins label
27 27
28 R2 = -L1_CACHE_BYTES;
29
30 /* start = (start & -L1_CACHE_BYTES) */
31 R0 = R0 & R2;
32
28 /* end = ((end - 1) & -L1_CACHE_BYTES) + L1_CACHE_BYTES; */ 33 /* end = ((end - 1) & -L1_CACHE_BYTES) + L1_CACHE_BYTES; */
29 R1 += -1; 34 R1 += -1;
30 R2 = -L1_CACHE_BYTES;
31 R1 = R1 & R2; 35 R1 = R1 & R2;
32 R1 += L1_CACHE_BYTES; 36 R1 += L1_CACHE_BYTES;
33 37
@@ -63,7 +67,7 @@ ENDPROC(_blackfin_icache_flush_range)
63 67
64/* Flush all cache lines assocoiated with this area of memory. */ 68/* Flush all cache lines assocoiated with this area of memory. */
65ENTRY(_blackfin_icache_dcache_flush_range) 69ENTRY(_blackfin_icache_dcache_flush_range)
66 do_flush IFLUSH, FLUSH 70 do_flush FLUSH, IFLUSH
67ENDPROC(_blackfin_icache_dcache_flush_range) 71ENDPROC(_blackfin_icache_dcache_flush_range)
68 72
69/* Throw away all D-cached data in specified region without any obligation to 73/* Throw away all D-cached data in specified region without any obligation to
diff --git a/arch/blackfin/mach-common/cpufreq.c b/arch/blackfin/mach-common/cpufreq.c
index c22c47b60127..dda5443b37ed 100644
--- a/arch/blackfin/mach-common/cpufreq.c
+++ b/arch/blackfin/mach-common/cpufreq.c
@@ -72,13 +72,13 @@ unsigned int __bfin_cycles_mod;
72 72
73/**************************************************************************/ 73/**************************************************************************/
74 74
75static unsigned int bfin_getfreq(unsigned int cpu) 75static unsigned int bfin_getfreq_khz(unsigned int cpu)
76{ 76{
77 /* The driver only support single cpu */ 77 /* The driver only support single cpu */
78 if (cpu != 0) 78 if (cpu != 0)
79 return -1; 79 return -1;
80 80
81 return get_cclk(); 81 return get_cclk() / 1000;
82} 82}
83 83
84 84
@@ -96,7 +96,7 @@ static int bfin_target(struct cpufreq_policy *policy,
96 96
97 cclk_hz = bfin_freq_table[index].frequency; 97 cclk_hz = bfin_freq_table[index].frequency;
98 98
99 freqs.old = bfin_getfreq(0); 99 freqs.old = bfin_getfreq_khz(0);
100 freqs.new = cclk_hz; 100 freqs.new = cclk_hz;
101 freqs.cpu = 0; 101 freqs.cpu = 0;
102 102
@@ -137,8 +137,8 @@ static int __init __bfin_cpu_init(struct cpufreq_policy *policy)
137 if (policy->cpu != 0) 137 if (policy->cpu != 0)
138 return -EINVAL; 138 return -EINVAL;
139 139
140 cclk = get_cclk(); 140 cclk = get_cclk() / 1000;
141 sclk = get_sclk(); 141 sclk = get_sclk() / 1000;
142 142
143#if ANOMALY_05000273 || (!defined(CONFIG_BF54x) && defined(CONFIG_BFIN_DCACHE)) 143#if ANOMALY_05000273 || (!defined(CONFIG_BF54x) && defined(CONFIG_BFIN_DCACHE))
144 min_cclk = sclk * 2; 144 min_cclk = sclk * 2;
@@ -152,7 +152,7 @@ static int __init __bfin_cpu_init(struct cpufreq_policy *policy)
152 dpm_state_table[index].csel = csel << 4; /* Shift now into PLL_DIV bitpos */ 152 dpm_state_table[index].csel = csel << 4; /* Shift now into PLL_DIV bitpos */
153 dpm_state_table[index].tscale = (TIME_SCALE / (1 << csel)) - 1; 153 dpm_state_table[index].tscale = (TIME_SCALE / (1 << csel)) - 1;
154 154
155 pr_debug("cpufreq: freq:%d csel:%d tscale:%d\n", 155 pr_debug("cpufreq: freq:%d csel:0x%x tscale:%d\n",
156 bfin_freq_table[index].frequency, 156 bfin_freq_table[index].frequency,
157 dpm_state_table[index].csel, 157 dpm_state_table[index].csel,
158 dpm_state_table[index].tscale); 158 dpm_state_table[index].tscale);
@@ -173,7 +173,7 @@ static struct freq_attr *bfin_freq_attr[] = {
173static struct cpufreq_driver bfin_driver = { 173static struct cpufreq_driver bfin_driver = {
174 .verify = bfin_verify_speed, 174 .verify = bfin_verify_speed,
175 .target = bfin_target, 175 .target = bfin_target,
176 .get = bfin_getfreq, 176 .get = bfin_getfreq_khz,
177 .init = __bfin_cpu_init, 177 .init = __bfin_cpu_init,
178 .name = "bfin cpufreq", 178 .name = "bfin cpufreq",
179 .owner = THIS_MODULE, 179 .owner = THIS_MODULE,
diff --git a/arch/blackfin/mach-common/entry.S b/arch/blackfin/mach-common/entry.S
index c13fa8da28c7..bde6dc4e2614 100644
--- a/arch/blackfin/mach-common/entry.S
+++ b/arch/blackfin/mach-common/entry.S
@@ -277,7 +277,7 @@ ENTRY(_bfin_return_from_exception)
277 p5.h = hi(ILAT); 277 p5.h = hi(ILAT);
278 r6 = [p5]; 278 r6 = [p5];
279 r7 = 0x20; /* Did I just cause anther HW error? */ 279 r7 = 0x20; /* Did I just cause anther HW error? */
280 r7 = r7 & r1; 280 r6 = r7 & r6;
281 CC = R7 == R6; 281 CC = R7 == R6;
282 if CC JUMP _double_fault; 282 if CC JUMP _double_fault;
283#endif 283#endif
diff --git a/arch/blackfin/mm/sram-alloc.c b/arch/blackfin/mm/sram-alloc.c
index 0f1ca6930c16..cc6f336e7313 100644
--- a/arch/blackfin/mm/sram-alloc.c
+++ b/arch/blackfin/mm/sram-alloc.c
@@ -183,10 +183,10 @@ static void __init l2_sram_init(void)
183 return; 183 return;
184 } 184 }
185 185
186 free_l2_sram_head.next->paddr = (void *)L2_START + 186 free_l2_sram_head.next->paddr =
187 (_etext_l2 - _stext_l2) + (_edata_l2 - _sdata_l2); 187 (void *)L2_START + (_ebss_l2 - _stext_l2);
188 free_l2_sram_head.next->size = L2_LENGTH - 188 free_l2_sram_head.next->size =
189 (_etext_l2 - _stext_l2) + (_edata_l2 - _sdata_l2); 189 L2_LENGTH - (_ebss_l2 - _stext_l2);
190 free_l2_sram_head.next->pid = 0; 190 free_l2_sram_head.next->pid = 0;
191 free_l2_sram_head.next->next = NULL; 191 free_l2_sram_head.next->next = NULL;
192 192
diff --git a/arch/ia64/kvm/Kconfig b/arch/ia64/kvm/Kconfig
index 8e99fed6b3fd..f833a0b4188d 100644
--- a/arch/ia64/kvm/Kconfig
+++ b/arch/ia64/kvm/Kconfig
@@ -20,6 +20,8 @@ if VIRTUALIZATION
20config KVM 20config KVM
21 tristate "Kernel-based Virtual Machine (KVM) support" 21 tristate "Kernel-based Virtual Machine (KVM) support"
22 depends on HAVE_KVM && EXPERIMENTAL 22 depends on HAVE_KVM && EXPERIMENTAL
23 # for device assignment:
24 depends on PCI
23 select PREEMPT_NOTIFIERS 25 select PREEMPT_NOTIFIERS
24 select ANON_INODES 26 select ANON_INODES
25 ---help--- 27 ---help---
diff --git a/arch/ia64/kvm/kvm-ia64.c b/arch/ia64/kvm/kvm-ia64.c
index 3caac477de9e..af1464f7a6ad 100644
--- a/arch/ia64/kvm/kvm-ia64.c
+++ b/arch/ia64/kvm/kvm-ia64.c
@@ -673,16 +673,16 @@ int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
673 673
674 vcpu_load(vcpu); 674 vcpu_load(vcpu);
675 675
676 if (vcpu->sigset_active)
677 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
678
676 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) { 679 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
677 kvm_vcpu_block(vcpu); 680 kvm_vcpu_block(vcpu);
678 clear_bit(KVM_REQ_UNHALT, &vcpu->requests); 681 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
679 vcpu_put(vcpu); 682 r = -EAGAIN;
680 return -EAGAIN; 683 goto out;
681 } 684 }
682 685
683 if (vcpu->sigset_active)
684 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
685
686 if (vcpu->mmio_needed) { 686 if (vcpu->mmio_needed) {
687 memcpy(vcpu->mmio_data, kvm_run->mmio.data, 8); 687 memcpy(vcpu->mmio_data, kvm_run->mmio.data, 8);
688 kvm_set_mmio_data(vcpu); 688 kvm_set_mmio_data(vcpu);
@@ -690,7 +690,7 @@ int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
690 vcpu->mmio_needed = 0; 690 vcpu->mmio_needed = 0;
691 } 691 }
692 r = __vcpu_run(vcpu, kvm_run); 692 r = __vcpu_run(vcpu, kvm_run);
693 693out:
694 if (vcpu->sigset_active) 694 if (vcpu->sigset_active)
695 sigprocmask(SIG_SETMASK, &sigsaved, NULL); 695 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
696 696
diff --git a/arch/ia64/kvm/vcpu.h b/arch/ia64/kvm/vcpu.h
index 341e3fee280c..e9b2a4e121c0 100644
--- a/arch/ia64/kvm/vcpu.h
+++ b/arch/ia64/kvm/vcpu.h
@@ -384,6 +384,10 @@ static inline u64 __gpfn_is_io(u64 gpfn)
384#define MODE_IND(psr) \ 384#define MODE_IND(psr) \
385 (((psr).it << 2) + ((psr).dt << 1) + (psr).rt) 385 (((psr).it << 2) + ((psr).dt << 1) + (psr).rt)
386 386
387#ifndef CONFIG_SMP
388#define _vmm_raw_spin_lock(x) do {}while(0)
389#define _vmm_raw_spin_unlock(x) do {}while(0)
390#else
387#define _vmm_raw_spin_lock(x) \ 391#define _vmm_raw_spin_lock(x) \
388 do { \ 392 do { \
389 __u32 *ia64_spinlock_ptr = (__u32 *) (x); \ 393 __u32 *ia64_spinlock_ptr = (__u32 *) (x); \
@@ -403,6 +407,7 @@ static inline u64 __gpfn_is_io(u64 gpfn)
403 do { barrier(); \ 407 do { barrier(); \
404 ((spinlock_t *)x)->raw_lock.lock = 0; } \ 408 ((spinlock_t *)x)->raw_lock.lock = 0; } \
405while (0) 409while (0)
410#endif
406 411
407void vmm_spin_lock(spinlock_t *lock); 412void vmm_spin_lock(spinlock_t *lock);
408void vmm_spin_unlock(spinlock_t *lock); 413void vmm_spin_unlock(spinlock_t *lock);
diff --git a/arch/m68k/kernel/ints.c b/arch/m68k/kernel/ints.c
index 7e8a0d394e61..761ee0440c99 100644
--- a/arch/m68k/kernel/ints.c
+++ b/arch/m68k/kernel/ints.c
@@ -133,7 +133,7 @@ void __init m68k_setup_user_interrupt(unsigned int vec, unsigned int cnt,
133{ 133{
134 int i; 134 int i;
135 135
136 BUG_ON(IRQ_USER + cnt >= NR_IRQS); 136 BUG_ON(IRQ_USER + cnt > NR_IRQS);
137 m68k_first_user_vec = vec; 137 m68k_first_user_vec = vec;
138 for (i = 0; i < cnt; i++) 138 for (i = 0; i < cnt; i++)
139 irq_controller[IRQ_USER + i] = &user_irq_controller; 139 irq_controller[IRQ_USER + i] = &user_irq_controller;
diff --git a/arch/mn10300/Kconfig.debug b/arch/mn10300/Kconfig.debug
index 524e33819f32..ff80e86b9bd2 100644
--- a/arch/mn10300/Kconfig.debug
+++ b/arch/mn10300/Kconfig.debug
@@ -15,6 +15,15 @@ config DEBUG_DECOMPRESS_KERNEL
15 decompressing Linux seeing "Uncompressing Linux... " and 15 decompressing Linux seeing "Uncompressing Linux... " and
16 "Ok, booting the kernel.\n" on console. 16 "Ok, booting the kernel.\n" on console.
17 17
18config TEST_MISALIGNMENT_HANDLER
19 bool "Run tests on the misalignment handler"
20 depends on DEBUG_KERNEL
21 default n
22 help
23 If you say Y here the kernel will execute a list of misaligned memory
24 accesses to make sure the misalignment handler deals them with
25 correctly. If it does not, the kernel will throw a BUG.
26
18config KPROBES 27config KPROBES
19 bool "Kprobes" 28 bool "Kprobes"
20 depends on DEBUG_KERNEL 29 depends on DEBUG_KERNEL
diff --git a/arch/mn10300/mm/misalignment.c b/arch/mn10300/mm/misalignment.c
index 32aa89dc3848..94c4a4358065 100644
--- a/arch/mn10300/mm/misalignment.c
+++ b/arch/mn10300/mm/misalignment.c
@@ -37,26 +37,22 @@
37#include <asm/asm-offsets.h> 37#include <asm/asm-offsets.h>
38 38
39#if 0 39#if 0
40#define kdebug(FMT, ...) printk(KERN_DEBUG FMT, ##__VA_ARGS__) 40#define kdebug(FMT, ...) printk(KERN_DEBUG "MISALIGN: "FMT"\n", ##__VA_ARGS__)
41#else 41#else
42#define kdebug(FMT, ...) do {} while (0) 42#define kdebug(FMT, ...) do {} while (0)
43#endif 43#endif
44 44
45static int misalignment_addr(unsigned long *registers, unsigned params, 45static int misalignment_addr(unsigned long *registers, unsigned long sp,
46 unsigned opcode, unsigned disp, 46 unsigned params, unsigned opcode,
47 void **_address, unsigned long **_postinc); 47 unsigned long disp,
48 void **_address, unsigned long **_postinc,
49 unsigned long *_inc);
48 50
49static int misalignment_reg(unsigned long *registers, unsigned params, 51static int misalignment_reg(unsigned long *registers, unsigned params,
50 unsigned opcode, unsigned disp, 52 unsigned opcode, unsigned long disp,
51 unsigned long **_register); 53 unsigned long **_register);
52 54
53static inline unsigned int_log2(unsigned x) 55static void misalignment_MOV_Lcc(struct pt_regs *regs, uint32_t opcode);
54{
55 unsigned y;
56 asm("bsch %1,%0" : "=r"(y) : "r"(x), "0"(0));
57 return y;
58}
59#define log2(x) int_log2(x)
60 56
61static const unsigned Dreg_index[] = { 57static const unsigned Dreg_index[] = {
62 REG_D0 >> 2, REG_D1 >> 2, REG_D2 >> 2, REG_D3 >> 2 58 REG_D0 >> 2, REG_D1 >> 2, REG_D2 >> 2, REG_D3 >> 2
@@ -86,9 +82,10 @@ enum format_id {
86 FMT_D7, 82 FMT_D7,
87 FMT_D8, 83 FMT_D8,
88 FMT_D9, 84 FMT_D9,
85 FMT_D10,
89}; 86};
90 87
91struct { 88static const struct {
92 u_int8_t opsz, dispsz; 89 u_int8_t opsz, dispsz;
93} format_tbl[16] = { 90} format_tbl[16] = {
94 [FMT_S0] = { 8, 0 }, 91 [FMT_S0] = { 8, 0 },
@@ -103,6 +100,7 @@ struct {
103 [FMT_D7] = { 24, 8 }, 100 [FMT_D7] = { 24, 8 },
104 [FMT_D8] = { 24, 24 }, 101 [FMT_D8] = { 24, 24 },
105 [FMT_D9] = { 24, 32 }, 102 [FMT_D9] = { 24, 32 },
103 [FMT_D10] = { 32, 0 },
106}; 104};
107 105
108enum value_id { 106enum value_id {
@@ -128,9 +126,14 @@ enum value_id {
128 SD24, /* 24-bit signed displacement */ 126 SD24, /* 24-bit signed displacement */
129 SIMM4_2, /* 4-bit signed displacement in opcode bits 4-7 */ 127 SIMM4_2, /* 4-bit signed displacement in opcode bits 4-7 */
130 SIMM8, /* 8-bit signed immediate */ 128 SIMM8, /* 8-bit signed immediate */
129 IMM8, /* 8-bit unsigned immediate */
130 IMM16, /* 16-bit unsigned immediate */
131 IMM24, /* 24-bit unsigned immediate */ 131 IMM24, /* 24-bit unsigned immediate */
132 IMM32, /* 32-bit unsigned immediate */ 132 IMM32, /* 32-bit unsigned immediate */
133 IMM32_HIGH8, /* 32-bit unsigned immediate, high 8-bits in opcode */ 133 IMM32_HIGH8, /* 32-bit unsigned immediate, LSB in opcode */
134
135 IMM32_MEM, /* 32-bit unsigned displacement */
136 IMM32_HIGH8_MEM, /* 32-bit unsigned displacement, LSB in opcode */
134 137
135 DN0 = DM0, 138 DN0 = DM0,
136 DN1 = DM1, 139 DN1 = DM1,
@@ -149,7 +152,7 @@ enum value_id {
149}; 152};
150 153
151struct mn10300_opcode { 154struct mn10300_opcode {
152 const char *name; 155 const char name[8];
153 u_int32_t opcode; 156 u_int32_t opcode;
154 u_int32_t opmask; 157 u_int32_t opmask;
155 unsigned exclusion; 158 unsigned exclusion;
@@ -185,6 +188,10 @@ struct mn10300_opcode {
185 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. 188 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
186*/ 189*/
187static const struct mn10300_opcode mn10300_opcodes[] = { 190static const struct mn10300_opcode mn10300_opcodes[] = {
191{ "mov", 0x4200, 0xf300, 0, FMT_S1, 0, {DM1, MEM2(IMM8, SP)}},
192{ "mov", 0x4300, 0xf300, 0, FMT_S1, 0, {AM1, MEM2(IMM8, SP)}},
193{ "mov", 0x5800, 0xfc00, 0, FMT_S1, 0, {MEM2(IMM8, SP), DN0}},
194{ "mov", 0x5c00, 0xfc00, 0, FMT_S1, 0, {MEM2(IMM8, SP), AN0}},
188{ "mov", 0x60, 0xf0, 0, FMT_S0, 0, {DM1, MEM(AN0)}}, 195{ "mov", 0x60, 0xf0, 0, FMT_S0, 0, {DM1, MEM(AN0)}},
189{ "mov", 0x70, 0xf0, 0, FMT_S0, 0, {MEM(AM0), DN1}}, 196{ "mov", 0x70, 0xf0, 0, FMT_S0, 0, {MEM(AM0), DN1}},
190{ "mov", 0xf000, 0xfff0, 0, FMT_D0, 0, {MEM(AM0), AN1}}, 197{ "mov", 0xf000, 0xfff0, 0, FMT_D0, 0, {MEM(AM0), AN1}},
@@ -197,8 +204,6 @@ static const struct mn10300_opcode mn10300_opcodes[] = {
197{ "mov", 0xf81000, 0xfff000, 0, FMT_D1, 0, {DM1, MEM2(SD8, AN0)}}, 204{ "mov", 0xf81000, 0xfff000, 0, FMT_D1, 0, {DM1, MEM2(SD8, AN0)}},
198{ "mov", 0xf82000, 0xfff000, 0, FMT_D1, 0, {MEM2(SD8,AM0), AN1}}, 205{ "mov", 0xf82000, 0xfff000, 0, FMT_D1, 0, {MEM2(SD8,AM0), AN1}},
199{ "mov", 0xf83000, 0xfff000, 0, FMT_D1, 0, {AM1, MEM2(SD8, AN0)}}, 206{ "mov", 0xf83000, 0xfff000, 0, FMT_D1, 0, {AM1, MEM2(SD8, AN0)}},
200{ "mov", 0xf8f000, 0xfffc00, 0, FMT_D1, AM33, {MEM2(SD8, AM0), SP}},
201{ "mov", 0xf8f400, 0xfffc00, 0, FMT_D1, AM33, {SP, MEM2(SD8, AN0)}},
202{ "mov", 0xf90a00, 0xffff00, 0, FMT_D6, AM33, {MEM(RM0), RN2}}, 207{ "mov", 0xf90a00, 0xffff00, 0, FMT_D6, AM33, {MEM(RM0), RN2}},
203{ "mov", 0xf91a00, 0xffff00, 0, FMT_D6, AM33, {RM2, MEM(RN0)}}, 208{ "mov", 0xf91a00, 0xffff00, 0, FMT_D6, AM33, {RM2, MEM(RN0)}},
204{ "mov", 0xf96a00, 0xffff00, 0x12, FMT_D6, AM33, {MEMINC(RM0), RN2}}, 209{ "mov", 0xf96a00, 0xffff00, 0x12, FMT_D6, AM33, {MEMINC(RM0), RN2}},
@@ -207,24 +212,46 @@ static const struct mn10300_opcode mn10300_opcodes[] = {
207{ "mov", 0xfa100000, 0xfff00000, 0, FMT_D2, 0, {DM1, MEM2(SD16, AN0)}}, 212{ "mov", 0xfa100000, 0xfff00000, 0, FMT_D2, 0, {DM1, MEM2(SD16, AN0)}},
208{ "mov", 0xfa200000, 0xfff00000, 0, FMT_D2, 0, {MEM2(SD16, AM0), AN1}}, 213{ "mov", 0xfa200000, 0xfff00000, 0, FMT_D2, 0, {MEM2(SD16, AM0), AN1}},
209{ "mov", 0xfa300000, 0xfff00000, 0, FMT_D2, 0, {AM1, MEM2(SD16, AN0)}}, 214{ "mov", 0xfa300000, 0xfff00000, 0, FMT_D2, 0, {AM1, MEM2(SD16, AN0)}},
215{ "mov", 0xfa900000, 0xfff30000, 0, FMT_D2, 0, {AM1, MEM2(IMM16, SP)}},
216{ "mov", 0xfa910000, 0xfff30000, 0, FMT_D2, 0, {DM1, MEM2(IMM16, SP)}},
217{ "mov", 0xfab00000, 0xfffc0000, 0, FMT_D2, 0, {MEM2(IMM16, SP), AN0}},
218{ "mov", 0xfab40000, 0xfffc0000, 0, FMT_D2, 0, {MEM2(IMM16, SP), DN0}},
210{ "mov", 0xfb0a0000, 0xffff0000, 0, FMT_D7, AM33, {MEM2(SD8, RM0), RN2}}, 219{ "mov", 0xfb0a0000, 0xffff0000, 0, FMT_D7, AM33, {MEM2(SD8, RM0), RN2}},
211{ "mov", 0xfb1a0000, 0xffff0000, 0, FMT_D7, AM33, {RM2, MEM2(SD8, RN0)}}, 220{ "mov", 0xfb1a0000, 0xffff0000, 0, FMT_D7, AM33, {RM2, MEM2(SD8, RN0)}},
212{ "mov", 0xfb6a0000, 0xffff0000, 0x22, FMT_D7, AM33, {MEMINC2 (RM0, SIMM8), RN2}}, 221{ "mov", 0xfb6a0000, 0xffff0000, 0x22, FMT_D7, AM33, {MEMINC2 (RM0, SIMM8), RN2}},
213{ "mov", 0xfb7a0000, 0xffff0000, 0, FMT_D7, AM33, {RM2, MEMINC2 (RN0, SIMM8)}}, 222{ "mov", 0xfb7a0000, 0xffff0000, 0, FMT_D7, AM33, {RM2, MEMINC2 (RN0, SIMM8)}},
223{ "mov", 0xfb8a0000, 0xffff0f00, 0, FMT_D7, AM33, {MEM2(IMM8, SP), RN2}},
214{ "mov", 0xfb8e0000, 0xffff000f, 0, FMT_D7, AM33, {MEM2(RI, RM0), RD2}}, 224{ "mov", 0xfb8e0000, 0xffff000f, 0, FMT_D7, AM33, {MEM2(RI, RM0), RD2}},
225{ "mov", 0xfb9a0000, 0xffff0f00, 0, FMT_D7, AM33, {RM2, MEM2(IMM8, SP)}},
215{ "mov", 0xfb9e0000, 0xffff000f, 0, FMT_D7, AM33, {RD2, MEM2(RI, RN0)}}, 226{ "mov", 0xfb9e0000, 0xffff000f, 0, FMT_D7, AM33, {RD2, MEM2(RI, RN0)}},
216{ "mov", 0xfc000000, 0xfff00000, 0, FMT_D4, 0, {MEM2(IMM32,AM0), DN1}}, 227{ "mov", 0xfc000000, 0xfff00000, 0, FMT_D4, 0, {MEM2(IMM32,AM0), DN1}},
217{ "mov", 0xfc100000, 0xfff00000, 0, FMT_D4, 0, {DM1, MEM2(IMM32,AN0)}}, 228{ "mov", 0xfc100000, 0xfff00000, 0, FMT_D4, 0, {DM1, MEM2(IMM32,AN0)}},
218{ "mov", 0xfc200000, 0xfff00000, 0, FMT_D4, 0, {MEM2(IMM32,AM0), AN1}}, 229{ "mov", 0xfc200000, 0xfff00000, 0, FMT_D4, 0, {MEM2(IMM32,AM0), AN1}},
219{ "mov", 0xfc300000, 0xfff00000, 0, FMT_D4, 0, {AM1, MEM2(IMM32,AN0)}}, 230{ "mov", 0xfc300000, 0xfff00000, 0, FMT_D4, 0, {AM1, MEM2(IMM32,AN0)}},
231{ "mov", 0xfc800000, 0xfff30000, 0, FMT_D4, 0, {AM1, MEM(IMM32_MEM)}},
232{ "mov", 0xfc810000, 0xfff30000, 0, FMT_D4, 0, {DM1, MEM(IMM32_MEM)}},
233{ "mov", 0xfc900000, 0xfff30000, 0, FMT_D4, 0, {AM1, MEM2(IMM32, SP)}},
234{ "mov", 0xfc910000, 0xfff30000, 0, FMT_D4, 0, {DM1, MEM2(IMM32, SP)}},
235{ "mov", 0xfca00000, 0xfffc0000, 0, FMT_D4, 0, {MEM(IMM32_MEM), AN0}},
236{ "mov", 0xfca40000, 0xfffc0000, 0, FMT_D4, 0, {MEM(IMM32_MEM), DN0}},
237{ "mov", 0xfcb00000, 0xfffc0000, 0, FMT_D4, 0, {MEM2(IMM32, SP), AN0}},
238{ "mov", 0xfcb40000, 0xfffc0000, 0, FMT_D4, 0, {MEM2(IMM32, SP), DN0}},
220{ "mov", 0xfd0a0000, 0xffff0000, 0, FMT_D8, AM33, {MEM2(SD24, RM0), RN2}}, 239{ "mov", 0xfd0a0000, 0xffff0000, 0, FMT_D8, AM33, {MEM2(SD24, RM0), RN2}},
221{ "mov", 0xfd1a0000, 0xffff0000, 0, FMT_D8, AM33, {RM2, MEM2(SD24, RN0)}}, 240{ "mov", 0xfd1a0000, 0xffff0000, 0, FMT_D8, AM33, {RM2, MEM2(SD24, RN0)}},
222{ "mov", 0xfd6a0000, 0xffff0000, 0x22, FMT_D8, AM33, {MEMINC2 (RM0, IMM24), RN2}}, 241{ "mov", 0xfd6a0000, 0xffff0000, 0x22, FMT_D8, AM33, {MEMINC2 (RM0, IMM24), RN2}},
223{ "mov", 0xfd7a0000, 0xffff0000, 0, FMT_D8, AM33, {RM2, MEMINC2 (RN0, IMM24)}}, 242{ "mov", 0xfd7a0000, 0xffff0000, 0, FMT_D8, AM33, {RM2, MEMINC2 (RN0, IMM24)}},
243{ "mov", 0xfd8a0000, 0xffff0f00, 0, FMT_D8, AM33, {MEM2(IMM24, SP), RN2}},
244{ "mov", 0xfd9a0000, 0xffff0f00, 0, FMT_D8, AM33, {RM2, MEM2(IMM24, SP)}},
224{ "mov", 0xfe0a0000, 0xffff0000, 0, FMT_D9, AM33, {MEM2(IMM32_HIGH8,RM0), RN2}}, 245{ "mov", 0xfe0a0000, 0xffff0000, 0, FMT_D9, AM33, {MEM2(IMM32_HIGH8,RM0), RN2}},
246{ "mov", 0xfe0a0000, 0xffff0000, 0, FMT_D9, AM33, {MEM2(IMM32_HIGH8,RM0), RN2}},
247{ "mov", 0xfe0e0000, 0xffff0f00, 0, FMT_D9, AM33, {MEM(IMM32_HIGH8_MEM), RN2}},
248{ "mov", 0xfe1a0000, 0xffff0000, 0, FMT_D9, AM33, {RM2, MEM2(IMM32_HIGH8, RN0)}},
225{ "mov", 0xfe1a0000, 0xffff0000, 0, FMT_D9, AM33, {RM2, MEM2(IMM32_HIGH8, RN0)}}, 249{ "mov", 0xfe1a0000, 0xffff0000, 0, FMT_D9, AM33, {RM2, MEM2(IMM32_HIGH8, RN0)}},
250{ "mov", 0xfe1e0000, 0xffff0f00, 0, FMT_D9, AM33, {RM2, MEM(IMM32_HIGH8_MEM)}},
226{ "mov", 0xfe6a0000, 0xffff0000, 0x22, FMT_D9, AM33, {MEMINC2 (RM0, IMM32_HIGH8), RN2}}, 251{ "mov", 0xfe6a0000, 0xffff0000, 0x22, FMT_D9, AM33, {MEMINC2 (RM0, IMM32_HIGH8), RN2}},
227{ "mov", 0xfe7a0000, 0xffff0000, 0, FMT_D9, AM33, {RN2, MEMINC2 (RM0, IMM32_HIGH8)}}, 252{ "mov", 0xfe7a0000, 0xffff0000, 0, FMT_D9, AM33, {RN2, MEMINC2 (RM0, IMM32_HIGH8)}},
253{ "mov", 0xfe8a0000, 0xffff0f00, 0, FMT_D9, AM33, {MEM2(IMM32_HIGH8, SP), RN2}},
254{ "mov", 0xfe9a0000, 0xffff0f00, 0, FMT_D9, AM33, {RM2, MEM2(IMM32_HIGH8, SP)}},
228 255
229{ "movhu", 0xf060, 0xfff0, 0, FMT_D0, 0, {MEM(AM0), DN1}}, 256{ "movhu", 0xf060, 0xfff0, 0, FMT_D0, 0, {MEM(AM0), DN1}},
230{ "movhu", 0xf070, 0xfff0, 0, FMT_D0, 0, {DM1, MEM(AN0)}}, 257{ "movhu", 0xf070, 0xfff0, 0, FMT_D0, 0, {DM1, MEM(AN0)}},
@@ -232,29 +259,58 @@ static const struct mn10300_opcode mn10300_opcodes[] = {
232{ "movhu", 0xf4c0, 0xffc0, 0, FMT_D0, 0, {DM2, MEM2(DI, AN0)}}, 259{ "movhu", 0xf4c0, 0xffc0, 0, FMT_D0, 0, {DM2, MEM2(DI, AN0)}},
233{ "movhu", 0xf86000, 0xfff000, 0, FMT_D1, 0, {MEM2(SD8, AM0), DN1}}, 260{ "movhu", 0xf86000, 0xfff000, 0, FMT_D1, 0, {MEM2(SD8, AM0), DN1}},
234{ "movhu", 0xf87000, 0xfff000, 0, FMT_D1, 0, {DM1, MEM2(SD8, AN0)}}, 261{ "movhu", 0xf87000, 0xfff000, 0, FMT_D1, 0, {DM1, MEM2(SD8, AN0)}},
262{ "movhu", 0xf89300, 0xfff300, 0, FMT_D1, 0, {DM1, MEM2(IMM8, SP)}},
263{ "movhu", 0xf8bc00, 0xfffc00, 0, FMT_D1, 0, {MEM2(IMM8, SP), DN0}},
235{ "movhu", 0xf94a00, 0xffff00, 0, FMT_D6, AM33, {MEM(RM0), RN2}}, 264{ "movhu", 0xf94a00, 0xffff00, 0, FMT_D6, AM33, {MEM(RM0), RN2}},
236{ "movhu", 0xf95a00, 0xffff00, 0, FMT_D6, AM33, {RM2, MEM(RN0)}}, 265{ "movhu", 0xf95a00, 0xffff00, 0, FMT_D6, AM33, {RM2, MEM(RN0)}},
237{ "movhu", 0xf9ea00, 0xffff00, 0x12, FMT_D6, AM33, {MEMINC(RM0), RN2}}, 266{ "movhu", 0xf9ea00, 0xffff00, 0x12, FMT_D6, AM33, {MEMINC(RM0), RN2}},
238{ "movhu", 0xf9fa00, 0xffff00, 0, FMT_D6, AM33, {RM2, MEMINC(RN0)}}, 267{ "movhu", 0xf9fa00, 0xffff00, 0, FMT_D6, AM33, {RM2, MEMINC(RN0)}},
239{ "movhu", 0xfa600000, 0xfff00000, 0, FMT_D2, 0, {MEM2(SD16, AM0), DN1}}, 268{ "movhu", 0xfa600000, 0xfff00000, 0, FMT_D2, 0, {MEM2(SD16, AM0), DN1}},
240{ "movhu", 0xfa700000, 0xfff00000, 0, FMT_D2, 0, {DM1, MEM2(SD16, AN0)}}, 269{ "movhu", 0xfa700000, 0xfff00000, 0, FMT_D2, 0, {DM1, MEM2(SD16, AN0)}},
270{ "movhu", 0xfa930000, 0xfff30000, 0, FMT_D2, 0, {DM1, MEM2(IMM16, SP)}},
271{ "movhu", 0xfabc0000, 0xfffc0000, 0, FMT_D2, 0, {MEM2(IMM16, SP), DN0}},
241{ "movhu", 0xfb4a0000, 0xffff0000, 0, FMT_D7, AM33, {MEM2(SD8, RM0), RN2}}, 272{ "movhu", 0xfb4a0000, 0xffff0000, 0, FMT_D7, AM33, {MEM2(SD8, RM0), RN2}},
242{ "movhu", 0xfb5a0000, 0xffff0000, 0, FMT_D7, AM33, {RM2, MEM2(SD8, RN0)}}, 273{ "movhu", 0xfb5a0000, 0xffff0000, 0, FMT_D7, AM33, {RM2, MEM2(SD8, RN0)}},
274{ "movhu", 0xfbca0000, 0xffff0f00, 0, FMT_D7, AM33, {MEM2(IMM8, SP), RN2}},
243{ "movhu", 0xfbce0000, 0xffff000f, 0, FMT_D7, AM33, {MEM2(RI, RM0), RD2}}, 275{ "movhu", 0xfbce0000, 0xffff000f, 0, FMT_D7, AM33, {MEM2(RI, RM0), RD2}},
276{ "movhu", 0xfbda0000, 0xffff0f00, 0, FMT_D7, AM33, {RM2, MEM2(IMM8, SP)}},
244{ "movhu", 0xfbde0000, 0xffff000f, 0, FMT_D7, AM33, {RD2, MEM2(RI, RN0)}}, 277{ "movhu", 0xfbde0000, 0xffff000f, 0, FMT_D7, AM33, {RD2, MEM2(RI, RN0)}},
245{ "movhu", 0xfbea0000, 0xffff0000, 0x22, FMT_D7, AM33, {MEMINC2 (RM0, SIMM8), RN2}}, 278{ "movhu", 0xfbea0000, 0xffff0000, 0x22, FMT_D7, AM33, {MEMINC2 (RM0, SIMM8), RN2}},
246{ "movhu", 0xfbfa0000, 0xffff0000, 0, FMT_D7, AM33, {RM2, MEMINC2 (RN0, SIMM8)}}, 279{ "movhu", 0xfbfa0000, 0xffff0000, 0, FMT_D7, AM33, {RM2, MEMINC2 (RN0, SIMM8)}},
247{ "movhu", 0xfc600000, 0xfff00000, 0, FMT_D4, 0, {MEM2(IMM32,AM0), DN1}}, 280{ "movhu", 0xfc600000, 0xfff00000, 0, FMT_D4, 0, {MEM2(IMM32,AM0), DN1}},
248{ "movhu", 0xfc700000, 0xfff00000, 0, FMT_D4, 0, {DM1, MEM2(IMM32,AN0)}}, 281{ "movhu", 0xfc700000, 0xfff00000, 0, FMT_D4, 0, {DM1, MEM2(IMM32,AN0)}},
282{ "movhu", 0xfc830000, 0xfff30000, 0, FMT_D4, 0, {DM1, MEM(IMM32_MEM)}},
283{ "movhu", 0xfc930000, 0xfff30000, 0, FMT_D4, 0, {DM1, MEM2(IMM32, SP)}},
284{ "movhu", 0xfcac0000, 0xfffc0000, 0, FMT_D4, 0, {MEM(IMM32_MEM), DN0}},
285{ "movhu", 0xfcbc0000, 0xfffc0000, 0, FMT_D4, 0, {MEM2(IMM32, SP), DN0}},
249{ "movhu", 0xfd4a0000, 0xffff0000, 0, FMT_D8, AM33, {MEM2(SD24, RM0), RN2}}, 286{ "movhu", 0xfd4a0000, 0xffff0000, 0, FMT_D8, AM33, {MEM2(SD24, RM0), RN2}},
250{ "movhu", 0xfd5a0000, 0xffff0000, 0, FMT_D8, AM33, {RM2, MEM2(SD24, RN0)}}, 287{ "movhu", 0xfd5a0000, 0xffff0000, 0, FMT_D8, AM33, {RM2, MEM2(SD24, RN0)}},
288{ "movhu", 0xfdca0000, 0xffff0f00, 0, FMT_D8, AM33, {MEM2(IMM24, SP), RN2}},
289{ "movhu", 0xfdda0000, 0xffff0f00, 0, FMT_D8, AM33, {RM2, MEM2(IMM24, SP)}},
251{ "movhu", 0xfdea0000, 0xffff0000, 0x22, FMT_D8, AM33, {MEMINC2 (RM0, IMM24), RN2}}, 290{ "movhu", 0xfdea0000, 0xffff0000, 0x22, FMT_D8, AM33, {MEMINC2 (RM0, IMM24), RN2}},
252{ "movhu", 0xfdfa0000, 0xffff0000, 0, FMT_D8, AM33, {RM2, MEMINC2 (RN0, IMM24)}}, 291{ "movhu", 0xfdfa0000, 0xffff0000, 0, FMT_D8, AM33, {RM2, MEMINC2 (RN0, IMM24)}},
253{ "movhu", 0xfe4a0000, 0xffff0000, 0, FMT_D9, AM33, {MEM2(IMM32_HIGH8,RM0), RN2}}, 292{ "movhu", 0xfe4a0000, 0xffff0000, 0, FMT_D9, AM33, {MEM2(IMM32_HIGH8,RM0), RN2}},
293{ "movhu", 0xfe4e0000, 0xffff0f00, 0, FMT_D9, AM33, {MEM(IMM32_HIGH8_MEM), RN2}},
254{ "movhu", 0xfe5a0000, 0xffff0000, 0, FMT_D9, AM33, {RM2, MEM2(IMM32_HIGH8, RN0)}}, 294{ "movhu", 0xfe5a0000, 0xffff0000, 0, FMT_D9, AM33, {RM2, MEM2(IMM32_HIGH8, RN0)}},
295{ "movhu", 0xfe5e0000, 0xffff0f00, 0, FMT_D9, AM33, {RM2, MEM(IMM32_HIGH8_MEM)}},
296{ "movhu", 0xfeca0000, 0xffff0f00, 0, FMT_D9, AM33, {MEM2(IMM32_HIGH8, SP), RN2}},
297{ "movhu", 0xfeda0000, 0xffff0f00, 0, FMT_D9, AM33, {RM2, MEM2(IMM32_HIGH8, SP)}},
255{ "movhu", 0xfeea0000, 0xffff0000, 0x22, FMT_D9, AM33, {MEMINC2 (RM0, IMM32_HIGH8), RN2}}, 298{ "movhu", 0xfeea0000, 0xffff0000, 0x22, FMT_D9, AM33, {MEMINC2 (RM0, IMM32_HIGH8), RN2}},
256{ "movhu", 0xfefa0000, 0xffff0000, 0, FMT_D9, AM33, {RN2, MEMINC2 (RM0, IMM32_HIGH8)}}, 299{ "movhu", 0xfefa0000, 0xffff0000, 0, FMT_D9, AM33, {RN2, MEMINC2 (RM0, IMM32_HIGH8)}},
257{ 0, 0, 0, 0, 0, 0, {0}}, 300
301{ "mov_llt", 0xf7e00000, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}},
302{ "mov_lgt", 0xf7e00001, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}},
303{ "mov_lge", 0xf7e00002, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}},
304{ "mov_lle", 0xf7e00003, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}},
305{ "mov_lcs", 0xf7e00004, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}},
306{ "mov_lhi", 0xf7e00005, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}},
307{ "mov_lcc", 0xf7e00006, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}},
308{ "mov_lls", 0xf7e00007, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}},
309{ "mov_leq", 0xf7e00008, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}},
310{ "mov_lne", 0xf7e00009, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}},
311{ "mov_lra", 0xf7e0000a, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}},
312
313{ "", 0, 0, 0, 0, 0, {0}},
258}; 314};
259 315
260/* 316/*
@@ -265,18 +321,21 @@ asmlinkage void misalignment(struct pt_regs *regs, enum exception_code code)
265 const struct exception_table_entry *fixup; 321 const struct exception_table_entry *fixup;
266 const struct mn10300_opcode *pop; 322 const struct mn10300_opcode *pop;
267 unsigned long *registers = (unsigned long *) regs; 323 unsigned long *registers = (unsigned long *) regs;
268 unsigned long data, *store, *postinc; 324 unsigned long data, *store, *postinc, disp, inc, sp;
269 mm_segment_t seg; 325 mm_segment_t seg;
270 siginfo_t info; 326 siginfo_t info;
271 uint32_t opcode, disp, noc, xo, xm; 327 uint32_t opcode, noc, xo, xm;
272 uint8_t *pc, byte; 328 uint8_t *pc, byte, datasz;
273 void *address; 329 void *address;
274 unsigned tmp, npop; 330 unsigned tmp, npop, dispsz, loop;
331
332 /* we don't fix up userspace misalignment faults */
333 if (user_mode(regs))
334 goto bus_error;
275 335
276 kdebug("MISALIGN at %lx\n", regs->pc); 336 sp = (unsigned long) regs + sizeof(*regs);
277 337
278 if (in_interrupt()) 338 kdebug("==>misalignment({pc=%lx,sp=%lx})", regs->pc, sp);
279 die("Misalignment trap in interrupt context", regs, code);
280 339
281 if (regs->epsw & EPSW_IE) 340 if (regs->epsw & EPSW_IE)
282 asm volatile("or %0,epsw" : : "i"(EPSW_IE)); 341 asm volatile("or %0,epsw" : : "i"(EPSW_IE));
@@ -294,8 +353,8 @@ asmlinkage void misalignment(struct pt_regs *regs, enum exception_code code)
294 opcode = byte; 353 opcode = byte;
295 noc = 8; 354 noc = 8;
296 355
297 for (pop = mn10300_opcodes; pop->name; pop++) { 356 for (pop = mn10300_opcodes; pop->name[0]; pop++) {
298 npop = log2(pop->opcode | pop->opmask); 357 npop = ilog2(pop->opcode | pop->opmask);
299 if (npop <= 0 || npop > 31) 358 if (npop <= 0 || npop > 31)
300 continue; 359 continue;
301 npop = (npop + 8) & ~7; 360 npop = (npop + 8) & ~7;
@@ -328,15 +387,15 @@ asmlinkage void misalignment(struct pt_regs *regs, enum exception_code code)
328 } 387 }
329 388
330 /* didn't manage to find a fixup */ 389 /* didn't manage to find a fixup */
331 if (!user_mode(regs)) 390 printk(KERN_CRIT "MISALIGN: %lx: unsupported instruction %x\n",
332 printk(KERN_CRIT "MISALIGN: %lx: unsupported instruction %x\n", 391 regs->pc, opcode);
333 regs->pc, opcode);
334 392
335failed: 393failed:
336 set_fs(seg); 394 set_fs(seg);
337 if (die_if_no_fixup("misalignment error", regs, code)) 395 if (die_if_no_fixup("misalignment error", regs, code))
338 return; 396 return;
339 397
398bus_error:
340 info.si_signo = SIGBUS; 399 info.si_signo = SIGBUS;
341 info.si_errno = 0; 400 info.si_errno = 0;
342 info.si_code = BUS_ADRALN; 401 info.si_code = BUS_ADRALN;
@@ -346,31 +405,27 @@ failed:
346 405
347 /* error reading opcodes */ 406 /* error reading opcodes */
348fetch_error: 407fetch_error:
349 if (!user_mode(regs)) 408 printk(KERN_CRIT
350 printk(KERN_CRIT 409 "MISALIGN: %p: fault whilst reading instruction data\n",
351 "MISALIGN: %p: fault whilst reading instruction data\n", 410 pc);
352 pc);
353 goto failed; 411 goto failed;
354 412
355bad_addr_mode: 413bad_addr_mode:
356 if (!user_mode(regs)) 414 printk(KERN_CRIT
357 printk(KERN_CRIT 415 "MISALIGN: %lx: unsupported addressing mode %x\n",
358 "MISALIGN: %lx: unsupported addressing mode %x\n", 416 regs->pc, opcode);
359 regs->pc, opcode);
360 goto failed; 417 goto failed;
361 418
362bad_reg_mode: 419bad_reg_mode:
363 if (!user_mode(regs)) 420 printk(KERN_CRIT
364 printk(KERN_CRIT 421 "MISALIGN: %lx: unsupported register mode %x\n",
365 "MISALIGN: %lx: unsupported register mode %x\n", 422 regs->pc, opcode);
366 regs->pc, opcode);
367 goto failed; 423 goto failed;
368 424
369unsupported_instruction: 425unsupported_instruction:
370 if (!user_mode(regs)) 426 printk(KERN_CRIT
371 printk(KERN_CRIT 427 "MISALIGN: %lx: unsupported instruction %x (%s)\n",
372 "MISALIGN: %lx: unsupported instruction %x (%s)\n", 428 regs->pc, opcode, pop->name);
373 regs->pc, opcode, pop->name);
374 goto failed; 429 goto failed;
375 430
376transfer_failed: 431transfer_failed:
@@ -391,7 +446,7 @@ transfer_failed:
391 446
392 /* we matched the opcode */ 447 /* we matched the opcode */
393found_opcode: 448found_opcode:
394 kdebug("MISALIGN: %lx: %x==%x { %x, %x }\n", 449 kdebug("%lx: %x==%x { %x, %x }",
395 regs->pc, opcode, pop->opcode, pop->params[0], pop->params[1]); 450 regs->pc, opcode, pop->opcode, pop->params[0], pop->params[1]);
396 451
397 tmp = format_tbl[pop->format].opsz; 452 tmp = format_tbl[pop->format].opsz;
@@ -406,106 +461,108 @@ found_opcode:
406 461
407 /* grab the extra displacement (note it's LSB first) */ 462 /* grab the extra displacement (note it's LSB first) */
408 disp = 0; 463 disp = 0;
409 tmp = format_tbl[pop->format].dispsz >> 3; 464 dispsz = format_tbl[pop->format].dispsz;
410 while (tmp > 0) { 465 for (loop = 0; loop < dispsz; loop += 8) {
411 tmp--;
412 disp <<= 8;
413
414 pc++; 466 pc++;
415 if (__get_user(byte, pc) != 0) 467 if (__get_user(byte, pc) != 0)
416 goto fetch_error; 468 goto fetch_error;
417 disp |= byte; 469 disp |= byte << loop;
470 kdebug("{%p} disp[%02x]=%02x", pc, loop, byte);
418 } 471 }
419 472
473 kdebug("disp=%lx", disp);
474
420 set_fs(KERNEL_XDS); 475 set_fs(KERNEL_XDS);
421 if (fixup || regs->epsw & EPSW_nSL) 476 if (fixup)
422 set_fs(seg); 477 set_fs(seg);
423 478
424 tmp = (pop->params[0] ^ pop->params[1]) & 0x80000000; 479 tmp = (pop->params[0] ^ pop->params[1]) & 0x80000000;
425 if (!tmp) { 480 if (!tmp) {
426 if (!user_mode(regs)) 481 printk(KERN_CRIT
427 printk(KERN_CRIT 482 "MISALIGN: %lx: insn not move to/from memory %x\n",
428 "MISALIGN: %lx:" 483 regs->pc, opcode);
429 " insn not move to/from memory %x\n",
430 regs->pc, opcode);
431 goto failed; 484 goto failed;
432 } 485 }
433 486
487 /* determine the data transfer size of the move */
488 if (pop->name[3] == 0 || /* "mov" */
489 pop->name[4] == 'l') /* mov_lcc */
490 inc = datasz = 4;
491 else if (pop->name[3] == 'h') /* movhu */
492 inc = datasz = 2;
493 else
494 goto unsupported_instruction;
495
434 if (pop->params[0] & 0x80000000) { 496 if (pop->params[0] & 0x80000000) {
435 /* move memory to register */ 497 /* move memory to register */
436 if (!misalignment_addr(registers, pop->params[0], opcode, disp, 498 if (!misalignment_addr(registers, sp,
437 &address, &postinc)) 499 pop->params[0], opcode, disp,
500 &address, &postinc, &inc))
438 goto bad_addr_mode; 501 goto bad_addr_mode;
439 502
440 if (!misalignment_reg(registers, pop->params[1], opcode, disp, 503 if (!misalignment_reg(registers, pop->params[1], opcode, disp,
441 &store)) 504 &store))
442 goto bad_reg_mode; 505 goto bad_reg_mode;
443 506
444 if (strcmp(pop->name, "mov") == 0) { 507 kdebug("mov%u (%p),DARn", datasz, address);
445 kdebug("FIXUP: mov (%p),DARn\n", address); 508 if (copy_from_user(&data, (void *) address, datasz) != 0)
446 if (copy_from_user(&data, (void *) address, 4) != 0) 509 goto transfer_failed;
447 goto transfer_failed; 510 if (pop->params[0] & 0x1000000) {
448 if (pop->params[0] & 0x1000000) 511 kdebug("inc=%lx", inc);
449 *postinc += 4; 512 *postinc += inc;
450 } else if (strcmp(pop->name, "movhu") == 0) {
451 kdebug("FIXUP: movhu (%p),DARn\n", address);
452 data = 0;
453 if (copy_from_user(&data, (void *) address, 2) != 0)
454 goto transfer_failed;
455 if (pop->params[0] & 0x1000000)
456 *postinc += 2;
457 } else {
458 goto unsupported_instruction;
459 } 513 }
460 514
461 *store = data; 515 *store = data;
516 kdebug("loaded %lx", data);
462 } else { 517 } else {
463 /* move register to memory */ 518 /* move register to memory */
464 if (!misalignment_reg(registers, pop->params[0], opcode, disp, 519 if (!misalignment_reg(registers, pop->params[0], opcode, disp,
465 &store)) 520 &store))
466 goto bad_reg_mode; 521 goto bad_reg_mode;
467 522
468 if (!misalignment_addr(registers, pop->params[1], opcode, disp, 523 if (!misalignment_addr(registers, sp,
469 &address, &postinc)) 524 pop->params[1], opcode, disp,
525 &address, &postinc, &inc))
470 goto bad_addr_mode; 526 goto bad_addr_mode;
471 527
472 data = *store; 528 data = *store;
473 529
474 if (strcmp(pop->name, "mov") == 0) { 530 kdebug("mov%u %lx,(%p)", datasz, data, address);
475 kdebug("FIXUP: mov %lx,(%p)\n", data, address); 531 if (copy_to_user((void *) address, &data, datasz) != 0)
476 if (copy_to_user((void *) address, &data, 4) != 0) 532 goto transfer_failed;
477 goto transfer_failed; 533 if (pop->params[1] & 0x1000000)
478 if (pop->params[1] & 0x1000000) 534 *postinc += inc;
479 *postinc += 4;
480 } else if (strcmp(pop->name, "movhu") == 0) {
481 kdebug("FIXUP: movhu %hx,(%p)\n",
482 (uint16_t) data, address);
483 if (copy_to_user((void *) address, &data, 2) != 0)
484 goto transfer_failed;
485 if (pop->params[1] & 0x1000000)
486 *postinc += 2;
487 } else {
488 goto unsupported_instruction;
489 }
490 } 535 }
491 536
492 tmp = format_tbl[pop->format].opsz + format_tbl[pop->format].dispsz; 537 tmp = format_tbl[pop->format].opsz + format_tbl[pop->format].dispsz;
493 regs->pc += tmp >> 3; 538 regs->pc += tmp >> 3;
494 539
540 /* handle MOV_Lcc, which are currently the only FMT_D10 insns that
541 * access memory */
542 if (pop->format == FMT_D10)
543 misalignment_MOV_Lcc(regs, opcode);
544
495 set_fs(seg); 545 set_fs(seg);
496 return;
497} 546}
498 547
499/* 548/*
500 * determine the address that was being accessed 549 * determine the address that was being accessed
501 */ 550 */
502static int misalignment_addr(unsigned long *registers, unsigned params, 551static int misalignment_addr(unsigned long *registers, unsigned long sp,
503 unsigned opcode, unsigned disp, 552 unsigned params, unsigned opcode,
504 void **_address, unsigned long **_postinc) 553 unsigned long disp,
554 void **_address, unsigned long **_postinc,
555 unsigned long *_inc)
505{ 556{
506 unsigned long *postinc = NULL, address = 0, tmp; 557 unsigned long *postinc = NULL, address = 0, tmp;
507 558
508 params &= 0x7fffffff; 559 if (!(params & 0x1000000)) {
560 kdebug("noinc");
561 *_inc = 0;
562 _inc = NULL;
563 }
564
565 params &= 0x00ffffff;
509 566
510 do { 567 do {
511 switch (params & 0xff) { 568 switch (params & 0xff) {
@@ -514,11 +571,11 @@ static int misalignment_addr(unsigned long *registers, unsigned params,
514 address += *postinc; 571 address += *postinc;
515 break; 572 break;
516 case DM1: 573 case DM1:
517 postinc = &registers[Dreg_index[opcode >> 2 & 0x0c]]; 574 postinc = &registers[Dreg_index[opcode >> 2 & 0x03]];
518 address += *postinc; 575 address += *postinc;
519 break; 576 break;
520 case DM2: 577 case DM2:
521 postinc = &registers[Dreg_index[opcode >> 4 & 0x30]]; 578 postinc = &registers[Dreg_index[opcode >> 4 & 0x03]];
522 address += *postinc; 579 address += *postinc;
523 break; 580 break;
524 case AM0: 581 case AM0:
@@ -526,11 +583,11 @@ static int misalignment_addr(unsigned long *registers, unsigned params,
526 address += *postinc; 583 address += *postinc;
527 break; 584 break;
528 case AM1: 585 case AM1:
529 postinc = &registers[Areg_index[opcode >> 2 & 0x0c]]; 586 postinc = &registers[Areg_index[opcode >> 2 & 0x03]];
530 address += *postinc; 587 address += *postinc;
531 break; 588 break;
532 case AM2: 589 case AM2:
533 postinc = &registers[Areg_index[opcode >> 4 & 0x30]]; 590 postinc = &registers[Areg_index[opcode >> 4 & 0x03]];
534 address += *postinc; 591 address += *postinc;
535 break; 592 break;
536 case RM0: 593 case RM0:
@@ -561,33 +618,53 @@ static int misalignment_addr(unsigned long *registers, unsigned params,
561 postinc = &registers[Rreg_index[disp >> 4 & 0x0f]]; 618 postinc = &registers[Rreg_index[disp >> 4 & 0x0f]];
562 address += *postinc; 619 address += *postinc;
563 break; 620 break;
621 case SP:
622 address += sp;
623 break;
564 624
625 /* displacements are either to be added to the address
626 * before use, or, in the case of post-inc addressing,
627 * to be added into the base register after use */
565 case SD8: 628 case SD8:
566 case SIMM8: 629 case SIMM8:
567 address += (int32_t) (int8_t) (disp & 0xff); 630 disp = (long) (int8_t) (disp & 0xff);
568 break; 631 goto displace_or_inc;
569 case SD16: 632 case SD16:
570 address += (int32_t) (int16_t) (disp & 0xffff); 633 disp = (long) (int16_t) (disp & 0xffff);
571 break; 634 goto displace_or_inc;
572 case SD24: 635 case SD24:
573 tmp = disp << 8; 636 tmp = disp << 8;
574 asm("asr 8,%0" : "=r"(tmp) : "0"(tmp)); 637 asm("asr 8,%0" : "=r"(tmp) : "0"(tmp));
575 address += tmp; 638 disp = (long) tmp;
576 break; 639 goto displace_or_inc;
577 case SIMM4_2: 640 case SIMM4_2:
578 tmp = opcode >> 4 & 0x0f; 641 tmp = opcode >> 4 & 0x0f;
579 tmp <<= 28; 642 tmp <<= 28;
580 asm("asr 28,%0" : "=r"(tmp) : "0"(tmp)); 643 asm("asr 28,%0" : "=r"(tmp) : "0"(tmp));
581 address += tmp; 644 disp = (long) tmp;
582 break; 645 goto displace_or_inc;
646 case IMM8:
647 disp &= 0x000000ff;
648 goto displace_or_inc;
649 case IMM16:
650 disp &= 0x0000ffff;
651 goto displace_or_inc;
583 case IMM24: 652 case IMM24:
584 address += disp & 0x00ffffff; 653 disp &= 0x00ffffff;
585 break; 654 goto displace_or_inc;
586 case IMM32: 655 case IMM32:
656 case IMM32_MEM:
587 case IMM32_HIGH8: 657 case IMM32_HIGH8:
588 address += disp; 658 case IMM32_HIGH8_MEM:
659 displace_or_inc:
660 kdebug("%s %lx", _inc ? "incr" : "disp", disp);
661 if (!_inc)
662 address += disp;
663 else
664 *_inc = disp;
589 break; 665 break;
590 default: 666 default:
667 BUG();
591 return 0; 668 return 0;
592 } 669 }
593 } while ((params >>= 8)); 670 } while ((params >>= 8));
@@ -601,7 +678,7 @@ static int misalignment_addr(unsigned long *registers, unsigned params,
601 * determine the register that is acting as source/dest 678 * determine the register that is acting as source/dest
602 */ 679 */
603static int misalignment_reg(unsigned long *registers, unsigned params, 680static int misalignment_reg(unsigned long *registers, unsigned params,
604 unsigned opcode, unsigned disp, 681 unsigned opcode, unsigned long disp,
605 unsigned long **_register) 682 unsigned long **_register)
606{ 683{
607 params &= 0x7fffffff; 684 params &= 0x7fffffff;
@@ -654,8 +731,239 @@ static int misalignment_reg(unsigned long *registers, unsigned params,
654 break; 731 break;
655 732
656 default: 733 default:
734 BUG();
657 return 0; 735 return 0;
658 } 736 }
659 737
660 return 1; 738 return 1;
661} 739}
740
741/*
742 * handle the conditional loop part of the move-and-loop instructions
743 */
744static void misalignment_MOV_Lcc(struct pt_regs *regs, uint32_t opcode)
745{
746 unsigned long epsw = regs->epsw;
747 unsigned long NxorV;
748
749 kdebug("MOV_Lcc %x [flags=%lx]", opcode, epsw & 0xf);
750
751 /* calculate N^V and shift onto the same bit position as Z */
752 NxorV = ((epsw >> 3) ^ epsw >> 1) & 1;
753
754 switch (opcode & 0xf) {
755 case 0x0: /* MOV_LLT: N^V */
756 if (NxorV)
757 goto take_the_loop;
758 return;
759 case 0x1: /* MOV_LGT: ~(Z or (N^V))*/
760 if (!((epsw & EPSW_FLAG_Z) | NxorV))
761 goto take_the_loop;
762 return;
763 case 0x2: /* MOV_LGE: ~(N^V) */
764 if (!NxorV)
765 goto take_the_loop;
766 return;
767 case 0x3: /* MOV_LLE: Z or (N^V) */
768 if ((epsw & EPSW_FLAG_Z) | NxorV)
769 goto take_the_loop;
770 return;
771
772 case 0x4: /* MOV_LCS: C */
773 if (epsw & EPSW_FLAG_C)
774 goto take_the_loop;
775 return;
776 case 0x5: /* MOV_LHI: ~(C or Z) */
777 if (!(epsw & (EPSW_FLAG_C | EPSW_FLAG_Z)))
778 goto take_the_loop;
779 return;
780 case 0x6: /* MOV_LCC: ~C */
781 if (!(epsw & EPSW_FLAG_C))
782 goto take_the_loop;
783 return;
784 case 0x7: /* MOV_LLS: C or Z */
785 if (epsw & (EPSW_FLAG_C | EPSW_FLAG_Z))
786 goto take_the_loop;
787 return;
788
789 case 0x8: /* MOV_LEQ: Z */
790 if (epsw & EPSW_FLAG_Z)
791 goto take_the_loop;
792 return;
793 case 0x9: /* MOV_LNE: ~Z */
794 if (!(epsw & EPSW_FLAG_Z))
795 goto take_the_loop;
796 return;
797 case 0xa: /* MOV_LRA: always */
798 goto take_the_loop;
799
800 default:
801 BUG();
802 }
803
804take_the_loop:
805 /* wind the PC back to just after the SETLB insn */
806 kdebug("loop LAR=%lx", regs->lar);
807 regs->pc = regs->lar - 4;
808}
809
810/*
811 * misalignment handler tests
812 */
813#ifdef CONFIG_TEST_MISALIGNMENT_HANDLER
814static u8 __initdata testbuf[512] __attribute__((aligned(16))) = {
815 [257] = 0x11,
816 [258] = 0x22,
817 [259] = 0x33,
818 [260] = 0x44,
819};
820
821#define ASSERTCMP(X, OP, Y) \
822do { \
823 if (unlikely(!((X) OP (Y)))) { \
824 printk(KERN_ERR "\n"); \
825 printk(KERN_ERR "MISALIGN: Assertion failed at line %u\n", \
826 __LINE__); \
827 printk(KERN_ERR "0x%lx " #OP " 0x%lx is false\n", \
828 (unsigned long)(X), (unsigned long)(Y)); \
829 BUG(); \
830 } \
831} while(0)
832
833static int __init test_misalignment(void)
834{
835 register void *r asm("e0");
836 register u32 y asm("e1");
837 void *p = testbuf, *q;
838 u32 tmp, tmp2, x;
839
840 printk(KERN_NOTICE "==>test_misalignment() [testbuf=%p]\n", p);
841 p++;
842
843 printk(KERN_NOTICE "___ MOV (Am),Dn ___\n");
844 q = p + 256;
845 asm volatile("mov (%0),%1" : "+a"(q), "=d"(x));
846 ASSERTCMP(q, ==, p + 256);
847 ASSERTCMP(x, ==, 0x44332211);
848
849 printk(KERN_NOTICE "___ MOV (256,Am),Dn ___\n");
850 q = p;
851 asm volatile("mov (256,%0),%1" : "+a"(q), "=d"(x));
852 ASSERTCMP(q, ==, p);
853 ASSERTCMP(x, ==, 0x44332211);
854
855 printk(KERN_NOTICE "___ MOV (Di,Am),Dn ___\n");
856 tmp = 256;
857 q = p;
858 asm volatile("mov (%2,%0),%1" : "+a"(q), "=d"(x), "+d"(tmp));
859 ASSERTCMP(q, ==, p);
860 ASSERTCMP(x, ==, 0x44332211);
861 ASSERTCMP(tmp, ==, 256);
862
863 printk(KERN_NOTICE "___ MOV (256,Rm),Rn ___\n");
864 r = p;
865 asm volatile("mov (256,%0),%1" : "+r"(r), "=r"(y));
866 ASSERTCMP(r, ==, p);
867 ASSERTCMP(y, ==, 0x44332211);
868
869 printk(KERN_NOTICE "___ MOV (Rm+),Rn ___\n");
870 r = p + 256;
871 asm volatile("mov (%0+),%1" : "+r"(r), "=r"(y));
872 ASSERTCMP(r, ==, p + 256 + 4);
873 ASSERTCMP(y, ==, 0x44332211);
874
875 printk(KERN_NOTICE "___ MOV (Rm+,8),Rn ___\n");
876 r = p + 256;
877 asm volatile("mov (%0+,8),%1" : "+r"(r), "=r"(y));
878 ASSERTCMP(r, ==, p + 256 + 8);
879 ASSERTCMP(y, ==, 0x44332211);
880
881 printk(KERN_NOTICE "___ MOV (7,SP),Rn ___\n");
882 asm volatile(
883 "add -16,sp \n"
884 "mov +0x11,%0 \n"
885 "movbu %0,(7,sp) \n"
886 "mov +0x22,%0 \n"
887 "movbu %0,(8,sp) \n"
888 "mov +0x33,%0 \n"
889 "movbu %0,(9,sp) \n"
890 "mov +0x44,%0 \n"
891 "movbu %0,(10,sp) \n"
892 "mov (7,sp),%1 \n"
893 "add +16,sp \n"
894 : "+a"(q), "=d"(x));
895 ASSERTCMP(x, ==, 0x44332211);
896
897 printk(KERN_NOTICE "___ MOV (259,SP),Rn ___\n");
898 asm volatile(
899 "add -264,sp \n"
900 "mov +0x11,%0 \n"
901 "movbu %0,(259,sp) \n"
902 "mov +0x22,%0 \n"
903 "movbu %0,(260,sp) \n"
904 "mov +0x33,%0 \n"
905 "movbu %0,(261,sp) \n"
906 "mov +0x55,%0 \n"
907 "movbu %0,(262,sp) \n"
908 "mov (259,sp),%1 \n"
909 "add +264,sp \n"
910 : "+d"(tmp), "=d"(x));
911 ASSERTCMP(x, ==, 0x55332211);
912
913 printk(KERN_NOTICE "___ MOV (260,SP),Rn ___\n");
914 asm volatile(
915 "add -264,sp \n"
916 "mov +0x11,%0 \n"
917 "movbu %0,(260,sp) \n"
918 "mov +0x22,%0 \n"
919 "movbu %0,(261,sp) \n"
920 "mov +0x33,%0 \n"
921 "movbu %0,(262,sp) \n"
922 "mov +0x55,%0 \n"
923 "movbu %0,(263,sp) \n"
924 "mov (260,sp),%1 \n"
925 "add +264,sp \n"
926 : "+d"(tmp), "=d"(x));
927 ASSERTCMP(x, ==, 0x55332211);
928
929
930 printk(KERN_NOTICE "___ MOV_LNE ___\n");
931 tmp = 1;
932 tmp2 = 2;
933 q = p + 256;
934 asm volatile(
935 "setlb \n"
936 "mov %2,%3 \n"
937 "mov %1,%2 \n"
938 "cmp +0,%1 \n"
939 "mov_lne (%0+,4),%1"
940 : "+r"(q), "+d"(tmp), "+d"(tmp2), "=d"(x)
941 :
942 : "cc");
943 ASSERTCMP(q, ==, p + 256 + 12);
944 ASSERTCMP(x, ==, 0x44332211);
945
946 printk(KERN_NOTICE "___ MOV in SETLB ___\n");
947 tmp = 1;
948 tmp2 = 2;
949 q = p + 256;
950 asm volatile(
951 "setlb \n"
952 "mov %1,%3 \n"
953 "mov (%0+),%1 \n"
954 "cmp +0,%1 \n"
955 "lne "
956 : "+a"(q), "+d"(tmp), "+d"(tmp2), "=d"(x)
957 :
958 : "cc");
959
960 ASSERTCMP(q, ==, p + 256 + 8);
961 ASSERTCMP(x, ==, 0x44332211);
962
963 printk(KERN_NOTICE "<==test_misalignment()\n");
964 return 0;
965}
966
967arch_initcall(test_misalignment);
968
969#endif /* CONFIG_TEST_MISALIGNMENT_HANDLER */
diff --git a/arch/parisc/include/asm/smp.h b/arch/parisc/include/asm/smp.h
index 398cdbaf4e54..409e698f4361 100644
--- a/arch/parisc/include/asm/smp.h
+++ b/arch/parisc/include/asm/smp.h
@@ -44,8 +44,6 @@ extern void arch_send_call_function_ipi(cpumask_t mask);
44 44
45#define PROC_CHANGE_PENALTY 15 /* Schedule penalty */ 45#define PROC_CHANGE_PENALTY 15 /* Schedule penalty */
46 46
47extern unsigned long cpu_present_mask;
48
49#define raw_smp_processor_id() (current_thread_info()->cpu) 47#define raw_smp_processor_id() (current_thread_info()->cpu)
50 48
51#else /* CONFIG_SMP */ 49#else /* CONFIG_SMP */
diff --git a/arch/s390/kernel/entry.S b/arch/s390/kernel/entry.S
index ed500ef799b7..08844fc24a2e 100644
--- a/arch/s390/kernel/entry.S
+++ b/arch/s390/kernel/entry.S
@@ -61,22 +61,25 @@ STACK_SIZE = 1 << STACK_SHIFT
61 61
62#ifdef CONFIG_TRACE_IRQFLAGS 62#ifdef CONFIG_TRACE_IRQFLAGS
63 .macro TRACE_IRQS_ON 63 .macro TRACE_IRQS_ON
64 l %r1,BASED(.Ltrace_irq_on) 64 basr %r2,%r0
65 l %r1,BASED(.Ltrace_irq_on_caller)
65 basr %r14,%r1 66 basr %r14,%r1
66 .endm 67 .endm
67 68
68 .macro TRACE_IRQS_OFF 69 .macro TRACE_IRQS_OFF
69 l %r1,BASED(.Ltrace_irq_off) 70 basr %r2,%r0
71 l %r1,BASED(.Ltrace_irq_off_caller)
70 basr %r14,%r1 72 basr %r14,%r1
71 .endm 73 .endm
72 74
73 .macro TRACE_IRQS_CHECK 75 .macro TRACE_IRQS_CHECK
76 basr %r2,%r0
74 tm SP_PSW(%r15),0x03 # irqs enabled? 77 tm SP_PSW(%r15),0x03 # irqs enabled?
75 jz 0f 78 jz 0f
76 l %r1,BASED(.Ltrace_irq_on) 79 l %r1,BASED(.Ltrace_irq_on_caller)
77 basr %r14,%r1 80 basr %r14,%r1
78 j 1f 81 j 1f
790: l %r1,BASED(.Ltrace_irq_off) 820: l %r1,BASED(.Ltrace_irq_off_caller)
80 basr %r14,%r1 83 basr %r14,%r1
811: 841:
82 .endm 85 .endm
@@ -1113,9 +1116,12 @@ cleanup_io_leave_insn:
1113.Lschedtail: .long schedule_tail 1116.Lschedtail: .long schedule_tail
1114.Lsysc_table: .long sys_call_table 1117.Lsysc_table: .long sys_call_table
1115#ifdef CONFIG_TRACE_IRQFLAGS 1118#ifdef CONFIG_TRACE_IRQFLAGS
1116.Ltrace_irq_on: .long trace_hardirqs_on 1119.Ltrace_irq_on_caller:
1117.Ltrace_irq_off: 1120 .long trace_hardirqs_on_caller
1118 .long trace_hardirqs_off 1121.Ltrace_irq_off_caller:
1122 .long trace_hardirqs_off_caller
1123#endif
1124#ifdef CONFIG_LOCKDEP
1119.Llockdep_sys_exit: 1125.Llockdep_sys_exit:
1120 .long lockdep_sys_exit 1126 .long lockdep_sys_exit
1121#endif 1127#endif
diff --git a/arch/s390/kernel/entry64.S b/arch/s390/kernel/entry64.S
index d7ce150453f2..41aca06682aa 100644
--- a/arch/s390/kernel/entry64.S
+++ b/arch/s390/kernel/entry64.S
@@ -61,19 +61,22 @@ _TIF_WORK_INT = (_TIF_SIGPENDING | _TIF_NOTIFY_RESUME | _TIF_NEED_RESCHED | \
61 61
62#ifdef CONFIG_TRACE_IRQFLAGS 62#ifdef CONFIG_TRACE_IRQFLAGS
63 .macro TRACE_IRQS_ON 63 .macro TRACE_IRQS_ON
64 brasl %r14,trace_hardirqs_on 64 basr %r2,%r0
65 brasl %r14,trace_hardirqs_on_caller
65 .endm 66 .endm
66 67
67 .macro TRACE_IRQS_OFF 68 .macro TRACE_IRQS_OFF
68 brasl %r14,trace_hardirqs_off 69 basr %r2,%r0
70 brasl %r14,trace_hardirqs_off_caller
69 .endm 71 .endm
70 72
71 .macro TRACE_IRQS_CHECK 73 .macro TRACE_IRQS_CHECK
74 basr %r2,%r0
72 tm SP_PSW(%r15),0x03 # irqs enabled? 75 tm SP_PSW(%r15),0x03 # irqs enabled?
73 jz 0f 76 jz 0f
74 brasl %r14,trace_hardirqs_on 77 brasl %r14,trace_hardirqs_on_caller
75 j 1f 78 j 1f
760: brasl %r14,trace_hardirqs_off 790: brasl %r14,trace_hardirqs_off_caller
771: 801:
78 .endm 81 .endm
79#else 82#else
diff --git a/arch/s390/kernel/process.c b/arch/s390/kernel/process.c
index 3e2c05cb6a87..04f8c67a6101 100644
--- a/arch/s390/kernel/process.c
+++ b/arch/s390/kernel/process.c
@@ -136,9 +136,12 @@ static void default_idle(void)
136 return; 136 return;
137 } 137 }
138 trace_hardirqs_on(); 138 trace_hardirqs_on();
139 /* Don't trace preempt off for idle. */
140 stop_critical_timings();
139 /* Wait for external, I/O or machine check interrupt. */ 141 /* Wait for external, I/O or machine check interrupt. */
140 __load_psw_mask(psw_kernel_bits | PSW_MASK_WAIT | 142 __load_psw_mask(psw_kernel_bits | PSW_MASK_WAIT |
141 PSW_MASK_IO | PSW_MASK_EXT); 143 PSW_MASK_IO | PSW_MASK_EXT);
144 start_critical_timings();
142} 145}
143 146
144void cpu_idle(void) 147void cpu_idle(void)
diff --git a/arch/s390/kernel/setup.c b/arch/s390/kernel/setup.c
index 62122bad1e33..400b040df7fa 100644
--- a/arch/s390/kernel/setup.c
+++ b/arch/s390/kernel/setup.c
@@ -604,13 +604,13 @@ setup_memory(void)
604 if (memory_chunk[i].type != CHUNK_READ_WRITE) 604 if (memory_chunk[i].type != CHUNK_READ_WRITE)
605 continue; 605 continue;
606 start_chunk = PFN_DOWN(memory_chunk[i].addr); 606 start_chunk = PFN_DOWN(memory_chunk[i].addr);
607 end_chunk = start_chunk + PFN_DOWN(memory_chunk[i].size) - 1; 607 end_chunk = start_chunk + PFN_DOWN(memory_chunk[i].size);
608 end_chunk = min(end_chunk, end_pfn); 608 end_chunk = min(end_chunk, end_pfn);
609 if (start_chunk >= end_chunk) 609 if (start_chunk >= end_chunk)
610 continue; 610 continue;
611 add_active_range(0, start_chunk, end_chunk); 611 add_active_range(0, start_chunk, end_chunk);
612 pfn = max(start_chunk, start_pfn); 612 pfn = max(start_chunk, start_pfn);
613 for (; pfn <= end_chunk; pfn++) 613 for (; pfn < end_chunk; pfn++)
614 page_set_storage_key(PFN_PHYS(pfn), PAGE_DEFAULT_KEY); 614 page_set_storage_key(PFN_PHYS(pfn), PAGE_DEFAULT_KEY);
615 } 615 }
616 616
diff --git a/arch/s390/kernel/sys_s390.c b/arch/s390/kernel/sys_s390.c
index 5fdb799062b7..4fe952e557ac 100644
--- a/arch/s390/kernel/sys_s390.c
+++ b/arch/s390/kernel/sys_s390.c
@@ -198,7 +198,7 @@ asmlinkage long s390x_newuname(struct new_utsname __user *name)
198{ 198{
199 int ret = sys_newuname(name); 199 int ret = sys_newuname(name);
200 200
201 if (current->personality == PER_LINUX32 && !ret) { 201 if (personality(current->personality) == PER_LINUX32 && !ret) {
202 ret = copy_to_user(name->machine, "s390\0\0\0\0", 8); 202 ret = copy_to_user(name->machine, "s390\0\0\0\0", 8);
203 if (ret) ret = -EFAULT; 203 if (ret) ret = -EFAULT;
204 } 204 }
diff --git a/arch/s390/kernel/topology.c b/arch/s390/kernel/topology.c
index 632b13e10053..a947899dcba1 100644
--- a/arch/s390/kernel/topology.c
+++ b/arch/s390/kernel/topology.c
@@ -65,18 +65,21 @@ static int machine_has_topology_irq;
65static struct timer_list topology_timer; 65static struct timer_list topology_timer;
66static void set_topology_timer(void); 66static void set_topology_timer(void);
67static DECLARE_WORK(topology_work, topology_work_fn); 67static DECLARE_WORK(topology_work, topology_work_fn);
68/* topology_lock protects the core linked list */
69static DEFINE_SPINLOCK(topology_lock);
68 70
69cpumask_t cpu_core_map[NR_CPUS]; 71cpumask_t cpu_core_map[NR_CPUS];
70 72
71cpumask_t cpu_coregroup_map(unsigned int cpu) 73cpumask_t cpu_coregroup_map(unsigned int cpu)
72{ 74{
73 struct core_info *core = &core_info; 75 struct core_info *core = &core_info;
76 unsigned long flags;
74 cpumask_t mask; 77 cpumask_t mask;
75 78
76 cpus_clear(mask); 79 cpus_clear(mask);
77 if (!machine_has_topology) 80 if (!machine_has_topology)
78 return cpu_present_map; 81 return cpu_present_map;
79 mutex_lock(&smp_cpu_state_mutex); 82 spin_lock_irqsave(&topology_lock, flags);
80 while (core) { 83 while (core) {
81 if (cpu_isset(cpu, core->mask)) { 84 if (cpu_isset(cpu, core->mask)) {
82 mask = core->mask; 85 mask = core->mask;
@@ -84,7 +87,7 @@ cpumask_t cpu_coregroup_map(unsigned int cpu)
84 } 87 }
85 core = core->next; 88 core = core->next;
86 } 89 }
87 mutex_unlock(&smp_cpu_state_mutex); 90 spin_unlock_irqrestore(&topology_lock, flags);
88 if (cpus_empty(mask)) 91 if (cpus_empty(mask))
89 mask = cpumask_of_cpu(cpu); 92 mask = cpumask_of_cpu(cpu);
90 return mask; 93 return mask;
@@ -133,7 +136,7 @@ static void tl_to_cores(struct tl_info *info)
133 union tl_entry *tle, *end; 136 union tl_entry *tle, *end;
134 struct core_info *core = &core_info; 137 struct core_info *core = &core_info;
135 138
136 mutex_lock(&smp_cpu_state_mutex); 139 spin_lock_irq(&topology_lock);
137 clear_cores(); 140 clear_cores();
138 tle = info->tle; 141 tle = info->tle;
139 end = (union tl_entry *)((unsigned long)info + info->length); 142 end = (union tl_entry *)((unsigned long)info + info->length);
@@ -157,7 +160,7 @@ static void tl_to_cores(struct tl_info *info)
157 } 160 }
158 tle = next_tle(tle); 161 tle = next_tle(tle);
159 } 162 }
160 mutex_unlock(&smp_cpu_state_mutex); 163 spin_unlock_irq(&topology_lock);
161} 164}
162 165
163static void topology_update_polarization_simple(void) 166static void topology_update_polarization_simple(void)
diff --git a/arch/sh/include/asm/io.h b/arch/sh/include/asm/io.h
index 436c28539577..65eaae34e753 100644
--- a/arch/sh/include/asm/io.h
+++ b/arch/sh/include/asm/io.h
@@ -293,6 +293,10 @@ __ioremap_mode(unsigned long offset, unsigned long size, unsigned long flags)
293 */ 293 */
294#define xlate_dev_kmem_ptr(p) p 294#define xlate_dev_kmem_ptr(p) p
295 295
296#define ARCH_HAS_VALID_PHYS_ADDR_RANGE
297int valid_phys_addr_range(unsigned long addr, size_t size);
298int valid_mmap_phys_addr_range(unsigned long pfn, size_t size);
299
296#endif /* __KERNEL__ */ 300#endif /* __KERNEL__ */
297 301
298#endif /* __ASM_SH_IO_H */ 302#endif /* __ASM_SH_IO_H */
diff --git a/arch/sh/include/asm/pgtable.h b/arch/sh/include/asm/pgtable.h
index 52220d70a096..b517ae08b9c0 100644
--- a/arch/sh/include/asm/pgtable.h
+++ b/arch/sh/include/asm/pgtable.h
@@ -148,6 +148,12 @@ extern void paging_init(void);
148extern void page_table_range_init(unsigned long start, unsigned long end, 148extern void page_table_range_init(unsigned long start, unsigned long end,
149 pgd_t *pgd); 149 pgd_t *pgd);
150 150
151#if !defined(CONFIG_CACHE_OFF) && defined(CONFIG_CPU_SH4) && defined(CONFIG_MMU)
152extern void kmap_coherent_init(void);
153#else
154#define kmap_coherent_init() do { } while (0)
155#endif
156
151#include <asm-generic/pgtable.h> 157#include <asm-generic/pgtable.h>
152 158
153#endif /* __ASM_SH_PGTABLE_H */ 159#endif /* __ASM_SH_PGTABLE_H */
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7723.c b/arch/sh/kernel/cpu/sh4a/setup-sh7723.c
index a7412cede534..6d9e6972cfc9 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7723.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7723.c
@@ -119,17 +119,17 @@ static struct plat_sci_port sci_platform_data[] = {
119 },{ 119 },{
120 .mapbase = 0xa4e30000, 120 .mapbase = 0xa4e30000,
121 .flags = UPF_BOOT_AUTOCONF, 121 .flags = UPF_BOOT_AUTOCONF,
122 .type = PORT_SCI, 122 .type = PORT_SCIFA,
123 .irqs = { 56, 56, 56, 56 }, 123 .irqs = { 56, 56, 56, 56 },
124 },{ 124 },{
125 .mapbase = 0xa4e40000, 125 .mapbase = 0xa4e40000,
126 .flags = UPF_BOOT_AUTOCONF, 126 .flags = UPF_BOOT_AUTOCONF,
127 .type = PORT_SCI, 127 .type = PORT_SCIFA,
128 .irqs = { 88, 88, 88, 88 }, 128 .irqs = { 88, 88, 88, 88 },
129 },{ 129 },{
130 .mapbase = 0xa4e50000, 130 .mapbase = 0xa4e50000,
131 .flags = UPF_BOOT_AUTOCONF, 131 .flags = UPF_BOOT_AUTOCONF,
132 .type = PORT_SCI, 132 .type = PORT_SCIFA,
133 .irqs = { 109, 109, 109, 109 }, 133 .irqs = { 109, 109, 109, 109 },
134 }, { 134 }, {
135 .flags = 0, 135 .flags = 0,
diff --git a/arch/sh/kernel/early_printk.c b/arch/sh/kernel/early_printk.c
index 6b7d166694e2..a952dcf9999d 100644
--- a/arch/sh/kernel/early_printk.c
+++ b/arch/sh/kernel/early_printk.c
@@ -75,6 +75,7 @@ static struct console bios_console = {
75#endif 75#endif
76 76
77static struct uart_port scif_port = { 77static struct uart_port scif_port = {
78 .type = PORT_SCIF,
78 .mapbase = CONFIG_EARLY_SCIF_CONSOLE_PORT, 79 .mapbase = CONFIG_EARLY_SCIF_CONSOLE_PORT,
79 .membase = (char __iomem *)CONFIG_EARLY_SCIF_CONSOLE_PORT, 80 .membase = (char __iomem *)CONFIG_EARLY_SCIF_CONSOLE_PORT,
80}; 81};
@@ -84,9 +85,9 @@ static void scif_sercon_putc(int c)
84 while (((sci_in(&scif_port, SCFDR) & EPK_FIFO_BITS) >= EPK_FIFO_SIZE)) 85 while (((sci_in(&scif_port, SCFDR) & EPK_FIFO_BITS) >= EPK_FIFO_SIZE))
85 ; 86 ;
86 87
87 sci_out(&scif_port, SCxTDR, c);
88 sci_in(&scif_port, SCxSR); 88 sci_in(&scif_port, SCxSR);
89 sci_out(&scif_port, SCxSR, 0xf3 & ~(0x20 | 0x40)); 89 sci_out(&scif_port, SCxSR, 0xf3 & ~(0x20 | 0x40));
90 sci_out(&scif_port, SCxTDR, c);
90 91
91 while ((sci_in(&scif_port, SCxSR) & 0x40) == 0) 92 while ((sci_in(&scif_port, SCxSR) & 0x40) == 0)
92 ; 93 ;
diff --git a/arch/sh/kernel/timers/timer-tmu.c b/arch/sh/kernel/timers/timer-tmu.c
index aaaf90d06b85..3c61ddd4d43e 100644
--- a/arch/sh/kernel/timers/timer-tmu.c
+++ b/arch/sh/kernel/timers/timer-tmu.c
@@ -120,7 +120,7 @@ static void tmu_set_mode(enum clock_event_mode mode,
120{ 120{
121 switch (mode) { 121 switch (mode) {
122 case CLOCK_EVT_MODE_PERIODIC: 122 case CLOCK_EVT_MODE_PERIODIC:
123 ctrl_outl(ctrl_inl(TMU0_TCNT), TMU0_TCOR); 123 ctrl_outl(tmu_latest_interval[TMU0], TMU0_TCOR);
124 break; 124 break;
125 case CLOCK_EVT_MODE_ONESHOT: 125 case CLOCK_EVT_MODE_ONESHOT:
126 ctrl_outl(0, TMU0_TCOR); 126 ctrl_outl(0, TMU0_TCOR);
diff --git a/arch/sh/lib/copy_page.S b/arch/sh/lib/copy_page.S
index 5d12e657be34..43de7e8e4e17 100644
--- a/arch/sh/lib/copy_page.S
+++ b/arch/sh/lib/copy_page.S
@@ -80,6 +80,11 @@ ENTRY(copy_page)
80 .section __ex_table, "a"; \ 80 .section __ex_table, "a"; \
81 .long 9999b, 6000f ; \ 81 .long 9999b, 6000f ; \
82 .previous 82 .previous
83#define EX_NO_POP(...) \
84 9999: __VA_ARGS__ ; \
85 .section __ex_table, "a"; \
86 .long 9999b, 6005f ; \
87 .previous
83ENTRY(__copy_user) 88ENTRY(__copy_user)
84 ! Check if small number of bytes 89 ! Check if small number of bytes
85 mov #11,r0 90 mov #11,r0
@@ -139,9 +144,9 @@ EX( mov.b r1,@r4 )
139 bt 1f 144 bt 1f
140 145
1412: 1462:
142EX( mov.b @r5+,r0 ) 147EX_NO_POP( mov.b @r5+,r0 )
143 dt r6 148 dt r6
144EX( mov.b r0,@r4 ) 149EX_NO_POP( mov.b r0,@r4 )
145 bf/s 2b 150 bf/s 2b
146 add #1,r4 151 add #1,r4
147 152
@@ -150,7 +155,7 @@ EX( mov.b r0,@r4 )
150 155
151# Exception handler: 156# Exception handler:
152.section .fixup, "ax" 157.section .fixup, "ax"
1536000: 1586005:
154 mov.l 8000f,r1 159 mov.l 8000f,r1
155 mov r3,r0 160 mov r3,r0
156 jmp @r1 161 jmp @r1
diff --git a/arch/sh/mm/Makefile_32 b/arch/sh/mm/Makefile_32
index 70e0906023cc..f066e76da204 100644
--- a/arch/sh/mm/Makefile_32
+++ b/arch/sh/mm/Makefile_32
@@ -2,7 +2,7 @@
2# Makefile for the Linux SuperH-specific parts of the memory manager. 2# Makefile for the Linux SuperH-specific parts of the memory manager.
3# 3#
4 4
5obj-y := init.o extable_32.o consistent.o 5obj-y := init.o extable_32.o consistent.o mmap.o
6 6
7ifndef CONFIG_CACHE_OFF 7ifndef CONFIG_CACHE_OFF
8cache-$(CONFIG_CPU_SH2) := cache-sh2.o 8cache-$(CONFIG_CPU_SH2) := cache-sh2.o
diff --git a/arch/sh/mm/Makefile_64 b/arch/sh/mm/Makefile_64
index 0d92a8a3ac9a..9481d0f54efd 100644
--- a/arch/sh/mm/Makefile_64
+++ b/arch/sh/mm/Makefile_64
@@ -2,7 +2,7 @@
2# Makefile for the Linux SuperH-specific parts of the memory manager. 2# Makefile for the Linux SuperH-specific parts of the memory manager.
3# 3#
4 4
5obj-y := init.o consistent.o 5obj-y := init.o consistent.o mmap.o
6 6
7mmu-y := tlb-nommu.o pg-nommu.o extable_32.o 7mmu-y := tlb-nommu.o pg-nommu.o extable_32.o
8mmu-$(CONFIG_MMU) := fault_64.o ioremap_64.o tlbflush_64.o tlb-sh5.o \ 8mmu-$(CONFIG_MMU) := fault_64.o ioremap_64.o tlbflush_64.o tlb-sh5.o \
diff --git a/arch/sh/mm/init.c b/arch/sh/mm/init.c
index 4abf00031dae..6cbef8caeb56 100644
--- a/arch/sh/mm/init.c
+++ b/arch/sh/mm/init.c
@@ -137,6 +137,7 @@ void __init page_table_range_init(unsigned long start, unsigned long end,
137void __init paging_init(void) 137void __init paging_init(void)
138{ 138{
139 unsigned long max_zone_pfns[MAX_NR_ZONES]; 139 unsigned long max_zone_pfns[MAX_NR_ZONES];
140 unsigned long vaddr;
140 int nid; 141 int nid;
141 142
142 /* We don't need to map the kernel through the TLB, as 143 /* We don't need to map the kernel through the TLB, as
@@ -148,10 +149,15 @@ void __init paging_init(void)
148 * check for a null value. */ 149 * check for a null value. */
149 set_TTB(swapper_pg_dir); 150 set_TTB(swapper_pg_dir);
150 151
151 /* Populate the relevant portions of swapper_pg_dir so that 152 /*
153 * Populate the relevant portions of swapper_pg_dir so that
152 * we can use the fixmap entries without calling kmalloc. 154 * we can use the fixmap entries without calling kmalloc.
153 * pte's will be filled in by __set_fixmap(). */ 155 * pte's will be filled in by __set_fixmap().
154 page_table_range_init(FIXADDR_START, FIXADDR_TOP, swapper_pg_dir); 156 */
157 vaddr = __fix_to_virt(__end_of_fixed_addresses - 1) & PMD_MASK;
158 page_table_range_init(vaddr, 0, swapper_pg_dir);
159
160 kmap_coherent_init();
155 161
156 memset(max_zone_pfns, 0, sizeof(max_zone_pfns)); 162 memset(max_zone_pfns, 0, sizeof(max_zone_pfns));
157 163
diff --git a/arch/sh/mm/mmap.c b/arch/sh/mm/mmap.c
new file mode 100644
index 000000000000..8837d511710a
--- /dev/null
+++ b/arch/sh/mm/mmap.c
@@ -0,0 +1,31 @@
1/*
2 * arch/sh/mm/mmap.c
3 *
4 * Copyright (C) 2008 Paul Mundt
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10#include <linux/io.h>
11#include <linux/mm.h>
12#include <asm/page.h>
13
14/*
15 * You really shouldn't be using read() or write() on /dev/mem. This
16 * might go away in the future.
17 */
18int valid_phys_addr_range(unsigned long addr, size_t count)
19{
20 if (addr < __MEMORY_START)
21 return 0;
22 if (addr + count > __pa(high_memory))
23 return 0;
24
25 return 1;
26}
27
28int valid_mmap_phys_addr_range(unsigned long pfn, size_t size)
29{
30 return 1;
31}
diff --git a/arch/sh/mm/pg-sh4.c b/arch/sh/mm/pg-sh4.c
index 38870e0fc182..2fe14da1f839 100644
--- a/arch/sh/mm/pg-sh4.c
+++ b/arch/sh/mm/pg-sh4.c
@@ -7,6 +7,7 @@
7 * Released under the terms of the GNU GPL v2.0. 7 * Released under the terms of the GNU GPL v2.0.
8 */ 8 */
9#include <linux/mm.h> 9#include <linux/mm.h>
10#include <linux/init.h>
10#include <linux/mutex.h> 11#include <linux/mutex.h>
11#include <linux/fs.h> 12#include <linux/fs.h>
12#include <linux/highmem.h> 13#include <linux/highmem.h>
@@ -16,6 +17,20 @@
16 17
17#define CACHE_ALIAS (current_cpu_data.dcache.alias_mask) 18#define CACHE_ALIAS (current_cpu_data.dcache.alias_mask)
18 19
20#define kmap_get_fixmap_pte(vaddr) \
21 pte_offset_kernel(pmd_offset(pud_offset(pgd_offset_k(vaddr), (vaddr)), (vaddr)), (vaddr))
22
23static pte_t *kmap_coherent_pte;
24
25void __init kmap_coherent_init(void)
26{
27 unsigned long vaddr;
28
29 /* cache the first coherent kmap pte */
30 vaddr = __fix_to_virt(FIX_CMAP_BEGIN);
31 kmap_coherent_pte = kmap_get_fixmap_pte(vaddr);
32}
33
19static inline void *kmap_coherent(struct page *page, unsigned long addr) 34static inline void *kmap_coherent(struct page *page, unsigned long addr)
20{ 35{
21 enum fixed_addresses idx; 36 enum fixed_addresses idx;
@@ -34,6 +49,8 @@ static inline void *kmap_coherent(struct page *page, unsigned long addr)
34 49
35 update_mmu_cache(NULL, vaddr, pte); 50 update_mmu_cache(NULL, vaddr, pte);
36 51
52 set_pte(kmap_coherent_pte - (FIX_CMAP_END - idx), pte);
53
37 return (void *)vaddr; 54 return (void *)vaddr;
38} 55}
39 56
diff --git a/arch/sparc/include/asm/termbits.h b/arch/sparc/include/asm/termbits.h
index d6ca3e2754f5..d72dfed1f9d7 100644
--- a/arch/sparc/include/asm/termbits.h
+++ b/arch/sparc/include/asm/termbits.h
@@ -29,10 +29,11 @@ struct termios {
29 tcflag_t c_cflag; /* control mode flags */ 29 tcflag_t c_cflag; /* control mode flags */
30 tcflag_t c_lflag; /* local mode flags */ 30 tcflag_t c_lflag; /* local mode flags */
31 cc_t c_line; /* line discipline */ 31 cc_t c_line; /* line discipline */
32#ifndef __KERNEL__
32 cc_t c_cc[NCCS]; /* control characters */ 33 cc_t c_cc[NCCS]; /* control characters */
33#ifdef __KERNEL__ 34#else
35 cc_t c_cc[NCCS+2]; /* kernel needs 2 more to hold vmin/vtime */
34#define SIZEOF_USER_TERMIOS sizeof (struct termios) - (2*sizeof (cc_t)) 36#define SIZEOF_USER_TERMIOS sizeof (struct termios) - (2*sizeof (cc_t))
35 cc_t _x_cc[2]; /* We need them to hold vmin/vtime */
36#endif 37#endif
37}; 38};
38 39
@@ -42,8 +43,7 @@ struct termios2 {
42 tcflag_t c_cflag; /* control mode flags */ 43 tcflag_t c_cflag; /* control mode flags */
43 tcflag_t c_lflag; /* local mode flags */ 44 tcflag_t c_lflag; /* local mode flags */
44 cc_t c_line; /* line discipline */ 45 cc_t c_line; /* line discipline */
45 cc_t c_cc[NCCS]; /* control characters */ 46 cc_t c_cc[NCCS+2]; /* control characters */
46 cc_t _x_cc[2]; /* padding to match ktermios */
47 speed_t c_ispeed; /* input speed */ 47 speed_t c_ispeed; /* input speed */
48 speed_t c_ospeed; /* output speed */ 48 speed_t c_ospeed; /* output speed */
49}; 49};
@@ -54,8 +54,7 @@ struct ktermios {
54 tcflag_t c_cflag; /* control mode flags */ 54 tcflag_t c_cflag; /* control mode flags */
55 tcflag_t c_lflag; /* local mode flags */ 55 tcflag_t c_lflag; /* local mode flags */
56 cc_t c_line; /* line discipline */ 56 cc_t c_line; /* line discipline */
57 cc_t c_cc[NCCS]; /* control characters */ 57 cc_t c_cc[NCCS+2]; /* control characters */
58 cc_t _x_cc[2]; /* We need them to hold vmin/vtime */
59 speed_t c_ispeed; /* input speed */ 58 speed_t c_ispeed; /* input speed */
60 speed_t c_ospeed; /* output speed */ 59 speed_t c_ospeed; /* output speed */
61}; 60};
diff --git a/arch/sparc/kernel/of_device.c b/arch/sparc/kernel/of_device.c
index 0837bd52e28f..0a83bd737654 100644
--- a/arch/sparc/kernel/of_device.c
+++ b/arch/sparc/kernel/of_device.c
@@ -563,9 +563,9 @@ build_resources:
563 op->dev.parent = parent; 563 op->dev.parent = parent;
564 op->dev.bus = &of_platform_bus_type; 564 op->dev.bus = &of_platform_bus_type;
565 if (!parent) 565 if (!parent)
566 strcpy(op->dev.bus_id, "root"); 566 dev_set_name(&op->dev, "root");
567 else 567 else
568 sprintf(op->dev.bus_id, "%08x", dp->node); 568 dev_set_name(&op->dev, "%08x", dp->node);
569 569
570 if (of_device_register(op)) { 570 if (of_device_register(op)) {
571 printk("%s: Could not register of device.\n", 571 printk("%s: Could not register of device.\n",
diff --git a/arch/x86/include/asm/acpi.h b/arch/x86/include/asm/acpi.h
index 8d676d8ecde9..9830681446ad 100644
--- a/arch/x86/include/asm/acpi.h
+++ b/arch/x86/include/asm/acpi.h
@@ -113,7 +113,6 @@ static inline void acpi_disable_pci(void)
113 acpi_pci_disabled = 1; 113 acpi_pci_disabled = 1;
114 acpi_noirq_set(); 114 acpi_noirq_set();
115} 115}
116extern int acpi_irq_balance_set(char *str);
117 116
118/* routines for saving/restoring kernel state */ 117/* routines for saving/restoring kernel state */
119extern int acpi_save_state_mem(void); 118extern int acpi_save_state_mem(void);
diff --git a/arch/x86/include/asm/iommu.h b/arch/x86/include/asm/iommu.h
index e4a552d44465..0b500c5b6446 100644
--- a/arch/x86/include/asm/iommu.h
+++ b/arch/x86/include/asm/iommu.h
@@ -6,7 +6,6 @@ extern void no_iommu_init(void);
6extern struct dma_mapping_ops nommu_dma_ops; 6extern struct dma_mapping_ops nommu_dma_ops;
7extern int force_iommu, no_iommu; 7extern int force_iommu, no_iommu;
8extern int iommu_detected; 8extern int iommu_detected;
9extern int dmar_disabled;
10 9
11extern unsigned long iommu_nr_pages(unsigned long addr, unsigned long len); 10extern unsigned long iommu_nr_pages(unsigned long addr, unsigned long len);
12 11
diff --git a/arch/x86/kernel/acpi/boot.c b/arch/x86/kernel/acpi/boot.c
index 8c1f76abae9e..4c51a2f8fd31 100644
--- a/arch/x86/kernel/acpi/boot.c
+++ b/arch/x86/kernel/acpi/boot.c
@@ -1343,7 +1343,6 @@ static void __init acpi_process_madt(void)
1343 error = acpi_parse_madt_ioapic_entries(); 1343 error = acpi_parse_madt_ioapic_entries();
1344 if (!error) { 1344 if (!error) {
1345 acpi_irq_model = ACPI_IRQ_MODEL_IOAPIC; 1345 acpi_irq_model = ACPI_IRQ_MODEL_IOAPIC;
1346 acpi_irq_balance_set(NULL);
1347 acpi_ioapic = 1; 1346 acpi_ioapic = 1;
1348 1347
1349 smp_found_config = 1; 1348 smp_found_config = 1;
diff --git a/arch/x86/kernel/early-quirks.c b/arch/x86/kernel/early-quirks.c
index 3ce029ffaa55..1b894b72c0f5 100644
--- a/arch/x86/kernel/early-quirks.c
+++ b/arch/x86/kernel/early-quirks.c
@@ -188,20 +188,6 @@ static void __init ati_bugs_contd(int num, int slot, int func)
188} 188}
189#endif 189#endif
190 190
191#ifdef CONFIG_DMAR
192static void __init intel_g33_dmar(int num, int slot, int func)
193{
194 struct acpi_table_header *dmar_tbl;
195 acpi_status status;
196
197 status = acpi_get_table(ACPI_SIG_DMAR, 0, &dmar_tbl);
198 if (ACPI_SUCCESS(status)) {
199 printk(KERN_INFO "BIOS BUG: DMAR advertised on Intel G31/G33 chipset -- ignoring\n");
200 dmar_disabled = 1;
201 }
202}
203#endif
204
205#define QFLAG_APPLY_ONCE 0x1 191#define QFLAG_APPLY_ONCE 0x1
206#define QFLAG_APPLIED 0x2 192#define QFLAG_APPLIED 0x2
207#define QFLAG_DONE (QFLAG_APPLY_ONCE|QFLAG_APPLIED) 193#define QFLAG_DONE (QFLAG_APPLY_ONCE|QFLAG_APPLIED)
@@ -225,10 +211,6 @@ static struct chipset early_qrk[] __initdata = {
225 PCI_CLASS_SERIAL_SMBUS, PCI_ANY_ID, 0, ati_bugs }, 211 PCI_CLASS_SERIAL_SMBUS, PCI_ANY_ID, 0, ati_bugs },
226 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS, 212 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS,
227 PCI_CLASS_SERIAL_SMBUS, PCI_ANY_ID, 0, ati_bugs_contd }, 213 PCI_CLASS_SERIAL_SMBUS, PCI_ANY_ID, 0, ati_bugs_contd },
228#ifdef CONFIG_DMAR
229 { PCI_VENDOR_ID_INTEL, 0x29c0,
230 PCI_CLASS_BRIDGE_HOST, PCI_ANY_ID, 0, intel_g33_dmar },
231#endif
232 {} 214 {}
233}; 215};
234 216
diff --git a/arch/x86/kernel/kvmclock.c b/arch/x86/kernel/kvmclock.c
index 774ac4991568..1c9cc431ea4f 100644
--- a/arch/x86/kernel/kvmclock.c
+++ b/arch/x86/kernel/kvmclock.c
@@ -128,7 +128,7 @@ static int kvm_register_clock(char *txt)
128} 128}
129 129
130#ifdef CONFIG_X86_LOCAL_APIC 130#ifdef CONFIG_X86_LOCAL_APIC
131static void kvm_setup_secondary_clock(void) 131static void __devinit kvm_setup_secondary_clock(void)
132{ 132{
133 /* 133 /*
134 * Now that the first cpu already had this clocksource initialized, 134 * Now that the first cpu already had this clocksource initialized,
diff --git a/arch/x86/kvm/Kconfig b/arch/x86/kvm/Kconfig
index ce3251ce5504..b81125f0bdee 100644
--- a/arch/x86/kvm/Kconfig
+++ b/arch/x86/kvm/Kconfig
@@ -20,6 +20,8 @@ if VIRTUALIZATION
20config KVM 20config KVM
21 tristate "Kernel-based Virtual Machine (KVM) support" 21 tristate "Kernel-based Virtual Machine (KVM) support"
22 depends on HAVE_KVM 22 depends on HAVE_KVM
23 # for device assignment:
24 depends on PCI
23 select PREEMPT_NOTIFIERS 25 select PREEMPT_NOTIFIERS
24 select MMU_NOTIFIER 26 select MMU_NOTIFIER
25 select ANON_INODES 27 select ANON_INODES
diff --git a/arch/x86/kvm/i8254.c b/arch/x86/kvm/i8254.c
index 8772dc946823..59ebd37ad79e 100644
--- a/arch/x86/kvm/i8254.c
+++ b/arch/x86/kvm/i8254.c
@@ -548,8 +548,10 @@ struct kvm_pit *kvm_create_pit(struct kvm *kvm)
548 mutex_lock(&kvm->lock); 548 mutex_lock(&kvm->lock);
549 pit->irq_source_id = kvm_request_irq_source_id(kvm); 549 pit->irq_source_id = kvm_request_irq_source_id(kvm);
550 mutex_unlock(&kvm->lock); 550 mutex_unlock(&kvm->lock);
551 if (pit->irq_source_id < 0) 551 if (pit->irq_source_id < 0) {
552 kfree(pit);
552 return NULL; 553 return NULL;
554 }
553 555
554 mutex_init(&pit->pit_state.lock); 556 mutex_init(&pit->pit_state.lock);
555 mutex_lock(&pit->pit_state.lock); 557 mutex_lock(&pit->pit_state.lock);
diff --git a/arch/x86/kvm/mmu.c b/arch/x86/kvm/mmu.c
index 2a5e64881d9b..f1983d9477cd 100644
--- a/arch/x86/kvm/mmu.c
+++ b/arch/x86/kvm/mmu.c
@@ -314,7 +314,7 @@ static int mmu_topup_memory_caches(struct kvm_vcpu *vcpu)
314 if (r) 314 if (r)
315 goto out; 315 goto out;
316 r = mmu_topup_memory_cache(&vcpu->arch.mmu_rmap_desc_cache, 316 r = mmu_topup_memory_cache(&vcpu->arch.mmu_rmap_desc_cache,
317 rmap_desc_cache, 1); 317 rmap_desc_cache, 4);
318 if (r) 318 if (r)
319 goto out; 319 goto out;
320 r = mmu_topup_memory_cache_page(&vcpu->arch.mmu_page_cache, 8); 320 r = mmu_topup_memory_cache_page(&vcpu->arch.mmu_page_cache, 8);
diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c
index 2643b430d83a..d06b4dc0e2ea 100644
--- a/arch/x86/kvm/vmx.c
+++ b/arch/x86/kvm/vmx.c
@@ -3564,7 +3564,8 @@ static int __init vmx_init(void)
3564 bypass_guest_pf = 0; 3564 bypass_guest_pf = 0;
3565 kvm_mmu_set_base_ptes(VMX_EPT_READABLE_MASK | 3565 kvm_mmu_set_base_ptes(VMX_EPT_READABLE_MASK |
3566 VMX_EPT_WRITABLE_MASK | 3566 VMX_EPT_WRITABLE_MASK |
3567 VMX_EPT_DEFAULT_MT << VMX_EPT_MT_EPTE_SHIFT); 3567 VMX_EPT_DEFAULT_MT << VMX_EPT_MT_EPTE_SHIFT |
3568 VMX_EPT_IGMT_BIT);
3568 kvm_mmu_set_mask_ptes(0ull, 0ull, 0ull, 0ull, 3569 kvm_mmu_set_mask_ptes(0ull, 0ull, 0ull, 0ull,
3569 VMX_EPT_EXECUTABLE_MASK); 3570 VMX_EPT_EXECUTABLE_MASK);
3570 kvm_enable_tdp(); 3571 kvm_enable_tdp();
diff --git a/arch/x86/kvm/vmx.h b/arch/x86/kvm/vmx.h
index 3e010d21fdd7..ec5edc339da6 100644
--- a/arch/x86/kvm/vmx.h
+++ b/arch/x86/kvm/vmx.h
@@ -352,6 +352,7 @@ enum vmcs_field {
352#define VMX_EPT_READABLE_MASK 0x1ull 352#define VMX_EPT_READABLE_MASK 0x1ull
353#define VMX_EPT_WRITABLE_MASK 0x2ull 353#define VMX_EPT_WRITABLE_MASK 0x2ull
354#define VMX_EPT_EXECUTABLE_MASK 0x4ull 354#define VMX_EPT_EXECUTABLE_MASK 0x4ull
355#define VMX_EPT_IGMT_BIT (1ull << 6)
355 356
356#define VMX_EPT_IDENTITY_PAGETABLE_ADDR 0xfffbc000ul 357#define VMX_EPT_IDENTITY_PAGETABLE_ADDR 0xfffbc000ul
357 358
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-28 13:23:15 -0500