From 72bc2b1ad62f4d2f0a51b35829093d41f55accce Mon Sep 17 00:00:00 2001 From: Nicolas Pitre Date: Sat, 8 Nov 2008 21:15:53 +0100 Subject: [ARM] 5329/1: Feroceon: fix feroceon_l2_inv_range Same fix as commit c7cf72dcadb: when 'start' and 'end' are less than a cacheline apart and 'start' is unaligned we are done after cleaning and invalidating the first cacheline. Cc: Signed-off-by: Nicolas Pitre Signed-off-by: Russell King --- arch/arm/mm/cache-feroceon-l2.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/arm/mm/cache-feroceon-l2.c b/arch/arm/mm/cache-feroceon-l2.c index 13cdae8b0d44..80cd207cbaea 100644 --- a/arch/arm/mm/cache-feroceon-l2.c +++ b/arch/arm/mm/cache-feroceon-l2.c @@ -150,7 +150,7 @@ static void feroceon_l2_inv_range(unsigned long start, unsigned long end) /* * Clean and invalidate partial last cache line. */ - if (end & (CACHE_LINE_SIZE - 1)) { + if (start < end && end & (CACHE_LINE_SIZE - 1)) { l2_clean_inv_pa(end & ~(CACHE_LINE_SIZE - 1)); end &= ~(CACHE_LINE_SIZE - 1); } @@ -158,7 +158,7 @@ static void feroceon_l2_inv_range(unsigned long start, unsigned long end) /* * Invalidate all full cache lines between 'start' and 'end'. */ - while (start != end) { + while (start < end) { unsigned long range_end = calc_range_end(start, end); l2_inv_pa_range(start, range_end - CACHE_LINE_SIZE); start = range_end; -- cgit v1.2.2 From 0fded351a7d03fc69484d5a9e655fbd15a8e7dab Mon Sep 17 00:00:00 2001 From: Russell King Date: Sat, 8 Nov 2008 19:14:56 +0000 Subject: [ARM] realview: correct MMC clock rate The MMC clock source is actually 24MHz, not 33MHz. Signed-off-by: Russell King --- arch/arm/mach-realview/clock.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/mach-realview/clock.c b/arch/arm/mach-realview/clock.c index 3e706c57833a..3347c4236a60 100644 --- a/arch/arm/mach-realview/clock.c +++ b/arch/arm/mach-realview/clock.c @@ -104,7 +104,7 @@ static struct clk uart_clk = { static struct clk mmci_clk = { .name = "MCLK", - .rate = 33000000, + .rate = 24000000, }; int clk_register(struct clk *clk) -- cgit v1.2.2 From 7bfc0b2e266dd4cd3d3f27a3ad31bf79974190b1 Mon Sep 17 00:00:00 2001 From: Russell King Date: Sat, 8 Nov 2008 20:12:36 +0000 Subject: [ARM] versatile: correct MMC clock rate The MMC clock source is actually 24MHz, not 33MHz. Signed-off-by: Russell King --- arch/arm/mach-versatile/clock.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/mach-versatile/clock.c b/arch/arm/mach-versatile/clock.c index 9336508ec0b2..58937f1fb38c 100644 --- a/arch/arm/mach-versatile/clock.c +++ b/arch/arm/mach-versatile/clock.c @@ -105,7 +105,7 @@ static struct clk uart_clk = { static struct clk mmci_clk = { .name = "MCLK", - .rate = 33000000, + .rate = 24000000, }; int clk_register(struct clk *clk) -- cgit v1.2.2 From ebb4c65869db7213280ad9c510637683939b5ff8 Mon Sep 17 00:00:00 2001 From: Russell King Date: Sun, 9 Nov 2008 11:18:36 +0000 Subject: [ARM] iop: iop3xx needs registers mapped uncached+unbuffered Mikael Pettersson reported: The 2.6.28-rc kernels fail to detect PCI device 0000:00:01.0 (the first ethernet port) on my Thecus n2100 XScale box. There is however still a strange "ghost" device that gets partially detected in 2.6.28-rc2 vanilla. The IOP321 manual says: The user designates the memory region containing the OCCDR as non-cacheable and non-bufferable from the IntelR XScaleTM core. This guarantees that all load/stores to the OCCDR are only of DWORD quantities. Ensure that the OCCDR is so mapped. Signed-off-by: Russell King --- arch/arm/include/asm/mach/map.h | 13 +++++++------ arch/arm/mm/mmu.c | 6 ++++++ arch/arm/plat-iop/setup.c | 5 +++-- 3 files changed, 16 insertions(+), 8 deletions(-) (limited to 'arch') diff --git a/arch/arm/include/asm/mach/map.h b/arch/arm/include/asm/mach/map.h index cb1139ac1943..39d949b63e80 100644 --- a/arch/arm/include/asm/mach/map.h +++ b/arch/arm/include/asm/mach/map.h @@ -19,12 +19,13 @@ struct map_desc { }; /* types 0-3 are defined in asm/io.h */ -#define MT_CACHECLEAN 4 -#define MT_MINICLEAN 5 -#define MT_LOW_VECTORS 6 -#define MT_HIGH_VECTORS 7 -#define MT_MEMORY 8 -#define MT_ROM 9 +#define MT_UNCACHED 4 +#define MT_CACHECLEAN 5 +#define MT_MINICLEAN 6 +#define MT_LOW_VECTORS 7 +#define MT_HIGH_VECTORS 8 +#define MT_MEMORY 9 +#define MT_ROM 10 #ifdef CONFIG_MMU extern void iotable_init(struct map_desc *, int); diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c index e63db11f16a8..7f36c825718d 100644 --- a/arch/arm/mm/mmu.c +++ b/arch/arm/mm/mmu.c @@ -208,6 +208,12 @@ static struct mem_type mem_types[] = { .prot_sect = PROT_SECT_DEVICE, .domain = DOMAIN_IO, }, + [MT_UNCACHED] = { + .prot_pte = PROT_PTE_DEVICE, + .prot_l1 = PMD_TYPE_TABLE, + .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN, + .domain = DOMAIN_IO, + }, [MT_CACHECLEAN] = { .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN, .domain = DOMAIN_KERNEL, diff --git a/arch/arm/plat-iop/setup.c b/arch/arm/plat-iop/setup.c index 4689db638e95..9e573e78176a 100644 --- a/arch/arm/plat-iop/setup.c +++ b/arch/arm/plat-iop/setup.c @@ -16,14 +16,15 @@ #include /* - * Standard IO mapping for all IOP3xx based systems + * Standard IO mapping for all IOP3xx based systems. Note that + * the IOP3xx OCCDR must be mapped uncached and unbuffered. */ static struct map_desc iop3xx_std_desc[] __initdata = { { /* mem mapped registers */ .virtual = IOP3XX_PERIPHERAL_VIRT_BASE, .pfn = __phys_to_pfn(IOP3XX_PERIPHERAL_PHYS_BASE), .length = IOP3XX_PERIPHERAL_SIZE, - .type = MT_DEVICE, + .type = MT_UNCACHED, }, { /* PCI IO space */ .virtual = IOP3XX_PCI_LOWER_IO_VA, .pfn = __phys_to_pfn(IOP3XX_PCI_LOWER_IO_PA), -- cgit v1.2.2 From acca4f4d9bd657e8bc7e1665ba5077465138f133 Mon Sep 17 00:00:00 2001 From: Paul Mundt Date: Mon, 10 Nov 2008 20:00:45 +0900 Subject: sh: Handle fixmap TLB eviction more coherently. There was a race in the kmap_coherent() implementation. While we guarded against preemption, there was nothing preventing eviction of the pre-faulted fixmap entry from the UTLB. Under certain workloads this would result in the fixmap entries used for cache colouring being evicted from the UTLB in the midst of a copy_page(). In addition to pre-faulting, we also make sure to preserve the PTEs in the kernel page table and introduce a cached PTE for kmap_coherent() usage. This follows a similar change on MIPS ("[MIPS] Fix aliasing bug in copy_to_user_page / copy_from_user_page"). Reported-by: Hideo Saito Reported-by: CHIKAMA Masaki Tested-by: Yoshihiro Shimoda Signed-off-by: Paul Mundt --- arch/sh/include/asm/pgtable.h | 6 ++++++ arch/sh/mm/init.c | 12 +++++++++--- arch/sh/mm/pg-sh4.c | 17 +++++++++++++++++ 3 files changed, 32 insertions(+), 3 deletions(-) (limited to 'arch') diff --git a/arch/sh/include/asm/pgtable.h b/arch/sh/include/asm/pgtable.h index 52220d70a096..b517ae08b9c0 100644 --- a/arch/sh/include/asm/pgtable.h +++ b/arch/sh/include/asm/pgtable.h @@ -148,6 +148,12 @@ extern void paging_init(void); extern void page_table_range_init(unsigned long start, unsigned long end, pgd_t *pgd); +#if !defined(CONFIG_CACHE_OFF) && defined(CONFIG_CPU_SH4) && defined(CONFIG_MMU) +extern void kmap_coherent_init(void); +#else +#define kmap_coherent_init() do { } while (0) +#endif + #include #endif /* __ASM_SH_PGTABLE_H */ diff --git a/arch/sh/mm/init.c b/arch/sh/mm/init.c index 4abf00031dae..6cbef8caeb56 100644 --- a/arch/sh/mm/init.c +++ b/arch/sh/mm/init.c @@ -137,6 +137,7 @@ void __init page_table_range_init(unsigned long start, unsigned long end, void __init paging_init(void) { unsigned long max_zone_pfns[MAX_NR_ZONES]; + unsigned long vaddr; int nid; /* We don't need to map the kernel through the TLB, as @@ -148,10 +149,15 @@ void __init paging_init(void) * check for a null value. */ set_TTB(swapper_pg_dir); - /* Populate the relevant portions of swapper_pg_dir so that + /* + * Populate the relevant portions of swapper_pg_dir so that * we can use the fixmap entries without calling kmalloc. - * pte's will be filled in by __set_fixmap(). */ - page_table_range_init(FIXADDR_START, FIXADDR_TOP, swapper_pg_dir); + * pte's will be filled in by __set_fixmap(). + */ + vaddr = __fix_to_virt(__end_of_fixed_addresses - 1) & PMD_MASK; + page_table_range_init(vaddr, 0, swapper_pg_dir); + + kmap_coherent_init(); memset(max_zone_pfns, 0, sizeof(max_zone_pfns)); diff --git a/arch/sh/mm/pg-sh4.c b/arch/sh/mm/pg-sh4.c index 38870e0fc182..2fe14da1f839 100644 --- a/arch/sh/mm/pg-sh4.c +++ b/arch/sh/mm/pg-sh4.c @@ -7,6 +7,7 @@ * Released under the terms of the GNU GPL v2.0. */ #include +#include #include #include #include @@ -16,6 +17,20 @@ #define CACHE_ALIAS (current_cpu_data.dcache.alias_mask) +#define kmap_get_fixmap_pte(vaddr) \ + pte_offset_kernel(pmd_offset(pud_offset(pgd_offset_k(vaddr), (vaddr)), (vaddr)), (vaddr)) + +static pte_t *kmap_coherent_pte; + +void __init kmap_coherent_init(void) +{ + unsigned long vaddr; + + /* cache the first coherent kmap pte */ + vaddr = __fix_to_virt(FIX_CMAP_BEGIN); + kmap_coherent_pte = kmap_get_fixmap_pte(vaddr); +} + static inline void *kmap_coherent(struct page *page, unsigned long addr) { enum fixed_addresses idx; @@ -34,6 +49,8 @@ static inline void *kmap_coherent(struct page *page, unsigned long addr) update_mmu_cache(NULL, vaddr, pte); + set_pte(kmap_coherent_pte - (FIX_CMAP_END - idx), pte); + return (void *)vaddr; } -- cgit v1.2.2 From c41ef344de212bd918f7765af21b5008628c03e0 Mon Sep 17 00:00:00 2001 From: Marcelo Tosatti Date: Tue, 28 Oct 2008 18:16:58 -0200 Subject: KVM: MMU: increase per-vcpu rmap cache alloc size The page fault path can use two rmap_desc structures, if: - walk_addr's dirty pte update allocates one rmap_desc. - mmu_lock is dropped, sptes are zapped resulting in rmap_desc being freed. - fetch->mmu_set_spte allocates another rmap_desc. Increase to 4 for safety. Signed-off-by: Marcelo Tosatti Signed-off-by: Avi Kivity --- arch/x86/kvm/mmu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/x86/kvm/mmu.c b/arch/x86/kvm/mmu.c index 2a5e64881d9b..f1983d9477cd 100644 --- a/arch/x86/kvm/mmu.c +++ b/arch/x86/kvm/mmu.c @@ -314,7 +314,7 @@ static int mmu_topup_memory_caches(struct kvm_vcpu *vcpu) if (r) goto out; r = mmu_topup_memory_cache(&vcpu->arch.mmu_rmap_desc_cache, - rmap_desc_cache, 1); + rmap_desc_cache, 4); if (r) goto out; r = mmu_topup_memory_cache_page(&vcpu->arch.mmu_page_cache, 8); -- cgit v1.2.2 From a2e4e28946c2c282a040ba4945c8f7288de69118 Mon Sep 17 00:00:00 2001 From: Xiantao Zhang Date: Thu, 23 Oct 2008 15:02:52 +0800 Subject: KVM: ia64: Use guest signal mask when blocking Before a vcpu blocks, it should switch to the guest signal mask to allow signals to unblock it. Signed-off-by: Xiantao Zhang Signed-off-by: Avi Kivity --- arch/ia64/kvm/kvm-ia64.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) (limited to 'arch') diff --git a/arch/ia64/kvm/kvm-ia64.c b/arch/ia64/kvm/kvm-ia64.c index 3caac477de9e..af1464f7a6ad 100644 --- a/arch/ia64/kvm/kvm-ia64.c +++ b/arch/ia64/kvm/kvm-ia64.c @@ -673,16 +673,16 @@ int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) vcpu_load(vcpu); + if (vcpu->sigset_active) + sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved); + if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) { kvm_vcpu_block(vcpu); clear_bit(KVM_REQ_UNHALT, &vcpu->requests); - vcpu_put(vcpu); - return -EAGAIN; + r = -EAGAIN; + goto out; } - if (vcpu->sigset_active) - sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved); - if (vcpu->mmio_needed) { memcpy(vcpu->mmio_data, kvm_run->mmio.data, 8); kvm_set_mmio_data(vcpu); @@ -690,7 +690,7 @@ int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) vcpu->mmio_needed = 0; } r = __vcpu_run(vcpu, kvm_run); - +out: if (vcpu->sigset_active) sigprocmask(SIG_SETMASK, &sigsaved, NULL); -- cgit v1.2.2 From a29a2af378f3f6362b68e126e2541c8bde885ead Mon Sep 17 00:00:00 2001 From: Rakib Mullick Date: Wed, 29 Oct 2008 14:13:39 -0700 Subject: x86: KVM guest: fix section mismatch warning in kvmclock.c WARNING: arch/x86/kernel/built-in.o(.text+0x1722c): Section mismatch in reference from the function kvm_setup_secondary_clock() to the function .devinit.text:setup_secondary_APIC_clock() The function kvm_setup_secondary_clock() references the function __devinit setup_secondary_APIC_clock(). This is often because kvm_setup_secondary_clock lacks a __devinit annotation or the annotation of setup_secondary_APIC_clock is wrong. Signed-off-by: Md.Rakib H. Mullick Cc: Ingo Molnar Signed-off-by: Andrew Morton Signed-off-by: Avi Kivity --- arch/x86/kernel/kvmclock.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/x86/kernel/kvmclock.c b/arch/x86/kernel/kvmclock.c index 774ac4991568..1c9cc431ea4f 100644 --- a/arch/x86/kernel/kvmclock.c +++ b/arch/x86/kernel/kvmclock.c @@ -128,7 +128,7 @@ static int kvm_register_clock(char *txt) } #ifdef CONFIG_X86_LOCAL_APIC -static void kvm_setup_secondary_clock(void) +static void __devinit kvm_setup_secondary_clock(void) { /* * Now that the first cpu already had this clocksource initialized, -- cgit v1.2.2 From ca93e992fdfdc6569ac2845d7560eeb5de4a4e0b Mon Sep 17 00:00:00 2001 From: Avi Kivity Date: Tue, 4 Nov 2008 11:25:17 +0200 Subject: KVM: Require the PCI subsystem PCI device assignment makes calls to pci code, so require it to be built into the kernel. Signed-off-by: Avi Kivity --- arch/ia64/kvm/Kconfig | 2 ++ arch/x86/kvm/Kconfig | 2 ++ 2 files changed, 4 insertions(+) (limited to 'arch') diff --git a/arch/ia64/kvm/Kconfig b/arch/ia64/kvm/Kconfig index 8e99fed6b3fd..f833a0b4188d 100644 --- a/arch/ia64/kvm/Kconfig +++ b/arch/ia64/kvm/Kconfig @@ -20,6 +20,8 @@ if VIRTUALIZATION config KVM tristate "Kernel-based Virtual Machine (KVM) support" depends on HAVE_KVM && EXPERIMENTAL + # for device assignment: + depends on PCI select PREEMPT_NOTIFIERS select ANON_INODES ---help--- diff --git a/arch/x86/kvm/Kconfig b/arch/x86/kvm/Kconfig index ce3251ce5504..b81125f0bdee 100644 --- a/arch/x86/kvm/Kconfig +++ b/arch/x86/kvm/Kconfig @@ -20,6 +20,8 @@ if VIRTUALIZATION config KVM tristate "Kernel-based Virtual Machine (KVM) support" depends on HAVE_KVM + # for device assignment: + depends on PCI select PREEMPT_NOTIFIERS select MMU_NOTIFIER select ANON_INODES -- cgit v1.2.2 From 928d4bf747e9c290b690ff515d8f81e8ee226d97 Mon Sep 17 00:00:00 2001 From: Sheng Yang Date: Thu, 6 Nov 2008 14:55:45 +0800 Subject: KVM: VMX: Set IGMT bit in EPT entry There is a potential issue that, when guest using pagetable without vmexit when EPT enabled, guest would use PAT/PCD/PWT bits to index PAT msr for it's memory, which would be inconsistent with host side and would cause host MCE due to inconsistent cache attribute. The patch set IGMT bit in EPT entry to ignore guest PAT and use WB as default memory type to protect host (notice that all memory mapped by KVM should be WB). Signed-off-by: Sheng Yang Signed-off-by: Avi Kivity --- arch/x86/kvm/vmx.c | 3 ++- arch/x86/kvm/vmx.h | 1 + 2 files changed, 3 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c index 2643b430d83a..d06b4dc0e2ea 100644 --- a/arch/x86/kvm/vmx.c +++ b/arch/x86/kvm/vmx.c @@ -3564,7 +3564,8 @@ static int __init vmx_init(void) bypass_guest_pf = 0; kvm_mmu_set_base_ptes(VMX_EPT_READABLE_MASK | VMX_EPT_WRITABLE_MASK | - VMX_EPT_DEFAULT_MT << VMX_EPT_MT_EPTE_SHIFT); + VMX_EPT_DEFAULT_MT << VMX_EPT_MT_EPTE_SHIFT | + VMX_EPT_IGMT_BIT); kvm_mmu_set_mask_ptes(0ull, 0ull, 0ull, 0ull, VMX_EPT_EXECUTABLE_MASK); kvm_enable_tdp(); diff --git a/arch/x86/kvm/vmx.h b/arch/x86/kvm/vmx.h index 3e010d21fdd7..ec5edc339da6 100644 --- a/arch/x86/kvm/vmx.h +++ b/arch/x86/kvm/vmx.h @@ -352,6 +352,7 @@ enum vmcs_field { #define VMX_EPT_READABLE_MASK 0x1ull #define VMX_EPT_WRITABLE_MASK 0x2ull #define VMX_EPT_EXECUTABLE_MASK 0x4ull +#define VMX_EPT_IGMT_BIT (1ull << 6) #define VMX_EPT_IDENTITY_PAGETABLE_ADDR 0xfffbc000ul -- cgit v1.2.2 From c60ff51eb26dfcfb0bdc807b09a096aeadd01325 Mon Sep 17 00:00:00 2001 From: Xiantao Zhang Date: Sat, 8 Nov 2008 15:46:59 +0800 Subject: KVM: ia64: fix vmm_spin_{un}lock for !CONFIG_SMP In the case of !CONFIG_SMP, raw_spinlock_t is empty and the spinlock functions don't build. Fix by defining spinlock functions for the uniprocessor case. Signed-off-by: Xiantao Zhang Signed-off-by: Avi Kivity --- arch/ia64/kvm/vcpu.h | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch') diff --git a/arch/ia64/kvm/vcpu.h b/arch/ia64/kvm/vcpu.h index 341e3fee280c..e9b2a4e121c0 100644 --- a/arch/ia64/kvm/vcpu.h +++ b/arch/ia64/kvm/vcpu.h @@ -384,6 +384,10 @@ static inline u64 __gpfn_is_io(u64 gpfn) #define MODE_IND(psr) \ (((psr).it << 2) + ((psr).dt << 1) + (psr).rt) +#ifndef CONFIG_SMP +#define _vmm_raw_spin_lock(x) do {}while(0) +#define _vmm_raw_spin_unlock(x) do {}while(0) +#else #define _vmm_raw_spin_lock(x) \ do { \ __u32 *ia64_spinlock_ptr = (__u32 *) (x); \ @@ -403,6 +407,7 @@ static inline u64 __gpfn_is_io(u64 gpfn) do { barrier(); \ ((spinlock_t *)x)->raw_lock.lock = 0; } \ while (0) +#endif void vmm_spin_lock(spinlock_t *lock); void vmm_spin_unlock(spinlock_t *lock); -- cgit v1.2.2 From e17d1dc0863767bab8fde4ba9be92c7f79e7fe50 Mon Sep 17 00:00:00 2001 From: Avi Kivity Date: Tue, 11 Nov 2008 13:09:36 +0200 Subject: KVM: Fix pit memory leak if unable to allocate irq source id MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Reported-By: Daniel Marjamäki Signed-off-by: Avi Kivity --- arch/x86/kvm/i8254.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/x86/kvm/i8254.c b/arch/x86/kvm/i8254.c index 8772dc946823..59ebd37ad79e 100644 --- a/arch/x86/kvm/i8254.c +++ b/arch/x86/kvm/i8254.c @@ -548,8 +548,10 @@ struct kvm_pit *kvm_create_pit(struct kvm *kvm) mutex_lock(&kvm->lock); pit->irq_source_id = kvm_request_irq_source_id(kvm); mutex_unlock(&kvm->lock); - if (pit->irq_source_id < 0) + if (pit->irq_source_id < 0) { + kfree(pit); return NULL; + } mutex_init(&pit->pit_state.lock); mutex_lock(&pit->pit_state.lock); -- cgit v1.2.2 From 65e503814dec83c7b2ac955e75919d009109c919 Mon Sep 17 00:00:00 2001 From: Dan Williams Date: Tue, 11 Nov 2008 13:12:33 -0700 Subject: iop-adma: use iop_paranoia() for debug BUG_ONs Now that the critical read back to flush the next descriptor address is fixed we can downgrade some BUG_ONs that need only be enabled when testing changes to the driver. Signed-off-by: Dan Williams --- arch/arm/include/asm/hardware/iop3xx-adma.h | 5 +++-- arch/arm/include/asm/hardware/iop_adma.h | 6 ++++++ arch/arm/mach-iop13xx/include/mach/adma.h | 3 ++- 3 files changed, 11 insertions(+), 3 deletions(-) (limited to 'arch') diff --git a/arch/arm/include/asm/hardware/iop3xx-adma.h b/arch/arm/include/asm/hardware/iop3xx-adma.h index 87bff09633aa..83e6ba338e2c 100644 --- a/arch/arm/include/asm/hardware/iop3xx-adma.h +++ b/arch/arm/include/asm/hardware/iop3xx-adma.h @@ -730,7 +730,8 @@ static inline void iop_desc_set_next_desc(struct iop_adma_desc_slot *desc, { /* hw_desc->next_desc is the same location for all channels */ union iop3xx_desc hw_desc = { .ptr = desc->hw_desc, }; - BUG_ON(hw_desc.dma->next_desc); + + iop_paranoia(hw_desc.dma->next_desc); hw_desc.dma->next_desc = next_desc_addr; } @@ -760,7 +761,7 @@ static inline int iop_desc_get_zero_result(struct iop_adma_desc_slot *desc) struct iop3xx_desc_aau *hw_desc = desc->hw_desc; struct iop3xx_aau_desc_ctrl desc_ctrl = hw_desc->desc_ctrl_field; - BUG_ON(!(desc_ctrl.tx_complete && desc_ctrl.zero_result_en)); + iop_paranoia(!(desc_ctrl.tx_complete && desc_ctrl.zero_result_en)); return desc_ctrl.zero_result_err; } diff --git a/arch/arm/include/asm/hardware/iop_adma.h b/arch/arm/include/asm/hardware/iop_adma.h index cb7e3611bcba..385c6e8cbbd2 100644 --- a/arch/arm/include/asm/hardware/iop_adma.h +++ b/arch/arm/include/asm/hardware/iop_adma.h @@ -23,6 +23,12 @@ #define IOP_ADMA_SLOT_SIZE 32 #define IOP_ADMA_THRESHOLD 4 +#ifdef DEBUG +#define IOP_PARANOIA 1 +#else +#define IOP_PARANOIA 0 +#endif +#define iop_paranoia(x) BUG_ON(IOP_PARANOIA && (x)) /** * struct iop_adma_device - internal representation of an ADMA device diff --git a/arch/arm/mach-iop13xx/include/mach/adma.h b/arch/arm/mach-iop13xx/include/mach/adma.h index 60019c8e6465..5722e86f2174 100644 --- a/arch/arm/mach-iop13xx/include/mach/adma.h +++ b/arch/arm/mach-iop13xx/include/mach/adma.h @@ -404,7 +404,8 @@ static inline void iop_desc_set_next_desc(struct iop_adma_desc_slot *desc, u32 next_desc_addr) { struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc; - BUG_ON(hw_desc->next_desc); + + iop_paranoia(hw_desc->next_desc); hw_desc->next_desc = next_desc_addr; } -- cgit v1.2.2 From 32836259ff25ce97010569706cd33ba94de81d62 Mon Sep 17 00:00:00 2001 From: Bjorn Helgaas Date: Wed, 5 Nov 2008 16:17:52 -0700 Subject: ACPI: pci_link: remove acpi_irq_balance_set() interface This removes the acpi_irq_balance_set() interface from the PCI interrupt link driver. x86 used acpi_irq_balance_set() to tell the PCI interrupt link driver to configure links to minimize IRQ sharing. But the link driver can easily figure out whether to turn on IRQ balancing based on the IRQ model (PIC/IOAPIC/etc), so we can get rid of that external interface. It's better for the driver to figure this out at init-time. If we set it externally via the x86 code, the interface reduces modularity, and we depend on the fact that acpi_process_madt() happens before we process the kernel command line. Signed-off-by: Bjorn Helgaas Signed-off-by: Len Brown --- arch/x86/include/asm/acpi.h | 1 - arch/x86/kernel/acpi/boot.c | 1 - 2 files changed, 2 deletions(-) (limited to 'arch') diff --git a/arch/x86/include/asm/acpi.h b/arch/x86/include/asm/acpi.h index 8d676d8ecde9..9830681446ad 100644 --- a/arch/x86/include/asm/acpi.h +++ b/arch/x86/include/asm/acpi.h @@ -113,7 +113,6 @@ static inline void acpi_disable_pci(void) acpi_pci_disabled = 1; acpi_noirq_set(); } -extern int acpi_irq_balance_set(char *str); /* routines for saving/restoring kernel state */ extern int acpi_save_state_mem(void); diff --git a/arch/x86/kernel/acpi/boot.c b/arch/x86/kernel/acpi/boot.c index 8c1f76abae9e..4c51a2f8fd31 100644 --- a/arch/x86/kernel/acpi/boot.c +++ b/arch/x86/kernel/acpi/boot.c @@ -1343,7 +1343,6 @@ static void __init acpi_process_madt(void) error = acpi_parse_madt_ioapic_entries(); if (!error) { acpi_irq_model = ACPI_IRQ_MODEL_IOAPIC; - acpi_irq_balance_set(NULL); acpi_ioapic = 1; smp_found_config = 1; -- cgit v1.2.2 From 51ee3d92bfb983790b9ed576c22f59d42adff329 Mon Sep 17 00:00:00 2001 From: Yoshihiro Shimoda Date: Tue, 11 Nov 2008 12:19:11 +0900 Subject: fix sci type for SH7723 This patch changes sci type of SH7723 from PORT_SCI to PORT_SCIFA. Signed-off-by: Yoshihiro Shimoda Signed-off-by: Paul Mundt --- arch/sh/kernel/cpu/sh4a/setup-sh7723.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'arch') diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7723.c b/arch/sh/kernel/cpu/sh4a/setup-sh7723.c index a7412cede534..6d9e6972cfc9 100644 --- a/arch/sh/kernel/cpu/sh4a/setup-sh7723.c +++ b/arch/sh/kernel/cpu/sh4a/setup-sh7723.c @@ -119,17 +119,17 @@ static struct plat_sci_port sci_platform_data[] = { },{ .mapbase = 0xa4e30000, .flags = UPF_BOOT_AUTOCONF, - .type = PORT_SCI, + .type = PORT_SCIFA, .irqs = { 56, 56, 56, 56 }, },{ .mapbase = 0xa4e40000, .flags = UPF_BOOT_AUTOCONF, - .type = PORT_SCI, + .type = PORT_SCIFA, .irqs = { 88, 88, 88, 88 }, },{ .mapbase = 0xa4e50000, .flags = UPF_BOOT_AUTOCONF, - .type = PORT_SCI, + .type = PORT_SCIFA, .irqs = { 109, 109, 109, 109 }, }, { .flags = 0, -- cgit v1.2.2 From 185aed75570fb4f78ef283dfa26cd9da5fa06a91 Mon Sep 17 00:00:00 2001 From: Paul Mundt Date: Wed, 12 Nov 2008 12:53:48 +0900 Subject: sh: Provide a sane valid_phys_addr_range() to prevent TLB reset with PMB. With the PMB enabled, only P1SEG and up are covered by the PMB mappings, meaning that situations where out-of-bounds physical addresses are read from will lead to TLB reset after the PMB miss, allowing for use cases like dd if=/dev/mem to reset the TLB. Fix this up to make sure the reference is between __MEMORY_START (phys) and __pa(high_memory). This is coherent across all variants of sh/sh64 with and without MMU, though the PMB bug itself is only applicable to SH-4A parts. Reported-by: Hideo Saito Signed-off-by: Paul Mundt --- arch/sh/include/asm/io.h | 4 ++++ arch/sh/mm/Makefile_32 | 2 +- arch/sh/mm/Makefile_64 | 2 +- arch/sh/mm/mmap.c | 31 +++++++++++++++++++++++++++++++ 4 files changed, 37 insertions(+), 2 deletions(-) create mode 100644 arch/sh/mm/mmap.c (limited to 'arch') diff --git a/arch/sh/include/asm/io.h b/arch/sh/include/asm/io.h index 436c28539577..65eaae34e753 100644 --- a/arch/sh/include/asm/io.h +++ b/arch/sh/include/asm/io.h @@ -293,6 +293,10 @@ __ioremap_mode(unsigned long offset, unsigned long size, unsigned long flags) */ #define xlate_dev_kmem_ptr(p) p +#define ARCH_HAS_VALID_PHYS_ADDR_RANGE +int valid_phys_addr_range(unsigned long addr, size_t size); +int valid_mmap_phys_addr_range(unsigned long pfn, size_t size); + #endif /* __KERNEL__ */ #endif /* __ASM_SH_IO_H */ diff --git a/arch/sh/mm/Makefile_32 b/arch/sh/mm/Makefile_32 index 70e0906023cc..f066e76da204 100644 --- a/arch/sh/mm/Makefile_32 +++ b/arch/sh/mm/Makefile_32 @@ -2,7 +2,7 @@ # Makefile for the Linux SuperH-specific parts of the memory manager. # -obj-y := init.o extable_32.o consistent.o +obj-y := init.o extable_32.o consistent.o mmap.o ifndef CONFIG_CACHE_OFF cache-$(CONFIG_CPU_SH2) := cache-sh2.o diff --git a/arch/sh/mm/Makefile_64 b/arch/sh/mm/Makefile_64 index 0d92a8a3ac9a..9481d0f54efd 100644 --- a/arch/sh/mm/Makefile_64 +++ b/arch/sh/mm/Makefile_64 @@ -2,7 +2,7 @@ # Makefile for the Linux SuperH-specific parts of the memory manager. # -obj-y := init.o consistent.o +obj-y := init.o consistent.o mmap.o mmu-y := tlb-nommu.o pg-nommu.o extable_32.o mmu-$(CONFIG_MMU) := fault_64.o ioremap_64.o tlbflush_64.o tlb-sh5.o \ diff --git a/arch/sh/mm/mmap.c b/arch/sh/mm/mmap.c new file mode 100644 index 000000000000..1f3cc3d92d3d --- /dev/null +++ b/arch/sh/mm/mmap.c @@ -0,0 +1,31 @@ +/* + * arch/sh/mm/mmap.c + * + * Copyright (C) 2008 Paul Mundt + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ +#include +#include +#include + +/* + * You really shouldn't be using read() or write() on /dev/mem. This + * might go away in the future. + */ +int valid_phys_addr_range(unsigned long addr, size_t count) +{ + if (addr < (PAGE_OFFSET + (PFN_START << PAGE_SHIFT))) + return 0; + if (addr + count > __pa(high_memory)) + return 0; + + return 1; +} + +int valid_mmap_phys_addr_range(unsigned long pfn, size_t size) +{ + return 1; +} -- cgit v1.2.2 From 31ea24bba77a16d3220b0822838785cbafb78175 Mon Sep 17 00:00:00 2001 From: David Howells Date: Wed, 12 Nov 2008 15:34:59 +0000 Subject: MN10300: Clean up the misalignment handler a little Clean up the MN10300 misalignment handler a little by: (1) Use ilog2() rather than doing implementing log2() locally. (2) Make format_tbl[] const and static. (3) Making the debugging prints more consistent. Signed-off-by: David Howells Signed-off-by: Linus Torvalds --- arch/mn10300/mm/misalignment.c | 27 +++++++++------------------ 1 file changed, 9 insertions(+), 18 deletions(-) (limited to 'arch') diff --git a/arch/mn10300/mm/misalignment.c b/arch/mn10300/mm/misalignment.c index 32aa89dc3848..416c43baaa21 100644 --- a/arch/mn10300/mm/misalignment.c +++ b/arch/mn10300/mm/misalignment.c @@ -37,7 +37,7 @@ #include #if 0 -#define kdebug(FMT, ...) printk(KERN_DEBUG FMT, ##__VA_ARGS__) +#define kdebug(FMT, ...) printk(KERN_DEBUG "MISALIGN: "FMT"\n", ##__VA_ARGS__) #else #define kdebug(FMT, ...) do {} while (0) #endif @@ -50,14 +50,6 @@ static int misalignment_reg(unsigned long *registers, unsigned params, unsigned opcode, unsigned disp, unsigned long **_register); -static inline unsigned int_log2(unsigned x) -{ - unsigned y; - asm("bsch %1,%0" : "=r"(y) : "r"(x), "0"(0)); - return y; -} -#define log2(x) int_log2(x) - static const unsigned Dreg_index[] = { REG_D0 >> 2, REG_D1 >> 2, REG_D2 >> 2, REG_D3 >> 2 }; @@ -88,7 +80,7 @@ enum format_id { FMT_D9, }; -struct { +static const struct { u_int8_t opsz, dispsz; } format_tbl[16] = { [FMT_S0] = { 8, 0 }, @@ -273,7 +265,7 @@ asmlinkage void misalignment(struct pt_regs *regs, enum exception_code code) void *address; unsigned tmp, npop; - kdebug("MISALIGN at %lx\n", regs->pc); + kdebug("==>misalignment({pc=%lx})", regs->pc); if (in_interrupt()) die("Misalignment trap in interrupt context", regs, code); @@ -295,7 +287,7 @@ asmlinkage void misalignment(struct pt_regs *regs, enum exception_code code) noc = 8; for (pop = mn10300_opcodes; pop->name; pop++) { - npop = log2(pop->opcode | pop->opmask); + npop = ilog2(pop->opcode | pop->opmask); if (npop <= 0 || npop > 31) continue; npop = (npop + 8) & ~7; @@ -391,7 +383,7 @@ transfer_failed: /* we matched the opcode */ found_opcode: - kdebug("MISALIGN: %lx: %x==%x { %x, %x }\n", + kdebug("%lx: %x==%x { %x, %x }", regs->pc, opcode, pop->opcode, pop->params[0], pop->params[1]); tmp = format_tbl[pop->format].opsz; @@ -442,13 +434,13 @@ found_opcode: goto bad_reg_mode; if (strcmp(pop->name, "mov") == 0) { - kdebug("FIXUP: mov (%p),DARn\n", address); + kdebug("mov (%p),DARn", address); if (copy_from_user(&data, (void *) address, 4) != 0) goto transfer_failed; if (pop->params[0] & 0x1000000) *postinc += 4; } else if (strcmp(pop->name, "movhu") == 0) { - kdebug("FIXUP: movhu (%p),DARn\n", address); + kdebug("movhu (%p),DARn", address); data = 0; if (copy_from_user(&data, (void *) address, 2) != 0) goto transfer_failed; @@ -472,14 +464,13 @@ found_opcode: data = *store; if (strcmp(pop->name, "mov") == 0) { - kdebug("FIXUP: mov %lx,(%p)\n", data, address); + kdebug("mov %lx,(%p)", data, address); if (copy_to_user((void *) address, &data, 4) != 0) goto transfer_failed; if (pop->params[1] & 0x1000000) *postinc += 4; } else if (strcmp(pop->name, "movhu") == 0) { - kdebug("FIXUP: movhu %hx,(%p)\n", - (uint16_t) data, address); + kdebug("movhu %hx,(%p)", (uint16_t) data, address); if (copy_to_user((void *) address, &data, 2) != 0) goto transfer_failed; if (pop->params[1] & 0x1000000) -- cgit v1.2.2 From 9f55588968095306d52bd30564666d4fadce5e39 Mon Sep 17 00:00:00 2001 From: David Howells Date: Wed, 12 Nov 2008 15:35:04 +0000 Subject: MN10300: Add built-in testing for misalignment handler Add configurable built-in testing for the MN10300 misalignment handler. Signed-off-by: David Howells Signed-off-by: Linus Torvalds --- arch/mn10300/Kconfig.debug | 9 +++ arch/mn10300/mm/misalignment.c | 161 +++++++++++++++++++++++++++++++++++++++++ 2 files changed, 170 insertions(+) (limited to 'arch') diff --git a/arch/mn10300/Kconfig.debug b/arch/mn10300/Kconfig.debug index 524e33819f32..ff80e86b9bd2 100644 --- a/arch/mn10300/Kconfig.debug +++ b/arch/mn10300/Kconfig.debug @@ -15,6 +15,15 @@ config DEBUG_DECOMPRESS_KERNEL decompressing Linux seeing "Uncompressing Linux... " and "Ok, booting the kernel.\n" on console. +config TEST_MISALIGNMENT_HANDLER + bool "Run tests on the misalignment handler" + depends on DEBUG_KERNEL + default n + help + If you say Y here the kernel will execute a list of misaligned memory + accesses to make sure the misalignment handler deals them with + correctly. If it does not, the kernel will throw a BUG. + config KPROBES bool "Kprobes" depends on DEBUG_KERNEL diff --git a/arch/mn10300/mm/misalignment.c b/arch/mn10300/mm/misalignment.c index 416c43baaa21..93e09c4be1db 100644 --- a/arch/mn10300/mm/misalignment.c +++ b/arch/mn10300/mm/misalignment.c @@ -650,3 +650,164 @@ static int misalignment_reg(unsigned long *registers, unsigned params, return 1; } + +/* + * misalignment handler tests + */ +#ifdef CONFIG_TEST_MISALIGNMENT_HANDLER +static u8 __initdata testbuf[512] __attribute__((aligned(16))) = { + [257] = 0x11, + [258] = 0x22, + [259] = 0x33, + [260] = 0x44, +}; + +#define ASSERTCMP(X, OP, Y) \ +do { \ + if (unlikely(!((X) OP (Y)))) { \ + printk(KERN_ERR "\n"); \ + printk(KERN_ERR "MISALIGN: Assertion failed at line %u\n", \ + __LINE__); \ + printk(KERN_ERR "0x%lx " #OP " 0x%lx is false\n", \ + (unsigned long)(X), (unsigned long)(Y)); \ + BUG(); \ + } \ +} while(0) + +static int __init test_misalignment(void) +{ + register void *r asm("e0"); + register u32 y asm("e1"); + void *p = testbuf, *q; + u32 tmp, tmp2, x; + + printk(KERN_NOTICE "==>test_misalignment() [testbuf=%p]\n", p); + p++; + + printk(KERN_NOTICE "___ MOV (Am),Dn ___\n"); + q = p + 256; + asm volatile("mov (%0),%1" : "+a"(q), "=d"(x)); + ASSERTCMP(q, ==, p + 256); + ASSERTCMP(x, ==, 0x44332211); + + printk(KERN_NOTICE "___ MOV (256,Am),Dn ___\n"); + q = p; + asm volatile("mov (256,%0),%1" : "+a"(q), "=d"(x)); + ASSERTCMP(q, ==, p); + ASSERTCMP(x, ==, 0x44332211); + + printk(KERN_NOTICE "___ MOV (Di,Am),Dn ___\n"); + tmp = 256; + q = p; + asm volatile("mov (%2,%0),%1" : "+a"(q), "=d"(x), "+d"(tmp)); + ASSERTCMP(q, ==, p); + ASSERTCMP(x, ==, 0x44332211); + ASSERTCMP(tmp, ==, 256); + + printk(KERN_NOTICE "___ MOV (256,Rm),Rn ___\n"); + r = p; + asm volatile("mov (256,%0),%1" : "+r"(r), "=r"(y)); + ASSERTCMP(r, ==, p); + ASSERTCMP(y, ==, 0x44332211); + + printk(KERN_NOTICE "___ MOV (Rm+),Rn ___\n"); + r = p + 256; + asm volatile("mov (%0+),%1" : "+r"(r), "=r"(y)); + ASSERTCMP(r, ==, p + 256 + 4); + ASSERTCMP(y, ==, 0x44332211); + + printk(KERN_NOTICE "___ MOV (Rm+,8),Rn ___\n"); + r = p + 256; + asm volatile("mov (%0+,8),%1" : "+r"(r), "=r"(y)); + ASSERTCMP(r, ==, p + 256 + 8); + ASSERTCMP(y, ==, 0x44332211); + + printk(KERN_NOTICE "___ MOV (7,SP),Rn ___\n"); + asm volatile( + "add -16,sp \n" + "mov +0x11,%0 \n" + "movbu %0,(7,sp) \n" + "mov +0x22,%0 \n" + "movbu %0,(8,sp) \n" + "mov +0x33,%0 \n" + "movbu %0,(9,sp) \n" + "mov +0x44,%0 \n" + "movbu %0,(10,sp) \n" + "mov (7,sp),%1 \n" + "add +16,sp \n" + : "+a"(q), "=d"(x)); + ASSERTCMP(x, ==, 0x44332211); + + printk(KERN_NOTICE "___ MOV (259,SP),Rn ___\n"); + asm volatile( + "add -264,sp \n" + "mov +0x11,%0 \n" + "movbu %0,(259,sp) \n" + "mov +0x22,%0 \n" + "movbu %0,(260,sp) \n" + "mov +0x33,%0 \n" + "movbu %0,(261,sp) \n" + "mov +0x55,%0 \n" + "movbu %0,(262,sp) \n" + "mov (259,sp),%1 \n" + "add +264,sp \n" + : "+d"(tmp), "=d"(x)); + ASSERTCMP(x, ==, 0x55332211); + + printk(KERN_NOTICE "___ MOV (260,SP),Rn ___\n"); + asm volatile( + "add -264,sp \n" + "mov +0x11,%0 \n" + "movbu %0,(260,sp) \n" + "mov +0x22,%0 \n" + "movbu %0,(261,sp) \n" + "mov +0x33,%0 \n" + "movbu %0,(262,sp) \n" + "mov +0x55,%0 \n" + "movbu %0,(263,sp) \n" + "mov (260,sp),%1 \n" + "add +264,sp \n" + : "+d"(tmp), "=d"(x)); + ASSERTCMP(x, ==, 0x55332211); + + + printk(KERN_NOTICE "___ MOV_LNE ___\n"); + tmp = 1; + tmp2 = 2; + q = p + 256; + asm volatile( + "setlb \n" + "mov %2,%3 \n" + "mov %1,%2 \n" + "cmp +0,%1 \n" + "mov_lne (%0+,4),%1" + : "+r"(q), "+d"(tmp), "+d"(tmp2), "=d"(x) + : + : "cc"); + ASSERTCMP(q, ==, p + 256 + 12); + ASSERTCMP(x, ==, 0x44332211); + + printk(KERN_NOTICE "___ MOV in SETLB ___\n"); + tmp = 1; + tmp2 = 2; + q = p + 256; + asm volatile( + "setlb \n" + "mov %1,%3 \n" + "mov (%0+),%1 \n" + "cmp +0,%1 \n" + "lne " + : "+a"(q), "+d"(tmp), "+d"(tmp2), "=d"(x) + : + : "cc"); + + ASSERTCMP(q, ==, p + 256 + 8); + ASSERTCMP(x, ==, 0x44332211); + + printk(KERN_NOTICE "<==test_misalignment()\n"); + return 0; +} + +arch_initcall(test_misalignment); + +#endif /* CONFIG_TEST_MISALIGNMENT_HANDLER */ -- cgit v1.2.2 From ee6e740cf7e5605b353af539eb9a6e17948747b6 Mon Sep 17 00:00:00 2001 From: David Howells Date: Wed, 12 Nov 2008 15:35:09 +0000 Subject: MN10300: Add further misalignment fixups Add further misalignment fixup support to the MN10300 arch, notably for ABS32 and SP+disp addressing. Signed-off-by: David Howells Signed-off-by: Linus Torvalds --- arch/mn10300/mm/misalignment.c | 54 +++++++++++++++++++++++++++++++++++++++++- 1 file changed, 53 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/mn10300/mm/misalignment.c b/arch/mn10300/mm/misalignment.c index 93e09c4be1db..ab03bac497cb 100644 --- a/arch/mn10300/mm/misalignment.c +++ b/arch/mn10300/mm/misalignment.c @@ -120,9 +120,14 @@ enum value_id { SD24, /* 24-bit signed displacement */ SIMM4_2, /* 4-bit signed displacement in opcode bits 4-7 */ SIMM8, /* 8-bit signed immediate */ + IMM8, /* 8-bit unsigned immediate */ + IMM16, /* 16-bit unsigned immediate */ IMM24, /* 24-bit unsigned immediate */ IMM32, /* 32-bit unsigned immediate */ - IMM32_HIGH8, /* 32-bit unsigned immediate, high 8-bits in opcode */ + IMM32_HIGH8, /* 32-bit unsigned immediate, LSB in opcode */ + + IMM32_MEM, /* 32-bit unsigned displacement */ + IMM32_HIGH8_MEM, /* 32-bit unsigned displacement, LSB in opcode */ DN0 = DM0, DN1 = DM1, @@ -177,6 +182,10 @@ struct mn10300_opcode { Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ static const struct mn10300_opcode mn10300_opcodes[] = { +{ "mov", 0x4200, 0xf300, 0, FMT_S1, 0, {DM1, MEM2(IMM8, SP)}}, +{ "mov", 0x4300, 0xf300, 0, FMT_S1, 0, {AM1, MEM2(IMM8, SP)}}, +{ "mov", 0x5800, 0xfc00, 0, FMT_S1, 0, {MEM2(IMM8, SP), DN0}}, +{ "mov", 0x5c00, 0xfc00, 0, FMT_S1, 0, {MEM2(IMM8, SP), AN0}}, { "mov", 0x60, 0xf0, 0, FMT_S0, 0, {DM1, MEM(AN0)}}, { "mov", 0x70, 0xf0, 0, FMT_S0, 0, {MEM(AM0), DN1}}, { "mov", 0xf000, 0xfff0, 0, FMT_D0, 0, {MEM(AM0), AN1}}, @@ -199,24 +208,46 @@ static const struct mn10300_opcode mn10300_opcodes[] = { { "mov", 0xfa100000, 0xfff00000, 0, FMT_D2, 0, {DM1, MEM2(SD16, AN0)}}, { "mov", 0xfa200000, 0xfff00000, 0, FMT_D2, 0, {MEM2(SD16, AM0), AN1}}, { "mov", 0xfa300000, 0xfff00000, 0, FMT_D2, 0, {AM1, MEM2(SD16, AN0)}}, +{ "mov", 0xfa900000, 0xfff30000, 0, FMT_D2, 0, {AM1, MEM2(IMM16, SP)}}, +{ "mov", 0xfa910000, 0xfff30000, 0, FMT_D2, 0, {DM1, MEM2(IMM16, SP)}}, +{ "mov", 0xfab00000, 0xfffc0000, 0, FMT_D2, 0, {MEM2(IMM16, SP), AN0}}, +{ "mov", 0xfab40000, 0xfffc0000, 0, FMT_D2, 0, {MEM2(IMM16, SP), DN0}}, { "mov", 0xfb0a0000, 0xffff0000, 0, FMT_D7, AM33, {MEM2(SD8, RM0), RN2}}, { "mov", 0xfb1a0000, 0xffff0000, 0, FMT_D7, AM33, {RM2, MEM2(SD8, RN0)}}, { "mov", 0xfb6a0000, 0xffff0000, 0x22, FMT_D7, AM33, {MEMINC2 (RM0, SIMM8), RN2}}, { "mov", 0xfb7a0000, 0xffff0000, 0, FMT_D7, AM33, {RM2, MEMINC2 (RN0, SIMM8)}}, +{ "mov", 0xfb8a0000, 0xffff0f00, 0, FMT_D7, AM33, {MEM2(IMM8, SP), RN2}}, { "mov", 0xfb8e0000, 0xffff000f, 0, FMT_D7, AM33, {MEM2(RI, RM0), RD2}}, +{ "mov", 0xfb9a0000, 0xffff0f00, 0, FMT_D7, AM33, {RM2, MEM2(IMM8, SP)}}, { "mov", 0xfb9e0000, 0xffff000f, 0, FMT_D7, AM33, {RD2, MEM2(RI, RN0)}}, { "mov", 0xfc000000, 0xfff00000, 0, FMT_D4, 0, {MEM2(IMM32,AM0), DN1}}, { "mov", 0xfc100000, 0xfff00000, 0, FMT_D4, 0, {DM1, MEM2(IMM32,AN0)}}, { "mov", 0xfc200000, 0xfff00000, 0, FMT_D4, 0, {MEM2(IMM32,AM0), AN1}}, { "mov", 0xfc300000, 0xfff00000, 0, FMT_D4, 0, {AM1, MEM2(IMM32,AN0)}}, +{ "mov", 0xfc800000, 0xfff30000, 0, FMT_D4, 0, {AM1, MEM(IMM32_MEM)}}, +{ "mov", 0xfc810000, 0xfff30000, 0, FMT_D4, 0, {DM1, MEM(IMM32_MEM)}}, +{ "mov", 0xfc900000, 0xfff30000, 0, FMT_D4, 0, {AM1, MEM2(IMM32, SP)}}, +{ "mov", 0xfc910000, 0xfff30000, 0, FMT_D4, 0, {DM1, MEM2(IMM32, SP)}}, +{ "mov", 0xfca00000, 0xfffc0000, 0, FMT_D4, 0, {MEM(IMM32_MEM), AN0}}, +{ "mov", 0xfca40000, 0xfffc0000, 0, FMT_D4, 0, {MEM(IMM32_MEM), DN0}}, +{ "mov", 0xfcb00000, 0xfffc0000, 0, FMT_D4, 0, {MEM2(IMM32, SP), AN0}}, +{ "mov", 0xfcb40000, 0xfffc0000, 0, FMT_D4, 0, {MEM2(IMM32, SP), DN0}}, { "mov", 0xfd0a0000, 0xffff0000, 0, FMT_D8, AM33, {MEM2(SD24, RM0), RN2}}, { "mov", 0xfd1a0000, 0xffff0000, 0, FMT_D8, AM33, {RM2, MEM2(SD24, RN0)}}, { "mov", 0xfd6a0000, 0xffff0000, 0x22, FMT_D8, AM33, {MEMINC2 (RM0, IMM24), RN2}}, { "mov", 0xfd7a0000, 0xffff0000, 0, FMT_D8, AM33, {RM2, MEMINC2 (RN0, IMM24)}}, +{ "mov", 0xfd8a0000, 0xffff0f00, 0, FMT_D8, AM33, {MEM2(IMM24, SP), RN2}}, +{ "mov", 0xfd9a0000, 0xffff0f00, 0, FMT_D8, AM33, {RM2, MEM2(IMM24, SP)}}, +{ "mov", 0xfe0a0000, 0xffff0000, 0, FMT_D9, AM33, {MEM2(IMM32_HIGH8,RM0), RN2}}, { "mov", 0xfe0a0000, 0xffff0000, 0, FMT_D9, AM33, {MEM2(IMM32_HIGH8,RM0), RN2}}, +{ "mov", 0xfe0e0000, 0xffff0f00, 0, FMT_D9, AM33, {MEM(IMM32_HIGH8_MEM), RN2}}, { "mov", 0xfe1a0000, 0xffff0000, 0, FMT_D9, AM33, {RM2, MEM2(IMM32_HIGH8, RN0)}}, +{ "mov", 0xfe1a0000, 0xffff0000, 0, FMT_D9, AM33, {RM2, MEM2(IMM32_HIGH8, RN0)}}, +{ "mov", 0xfe1e0000, 0xffff0f00, 0, FMT_D9, AM33, {RM2, MEM(IMM32_HIGH8_MEM)}}, { "mov", 0xfe6a0000, 0xffff0000, 0x22, FMT_D9, AM33, {MEMINC2 (RM0, IMM32_HIGH8), RN2}}, { "mov", 0xfe7a0000, 0xffff0000, 0, FMT_D9, AM33, {RN2, MEMINC2 (RM0, IMM32_HIGH8)}}, +{ "mov", 0xfe8a0000, 0xffff0f00, 0, FMT_D9, AM33, {MEM2(IMM32_HIGH8, SP), RN2}}, +{ "mov", 0xfe9a0000, 0xffff0f00, 0, FMT_D9, AM33, {RM2, MEM2(IMM32_HIGH8, SP)}}, { "movhu", 0xf060, 0xfff0, 0, FMT_D0, 0, {MEM(AM0), DN1}}, { "movhu", 0xf070, 0xfff0, 0, FMT_D0, 0, {DM1, MEM(AN0)}}, @@ -224,26 +255,42 @@ static const struct mn10300_opcode mn10300_opcodes[] = { { "movhu", 0xf4c0, 0xffc0, 0, FMT_D0, 0, {DM2, MEM2(DI, AN0)}}, { "movhu", 0xf86000, 0xfff000, 0, FMT_D1, 0, {MEM2(SD8, AM0), DN1}}, { "movhu", 0xf87000, 0xfff000, 0, FMT_D1, 0, {DM1, MEM2(SD8, AN0)}}, +{ "movhu", 0xf89300, 0xfff300, 0, FMT_D1, 0, {DM1, MEM2(IMM8, SP)}}, +{ "movhu", 0xf8bc00, 0xfffc00, 0, FMT_D1, 0, {MEM2(IMM8, SP), DN0}}, { "movhu", 0xf94a00, 0xffff00, 0, FMT_D6, AM33, {MEM(RM0), RN2}}, { "movhu", 0xf95a00, 0xffff00, 0, FMT_D6, AM33, {RM2, MEM(RN0)}}, { "movhu", 0xf9ea00, 0xffff00, 0x12, FMT_D6, AM33, {MEMINC(RM0), RN2}}, { "movhu", 0xf9fa00, 0xffff00, 0, FMT_D6, AM33, {RM2, MEMINC(RN0)}}, { "movhu", 0xfa600000, 0xfff00000, 0, FMT_D2, 0, {MEM2(SD16, AM0), DN1}}, { "movhu", 0xfa700000, 0xfff00000, 0, FMT_D2, 0, {DM1, MEM2(SD16, AN0)}}, +{ "movhu", 0xfa930000, 0xfff30000, 0, FMT_D2, 0, {DM1, MEM2(IMM16, SP)}}, +{ "movhu", 0xfabc0000, 0xfffc0000, 0, FMT_D2, 0, {MEM2(IMM16, SP), DN0}}, { "movhu", 0xfb4a0000, 0xffff0000, 0, FMT_D7, AM33, {MEM2(SD8, RM0), RN2}}, { "movhu", 0xfb5a0000, 0xffff0000, 0, FMT_D7, AM33, {RM2, MEM2(SD8, RN0)}}, +{ "movhu", 0xfbca0000, 0xffff0f00, 0, FMT_D7, AM33, {MEM2(IMM8, SP), RN2}}, { "movhu", 0xfbce0000, 0xffff000f, 0, FMT_D7, AM33, {MEM2(RI, RM0), RD2}}, +{ "movhu", 0xfbda0000, 0xffff0f00, 0, FMT_D7, AM33, {RM2, MEM2(IMM8, SP)}}, { "movhu", 0xfbde0000, 0xffff000f, 0, FMT_D7, AM33, {RD2, MEM2(RI, RN0)}}, { "movhu", 0xfbea0000, 0xffff0000, 0x22, FMT_D7, AM33, {MEMINC2 (RM0, SIMM8), RN2}}, { "movhu", 0xfbfa0000, 0xffff0000, 0, FMT_D7, AM33, {RM2, MEMINC2 (RN0, SIMM8)}}, { "movhu", 0xfc600000, 0xfff00000, 0, FMT_D4, 0, {MEM2(IMM32,AM0), DN1}}, { "movhu", 0xfc700000, 0xfff00000, 0, FMT_D4, 0, {DM1, MEM2(IMM32,AN0)}}, +{ "movhu", 0xfc830000, 0xfff30000, 0, FMT_D4, 0, {DM1, MEM(IMM32_MEM)}}, +{ "movhu", 0xfc930000, 0xfff30000, 0, FMT_D4, 0, {DM1, MEM2(IMM32, SP)}}, +{ "movhu", 0xfcac0000, 0xfffc0000, 0, FMT_D4, 0, {MEM(IMM32_MEM), DN0}}, +{ "movhu", 0xfcbc0000, 0xfffc0000, 0, FMT_D4, 0, {MEM2(IMM32, SP), DN0}}, { "movhu", 0xfd4a0000, 0xffff0000, 0, FMT_D8, AM33, {MEM2(SD24, RM0), RN2}}, { "movhu", 0xfd5a0000, 0xffff0000, 0, FMT_D8, AM33, {RM2, MEM2(SD24, RN0)}}, +{ "movhu", 0xfdca0000, 0xffff0f00, 0, FMT_D8, AM33, {MEM2(IMM24, SP), RN2}}, +{ "movhu", 0xfdda0000, 0xffff0f00, 0, FMT_D8, AM33, {RM2, MEM2(IMM24, SP)}}, { "movhu", 0xfdea0000, 0xffff0000, 0x22, FMT_D8, AM33, {MEMINC2 (RM0, IMM24), RN2}}, { "movhu", 0xfdfa0000, 0xffff0000, 0, FMT_D8, AM33, {RM2, MEMINC2 (RN0, IMM24)}}, { "movhu", 0xfe4a0000, 0xffff0000, 0, FMT_D9, AM33, {MEM2(IMM32_HIGH8,RM0), RN2}}, +{ "movhu", 0xfe4e0000, 0xffff0f00, 0, FMT_D9, AM33, {MEM(IMM32_HIGH8_MEM), RN2}}, { "movhu", 0xfe5a0000, 0xffff0000, 0, FMT_D9, AM33, {RM2, MEM2(IMM32_HIGH8, RN0)}}, +{ "movhu", 0xfe5e0000, 0xffff0f00, 0, FMT_D9, AM33, {RM2, MEM(IMM32_HIGH8_MEM)}}, +{ "movhu", 0xfeca0000, 0xffff0f00, 0, FMT_D9, AM33, {MEM2(IMM32_HIGH8, SP), RN2}}, +{ "movhu", 0xfeda0000, 0xffff0f00, 0, FMT_D9, AM33, {RM2, MEM2(IMM32_HIGH8, SP)}}, { "movhu", 0xfeea0000, 0xffff0000, 0x22, FMT_D9, AM33, {MEMINC2 (RM0, IMM32_HIGH8), RN2}}, { "movhu", 0xfefa0000, 0xffff0000, 0, FMT_D9, AM33, {RN2, MEMINC2 (RM0, IMM32_HIGH8)}}, { 0, 0, 0, 0, 0, 0, {0}}, @@ -552,6 +599,9 @@ static int misalignment_addr(unsigned long *registers, unsigned params, postinc = ®isters[Rreg_index[disp >> 4 & 0x0f]]; address += *postinc; break; + case SP: + address += registers[REG_SP >> 2]; + break; case SD8: case SIMM8: @@ -575,7 +625,9 @@ static int misalignment_addr(unsigned long *registers, unsigned params, address += disp & 0x00ffffff; break; case IMM32: + case IMM32_MEM: case IMM32_HIGH8: + case IMM32_HIGH8_MEM: address += disp; break; default: -- cgit v1.2.2 From b308bf3be1f75207c307eea9ada90e0b76194911 Mon Sep 17 00:00:00 2001 From: David Howells Date: Wed, 12 Nov 2008 15:35:14 +0000 Subject: MN10300: Extract the displacement from an insn correctly in misalignment fixup Extract the displacement from an MN10300 instruction correctly in the misalignment fixup handler. The code should extract the displacement in LSB order, not MSB order. Signed-off-by: David Howells Signed-off-by: Linus Torvalds --- arch/mn10300/mm/misalignment.c | 26 +++++++++++++------------- 1 file changed, 13 insertions(+), 13 deletions(-) (limited to 'arch') diff --git a/arch/mn10300/mm/misalignment.c b/arch/mn10300/mm/misalignment.c index ab03bac497cb..614c32b6325b 100644 --- a/arch/mn10300/mm/misalignment.c +++ b/arch/mn10300/mm/misalignment.c @@ -43,11 +43,11 @@ #endif static int misalignment_addr(unsigned long *registers, unsigned params, - unsigned opcode, unsigned disp, + unsigned opcode, unsigned long disp, void **_address, unsigned long **_postinc); static int misalignment_reg(unsigned long *registers, unsigned params, - unsigned opcode, unsigned disp, + unsigned opcode, unsigned long disp, unsigned long **_register); static const unsigned Dreg_index[] = { @@ -304,13 +304,13 @@ asmlinkage void misalignment(struct pt_regs *regs, enum exception_code code) const struct exception_table_entry *fixup; const struct mn10300_opcode *pop; unsigned long *registers = (unsigned long *) regs; - unsigned long data, *store, *postinc; + unsigned long data, *store, *postinc, disp; mm_segment_t seg; siginfo_t info; - uint32_t opcode, disp, noc, xo, xm; + uint32_t opcode, noc, xo, xm; uint8_t *pc, byte; void *address; - unsigned tmp, npop; + unsigned tmp, npop, dispsz, loop; kdebug("==>misalignment({pc=%lx})", regs->pc); @@ -445,17 +445,17 @@ found_opcode: /* grab the extra displacement (note it's LSB first) */ disp = 0; - tmp = format_tbl[pop->format].dispsz >> 3; - while (tmp > 0) { - tmp--; - disp <<= 8; - + dispsz = format_tbl[pop->format].dispsz; + for (loop = 0; loop < dispsz; loop += 8) { pc++; if (__get_user(byte, pc) != 0) goto fetch_error; - disp |= byte; + disp |= byte << loop; + kdebug("{%p} disp[%02x]=%02x", pc, loop, byte); } + kdebug("disp=%lx", disp); + set_fs(KERNEL_XDS); if (fixup || regs->epsw & EPSW_nSL) set_fs(seg); @@ -538,7 +538,7 @@ found_opcode: * determine the address that was being accessed */ static int misalignment_addr(unsigned long *registers, unsigned params, - unsigned opcode, unsigned disp, + unsigned opcode, unsigned long disp, void **_address, unsigned long **_postinc) { unsigned long *postinc = NULL, address = 0, tmp; @@ -644,7 +644,7 @@ static int misalignment_addr(unsigned long *registers, unsigned params, * determine the register that is acting as source/dest */ static int misalignment_reg(unsigned long *registers, unsigned params, - unsigned opcode, unsigned disp, + unsigned opcode, unsigned long disp, unsigned long **_register) { params &= 0x7fffffff; -- cgit v1.2.2 From f911c685d65ea1855eb3f95b8eaf871e5d9342fa Mon Sep 17 00:00:00 2001 From: David Howells Date: Wed, 12 Nov 2008 15:35:20 +0000 Subject: MN10300: Fix register-postinc addressing misalignment handling Fix misalignment handling of operands with register postincrement addressing. The flag to indicate that postincrement is required should not be interpreted as an specification of a value to be added to the address. Also add BUGs to catch unimplemented parameter markings in the opcodes table. Signed-off-by: David Howells Signed-off-by: Linus Torvalds --- arch/mn10300/mm/misalignment.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/mn10300/mm/misalignment.c b/arch/mn10300/mm/misalignment.c index 614c32b6325b..066ddc625a14 100644 --- a/arch/mn10300/mm/misalignment.c +++ b/arch/mn10300/mm/misalignment.c @@ -543,7 +543,7 @@ static int misalignment_addr(unsigned long *registers, unsigned params, { unsigned long *postinc = NULL, address = 0, tmp; - params &= 0x7fffffff; + params &= 0x00ffffff; do { switch (params & 0xff) { @@ -631,6 +631,7 @@ static int misalignment_addr(unsigned long *registers, unsigned params, address += disp; break; default: + BUG(); return 0; } } while ((params >>= 8)); @@ -697,6 +698,7 @@ static int misalignment_reg(unsigned long *registers, unsigned params, break; default: + BUG(); return 0; } -- cgit v1.2.2 From aefefbbec1ad25bafa97a7a1db25313ce26563e2 Mon Sep 17 00:00:00 2001 From: David Howells Date: Wed, 12 Nov 2008 15:35:25 +0000 Subject: MN10300: Allow misalignment fixup in interrupt handling Allow misalignment fixup in interrupt handling in the MN10300 arch. Signed-off-by: David Howells Signed-off-by: Linus Torvalds --- arch/mn10300/mm/misalignment.c | 3 --- 1 file changed, 3 deletions(-) (limited to 'arch') diff --git a/arch/mn10300/mm/misalignment.c b/arch/mn10300/mm/misalignment.c index 066ddc625a14..05a3c2f8d2df 100644 --- a/arch/mn10300/mm/misalignment.c +++ b/arch/mn10300/mm/misalignment.c @@ -314,9 +314,6 @@ asmlinkage void misalignment(struct pt_regs *regs, enum exception_code code) kdebug("==>misalignment({pc=%lx})", regs->pc); - if (in_interrupt()) - die("Misalignment trap in interrupt context", regs, code); - if (regs->epsw & EPSW_IE) asm volatile("or %0,epsw" : : "i"(EPSW_IE)); -- cgit v1.2.2 From ddb6d05cbaea76eddbee52585152ab801a8aedc7 Mon Sep 17 00:00:00 2001 From: David Howells Date: Wed, 12 Nov 2008 15:35:30 +0000 Subject: MN10300: Perform misalignment fixups of MOV_Lcc Perform misalignment fixups of the MOV_Lcc instructions (move postinc memory to register and conditionally loop). Signed-off-by: David Howells Signed-off-by: Linus Torvalds --- arch/mn10300/mm/misalignment.c | 95 +++++++++++++++++++++++++++++++++++++++++- 1 file changed, 94 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/mn10300/mm/misalignment.c b/arch/mn10300/mm/misalignment.c index 05a3c2f8d2df..d5b45bb7d108 100644 --- a/arch/mn10300/mm/misalignment.c +++ b/arch/mn10300/mm/misalignment.c @@ -50,6 +50,8 @@ static int misalignment_reg(unsigned long *registers, unsigned params, unsigned opcode, unsigned long disp, unsigned long **_register); +static void misalignment_MOV_Lcc(struct pt_regs *regs, uint32_t opcode); + static const unsigned Dreg_index[] = { REG_D0 >> 2, REG_D1 >> 2, REG_D2 >> 2, REG_D3 >> 2 }; @@ -78,6 +80,7 @@ enum format_id { FMT_D7, FMT_D8, FMT_D9, + FMT_D10, }; static const struct { @@ -95,6 +98,7 @@ static const struct { [FMT_D7] = { 24, 8 }, [FMT_D8] = { 24, 24 }, [FMT_D9] = { 24, 32 }, + [FMT_D10] = { 32, 0 }, }; enum value_id { @@ -293,6 +297,19 @@ static const struct mn10300_opcode mn10300_opcodes[] = { { "movhu", 0xfeda0000, 0xffff0f00, 0, FMT_D9, AM33, {RM2, MEM2(IMM32_HIGH8, SP)}}, { "movhu", 0xfeea0000, 0xffff0000, 0x22, FMT_D9, AM33, {MEMINC2 (RM0, IMM32_HIGH8), RN2}}, { "movhu", 0xfefa0000, 0xffff0000, 0, FMT_D9, AM33, {RN2, MEMINC2 (RM0, IMM32_HIGH8)}}, + +{ "mov_llt", 0xf7e00000, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}}, +{ "mov_lgt", 0xf7e00001, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}}, +{ "mov_lge", 0xf7e00002, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}}, +{ "mov_lle", 0xf7e00003, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}}, +{ "mov_lcs", 0xf7e00004, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}}, +{ "mov_lhi", 0xf7e00005, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}}, +{ "mov_lcc", 0xf7e00006, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}}, +{ "mov_lls", 0xf7e00007, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}}, +{ "mov_leq", 0xf7e00008, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}}, +{ "mov_lne", 0xf7e00009, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}}, +{ "mov_lra", 0xf7e0000a, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}}, + { 0, 0, 0, 0, 0, 0, {0}}, }; @@ -477,7 +494,8 @@ found_opcode: &store)) goto bad_reg_mode; - if (strcmp(pop->name, "mov") == 0) { + if (strcmp(pop->name, "mov") == 0 || + memcmp(pop->name, "mov_l", 5) == 0) { kdebug("mov (%p),DARn", address); if (copy_from_user(&data, (void *) address, 4) != 0) goto transfer_failed; @@ -495,6 +513,7 @@ found_opcode: } *store = data; + kdebug("loaded %lx", data); } else { /* move register to memory */ if (!misalignment_reg(registers, pop->params[0], opcode, disp, @@ -527,6 +546,11 @@ found_opcode: tmp = format_tbl[pop->format].opsz + format_tbl[pop->format].dispsz; regs->pc += tmp >> 3; + /* handle MOV_Lcc, which are currently the only FMT_D10 insns that + * access memory */ + if (pop->format == FMT_D10) + misalignment_MOV_Lcc(regs, opcode); + set_fs(seg); return; } @@ -702,6 +726,75 @@ static int misalignment_reg(unsigned long *registers, unsigned params, return 1; } +/* + * handle the conditional loop part of the move-and-loop instructions + */ +static void misalignment_MOV_Lcc(struct pt_regs *regs, uint32_t opcode) +{ + unsigned long epsw = regs->epsw; + unsigned long NxorV; + + kdebug("MOV_Lcc %x [flags=%lx]", opcode, epsw & 0xf); + + /* calculate N^V and shift onto the same bit position as Z */ + NxorV = ((epsw >> 3) ^ epsw >> 1) & 1; + + switch (opcode & 0xf) { + case 0x0: /* MOV_LLT: N^V */ + if (NxorV) + goto take_the_loop; + return; + case 0x1: /* MOV_LGT: ~(Z or (N^V))*/ + if (!((epsw & EPSW_FLAG_Z) | NxorV)) + goto take_the_loop; + return; + case 0x2: /* MOV_LGE: ~(N^V) */ + if (!NxorV) + goto take_the_loop; + return; + case 0x3: /* MOV_LLE: Z or (N^V) */ + if ((epsw & EPSW_FLAG_Z) | NxorV) + goto take_the_loop; + return; + + case 0x4: /* MOV_LCS: C */ + if (epsw & EPSW_FLAG_C) + goto take_the_loop; + return; + case 0x5: /* MOV_LHI: ~(C or Z) */ + if (!(epsw & (EPSW_FLAG_C | EPSW_FLAG_Z))) + goto take_the_loop; + return; + case 0x6: /* MOV_LCC: ~C */ + if (!(epsw & EPSW_FLAG_C)) + goto take_the_loop; + return; + case 0x7: /* MOV_LLS: C or Z */ + if (epsw & (EPSW_FLAG_C | EPSW_FLAG_Z)) + goto take_the_loop; + return; + + case 0x8: /* MOV_LEQ: Z */ + if (epsw & EPSW_FLAG_Z) + goto take_the_loop; + return; + case 0x9: /* MOV_LNE: ~Z */ + if (!(epsw & EPSW_FLAG_Z)) + goto take_the_loop; + return; + case 0xa: /* MOV_LRA: always */ + goto take_the_loop; + + default: + BUG(); + } + +take_the_loop: + /* wind the PC back to just after the SETLB insn */ + kdebug("loop LAR=%lx", regs->lar); + regs->pc = regs->lar - 4; +} + /* * misalignment handler tests */ -- cgit v1.2.2 From 6d615c78fb92fbd80e52ba7acb2d4c4d503006c3 Mon Sep 17 00:00:00 2001 From: David Howells Date: Wed, 12 Nov 2008 15:35:35 +0000 Subject: MN10300: Handle misaligned postinc-with-imm addressing mode correctly Correctly handle misalignment in MOV instructions with postinc-with-immediate addressing mode operands. In these, the immediate value is the increment to be applied the address register, not the displacement to the address. Signed-off-by: David Howells Signed-off-by: Linus Torvalds --- arch/mn10300/mm/misalignment.c | 107 +++++++++++++++++++++-------------------- 1 file changed, 56 insertions(+), 51 deletions(-) (limited to 'arch') diff --git a/arch/mn10300/mm/misalignment.c b/arch/mn10300/mm/misalignment.c index d5b45bb7d108..61e65ec47db8 100644 --- a/arch/mn10300/mm/misalignment.c +++ b/arch/mn10300/mm/misalignment.c @@ -44,7 +44,8 @@ static int misalignment_addr(unsigned long *registers, unsigned params, unsigned opcode, unsigned long disp, - void **_address, unsigned long **_postinc); + void **_address, unsigned long **_postinc, + unsigned long *_inc); static int misalignment_reg(unsigned long *registers, unsigned params, unsigned opcode, unsigned long disp, @@ -150,7 +151,7 @@ enum value_id { }; struct mn10300_opcode { - const char *name; + const char name[8]; u_int32_t opcode; u_int32_t opmask; unsigned exclusion; @@ -310,7 +311,7 @@ static const struct mn10300_opcode mn10300_opcodes[] = { { "mov_lne", 0xf7e00009, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}}, { "mov_lra", 0xf7e0000a, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}}, -{ 0, 0, 0, 0, 0, 0, {0}}, +{ "", 0, 0, 0, 0, 0, {0}}, }; /* @@ -321,11 +322,11 @@ asmlinkage void misalignment(struct pt_regs *regs, enum exception_code code) const struct exception_table_entry *fixup; const struct mn10300_opcode *pop; unsigned long *registers = (unsigned long *) regs; - unsigned long data, *store, *postinc, disp; + unsigned long data, *store, *postinc, disp, inc; mm_segment_t seg; siginfo_t info; uint32_t opcode, noc, xo, xm; - uint8_t *pc, byte; + uint8_t *pc, byte, datasz; void *address; unsigned tmp, npop, dispsz, loop; @@ -347,7 +348,7 @@ asmlinkage void misalignment(struct pt_regs *regs, enum exception_code code) opcode = byte; noc = 8; - for (pop = mn10300_opcodes; pop->name; pop++) { + for (pop = mn10300_opcodes; pop->name[0]; pop++) { npop = ilog2(pop->opcode | pop->opmask); if (npop <= 0 || npop > 31) continue; @@ -484,32 +485,31 @@ found_opcode: goto failed; } + /* determine the data transfer size of the move */ + if (pop->name[3] == 0 || /* "mov" */ + pop->name[4] == 'l') /* mov_lcc */ + inc = datasz = 4; + else if (pop->name[3] == 'h') /* movhu */ + inc = datasz = 2; + else + goto unsupported_instruction; + if (pop->params[0] & 0x80000000) { /* move memory to register */ if (!misalignment_addr(registers, pop->params[0], opcode, disp, - &address, &postinc)) + &address, &postinc, &inc)) goto bad_addr_mode; if (!misalignment_reg(registers, pop->params[1], opcode, disp, &store)) goto bad_reg_mode; - if (strcmp(pop->name, "mov") == 0 || - memcmp(pop->name, "mov_l", 5) == 0) { - kdebug("mov (%p),DARn", address); - if (copy_from_user(&data, (void *) address, 4) != 0) - goto transfer_failed; - if (pop->params[0] & 0x1000000) - *postinc += 4; - } else if (strcmp(pop->name, "movhu") == 0) { - kdebug("movhu (%p),DARn", address); - data = 0; - if (copy_from_user(&data, (void *) address, 2) != 0) - goto transfer_failed; - if (pop->params[0] & 0x1000000) - *postinc += 2; - } else { - goto unsupported_instruction; + kdebug("mov%u (%p),DARn", datasz, address); + if (copy_from_user(&data, (void *) address, datasz) != 0) + goto transfer_failed; + if (pop->params[0] & 0x1000000) { + kdebug("inc=%lx", inc); + *postinc += inc; } *store = data; @@ -521,26 +521,16 @@ found_opcode: goto bad_reg_mode; if (!misalignment_addr(registers, pop->params[1], opcode, disp, - &address, &postinc)) + &address, &postinc, &inc)) goto bad_addr_mode; data = *store; - if (strcmp(pop->name, "mov") == 0) { - kdebug("mov %lx,(%p)", data, address); - if (copy_to_user((void *) address, &data, 4) != 0) - goto transfer_failed; - if (pop->params[1] & 0x1000000) - *postinc += 4; - } else if (strcmp(pop->name, "movhu") == 0) { - kdebug("movhu %hx,(%p)", (uint16_t) data, address); - if (copy_to_user((void *) address, &data, 2) != 0) - goto transfer_failed; - if (pop->params[1] & 0x1000000) - *postinc += 2; - } else { - goto unsupported_instruction; - } + kdebug("mov%u %lx,(%p)", datasz, data, address); + if (copy_to_user((void *) address, &data, datasz) != 0) + goto transfer_failed; + if (pop->params[1] & 0x1000000) + *postinc += inc; } tmp = format_tbl[pop->format].opsz + format_tbl[pop->format].dispsz; @@ -560,10 +550,17 @@ found_opcode: */ static int misalignment_addr(unsigned long *registers, unsigned params, unsigned opcode, unsigned long disp, - void **_address, unsigned long **_postinc) + void **_address, unsigned long **_postinc, + unsigned long *_inc) { unsigned long *postinc = NULL, address = 0, tmp; + if (!(params & 0x1000000)) { + kdebug("noinc"); + *_inc = 0; + _inc = NULL; + } + params &= 0x00ffffff; do { @@ -624,32 +621,40 @@ static int misalignment_addr(unsigned long *registers, unsigned params, address += registers[REG_SP >> 2]; break; + /* displacements are either to be added to the address + * before use, or, in the case of post-inc addressing, + * to be added into the base register after use */ case SD8: case SIMM8: - address += (int32_t) (int8_t) (disp & 0xff); - break; + disp = (long) (int8_t) (disp & 0xff); + goto displace_or_inc; case SD16: - address += (int32_t) (int16_t) (disp & 0xffff); - break; + disp = (long) (int16_t) (disp & 0xffff); + goto displace_or_inc; case SD24: tmp = disp << 8; asm("asr 8,%0" : "=r"(tmp) : "0"(tmp)); - address += tmp; - break; + disp = (long) tmp; + goto displace_or_inc; case SIMM4_2: tmp = opcode >> 4 & 0x0f; tmp <<= 28; asm("asr 28,%0" : "=r"(tmp) : "0"(tmp)); - address += tmp; - break; + disp = (long) tmp; + goto displace_or_inc; case IMM24: - address += disp & 0x00ffffff; - break; + disp &= 0x00ffffff; + goto displace_or_inc; case IMM32: case IMM32_MEM: case IMM32_HIGH8: case IMM32_HIGH8_MEM: - address += disp; + displace_or_inc: + kdebug("%s %lx", _inc ? "incr" : "disp", disp); + if (!_inc) + address += disp; + else + *_inc = disp; break; default: BUG(); -- cgit v1.2.2 From 852c15b7362cf34e0d7949abefbfeeb0845d93b4 Mon Sep 17 00:00:00 2001 From: David Howells Date: Wed, 12 Nov 2008 15:35:40 +0000 Subject: MN10300: Fix misaligned index-register addressing handling Fix misalignment handling for an address calculated from the sum of two registers. Signed-off-by: David Howells Signed-off-by: Linus Torvalds --- arch/mn10300/mm/misalignment.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'arch') diff --git a/arch/mn10300/mm/misalignment.c b/arch/mn10300/mm/misalignment.c index 61e65ec47db8..a59836804bc6 100644 --- a/arch/mn10300/mm/misalignment.c +++ b/arch/mn10300/mm/misalignment.c @@ -570,11 +570,11 @@ static int misalignment_addr(unsigned long *registers, unsigned params, address += *postinc; break; case DM1: - postinc = ®isters[Dreg_index[opcode >> 2 & 0x0c]]; + postinc = ®isters[Dreg_index[opcode >> 2 & 0x03]]; address += *postinc; break; case DM2: - postinc = ®isters[Dreg_index[opcode >> 4 & 0x30]]; + postinc = ®isters[Dreg_index[opcode >> 4 & 0x03]]; address += *postinc; break; case AM0: @@ -582,11 +582,11 @@ static int misalignment_addr(unsigned long *registers, unsigned params, address += *postinc; break; case AM1: - postinc = ®isters[Areg_index[opcode >> 2 & 0x0c]]; + postinc = ®isters[Areg_index[opcode >> 2 & 0x03]]; address += *postinc; break; case AM2: - postinc = ®isters[Areg_index[opcode >> 4 & 0x30]]; + postinc = ®isters[Areg_index[opcode >> 4 & 0x03]]; address += *postinc; break; case RM0: -- cgit v1.2.2 From d3bd462865421dd8be310fac2d2f6da6069f9679 Mon Sep 17 00:00:00 2001 From: David Howells Date: Wed, 12 Nov 2008 15:35:45 +0000 Subject: MN10300: Handle misaligned SP-based operands Support misalignment handling for instructions that have kernel SP-based address operands, including fixing those that include IMM8 or IMM16 displacements. Signed-off-by: David Howells Signed-off-by: Linus Torvalds --- arch/mn10300/mm/misalignment.c | 33 ++++++++++++++++++++++++--------- 1 file changed, 24 insertions(+), 9 deletions(-) (limited to 'arch') diff --git a/arch/mn10300/mm/misalignment.c b/arch/mn10300/mm/misalignment.c index a59836804bc6..e247a6e1b8de 100644 --- a/arch/mn10300/mm/misalignment.c +++ b/arch/mn10300/mm/misalignment.c @@ -42,8 +42,9 @@ #define kdebug(FMT, ...) do {} while (0) #endif -static int misalignment_addr(unsigned long *registers, unsigned params, - unsigned opcode, unsigned long disp, +static int misalignment_addr(unsigned long *registers, unsigned long sp, + unsigned params, unsigned opcode, + unsigned long disp, void **_address, unsigned long **_postinc, unsigned long *_inc); @@ -322,7 +323,7 @@ asmlinkage void misalignment(struct pt_regs *regs, enum exception_code code) const struct exception_table_entry *fixup; const struct mn10300_opcode *pop; unsigned long *registers = (unsigned long *) regs; - unsigned long data, *store, *postinc, disp, inc; + unsigned long data, *store, *postinc, disp, inc, sp; mm_segment_t seg; siginfo_t info; uint32_t opcode, noc, xo, xm; @@ -330,7 +331,12 @@ asmlinkage void misalignment(struct pt_regs *regs, enum exception_code code) void *address; unsigned tmp, npop, dispsz, loop; - kdebug("==>misalignment({pc=%lx})", regs->pc); + if (user_mode(regs)) + sp = regs->sp; + else + sp = (unsigned long) regs + sizeof(*regs); + + kdebug("==>misalignment({pc=%lx,sp=%lx})", regs->pc, sp); if (regs->epsw & EPSW_IE) asm volatile("or %0,epsw" : : "i"(EPSW_IE)); @@ -496,7 +502,8 @@ found_opcode: if (pop->params[0] & 0x80000000) { /* move memory to register */ - if (!misalignment_addr(registers, pop->params[0], opcode, disp, + if (!misalignment_addr(registers, sp, + pop->params[0], opcode, disp, &address, &postinc, &inc)) goto bad_addr_mode; @@ -520,7 +527,8 @@ found_opcode: &store)) goto bad_reg_mode; - if (!misalignment_addr(registers, pop->params[1], opcode, disp, + if (!misalignment_addr(registers, sp, + pop->params[1], opcode, disp, &address, &postinc, &inc)) goto bad_addr_mode; @@ -548,8 +556,9 @@ found_opcode: /* * determine the address that was being accessed */ -static int misalignment_addr(unsigned long *registers, unsigned params, - unsigned opcode, unsigned long disp, +static int misalignment_addr(unsigned long *registers, unsigned long sp, + unsigned params, unsigned opcode, + unsigned long disp, void **_address, unsigned long **_postinc, unsigned long *_inc) { @@ -618,7 +627,7 @@ static int misalignment_addr(unsigned long *registers, unsigned params, address += *postinc; break; case SP: - address += registers[REG_SP >> 2]; + address += sp; break; /* displacements are either to be added to the address @@ -642,6 +651,12 @@ static int misalignment_addr(unsigned long *registers, unsigned params, asm("asr 28,%0" : "=r"(tmp) : "0"(tmp)); disp = (long) tmp; goto displace_or_inc; + case IMM8: + disp &= 0x000000ff; + goto displace_or_inc; + case IMM16: + disp &= 0x0000ffff; + goto displace_or_inc; case IMM24: disp &= 0x00ffffff; goto displace_or_inc; -- cgit v1.2.2 From bd9384a9fdd6c15da6b01b2844c3471d07a45d64 Mon Sep 17 00:00:00 2001 From: David Howells Date: Wed, 12 Nov 2008 15:35:50 +0000 Subject: MN10300: Don't handle misaligned loading and storing of SP Don't handle the misaligned loading and storing of the SP register as in C code that's most certainly a compiler bug. Signed-off-by: David Howells Signed-off-by: Linus Torvalds --- arch/mn10300/mm/misalignment.c | 2 -- 1 file changed, 2 deletions(-) (limited to 'arch') diff --git a/arch/mn10300/mm/misalignment.c b/arch/mn10300/mm/misalignment.c index e247a6e1b8de..7b670a3d7659 100644 --- a/arch/mn10300/mm/misalignment.c +++ b/arch/mn10300/mm/misalignment.c @@ -204,8 +204,6 @@ static const struct mn10300_opcode mn10300_opcodes[] = { { "mov", 0xf81000, 0xfff000, 0, FMT_D1, 0, {DM1, MEM2(SD8, AN0)}}, { "mov", 0xf82000, 0xfff000, 0, FMT_D1, 0, {MEM2(SD8,AM0), AN1}}, { "mov", 0xf83000, 0xfff000, 0, FMT_D1, 0, {AM1, MEM2(SD8, AN0)}}, -{ "mov", 0xf8f000, 0xfffc00, 0, FMT_D1, AM33, {MEM2(SD8, AM0), SP}}, -{ "mov", 0xf8f400, 0xfffc00, 0, FMT_D1, AM33, {SP, MEM2(SD8, AN0)}}, { "mov", 0xf90a00, 0xffff00, 0, FMT_D6, AM33, {MEM(RM0), RN2}}, { "mov", 0xf91a00, 0xffff00, 0, FMT_D6, AM33, {RM2, MEM(RN0)}}, { "mov", 0xf96a00, 0xffff00, 0x12, FMT_D6, AM33, {MEMINC(RM0), RN2}}, -- cgit v1.2.2 From 58a47481b6ecb6dd05ab4a788e1f2ae3c7c46f57 Mon Sep 17 00:00:00 2001 From: David Howells Date: Wed, 12 Nov 2008 15:35:55 +0000 Subject: MN10300: Don't do misalignment handling for userspace Don't do misalignment handling for userspace misalignment faults: just generate an appropriate SIGBUS instead. Signed-off-by: David Howells Signed-off-by: Linus Torvalds --- arch/mn10300/mm/misalignment.c | 52 +++++++++++++++++++----------------------- 1 file changed, 23 insertions(+), 29 deletions(-) (limited to 'arch') diff --git a/arch/mn10300/mm/misalignment.c b/arch/mn10300/mm/misalignment.c index 7b670a3d7659..94c4a4358065 100644 --- a/arch/mn10300/mm/misalignment.c +++ b/arch/mn10300/mm/misalignment.c @@ -329,10 +329,11 @@ asmlinkage void misalignment(struct pt_regs *regs, enum exception_code code) void *address; unsigned tmp, npop, dispsz, loop; + /* we don't fix up userspace misalignment faults */ if (user_mode(regs)) - sp = regs->sp; - else - sp = (unsigned long) regs + sizeof(*regs); + goto bus_error; + + sp = (unsigned long) regs + sizeof(*regs); kdebug("==>misalignment({pc=%lx,sp=%lx})", regs->pc, sp); @@ -386,15 +387,15 @@ asmlinkage void misalignment(struct pt_regs *regs, enum exception_code code) } /* didn't manage to find a fixup */ - if (!user_mode(regs)) - printk(KERN_CRIT "MISALIGN: %lx: unsupported instruction %x\n", - regs->pc, opcode); + printk(KERN_CRIT "MISALIGN: %lx: unsupported instruction %x\n", + regs->pc, opcode); failed: set_fs(seg); if (die_if_no_fixup("misalignment error", regs, code)) return; +bus_error: info.si_signo = SIGBUS; info.si_errno = 0; info.si_code = BUS_ADRALN; @@ -404,31 +405,27 @@ failed: /* error reading opcodes */ fetch_error: - if (!user_mode(regs)) - printk(KERN_CRIT - "MISALIGN: %p: fault whilst reading instruction data\n", - pc); + printk(KERN_CRIT + "MISALIGN: %p: fault whilst reading instruction data\n", + pc); goto failed; bad_addr_mode: - if (!user_mode(regs)) - printk(KERN_CRIT - "MISALIGN: %lx: unsupported addressing mode %x\n", - regs->pc, opcode); + printk(KERN_CRIT + "MISALIGN: %lx: unsupported addressing mode %x\n", + regs->pc, opcode); goto failed; bad_reg_mode: - if (!user_mode(regs)) - printk(KERN_CRIT - "MISALIGN: %lx: unsupported register mode %x\n", - regs->pc, opcode); + printk(KERN_CRIT + "MISALIGN: %lx: unsupported register mode %x\n", + regs->pc, opcode); goto failed; unsupported_instruction: - if (!user_mode(regs)) - printk(KERN_CRIT - "MISALIGN: %lx: unsupported instruction %x (%s)\n", - regs->pc, opcode, pop->name); + printk(KERN_CRIT + "MISALIGN: %lx: unsupported instruction %x (%s)\n", + regs->pc, opcode, pop->name); goto failed; transfer_failed: @@ -476,16 +473,14 @@ found_opcode: kdebug("disp=%lx", disp); set_fs(KERNEL_XDS); - if (fixup || regs->epsw & EPSW_nSL) + if (fixup) set_fs(seg); tmp = (pop->params[0] ^ pop->params[1]) & 0x80000000; if (!tmp) { - if (!user_mode(regs)) - printk(KERN_CRIT - "MISALIGN: %lx:" - " insn not move to/from memory %x\n", - regs->pc, opcode); + printk(KERN_CRIT + "MISALIGN: %lx: insn not move to/from memory %x\n", + regs->pc, opcode); goto failed; } @@ -548,7 +543,6 @@ found_opcode: misalignment_MOV_Lcc(regs, opcode); set_fs(seg); - return; } /* -- cgit v1.2.2 From bfbedf787c6b77270679429caadb044b2d33c94c Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Thu, 13 Nov 2008 15:33:45 +0900 Subject: sh: early printk port type fix Add PORT_SCIF to unbreak the early printk code. Signed-off-by: Magnus Damm Signed-off-by: Paul Mundt --- arch/sh/kernel/early_printk.c | 1 + 1 file changed, 1 insertion(+) (limited to 'arch') diff --git a/arch/sh/kernel/early_printk.c b/arch/sh/kernel/early_printk.c index 6b7d166694e2..98a29a782301 100644 --- a/arch/sh/kernel/early_printk.c +++ b/arch/sh/kernel/early_printk.c @@ -75,6 +75,7 @@ static struct console bios_console = { #endif static struct uart_port scif_port = { + .type = PORT_SCIF, .mapbase = CONFIG_EARLY_SCIF_CONSOLE_PORT, .membase = (char __iomem *)CONFIG_EARLY_SCIF_CONSOLE_PORT, }; -- cgit v1.2.2 From 10840f034e2329150ce0e683e636ea13b268d333 Mon Sep 17 00:00:00 2001 From: Paul Mundt Date: Thu, 13 Nov 2008 15:38:02 +0900 Subject: sh: Don't factor in PAGE_OFFSET for valid_phys_addr_range() check. Signed-off-by: Paul Mundt --- arch/sh/mm/mmap.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/sh/mm/mmap.c b/arch/sh/mm/mmap.c index 1f3cc3d92d3d..8837d511710a 100644 --- a/arch/sh/mm/mmap.c +++ b/arch/sh/mm/mmap.c @@ -17,7 +17,7 @@ */ int valid_phys_addr_range(unsigned long addr, size_t count) { - if (addr < (PAGE_OFFSET + (PFN_START << PAGE_SHIFT))) + if (addr < __MEMORY_START) return 0; if (addr + count > __pa(high_memory)) return 0; -- cgit v1.2.2 From 5acdc1fa2d9614ecd301f3d27f19bfeabe811ade Mon Sep 17 00:00:00 2001 From: Kay Sievers Date: Wed, 12 Nov 2008 23:48:40 -0800 Subject: sparc: struct device - replace bus_id with dev_name(), dev_set_name() Acked-by: Greg Kroah-Hartman Signed-off-by: Kay Sievers Signed-off-by: David S. Miller --- arch/sparc/kernel/of_device.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/sparc/kernel/of_device.c b/arch/sparc/kernel/of_device.c index 0837bd52e28f..0a83bd737654 100644 --- a/arch/sparc/kernel/of_device.c +++ b/arch/sparc/kernel/of_device.c @@ -563,9 +563,9 @@ build_resources: op->dev.parent = parent; op->dev.bus = &of_platform_bus_type; if (!parent) - strcpy(op->dev.bus_id, "root"); + dev_set_name(&op->dev, "root"); else - sprintf(op->dev.bus_id, "%08x", dp->node); + dev_set_name(&op->dev, "%08x", dp->node); if (of_device_register(op)) { printk("%s: Could not register of device.\n", -- cgit v1.2.2 From e64ed0225bd82d4c108c9f78f46070cfade14fac Mon Sep 17 00:00:00 2001 From: Robert Reif Date: Wed, 12 Nov 2008 23:51:54 -0800 Subject: sparc: Fix tty compile warnings. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This patch fixes tty compile warnings as sugested by Alan Cox: CC drivers/char/n_tty.o drivers/char/n_tty.c: In function ‘normal_poll’: drivers/char/n_tty.c:1555: warning: array subscript is above array bounds drivers/char/n_tty.c:1564: warning: array subscript is above array bounds drivers/char/n_tty.c: In function ‘read_chan’: drivers/char/n_tty.c:1269: warning: array subscript is above array bounds CC drivers/char/tty_ioctl.o drivers/char/tty_ioctl.c: In function ‘set_termios’: drivers/char/tty_ioctl.c:533: warning: array subscript is above array bounds drivers/char/tty_ioctl.c:537: warning: array subscript is above array bounds drivers/char/tty_ioctl.c: In function ‘tty_mode_ioctl’: drivers/char/tty_ioctl.c:662: warning: array subscript is above array bounds drivers/char/tty_ioctl.c:892: warning: array subscript is above array bounds drivers/char/tty_ioctl.c:896: warning: array subscript is above array bounds drivers/char/tty_ioctl.c:577: warning: array subscript is above array bounds drivers/char/tty_ioctl.c:928: warning: array subscript is above array bounds drivers/char/tty_ioctl.c:934: warning: array subscript is above array bounds Signed-off-by: Robert Reif Signed-off-by: David S. Miller --- arch/sparc/include/asm/termbits.h | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) (limited to 'arch') diff --git a/arch/sparc/include/asm/termbits.h b/arch/sparc/include/asm/termbits.h index d6ca3e2754f5..d72dfed1f9d7 100644 --- a/arch/sparc/include/asm/termbits.h +++ b/arch/sparc/include/asm/termbits.h @@ -29,10 +29,11 @@ struct termios { tcflag_t c_cflag; /* control mode flags */ tcflag_t c_lflag; /* local mode flags */ cc_t c_line; /* line discipline */ +#ifndef __KERNEL__ cc_t c_cc[NCCS]; /* control characters */ -#ifdef __KERNEL__ +#else + cc_t c_cc[NCCS+2]; /* kernel needs 2 more to hold vmin/vtime */ #define SIZEOF_USER_TERMIOS sizeof (struct termios) - (2*sizeof (cc_t)) - cc_t _x_cc[2]; /* We need them to hold vmin/vtime */ #endif }; @@ -42,8 +43,7 @@ struct termios2 { tcflag_t c_cflag; /* control mode flags */ tcflag_t c_lflag; /* local mode flags */ cc_t c_line; /* line discipline */ - cc_t c_cc[NCCS]; /* control characters */ - cc_t _x_cc[2]; /* padding to match ktermios */ + cc_t c_cc[NCCS+2]; /* control characters */ speed_t c_ispeed; /* input speed */ speed_t c_ospeed; /* output speed */ }; @@ -54,8 +54,7 @@ struct ktermios { tcflag_t c_cflag; /* control mode flags */ tcflag_t c_lflag; /* local mode flags */ cc_t c_line; /* line discipline */ - cc_t c_cc[NCCS]; /* control characters */ - cc_t _x_cc[2]; /* We need them to hold vmin/vtime */ + cc_t c_cc[NCCS+2]; /* control characters */ speed_t c_ispeed; /* input speed */ speed_t c_ospeed; /* output speed */ }; -- cgit v1.2.2 From 2cd0ebc83d771220eeddec91fd6d4cfefc2cc46e Mon Sep 17 00:00:00 2001 From: Francesco VIRLINZI Date: Wed, 15 Oct 2008 11:58:24 +0200 Subject: sh: Fixed the TMU0 reload value on resume This patch fixes the TMU0 interrupt frequency on suspend/resume. During the resume the kernel reprograms the TMU0.ClockEvent mode but if the mode is periodic than the TMU0.TCOR is updated with a random wrong value without taking care latest valid saved value. There was no problem with No_HZ system where TMU0.TCOR isn't used. Signed-off-by: Francesco M. Virlinzi Signed-off-by: Stuart Menefy Signed-off-by: Paul Mundt --- arch/sh/kernel/timers/timer-tmu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/sh/kernel/timers/timer-tmu.c b/arch/sh/kernel/timers/timer-tmu.c index aaaf90d06b85..3c61ddd4d43e 100644 --- a/arch/sh/kernel/timers/timer-tmu.c +++ b/arch/sh/kernel/timers/timer-tmu.c @@ -120,7 +120,7 @@ static void tmu_set_mode(enum clock_event_mode mode, { switch (mode) { case CLOCK_EVT_MODE_PERIODIC: - ctrl_outl(ctrl_inl(TMU0_TCNT), TMU0_TCOR); + ctrl_outl(tmu_latest_interval[TMU0], TMU0_TCOR); break; case CLOCK_EVT_MODE_ONESHOT: ctrl_outl(0, TMU0_TCOR); -- cgit v1.2.2 From 5d52013cbb3d39bde9f5a6023193058eeb112e98 Mon Sep 17 00:00:00 2001 From: Stuart MENEFY Date: Fri, 10 Oct 2008 19:49:30 +0100 Subject: sh: __copy_user function can corrupt the stack in case of exception The __copy_user function can corrupt the stack in the case of a non-trivial length of data, and either of the first two move instructions cause an exception. This is because the fixup for these two instructions is mapped to the no_pop case, but these instructions execute after the stack is pushed. This change creates an explicit NO_POP exception mapping macro, and uses it for the two instructions executed in the trivial case where no stack pushes occur. More information at ST Linux bugzilla: https://bugzilla.stlinux.com/show_bug.cgi?id=4824 Signed-off-by: Dylan Reid Signed-off-by: Stuart Menefy Signed-off-by: Paul Mundt --- arch/sh/lib/copy_page.S | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) (limited to 'arch') diff --git a/arch/sh/lib/copy_page.S b/arch/sh/lib/copy_page.S index 5d12e657be34..43de7e8e4e17 100644 --- a/arch/sh/lib/copy_page.S +++ b/arch/sh/lib/copy_page.S @@ -80,6 +80,11 @@ ENTRY(copy_page) .section __ex_table, "a"; \ .long 9999b, 6000f ; \ .previous +#define EX_NO_POP(...) \ + 9999: __VA_ARGS__ ; \ + .section __ex_table, "a"; \ + .long 9999b, 6005f ; \ + .previous ENTRY(__copy_user) ! Check if small number of bytes mov #11,r0 @@ -139,9 +144,9 @@ EX( mov.b r1,@r4 ) bt 1f 2: -EX( mov.b @r5+,r0 ) +EX_NO_POP( mov.b @r5+,r0 ) dt r6 -EX( mov.b r0,@r4 ) +EX_NO_POP( mov.b r0,@r4 ) bf/s 2b add #1,r4 @@ -150,7 +155,7 @@ EX( mov.b r0,@r4 ) # Exception handler: .section .fixup, "ax" -6000: +6005: mov.l 8000f,r1 mov r3,r0 jmp @r1 -- cgit v1.2.2 From 272966c070237c8cb540fe67e06df51bc6ea9cc2 Mon Sep 17 00:00:00 2001 From: Paul Mundt Date: Thu, 13 Nov 2008 17:46:06 +0900 Subject: serial: sh-sci: Reorder the SCxTDR write after the TDxE clear. Under qemu there is a race between the TDxE read-and-clear and the SCxTDR write. While on hardware it can be gauranteed that the read-and-clear will happen prior to the character being written out, no such assumption can be made under emulation. As this path happens with IRQs off and the hardware itself doesn't care about the ordering, move the SCxTDR write until after the read-and-clear. Signed-off-by: Vladimir Prus Signed-off-by: Paul Mundt --- arch/sh/kernel/early_printk.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/sh/kernel/early_printk.c b/arch/sh/kernel/early_printk.c index 98a29a782301..a952dcf9999d 100644 --- a/arch/sh/kernel/early_printk.c +++ b/arch/sh/kernel/early_printk.c @@ -85,9 +85,9 @@ static void scif_sercon_putc(int c) while (((sci_in(&scif_port, SCFDR) & EPK_FIFO_BITS) >= EPK_FIFO_SIZE)) ; - sci_out(&scif_port, SCxTDR, c); sci_in(&scif_port, SCxSR); sci_out(&scif_port, SCxSR, 0xf3 & ~(0x20 | 0x40)); + sci_out(&scif_port, SCxTDR, c); while ((sci_in(&scif_port, SCxSR) & 0x40) == 0) ; -- cgit v1.2.2 From 9fa767928fe738aba8e99dae511e91f02fe20b28 Mon Sep 17 00:00:00 2001 From: Russell King Date: Thu, 13 Nov 2008 14:33:51 +0000 Subject: [ARM] dma-mapping: fix compiler warning arch/arm/mm/dma-mapping.c: In function `dma_sync_sg_for_cpu': arch/arm/mm/dma-mapping.c:588: warning: statement with no effect Signed-off-by: Russell King --- arch/arm/include/asm/dma-mapping.h | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/arm/include/asm/dma-mapping.h b/arch/arm/include/asm/dma-mapping.h index 1cb8602dd9d5..4ed149cbb32a 100644 --- a/arch/arm/include/asm/dma-mapping.h +++ b/arch/arm/include/asm/dma-mapping.h @@ -256,8 +256,17 @@ int dmabounce_sync_for_cpu(struct device *, dma_addr_t, unsigned long, int dmabounce_sync_for_device(struct device *, dma_addr_t, unsigned long, size_t, enum dma_data_direction); #else -#define dmabounce_sync_for_cpu(dev,dma,off,sz,dir) (1) -#define dmabounce_sync_for_device(dev,dma,off,sz,dir) (1) +static inline int dmabounce_sync_for_cpu(struct device *d, dma_addr_t addr, + unsigned long offset, size_t size, enum dma_data_direction dir) +{ + return 1; +} + +static inline int dmabounce_sync_for_device(struct device *d, dma_addr_t addr, + unsigned long offset, size_t size, enum dma_data_direction dir) +{ + return 1; +} /** -- cgit v1.2.2 From 1e8b0416ca387d754410a4e5d6b92ad6e2fb00eb Mon Sep 17 00:00:00 2001 From: Russell King Date: Thu, 13 Nov 2008 14:43:03 +0000 Subject: [ARM] integrator,realview,versatile: remove FLASH_* and EPROM_* constants FLASH_* and EPROM_* constants are unused, and clash with drivers: drivers/atm/ambassador.h:257:1: warning: "FLASH_BASE" redefined drivers/atm/ambassador.h:258:1: warning: "FLASH_SIZE" redefined drivers/atm/iphase.h:332:1: warning: "EPROM_SIZE" redefined so remove them. Signed-off-by: Russell King --- arch/arm/mach-integrator/include/mach/platform.h | 19 +------------------ arch/arm/mach-realview/include/mach/platform.h | 19 +------------------ arch/arm/mach-versatile/include/mach/platform.h | 18 +----------------- 3 files changed, 3 insertions(+), 53 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-integrator/include/mach/platform.h b/arch/arm/mach-integrator/include/mach/platform.h index 028b87839c0f..e00a2624f269 100644 --- a/arch/arm/mach-integrator/include/mach/platform.h +++ b/arch/arm/mach-integrator/include/mach/platform.h @@ -407,28 +407,11 @@ */ #define uHAL_MEMORY_SIZE INTEGRATOR_SSRAM_SIZE -/* - * Application Flash - * - */ -#define FLASH_BASE INTEGRATOR_FLASH_BASE -#define FLASH_SIZE INTEGRATOR_FLASH_SIZE -#define FLASH_END (FLASH_BASE + FLASH_SIZE - 1) -#define FLASH_BLOCK_SIZE SZ_128K - -/* - * Boot Flash - * - */ -#define EPROM_BASE INTEGRATOR_BOOT_ROM_HI -#define EPROM_SIZE INTEGRATOR_BOOT_ROM_SIZE -#define EPROM_END (EPROM_BASE + EPROM_SIZE - 1) - /* * Clean base - dummy * */ -#define CLEAN_BASE EPROM_BASE +#define CLEAN_BASE INTEGRATOR_BOOT_ROM_HI /* * Timer definitions diff --git a/arch/arm/mach-realview/include/mach/platform.h b/arch/arm/mach-realview/include/mach/platform.h index 4034b54950c2..793a3a332712 100644 --- a/arch/arm/mach-realview/include/mach/platform.h +++ b/arch/arm/mach-realview/include/mach/platform.h @@ -238,28 +238,11 @@ #define REALVIEW_INTREG_OFFSET 0x8 /* Interrupt control */ #define REALVIEW_DECODE_OFFSET 0xC /* Fitted logic modules */ -/* - * Application Flash - * - */ -#define FLASH_BASE REALVIEW_FLASH_BASE -#define FLASH_SIZE REALVIEW_FLASH_SIZE -#define FLASH_END (FLASH_BASE + FLASH_SIZE - 1) -#define FLASH_BLOCK_SIZE SZ_128K - -/* - * Boot Flash - * - */ -#define EPROM_BASE REALVIEW_BOOT_ROM_HI -#define EPROM_SIZE REALVIEW_BOOT_ROM_SIZE -#define EPROM_END (EPROM_BASE + EPROM_SIZE - 1) - /* * Clean base - dummy * */ -#define CLEAN_BASE EPROM_BASE +#define CLEAN_BASE REALVIEW_BOOT_ROM_HI /* * System controller bit assignment diff --git a/arch/arm/mach-versatile/include/mach/platform.h b/arch/arm/mach-versatile/include/mach/platform.h index 27cbe6a3f220..f91ba930ca8a 100644 --- a/arch/arm/mach-versatile/include/mach/platform.h +++ b/arch/arm/mach-versatile/include/mach/platform.h @@ -436,28 +436,12 @@ #define SIC_INTMASK_PCI1 (1 << SIC_INT_PCI1) #define SIC_INTMASK_PCI2 (1 << SIC_INT_PCI2) #define SIC_INTMASK_PCI3 (1 << SIC_INT_PCI3) -/* - * Application Flash - * - */ -#define FLASH_BASE VERSATILE_FLASH_BASE -#define FLASH_SIZE VERSATILE_FLASH_SIZE -#define FLASH_END (FLASH_BASE + FLASH_SIZE - 1) -#define FLASH_BLOCK_SIZE SZ_128K - -/* - * Boot Flash - * - */ -#define EPROM_BASE VERSATILE_BOOT_ROM_HI -#define EPROM_SIZE VERSATILE_BOOT_ROM_SIZE -#define EPROM_END (EPROM_BASE + EPROM_SIZE - 1) /* * Clean base - dummy * */ -#define CLEAN_BASE EPROM_BASE +#define CLEAN_BASE VERSATILE_BOOT_ROM_HI /* * System controller bit assignment -- cgit v1.2.2 From d9a682a592ff5905d328c648fd30ee7fa12ce8ab Mon Sep 17 00:00:00 2001 From: Russell King Date: Thu, 13 Nov 2008 14:53:08 +0000 Subject: [ARM] cdb89712,clps7500,h720x: avoid namespace clash for FLASH_* constants Signed-off-by: Russell King --- arch/arm/mach-clps711x/include/mach/hardware.h | 4 ---- arch/arm/mach-clps7500/core.c | 6 +++--- arch/arm/mach-clps7500/include/mach/hardware.h | 6 +++--- arch/arm/mach-h720x/include/mach/boards.h | 6 +++--- 4 files changed, 9 insertions(+), 13 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-clps711x/include/mach/hardware.h b/arch/arm/mach-clps711x/include/mach/hardware.h index 4c3e101b96c9..7cc675c93e20 100644 --- a/arch/arm/mach-clps711x/include/mach/hardware.h +++ b/arch/arm/mach-clps711x/include/mach/hardware.h @@ -95,10 +95,6 @@ #include /* dynamic ioremap() areas */ -#define FLASH_START 0x00000000 -#define FLASH_SIZE 0x800000 -#define FLASH_WIDTH 4 - #define SRAM_START 0x60000000 #define SRAM_SIZE 0xc000 #define SRAM_WIDTH 4 diff --git a/arch/arm/mach-clps7500/core.c b/arch/arm/mach-clps7500/core.c index c3a33b8a5aac..7e247c04d41c 100644 --- a/arch/arm/mach-clps7500/core.c +++ b/arch/arm/mach-clps7500/core.c @@ -275,9 +275,9 @@ static struct map_desc cl7500_io_desc[] __initdata = { .length = ISA_SIZE, .type = MT_DEVICE }, { /* Flash */ - .virtual = FLASH_BASE, - .pfn = __phys_to_pfn(FLASH_START), - .length = FLASH_SIZE, + .virtual = CLPS7500_FLASH_BASE, + .pfn = __phys_to_pfn(CLPS7500_FLASH_START), + .length = CLPS7500_FLASH_SIZE, .type = MT_DEVICE }, { /* LED */ .virtual = LED_BASE, diff --git a/arch/arm/mach-clps7500/include/mach/hardware.h b/arch/arm/mach-clps7500/include/mach/hardware.h index d66578a3371c..a6ad1d44badf 100644 --- a/arch/arm/mach-clps7500/include/mach/hardware.h +++ b/arch/arm/mach-clps7500/include/mach/hardware.h @@ -39,9 +39,9 @@ #define ISA_SIZE 0x00010000 #define ISA_BASE 0xe1000000 -#define FLASH_START 0x01000000 /* XXX */ -#define FLASH_SIZE 0x01000000 -#define FLASH_BASE 0xe2000000 +#define CLPS7500_FLASH_START 0x01000000 /* XXX */ +#define CLPS7500_FLASH_SIZE 0x01000000 +#define CLPS7500_FLASH_BASE 0xe2000000 #define LED_START 0x0302B000 #define LED_SIZE 0x00001000 diff --git a/arch/arm/mach-h720x/include/mach/boards.h b/arch/arm/mach-h720x/include/mach/boards.h index 079b279e1242..38b8e0d61fbf 100644 --- a/arch/arm/mach-h720x/include/mach/boards.h +++ b/arch/arm/mach-h720x/include/mach/boards.h @@ -19,9 +19,9 @@ #ifdef CONFIG_ARCH_H7202 /* FLASH */ -#define FLASH_VIRT 0xd0000000 -#define FLASH_PHYS 0x00000000 -#define FLASH_SIZE 0x02000000 +#define H720X_FLASH_VIRT 0xd0000000 +#define H720X_FLASH_PHYS 0x00000000 +#define H720X_FLASH_SIZE 0x02000000 /* onboard LAN controller */ # define ETH0_PHYS 0x08000000 -- cgit v1.2.2 From 8959dabdf2f8f9ce982a2c4cfe6d1652a2fb6320 Mon Sep 17 00:00:00 2001 From: Russell King Date: Thu, 13 Nov 2008 15:02:41 +0000 Subject: [ARM] cdb89712: avoid namespace clashes with SRAM_ and BOOTROM_ constants Signed-off-by: Russell King --- arch/arm/mach-clps711x/include/mach/hardware.h | 18 ------------------ 1 file changed, 18 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-clps711x/include/mach/hardware.h b/arch/arm/mach-clps711x/include/mach/hardware.h index 7cc675c93e20..b3ebe9e4871f 100644 --- a/arch/arm/mach-clps711x/include/mach/hardware.h +++ b/arch/arm/mach-clps711x/include/mach/hardware.h @@ -94,16 +94,6 @@ #include #include -/* dynamic ioremap() areas */ -#define SRAM_START 0x60000000 -#define SRAM_SIZE 0xc000 -#define SRAM_WIDTH 4 - -#define BOOTROM_START 0x70000000 -#define BOOTROM_SIZE 0x80 -#define BOOTROM_WIDTH 4 - - /* static cdb89712_map_io() areas */ #define REGISTER_START 0x80000000 #define REGISTER_SIZE 0x4000 @@ -194,14 +184,6 @@ #define CEIVA_FLASH_SIZE 0x100000 #define CEIVA_FLASH_WIDTH 2 -#define SRAM_START 0x60000000 -#define SRAM_SIZE 0xc000 -#define SRAM_WIDTH 4 - -#define BOOTROM_START 0x70000000 -#define BOOTROM_SIZE 0x80 -#define BOOTROM_WIDTH 4 - /* * SED1355 LCD controller */ -- cgit v1.2.2 From 906bf113beb07a76b665c3863aa864acdc8f9950 Mon Sep 17 00:00:00 2001 From: Helge Deller Date: Thu, 13 Nov 2008 18:55:54 +0100 Subject: fix cpumask build breakage on parisc Commit 2d3854a37e8b767a51aba38ed6d22817b0631e33 ("cpumask: introduce new API, without changing anything") introduced a build breakage on parisc. This trivial patch fixes it. Signed-off-by: Helge Deller Cc: Rusty Russell Cc: Andrew Morton Cc: Kyle Mc Martin Signed-off-by: Linus Torvalds --- arch/parisc/include/asm/smp.h | 2 -- 1 file changed, 2 deletions(-) (limited to 'arch') diff --git a/arch/parisc/include/asm/smp.h b/arch/parisc/include/asm/smp.h index 398cdbaf4e54..409e698f4361 100644 --- a/arch/parisc/include/asm/smp.h +++ b/arch/parisc/include/asm/smp.h @@ -44,8 +44,6 @@ extern void arch_send_call_function_ipi(cpumask_t mask); #define PROC_CHANGE_PENALTY 15 /* Schedule penalty */ -extern unsigned long cpu_present_mask; - #define raw_smp_processor_id() (current_thread_info()->cpu) #else /* CONFIG_SMP */ -- cgit v1.2.2 From fb2e7c5e33b341699f139b2ed972dca0a463a670 Mon Sep 17 00:00:00 2001 From: Gerald Schaefer Date: Fri, 14 Nov 2008 18:18:00 +0100 Subject: [S390] Fix range for add_active_range() in setup_memory() add_active_range() expects start_pfn + size as end_pfn value, i.e. not the pfn of the last page frame but the one behind that. We used the pfn of the last page frame so far, which can lead to a BUG_ON in move_freepages(), when the kernelcore parameter is specified (page_zone(start_page) != page_zone(end_page)). Signed-off-by: Gerald Schaefer Signed-off-by: Martin Schwidefsky --- arch/s390/kernel/setup.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/s390/kernel/setup.c b/arch/s390/kernel/setup.c index 62122bad1e33..400b040df7fa 100644 --- a/arch/s390/kernel/setup.c +++ b/arch/s390/kernel/setup.c @@ -604,13 +604,13 @@ setup_memory(void) if (memory_chunk[i].type != CHUNK_READ_WRITE) continue; start_chunk = PFN_DOWN(memory_chunk[i].addr); - end_chunk = start_chunk + PFN_DOWN(memory_chunk[i].size) - 1; + end_chunk = start_chunk + PFN_DOWN(memory_chunk[i].size); end_chunk = min(end_chunk, end_pfn); if (start_chunk >= end_chunk) continue; add_active_range(0, start_chunk, end_chunk); pfn = max(start_chunk, start_pfn); - for (; pfn <= end_chunk; pfn++) + for (; pfn < end_chunk; pfn++) page_set_storage_key(PFN_PHYS(pfn), PAGE_DEFAULT_KEY); } -- cgit v1.2.2 From af4c68740e848019d8d14c52704ed8eacceddac6 Mon Sep 17 00:00:00 2001 From: Heiko Carstens Date: Fri, 14 Nov 2008 18:18:03 +0100 Subject: [S390] lockdep: fix compile bug arch/s390/kernel/built-in.o: In function `cleanup_io_leave_insn': mem_detect.c:(.text+0x10592): undefined reference to `lockdep_sys_exit' Signed-off-by: Heiko Carstens Signed-off-by: Martin Schwidefsky --- arch/s390/kernel/entry.S | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch') diff --git a/arch/s390/kernel/entry.S b/arch/s390/kernel/entry.S index ed500ef799b7..5f0c4fba87c3 100644 --- a/arch/s390/kernel/entry.S +++ b/arch/s390/kernel/entry.S @@ -1116,6 +1116,8 @@ cleanup_io_leave_insn: .Ltrace_irq_on: .long trace_hardirqs_on .Ltrace_irq_off: .long trace_hardirqs_off +#endif +#ifdef CONFIG_LOCKDEP .Llockdep_sys_exit: .long lockdep_sys_exit #endif -- cgit v1.2.2 From 632448f65001c4935ed0d3bb362017d773da2eca Mon Sep 17 00:00:00 2001 From: Heiko Carstens Date: Fri, 14 Nov 2008 18:18:04 +0100 Subject: [S390] ftrace: disable tracing on idle psw Disable tracing on idle psw. Otherwise it would give us huge preempt off times for idle. Which is rather pointless. Signed-off-by: Heiko Carstens Signed-off-by: Martin Schwidefsky --- arch/s390/kernel/process.c | 3 +++ 1 file changed, 3 insertions(+) (limited to 'arch') diff --git a/arch/s390/kernel/process.c b/arch/s390/kernel/process.c index 3e2c05cb6a87..04f8c67a6101 100644 --- a/arch/s390/kernel/process.c +++ b/arch/s390/kernel/process.c @@ -136,9 +136,12 @@ static void default_idle(void) return; } trace_hardirqs_on(); + /* Don't trace preempt off for idle. */ + stop_critical_timings(); /* Wait for external, I/O or machine check interrupt. */ __load_psw_mask(psw_kernel_bits | PSW_MASK_WAIT | PSW_MASK_IO | PSW_MASK_EXT); + start_critical_timings(); } void cpu_idle(void) -- cgit v1.2.2 From 50bec4ce5d36ebf96189dcc54e20c7fce4bf61bf Mon Sep 17 00:00:00 2001 From: Heiko Carstens Date: Fri, 14 Nov 2008 18:18:05 +0100 Subject: [S390] ftrace: fix kernel stack backchain walking With CONFIG_IRQSOFF_TRACER the trace_hardirqs_off() function includes a call to __builtin_return_address(1). But we calltrace_hardirqs_off() from early entry code. There we have just a single stack frame. So this results in a kernel stack backchain walk that would walk beyond the kernel stack. Following the NULL terminated backchain this results in a lowcore read access. To fix this we simply call trace_hardirqs_off_caller() and pass the current instruction pointer. Signed-off-by: Heiko Carstens Signed-off-by: Martin Schwidefsky --- arch/s390/kernel/entry.S | 18 +++++++++++------- arch/s390/kernel/entry64.S | 11 +++++++---- 2 files changed, 18 insertions(+), 11 deletions(-) (limited to 'arch') diff --git a/arch/s390/kernel/entry.S b/arch/s390/kernel/entry.S index 5f0c4fba87c3..08844fc24a2e 100644 --- a/arch/s390/kernel/entry.S +++ b/arch/s390/kernel/entry.S @@ -61,22 +61,25 @@ STACK_SIZE = 1 << STACK_SHIFT #ifdef CONFIG_TRACE_IRQFLAGS .macro TRACE_IRQS_ON - l %r1,BASED(.Ltrace_irq_on) + basr %r2,%r0 + l %r1,BASED(.Ltrace_irq_on_caller) basr %r14,%r1 .endm .macro TRACE_IRQS_OFF - l %r1,BASED(.Ltrace_irq_off) + basr %r2,%r0 + l %r1,BASED(.Ltrace_irq_off_caller) basr %r14,%r1 .endm .macro TRACE_IRQS_CHECK + basr %r2,%r0 tm SP_PSW(%r15),0x03 # irqs enabled? jz 0f - l %r1,BASED(.Ltrace_irq_on) + l %r1,BASED(.Ltrace_irq_on_caller) basr %r14,%r1 j 1f -0: l %r1,BASED(.Ltrace_irq_off) +0: l %r1,BASED(.Ltrace_irq_off_caller) basr %r14,%r1 1: .endm @@ -1113,9 +1116,10 @@ cleanup_io_leave_insn: .Lschedtail: .long schedule_tail .Lsysc_table: .long sys_call_table #ifdef CONFIG_TRACE_IRQFLAGS -.Ltrace_irq_on: .long trace_hardirqs_on -.Ltrace_irq_off: - .long trace_hardirqs_off +.Ltrace_irq_on_caller: + .long trace_hardirqs_on_caller +.Ltrace_irq_off_caller: + .long trace_hardirqs_off_caller #endif #ifdef CONFIG_LOCKDEP .Llockdep_sys_exit: diff --git a/arch/s390/kernel/entry64.S b/arch/s390/kernel/entry64.S index d7ce150453f2..41aca06682aa 100644 --- a/arch/s390/kernel/entry64.S +++ b/arch/s390/kernel/entry64.S @@ -61,19 +61,22 @@ _TIF_WORK_INT = (_TIF_SIGPENDING | _TIF_NOTIFY_RESUME | _TIF_NEED_RESCHED | \ #ifdef CONFIG_TRACE_IRQFLAGS .macro TRACE_IRQS_ON - brasl %r14,trace_hardirqs_on + basr %r2,%r0 + brasl %r14,trace_hardirqs_on_caller .endm .macro TRACE_IRQS_OFF - brasl %r14,trace_hardirqs_off + basr %r2,%r0 + brasl %r14,trace_hardirqs_off_caller .endm .macro TRACE_IRQS_CHECK + basr %r2,%r0 tm SP_PSW(%r15),0x03 # irqs enabled? jz 0f - brasl %r14,trace_hardirqs_on + brasl %r14,trace_hardirqs_on_caller j 1f -0: brasl %r14,trace_hardirqs_off +0: brasl %r14,trace_hardirqs_off_caller 1: .endm #else -- cgit v1.2.2 From 74af283102b358b0da545460d0d176f473e110f6 Mon Sep 17 00:00:00 2001 From: Heiko Carstens Date: Fri, 14 Nov 2008 18:18:07 +0100 Subject: [S390] cpu topology: fix locking cpu_coregroup_map used to grab a mutex on s390 since it was only called from process context. Since c7c22e4d5c1fdebfac4dba76de7d0338c2b0d832 "block: add support for IO CPU affinity" this is not true anymore. It now also gets called from softirq context. To prevent possible deadlocks change this in architecture code and use a spinlock instead of a mutex. Cc: stable@kernel.org Cc: Jens Axboe Signed-off-by: Heiko Carstens Signed-off-by: Martin Schwidefsky --- arch/s390/kernel/topology.c | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) (limited to 'arch') diff --git a/arch/s390/kernel/topology.c b/arch/s390/kernel/topology.c index 632b13e10053..a947899dcba1 100644 --- a/arch/s390/kernel/topology.c +++ b/arch/s390/kernel/topology.c @@ -65,18 +65,21 @@ static int machine_has_topology_irq; static struct timer_list topology_timer; static void set_topology_timer(void); static DECLARE_WORK(topology_work, topology_work_fn); +/* topology_lock protects the core linked list */ +static DEFINE_SPINLOCK(topology_lock); cpumask_t cpu_core_map[NR_CPUS]; cpumask_t cpu_coregroup_map(unsigned int cpu) { struct core_info *core = &core_info; + unsigned long flags; cpumask_t mask; cpus_clear(mask); if (!machine_has_topology) return cpu_present_map; - mutex_lock(&smp_cpu_state_mutex); + spin_lock_irqsave(&topology_lock, flags); while (core) { if (cpu_isset(cpu, core->mask)) { mask = core->mask; @@ -84,7 +87,7 @@ cpumask_t cpu_coregroup_map(unsigned int cpu) } core = core->next; } - mutex_unlock(&smp_cpu_state_mutex); + spin_unlock_irqrestore(&topology_lock, flags); if (cpus_empty(mask)) mask = cpumask_of_cpu(cpu); return mask; @@ -133,7 +136,7 @@ static void tl_to_cores(struct tl_info *info) union tl_entry *tle, *end; struct core_info *core = &core_info; - mutex_lock(&smp_cpu_state_mutex); + spin_lock_irq(&topology_lock); clear_cores(); tle = info->tle; end = (union tl_entry *)((unsigned long)info + info->length); @@ -157,7 +160,7 @@ static void tl_to_cores(struct tl_info *info) } tle = next_tle(tle); } - mutex_unlock(&smp_cpu_state_mutex); + spin_unlock_irq(&topology_lock); } static void topology_update_polarization_simple(void) -- cgit v1.2.2 From d2f019fe40e8fecd822f87bc759f74925a5c31d6 Mon Sep 17 00:00:00 2001 From: Martin Schwidefsky Date: Fri, 14 Nov 2008 18:18:09 +0100 Subject: [S390] fix s390x_newuname The uname system call for 64 bit compares current->personality without masking the upper 16 bits. If e.g. READ_IMPLIES_EXEC is set the result of a uname system call will always be s390x even if the process uses the s390 personality. Signed-off-by: Martin Schwidefsky --- arch/s390/kernel/sys_s390.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/s390/kernel/sys_s390.c b/arch/s390/kernel/sys_s390.c index 5fdb799062b7..4fe952e557ac 100644 --- a/arch/s390/kernel/sys_s390.c +++ b/arch/s390/kernel/sys_s390.c @@ -198,7 +198,7 @@ asmlinkage long s390x_newuname(struct new_utsname __user *name) { int ret = sys_newuname(name); - if (current->personality == PER_LINUX32 && !ret) { + if (personality(current->personality) == PER_LINUX32 && !ret) { ret = copy_to_user(name->machine, "s390\0\0\0\0", 8); if (ret) ret = -EFAULT; } -- cgit v1.2.2 From 27123cbc264de89ce6951b1b4c84c223eb0f1702 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Fri, 14 Nov 2008 08:10:19 +0100 Subject: m68k: Fix off-by-one in m68k_setup_user_interrupt() commit 69961c375288bdab7604e0bb1c8d22999bb8a347 ("[PATCH] m68k/Atari: Interrupt updates") added a BUG_ON() with an incorrect upper bound comparison, which causes an early crash on VME boards, where IRQ_USER is 8, cnt is 192 and NR_IRQS is 200. Reported-by: Stephen N Chivers Tested-by: Kars de Jong Signed-off-by: Geert Uytterhoeven Cc: stable@kernel.org Signed-off-by: Linus Torvalds --- arch/m68k/kernel/ints.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/m68k/kernel/ints.c b/arch/m68k/kernel/ints.c index 7e8a0d394e61..761ee0440c99 100644 --- a/arch/m68k/kernel/ints.c +++ b/arch/m68k/kernel/ints.c @@ -133,7 +133,7 @@ void __init m68k_setup_user_interrupt(unsigned int vec, unsigned int cnt, { int i; - BUG_ON(IRQ_USER + cnt >= NR_IRQS); + BUG_ON(IRQ_USER + cnt > NR_IRQS); m68k_first_user_vec = vec; for (i = 0; i < cnt; i++) irq_controller[IRQ_USER + i] = &user_irq_controller; -- cgit v1.2.2 From 52168e60f7d86d83124903098ac8c2dba93cd1c4 Mon Sep 17 00:00:00 2001 From: David Woodhouse Date: Fri, 14 Nov 2008 13:47:31 +0000 Subject: Revert "x86: blacklist DMAR on Intel G31/G33 chipsets" This reverts commit e51af6630848406fc97adbd71443818cdcda297b, which was wrongly hoovered up and submitted about a month after a better fix had already been merged. The better fix is commit cbda1ba898647aeb4ee770b803c922f595e97731 ("PCI/iommu: blacklist DMAR on Intel G31/G33 chipsets"), where we do this blacklisting based on the DMI identification for the offending motherboard, since sometimes this chipset (or at least a chipset with the same PCI ID) apparently _does_ actually have an IOMMU. Signed-off-by: David Woodhouse Signed-off-by: Linus Torvalds --- arch/x86/include/asm/iommu.h | 1 - arch/x86/kernel/early-quirks.c | 18 ------------------ 2 files changed, 19 deletions(-) (limited to 'arch') diff --git a/arch/x86/include/asm/iommu.h b/arch/x86/include/asm/iommu.h index e4a552d44465..0b500c5b6446 100644 --- a/arch/x86/include/asm/iommu.h +++ b/arch/x86/include/asm/iommu.h @@ -6,7 +6,6 @@ extern void no_iommu_init(void); extern struct dma_mapping_ops nommu_dma_ops; extern int force_iommu, no_iommu; extern int iommu_detected; -extern int dmar_disabled; extern unsigned long iommu_nr_pages(unsigned long addr, unsigned long len); diff --git a/arch/x86/kernel/early-quirks.c b/arch/x86/kernel/early-quirks.c index 3ce029ffaa55..1b894b72c0f5 100644 --- a/arch/x86/kernel/early-quirks.c +++ b/arch/x86/kernel/early-quirks.c @@ -188,20 +188,6 @@ static void __init ati_bugs_contd(int num, int slot, int func) } #endif -#ifdef CONFIG_DMAR -static void __init intel_g33_dmar(int num, int slot, int func) -{ - struct acpi_table_header *dmar_tbl; - acpi_status status; - - status = acpi_get_table(ACPI_SIG_DMAR, 0, &dmar_tbl); - if (ACPI_SUCCESS(status)) { - printk(KERN_INFO "BIOS BUG: DMAR advertised on Intel G31/G33 chipset -- ignoring\n"); - dmar_disabled = 1; - } -} -#endif - #define QFLAG_APPLY_ONCE 0x1 #define QFLAG_APPLIED 0x2 #define QFLAG_DONE (QFLAG_APPLY_ONCE|QFLAG_APPLIED) @@ -225,10 +211,6 @@ static struct chipset early_qrk[] __initdata = { PCI_CLASS_SERIAL_SMBUS, PCI_ANY_ID, 0, ati_bugs }, { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS, PCI_CLASS_SERIAL_SMBUS, PCI_ANY_ID, 0, ati_bugs_contd }, -#ifdef CONFIG_DMAR - { PCI_VENDOR_ID_INTEL, 0x29c0, - PCI_CLASS_BRIDGE_HOST, PCI_ANY_ID, 0, intel_g33_dmar }, -#endif {} }; -- cgit v1.2.2 From 6a0bfff44e4aa4ee1721b3daa004d2039576c70d Mon Sep 17 00:00:00 2001 From: Tim Pepper Date: Mon, 27 Oct 2008 12:18:36 +0800 Subject: Blackfin arch: handle case of d_path() returning error in decode_address() d_path() can return an error. Most of its callers do something or other to make up something sane in that case. Do similar for blackfin's decode_address() call to d_path(). Signed-off-by: Tim Pepper Signed-off-by: Bryan Wu --- arch/blackfin/kernel/traps.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/blackfin/kernel/traps.c b/arch/blackfin/kernel/traps.c index 1aa2c788e228..0003616d02a2 100644 --- a/arch/blackfin/kernel/traps.c +++ b/arch/blackfin/kernel/traps.c @@ -147,9 +147,12 @@ static void decode_address(char *buf, unsigned long address) char *name = p->comm; struct file *file = vma->vm_file; - if (file) - name = d_path(&file->f_path, _tmpbuf, + if (file) { + char *d_name = d_path(&file->f_path, _tmpbuf, sizeof(_tmpbuf)); + if (!IS_ERR(d_name)) + name = d_name; + } /* FLAT does not have its text aligned to the start of * the map while FDPIC ELF does ... -- cgit v1.2.2 From 6776cf4476833df0f1e96bd9dba18c1ea4f582d5 Mon Sep 17 00:00:00 2001 From: Graf Yang Date: Mon, 27 Oct 2008 18:12:53 +0800 Subject: Blackfin arch: fix bug - Fail to boot jffs2 kernel for BF561 with SMP patch only if the cplb block overlapped with kernel area, this cplb need be locked Signed-off-by: Graf Yang Signed-off-by: Bryan Wu --- arch/blackfin/kernel/cplb-nompu/cplbinit.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) (limited to 'arch') diff --git a/arch/blackfin/kernel/cplb-nompu/cplbinit.c b/arch/blackfin/kernel/cplb-nompu/cplbinit.c index 512f8c92ead5..2debc900e246 100644 --- a/arch/blackfin/kernel/cplb-nompu/cplbinit.c +++ b/arch/blackfin/kernel/cplb-nompu/cplbinit.c @@ -188,10 +188,11 @@ static struct cplb_desc cplb_data[] = { static u16 __init lock_kernel_check(u32 start, u32 end) { - if ((end <= (u32) _end && end >= (u32)_stext) || - (start <= (u32) _end && start >= (u32)_stext)) - return IN_KERNEL; - return 0; + if (start >= (u32)_end || end <= (u32)_stext) + return 0; + + /* This cplb block overlapped with kernel area. */ + return IN_KERNEL; } static unsigned short __init -- cgit v1.2.2 From 3b1f26a50a2bfbd2825345b49b1d7f78432a7a4c Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Mon, 27 Oct 2008 18:21:43 +0800 Subject: Blackfin arch: don't copy bss when copying L1 when copying L1 regions, go to the start of bss rather than end since we have code to zero it out already Signed-off-by: Mike Frysinger Signed-off-by: Bryan Wu --- arch/blackfin/include/asm/bfin-global.h | 2 +- arch/blackfin/kernel/setup.c | 10 +++++----- 2 files changed, 6 insertions(+), 6 deletions(-) (limited to 'arch') diff --git a/arch/blackfin/include/asm/bfin-global.h b/arch/blackfin/include/asm/bfin-global.h index 56dcb0a2d244..77295666c34b 100644 --- a/arch/blackfin/include/asm/bfin-global.h +++ b/arch/blackfin/include/asm/bfin-global.h @@ -101,7 +101,7 @@ extern u16 _bfin_swrst; /* shadow for Software Reset Register (SWRST) */ extern unsigned long _ramstart, _ramend, _rambase; extern unsigned long memory_start, memory_end, physical_mem_end; extern char _stext_l1[], _etext_l1[], _sdata_l1[], _edata_l1[], _sbss_l1[], - _ebss_l1[], _l1_lma_start[], _sdata_b_l1[], _ebss_b_l1[], + _ebss_l1[], _l1_lma_start[], _sdata_b_l1[], _sbss_b_l1[], _ebss_b_l1[], _stext_l2[], _etext_l2[], _sdata_l2[], _edata_l2[], _sbss_l2[], _ebss_l2[], _l2_lma_start[]; diff --git a/arch/blackfin/kernel/setup.c b/arch/blackfin/kernel/setup.c index 7f35d1046cd8..8337dc3a62d7 100644 --- a/arch/blackfin/kernel/setup.c +++ b/arch/blackfin/kernel/setup.c @@ -119,23 +119,23 @@ void __init bfin_relocate_l1_mem(void) /* Copy _stext_l1 to _etext_l1 to L1 instruction SRAM */ dma_memcpy(_stext_l1, _l1_lma_start, l1_code_length); - l1_data_a_length = _ebss_l1 - _sdata_l1; + l1_data_a_length = _sbss_l1 - _sdata_l1; if (l1_data_a_length > L1_DATA_A_LENGTH) panic("L1 Data SRAM Bank A Overflow\n"); - /* Copy _sdata_l1 to _ebss_l1 to L1 data bank A SRAM */ + /* Copy _sdata_l1 to _sbss_l1 to L1 data bank A SRAM */ dma_memcpy(_sdata_l1, _l1_lma_start + l1_code_length, l1_data_a_length); - l1_data_b_length = _ebss_b_l1 - _sdata_b_l1; + l1_data_b_length = _sbss_b_l1 - _sdata_b_l1; if (l1_data_b_length > L1_DATA_B_LENGTH) panic("L1 Data SRAM Bank B Overflow\n"); - /* Copy _sdata_b_l1 to _ebss_b_l1 to L1 data bank B SRAM */ + /* Copy _sdata_b_l1 to _sbss_b_l1 to L1 data bank B SRAM */ dma_memcpy(_sdata_b_l1, _l1_lma_start + l1_code_length + l1_data_a_length, l1_data_b_length); if (L2_LENGTH != 0) { - l2_length = _ebss_l2 - _stext_l2; + l2_length = _sbss_l2 - _stext_l2; if (l2_length > L2_LENGTH) panic("L2 SRAM Overflow\n"); -- cgit v1.2.2 From 4ee1c45337e7b529eed644c6f62399d797dcbc10 Mon Sep 17 00:00:00 2001 From: Robin Getz Date: Tue, 28 Oct 2008 11:36:11 +0800 Subject: Blackfin arch: Fix typo when adding CONFIG_DEBUG_VERBOSE Signed-off-by: Robin Getz Signed-off-by: Bryan Wu --- arch/blackfin/kernel/traps.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/blackfin/kernel/traps.c b/arch/blackfin/kernel/traps.c index 0003616d02a2..bef025b07443 100644 --- a/arch/blackfin/kernel/traps.c +++ b/arch/blackfin/kernel/traps.c @@ -59,7 +59,7 @@ #endif -#ifdef CONFIG_VERBOSE_DEBUG +#ifdef CONFIG_DEBUG_VERBOSE #define verbose_printk(fmt, arg...) \ printk(fmt, ##arg) #else @@ -574,7 +574,7 @@ asmlinkage void trap_c(struct pt_regs *fp) #endif panic("Kernel exception"); } else { -#ifdef CONFIG_VERBOSE_DEBUG +#ifdef CONFIG_DEBUG_VERBOSE unsigned long *stack; /* Dump the user space stack */ stack = (unsigned long *)rdusp(); -- cgit v1.2.2 From 39e96c8835c36b6867b4e18698b06746972cdfcc Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Tue, 18 Nov 2008 17:48:22 +0800 Subject: Blackfin arch: fix bug - dmacopy test case fail on all platform The cache code I added flushes 1 line too little if the start address is not aligned to the cache size. Cache align the start address so that when we straddle cache aligns, we get the right count. Signed-off-by: Mike Frysinger Signed-off-by: Bryan Wu --- arch/blackfin/mach-common/cache.S | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/blackfin/mach-common/cache.S b/arch/blackfin/mach-common/cache.S index db532181fbde..d6780b495241 100644 --- a/arch/blackfin/mach-common/cache.S +++ b/arch/blackfin/mach-common/cache.S @@ -25,9 +25,13 @@ */ .macro do_flush flushins:req optflushins optnopins label + R2 = -L1_CACHE_BYTES; + + /* start = (start & -L1_CACHE_BYTES) */ + R0 = R0 & R2; + /* end = ((end - 1) & -L1_CACHE_BYTES) + L1_CACHE_BYTES; */ R1 += -1; - R2 = -L1_CACHE_BYTES; R1 = R1 & R2; R1 += L1_CACHE_BYTES; -- cgit v1.2.2 From 7f6b2e7b1ff70bc60cedc9a00b01c1fad5c21371 Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Tue, 28 Oct 2008 12:29:26 +0800 Subject: Blackfin arch: fix bug - kernel build with write back policy fails to be booted up Make sure IFLUSH is not the last instruction in the hardware loop to avoid infinite core stall. The dcache/icache function that only gets used in writeback mode was putting IFLUSH as the last instruction in the hardware loop ... we know from design that this may often lead to inifite core stalling, so switch the FLUSH/IFLUSH order. Signed-off-by: Mike Frysinger Signed-off-by: Bryan Wu --- arch/blackfin/mach-common/cache.S | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/blackfin/mach-common/cache.S b/arch/blackfin/mach-common/cache.S index d6780b495241..a028e9450419 100644 --- a/arch/blackfin/mach-common/cache.S +++ b/arch/blackfin/mach-common/cache.S @@ -67,7 +67,7 @@ ENDPROC(_blackfin_icache_flush_range) /* Flush all cache lines assocoiated with this area of memory. */ ENTRY(_blackfin_icache_dcache_flush_range) - do_flush IFLUSH, FLUSH + do_flush FLUSH, IFLUSH ENDPROC(_blackfin_icache_dcache_flush_range) /* Throw away all D-cached data in specified region without any obligation to -- cgit v1.2.2 From da986b9ffff79224417b69cf43506192bd9c29dc Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Tue, 28 Oct 2008 13:58:15 +0800 Subject: Blackfin arch: dont warn when running a kernel on the oldest supported silicon Signed-off-by: Mike Frysinger Signed-off-by: Bryan Wu --- arch/blackfin/kernel/setup.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/blackfin/kernel/setup.c b/arch/blackfin/kernel/setup.c index 8337dc3a62d7..71a9a8c53cea 100644 --- a/arch/blackfin/kernel/setup.c +++ b/arch/blackfin/kernel/setup.c @@ -827,7 +827,7 @@ void __init setup_arch(char **cmdline_p) printk(KERN_ERR "Warning: Compiled for Rev %d, but running on Rev %d\n", bfin_compiled_revid(), bfin_revid()); } - if (bfin_revid() <= CONFIG_BF_REV_MIN || bfin_revid() > CONFIG_BF_REV_MAX) + if (bfin_revid() < CONFIG_BF_REV_MIN || bfin_revid() > CONFIG_BF_REV_MAX) printk(KERN_ERR "Warning: Unsupported Chip Revision ADSP-%s Rev 0.%d detected\n", CPU, bfin_revid()); } -- cgit v1.2.2 From a10101d5ff9e34c0a1a526725474eef84409529a Mon Sep 17 00:00:00 2001 From: Michael Hennerich Date: Tue, 28 Oct 2008 14:18:29 +0800 Subject: Blackfin arch: fix bug - Cpufreq assumes clocks in kHz and not Hz. Signed-off-by: Michael Hennerich Signed-off-by: Bryan Wu --- arch/blackfin/mach-common/cpufreq.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) (limited to 'arch') diff --git a/arch/blackfin/mach-common/cpufreq.c b/arch/blackfin/mach-common/cpufreq.c index c22c47b60127..dda5443b37ed 100644 --- a/arch/blackfin/mach-common/cpufreq.c +++ b/arch/blackfin/mach-common/cpufreq.c @@ -72,13 +72,13 @@ unsigned int __bfin_cycles_mod; /**************************************************************************/ -static unsigned int bfin_getfreq(unsigned int cpu) +static unsigned int bfin_getfreq_khz(unsigned int cpu) { /* The driver only support single cpu */ if (cpu != 0) return -1; - return get_cclk(); + return get_cclk() / 1000; } @@ -96,7 +96,7 @@ static int bfin_target(struct cpufreq_policy *policy, cclk_hz = bfin_freq_table[index].frequency; - freqs.old = bfin_getfreq(0); + freqs.old = bfin_getfreq_khz(0); freqs.new = cclk_hz; freqs.cpu = 0; @@ -137,8 +137,8 @@ static int __init __bfin_cpu_init(struct cpufreq_policy *policy) if (policy->cpu != 0) return -EINVAL; - cclk = get_cclk(); - sclk = get_sclk(); + cclk = get_cclk() / 1000; + sclk = get_sclk() / 1000; #if ANOMALY_05000273 || (!defined(CONFIG_BF54x) && defined(CONFIG_BFIN_DCACHE)) min_cclk = sclk * 2; @@ -152,7 +152,7 @@ static int __init __bfin_cpu_init(struct cpufreq_policy *policy) dpm_state_table[index].csel = csel << 4; /* Shift now into PLL_DIV bitpos */ dpm_state_table[index].tscale = (TIME_SCALE / (1 << csel)) - 1; - pr_debug("cpufreq: freq:%d csel:%d tscale:%d\n", + pr_debug("cpufreq: freq:%d csel:0x%x tscale:%d\n", bfin_freq_table[index].frequency, dpm_state_table[index].csel, dpm_state_table[index].tscale); @@ -173,7 +173,7 @@ static struct freq_attr *bfin_freq_attr[] = { static struct cpufreq_driver bfin_driver = { .verify = bfin_verify_speed, .target = bfin_target, - .get = bfin_getfreq, + .get = bfin_getfreq_khz, .init = __bfin_cpu_init, .name = "bfin cpufreq", .owner = THIS_MODULE, -- cgit v1.2.2 From 72edff8dd45fdee6e1a2bc431baefd8a5372f7cb Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Tue, 28 Oct 2008 15:42:13 +0800 Subject: Blackfin arch: fix incorrect limit check for bf54x check_gpio Signed-off-by: Mike Frysinger Signed-off-by: Bryan Wu --- arch/blackfin/kernel/bfin_gpio.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/blackfin/kernel/bfin_gpio.c b/arch/blackfin/kernel/bfin_gpio.c index 6e08f425bb44..5c0800adb4dd 100644 --- a/arch/blackfin/kernel/bfin_gpio.c +++ b/arch/blackfin/kernel/bfin_gpio.c @@ -218,7 +218,7 @@ inline int check_gpio(unsigned gpio) if (gpio == GPIO_PB15 || gpio == GPIO_PC14 || gpio == GPIO_PC15 || gpio == GPIO_PH14 || gpio == GPIO_PH15 || gpio == GPIO_PJ14 || gpio == GPIO_PJ15 - || gpio > MAX_BLACKFIN_GPIOS) + || gpio >= MAX_BLACKFIN_GPIOS) return -EINVAL; return 0; } -- cgit v1.2.2 From b2c2f30388c682520ae2d07c8852b4225dd4a4d7 Mon Sep 17 00:00:00 2001 From: Jie Zhang Date: Tue, 28 Oct 2008 15:57:49 +0800 Subject: Blackfin arch: fix bug - shared lib function in L2 failed be called Allow user space to access L2 SRAM. Signed-off-by: Jie Zhang Signed-off-by: Bryan Wu --- arch/blackfin/kernel/process.c | 7 ++++++- arch/blackfin/mm/sram-alloc.c | 8 ++++---- 2 files changed, 10 insertions(+), 5 deletions(-) (limited to 'arch') diff --git a/arch/blackfin/kernel/process.c b/arch/blackfin/kernel/process.c index 77800dd83e57..0c3ea118b657 100644 --- a/arch/blackfin/kernel/process.c +++ b/arch/blackfin/kernel/process.c @@ -351,9 +351,14 @@ int _access_ok(unsigned long addr, unsigned long size) return 1; #endif #if L1_DATA_B_LENGTH != 0 - if (addr >= L1_DATA_B_START + if (addr >= L1_DATA_B_START + (_ebss_b_l1 - _sdata_b_l1) && addr + size <= L1_DATA_B_START + L1_DATA_B_LENGTH) return 1; +#endif +#if L2_LENGTH != 0 + if (addr >= L2_START + (_ebss_l2 - _stext_l2) + && addr + size <= L2_START + L2_LENGTH) + return 1; #endif return 0; } diff --git a/arch/blackfin/mm/sram-alloc.c b/arch/blackfin/mm/sram-alloc.c index 0f1ca6930c16..cc6f336e7313 100644 --- a/arch/blackfin/mm/sram-alloc.c +++ b/arch/blackfin/mm/sram-alloc.c @@ -183,10 +183,10 @@ static void __init l2_sram_init(void) return; } - free_l2_sram_head.next->paddr = (void *)L2_START + - (_etext_l2 - _stext_l2) + (_edata_l2 - _sdata_l2); - free_l2_sram_head.next->size = L2_LENGTH - - (_etext_l2 - _stext_l2) + (_edata_l2 - _sdata_l2); + free_l2_sram_head.next->paddr = + (void *)L2_START + (_ebss_l2 - _stext_l2); + free_l2_sram_head.next->size = + L2_LENGTH - (_ebss_l2 - _stext_l2); free_l2_sram_head.next->pid = 0; free_l2_sram_head.next->next = NULL; -- cgit v1.2.2 From 4213cb64004e38b3e78424f30e1e638f8004c7a8 Mon Sep 17 00:00:00 2001 From: Graf Yang Date: Tue, 18 Nov 2008 17:48:22 +0800 Subject: Blackfin arch: fix bug - Turn on DEBUG_DOUBLEFAULT, booting SMP kernel crash Signed-off-by: Graf Yang Signed-off-by: Bryan Wu --- arch/blackfin/mach-common/entry.S | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/blackfin/mach-common/entry.S b/arch/blackfin/mach-common/entry.S index c13fa8da28c7..bde6dc4e2614 100644 --- a/arch/blackfin/mach-common/entry.S +++ b/arch/blackfin/mach-common/entry.S @@ -277,7 +277,7 @@ ENTRY(_bfin_return_from_exception) p5.h = hi(ILAT); r6 = [p5]; r7 = 0x20; /* Did I just cause anther HW error? */ - r7 = r7 & r1; + r6 = r7 & r6; CC = R7 == R6; if CC JUMP _double_fault; #endif -- cgit v1.2.2 From 62273eeb6ac516ab0abf49417378726ad8875b03 Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Tue, 18 Nov 2008 17:48:22 +0800 Subject: Blackfin arch: fix a broken define in dma-mapping dma_mapping_error is an actual function, so fix broken define with a real inline stub Signed-off-by: Mike Frysinger Signed-off-by: Bryan Wu --- arch/blackfin/include/asm/dma-mapping.h | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/blackfin/include/asm/dma-mapping.h b/arch/blackfin/include/asm/dma-mapping.h index ede748d67efd..d7d9148e433c 100644 --- a/arch/blackfin/include/asm/dma-mapping.h +++ b/arch/blackfin/include/asm/dma-mapping.h @@ -15,7 +15,11 @@ void dma_free_coherent(struct device *dev, size_t size, void *vaddr, #define dma_alloc_noncoherent(d, s, h, f) dma_alloc_coherent(d, s, h, f) #define dma_free_noncoherent(d, s, v, h) dma_free_coherent(d, s, v, h) -#define dma_mapping_error +static inline +int dma_mapping_error(struct device *dev, dma_addr_t dma_addr) +{ + return 0; +} /* * Map a single buffer of the indicated size for DMA in streaming mode. -- cgit v1.2.2