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authorMax Filippov <jcmvbkbc@gmail.com>2012-09-16 21:44:54 -0400
committerChris Zankel <chris@zankel.net>2012-10-03 18:12:43 -0400
commiteb9a63a1e550c489ba389c53bef0f7a94156fa8e (patch)
treeb36faff105cf9bca99931a2ffa613c0fca05b4b7 /arch/xtensa
parenta4c8aa5e5c229be926c40f83509c8a30145802c6 (diff)
xtensa: rename MISC SR definition to avoid name clashes
There are other special register that cause build warnings and may as well need renaming as well. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Chris Zankel <chris@zankel.net>
Diffstat (limited to 'arch/xtensa')
-rw-r--r--arch/xtensa/include/asm/regs.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/xtensa/include/asm/regs.h b/arch/xtensa/include/asm/regs.h
index d4baed246928..a3075b12aff1 100644
--- a/arch/xtensa/include/asm/regs.h
+++ b/arch/xtensa/include/asm/regs.h
@@ -66,7 +66,7 @@
66#define ICOUNTLEVEL 237 66#define ICOUNTLEVEL 237
67#define EXCVADDR 238 67#define EXCVADDR 238
68#define CCOMPARE 240 68#define CCOMPARE 240
69#define MISC 244 69#define MISC_SR 244
70 70
71/* Special names for read-only and write-only interrupt registers. */ 71/* Special names for read-only and write-only interrupt registers. */
72 72