aboutsummaryrefslogtreecommitdiffstats
path: root/arch/xtensa/variants
diff options
context:
space:
mode:
authorDaniel Glöckner <dg@emlix.com>2014-10-18 18:46:25 -0400
committerMax Filippov <jcmvbkbc@gmail.com>2014-10-21 05:29:01 -0400
commit4006e565e1500db40b8546dcc6011737bc5d986c (patch)
treeff158ef0a7de01246cf3793787e50b74c5838218 /arch/xtensa/variants
parent3932b9ca55b0be314a36d3e84faff3e823c081f5 (diff)
xtensa: remove s6000 variant and s6105 platform
The Stretch s6000 family support has been merged into mainline 5 years ago. There appear to be no users of this code since nobody complained that there is a merge error preventing compilation. Apart from the s6105 IP camera reference design there are no s6000 devices known to ever have run Linux and as the chips are out of production there probably never will be. The successor s7000 no longer uses an Xtensa core for the OS. Let's remove the code until someone is found who actually needs it. Signed-off-by: Daniel Glöckner <dg@emlix.com> Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Diffstat (limited to 'arch/xtensa/variants')
-rw-r--r--arch/xtensa/variants/s6000/Makefile4
-rw-r--r--arch/xtensa/variants/s6000/delay.c25
-rw-r--r--arch/xtensa/variants/s6000/dmac.c173
-rw-r--r--arch/xtensa/variants/s6000/gpio.c230
-rw-r--r--arch/xtensa/variants/s6000/include/variant/core.h431
-rw-r--r--arch/xtensa/variants/s6000/include/variant/dmac.h387
-rw-r--r--arch/xtensa/variants/s6000/include/variant/gpio.h6
-rw-r--r--arch/xtensa/variants/s6000/include/variant/hardware.h259
-rw-r--r--arch/xtensa/variants/s6000/include/variant/irq.h8
-rw-r--r--arch/xtensa/variants/s6000/include/variant/tie-asm.h304
-rw-r--r--arch/xtensa/variants/s6000/include/variant/tie.h191
-rw-r--r--arch/xtensa/variants/s6000/irq.c74
12 files changed, 0 insertions, 2092 deletions
diff --git a/arch/xtensa/variants/s6000/Makefile b/arch/xtensa/variants/s6000/Makefile
deleted file mode 100644
index 3e7ef0a0c498..000000000000
--- a/arch/xtensa/variants/s6000/Makefile
+++ /dev/null
@@ -1,4 +0,0 @@
1# s6000 Makefile
2
3obj-y += irq.o gpio.o dmac.o
4obj-$(CONFIG_XTENSA_CALIBRATE_CCOUNT) += delay.o
diff --git a/arch/xtensa/variants/s6000/delay.c b/arch/xtensa/variants/s6000/delay.c
deleted file mode 100644
index 39154563ee17..000000000000
--- a/arch/xtensa/variants/s6000/delay.c
+++ /dev/null
@@ -1,25 +0,0 @@
1#include <asm/timex.h>
2#include <asm/io.h>
3#include <variant/hardware.h>
4
5#define LOOPS 10
6void platform_calibrate_ccount(void)
7{
8 u32 uninitialized_var(a);
9 u32 uninitialized_var(u);
10 u32 b;
11 u32 tstamp = S6_REG_GREG1 + S6_GREG1_GLOBAL_TIMER;
12 int i = LOOPS+1;
13 do {
14 u32 t = u;
15 asm volatile(
16 "1: l32i %0, %2, 0 ;"
17 " beq %0, %1, 1b ;"
18 : "=&a"(u) : "a"(t), "a"(tstamp));
19 b = get_ccount();
20 if (i == LOOPS)
21 a = b;
22 } while (--i >= 0);
23 b -= a;
24 ccount_freq = b * (100000UL / LOOPS);
25}
diff --git a/arch/xtensa/variants/s6000/dmac.c b/arch/xtensa/variants/s6000/dmac.c
deleted file mode 100644
index 340f5bb0b5ef..000000000000
--- a/arch/xtensa/variants/s6000/dmac.c
+++ /dev/null
@@ -1,173 +0,0 @@
1/*
2 * Authors: Oskar Schirmer <oskar@scara.com>
3 * Daniel Gloeckner <dg@emlix.com>
4 * (c) 2008 emlix GmbH http://www.emlix.com
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
11
12#include <linux/kernel.h>
13#include <linux/io.h>
14#include <linux/types.h>
15#include <linux/errno.h>
16#include <linux/spinlock.h>
17#include <asm/cacheflush.h>
18#include <variant/dmac.h>
19
20/* DMA engine lookup */
21
22struct s6dmac_ctrl s6dmac_ctrl[S6_DMAC_NB];
23
24
25/* DMA control, per engine */
26
27void s6dmac_put_fifo_cache(u32 dmac, int chan, u32 src, u32 dst, u32 size)
28{
29 if (xtensa_need_flush_dma_source(src)) {
30 u32 base = src;
31 u32 span = size;
32 u32 chunk = readl(DMA_CHNL(dmac, chan) + S6_DMA_CMONCHUNK);
33 if (chunk && (size > chunk)) {
34 s32 skip =
35 readl(DMA_CHNL(dmac, chan) + S6_DMA_SRCSKIP);
36 u32 gaps = (size+chunk-1)/chunk - 1;
37 if (skip >= 0) {
38 span += gaps * skip;
39 } else if (-skip > chunk) {
40 s32 decr = gaps * (chunk + skip);
41 base += decr;
42 span = chunk - decr;
43 } else {
44 span = max(span + gaps * skip,
45 (chunk + skip) * gaps - skip);
46 }
47 }
48 flush_dcache_unaligned(base, span);
49 }
50 if (xtensa_need_invalidate_dma_destination(dst)) {
51 u32 base = dst;
52 u32 span = size;
53 u32 chunk = readl(DMA_CHNL(dmac, chan) + S6_DMA_CMONCHUNK);
54 if (chunk && (size > chunk)) {
55 s32 skip =
56 readl(DMA_CHNL(dmac, chan) + S6_DMA_DSTSKIP);
57 u32 gaps = (size+chunk-1)/chunk - 1;
58 if (skip >= 0) {
59 span += gaps * skip;
60 } else if (-skip > chunk) {
61 s32 decr = gaps * (chunk + skip);
62 base += decr;
63 span = chunk - decr;
64 } else {
65 span = max(span + gaps * skip,
66 (chunk + skip) * gaps - skip);
67 }
68 }
69 invalidate_dcache_unaligned(base, span);
70 }
71 s6dmac_put_fifo(dmac, chan, src, dst, size);
72}
73
74void s6dmac_disable_error_irqs(u32 dmac, u32 mask)
75{
76 unsigned long flags;
77 spinlock_t *spinl = &s6dmac_ctrl[_dmac_addr_index(dmac)].lock;
78 spin_lock_irqsave(spinl, flags);
79 _s6dmac_disable_error_irqs(dmac, mask);
80 spin_unlock_irqrestore(spinl, flags);
81}
82
83u32 s6dmac_int_sources(u32 dmac, u32 channel)
84{
85 u32 mask, ret, tmp;
86 mask = 1 << channel;
87
88 tmp = readl(dmac + S6_DMA_TERMCNTIRQSTAT);
89 tmp &= mask;
90 writel(tmp, dmac + S6_DMA_TERMCNTIRQCLR);
91 ret = tmp >> channel;
92
93 tmp = readl(dmac + S6_DMA_PENDCNTIRQSTAT);
94 tmp &= mask;
95 writel(tmp, dmac + S6_DMA_PENDCNTIRQCLR);
96 ret |= (tmp >> channel) << 1;
97
98 tmp = readl(dmac + S6_DMA_LOWWMRKIRQSTAT);
99 tmp &= mask;
100 writel(tmp, dmac + S6_DMA_LOWWMRKIRQCLR);
101 ret |= (tmp >> channel) << 2;
102
103 tmp = readl(dmac + S6_DMA_INTRAW0);
104 tmp &= (mask << S6_DMA_INT0_OVER) | (mask << S6_DMA_INT0_UNDER);
105 writel(tmp, dmac + S6_DMA_INTCLEAR0);
106
107 if (tmp & (mask << S6_DMA_INT0_UNDER))
108 ret |= 1 << 3;
109 if (tmp & (mask << S6_DMA_INT0_OVER))
110 ret |= 1 << 4;
111
112 tmp = readl(dmac + S6_DMA_MASTERERRINFO);
113 mask <<= S6_DMA_INT1_CHANNEL;
114 if (((tmp >> S6_DMA_MASTERERR_CHAN(0)) & S6_DMA_MASTERERR_CHAN_MASK)
115 == channel)
116 mask |= 1 << S6_DMA_INT1_MASTER;
117 if (((tmp >> S6_DMA_MASTERERR_CHAN(1)) & S6_DMA_MASTERERR_CHAN_MASK)
118 == channel)
119 mask |= 1 << (S6_DMA_INT1_MASTER + 1);
120 if (((tmp >> S6_DMA_MASTERERR_CHAN(2)) & S6_DMA_MASTERERR_CHAN_MASK)
121 == channel)
122 mask |= 1 << (S6_DMA_INT1_MASTER + 2);
123
124 tmp = readl(dmac + S6_DMA_INTRAW1) & mask;
125 writel(tmp, dmac + S6_DMA_INTCLEAR1);
126 ret |= ((tmp >> channel) & 1) << 5;
127 ret |= ((tmp >> S6_DMA_INT1_MASTER) & S6_DMA_INT1_MASTER_MASK) << 6;
128
129 return ret;
130}
131
132void s6dmac_release_chan(u32 dmac, int chan)
133{
134 if (chan >= 0)
135 s6dmac_disable_chan(dmac, chan);
136}
137
138
139/* global init */
140
141static inline void __init dmac_init(u32 dmac, u8 chan_nb)
142{
143 s6dmac_ctrl[S6_DMAC_INDEX(dmac)].dmac = dmac;
144 spin_lock_init(&s6dmac_ctrl[S6_DMAC_INDEX(dmac)].lock);
145 s6dmac_ctrl[S6_DMAC_INDEX(dmac)].chan_nb = chan_nb;
146 writel(S6_DMA_INT1_MASTER_MASK << S6_DMA_INT1_MASTER,
147 dmac + S6_DMA_INTCLEAR1);
148}
149
150static inline void __init dmac_master(u32 dmac,
151 u32 m0start, u32 m0end, u32 m1start, u32 m1end)
152{
153 writel(m0start, dmac + S6_DMA_MASTER0START);
154 writel(m0end - 1, dmac + S6_DMA_MASTER0END);
155 writel(m1start, dmac + S6_DMA_MASTER1START);
156 writel(m1end - 1, dmac + S6_DMA_MASTER1END);
157}
158
159static void __init s6_dmac_init(void)
160{
161 dmac_init(S6_REG_LMSDMA, S6_LMSDMA_NB);
162 dmac_master(S6_REG_LMSDMA,
163 S6_MEM_DDR, S6_MEM_PCIE_APER, S6_MEM_EFI, S6_MEM_GMAC);
164 dmac_init(S6_REG_NIDMA, S6_NIDMA_NB);
165 dmac_init(S6_REG_DPDMA, S6_DPDMA_NB);
166 dmac_master(S6_REG_DPDMA,
167 S6_MEM_DDR, S6_MEM_PCIE_APER, S6_REG_DP, S6_REG_DPDMA);
168 dmac_init(S6_REG_HIFDMA, S6_HIFDMA_NB);
169 dmac_master(S6_REG_HIFDMA,
170 S6_MEM_GMAC, S6_MEM_PCIE_CFG, S6_MEM_PCIE_APER, S6_MEM_AUX);
171}
172
173arch_initcall(s6_dmac_init);
diff --git a/arch/xtensa/variants/s6000/gpio.c b/arch/xtensa/variants/s6000/gpio.c
deleted file mode 100644
index da9e85c13b08..000000000000
--- a/arch/xtensa/variants/s6000/gpio.c
+++ /dev/null
@@ -1,230 +0,0 @@
1/*
2 * s6000 gpio driver
3 *
4 * Copyright (c) 2009 emlix GmbH
5 * Authors: Oskar Schirmer <oskar@scara.com>
6 * Johannes Weiner <hannes@cmpxchg.org>
7 * Daniel Gloeckner <dg@emlix.com>
8 */
9#include <linux/bitops.h>
10#include <linux/kernel.h>
11#include <linux/module.h>
12#include <linux/init.h>
13#include <linux/io.h>
14#include <linux/irq.h>
15#include <linux/gpio.h>
16
17#include <variant/hardware.h>
18
19#define IRQ_BASE XTENSA_NR_IRQS
20
21#define S6_GPIO_DATA 0x000
22#define S6_GPIO_IS 0x404
23#define S6_GPIO_IBE 0x408
24#define S6_GPIO_IEV 0x40C
25#define S6_GPIO_IE 0x410
26#define S6_GPIO_RIS 0x414
27#define S6_GPIO_MIS 0x418
28#define S6_GPIO_IC 0x41C
29#define S6_GPIO_AFSEL 0x420
30#define S6_GPIO_DIR 0x800
31#define S6_GPIO_BANK(nr) ((nr) * 0x1000)
32#define S6_GPIO_MASK(nr) (4 << (nr))
33#define S6_GPIO_OFFSET(nr) \
34 (S6_GPIO_BANK((nr) >> 3) + S6_GPIO_MASK((nr) & 7))
35
36static int direction_input(struct gpio_chip *chip, unsigned int off)
37{
38 writeb(0, S6_REG_GPIO + S6_GPIO_DIR + S6_GPIO_OFFSET(off));
39 return 0;
40}
41
42static int get(struct gpio_chip *chip, unsigned int off)
43{
44 return readb(S6_REG_GPIO + S6_GPIO_DATA + S6_GPIO_OFFSET(off));
45}
46
47static int direction_output(struct gpio_chip *chip, unsigned int off, int val)
48{
49 unsigned rel = S6_GPIO_OFFSET(off);
50 writeb(~0, S6_REG_GPIO + S6_GPIO_DIR + rel);
51 writeb(val ? ~0 : 0, S6_REG_GPIO + S6_GPIO_DATA + rel);
52 return 0;
53}
54
55static void set(struct gpio_chip *chip, unsigned int off, int val)
56{
57 writeb(val ? ~0 : 0, S6_REG_GPIO + S6_GPIO_DATA + S6_GPIO_OFFSET(off));
58}
59
60static int to_irq(struct gpio_chip *chip, unsigned offset)
61{
62 if (offset < 8)
63 return offset + IRQ_BASE;
64 return -EINVAL;
65}
66
67static struct gpio_chip gpiochip = {
68 .owner = THIS_MODULE,
69 .direction_input = direction_input,
70 .get = get,
71 .direction_output = direction_output,
72 .set = set,
73 .to_irq = to_irq,
74 .base = 0,
75 .ngpio = 24,
76 .can_sleep = 0, /* no blocking io needed */
77 .exported = 0, /* no exporting to userspace */
78};
79
80int s6_gpio_init(u32 afsel)
81{
82 writeb(afsel, S6_REG_GPIO + S6_GPIO_BANK(0) + S6_GPIO_AFSEL);
83 writeb(afsel >> 8, S6_REG_GPIO + S6_GPIO_BANK(1) + S6_GPIO_AFSEL);
84 writeb(afsel >> 16, S6_REG_GPIO + S6_GPIO_BANK(2) + S6_GPIO_AFSEL);
85 return gpiochip_add(&gpiochip);
86}
87
88static void ack(struct irq_data *d)
89{
90 writeb(1 << (d->irq - IRQ_BASE), S6_REG_GPIO + S6_GPIO_IC);
91}
92
93static void mask(struct irq_data *d)
94{
95 u8 r = readb(S6_REG_GPIO + S6_GPIO_IE);
96 r &= ~(1 << (d->irq - IRQ_BASE));
97 writeb(r, S6_REG_GPIO + S6_GPIO_IE);
98}
99
100static void unmask(struct irq_data *d)
101{
102 u8 m = readb(S6_REG_GPIO + S6_GPIO_IE);
103 m |= 1 << (d->irq - IRQ_BASE);
104 writeb(m, S6_REG_GPIO + S6_GPIO_IE);
105}
106
107static int set_type(struct irq_data *d, unsigned int type)
108{
109 const u8 m = 1 << (d->irq - IRQ_BASE);
110 irq_flow_handler_t handler;
111 u8 reg;
112
113 if (type == IRQ_TYPE_PROBE) {
114 if ((readb(S6_REG_GPIO + S6_GPIO_BANK(0) + S6_GPIO_AFSEL) & m)
115 || (readb(S6_REG_GPIO + S6_GPIO_BANK(0) + S6_GPIO_IE) & m)
116 || readb(S6_REG_GPIO + S6_GPIO_BANK(0) + S6_GPIO_DIR
117 + S6_GPIO_MASK(irq - IRQ_BASE)))
118 return 0;
119 type = IRQ_TYPE_EDGE_BOTH;
120 }
121
122 reg = readb(S6_REG_GPIO + S6_GPIO_BANK(0) + S6_GPIO_IS);
123 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) {
124 reg |= m;
125 handler = handle_level_irq;
126 } else {
127 reg &= ~m;
128 handler = handle_edge_irq;
129 }
130 writeb(reg, S6_REG_GPIO + S6_GPIO_BANK(0) + S6_GPIO_IS);
131 __irq_set_handler_locked(irq, handler);
132
133 reg = readb(S6_REG_GPIO + S6_GPIO_BANK(0) + S6_GPIO_IEV);
134 if (type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_EDGE_RISING))
135 reg |= m;
136 else
137 reg &= ~m;
138 writeb(reg, S6_REG_GPIO + S6_GPIO_BANK(0) + S6_GPIO_IEV);
139
140 reg = readb(S6_REG_GPIO + S6_GPIO_BANK(0) + S6_GPIO_IBE);
141 if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH)
142 reg |= m;
143 else
144 reg &= ~m;
145 writeb(reg, S6_REG_GPIO + S6_GPIO_BANK(0) + S6_GPIO_IBE);
146 return 0;
147}
148
149static struct irq_chip gpioirqs = {
150 .name = "GPIO",
151 .irq_ack = ack,
152 .irq_mask = mask,
153 .irq_unmask = unmask,
154 .irq_set_type = set_type,
155};
156
157static u8 demux_masks[4];
158
159static void demux_irqs(unsigned int irq, struct irq_desc *desc)
160{
161 struct irq_chip *chip = irq_desc_get_chip(desc);
162 u8 *mask = irq_desc_get_handler_data(desc);
163 u8 pending;
164 int cirq;
165
166 chip->irq_mask(&desc->irq_data);
167 chip->irq_ack(&desc->irq_data);
168 pending = readb(S6_REG_GPIO + S6_GPIO_BANK(0) + S6_GPIO_MIS) & *mask;
169 cirq = IRQ_BASE - 1;
170 while (pending) {
171 int n = ffs(pending);
172 cirq += n;
173 pending >>= n;
174 generic_handle_irq(cirq);
175 }
176 chip->irq_unmask(&desc->irq_data);
177}
178
179extern const signed char *platform_irq_mappings[XTENSA_NR_IRQS];
180
181void __init variant_init_irq(void)
182{
183 int irq, n;
184 writeb(0, S6_REG_GPIO + S6_GPIO_BANK(0) + S6_GPIO_IE);
185 for (irq = n = 0; irq < XTENSA_NR_IRQS; irq++) {
186 const signed char *mapping = platform_irq_mappings[irq];
187 int alone = 1;
188 u8 mask;
189 if (!mapping)
190 continue;
191 for(mask = 0; *mapping != -1; mapping++)
192 switch (*mapping) {
193 case S6_INTC_GPIO(0):
194 mask |= 1 << 0;
195 break;
196 case S6_INTC_GPIO(1):
197 mask |= 1 << 1;
198 break;
199 case S6_INTC_GPIO(2):
200 mask |= 1 << 2;
201 break;
202 case S6_INTC_GPIO(3):
203 mask |= 0x1f << 3;
204 break;
205 default:
206 alone = 0;
207 }
208 if (mask) {
209 int cirq, i;
210 if (!alone) {
211 printk(KERN_ERR "chained irq chips can't share"
212 " parent irq %i\n", irq);
213 continue;
214 }
215 demux_masks[n] = mask;
216 cirq = IRQ_BASE - 1;
217 do {
218 i = ffs(mask);
219 cirq += i;
220 mask >>= i;
221 irq_set_chip(cirq, &gpioirqs);
222 irq_set_irq_type(irq, IRQ_TYPE_LEVEL_LOW);
223 } while (mask);
224 irq_set_handler_data(irq, demux_masks + n);
225 irq_set_chained_handler(irq, demux_irqs);
226 if (++n == ARRAY_SIZE(demux_masks))
227 break;
228 }
229 }
230}
diff --git a/arch/xtensa/variants/s6000/include/variant/core.h b/arch/xtensa/variants/s6000/include/variant/core.h
deleted file mode 100644
index af007953027e..000000000000
--- a/arch/xtensa/variants/s6000/include/variant/core.h
+++ /dev/null
@@ -1,431 +0,0 @@
1/*
2 * Xtensa processor core configuration information.
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
6 * for more details.
7 *
8 * Copyright (c) 1999-2008 Tensilica Inc.
9 */
10
11#ifndef _XTENSA_CORE_CONFIGURATION_H
12#define _XTENSA_CORE_CONFIGURATION_H
13
14
15/****************************************************************************
16 Parameters Useful for Any Code, USER or PRIVILEGED
17 ****************************************************************************/
18
19/*
20 * Note: Macros of the form XCHAL_HAVE_*** have a value of 1 if the option is
21 * configured, and a value of 0 otherwise. These macros are always defined.
22 */
23
24
25/*----------------------------------------------------------------------
26 ISA
27 ----------------------------------------------------------------------*/
28
29#define XCHAL_HAVE_BE 0 /* big-endian byte ordering */
30#define XCHAL_HAVE_WINDOWED 1 /* windowed registers option */
31#define XCHAL_NUM_AREGS 64 /* num of physical addr regs */
32#define XCHAL_NUM_AREGS_LOG2 6 /* log2(XCHAL_NUM_AREGS) */
33#define XCHAL_MAX_INSTRUCTION_SIZE 8 /* max instr bytes (3..8) */
34#define XCHAL_HAVE_DEBUG 1 /* debug option */
35#define XCHAL_HAVE_DENSITY 1 /* 16-bit instructions */
36#define XCHAL_HAVE_LOOPS 1 /* zero-overhead loops */
37#define XCHAL_HAVE_NSA 1 /* NSA/NSAU instructions */
38#define XCHAL_HAVE_MINMAX 1 /* MIN/MAX instructions */
39#define XCHAL_HAVE_SEXT 1 /* SEXT instruction */
40#define XCHAL_HAVE_CLAMPS 1 /* CLAMPS instruction */
41#define XCHAL_HAVE_MUL16 1 /* MUL16S/MUL16U instructions */
42#define XCHAL_HAVE_MUL32 1 /* MULL instruction */
43#define XCHAL_HAVE_MUL32_HIGH 1 /* MULUH/MULSH instructions */
44#define XCHAL_HAVE_DIV32 0 /* QUOS/QUOU/REMS/REMU instructions */
45#define XCHAL_HAVE_L32R 1 /* L32R instruction */
46#define XCHAL_HAVE_ABSOLUTE_LITERALS 1 /* non-PC-rel (extended) L32R */
47#define XCHAL_HAVE_CONST16 0 /* CONST16 instruction */
48#define XCHAL_HAVE_ADDX 1 /* ADDX#/SUBX# instructions */
49#define XCHAL_HAVE_WIDE_BRANCHES 0 /* B*.W18 or B*.W15 instr's */
50#define XCHAL_HAVE_PREDICTED_BRANCHES 0 /* B[EQ/EQZ/NE/NEZ]T instr's */
51#define XCHAL_HAVE_CALL4AND12 1 /* (obsolete option) */
52#define XCHAL_HAVE_ABS 1 /* ABS instruction */
53/*#define XCHAL_HAVE_POPC 0*/ /* POPC instruction */
54/*#define XCHAL_HAVE_CRC 0*/ /* CRC instruction */
55#define XCHAL_HAVE_RELEASE_SYNC 0 /* L32AI/S32RI instructions */
56#define XCHAL_HAVE_S32C1I 0 /* S32C1I instruction */
57#define XCHAL_HAVE_SPECULATION 0 /* speculation */
58#define XCHAL_HAVE_FULL_RESET 0 /* all regs/state reset */
59#define XCHAL_NUM_CONTEXTS 1 /* */
60#define XCHAL_NUM_MISC_REGS 4 /* num of scratch regs (0..4) */
61#define XCHAL_HAVE_TAP_MASTER 0 /* JTAG TAP control instr's */
62#define XCHAL_HAVE_PRID 0 /* processor ID register */
63#define XCHAL_HAVE_THREADPTR 0 /* THREADPTR register */
64#define XCHAL_HAVE_BOOLEANS 1 /* boolean registers */
65#define XCHAL_HAVE_CP 1 /* CPENABLE reg (coprocessor) */
66#define XCHAL_CP_MAXCFG 8 /* max allowed cp id plus one */
67#define XCHAL_HAVE_MAC16 0 /* MAC16 package */
68#define XCHAL_HAVE_VECTORFPU2005 0 /* vector floating-point pkg */
69#define XCHAL_HAVE_FP 1 /* floating point pkg */
70#define XCHAL_HAVE_VECTRA1 0 /* Vectra I pkg */
71#define XCHAL_HAVE_VECTRALX 0 /* Vectra LX pkg */
72#define XCHAL_HAVE_HIFI2 0 /* HiFi2 Audio Engine pkg */
73
74
75/*----------------------------------------------------------------------
76 MISC
77 ----------------------------------------------------------------------*/
78
79#define XCHAL_NUM_WRITEBUFFER_ENTRIES 8 /* size of write buffer */
80#define XCHAL_INST_FETCH_WIDTH 8 /* instr-fetch width in bytes */
81#define XCHAL_DATA_WIDTH 16 /* data width in bytes */
82/* In T1050, applies to selected core load and store instructions (see ISA): */
83#define XCHAL_UNALIGNED_LOAD_EXCEPTION 1 /* unaligned loads cause exc. */
84#define XCHAL_UNALIGNED_STORE_EXCEPTION 1 /* unaligned stores cause exc.*/
85
86#define XCHAL_SW_VERSION 701001 /* sw version of this header */
87
88#define XCHAL_CORE_ID "stretch_bali" /* alphanum core name
89 (CoreID) set in the Xtensa
90 Processor Generator */
91
92#define XCHAL_BUILD_UNIQUE_ID 0x000104B9 /* 22-bit sw build ID */
93
94/*
95 * These definitions describe the hardware targeted by this software.
96 */
97#define XCHAL_HW_CONFIGID0 0xC2F3F9FE /* ConfigID hi 32 bits*/
98#define XCHAL_HW_CONFIGID1 0x054104B9 /* ConfigID lo 32 bits*/
99#define XCHAL_HW_VERSION_NAME "LX1.0.2" /* full version name */
100#define XCHAL_HW_VERSION_MAJOR 2100 /* major ver# of targeted hw */
101#define XCHAL_HW_VERSION_MINOR 2 /* minor ver# of targeted hw */
102#define XCHAL_HW_VERSION 210002 /* major*100+minor */
103#define XCHAL_HW_REL_LX1 1
104#define XCHAL_HW_REL_LX1_0 1
105#define XCHAL_HW_REL_LX1_0_2 1
106#define XCHAL_HW_CONFIGID_RELIABLE 1
107/* If software targets a *range* of hardware versions, these are the bounds: */
108#define XCHAL_HW_MIN_VERSION_MAJOR 2100 /* major v of earliest tgt hw */
109#define XCHAL_HW_MIN_VERSION_MINOR 2 /* minor v of earliest tgt hw */
110#define XCHAL_HW_MIN_VERSION 210002 /* earliest targeted hw */
111#define XCHAL_HW_MAX_VERSION_MAJOR 2100 /* major v of latest tgt hw */
112#define XCHAL_HW_MAX_VERSION_MINOR 2 /* minor v of latest tgt hw */
113#define XCHAL_HW_MAX_VERSION 210002 /* latest targeted hw */
114
115
116/*----------------------------------------------------------------------
117 CACHE
118 ----------------------------------------------------------------------*/
119
120#define XCHAL_ICACHE_LINESIZE 16 /* I-cache line size in bytes */
121#define XCHAL_DCACHE_LINESIZE 16 /* D-cache line size in bytes */
122#define XCHAL_ICACHE_LINEWIDTH 4 /* log2(I line size in bytes) */
123#define XCHAL_DCACHE_LINEWIDTH 4 /* log2(D line size in bytes) */
124
125#define XCHAL_ICACHE_SIZE 32768 /* I-cache size in bytes or 0 */
126#define XCHAL_DCACHE_SIZE 32768 /* D-cache size in bytes or 0 */
127
128#define XCHAL_DCACHE_IS_WRITEBACK 1 /* writeback feature */
129
130
131
132
133/****************************************************************************
134 Parameters Useful for PRIVILEGED (Supervisory or Non-Virtualized) Code
135 ****************************************************************************/
136
137
138#ifndef XTENSA_HAL_NON_PRIVILEGED_ONLY
139
140/*----------------------------------------------------------------------
141 CACHE
142 ----------------------------------------------------------------------*/
143
144#define XCHAL_HAVE_PIF 1 /* any outbound PIF present */
145
146/* If present, cache size in bytes == (ways * 2^(linewidth + setwidth)). */
147
148/* Number of cache sets in log2(lines per way): */
149#define XCHAL_ICACHE_SETWIDTH 9
150#define XCHAL_DCACHE_SETWIDTH 10
151
152/* Cache set associativity (number of ways): */
153#define XCHAL_ICACHE_WAYS 4
154#define XCHAL_DCACHE_WAYS 2
155
156/* Cache features: */
157#define XCHAL_ICACHE_LINE_LOCKABLE 1
158#define XCHAL_DCACHE_LINE_LOCKABLE 0
159#define XCHAL_ICACHE_ECC_PARITY 0
160#define XCHAL_DCACHE_ECC_PARITY 0
161
162/* Number of encoded cache attr bits (see <xtensa/hal.h> for decoded bits): */
163#define XCHAL_CA_BITS 4
164
165
166/*----------------------------------------------------------------------
167 INTERNAL I/D RAM/ROMs and XLMI
168 ----------------------------------------------------------------------*/
169
170#define XCHAL_NUM_INSTROM 0 /* number of core instr. ROMs */
171#define XCHAL_NUM_INSTRAM 0 /* number of core instr. RAMs */
172#define XCHAL_NUM_DATAROM 0 /* number of core data ROMs */
173#define XCHAL_NUM_DATARAM 1 /* number of core data RAMs */
174#define XCHAL_NUM_URAM 0 /* number of core unified RAMs*/
175#define XCHAL_NUM_XLMI 1 /* number of core XLMI ports */
176
177/* Data RAM 0: */
178#define XCHAL_DATARAM0_VADDR 0x3FFF0000
179#define XCHAL_DATARAM0_PADDR 0x3FFF0000
180#define XCHAL_DATARAM0_SIZE 65536
181#define XCHAL_DATARAM0_ECC_PARITY 0
182
183/* XLMI Port 0: */
184#define XCHAL_XLMI0_VADDR 0x37F80000
185#define XCHAL_XLMI0_PADDR 0x37F80000
186#define XCHAL_XLMI0_SIZE 262144
187#define XCHAL_XLMI0_ECC_PARITY 0
188
189
190/*----------------------------------------------------------------------
191 INTERRUPTS and TIMERS
192 ----------------------------------------------------------------------*/
193
194#define XCHAL_HAVE_INTERRUPTS 1 /* interrupt option */
195#define XCHAL_HAVE_HIGHPRI_INTERRUPTS 1 /* med/high-pri. interrupts */
196#define XCHAL_HAVE_NMI 1 /* non-maskable interrupt */
197#define XCHAL_HAVE_CCOUNT 1 /* CCOUNT reg. (timer option) */
198#define XCHAL_NUM_TIMERS 3 /* number of CCOMPAREn regs */
199#define XCHAL_NUM_INTERRUPTS 27 /* number of interrupts */
200#define XCHAL_NUM_INTERRUPTS_LOG2 5 /* ceil(log2(NUM_INTERRUPTS)) */
201#define XCHAL_NUM_EXTINTERRUPTS 20 /* num of external interrupts */
202#define XCHAL_NUM_INTLEVELS 4 /* number of interrupt levels
203 (not including level zero) */
204#define XCHAL_EXCM_LEVEL 1 /* level masked by PS.EXCM */
205 /* (always 1 in XEA1; levels 2 .. EXCM_LEVEL are "medium priority") */
206
207/* Masks of interrupts at each interrupt level: */
208#define XCHAL_INTLEVEL1_MASK 0x01F07FFF
209#define XCHAL_INTLEVEL2_MASK 0x02018000
210#define XCHAL_INTLEVEL3_MASK 0x04060000
211#define XCHAL_INTLEVEL4_MASK 0x00000000
212#define XCHAL_INTLEVEL5_MASK 0x00080000
213#define XCHAL_INTLEVEL6_MASK 0x00000000
214#define XCHAL_INTLEVEL7_MASK 0x00000000
215
216/* Masks of interrupts at each range 1..n of interrupt levels: */
217#define XCHAL_INTLEVEL1_ANDBELOW_MASK 0x01F07FFF
218#define XCHAL_INTLEVEL2_ANDBELOW_MASK 0x03F1FFFF
219#define XCHAL_INTLEVEL3_ANDBELOW_MASK 0x07F7FFFF
220#define XCHAL_INTLEVEL4_ANDBELOW_MASK 0x07F7FFFF
221#define XCHAL_INTLEVEL5_ANDBELOW_MASK 0x07FFFFFF
222#define XCHAL_INTLEVEL6_ANDBELOW_MASK 0x07FFFFFF
223#define XCHAL_INTLEVEL7_ANDBELOW_MASK 0x07FFFFFF
224
225/* Level of each interrupt: */
226#define XCHAL_INT0_LEVEL 1
227#define XCHAL_INT1_LEVEL 1
228#define XCHAL_INT2_LEVEL 1
229#define XCHAL_INT3_LEVEL 1
230#define XCHAL_INT4_LEVEL 1
231#define XCHAL_INT5_LEVEL 1
232#define XCHAL_INT6_LEVEL 1
233#define XCHAL_INT7_LEVEL 1
234#define XCHAL_INT8_LEVEL 1
235#define XCHAL_INT9_LEVEL 1
236#define XCHAL_INT10_LEVEL 1
237#define XCHAL_INT11_LEVEL 1
238#define XCHAL_INT12_LEVEL 1
239#define XCHAL_INT13_LEVEL 1
240#define XCHAL_INT14_LEVEL 1
241#define XCHAL_INT15_LEVEL 2
242#define XCHAL_INT16_LEVEL 2
243#define XCHAL_INT17_LEVEL 3
244#define XCHAL_INT18_LEVEL 3
245#define XCHAL_INT19_LEVEL 5
246#define XCHAL_INT20_LEVEL 1
247#define XCHAL_INT21_LEVEL 1
248#define XCHAL_INT22_LEVEL 1
249#define XCHAL_INT23_LEVEL 1
250#define XCHAL_INT24_LEVEL 1
251#define XCHAL_INT25_LEVEL 2
252#define XCHAL_INT26_LEVEL 3
253#define XCHAL_DEBUGLEVEL 4 /* debug interrupt level */
254#define XCHAL_HAVE_DEBUG_EXTERN_INT 1 /* OCD external db interrupt */
255#define XCHAL_NMILEVEL 5 /* NMI "level" (for use with
256 EXCSAVE/EPS/EPC_n, RFI n) */
257
258/* Type of each interrupt: */
259#define XCHAL_INT0_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
260#define XCHAL_INT1_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
261#define XCHAL_INT2_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
262#define XCHAL_INT3_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
263#define XCHAL_INT4_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
264#define XCHAL_INT5_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
265#define XCHAL_INT6_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
266#define XCHAL_INT7_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
267#define XCHAL_INT8_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
268#define XCHAL_INT9_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
269#define XCHAL_INT10_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
270#define XCHAL_INT11_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
271#define XCHAL_INT12_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
272#define XCHAL_INT13_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
273#define XCHAL_INT14_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
274#define XCHAL_INT15_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
275#define XCHAL_INT16_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
276#define XCHAL_INT17_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
277#define XCHAL_INT18_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
278#define XCHAL_INT19_TYPE XTHAL_INTTYPE_NMI
279#define XCHAL_INT20_TYPE XTHAL_INTTYPE_SOFTWARE
280#define XCHAL_INT21_TYPE XTHAL_INTTYPE_SOFTWARE
281#define XCHAL_INT22_TYPE XTHAL_INTTYPE_SOFTWARE
282#define XCHAL_INT23_TYPE XTHAL_INTTYPE_SOFTWARE
283#define XCHAL_INT24_TYPE XTHAL_INTTYPE_TIMER
284#define XCHAL_INT25_TYPE XTHAL_INTTYPE_TIMER
285#define XCHAL_INT26_TYPE XTHAL_INTTYPE_TIMER
286
287/* Masks of interrupts for each type of interrupt: */
288#define XCHAL_INTTYPE_MASK_UNCONFIGURED 0xF8000000
289#define XCHAL_INTTYPE_MASK_SOFTWARE 0x00F00000
290#define XCHAL_INTTYPE_MASK_EXTERN_EDGE 0x00000000
291#define XCHAL_INTTYPE_MASK_EXTERN_LEVEL 0x0007FFFF
292#define XCHAL_INTTYPE_MASK_TIMER 0x07000000
293#define XCHAL_INTTYPE_MASK_NMI 0x00080000
294#define XCHAL_INTTYPE_MASK_WRITE_ERROR 0x00000000
295
296/* Interrupt numbers assigned to specific interrupt sources: */
297#define XCHAL_TIMER0_INTERRUPT 24 /* CCOMPARE0 */
298#define XCHAL_TIMER1_INTERRUPT 25 /* CCOMPARE1 */
299#define XCHAL_TIMER2_INTERRUPT 26 /* CCOMPARE2 */
300#define XCHAL_TIMER3_INTERRUPT XTHAL_TIMER_UNCONFIGURED
301#define XCHAL_NMI_INTERRUPT 19 /* non-maskable interrupt */
302
303/* Interrupt numbers for levels at which only one interrupt is configured: */
304#define XCHAL_INTLEVEL5_NUM 19
305/* (There are many interrupts each at level(s) 1, 2, 3.) */
306
307
308/*
309 * External interrupt vectors/levels.
310 * These macros describe how Xtensa processor interrupt numbers
311 * (as numbered internally, eg. in INTERRUPT and INTENABLE registers)
312 * map to external BInterrupt<n> pins, for those interrupts
313 * configured as external (level-triggered, edge-triggered, or NMI).
314 * See the Xtensa processor databook for more details.
315 */
316
317/* Core interrupt numbers mapped to each EXTERNAL interrupt number: */
318#define XCHAL_EXTINT0_NUM 0 /* (intlevel 1) */
319#define XCHAL_EXTINT1_NUM 1 /* (intlevel 1) */
320#define XCHAL_EXTINT2_NUM 2 /* (intlevel 1) */
321#define XCHAL_EXTINT3_NUM 3 /* (intlevel 1) */
322#define XCHAL_EXTINT4_NUM 4 /* (intlevel 1) */
323#define XCHAL_EXTINT5_NUM 5 /* (intlevel 1) */
324#define XCHAL_EXTINT6_NUM 6 /* (intlevel 1) */
325#define XCHAL_EXTINT7_NUM 7 /* (intlevel 1) */
326#define XCHAL_EXTINT8_NUM 8 /* (intlevel 1) */
327#define XCHAL_EXTINT9_NUM 9 /* (intlevel 1) */
328#define XCHAL_EXTINT10_NUM 10 /* (intlevel 1) */
329#define XCHAL_EXTINT11_NUM 11 /* (intlevel 1) */
330#define XCHAL_EXTINT12_NUM 12 /* (intlevel 1) */
331#define XCHAL_EXTINT13_NUM 13 /* (intlevel 1) */
332#define XCHAL_EXTINT14_NUM 14 /* (intlevel 1) */
333#define XCHAL_EXTINT15_NUM 15 /* (intlevel 2) */
334#define XCHAL_EXTINT16_NUM 16 /* (intlevel 2) */
335#define XCHAL_EXTINT17_NUM 17 /* (intlevel 3) */
336#define XCHAL_EXTINT18_NUM 18 /* (intlevel 3) */
337#define XCHAL_EXTINT19_NUM 19 /* (intlevel 5) */
338
339
340/*----------------------------------------------------------------------
341 EXCEPTIONS and VECTORS
342 ----------------------------------------------------------------------*/
343
344#define XCHAL_XEA_VERSION 2 /* Xtensa Exception Architecture
345 number: 1 == XEA1 (old)
346 2 == XEA2 (new)
347 0 == XEAX (extern) */
348#define XCHAL_HAVE_XEA1 0 /* Exception Architecture 1 */
349#define XCHAL_HAVE_XEA2 1 /* Exception Architecture 2 */
350#define XCHAL_HAVE_XEAX 0 /* External Exception Arch. */
351#define XCHAL_HAVE_EXCEPTIONS 1 /* exception option */
352#define XCHAL_HAVE_MEM_ECC_PARITY 0 /* local memory ECC/parity */
353#define XCHAL_HAVE_VECTOR_SELECT 0 /* relocatable vectors */
354#define XCHAL_HAVE_VECBASE 0 /* relocatable vectors */
355
356#define XCHAL_RESET_VECOFS 0x00000000
357#define XCHAL_RESET_VECTOR_VADDR 0x3FFE03D0
358#define XCHAL_RESET_VECTOR_PADDR 0x3FFE03D0
359#define XCHAL_USER_VECOFS 0x00000000
360#define XCHAL_USER_VECTOR_VADDR 0x40000220
361#define XCHAL_USER_VECTOR_PADDR 0x40000220
362#define XCHAL_KERNEL_VECOFS 0x00000000
363#define XCHAL_KERNEL_VECTOR_VADDR 0x40000200
364#define XCHAL_KERNEL_VECTOR_PADDR 0x40000200
365#define XCHAL_DOUBLEEXC_VECOFS 0x00000000
366#define XCHAL_DOUBLEEXC_VECTOR_VADDR 0x400002A0
367#define XCHAL_DOUBLEEXC_VECTOR_PADDR 0x400002A0
368#define XCHAL_WINDOW_OF4_VECOFS 0x00000000
369#define XCHAL_WINDOW_UF4_VECOFS 0x00000040
370#define XCHAL_WINDOW_OF8_VECOFS 0x00000080
371#define XCHAL_WINDOW_UF8_VECOFS 0x000000C0
372#define XCHAL_WINDOW_OF12_VECOFS 0x00000100
373#define XCHAL_WINDOW_UF12_VECOFS 0x00000140
374#define XCHAL_WINDOW_VECTORS_VADDR 0x40000000
375#define XCHAL_WINDOW_VECTORS_PADDR 0x40000000
376#define XCHAL_INTLEVEL2_VECOFS 0x00000000
377#define XCHAL_INTLEVEL2_VECTOR_VADDR 0x40000240
378#define XCHAL_INTLEVEL2_VECTOR_PADDR 0x40000240
379#define XCHAL_INTLEVEL3_VECOFS 0x00000000
380#define XCHAL_INTLEVEL3_VECTOR_VADDR 0x40000260
381#define XCHAL_INTLEVEL3_VECTOR_PADDR 0x40000260
382#define XCHAL_INTLEVEL4_VECOFS 0x00000000
383#define XCHAL_INTLEVEL4_VECTOR_VADDR 0x40000390
384#define XCHAL_INTLEVEL4_VECTOR_PADDR 0x40000390
385#define XCHAL_DEBUG_VECOFS XCHAL_INTLEVEL4_VECOFS
386#define XCHAL_DEBUG_VECTOR_VADDR XCHAL_INTLEVEL4_VECTOR_VADDR
387#define XCHAL_DEBUG_VECTOR_PADDR XCHAL_INTLEVEL4_VECTOR_PADDR
388#define XCHAL_NMI_VECOFS 0x00000000
389#define XCHAL_NMI_VECTOR_VADDR 0x400003B0
390#define XCHAL_NMI_VECTOR_PADDR 0x400003B0
391#define XCHAL_INTLEVEL5_VECOFS XCHAL_NMI_VECOFS
392#define XCHAL_INTLEVEL5_VECTOR_VADDR XCHAL_NMI_VECTOR_VADDR
393#define XCHAL_INTLEVEL5_VECTOR_PADDR XCHAL_NMI_VECTOR_PADDR
394
395
396/*----------------------------------------------------------------------
397 DEBUG
398 ----------------------------------------------------------------------*/
399
400#define XCHAL_HAVE_OCD 1 /* OnChipDebug option */
401#define XCHAL_NUM_IBREAK 2 /* number of IBREAKn regs */
402#define XCHAL_NUM_DBREAK 2 /* number of DBREAKn regs */
403#define XCHAL_HAVE_OCD_DIR_ARRAY 1 /* faster OCD option */
404
405
406/*----------------------------------------------------------------------
407 MMU
408 ----------------------------------------------------------------------*/
409
410/* See core-matmap.h header file for more details. */
411
412#define XCHAL_HAVE_TLBS 1 /* inverse of HAVE_CACHEATTR */
413#define XCHAL_HAVE_SPANNING_WAY 1 /* one way maps I+D 4GB vaddr */
414#define XCHAL_HAVE_IDENTITY_MAP 1 /* vaddr == paddr always */
415#define XCHAL_HAVE_CACHEATTR 0 /* CACHEATTR register present */
416#define XCHAL_HAVE_MIMIC_CACHEATTR 1 /* region protection */
417#define XCHAL_HAVE_XLT_CACHEATTR 0 /* region prot. w/translation */
418#define XCHAL_HAVE_PTP_MMU 0 /* full MMU (with page table
419 [autorefill] and protection)
420 usable for an MMU-based OS */
421/* If none of the above last 4 are set, it's a custom TLB configuration. */
422
423#define XCHAL_MMU_ASID_BITS 0 /* number of bits in ASIDs */
424#define XCHAL_MMU_RINGS 1 /* number of rings (1..4) */
425#define XCHAL_MMU_RING_BITS 0 /* num of bits in RING field */
426
427#endif /* !XTENSA_HAL_NON_PRIVILEGED_ONLY */
428
429
430#endif /* _XTENSA_CORE_CONFIGURATION_H */
431
diff --git a/arch/xtensa/variants/s6000/include/variant/dmac.h b/arch/xtensa/variants/s6000/include/variant/dmac.h
deleted file mode 100644
index 3f88d9fc6897..000000000000
--- a/arch/xtensa/variants/s6000/include/variant/dmac.h
+++ /dev/null
@@ -1,387 +0,0 @@
1/*
2 * include/asm-xtensa/variant-s6000/dmac.h
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
6 * for more details.
7 *
8 * Copyright (C) 2006 Tensilica Inc.
9 * Copyright (C) 2008 Emlix GmbH <info@emlix.com>
10 * Authors: Fabian Godehardt <fg@emlix.com>
11 * Oskar Schirmer <oskar@scara.com>
12 * Daniel Gloeckner <dg@emlix.com>
13 */
14
15#ifndef __ASM_XTENSA_S6000_DMAC_H
16#define __ASM_XTENSA_S6000_DMAC_H
17#include <linux/io.h>
18#include <variant/hardware.h>
19
20/* DMA global */
21
22#define S6_DMA_INTSTAT0 0x000
23#define S6_DMA_INTSTAT1 0x004
24#define S6_DMA_INTENABLE0 0x008
25#define S6_DMA_INTENABLE1 0x00C
26#define S6_DMA_INTRAW0 0x010
27#define S6_DMA_INTRAW1 0x014
28#define S6_DMA_INTCLEAR0 0x018
29#define S6_DMA_INTCLEAR1 0x01C
30#define S6_DMA_INTSET0 0x020
31#define S6_DMA_INTSET1 0x024
32#define S6_DMA_INT0_UNDER 0
33#define S6_DMA_INT0_OVER 16
34#define S6_DMA_INT1_CHANNEL 0
35#define S6_DMA_INT1_MASTER 16
36#define S6_DMA_INT1_MASTER_MASK 7
37#define S6_DMA_TERMCNTIRQSTAT 0x028
38#define S6_DMA_TERMCNTIRQCLR 0x02C
39#define S6_DMA_TERMCNTIRQSET 0x030
40#define S6_DMA_PENDCNTIRQSTAT 0x034
41#define S6_DMA_PENDCNTIRQCLR 0x038
42#define S6_DMA_PENDCNTIRQSET 0x03C
43#define S6_DMA_LOWWMRKIRQSTAT 0x040
44#define S6_DMA_LOWWMRKIRQCLR 0x044
45#define S6_DMA_LOWWMRKIRQSET 0x048
46#define S6_DMA_MASTERERRINFO 0x04C
47#define S6_DMA_MASTERERR_CHAN(n) (4*(n))
48#define S6_DMA_MASTERERR_CHAN_MASK 0xF
49#define S6_DMA_DESCRFIFO0 0x050
50#define S6_DMA_DESCRFIFO1 0x054
51#define S6_DMA_DESCRFIFO2 0x058
52#define S6_DMA_DESCRFIFO2_AUTODISABLE 24
53#define S6_DMA_DESCRFIFO3 0x05C
54#define S6_DMA_MASTER0START 0x060
55#define S6_DMA_MASTER0END 0x064
56#define S6_DMA_MASTER1START 0x068
57#define S6_DMA_MASTER1END 0x06C
58#define S6_DMA_NEXTFREE 0x070
59#define S6_DMA_NEXTFREE_CHAN 0
60#define S6_DMA_NEXTFREE_CHAN_MASK 0x1F
61#define S6_DMA_NEXTFREE_ENA 16
62#define S6_DMA_NEXTFREE_ENA_MASK ((1 << 16) - 1)
63#define S6_DMA_DPORTCTRLGRP(p) ((p) * 4 + 0x074)
64#define S6_DMA_DPORTCTRLGRP_FRAMEREP 0
65#define S6_DMA_DPORTCTRLGRP_NRCHANS 1
66#define S6_DMA_DPORTCTRLGRP_NRCHANS_1 0
67#define S6_DMA_DPORTCTRLGRP_NRCHANS_3 1
68#define S6_DMA_DPORTCTRLGRP_NRCHANS_4 2
69#define S6_DMA_DPORTCTRLGRP_NRCHANS_2 3
70#define S6_DMA_DPORTCTRLGRP_ENA 31
71
72
73/* DMA per channel */
74
75#define DMA_CHNL(dmac, n) ((dmac) + 0x1000 + (n) * 0x100)
76#define DMA_INDEX_CHNL(addr) (((addr) >> 8) & 0xF)
77#define DMA_MASK_DMAC(addr) ((addr) & 0xFFFF0000)
78#define S6_DMA_CHNCTRL 0x000
79#define S6_DMA_CHNCTRL_ENABLE 0
80#define S6_DMA_CHNCTRL_PAUSE 1
81#define S6_DMA_CHNCTRL_PRIO 2
82#define S6_DMA_CHNCTRL_PRIO_MASK 3
83#define S6_DMA_CHNCTRL_PERIPHXFER 4
84#define S6_DMA_CHNCTRL_PERIPHENA 5
85#define S6_DMA_CHNCTRL_SRCINC 6
86#define S6_DMA_CHNCTRL_DSTINC 7
87#define S6_DMA_CHNCTRL_BURSTLOG 8
88#define S6_DMA_CHNCTRL_BURSTLOG_MASK 7
89#define S6_DMA_CHNCTRL_DESCFIFODEPTH 12
90#define S6_DMA_CHNCTRL_DESCFIFODEPTH_MASK 0x1F
91#define S6_DMA_CHNCTRL_DESCFIFOFULL 17
92#define S6_DMA_CHNCTRL_BWCONSEL 18
93#define S6_DMA_CHNCTRL_BWCONENA 19
94#define S6_DMA_CHNCTRL_PENDGCNTSTAT 20
95#define S6_DMA_CHNCTRL_PENDGCNTSTAT_MASK 0x3F
96#define S6_DMA_CHNCTRL_LOWWMARK 26
97#define S6_DMA_CHNCTRL_LOWWMARK_MASK 0xF
98#define S6_DMA_CHNCTRL_TSTAMP 30
99#define S6_DMA_TERMCNTNB 0x004
100#define S6_DMA_TERMCNTNB_MASK 0xFFFF
101#define S6_DMA_TERMCNTTMO 0x008
102#define S6_DMA_TERMCNTSTAT 0x00C
103#define S6_DMA_TERMCNTSTAT_MASK 0xFF
104#define S6_DMA_CMONCHUNK 0x010
105#define S6_DMA_SRCSKIP 0x014
106#define S6_DMA_DSTSKIP 0x018
107#define S6_DMA_CUR_SRC 0x024
108#define S6_DMA_CUR_DST 0x028
109#define S6_DMA_TIMESTAMP 0x030
110
111/* DMA channel lists */
112
113#define S6_DPDMA_CHAN(stream, channel) (4 * (stream) + (channel))
114#define S6_DPDMA_NB 16
115
116#define S6_HIFDMA_GMACTX 0
117#define S6_HIFDMA_GMACRX 1
118#define S6_HIFDMA_I2S0 2
119#define S6_HIFDMA_I2S1 3
120#define S6_HIFDMA_EGIB 4
121#define S6_HIFDMA_PCITX 5
122#define S6_HIFDMA_PCIRX 6
123#define S6_HIFDMA_NB 7
124
125#define S6_NIDMA_NB 4
126
127#define S6_LMSDMA_NB 12
128
129/* controller access */
130
131#define S6_DMAC_NB 4
132#define S6_DMAC_INDEX(dmac) (((unsigned)(dmac) >> 18) % S6_DMAC_NB)
133
134struct s6dmac_ctrl {
135 u32 dmac;
136 spinlock_t lock;
137 u8 chan_nb;
138};
139
140extern struct s6dmac_ctrl s6dmac_ctrl[S6_DMAC_NB];
141
142
143/* DMA control, per channel */
144
145static inline int s6dmac_fifo_full(u32 dmac, int chan)
146{
147 return (readl(DMA_CHNL(dmac, chan) + S6_DMA_CHNCTRL)
148 & (1 << S6_DMA_CHNCTRL_DESCFIFOFULL)) && 1;
149}
150
151static inline int s6dmac_termcnt_irq(u32 dmac, int chan)
152{
153 u32 m = 1 << chan;
154 int r = (readl(dmac + S6_DMA_TERMCNTIRQSTAT) & m) && 1;
155 if (r)
156 writel(m, dmac + S6_DMA_TERMCNTIRQCLR);
157 return r;
158}
159
160static inline int s6dmac_pendcnt_irq(u32 dmac, int chan)
161{
162 u32 m = 1 << chan;
163 int r = (readl(dmac + S6_DMA_PENDCNTIRQSTAT) & m) && 1;
164 if (r)
165 writel(m, dmac + S6_DMA_PENDCNTIRQCLR);
166 return r;
167}
168
169static inline int s6dmac_lowwmark_irq(u32 dmac, int chan)
170{
171 int r = (readl(dmac + S6_DMA_LOWWMRKIRQSTAT) & (1 << chan)) ? 1 : 0;
172 if (r)
173 writel(1 << chan, dmac + S6_DMA_LOWWMRKIRQCLR);
174 return r;
175}
176
177static inline u32 s6dmac_pending_count(u32 dmac, int chan)
178{
179 return (readl(DMA_CHNL(dmac, chan) + S6_DMA_CHNCTRL)
180 >> S6_DMA_CHNCTRL_PENDGCNTSTAT)
181 & S6_DMA_CHNCTRL_PENDGCNTSTAT_MASK;
182}
183
184static inline void s6dmac_set_terminal_count(u32 dmac, int chan, u32 n)
185{
186 n &= S6_DMA_TERMCNTNB_MASK;
187 n |= readl(DMA_CHNL(dmac, chan) + S6_DMA_TERMCNTNB)
188 & ~S6_DMA_TERMCNTNB_MASK;
189 writel(n, DMA_CHNL(dmac, chan) + S6_DMA_TERMCNTNB);
190}
191
192static inline u32 s6dmac_get_terminal_count(u32 dmac, int chan)
193{
194 return (readl(DMA_CHNL(dmac, chan) + S6_DMA_TERMCNTNB))
195 & S6_DMA_TERMCNTNB_MASK;
196}
197
198static inline u32 s6dmac_timestamp(u32 dmac, int chan)
199{
200 return readl(DMA_CHNL(dmac, chan) + S6_DMA_TIMESTAMP);
201}
202
203static inline u32 s6dmac_cur_src(u32 dmac, int chan)
204{
205 return readl(DMA_CHNL(dmac, chan) + S6_DMA_CUR_SRC);
206}
207
208static inline u32 s6dmac_cur_dst(u32 dmac, int chan)
209{
210 return readl(DMA_CHNL(dmac, chan) + S6_DMA_CUR_DST);
211}
212
213static inline void s6dmac_disable_chan(u32 dmac, int chan)
214{
215 u32 ctrl;
216 writel(readl(DMA_CHNL(dmac, chan) + S6_DMA_CHNCTRL)
217 & ~(1 << S6_DMA_CHNCTRL_ENABLE),
218 DMA_CHNL(dmac, chan) + S6_DMA_CHNCTRL);
219 do
220 ctrl = readl(DMA_CHNL(dmac, chan) + S6_DMA_CHNCTRL);
221 while (ctrl & (1 << S6_DMA_CHNCTRL_ENABLE));
222}
223
224static inline void s6dmac_set_stride_skip(u32 dmac, int chan,
225 int comchunk, /* 0: disable scatter/gather */
226 int srcskip, int dstskip)
227{
228 writel(comchunk, DMA_CHNL(dmac, chan) + S6_DMA_CMONCHUNK);
229 writel(srcskip, DMA_CHNL(dmac, chan) + S6_DMA_SRCSKIP);
230 writel(dstskip, DMA_CHNL(dmac, chan) + S6_DMA_DSTSKIP);
231}
232
233static inline void s6dmac_enable_chan(u32 dmac, int chan,
234 int prio, /* 0 (highest) .. 3 (lowest) */
235 int periphxfer, /* <0: disable p.req.line, 0..1: mode */
236 int srcinc, int dstinc, /* 0: dont increment src/dst address */
237 int comchunk, /* 0: disable scatter/gather */
238 int srcskip, int dstskip,
239 int burstsize, /* 4 for I2S, 7 for everything else */
240 int bandwidthconserve, /* <0: disable, 0..1: select */
241 int lowwmark, /* 0..15 */
242 int timestamp, /* 0: disable timestamp */
243 int enable) /* 0: disable for now */
244{
245 writel(1, DMA_CHNL(dmac, chan) + S6_DMA_TERMCNTNB);
246 writel(0, DMA_CHNL(dmac, chan) + S6_DMA_TERMCNTTMO);
247 writel(lowwmark << S6_DMA_CHNCTRL_LOWWMARK,
248 DMA_CHNL(dmac, chan) + S6_DMA_CHNCTRL);
249 s6dmac_set_stride_skip(dmac, chan, comchunk, srcskip, dstskip);
250 writel(((enable ? 1 : 0) << S6_DMA_CHNCTRL_ENABLE) |
251 (prio << S6_DMA_CHNCTRL_PRIO) |
252 (((periphxfer > 0) ? 1 : 0) << S6_DMA_CHNCTRL_PERIPHXFER) |
253 (((periphxfer < 0) ? 0 : 1) << S6_DMA_CHNCTRL_PERIPHENA) |
254 ((srcinc ? 1 : 0) << S6_DMA_CHNCTRL_SRCINC) |
255 ((dstinc ? 1 : 0) << S6_DMA_CHNCTRL_DSTINC) |
256 (burstsize << S6_DMA_CHNCTRL_BURSTLOG) |
257 (((bandwidthconserve > 0) ? 1 : 0) << S6_DMA_CHNCTRL_BWCONSEL) |
258 (((bandwidthconserve < 0) ? 0 : 1) << S6_DMA_CHNCTRL_BWCONENA) |
259 (lowwmark << S6_DMA_CHNCTRL_LOWWMARK) |
260 ((timestamp ? 1 : 0) << S6_DMA_CHNCTRL_TSTAMP),
261 DMA_CHNL(dmac, chan) + S6_DMA_CHNCTRL);
262}
263
264
265/* DMA control, per engine */
266
267static inline unsigned _dmac_addr_index(u32 dmac)
268{
269 unsigned i = S6_DMAC_INDEX(dmac);
270 if (s6dmac_ctrl[i].dmac != dmac)
271 BUG();
272 return i;
273}
274
275static inline void _s6dmac_disable_error_irqs(u32 dmac, u32 mask)
276{
277 writel(mask, dmac + S6_DMA_TERMCNTIRQCLR);
278 writel(mask, dmac + S6_DMA_PENDCNTIRQCLR);
279 writel(mask, dmac + S6_DMA_LOWWMRKIRQCLR);
280 writel(readl(dmac + S6_DMA_INTENABLE0)
281 & ~((mask << S6_DMA_INT0_UNDER) | (mask << S6_DMA_INT0_OVER)),
282 dmac + S6_DMA_INTENABLE0);
283 writel(readl(dmac + S6_DMA_INTENABLE1) & ~(mask << S6_DMA_INT1_CHANNEL),
284 dmac + S6_DMA_INTENABLE1);
285 writel((mask << S6_DMA_INT0_UNDER) | (mask << S6_DMA_INT0_OVER),
286 dmac + S6_DMA_INTCLEAR0);
287 writel(mask << S6_DMA_INT1_CHANNEL, dmac + S6_DMA_INTCLEAR1);
288}
289
290/*
291 * request channel from specified engine
292 * with chan<0, accept any channel
293 * further parameters see s6dmac_enable_chan
294 * returns < 0 upon error, channel nb otherwise
295 */
296static inline int s6dmac_request_chan(u32 dmac, int chan,
297 int prio,
298 int periphxfer,
299 int srcinc, int dstinc,
300 int comchunk,
301 int srcskip, int dstskip,
302 int burstsize,
303 int bandwidthconserve,
304 int lowwmark,
305 int timestamp,
306 int enable)
307{
308 int r = chan;
309 unsigned long flags;
310 spinlock_t *spinl = &s6dmac_ctrl[_dmac_addr_index(dmac)].lock;
311 spin_lock_irqsave(spinl, flags);
312 if (r < 0) {
313 r = (readl(dmac + S6_DMA_NEXTFREE) >> S6_DMA_NEXTFREE_CHAN)
314 & S6_DMA_NEXTFREE_CHAN_MASK;
315 }
316 if (r >= s6dmac_ctrl[_dmac_addr_index(dmac)].chan_nb) {
317 if (chan < 0)
318 r = -EBUSY;
319 else
320 r = -ENXIO;
321 } else if (((readl(dmac + S6_DMA_NEXTFREE) >> S6_DMA_NEXTFREE_ENA)
322 >> r) & 1) {
323 r = -EBUSY;
324 } else {
325 s6dmac_enable_chan(dmac, r, prio, periphxfer,
326 srcinc, dstinc, comchunk, srcskip, dstskip, burstsize,
327 bandwidthconserve, lowwmark, timestamp, enable);
328 }
329 spin_unlock_irqrestore(spinl, flags);
330 return r;
331}
332
333static inline void s6dmac_put_fifo(u32 dmac, int chan,
334 u32 src, u32 dst, u32 size)
335{
336 unsigned long flags;
337 spinlock_t *spinl = &s6dmac_ctrl[_dmac_addr_index(dmac)].lock;
338 spin_lock_irqsave(spinl, flags);
339 writel(src, dmac + S6_DMA_DESCRFIFO0);
340 writel(dst, dmac + S6_DMA_DESCRFIFO1);
341 writel(size, dmac + S6_DMA_DESCRFIFO2);
342 writel(chan, dmac + S6_DMA_DESCRFIFO3);
343 spin_unlock_irqrestore(spinl, flags);
344}
345
346static inline u32 s6dmac_channel_enabled(u32 dmac, int chan)
347{
348 return readl(DMA_CHNL(dmac, chan) + S6_DMA_CHNCTRL) &
349 (1 << S6_DMA_CHNCTRL_ENABLE);
350}
351
352/*
353 * group 1-4 data port channels
354 * with port=0..3, nrch=1-4 channels,
355 * frrep=0/1 (dis- or enable frame repeat)
356 */
357static inline void s6dmac_dp_setup_group(u32 dmac, int port,
358 int nrch, int frrep)
359{
360 static const u8 mask[4] = {0, 3, 1, 2};
361 BUG_ON(dmac != S6_REG_DPDMA);
362 if ((port < 0) || (port > 3) || (nrch < 1) || (nrch > 4))
363 return;
364 writel((mask[nrch - 1] << S6_DMA_DPORTCTRLGRP_NRCHANS)
365 | ((frrep ? 1 : 0) << S6_DMA_DPORTCTRLGRP_FRAMEREP),
366 dmac + S6_DMA_DPORTCTRLGRP(port));
367}
368
369static inline void s6dmac_dp_switch_group(u32 dmac, int port, int enable)
370{
371 u32 tmp;
372 BUG_ON(dmac != S6_REG_DPDMA);
373 tmp = readl(dmac + S6_DMA_DPORTCTRLGRP(port));
374 if (enable)
375 tmp |= (1 << S6_DMA_DPORTCTRLGRP_ENA);
376 else
377 tmp &= ~(1 << S6_DMA_DPORTCTRLGRP_ENA);
378 writel(tmp, dmac + S6_DMA_DPORTCTRLGRP(port));
379}
380
381extern void s6dmac_put_fifo_cache(u32 dmac, int chan,
382 u32 src, u32 dst, u32 size);
383extern void s6dmac_disable_error_irqs(u32 dmac, u32 mask);
384extern u32 s6dmac_int_sources(u32 dmac, u32 channel);
385extern void s6dmac_release_chan(u32 dmac, int chan);
386
387#endif /* __ASM_XTENSA_S6000_DMAC_H */
diff --git a/arch/xtensa/variants/s6000/include/variant/gpio.h b/arch/xtensa/variants/s6000/include/variant/gpio.h
deleted file mode 100644
index 8484ab0df461..000000000000
--- a/arch/xtensa/variants/s6000/include/variant/gpio.h
+++ /dev/null
@@ -1,6 +0,0 @@
1#ifndef _XTENSA_VARIANT_S6000_GPIO_H
2#define _XTENSA_VARIANT_S6000_GPIO_H
3
4extern int s6_gpio_init(u32 afsel);
5
6#endif /* _XTENSA_VARIANT_S6000_GPIO_H */
diff --git a/arch/xtensa/variants/s6000/include/variant/hardware.h b/arch/xtensa/variants/s6000/include/variant/hardware.h
deleted file mode 100644
index 5d9ba098d84a..000000000000
--- a/arch/xtensa/variants/s6000/include/variant/hardware.h
+++ /dev/null
@@ -1,259 +0,0 @@
1#ifndef __XTENSA_S6000_HARDWARE_H
2#define __XTENSA_S6000_HARDWARE_H
3
4#define S6_SCLK 1843200
5
6#define S6_MEM_REG 0x20000000
7#define S6_MEM_EFI 0x33F00000
8#define S6_MEM_PCIE_DATARAM1 0x34000000
9#define S6_MEM_XLMI 0x37F80000
10#define S6_MEM_PIF_DATARAM1 0x37FFC000
11#define S6_MEM_GMAC 0x38000000
12#define S6_MEM_I2S 0x3A000000
13#define S6_MEM_EGIB 0x3C000000
14#define S6_MEM_PCIE_CFG 0x3E000000
15#define S6_MEM_PIF_DATARAM 0x3FFE0000
16#define S6_MEM_XLMI_DATARAM 0x3FFF0000
17#define S6_MEM_DDR 0x40000000
18#define S6_MEM_PCIE_APER 0xC0000000
19#define S6_MEM_AUX 0xF0000000
20
21/* Device addresses */
22
23#define S6_REG_SCB S6_MEM_REG
24#define S6_REG_NB (S6_REG_SCB + 0x10000)
25#define S6_REG_LMSDMA (S6_REG_SCB + 0x20000)
26#define S6_REG_NI (S6_REG_SCB + 0x30000)
27#define S6_REG_NIDMA (S6_REG_SCB + 0x40000)
28#define S6_REG_NS (S6_REG_SCB + 0x50000)
29#define S6_REG_DDR (S6_REG_SCB + 0x60000)
30#define S6_REG_GREG1 (S6_REG_SCB + 0x70000)
31#define S6_REG_DP (S6_REG_SCB + 0x80000)
32#define S6_REG_DPDMA (S6_REG_SCB + 0x90000)
33#define S6_REG_EGIB (S6_REG_SCB + 0xA0000)
34#define S6_REG_PCIE (S6_REG_SCB + 0xB0000)
35#define S6_REG_I2S (S6_REG_SCB + 0xC0000)
36#define S6_REG_GMAC (S6_REG_SCB + 0xD0000)
37#define S6_REG_HIFDMA (S6_REG_SCB + 0xE0000)
38#define S6_REG_GREG2 (S6_REG_SCB + 0xF0000)
39
40#define S6_REG_APB S6_REG_SCB
41#define S6_REG_UART (S6_REG_APB + 0x0000)
42#define S6_REG_INTC (S6_REG_APB + 0x2000)
43#define S6_REG_SPI (S6_REG_APB + 0x3000)
44#define S6_REG_I2C (S6_REG_APB + 0x4000)
45#define S6_REG_GPIO (S6_REG_APB + 0x8000)
46
47/* Global register block */
48
49#define S6_GREG1_PLL_LOCKCLEAR 0x000
50#define S6_GREG1_PLL_LOCK_SYS 0
51#define S6_GREG1_PLL_LOCK_IO 1
52#define S6_GREG1_PLL_LOCK_AIM 2
53#define S6_GREG1_PLL_LOCK_DP0 3
54#define S6_GREG1_PLL_LOCK_DP2 4
55#define S6_GREG1_PLL_LOCK_DDR 5
56#define S6_GREG1_PLL_LOCKSTAT 0x004
57#define S6_GREG1_PLL_LOCKSTAT_CURLOCK 0
58#define S6_GREG1_PLL_LOCKSTAT_EVERUNLCK 8
59#define S6_GREG1_PLLSEL 0x010
60#define S6_GREG1_PLLSEL_AIM 0
61#define S6_GREG1_PLLSEL_AIM_DDR2 0
62#define S6_GREG1_PLLSEL_AIM_300MHZ 1
63#define S6_GREG1_PLLSEL_AIM_240MHZ 2
64#define S6_GREG1_PLLSEL_AIM_200MHZ 3
65#define S6_GREG1_PLLSEL_AIM_150MHZ 4
66#define S6_GREG1_PLLSEL_AIM_120MHZ 5
67#define S6_GREG1_PLLSEL_AIM_40MHZ 6
68#define S6_GREG1_PLLSEL_AIM_PLLAIMREF 7
69#define S6_GREG1_PLLSEL_AIM_MASK 7
70#define S6_GREG1_PLLSEL_DDR 8
71#define S6_GREG1_PLLSEL_DDR_HS 0
72#define S6_GREG1_PLLSEL_DDR_333MHZ 1
73#define S6_GREG1_PLLSEL_DDR_250MHZ 2
74#define S6_GREG1_PLLSEL_DDR_200MHZ 3
75#define S6_GREG1_PLLSEL_DDR_167MHZ 4
76#define S6_GREG1_PLLSEL_DDR_100MHZ 5
77#define S6_GREG1_PLLSEL_DDR_33MHZ 6
78#define S6_GREG1_PLLSEL_DDR_PLLIOREF 7
79#define S6_GREG1_PLLSEL_DDR_MASK 7
80#define S6_GREG1_PLLSEL_GMAC 16
81#define S6_GREG1_PLLSEL_GMAC_125MHZ 0
82#define S6_GREG1_PLLSEL_GMAC_25MHZ 1
83#define S6_GREG1_PLLSEL_GMAC_2500KHZ 2
84#define S6_GREG1_PLLSEL_GMAC_EXTERN 3
85#define S6_GREG1_PLLSEL_GMAC_MASK 3
86#define S6_GREG1_PLLSEL_GMII 18
87#define S6_GREG1_PLLSEL_GMII_111MHZ 0
88#define S6_GREG1_PLLSEL_GMII_IOREF 1
89#define S6_GREG1_PLLSEL_GMII_NONE 2
90#define S6_GREG1_PLLSEL_GMII_125MHZ 3
91#define S6_GREG1_PLLSEL_GMII_MASK 3
92#define S6_GREG1_SYSUNLOCKCNT 0x020
93#define S6_GREG1_IOUNLOCKCNT 0x024
94#define S6_GREG1_AIMUNLOCKCNT 0x028
95#define S6_GREG1_DP0UNLOCKCNT 0x02C
96#define S6_GREG1_DP2UNLOCKCNT 0x030
97#define S6_GREG1_DDRUNLOCKCNT 0x034
98#define S6_GREG1_CLKBAL0 0x040
99#define S6_GREG1_CLKBAL0_LSGB 0
100#define S6_GREG1_CLKBAL0_LSPX 8
101#define S6_GREG1_CLKBAL0_MEMDO 16
102#define S6_GREG1_CLKBAL0_HSXT1 24
103#define S6_GREG1_CLKBAL1 0x044
104#define S6_GREG1_CLKBAL1_HSISEF 0
105#define S6_GREG1_CLKBAL1_HSNI 8
106#define S6_GREG1_CLKBAL1_HSNS 16
107#define S6_GREG1_CLKBAL1_HSISEFCFG 24
108#define S6_GREG1_CLKBAL2 0x048
109#define S6_GREG1_CLKBAL2_LSNB 0
110#define S6_GREG1_CLKBAL2_LSSB 8
111#define S6_GREG1_CLKBAL2_LSREST 24
112#define S6_GREG1_CLKBAL3 0x04C
113#define S6_GREG1_CLKBAL3_ISEFXAD 0
114#define S6_GREG1_CLKBAL3_ISEFLMS 8
115#define S6_GREG1_CLKBAL3_ISEFISEF 16
116#define S6_GREG1_CLKBAL3_DDRDD 24
117#define S6_GREG1_CLKBAL4 0x050
118#define S6_GREG1_CLKBAL4_DDRDP 0
119#define S6_GREG1_CLKBAL4_DDRDO 8
120#define S6_GREG1_CLKBAL4_DDRNB 16
121#define S6_GREG1_CLKBAL4_DDRLMS 24
122#define S6_GREG1_BLOCKENA 0x100
123#define S6_GREG1_BLOCK_DDR 0
124#define S6_GREG1_BLOCK_DP 1
125#define S6_GREG1_BLOCK_NSNI 2
126#define S6_GREG1_BLOCK_PCIE 3
127#define S6_GREG1_BLOCK_GMAC 4
128#define S6_GREG1_BLOCK_I2S 5
129#define S6_GREG1_BLOCK_EGIB 6
130#define S6_GREG1_BLOCK_SB 7
131#define S6_GREG1_BLOCK_XT1 8
132#define S6_GREG1_CLKGATE 0x104
133#define S6_GREG1_BGATE_AIMNORTH 9
134#define S6_GREG1_BGATE_AIMEAST 10
135#define S6_GREG1_BGATE_AIMWEST 11
136#define S6_GREG1_BGATE_AIMSOUTH 12
137#define S6_GREG1_CHIPRES 0x108
138#define S6_GREG1_CHIPRES_SOFTRES 0
139#define S6_GREG1_CHIPRES_LOSTLOCK 1
140#define S6_GREG1_RESETCAUSE 0x10C
141#define S6_GREG1_RESETCAUSE_RESETN 0
142#define S6_GREG1_RESETCAUSE_GLOBAL 1
143#define S6_GREG1_RESETCAUSE_WDOGTIMER 2
144#define S6_GREG1_RESETCAUSE_SWCHIP 3
145#define S6_GREG1_RESETCAUSE_PLLSYSLOSS 4
146#define S6_GREG1_RESETCAUSE_PCIE 5
147#define S6_GREG1_RESETCAUSE_CREATEDGLOB 6
148#define S6_GREG1_REFCLOCKCNT 0x110
149#define S6_GREG1_RESETTIMER 0x114
150#define S6_GREG1_NMITIMER 0x118
151#define S6_GREG1_GLOBAL_TIMER 0x11C
152#define S6_GREG1_TIMER0 0x180
153#define S6_GREG1_TIMER1 0x184
154#define S6_GREG1_UARTCLOCKSEL 0x204
155#define S6_GREG1_CHIPVERSPACKG 0x208
156#define S6_GREG1_CHIPVERSPACKG_CHIPVID 0
157#define S6_GREG1_CHIPVERSPACKG_PACKSEL 8
158#define S6_GREG1_ONDIETERMCTRL 0x20C
159#define S6_GREG1_ONDIETERMCTRL_WEST 0
160#define S6_GREG1_ONDIETERMCTRL_NORTH 2
161#define S6_GREG1_ONDIETERMCTRL_EAST 4
162#define S6_GREG1_ONDIETERMCTRL_SOUTH 6
163#define S6_GREG1_ONDIETERMCTRL_NONE 0
164#define S6_GREG1_ONDIETERMCTRL_75OHM 2
165#define S6_GREG1_ONDIETERMCTRL_MASK 3
166#define S6_GREG1_BOOT_CFG0 0x210
167#define S6_GREG1_BOOT_CFG0_AIMSTRONG 1
168#define S6_GREG1_BOOT_CFG0_MINIBOOTDL 2
169#define S6_GREG1_BOOT_CFG0_OCDGPIO8SET 5
170#define S6_GREG1_BOOT_CFG0_OCDGPIOENA 6
171#define S6_GREG1_BOOT_CFG0_DOWNSTREAM 7
172#define S6_GREG1_BOOT_CFG0_PLLSYSDIV 8
173#define S6_GREG1_BOOT_CFG0_PLLSYSDIV_300MHZ 1
174#define S6_GREG1_BOOT_CFG0_PLLSYSDIV_240MHZ 2
175#define S6_GREG1_BOOT_CFG0_PLLSYSDIV_200MHZ 3
176#define S6_GREG1_BOOT_CFG0_PLLSYSDIV_150MHZ 4
177#define S6_GREG1_BOOT_CFG0_PLLSYSDIV_120MHZ 5
178#define S6_GREG1_BOOT_CFG0_PLLSYSDIV_40MHZ 6
179#define S6_GREG1_BOOT_CFG0_PLLSYSDIV_MASK 7
180#define S6_GREG1_BOOT_CFG0_BALHSLMS 12
181#define S6_GREG1_BOOT_CFG0_BALHSNB 18
182#define S6_GREG1_BOOT_CFG0_BALHSXAD 24
183#define S6_GREG1_BOOT_CFG1 0x214
184#define S6_GREG1_BOOT_CFG1_PCIE1LANE 1
185#define S6_GREG1_BOOT_CFG1_MPLLPRESCALE 2
186#define S6_GREG1_BOOT_CFG1_MPLLNCY 4
187#define S6_GREG1_BOOT_CFG1_MPLLNCY5 9
188#define S6_GREG1_BOOT_CFG1_BALHSREST 14
189#define S6_GREG1_BOOT_CFG1_BALHSPSMEMS 20
190#define S6_GREG1_BOOT_CFG1_BALLSGI 26
191#define S6_GREG1_BOOT_CFG2 0x218
192#define S6_GREG1_BOOT_CFG2_PEID 0
193#define S6_GREG1_BOOT_CFG3 0x21C
194#define S6_GREG1_DRAMBUSYHOLDOF 0x220
195#define S6_GREG1_DRAMBUSYHOLDOF_XT0 0
196#define S6_GREG1_DRAMBUSYHOLDOF_XT1 4
197#define S6_GREG1_DRAMBUSYHOLDOF_XT_MASK 7
198#define S6_GREG1_PCIEBAR1SIZE 0x224
199#define S6_GREG1_PCIEBAR2SIZE 0x228
200#define S6_GREG1_PCIEVENDOR 0x22C
201#define S6_GREG1_PCIEDEVICE 0x230
202#define S6_GREG1_PCIEREV 0x234
203#define S6_GREG1_PCIECLASS 0x238
204#define S6_GREG1_XT1DCACHEMISS 0x240
205#define S6_GREG1_XT1ICACHEMISS 0x244
206#define S6_GREG1_HWSEMAPHORE(n) (0x400 + 4 * (n))
207#define S6_GREG1_HWSEMAPHORE_NB 16
208
209/* peripheral interrupt numbers */
210
211#define S6_INTC_GPIO(n) (n) /* 0..3 */
212#define S6_INTC_I2C 4
213#define S6_INTC_SPI 5
214#define S6_INTC_NB_ERR 6
215#define S6_INTC_DMA_LMSERR 7
216#define S6_INTC_DMA_LMSLOWWMRK(n) (8 + (n)) /* 0..11 */
217#define S6_INTC_DMA_LMSPENDCNT(n) (20 + (n)) /* 0..11 */
218#define S6_INTC_DMA HOSTLOWWMRK(n) (32 + (n)) /* 0..6 */
219#define S6_INTC_DMA_HOSTPENDCNT(n) (39 + (n)) /* 0..6 */
220#define S6_INTC_DMA_HOSTERR 46
221#define S6_INTC_UART(n) (47 + (n)) /* 0..1 */
222#define S6_INTC_XAD 49
223#define S6_INTC_NI_ERR 50
224#define S6_INTC_NI_INFIFOFULL 51
225#define S6_INTC_DMA_NIERR 52
226#define S6_INTC_DMA_NILOWWMRK(n) (53 + (n)) /* 0..3 */
227#define S6_INTC_DMA_NIPENDCNT(n) (57 + (n)) /* 0..3 */
228#define S6_INTC_DDR 61
229#define S6_INTC_NS_ERR 62
230#define S6_INTC_EFI_CFGERR 63
231#define S6_INTC_EFI_ISEFTEST 64
232#define S6_INTC_EFI_WRITEERR 65
233#define S6_INTC_NMI_TIMER 66
234#define S6_INTC_PLLLOCK_SYS 67
235#define S6_INTC_PLLLOCK_IO 68
236#define S6_INTC_PLLLOCK_AIM 69
237#define S6_INTC_PLLLOCK_DP0 70
238#define S6_INTC_PLLLOCK_DP2 71
239#define S6_INTC_I2S_ERR 72
240#define S6_INTC_GMAC_STAT 73
241#define S6_INTC_GMAC_ERR 74
242#define S6_INTC_GIB_ERR 75
243#define S6_INTC_PCIE_ERR 76
244#define S6_INTC_PCIE_MSI(n) (77 + (n)) /* 0..3 */
245#define S6_INTC_PCIE_INTA 81
246#define S6_INTC_PCIE_INTB 82
247#define S6_INTC_PCIE_INTC 83
248#define S6_INTC_PCIE_INTD 84
249#define S6_INTC_SW(n) (85 + (n)) /* 0..9 */
250#define S6_INTC_SW_ENABLE(n) (85 + 256 + (n))
251#define S6_INTC_DMA_DP_ERR 95
252#define S6_INTC_DMA_DPLOWWMRK(n) (96 + (n)) /* 0..3 */
253#define S6_INTC_DMA_DPPENDCNT(n) (100 + (n)) /* 0..3 */
254#define S6_INTC_DMA_DPTERMCNT(n) (104 + (n)) /* 0..3 */
255#define S6_INTC_TIMER0 108
256#define S6_INTC_TIMER1 109
257#define S6_INTC_DMA_HOSTTERMCNT(n) (110 + (n)) /* 0..6 */
258
259#endif /* __XTENSA_S6000_HARDWARE_H */
diff --git a/arch/xtensa/variants/s6000/include/variant/irq.h b/arch/xtensa/variants/s6000/include/variant/irq.h
deleted file mode 100644
index 39ca751a6255..000000000000
--- a/arch/xtensa/variants/s6000/include/variant/irq.h
+++ /dev/null
@@ -1,8 +0,0 @@
1#ifndef _XTENSA_S6000_IRQ_H
2#define _XTENSA_S6000_IRQ_H
3
4#define VARIANT_NR_IRQS 8 /* GPIO interrupts */
5
6extern void variant_irq_enable(unsigned int irq);
7
8#endif /* __XTENSA_S6000_IRQ_H */
diff --git a/arch/xtensa/variants/s6000/include/variant/tie-asm.h b/arch/xtensa/variants/s6000/include/variant/tie-asm.h
deleted file mode 100644
index f02d0a3a2e20..000000000000
--- a/arch/xtensa/variants/s6000/include/variant/tie-asm.h
+++ /dev/null
@@ -1,304 +0,0 @@
1/*
2 * This header file contains assembly-language definitions (assembly
3 * macros, etc.) for this specific Xtensa processor's TIE extensions
4 * and options. It is customized to this Xtensa processor configuration.
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 *
10 * Copyright (C) 1999-2008 Tensilica Inc.
11 */
12
13#ifndef _XTENSA_CORE_TIE_ASM_H
14#define _XTENSA_CORE_TIE_ASM_H
15
16/* Selection parameter values for save-area save/restore macros: */
17/* Option vs. TIE: */
18#define XTHAL_SAS_TIE 0x0001 /* custom extension or coprocessor */
19#define XTHAL_SAS_OPT 0x0002 /* optional (and not a coprocessor) */
20/* Whether used automatically by compiler: */
21#define XTHAL_SAS_NOCC 0x0004 /* not used by compiler w/o special opts/code */
22#define XTHAL_SAS_CC 0x0008 /* used by compiler without special opts/code */
23/* ABI handling across function calls: */
24#define XTHAL_SAS_CALR 0x0010 /* caller-saved */
25#define XTHAL_SAS_CALE 0x0020 /* callee-saved */
26#define XTHAL_SAS_GLOB 0x0040 /* global across function calls (in thread) */
27/* Misc */
28#define XTHAL_SAS_ALL 0xFFFF /* include all default NCP contents */
29
30
31
32/* Macro to save all non-coprocessor (extra) custom TIE and optional state
33 * (not including zero-overhead loop registers).
34 * Save area ptr (clobbered): ptr (16 byte aligned)
35 * Scratch regs (clobbered): at1..at4 (only first XCHAL_NCP_NUM_ATMPS needed)
36 */
37 .macro xchal_ncp_store ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL
38 xchal_sa_start \continue, \ofs
39 .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~\select
40 xchal_sa_align \ptr, 0, 1024-4, 4, 4
41 rsr \at1, BR // boolean option
42 s32i \at1, \ptr, .Lxchal_ofs_ + 0
43 .set .Lxchal_ofs_, .Lxchal_ofs_ + 4
44 .endif
45 .endm // xchal_ncp_store
46
47/* Macro to save all non-coprocessor (extra) custom TIE and optional state
48 * (not including zero-overhead loop registers).
49 * Save area ptr (clobbered): ptr (16 byte aligned)
50 * Scratch regs (clobbered): at1..at4 (only first XCHAL_NCP_NUM_ATMPS needed)
51 */
52 .macro xchal_ncp_load ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL
53 xchal_sa_start \continue, \ofs
54 .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~\select
55 xchal_sa_align \ptr, 0, 1024-4, 4, 4
56 l32i \at1, \ptr, .Lxchal_ofs_ + 0
57 wsr \at1, BR // boolean option
58 .set .Lxchal_ofs_, .Lxchal_ofs_ + 4
59 .endif
60 .endm // xchal_ncp_load
61
62
63
64#define XCHAL_NCP_NUM_ATMPS 1
65
66
67
68/* Macro to save the state of TIE coprocessor FPU.
69 * Save area ptr (clobbered): ptr (16 byte aligned)
70 * Scratch regs (clobbered): at1..at4 (only first XCHAL_CP0_NUM_ATMPS needed)
71 */
72#define xchal_cp_FPU_store xchal_cp0_store
73/* #define xchal_cp_FPU_store_a2 xchal_cp0_store a2 a3 a4 a5 a6 */
74 .macro xchal_cp0_store ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL
75 xchal_sa_start \continue, \ofs
76 .ifeq (XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~\select
77 xchal_sa_align \ptr, 0, 0, 1, 16
78 rur232 \at1 // FCR
79 s32i \at1, \ptr, 0
80 rur233 \at1 // FSR
81 s32i \at1, \ptr, 4
82 SSI f0, \ptr, 8
83 SSI f1, \ptr, 12
84 SSI f2, \ptr, 16
85 SSI f3, \ptr, 20
86 SSI f4, \ptr, 24
87 SSI f5, \ptr, 28
88 SSI f6, \ptr, 32
89 SSI f7, \ptr, 36
90 SSI f8, \ptr, 40
91 SSI f9, \ptr, 44
92 SSI f10, \ptr, 48
93 SSI f11, \ptr, 52
94 SSI f12, \ptr, 56
95 SSI f13, \ptr, 60
96 SSI f14, \ptr, 64
97 SSI f15, \ptr, 68
98 .set .Lxchal_ofs_, .Lxchal_ofs_ + 72
99 .endif
100 .endm // xchal_cp0_store
101
102/* Macro to restore the state of TIE coprocessor FPU.
103 * Save area ptr (clobbered): ptr (16 byte aligned)
104 * Scratch regs (clobbered): at1..at4 (only first XCHAL_CP0_NUM_ATMPS needed)
105 */
106#define xchal_cp_FPU_load xchal_cp0_load
107/* #define xchal_cp_FPU_load_a2 xchal_cp0_load a2 a3 a4 a5 a6 */
108 .macro xchal_cp0_load ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL
109 xchal_sa_start \continue, \ofs
110 .ifeq (XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~\select
111 xchal_sa_align \ptr, 0, 0, 1, 16
112 l32i \at1, \ptr, 0
113 wur232 \at1 // FCR
114 l32i \at1, \ptr, 4
115 wur233 \at1 // FSR
116 LSI f0, \ptr, 8
117 LSI f1, \ptr, 12
118 LSI f2, \ptr, 16
119 LSI f3, \ptr, 20
120 LSI f4, \ptr, 24
121 LSI f5, \ptr, 28
122 LSI f6, \ptr, 32
123 LSI f7, \ptr, 36
124 LSI f8, \ptr, 40
125 LSI f9, \ptr, 44
126 LSI f10, \ptr, 48
127 LSI f11, \ptr, 52
128 LSI f12, \ptr, 56
129 LSI f13, \ptr, 60
130 LSI f14, \ptr, 64
131 LSI f15, \ptr, 68
132 .set .Lxchal_ofs_, .Lxchal_ofs_ + 72
133 .endif
134 .endm // xchal_cp0_load
135
136#define XCHAL_CP0_NUM_ATMPS 1
137
138/* Macro to save the state of TIE coprocessor XAD.
139 * Save area ptr (clobbered): ptr (16 byte aligned)
140 * Scratch regs (clobbered): at1..at4 (only first XCHAL_CP6_NUM_ATMPS needed)
141 */
142#define xchal_cp_XAD_store xchal_cp6_store
143/* #define xchal_cp_XAD_store_a2 xchal_cp6_store a2 a3 a4 a5 a6 */
144 .macro xchal_cp6_store ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL
145 xchal_sa_start \continue, \ofs
146 .ifeq (XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~\select
147 xchal_sa_align \ptr, 0, 0, 1, 16
148 rur0 \at1 // LDCBHI
149 s32i \at1, \ptr, 0
150 rur1 \at1 // LDCBLO
151 s32i \at1, \ptr, 4
152 rur2 \at1 // STCBHI
153 s32i \at1, \ptr, 8
154 rur3 \at1 // STCBLO
155 s32i \at1, \ptr, 12
156 rur8 \at1 // LDBRBASE
157 s32i \at1, \ptr, 16
158 rur9 \at1 // LDBROFF
159 s32i \at1, \ptr, 20
160 rur10 \at1 // LDBRINC
161 s32i \at1, \ptr, 24
162 rur11 \at1 // STBRBASE
163 s32i \at1, \ptr, 28
164 rur12 \at1 // STBROFF
165 s32i \at1, \ptr, 32
166 rur13 \at1 // STBRINC
167 s32i \at1, \ptr, 36
168 rur24 \at1 // SCRATCH0
169 s32i \at1, \ptr, 40
170 rur25 \at1 // SCRATCH1
171 s32i \at1, \ptr, 44
172 rur26 \at1 // SCRATCH2
173 s32i \at1, \ptr, 48
174 rur27 \at1 // SCRATCH3
175 s32i \at1, \ptr, 52
176 WRAS128I wra0, \ptr, 64
177 WRAS128I wra1, \ptr, 80
178 WRAS128I wra2, \ptr, 96
179 WRAS128I wra3, \ptr, 112
180 WRAS128I wra4, \ptr, 128
181 WRAS128I wra5, \ptr, 144
182 WRAS128I wra6, \ptr, 160
183 WRAS128I wra7, \ptr, 176
184 WRAS128I wra8, \ptr, 192
185 WRAS128I wra9, \ptr, 208
186 WRAS128I wra10, \ptr, 224
187 WRAS128I wra11, \ptr, 240
188 WRAS128I wra12, \ptr, 256
189 WRAS128I wra13, \ptr, 272
190 WRAS128I wra14, \ptr, 288
191 WRAS128I wra15, \ptr, 304
192 WRBS128I wrb0, \ptr, 320
193 WRBS128I wrb1, \ptr, 336
194 WRBS128I wrb2, \ptr, 352
195 WRBS128I wrb3, \ptr, 368
196 WRBS128I wrb4, \ptr, 384
197 WRBS128I wrb5, \ptr, 400
198 WRBS128I wrb6, \ptr, 416
199 WRBS128I wrb7, \ptr, 432
200 WRBS128I wrb8, \ptr, 448
201 WRBS128I wrb9, \ptr, 464
202 WRBS128I wrb10, \ptr, 480
203 WRBS128I wrb11, \ptr, 496
204 WRBS128I wrb12, \ptr, 512
205 WRBS128I wrb13, \ptr, 528
206 WRBS128I wrb14, \ptr, 544
207 WRBS128I wrb15, \ptr, 560
208 .set .Lxchal_ofs_, .Lxchal_ofs_ + 576
209 .endif
210 .endm // xchal_cp6_store
211
212/* Macro to restore the state of TIE coprocessor XAD.
213 * Save area ptr (clobbered): ptr (16 byte aligned)
214 * Scratch regs (clobbered): at1..at4 (only first XCHAL_CP6_NUM_ATMPS needed)
215 */
216#define xchal_cp_XAD_load xchal_cp6_load
217/* #define xchal_cp_XAD_load_a2 xchal_cp6_load a2 a3 a4 a5 a6 */
218 .macro xchal_cp6_load ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL
219 xchal_sa_start \continue, \ofs
220 .ifeq (XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~\select
221 xchal_sa_align \ptr, 0, 0, 1, 16
222 l32i \at1, \ptr, 0
223 wur0 \at1 // LDCBHI
224 l32i \at1, \ptr, 4
225 wur1 \at1 // LDCBLO
226 l32i \at1, \ptr, 8
227 wur2 \at1 // STCBHI
228 l32i \at1, \ptr, 12
229 wur3 \at1 // STCBLO
230 l32i \at1, \ptr, 16
231 wur8 \at1 // LDBRBASE
232 l32i \at1, \ptr, 20
233 wur9 \at1 // LDBROFF
234 l32i \at1, \ptr, 24
235 wur10 \at1 // LDBRINC
236 l32i \at1, \ptr, 28
237 wur11 \at1 // STBRBASE
238 l32i \at1, \ptr, 32
239 wur12 \at1 // STBROFF
240 l32i \at1, \ptr, 36
241 wur13 \at1 // STBRINC
242 l32i \at1, \ptr, 40
243 wur24 \at1 // SCRATCH0
244 l32i \at1, \ptr, 44
245 wur25 \at1 // SCRATCH1
246 l32i \at1, \ptr, 48
247 wur26 \at1 // SCRATCH2
248 l32i \at1, \ptr, 52
249 wur27 \at1 // SCRATCH3
250 WRBL128I wrb0, \ptr, 320
251 WRBL128I wrb1, \ptr, 336
252 WRBL128I wrb2, \ptr, 352
253 WRBL128I wrb3, \ptr, 368
254 WRBL128I wrb4, \ptr, 384
255 WRBL128I wrb5, \ptr, 400
256 WRBL128I wrb6, \ptr, 416
257 WRBL128I wrb7, \ptr, 432
258 WRBL128I wrb8, \ptr, 448
259 WRBL128I wrb9, \ptr, 464
260 WRBL128I wrb10, \ptr, 480
261 WRBL128I wrb11, \ptr, 496
262 WRBL128I wrb12, \ptr, 512
263 WRBL128I wrb13, \ptr, 528
264 WRBL128I wrb14, \ptr, 544
265 WRBL128I wrb15, \ptr, 560
266 WRAL128I wra0, \ptr, 64
267 WRAL128I wra1, \ptr, 80
268 WRAL128I wra2, \ptr, 96
269 WRAL128I wra3, \ptr, 112
270 WRAL128I wra4, \ptr, 128
271 WRAL128I wra5, \ptr, 144
272 WRAL128I wra6, \ptr, 160
273 WRAL128I wra7, \ptr, 176
274 WRAL128I wra8, \ptr, 192
275 WRAL128I wra9, \ptr, 208
276 WRAL128I wra10, \ptr, 224
277 WRAL128I wra11, \ptr, 240
278 WRAL128I wra12, \ptr, 256
279 WRAL128I wra13, \ptr, 272
280 WRAL128I wra14, \ptr, 288
281 WRAL128I wra15, \ptr, 304
282 .set .Lxchal_ofs_, .Lxchal_ofs_ + 576
283 .endif
284 .endm // xchal_cp6_load
285
286#define XCHAL_CP6_NUM_ATMPS 1
287#define XCHAL_SA_NUM_ATMPS 1
288
289 /* Empty macros for unconfigured coprocessors: */
290 .macro xchal_cp1_store p a b c d continue=0 ofs=-1 select=-1 ; .endm
291 .macro xchal_cp1_load p a b c d continue=0 ofs=-1 select=-1 ; .endm
292 .macro xchal_cp2_store p a b c d continue=0 ofs=-1 select=-1 ; .endm
293 .macro xchal_cp2_load p a b c d continue=0 ofs=-1 select=-1 ; .endm
294 .macro xchal_cp3_store p a b c d continue=0 ofs=-1 select=-1 ; .endm
295 .macro xchal_cp3_load p a b c d continue=0 ofs=-1 select=-1 ; .endm
296 .macro xchal_cp4_store p a b c d continue=0 ofs=-1 select=-1 ; .endm
297 .macro xchal_cp4_load p a b c d continue=0 ofs=-1 select=-1 ; .endm
298 .macro xchal_cp5_store p a b c d continue=0 ofs=-1 select=-1 ; .endm
299 .macro xchal_cp5_load p a b c d continue=0 ofs=-1 select=-1 ; .endm
300 .macro xchal_cp7_store p a b c d continue=0 ofs=-1 select=-1 ; .endm
301 .macro xchal_cp7_load p a b c d continue=0 ofs=-1 select=-1 ; .endm
302
303#endif /*_XTENSA_CORE_TIE_ASM_H*/
304
diff --git a/arch/xtensa/variants/s6000/include/variant/tie.h b/arch/xtensa/variants/s6000/include/variant/tie.h
deleted file mode 100644
index be7ea843d5df..000000000000
--- a/arch/xtensa/variants/s6000/include/variant/tie.h
+++ /dev/null
@@ -1,191 +0,0 @@
1/*
2 * This header file describes this specific Xtensa processor's TIE extensions
3 * that extend basic Xtensa core functionality. It is customized to this
4 * Xtensa processor configuration.
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 *
10 * Copyright (C) 1999-2008 Tensilica Inc.
11 */
12
13#ifndef _XTENSA_CORE_TIE_H
14#define _XTENSA_CORE_TIE_H
15
16#define XCHAL_CP_NUM 2 /* number of coprocessors */
17#define XCHAL_CP_MAX 7 /* max CP ID + 1 (0 if none) */
18#define XCHAL_CP_MASK 0x41 /* bitmask of all CPs by ID */
19#define XCHAL_CP_PORT_MASK 0x00 /* bitmask of only port CPs */
20
21/* Basic parameters of each coprocessor: */
22#define XCHAL_CP0_NAME "FPU"
23#define XCHAL_CP0_IDENT FPU
24#define XCHAL_CP0_SA_SIZE 72 /* size of state save area */
25#define XCHAL_CP0_SA_ALIGN 4 /* min alignment of save area */
26#define XCHAL_CP_ID_FPU 0 /* coprocessor ID (0..7) */
27#define XCHAL_CP6_NAME "XAD"
28#define XCHAL_CP6_IDENT XAD
29#define XCHAL_CP6_SA_SIZE 576 /* size of state save area */
30#define XCHAL_CP6_SA_ALIGN 16 /* min alignment of save area */
31#define XCHAL_CP_ID_XAD 6 /* coprocessor ID (0..7) */
32
33/* Filler info for unassigned coprocessors, to simplify arrays etc: */
34#define XCHAL_CP1_SA_SIZE 0
35#define XCHAL_CP1_SA_ALIGN 1
36#define XCHAL_CP2_SA_SIZE 0
37#define XCHAL_CP2_SA_ALIGN 1
38#define XCHAL_CP3_SA_SIZE 0
39#define XCHAL_CP3_SA_ALIGN 1
40#define XCHAL_CP4_SA_SIZE 0
41#define XCHAL_CP4_SA_ALIGN 1
42#define XCHAL_CP5_SA_SIZE 0
43#define XCHAL_CP5_SA_ALIGN 1
44#define XCHAL_CP7_SA_SIZE 0
45#define XCHAL_CP7_SA_ALIGN 1
46
47/* Save area for non-coprocessor optional and custom (TIE) state: */
48#define XCHAL_NCP_SA_SIZE 4
49#define XCHAL_NCP_SA_ALIGN 4
50
51/* Total save area for optional and custom state (NCP + CPn): */
52#define XCHAL_TOTAL_SA_SIZE 672 /* with 16-byte align padding */
53#define XCHAL_TOTAL_SA_ALIGN 16 /* actual minimum alignment */
54
55/*
56 * Detailed contents of save areas.
57 * NOTE: caller must define the XCHAL_SA_REG macro (not defined here)
58 * before expanding the XCHAL_xxx_SA_LIST() macros.
59 *
60 * XCHAL_SA_REG(s,ccused,abikind,kind,opt,name,galign,align,asize,
61 * dbnum,base,regnum,bitsz,gapsz,reset,x...)
62 *
63 * s = passed from XCHAL_*_LIST(s), eg. to select how to expand
64 * ccused = set if used by compiler without special options or code
65 * abikind = 0 (caller-saved), 1 (callee-saved), or 2 (thread-global)
66 * kind = 0 (special reg), 1 (TIE user reg), or 2 (TIE regfile reg)
67 * opt = 0 (custom TIE extension or coprocessor), or 1 (optional reg)
68 * name = lowercase reg name (no quotes)
69 * galign = group byte alignment (power of 2) (galign >= align)
70 * align = register byte alignment (power of 2)
71 * asize = allocated size in bytes (asize*8 == bitsz + gapsz + padsz)
72 * (not including any pad bytes required to galign this or next reg)
73 * dbnum = unique target number f/debug (see <xtensa-libdb-macros.h>)
74 * base = reg shortname w/o index (or sr=special, ur=TIE user reg)
75 * regnum = reg index in regfile, or special/TIE-user reg number
76 * bitsz = number of significant bits (regfile width, or ur/sr mask bits)
77 * gapsz = intervening bits, if bitsz bits not stored contiguously
78 * (padsz = pad bits at end [TIE regfile] or at msbits [ur,sr] of asize)
79 * reset = register reset value (or 0 if undefined at reset)
80 * x = reserved for future use (0 until then)
81 *
82 * To filter out certain registers, e.g. to expand only the non-global
83 * registers used by the compiler, you can do something like this:
84 *
85 * #define XCHAL_SA_REG(s,ccused,p...) SELCC##ccused(p)
86 * #define SELCC0(p...)
87 * #define SELCC1(abikind,p...) SELAK##abikind(p)
88 * #define SELAK0(p...) REG(p)
89 * #define SELAK1(p...) REG(p)
90 * #define SELAK2(p...)
91 * #define REG(kind,tie,name,galn,aln,asz,csz,dbnum,base,rnum,bsz,rst,x...) \
92 * ...what you want to expand...
93 */
94
95#define XCHAL_NCP_SA_NUM 1
96#define XCHAL_NCP_SA_LIST(s) \
97 XCHAL_SA_REG(s,0,0,0,1, br, 4, 4, 4,0x0204, sr,4 , 16,0,0,0)
98
99#define XCHAL_CP0_SA_NUM 18
100#define XCHAL_CP0_SA_LIST(s) \
101 XCHAL_SA_REG(s,0,0,1,0, fcr, 4, 4, 4,0x03E8, ur,232, 32,0,0,0) \
102 XCHAL_SA_REG(s,0,0,1,0, fsr, 4, 4, 4,0x03E9, ur,233, 32,0,0,0) \
103 XCHAL_SA_REG(s,0,0,2,0, f0, 4, 4, 4,0x0030, f,0 , 32,0,0,0) \
104 XCHAL_SA_REG(s,0,0,2,0, f1, 4, 4, 4,0x0031, f,1 , 32,0,0,0) \
105 XCHAL_SA_REG(s,0,0,2,0, f2, 4, 4, 4,0x0032, f,2 , 32,0,0,0) \
106 XCHAL_SA_REG(s,0,0,2,0, f3, 4, 4, 4,0x0033, f,3 , 32,0,0,0) \
107 XCHAL_SA_REG(s,0,0,2,0, f4, 4, 4, 4,0x0034, f,4 , 32,0,0,0) \
108 XCHAL_SA_REG(s,0,0,2,0, f5, 4, 4, 4,0x0035, f,5 , 32,0,0,0) \
109 XCHAL_SA_REG(s,0,0,2,0, f6, 4, 4, 4,0x0036, f,6 , 32,0,0,0) \
110 XCHAL_SA_REG(s,0,0,2,0, f7, 4, 4, 4,0x0037, f,7 , 32,0,0,0) \
111 XCHAL_SA_REG(s,0,0,2,0, f8, 4, 4, 4,0x0038, f,8 , 32,0,0,0) \
112 XCHAL_SA_REG(s,0,0,2,0, f9, 4, 4, 4,0x0039, f,9 , 32,0,0,0) \
113 XCHAL_SA_REG(s,0,0,2,0, f10, 4, 4, 4,0x003A, f,10 , 32,0,0,0) \
114 XCHAL_SA_REG(s,0,0,2,0, f11, 4, 4, 4,0x003B, f,11 , 32,0,0,0) \
115 XCHAL_SA_REG(s,0,0,2,0, f12, 4, 4, 4,0x003C, f,12 , 32,0,0,0) \
116 XCHAL_SA_REG(s,0,0,2,0, f13, 4, 4, 4,0x003D, f,13 , 32,0,0,0) \
117 XCHAL_SA_REG(s,0,0,2,0, f14, 4, 4, 4,0x003E, f,14 , 32,0,0,0) \
118 XCHAL_SA_REG(s,0,0,2,0, f15, 4, 4, 4,0x003F, f,15 , 32,0,0,0)
119
120#define XCHAL_CP1_SA_NUM 0
121#define XCHAL_CP1_SA_LIST(s) /* empty */
122
123#define XCHAL_CP2_SA_NUM 0
124#define XCHAL_CP2_SA_LIST(s) /* empty */
125
126#define XCHAL_CP3_SA_NUM 0
127#define XCHAL_CP3_SA_LIST(s) /* empty */
128
129#define XCHAL_CP4_SA_NUM 0
130#define XCHAL_CP4_SA_LIST(s) /* empty */
131
132#define XCHAL_CP5_SA_NUM 0
133#define XCHAL_CP5_SA_LIST(s) /* empty */
134
135#define XCHAL_CP6_SA_NUM 46
136#define XCHAL_CP6_SA_LIST(s) \
137 XCHAL_SA_REG(s,0,0,1,0, ldcbhi,16, 4, 4,0x0300, ur,0 , 32,0,0,0) \
138 XCHAL_SA_REG(s,0,0,1,0, ldcblo, 4, 4, 4,0x0301, ur,1 , 32,0,0,0) \
139 XCHAL_SA_REG(s,0,0,1,0, stcbhi, 4, 4, 4,0x0302, ur,2 , 32,0,0,0) \
140 XCHAL_SA_REG(s,0,0,1,0, stcblo, 4, 4, 4,0x0303, ur,3 , 32,0,0,0) \
141 XCHAL_SA_REG(s,0,0,1,0, ldbrbase, 4, 4, 4,0x0308, ur,8 , 32,0,0,0) \
142 XCHAL_SA_REG(s,0,0,1,0, ldbroff, 4, 4, 4,0x0309, ur,9 , 32,0,0,0) \
143 XCHAL_SA_REG(s,0,0,1,0, ldbrinc, 4, 4, 4,0x030A, ur,10 , 32,0,0,0) \
144 XCHAL_SA_REG(s,0,0,1,0, stbrbase, 4, 4, 4,0x030B, ur,11 , 32,0,0,0) \
145 XCHAL_SA_REG(s,0,0,1,0, stbroff, 4, 4, 4,0x030C, ur,12 , 32,0,0,0) \
146 XCHAL_SA_REG(s,0,0,1,0, stbrinc, 4, 4, 4,0x030D, ur,13 , 32,0,0,0) \
147 XCHAL_SA_REG(s,0,0,1,0, scratch0, 4, 4, 4,0x0318, ur,24 , 32,0,0,0) \
148 XCHAL_SA_REG(s,0,0,1,0, scratch1, 4, 4, 4,0x0319, ur,25 , 32,0,0,0) \
149 XCHAL_SA_REG(s,0,0,1,0, scratch2, 4, 4, 4,0x031A, ur,26 , 32,0,0,0) \
150 XCHAL_SA_REG(s,0,0,1,0, scratch3, 4, 4, 4,0x031B, ur,27 , 32,0,0,0) \
151 XCHAL_SA_REG(s,0,0,2,0, wra0,16,16,16,0x1010, wra,0 ,128,0,0,0) \
152 XCHAL_SA_REG(s,0,0,2,0, wra1,16,16,16,0x1011, wra,1 ,128,0,0,0) \
153 XCHAL_SA_REG(s,0,0,2,0, wra2,16,16,16,0x1012, wra,2 ,128,0,0,0) \
154 XCHAL_SA_REG(s,0,0,2,0, wra3,16,16,16,0x1013, wra,3 ,128,0,0,0) \
155 XCHAL_SA_REG(s,0,0,2,0, wra4,16,16,16,0x1014, wra,4 ,128,0,0,0) \
156 XCHAL_SA_REG(s,0,0,2,0, wra5,16,16,16,0x1015, wra,5 ,128,0,0,0) \
157 XCHAL_SA_REG(s,0,0,2,0, wra6,16,16,16,0x1016, wra,6 ,128,0,0,0) \
158 XCHAL_SA_REG(s,0,0,2,0, wra7,16,16,16,0x1017, wra,7 ,128,0,0,0) \
159 XCHAL_SA_REG(s,0,0,2,0, wra8,16,16,16,0x1018, wra,8 ,128,0,0,0) \
160 XCHAL_SA_REG(s,0,0,2,0, wra9,16,16,16,0x1019, wra,9 ,128,0,0,0) \
161 XCHAL_SA_REG(s,0,0,2,0, wra10,16,16,16,0x101A, wra,10 ,128,0,0,0) \
162 XCHAL_SA_REG(s,0,0,2,0, wra11,16,16,16,0x101B, wra,11 ,128,0,0,0) \
163 XCHAL_SA_REG(s,0,0,2,0, wra12,16,16,16,0x101C, wra,12 ,128,0,0,0) \
164 XCHAL_SA_REG(s,0,0,2,0, wra13,16,16,16,0x101D, wra,13 ,128,0,0,0) \
165 XCHAL_SA_REG(s,0,0,2,0, wra14,16,16,16,0x101E, wra,14 ,128,0,0,0) \
166 XCHAL_SA_REG(s,0,0,2,0, wra15,16,16,16,0x101F, wra,15 ,128,0,0,0) \
167 XCHAL_SA_REG(s,0,0,2,0, wrb0,16,16,16,0x1020, wrb,0 ,128,0,0,0) \
168 XCHAL_SA_REG(s,0,0,2,0, wrb1,16,16,16,0x1021, wrb,1 ,128,0,0,0) \
169 XCHAL_SA_REG(s,0,0,2,0, wrb2,16,16,16,0x1022, wrb,2 ,128,0,0,0) \
170 XCHAL_SA_REG(s,0,0,2,0, wrb3,16,16,16,0x1023, wrb,3 ,128,0,0,0) \
171 XCHAL_SA_REG(s,0,0,2,0, wrb4,16,16,16,0x1024, wrb,4 ,128,0,0,0) \
172 XCHAL_SA_REG(s,0,0,2,0, wrb5,16,16,16,0x1025, wrb,5 ,128,0,0,0) \
173 XCHAL_SA_REG(s,0,0,2,0, wrb6,16,16,16,0x1026, wrb,6 ,128,0,0,0) \
174 XCHAL_SA_REG(s,0,0,2,0, wrb7,16,16,16,0x1027, wrb,7 ,128,0,0,0) \
175 XCHAL_SA_REG(s,0,0,2,0, wrb8,16,16,16,0x1028, wrb,8 ,128,0,0,0) \
176 XCHAL_SA_REG(s,0,0,2,0, wrb9,16,16,16,0x1029, wrb,9 ,128,0,0,0) \
177 XCHAL_SA_REG(s,0,0,2,0, wrb10,16,16,16,0x102A, wrb,10 ,128,0,0,0) \
178 XCHAL_SA_REG(s,0,0,2,0, wrb11,16,16,16,0x102B, wrb,11 ,128,0,0,0) \
179 XCHAL_SA_REG(s,0,0,2,0, wrb12,16,16,16,0x102C, wrb,12 ,128,0,0,0) \
180 XCHAL_SA_REG(s,0,0,2,0, wrb13,16,16,16,0x102D, wrb,13 ,128,0,0,0) \
181 XCHAL_SA_REG(s,0,0,2,0, wrb14,16,16,16,0x102E, wrb,14 ,128,0,0,0) \
182 XCHAL_SA_REG(s,0,0,2,0, wrb15,16,16,16,0x102F, wrb,15 ,128,0,0,0)
183
184#define XCHAL_CP7_SA_NUM 0
185#define XCHAL_CP7_SA_LIST(s) /* empty */
186
187/* Byte length of instruction from its first nibble (op0 field), per FLIX. */
188#define XCHAL_OP0_FORMAT_LENGTHS 3,3,3,3,3,3,3,3,2,2,2,2,2,2,8,8
189
190#endif /*_XTENSA_CORE_TIE_H*/
191
diff --git a/arch/xtensa/variants/s6000/irq.c b/arch/xtensa/variants/s6000/irq.c
deleted file mode 100644
index 81a241e79075..000000000000
--- a/arch/xtensa/variants/s6000/irq.c
+++ /dev/null
@@ -1,74 +0,0 @@
1/*
2 * s6000 irq crossbar
3 *
4 * Copyright (c) 2009 emlix GmbH
5 * Authors: Johannes Weiner <hannes@cmpxchg.org>
6 * Oskar Schirmer <oskar@scara.com>
7 */
8#include <linux/io.h>
9#include <asm/irq.h>
10#include <variant/hardware.h>
11
12/* S6_REG_INTC */
13#define INTC_STATUS 0x000
14#define INTC_RAW 0x010
15#define INTC_STATUS_AG 0x100
16#define INTC_CFG(n) (0x200 + 4 * (n))
17
18/*
19 * The s6000 has a crossbar that multiplexes interrupt output lines
20 * from the peripherals to input lines on the xtensa core.
21 *
22 * We leave the mapping decisions to the platform as it depends on the
23 * actually connected peripherals which distribution makes sense.
24 */
25extern const signed char *platform_irq_mappings[NR_IRQS];
26
27static unsigned long scp_to_intc_enable[] = {
28#define TO_INTC_ENABLE(n) (((n) << 1) + 1)
29 TO_INTC_ENABLE(0),
30 TO_INTC_ENABLE(1),
31 TO_INTC_ENABLE(2),
32 TO_INTC_ENABLE(3),
33 TO_INTC_ENABLE(4),
34 TO_INTC_ENABLE(5),
35 TO_INTC_ENABLE(6),
36 TO_INTC_ENABLE(7),
37 TO_INTC_ENABLE(8),
38 TO_INTC_ENABLE(9),
39 TO_INTC_ENABLE(10),
40 TO_INTC_ENABLE(11),
41 TO_INTC_ENABLE(12),
42 -1,
43 -1,
44 TO_INTC_ENABLE(13),
45 -1,
46 TO_INTC_ENABLE(14),
47 -1,
48 TO_INTC_ENABLE(15),
49#undef TO_INTC_ENABLE
50};
51
52static void irq_set(unsigned int irq, int enable)
53{
54 unsigned long en;
55 const signed char *m = platform_irq_mappings[irq];
56
57 if (!m)
58 return;
59 en = enable ? scp_to_intc_enable[irq] : 0;
60 while (*m >= 0) {
61 writel(en, S6_REG_INTC + INTC_CFG(*m));
62 m++;
63 }
64}
65
66void variant_irq_enable(unsigned int irq)
67{
68 irq_set(irq, 1);
69}
70
71void variant_irq_disable(unsigned int irq)
72{
73 irq_set(irq, 0);
74}
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-11 16:25:05 -0500