Merge branch 'master' into for-next

Conflicts:
	drivers/devfreq/exynos4_bus.c

Sync with Linus' tree to be able to apply patches that are
against newer code (mvneta).

1 files changed, 99 insertions, 33 deletions

diff --git a/arch/xtensa/kernel/irq.c b/arch/xtensa/kernel/irq.c
index a6ce3e563739..6f4f9749cff7 100644
--- a/arch/xtensa/kernel/irq.c
+++ b/arch/xtensa/kernel/irq.c
@@ -18,6 +18,8 @@
 #include <linux/interrupt.h>
 #include <linux/irq.h>
 #include <linux/kernel_stat.h>
+#include <linux/irqdomain.h>
+#include <linux/of.h>
 
 #include <asm/uaccess.h>
 #include <asm/platform.h>
@@ -26,19 +28,22 @@ static unsigned int cached_irq_mask;
 
 atomic_t irq_err_count;
 
+static struct irq_domain *root_domain;
+
 /*
  * do_IRQ handles all normal device IRQ's (the special
  * SMP cross-CPU interrupts have their own specific
  * handlers).
  */
 
-asmlinkage void do_IRQ(int irq, struct pt_regs *regs)
+asmlinkage void do_IRQ(int hwirq, struct pt_regs *regs)
 {
         struct pt_regs *old_regs = set_irq_regs(regs);
+        int irq = irq_find_mapping(root_domain, hwirq);
 
-        if (irq >= NR_IRQS) {
+        if (hwirq >= NR_IRQS) {
                 printk(KERN_EMERG "%s: cannot handle IRQ %d\n",
-                                __func__, irq);
+                                __func__, hwirq);
         }
 
         irq_enter();
@@ -71,40 +76,39 @@ int arch_show_interrupts(struct seq_file *p, int prec)
 
 static void xtensa_irq_mask(struct irq_data *d)
 {
-        cached_irq_mask &= ~(1 << d->irq);
+        cached_irq_mask &= ~(1 << d->hwirq);
         set_sr (cached_irq_mask, intenable);
 }
 
 static void xtensa_irq_unmask(struct irq_data *d)
 {
-        cached_irq_mask |= 1 << d->irq;
+        cached_irq_mask |= 1 << d->hwirq;
         set_sr (cached_irq_mask, intenable);
 }
 
 static void xtensa_irq_enable(struct irq_data *d)
 {
-        variant_irq_enable(d->irq);
+        variant_irq_enable(d->hwirq);
         xtensa_irq_unmask(d);
 }
 
 static void xtensa_irq_disable(struct irq_data *d)
 {
         xtensa_irq_mask(d);
-        variant_irq_disable(d->irq);
+        variant_irq_disable(d->hwirq);
 }
 
 static void xtensa_irq_ack(struct irq_data *d)
 {
-        set_sr(1 << d->irq, intclear);
+        set_sr(1 << d->hwirq, intclear);
 }
 
 static int xtensa_irq_retrigger(struct irq_data *d)
 {
-        set_sr (1 << d->irq, INTSET);
+        set_sr(1 << d->hwirq, intset);
         return 1;
 }
 
-
 static struct irq_chip xtensa_irq_chip = {
         .name           = "xtensa",
         .irq_enable     = xtensa_irq_enable,
@@ -115,37 +119,99 @@ static struct irq_chip xtensa_irq_chip = {
         .irq_retrigger  = xtensa_irq_retrigger,
 };
 
-void __init init_IRQ(void)
+static int xtensa_irq_map(struct irq_domain *d, unsigned int irq,
+                irq_hw_number_t hw)
 {
-        int index;
-
-        for (index = 0; index < XTENSA_NR_IRQS; index++) {
-                int mask = 1 << index;
-
-                if (mask & XCHAL_INTTYPE_MASK_SOFTWARE)
-                        irq_set_chip_and_handler(index, &xtensa_irq_chip,
-                                                 handle_simple_irq);
+        u32 mask = 1 << hw;
+
+        if (mask & XCHAL_INTTYPE_MASK_SOFTWARE) {
+                irq_set_chip_and_handler_name(irq, &xtensa_irq_chip,
+                                handle_simple_irq, "level");
+                irq_set_status_flags(irq, IRQ_LEVEL);
+        } else if (mask & XCHAL_INTTYPE_MASK_EXTERN_EDGE) {
+                irq_set_chip_and_handler_name(irq, &xtensa_irq_chip,
+                                handle_edge_irq, "edge");
+                irq_clear_status_flags(irq, IRQ_LEVEL);
+        } else if (mask & XCHAL_INTTYPE_MASK_EXTERN_LEVEL) {
+                irq_set_chip_and_handler_name(irq, &xtensa_irq_chip,
+                                handle_level_irq, "level");
+                irq_set_status_flags(irq, IRQ_LEVEL);
+        } else if (mask & XCHAL_INTTYPE_MASK_TIMER) {
+                irq_set_chip_and_handler_name(irq, &xtensa_irq_chip,
+                                handle_edge_irq, "edge");
+                irq_clear_status_flags(irq, IRQ_LEVEL);
+        } else {/* XCHAL_INTTYPE_MASK_WRITE_ERROR */
+                /* XCHAL_INTTYPE_MASK_NMI */
+
+                irq_set_chip_and_handler_name(irq, &xtensa_irq_chip,
+                                handle_level_irq, "level");
+                irq_set_status_flags(irq, IRQ_LEVEL);
+        }
+        return 0;
+}
 
-                else if (mask & XCHAL_INTTYPE_MASK_EXTERN_EDGE)
-                        irq_set_chip_and_handler(index, &xtensa_irq_chip,
-                                                 handle_edge_irq);
+static unsigned map_ext_irq(unsigned ext_irq)
+{
+        unsigned mask = XCHAL_INTTYPE_MASK_EXTERN_EDGE |
+                XCHAL_INTTYPE_MASK_EXTERN_LEVEL;
+        unsigned i;
 
-                else if (mask & XCHAL_INTTYPE_MASK_EXTERN_LEVEL)
-                        irq_set_chip_and_handler(index, &xtensa_irq_chip,
-                                                 handle_level_irq);
+        for (i = 0; mask; ++i, mask >>= 1) {
+                if ((mask & 1) && ext_irq-- == 0)
+                        return i;
+        }
+        return XCHAL_NUM_INTERRUPTS;
+}
 
-                else if (mask & XCHAL_INTTYPE_MASK_TIMER)
-                        irq_set_chip_and_handler(index, &xtensa_irq_chip,
-                                                 handle_edge_irq);
+/*
+ * Device Tree IRQ specifier translation function which works with one or
+ * two cell bindings. First cell value maps directly to the hwirq number.
+ * Second cell if present specifies whether hwirq number is external (1) or
+ * internal (0).
+ */
+int xtensa_irq_domain_xlate(struct irq_domain *d, struct device_node *ctrlr,
+                const u32 *intspec, unsigned int intsize,
+                unsigned long *out_hwirq, unsigned int *out_type)
+{
+        if (WARN_ON(intsize < 1 || intsize > 2))
+                return -EINVAL;
+        if (intsize == 2 && intspec[1] == 1) {
+                unsigned int_irq = map_ext_irq(intspec[0]);
+                if (int_irq < XCHAL_NUM_INTERRUPTS)
+                        *out_hwirq = int_irq;
+                else
+                        return -EINVAL;
+        } else {
+                *out_hwirq = intspec[0];
+        }
+        *out_type = IRQ_TYPE_NONE;
+        return 0;
+}
 
-                else    /* XCHAL_INTTYPE_MASK_WRITE_ERROR */
-                        /* XCHAL_INTTYPE_MASK_NMI */
+static const struct irq_domain_ops xtensa_irq_domain_ops = {
+        .xlate = xtensa_irq_domain_xlate,
+        .map = xtensa_irq_map,
+};
 
-                        irq_set_chip_and_handler(index, &xtensa_irq_chip,
-                                                 handle_level_irq);
-        }
+void __init init_IRQ(void)
+{
+        struct device_node *intc = NULL;
 
         cached_irq_mask = 0;
+        set_sr(~0, intclear);
+
+#ifdef CONFIG_OF
+        /* The interrupt controller device node is mandatory */
+        intc = of_find_compatible_node(NULL, NULL, "xtensa,pic");
+        BUG_ON(!intc);
+
+        root_domain = irq_domain_add_linear(intc, NR_IRQS,
+                        &xtensa_irq_domain_ops, NULL);
+#else
+        root_domain = irq_domain_add_legacy(intc, NR_IRQS, 0, 0,
+                        &xtensa_irq_domain_ops, NULL);
+#endif
+        irq_set_default_host(root_domain);
 
         variant_init_irq();
 }