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authorMax Filippov <jcmvbkbc@gmail.com>2012-10-14 19:55:38 -0400
committerChris Zankel <chris@zankel.net>2012-10-16 00:48:08 -0400
commitbc5378fcba974317f9657c4fdc78af227e1e1068 (patch)
tree998b8f8badf1d7a5dc0fd796f3e8501f8c5394ae /arch/xtensa/include
parentf4349b6e01c8927a04795885702a173b6a60573c (diff)
xtensa: reorganize SR referencing
- reference SRs by names where possible, not by numbers; - get rid of __stringify around SR names where possible; - remove unneeded SR names from asm/regs.h; - add SREG_ prefix to remaining SR names; Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Chris Zankel <chris@zankel.net>
Diffstat (limited to 'arch/xtensa/include')
-rw-r--r--arch/xtensa/include/asm/atomic.h12
-rw-r--r--arch/xtensa/include/asm/cacheflush.h2
-rw-r--r--arch/xtensa/include/asm/cmpxchg.h4
-rw-r--r--arch/xtensa/include/asm/coprocessor.h5
-rw-r--r--arch/xtensa/include/asm/delay.h2
-rw-r--r--arch/xtensa/include/asm/irqflags.h4
-rw-r--r--arch/xtensa/include/asm/mmu_context.h4
-rw-r--r--arch/xtensa/include/asm/regs.h55
-rw-r--r--arch/xtensa/include/asm/timex.h8
-rw-r--r--arch/xtensa/include/asm/tlbflush.h8
10 files changed, 33 insertions, 71 deletions
diff --git a/arch/xtensa/include/asm/atomic.h b/arch/xtensa/include/asm/atomic.h
index b40989308775..24f50cada70c 100644
--- a/arch/xtensa/include/asm/atomic.h
+++ b/arch/xtensa/include/asm/atomic.h
@@ -73,7 +73,7 @@ static inline void atomic_add(int i, atomic_t * v)
73 "l32i %0, %2, 0 \n\t" 73 "l32i %0, %2, 0 \n\t"
74 "add %0, %0, %1 \n\t" 74 "add %0, %0, %1 \n\t"
75 "s32i %0, %2, 0 \n\t" 75 "s32i %0, %2, 0 \n\t"
76 "wsr a15, "__stringify(PS)" \n\t" 76 "wsr a15, ps \n\t"
77 "rsync \n" 77 "rsync \n"
78 : "=&a" (vval) 78 : "=&a" (vval)
79 : "a" (i), "a" (v) 79 : "a" (i), "a" (v)
@@ -97,7 +97,7 @@ static inline void atomic_sub(int i, atomic_t *v)
97 "l32i %0, %2, 0 \n\t" 97 "l32i %0, %2, 0 \n\t"
98 "sub %0, %0, %1 \n\t" 98 "sub %0, %0, %1 \n\t"
99 "s32i %0, %2, 0 \n\t" 99 "s32i %0, %2, 0 \n\t"
100 "wsr a15, "__stringify(PS)" \n\t" 100 "wsr a15, ps \n\t"
101 "rsync \n" 101 "rsync \n"
102 : "=&a" (vval) 102 : "=&a" (vval)
103 : "a" (i), "a" (v) 103 : "a" (i), "a" (v)
@@ -118,7 +118,7 @@ static inline int atomic_add_return(int i, atomic_t * v)
118 "l32i %0, %2, 0 \n\t" 118 "l32i %0, %2, 0 \n\t"
119 "add %0, %0, %1 \n\t" 119 "add %0, %0, %1 \n\t"
120 "s32i %0, %2, 0 \n\t" 120 "s32i %0, %2, 0 \n\t"
121 "wsr a15, "__stringify(PS)" \n\t" 121 "wsr a15, ps \n\t"
122 "rsync \n" 122 "rsync \n"
123 : "=&a" (vval) 123 : "=&a" (vval)
124 : "a" (i), "a" (v) 124 : "a" (i), "a" (v)
@@ -137,7 +137,7 @@ static inline int atomic_sub_return(int i, atomic_t * v)
137 "l32i %0, %2, 0 \n\t" 137 "l32i %0, %2, 0 \n\t"
138 "sub %0, %0, %1 \n\t" 138 "sub %0, %0, %1 \n\t"
139 "s32i %0, %2, 0 \n\t" 139 "s32i %0, %2, 0 \n\t"
140 "wsr a15, "__stringify(PS)" \n\t" 140 "wsr a15, ps \n\t"
141 "rsync \n" 141 "rsync \n"
142 : "=&a" (vval) 142 : "=&a" (vval)
143 : "a" (i), "a" (v) 143 : "a" (i), "a" (v)
@@ -260,7 +260,7 @@ static inline void atomic_clear_mask(unsigned int mask, atomic_t *v)
260 "xor %1, %4, %3 \n\t" 260 "xor %1, %4, %3 \n\t"
261 "and %0, %0, %4 \n\t" 261 "and %0, %0, %4 \n\t"
262 "s32i %0, %2, 0 \n\t" 262 "s32i %0, %2, 0 \n\t"
263 "wsr a15, "__stringify(PS)" \n\t" 263 "wsr a15, ps \n\t"
264 "rsync \n" 264 "rsync \n"
265 : "=&a" (vval), "=a" (mask) 265 : "=&a" (vval), "=a" (mask)
266 : "a" (v), "a" (all_f), "1" (mask) 266 : "a" (v), "a" (all_f), "1" (mask)
@@ -277,7 +277,7 @@ static inline void atomic_set_mask(unsigned int mask, atomic_t *v)
277 "l32i %0, %2, 0 \n\t" 277 "l32i %0, %2, 0 \n\t"
278 "or %0, %0, %1 \n\t" 278 "or %0, %0, %1 \n\t"
279 "s32i %0, %2, 0 \n\t" 279 "s32i %0, %2, 0 \n\t"
280 "wsr a15, "__stringify(PS)" \n\t" 280 "wsr a15, ps \n\t"
281 "rsync \n" 281 "rsync \n"
282 : "=&a" (vval) 282 : "=&a" (vval)
283 : "a" (mask), "a" (v) 283 : "a" (mask), "a" (v)
diff --git a/arch/xtensa/include/asm/cacheflush.h b/arch/xtensa/include/asm/cacheflush.h
index 376cd9d5f455..569fec4f9a20 100644
--- a/arch/xtensa/include/asm/cacheflush.h
+++ b/arch/xtensa/include/asm/cacheflush.h
@@ -165,7 +165,7 @@ extern void copy_from_user_page(struct vm_area_struct*, struct page*,
165static inline u32 xtensa_get_cacheattr(void) 165static inline u32 xtensa_get_cacheattr(void)
166{ 166{
167 u32 r; 167 u32 r;
168 asm volatile(" rsr %0, CACHEATTR" : "=a"(r)); 168 asm volatile(" rsr %0, cacheattr" : "=a"(r));
169 return r; 169 return r;
170} 170}
171 171
diff --git a/arch/xtensa/include/asm/cmpxchg.h b/arch/xtensa/include/asm/cmpxchg.h
index e32149063d83..64dad04a9d27 100644
--- a/arch/xtensa/include/asm/cmpxchg.h
+++ b/arch/xtensa/include/asm/cmpxchg.h
@@ -27,7 +27,7 @@ __cmpxchg_u32(volatile int *p, int old, int new)
27 "bne %0, %2, 1f \n\t" 27 "bne %0, %2, 1f \n\t"
28 "s32i %3, %1, 0 \n\t" 28 "s32i %3, %1, 0 \n\t"
29 "1: \n\t" 29 "1: \n\t"
30 "wsr a15, "__stringify(PS)" \n\t" 30 "wsr a15, ps \n\t"
31 "rsync \n\t" 31 "rsync \n\t"
32 : "=&a" (old) 32 : "=&a" (old)
33 : "a" (p), "a" (old), "r" (new) 33 : "a" (p), "a" (old), "r" (new)
@@ -97,7 +97,7 @@ static inline unsigned long xchg_u32(volatile int * m, unsigned long val)
97 __asm__ __volatile__("rsil a15, "__stringify(LOCKLEVEL)"\n\t" 97 __asm__ __volatile__("rsil a15, "__stringify(LOCKLEVEL)"\n\t"
98 "l32i %0, %1, 0 \n\t" 98 "l32i %0, %1, 0 \n\t"
99 "s32i %2, %1, 0 \n\t" 99 "s32i %2, %1, 0 \n\t"
100 "wsr a15, "__stringify(PS)" \n\t" 100 "wsr a15, ps \n\t"
101 "rsync \n\t" 101 "rsync \n\t"
102 : "=&a" (tmp) 102 : "=&a" (tmp)
103 : "a" (m), "a" (val) 103 : "a" (m), "a" (val)
diff --git a/arch/xtensa/include/asm/coprocessor.h b/arch/xtensa/include/asm/coprocessor.h
index 75c94a1658b0..677501b32dfc 100644
--- a/arch/xtensa/include/asm/coprocessor.h
+++ b/arch/xtensa/include/asm/coprocessor.h
@@ -94,11 +94,10 @@
94#if XCHAL_HAVE_CP 94#if XCHAL_HAVE_CP
95 95
96#define RSR_CPENABLE(x) do { \ 96#define RSR_CPENABLE(x) do { \
97 __asm__ __volatile__("rsr %0," __stringify(CPENABLE) : "=a" (x)); \ 97 __asm__ __volatile__("rsr %0, cpenable" : "=a" (x)); \
98 } while(0); 98 } while(0);
99#define WSR_CPENABLE(x) do { \ 99#define WSR_CPENABLE(x) do { \
100 __asm__ __volatile__("wsr %0," __stringify(CPENABLE) "; rsync" \ 100 __asm__ __volatile__("wsr %0, cpenable; rsync" :: "a" (x)); \
101 :: "a" (x)); \
102 } while(0); 101 } while(0);
103 102
104#endif /* XCHAL_HAVE_CP */ 103#endif /* XCHAL_HAVE_CP */
diff --git a/arch/xtensa/include/asm/delay.h b/arch/xtensa/include/asm/delay.h
index e1d8c9e010c1..58c0a4fd4003 100644
--- a/arch/xtensa/include/asm/delay.h
+++ b/arch/xtensa/include/asm/delay.h
@@ -27,7 +27,7 @@ static inline void __delay(unsigned long loops)
27static __inline__ u32 xtensa_get_ccount(void) 27static __inline__ u32 xtensa_get_ccount(void)
28{ 28{
29 u32 ccount; 29 u32 ccount;
30 asm volatile ("rsr %0, 234; # CCOUNT\n" : "=r" (ccount)); 30 asm volatile ("rsr %0, ccount\n" : "=r" (ccount));
31 return ccount; 31 return ccount;
32} 32}
33 33
diff --git a/arch/xtensa/include/asm/irqflags.h b/arch/xtensa/include/asm/irqflags.h
index dae9a8bdcb17..f865b1c1eae4 100644
--- a/arch/xtensa/include/asm/irqflags.h
+++ b/arch/xtensa/include/asm/irqflags.h
@@ -16,7 +16,7 @@
16static inline unsigned long arch_local_save_flags(void) 16static inline unsigned long arch_local_save_flags(void)
17{ 17{
18 unsigned long flags; 18 unsigned long flags;
19 asm volatile("rsr %0,"__stringify(PS) : "=a" (flags)); 19 asm volatile("rsr %0, ps" : "=a" (flags));
20 return flags; 20 return flags;
21} 21}
22 22
@@ -41,7 +41,7 @@ static inline void arch_local_irq_enable(void)
41 41
42static inline void arch_local_irq_restore(unsigned long flags) 42static inline void arch_local_irq_restore(unsigned long flags)
43{ 43{
44 asm volatile("wsr %0, "__stringify(PS)" ; rsync" 44 asm volatile("wsr %0, ps; rsync"
45 :: "a" (flags) : "memory"); 45 :: "a" (flags) : "memory");
46} 46}
47 47
diff --git a/arch/xtensa/include/asm/mmu_context.h b/arch/xtensa/include/asm/mmu_context.h
index dbd8731a876a..feb10af96519 100644
--- a/arch/xtensa/include/asm/mmu_context.h
+++ b/arch/xtensa/include/asm/mmu_context.h
@@ -51,14 +51,14 @@ extern unsigned long asid_cache;
51 51
52static inline void set_rasid_register (unsigned long val) 52static inline void set_rasid_register (unsigned long val)
53{ 53{
54 __asm__ __volatile__ (" wsr %0, "__stringify(RASID)"\n\t" 54 __asm__ __volatile__ (" wsr %0, rasid\n\t"
55 " isync\n" : : "a" (val)); 55 " isync\n" : : "a" (val));
56} 56}
57 57
58static inline unsigned long get_rasid_register (void) 58static inline unsigned long get_rasid_register (void)
59{ 59{
60 unsigned long tmp; 60 unsigned long tmp;
61 __asm__ __volatile__ (" rsr %0,"__stringify(RASID)"\n\t" : "=a" (tmp)); 61 __asm__ __volatile__ (" rsr %0, rasid\n\t" : "=a" (tmp));
62 return tmp; 62 return tmp;
63} 63}
64 64
diff --git a/arch/xtensa/include/asm/regs.h b/arch/xtensa/include/asm/regs.h
index a3075b12aff1..8a8aa61ccc8d 100644
--- a/arch/xtensa/include/asm/regs.h
+++ b/arch/xtensa/include/asm/regs.h
@@ -27,52 +27,15 @@
27 27
28/* Special registers. */ 28/* Special registers. */
29 29
30#define LBEG 0 30#define SREG_MR 32
31#define LEND 1 31#define SREG_IBREAKA 128
32#define LCOUNT 2 32#define SREG_DBREAKA 144
33#define SAR 3 33#define SREG_DBREAKC 160
34#define BR 4 34#define SREG_EPC 176
35#define SCOMPARE1 12 35#define SREG_EPS 192
36#define ACCHI 16 36#define SREG_EXCSAVE 208
37#define ACCLO 17 37#define SREG_CCOMPARE 240
38#define MR 32 38#define SREG_MISC 244
39#define WINDOWBASE 72
40#define WINDOWSTART 73
41#define PTEVADDR 83
42#define RASID 90
43#define ITLBCFG 91
44#define DTLBCFG 92
45#define IBREAKENABLE 96
46#define DDR 104
47#define IBREAKA 128
48#define DBREAKA 144
49#define DBREAKC 160
50#define EPC 176
51#define EPC_1 177
52#define DEPC 192
53#define EPS 192
54#define EPS_1 193
55#define EXCSAVE 208
56#define EXCSAVE_1 209
57#define INTERRUPT 226
58#define INTENABLE 228
59#define PS 230
60#define THREADPTR 231
61#define EXCCAUSE 232
62#define DEBUGCAUSE 233
63#define CCOUNT 234
64#define PRID 235
65#define ICOUNT 236
66#define ICOUNTLEVEL 237
67#define EXCVADDR 238
68#define CCOMPARE 240
69#define MISC_SR 244
70
71/* Special names for read-only and write-only interrupt registers. */
72
73#define INTREAD 226
74#define INTSET 226
75#define INTCLEAR 227
76 39
77/* EXCCAUSE register fields */ 40/* EXCCAUSE register fields */
78 41
diff --git a/arch/xtensa/include/asm/timex.h b/arch/xtensa/include/asm/timex.h
index 053bc4272106..175b3d5e1b01 100644
--- a/arch/xtensa/include/asm/timex.h
+++ b/arch/xtensa/include/asm/timex.h
@@ -63,10 +63,10 @@ extern cycles_t cacheflush_time;
63 * Register access. 63 * Register access.
64 */ 64 */
65 65
66#define WSR_CCOUNT(r) asm volatile ("wsr %0,"__stringify(CCOUNT) :: "a" (r)) 66#define WSR_CCOUNT(r) asm volatile ("wsr %0, ccount" :: "a" (r))
67#define RSR_CCOUNT(r) asm volatile ("rsr %0,"__stringify(CCOUNT) : "=a" (r)) 67#define RSR_CCOUNT(r) asm volatile ("rsr %0, ccount" : "=a" (r))
68#define WSR_CCOMPARE(x,r) asm volatile ("wsr %0,"__stringify(CCOMPARE)"+"__stringify(x) :: "a"(r)) 68#define WSR_CCOMPARE(x,r) asm volatile ("wsr %0,"__stringify(SREG_CCOMPARE)"+"__stringify(x) :: "a"(r))
69#define RSR_CCOMPARE(x,r) asm volatile ("rsr %0,"__stringify(CCOMPARE)"+"__stringify(x) : "=a"(r)) 69#define RSR_CCOMPARE(x,r) asm volatile ("rsr %0,"__stringify(SREG_CCOMPARE)"+"__stringify(x) : "=a"(r))
70 70
71static inline unsigned long get_ccount (void) 71static inline unsigned long get_ccount (void)
72{ 72{
diff --git a/arch/xtensa/include/asm/tlbflush.h b/arch/xtensa/include/asm/tlbflush.h
index 46d240074f74..43dd348a5a47 100644
--- a/arch/xtensa/include/asm/tlbflush.h
+++ b/arch/xtensa/include/asm/tlbflush.h
@@ -86,26 +86,26 @@ static inline void invalidate_dtlb_entry_no_isync (unsigned entry)
86 86
87static inline void set_itlbcfg_register (unsigned long val) 87static inline void set_itlbcfg_register (unsigned long val)
88{ 88{
89 __asm__ __volatile__("wsr %0, "__stringify(ITLBCFG)"\n\t" "isync\n\t" 89 __asm__ __volatile__("wsr %0, itlbcfg\n\t" "isync\n\t"
90 : : "a" (val)); 90 : : "a" (val));
91} 91}
92 92
93static inline void set_dtlbcfg_register (unsigned long val) 93static inline void set_dtlbcfg_register (unsigned long val)
94{ 94{
95 __asm__ __volatile__("wsr %0, "__stringify(DTLBCFG)"; dsync\n\t" 95 __asm__ __volatile__("wsr %0, dtlbcfg; dsync\n\t"
96 : : "a" (val)); 96 : : "a" (val));
97} 97}
98 98
99static inline void set_ptevaddr_register (unsigned long val) 99static inline void set_ptevaddr_register (unsigned long val)
100{ 100{
101 __asm__ __volatile__(" wsr %0, "__stringify(PTEVADDR)"; isync\n" 101 __asm__ __volatile__(" wsr %0, ptevaddr; isync\n"
102 : : "a" (val)); 102 : : "a" (val));
103} 103}
104 104
105static inline unsigned long read_ptevaddr_register (void) 105static inline unsigned long read_ptevaddr_register (void)
106{ 106{
107 unsigned long tmp; 107 unsigned long tmp;
108 __asm__ __volatile__("rsr %0, "__stringify(PTEVADDR)"\n\t" : "=a" (tmp)); 108 __asm__ __volatile__("rsr %0, ptevaddr\n\t" : "=a" (tmp));
109 return tmp; 109 return tmp;
110} 110}
111 111
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