x86: Don't setup ioapic irq for sci twice

The sparseirq rework triggered a warning in the iommu code, which was
caused by setting up ioapic for ACPI irq 9 twice. This function is
solely to handle interrupts which are on a secondary ioapic and
outside the legacy irq range.

Replace the sparse irq_to_desc check with a non ifdeffed version.

[ tglx: Moved it before the ioapic sparse conversion and simplified
  	the inverse logic ]

Signed-off-by: Yinghai Lu <yinghai@kernel.org>
LKML-Reference: <4CB00122.3030301@kernel.org>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Ingo Molnar <mingo@elte.hu>

1 files changed, 4 insertions, 4 deletions

diff --git a/arch/x86/kernel/apic/io_apic.c b/arch/x86/kernel/apic/io_apic.c
index 06da8fe2647e..5aae718a7133 100644
--- a/arch/x86/kernel/apic/io_apic.c
+++ b/arch/x86/kernel/apic/io_apic.c
@@ -1565,11 +1565,11 @@ void setup_IO_APIC_irq_extra(u32 gsi)
                 return;
 
         irq = pin_2_irq(idx, apic_id, pin);
-#ifdef CONFIG_SPARSE_IRQ
-        desc = irq_to_desc(irq);
-        if (desc)
+
+        /* Only handle the non legacy irqs on secondary ioapics */
+        if (apic_id == 0 || irq < NR_IRQS_LEGACY)
                 return;
-#endif
+
         desc = irq_to_desc_alloc_node(irq, node);
         if (!desc) {
                 printk(KERN_INFO "can not get irq_desc for %d\n", irq);