Merge branch 'perf-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip

Pull perf updates from Ingo Molnar:
 "This tree includes some late late perf items that missed the first
  round:

  tools:

   - Bash auto completion improvements, now we can auto complete the
     tools long options, tracepoint event names, etc, from Namhyung Kim.

   - Look up thread using tid instead of pid in 'perf sched'.

   - Move global variables into a perf_kvm struct, from David Ahern.

   - Hists refactorings, preparatory for improved 'diff' command, from
     Jiri Olsa.

   - Hists refactorings, preparatory for event group viewieng work, from
     Namhyung Kim.

   - Remove double negation on optional feature macro definitions, from
     Namhyung Kim.

   - Remove several cases of needless global variables, on most
     builtins.

   - misc fixes

  kernel:

   - sysfs support for IBS on AMD CPUs, from Robert Richter.

   - Support for an upcoming Intel CPU, the Xeon-Phi / Knights Corner
     HPC blade PMU, from Vince Weaver.

   - misc fixes"

* 'perf-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (46 commits)
  perf: Fix perf_cgroup_switch for sw-events
  perf: Clarify perf_cpu_context::active_pmu usage by renaming it to ::unique_pmu
  perf/AMD/IBS: Add sysfs support
  perf hists: Add more helpers for hist entry stat
  perf hists: Move he->stat.nr_events initialization to a template
  perf hists: Introduce struct he_stat
  perf diff: Removing the total_period argument from output code
  perf tool: Add hpp interface to enable/disable hpp column
  perf tools: Removing hists pair argument from output path
  perf hists: Separate overhead and baseline columns
  perf diff: Refactor diff displacement possition info
  perf hists: Add struct hists pointer to struct hist_entry
  perf tools: Complete tracepoint event names
  perf/x86: Add support for Intel Xeon-Phi Knights Corner PMU
  perf evlist: Remove some unused methods
  perf evlist: Introduce add_newtp method
  perf kvm: Move global variables into a perf_kvm struct
  perf tools: Convert to BACKTRACE_SUPPORT
  perf tools: Long option completion support for each subcommands
  perf tools: Complete long option names of perf command
  ...

7 files changed, 311 insertions, 13 deletions

diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
index fbee9714d9ab..7f0edceb7563 100644
--- a/arch/x86/include/asm/msr-index.h
+++ b/arch/x86/include/asm/msr-index.h
@@ -121,6 +121,11 @@
 #define MSR_P6_EVNTSEL0                 0x00000186
 #define MSR_P6_EVNTSEL1                 0x00000187
 
+#define MSR_KNC_PERFCTR0               0x00000020
+#define MSR_KNC_PERFCTR1               0x00000021
+#define MSR_KNC_EVNTSEL0               0x00000028
+#define MSR_KNC_EVNTSEL1               0x00000029
+
 /* AMD64 MSRs. Not complete. See the architecture manual for a more
    complete list. */
 
diff --git a/arch/x86/kernel/cpu/Makefile b/arch/x86/kernel/cpu/Makefile
index d30a6a9a0121..a0e067d3d96c 100644
--- a/arch/x86/kernel/cpu/Makefile
+++ b/arch/x86/kernel/cpu/Makefile
@@ -32,7 +32,7 @@ obj-$(CONFIG_PERF_EVENTS)		+= perf_event.o
 
 ifdef CONFIG_PERF_EVENTS
 obj-$(CONFIG_CPU_SUP_AMD)               += perf_event_amd.o
-obj-$(CONFIG_CPU_SUP_INTEL)             += perf_event_p6.o perf_event_p4.o
+obj-$(CONFIG_CPU_SUP_INTEL)             += perf_event_p6.o perf_event_knc.o perf_event_p4.o
 obj-$(CONFIG_CPU_SUP_INTEL)             += perf_event_intel_lbr.o perf_event_intel_ds.o perf_event_intel.o
 obj-$(CONFIG_CPU_SUP_INTEL)             += perf_event_intel_uncore.o
 endif
diff --git a/arch/x86/kernel/cpu/perf_event.h b/arch/x86/kernel/cpu/perf_event.h
index 8b6defe7eefc..271d25700297 100644
--- a/arch/x86/kernel/cpu/perf_event.h
+++ b/arch/x86/kernel/cpu/perf_event.h
@@ -626,6 +626,8 @@ int p4_pmu_init(void);
 
 int p6_pmu_init(void);
 
+int knc_pmu_init(void);
+
 #else /* CONFIG_CPU_SUP_INTEL */
 
 static inline void reserve_ds_buffers(void)
diff --git a/arch/x86/kernel/cpu/perf_event_amd_ibs.c b/arch/x86/kernel/cpu/perf_event_amd_ibs.c
index eebd5ffe1bba..6336bcbd0618 100644
--- a/arch/x86/kernel/cpu/perf_event_amd_ibs.c
+++ b/arch/x86/kernel/cpu/perf_event_amd_ibs.c
@@ -41,17 +41,22 @@ struct cpu_perf_ibs {
 };
 
 struct perf_ibs {
-        struct pmu      pmu;
-        unsigned int    msr;
-        u64             config_mask;
-        u64             cnt_mask;
-        u64             enable_mask;
-        u64             valid_mask;
-        u64             max_period;
-        unsigned long   offset_mask[1];
-        int             offset_max;
-        struct cpu_perf_ibs __percpu *pcpu;
-        u64             (*get_count)(u64 config);
+        struct pmu                      pmu;
+        unsigned int                    msr;
+        u64                             config_mask;
+        u64                             cnt_mask;
+        u64                             enable_mask;
+        u64                             valid_mask;
+        u64                             max_period;
+        unsigned long                   offset_mask[1];
+        int                             offset_max;
+        struct cpu_perf_ibs __percpu    *pcpu;
+
+        struct attribute                **format_attrs;
+        struct attribute_group          format_group;
+        const struct attribute_group    *attr_groups[2];
+
+        u64                             (*get_count)(u64 config);
 };
 
 struct perf_ibs_data {
@@ -446,6 +451,19 @@ static void perf_ibs_del(struct perf_event *event, int flags)
 
 static void perf_ibs_read(struct perf_event *event) { }
 
+PMU_FORMAT_ATTR(rand_en,        "config:57");
+PMU_FORMAT_ATTR(cnt_ctl,        "config:19");
+
+static struct attribute *ibs_fetch_format_attrs[] = {
+        &format_attr_rand_en.attr,
+        NULL,
+};
+
+static struct attribute *ibs_op_format_attrs[] = {
+        NULL,   /* &format_attr_cnt_ctl.attr if IBS_CAPS_OPCNT */
+        NULL,
+};
+
 static struct perf_ibs perf_ibs_fetch = {
         .pmu = {
                 .task_ctx_nr    = perf_invalid_context,
@@ -465,6 +483,7 @@ static struct perf_ibs perf_ibs_fetch = {
         .max_period             = IBS_FETCH_MAX_CNT << 4,
         .offset_mask            = { MSR_AMD64_IBSFETCH_REG_MASK },
         .offset_max             = MSR_AMD64_IBSFETCH_REG_COUNT,
+        .format_attrs           = ibs_fetch_format_attrs,
 
         .get_count              = get_ibs_fetch_count,
 };
@@ -488,6 +507,7 @@ static struct perf_ibs perf_ibs_op = {
         .max_period             = IBS_OP_MAX_CNT << 4,
         .offset_mask            = { MSR_AMD64_IBSOP_REG_MASK },
         .offset_max             = MSR_AMD64_IBSOP_REG_COUNT,
+        .format_attrs           = ibs_op_format_attrs,
 
         .get_count              = get_ibs_op_count,
 };
@@ -597,6 +617,17 @@ static __init int perf_ibs_pmu_init(struct perf_ibs *perf_ibs, char *name)
 
         perf_ibs->pcpu = pcpu;
 
+        /* register attributes */
+        if (perf_ibs->format_attrs[0]) {
+                memset(&perf_ibs->format_group, 0, sizeof(perf_ibs->format_group));
+                perf_ibs->format_group.name     = "format";
+                perf_ibs->format_group.attrs    = perf_ibs->format_attrs;
+
+                memset(&perf_ibs->attr_groups, 0, sizeof(perf_ibs->attr_groups));
+                perf_ibs->attr_groups[0]        = &perf_ibs->format_group;
+                perf_ibs->pmu.attr_groups       = perf_ibs->attr_groups;
+        }
+
         ret = perf_pmu_register(&perf_ibs->pmu, name, -1);
         if (ret) {
                 perf_ibs->pcpu = NULL;
@@ -608,13 +639,19 @@ static __init int perf_ibs_pmu_init(struct perf_ibs *perf_ibs, char *name)
 
 static __init int perf_event_ibs_init(void)
 {
+        struct attribute **attr = ibs_op_format_attrs;
+
         if (!ibs_caps)
                 return -ENODEV; /* ibs not supported by the cpu */
 
         perf_ibs_pmu_init(&perf_ibs_fetch, "ibs_fetch");
-        if (ibs_caps & IBS_CAPS_OPCNT)
+
+        if (ibs_caps & IBS_CAPS_OPCNT) {
                 perf_ibs_op.config_mask |= IBS_OP_CNT_CTL;
+                *attr++ = &format_attr_cnt_ctl.attr;
+        }
         perf_ibs_pmu_init(&perf_ibs_op, "ibs_op");
+
         register_nmi_handler(NMI_LOCAL, perf_ibs_nmi_handler, 0, "perf_ibs");
         printk(KERN_INFO "perf: AMD IBS detected (0x%08x)\n", ibs_caps);
 
diff --git a/arch/x86/kernel/cpu/perf_event_intel.c b/arch/x86/kernel/cpu/perf_event_intel.c
index 6bca492b8547..324bb523d9d9 100644
--- a/arch/x86/kernel/cpu/perf_event_intel.c
+++ b/arch/x86/kernel/cpu/perf_event_intel.c
@@ -1906,6 +1906,8 @@ __init int intel_pmu_init(void)
                 switch (boot_cpu_data.x86) {
                 case 0x6:
                         return p6_pmu_init();
+                case 0xb:
+                        return knc_pmu_init();
                 case 0xf:
                         return p4_pmu_init();
                 }
diff --git a/arch/x86/kernel/cpu/perf_event_knc.c b/arch/x86/kernel/cpu/perf_event_knc.c
new file mode 100644
index 000000000000..7c46bfdbc373
--- /dev/null
+++ b/arch/x86/kernel/cpu/perf_event_knc.c
@@ -0,0 +1,248 @@
+/* Driver for Intel Xeon Phi "Knights Corner" PMU */
+
+#include <linux/perf_event.h>
+#include <linux/types.h>
+
+#include "perf_event.h"
+
+static const u64 knc_perfmon_event_map[] =
+{
+  [PERF_COUNT_HW_CPU_CYCLES]            = 0x002a,
+  [PERF_COUNT_HW_INSTRUCTIONS]          = 0x0016,
+  [PERF_COUNT_HW_CACHE_REFERENCES]      = 0x0028,
+  [PERF_COUNT_HW_CACHE_MISSES]          = 0x0029,
+  [PERF_COUNT_HW_BRANCH_INSTRUCTIONS]   = 0x0012,
+  [PERF_COUNT_HW_BRANCH_MISSES]         = 0x002b,
+};
+
+static __initconst u64 knc_hw_cache_event_ids
+                                [PERF_COUNT_HW_CACHE_MAX]
+                                [PERF_COUNT_HW_CACHE_OP_MAX]
+                                [PERF_COUNT_HW_CACHE_RESULT_MAX] =
+{
+ [ C(L1D) ] = {
+        [ C(OP_READ) ] = {
+                /* On Xeon Phi event "0" is a valid DATA_READ          */
+                /*   (L1 Data Cache Reads) Instruction.                */
+                /* We code this as ARCH_PERFMON_EVENTSEL_INT as this   */
+                /* bit will always be set in x86_pmu_hw_config().      */
+                [ C(RESULT_ACCESS) ] = ARCH_PERFMON_EVENTSEL_INT,
+                                                /* DATA_READ           */
+                [ C(RESULT_MISS)   ] = 0x0003,  /* DATA_READ_MISS      */
+        },
+        [ C(OP_WRITE) ] = {
+                [ C(RESULT_ACCESS) ] = 0x0001,  /* DATA_WRITE          */
+                [ C(RESULT_MISS)   ] = 0x0004,  /* DATA_WRITE_MISS     */
+        },
+        [ C(OP_PREFETCH) ] = {
+                [ C(RESULT_ACCESS) ] = 0x0011,  /* L1_DATA_PF1         */
+                [ C(RESULT_MISS)   ] = 0x001c,  /* L1_DATA_PF1_MISS    */
+        },
+ },
+ [ C(L1I ) ] = {
+        [ C(OP_READ) ] = {
+                [ C(RESULT_ACCESS) ] = 0x000c,  /* CODE_READ          */
+                [ C(RESULT_MISS)   ] = 0x000e,  /* CODE_CACHE_MISS    */
+        },
+        [ C(OP_WRITE) ] = {
+                [ C(RESULT_ACCESS) ] = -1,
+                [ C(RESULT_MISS)   ] = -1,
+        },
+        [ C(OP_PREFETCH) ] = {
+                [ C(RESULT_ACCESS) ] = 0x0,
+                [ C(RESULT_MISS)   ] = 0x0,
+        },
+ },
+ [ C(LL  ) ] = {
+        [ C(OP_READ) ] = {
+                [ C(RESULT_ACCESS) ] = 0,
+                [ C(RESULT_MISS)   ] = 0x10cb,  /* L2_READ_MISS */
+        },
+        [ C(OP_WRITE) ] = {
+                [ C(RESULT_ACCESS) ] = 0x10cc,  /* L2_WRITE_HIT */
+                [ C(RESULT_MISS)   ] = 0,
+        },
+        [ C(OP_PREFETCH) ] = {
+                [ C(RESULT_ACCESS) ] = 0x10fc,  /* L2_DATA_PF2      */
+                [ C(RESULT_MISS)   ] = 0x10fe,  /* L2_DATA_PF2_MISS */
+        },
+ },
+ [ C(DTLB) ] = {
+        [ C(OP_READ) ] = {
+                [ C(RESULT_ACCESS) ] = ARCH_PERFMON_EVENTSEL_INT,
+                                                /* DATA_READ */
+                                                /* see note on L1 OP_READ */
+                [ C(RESULT_MISS)   ] = 0x0002,  /* DATA_PAGE_WALK */
+        },
+        [ C(OP_WRITE) ] = {
+                [ C(RESULT_ACCESS) ] = 0x0001,  /* DATA_WRITE */
+                [ C(RESULT_MISS)   ] = 0x0002,  /* DATA_PAGE_WALK */
+        },
+        [ C(OP_PREFETCH) ] = {
+                [ C(RESULT_ACCESS) ] = 0x0,
+                [ C(RESULT_MISS)   ] = 0x0,
+        },
+ },
+ [ C(ITLB) ] = {
+        [ C(OP_READ) ] = {
+                [ C(RESULT_ACCESS) ] = 0x000c,  /* CODE_READ */
+                [ C(RESULT_MISS)   ] = 0x000d,  /* CODE_PAGE_WALK */
+        },
+        [ C(OP_WRITE) ] = {
+                [ C(RESULT_ACCESS) ] = -1,
+                [ C(RESULT_MISS)   ] = -1,
+        },
+        [ C(OP_PREFETCH) ] = {
+                [ C(RESULT_ACCESS) ] = -1,
+                [ C(RESULT_MISS)   ] = -1,
+        },
+ },
+ [ C(BPU ) ] = {
+        [ C(OP_READ) ] = {
+                [ C(RESULT_ACCESS) ] = 0x0012,  /* BRANCHES */
+                [ C(RESULT_MISS)   ] = 0x002b,  /* BRANCHES_MISPREDICTED */
+        },
+        [ C(OP_WRITE) ] = {
+                [ C(RESULT_ACCESS) ] = -1,
+                [ C(RESULT_MISS)   ] = -1,
+        },
+        [ C(OP_PREFETCH) ] = {
+                [ C(RESULT_ACCESS) ] = -1,
+                [ C(RESULT_MISS)   ] = -1,
+        },
+ },
+};
+
+
+static u64 knc_pmu_event_map(int hw_event)
+{
+        return knc_perfmon_event_map[hw_event];
+}
+
+static struct event_constraint knc_event_constraints[] =
+{
+        INTEL_EVENT_CONSTRAINT(0xc3, 0x1),      /* HWP_L2HIT */
+        INTEL_EVENT_CONSTRAINT(0xc4, 0x1),      /* HWP_L2MISS */
+        INTEL_EVENT_CONSTRAINT(0xc8, 0x1),      /* L2_READ_HIT_E */
+        INTEL_EVENT_CONSTRAINT(0xc9, 0x1),      /* L2_READ_HIT_M */
+        INTEL_EVENT_CONSTRAINT(0xca, 0x1),      /* L2_READ_HIT_S */
+        INTEL_EVENT_CONSTRAINT(0xcb, 0x1),      /* L2_READ_MISS */
+        INTEL_EVENT_CONSTRAINT(0xcc, 0x1),      /* L2_WRITE_HIT */
+        INTEL_EVENT_CONSTRAINT(0xce, 0x1),      /* L2_STRONGLY_ORDERED_STREAMING_VSTORES_MISS */
+        INTEL_EVENT_CONSTRAINT(0xcf, 0x1),      /* L2_WEAKLY_ORDERED_STREAMING_VSTORE_MISS */
+        INTEL_EVENT_CONSTRAINT(0xd7, 0x1),      /* L2_VICTIM_REQ_WITH_DATA */
+        INTEL_EVENT_CONSTRAINT(0xe3, 0x1),      /* SNP_HITM_BUNIT */
+        INTEL_EVENT_CONSTRAINT(0xe6, 0x1),      /* SNP_HIT_L2 */
+        INTEL_EVENT_CONSTRAINT(0xe7, 0x1),      /* SNP_HITM_L2 */
+        INTEL_EVENT_CONSTRAINT(0xf1, 0x1),      /* L2_DATA_READ_MISS_CACHE_FILL */
+        INTEL_EVENT_CONSTRAINT(0xf2, 0x1),      /* L2_DATA_WRITE_MISS_CACHE_FILL */
+        INTEL_EVENT_CONSTRAINT(0xf6, 0x1),      /* L2_DATA_READ_MISS_MEM_FILL */
+        INTEL_EVENT_CONSTRAINT(0xf7, 0x1),      /* L2_DATA_WRITE_MISS_MEM_FILL */
+        INTEL_EVENT_CONSTRAINT(0xfc, 0x1),      /* L2_DATA_PF2 */
+        INTEL_EVENT_CONSTRAINT(0xfd, 0x1),      /* L2_DATA_PF2_DROP */
+        INTEL_EVENT_CONSTRAINT(0xfe, 0x1),      /* L2_DATA_PF2_MISS */
+        INTEL_EVENT_CONSTRAINT(0xff, 0x1),      /* L2_DATA_HIT_INFLIGHT_PF2 */
+        EVENT_CONSTRAINT_END
+};
+
+#define MSR_KNC_IA32_PERF_GLOBAL_STATUS         0x0000002d
+#define MSR_KNC_IA32_PERF_GLOBAL_OVF_CONTROL    0x0000002e
+#define MSR_KNC_IA32_PERF_GLOBAL_CTRL           0x0000002f
+
+#define KNC_ENABLE_COUNTER0                     0x00000001
+#define KNC_ENABLE_COUNTER1                     0x00000002
+
+static void knc_pmu_disable_all(void)
+{
+        u64 val;
+
+        rdmsrl(MSR_KNC_IA32_PERF_GLOBAL_CTRL, val);
+        val &= ~(KNC_ENABLE_COUNTER0|KNC_ENABLE_COUNTER1);
+        wrmsrl(MSR_KNC_IA32_PERF_GLOBAL_CTRL, val);
+}
+
+static void knc_pmu_enable_all(int added)
+{
+        u64 val;
+
+        rdmsrl(MSR_KNC_IA32_PERF_GLOBAL_CTRL, val);
+        val |= (KNC_ENABLE_COUNTER0|KNC_ENABLE_COUNTER1);
+        wrmsrl(MSR_KNC_IA32_PERF_GLOBAL_CTRL, val);
+}
+
+static inline void
+knc_pmu_disable_event(struct perf_event *event)
+{
+        struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
+        struct hw_perf_event *hwc = &event->hw;
+        u64 val;
+
+        val = hwc->config;
+        if (cpuc->enabled)
+                val &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
+
+        (void)wrmsrl_safe(hwc->config_base + hwc->idx, val);
+}
+
+static void knc_pmu_enable_event(struct perf_event *event)
+{
+        struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
+        struct hw_perf_event *hwc = &event->hw;
+        u64 val;
+
+        val = hwc->config;
+        if (cpuc->enabled)
+                val |= ARCH_PERFMON_EVENTSEL_ENABLE;
+
+        (void)wrmsrl_safe(hwc->config_base + hwc->idx, val);
+}
+
+PMU_FORMAT_ATTR(event,  "config:0-7"    );
+PMU_FORMAT_ATTR(umask,  "config:8-15"   );
+PMU_FORMAT_ATTR(edge,   "config:18"     );
+PMU_FORMAT_ATTR(inv,    "config:23"     );
+PMU_FORMAT_ATTR(cmask,  "config:24-31"  );
+
+static struct attribute *intel_knc_formats_attr[] = {
+        &format_attr_event.attr,
+        &format_attr_umask.attr,
+        &format_attr_edge.attr,
+        &format_attr_inv.attr,
+        &format_attr_cmask.attr,
+        NULL,
+};
+
+static __initconst struct x86_pmu knc_pmu = {
+        .name                   = "knc",
+        .handle_irq             = x86_pmu_handle_irq,
+        .disable_all            = knc_pmu_disable_all,
+        .enable_all             = knc_pmu_enable_all,
+        .enable                 = knc_pmu_enable_event,
+        .disable                = knc_pmu_disable_event,
+        .hw_config              = x86_pmu_hw_config,
+        .schedule_events        = x86_schedule_events,
+        .eventsel               = MSR_KNC_EVNTSEL0,
+        .perfctr                = MSR_KNC_PERFCTR0,
+        .event_map              = knc_pmu_event_map,
+        .max_events             = ARRAY_SIZE(knc_perfmon_event_map),
+        .apic                   = 1,
+        .max_period             = (1ULL << 31) - 1,
+        .version                = 0,
+        .num_counters           = 2,
+        /* in theory 40 bits, early silicon is buggy though */
+        .cntval_bits            = 32,
+        .cntval_mask            = (1ULL << 32) - 1,
+        .get_event_constraints  = x86_get_event_constraints,
+        .event_constraints      = knc_event_constraints,
+        .format_attrs           = intel_knc_formats_attr,
+};
+
+__init int knc_pmu_init(void)
+{
+        x86_pmu = knc_pmu;
+
+        memcpy(hw_cache_event_ids, knc_hw_cache_event_ids, 
+                sizeof(hw_cache_event_ids));
+
+        return 0;
+}
diff --git a/arch/x86/kernel/cpu/perfctr-watchdog.c b/arch/x86/kernel/cpu/perfctr-watchdog.c
index 966512b2cacf..2e8caf03f593 100644
--- a/arch/x86/kernel/cpu/perfctr-watchdog.c
+++ b/arch/x86/kernel/cpu/perfctr-watchdog.c
@@ -56,6 +56,8 @@ static inline unsigned int nmi_perfctr_msr_to_bit(unsigned int msr)
                 switch (boot_cpu_data.x86) {
                 case 6:
                         return msr - MSR_P6_PERFCTR0;
+                case 11:
+                        return msr - MSR_KNC_PERFCTR0;
                 case 15:
                         return msr - MSR_P4_BPU_PERFCTR0;
                 }
@@ -82,6 +84,8 @@ static inline unsigned int nmi_evntsel_msr_to_bit(unsigned int msr)
                 switch (boot_cpu_data.x86) {
                 case 6:
                         return msr - MSR_P6_EVNTSEL0;
+                case 11:
+                        return msr - MSR_KNC_EVNTSEL0;
                 case 15:
                         return msr - MSR_P4_BSU_ESCR0;
                 }