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authorLinus Torvalds <torvalds@linux-foundation.org>2014-04-19 13:41:43 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2014-04-19 13:41:43 -0400
commit6d4596905b65bf4c63c1a008f50bf385fa49f19b (patch)
tree3631875baa6ef07ff0c207b1c84d95eb7c1f7e09 /arch/x86
parent8f98f6f5d68028018d2362c13b5527c920d9115f (diff)
parentea431643d6c38728195e2c456801c3ef66bb9991 (diff)
Merge branch 'x86-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull x86 fix from Ingo Molnar: "This fixes the preemption-count imbalance crash reported by Owen Kibel" * 'x86-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: x86/mce: Fix CMCI preemption bugs
Diffstat (limited to 'arch/x86')
-rw-r--r--arch/x86/kernel/cpu/mcheck/mce.c4
-rw-r--r--arch/x86/kernel/cpu/mcheck/mce_intel.c18
2 files changed, 10 insertions, 12 deletions
diff --git a/arch/x86/kernel/cpu/mcheck/mce.c b/arch/x86/kernel/cpu/mcheck/mce.c
index eeee23ff75ef..68317c80de7f 100644
--- a/arch/x86/kernel/cpu/mcheck/mce.c
+++ b/arch/x86/kernel/cpu/mcheck/mce.c
@@ -598,7 +598,6 @@ void machine_check_poll(enum mcp_flags flags, mce_banks_t *b)
598{ 598{
599 struct mce m; 599 struct mce m;
600 int i; 600 int i;
601 unsigned long *v;
602 601
603 this_cpu_inc(mce_poll_count); 602 this_cpu_inc(mce_poll_count);
604 603
@@ -618,8 +617,7 @@ void machine_check_poll(enum mcp_flags flags, mce_banks_t *b)
618 if (!(m.status & MCI_STATUS_VAL)) 617 if (!(m.status & MCI_STATUS_VAL))
619 continue; 618 continue;
620 619
621 v = &get_cpu_var(mce_polled_error); 620 this_cpu_write(mce_polled_error, 1);
622 set_bit(0, v);
623 /* 621 /*
624 * Uncorrected or signalled events are handled by the exception 622 * Uncorrected or signalled events are handled by the exception
625 * handler when it is enabled, so don't process those here. 623 * handler when it is enabled, so don't process those here.
diff --git a/arch/x86/kernel/cpu/mcheck/mce_intel.c b/arch/x86/kernel/cpu/mcheck/mce_intel.c
index 3bdb95ae8c43..9a316b21df8b 100644
--- a/arch/x86/kernel/cpu/mcheck/mce_intel.c
+++ b/arch/x86/kernel/cpu/mcheck/mce_intel.c
@@ -42,7 +42,7 @@ static DEFINE_PER_CPU(mce_banks_t, mce_banks_owned);
42 * cmci_discover_lock protects against parallel discovery attempts 42 * cmci_discover_lock protects against parallel discovery attempts
43 * which could race against each other. 43 * which could race against each other.
44 */ 44 */
45static DEFINE_RAW_SPINLOCK(cmci_discover_lock); 45static DEFINE_SPINLOCK(cmci_discover_lock);
46 46
47#define CMCI_THRESHOLD 1 47#define CMCI_THRESHOLD 1
48#define CMCI_POLL_INTERVAL (30 * HZ) 48#define CMCI_POLL_INTERVAL (30 * HZ)
@@ -144,14 +144,14 @@ static void cmci_storm_disable_banks(void)
144 int bank; 144 int bank;
145 u64 val; 145 u64 val;
146 146
147 raw_spin_lock_irqsave(&cmci_discover_lock, flags); 147 spin_lock_irqsave(&cmci_discover_lock, flags);
148 owned = __get_cpu_var(mce_banks_owned); 148 owned = __get_cpu_var(mce_banks_owned);
149 for_each_set_bit(bank, owned, MAX_NR_BANKS) { 149 for_each_set_bit(bank, owned, MAX_NR_BANKS) {
150 rdmsrl(MSR_IA32_MCx_CTL2(bank), val); 150 rdmsrl(MSR_IA32_MCx_CTL2(bank), val);
151 val &= ~MCI_CTL2_CMCI_EN; 151 val &= ~MCI_CTL2_CMCI_EN;
152 wrmsrl(MSR_IA32_MCx_CTL2(bank), val); 152 wrmsrl(MSR_IA32_MCx_CTL2(bank), val);
153 } 153 }
154 raw_spin_unlock_irqrestore(&cmci_discover_lock, flags); 154 spin_unlock_irqrestore(&cmci_discover_lock, flags);
155} 155}
156 156
157static bool cmci_storm_detect(void) 157static bool cmci_storm_detect(void)
@@ -211,7 +211,7 @@ static void cmci_discover(int banks)
211 int i; 211 int i;
212 int bios_wrong_thresh = 0; 212 int bios_wrong_thresh = 0;
213 213
214 raw_spin_lock_irqsave(&cmci_discover_lock, flags); 214 spin_lock_irqsave(&cmci_discover_lock, flags);
215 for (i = 0; i < banks; i++) { 215 for (i = 0; i < banks; i++) {
216 u64 val; 216 u64 val;
217 int bios_zero_thresh = 0; 217 int bios_zero_thresh = 0;
@@ -266,7 +266,7 @@ static void cmci_discover(int banks)
266 WARN_ON(!test_bit(i, __get_cpu_var(mce_poll_banks))); 266 WARN_ON(!test_bit(i, __get_cpu_var(mce_poll_banks)));
267 } 267 }
268 } 268 }
269 raw_spin_unlock_irqrestore(&cmci_discover_lock, flags); 269 spin_unlock_irqrestore(&cmci_discover_lock, flags);
270 if (mca_cfg.bios_cmci_threshold && bios_wrong_thresh) { 270 if (mca_cfg.bios_cmci_threshold && bios_wrong_thresh) {
271 pr_info_once( 271 pr_info_once(
272 "bios_cmci_threshold: Some banks do not have valid thresholds set\n"); 272 "bios_cmci_threshold: Some banks do not have valid thresholds set\n");
@@ -316,10 +316,10 @@ void cmci_clear(void)
316 316
317 if (!cmci_supported(&banks)) 317 if (!cmci_supported(&banks))
318 return; 318 return;
319 raw_spin_lock_irqsave(&cmci_discover_lock, flags); 319 spin_lock_irqsave(&cmci_discover_lock, flags);
320 for (i = 0; i < banks; i++) 320 for (i = 0; i < banks; i++)
321 __cmci_disable_bank(i); 321 __cmci_disable_bank(i);
322 raw_spin_unlock_irqrestore(&cmci_discover_lock, flags); 322 spin_unlock_irqrestore(&cmci_discover_lock, flags);
323} 323}
324 324
325static void cmci_rediscover_work_func(void *arg) 325static void cmci_rediscover_work_func(void *arg)
@@ -360,9 +360,9 @@ void cmci_disable_bank(int bank)
360 if (!cmci_supported(&banks)) 360 if (!cmci_supported(&banks))
361 return; 361 return;
362 362
363 raw_spin_lock_irqsave(&cmci_discover_lock, flags); 363 spin_lock_irqsave(&cmci_discover_lock, flags);
364 __cmci_disable_bank(bank); 364 __cmci_disable_bank(bank);
365 raw_spin_unlock_irqrestore(&cmci_discover_lock, flags); 365 spin_unlock_irqrestore(&cmci_discover_lock, flags);
366} 366}
367 367
368static void intel_init_cmci(void) 368static void intel_init_cmci(void)