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authorAndi Kleen <ak@linux.intel.com>2014-11-03 20:00:27 -0500
committerIngo Molnar <mingo@kernel.org>2014-11-16 03:45:47 -0500
commit41a134a5830a5e1396723ace0a63000780d6e267 (patch)
treecf0a667727f57db649606fc92907d9c363734b7f /arch/x86
parent226424eee809251ec23bd4b09d8efba09c10fc3c (diff)
perf/x86/intel/uncore: Fix IRP uncore register offsets on Haswell EP
The counter register offsets for the IRP box PMU for Haswell-EP were incorrect. The offsets actually changed over IvyBridge EP. Fix them to the correct values. For this we need to fork the read function from the IVB and use an own counter array. Tested-by: patrick.lu@intel.com Signed-off-by: Andi Kleen <ak@linux.intel.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Cc: Arnaldo Carvalho de Melo <acme@kernel.org> Link: http://lkml.kernel.org/r/1415062828-19759-3-git-send-email-andi@firstfloor.org Signed-off-by: Ingo Molnar <mingo@kernel.org>
Diffstat (limited to 'arch/x86')
-rw-r--r--arch/x86/kernel/cpu/perf_event_intel_uncore_snbep.c16
1 files changed, 15 insertions, 1 deletions
diff --git a/arch/x86/kernel/cpu/perf_event_intel_uncore_snbep.c b/arch/x86/kernel/cpu/perf_event_intel_uncore_snbep.c
index adf138eac85c..0af1c932fa0f 100644
--- a/arch/x86/kernel/cpu/perf_event_intel_uncore_snbep.c
+++ b/arch/x86/kernel/cpu/perf_event_intel_uncore_snbep.c
@@ -2025,13 +2025,27 @@ static struct intel_uncore_type hswep_uncore_imc = {
2025 SNBEP_UNCORE_PCI_COMMON_INIT(), 2025 SNBEP_UNCORE_PCI_COMMON_INIT(),
2026}; 2026};
2027 2027
2028static unsigned hswep_uncore_irp_ctrs[] = {0xa0, 0xa8, 0xb0, 0xb8};
2029
2030static u64 hswep_uncore_irp_read_counter(struct intel_uncore_box *box, struct perf_event *event)
2031{
2032 struct pci_dev *pdev = box->pci_dev;
2033 struct hw_perf_event *hwc = &event->hw;
2034 u64 count = 0;
2035
2036 pci_read_config_dword(pdev, hswep_uncore_irp_ctrs[hwc->idx], (u32 *)&count);
2037 pci_read_config_dword(pdev, hswep_uncore_irp_ctrs[hwc->idx] + 4, (u32 *)&count + 1);
2038
2039 return count;
2040}
2041
2028static struct intel_uncore_ops hswep_uncore_irp_ops = { 2042static struct intel_uncore_ops hswep_uncore_irp_ops = {
2029 .init_box = snbep_uncore_pci_init_box, 2043 .init_box = snbep_uncore_pci_init_box,
2030 .disable_box = snbep_uncore_pci_disable_box, 2044 .disable_box = snbep_uncore_pci_disable_box,
2031 .enable_box = snbep_uncore_pci_enable_box, 2045 .enable_box = snbep_uncore_pci_enable_box,
2032 .disable_event = ivbep_uncore_irp_disable_event, 2046 .disable_event = ivbep_uncore_irp_disable_event,
2033 .enable_event = ivbep_uncore_irp_enable_event, 2047 .enable_event = ivbep_uncore_irp_enable_event,
2034 .read_counter = ivbep_uncore_irp_read_counter, 2048 .read_counter = hswep_uncore_irp_read_counter,
2035}; 2049};
2036 2050
2037static struct intel_uncore_type hswep_uncore_irp = { 2051static struct intel_uncore_type hswep_uncore_irp = {