diff options
author | Andi Kleen <ak@linux.intel.com> | 2014-09-24 10:34:47 -0400 |
---|---|---|
committer | Ingo Molnar <mingo@kernel.org> | 2014-11-16 05:41:55 -0500 |
commit | 0dbc94796d8714f78446245ef0f080d2c0b7ff0e (patch) | |
tree | ab81183bd7ade5033c5df7e9f189cb797045b312 /arch/x86 | |
parent | 7550ddffe4c8040db31c66e5bd64531e2916bbf1 (diff) |
perf/x86/intel: Use INTEL_FLAGS_UEVENT_CONSTRAINT for PRECDIST
My earlier commit:
86a04461a99f ("perf/x86: Revamp PEBS event selection")
made nearly all PEBS on Sandy/IvyBridge/Haswell to reject non zero flags.
However this wasn't done for the INST_RETIRED.PREC_DIST event
because no suitable macro existed. Now that we have
INTEL_FLAGS_UEVENT_CONSTRAINT enforce zero flags for
INST_RETIRED.PREC_DIST too.
Signed-off-by: Andi Kleen <ak@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Cc: Arnaldo Carvalho de Melo <acme@kernel.org>
Link: http://lkml.kernel.org/r/1411569288-5627-2-git-send-email-andi@firstfloor.org
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Diffstat (limited to 'arch/x86')
-rw-r--r-- | arch/x86/kernel/cpu/perf_event_intel_ds.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/arch/x86/kernel/cpu/perf_event_intel_ds.c b/arch/x86/kernel/cpu/perf_event_intel_ds.c index 46211bcc813e..12fe1dc6f875 100644 --- a/arch/x86/kernel/cpu/perf_event_intel_ds.c +++ b/arch/x86/kernel/cpu/perf_event_intel_ds.c | |||
@@ -606,7 +606,7 @@ struct event_constraint intel_westmere_pebs_event_constraints[] = { | |||
606 | }; | 606 | }; |
607 | 607 | ||
608 | struct event_constraint intel_snb_pebs_event_constraints[] = { | 608 | struct event_constraint intel_snb_pebs_event_constraints[] = { |
609 | INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PRECDIST */ | 609 | INTEL_FLAGS_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PRECDIST */ |
610 | INTEL_PLD_CONSTRAINT(0x01cd, 0x8), /* MEM_TRANS_RETIRED.LAT_ABOVE_THR */ | 610 | INTEL_PLD_CONSTRAINT(0x01cd, 0x8), /* MEM_TRANS_RETIRED.LAT_ABOVE_THR */ |
611 | INTEL_PST_CONSTRAINT(0x02cd, 0x8), /* MEM_TRANS_RETIRED.PRECISE_STORES */ | 611 | INTEL_PST_CONSTRAINT(0x02cd, 0x8), /* MEM_TRANS_RETIRED.PRECISE_STORES */ |
612 | /* UOPS_RETIRED.ALL, inv=1, cmask=16 (cycles:p). */ | 612 | /* UOPS_RETIRED.ALL, inv=1, cmask=16 (cycles:p). */ |
@@ -617,7 +617,7 @@ struct event_constraint intel_snb_pebs_event_constraints[] = { | |||
617 | }; | 617 | }; |
618 | 618 | ||
619 | struct event_constraint intel_ivb_pebs_event_constraints[] = { | 619 | struct event_constraint intel_ivb_pebs_event_constraints[] = { |
620 | INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PRECDIST */ | 620 | INTEL_FLAGS_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PRECDIST */ |
621 | INTEL_PLD_CONSTRAINT(0x01cd, 0x8), /* MEM_TRANS_RETIRED.LAT_ABOVE_THR */ | 621 | INTEL_PLD_CONSTRAINT(0x01cd, 0x8), /* MEM_TRANS_RETIRED.LAT_ABOVE_THR */ |
622 | INTEL_PST_CONSTRAINT(0x02cd, 0x8), /* MEM_TRANS_RETIRED.PRECISE_STORES */ | 622 | INTEL_PST_CONSTRAINT(0x02cd, 0x8), /* MEM_TRANS_RETIRED.PRECISE_STORES */ |
623 | /* UOPS_RETIRED.ALL, inv=1, cmask=16 (cycles:p). */ | 623 | /* UOPS_RETIRED.ALL, inv=1, cmask=16 (cycles:p). */ |
@@ -628,7 +628,7 @@ struct event_constraint intel_ivb_pebs_event_constraints[] = { | |||
628 | }; | 628 | }; |
629 | 629 | ||
630 | struct event_constraint intel_hsw_pebs_event_constraints[] = { | 630 | struct event_constraint intel_hsw_pebs_event_constraints[] = { |
631 | INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PRECDIST */ | 631 | INTEL_FLAGS_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PRECDIST */ |
632 | INTEL_PLD_CONSTRAINT(0x01cd, 0xf), /* MEM_TRANS_RETIRED.* */ | 632 | INTEL_PLD_CONSTRAINT(0x01cd, 0xf), /* MEM_TRANS_RETIRED.* */ |
633 | /* UOPS_RETIRED.ALL, inv=1, cmask=16 (cycles:p). */ | 633 | /* UOPS_RETIRED.ALL, inv=1, cmask=16 (cycles:p). */ |
634 | INTEL_FLAGS_EVENT_CONSTRAINT(0x108001c2, 0xf), | 634 | INTEL_FLAGS_EVENT_CONSTRAINT(0x108001c2, 0xf), |