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authorGlenn Elliott <gelliott@cs.unc.edu>2012-03-04 19:47:13 -0500
committerGlenn Elliott <gelliott@cs.unc.edu>2012-03-04 19:47:13 -0500
commitc71c03bda1e86c9d5198c5d83f712e695c4f2a1e (patch)
treeecb166cb3e2b7e2adb3b5e292245fefd23381ac8 /arch/x86/platform/mrst
parentea53c912f8a86a8567697115b6a0d8152beee5c8 (diff)
parent6a00f206debf8a5c8899055726ad127dbeeed098 (diff)
Merge branch 'mpi-master' into wip-k-fmlpwip-k-fmlp
Conflicts: litmus/sched_cedf.c
Diffstat (limited to 'arch/x86/platform/mrst')
-rw-r--r--arch/x86/platform/mrst/Makefile3
-rw-r--r--arch/x86/platform/mrst/early_printk_mrst.c319
-rw-r--r--arch/x86/platform/mrst/mrst.c811
-rw-r--r--arch/x86/platform/mrst/vrtc.c159
4 files changed, 1292 insertions, 0 deletions
diff --git a/arch/x86/platform/mrst/Makefile b/arch/x86/platform/mrst/Makefile
new file mode 100644
index 000000000000..f61ccdd49341
--- /dev/null
+++ b/arch/x86/platform/mrst/Makefile
@@ -0,0 +1,3 @@
1obj-$(CONFIG_X86_MRST) += mrst.o
2obj-$(CONFIG_X86_MRST) += vrtc.o
3obj-$(CONFIG_EARLY_PRINTK_MRST) += early_printk_mrst.o
diff --git a/arch/x86/platform/mrst/early_printk_mrst.c b/arch/x86/platform/mrst/early_printk_mrst.c
new file mode 100644
index 000000000000..25bfdbb5b130
--- /dev/null
+++ b/arch/x86/platform/mrst/early_printk_mrst.c
@@ -0,0 +1,319 @@
1/*
2 * early_printk_mrst.c - early consoles for Intel MID platforms
3 *
4 * Copyright (c) 2008-2010, Intel Corporation
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; version 2
9 * of the License.
10 */
11
12/*
13 * This file implements two early consoles named mrst and hsu.
14 * mrst is based on Maxim3110 spi-uart device, it exists in both
15 * Moorestown and Medfield platforms, while hsu is based on a High
16 * Speed UART device which only exists in the Medfield platform
17 */
18
19#include <linux/serial_reg.h>
20#include <linux/serial_mfd.h>
21#include <linux/kmsg_dump.h>
22#include <linux/console.h>
23#include <linux/kernel.h>
24#include <linux/delay.h>
25#include <linux/init.h>
26#include <linux/io.h>
27
28#include <asm/fixmap.h>
29#include <asm/pgtable.h>
30#include <asm/mrst.h>
31
32#define MRST_SPI_TIMEOUT 0x200000
33#define MRST_REGBASE_SPI0 0xff128000
34#define MRST_REGBASE_SPI1 0xff128400
35#define MRST_CLK_SPI0_REG 0xff11d86c
36
37/* Bit fields in CTRLR0 */
38#define SPI_DFS_OFFSET 0
39
40#define SPI_FRF_OFFSET 4
41#define SPI_FRF_SPI 0x0
42#define SPI_FRF_SSP 0x1
43#define SPI_FRF_MICROWIRE 0x2
44#define SPI_FRF_RESV 0x3
45
46#define SPI_MODE_OFFSET 6
47#define SPI_SCPH_OFFSET 6
48#define SPI_SCOL_OFFSET 7
49#define SPI_TMOD_OFFSET 8
50#define SPI_TMOD_TR 0x0 /* xmit & recv */
51#define SPI_TMOD_TO 0x1 /* xmit only */
52#define SPI_TMOD_RO 0x2 /* recv only */
53#define SPI_TMOD_EPROMREAD 0x3 /* eeprom read mode */
54
55#define SPI_SLVOE_OFFSET 10
56#define SPI_SRL_OFFSET 11
57#define SPI_CFS_OFFSET 12
58
59/* Bit fields in SR, 7 bits */
60#define SR_MASK 0x7f /* cover 7 bits */
61#define SR_BUSY (1 << 0)
62#define SR_TF_NOT_FULL (1 << 1)
63#define SR_TF_EMPT (1 << 2)
64#define SR_RF_NOT_EMPT (1 << 3)
65#define SR_RF_FULL (1 << 4)
66#define SR_TX_ERR (1 << 5)
67#define SR_DCOL (1 << 6)
68
69struct dw_spi_reg {
70 u32 ctrl0;
71 u32 ctrl1;
72 u32 ssienr;
73 u32 mwcr;
74 u32 ser;
75 u32 baudr;
76 u32 txfltr;
77 u32 rxfltr;
78 u32 txflr;
79 u32 rxflr;
80 u32 sr;
81 u32 imr;
82 u32 isr;
83 u32 risr;
84 u32 txoicr;
85 u32 rxoicr;
86 u32 rxuicr;
87 u32 msticr;
88 u32 icr;
89 u32 dmacr;
90 u32 dmatdlr;
91 u32 dmardlr;
92 u32 idr;
93 u32 version;
94
95 /* Currently operates as 32 bits, though only the low 16 bits matter */
96 u32 dr;
97} __packed;
98
99#define dw_readl(dw, name) __raw_readl(&(dw)->name)
100#define dw_writel(dw, name, val) __raw_writel((val), &(dw)->name)
101
102/* Default use SPI0 register for mrst, we will detect Penwell and use SPI1 */
103static unsigned long mrst_spi_paddr = MRST_REGBASE_SPI0;
104
105static u32 *pclk_spi0;
106/* Always contains an accessible address, start with 0 */
107static struct dw_spi_reg *pspi;
108
109static struct kmsg_dumper dw_dumper;
110static int dumper_registered;
111
112static void dw_kmsg_dump(struct kmsg_dumper *dumper,
113 enum kmsg_dump_reason reason,
114 const char *s1, unsigned long l1,
115 const char *s2, unsigned long l2)
116{
117 int i;
118
119 /* When run to this, we'd better re-init the HW */
120 mrst_early_console_init();
121
122 for (i = 0; i < l1; i++)
123 early_mrst_console.write(&early_mrst_console, s1 + i, 1);
124 for (i = 0; i < l2; i++)
125 early_mrst_console.write(&early_mrst_console, s2 + i, 1);
126}
127
128/* Set the ratio rate to 115200, 8n1, IRQ disabled */
129static void max3110_write_config(void)
130{
131 u16 config;
132
133 config = 0xc001;
134 dw_writel(pspi, dr, config);
135}
136
137/* Translate char to a eligible word and send to max3110 */
138static void max3110_write_data(char c)
139{
140 u16 data;
141
142 data = 0x8000 | c;
143 dw_writel(pspi, dr, data);
144}
145
146void mrst_early_console_init(void)
147{
148 u32 ctrlr0 = 0;
149 u32 spi0_cdiv;
150 u32 freq; /* Freqency info only need be searched once */
151
152 /* Base clk is 100 MHz, the actual clk = 100M / (clk_divider + 1) */
153 pclk_spi0 = (void *)set_fixmap_offset_nocache(FIX_EARLYCON_MEM_BASE,
154 MRST_CLK_SPI0_REG);
155 spi0_cdiv = ((*pclk_spi0) & 0xe00) >> 9;
156 freq = 100000000 / (spi0_cdiv + 1);
157
158 if (mrst_identify_cpu() == MRST_CPU_CHIP_PENWELL)
159 mrst_spi_paddr = MRST_REGBASE_SPI1;
160
161 pspi = (void *)set_fixmap_offset_nocache(FIX_EARLYCON_MEM_BASE,
162 mrst_spi_paddr);
163
164 /* Disable SPI controller */
165 dw_writel(pspi, ssienr, 0);
166
167 /* Set control param, 8 bits, transmit only mode */
168 ctrlr0 = dw_readl(pspi, ctrl0);
169
170 ctrlr0 &= 0xfcc0;
171 ctrlr0 |= 0xf | (SPI_FRF_SPI << SPI_FRF_OFFSET)
172 | (SPI_TMOD_TO << SPI_TMOD_OFFSET);
173 dw_writel(pspi, ctrl0, ctrlr0);
174
175 /*
176 * Change the spi0 clk to comply with 115200 bps, use 100000 to
177 * calculate the clk dividor to make the clock a little slower
178 * than real baud rate.
179 */
180 dw_writel(pspi, baudr, freq/100000);
181
182 /* Disable all INT for early phase */
183 dw_writel(pspi, imr, 0x0);
184
185 /* Set the cs to spi-uart */
186 dw_writel(pspi, ser, 0x2);
187
188 /* Enable the HW, the last step for HW init */
189 dw_writel(pspi, ssienr, 0x1);
190
191 /* Set the default configuration */
192 max3110_write_config();
193
194 /* Register the kmsg dumper */
195 if (!dumper_registered) {
196 dw_dumper.dump = dw_kmsg_dump;
197 kmsg_dump_register(&dw_dumper);
198 dumper_registered = 1;
199 }
200}
201
202/* Slave select should be called in the read/write function */
203static void early_mrst_spi_putc(char c)
204{
205 unsigned int timeout;
206 u32 sr;
207
208 timeout = MRST_SPI_TIMEOUT;
209 /* Early putc needs to make sure the TX FIFO is not full */
210 while (--timeout) {
211 sr = dw_readl(pspi, sr);
212 if (!(sr & SR_TF_NOT_FULL))
213 cpu_relax();
214 else
215 break;
216 }
217
218 if (!timeout)
219 pr_warning("MRST earlycon: timed out\n");
220 else
221 max3110_write_data(c);
222}
223
224/* Early SPI only uses polling mode */
225static void early_mrst_spi_write(struct console *con, const char *str, unsigned n)
226{
227 int i;
228
229 for (i = 0; i < n && *str; i++) {
230 if (*str == '\n')
231 early_mrst_spi_putc('\r');
232 early_mrst_spi_putc(*str);
233 str++;
234 }
235}
236
237struct console early_mrst_console = {
238 .name = "earlymrst",
239 .write = early_mrst_spi_write,
240 .flags = CON_PRINTBUFFER,
241 .index = -1,
242};
243
244/*
245 * Following is the early console based on Medfield HSU (High
246 * Speed UART) device.
247 */
248#define HSU_PORT2_PADDR 0xffa28180
249
250static void __iomem *phsu;
251
252void hsu_early_console_init(void)
253{
254 u8 lcr;
255
256 phsu = (void *)set_fixmap_offset_nocache(FIX_EARLYCON_MEM_BASE,
257 HSU_PORT2_PADDR);
258
259 /* Disable FIFO */
260 writeb(0x0, phsu + UART_FCR);
261
262 /* Set to default 115200 bps, 8n1 */
263 lcr = readb(phsu + UART_LCR);
264 writeb((0x80 | lcr), phsu + UART_LCR);
265 writeb(0x18, phsu + UART_DLL);
266 writeb(lcr, phsu + UART_LCR);
267 writel(0x3600, phsu + UART_MUL*4);
268
269 writeb(0x8, phsu + UART_MCR);
270 writeb(0x7, phsu + UART_FCR);
271 writeb(0x3, phsu + UART_LCR);
272
273 /* Clear IRQ status */
274 readb(phsu + UART_LSR);
275 readb(phsu + UART_RX);
276 readb(phsu + UART_IIR);
277 readb(phsu + UART_MSR);
278
279 /* Enable FIFO */
280 writeb(0x7, phsu + UART_FCR);
281}
282
283#define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
284
285static void early_hsu_putc(char ch)
286{
287 unsigned int timeout = 10000; /* 10ms */
288 u8 status;
289
290 while (--timeout) {
291 status = readb(phsu + UART_LSR);
292 if (status & BOTH_EMPTY)
293 break;
294 udelay(1);
295 }
296
297 /* Only write the char when there was no timeout */
298 if (timeout)
299 writeb(ch, phsu + UART_TX);
300}
301
302static void early_hsu_write(struct console *con, const char *str, unsigned n)
303{
304 int i;
305
306 for (i = 0; i < n && *str; i++) {
307 if (*str == '\n')
308 early_hsu_putc('\r');
309 early_hsu_putc(*str);
310 str++;
311 }
312}
313
314struct console early_hsu_console = {
315 .name = "earlyhsu",
316 .write = early_hsu_write,
317 .flags = CON_PRINTBUFFER,
318 .index = -1,
319};
diff --git a/arch/x86/platform/mrst/mrst.c b/arch/x86/platform/mrst/mrst.c
new file mode 100644
index 000000000000..7000e74b3087
--- /dev/null
+++ b/arch/x86/platform/mrst/mrst.c
@@ -0,0 +1,811 @@
1/*
2 * mrst.c: Intel Moorestown platform specific setup code
3 *
4 * (C) Copyright 2008 Intel Corporation
5 * Author: Jacob Pan (jacob.jun.pan@intel.com)
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; version 2
10 * of the License.
11 */
12
13#define pr_fmt(fmt) "mrst: " fmt
14
15#include <linux/init.h>
16#include <linux/kernel.h>
17#include <linux/sfi.h>
18#include <linux/intel_pmic_gpio.h>
19#include <linux/spi/spi.h>
20#include <linux/i2c.h>
21#include <linux/i2c/pca953x.h>
22#include <linux/gpio_keys.h>
23#include <linux/input.h>
24#include <linux/platform_device.h>
25#include <linux/irq.h>
26#include <linux/module.h>
27
28#include <asm/setup.h>
29#include <asm/mpspec_def.h>
30#include <asm/hw_irq.h>
31#include <asm/apic.h>
32#include <asm/io_apic.h>
33#include <asm/mrst.h>
34#include <asm/mrst-vrtc.h>
35#include <asm/io.h>
36#include <asm/i8259.h>
37#include <asm/intel_scu_ipc.h>
38#include <asm/apb_timer.h>
39#include <asm/reboot.h>
40
41/*
42 * the clockevent devices on Moorestown/Medfield can be APBT or LAPIC clock,
43 * cmdline option x86_mrst_timer can be used to override the configuration
44 * to prefer one or the other.
45 * at runtime, there are basically three timer configurations:
46 * 1. per cpu apbt clock only
47 * 2. per cpu always-on lapic clocks only, this is Penwell/Medfield only
48 * 3. per cpu lapic clock (C3STOP) and one apbt clock, with broadcast.
49 *
50 * by default (without cmdline option), platform code first detects cpu type
51 * to see if we are on lincroft or penwell, then set up both lapic or apbt
52 * clocks accordingly.
53 * i.e. by default, medfield uses configuration #2, moorestown uses #1.
54 * config #3 is supported but not recommended on medfield.
55 *
56 * rating and feature summary:
57 * lapic (with C3STOP) --------- 100
58 * apbt (always-on) ------------ 110
59 * lapic (always-on,ARAT) ------ 150
60 */
61
62__cpuinitdata enum mrst_timer_options mrst_timer_options;
63
64static u32 sfi_mtimer_usage[SFI_MTMR_MAX_NUM];
65static struct sfi_timer_table_entry sfi_mtimer_array[SFI_MTMR_MAX_NUM];
66enum mrst_cpu_type __mrst_cpu_chip;
67EXPORT_SYMBOL_GPL(__mrst_cpu_chip);
68
69int sfi_mtimer_num;
70
71struct sfi_rtc_table_entry sfi_mrtc_array[SFI_MRTC_MAX];
72EXPORT_SYMBOL_GPL(sfi_mrtc_array);
73int sfi_mrtc_num;
74
75/* parse all the mtimer info to a static mtimer array */
76static int __init sfi_parse_mtmr(struct sfi_table_header *table)
77{
78 struct sfi_table_simple *sb;
79 struct sfi_timer_table_entry *pentry;
80 struct mpc_intsrc mp_irq;
81 int totallen;
82
83 sb = (struct sfi_table_simple *)table;
84 if (!sfi_mtimer_num) {
85 sfi_mtimer_num = SFI_GET_NUM_ENTRIES(sb,
86 struct sfi_timer_table_entry);
87 pentry = (struct sfi_timer_table_entry *) sb->pentry;
88 totallen = sfi_mtimer_num * sizeof(*pentry);
89 memcpy(sfi_mtimer_array, pentry, totallen);
90 }
91
92 pr_debug("SFI MTIMER info (num = %d):\n", sfi_mtimer_num);
93 pentry = sfi_mtimer_array;
94 for (totallen = 0; totallen < sfi_mtimer_num; totallen++, pentry++) {
95 pr_debug("timer[%d]: paddr = 0x%08x, freq = %dHz,"
96 " irq = %d\n", totallen, (u32)pentry->phys_addr,
97 pentry->freq_hz, pentry->irq);
98 if (!pentry->irq)
99 continue;
100 mp_irq.type = MP_INTSRC;
101 mp_irq.irqtype = mp_INT;
102/* triggering mode edge bit 2-3, active high polarity bit 0-1 */
103 mp_irq.irqflag = 5;
104 mp_irq.srcbus = MP_BUS_ISA;
105 mp_irq.srcbusirq = pentry->irq; /* IRQ */
106 mp_irq.dstapic = MP_APIC_ALL;
107 mp_irq.dstirq = pentry->irq;
108 mp_save_irq(&mp_irq);
109 }
110
111 return 0;
112}
113
114struct sfi_timer_table_entry *sfi_get_mtmr(int hint)
115{
116 int i;
117 if (hint < sfi_mtimer_num) {
118 if (!sfi_mtimer_usage[hint]) {
119 pr_debug("hint taken for timer %d irq %d\n",\
120 hint, sfi_mtimer_array[hint].irq);
121 sfi_mtimer_usage[hint] = 1;
122 return &sfi_mtimer_array[hint];
123 }
124 }
125 /* take the first timer available */
126 for (i = 0; i < sfi_mtimer_num;) {
127 if (!sfi_mtimer_usage[i]) {
128 sfi_mtimer_usage[i] = 1;
129 return &sfi_mtimer_array[i];
130 }
131 i++;
132 }
133 return NULL;
134}
135
136void sfi_free_mtmr(struct sfi_timer_table_entry *mtmr)
137{
138 int i;
139 for (i = 0; i < sfi_mtimer_num;) {
140 if (mtmr->irq == sfi_mtimer_array[i].irq) {
141 sfi_mtimer_usage[i] = 0;
142 return;
143 }
144 i++;
145 }
146}
147
148/* parse all the mrtc info to a global mrtc array */
149int __init sfi_parse_mrtc(struct sfi_table_header *table)
150{
151 struct sfi_table_simple *sb;
152 struct sfi_rtc_table_entry *pentry;
153 struct mpc_intsrc mp_irq;
154
155 int totallen;
156
157 sb = (struct sfi_table_simple *)table;
158 if (!sfi_mrtc_num) {
159 sfi_mrtc_num = SFI_GET_NUM_ENTRIES(sb,
160 struct sfi_rtc_table_entry);
161 pentry = (struct sfi_rtc_table_entry *)sb->pentry;
162 totallen = sfi_mrtc_num * sizeof(*pentry);
163 memcpy(sfi_mrtc_array, pentry, totallen);
164 }
165
166 pr_debug("SFI RTC info (num = %d):\n", sfi_mrtc_num);
167 pentry = sfi_mrtc_array;
168 for (totallen = 0; totallen < sfi_mrtc_num; totallen++, pentry++) {
169 pr_debug("RTC[%d]: paddr = 0x%08x, irq = %d\n",
170 totallen, (u32)pentry->phys_addr, pentry->irq);
171 mp_irq.type = MP_INTSRC;
172 mp_irq.irqtype = mp_INT;
173 mp_irq.irqflag = 0xf; /* level trigger and active low */
174 mp_irq.srcbus = MP_BUS_ISA;
175 mp_irq.srcbusirq = pentry->irq; /* IRQ */
176 mp_irq.dstapic = MP_APIC_ALL;
177 mp_irq.dstirq = pentry->irq;
178 mp_save_irq(&mp_irq);
179 }
180 return 0;
181}
182
183static unsigned long __init mrst_calibrate_tsc(void)
184{
185 unsigned long flags, fast_calibrate;
186
187 local_irq_save(flags);
188 fast_calibrate = apbt_quick_calibrate();
189 local_irq_restore(flags);
190
191 if (fast_calibrate)
192 return fast_calibrate;
193
194 return 0;
195}
196
197static void __init mrst_time_init(void)
198{
199 sfi_table_parse(SFI_SIG_MTMR, NULL, NULL, sfi_parse_mtmr);
200 switch (mrst_timer_options) {
201 case MRST_TIMER_APBT_ONLY:
202 break;
203 case MRST_TIMER_LAPIC_APBT:
204 x86_init.timers.setup_percpu_clockev = setup_boot_APIC_clock;
205 x86_cpuinit.setup_percpu_clockev = setup_secondary_APIC_clock;
206 break;
207 default:
208 if (!boot_cpu_has(X86_FEATURE_ARAT))
209 break;
210 x86_init.timers.setup_percpu_clockev = setup_boot_APIC_clock;
211 x86_cpuinit.setup_percpu_clockev = setup_secondary_APIC_clock;
212 return;
213 }
214 /* we need at least one APB timer */
215 pre_init_apic_IRQ0();
216 apbt_time_init();
217}
218
219static void __cpuinit mrst_arch_setup(void)
220{
221 if (boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model == 0x27)
222 __mrst_cpu_chip = MRST_CPU_CHIP_PENWELL;
223 else if (boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model == 0x26)
224 __mrst_cpu_chip = MRST_CPU_CHIP_LINCROFT;
225 else {
226 pr_err("Unknown Moorestown CPU (%d:%d), default to Lincroft\n",
227 boot_cpu_data.x86, boot_cpu_data.x86_model);
228 __mrst_cpu_chip = MRST_CPU_CHIP_LINCROFT;
229 }
230 pr_debug("Moorestown CPU %s identified\n",
231 (__mrst_cpu_chip == MRST_CPU_CHIP_LINCROFT) ?
232 "Lincroft" : "Penwell");
233}
234
235/* MID systems don't have i8042 controller */
236static int mrst_i8042_detect(void)
237{
238 return 0;
239}
240
241/* Reboot and power off are handled by the SCU on a MID device */
242static void mrst_power_off(void)
243{
244 intel_scu_ipc_simple_command(0xf1, 1);
245}
246
247static void mrst_reboot(void)
248{
249 intel_scu_ipc_simple_command(0xf1, 0);
250}
251
252/*
253 * Moorestown specific x86_init function overrides and early setup
254 * calls.
255 */
256void __init x86_mrst_early_setup(void)
257{
258 x86_init.resources.probe_roms = x86_init_noop;
259 x86_init.resources.reserve_resources = x86_init_noop;
260
261 x86_init.timers.timer_init = mrst_time_init;
262 x86_init.timers.setup_percpu_clockev = x86_init_noop;
263
264 x86_init.irqs.pre_vector_init = x86_init_noop;
265
266 x86_init.oem.arch_setup = mrst_arch_setup;
267
268 x86_cpuinit.setup_percpu_clockev = apbt_setup_secondary_clock;
269
270 x86_platform.calibrate_tsc = mrst_calibrate_tsc;
271 x86_platform.i8042_detect = mrst_i8042_detect;
272 x86_init.timers.wallclock_init = mrst_rtc_init;
273 x86_init.pci.init = pci_mrst_init;
274 x86_init.pci.fixup_irqs = x86_init_noop;
275
276 legacy_pic = &null_legacy_pic;
277
278 /* Moorestown specific power_off/restart method */
279 pm_power_off = mrst_power_off;
280 machine_ops.emergency_restart = mrst_reboot;
281
282 /* Avoid searching for BIOS MP tables */
283 x86_init.mpparse.find_smp_config = x86_init_noop;
284 x86_init.mpparse.get_smp_config = x86_init_uint_noop;
285 set_bit(MP_BUS_ISA, mp_bus_not_pci);
286}
287
288/*
289 * if user does not want to use per CPU apb timer, just give it a lower rating
290 * than local apic timer and skip the late per cpu timer init.
291 */
292static inline int __init setup_x86_mrst_timer(char *arg)
293{
294 if (!arg)
295 return -EINVAL;
296
297 if (strcmp("apbt_only", arg) == 0)
298 mrst_timer_options = MRST_TIMER_APBT_ONLY;
299 else if (strcmp("lapic_and_apbt", arg) == 0)
300 mrst_timer_options = MRST_TIMER_LAPIC_APBT;
301 else {
302 pr_warning("X86 MRST timer option %s not recognised"
303 " use x86_mrst_timer=apbt_only or lapic_and_apbt\n",
304 arg);
305 return -EINVAL;
306 }
307 return 0;
308}
309__setup("x86_mrst_timer=", setup_x86_mrst_timer);
310
311/*
312 * Parsing GPIO table first, since the DEVS table will need this table
313 * to map the pin name to the actual pin.
314 */
315static struct sfi_gpio_table_entry *gpio_table;
316static int gpio_num_entry;
317
318static int __init sfi_parse_gpio(struct sfi_table_header *table)
319{
320 struct sfi_table_simple *sb;
321 struct sfi_gpio_table_entry *pentry;
322 int num, i;
323
324 if (gpio_table)
325 return 0;
326 sb = (struct sfi_table_simple *)table;
327 num = SFI_GET_NUM_ENTRIES(sb, struct sfi_gpio_table_entry);
328 pentry = (struct sfi_gpio_table_entry *)sb->pentry;
329
330 gpio_table = (struct sfi_gpio_table_entry *)
331 kmalloc(num * sizeof(*pentry), GFP_KERNEL);
332 if (!gpio_table)
333 return -1;
334 memcpy(gpio_table, pentry, num * sizeof(*pentry));
335 gpio_num_entry = num;
336
337 pr_debug("GPIO pin info:\n");
338 for (i = 0; i < num; i++, pentry++)
339 pr_debug("info[%2d]: controller = %16.16s, pin_name = %16.16s,"
340 " pin = %d\n", i,
341 pentry->controller_name,
342 pentry->pin_name,
343 pentry->pin_no);
344 return 0;
345}
346
347static int get_gpio_by_name(const char *name)
348{
349 struct sfi_gpio_table_entry *pentry = gpio_table;
350 int i;
351
352 if (!pentry)
353 return -1;
354 for (i = 0; i < gpio_num_entry; i++, pentry++) {
355 if (!strncmp(name, pentry->pin_name, SFI_NAME_LEN))
356 return pentry->pin_no;
357 }
358 return -1;
359}
360
361/*
362 * Here defines the array of devices platform data that IAFW would export
363 * through SFI "DEVS" table, we use name and type to match the device and
364 * its platform data.
365 */
366struct devs_id {
367 char name[SFI_NAME_LEN + 1];
368 u8 type;
369 u8 delay;
370 void *(*get_platform_data)(void *info);
371};
372
373/* the offset for the mapping of global gpio pin to irq */
374#define MRST_IRQ_OFFSET 0x100
375
376static void __init *pmic_gpio_platform_data(void *info)
377{
378 static struct intel_pmic_gpio_platform_data pmic_gpio_pdata;
379 int gpio_base = get_gpio_by_name("pmic_gpio_base");
380
381 if (gpio_base == -1)
382 gpio_base = 64;
383 pmic_gpio_pdata.gpio_base = gpio_base;
384 pmic_gpio_pdata.irq_base = gpio_base + MRST_IRQ_OFFSET;
385 pmic_gpio_pdata.gpiointr = 0xffffeff8;
386
387 return &pmic_gpio_pdata;
388}
389
390static void __init *max3111_platform_data(void *info)
391{
392 struct spi_board_info *spi_info = info;
393 int intr = get_gpio_by_name("max3111_int");
394
395 if (intr == -1)
396 return NULL;
397 spi_info->irq = intr + MRST_IRQ_OFFSET;
398 return NULL;
399}
400
401/* we have multiple max7315 on the board ... */
402#define MAX7315_NUM 2
403static void __init *max7315_platform_data(void *info)
404{
405 static struct pca953x_platform_data max7315_pdata[MAX7315_NUM];
406 static int nr;
407 struct pca953x_platform_data *max7315 = &max7315_pdata[nr];
408 struct i2c_board_info *i2c_info = info;
409 int gpio_base, intr;
410 char base_pin_name[SFI_NAME_LEN + 1];
411 char intr_pin_name[SFI_NAME_LEN + 1];
412
413 if (nr == MAX7315_NUM) {
414 pr_err("too many max7315s, we only support %d\n",
415 MAX7315_NUM);
416 return NULL;
417 }
418 /* we have several max7315 on the board, we only need load several
419 * instances of the same pca953x driver to cover them
420 */
421 strcpy(i2c_info->type, "max7315");
422 if (nr++) {
423 sprintf(base_pin_name, "max7315_%d_base", nr);
424 sprintf(intr_pin_name, "max7315_%d_int", nr);
425 } else {
426 strcpy(base_pin_name, "max7315_base");
427 strcpy(intr_pin_name, "max7315_int");
428 }
429
430 gpio_base = get_gpio_by_name(base_pin_name);
431 intr = get_gpio_by_name(intr_pin_name);
432
433 if (gpio_base == -1)
434 return NULL;
435 max7315->gpio_base = gpio_base;
436 if (intr != -1) {
437 i2c_info->irq = intr + MRST_IRQ_OFFSET;
438 max7315->irq_base = gpio_base + MRST_IRQ_OFFSET;
439 } else {
440 i2c_info->irq = -1;
441 max7315->irq_base = -1;
442 }
443 return max7315;
444}
445
446static void __init *emc1403_platform_data(void *info)
447{
448 static short intr2nd_pdata;
449 struct i2c_board_info *i2c_info = info;
450 int intr = get_gpio_by_name("thermal_int");
451 int intr2nd = get_gpio_by_name("thermal_alert");
452
453 if (intr == -1 || intr2nd == -1)
454 return NULL;
455
456 i2c_info->irq = intr + MRST_IRQ_OFFSET;
457 intr2nd_pdata = intr2nd + MRST_IRQ_OFFSET;
458
459 return &intr2nd_pdata;
460}
461
462static void __init *lis331dl_platform_data(void *info)
463{
464 static short intr2nd_pdata;
465 struct i2c_board_info *i2c_info = info;
466 int intr = get_gpio_by_name("accel_int");
467 int intr2nd = get_gpio_by_name("accel_2");
468
469 if (intr == -1 || intr2nd == -1)
470 return NULL;
471
472 i2c_info->irq = intr + MRST_IRQ_OFFSET;
473 intr2nd_pdata = intr2nd + MRST_IRQ_OFFSET;
474
475 return &intr2nd_pdata;
476}
477
478static void __init *no_platform_data(void *info)
479{
480 return NULL;
481}
482
483static const struct devs_id __initconst device_ids[] = {
484 {"pmic_gpio", SFI_DEV_TYPE_SPI, 1, &pmic_gpio_platform_data},
485 {"spi_max3111", SFI_DEV_TYPE_SPI, 0, &max3111_platform_data},
486 {"i2c_max7315", SFI_DEV_TYPE_I2C, 1, &max7315_platform_data},
487 {"i2c_max7315_2", SFI_DEV_TYPE_I2C, 1, &max7315_platform_data},
488 {"emc1403", SFI_DEV_TYPE_I2C, 1, &emc1403_platform_data},
489 {"i2c_accel", SFI_DEV_TYPE_I2C, 0, &lis331dl_platform_data},
490 {"pmic_audio", SFI_DEV_TYPE_IPC, 1, &no_platform_data},
491 {"msic_audio", SFI_DEV_TYPE_IPC, 1, &no_platform_data},
492 {},
493};
494
495#define MAX_IPCDEVS 24
496static struct platform_device *ipc_devs[MAX_IPCDEVS];
497static int ipc_next_dev;
498
499#define MAX_SCU_SPI 24
500static struct spi_board_info *spi_devs[MAX_SCU_SPI];
501static int spi_next_dev;
502
503#define MAX_SCU_I2C 24
504static struct i2c_board_info *i2c_devs[MAX_SCU_I2C];
505static int i2c_bus[MAX_SCU_I2C];
506static int i2c_next_dev;
507
508static void __init intel_scu_device_register(struct platform_device *pdev)
509{
510 if(ipc_next_dev == MAX_IPCDEVS)
511 pr_err("too many SCU IPC devices");
512 else
513 ipc_devs[ipc_next_dev++] = pdev;
514}
515
516static void __init intel_scu_spi_device_register(struct spi_board_info *sdev)
517{
518 struct spi_board_info *new_dev;
519
520 if (spi_next_dev == MAX_SCU_SPI) {
521 pr_err("too many SCU SPI devices");
522 return;
523 }
524
525 new_dev = kzalloc(sizeof(*sdev), GFP_KERNEL);
526 if (!new_dev) {
527 pr_err("failed to alloc mem for delayed spi dev %s\n",
528 sdev->modalias);
529 return;
530 }
531 memcpy(new_dev, sdev, sizeof(*sdev));
532
533 spi_devs[spi_next_dev++] = new_dev;
534}
535
536static void __init intel_scu_i2c_device_register(int bus,
537 struct i2c_board_info *idev)
538{
539 struct i2c_board_info *new_dev;
540
541 if (i2c_next_dev == MAX_SCU_I2C) {
542 pr_err("too many SCU I2C devices");
543 return;
544 }
545
546 new_dev = kzalloc(sizeof(*idev), GFP_KERNEL);
547 if (!new_dev) {
548 pr_err("failed to alloc mem for delayed i2c dev %s\n",
549 idev->type);
550 return;
551 }
552 memcpy(new_dev, idev, sizeof(*idev));
553
554 i2c_bus[i2c_next_dev] = bus;
555 i2c_devs[i2c_next_dev++] = new_dev;
556}
557
558/* Called by IPC driver */
559void intel_scu_devices_create(void)
560{
561 int i;
562
563 for (i = 0; i < ipc_next_dev; i++)
564 platform_device_add(ipc_devs[i]);
565
566 for (i = 0; i < spi_next_dev; i++)
567 spi_register_board_info(spi_devs[i], 1);
568
569 for (i = 0; i < i2c_next_dev; i++) {
570 struct i2c_adapter *adapter;
571 struct i2c_client *client;
572
573 adapter = i2c_get_adapter(i2c_bus[i]);
574 if (adapter) {
575 client = i2c_new_device(adapter, i2c_devs[i]);
576 if (!client)
577 pr_err("can't create i2c device %s\n",
578 i2c_devs[i]->type);
579 } else
580 i2c_register_board_info(i2c_bus[i], i2c_devs[i], 1);
581 }
582}
583EXPORT_SYMBOL_GPL(intel_scu_devices_create);
584
585/* Called by IPC driver */
586void intel_scu_devices_destroy(void)
587{
588 int i;
589
590 for (i = 0; i < ipc_next_dev; i++)
591 platform_device_del(ipc_devs[i]);
592}
593EXPORT_SYMBOL_GPL(intel_scu_devices_destroy);
594
595static void __init install_irq_resource(struct platform_device *pdev, int irq)
596{
597 /* Single threaded */
598 static struct resource __initdata res = {
599 .name = "IRQ",
600 .flags = IORESOURCE_IRQ,
601 };
602 res.start = irq;
603 platform_device_add_resources(pdev, &res, 1);
604}
605
606static void __init sfi_handle_ipc_dev(struct platform_device *pdev)
607{
608 const struct devs_id *dev = device_ids;
609 void *pdata = NULL;
610
611 while (dev->name[0]) {
612 if (dev->type == SFI_DEV_TYPE_IPC &&
613 !strncmp(dev->name, pdev->name, SFI_NAME_LEN)) {
614 pdata = dev->get_platform_data(pdev);
615 break;
616 }
617 dev++;
618 }
619 pdev->dev.platform_data = pdata;
620 intel_scu_device_register(pdev);
621}
622
623static void __init sfi_handle_spi_dev(struct spi_board_info *spi_info)
624{
625 const struct devs_id *dev = device_ids;
626 void *pdata = NULL;
627
628 while (dev->name[0]) {
629 if (dev->type == SFI_DEV_TYPE_SPI &&
630 !strncmp(dev->name, spi_info->modalias, SFI_NAME_LEN)) {
631 pdata = dev->get_platform_data(spi_info);
632 break;
633 }
634 dev++;
635 }
636 spi_info->platform_data = pdata;
637 if (dev->delay)
638 intel_scu_spi_device_register(spi_info);
639 else
640 spi_register_board_info(spi_info, 1);
641}
642
643static void __init sfi_handle_i2c_dev(int bus, struct i2c_board_info *i2c_info)
644{
645 const struct devs_id *dev = device_ids;
646 void *pdata = NULL;
647
648 while (dev->name[0]) {
649 if (dev->type == SFI_DEV_TYPE_I2C &&
650 !strncmp(dev->name, i2c_info->type, SFI_NAME_LEN)) {
651 pdata = dev->get_platform_data(i2c_info);
652 break;
653 }
654 dev++;
655 }
656 i2c_info->platform_data = pdata;
657
658 if (dev->delay)
659 intel_scu_i2c_device_register(bus, i2c_info);
660 else
661 i2c_register_board_info(bus, i2c_info, 1);
662 }
663
664
665static int __init sfi_parse_devs(struct sfi_table_header *table)
666{
667 struct sfi_table_simple *sb;
668 struct sfi_device_table_entry *pentry;
669 struct spi_board_info spi_info;
670 struct i2c_board_info i2c_info;
671 struct platform_device *pdev;
672 int num, i, bus;
673 int ioapic;
674 struct io_apic_irq_attr irq_attr;
675
676 sb = (struct sfi_table_simple *)table;
677 num = SFI_GET_NUM_ENTRIES(sb, struct sfi_device_table_entry);
678 pentry = (struct sfi_device_table_entry *)sb->pentry;
679
680 for (i = 0; i < num; i++, pentry++) {
681 if (pentry->irq != (u8)0xff) { /* native RTE case */
682 /* these SPI2 devices are not exposed to system as PCI
683 * devices, but they have separate RTE entry in IOAPIC
684 * so we have to enable them one by one here
685 */
686 ioapic = mp_find_ioapic(pentry->irq);
687 irq_attr.ioapic = ioapic;
688 irq_attr.ioapic_pin = pentry->irq;
689 irq_attr.trigger = 1;
690 irq_attr.polarity = 1;
691 io_apic_set_pci_routing(NULL, pentry->irq, &irq_attr);
692 }
693 switch (pentry->type) {
694 case SFI_DEV_TYPE_IPC:
695 /* ID as IRQ is a hack that will go away */
696 pdev = platform_device_alloc(pentry->name, pentry->irq);
697 if (pdev == NULL) {
698 pr_err("out of memory for SFI platform device '%s'.\n",
699 pentry->name);
700 continue;
701 }
702 install_irq_resource(pdev, pentry->irq);
703 pr_debug("info[%2d]: IPC bus, name = %16.16s, "
704 "irq = 0x%2x\n", i, pentry->name, pentry->irq);
705 sfi_handle_ipc_dev(pdev);
706 break;
707 case SFI_DEV_TYPE_SPI:
708 memset(&spi_info, 0, sizeof(spi_info));
709 strncpy(spi_info.modalias, pentry->name, SFI_NAME_LEN);
710 spi_info.irq = pentry->irq;
711 spi_info.bus_num = pentry->host_num;
712 spi_info.chip_select = pentry->addr;
713 spi_info.max_speed_hz = pentry->max_freq;
714 pr_debug("info[%2d]: SPI bus = %d, name = %16.16s, "
715 "irq = 0x%2x, max_freq = %d, cs = %d\n", i,
716 spi_info.bus_num,
717 spi_info.modalias,
718 spi_info.irq,
719 spi_info.max_speed_hz,
720 spi_info.chip_select);
721 sfi_handle_spi_dev(&spi_info);
722 break;
723 case SFI_DEV_TYPE_I2C:
724 memset(&i2c_info, 0, sizeof(i2c_info));
725 bus = pentry->host_num;
726 strncpy(i2c_info.type, pentry->name, SFI_NAME_LEN);
727 i2c_info.irq = pentry->irq;
728 i2c_info.addr = pentry->addr;
729 pr_debug("info[%2d]: I2C bus = %d, name = %16.16s, "
730 "irq = 0x%2x, addr = 0x%x\n", i, bus,
731 i2c_info.type,
732 i2c_info.irq,
733 i2c_info.addr);
734 sfi_handle_i2c_dev(bus, &i2c_info);
735 break;
736 case SFI_DEV_TYPE_UART:
737 case SFI_DEV_TYPE_HSI:
738 default:
739 ;
740 }
741 }
742 return 0;
743}
744
745static int __init mrst_platform_init(void)
746{
747 sfi_table_parse(SFI_SIG_GPIO, NULL, NULL, sfi_parse_gpio);
748 sfi_table_parse(SFI_SIG_DEVS, NULL, NULL, sfi_parse_devs);
749 return 0;
750}
751arch_initcall(mrst_platform_init);
752
753/*
754 * we will search these buttons in SFI GPIO table (by name)
755 * and register them dynamically. Please add all possible
756 * buttons here, we will shrink them if no GPIO found.
757 */
758static struct gpio_keys_button gpio_button[] = {
759 {KEY_POWER, -1, 1, "power_btn", EV_KEY, 0, 3000},
760 {KEY_PROG1, -1, 1, "prog_btn1", EV_KEY, 0, 20},
761 {KEY_PROG2, -1, 1, "prog_btn2", EV_KEY, 0, 20},
762 {SW_LID, -1, 1, "lid_switch", EV_SW, 0, 20},
763 {KEY_VOLUMEUP, -1, 1, "vol_up", EV_KEY, 0, 20},
764 {KEY_VOLUMEDOWN, -1, 1, "vol_down", EV_KEY, 0, 20},
765 {KEY_CAMERA, -1, 1, "camera_full", EV_KEY, 0, 20},
766 {KEY_CAMERA_FOCUS, -1, 1, "camera_half", EV_KEY, 0, 20},
767 {SW_KEYPAD_SLIDE, -1, 1, "MagSw1", EV_SW, 0, 20},
768 {SW_KEYPAD_SLIDE, -1, 1, "MagSw2", EV_SW, 0, 20},
769};
770
771static struct gpio_keys_platform_data mrst_gpio_keys = {
772 .buttons = gpio_button,
773 .rep = 1,
774 .nbuttons = -1, /* will fill it after search */
775};
776
777static struct platform_device pb_device = {
778 .name = "gpio-keys",
779 .id = -1,
780 .dev = {
781 .platform_data = &mrst_gpio_keys,
782 },
783};
784
785/*
786 * Shrink the non-existent buttons, register the gpio button
787 * device if there is some
788 */
789static int __init pb_keys_init(void)
790{
791 struct gpio_keys_button *gb = gpio_button;
792 int i, num, good = 0;
793
794 num = sizeof(gpio_button) / sizeof(struct gpio_keys_button);
795 for (i = 0; i < num; i++) {
796 gb[i].gpio = get_gpio_by_name(gb[i].desc);
797 if (gb[i].gpio == -1)
798 continue;
799
800 if (i != good)
801 gb[good] = gb[i];
802 good++;
803 }
804
805 if (good) {
806 mrst_gpio_keys.nbuttons = good;
807 return platform_device_register(&pb_device);
808 }
809 return 0;
810}
811late_initcall(pb_keys_init);
diff --git a/arch/x86/platform/mrst/vrtc.c b/arch/x86/platform/mrst/vrtc.c
new file mode 100644
index 000000000000..73d70d65e76e
--- /dev/null
+++ b/arch/x86/platform/mrst/vrtc.c
@@ -0,0 +1,159 @@
1/*
2 * vrtc.c: Driver for virtual RTC device on Intel MID platform
3 *
4 * (C) Copyright 2009 Intel Corporation
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; version 2
9 * of the License.
10 *
11 * Note:
12 * VRTC is emulated by system controller firmware, the real HW
13 * RTC is located in the PMIC device. SCU FW shadows PMIC RTC
14 * in a memory mapped IO space that is visible to the host IA
15 * processor.
16 *
17 * This driver is based on RTC CMOS driver.
18 */
19
20#include <linux/kernel.h>
21#include <linux/init.h>
22#include <linux/sfi.h>
23#include <linux/platform_device.h>
24
25#include <asm/mrst.h>
26#include <asm/mrst-vrtc.h>
27#include <asm/time.h>
28#include <asm/fixmap.h>
29
30static unsigned char __iomem *vrtc_virt_base;
31
32unsigned char vrtc_cmos_read(unsigned char reg)
33{
34 unsigned char retval;
35
36 /* vRTC's registers range from 0x0 to 0xD */
37 if (reg > 0xd || !vrtc_virt_base)
38 return 0xff;
39
40 lock_cmos_prefix(reg);
41 retval = __raw_readb(vrtc_virt_base + (reg << 2));
42 lock_cmos_suffix(reg);
43 return retval;
44}
45EXPORT_SYMBOL_GPL(vrtc_cmos_read);
46
47void vrtc_cmos_write(unsigned char val, unsigned char reg)
48{
49 if (reg > 0xd || !vrtc_virt_base)
50 return;
51
52 lock_cmos_prefix(reg);
53 __raw_writeb(val, vrtc_virt_base + (reg << 2));
54 lock_cmos_suffix(reg);
55}
56EXPORT_SYMBOL_GPL(vrtc_cmos_write);
57
58unsigned long vrtc_get_time(void)
59{
60 u8 sec, min, hour, mday, mon;
61 u32 year;
62
63 while ((vrtc_cmos_read(RTC_FREQ_SELECT) & RTC_UIP))
64 cpu_relax();
65
66 sec = vrtc_cmos_read(RTC_SECONDS);
67 min = vrtc_cmos_read(RTC_MINUTES);
68 hour = vrtc_cmos_read(RTC_HOURS);
69 mday = vrtc_cmos_read(RTC_DAY_OF_MONTH);
70 mon = vrtc_cmos_read(RTC_MONTH);
71 year = vrtc_cmos_read(RTC_YEAR);
72
73 /* vRTC YEAR reg contains the offset to 1960 */
74 year += 1960;
75
76 printk(KERN_INFO "vRTC: sec: %d min: %d hour: %d day: %d "
77 "mon: %d year: %d\n", sec, min, hour, mday, mon, year);
78
79 return mktime(year, mon, mday, hour, min, sec);
80}
81
82/* Only care about the minutes and seconds */
83int vrtc_set_mmss(unsigned long nowtime)
84{
85 int real_sec, real_min;
86 int vrtc_min;
87
88 vrtc_min = vrtc_cmos_read(RTC_MINUTES);
89
90 real_sec = nowtime % 60;
91 real_min = nowtime / 60;
92 if (((abs(real_min - vrtc_min) + 15)/30) & 1)
93 real_min += 30;
94 real_min %= 60;
95
96 vrtc_cmos_write(real_sec, RTC_SECONDS);
97 vrtc_cmos_write(real_min, RTC_MINUTES);
98 return 0;
99}
100
101void __init mrst_rtc_init(void)
102{
103 unsigned long vrtc_paddr;
104
105 sfi_table_parse(SFI_SIG_MRTC, NULL, NULL, sfi_parse_mrtc);
106
107 vrtc_paddr = sfi_mrtc_array[0].phys_addr;
108 if (!sfi_mrtc_num || !vrtc_paddr)
109 return;
110
111 vrtc_virt_base = (void __iomem *)set_fixmap_offset_nocache(FIX_LNW_VRTC,
112 vrtc_paddr);
113 x86_platform.get_wallclock = vrtc_get_time;
114 x86_platform.set_wallclock = vrtc_set_mmss;
115}
116
117/*
118 * The Moorestown platform has a memory mapped virtual RTC device that emulates
119 * the programming interface of the RTC.
120 */
121
122static struct resource vrtc_resources[] = {
123 [0] = {
124 .flags = IORESOURCE_MEM,
125 },
126 [1] = {
127 .flags = IORESOURCE_IRQ,
128 }
129};
130
131static struct platform_device vrtc_device = {
132 .name = "rtc_mrst",
133 .id = -1,
134 .resource = vrtc_resources,
135 .num_resources = ARRAY_SIZE(vrtc_resources),
136};
137
138/* Register the RTC device if appropriate */
139static int __init mrst_device_create(void)
140{
141 /* No Moorestown, no device */
142 if (!mrst_identify_cpu())
143 return -ENODEV;
144 /* No timer, no device */
145 if (!sfi_mrtc_num)
146 return -ENODEV;
147
148 /* iomem resource */
149 vrtc_resources[0].start = sfi_mrtc_array[0].phys_addr;
150 vrtc_resources[0].end = sfi_mrtc_array[0].phys_addr +
151 MRST_VRTC_MAP_SZ;
152 /* irq resource */
153 vrtc_resources[1].start = sfi_mrtc_array[0].irq;
154 vrtc_resources[1].end = sfi_mrtc_array[0].irq;
155
156 return platform_device_register(&vrtc_device);
157}
158
159module_init(mrst_device_create);