diff options
author | Andi Kleen <ak@suse.de> | 2008-02-04 10:48:03 -0500 |
---|---|---|
committer | Ingo Molnar <mingo@elte.hu> | 2008-02-04 10:48:03 -0500 |
commit | c7e844f0415252c7e1a2153a97e7a0c511d61ada (patch) | |
tree | 7d8a503b4112ba50a35b2d731b86803935507756 /arch/x86/pci | |
parent | fa0c864d998c9c97d11db097d5736028d5c80985 (diff) |
x86: move NUMAQ io handling into arch/x86/pci/numa.c
numa.c is the only user of the {in,out}*_quad functions. And it has only a few call
sites. Change them to open code the magic NUMAQ port access.
Signed-off-by: Andi Kleen <ak@suse.de>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Diffstat (limited to 'arch/x86/pci')
-rw-r--r-- | arch/x86/pci/numa.c | 52 |
1 files changed, 44 insertions, 8 deletions
diff --git a/arch/x86/pci/numa.c b/arch/x86/pci/numa.c index f5f165f69e0c..55270c26237c 100644 --- a/arch/x86/pci/numa.c +++ b/arch/x86/pci/numa.c | |||
@@ -5,36 +5,62 @@ | |||
5 | #include <linux/pci.h> | 5 | #include <linux/pci.h> |
6 | #include <linux/init.h> | 6 | #include <linux/init.h> |
7 | #include <linux/nodemask.h> | 7 | #include <linux/nodemask.h> |
8 | #include <mach_apic.h> | ||
8 | #include "pci.h" | 9 | #include "pci.h" |
9 | 10 | ||
11 | #define XQUAD_PORTIO_BASE 0xfe400000 | ||
12 | #define XQUAD_PORTIO_QUAD 0x40000 /* 256k per quad. */ | ||
13 | |||
10 | #define BUS2QUAD(global) (mp_bus_id_to_node[global]) | 14 | #define BUS2QUAD(global) (mp_bus_id_to_node[global]) |
11 | #define BUS2LOCAL(global) (mp_bus_id_to_local[global]) | 15 | #define BUS2LOCAL(global) (mp_bus_id_to_local[global]) |
12 | #define QUADLOCAL2BUS(quad,local) (quad_local_to_mp_bus_id[quad][local]) | 16 | #define QUADLOCAL2BUS(quad,local) (quad_local_to_mp_bus_id[quad][local]) |
13 | 17 | ||
18 | extern void *xquad_portio; /* Where the IO area was mapped */ | ||
19 | #define XQUAD_PORT_ADDR(port, quad) (xquad_portio + (XQUAD_PORTIO_QUAD*quad) + port) | ||
20 | |||
14 | #define PCI_CONF1_MQ_ADDRESS(bus, devfn, reg) \ | 21 | #define PCI_CONF1_MQ_ADDRESS(bus, devfn, reg) \ |
15 | (0x80000000 | (BUS2LOCAL(bus) << 16) | (devfn << 8) | (reg & ~3)) | 22 | (0x80000000 | (BUS2LOCAL(bus) << 16) | (devfn << 8) | (reg & ~3)) |
16 | 23 | ||
24 | static void write_cf8(unsigned bus, unsigned devfn, unsigned reg) | ||
25 | { | ||
26 | unsigned val = PCI_CONF1_MQ_ADDRESS(bus, devfn, reg); | ||
27 | if (xquad_portio) | ||
28 | writel(val, XQUAD_PORT_ADDR(0xcf8, BUS2QUAD(bus))); | ||
29 | else | ||
30 | outl(val, 0xCF8); | ||
31 | } | ||
32 | |||
17 | static int pci_conf1_mq_read(unsigned int seg, unsigned int bus, | 33 | static int pci_conf1_mq_read(unsigned int seg, unsigned int bus, |
18 | unsigned int devfn, int reg, int len, u32 *value) | 34 | unsigned int devfn, int reg, int len, u32 *value) |
19 | { | 35 | { |
20 | unsigned long flags; | 36 | unsigned long flags; |
37 | void *adr __iomem = XQUAD_PORT_ADDR(0xcfc, BUS2QUAD(bus)); | ||
21 | 38 | ||
22 | if (!value || (bus >= MAX_MP_BUSSES) || (devfn > 255) || (reg > 255)) | 39 | if (!value || (bus >= MAX_MP_BUSSES) || (devfn > 255) || (reg > 255)) |
23 | return -EINVAL; | 40 | return -EINVAL; |
24 | 41 | ||
25 | spin_lock_irqsave(&pci_config_lock, flags); | 42 | spin_lock_irqsave(&pci_config_lock, flags); |
26 | 43 | ||
27 | outl_quad(PCI_CONF1_MQ_ADDRESS(bus, devfn, reg), 0xCF8, BUS2QUAD(bus)); | 44 | write_cf8(bus, devfn, reg); |
28 | 45 | ||
29 | switch (len) { | 46 | switch (len) { |
30 | case 1: | 47 | case 1: |
31 | *value = inb_quad(0xCFC + (reg & 3), BUS2QUAD(bus)); | 48 | if (xquad_portio) |
49 | *value = readb(adr + (reg & 3)); | ||
50 | else | ||
51 | *value = inb(0xCFC + (reg & 3)); | ||
32 | break; | 52 | break; |
33 | case 2: | 53 | case 2: |
34 | *value = inw_quad(0xCFC + (reg & 2), BUS2QUAD(bus)); | 54 | if (xquad_portio) |
55 | *value = readw(adr + (reg & 2)); | ||
56 | else | ||
57 | *value = inw(0xCFC + (reg & 2)); | ||
35 | break; | 58 | break; |
36 | case 4: | 59 | case 4: |
37 | *value = inl_quad(0xCFC, BUS2QUAD(bus)); | 60 | if (xquad_portio) |
61 | *value = readl(adr); | ||
62 | else | ||
63 | *value = inl(0xCFC); | ||
38 | break; | 64 | break; |
39 | } | 65 | } |
40 | 66 | ||
@@ -47,23 +73,33 @@ static int pci_conf1_mq_write(unsigned int seg, unsigned int bus, | |||
47 | unsigned int devfn, int reg, int len, u32 value) | 73 | unsigned int devfn, int reg, int len, u32 value) |
48 | { | 74 | { |
49 | unsigned long flags; | 75 | unsigned long flags; |
76 | void *adr __iomem = XQUAD_PORT_ADDR(0xcfc, BUS2QUAD(bus)); | ||
50 | 77 | ||
51 | if ((bus >= MAX_MP_BUSSES) || (devfn > 255) || (reg > 255)) | 78 | if ((bus >= MAX_MP_BUSSES) || (devfn > 255) || (reg > 255)) |
52 | return -EINVAL; | 79 | return -EINVAL; |
53 | 80 | ||
54 | spin_lock_irqsave(&pci_config_lock, flags); | 81 | spin_lock_irqsave(&pci_config_lock, flags); |
55 | 82 | ||
56 | outl_quad(PCI_CONF1_MQ_ADDRESS(bus, devfn, reg), 0xCF8, BUS2QUAD(bus)); | 83 | write_cf8(bus, devfn, reg); |
57 | 84 | ||
58 | switch (len) { | 85 | switch (len) { |
59 | case 1: | 86 | case 1: |
60 | outb_quad((u8)value, 0xCFC + (reg & 3), BUS2QUAD(bus)); | 87 | if (xquad_portio) |
88 | writeb(value, adr + (reg & 3)); | ||
89 | else | ||
90 | outb((u8)value, 0xCFC + (reg & 3)); | ||
61 | break; | 91 | break; |
62 | case 2: | 92 | case 2: |
63 | outw_quad((u16)value, 0xCFC + (reg & 2), BUS2QUAD(bus)); | 93 | if (xquad_portio) |
94 | writew(value, adr + (reg & 2)); | ||
95 | else | ||
96 | outw((u16)value, 0xCFC + (reg & 2)); | ||
64 | break; | 97 | break; |
65 | case 4: | 98 | case 4: |
66 | outl_quad((u32)value, 0xCFC, BUS2QUAD(bus)); | 99 | if (xquad_portio) |
100 | writel(value, adr + reg); | ||
101 | else | ||
102 | outl((u32)value, 0xCFC); | ||
67 | break; | 103 | break; |
68 | } | 104 | } |
69 | 105 | ||